From 4168779361ccb557657fac241f7be9dba78a7b69 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 25 Apr 2016 17:20:36 +0100 Subject: [PATCH 01/11] uvision - flags dict creation All flags for uvision are in one dictionary, therefore an exporter or external scripts can get those and use. --- workspace_tools/toolchains/arm.py | 52 +++++++++++++++---------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/workspace_tools/toolchains/arm.py b/workspace_tools/toolchains/arm.py index 19baf30ec91..4a072c7a20c 100644 --- a/workspace_tools/toolchains/arm.py +++ b/workspace_tools/toolchains/arm.py @@ -30,6 +30,16 @@ class ARM(mbedToolchain): DIAGNOSTIC_PATTERN = re.compile('"(?P[^"]+)", line (?P\d+)( \(column (?P\d+)\)|): (?PWarning|Error): (?P.+)') DEP_PATTERN = re.compile('\S+:\s(?P.+)\n') + DEFAULT_FLAGS = { + 'common': ["-c", "--gnu", "-Otime", "--split_sections", "--apcs=interwork", + "--brief_diagnostics", "--restrict", "--multibyte_chars"], + 'asm': ['-I%s' % ARM_INC], + 'c': ["--md", "--no_depend_system_headers", '-I%s' % ARM_INC, + "--c99", "-D__ASSERT_MSG" ], + 'cxx': ["--cpp", "--no_rtti", "-D__ASSERT_MSG"], + 'ld': [], + } + def __init__(self, target, options=None, notify=None, macros=None, silent=False, extra_verbose=False): mbedToolchain.__init__(self, target, options, notify, macros, silent, extra_verbose=extra_verbose) @@ -43,33 +53,25 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, cpu = target.core main_cc = join(ARM_BIN, "armcc") - common = ["-c", - "--cpu=%s" % cpu, "--gnu", - "-Otime", "--split_sections", "--apcs=interwork", - "--brief_diagnostics", "--restrict", "--multibyte_chars" - ] + self.flags = self.DEFAULT_FLAGS + self.flags['common'] += ["--cpu=%s" % cpu] if "save-asm" in self.options: - common.extend(["--asm", "--interleave"]) + self.flags['common'].extend(["--asm", "--interleave"]) if "debug-info" in self.options: - common.append("-g") - common.append("-O0") + self.flags['common'].append("-g") + self.flags['common'].append("-O0") else: - common.append("-O3") - - common_c = [ - "--md", "--no_depend_system_headers", - '-I%s' % ARM_INC - ] + self.flags['common'].append("-O3") - self.asm = [main_cc] + common + ['-I%s' % ARM_INC] + self.asm = [main_cc] + self.flags['common'] + self.flags['asm'] if not "analyze" in self.options: - self.cc = [main_cc] + common + common_c + ["--c99"] - self.cppc = [main_cc] + common + common_c + ["--cpp", "--no_rtti"] + self.cc = [main_cc] + self.flags['common'] + self.flags['c'] + self.cppc = [main_cc] + self.flags['common'] + self.flags['c'] + self.flags['cxx'] else: - self.cc = [join(GOANNA_PATH, "goannacc"), "--with-cc=" + main_cc.replace('\\', '/'), "--dialect=armcc", '--output-format="%s"' % self.GOANNA_FORMAT] + common + common_c + ["--c99"] - self.cppc= [join(GOANNA_PATH, "goannac++"), "--with-cxx=" + main_cc.replace('\\', '/'), "--dialect=armcc", '--output-format="%s"' % self.GOANNA_FORMAT] + common + common_c + ["--cpp", "--no_rtti"] + self.cc = [join(GOANNA_PATH, "goannacc"), "--with-cc=" + main_cc.replace('\\', '/'), "--dialect=armcc", '--output-format="%s"' % self.GOANNA_FORMAT] + self.flags['common'] + self.flags['c'] + self.cppc= [join(GOANNA_PATH, "goannac++"), "--with-cxx=" + main_cc.replace('\\', '/'), "--dialect=armcc", '--output-format="%s"' % self.GOANNA_FORMAT] + self.flags['common'] + self.flags['c'] + self.flags['cxx'] self.ld = [join(ARM_BIN, "armlink")] self.sys_libs = [] @@ -151,8 +153,6 @@ def binary(self, resources, elf, bin): class ARM_STD(ARM): def __init__(self, target, options=None, notify=None, macros=None, silent=False, extra_verbose=False): ARM.__init__(self, target, options, notify, macros, silent, extra_verbose=extra_verbose) - self.cc += ["-D__ASSERT_MSG"] - self.cppc += ["-D__ASSERT_MSG"] self.ld.append("--libpath=%s" % ARM_LIB) @@ -163,17 +163,17 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, ARM.__init__(self, target, options, notify, macros, silent, extra_verbose=extra_verbose) # Compiler - self.asm += ["-D__MICROLIB"] - self.cc += ["--library_type=microlib", "-D__MICROLIB", "-D__ASSERT_MSG"] - self.cppc += ["--library_type=microlib", "-D__MICROLIB", "-D__ASSERT_MSG"] + self.flags['asm'] += ["-D__MICROLIB"] + self.flags['c'] += ["--library_type=microlib", "-D__MICROLIB"] + self.flags['cxx'] += ["--library_type=microlib", "-D__MICROLIB"] # Linker - self.ld.append("--library_type=microlib") + self.flags['ld'].append("--library_type=microlib") # We had to patch microlib to add C++ support # In later releases this patch should have entered mainline if ARM_MICRO.PATCHED_LIBRARY: - self.ld.append("--noscanlib") + self.flags['ld'].append("--noscanlib") # System Libraries self.sys_libs.extend([join(MY_ARM_CLIB, lib+".l") for lib in ["mc_p", "mf_p", "m_ps"]]) From 690b8f0e8b196ef4d654d910ce6b491860919317 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 25 Apr 2016 17:42:34 +0100 Subject: [PATCH 02/11] uvision exporter - use toolchain flags progen uses flags set by the toolchain, this should produce the same result within the build and an exporter project. --- workspace_tools/export/uvision4.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 148126438a3..d49dbbe44d5 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -64,6 +64,16 @@ def generate(self): project_data['tool_specific'] = {} project_data['tool_specific'].update(tool_specific) + + # get flags from toolchain and apply + project_data['tool_specific']['uvision']['misc'] = {} + project_data['tool_specific']['uvision']['misc']['asm_flags'] = self.toolchain.flags['common'] + self.toolchain.flags['asm'] + project_data['tool_specific']['uvision']['misc']['c_flags'] = self.toolchain.flags['common'] + self.toolchain.flags['c'] + # not compatible with c99 flag set in the template + project_data['tool_specific']['uvision']['misc']['c_flags'].remove("--c99") + project_data['tool_specific']['uvision']['misc']['cxx_flags'] = self.toolchain.flags['common'] + self.toolchain.flags['ld'] + project_data['tool_specific']['uvision']['misc']['ld_flags'] = self.toolchain.flags['ld'] + i = 0 for macro in project_data['common']['macros']: # armasm does not like floating numbers in macros, timestamp to int From acb896b3cbdb7e531afc0f4788a3fc108e2c0eaa Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh-R9AADQ Date: Fri, 11 Mar 2016 11:03:19 -0600 Subject: [PATCH 03/11] Removed Freescale Kinetis SDK 1.0 based implementations This will be replaced by Kinetis SDK 2.0 based implemenation under the TARGET_NXP folder Signed-off-by: Mahadevan Mahesh --- .../TARGET_Freescale/TARGET_K22F/MK22F51212.h | 10137 ----------- .../TOOLCHAIN_ARM_STD/MK22F51212.sct | 13 - .../TOOLCHAIN_ARM_STD/startup_MK22F12.S | 679 - .../TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp | 31 - .../TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld | 164 - .../TOOLCHAIN_GCC_ARM/startup_MK22F12.S | 369 - .../TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf | 43 - .../TOOLCHAIN_IAR/startup_MK22F12.S | 535 - .../TARGET_Freescale/TARGET_K22F/cmsis.h | 13 - .../TARGET_Freescale/TARGET_K22F/cmsis_nvic.c | 54 - .../TARGET_Freescale/TARGET_K22F/cmsis_nvic.h | 51 - .../TARGET_K22F/system_MK22F51212.c | 395 - .../TARGET_K22F/system_MK22F51212.h | 367 - .../TARGET_MCU_K64F/MK64F12.h | 14420 ---------------- .../TOOLCHAIN_ARM_STD/MK64F.sct | 14 - .../TOOLCHAIN_ARM_STD/startup_MK64F12.S | 685 - .../TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp | 31 - .../TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld | 164 - .../TOOLCHAIN_GCC_ARM/startup_MK64F12.S | 369 - .../TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf | 49 - .../TOOLCHAIN_IAR/startup_MK64F12.S | 394 - .../TARGET_Freescale/TARGET_MCU_K64F/cmsis.h | 13 - .../TARGET_MCU_K64F/cmsis_nvic.c | 55 - .../TARGET_MCU_K64F/cmsis_nvic.h | 51 - .../TARGET_MCU_K64F/system_MK64F12.c | 391 - .../TARGET_MCU_K64F/system_MK64F12.h | 339 - .../TARGET_KPSDK_MCUS/PeripheralPins.h | 49 - .../TARGET_KPSDK_MCUS/PortNames.h | 35 - .../MK22F51212/fsl_clock_K22F51212.c | 477 - .../MK22F51212/fsl_clock_K22F51212.h | 1033 -- .../MK22F51212/fsl_sim_hal_K22F51212.c | 1187 -- .../MK22F51212/fsl_sim_hal_K22F51212.h | 839 - .../TARGET_K22F/PeripheralNames.h | 133 - .../TARGET_K22F/PeripheralPins.c | 185 - .../TARGET_KPSDK_MCUS/TARGET_K22F/PinNames.h | 259 - .../TARGET_KPSDK_MCUS/TARGET_K22F/device.h | 58 - .../device/MK22F51212/MK22F51212.h | 10137 ----------- .../device/MK22F51212/MK22F51212_adc.h | 2339 --- .../device/MK22F51212/MK22F51212_aips.h | 13604 --------------- .../device/MK22F51212/MK22F51212_cmp.h | 940 - .../device/MK22F51212/MK22F51212_crc.h | 1406 -- .../device/MK22F51212/MK22F51212_dac.h | 837 - .../device/MK22F51212/MK22F51212_dma.h | 5785 ------- .../device/MK22F51212/MK22F51212_dmamux.h | 237 - .../device/MK22F51212/MK22F51212_ewm.h | 504 - .../device/MK22F51212/MK22F51212_fb.h | 904 - .../device/MK22F51212/MK22F51212_fmc.h | 1979 --- .../device/MK22F51212/MK22F51212_ftfa.h | 3194 ---- .../device/MK22F51212/MK22F51212_ftm.h | 5936 ------- .../device/MK22F51212/MK22F51212_gpio.h | 487 - .../device/MK22F51212/MK22F51212_i2c.h | 1724 -- .../device/MK22F51212/MK22F51212_i2s.h | 3270 ---- .../device/MK22F51212/MK22F51212_llwu.h | 1950 --- .../device/MK22F51212/MK22F51212_lptmr.h | 614 - .../device/MK22F51212/MK22F51212_lpuart.h | 2519 --- .../device/MK22F51212/MK22F51212_mcg.h | 1779 -- .../device/MK22F51212/MK22F51212_mcm.h | 713 - .../device/MK22F51212/MK22F51212_nv.h | 869 - .../device/MK22F51212/MK22F51212_osc.h | 378 - .../device/MK22F51212/MK22F51212_pdb.h | 1326 -- .../device/MK22F51212/MK22F51212_pit.h | 516 - .../device/MK22F51212/MK22F51212_pmc.h | 572 - .../device/MK22F51212/MK22F51212_port.h | 892 - .../device/MK22F51212/MK22F51212_rcm.h | 1154 -- .../device/MK22F51212/MK22F51212_rfsys.h | 239 - .../device/MK22F51212/MK22F51212_rfvbat.h | 239 - .../device/MK22F51212/MK22F51212_rng.h | 587 - .../device/MK22F51212/MK22F51212_rtc.h | 1659 -- .../device/MK22F51212/MK22F51212_sim.h | 4023 ----- .../device/MK22F51212/MK22F51212_smc.h | 597 - .../device/MK22F51212/MK22F51212_spi.h | 2239 --- .../device/MK22F51212/MK22F51212_uart.h | 4876 ------ .../device/MK22F51212/MK22F51212_usb.h | 3804 ---- .../device/MK22F51212/MK22F51212_vref.h | 384 - .../device/MK22F51212/MK22F51212_wdog.h | 1153 -- .../device/MK22F51212/fsl_bitaccess.h | 526 - .../TARGET_K22F/device/fsl_device_registers.h | 1526 -- .../TARGET_K22F/mbed_overrides.c | 33 - .../common/phyksz8081/fsl_phy_driver.c | 267 - .../common/phyksz8081/fsl_phy_driver.h | 195 - .../drivers/clock/fsl_clock_manager.c | 299 - .../drivers/clock/fsl_clock_manager.h | 429 - .../drivers/enet/fsl_enet_driver.h | 952 - .../drivers/enet/fsl_enet_rtcs_adapter.h | 513 - .../drivers/enet/src/fsl_enet_irq.c | 89 - .../TARGET_KPSDK_CODE/drivers/enet/subdir.mk | 4 - .../interrupt/fsl_interrupt_features.h | 126 - .../drivers/interrupt/fsl_interrupt_manager.h | 142 - .../drivers/pit/common/fsl_pit_common.c | 47 - .../drivers/pit/common/fsl_pit_common.h | 49 - .../drivers/pit/fsl_pit_driver.h | 251 - .../drivers/pit/src/fsl_pit_driver.c | 264 - .../drivers/pit/src/fsl_pit_irq.c | 154 - .../hal/adc/fsl_adc_features.h | 220 - .../TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c | 152 - .../TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h | 906 - .../hal/can/fsl_flexcan_features.h | 119 - .../hal/can/fsl_flexcan_hal.c | 1845 -- .../hal/can/fsl_flexcan_hal.h | 837 - .../hal/dac/fsl_dac_features.h | 100 - .../TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c | 105 - .../TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h | 488 - .../hal/dmamux/fsl_dmamux_features.h | 114 - .../hal/dmamux/fsl_dmamux_hal.c | 56 - .../hal/dmamux/fsl_dmamux_hal.h | 136 - .../hal/dspi/fsl_dspi_features.h | 247 - .../TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c | 604 - .../TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h | 900 - .../hal/edma/fsl_edma_features.h | 135 - .../TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c | 633 - .../TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h | 1418 -- .../hal/enet/fsl_enet_features.h | 56 - .../TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c | 557 - .../TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h | 1420 -- .../hal/flextimer/fsl_ftm_features.h | 156 - .../hal/flextimer/fsl_ftm_hal.c | 186 - .../hal/flextimer/fsl_ftm_hal.h | 1433 -- .../hal/gpio/fsl_gpio_features.h | 188 - .../TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.c | 77 - .../TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.h | 406 - .../hal/i2c/fsl_i2c_features.h | 283 - .../TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c | 291 - .../TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h | 702 - .../hal/llwu/fsl_llwu_features.h | 153 - .../TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c | 616 - .../TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h | 248 - .../hal/lptmr/fsl_lptmr_features.h | 86 - .../hal/lptmr/fsl_lptmr_hal.c | 68 - .../hal/lptmr/fsl_lptmr_hal.h | 413 - .../hal/lpuart/fsl_lpuart_features.h | 220 - .../hal/lpuart/fsl_lpuart_hal.c | 782 - .../hal/lpuart/fsl_lpuart_hal.h | 1134 -- .../hal/mcg/fsl_mcg_features.h | 705 - .../TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c | 432 - .../TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h | 2184 --- .../hal/mcg/fsl_mcg_hal_modes.c | 2501 --- .../hal/mcg/fsl_mcg_hal_modes.h | 526 - .../hal/mpu/fsl_mpu_features.h | 146 - .../TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c | 71 - .../TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h | 1545 -- .../hal/osc/fsl_osc_features.h | 166 - .../TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c | 192 - .../TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h | 177 - .../hal/pdb/fsl_pdb_features.h | 87 - .../TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c | 232 - .../TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h | 631 - .../hal/pit/fsl_pit_features.h | 127 - .../TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c | 63 - .../TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h | 336 - .../hal/pmc/fsl_pmc_features.h | 109 - .../TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c | 68 - .../TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h | 321 - .../hal/port/fsl_port_features.h | 333 - .../TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c | 68 - .../TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h | 450 - .../hal/rcm/fsl_rcm_features.h | 109 - .../TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c | 109 - .../TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h | 199 - .../hal/rtc/fsl_rtc_features.h | 144 - .../TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c | 381 - .../TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h | 1976 --- .../hal/sai/fsl_sai_features.h | 168 - .../TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c | 835 - .../TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h | 1423 -- .../hal/sdhc/fsl_sdhc_features.h | 84 - .../TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c | 167 - .../TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h | 1236 -- .../hal/sim/fsl_sim_features.h | 4222 ----- .../TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c | 1468 -- .../TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h | 1620 -- .../hal/smc/fsl_smc_features.h | 245 - .../TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c | 671 - .../TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h | 475 - .../hal/uart/fsl_uart_features.h | 1218 -- .../TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c | 961 - .../TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h | 1333 -- .../hal/wdog/fsl_wdog_features.h | 87 - .../TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c | 75 - .../TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h | 609 - .../TARGET_KPSDK_CODE/mbed KSDK readme.txt | 15 - .../utilities/fsl_misc_utilities.h | 60 - .../utilities/fsl_os_abstraction.h | 572 - .../utilities/fsl_os_abstraction_mbed.h | 38 - .../utilities/src/fsl_misc_utilities.c | 68 - .../utilities/src/fsl_os_abstraction_mbed.c | 35 - .../TARGET_KPSDK_CODE/utilities/sw_timer.h | 191 - .../MK64F12/fsl_clock_K64F12.c | 592 - .../MK64F12/fsl_clock_K64F12.h | 1248 -- .../MK64F12/fsl_sim_hal_K64F12.c | 1410 -- .../MK64F12/fsl_sim_hal_K64F12.h | 1009 -- .../TARGET_FRDM/PeripheralNames.h | 139 - .../TARGET_FRDM/PeripheralPins.c | 208 - .../TARGET_MCU_K64F/TARGET_FRDM/PinNames.h | 258 - .../TARGET_MCU_K64F/TARGET_FRDM/crc.c | 234 - .../TARGET_MCU_K64F/TARGET_FRDM/crc.h | 77 - .../TARGET_MCU_K64F/TARGET_FRDM/device.h | 58 - .../TARGET_FRDM/mbed_overrides.c | 72 - .../TARGET_MTS_GAMBIT/PeripheralNames.h | 133 - .../TARGET_MTS_GAMBIT/PeripheralPins.c | 112 - .../TARGET_MTS_GAMBIT/PinNames.h | 268 - .../TARGET_MTS_GAMBIT/device.h | 58 - .../TARGET_MTS_GAMBIT/mbed_overrides.c | 23 - .../device/MK64F12/fsl_bitaccess.h | 529 - .../device/device/MK64F12/MK64F12.h | 14420 ---------------- .../device/device/MK64F12/MK64F12_adc.h | 2342 --- .../device/device/MK64F12/MK64F12_aips.h | 12467 ------------- .../device/device/MK64F12/MK64F12_axbs.h | 1030 -- .../device/device/MK64F12/MK64F12_can.h | 3579 ---- .../device/device/MK64F12/MK64F12_cau.h | 5229 ------ .../device/device/MK64F12/MK64F12_cmp.h | 942 - .../device/device/MK64F12/MK64F12_cmt.h | 1120 -- .../device/device/MK64F12/MK64F12_crc.h | 1409 -- .../device/device/MK64F12/MK64F12_dac.h | 818 - .../device/device/MK64F12/MK64F12_dma.h | 5365 ------ .../device/device/MK64F12/MK64F12_dmamux.h | 241 - .../device/device/MK64F12/MK64F12_enet.h | 7497 -------- .../device/device/MK64F12/MK64F12_ewm.h | 440 - .../device/device/MK64F12/MK64F12_fb.h | 907 - .../device/device/MK64F12/MK64F12_fmc.h | 1982 --- .../device/device/MK64F12/MK64F12_ftfe.h | 2344 --- .../device/device/MK64F12/MK64F12_ftm.h | 5910 ------- .../device/device/MK64F12/MK64F12_gpio.h | 490 - .../device/device/MK64F12/MK64F12_i2c.h | 1728 -- .../device/device/MK64F12/MK64F12_i2s.h | 3098 ---- .../device/device/MK64F12/MK64F12_llwu.h | 2052 --- .../device/device/MK64F12/MK64F12_lptmr.h | 617 - .../device/device/MK64F12/MK64F12_mcg.h | 1782 -- .../device/device/MK64F12/MK64F12_mcm.h | 1089 -- .../device/device/MK64F12/MK64F12_mpu.h | 1741 -- .../device/device/MK64F12/MK64F12_nv.h | 929 - .../device/device/MK64F12/MK64F12_osc.h | 312 - .../device/device/MK64F12/MK64F12_pdb.h | 1329 -- .../device/device/MK64F12/MK64F12_pit.h | 519 - .../device/device/MK64F12/MK64F12_pmc.h | 575 - .../device/device/MK64F12/MK64F12_port.h | 895 - .../device/device/MK64F12/MK64F12_rcm.h | 722 - .../device/device/MK64F12/MK64F12_rfsys.h | 242 - .../device/device/MK64F12/MK64F12_rfvbat.h | 242 - .../device/device/MK64F12/MK64F12_rng.h | 590 - .../device/device/MK64F12/MK64F12_rtc.h | 1662 -- .../device/device/MK64F12/MK64F12_sdhc.h | 5200 ------ .../device/device/MK64F12/MK64F12_sim.h | 4084 ----- .../device/device/MK64F12/MK64F12_smc.h | 566 - .../device/device/MK64F12/MK64F12_spi.h | 2243 --- .../device/device/MK64F12/MK64F12_uart.h | 4474 ----- .../device/device/MK64F12/MK64F12_usb.h | 3828 ---- .../device/device/MK64F12/MK64F12_usbdcd.h | 938 - .../device/device/MK64F12/MK64F12_vref.h | 387 - .../device/device/MK64F12/MK64F12_wdog.h | 1156 -- .../device/device/fsl_device_registers.h | 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b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h deleted file mode 100644 index fd48b0f8c25..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h +++ /dev/null @@ -1,10137 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK22F51212 -** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK22F51212.h - * @version 2.5 - * @date 2014-05-06 - * @brief CMSIS Peripheral Access Layer for MK22F51212 - * - * CMSIS Peripheral Access Layer for MK22F51212 - */ - - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */ -#define MK22F51212_H_ -#define MCU_MK22F51212 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0005u - -/** - * @brief Macro to calculate address of an aliased word in the peripheral - * bitband area for a peripheral register and bit (bit band region 0x40000000 to - * 0x400FFFFF). - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Address of the aliased word in the peripheral bitband area. - */ -#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 32bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 16bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 8bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ - DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ - DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ - DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ - DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ - DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ - DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ - DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ - DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ - DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ - DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ - DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ - DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ - DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ - DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ - DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ - MCM_IRQn = 17, /**< Normal Interrupt */ - FTF_IRQn = 18, /**< FTFA Command complete interrupt */ - Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG Interrupt */ - RNG_IRQn = 23, /**< RNG Interrupt */ - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, /**< I2C1 interrupt */ - SPI0_IRQn = 26, /**< SPI0 Interrupt */ - SPI1_IRQn = 27, /**< SPI1 Interrupt */ - I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ - LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */ - UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ - UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ - UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ - UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ - UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ - UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ - Reserved53_IRQn = 37, /**< Reserved interrupt 53 */ - Reserved54_IRQn = 38, /**< Reserved interrupt 54 */ - ADC0_IRQn = 39, /**< ADC0 interrupt */ - CMP0_IRQn = 40, /**< CMP0 interrupt */ - CMP1_IRQn = 41, /**< CMP1 interrupt */ - FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt 61 */ - RTC_IRQn = 46, /**< RTC interrupt */ - RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ - PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 52, /**< PDB0 Interrupt */ - USB0_IRQn = 53, /**< USB0 interrupt */ - Reserved70_IRQn = 54, /**< Reserved interrupt 70 */ - Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ - DAC0_IRQn = 56, /**< DAC0 interrupt */ - MCG_IRQn = 57, /**< MCG Interrupt */ - LPTimer_IRQn = 58, /**< LPTimer interrupt */ - PORTA_IRQn = 59, /**< Port A interrupt */ - PORTB_IRQn = 60, /**< Port B interrupt */ - PORTC_IRQn = 61, /**< Port C interrupt */ - PORTD_IRQn = 62, /**< Port D interrupt */ - PORTE_IRQn = 63, /**< Port E interrupt */ - SWI_IRQn = 64, /**< Software interrupt */ - Reserved81_IRQn = 65, /**< Reserved interrupt 81 */ - Reserved82_IRQn = 66, /**< Reserved interrupt 82 */ - Reserved83_IRQn = 67, /**< Reserved interrupt 83 */ - Reserved84_IRQn = 68, /**< Reserved interrupt 84 */ - Reserved85_IRQn = 69, /**< Reserved interrupt 85 */ - Reserved86_IRQn = 70, /**< Reserved interrupt 86 */ - FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ - DAC1_IRQn = 72, /**< DAC1 interrupt */ - ADC1_IRQn = 73, /**< ADC1 interrupt */ - Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */ - Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */ - Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */ - Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */ - Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */ - Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */ - Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */ - Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */ - Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */ - Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */ - Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */ - Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK22F51212.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_EARS_REG(base) ((base)->EARS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) -#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Register_Masks FB Register Masks - * @{ - */ - -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFA_FCNFG_REG(base) ((base)->FCNFG) -#define FTFA_FSEC_REG(base) ((base)->FSEC) -#define FTFA_FOPT_REG(base) ((base)->FOPT) -#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFA_FPROT3_REG(base) ((base)->FPROT3) -#define FTFA_FPROT2_REG(base) ((base)->FPROT2) -#define FTFA_FPROT1_REG(base) ((base)->FPROT1) -#define FTFA_FPROT0_REG(base) ((base)->FPROT0) -#define FTFA_XACCH3_REG(base) ((base)->XACCH3) -#define FTFA_XACCH2_REG(base) ((base)->XACCH2) -#define FTFA_XACCH1_REG(base) ((base)->XACCH1) -#define FTFA_XACCH0_REG(base) ((base)->XACCH0) -#define FTFA_XACCL3_REG(base) ((base)->XACCL3) -#define FTFA_XACCL2_REG(base) ((base)->XACCL2) -#define FTFA_XACCL1_REG(base) ((base)->XACCL1) -#define FTFA_XACCL0_REG(base) ((base)->XACCL0) -#define FTFA_SACCH3_REG(base) ((base)->SACCH3) -#define FTFA_SACCH2_REG(base) ((base)->SACCH2) -#define FTFA_SACCH1_REG(base) ((base)->SACCH1) -#define FTFA_SACCH0_REG(base) ((base)->SACCH0) -#define FTFA_SACCL3_REG(base) ((base)->SACCL3) -#define FTFA_SACCL2_REG(base) ((base)->SACCL2) -#define FTFA_SACCL1_REG(base) ((base)->SACCL1) -#define FTFA_SACCL0_REG(base) ((base)->SACCL0) -#define FTFA_FACSS_REG(base) ((base)->FACSS) -#define FTFA_FACSN_REG(base) ((base)->FACSN) - -/*! - * @} - */ /* end of group FTFA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTFA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFA_Register_Masks FTFA Register Masks - * @{ - */ - -/* FSTAT Bit Fields */ -#define FTFA_FSTAT_MGSTAT0_MASK 0x1u -#define FTFA_FSTAT_MGSTAT0_SHIFT 0 -#define FTFA_FSTAT_FPVIOL_MASK 0x10u -#define FTFA_FSTAT_FPVIOL_SHIFT 4 -#define FTFA_FSTAT_ACCERR_MASK 0x20u -#define FTFA_FSTAT_ACCERR_SHIFT 5 -#define FTFA_FSTAT_RDCOLERR_MASK 0x40u -#define FTFA_FSTAT_RDCOLERR_SHIFT 6 -#define FTFA_FSTAT_CCIF_MASK 0x80u -#define FTFA_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFA_FCNFG_ERSSUSP_MASK 0x10u -#define FTFA_FCNFG_ERSSUSP_SHIFT 4 -#define FTFA_FCNFG_ERSAREQ_MASK 0x20u -#define FTFA_FCNFG_ERSAREQ_SHIFT 5 -#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFA_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFA_FCNFG_CCIE_MASK 0x80u -#define FTFA_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFA_FSEC_SEC_MASK 0x3u -#define FTFA_FSEC_SEC_SHIFT 0 -#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTM_Register_Masks FTM Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<BAUD) -#define LPUART_STAT_REG(base) ((base)->STAT) -#define LPUART_CTRL_REG(base) ((base)->CTRL) -#define LPUART_DATA_REG(base) ((base)->DATA) -#define LPUART_MATCH_REG(base) ((base)->MATCH) -#define LPUART_MODIR_REG(base) ((base)->MODIR) - -/*! - * @} - */ /* end of group LPUART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/* BAUD Bit Fields */ -#define LPUART_BAUD_SBR_MASK 0x1FFFu -#define LPUART_BAUD_SBR_SHIFT 0 -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_PLACR_REG(base) ((base)->PLACR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_CPO_REG(base) ((base)->CPO) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) -#define OSC_DIV_REG(base) ((base)->DIV) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 -/* DIV Bit Fields */ -#define OSC_DIV_ERPS_MASK 0xC0u -#define OSC_DIV_ERPS_SHIFT 6 -#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PDB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Masks PDB Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) -#define RCM_SSRS0_REG(base) ((base)->SSRS0) -#define RCM_SSRS1_REG(base) ((base)->SSRS1) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFVBAT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_HA_MASK 0x2u -#define RNG_CR_HA_SHIFT 1 -#define RNG_CR_INTM_MASK 0x4u -#define RNG_CR_INTM_SHIFT 2 -#define RNG_CR_CLRI_MASK 0x8u -#define RNG_CR_CLRI_SHIFT 3 -#define RNG_CR_SLP_MASK 0x10u -#define RNG_CR_SLP_SHIFT 4 -/* SR Bit Fields */ -#define RNG_SR_SECV_MASK 0x1u -#define RNG_SR_SECV_SHIFT 0 -#define RNG_SR_LRS_MASK 0x2u -#define RNG_SR_LRS_SHIFT 1 -#define RNG_SR_ORU_MASK 0x4u -#define RNG_SR_ORU_SHIFT 2 -#define RNG_SR_ERRI_MASK 0x8u -#define RNG_SR_ERRI_SHIFT 3 -#define RNG_SR_SLP_MASK 0x10u -#define RNG_SR_SLP_SHIFT 4 -#define RNG_SR_OREG_LVL_MASK 0xFF00u -#define RNG_SR_OREG_LVL_SHIFT 8 -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SOPT8_REG(base) ((base)->SOPT8) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -#define SMC_PMPROT_AHSRUN_MASK 0x80u -#define SMC_PMPROT_AHSRUN_SHIFT 7 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816_REG(base) ((base)->WP7816) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) -#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) -#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) -#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) -#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) -#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) -#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) -#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<>> ------------------ -; * -; *****************************************************************************/ - - -__initial_sp EQU 0x20010000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete - DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete - DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete - DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete - DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete - DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete - DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete - DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete - DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete - DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete - DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete - DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete - DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete - DCD DMA_Error_IRQHandler ; DMA Error Interrupt - DCD MCM_IRQHandler ; Normal Interrupt - DCD FTFE_IRQHandler ; FTFE Command complete interrupt - DCD Read_Collision_IRQHandler ; Read Collision Interrupt - DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ; Low Leakage Wakeup - DCD Watchdog_IRQHandler ; WDOG Interrupt - DCD Reserved39_IRQHandler ; Reserved Interrupt 39 - DCD I2C0_IRQHandler ; I2C0 interrupt - DCD I2C1_IRQHandler ; I2C1 interrupt - DCD SPI0_IRQHandler ; SPI0 Interrupt - DCD SPI1_IRQHandler ; SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt - DCD UART0_LON_IRQHandler ; UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ; UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ; UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ; UART2 Error interrupt - DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt - DCD UART3_ERR_IRQHandler ; UART3 Error interrupt - DCD ADC0_IRQHandler ; ADC0 interrupt - DCD CMP0_IRQHandler ; CMP0 interrupt - DCD CMP1_IRQHandler ; CMP1 interrupt - DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ; CMT interrupt - DCD RTC_IRQHandler ; RTC interrupt - DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt - DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ; PDB0 Interrupt - DCD USB0_IRQHandler ; USB0 interrupt - DCD USBDCD_IRQHandler ; USBDCD Interrupt - DCD Reserved71_IRQHandler ; Reserved interrupt 71 - DCD DAC0_IRQHandler ; DAC0 interrupt - DCD MCG_IRQHandler ; MCG Interrupt - DCD LPTimer_IRQHandler ; LPTimer interrupt - DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTB_IRQHandler ; Port B interrupt - DCD PORTC_IRQHandler ; Port C interrupt - DCD PORTD_IRQHandler ; Port D interrupt - DCD PORTE_IRQHandler ; Port E interrupt - DCD SWI_IRQHandler ; Software interrupt - DCD SPI2_IRQHandler ; SPI2 Interrupt - DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt - DCD UART4_ERR_IRQHandler ; UART4 Error interrupt - DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt - DCD UART5_ERR_IRQHandler ; UART5 Error interrupt - DCD CMP2_IRQHandler ; CMP2 interrupt - DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt - DCD DAC1_IRQHandler ; DAC1 interrupt - DCD ADC1_IRQHandler ; ADC1 interrupt - DCD I2C2_IRQHandler ; I2C2 interrupt - DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ; CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt - DCD SDHC_IRQHandler ; SDHC interrupt - DCD DefaultISR ; 98 - DCD DefaultISR ; 99 - DCD DefaultISR ; 100 - DCD DefaultISR ; 101 - DCD DefaultISR ; 102 - DCD DefaultISR ; 103 - DCD DefaultISR ; 104 - DCD DefaultISR ; 105 - DCD DefaultISR ; 106 - DCD DefaultISR ; 107 - DCD DefaultISR ; 108 - DCD DefaultISR ; 109 - DCD DefaultISR ; 110 - DCD DefaultISR ; 111 - DCD DefaultISR ; 112 - DCD DefaultISR ; 113 - DCD DefaultISR ; 114 - DCD DefaultISR ; 115 - DCD DefaultISR ; 116 - DCD DefaultISR ; 117 - DCD DefaultISR ; 118 - DCD DefaultISR ; 119 - DCD DefaultISR ; 120 - DCD DefaultISR ; 121 - DCD DefaultISR ; 122 - DCD DefaultISR ; 123 - DCD DefaultISR ; 124 - DCD DefaultISR ; 125 - DCD DefaultISR ; 126 - DCD DefaultISR ; 127 - DCD DefaultISR ; 128 - DCD DefaultISR ; 129 - DCD DefaultISR ; 130 - DCD DefaultISR ; 131 - DCD DefaultISR ; 132 - DCD DefaultISR ; 133 - DCD DefaultISR ; 134 - DCD DefaultISR ; 135 - DCD DefaultISR ; 136 - DCD DefaultISR ; 137 - DCD DefaultISR ; 138 - DCD DefaultISR ; 139 - DCD DefaultISR ; 140 - DCD DefaultISR ; 141 - DCD DefaultISR ; 142 - DCD DefaultISR ; 143 - DCD DefaultISR ; 144 - DCD DefaultISR ; 145 - DCD DefaultISR ; 146 - DCD DefaultISR ; 147 - DCD DefaultISR ; 148 - DCD DefaultISR ; 149 - DCD DefaultISR ; 150 - DCD DefaultISR ; 151 - DCD DefaultISR ; 152 - DCD DefaultISR ; 153 - DCD DefaultISR ; 154 - DCD DefaultISR ; 155 - DCD DefaultISR ; 156 - DCD DefaultISR ; 157 - DCD DefaultISR ; 158 - DCD DefaultISR ; 159 - DCD DefaultISR ; 160 - DCD DefaultISR ; 161 - DCD DefaultISR ; 162 - DCD DefaultISR ; 163 - DCD DefaultISR ; 164 - DCD DefaultISR ; 165 - DCD DefaultISR ; 166 - DCD DefaultISR ; 167 - DCD DefaultISR ; 168 - DCD DefaultISR ; 169 - DCD DefaultISR ; 170 - DCD DefaultISR ; 171 - DCD DefaultISR ; 172 - DCD DefaultISR ; 173 - DCD DefaultISR ; 174 - DCD DefaultISR ; 175 - DCD DefaultISR ; 176 - DCD DefaultISR ; 177 - DCD DefaultISR ; 178 - DCD DefaultISR ; 179 - DCD DefaultISR ; 180 - DCD DefaultISR ; 181 - DCD DefaultISR ; 182 - DCD DefaultISR ; 183 - DCD DefaultISR ; 184 - DCD DefaultISR ; 185 - DCD DefaultISR ; 186 - DCD DefaultISR ; 187 - DCD DefaultISR ; 188 - DCD DefaultISR ; 189 - DCD DefaultISR ; 190 - DCD DefaultISR ; 191 - DCD DefaultISR ; 192 - DCD DefaultISR ; 193 - DCD DefaultISR ; 194 - DCD DefaultISR ; 195 - DCD DefaultISR ; 196 - DCD DefaultISR ; 197 - DCD DefaultISR ; 198 - DCD DefaultISR ; 199 - DCD DefaultISR ; 200 - DCD DefaultISR ; 201 - DCD DefaultISR ; 202 - DCD DefaultISR ; 203 - DCD DefaultISR ; 204 - DCD DefaultISR ; 205 - DCD DefaultISR ; 206 - DCD DefaultISR ; 207 - DCD DefaultISR ; 208 - DCD DefaultISR ; 209 - DCD DefaultISR ; 210 - DCD DefaultISR ; 211 - DCD DefaultISR ; 212 - DCD DefaultISR ; 213 - DCD DefaultISR ; 214 - DCD DefaultISR ; 215 - DCD DefaultISR ; 216 - DCD DefaultISR ; 217 - DCD DefaultISR ; 218 - DCD DefaultISR ; 219 - DCD DefaultISR ; 220 - DCD DefaultISR ; 221 - DCD DefaultISR ; 222 - DCD DefaultISR ; 223 - DCD DefaultISR ; 224 - DCD DefaultISR ; 225 - DCD DefaultISR ; 226 - DCD DefaultISR ; 227 - DCD DefaultISR ; 228 - DCD DefaultISR ; 229 - DCD DefaultISR ; 230 - DCD DefaultISR ; 231 - DCD DefaultISR ; 232 - DCD DefaultISR ; 233 - DCD DefaultISR ; 234 - DCD DefaultISR ; 235 - DCD DefaultISR ; 236 - DCD DefaultISR ; 237 - DCD DefaultISR ; 238 - DCD DefaultISR ; 239 - DCD DefaultISR ; 240 - DCD DefaultISR ; 241 - DCD DefaultISR ; 242 - DCD DefaultISR ; 243 - DCD DefaultISR ; 244 - DCD DefaultISR ; 245 - DCD DefaultISR ; 246 - DCD DefaultISR ; 247 - DCD DefaultISR ; 248 - DCD DefaultISR ; 249 - DCD DefaultISR ; 250 - DCD DefaultISR ; 251 - DCD DefaultISR ; 252 - DCD DefaultISR ; 253 - DCD DefaultISR ; 254 - DCD DefaultISR ; 255 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict acces to the FTFL module. -; Backdoor Comparison Key -; Backdoor Key 0 <0x0-0xFF:2> -; Backdoor Key 1 <0x0-0xFF:2> -; Backdoor Key 2 <0x0-0xFF:2> -; Backdoor Key 3 <0x0-0xFF:2> -; Backdoor Key 4 <0x0-0xFF:2> -; Backdoor Key 5 <0x0-0xFF:2> -; Backdoor Key 6 <0x0-0xFF:2> -; Backdoor Key 7 <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program flash protection bytes -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Data flash protection byte (FDPROT) -; Each bit protects a 1/8 region of the data flash memory. -; (Program flash only devices: Reserved) -; FDPROT.0 -; FDPROT.1 -; FDPROT.2 -; FDPROT.3 -; FDPROT.4 -; FDPROT.5 -; FDPROT.6 -; FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; -; EEPROM protection byte (FEPROT) -; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; (Program flash only devices: Reserved) -; FEPROT.0 -; FEPROT.1 -; FEPROT.2 -; FEPROT.3 -; FEPROT.4 -; FEPROT.5 -; FEPROT.6 -; FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> normal boot -; EZPORT_DIS -; <0=> EzPort operation is enabled -; <1=> EzPort operation is disabled -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; This bits define the security state of the MCU. -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; This bits define the security state of the MCU. -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; Mass Erase Enable Bits -; Enables and disables mass erase capability of the FTFL module -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor key Security Enable -; These bits enable and disable backdoor key access to the FTFL module. -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA |.ARM.__at_0x400|, CODE, READONLY - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT - ENDIF - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT DMA4_IRQHandler [WEAK] - EXPORT DMA5_IRQHandler [WEAK] - EXPORT DMA6_IRQHandler [WEAK] - EXPORT DMA7_IRQHandler [WEAK] - EXPORT DMA8_IRQHandler [WEAK] - EXPORT DMA9_IRQHandler [WEAK] - EXPORT DMA10_IRQHandler [WEAK] - EXPORT DMA11_IRQHandler [WEAK] - EXPORT DMA12_IRQHandler [WEAK] - EXPORT DMA13_IRQHandler [WEAK] - EXPORT DMA14_IRQHandler [WEAK] - EXPORT DMA15_IRQHandler [WEAK] - EXPORT DMA_Error_IRQHandler [WEAK] - EXPORT MCM_IRQHandler [WEAK] - EXPORT FTFE_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLW_IRQHandler [WEAK] - EXPORT Watchdog_IRQHandler [WEAK] - EXPORT Reserved39_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT I2S0_Tx_IRQHandler [WEAK] - EXPORT I2S0_Rx_IRQHandler [WEAK] - EXPORT UART0_LON_IRQHandler [WEAK] - EXPORT UART0_RX_TX_IRQHandler [WEAK] - EXPORT UART0_ERR_IRQHandler [WEAK] - EXPORT UART1_RX_TX_IRQHandler [WEAK] - EXPORT UART1_ERR_IRQHandler [WEAK] - EXPORT UART2_RX_TX_IRQHandler [WEAK] - EXPORT UART2_ERR_IRQHandler [WEAK] - EXPORT UART3_RX_TX_IRQHandler [WEAK] - EXPORT UART3_ERR_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTimer_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART4_RX_TX_IRQHandler [WEAK] - EXPORT UART4_ERR_IRQHandler [WEAK] - EXPORT UART5_RX_TX_IRQHandler [WEAK] - EXPORT UART5_ERR_IRQHandler [WEAK] - EXPORT CMP2_IRQHandler [WEAK] - EXPORT FTM3_IRQHandler [WEAK] - EXPORT DAC1_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] - EXPORT CAN0_Bus_Off_IRQHandler [WEAK] - EXPORT CAN0_Error_IRQHandler [WEAK] - EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] - EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] - EXPORT CAN0_Wake_Up_IRQHandler [WEAK] - EXPORT SDHC_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] - -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -DMA4_IRQHandler -DMA5_IRQHandler -DMA6_IRQHandler -DMA7_IRQHandler -DMA8_IRQHandler -DMA9_IRQHandler -DMA10_IRQHandler -DMA11_IRQHandler -DMA12_IRQHandler -DMA13_IRQHandler -DMA14_IRQHandler -DMA15_IRQHandler -DMA_Error_IRQHandler -MCM_IRQHandler -FTFE_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLW_IRQHandler -Watchdog_IRQHandler -Reserved39_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -I2S0_Tx_IRQHandler -I2S0_Rx_IRQHandler -UART0_LON_IRQHandler -UART0_RX_TX_IRQHandler -UART0_ERR_IRQHandler -UART1_RX_TX_IRQHandler -UART1_ERR_IRQHandler -UART2_RX_TX_IRQHandler -UART2_ERR_IRQHandler -UART3_RX_TX_IRQHandler -UART3_ERR_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -DAC0_IRQHandler -MCG_IRQHandler -LPTimer_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -SPI2_IRQHandler -UART4_RX_TX_IRQHandler -UART4_ERR_IRQHandler -UART5_RX_TX_IRQHandler -UART5_ERR_IRQHandler -CMP2_IRQHandler -FTM3_IRQHandler -DAC1_IRQHandler -ADC1_IRQHandler -I2C2_IRQHandler -CAN0_ORed_Message_buffer_IRQHandler -CAN0_Bus_Off_IRQHandler -CAN0_Error_IRQHandler -CAN0_Tx_Warning_IRQHandler -CAN0_Rx_Warning_IRQHandler -CAN0_Wake_Up_IRQHandler -SDHC_IRQHandler -DefaultISR - - B . - - ENDP - - - ALIGN - END - diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp deleted file mode 100644 index b129b2c2a5b..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld deleted file mode 100644 index b7b3fe61c23..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld +++ /dev/null @@ -1,164 +0,0 @@ -/* - * K64F ARM GCC linker script file - */ - -MEMORY -{ - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x000080000 - 0x00000410 - RAM (rwx) : ORIGIN = 0x1FFF0400, LENGTH = 0x000020000 - 0x00000400 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .isr_vector : - { - __vector_table = .; - KEEP(*(.vector_table)) - *(.text.Reset_Handler) - *(.text.System_Init) - . = ALIGN(4); - } > VECTORS - - .flash_protect : - { - KEEP(*(.kinetis_flash_config_field)) - . = ALIGN(4); - } > FLASH_PROTECTION - - .text : - { - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S deleted file mode 100644 index 2b56751648d..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S +++ /dev/null @@ -1,369 +0,0 @@ -/* K64F startup ARM GCC - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv7-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0xC00 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vector_table,"a",%progbits - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ - .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ - .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ - .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ - .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/ - .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/ - .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/ - .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/ - .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/ - .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/ - .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/ - .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/ - .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/ - .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/ - .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/ - .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/ - .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ - .long MCM_IRQHandler /* Normal Interrupt*/ - .long FTF_IRQHandler /* FTFA Command complete interrupt*/ - .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ - .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ - .long LLW_IRQHandler /* Low Leakage Wakeup*/ - .long Watchdog_IRQHandler /* WDOG Interrupt*/ - .long RNG_IRQHandler /* RNG Interrupt*/ - .long I2C0_IRQHandler /* I2C0 interrupt*/ - .long I2C1_IRQHandler /* I2C1 interrupt*/ - .long SPI0_IRQHandler /* SPI0 Interrupt*/ - .long SPI1_IRQHandler /* SPI1 Interrupt*/ - .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ - .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ - .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/ - .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ - .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ - .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ - .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ - .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ - .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ - .long Reserved53_IRQHandler /* Reserved interrupt 53*/ - .long Reserved54_IRQHandler /* Reserved interrupt 54*/ - .long ADC0_IRQHandler /* ADC0 interrupt*/ - .long CMP0_IRQHandler /* CMP0 interrupt*/ - .long CMP1_IRQHandler /* CMP1 interrupt*/ - .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ - .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ - .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ - .long Reserved61_IRQHandler /* Reserved interrupt 61*/ - .long RTC_IRQHandler /* RTC interrupt*/ - .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ - .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ - .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ - .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ - .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ - .long PDB0_IRQHandler /* PDB0 Interrupt*/ - .long USB0_IRQHandler /* USB0 interrupt*/ - .long Reserved70_IRQHandler /* Reserved interrupt 70*/ - .long Reserved71_IRQHandler /* Reserved interrupt 71*/ - .long DAC0_IRQHandler /* DAC0 interrupt*/ - .long MCG_IRQHandler /* MCG Interrupt*/ - .long LPTimer_IRQHandler /* LPTimer interrupt*/ - .long PORTA_IRQHandler /* Port A interrupt*/ - .long PORTB_IRQHandler /* Port B interrupt*/ - .long PORTC_IRQHandler /* Port C interrupt*/ - .long PORTD_IRQHandler /* Port D interrupt*/ - .long PORTE_IRQHandler /* Port E interrupt*/ - .long SWI_IRQHandler /* Software interrupt*/ - .long Reserved81_IRQHandler /* Reserved interrupt 81*/ - .long Reserved82_IRQHandler /* Reserved interrupt 82*/ - .long Reserved83_IRQHandler /* Reserved interrupt 83*/ - .long Reserved84_IRQHandler /* Reserved interrupt 84*/ - .long Reserved85_IRQHandler /* Reserved interrupt 85*/ - .long Reserved86_IRQHandler /* Reserved interrupt 86*/ - .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ - .long DAC1_IRQHandler /* DAC1 interrupt*/ - .long ADC1_IRQHandler /* ADC1 interrupt*/ - .long Reserved90_IRQHandler /* Reserved Interrupt 90*/ - .long Reserved91_IRQHandler /* Reserved Interrupt 91*/ - .long Reserved92_IRQHandler /* Reserved Interrupt 92*/ - .long Reserved93_IRQHandler /* Reserved Interrupt 93*/ - .long Reserved94_IRQHandler /* Reserved Interrupt 94*/ - .long Reserved95_IRQHandler /* Reserved Interrupt 95*/ - .long Reserved96_IRQHandler /* Reserved Interrupt 96*/ - .long Reserved97_IRQHandler /* Reserved Interrupt 97*/ - .long Reserved98_IRQHandler /* Reserved Interrupt 98*/ - .long Reserved99_IRQHandler /* Reserved Interrupt 99*/ - .long Reserved100_IRQHandler /* Reserved Interrupt 100*/ - .long Reserved101_IRQHandler /* Reserved Interrupt 101*/ - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - -disable_watchdog: - /* unlock */ - ldr r1, =0x4005200e - ldr r0, =0xc520 - strh r0, [r1] - ldr r0, =0xd928 - strh r0, [r1] - /* disable */ - ldr r1, =0x40052000 - ldr r0, =0x01d2 - strh r0, [r1] - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - -/* IRQ Handlers */ - def_irq_default_handler DMA0_IRQHandler - def_irq_default_handler DMA1_IRQHandler - def_irq_default_handler DMA2_IRQHandler - def_irq_default_handler DMA3_IRQHandler - def_irq_default_handler DMA4_IRQHandler - def_irq_default_handler DMA5_IRQHandler - def_irq_default_handler DMA6_IRQHandler - def_irq_default_handler DMA7_IRQHandler - def_irq_default_handler DMA8_IRQHandler - def_irq_default_handler DMA9_IRQHandler - def_irq_default_handler DMA10_IRQHandler - def_irq_default_handler DMA11_IRQHandler - def_irq_default_handler DMA12_IRQHandler - def_irq_default_handler DMA13_IRQHandler - def_irq_default_handler DMA14_IRQHandler - def_irq_default_handler DMA15_IRQHandler - def_irq_default_handler DMA_Error_IRQHandler - def_irq_default_handler MCM_IRQHandler - def_irq_default_handler FTF_IRQHandler - def_irq_default_handler Read_Collision_IRQHandler - def_irq_default_handler LVD_LVW_IRQHandler - def_irq_default_handler LLW_IRQHandler - def_irq_default_handler Watchdog_IRQHandler - def_irq_default_handler RNG_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler I2S0_Tx_IRQHandler - def_irq_default_handler I2S0_Rx_IRQHandler - def_irq_default_handler LPUART0_IRQHandler - def_irq_default_handler UART0_RX_TX_IRQHandler - def_irq_default_handler UART0_ERR_IRQHandler - def_irq_default_handler UART1_RX_TX_IRQHandler - def_irq_default_handler UART1_ERR_IRQHandler - def_irq_default_handler UART2_RX_TX_IRQHandler - def_irq_default_handler UART2_ERR_IRQHandler - def_irq_default_handler Reserved53_IRQHandler - def_irq_default_handler Reserved54_IRQHandler - def_irq_default_handler ADC0_IRQHandler - def_irq_default_handler CMP0_IRQHandler - def_irq_default_handler CMP1_IRQHandler - def_irq_default_handler FTM0_IRQHandler - def_irq_default_handler FTM1_IRQHandler - def_irq_default_handler FTM2_IRQHandler - def_irq_default_handler Reserved61_IRQHandler - def_irq_default_handler RTC_IRQHandler - def_irq_default_handler RTC_Seconds_IRQHandler - def_irq_default_handler PIT0_IRQHandler - def_irq_default_handler PIT1_IRQHandler - def_irq_default_handler PIT2_IRQHandler - def_irq_default_handler PIT3_IRQHandler - def_irq_default_handler PDB0_IRQHandler - def_irq_default_handler USB0_IRQHandler - def_irq_default_handler Reserved70_IRQHandler - def_irq_default_handler Reserved71_IRQHandler - def_irq_default_handler DAC0_IRQHandler - def_irq_default_handler MCG_IRQHandler - def_irq_default_handler LPTimer_IRQHandler - def_irq_default_handler PORTA_IRQHandler - def_irq_default_handler PORTB_IRQHandler - def_irq_default_handler PORTC_IRQHandler - def_irq_default_handler PORTD_IRQHandler - def_irq_default_handler PORTE_IRQHandler - def_irq_default_handler SWI_IRQHandler - def_irq_default_handler Reserved81_IRQHandler - def_irq_default_handler Reserved82_IRQHandler - def_irq_default_handler Reserved83_IRQHandler - def_irq_default_handler Reserved84_IRQHandler - def_irq_default_handler Reserved85_IRQHandler - def_irq_default_handler Reserved86_IRQHandler - def_irq_default_handler FTM3_IRQHandler - def_irq_default_handler DAC1_IRQHandler - def_irq_default_handler ADC1_IRQHandler - def_irq_default_handler Reserved90_IRQHandler - def_irq_default_handler Reserved91_IRQHandler - def_irq_default_handler Reserved92_IRQHandler - def_irq_default_handler Reserved93_IRQHandler - def_irq_default_handler Reserved94_IRQHandler - def_irq_default_handler Reserved95_IRQHandler - def_irq_default_handler Reserved96_IRQHandler - def_irq_default_handler Reserved97_IRQHandler - def_irq_default_handler Reserved98_IRQHandler - def_irq_default_handler Reserved99_IRQHandler - def_irq_default_handler Reserved100_IRQHandler - def_irq_default_handler Reserved101_IRQHandler - def_irq_default_handler DefaultISR - -/* Flash protection region, placed at 0x400 */ - .text - .thumb - .align 2 - .section .kinetis_flash_config_field,"a",%progbits -kinetis_flash_config: - .long 0xffffffff - .long 0xffffffff - .long 0xffffffff - .long 0xfffffffe - - .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf deleted file mode 100644 index 4955517c8ec..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007ffff; -define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff03ff; -define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0400; -define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; -/*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = 0x4000; -define symbol __ICFEDIT_size_heap__ = 0x8000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_RAM2_start__ = 0x20000000; -define symbol __region_RAM2_end__ = 0x2000ffff; - -define symbol __FlashConfig_start__ = 0x00000400; -define symbol __FlashConfig_end__ = 0x0000040f; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__]; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in FlashConfig_region {section FlashConfig}; - -place in ROM_region { readonly }; - -place in RAM_region { readwrite, block HEAP, block CSTACK }; diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S deleted file mode 100644 index 90ee34879a9..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S +++ /dev/null @@ -1,535 +0,0 @@ -/************************************************** - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 16 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:ROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - ; External Interrupts - DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete - DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete - DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete - DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete - DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete - DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete - DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete - DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete - DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete - DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete - DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete - DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete - DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete - DCD DMA_Error_IRQHandler ; DMA Error Interrupt - DCD MCM_IRQHandler ; Normal Interrupt - DCD FTFE_IRQHandler ; FTFE Command complete interrupt - DCD Read_Collision_IRQHandler ; Read Collision Interrupt - DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ; Low Leakage Wakeup - DCD Watchdog_IRQHandler ; WDOG Interrupt - DCD 0 ; Reserved - DCD I2C0_IRQHandler ; I2C0 interrupt - DCD I2C1_IRQHandler ; I2C1 interrupt - DCD SPI0_IRQHandler ; SPI0 Interrupt - DCD SPI1_IRQHandler ; SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt - DCD UART0_LON_IRQHandler ; UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ; UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ; UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ; UART2 Error interrupt - DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt - DCD UART3_ERR_IRQHandler ; UART3 Error interrupt - DCD ADC0_IRQHandler ; ADC0 interrupt - DCD CMP0_IRQHandler ; CMP0 interrupt - DCD CMP1_IRQHandler ; CMP1 interrupt - DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ; CMT interrupt - DCD RTC_IRQHandler ; RTC interrupt - DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt - DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ; PDB0 Interrupt - DCD USB0_IRQHandler ; USB0 interrupt - DCD USBDCD_IRQHandler ; USBDCD Interrupt - DCD 0 ; Reserved - DCD DAC0_IRQHandler ; DAC0 interrupt - DCD MCG_IRQHandler ; MCG Interrupt - DCD LPTimer_IRQHandler ; LPTimer interrupt - DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTB_IRQHandler ; Port B interrupt - DCD PORTC_IRQHandler ; Port C interrupt - DCD PORTD_IRQHandler ; Port D interrupt - DCD PORTE_IRQHandler ; Port E interrupt - DCD SWI_IRQHandler ; Software interrupt - DCD SPI2_IRQHandler ; SPI2 Interrupt - DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt - DCD UART4_ERR_IRQHandler ; UART4 Error interrupt - DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt - DCD UART5_ERR_IRQHandler ; UART5 Error interrupt - DCD CMP2_IRQHandler ; CMP2 interrupt - DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt - DCD DAC1_IRQHandler ; DAC1 interrupt - DCD ADC1_IRQHandler ; ADC1 interrupt - DCD I2C2_IRQHandler ; I2C2 interrupt - DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ; CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt - DCD SDHC_IRQHandler ; SDHC interrupt - DCD Default_Handler ; 98 - DCD Default_Handler ; 99 - DCD Default_Handler ; 100 - DCD Default_Handler ; 101 - DCD Default_Handler ; 102 - DCD Default_Handler ; 103 - DCD Default_Handler ; 104 - DCD Default_Handler ; 105 - DCD Default_Handler ; 106 - DCD Default_Handler ; 107 - DCD Default_Handler ; 108 - DCD Default_Handler ; 109 - DCD Default_Handler ; 110 - DCD Default_Handler ; 111 - DCD Default_Handler ; 112 - DCD Default_Handler ; 113 - DCD Default_Handler ; 114 - DCD Default_Handler ; 115 - DCD Default_Handler ; 116 - DCD Default_Handler ; 117 - DCD Default_Handler ; 118 - DCD Default_Handler ; 119 - DCD Default_Handler ; 120 - DCD Default_Handler ; 121 - DCD Default_Handler ; 122 - DCD Default_Handler ; 123 - DCD Default_Handler ; 124 - DCD Default_Handler ; 125 - DCD Default_Handler ; 126 - DCD Default_Handler ; 127 - DCD Default_Handler ; 128 - DCD Default_Handler ; 129 - DCD Default_Handler ; 130 - DCD Default_Handler ; 131 - DCD Default_Handler ; 132 - DCD Default_Handler ; 133 - DCD Default_Handler ; 134 - DCD Default_Handler ; 135 - DCD Default_Handler ; 136 - DCD Default_Handler ; 137 - DCD Default_Handler ; 138 - DCD Default_Handler ; 139 - DCD Default_Handler ; 140 - DCD Default_Handler ; 141 - DCD Default_Handler ; 142 - DCD Default_Handler ; 143 - DCD Default_Handler ; 144 - DCD Default_Handler ; 145 - DCD Default_Handler ; 146 - DCD Default_Handler ; 147 - DCD Default_Handler ; 148 - DCD Default_Handler ; 149 - DCD Default_Handler ; 150 - DCD Default_Handler ; 151 - DCD Default_Handler ; 152 - DCD Default_Handler ; 153 - DCD Default_Handler ; 154 - DCD Default_Handler ; 155 - DCD Default_Handler ; 156 - DCD Default_Handler ; 157 - DCD Default_Handler ; 158 - DCD Default_Handler ; 159 - DCD Default_Handler ; 160 - DCD Default_Handler ; 161 - DCD Default_Handler ; 162 - DCD Default_Handler ; 163 - DCD Default_Handler ; 164 - DCD Default_Handler ; 165 - DCD Default_Handler ; 166 - DCD Default_Handler ; 167 - DCD Default_Handler ; 168 - DCD Default_Handler ; 169 - DCD Default_Handler ; 170 - DCD Default_Handler ; 171 - DCD Default_Handler ; 172 - DCD Default_Handler ; 173 - DCD Default_Handler ; 174 - DCD Default_Handler ; 175 - DCD Default_Handler ; 176 - DCD Default_Handler ; 177 - DCD Default_Handler ; 178 - DCD Default_Handler ; 179 - DCD Default_Handler ; 180 - DCD Default_Handler ; 181 - DCD Default_Handler ; 182 - DCD Default_Handler ; 183 - DCD Default_Handler ; 184 - DCD Default_Handler ; 185 - DCD Default_Handler ; 186 - DCD Default_Handler ; 187 - DCD Default_Handler ; 188 - DCD Default_Handler ; 189 - DCD Default_Handler ; 190 - DCD Default_Handler ; 191 - DCD Default_Handler ; 192 - DCD Default_Handler ; 193 - DCD Default_Handler ; 194 - DCD Default_Handler ; 195 - DCD Default_Handler ; 196 - DCD Default_Handler ; 197 - DCD Default_Handler ; 198 - DCD Default_Handler ; 199 - DCD Default_Handler ; 200 - DCD Default_Handler ; 201 - DCD Default_Handler ; 202 - DCD Default_Handler ; 203 - DCD Default_Handler ; 204 - DCD Default_Handler ; 205 - DCD Default_Handler ; 206 - DCD Default_Handler ; 207 - DCD Default_Handler ; 208 - DCD Default_Handler ; 209 - DCD Default_Handler ; 210 - DCD Default_Handler ; 211 - DCD Default_Handler ; 212 - DCD Default_Handler ; 213 - DCD Default_Handler ; 214 - DCD Default_Handler ; 215 - DCD Default_Handler ; 216 - DCD Default_Handler ; 217 - DCD Default_Handler ; 218 - DCD Default_Handler ; 219 - DCD Default_Handler ; 220 - DCD Default_Handler ; 221 - DCD Default_Handler ; 222 - DCD Default_Handler ; 223 - DCD Default_Handler ; 224 - DCD Default_Handler ; 225 - DCD Default_Handler ; 226 - DCD Default_Handler ; 227 - DCD Default_Handler ; 228 - DCD Default_Handler ; 229 - DCD Default_Handler ; 230 - DCD Default_Handler ; 231 - DCD Default_Handler ; 232 - DCD Default_Handler ; 233 - DCD Default_Handler ; 234 - DCD Default_Handler ; 235 - DCD Default_Handler ; 236 - DCD Default_Handler ; 237 - DCD Default_Handler ; 238 - DCD Default_Handler ; 239 - DCD Default_Handler ; 240 - DCD Default_Handler ; 241 - DCD Default_Handler ; 242 - DCD Default_Handler ; 243 - DCD Default_Handler ; 244 - DCD Default_Handler ; 245 - DCD Default_Handler ; 246 - DCD Default_Handler ; 247 - DCD Default_Handler ; 248 - DCD Default_Handler ; 249 - DCD Default_Handler ; 250 - DCD Default_Handler ; 251 - DCD Default_Handler ; 252 - DCD Default_Handler ; 253 - DCD Default_Handler ; 254 - DCD Default_Handler ; 255 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;;Flash Configuration -;;16-byte flash configuration field that stores default protection settings (loaded on reset) -;;and security information that allows the MCU to restrict acces to the FTFL module. - -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF - -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0^0xFF - -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1^0xFF - -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2^0xFF - -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3^0xFF - -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT^0xFF - -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT^0xFF - -FOPT EQU 0xFF - -FSEC EQU 0xFE - SECTION FlashConfig:CONST:REORDER:ROOT(2) -Config: - DATA - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA8_IRQHandler - PUBWEAK DMA9_IRQHandler - PUBWEAK DMA10_IRQHandler - PUBWEAK DMA11_IRQHandler - PUBWEAK DMA12_IRQHandler - PUBWEAK DMA13_IRQHandler - PUBWEAK DMA14_IRQHandler - PUBWEAK DMA15_IRQHandler - PUBWEAK DMA_Error_IRQHandler - PUBWEAK MCM_IRQHandler - PUBWEAK FTFE_IRQHandler - PUBWEAK Read_Collision_IRQHandler - PUBWEAK LVD_LVW_IRQHandler - PUBWEAK LLW_IRQHandler - PUBWEAK Watchdog_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK I2S0_Tx_IRQHandler - PUBWEAK I2S0_Rx_IRQHandler - PUBWEAK UART0_LON_IRQHandler - PUBWEAK UART0_RX_TX_IRQHandler - PUBWEAK UART0_ERR_IRQHandler - PUBWEAK UART1_RX_TX_IRQHandler - PUBWEAK UART1_ERR_IRQHandler - PUBWEAK UART2_RX_TX_IRQHandler - PUBWEAK UART2_ERR_IRQHandler - PUBWEAK UART3_RX_TX_IRQHandler - PUBWEAK UART3_ERR_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK CMP1_IRQHandler - PUBWEAK FTM0_IRQHandler - PUBWEAK FTM1_IRQHandler - PUBWEAK FTM2_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK PIT1_IRQHandler - PUBWEAK PIT2_IRQHandler - PUBWEAK PIT3_IRQHandler - PUBWEAK PDB0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK USBDCD_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTimer_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK SWI_IRQHandler - PUBWEAK SPI2_IRQHandler - PUBWEAK UART4_RX_TX_IRQHandler - PUBWEAK UART4_ERR_IRQHandler - PUBWEAK UART5_RX_TX_IRQHandler - PUBWEAK UART5_ERR_IRQHandler - PUBWEAK CMP2_IRQHandler - PUBWEAK FTM3_IRQHandler - PUBWEAK DAC1_IRQHandler - PUBWEAK ADC1_IRQHandler - PUBWEAK I2C2_IRQHandler - PUBWEAK CAN0_ORed_Message_buffer_IRQHandler - PUBWEAK CAN0_Bus_Off_IRQHandler - PUBWEAK CAN0_Error_IRQHandler - PUBWEAK CAN0_Tx_Warning_IRQHandler - PUBWEAK CAN0_Rx_Warning_IRQHandler - PUBWEAK CAN0_Wake_Up_IRQHandler - PUBWEAK SDHC_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -DMA4_IRQHandler -DMA5_IRQHandler -DMA6_IRQHandler -DMA7_IRQHandler -DMA8_IRQHandler -DMA9_IRQHandler -DMA10_IRQHandler -DMA11_IRQHandler -DMA12_IRQHandler -DMA13_IRQHandler -DMA14_IRQHandler -DMA15_IRQHandler -DMA_Error_IRQHandler -MCM_IRQHandler -FTFE_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLW_IRQHandler -Watchdog_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -I2S0_Tx_IRQHandler -I2S0_Rx_IRQHandler -UART0_LON_IRQHandler -UART0_RX_TX_IRQHandler -UART0_ERR_IRQHandler -UART1_RX_TX_IRQHandler -UART1_ERR_IRQHandler -UART2_RX_TX_IRQHandler -UART2_ERR_IRQHandler -UART3_RX_TX_IRQHandler -UART3_ERR_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -DAC0_IRQHandler -MCG_IRQHandler -LPTimer_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -SPI2_IRQHandler -UART4_RX_TX_IRQHandler -UART4_ERR_IRQHandler -UART5_RX_TX_IRQHandler -UART5_ERR_IRQHandler -CMP2_IRQHandler -FTM3_IRQHandler -DAC1_IRQHandler -ADC1_IRQHandler -I2C2_IRQHandler -CAN0_ORed_Message_buffer_IRQHandler -CAN0_Bus_Off_IRQHandler -CAN0_Error_IRQHandler -CAN0_Tx_Warning_IRQHandler -CAN0_Rx_Warning_IRQHandler -CAN0_Wake_Up_IRQHandler -SDHC_IRQHandler -Default_Handler - - B Default_Handler - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h deleted file mode 100644 index ff19283b740..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MK22F51212.h" -#include "cmsis_nvic.h" - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c deleted file mode 100644 index 784193b6648..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c +++ /dev/null @@ -1,54 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR < NVIC_RAM_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h deleted file mode 100644 index 206b645437e..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h +++ /dev/null @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c deleted file mode 100644 index bc387c16c48..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c +++ /dev/null @@ -1,395 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140611 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK22F51212 - * @version 2.5 - * @date 2014-05-06 - * @brief Device specific configuration file for MK22F51212 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "cmsis.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - -#if (DISABLE_WDOG) - /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ - WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ - /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ - WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ - /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ - WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | - WDOG_STCTRLH_WAITEN_MASK | - WDOG_STCTRLH_STOPEN_MASK | - WDOG_STCTRLH_ALLOWUPDATE_MASK | - WDOG_STCTRLH_CLKSRC_MASK | - 0x0100U; -#endif /* (DISABLE_WDOG) */ - if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U) - { - if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U) - { - PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/ - } - } else { -#ifdef SYSTEM_RTC_CR_VALUE - SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; - if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */ - RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE); - RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK; - RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK; - } -#endif - } - - /* Power mode protection initialization */ -#ifdef SYSTEM_SMC_PMPROT_VALUE - SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE; -#endif - - /* High speed run mode enable */ -#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT)) - SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */ - while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */ - } -#endif - /* System clock initialization */ - /* Internal reference clock trim initialization */ -#if defined(SLOW_TRIM_ADDRESS) - if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */ - MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); - #endif /* defined(SLOW_TRIM_ADDRESS) */ - #if defined(SLOW_FINE_TRIM_ADDRESS) - MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK); - #endif - #if defined(FAST_TRIM_ADDRESS) - MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK); - #endif - #if defined(FAST_FINE_TRIM_ADDRESS) - MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK); - #endif /* defined(FAST_FINE_TRIM_ADDRESS) */ -#if defined(SLOW_TRIM_ADDRESS) - } - #endif /* defined(SLOW_TRIM_ADDRESS) */ - - /* Set system prescalers and clock sources */ - SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */ - SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */ - SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */ -#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) - /* Set MCG and OSC */ -#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U))) - /* SIM_SCGC5: PORTA=1 */ - SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR18: ISF=0,MUX=0 */ - PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) { - /* PORTA_PCR19: ISF=0,MUX=0 */ - PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } -#endif - MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ - MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ - /* Check that the source of the FLL reference clock is the requested one. */ - if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { - } - } else { - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { - } - } - MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ - MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ - OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ - MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ - #if (MCG_MODE == MCG_MODE_BLPI) - /* BLPI specific */ - MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ - #endif - -#else /* MCG_MODE */ - /* Set MCG and OSC */ -#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U) - /* SIM_SCGC5: PORTA=1 */ - SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR18: ISF=0,MUX=0 */ - PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) { - /* PORTA_PCR19: ISF=0,MUX=0 */ - PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } -#endif - MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ - MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ - OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ - MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ - #if (MCG_MODE == MCG_MODE_PEE) - MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/ - #else - MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ - #endif - if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) { - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ - } - } - /* Check that the source of the FLL reference clock is the requested one. */ - if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { - } - } else { - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { - } - } - MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ -#endif /* MCG_MODE */ - - /* Common for all MCG modes */ - - /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */ - MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */ - MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ - if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) { - MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */ - } - /* BLPE, PEE and PBE MCG mode specific */ - -#if (MCG_MODE == MCG_MODE_BLPE) - MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ -#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE)) - MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/ - } - #if (MCG_MODE == MCG_MODE_PEE) - MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK); - #endif -#endif -#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */ - } -#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ - } -#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ - } -#elif (MCG_MODE == MCG_MODE_PEE) - while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */ - } -#endif -#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT)) - SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */ - while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */ - } -#endif - -#if defined(SYSTEM_SIM_CLKDIV2_VALUE) - SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */ -#endif - - /* PLL loss of lock interrupt request initialization */ - if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) { - NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */ - } -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint16_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { - /* External reference clock is selected */ - switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { - case 0x00U: - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - break; - case 0x01U: - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - break; - case 0x02U: - default: - MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ - break; - } - if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { - switch (MCG->C1 & MCG_C1_FRDIV_MASK) { - case 0x38U: - Divider = 1536U; - break; - case 0x30U: - Divider = 1280U; - break; - default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - break; - } - } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - } - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x00U: - MCGOUTClock *= 640U; - break; - case 0x20U: - MCGOUTClock *= 1280U; - break; - case 0x40U: - MCGOUTClock *= 1920U; - break; - case 0x60U: - MCGOUTClock *= 2560U; - break; - case 0x80U: - MCGOUTClock *= 732U; - break; - case 0xA0U: - MCGOUTClock *= 1464U; - break; - case 0xC0U: - MCGOUTClock *= 2197U; - break; - case 0xE0U: - MCGOUTClock *= 2929U; - break; - default: - break; - } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - /* PLL is selected */ - Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); - MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { - /* External reference clock is selected */ - switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { - case 0x00U: - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - break; - case 0x01U: - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - break; - case 0x02U: - default: - MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ - break; - } - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h deleted file mode 100644 index bdeed9c5a2e..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h +++ /dev/null @@ -1,367 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140611 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK22F51212 - * @version 2.5 - * @date 2014-05-06 - * @brief Device specific configuration file for MK22F51212 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MK22F51212_H_ -#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#define DISABLE_WDOG 1 - -#ifndef CLOCK_SETUP - #define CLOCK_SETUP 4 -#endif - -/* MCG mode constants */ - -#define MCG_MODE_FEI 0U -#define MCG_MODE_FBI 1U -#define MCG_MODE_BLPI 2U -#define MCG_MODE_FEE 3U -#define MCG_MODE_FBE 4U -#define MCG_MODE_BLPE 5U -#define MCG_MODE_PBE 6U -#define MCG_MODE_PEE 7U - -/* Predefined clock setups - 0 ... Default part configuration - Multipurpose Clock Generator (MCG) in FEI mode. - Reference clock source for MCG module: Slow internal reference clock - Core clock = 20.97152MHz - Bus clock = 20.97152MHz - 1 ... Maximum achievable clock frequency configuration - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 120MHz - Bus clock = 60MHz - 2 ... Chip internaly clocked, ready for Very Low Power Run mode. - Multipurpose Clock Generator (MCG) in BLPI mode. - Reference clock source for MCG module: Fast internal reference clock - Core clock = 4MHz - Bus clock = 4MHz - 3 ... Chip externally clocked, ready for Very Low Power Run mode. - Multipurpose Clock Generator (MCG) in BLPE mode. - Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 4MHz - Bus clock = 4MHz - 4 ... USB clock setup - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 120MHz - Bus clock = 60MHz - 5 ... Maximum achievable clock frequency configuration in RUN mode - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 80MHz - Bus clock = 40MHz - */ - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ -#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ -#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ - -/* RTC oscillator setting */ -/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ -#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ - -/* Low power mode enable */ -/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */ -#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */ - -/* Internal reference clock trim */ -/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ - -#if (CLOCK_SETUP == 0) - #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ -/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 1) - #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ - #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */ - #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 2) - #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ - /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 3) - #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ - /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ -/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 4) - #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ - #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */ - #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */ -/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ - #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 5) - #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ - #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */ - #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ -#endif - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MK22F51212_H_) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h deleted file mode 100644 index 28a78cedcde..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h +++ /dev/null @@ -1,14420 +0,0 @@ -/* -** ################################################################### -** Processors: MK64FN1M0VDC12 -** MK64FN1M0VLL12 -** MK64FN1M0VLQ12 -** MK64FN1M0VMD12 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK64F12 -** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK64F12.h - * @version 2.5 - * @date 2014-02-10 - * @brief CMSIS Peripheral Access Layer for MK64F12 - * - * CMSIS Peripheral Access Layer for MK64F12 - */ - - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK64F12_H_) /* Check if memory map has not been already included */ -#define MK64F12_H_ -#define MCU_MK64F12 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0005u - -/** - * @brief Macro to calculate address of an aliased word in the peripheral - * bitband area for a peripheral register and bit (bit band region 0x40000000 to - * 0x400FFFFF). - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Address of the aliased word in the peripheral bitband area. - */ -#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 32bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 16bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 8bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ - DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ - DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ - DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ - DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ - DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ - DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ - DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ - DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ - DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ - DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ - DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ - DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ - DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ - DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ - DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ - MCM_IRQn = 17, /**< Normal Interrupt */ - FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ - Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG Interrupt */ - RNG_IRQn = 23, /**< RNG Interrupt */ - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, /**< I2C1 interrupt */ - SPI0_IRQn = 26, /**< SPI0 Interrupt */ - SPI1_IRQn = 27, /**< SPI1 Interrupt */ - I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ - UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ - UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ - UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ - UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ - UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ - UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ - UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ - UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ - UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ - ADC0_IRQn = 39, /**< ADC0 interrupt */ - CMP0_IRQn = 40, /**< CMP0 interrupt */ - CMP1_IRQn = 41, /**< CMP1 interrupt */ - FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ - CMT_IRQn = 45, /**< CMT interrupt */ - RTC_IRQn = 46, /**< RTC interrupt */ - RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ - PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 52, /**< PDB0 Interrupt */ - USB0_IRQn = 53, /**< USB0 interrupt */ - USBDCD_IRQn = 54, /**< USBDCD Interrupt */ - Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ - DAC0_IRQn = 56, /**< DAC0 interrupt */ - MCG_IRQn = 57, /**< MCG Interrupt */ - LPTimer_IRQn = 58, /**< LPTimer interrupt */ - PORTA_IRQn = 59, /**< Port A interrupt */ - PORTB_IRQn = 60, /**< Port B interrupt */ - PORTC_IRQn = 61, /**< Port C interrupt */ - PORTD_IRQn = 62, /**< Port D interrupt */ - PORTE_IRQn = 63, /**< Port E interrupt */ - SWI_IRQn = 64, /**< Software interrupt */ - SPI2_IRQn = 65, /**< SPI2 Interrupt */ - UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ - UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ - UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ - UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ - CMP2_IRQn = 70, /**< CMP2 interrupt */ - FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ - DAC1_IRQn = 72, /**< DAC1 interrupt */ - ADC1_IRQn = 73, /**< ADC1 interrupt */ - I2C2_IRQn = 74, /**< I2C2 interrupt */ - CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ - CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ - CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ - CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ - CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ - CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ - SDHC_IRQn = 81, /**< SDHC interrupt */ - ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ - ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ - ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ - ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK64F12.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) -#define AIPS_PACRA_REG(base) ((base)->PACRA) -#define AIPS_PACRB_REG(base) ((base)->PACRB) -#define AIPS_PACRC_REG(base) ((base)->PACRC) -#define AIPS_PACRD_REG(base) ((base)->PACRD) -#define AIPS_PACRE_REG(base) ((base)->PACRE) -#define AIPS_PACRF_REG(base) ((base)->PACRF) -#define AIPS_PACRG_REG(base) ((base)->PACRG) -#define AIPS_PACRH_REG(base) ((base)->PACRH) -#define AIPS_PACRI_REG(base) ((base)->PACRI) -#define AIPS_PACRJ_REG(base) ((base)->PACRJ) -#define AIPS_PACRK_REG(base) ((base)->PACRK) -#define AIPS_PACRL_REG(base) ((base)->PACRL) -#define AIPS_PACRM_REG(base) ((base)->PACRM) -#define AIPS_PACRN_REG(base) ((base)->PACRN) -#define AIPS_PACRO_REG(base) ((base)->PACRO) -#define AIPS_PACRP_REG(base) ((base)->PACRP) -#define AIPS_PACRU_REG(base) ((base)->PACRU) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- AIPS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPS_Register_Masks AIPS Register Masks - * @{ - */ - -/* MPRA Bit Fields */ -#define AIPS_MPRA_MPL5_MASK 0x100u -#define AIPS_MPRA_MPL5_SHIFT 8 -#define AIPS_MPRA_MTW5_MASK 0x200u -#define AIPS_MPRA_MTW5_SHIFT 9 -#define AIPS_MPRA_MTR5_MASK 0x400u -#define AIPS_MPRA_MTR5_SHIFT 10 -#define AIPS_MPRA_MPL4_MASK 0x1000u -#define AIPS_MPRA_MPL4_SHIFT 12 -#define AIPS_MPRA_MTW4_MASK 0x2000u -#define AIPS_MPRA_MTW4_SHIFT 13 -#define AIPS_MPRA_MTR4_MASK 0x4000u -#define AIPS_MPRA_MTR4_SHIFT 14 -#define AIPS_MPRA_MPL3_MASK 0x10000u -#define AIPS_MPRA_MPL3_SHIFT 16 -#define AIPS_MPRA_MTW3_MASK 0x20000u -#define AIPS_MPRA_MTW3_SHIFT 17 -#define AIPS_MPRA_MTR3_MASK 0x40000u -#define AIPS_MPRA_MTR3_SHIFT 18 -#define AIPS_MPRA_MPL2_MASK 0x100000u -#define AIPS_MPRA_MPL2_SHIFT 20 -#define AIPS_MPRA_MTW2_MASK 0x200000u -#define AIPS_MPRA_MTW2_SHIFT 21 -#define AIPS_MPRA_MTR2_MASK 0x400000u -#define AIPS_MPRA_MTR2_SHIFT 22 -#define AIPS_MPRA_MPL1_MASK 0x1000000u -#define AIPS_MPRA_MPL1_SHIFT 24 -#define AIPS_MPRA_MTW1_MASK 0x2000000u -#define AIPS_MPRA_MTW1_SHIFT 25 -#define AIPS_MPRA_MTR1_MASK 0x4000000u -#define AIPS_MPRA_MTR1_SHIFT 26 -#define AIPS_MPRA_MPL0_MASK 0x10000000u -#define AIPS_MPRA_MPL0_SHIFT 28 -#define AIPS_MPRA_MTW0_MASK 0x20000000u -#define AIPS_MPRA_MTW0_SHIFT 29 -#define AIPS_MPRA_MTR0_MASK 0x40000000u -#define AIPS_MPRA_MTR0_SHIFT 30 -/* PACRA Bit Fields */ -#define AIPS_PACRA_TP7_MASK 0x1u -#define AIPS_PACRA_TP7_SHIFT 0 -#define AIPS_PACRA_WP7_MASK 0x2u -#define AIPS_PACRA_WP7_SHIFT 1 -#define AIPS_PACRA_SP7_MASK 0x4u -#define AIPS_PACRA_SP7_SHIFT 2 -#define AIPS_PACRA_TP6_MASK 0x10u -#define AIPS_PACRA_TP6_SHIFT 4 -#define AIPS_PACRA_WP6_MASK 0x20u -#define AIPS_PACRA_WP6_SHIFT 5 -#define AIPS_PACRA_SP6_MASK 0x40u -#define AIPS_PACRA_SP6_SHIFT 6 -#define AIPS_PACRA_TP5_MASK 0x100u -#define AIPS_PACRA_TP5_SHIFT 8 -#define AIPS_PACRA_WP5_MASK 0x200u -#define AIPS_PACRA_WP5_SHIFT 9 -#define AIPS_PACRA_SP5_MASK 0x400u -#define AIPS_PACRA_SP5_SHIFT 10 -#define AIPS_PACRA_TP4_MASK 0x1000u -#define AIPS_PACRA_TP4_SHIFT 12 -#define AIPS_PACRA_WP4_MASK 0x2000u -#define AIPS_PACRA_WP4_SHIFT 13 -#define AIPS_PACRA_SP4_MASK 0x4000u -#define AIPS_PACRA_SP4_SHIFT 14 -#define AIPS_PACRA_TP3_MASK 0x10000u -#define AIPS_PACRA_TP3_SHIFT 16 -#define AIPS_PACRA_WP3_MASK 0x20000u -#define AIPS_PACRA_WP3_SHIFT 17 -#define AIPS_PACRA_SP3_MASK 0x40000u -#define AIPS_PACRA_SP3_SHIFT 18 -#define AIPS_PACRA_TP2_MASK 0x100000u -#define AIPS_PACRA_TP2_SHIFT 20 -#define AIPS_PACRA_WP2_MASK 0x200000u -#define AIPS_PACRA_WP2_SHIFT 21 -#define AIPS_PACRA_SP2_MASK 0x400000u -#define AIPS_PACRA_SP2_SHIFT 22 -#define AIPS_PACRA_TP1_MASK 0x1000000u -#define AIPS_PACRA_TP1_SHIFT 24 -#define AIPS_PACRA_WP1_MASK 0x2000000u -#define AIPS_PACRA_WP1_SHIFT 25 -#define AIPS_PACRA_SP1_MASK 0x4000000u -#define AIPS_PACRA_SP1_SHIFT 26 -#define AIPS_PACRA_TP0_MASK 0x10000000u -#define AIPS_PACRA_TP0_SHIFT 28 -#define AIPS_PACRA_WP0_MASK 0x20000000u -#define AIPS_PACRA_WP0_SHIFT 29 -#define AIPS_PACRA_SP0_MASK 0x40000000u -#define AIPS_PACRA_SP0_SHIFT 30 -/* PACRB Bit Fields */ -#define AIPS_PACRB_TP7_MASK 0x1u -#define AIPS_PACRB_TP7_SHIFT 0 -#define AIPS_PACRB_WP7_MASK 0x2u -#define AIPS_PACRB_WP7_SHIFT 1 -#define AIPS_PACRB_SP7_MASK 0x4u -#define AIPS_PACRB_SP7_SHIFT 2 -#define AIPS_PACRB_TP6_MASK 0x10u -#define AIPS_PACRB_TP6_SHIFT 4 -#define AIPS_PACRB_WP6_MASK 0x20u -#define AIPS_PACRB_WP6_SHIFT 5 -#define AIPS_PACRB_SP6_MASK 0x40u -#define AIPS_PACRB_SP6_SHIFT 6 -#define AIPS_PACRB_TP5_MASK 0x100u -#define AIPS_PACRB_TP5_SHIFT 8 -#define AIPS_PACRB_WP5_MASK 0x200u -#define AIPS_PACRB_WP5_SHIFT 9 -#define AIPS_PACRB_SP5_MASK 0x400u -#define AIPS_PACRB_SP5_SHIFT 10 -#define AIPS_PACRB_TP4_MASK 0x1000u -#define AIPS_PACRB_TP4_SHIFT 12 -#define AIPS_PACRB_WP4_MASK 0x2000u -#define AIPS_PACRB_WP4_SHIFT 13 -#define AIPS_PACRB_SP4_MASK 0x4000u -#define AIPS_PACRB_SP4_SHIFT 14 -#define AIPS_PACRB_TP3_MASK 0x10000u -#define AIPS_PACRB_TP3_SHIFT 16 -#define AIPS_PACRB_WP3_MASK 0x20000u -#define AIPS_PACRB_WP3_SHIFT 17 -#define AIPS_PACRB_SP3_MASK 0x40000u -#define AIPS_PACRB_SP3_SHIFT 18 -#define AIPS_PACRB_TP2_MASK 0x100000u -#define AIPS_PACRB_TP2_SHIFT 20 -#define AIPS_PACRB_WP2_MASK 0x200000u -#define AIPS_PACRB_WP2_SHIFT 21 -#define AIPS_PACRB_SP2_MASK 0x400000u -#define AIPS_PACRB_SP2_SHIFT 22 -#define AIPS_PACRB_TP1_MASK 0x1000000u -#define AIPS_PACRB_TP1_SHIFT 24 -#define AIPS_PACRB_WP1_MASK 0x2000000u -#define AIPS_PACRB_WP1_SHIFT 25 -#define AIPS_PACRB_SP1_MASK 0x4000000u -#define AIPS_PACRB_SP1_SHIFT 26 -#define AIPS_PACRB_TP0_MASK 0x10000000u -#define AIPS_PACRB_TP0_SHIFT 28 -#define AIPS_PACRB_WP0_MASK 0x20000000u -#define AIPS_PACRB_WP0_SHIFT 29 -#define AIPS_PACRB_SP0_MASK 0x40000000u -#define AIPS_PACRB_SP0_SHIFT 30 -/* PACRC Bit Fields */ -#define AIPS_PACRC_TP7_MASK 0x1u -#define AIPS_PACRC_TP7_SHIFT 0 -#define AIPS_PACRC_WP7_MASK 0x2u -#define AIPS_PACRC_WP7_SHIFT 1 -#define AIPS_PACRC_SP7_MASK 0x4u -#define AIPS_PACRC_SP7_SHIFT 2 -#define AIPS_PACRC_TP6_MASK 0x10u -#define AIPS_PACRC_TP6_SHIFT 4 -#define AIPS_PACRC_WP6_MASK 0x20u -#define AIPS_PACRC_WP6_SHIFT 5 -#define AIPS_PACRC_SP6_MASK 0x40u -#define AIPS_PACRC_SP6_SHIFT 6 -#define AIPS_PACRC_TP5_MASK 0x100u -#define AIPS_PACRC_TP5_SHIFT 8 -#define AIPS_PACRC_WP5_MASK 0x200u -#define AIPS_PACRC_WP5_SHIFT 9 -#define AIPS_PACRC_SP5_MASK 0x400u -#define AIPS_PACRC_SP5_SHIFT 10 -#define AIPS_PACRC_TP4_MASK 0x1000u -#define AIPS_PACRC_TP4_SHIFT 12 -#define AIPS_PACRC_WP4_MASK 0x2000u -#define AIPS_PACRC_WP4_SHIFT 13 -#define AIPS_PACRC_SP4_MASK 0x4000u -#define AIPS_PACRC_SP4_SHIFT 14 -#define AIPS_PACRC_TP3_MASK 0x10000u -#define AIPS_PACRC_TP3_SHIFT 16 -#define AIPS_PACRC_WP3_MASK 0x20000u -#define AIPS_PACRC_WP3_SHIFT 17 -#define AIPS_PACRC_SP3_MASK 0x40000u -#define AIPS_PACRC_SP3_SHIFT 18 -#define AIPS_PACRC_TP2_MASK 0x100000u -#define AIPS_PACRC_TP2_SHIFT 20 -#define AIPS_PACRC_WP2_MASK 0x200000u -#define AIPS_PACRC_WP2_SHIFT 21 -#define AIPS_PACRC_SP2_MASK 0x400000u -#define AIPS_PACRC_SP2_SHIFT 22 -#define AIPS_PACRC_TP1_MASK 0x1000000u -#define AIPS_PACRC_TP1_SHIFT 24 -#define AIPS_PACRC_WP1_MASK 0x2000000u -#define AIPS_PACRC_WP1_SHIFT 25 -#define AIPS_PACRC_SP1_MASK 0x4000000u -#define AIPS_PACRC_SP1_SHIFT 26 -#define AIPS_PACRC_TP0_MASK 0x10000000u -#define AIPS_PACRC_TP0_SHIFT 28 -#define AIPS_PACRC_WP0_MASK 0x20000000u -#define AIPS_PACRC_WP0_SHIFT 29 -#define AIPS_PACRC_SP0_MASK 0x40000000u -#define AIPS_PACRC_SP0_SHIFT 30 -/* PACRD Bit Fields */ -#define AIPS_PACRD_TP7_MASK 0x1u -#define AIPS_PACRD_TP7_SHIFT 0 -#define AIPS_PACRD_WP7_MASK 0x2u -#define AIPS_PACRD_WP7_SHIFT 1 -#define AIPS_PACRD_SP7_MASK 0x4u -#define AIPS_PACRD_SP7_SHIFT 2 -#define AIPS_PACRD_TP6_MASK 0x10u -#define AIPS_PACRD_TP6_SHIFT 4 -#define AIPS_PACRD_WP6_MASK 0x20u -#define AIPS_PACRD_WP6_SHIFT 5 -#define AIPS_PACRD_SP6_MASK 0x40u -#define AIPS_PACRD_SP6_SHIFT 6 -#define AIPS_PACRD_TP5_MASK 0x100u -#define AIPS_PACRD_TP5_SHIFT 8 -#define AIPS_PACRD_WP5_MASK 0x200u -#define AIPS_PACRD_WP5_SHIFT 9 -#define AIPS_PACRD_SP5_MASK 0x400u -#define AIPS_PACRD_SP5_SHIFT 10 -#define AIPS_PACRD_TP4_MASK 0x1000u -#define AIPS_PACRD_TP4_SHIFT 12 -#define AIPS_PACRD_WP4_MASK 0x2000u -#define AIPS_PACRD_WP4_SHIFT 13 -#define AIPS_PACRD_SP4_MASK 0x4000u -#define AIPS_PACRD_SP4_SHIFT 14 -#define AIPS_PACRD_TP3_MASK 0x10000u -#define AIPS_PACRD_TP3_SHIFT 16 -#define AIPS_PACRD_WP3_MASK 0x20000u -#define AIPS_PACRD_WP3_SHIFT 17 -#define AIPS_PACRD_SP3_MASK 0x40000u -#define AIPS_PACRD_SP3_SHIFT 18 -#define AIPS_PACRD_TP2_MASK 0x100000u -#define AIPS_PACRD_TP2_SHIFT 20 -#define AIPS_PACRD_WP2_MASK 0x200000u -#define AIPS_PACRD_WP2_SHIFT 21 -#define AIPS_PACRD_SP2_MASK 0x400000u -#define AIPS_PACRD_SP2_SHIFT 22 -#define AIPS_PACRD_TP1_MASK 0x1000000u -#define AIPS_PACRD_TP1_SHIFT 24 -#define AIPS_PACRD_WP1_MASK 0x2000000u -#define AIPS_PACRD_WP1_SHIFT 25 -#define AIPS_PACRD_SP1_MASK 0x4000000u -#define AIPS_PACRD_SP1_SHIFT 26 -#define AIPS_PACRD_TP0_MASK 0x10000000u -#define AIPS_PACRD_TP0_SHIFT 28 -#define AIPS_PACRD_WP0_MASK 0x20000000u -#define AIPS_PACRD_WP0_SHIFT 29 -#define AIPS_PACRD_SP0_MASK 0x40000000u -#define AIPS_PACRD_SP0_SHIFT 30 -/* PACRE Bit Fields */ -#define AIPS_PACRE_TP7_MASK 0x1u -#define AIPS_PACRE_TP7_SHIFT 0 -#define AIPS_PACRE_WP7_MASK 0x2u -#define AIPS_PACRE_WP7_SHIFT 1 -#define AIPS_PACRE_SP7_MASK 0x4u -#define AIPS_PACRE_SP7_SHIFT 2 -#define AIPS_PACRE_TP6_MASK 0x10u -#define AIPS_PACRE_TP6_SHIFT 4 -#define AIPS_PACRE_WP6_MASK 0x20u -#define AIPS_PACRE_WP6_SHIFT 5 -#define AIPS_PACRE_SP6_MASK 0x40u -#define AIPS_PACRE_SP6_SHIFT 6 -#define AIPS_PACRE_TP5_MASK 0x100u -#define AIPS_PACRE_TP5_SHIFT 8 -#define AIPS_PACRE_WP5_MASK 0x200u -#define AIPS_PACRE_WP5_SHIFT 9 -#define AIPS_PACRE_SP5_MASK 0x400u -#define AIPS_PACRE_SP5_SHIFT 10 -#define AIPS_PACRE_TP4_MASK 0x1000u -#define AIPS_PACRE_TP4_SHIFT 12 -#define AIPS_PACRE_WP4_MASK 0x2000u -#define AIPS_PACRE_WP4_SHIFT 13 -#define AIPS_PACRE_SP4_MASK 0x4000u -#define AIPS_PACRE_SP4_SHIFT 14 -#define AIPS_PACRE_TP3_MASK 0x10000u -#define AIPS_PACRE_TP3_SHIFT 16 -#define AIPS_PACRE_WP3_MASK 0x20000u -#define AIPS_PACRE_WP3_SHIFT 17 -#define AIPS_PACRE_SP3_MASK 0x40000u -#define AIPS_PACRE_SP3_SHIFT 18 -#define AIPS_PACRE_TP2_MASK 0x100000u -#define AIPS_PACRE_TP2_SHIFT 20 -#define AIPS_PACRE_WP2_MASK 0x200000u -#define AIPS_PACRE_WP2_SHIFT 21 -#define AIPS_PACRE_SP2_MASK 0x400000u -#define AIPS_PACRE_SP2_SHIFT 22 -#define AIPS_PACRE_TP1_MASK 0x1000000u -#define AIPS_PACRE_TP1_SHIFT 24 -#define AIPS_PACRE_WP1_MASK 0x2000000u -#define AIPS_PACRE_WP1_SHIFT 25 -#define AIPS_PACRE_SP1_MASK 0x4000000u -#define AIPS_PACRE_SP1_SHIFT 26 -#define AIPS_PACRE_TP0_MASK 0x10000000u -#define AIPS_PACRE_TP0_SHIFT 28 -#define AIPS_PACRE_WP0_MASK 0x20000000u -#define AIPS_PACRE_WP0_SHIFT 29 -#define AIPS_PACRE_SP0_MASK 0x40000000u -#define AIPS_PACRE_SP0_SHIFT 30 -/* PACRF Bit Fields */ -#define AIPS_PACRF_TP7_MASK 0x1u -#define AIPS_PACRF_TP7_SHIFT 0 -#define AIPS_PACRF_WP7_MASK 0x2u -#define AIPS_PACRF_WP7_SHIFT 1 -#define AIPS_PACRF_SP7_MASK 0x4u -#define AIPS_PACRF_SP7_SHIFT 2 -#define AIPS_PACRF_TP6_MASK 0x10u -#define AIPS_PACRF_TP6_SHIFT 4 -#define AIPS_PACRF_WP6_MASK 0x20u -#define AIPS_PACRF_WP6_SHIFT 5 -#define AIPS_PACRF_SP6_MASK 0x40u -#define AIPS_PACRF_SP6_SHIFT 6 -#define AIPS_PACRF_TP5_MASK 0x100u -#define AIPS_PACRF_TP5_SHIFT 8 -#define AIPS_PACRF_WP5_MASK 0x200u -#define AIPS_PACRF_WP5_SHIFT 9 -#define AIPS_PACRF_SP5_MASK 0x400u -#define AIPS_PACRF_SP5_SHIFT 10 -#define AIPS_PACRF_TP4_MASK 0x1000u -#define AIPS_PACRF_TP4_SHIFT 12 -#define AIPS_PACRF_WP4_MASK 0x2000u -#define AIPS_PACRF_WP4_SHIFT 13 -#define AIPS_PACRF_SP4_MASK 0x4000u -#define AIPS_PACRF_SP4_SHIFT 14 -#define AIPS_PACRF_TP3_MASK 0x10000u -#define AIPS_PACRF_TP3_SHIFT 16 -#define AIPS_PACRF_WP3_MASK 0x20000u -#define AIPS_PACRF_WP3_SHIFT 17 -#define AIPS_PACRF_SP3_MASK 0x40000u -#define AIPS_PACRF_SP3_SHIFT 18 -#define AIPS_PACRF_TP2_MASK 0x100000u -#define AIPS_PACRF_TP2_SHIFT 20 -#define AIPS_PACRF_WP2_MASK 0x200000u -#define AIPS_PACRF_WP2_SHIFT 21 -#define AIPS_PACRF_SP2_MASK 0x400000u -#define AIPS_PACRF_SP2_SHIFT 22 -#define AIPS_PACRF_TP1_MASK 0x1000000u -#define AIPS_PACRF_TP1_SHIFT 24 -#define AIPS_PACRF_WP1_MASK 0x2000000u -#define AIPS_PACRF_WP1_SHIFT 25 -#define AIPS_PACRF_SP1_MASK 0x4000000u -#define AIPS_PACRF_SP1_SHIFT 26 -#define AIPS_PACRF_TP0_MASK 0x10000000u -#define AIPS_PACRF_TP0_SHIFT 28 -#define AIPS_PACRF_WP0_MASK 0x20000000u -#define AIPS_PACRF_WP0_SHIFT 29 -#define AIPS_PACRF_SP0_MASK 0x40000000u -#define AIPS_PACRF_SP0_SHIFT 30 -/* PACRG Bit Fields */ -#define AIPS_PACRG_TP7_MASK 0x1u -#define AIPS_PACRG_TP7_SHIFT 0 -#define AIPS_PACRG_WP7_MASK 0x2u -#define AIPS_PACRG_WP7_SHIFT 1 -#define AIPS_PACRG_SP7_MASK 0x4u -#define AIPS_PACRG_SP7_SHIFT 2 -#define AIPS_PACRG_TP6_MASK 0x10u -#define AIPS_PACRG_TP6_SHIFT 4 -#define AIPS_PACRG_WP6_MASK 0x20u -#define AIPS_PACRG_WP6_SHIFT 5 -#define AIPS_PACRG_SP6_MASK 0x40u -#define AIPS_PACRG_SP6_SHIFT 6 -#define AIPS_PACRG_TP5_MASK 0x100u -#define AIPS_PACRG_TP5_SHIFT 8 -#define AIPS_PACRG_WP5_MASK 0x200u -#define AIPS_PACRG_WP5_SHIFT 9 -#define AIPS_PACRG_SP5_MASK 0x400u -#define AIPS_PACRG_SP5_SHIFT 10 -#define AIPS_PACRG_TP4_MASK 0x1000u -#define AIPS_PACRG_TP4_SHIFT 12 -#define AIPS_PACRG_WP4_MASK 0x2000u -#define AIPS_PACRG_WP4_SHIFT 13 -#define AIPS_PACRG_SP4_MASK 0x4000u -#define AIPS_PACRG_SP4_SHIFT 14 -#define AIPS_PACRG_TP3_MASK 0x10000u -#define AIPS_PACRG_TP3_SHIFT 16 -#define AIPS_PACRG_WP3_MASK 0x20000u -#define AIPS_PACRG_WP3_SHIFT 17 -#define AIPS_PACRG_SP3_MASK 0x40000u -#define AIPS_PACRG_SP3_SHIFT 18 -#define AIPS_PACRG_TP2_MASK 0x100000u -#define AIPS_PACRG_TP2_SHIFT 20 -#define AIPS_PACRG_WP2_MASK 0x200000u -#define AIPS_PACRG_WP2_SHIFT 21 -#define AIPS_PACRG_SP2_MASK 0x400000u -#define AIPS_PACRG_SP2_SHIFT 22 -#define AIPS_PACRG_TP1_MASK 0x1000000u -#define AIPS_PACRG_TP1_SHIFT 24 -#define AIPS_PACRG_WP1_MASK 0x2000000u -#define AIPS_PACRG_WP1_SHIFT 25 -#define AIPS_PACRG_SP1_MASK 0x4000000u -#define AIPS_PACRG_SP1_SHIFT 26 -#define AIPS_PACRG_TP0_MASK 0x10000000u -#define AIPS_PACRG_TP0_SHIFT 28 -#define AIPS_PACRG_WP0_MASK 0x20000000u -#define AIPS_PACRG_WP0_SHIFT 29 -#define AIPS_PACRG_SP0_MASK 0x40000000u -#define AIPS_PACRG_SP0_SHIFT 30 -/* PACRH Bit Fields */ -#define AIPS_PACRH_TP7_MASK 0x1u -#define AIPS_PACRH_TP7_SHIFT 0 -#define AIPS_PACRH_WP7_MASK 0x2u -#define AIPS_PACRH_WP7_SHIFT 1 -#define AIPS_PACRH_SP7_MASK 0x4u -#define AIPS_PACRH_SP7_SHIFT 2 -#define AIPS_PACRH_TP6_MASK 0x10u -#define AIPS_PACRH_TP6_SHIFT 4 -#define AIPS_PACRH_WP6_MASK 0x20u -#define AIPS_PACRH_WP6_SHIFT 5 -#define AIPS_PACRH_SP6_MASK 0x40u -#define AIPS_PACRH_SP6_SHIFT 6 -#define AIPS_PACRH_TP5_MASK 0x100u -#define AIPS_PACRH_TP5_SHIFT 8 -#define AIPS_PACRH_WP5_MASK 0x200u -#define AIPS_PACRH_WP5_SHIFT 9 -#define AIPS_PACRH_SP5_MASK 0x400u -#define AIPS_PACRH_SP5_SHIFT 10 -#define AIPS_PACRH_TP4_MASK 0x1000u -#define AIPS_PACRH_TP4_SHIFT 12 -#define AIPS_PACRH_WP4_MASK 0x2000u -#define AIPS_PACRH_WP4_SHIFT 13 -#define AIPS_PACRH_SP4_MASK 0x4000u -#define AIPS_PACRH_SP4_SHIFT 14 -#define AIPS_PACRH_TP3_MASK 0x10000u -#define AIPS_PACRH_TP3_SHIFT 16 -#define AIPS_PACRH_WP3_MASK 0x20000u -#define AIPS_PACRH_WP3_SHIFT 17 -#define AIPS_PACRH_SP3_MASK 0x40000u -#define AIPS_PACRH_SP3_SHIFT 18 -#define AIPS_PACRH_TP2_MASK 0x100000u -#define AIPS_PACRH_TP2_SHIFT 20 -#define AIPS_PACRH_WP2_MASK 0x200000u -#define AIPS_PACRH_WP2_SHIFT 21 -#define AIPS_PACRH_SP2_MASK 0x400000u -#define AIPS_PACRH_SP2_SHIFT 22 -#define AIPS_PACRH_TP1_MASK 0x1000000u -#define AIPS_PACRH_TP1_SHIFT 24 -#define AIPS_PACRH_WP1_MASK 0x2000000u -#define AIPS_PACRH_WP1_SHIFT 25 -#define AIPS_PACRH_SP1_MASK 0x4000000u -#define AIPS_PACRH_SP1_SHIFT 26 -#define AIPS_PACRH_TP0_MASK 0x10000000u -#define AIPS_PACRH_TP0_SHIFT 28 -#define AIPS_PACRH_WP0_MASK 0x20000000u -#define AIPS_PACRH_WP0_SHIFT 29 -#define AIPS_PACRH_SP0_MASK 0x40000000u -#define AIPS_PACRH_SP0_SHIFT 30 -/* PACRI Bit Fields */ -#define AIPS_PACRI_TP7_MASK 0x1u -#define AIPS_PACRI_TP7_SHIFT 0 -#define AIPS_PACRI_WP7_MASK 0x2u -#define AIPS_PACRI_WP7_SHIFT 1 -#define AIPS_PACRI_SP7_MASK 0x4u -#define AIPS_PACRI_SP7_SHIFT 2 -#define AIPS_PACRI_TP6_MASK 0x10u -#define AIPS_PACRI_TP6_SHIFT 4 -#define AIPS_PACRI_WP6_MASK 0x20u -#define AIPS_PACRI_WP6_SHIFT 5 -#define AIPS_PACRI_SP6_MASK 0x40u -#define AIPS_PACRI_SP6_SHIFT 6 -#define AIPS_PACRI_TP5_MASK 0x100u -#define AIPS_PACRI_TP5_SHIFT 8 -#define AIPS_PACRI_WP5_MASK 0x200u -#define AIPS_PACRI_WP5_SHIFT 9 -#define AIPS_PACRI_SP5_MASK 0x400u -#define AIPS_PACRI_SP5_SHIFT 10 -#define AIPS_PACRI_TP4_MASK 0x1000u -#define AIPS_PACRI_TP4_SHIFT 12 -#define AIPS_PACRI_WP4_MASK 0x2000u -#define AIPS_PACRI_WP4_SHIFT 13 -#define AIPS_PACRI_SP4_MASK 0x4000u -#define AIPS_PACRI_SP4_SHIFT 14 -#define AIPS_PACRI_TP3_MASK 0x10000u -#define AIPS_PACRI_TP3_SHIFT 16 -#define AIPS_PACRI_WP3_MASK 0x20000u -#define AIPS_PACRI_WP3_SHIFT 17 -#define AIPS_PACRI_SP3_MASK 0x40000u -#define AIPS_PACRI_SP3_SHIFT 18 -#define AIPS_PACRI_TP2_MASK 0x100000u -#define AIPS_PACRI_TP2_SHIFT 20 -#define AIPS_PACRI_WP2_MASK 0x200000u -#define AIPS_PACRI_WP2_SHIFT 21 -#define AIPS_PACRI_SP2_MASK 0x400000u -#define AIPS_PACRI_SP2_SHIFT 22 -#define AIPS_PACRI_TP1_MASK 0x1000000u -#define AIPS_PACRI_TP1_SHIFT 24 -#define AIPS_PACRI_WP1_MASK 0x2000000u -#define AIPS_PACRI_WP1_SHIFT 25 -#define AIPS_PACRI_SP1_MASK 0x4000000u -#define AIPS_PACRI_SP1_SHIFT 26 -#define AIPS_PACRI_TP0_MASK 0x10000000u -#define AIPS_PACRI_TP0_SHIFT 28 -#define AIPS_PACRI_WP0_MASK 0x20000000u -#define AIPS_PACRI_WP0_SHIFT 29 -#define AIPS_PACRI_SP0_MASK 0x40000000u -#define AIPS_PACRI_SP0_SHIFT 30 -/* PACRJ Bit Fields */ -#define AIPS_PACRJ_TP7_MASK 0x1u -#define AIPS_PACRJ_TP7_SHIFT 0 -#define AIPS_PACRJ_WP7_MASK 0x2u -#define AIPS_PACRJ_WP7_SHIFT 1 -#define AIPS_PACRJ_SP7_MASK 0x4u -#define AIPS_PACRJ_SP7_SHIFT 2 -#define AIPS_PACRJ_TP6_MASK 0x10u -#define AIPS_PACRJ_TP6_SHIFT 4 -#define AIPS_PACRJ_WP6_MASK 0x20u -#define AIPS_PACRJ_WP6_SHIFT 5 -#define AIPS_PACRJ_SP6_MASK 0x40u -#define AIPS_PACRJ_SP6_SHIFT 6 -#define AIPS_PACRJ_TP5_MASK 0x100u -#define AIPS_PACRJ_TP5_SHIFT 8 -#define AIPS_PACRJ_WP5_MASK 0x200u -#define AIPS_PACRJ_WP5_SHIFT 9 -#define AIPS_PACRJ_SP5_MASK 0x400u -#define AIPS_PACRJ_SP5_SHIFT 10 -#define AIPS_PACRJ_TP4_MASK 0x1000u -#define AIPS_PACRJ_TP4_SHIFT 12 -#define AIPS_PACRJ_WP4_MASK 0x2000u -#define AIPS_PACRJ_WP4_SHIFT 13 -#define AIPS_PACRJ_SP4_MASK 0x4000u -#define AIPS_PACRJ_SP4_SHIFT 14 -#define AIPS_PACRJ_TP3_MASK 0x10000u -#define AIPS_PACRJ_TP3_SHIFT 16 -#define AIPS_PACRJ_WP3_MASK 0x20000u -#define AIPS_PACRJ_WP3_SHIFT 17 -#define AIPS_PACRJ_SP3_MASK 0x40000u -#define AIPS_PACRJ_SP3_SHIFT 18 -#define AIPS_PACRJ_TP2_MASK 0x100000u -#define AIPS_PACRJ_TP2_SHIFT 20 -#define AIPS_PACRJ_WP2_MASK 0x200000u -#define AIPS_PACRJ_WP2_SHIFT 21 -#define AIPS_PACRJ_SP2_MASK 0x400000u -#define AIPS_PACRJ_SP2_SHIFT 22 -#define AIPS_PACRJ_TP1_MASK 0x1000000u -#define AIPS_PACRJ_TP1_SHIFT 24 -#define AIPS_PACRJ_WP1_MASK 0x2000000u -#define AIPS_PACRJ_WP1_SHIFT 25 -#define AIPS_PACRJ_SP1_MASK 0x4000000u -#define AIPS_PACRJ_SP1_SHIFT 26 -#define AIPS_PACRJ_TP0_MASK 0x10000000u -#define AIPS_PACRJ_TP0_SHIFT 28 -#define AIPS_PACRJ_WP0_MASK 0x20000000u -#define AIPS_PACRJ_WP0_SHIFT 29 -#define AIPS_PACRJ_SP0_MASK 0x40000000u -#define AIPS_PACRJ_SP0_SHIFT 30 -/* PACRK Bit Fields */ -#define AIPS_PACRK_TP7_MASK 0x1u -#define AIPS_PACRK_TP7_SHIFT 0 -#define AIPS_PACRK_WP7_MASK 0x2u -#define AIPS_PACRK_WP7_SHIFT 1 -#define AIPS_PACRK_SP7_MASK 0x4u -#define AIPS_PACRK_SP7_SHIFT 2 -#define AIPS_PACRK_TP6_MASK 0x10u -#define AIPS_PACRK_TP6_SHIFT 4 -#define AIPS_PACRK_WP6_MASK 0x20u -#define AIPS_PACRK_WP6_SHIFT 5 -#define AIPS_PACRK_SP6_MASK 0x40u -#define AIPS_PACRK_SP6_SHIFT 6 -#define AIPS_PACRK_TP5_MASK 0x100u -#define AIPS_PACRK_TP5_SHIFT 8 -#define AIPS_PACRK_WP5_MASK 0x200u -#define AIPS_PACRK_WP5_SHIFT 9 -#define AIPS_PACRK_SP5_MASK 0x400u -#define AIPS_PACRK_SP5_SHIFT 10 -#define AIPS_PACRK_TP4_MASK 0x1000u -#define AIPS_PACRK_TP4_SHIFT 12 -#define AIPS_PACRK_WP4_MASK 0x2000u -#define AIPS_PACRK_WP4_SHIFT 13 -#define AIPS_PACRK_SP4_MASK 0x4000u -#define AIPS_PACRK_SP4_SHIFT 14 -#define AIPS_PACRK_TP3_MASK 0x10000u -#define AIPS_PACRK_TP3_SHIFT 16 -#define AIPS_PACRK_WP3_MASK 0x20000u -#define AIPS_PACRK_WP3_SHIFT 17 -#define AIPS_PACRK_SP3_MASK 0x40000u -#define AIPS_PACRK_SP3_SHIFT 18 -#define AIPS_PACRK_TP2_MASK 0x100000u -#define AIPS_PACRK_TP2_SHIFT 20 -#define AIPS_PACRK_WP2_MASK 0x200000u -#define AIPS_PACRK_WP2_SHIFT 21 -#define AIPS_PACRK_SP2_MASK 0x400000u -#define AIPS_PACRK_SP2_SHIFT 22 -#define AIPS_PACRK_TP1_MASK 0x1000000u -#define AIPS_PACRK_TP1_SHIFT 24 -#define AIPS_PACRK_WP1_MASK 0x2000000u -#define AIPS_PACRK_WP1_SHIFT 25 -#define AIPS_PACRK_SP1_MASK 0x4000000u -#define AIPS_PACRK_SP1_SHIFT 26 -#define AIPS_PACRK_TP0_MASK 0x10000000u -#define AIPS_PACRK_TP0_SHIFT 28 -#define AIPS_PACRK_WP0_MASK 0x20000000u -#define AIPS_PACRK_WP0_SHIFT 29 -#define AIPS_PACRK_SP0_MASK 0x40000000u -#define AIPS_PACRK_SP0_SHIFT 30 -/* PACRL Bit Fields */ -#define AIPS_PACRL_TP7_MASK 0x1u -#define AIPS_PACRL_TP7_SHIFT 0 -#define AIPS_PACRL_WP7_MASK 0x2u -#define AIPS_PACRL_WP7_SHIFT 1 -#define AIPS_PACRL_SP7_MASK 0x4u -#define AIPS_PACRL_SP7_SHIFT 2 -#define AIPS_PACRL_TP6_MASK 0x10u -#define AIPS_PACRL_TP6_SHIFT 4 -#define AIPS_PACRL_WP6_MASK 0x20u -#define AIPS_PACRL_WP6_SHIFT 5 -#define AIPS_PACRL_SP6_MASK 0x40u -#define AIPS_PACRL_SP6_SHIFT 6 -#define AIPS_PACRL_TP5_MASK 0x100u -#define AIPS_PACRL_TP5_SHIFT 8 -#define AIPS_PACRL_WP5_MASK 0x200u -#define AIPS_PACRL_WP5_SHIFT 9 -#define AIPS_PACRL_SP5_MASK 0x400u -#define AIPS_PACRL_SP5_SHIFT 10 -#define AIPS_PACRL_TP4_MASK 0x1000u -#define AIPS_PACRL_TP4_SHIFT 12 -#define AIPS_PACRL_WP4_MASK 0x2000u -#define AIPS_PACRL_WP4_SHIFT 13 -#define AIPS_PACRL_SP4_MASK 0x4000u -#define AIPS_PACRL_SP4_SHIFT 14 -#define AIPS_PACRL_TP3_MASK 0x10000u -#define AIPS_PACRL_TP3_SHIFT 16 -#define AIPS_PACRL_WP3_MASK 0x20000u -#define AIPS_PACRL_WP3_SHIFT 17 -#define AIPS_PACRL_SP3_MASK 0x40000u -#define AIPS_PACRL_SP3_SHIFT 18 -#define AIPS_PACRL_TP2_MASK 0x100000u -#define AIPS_PACRL_TP2_SHIFT 20 -#define AIPS_PACRL_WP2_MASK 0x200000u -#define AIPS_PACRL_WP2_SHIFT 21 -#define AIPS_PACRL_SP2_MASK 0x400000u -#define AIPS_PACRL_SP2_SHIFT 22 -#define AIPS_PACRL_TP1_MASK 0x1000000u -#define AIPS_PACRL_TP1_SHIFT 24 -#define AIPS_PACRL_WP1_MASK 0x2000000u -#define AIPS_PACRL_WP1_SHIFT 25 -#define AIPS_PACRL_SP1_MASK 0x4000000u -#define AIPS_PACRL_SP1_SHIFT 26 -#define AIPS_PACRL_TP0_MASK 0x10000000u -#define AIPS_PACRL_TP0_SHIFT 28 -#define AIPS_PACRL_WP0_MASK 0x20000000u -#define AIPS_PACRL_WP0_SHIFT 29 -#define AIPS_PACRL_SP0_MASK 0x40000000u -#define AIPS_PACRL_SP0_SHIFT 30 -/* PACRM Bit Fields */ -#define AIPS_PACRM_TP7_MASK 0x1u -#define AIPS_PACRM_TP7_SHIFT 0 -#define AIPS_PACRM_WP7_MASK 0x2u -#define AIPS_PACRM_WP7_SHIFT 1 -#define AIPS_PACRM_SP7_MASK 0x4u -#define AIPS_PACRM_SP7_SHIFT 2 -#define AIPS_PACRM_TP6_MASK 0x10u -#define AIPS_PACRM_TP6_SHIFT 4 -#define AIPS_PACRM_WP6_MASK 0x20u -#define AIPS_PACRM_WP6_SHIFT 5 -#define AIPS_PACRM_SP6_MASK 0x40u -#define AIPS_PACRM_SP6_SHIFT 6 -#define AIPS_PACRM_TP5_MASK 0x100u -#define AIPS_PACRM_TP5_SHIFT 8 -#define AIPS_PACRM_WP5_MASK 0x200u -#define AIPS_PACRM_WP5_SHIFT 9 -#define AIPS_PACRM_SP5_MASK 0x400u -#define AIPS_PACRM_SP5_SHIFT 10 -#define AIPS_PACRM_TP4_MASK 0x1000u -#define AIPS_PACRM_TP4_SHIFT 12 -#define AIPS_PACRM_WP4_MASK 0x2000u -#define AIPS_PACRM_WP4_SHIFT 13 -#define AIPS_PACRM_SP4_MASK 0x4000u -#define AIPS_PACRM_SP4_SHIFT 14 -#define AIPS_PACRM_TP3_MASK 0x10000u -#define AIPS_PACRM_TP3_SHIFT 16 -#define AIPS_PACRM_WP3_MASK 0x20000u -#define AIPS_PACRM_WP3_SHIFT 17 -#define AIPS_PACRM_SP3_MASK 0x40000u -#define AIPS_PACRM_SP3_SHIFT 18 -#define AIPS_PACRM_TP2_MASK 0x100000u -#define AIPS_PACRM_TP2_SHIFT 20 -#define AIPS_PACRM_WP2_MASK 0x200000u -#define AIPS_PACRM_WP2_SHIFT 21 -#define AIPS_PACRM_SP2_MASK 0x400000u -#define AIPS_PACRM_SP2_SHIFT 22 -#define AIPS_PACRM_TP1_MASK 0x1000000u -#define AIPS_PACRM_TP1_SHIFT 24 -#define AIPS_PACRM_WP1_MASK 0x2000000u -#define AIPS_PACRM_WP1_SHIFT 25 -#define AIPS_PACRM_SP1_MASK 0x4000000u -#define AIPS_PACRM_SP1_SHIFT 26 -#define AIPS_PACRM_TP0_MASK 0x10000000u -#define AIPS_PACRM_TP0_SHIFT 28 -#define AIPS_PACRM_WP0_MASK 0x20000000u -#define AIPS_PACRM_WP0_SHIFT 29 -#define AIPS_PACRM_SP0_MASK 0x40000000u -#define AIPS_PACRM_SP0_SHIFT 30 -/* PACRN Bit Fields */ -#define AIPS_PACRN_TP7_MASK 0x1u -#define AIPS_PACRN_TP7_SHIFT 0 -#define AIPS_PACRN_WP7_MASK 0x2u -#define AIPS_PACRN_WP7_SHIFT 1 -#define AIPS_PACRN_SP7_MASK 0x4u -#define AIPS_PACRN_SP7_SHIFT 2 -#define AIPS_PACRN_TP6_MASK 0x10u -#define AIPS_PACRN_TP6_SHIFT 4 -#define AIPS_PACRN_WP6_MASK 0x20u -#define AIPS_PACRN_WP6_SHIFT 5 -#define AIPS_PACRN_SP6_MASK 0x40u -#define AIPS_PACRN_SP6_SHIFT 6 -#define AIPS_PACRN_TP5_MASK 0x100u -#define AIPS_PACRN_TP5_SHIFT 8 -#define AIPS_PACRN_WP5_MASK 0x200u -#define AIPS_PACRN_WP5_SHIFT 9 -#define AIPS_PACRN_SP5_MASK 0x400u -#define AIPS_PACRN_SP5_SHIFT 10 -#define AIPS_PACRN_TP4_MASK 0x1000u -#define AIPS_PACRN_TP4_SHIFT 12 -#define AIPS_PACRN_WP4_MASK 0x2000u -#define AIPS_PACRN_WP4_SHIFT 13 -#define AIPS_PACRN_SP4_MASK 0x4000u -#define AIPS_PACRN_SP4_SHIFT 14 -#define AIPS_PACRN_TP3_MASK 0x10000u -#define AIPS_PACRN_TP3_SHIFT 16 -#define AIPS_PACRN_WP3_MASK 0x20000u -#define AIPS_PACRN_WP3_SHIFT 17 -#define AIPS_PACRN_SP3_MASK 0x40000u -#define AIPS_PACRN_SP3_SHIFT 18 -#define AIPS_PACRN_TP2_MASK 0x100000u -#define AIPS_PACRN_TP2_SHIFT 20 -#define AIPS_PACRN_WP2_MASK 0x200000u -#define AIPS_PACRN_WP2_SHIFT 21 -#define AIPS_PACRN_SP2_MASK 0x400000u -#define AIPS_PACRN_SP2_SHIFT 22 -#define AIPS_PACRN_TP1_MASK 0x1000000u -#define AIPS_PACRN_TP1_SHIFT 24 -#define AIPS_PACRN_WP1_MASK 0x2000000u -#define AIPS_PACRN_WP1_SHIFT 25 -#define AIPS_PACRN_SP1_MASK 0x4000000u -#define AIPS_PACRN_SP1_SHIFT 26 -#define AIPS_PACRN_TP0_MASK 0x10000000u -#define AIPS_PACRN_TP0_SHIFT 28 -#define AIPS_PACRN_WP0_MASK 0x20000000u -#define AIPS_PACRN_WP0_SHIFT 29 -#define AIPS_PACRN_SP0_MASK 0x40000000u -#define AIPS_PACRN_SP0_SHIFT 30 -/* PACRO Bit Fields */ -#define AIPS_PACRO_TP7_MASK 0x1u -#define AIPS_PACRO_TP7_SHIFT 0 -#define AIPS_PACRO_WP7_MASK 0x2u -#define AIPS_PACRO_WP7_SHIFT 1 -#define AIPS_PACRO_SP7_MASK 0x4u -#define AIPS_PACRO_SP7_SHIFT 2 -#define AIPS_PACRO_TP6_MASK 0x10u -#define AIPS_PACRO_TP6_SHIFT 4 -#define AIPS_PACRO_WP6_MASK 0x20u -#define AIPS_PACRO_WP6_SHIFT 5 -#define AIPS_PACRO_SP6_MASK 0x40u -#define AIPS_PACRO_SP6_SHIFT 6 -#define AIPS_PACRO_TP5_MASK 0x100u -#define AIPS_PACRO_TP5_SHIFT 8 -#define AIPS_PACRO_WP5_MASK 0x200u -#define AIPS_PACRO_WP5_SHIFT 9 -#define AIPS_PACRO_SP5_MASK 0x400u -#define AIPS_PACRO_SP5_SHIFT 10 -#define AIPS_PACRO_TP4_MASK 0x1000u -#define AIPS_PACRO_TP4_SHIFT 12 -#define AIPS_PACRO_WP4_MASK 0x2000u -#define AIPS_PACRO_WP4_SHIFT 13 -#define AIPS_PACRO_SP4_MASK 0x4000u -#define AIPS_PACRO_SP4_SHIFT 14 -#define AIPS_PACRO_TP3_MASK 0x10000u -#define AIPS_PACRO_TP3_SHIFT 16 -#define AIPS_PACRO_WP3_MASK 0x20000u -#define AIPS_PACRO_WP3_SHIFT 17 -#define AIPS_PACRO_SP3_MASK 0x40000u -#define AIPS_PACRO_SP3_SHIFT 18 -#define AIPS_PACRO_TP2_MASK 0x100000u -#define AIPS_PACRO_TP2_SHIFT 20 -#define AIPS_PACRO_WP2_MASK 0x200000u -#define AIPS_PACRO_WP2_SHIFT 21 -#define AIPS_PACRO_SP2_MASK 0x400000u -#define AIPS_PACRO_SP2_SHIFT 22 -#define AIPS_PACRO_TP1_MASK 0x1000000u -#define AIPS_PACRO_TP1_SHIFT 24 -#define AIPS_PACRO_WP1_MASK 0x2000000u -#define AIPS_PACRO_WP1_SHIFT 25 -#define AIPS_PACRO_SP1_MASK 0x4000000u -#define AIPS_PACRO_SP1_SHIFT 26 -#define AIPS_PACRO_TP0_MASK 0x10000000u -#define AIPS_PACRO_TP0_SHIFT 28 -#define AIPS_PACRO_WP0_MASK 0x20000000u -#define AIPS_PACRO_WP0_SHIFT 29 -#define AIPS_PACRO_SP0_MASK 0x40000000u -#define AIPS_PACRO_SP0_SHIFT 30 -/* PACRP Bit Fields */ -#define AIPS_PACRP_TP7_MASK 0x1u -#define AIPS_PACRP_TP7_SHIFT 0 -#define AIPS_PACRP_WP7_MASK 0x2u -#define AIPS_PACRP_WP7_SHIFT 1 -#define AIPS_PACRP_SP7_MASK 0x4u -#define AIPS_PACRP_SP7_SHIFT 2 -#define AIPS_PACRP_TP6_MASK 0x10u -#define AIPS_PACRP_TP6_SHIFT 4 -#define AIPS_PACRP_WP6_MASK 0x20u -#define AIPS_PACRP_WP6_SHIFT 5 -#define AIPS_PACRP_SP6_MASK 0x40u -#define AIPS_PACRP_SP6_SHIFT 6 -#define AIPS_PACRP_TP5_MASK 0x100u -#define AIPS_PACRP_TP5_SHIFT 8 -#define AIPS_PACRP_WP5_MASK 0x200u -#define AIPS_PACRP_WP5_SHIFT 9 -#define AIPS_PACRP_SP5_MASK 0x400u -#define AIPS_PACRP_SP5_SHIFT 10 -#define AIPS_PACRP_TP4_MASK 0x1000u -#define AIPS_PACRP_TP4_SHIFT 12 -#define AIPS_PACRP_WP4_MASK 0x2000u -#define AIPS_PACRP_WP4_SHIFT 13 -#define AIPS_PACRP_SP4_MASK 0x4000u -#define AIPS_PACRP_SP4_SHIFT 14 -#define AIPS_PACRP_TP3_MASK 0x10000u -#define AIPS_PACRP_TP3_SHIFT 16 -#define AIPS_PACRP_WP3_MASK 0x20000u -#define AIPS_PACRP_WP3_SHIFT 17 -#define AIPS_PACRP_SP3_MASK 0x40000u -#define AIPS_PACRP_SP3_SHIFT 18 -#define AIPS_PACRP_TP2_MASK 0x100000u -#define AIPS_PACRP_TP2_SHIFT 20 -#define AIPS_PACRP_WP2_MASK 0x200000u -#define AIPS_PACRP_WP2_SHIFT 21 -#define AIPS_PACRP_SP2_MASK 0x400000u -#define AIPS_PACRP_SP2_SHIFT 22 -#define AIPS_PACRP_TP1_MASK 0x1000000u -#define AIPS_PACRP_TP1_SHIFT 24 -#define AIPS_PACRP_WP1_MASK 0x2000000u -#define AIPS_PACRP_WP1_SHIFT 25 -#define AIPS_PACRP_SP1_MASK 0x4000000u -#define AIPS_PACRP_SP1_SHIFT 26 -#define AIPS_PACRP_TP0_MASK 0x10000000u -#define AIPS_PACRP_TP0_SHIFT 28 -#define AIPS_PACRP_WP0_MASK 0x20000000u -#define AIPS_PACRP_WP0_SHIFT 29 -#define AIPS_PACRP_SP0_MASK 0x40000000u -#define AIPS_PACRP_SP0_SHIFT 30 -/* PACRU Bit Fields */ -#define AIPS_PACRU_TP1_MASK 0x1000000u -#define AIPS_PACRU_TP1_SHIFT 24 -#define AIPS_PACRU_WP1_MASK 0x2000000u -#define AIPS_PACRU_WP1_SHIFT 25 -#define AIPS_PACRU_SP1_MASK 0x4000000u -#define AIPS_PACRU_SP1_SHIFT 26 -#define AIPS_PACRU_TP0_MASK 0x10000000u -#define AIPS_PACRU_TP0_SHIFT 28 -#define AIPS_PACRU_WP0_MASK 0x20000000u -#define AIPS_PACRU_WP0_SHIFT 29 -#define AIPS_PACRU_SP0_MASK 0x40000000u -#define AIPS_PACRU_SP0_SHIFT 30 - -/*! - * @} - */ /* end of group AIPS_Register_Masks */ - - -/* AIPS - Peripheral instance base addresses */ -/** Peripheral AIPS0 base address */ -#define AIPS0_BASE (0x40000000u) -/** Peripheral AIPS0 base pointer */ -#define AIPS0 ((AIPS_Type *)AIPS0_BASE) -#define AIPS0_BASE_PTR (AIPS0) -/** Peripheral AIPS1 base address */ -#define AIPS1_BASE (0x40080000u) -/** Peripheral AIPS1 base pointer */ -#define AIPS1 ((AIPS_Type *)AIPS1_BASE) -#define AIPS1_BASE_PTR (AIPS1) -/** Array initializer of AIPS peripheral base addresses */ -#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } -/** Array initializer of AIPS peripheral base pointers */ -#define AIPS_BASE_PTRS { AIPS0, AIPS1 } - -/* ---------------------------------------------------------------------------- - -- AIPS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros - * @{ - */ - - -/* AIPS - Register instance definitions */ -/* AIPS0 */ -#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) -#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) -#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) -#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) -#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) -#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) -#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) -#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) -#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) -#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) -#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) -#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) -#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) -#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) -#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) -#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) -#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) -#define AIPS0_PACRU AIPS_PACRU_REG(AIPS0) -/* AIPS1 */ -#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) -#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) -#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) -#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) -#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) -#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) -#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) -#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) -#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) -#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) -#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) -#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) -#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) -#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) -#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) -#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) -#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) -#define AIPS1_PACRU AIPS_PACRU_REG(AIPS1) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group AIPS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AXBS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer - * @{ - */ - -/** AXBS - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ - uint8_t RESERVED_0[12]; - __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_1[236]; - } SLAVE[5]; - uint8_t RESERVED_0[768]; - __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ - uint8_t RESERVED_1[252]; - __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ - uint8_t RESERVED_2[252]; - __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ - uint8_t RESERVED_3[252]; - __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ - uint8_t RESERVED_4[252]; - __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ - uint8_t RESERVED_5[252]; - __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ -} AXBS_Type, *AXBS_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- AXBS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros - * @{ - */ - - -/* AXBS - Register accessors */ -#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) -#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) -#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) -#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) -#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) -#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) -#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) -#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) - -/*! - * @} - */ /* end of group AXBS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- AXBS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Masks AXBS Register Masks - * @{ - */ - -/* PRS Bit Fields */ -#define AXBS_PRS_M0_MASK 0x7u -#define AXBS_PRS_M0_SHIFT 0 -#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define CAN_CTRL1_REG(base) ((base)->CTRL1) -#define CAN_TIMER_REG(base) ((base)->TIMER) -#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) -#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) -#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) -#define CAN_ECR_REG(base) ((base)->ECR) -#define CAN_ESR1_REG(base) ((base)->ESR1) -#define CAN_IMASK1_REG(base) ((base)->IMASK1) -#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) -#define CAN_CTRL2_REG(base) ((base)->CTRL2) -#define CAN_ESR2_REG(base) ((base)->ESR2) -#define CAN_CRCR_REG(base) ((base)->CRCR) -#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) -#define CAN_RXFIR_REG(base) ((base)->RXFIR) -#define CAN_CS_REG(base,index) ((base)->MB[index].CS) -#define CAN_ID_REG(base,index) ((base)->MB[index].ID) -#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) -#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) -#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) - -/*! - * @} - */ /* end of group CAN_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define CAN_MCR_MAXMB_MASK 0x7Fu -#define CAN_MCR_MAXMB_SHIFT 0 -#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index]) -#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) -#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) -#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) -#define CAU_STR_CASR_REG(base) ((base)->STR_CASR) -#define CAU_STR_CAA_REG(base) ((base)->STR_CAA) -#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) -#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) -#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) -#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) -#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) -#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) -#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) -#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) -#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) -#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) -#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) -#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) -#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) -#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) -#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) -#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) -#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) -#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) -#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) - -/*! - * @} - */ /* end of group CAU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CAU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU_Register_Masks CAU Register Masks - * @{ - */ - -/* DIRECT Bit Fields */ -#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu -#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 -#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) -#define CMT_CGL1_REG(base) ((base)->CGL1) -#define CMT_CGH2_REG(base) ((base)->CGH2) -#define CMT_CGL2_REG(base) ((base)->CGL2) -#define CMT_OC_REG(base) ((base)->OC) -#define CMT_MSC_REG(base) ((base)->MSC) -#define CMT_CMD1_REG(base) ((base)->CMD1) -#define CMT_CMD2_REG(base) ((base)->CMD2) -#define CMT_CMD3_REG(base) ((base)->CMD3) -#define CMT_CMD4_REG(base) ((base)->CMD4) -#define CMT_PPS_REG(base) ((base)->PPS) -#define CMT_DMA_REG(base) ((base)->DMA) - -/*! - * @} - */ /* end of group CMT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMT_Register_Masks CMT Register Masks - * @{ - */ - -/* CGH1 Bit Fields */ -#define CMT_CGH1_PH_MASK 0xFFu -#define CMT_CGH1_PH_SHIFT 0 -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<EIR) -#define ENET_EIMR_REG(base) ((base)->EIMR) -#define ENET_RDAR_REG(base) ((base)->RDAR) -#define ENET_TDAR_REG(base) ((base)->TDAR) -#define ENET_ECR_REG(base) ((base)->ECR) -#define ENET_MMFR_REG(base) ((base)->MMFR) -#define ENET_MSCR_REG(base) ((base)->MSCR) -#define ENET_MIBC_REG(base) ((base)->MIBC) -#define ENET_RCR_REG(base) ((base)->RCR) -#define ENET_TCR_REG(base) ((base)->TCR) -#define ENET_PALR_REG(base) ((base)->PALR) -#define ENET_PAUR_REG(base) ((base)->PAUR) -#define ENET_OPD_REG(base) ((base)->OPD) -#define ENET_IAUR_REG(base) ((base)->IAUR) -#define ENET_IALR_REG(base) ((base)->IALR) -#define ENET_GAUR_REG(base) ((base)->GAUR) -#define ENET_GALR_REG(base) ((base)->GALR) -#define ENET_TFWR_REG(base) ((base)->TFWR) -#define ENET_RDSR_REG(base) ((base)->RDSR) -#define ENET_TDSR_REG(base) ((base)->TDSR) -#define ENET_MRBR_REG(base) ((base)->MRBR) -#define ENET_RSFL_REG(base) ((base)->RSFL) -#define ENET_RSEM_REG(base) ((base)->RSEM) -#define ENET_RAEM_REG(base) ((base)->RAEM) -#define ENET_RAFL_REG(base) ((base)->RAFL) -#define ENET_TSEM_REG(base) ((base)->TSEM) -#define ENET_TAEM_REG(base) ((base)->TAEM) -#define ENET_TAFL_REG(base) ((base)->TAFL) -#define ENET_TIPG_REG(base) ((base)->TIPG) -#define ENET_FTRL_REG(base) ((base)->FTRL) -#define ENET_TACC_REG(base) ((base)->TACC) -#define ENET_RACC_REG(base) ((base)->RACC) -#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) -#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) -#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) -#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) -#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) -#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) -#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) -#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) -#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) -#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) -#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) -#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) -#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) -#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) -#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) -#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) -#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) -#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) -#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) -#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) -#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) -#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) -#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) -#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) -#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) -#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) -#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) -#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) -#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) -#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) -#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) -#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) -#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) -#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) -#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) -#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) -#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) -#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) -#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) -#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) -#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) -#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) -#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) -#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) -#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) -#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) -#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) -#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) -#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) -#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) -#define ENET_ATCR_REG(base) ((base)->ATCR) -#define ENET_ATVR_REG(base) ((base)->ATVR) -#define ENET_ATOFF_REG(base) ((base)->ATOFF) -#define ENET_ATPER_REG(base) ((base)->ATPER) -#define ENET_ATCOR_REG(base) ((base)->ATCOR) -#define ENET_ATINC_REG(base) ((base)->ATINC) -#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) -#define ENET_TGSR_REG(base) ((base)->TGSR) -#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) -#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) - -/*! - * @} - */ /* end of group ENET_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ENET Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Register_Masks ENET Register Masks - * @{ - */ - -/* EIR Bit Fields */ -#define ENET_EIR_TS_TIMER_MASK 0x8000u -#define ENET_EIR_TS_TIMER_SHIFT 15 -#define ENET_EIR_TS_AVAIL_MASK 0x10000u -#define ENET_EIR_TS_AVAIL_SHIFT 16 -#define ENET_EIR_WAKEUP_MASK 0x20000u -#define ENET_EIR_WAKEUP_SHIFT 17 -#define ENET_EIR_PLR_MASK 0x40000u -#define ENET_EIR_PLR_SHIFT 18 -#define ENET_EIR_UN_MASK 0x80000u -#define ENET_EIR_UN_SHIFT 19 -#define ENET_EIR_RL_MASK 0x100000u -#define ENET_EIR_RL_SHIFT 20 -#define ENET_EIR_LC_MASK 0x200000u -#define ENET_EIR_LC_SHIFT 21 -#define ENET_EIR_EBERR_MASK 0x400000u -#define ENET_EIR_EBERR_SHIFT 22 -#define ENET_EIR_MII_MASK 0x800000u -#define ENET_EIR_MII_SHIFT 23 -#define ENET_EIR_RXB_MASK 0x1000000u -#define ENET_EIR_RXB_SHIFT 24 -#define ENET_EIR_RXF_MASK 0x2000000u -#define ENET_EIR_RXF_SHIFT 25 -#define ENET_EIR_TXB_MASK 0x4000000u -#define ENET_EIR_TXB_SHIFT 26 -#define ENET_EIR_TXF_MASK 0x8000000u -#define ENET_EIR_TXF_SHIFT 27 -#define ENET_EIR_GRA_MASK 0x10000000u -#define ENET_EIR_GRA_SHIFT 28 -#define ENET_EIR_BABT_MASK 0x20000000u -#define ENET_EIR_BABT_SHIFT 29 -#define ENET_EIR_BABR_MASK 0x40000000u -#define ENET_EIR_BABR_SHIFT 30 -/* EIMR Bit Fields */ -#define ENET_EIMR_TS_TIMER_MASK 0x8000u -#define ENET_EIMR_TS_TIMER_SHIFT 15 -#define ENET_EIMR_TS_AVAIL_MASK 0x10000u -#define ENET_EIMR_TS_AVAIL_SHIFT 16 -#define ENET_EIMR_WAKEUP_MASK 0x20000u -#define ENET_EIMR_WAKEUP_SHIFT 17 -#define ENET_EIMR_PLR_MASK 0x40000u -#define ENET_EIMR_PLR_SHIFT 18 -#define ENET_EIMR_UN_MASK 0x80000u -#define ENET_EIMR_UN_SHIFT 19 -#define ENET_EIMR_RL_MASK 0x100000u -#define ENET_EIMR_RL_SHIFT 20 -#define ENET_EIMR_LC_MASK 0x200000u -#define ENET_EIMR_LC_SHIFT 21 -#define ENET_EIMR_EBERR_MASK 0x400000u -#define ENET_EIMR_EBERR_SHIFT 22 -#define ENET_EIMR_MII_MASK 0x800000u -#define ENET_EIMR_MII_SHIFT 23 -#define ENET_EIMR_RXB_MASK 0x1000000u -#define ENET_EIMR_RXB_SHIFT 24 -#define ENET_EIMR_RXF_MASK 0x2000000u -#define ENET_EIMR_RXF_SHIFT 25 -#define ENET_EIMR_TXB_MASK 0x4000000u -#define ENET_EIMR_TXB_SHIFT 26 -#define ENET_EIMR_TXF_MASK 0x8000000u -#define ENET_EIMR_TXF_SHIFT 27 -#define ENET_EIMR_GRA_MASK 0x10000000u -#define ENET_EIMR_GRA_SHIFT 28 -#define ENET_EIMR_BABT_MASK 0x20000000u -#define ENET_EIMR_BABT_SHIFT 29 -#define ENET_EIMR_BABR_MASK 0x40000000u -#define ENET_EIMR_BABR_SHIFT 30 -/* RDAR Bit Fields */ -#define ENET_RDAR_RDAR_MASK 0x1000000u -#define ENET_RDAR_RDAR_SHIFT 24 -/* TDAR Bit Fields */ -#define ENET_TDAR_TDAR_MASK 0x1000000u -#define ENET_TDAR_TDAR_SHIFT 24 -/* ECR Bit Fields */ -#define ENET_ECR_RESET_MASK 0x1u -#define ENET_ECR_RESET_SHIFT 0 -#define ENET_ECR_ETHEREN_MASK 0x2u -#define ENET_ECR_ETHEREN_SHIFT 1 -#define ENET_ECR_MAGICEN_MASK 0x4u -#define ENET_ECR_MAGICEN_SHIFT 2 -#define ENET_ECR_SLEEP_MASK 0x8u -#define ENET_ECR_SLEEP_SHIFT 3 -#define ENET_ECR_EN1588_MASK 0x10u -#define ENET_ECR_EN1588_SHIFT 4 -#define ENET_ECR_DBGEN_MASK 0x40u -#define ENET_ECR_DBGEN_SHIFT 6 -#define ENET_ECR_STOPEN_MASK 0x80u -#define ENET_ECR_STOPEN_SHIFT 7 -#define ENET_ECR_DBSWP_MASK 0x100u -#define ENET_ECR_DBSWP_SHIFT 8 -/* MMFR Bit Fields */ -#define ENET_MMFR_DATA_MASK 0xFFFFu -#define ENET_MMFR_DATA_SHIFT 0 -#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Register_Masks FB Register Masks - * @{ - */ - -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFE_FCNFG_REG(base) ((base)->FCNFG) -#define FTFE_FSEC_REG(base) ((base)->FSEC) -#define FTFE_FOPT_REG(base) ((base)->FOPT) -#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFE_FPROT3_REG(base) ((base)->FPROT3) -#define FTFE_FPROT2_REG(base) ((base)->FPROT2) -#define FTFE_FPROT1_REG(base) ((base)->FPROT1) -#define FTFE_FPROT0_REG(base) ((base)->FPROT0) -#define FTFE_FEPROT_REG(base) ((base)->FEPROT) -#define FTFE_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group FTFE_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTFE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFE_Register_Masks FTFE Register Masks - * @{ - */ - -/* FSTAT Bit Fields */ -#define FTFE_FSTAT_MGSTAT0_MASK 0x1u -#define FTFE_FSTAT_MGSTAT0_SHIFT 0 -#define FTFE_FSTAT_FPVIOL_MASK 0x10u -#define FTFE_FSTAT_FPVIOL_SHIFT 4 -#define FTFE_FSTAT_ACCERR_MASK 0x20u -#define FTFE_FSTAT_ACCERR_SHIFT 5 -#define FTFE_FSTAT_RDCOLERR_MASK 0x40u -#define FTFE_FSTAT_RDCOLERR_SHIFT 6 -#define FTFE_FSTAT_CCIF_MASK 0x80u -#define FTFE_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFE_FCNFG_EEERDY_MASK 0x1u -#define FTFE_FCNFG_EEERDY_SHIFT 0 -#define FTFE_FCNFG_RAMRDY_MASK 0x2u -#define FTFE_FCNFG_RAMRDY_SHIFT 1 -#define FTFE_FCNFG_PFLSH_MASK 0x4u -#define FTFE_FCNFG_PFLSH_SHIFT 2 -#define FTFE_FCNFG_SWAP_MASK 0x8u -#define FTFE_FCNFG_SWAP_SHIFT 3 -#define FTFE_FCNFG_ERSSUSP_MASK 0x10u -#define FTFE_FCNFG_ERSSUSP_SHIFT 4 -#define FTFE_FCNFG_ERSAREQ_MASK 0x20u -#define FTFE_FCNFG_ERSAREQ_SHIFT 5 -#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFE_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFE_FCNFG_CCIE_MASK 0x80u -#define FTFE_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFE_FSEC_SEC_MASK 0x3u -#define FTFE_FSEC_SEC_SHIFT 0 -#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTM_Register_Masks FTM Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) -#define LLWU_RST_REG(base) ((base)->RST) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_CR_REG(base) ((base)->CR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_ETBCC_REG(base) ((base)->ETBCC) -#define MCM_ETBRL_REG(base) ((base)->ETBRL) -#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) -#define MCM_PID_REG(base) ((base)->PID) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) -#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) -#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) -#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) -#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) - -/*! - * @} - */ /* end of group MPU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MPU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MPU_Register_Masks MPU Register Masks - * @{ - */ - -/* CESR Bit Fields */ -#define MPU_CESR_VLD_MASK 0x1u -#define MPU_CESR_VLD_SHIFT 0 -#define MPU_CESR_NRGD_MASK 0xF00u -#define MPU_CESR_NRGD_SHIFT 8 -#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) -#define NV_FEPROT_REG(base) ((base)->FEPROT) -#define NV_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 - -/*! - * @} - */ /* end of group OSC_Register_Masks */ - - -/* OSC - Peripheral instance base addresses */ -/** Peripheral OSC base address */ -#define OSC_BASE (0x40065000u) -/** Peripheral OSC base pointer */ -#define OSC ((OSC_Type *)OSC_BASE) -#define OSC_BASE_PTR (OSC) -/** Array initializer of OSC peripheral base addresses */ -#define OSC_BASE_ADDRS { OSC_BASE } -/** Array initializer of OSC peripheral base pointers */ -#define OSC_BASE_PTRS { OSC } - -/* ---------------------------------------------------------------------------- - -- OSC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros - * @{ - */ - - -/* OSC - Register instance definitions */ -/* OSC */ -#define OSC_CR OSC_CR_REG(OSC) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group OSC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PDB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer - * @{ - */ - -/** PDB - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ - __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ - __I uint32_t CNT; /**< Counter register, offset: 0x8 */ - __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ - struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ - __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ - __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ - uint8_t RESERVED_0[24]; - } CH[2]; - uint8_t RESERVED_0[240]; - struct { /* offset: 0x150, array step: 0x8 */ - __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ - __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ - } DAC[2]; - uint8_t RESERVED_1[48]; - __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ - __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ -} PDB_Type, *PDB_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- PDB - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros - * @{ - */ - - -/* PDB - Register accessors */ -#define PDB_SC_REG(base) ((base)->SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PDB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Masks PDB Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFVBAT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_HA_MASK 0x2u -#define RNG_CR_HA_SHIFT 1 -#define RNG_CR_INTM_MASK 0x4u -#define RNG_CR_INTM_SHIFT 2 -#define RNG_CR_CLRI_MASK 0x8u -#define RNG_CR_CLRI_SHIFT 3 -#define RNG_CR_SLP_MASK 0x10u -#define RNG_CR_SLP_SHIFT 4 -/* SR Bit Fields */ -#define RNG_SR_SECV_MASK 0x1u -#define RNG_SR_SECV_SHIFT 0 -#define RNG_SR_LRS_MASK 0x2u -#define RNG_SR_LRS_SHIFT 1 -#define RNG_SR_ORU_MASK 0x4u -#define RNG_SR_ORU_SHIFT 2 -#define RNG_SR_ERRI_MASK 0x8u -#define RNG_SR_ERRI_SHIFT 3 -#define RNG_SR_SLP_MASK 0x10u -#define RNG_SR_SLP_SHIFT 4 -#define RNG_SR_OREG_LVL_MASK 0xFF00u -#define RNG_SR_OREG_LVL_SHIFT 8 -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) -#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) -#define SDHC_CMDARG_REG(base) ((base)->CMDARG) -#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) -#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) -#define SDHC_DATPORT_REG(base) ((base)->DATPORT) -#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) -#define SDHC_PROCTL_REG(base) ((base)->PROCTL) -#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) -#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) -#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) -#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) -#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) -#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) -#define SDHC_WML_REG(base) ((base)->WML) -#define SDHC_FEVT_REG(base) ((base)->FEVT) -#define SDHC_ADMAES_REG(base) ((base)->ADMAES) -#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) -#define SDHC_VENDOR_REG(base) ((base)->VENDOR) -#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) -#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) - -/*! - * @} - */ /* end of group SDHC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDHC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDHC_Register_Masks SDHC Register Masks - * @{ - */ - -/* DSADDR Bit Fields */ -#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu -#define SDHC_DSADDR_DSADDR_SHIFT 2 -#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC1_REG(base) ((base)->SCGC1) -#define SIM_SCGC2_REG(base) ((base)->SCGC2) -#define SIM_SCGC3_REG(base) ((base)->SCGC3) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816T0_REG(base) ((base)->WP7816T0) -#define UART_WP7816T1_REG(base) ((base)->WP7816T1) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) -#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) -#define USBDCD_STATUS_REG(base) ((base)->STATUS) -#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) -#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) -#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11) -#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12) - -/*! - * @} - */ /* end of group USBDCD_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USBDCD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBDCD_Register_Masks USBDCD Register Masks - * @{ - */ - -/* CONTROL Bit Fields */ -#define USBDCD_CONTROL_IACK_MASK 0x1u -#define USBDCD_CONTROL_IACK_SHIFT 0 -#define USBDCD_CONTROL_IF_MASK 0x100u -#define USBDCD_CONTROL_IF_SHIFT 8 -#define USBDCD_CONTROL_IE_MASK 0x10000u -#define USBDCD_CONTROL_IE_SHIFT 16 -#define USBDCD_CONTROL_BC12_MASK 0x20000u -#define USBDCD_CONTROL_BC12_SHIFT 17 -#define USBDCD_CONTROL_START_MASK 0x1000000u -#define USBDCD_CONTROL_START_SHIFT 24 -#define USBDCD_CONTROL_SR_MASK 0x2000000u -#define USBDCD_CONTROL_SR_SHIFT 25 -/* CLOCK Bit Fields */ -#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u -#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 -#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu -#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 -#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<>> ------------------ -; * -; *****************************************************************************/ - - -__initial_sp EQU 0x20030000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete - DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete - DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete - DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete - DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete - DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete - DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete - DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete - DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete - DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete - DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete - DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete - DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete - DCD DMA_Error_IRQHandler ; DMA Error Interrupt - DCD MCM_IRQHandler ; Normal Interrupt - DCD FTFE_IRQHandler ; FTFE Command complete interrupt - DCD Read_Collision_IRQHandler ; Read Collision Interrupt - DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ; Low Leakage Wakeup - DCD Watchdog_IRQHandler ; WDOG Interrupt - DCD RNG_IRQHandler ; RNG Interrupt - DCD I2C0_IRQHandler ; I2C0 interrupt - DCD I2C1_IRQHandler ; I2C1 interrupt - DCD SPI0_IRQHandler ; SPI0 Interrupt - DCD SPI1_IRQHandler ; SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt - DCD UART0_LON_IRQHandler ; UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ; UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ; UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ; UART2 Error interrupt - DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt - DCD UART3_ERR_IRQHandler ; UART3 Error interrupt - DCD ADC0_IRQHandler ; ADC0 interrupt - DCD CMP0_IRQHandler ; CMP0 interrupt - DCD CMP1_IRQHandler ; CMP1 interrupt - DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ; CMT interrupt - DCD RTC_IRQHandler ; RTC interrupt - DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt - DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ; PDB0 Interrupt - DCD USB0_IRQHandler ; USB0 interrupt - DCD USBDCD_IRQHandler ; USBDCD Interrupt - DCD Reserved71_IRQHandler ; Reserved interrupt 71 - DCD DAC0_IRQHandler ; DAC0 interrupt - DCD MCG_IRQHandler ; MCG Interrupt - DCD LPTimer_IRQHandler ; LPTimer interrupt - DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTB_IRQHandler ; Port B interrupt - DCD PORTC_IRQHandler ; Port C interrupt - DCD PORTD_IRQHandler ; Port D interrupt - DCD PORTE_IRQHandler ; Port E interrupt - DCD SWI_IRQHandler ; Software interrupt - DCD SPI2_IRQHandler ; SPI2 Interrupt - DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt - DCD UART4_ERR_IRQHandler ; UART4 Error interrupt - DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt - DCD UART5_ERR_IRQHandler ; UART5 Error interrupt - DCD CMP2_IRQHandler ; CMP2 interrupt - DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt - DCD DAC1_IRQHandler ; DAC1 interrupt - DCD ADC1_IRQHandler ; ADC1 interrupt - DCD I2C2_IRQHandler ; I2C2 interrupt - DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ; CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt - DCD SDHC_IRQHandler ; SDHC interrupt - DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt - DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt - DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt - DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt - DCD DefaultISR ; 102 - DCD DefaultISR ; 103 - DCD DefaultISR ; 104 - DCD DefaultISR ; 105 - DCD DefaultISR ; 106 - DCD DefaultISR ; 107 - DCD DefaultISR ; 108 - DCD DefaultISR ; 109 - DCD DefaultISR ; 110 - DCD DefaultISR ; 111 - DCD DefaultISR ; 112 - DCD DefaultISR ; 113 - DCD DefaultISR ; 114 - DCD DefaultISR ; 115 - DCD DefaultISR ; 116 - DCD DefaultISR ; 117 - DCD DefaultISR ; 118 - DCD DefaultISR ; 119 - DCD DefaultISR ; 120 - DCD DefaultISR ; 121 - DCD DefaultISR ; 122 - DCD DefaultISR ; 123 - DCD DefaultISR ; 124 - DCD DefaultISR ; 125 - DCD DefaultISR ; 126 - DCD DefaultISR ; 127 - DCD DefaultISR ; 128 - DCD DefaultISR ; 129 - DCD DefaultISR ; 130 - DCD DefaultISR ; 131 - DCD DefaultISR ; 132 - DCD DefaultISR ; 133 - DCD DefaultISR ; 134 - DCD DefaultISR ; 135 - DCD DefaultISR ; 136 - DCD DefaultISR ; 137 - DCD DefaultISR ; 138 - DCD DefaultISR ; 139 - DCD DefaultISR ; 140 - DCD DefaultISR ; 141 - DCD DefaultISR ; 142 - DCD DefaultISR ; 143 - DCD DefaultISR ; 144 - DCD DefaultISR ; 145 - DCD DefaultISR ; 146 - DCD DefaultISR ; 147 - DCD DefaultISR ; 148 - DCD DefaultISR ; 149 - DCD DefaultISR ; 150 - DCD DefaultISR ; 151 - DCD DefaultISR ; 152 - DCD DefaultISR ; 153 - DCD DefaultISR ; 154 - DCD DefaultISR ; 155 - DCD DefaultISR ; 156 - DCD DefaultISR ; 157 - DCD DefaultISR ; 158 - DCD DefaultISR ; 159 - DCD DefaultISR ; 160 - DCD DefaultISR ; 161 - DCD DefaultISR ; 162 - DCD DefaultISR ; 163 - DCD DefaultISR ; 164 - DCD DefaultISR ; 165 - DCD DefaultISR ; 166 - DCD DefaultISR ; 167 - DCD DefaultISR ; 168 - DCD DefaultISR ; 169 - DCD DefaultISR ; 170 - DCD DefaultISR ; 171 - DCD DefaultISR ; 172 - DCD DefaultISR ; 173 - DCD DefaultISR ; 174 - DCD DefaultISR ; 175 - DCD DefaultISR ; 176 - DCD DefaultISR ; 177 - DCD DefaultISR ; 178 - DCD DefaultISR ; 179 - DCD DefaultISR ; 180 - DCD DefaultISR ; 181 - DCD DefaultISR ; 182 - DCD DefaultISR ; 183 - DCD DefaultISR ; 184 - DCD DefaultISR ; 185 - DCD DefaultISR ; 186 - DCD DefaultISR ; 187 - DCD DefaultISR ; 188 - DCD DefaultISR ; 189 - DCD DefaultISR ; 190 - DCD DefaultISR ; 191 - DCD DefaultISR ; 192 - DCD DefaultISR ; 193 - DCD DefaultISR ; 194 - DCD DefaultISR ; 195 - DCD DefaultISR ; 196 - DCD DefaultISR ; 197 - DCD DefaultISR ; 198 - DCD DefaultISR ; 199 - DCD DefaultISR ; 200 - DCD DefaultISR ; 201 - DCD DefaultISR ; 202 - DCD DefaultISR ; 203 - DCD DefaultISR ; 204 - DCD DefaultISR ; 205 - DCD DefaultISR ; 206 - DCD DefaultISR ; 207 - DCD DefaultISR ; 208 - DCD DefaultISR ; 209 - DCD DefaultISR ; 210 - DCD DefaultISR ; 211 - DCD DefaultISR ; 212 - DCD DefaultISR ; 213 - DCD DefaultISR ; 214 - DCD DefaultISR ; 215 - DCD DefaultISR ; 216 - DCD DefaultISR ; 217 - DCD DefaultISR ; 218 - DCD DefaultISR ; 219 - DCD DefaultISR ; 220 - DCD DefaultISR ; 221 - DCD DefaultISR ; 222 - DCD DefaultISR ; 223 - DCD DefaultISR ; 224 - DCD DefaultISR ; 225 - DCD DefaultISR ; 226 - DCD DefaultISR ; 227 - DCD DefaultISR ; 228 - DCD DefaultISR ; 229 - DCD DefaultISR ; 230 - DCD DefaultISR ; 231 - DCD DefaultISR ; 232 - DCD DefaultISR ; 233 - DCD DefaultISR ; 234 - DCD DefaultISR ; 235 - DCD DefaultISR ; 236 - DCD DefaultISR ; 237 - DCD DefaultISR ; 238 - DCD DefaultISR ; 239 - DCD DefaultISR ; 240 - DCD DefaultISR ; 241 - DCD DefaultISR ; 242 - DCD DefaultISR ; 243 - DCD DefaultISR ; 244 - DCD DefaultISR ; 245 - DCD DefaultISR ; 246 - DCD DefaultISR ; 247 - DCD DefaultISR ; 248 - DCD DefaultISR ; 249 - DCD DefaultISR ; 250 - DCD DefaultISR ; 251 - DCD DefaultISR ; 252 - DCD DefaultISR ; 253 - DCD DefaultISR ; 254 - DCD DefaultISR ; 255 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict acces to the FTFL module. -; Backdoor Comparison Key -; Backdoor Key 0 <0x0-0xFF:2> -; Backdoor Key 1 <0x0-0xFF:2> -; Backdoor Key 2 <0x0-0xFF:2> -; Backdoor Key 3 <0x0-0xFF:2> -; Backdoor Key 4 <0x0-0xFF:2> -; Backdoor Key 5 <0x0-0xFF:2> -; Backdoor Key 6 <0x0-0xFF:2> -; Backdoor Key 7 <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program flash protection bytes -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Data flash protection byte (FDPROT) -; Each bit protects a 1/8 region of the data flash memory. -; (Program flash only devices: Reserved) -; FDPROT.0 -; FDPROT.1 -; FDPROT.2 -; FDPROT.3 -; FDPROT.4 -; FDPROT.5 -; FDPROT.6 -; FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; -; EEPROM protection byte (FEPROT) -; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; (Program flash only devices: Reserved) -; FEPROT.0 -; FEPROT.1 -; FEPROT.2 -; FEPROT.3 -; FEPROT.4 -; FEPROT.5 -; FEPROT.6 -; FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> normal boot -; EZPORT_DIS -; <0=> EzPort operation is disabled -; <1=> EzPort operation is enabled -FOPT EQU 0xFD -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; This bits define the security state of the MCU. -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; This bits define the security state of the MCU. -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; Mass Erase Enable Bits -; Enables and disables mass erase capability of the FTFL module -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor key Security Enable -; These bits enable and disable backdoor key access to the FTFL module. -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA |.ARM.__at_0x400|, CODE, READONLY - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT - ENDIF - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT DMA4_IRQHandler [WEAK] - EXPORT DMA5_IRQHandler [WEAK] - EXPORT DMA6_IRQHandler [WEAK] - EXPORT DMA7_IRQHandler [WEAK] - EXPORT DMA8_IRQHandler [WEAK] - EXPORT DMA9_IRQHandler [WEAK] - EXPORT DMA10_IRQHandler [WEAK] - EXPORT DMA11_IRQHandler [WEAK] - EXPORT DMA12_IRQHandler [WEAK] - EXPORT DMA13_IRQHandler [WEAK] - EXPORT DMA14_IRQHandler [WEAK] - EXPORT DMA15_IRQHandler [WEAK] - EXPORT DMA_Error_IRQHandler [WEAK] - EXPORT MCM_IRQHandler [WEAK] - EXPORT FTFE_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLW_IRQHandler [WEAK] - EXPORT Watchdog_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT I2S0_Tx_IRQHandler [WEAK] - EXPORT I2S0_Rx_IRQHandler [WEAK] - EXPORT UART0_LON_IRQHandler [WEAK] - EXPORT UART0_RX_TX_IRQHandler [WEAK] - EXPORT UART0_ERR_IRQHandler [WEAK] - EXPORT UART1_RX_TX_IRQHandler [WEAK] - EXPORT UART1_ERR_IRQHandler [WEAK] - EXPORT UART2_RX_TX_IRQHandler [WEAK] - EXPORT UART2_ERR_IRQHandler [WEAK] - EXPORT UART3_RX_TX_IRQHandler [WEAK] - EXPORT UART3_ERR_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTimer_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART4_RX_TX_IRQHandler [WEAK] - EXPORT UART4_ERR_IRQHandler [WEAK] - EXPORT UART5_RX_TX_IRQHandler [WEAK] - EXPORT UART5_ERR_IRQHandler [WEAK] - EXPORT CMP2_IRQHandler [WEAK] - EXPORT FTM3_IRQHandler [WEAK] - EXPORT DAC1_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] - EXPORT CAN0_Bus_Off_IRQHandler [WEAK] - EXPORT CAN0_Error_IRQHandler [WEAK] - EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] - EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] - EXPORT CAN0_Wake_Up_IRQHandler [WEAK] - EXPORT SDHC_IRQHandler [WEAK] - EXPORT ENET_1588_Timer_IRQHandler [WEAK] - EXPORT ENET_Transmit_IRQHandler [WEAK] - EXPORT ENET_Receive_IRQHandler [WEAK] - EXPORT ENET_Error_IRQHandler [WEAK] - -DMA0_IRQHandler ; DMA Channel 0 Transfer Complete -DMA1_IRQHandler ; DMA Channel 1 Transfer Complete -DMA2_IRQHandler ; DMA Channel 2 Transfer Complete -DMA3_IRQHandler ; DMA Channel 3 Transfer Complete -DMA4_IRQHandler ; DMA Channel 4 Transfer Complete -DMA5_IRQHandler ; DMA Channel 5 Transfer Complete -DMA6_IRQHandler ; DMA Channel 6 Transfer Complete -DMA7_IRQHandler ; DMA Channel 7 Transfer Complete -DMA8_IRQHandler ; DMA Channel 8 Transfer Complete -DMA9_IRQHandler ; DMA Channel 9 Transfer Complete -DMA10_IRQHandler ; DMA Channel 10 Transfer Complete -DMA11_IRQHandler ; DMA Channel 11 Transfer Complete -DMA12_IRQHandler ; DMA Channel 12 Transfer Complete -DMA13_IRQHandler ; DMA Channel 13 Transfer Complete -DMA14_IRQHandler ; DMA Channel 14 Transfer Complete -DMA15_IRQHandler ; DMA Channel 15 Transfer Complete -DMA_Error_IRQHandler ; DMA Error Interrupt -MCM_IRQHandler ; Normal Interrupt -FTFE_IRQHandler ; FTFE Command complete interrupt -Read_Collision_IRQHandler ; Read Collision Interrupt -LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning -LLW_IRQHandler ; Low Leakage Wakeup -Watchdog_IRQHandler ; WDOG Interrupt -RNG_IRQHandler ; RNG Interrupt -I2C0_IRQHandler ; I2C0 interrupt -I2C1_IRQHandler ; I2C1 interrupt -SPI0_IRQHandler ; SPI0 Interrupt -SPI1_IRQHandler ; SPI1 Interrupt -I2S0_Tx_IRQHandler ; I2S0 transmit interrupt -I2S0_Rx_IRQHandler ; I2S0 receive interrupt -UART0_LON_IRQHandler ; UART0 LON interrupt -UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt -UART0_ERR_IRQHandler ; UART0 Error interrupt -UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt -UART1_ERR_IRQHandler ; UART1 Error interrupt -UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt -UART2_ERR_IRQHandler ; UART2 Error interrupt -UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt -UART3_ERR_IRQHandler ; UART3 Error interrupt -ADC0_IRQHandler ; ADC0 interrupt -CMP0_IRQHandler ; CMP0 interrupt -CMP1_IRQHandler ; CMP1 interrupt -FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt -FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt -FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt -CMT_IRQHandler ; CMT interrupt -RTC_IRQHandler ; RTC interrupt -RTC_Seconds_IRQHandler ; RTC seconds interrupt -PIT0_IRQHandler ; PIT timer channel 0 interrupt -PIT1_IRQHandler ; PIT timer channel 1 interrupt -PIT2_IRQHandler ; PIT timer channel 2 interrupt -PIT3_IRQHandler ; PIT timer channel 3 interrupt -PDB0_IRQHandler ; PDB0 Interrupt -USB0_IRQHandler ; USB0 interrupt -USBDCD_IRQHandler ; USBDCD Interrupt -Reserved71_IRQHandler ; Reserved interrupt 71 -DAC0_IRQHandler ; DAC0 interrupt -MCG_IRQHandler ; MCG Interrupt -LPTimer_IRQHandler ; LPTimer interrupt -PORTA_IRQHandler ; Port A interrupt -PORTB_IRQHandler ; Port B interrupt -PORTC_IRQHandler ; Port C interrupt -PORTD_IRQHandler ; Port D interrupt -PORTE_IRQHandler ; Port E interrupt -SWI_IRQHandler ; Software interrupt -SPI2_IRQHandler ; SPI2 Interrupt -UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt -UART4_ERR_IRQHandler ; UART4 Error interrupt -UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt -UART5_ERR_IRQHandler ; UART5 Error interrupt -CMP2_IRQHandler ; CMP2 interrupt -FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt -DAC1_IRQHandler ; DAC1 interrupt -ADC1_IRQHandler ; ADC1 interrupt -I2C2_IRQHandler ; I2C2 interrupt -CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt -CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt -CAN0_Error_IRQHandler ; CAN0 error interrupt -CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt -CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt -CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt -SDHC_IRQHandler ; SDHC interrupt -ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt -ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt -ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt -ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt -DefaultISR - - B . - - ENDP - - - ALIGN - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp deleted file mode 100644 index b129b2c2a5b..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld deleted file mode 100644 index 5bf14b145eb..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld +++ /dev/null @@ -1,164 +0,0 @@ -/* - * K64F ARM GCC linker script file - */ - -MEMORY -{ - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410 - RAM (rwx) : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .isr_vector : - { - __vector_table = .; - KEEP(*(.vector_table)) - *(.text.Reset_Handler) - *(.text.System_Init) - . = ALIGN(4); - } > VECTORS - - .flash_protect : - { - KEEP(*(.kinetis_flash_config_field)) - . = ALIGN(4); - } > FLASH_PROTECTION - - .text : - { - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S deleted file mode 100644 index 632979af3b1..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S +++ /dev/null @@ -1,369 +0,0 @@ -/* K64F startup ARM GCC - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv7-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0xC00 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vector_table,"a",%progbits - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete */ - .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete */ - .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete */ - .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete */ - .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete */ - .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete */ - .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete */ - .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete */ - .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete */ - .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete */ - .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete */ - .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete */ - .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete */ - .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete */ - .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete */ - .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete */ - .long DMA_Error_IRQHandler /* DMA Error Interrupt */ - .long MCM_IRQHandler /* Normal Interrupt */ - .long FTFE_IRQHandler /* FTFE Command complete interrupt */ - .long Read_Collision_IRQHandler /* Read Collision Interrupt */ - .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */ - .long LLW_IRQHandler /* Low Leakage Wakeup */ - .long Watchdog_IRQHandler /* WDOG Interrupt */ - .long RNG_IRQHandler /* RNG Interrupt */ - .long I2C0_IRQHandler /* I2C0 interrupt */ - .long I2C1_IRQHandler /* I2C1 interrupt */ - .long SPI0_IRQHandler /* SPI0 Interrupt */ - .long SPI1_IRQHandler /* SPI1 Interrupt */ - .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */ - .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */ - .long UART0_LON_IRQHandler /* UART0 LON interrupt */ - .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt */ - .long UART0_ERR_IRQHandler /* UART0 Error interrupt */ - .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt */ - .long UART1_ERR_IRQHandler /* UART1 Error interrupt */ - .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt */ - .long UART2_ERR_IRQHandler /* UART2 Error interrupt */ - .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt */ - .long UART3_ERR_IRQHandler /* UART3 Error interrupt */ - .long ADC0_IRQHandler /* ADC0 interrupt */ - .long CMP0_IRQHandler /* CMP0 interrupt */ - .long CMP1_IRQHandler /* CMP1 interrupt */ - .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */ - .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */ - .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt */ - .long CMT_IRQHandler /* CMT interrupt */ - .long RTC_IRQHandler /* RTC interrupt */ - .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */ - .long PIT0_IRQHandler /* PIT timer channel 0 interrupt */ - .long PIT1_IRQHandler /* PIT timer channel 1 interrupt */ - .long PIT2_IRQHandler /* PIT timer channel 2 interrupt */ - .long PIT3_IRQHandler /* PIT timer channel 3 interrupt */ - .long PDB0_IRQHandler /* PDB0 Interrupt */ - .long USB0_IRQHandler /* USB0 interrupt */ - .long USBDCD_IRQHandler /* USBDCD Interrupt */ - .long Reserved71_IRQHandler /* Reserved interrupt 71 */ - .long DAC0_IRQHandler /* DAC0 interrupt */ - .long MCG_IRQHandler /* MCG Interrupt */ - .long LPTimer_IRQHandler /* LPTimer interrupt */ - .long PORTA_IRQHandler /* Port A interrupt */ - .long PORTB_IRQHandler /* Port B interrupt */ - .long PORTC_IRQHandler /* Port C interrupt */ - .long PORTD_IRQHandler /* Port D interrupt */ - .long PORTE_IRQHandler /* Port E interrupt */ - .long SWI_IRQHandler /* Software interrupt */ - .long SPI2_IRQHandler /* SPI2 Interrupt */ - .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt */ - .long UART4_ERR_IRQHandler /* UART4 Error interrupt */ - .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt */ - .long UART5_ERR_IRQHandler /* UART5 Error interrupt */ - .long CMP2_IRQHandler /* CMP2 interrupt */ - .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt */ - .long DAC1_IRQHandler /* DAC1 interrupt */ - .long ADC1_IRQHandler /* ADC1 interrupt */ - .long I2C2_IRQHandler /* I2C2 interrupt */ - .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt */ - .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt */ - .long CAN0_Error_IRQHandler /* CAN0 error interrupt */ - .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt */ - .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt */ - .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt */ - .long SDHC_IRQHandler /* SDHC interrupt */ - .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt */ - .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt */ - .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt */ - .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt */ - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - -disable_watchdog: - /* unlock */ - ldr r1, =0x4005200e - ldr r0, =0xc520 - strh r0, [r1] - ldr r0, =0xd928 - strh r0, [r1] - /* disable */ - ldr r1, =0x40052000 - ldr r0, =0x01d2 - strh r0, [r1] - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - -/* IRQ Handlers */ - def_irq_default_handler DMA0_IRQHandler - def_irq_default_handler DMA1_IRQHandler - def_irq_default_handler DMA2_IRQHandler - def_irq_default_handler DMA3_IRQHandler - def_irq_default_handler DMA4_IRQHandler - def_irq_default_handler DMA5_IRQHandler - def_irq_default_handler DMA6_IRQHandler - def_irq_default_handler DMA7_IRQHandler - def_irq_default_handler DMA8_IRQHandler - def_irq_default_handler DMA9_IRQHandler - def_irq_default_handler DMA10_IRQHandler - def_irq_default_handler DMA11_IRQHandler - def_irq_default_handler DMA12_IRQHandler - def_irq_default_handler DMA13_IRQHandler - def_irq_default_handler DMA14_IRQHandler - def_irq_default_handler DMA15_IRQHandler - def_irq_default_handler DMA_Error_IRQHandler - def_irq_default_handler MCM_IRQHandler - def_irq_default_handler FTFE_IRQHandler - def_irq_default_handler Read_Collision_IRQHandler - def_irq_default_handler LVD_LVW_IRQHandler - def_irq_default_handler LLW_IRQHandler - def_irq_default_handler Watchdog_IRQHandler - def_irq_default_handler RNG_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler I2S0_Tx_IRQHandler - def_irq_default_handler I2S0_Rx_IRQHandler - def_irq_default_handler UART0_LON_IRQHandler - def_irq_default_handler UART0_RX_TX_IRQHandler - def_irq_default_handler UART0_ERR_IRQHandler - def_irq_default_handler UART1_RX_TX_IRQHandler - def_irq_default_handler UART1_ERR_IRQHandler - def_irq_default_handler UART2_RX_TX_IRQHandler - def_irq_default_handler UART2_ERR_IRQHandler - def_irq_default_handler UART3_RX_TX_IRQHandler - def_irq_default_handler UART3_ERR_IRQHandler - def_irq_default_handler ADC0_IRQHandler - def_irq_default_handler CMP0_IRQHandler - def_irq_default_handler CMP1_IRQHandler - def_irq_default_handler FTM0_IRQHandler - def_irq_default_handler FTM1_IRQHandler - def_irq_default_handler FTM2_IRQHandler - def_irq_default_handler CMT_IRQHandler - def_irq_default_handler RTC_IRQHandler - def_irq_default_handler RTC_Seconds_IRQHandler - def_irq_default_handler PIT0_IRQHandler - def_irq_default_handler PIT1_IRQHandler - def_irq_default_handler PIT2_IRQHandler - def_irq_default_handler PIT3_IRQHandler - def_irq_default_handler PDB0_IRQHandler - def_irq_default_handler USB0_IRQHandler - def_irq_default_handler USBDCD_IRQHandler - def_irq_default_handler Reserved71_IRQHandler - def_irq_default_handler DAC0_IRQHandler - def_irq_default_handler MCG_IRQHandler - def_irq_default_handler LPTimer_IRQHandler - def_irq_default_handler PORTA_IRQHandler - def_irq_default_handler PORTB_IRQHandler - def_irq_default_handler PORTC_IRQHandler - def_irq_default_handler PORTD_IRQHandler - def_irq_default_handler PORTE_IRQHandler - def_irq_default_handler SWI_IRQHandler - def_irq_default_handler SPI2_IRQHandler - def_irq_default_handler UART4_RX_TX_IRQHandler - def_irq_default_handler UART4_ERR_IRQHandler - def_irq_default_handler UART5_RX_TX_IRQHandler - def_irq_default_handler UART5_ERR_IRQHandler - def_irq_default_handler CMP2_IRQHandler - def_irq_default_handler FTM3_IRQHandler - def_irq_default_handler DAC1_IRQHandler - def_irq_default_handler ADC1_IRQHandler - def_irq_default_handler I2C2_IRQHandler - def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler - def_irq_default_handler CAN0_Bus_Off_IRQHandler - def_irq_default_handler CAN0_Error_IRQHandler - def_irq_default_handler CAN0_Tx_Warning_IRQHandler - def_irq_default_handler CAN0_Rx_Warning_IRQHandler - def_irq_default_handler CAN0_Wake_Up_IRQHandler - def_irq_default_handler SDHC_IRQHandler - def_irq_default_handler ENET_1588_Timer_IRQHandler - def_irq_default_handler ENET_Transmit_IRQHandler - def_irq_default_handler ENET_Receive_IRQHandler - def_irq_default_handler ENET_Error_IRQHandler - def_irq_default_handler DefaultISR - -/* Flash protection region, placed at 0x400 */ - .text - .thumb - .align 2 - .section .kinetis_flash_config_field,"a",%progbits -kinetis_flash_config: - .long 0xffffffff - .long 0xffffffff - .long 0xffffffff - .long 0xfffffdfe - - .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf deleted file mode 100644 index 6300e56e2e5..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf +++ /dev/null @@ -1,49 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x000fffff; -define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff0197; -define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0198; -define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; -/*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = 0x8000; -define symbol __ICFEDIT_size_heap__ = 0x10000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_RAM2_start__ = 0x20000000; -define symbol __region_RAM2_end__ = 0x2002ffff; - -define symbol __FlashConfig_start__ = 0x00000400; -define symbol __FlashConfig_end__ = 0x0000040f; - -define symbol __region_FlexRAM_start__ = 0x14000000; -define symbol __region_FlexRAM_end__ = 0x14000fff; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__]; -define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__]; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in FlashConfig_region {section FlashConfig}; - -place in ROM_region { readonly }; - -place in RAM_region { readwrite, block HEAP, block CSTACK }; - -place in FlexRAM_region { section .flex_ram }; diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.S deleted file mode 100644 index bd1368211f2..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.S +++ /dev/null @@ -1,394 +0,0 @@ -/************************************************** - * - * Copyright 2010 IAR Systems. All rights reserved. - * - * $Revision: 16 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:ROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - ; External Interrupts - DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete - DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete - DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete - DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete - DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete - DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete - DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete - DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete - DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete - DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete - DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete - DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete - DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete - DCD DMA_Error_IRQHandler ; DMA Error Interrupt - DCD MCM_IRQHandler ; Normal Interrupt - DCD FTFE_IRQHandler ; FTFE Command complete interrupt - DCD Read_Collision_IRQHandler ; Read Collision Interrupt - DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ; Low Leakage Wakeup - DCD Watchdog_IRQHandler ; WDOG Interrupt - DCD RNG_IRQHandler ; RNG Interrupt - DCD I2C0_IRQHandler ; I2C0 interrupt - DCD I2C1_IRQHandler ; I2C1 interrupt - DCD SPI0_IRQHandler ; SPI0 Interrupt - DCD SPI1_IRQHandler ; SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt - DCD UART0_LON_IRQHandler ; UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ; UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ; UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ; UART2 Error interrupt - DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt - DCD UART3_ERR_IRQHandler ; UART3 Error interrupt - DCD ADC0_IRQHandler ; ADC0 interrupt - DCD CMP0_IRQHandler ; CMP0 interrupt - DCD CMP1_IRQHandler ; CMP1 interrupt - DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ; CMT interrupt - DCD RTC_IRQHandler ; RTC interrupt - DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt - DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ; PDB0 Interrupt - DCD USB0_IRQHandler ; USB0 interrupt - DCD USBDCD_IRQHandler ; USBDCD Interrupt - DCD Reserved71_IRQHandler ; Reserved interrupt 71 - DCD DAC0_IRQHandler ; DAC0 interrupt - DCD MCG_IRQHandler ; MCG Interrupt - DCD LPTimer_IRQHandler ; LPTimer interrupt - DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTB_IRQHandler ; Port B interrupt - DCD PORTC_IRQHandler ; Port C interrupt - DCD PORTD_IRQHandler ; Port D interrupt - DCD PORTE_IRQHandler ; Port E interrupt - DCD SWI_IRQHandler ; Software interrupt - DCD SPI2_IRQHandler ; SPI2 Interrupt - DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt - DCD UART4_ERR_IRQHandler ; UART4 Error interrupt - DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt - DCD UART5_ERR_IRQHandler ; UART5 Error interrupt - DCD CMP2_IRQHandler ; CMP2 interrupt - DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt - DCD DAC1_IRQHandler ; DAC1 interrupt - DCD ADC1_IRQHandler ; ADC1 interrupt - DCD I2C2_IRQHandler ; I2C2 interrupt - DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ; CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt - DCD SDHC_IRQHandler ; SDHC interrupt - DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt - DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt - DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt - DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;;Flash Configuration -;;16-byte flash configuration field that stores default protection settings (loaded on reset) -;;and security information that allows the MCU to restrict acces to the FTFL module. - -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF - -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0^0xFF - -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1^0xFF - -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2^0xFF - -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3^0xFF - -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT^0xFF - -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT^0xFF - -FOPT EQU 0xFD - -FSEC EQU 0xFE - SECTION FlashConfig:CONST:REORDER:ROOT(2) -Config: - DATA - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA8_IRQHandler - PUBWEAK DMA9_IRQHandler - PUBWEAK DMA10_IRQHandler - PUBWEAK DMA11_IRQHandler - PUBWEAK DMA12_IRQHandler - PUBWEAK DMA13_IRQHandler - PUBWEAK DMA14_IRQHandler - PUBWEAK DMA15_IRQHandler - PUBWEAK DMA_Error_IRQHandler - PUBWEAK MCM_IRQHandler - PUBWEAK FTFE_IRQHandler - PUBWEAK Read_Collision_IRQHandler - PUBWEAK LVD_LVW_IRQHandler - PUBWEAK LLW_IRQHandler - PUBWEAK Watchdog_IRQHandler - PUBWEAK RNG_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK I2S0_Tx_IRQHandler - PUBWEAK I2S0_Rx_IRQHandler - PUBWEAK UART0_LON_IRQHandler - PUBWEAK UART0_RX_TX_IRQHandler - PUBWEAK UART0_ERR_IRQHandler - PUBWEAK UART1_RX_TX_IRQHandler - PUBWEAK UART1_ERR_IRQHandler - PUBWEAK UART2_RX_TX_IRQHandler - PUBWEAK UART2_ERR_IRQHandler - PUBWEAK UART3_RX_TX_IRQHandler - PUBWEAK UART3_ERR_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK CMP1_IRQHandler - PUBWEAK FTM0_IRQHandler - PUBWEAK FTM1_IRQHandler - PUBWEAK FTM2_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK PIT1_IRQHandler - PUBWEAK PIT2_IRQHandler - PUBWEAK PIT3_IRQHandler - PUBWEAK PDB0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK USBDCD_IRQHandler - PUBWEAK Reserved71_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTimer_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK SWI_IRQHandler - PUBWEAK SPI2_IRQHandler - PUBWEAK UART4_RX_TX_IRQHandler - PUBWEAK UART4_ERR_IRQHandler - PUBWEAK UART5_RX_TX_IRQHandler - PUBWEAK UART5_ERR_IRQHandler - PUBWEAK CMP2_IRQHandler - PUBWEAK FTM3_IRQHandler - PUBWEAK DAC1_IRQHandler - PUBWEAK ADC1_IRQHandler - PUBWEAK I2C2_IRQHandler - PUBWEAK CAN0_ORed_Message_buffer_IRQHandler - PUBWEAK CAN0_Bus_Off_IRQHandler - PUBWEAK CAN0_Error_IRQHandler - PUBWEAK CAN0_Tx_Warning_IRQHandler - PUBWEAK CAN0_Rx_Warning_IRQHandler - PUBWEAK CAN0_Wake_Up_IRQHandler - PUBWEAK SDHC_IRQHandler - PUBWEAK ENET_1588_Timer_IRQHandler - PUBWEAK ENET_Transmit_IRQHandler - PUBWEAK ENET_Receive_IRQHandler - PUBWEAK ENET_Error_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -DMA4_IRQHandler -DMA5_IRQHandler -DMA6_IRQHandler -DMA7_IRQHandler -DMA8_IRQHandler -DMA9_IRQHandler -DMA10_IRQHandler -DMA11_IRQHandler -DMA12_IRQHandler -DMA13_IRQHandler -DMA14_IRQHandler -DMA15_IRQHandler -DMA_Error_IRQHandler -MCM_IRQHandler -FTFE_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLW_IRQHandler -Watchdog_IRQHandler -RNG_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -I2S0_Tx_IRQHandler -I2S0_Rx_IRQHandler -UART0_LON_IRQHandler -UART0_RX_TX_IRQHandler -UART0_ERR_IRQHandler -UART1_RX_TX_IRQHandler -UART1_ERR_IRQHandler -UART2_RX_TX_IRQHandler -UART2_ERR_IRQHandler -UART3_RX_TX_IRQHandler -UART3_ERR_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -DAC0_IRQHandler -MCG_IRQHandler -LPTimer_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -SPI2_IRQHandler -UART4_RX_TX_IRQHandler -UART4_ERR_IRQHandler -UART5_RX_TX_IRQHandler -UART5_ERR_IRQHandler -CMP2_IRQHandler -FTM3_IRQHandler -DAC1_IRQHandler -ADC1_IRQHandler -I2C2_IRQHandler -CAN0_ORed_Message_buffer_IRQHandler -CAN0_Bus_Off_IRQHandler -CAN0_Error_IRQHandler -CAN0_Tx_Warning_IRQHandler -CAN0_Rx_Warning_IRQHandler -CAN0_Wake_Up_IRQHandler -SDHC_IRQHandler -ENET_1588_Timer_IRQHandler -ENET_Transmit_IRQHandler -ENET_Receive_IRQHandler -ENET_Error_IRQHandler -Default_Handler - - B Default_Handler - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h deleted file mode 100644 index 8c87549bd17..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MK64F12.h" -#include "cmsis_nvic.h" - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c deleted file mode 100644 index fc13c884fc0..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c +++ /dev/null @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h deleted file mode 100644 index 206b645437e..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h +++ /dev/null @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c deleted file mode 100644 index 849c58c74fa..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c +++ /dev/null @@ -1,391 +0,0 @@ -/* -** ################################################################### -** Processor: MK64FN1M0VMD12 -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140611 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK64F12 - * @version 2.5 - * @date 2014-02-10 - * @brief Device specific configuration file for MK64F12 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "cmsis.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ -#if (DISABLE_WDOG) - /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ - WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ - /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ - WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ - /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ - WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | - WDOG_STCTRLH_WAITEN_MASK | - WDOG_STCTRLH_STOPEN_MASK | - WDOG_STCTRLH_ALLOWUPDATE_MASK | - WDOG_STCTRLH_CLKSRC_MASK | - 0x0100U; -#endif /* (DISABLE_WDOG) */ - if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U) - { - if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U) - { - PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/ - } - } else { -#ifdef SYSTEM_RTC_CR_VALUE - SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; - if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */ - RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE); - RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK; - RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK; - } -#endif - } - - /* Power mode protection initialization */ -#ifdef SYSTEM_SMC_PMPROT_VALUE - SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE; -#endif - - /* System clock initialization */ - /* Internal reference clock trim initialization */ -#if defined(SLOW_TRIM_ADDRESS) - if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */ - MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); - #endif /* defined(SLOW_TRIM_ADDRESS) */ - #if defined(SLOW_FINE_TRIM_ADDRESS) - MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK); - #endif - #if defined(FAST_TRIM_ADDRESS) - MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK); - #endif - #if defined(FAST_FINE_TRIM_ADDRESS) - MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK); - #endif /* defined(FAST_FINE_TRIM_ADDRESS) */ -#if defined(SLOW_TRIM_ADDRESS) - } - #endif /* defined(SLOW_TRIM_ADDRESS) */ - - /* Set system prescalers and clock sources */ - SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */ - SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */ - SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */ -#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) - /* Set MCG and OSC */ -#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U))) - /* SIM_SCGC5: PORTA=1 */ - SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR18: ISF=0,MUX=0 */ - PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) { - /* PORTA_PCR19: ISF=0,MUX=0 */ - PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } -#endif - MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ - MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ - /* Check that the source of the FLL reference clock is the requested one. */ - if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { - } - } else { - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { - } - } - MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ - MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ - OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ - MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ - #if (MCG_MODE == MCG_MODE_BLPI) - /* BLPI specific */ - MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ - #endif - -#else /* MCG_MODE */ - /* Set MCG and OSC */ -#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U) - /* SIM_SCGC5: PORTA=1 */ - SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR18: ISF=0,MUX=0 */ - PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) { - /* PORTA_PCR19: ISF=0,MUX=0 */ - PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } -#endif - MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */ - MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ - OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ - MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ - #if (MCG_MODE == MCG_MODE_PEE) - MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/ - #else - MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ - #endif - if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) { - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ - } - } - /* Check that the source of the FLL reference clock is the requested one. */ - if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) { - while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { - } - } else { - while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { - } - } - MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */ -#endif /* MCG_MODE */ - - /* Common for all MCG modes */ - - /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */ - MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */ - MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ - if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) { - MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */ - } - /* BLPE, PEE and PBE MCG mode specific */ - -#if (MCG_MODE == MCG_MODE_BLPE) - MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ -#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE)) - MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/ - } - #if (MCG_MODE == MCG_MODE_PEE) - MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK); - #endif -#endif -#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */ - } -#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ - } -#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE)) - while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ - } -#elif (MCG_MODE == MCG_MODE_PEE) - while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */ - } -#endif -#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT)) - SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */ - while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */ - } -#endif - -#if defined(SYSTEM_SIM_CLKDIV2_VALUE) - SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */ -#endif - - /* PLL loss of lock interrupt request initialization */ - if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) { - NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */ - } -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint16_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { - /* External reference clock is selected */ - switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { - case 0x00U: - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - break; - case 0x01U: - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - break; - case 0x02U: - default: - MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ - break; - } - if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { - switch (MCG->C1 & MCG_C1_FRDIV_MASK) { - case 0x38U: - Divider = 1536U; - break; - case 0x30U: - Divider = 1280U; - break; - default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - break; - } - } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - } - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x00U: - MCGOUTClock *= 640U; - break; - case 0x20U: - MCGOUTClock *= 1280U; - break; - case 0x40U: - MCGOUTClock *= 1920U; - break; - case 0x60U: - MCGOUTClock *= 2560U; - break; - case 0x80U: - MCGOUTClock *= 732U; - break; - case 0xA0U: - MCGOUTClock *= 1464U; - break; - case 0xC0U: - MCGOUTClock *= 2197U; - break; - case 0xE0U: - MCGOUTClock *= 2929U; - break; - default: - break; - } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - /* PLL is selected */ - Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); - MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { - /* External reference clock is selected */ - switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { - case 0x00U: - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - break; - case 0x01U: - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - break; - case 0x02U: - default: - MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ - break; - } - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h deleted file mode 100644 index ebb7c2dbdec..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h +++ /dev/null @@ -1,339 +0,0 @@ -/* -** ################################################################### -** Processor: MK64FN1M0VMD12 -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140611 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK64F12 - * @version 2.5 - * @date 2014-02-10 - * @brief Device specific configuration file for MK64F12 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MK64F12_H_ -#define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#define DISABLE_WDOG 1 - -#ifndef CLOCK_SETUP - #define CLOCK_SETUP 4 -#endif - -/* MCG mode constants */ - -#define MCG_MODE_FEI 0U -#define MCG_MODE_FBI 1U -#define MCG_MODE_BLPI 2U -#define MCG_MODE_FEE 3U -#define MCG_MODE_FBE 4U -#define MCG_MODE_BLPE 5U -#define MCG_MODE_PBE 6U -#define MCG_MODE_PEE 7U - -/* Predefined clock setups - 0 ... Default part configuration - Multipurpose Clock Generator (MCG) in FEI mode. - Reference clock source for MCG module: Slow internal reference clock - Core clock = 20.97152MHz - Bus clock = 20.97152MHz - 1 ... Maximum achievable clock frequency configuration - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 120MHz - Bus clock = 60MHz - 2 ... Chip internaly clocked, ready for Very Low Power Run mode. - Multipurpose Clock Generator (MCG) in BLPI mode. - Reference clock source for MCG module: Fast internal reference clock - Core clock = 4MHz - Bus clock = 4MHz - 3 ... Chip externally clocked, ready for Very Low Power Run mode. - Multipurpose Clock Generator (MCG) in BLPE mode. - Reference clock source for MCG module: RTC oscillator reference clock - Core clock = 0.032768MHz - Bus clock = 0.032768MHz - 4 ... USB clock setup - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 120MHz - Bus clock = 60MHz - */ - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ -#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ -#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ - -/* RTC oscillator setting */ -/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ -#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ - -/* Low power mode enable */ -/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ -#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ - -/* Internal reference clock trim */ -/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ - -#if (CLOCK_SETUP == 0) - #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ -/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 1) - #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */ - #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */ - #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 2) - #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ - /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 3) - #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ - /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=1 */ - #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ -/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 4) - #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */ - #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */ -/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */ - #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */ -/* MCG_C7: OSCSEL=0 */ - #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ -/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */ -/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ - #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */ -/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ -#endif - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MK64F12_H_) */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PeripheralPins.h deleted file mode 100644 index 6cff2fed829..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PeripheralPins.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************RTC***************/ -extern const PinMap PinMap_RTC[]; - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************DAC***************/ -extern const PinMap PinMap_DAC[]; - -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PortNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PortNames.h deleted file mode 100644 index 476845b76d7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PortNames.h +++ /dev/null @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, - PortE = 4 -} PortName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c deleted file mode 100644 index aedae849029..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sim_hal.h" -#include "fsl_clock_manager.h" -#include "fsl_osc_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Table of base addresses for instances. */ -extern const uint32_t g_simBaseAddr[]; -extern const uint32_t g_mcgBaseAddr[]; -const uint32_t g_oscBaseAddr[] = OSC_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetDmaFreq - * Description : Gets the clock frequency for DMA module - * This function gets the clock frequency for DMA moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kSystemClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetDmamuxFreq - * Description : Gets the clock frequency for DMAMUX module - * This function gets the clock frequency for DMAMUX moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetPortFreq - * Description : Gets the clock frequency for PORT module - * This function gets the clock frequency for PORT moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kLpoClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetEwmFreq - * Description : Gets the clock frequency for Ewm module - * This function gets the clock frequency for Ewm moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kLpoClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFlexbusFreq - * Description : Gets the clock frequency for FLEXBUS module - * This function gets the clock frequency for FLEXBUS moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kSystemClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFtfFreq - * Description : Gets the clock frequency for FTF module. (Flash Memory) - * This function gets the clock frequency for FTF moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kFlashClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetCrcFreq - * Description : Gets the clock frequency for CRC module - * This function gets the clock frequency for CRC moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetRngaFreq - * Description : Gets the clock frequency for RNGA module - * This function gets the clock frequency for RNGA moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetAdcFreq - * Description : Gets the clock frequency for ADC module - * This function gets the clock frequency for ADC moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint32_t divider; - - CLOCK_SYS_GetFreq(kOsc0ErClock, &freq); - - divider = OSC_HAL_GetExternalRefClkDivCmd(g_oscBaseAddr[0]); - freq = freq >> divider; /* 2 bits divider, divide by 1/2/4/8 */ - - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetCmpFreq - * Description : Gets the clock frequency for CMP module - * This function gets the clock frequency for CMP moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetVrefFreq - * Description : Gets the clock frequency for VREF module - * This function gets the clock frequency for VREF moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetPdbFreq - * Description : Gets the clock frequency for PDB module - * This function gets the clock frequency for PDB moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFtmFreq - * Description : Gets the clock frequency for FTM module. (FlexTimers) - * This function gets the clock frequency for FTM moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kMcgFfClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetPitFreq - * Description : Gets the clock frequency for Pit module. - * This function gets the clock frequency for Pit moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetUsbFreq - * Description : Gets the clock frequency for USB FS OTG module. - * This function gets the clock frequency for USB FS OTG moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint8_t setting; - clock_names_t clockName; - uint32_t frac = 0; - uint32_t divider = 0; - - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockUsbSrc, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_usb_clock_source_t)setting) - { - case kSimUsbSrcClkIn: /* Core/system clock */ - clockName = kUSB_CLKIN; - break; - case kSimUsbSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */ - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_pllfll_clock_sel_t)setting) - { - case kSimPllFllSelFll: /* Fll clock */ - clockName = kMcgFllClock; - break; - case kSimPllFllSelPll: /* Pll0 clock */ - clockName = kMcgPll0Clock; - break; - case kSimPllFllSelIrc: /* Irc 48Mhz clock */ - clockName = kIrc48mClock; - break; - default: - clockName = kReserved; - break; - } - break; - default: - clockName = kReserved; - break; - } - - /* Get ref clock freq */ - CLOCK_SYS_GetFreq(clockName, &freq); - - /* Get divider and frac */ - CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbDiv, ÷r); - CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbFrac, &frac); - - /* Divider output clock = Divider input clock × [ (FRAC+1) / (DIV+1) ]*/ - freq = (freq) * (frac + 1) / (divider + 1); - - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSpiFreq - * Description : Gets the clock frequency for SPI module. - * This function gets the clock frequency for SPI moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetI2cFreq - * Description : Gets the clock frequency for I2C module. - * This function gets the clock frequency for I2C moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetUartFreq - * Description : Gets the clock frequency for UART module. - * This function gets the clock frequency for UART moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance) -{ - uint32_t freq = 0; - - switch (instance) - { - case 0: - case 1: - CLOCK_SYS_GetFreq(kSystemClock, &freq); - break; - case 2: - CLOCK_SYS_GetFreq(kBusClock, &freq); - break; - default: - break; - } - - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetLpuartFreq - * Description : Gets the clock frequency for LPUART module. - * This function gets the clock frequency for LPUART moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint8_t setting; - uint8_t setting1; - clock_names_t clockName; - uint32_t divider = 0; - - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockLpuartSrc, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_lpuart_clock_source_t)setting) - { - case kSimLpuartSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */ - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting1) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_pllfll_clock_sel_t)setting1) - { - case kSimPllFllSelFll: /* Fll clock */ - clockName = kMcgFllClock; - break; - case kSimPllFllSelPll: /* Pll0 clock */ - clockName = kMcgPll0Clock; - break; - case kSimPllFllSelIrc: /* Irc 48Mhz clock */ - clockName = kIrc48mClock; - break; - default: - clockName = kReserved; - break; - } - break; - case kSimLpuartSrcOscErclk: /* OscErClk with divider */ - clockName = kOsc0ErClock; - break; - case kSimLpuartSrcMcgIrclk: /* MCGIRCLK */ - clockName = kMcgIrClock; - break; - default: - clockName = kReserved; - break; - } - - /* Get ref clock freq */ - CLOCK_SYS_GetFreq(clockName, &freq); - - if ((sim_lpuart_clock_source_t)setting == kSimLpuartSrcOscErclk) - { - divider = OSC_HAL_GetExternalRefClkDivCmd(g_oscBaseAddr[0]); - freq = freq >> divider; /* 2 bits divider, divide by 1/2/4/8 */ - } - - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSaiFreq - * Description : Gets the clock frequency for I2S module - * This function gets the clock frequency for I2S moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetGpioFreq - * Description : Gets the clock frequency for GPIO module. - * This function gets the clock frequency for GPIO moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance) -{ - uint32_t freq = 0; - - CLOCK_SYS_GetFreq(kPlatformClock, &freq); - - return freq; -} - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h deleted file mode 100644 index 81c87ba87cc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h +++ /dev/null @@ -1,1033 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_CLOCK_K22F51212_H__) -#define __FSL_CLOCK_K22F51212__H__ - -/*! @addtogroup clock_manager*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Gets the clock frequency for DMA module. - * - * This function gets the clock frequence for DMA moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for DMAMUX module. - * - * This function gets the clock frequence for DMAMUX moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for PORT module. - * - * This function gets the clock frequence for PORT moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for EWM module. - * - * This function gets the clock frequence for EWM moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for FLEXBUS module. - * - * This function gets the clock frequence for FLEXBUS moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for FTF module. (Flash Memory) - * - * This function gets the clock frequence for FTF module. (Flash Memory) - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for CRC module. - * - * This function gets the clock frequence for CRC module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for RNGA module. - * - * This function gets the clock frequence for RNGA module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for ADC module. - * - * This function gets the clock frequence for ADC module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for CMP module. - * - * This function gets the clock frequence for CMP module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for VREF module. - * - * This function gets the clock frequence for VREF module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for PDB module. - * - * This function gets the clock frequence for PDB module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for FTM module. (FlexTimer) - * - * This function gets the clock frequence for FTM module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for PIT module. - * - * This function gets the clock frequence for PIT module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for USB FS OTG module - * - * This function gets the clock frequence for USB FS OTG module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for SPI module - * - * This function gets the clock frequence for SPI module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for I2C module - * - * This function gets the clock frequence for I2C module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for UART module - * - * This function gets the clock frequence for UART module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for LPUART module - * - * This function gets the clock frequence for LPUART module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for I2S module. - * - * This function gets the clock frequence for I2S module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for GPIO module - * - * This function gets the clock frequence for GPIO module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance); - -/*! - * @brief Enable the clock for DMA module. - * - * This function enables the clock for DMA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance) -{ - SIM_HAL_EnableDmaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for DMA module. - * - * This function disables the clock for DMA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance) -{ - SIM_HAL_DisableDmaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for DMA module. - * - * This function will get the clock gate state for DMA moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance) -{ - return SIM_HAL_GetDmaGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for DMAMUX module. - * - * This function enables the clock for DMAMUX moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance) -{ - SIM_HAL_EnableDmamuxClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for DMAMUX module. - * - * This function disables the clock for DMAMUX moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance) -{ - SIM_HAL_DisableDmamuxClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for DMAMUX module. - * - * This function will get the clock gate state for DMAMUX moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance) -{ - return SIM_HAL_GetDmamuxGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for PORT module. - * - * This function enables the clock for PORT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnablePortClock(uint32_t instance) -{ - SIM_HAL_EnablePortClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for PORT module. - * - * This function disables the clock for PORT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisablePortClock(uint32_t instance) -{ - SIM_HAL_DisablePortClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for PORT module. - * - * This function will get the clock gate state for PORT moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetPortGateCmd(uint32_t instance) -{ - return SIM_HAL_GetPortGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for EWM module. - * - * This function enables the clock for EWM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance) -{ - SIM_HAL_EnableEwmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for EWM module. - * - * This function disables the clock for EWM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance) -{ - SIM_HAL_DisableEwmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for EWM module. - * - * This function will get the clock gate state for EWM moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance) -{ - return SIM_HAL_GetEwmGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FLEXBUS module. - * - * This function enables the clock for FLEXBUS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance) -{ - SIM_HAL_EnableFlexbusClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FLEXBUS module. - * - * This function disables the clock for FLEXBUS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance) -{ - SIM_HAL_DisableFlexbusClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FLEXBUS module. - * - * This function will get the clock gate state for FLEXBUS moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFlexbusGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FTF module. - * - * This function enables the clock for FTF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance) -{ - SIM_HAL_EnableFtfClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FTF module. - * - * This function disables the clock for FTF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance) -{ - SIM_HAL_DisableFtfClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FTF module. - * - * This function will get the clock gate state for FTF moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFtfGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for CRC module. - * - * This function enables the clock for CRC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance) -{ - SIM_HAL_EnableCrcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for CRC module. - * - * This function disables the clock for CRC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance) -{ - SIM_HAL_DisableCrcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for CRC module. - * - * This function will get the clock gate state for CRC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetCrcGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for RNGA module. - * - * This function enables the clock for RNGA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance) -{ - SIM_HAL_EnableRngaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for RNGA module. - * - * This function disables the clock for RNGA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance) -{ - SIM_HAL_DisableRngaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for RNGA module. - * - * This function will get the clock gate state for RNGA moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance) -{ - return SIM_HAL_GetRngaGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for ADC module. - * - * This function enables the clock for ADC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance) -{ - SIM_HAL_EnableAdcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for ADC module. - * - * This function disables the clock for ADC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance) -{ - SIM_HAL_DisableAdcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for ADC module. - * - * This function will get the clock gate state for ADC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetAdcGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for CMP module. - * - * This function enables the clock for CMP moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance) -{ - SIM_HAL_EnableCmpClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for CMP module. - * - * This function disables the clock for CMP moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance) -{ - SIM_HAL_DisableCmpClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for CMP module. - * - * This function will get the clock gate state for CMP moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance) -{ - return SIM_HAL_GetCmpGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for DAC module. - * - * This function enables the clock for DAC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableDacClock(uint32_t instance) -{ - SIM_HAL_EnableDacClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for DAC module. - * - * This function disables the clock for DAC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableDacClock(uint32_t instance) -{ - SIM_HAL_DisableDacClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for DAC module. - * - * This function will get the clock gate state for DAC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance) -{ - return SIM_HAL_GetDacGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for VREF module. - * - * This function enables the clock for VREF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance) -{ - SIM_HAL_EnableVrefClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for VREF module. - * - * This function disables the clock for VREF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance) -{ - SIM_HAL_DisableVrefClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for VREF module. - * - * This function will get the clock gate state for VREF moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance) -{ - return SIM_HAL_GetVrefGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for SAI module. - * - * This function enables the clock for SAI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance) -{ - SIM_HAL_EnableSaiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for SAI module. - * - * This function disables the clock for SAI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance) -{ - SIM_HAL_DisableSaiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for SAI module. - * - * This function will get the clock gate state for SAI moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance) -{ - return SIM_HAL_GetSaiGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for PDB module. - * - * This function enables the clock for PDB moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance) -{ - SIM_HAL_EnablePdbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for PDB module. - * - * This function disables the clock for PDB moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance) -{ - SIM_HAL_DisablePdbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for PDB module. - * - * This function will get the clock gate state for PDB moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance) -{ - return SIM_HAL_GetPdbGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FTM module. - * - * This function enables the clock for FTM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance) -{ - SIM_HAL_EnableFtmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FTM module. - * - * This function disables the clock for FTM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance) -{ - SIM_HAL_DisableFtmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FTM module. - * - * This function will get the clock gate state for FTM moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFtmGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for PIT module. - * - * This function enables the clock for PIT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnablePitClock(uint32_t instance) -{ - SIM_HAL_EnablePitClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for PIT module. - * - * This function disables the clock for PIT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisablePitClock(uint32_t instance) -{ - SIM_HAL_DisablePitClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for PIT module. - * - * This function will get the clock gate state for PIT moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance) -{ - return SIM_HAL_GetPitGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for LPTIMER module. - * - * This function enables the clock for LPTIMER moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableLptimerClock(uint32_t instance) -{ - SIM_HAL_EnableLptimerClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for LPTIMER module. - * - * This function disables the clock for LPTIMER moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableLptimerClock(uint32_t instance) -{ - SIM_HAL_DisableLptimerClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for LPTIMER module. - * - * This function will get the clock gate state for LPTIMER moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetLptimerGateCmd(uint32_t instance) -{ - return SIM_HAL_GetLptimerGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for RTC module. - * - * This function enables the clock for RTC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance) -{ - SIM_HAL_EnableRtcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for RTC module. - * - * This function disables the clock for RTC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance) -{ - SIM_HAL_DisableRtcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for RTC module. - * - * This function will get the clock gate state for RTC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetRtcGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for USBFS module. - * - * This function enables the clock for USBFS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableUsbClock(uint32_t instance) -{ - SIM_HAL_EnableUsbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for USBFS module. - * - * This function disables the clock for USBFS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableUsbClock(uint32_t instance) -{ - SIM_HAL_DisableUsbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for USB module. - * - * This function will get the clock gate state for USB moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetUsbGateCmd(uint32_t instance) -{ - return SIM_HAL_GetUsbGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for SPI module. - * - * This function enables the clock for SPI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance) -{ - SIM_HAL_EnableSpiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for SPI module. - * - * This function disables the clock for SPI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance) -{ - SIM_HAL_DisableSpiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for SPI module. - * - * This function will get the clock gate state for SPI moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance) -{ - return SIM_HAL_GetSpiGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for I2C module. - * - * This function enables the clock for I2C moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance) -{ - SIM_HAL_EnableI2cClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for I2C module. - * - * This function disables the clock for I2C moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance) -{ - SIM_HAL_DisableI2cClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for I2C module. - * - * This function will get the clock gate state for I2C moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance) -{ - return SIM_HAL_GetI2cGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for UART module. - * - * This function enables the clock for UART moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableUartClock(uint32_t instance) -{ - SIM_HAL_EnableUartClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for UART module. - * - * This function disables the clock for UART moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableUartClock(uint32_t instance) -{ - SIM_HAL_DisableUartClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for UART module. - * - * This function will get the clock gate state for UART moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance) -{ - return SIM_HAL_GetUartGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for LPUART module. - * - * This function enables the clock for LPUART moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableLpuartClock(uint32_t instance) -{ - SIM_HAL_EnableLpuartClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for LPUART module. - * - * This function disables the clock for LPUART moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableLpuartClock(uint32_t instance) -{ - SIM_HAL_DisableLpuartClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for LPUART module. - * - * This function will get the clock gate state for LPUART moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance) -{ - return SIM_HAL_GetLpuartGateCmd(g_simBaseAddr[0], instance); -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_CLOCK_K22F51212_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c deleted file mode 100644 index 001a66eac29..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c +++ /dev/null @@ -1,1187 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sim_hal_K22F51212.h" -#include "fsl_sim_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief CLOCK name config table for K64*/ -const clock_name_config_t kClockNameConfigTable [] = { - {false, kSystemClock, kClockDividerOutdiv1}, - {false, kSystemClock, kClockDividerOutdiv1}, - {false, kSystemClock, kClockDividerOutdiv1}, - {false, kSystemClock, kClockDividerOutdiv2}, - {false, kSystemClock, kClockDividerOutdiv3}, - {false, kSystemClock, kClockDividerOutdiv4} -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableDmaClock - * Description : Enable the clock for DMA module - * This function enables the clock for DMA moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_DMA(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableDmaClock - * Description : Disable the clock for DMA module - * This function disables the clock for DMA moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableDmaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_DMA(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetDmaGateCmd - * Description : Get the the clock gate state for DMA module - * This function will get the clock gate state for DMA moudle - * - *END**************************************************************************/ -bool SIM_HAL_GetDmaGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC7_DMA(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableDmamuxClock - * Description : Enable the clock for DMAMUX module - * This function enables the clock for DMAMUX moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableDmamuxClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_DMAMUX(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableDmamuxClock - * Description : Disable the clock for DMAMUX module - * This function disables the clock for DMAMUX moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableDmamuxClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_DMAMUX(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetDmamuxGateCmd - * Description : Get the the clock gate state for DMAMUX module - * This function will get the clock gate state for DMAMUX moudle - * - *END**************************************************************************/ -bool SIM_HAL_GetDmamuxGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_DMAMUX(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnablePortClock - * Description : Enable the clock for PORT module - * This function enables the clock for PORT moudle - * - *END**************************************************************************/ -void SIM_HAL_EnablePortClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC5_PORTA(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC5_PORTB(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC5_PORTC(baseAddr, 1); - break; - case 3: - BW_SIM_SCGC5_PORTD(baseAddr, 1); - break; - case 4: - BW_SIM_SCGC5_PORTE(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisablePortClock - * Description : Disable the clock for PORT module - * This function disables the clock for PORT moudle - * - *END**************************************************************************/ -void SIM_HAL_DisablePortClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC5_PORTA(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC5_PORTB(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC5_PORTC(baseAddr, 0); - break; - case 3: - BW_SIM_SCGC5_PORTD(baseAddr, 0); - break; - case 4: - BW_SIM_SCGC5_PORTE(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetPortGateCmd - * Description : Get the the clock gate state for PORT module - * This function will get the clock gate state for PORT moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetPortGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC5_PORTA(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC5_PORTB(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC5_PORTC(baseAddr); - break; - case 3: - retValue = BR_SIM_SCGC5_PORTD(baseAddr); - break; - case 4: - retValue = BR_SIM_SCGC5_PORTE(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableEwmClock - * Description : Enable the clock for EWM module - * This function enables the clock for EWM moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableEwmClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_EWM(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableEwmClock - * Description : Disable the clock for EWM modul - * This function disables the clock for EWM moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_EWM(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetEwmGateCmd - * Description : Get the the clock gate state for EWM module - * This function will get the clock gate state for EWM moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_EWM(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFlexbusClock - * Description : Enable the clock for FLEXBUS module - * This function enables the clock for FLEXBUS moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_FLEXBUS(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFlexbusClock - * Description : Disable the clock for FLEXBUS module - * This function disables the clock for FLEXBUS moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_FLEXBUS(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFlexbusGateCmd - * Description : Get the the clock gate state for FLEXBUS module - * This function will get the clock gate state for FLEXBUS moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC7_FLEXBUS(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFtfClock - * Description : Enable the clock for FTF module - * This function enables the clock for FTF moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableFtfClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_FTF(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFtfClock - * Description : Disable the clock for FTF module - * This function disables the clock for FTF moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableFtfClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_FTF(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtfGateCmd - * Description : Get the the clock gate state for FTF module - * This function will get the clock gate state for FTF moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFtfGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_FTF(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableCrcClock - * Description : Enable the clock for CRC module - * This function enables the clock for CRC moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableCrcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_CRC(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableCrcClock - * Description : Disable the clock for CRC module - * This function disables the clock for CRC moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_CRC(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetCrcGateCmd - * Description : Get the the clock gate state for CRC module - * This function will get the clock gate state for CRC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_CRC(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableRngaClock - * Description : Enable the clock for RNGA module - * This function enables the clock for RNGA moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RNGA(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableRngaClock - * Description : Disable the clock for RNGA module - * This function disables the clock for RNGA moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RNGA(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetRngaGateCmd - * Description : Get the the clock gate state for RNGA module - * This function will get the clock gate state for RNGA moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_RNGA(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableAdcClock - * Description : Enable the clock for ADC module - * This function enables the clock for ADC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableAdcClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_ADC0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC6_ADC1(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableAdcClock - * Description : Disable the clock for ADC module - * This function disables the clock for ADC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableAdcClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_ADC0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC6_ADC1(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetAdcGateCmd - * Description : Get the the clock gate state for ADC module - * This function will get the clock gate state for ADC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetAdcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_ADC0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC6_ADC1(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableCmpClock - * Description : Enable the clock for CMP module - * This function enables the clock for CMP moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableCmpClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_CMP(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableCmpClock - * Description : Disable the clock for CMP module - * This function disables the clock for CMP moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableCmpClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_CMP(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetCmpGateCmd - * Description : Get the the clock gate state for CMP module - * This function will get the clock gate state for CMP moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetCmpGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_CMP(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableDacClock - * Description : Enable the clock for DAC module - * This function enables the clock for DAC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_DAC0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC6_DAC1(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableDacClock - * Description : Disable the clock for DAC module - * This function disables the clock for DAC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_DAC0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC6_DAC1(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetDacGateCmd - * Description : Get the the clock gate state for DAC module - * This function will get the clock gate state for DAC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_DAC0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC6_DAC1(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableVrefClock - * Description : Enable the clock for VREF module - * This function enables the clock for VREF moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableVrefClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_VREF(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableVrefClock - * Description : Disable the clock for VREF module - * This function disables the clock for VREF moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableVrefClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_VREF(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetVrefGateCmd - * Description : Get the the clock gate state for VREF module - * This function will get the clock gate state for VREF moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetVrefGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_VREF(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableSaiClock - * Description : Enable the clock for SAI module - * This function enables the clock for SAI moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableSaiClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_I2S(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableSaiClock - * Description : Disable the clock for SAI module - * This function disables the clock for SAI moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableSaiClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_I2S(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetSaiGateCmd - * Description : Get the the clock gate state for SAI module - * This function will get the clock gate state for SAI moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetSaiGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_I2S(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnablePdbClock - * Description : Enable the clock for PDB module - * This function enables the clock for PDB moudle - * - *END**************************************************************************/ -void SIM_HAL_EnablePdbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PDB(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisablePdbClock - * Description : Disable the clock for PDB module - * This function disables the clock for PDB moudle - * - *END**************************************************************************/ -void SIM_HAL_DisablePdbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PDB(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetPdbGateCmd - * Description : Get the the clock gate state for PDB module - * This function will get the clock gate state for PDB moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetPdbGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_PDB(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFtmClock - * Description : Enable the clock for FTM module - * This function enables the clock for FTM moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_FTM0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC6_FTM1(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC6_FTM2(baseAddr, 1); - break; - case 3: - BW_SIM_SCGC6_FTM3(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFtmClock - * Description : Disable the clock for FTM module - * This function disables the clock for FTM moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_FTM0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC6_FTM1(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC6_FTM2(baseAddr, 0); - break; - case 3: - BW_SIM_SCGC6_FTM3(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtmGateCmd - * Description : Get the the clock gate state for FTM module - * This function will get the clock gate state for FTM moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_FTM0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC6_FTM1(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC6_FTM2(baseAddr); - break; - case 3: - retValue = BR_SIM_SCGC6_FTM3(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnablePitClock - * Description : Enable the clock for PIT module - * This function enables the clock for PIT moudle - * - *END**************************************************************************/ -void SIM_HAL_EnablePitClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PIT(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisablePitClock - * Description : Disable the clock for PIT module - * This function disables the clock for PIT moudle - * - *END**************************************************************************/ -void SIM_HAL_DisablePitClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PIT(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetPitGateCmd - * Description : Get the the clock gate state for PIT module - * This function will get the clock gate state for PIT moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetPitGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_PIT(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableLptimerClock - * Description : Enable the clock for LPTIMER module - * This function enables the clock for LPTIMER moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableLptimerClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC5_LPTMR(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableLptimerClock - * Description : Disable the clock for LPTIMER module - * This function disables the clock for LPTIMER moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableLptimerClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC5_LPTMR(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetLptimerGateCmd - * Description : Get the the clock gate state for LPTIMER module - * This function will get the clock gate state for LPTIMER moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetLptimerGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC5_LPTMR(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableRtcClock - * Description : Enable the clock for RTC module - * This function enables the clock for RTC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableRtcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RTC(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableRtcClock - * Description : Disable the clock for RTC module - * This function disables the clock for RTC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableRtcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RTC(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetRtcGateCmd - * Description : Get the the clock gate state for RTC module - * This function will get the clock gate state for RTC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetRtcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_RTC(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableUsbClock - * Description : Enable the clock for USBFS module - * This function enables the clock for USBFS moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableUsbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_USBOTG(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableUsbClock - * Description : Disable the clock for USBFS module - * This function disables the clock for USBFS moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableUsbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_USBOTG(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUsbGateCmd - * Description : Get the the clock gate state for USB module - * This function will get the clock gate state for USB moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetUsbGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_USBOTG(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableSpiClock - * Description : Enable the clock for SPI module - * This function enables the clock for SPI moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableSpiClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_SPI0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC6_SPI1(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableSpiClock - * Description : Disable the clock for SPI module - * This function disables the clock for SPI moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableSpiClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_SPI0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC6_SPI1(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetSpiGateCmd - * Description : Get the the clock gate state for SPI module - * This function will get the clock gate state for SPI moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetSpiGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_SPI0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC6_SPI1(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableI2cClock - * Description : Enable the clock for I2C module - * This function enables the clock for I2C moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableI2cClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_I2C0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC4_I2C1(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableI2cClock - * Description : Disable the clock for I2C module - * This function disables the clock for I2C moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableI2cClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_I2C0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC4_I2C1(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetI2cGateCmd - * Description : Get the the clock gate state for I2C module - * This function will get the clock gate state for I2C moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetI2cGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC4_I2C0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC4_I2C1(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableUartClock - * Description : Enable the clock for UART module - * This function enables the clock for UART moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableUartClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_UART0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC4_UART1(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC4_UART2(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableUartClock - * Description : Disable the clock for UART module - * This function disables the clock for UART moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableUartClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_UART0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC4_UART1(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC4_UART2(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUartGateCmd - * Description : Get the the clock gate state for UART module - * This function will get the clock gate state for UART moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetUartGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC4_UART0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC4_UART1(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC4_UART2(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableLpuartClock - * Description : Enable the clock for LPUART module - * This function enables the clock for LPUART moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableLpuartClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_LPUART0(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableLpuartClock - * Description : Disable the clock for LPUART module - * This function disables the clock for LPUART moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableLpuartClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_LPUART0(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetLpuartGateCmd - * Description : Get the the clock gate state for LPUART module - * This function will get the clock gate state for LPUART moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetLpuartGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_LPUART0(baseAddr); -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h deleted file mode 100644 index cf0f2fd16a3..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h +++ /dev/null @@ -1,839 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_SIM_HAL_K22F51212_H__) -#define __FSL_SIM_HAL_K22F51212_H__ - -/*! @addtogroup sim_hal*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief SIM USB clock source */ -typedef enum _sim_usb_clock_source -{ - kSimUsbSrcClkIn, /* USB CLKIN Clock */ - kSimUsbSrcPllFllSel /* clock as selected by SOPT2[PLLFLLSEL] */ -} sim_usb_clock_source_t; - -/*! @brief SIM LPUART clock source */ -typedef enum _sim_lpuart_clock_source -{ - kSimLpuartSrcNone, /* Clock disabled */ - kSimLpuartSrcPllFllSel, /* Clock as selected by SOPT2[PLLFLLSEL] */ - kSimLpuartSrcOscErclk, /* OscErClk with special divider */ - kSimLpuartSrcMcgIrclk /* MCGIRCLK */ -} sim_lpuart_clock_source_t; - -/*! @brief SIM PLLFLLSEL clock source select */ -typedef enum _sim_pllfll_clock_sel -{ - kSimPllFllSelFll, /* Fll clock */ - kSimPllFllSelPll, /* Pll0 clock */ - kSimPllFllSelNone, /* reserved */ - kSimPllFllSelIrc /* IRC 48Mhz */ -} sim_pllfll_clock_sel_t; - -/*! @brief SIM OSC32KSEL clock source select */ -typedef enum _sim_osc32k_clock_sel -{ - kSimOsc32kSelOsc32k, /* OSC 32k clock */ - kSimOsc32kSelReserved, /* Reserved */ - kSimOsc32kSelRtc32k, /* RTC 32k clock */ - kSimOsc32kSelLpo /* LPO clock */ -} sim_osc32k_clock_sel_t; - -/*! @brief SIM TRACESEL clock source select */ -typedef enum _sim_trace_clock_sel -{ - kSimTraceMcgoutClk, /* MCG out clock */ - kSimTraceCoreClk /* core clock */ -} sim_trace_clock_sel_t; - -/*! @brief SIM CLKOUT_SEL clock source select */ -typedef enum _sim_clkout_clock_sel -{ - kSimClkoutFlexbusClk, /* Flexbus clock */ - kSimClkoutReserved, /* Reserved */ - kSimClkoutFlashClk, /* Flash clock */ - kSimClkoutLpoClk, /* LPO clock */ - kSimClkoutMcgIrcClk, /* MCG out clock */ - kSimClkoutRtc32kClk, /* RTC 32k clock */ - kSimClkoutOscErClk, - KsimClkoutIrcClk -} sim_clkout_clock_sel_t; - -/*! @brief SIM RTCCLKOUTSEL clock source select */ -typedef enum _sim_rtcclkout_clock_sel -{ - kSimRtcClkout1hzClk, /* 1Hz clock */ - kSimRtcClkout32kClk /* 32KHz clock */ -} sim_rtcclkout_clock_sel_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name IP related clock feature APIs*/ -/*@{*/ - -/*! - * @brief Enable the clock for DMA module. - * - * This function enables the clock for DMA moudle. - * @param instance module device instance - */ -void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for DMA module. - * - * This function disables the clock for DMA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableDmaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for DMA module. - * - * This function will get the clock gate state for DMA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetDmaGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for DMAMUX module. - * - * This function enables the clock for DMAMUX moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableDmamuxClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for DMAMUX module. - * - * This function disables the clock for DMAMUX moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableDmamuxClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for DMAMUX module. - * - * This function will get the clock gate state for DMAMUX moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetDmamuxGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for PORT module. - * - * This function enables the clock for PORT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnablePortClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for PORT module. - * - * This function disables the clock for PORT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisablePortClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for PORT module. - * - * This function will get the clock gate state for PORT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetPortGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for EWM module. - * - * This function enables the clock for EWM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableEwmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for EWM module. - * - * This function disables the clock for EWM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for EWM module. - * - * This function will get the clock gate state for EWM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FLEXBUS module. - * - * This function enables the clock for FLEXBUS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FLEXBUS module. - * - * This function disables the clock for FLEXBUS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FLEXBUS module. - * - * This function will get the clock gate state for FLEXBUS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FTF module. - * - * This function enables the clock for FTF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFtfClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FTF module. - * - * This function disables the clock for FTF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFtfClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FTF module. - * - * This function will get the clock gate state for FTF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFtfGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for CRC module. - * - * This function enables the clock for CRC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableCrcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for CRC module. - * - * This function disables the clock for CRC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for CRC module. - * - * This function will get the clock gate state for CRC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for RNGA module. - * - * This function enables the clock for RNGA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for RNGA module. - * - * This function disables the clock for RNGA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for RNGA module. - * - * This function will get the clock gate state for RNGA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for ADC module. - * - * This function enables the clock for ADC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableAdcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for ADC module. - * - * This function disables the clock for ADC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableAdcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for ADC module. - * - * This function will get the clock gate state for ADC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetAdcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for CMP module. - * - * This function enables the clock for CMP moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableCmpClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for CMP module. - * - * This function disables the clock for CMP moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableCmpClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for CMP module. - * - * This function will get the clock gate state for CMP moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetCmpGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for DAC module. - * - * This function enables the clock for DAC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for DAC module. - * - * This function disables the clock for DAC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for DAC module. - * - * This function will get the clock gate state for DAC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for VREF module. - * - * This function enables the clock for VREF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableVrefClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for VREF module. - * - * This function disables the clock for VREF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableVrefClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for VREF module. - * - * This function will get the clock gate state for VREF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetVrefGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for SAI module. - * - * This function enables the clock for SAI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableSaiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for SAI module. - * - * This function disables the clock for SAI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableSaiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for SAI module. - * - * This function will get the clock gate state for SAI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetSaiGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for PDB module. - * - * This function enables the clock for PDB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnablePdbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for PDB module. - * - * This function disables the clock for PDB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisablePdbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for PDB module. - * - * This function will get the clock gate state for PDB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetPdbGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FTM module. - * - * This function enables the clock for FTM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FTM module. - * - * This function disables the clock for FTM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FTM module. - * - * This function will get the clock gate state for FTM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for PIT module. - * - * This function enables the clock for PIT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnablePitClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for PIT module. - * - * This function disables the clock for PIT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisablePitClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for PIT module. - * - * This function will get the clock gate state for PIT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetPitGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for LPTIMER module. - * - * This function enables the clock for LPTIMER moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableLptimerClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for LPTIMER module. - * - * This function disables the clock for LPTIMER moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableLptimerClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for LPTIMER module. - * - * This function will get the clock gate state for LPTIMER moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetLptimerGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for RTC module. - * - * This function enables the clock for RTC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableRtcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for RTC module. - * - * This function disables the clock for RTC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableRtcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for RTC module. - * - * This function will get the clock gate state for RTC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetRtcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for USBFS module. - * - * This function enables the clock for USBFS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableUsbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for USBFS module. - * - * This function disables the clock for USBFS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableUsbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for USB module. - * - * This function will get the clock gate state for USB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetUsbGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for SPI module. - * - * This function enables the clock for SPI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableSpiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for SPI module. - * - * This function disables the clock for SPI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableSpiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for SPI module. - * - * This function will get the clock gate state for SPI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetSpiGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for I2C module. - * - * This function enables the clock for I2C moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableI2cClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for I2C module. - * - * This function disables the clock for I2C moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableI2cClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for I2C module. - * - * This function will get the clock gate state for I2C moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetI2cGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for UART module. - * - * This function enables the clock for UART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableUartClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for UART module. - * - * This function disables the clock for UART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableUartClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for UART module. - * - * This function will get the clock gate state for UART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetUartGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for LPUART module. - * - * This function enables the clock for LPUART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableLpuartClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for LPUART module. - * - * This function disables the clock for LPUART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableLpuartClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for LPUART module. - * - * This function will get the clock gate state for LPUART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetLpuartGateCmd(uint32_t baseAddr, uint32_t instance); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - - -/*! @}*/ - -#endif /* __FSL_SIM_HAL_K22F51212_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralNames.h deleted file mode 100644 index a471a6be718..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralNames.h +++ /dev/null @@ -1,133 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_0 = 0, - UART_1 = 1, - UART_2 = 2, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_1 - -typedef enum { - I2C_0 = 0, - I2C_1 = 1, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_00 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_01 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_02 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_03 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_04 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_05 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_06 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_07 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_10 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_11 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_12 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 - PWM_13 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 - PWM_14 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 - PWM_15 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 - PWM_16 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 - PWM_17 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 - PWM_20 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_21 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 - PWM_22 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 - PWM_23 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 - PWM_24 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 - PWM_25 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 - PWM_26 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 - PWM_27 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 - PWM_30 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 - PWM_31 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 - PWM_32 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 - PWM_33 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 - PWM_34 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 - PWM_35 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 - PWM_36 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 - PWM_37 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 -typedef enum { - ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, - ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, - ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, - ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, - ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, - ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, - ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, - ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, - ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, - ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, - ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, - ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, - ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, - ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, - ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, - ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, - ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, - ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, - ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, - ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, - ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, - ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, - ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, - ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, - ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, - ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_0 = 0, - SPI_1 = 1, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralPins.c deleted file mode 100644 index 50d938862f4..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralPins.c +++ /dev/null @@ -1,185 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTA17, ADC1_SE17, 0}, - {PTB0 , ADC0_SE8 , 0}, - {PTB1 , ADC0_SE9 , 0}, - {PTB2 , ADC0_SE12, 0}, - {PTB3 , ADC0_SE13, 0}, - {PTB6 , ADC1_SE12, 0}, - {PTB7 , ADC1_SE13, 0}, - {PTB10, ADC1_SE14, 0}, - {PTB11, ADC1_SE15, 0}, - {PTC0 , ADC0_SE14, 0}, - {PTC1 , ADC0_SE15, 0}, - {PTC2, ADC0_SE4b, 0}, - {PTC8, ADC1_SE4b, 0}, - {PTC9, ADC1_SE5b, 0}, - {PTC10, ADC1_SE6b, 0}, - {PTC11, ADC1_SE7b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {PTE0, ADC1_SE4a, 0}, - {PTE1, ADC1_SE5a, 0}, - {PTE2, ADC1_SE6a, 0}, - {PTE3, ADC1_SE7a, 0}, - //{PTE24, ADC0_SE17, 0}, //I2C pull up - //{PTE25, ADC0_SE18, 0}, //I2C pull up - {NC , NC , 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {DAC0_OUT, DAC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTB1 , I2C_0 , 2}, - {PTB3 , I2C_0 , 2}, - {PTC11, I2C_1 , 2}, - {PTD3 , I2C_0 , 7}, - {PTD9 , I2C_0 , 2}, - {PTE0 , I2C_1 , 6}, - {PTE25, I2C_0 , 5}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTB0 , I2C_0 , 2}, - {PTB2 , I2C_0 , 2}, - {PTC10, I2C_1 , 2}, - {PTD2 , I2C_0 , 7}, - {PTD8 , I2C_0 , 2}, - {PTE1 , I2C_1 , 6}, - {PTE24, I2C_0 , 5}, - {NC , NC , 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTA2 , UART_0, 2}, - {PTA14, UART_0, 3}, - {PTB17, UART_0, 3}, - {PTD7 , UART_0, 3}, - {PTC4 , UART_1, 3}, - {PTE0 , UART_1, 3}, - {PTD3 , UART_2, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTA1 , UART_0, 2}, - {PTA15, UART_0, 3}, - {PTB16, UART_0, 3}, - {PTD6 , UART_0, 3}, - {PTC3 , UART_1, 3}, - {PTE1 , UART_1, 3}, - {PTD2 , UART_2, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTD1 , SPI_0, 2}, - {PTE2 , SPI_1, 2}, - {PTA15, SPI_0, 2}, - {PTB11, SPI_1, 2}, - {PTC5 , SPI_0, 2}, - {PTD5 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTD2 , SPI_0, 2}, - {PTE1 , SPI_1, 2}, - {PTE3 , SPI_1, 7}, - {PTA16, SPI_0, 2}, - {PTB16, SPI_1, 2}, - {PTC6 , SPI_0, 2}, - {PTD6 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTD3 , SPI_0, 2}, - {PTE1 , SPI_1, 7}, - {PTE3 , SPI_1, 2}, - {PTA17, SPI_0, 2}, - {PTB17, SPI_1, 2}, - {PTC7 , SPI_0, 2}, - {PTD7 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTD0 , SPI_0, 2}, - {PTE4 , SPI_1, 2}, - {PTA14, SPI_0, 2}, - {PTB10, SPI_1, 2}, - {PTC4 , SPI_0, 2}, - {PTD4 , SPI_1, 7}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PTA0 , PWM_05, 3}, - {PTA1 , PWM_06, 3}, - {PTA2 , PWM_07, 3}, - {PTA3 , PWM_00, 3}, - {PTA4 , PWM_01, 3}, - {PTA5 , PWM_02, 3}, - {PTA10, PWM_20, 3}, - {PTA11, PWM_21, 3}, - {PTA12, PWM_10, 3}, - {PTA13, PWM_11, 3}, - - {PTB0 , PWM_10, 3}, - {PTB1 , PWM_11, 3}, - {PTB18, PWM_20, 3}, - {PTB19, PWM_21, 3}, - - {PTC1 , PWM_00, 4}, - {PTC2 , PWM_01, 4}, - {PTC3 , PWM_02, 4}, - {PTC4 , PWM_03, 4}, - {PTC5 , PWM_02, 7}, - - {PTD0 , PWM_30, 4}, - {PTD1 , PWM_31, 4}, - {PTD2 , PWM_32, 4}, - {PTD3 , PWM_33, 4}, - {PTD4 , PWM_04, 4}, - {PTD5 , PWM_05, 4}, - {PTD6 , PWM_06, 4}, - {PTD7 , PWM_07, 4}, - - {PTE5 , PWM_30, 6}, - {PTE6 , PWM_31, 6}, - {NC , NC , 0} -}; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PinNames.h deleted file mode 100644 index c18628ff11a..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PinNames.h +++ /dev/null @@ -1,259 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define GPIO_PORT_SHIFT 12 - -typedef enum { - PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), - PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), - PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), - PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), - PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), - PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), - PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), - PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), - PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), - PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), - PTA10 = (0 << GPIO_PORT_SHIFT | 10), - PTA11 = (0 << GPIO_PORT_SHIFT | 11), - PTA12 = (0 << GPIO_PORT_SHIFT | 12), - PTA13 = (0 << GPIO_PORT_SHIFT | 13), - PTA14 = (0 << GPIO_PORT_SHIFT | 14), - PTA15 = (0 << GPIO_PORT_SHIFT | 15), - PTA16 = (0 << GPIO_PORT_SHIFT | 16), - PTA17 = (0 << GPIO_PORT_SHIFT | 17), - PTA18 = (0 << GPIO_PORT_SHIFT | 18), - PTA19 = (0 << GPIO_PORT_SHIFT | 19), - PTA20 = (0 << GPIO_PORT_SHIFT | 20), - PTA21 = (0 << GPIO_PORT_SHIFT | 21), - PTA22 = (0 << GPIO_PORT_SHIFT | 22), - PTA23 = (0 << GPIO_PORT_SHIFT | 23), - PTA24 = (0 << GPIO_PORT_SHIFT | 24), - PTA25 = (0 << GPIO_PORT_SHIFT | 25), - PTA26 = (0 << GPIO_PORT_SHIFT | 26), - PTA27 = (0 << GPIO_PORT_SHIFT | 27), - PTA28 = (0 << GPIO_PORT_SHIFT | 28), - PTA29 = (0 << GPIO_PORT_SHIFT | 29), - PTA30 = (0 << GPIO_PORT_SHIFT | 30), - PTA31 = (0 << GPIO_PORT_SHIFT | 31), - PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), - PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), - PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), - PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), - PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), - PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), - PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), - PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), - PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), - PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), - PTB10 = (1 << GPIO_PORT_SHIFT | 10), - PTB11 = (1 << GPIO_PORT_SHIFT | 11), - PTB12 = (1 << GPIO_PORT_SHIFT | 12), - PTB13 = (1 << GPIO_PORT_SHIFT | 13), - PTB14 = (1 << GPIO_PORT_SHIFT | 14), - PTB15 = (1 << GPIO_PORT_SHIFT | 15), - PTB16 = (1 << GPIO_PORT_SHIFT | 16), - PTB17 = (1 << GPIO_PORT_SHIFT | 17), - PTB18 = (1 << GPIO_PORT_SHIFT | 18), - PTB19 = (1 << GPIO_PORT_SHIFT | 19), - PTB20 = (1 << GPIO_PORT_SHIFT | 20), - PTB21 = (1 << GPIO_PORT_SHIFT | 21), - PTB22 = (1 << GPIO_PORT_SHIFT | 22), - PTB23 = (1 << GPIO_PORT_SHIFT | 23), - PTB24 = (1 << GPIO_PORT_SHIFT | 24), - PTB25 = (1 << GPIO_PORT_SHIFT | 25), - PTB26 = (1 << GPIO_PORT_SHIFT | 26), - PTB27 = (1 << GPIO_PORT_SHIFT | 27), - PTB28 = (1 << GPIO_PORT_SHIFT | 28), - PTB29 = (1 << GPIO_PORT_SHIFT | 29), - PTB30 = (1 << GPIO_PORT_SHIFT | 30), - PTB31 = (1 << GPIO_PORT_SHIFT | 31), - PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), - PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), - PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), - PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), - PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), - PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), - PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), - PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), - PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), - PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), - PTC10 = (2 << GPIO_PORT_SHIFT | 10), - PTC11 = (2 << GPIO_PORT_SHIFT | 11), - PTC12 = (2 << GPIO_PORT_SHIFT | 12), - PTC13 = (2 << GPIO_PORT_SHIFT | 13), - PTC14 = (2 << GPIO_PORT_SHIFT | 14), - PTC15 = (2 << GPIO_PORT_SHIFT | 15), - PTC16 = (2 << GPIO_PORT_SHIFT | 16), - PTC17 = (2 << GPIO_PORT_SHIFT | 17), - PTC18 = (2 << GPIO_PORT_SHIFT | 18), - PTC19 = (2 << GPIO_PORT_SHIFT | 19), - PTC20 = (2 << GPIO_PORT_SHIFT | 20), - PTC21 = (2 << GPIO_PORT_SHIFT | 21), - PTC22 = (2 << GPIO_PORT_SHIFT | 22), - PTC23 = (2 << GPIO_PORT_SHIFT | 23), - PTC24 = (2 << GPIO_PORT_SHIFT | 24), - PTC25 = (2 << GPIO_PORT_SHIFT | 25), - PTC26 = (2 << GPIO_PORT_SHIFT | 26), - PTC27 = (2 << GPIO_PORT_SHIFT | 27), - PTC28 = (2 << GPIO_PORT_SHIFT | 28), - PTC29 = (2 << GPIO_PORT_SHIFT | 29), - PTC30 = (2 << GPIO_PORT_SHIFT | 30), - PTC31 = (2 << GPIO_PORT_SHIFT | 31), - PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), - PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), - PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), - PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), - PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), - PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), - PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), - PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), - PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), - PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), - PTD10 = (3 << GPIO_PORT_SHIFT | 10), - PTD11 = (3 << GPIO_PORT_SHIFT | 11), - PTD12 = (3 << GPIO_PORT_SHIFT | 12), - PTD13 = (3 << GPIO_PORT_SHIFT | 13), - PTD14 = (3 << GPIO_PORT_SHIFT | 14), - PTD15 = (3 << GPIO_PORT_SHIFT | 15), - PTD16 = (3 << GPIO_PORT_SHIFT | 16), - PTD17 = (3 << GPIO_PORT_SHIFT | 17), - PTD18 = (3 << GPIO_PORT_SHIFT | 18), - PTD19 = (3 << GPIO_PORT_SHIFT | 19), - PTD20 = (3 << GPIO_PORT_SHIFT | 20), - PTD21 = (3 << GPIO_PORT_SHIFT | 21), - PTD22 = (3 << GPIO_PORT_SHIFT | 22), - PTD23 = (3 << GPIO_PORT_SHIFT | 23), - PTD24 = (3 << GPIO_PORT_SHIFT | 24), - PTD25 = (3 << GPIO_PORT_SHIFT | 25), - PTD26 = (3 << GPIO_PORT_SHIFT | 26), - PTD27 = (3 << GPIO_PORT_SHIFT | 27), - PTD28 = (3 << GPIO_PORT_SHIFT | 28), - PTD29 = (3 << GPIO_PORT_SHIFT | 29), - PTD30 = (3 << GPIO_PORT_SHIFT | 30), - PTD31 = (3 << GPIO_PORT_SHIFT | 31), - PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), - PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), - PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), - PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), - PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), - PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), - PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), - PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), - PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), - PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), - PTE10 = (4 << GPIO_PORT_SHIFT | 10), - PTE11 = (4 << GPIO_PORT_SHIFT | 11), - PTE12 = (4 << GPIO_PORT_SHIFT | 12), - PTE13 = (4 << GPIO_PORT_SHIFT | 13), - PTE14 = (4 << GPIO_PORT_SHIFT | 14), - PTE15 = (4 << GPIO_PORT_SHIFT | 15), - PTE16 = (4 << GPIO_PORT_SHIFT | 16), - PTE17 = (4 << GPIO_PORT_SHIFT | 17), - PTE18 = (4 << GPIO_PORT_SHIFT | 18), - PTE19 = (4 << GPIO_PORT_SHIFT | 19), - PTE20 = (4 << GPIO_PORT_SHIFT | 20), - PTE21 = (4 << GPIO_PORT_SHIFT | 21), - PTE22 = (4 << GPIO_PORT_SHIFT | 22), - PTE23 = (4 << GPIO_PORT_SHIFT | 23), - PTE24 = (4 << GPIO_PORT_SHIFT | 24), - PTE25 = (4 << GPIO_PORT_SHIFT | 25), - PTE26 = (4 << GPIO_PORT_SHIFT | 26), - PTE27 = (4 << GPIO_PORT_SHIFT | 27), - PTE28 = (4 << GPIO_PORT_SHIFT | 28), - PTE29 = (4 << GPIO_PORT_SHIFT | 29), - PTE30 = (4 << GPIO_PORT_SHIFT | 30), - PTE31 = (4 << GPIO_PORT_SHIFT | 31), - - LED_RED = PTA1, - LED_GREEN = PTA2, - LED_BLUE = PTD5, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_RED, - - //Push buttons - SW2 = PTC1, - SW3 = PTB17, - - // USB Pins - USBTX = PTE0, - USBRX = PTE1, - - // Arduino Headers - - D0 = PTD2, - D1 = PTD3, - D2 = PTB16, - D3 = PTA2, - D4 = PTA4, - D5 = PTB18, - D6 = PTC3, - D7 = PTC6, - D8 = PTB19, - D9 = PTA1, - D10 = PTD4, - D11 = PTD6, - D12 = PTD7, - D13 = PTD5, - D14 = PTE0, - D15 = PTE1, - - I2C_SCL = D15, - I2C_SDA = D14, - - A0 = PTB0, - A1 = PTB1, - A2 = PTC1, - A3 = PTC2, - A4 = PTB3, - A5 = PTB2, - - DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device.h deleted file mode 100644 index 8f3ef7e1252..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h deleted file mode 100644 index fd48b0f8c25..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h +++ /dev/null @@ -1,10137 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK22F51212 -** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK22F51212.h - * @version 2.5 - * @date 2014-05-06 - * @brief CMSIS Peripheral Access Layer for MK22F51212 - * - * CMSIS Peripheral Access Layer for MK22F51212 - */ - - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */ -#define MK22F51212_H_ -#define MCU_MK22F51212 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0005u - -/** - * @brief Macro to calculate address of an aliased word in the peripheral - * bitband area for a peripheral register and bit (bit band region 0x40000000 to - * 0x400FFFFF). - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Address of the aliased word in the peripheral bitband area. - */ -#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 32bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 16bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 8bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ - DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ - DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ - DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ - DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ - DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ - DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ - DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ - DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ - DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ - DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ - DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ - DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ - DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ - DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ - DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ - MCM_IRQn = 17, /**< Normal Interrupt */ - FTF_IRQn = 18, /**< FTFA Command complete interrupt */ - Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG Interrupt */ - RNG_IRQn = 23, /**< RNG Interrupt */ - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, /**< I2C1 interrupt */ - SPI0_IRQn = 26, /**< SPI0 Interrupt */ - SPI1_IRQn = 27, /**< SPI1 Interrupt */ - I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ - LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */ - UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ - UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ - UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ - UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ - UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ - UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ - Reserved53_IRQn = 37, /**< Reserved interrupt 53 */ - Reserved54_IRQn = 38, /**< Reserved interrupt 54 */ - ADC0_IRQn = 39, /**< ADC0 interrupt */ - CMP0_IRQn = 40, /**< CMP0 interrupt */ - CMP1_IRQn = 41, /**< CMP1 interrupt */ - FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt 61 */ - RTC_IRQn = 46, /**< RTC interrupt */ - RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ - PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 52, /**< PDB0 Interrupt */ - USB0_IRQn = 53, /**< USB0 interrupt */ - Reserved70_IRQn = 54, /**< Reserved interrupt 70 */ - Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ - DAC0_IRQn = 56, /**< DAC0 interrupt */ - MCG_IRQn = 57, /**< MCG Interrupt */ - LPTimer_IRQn = 58, /**< LPTimer interrupt */ - PORTA_IRQn = 59, /**< Port A interrupt */ - PORTB_IRQn = 60, /**< Port B interrupt */ - PORTC_IRQn = 61, /**< Port C interrupt */ - PORTD_IRQn = 62, /**< Port D interrupt */ - PORTE_IRQn = 63, /**< Port E interrupt */ - SWI_IRQn = 64, /**< Software interrupt */ - Reserved81_IRQn = 65, /**< Reserved interrupt 81 */ - Reserved82_IRQn = 66, /**< Reserved interrupt 82 */ - Reserved83_IRQn = 67, /**< Reserved interrupt 83 */ - Reserved84_IRQn = 68, /**< Reserved interrupt 84 */ - Reserved85_IRQn = 69, /**< Reserved interrupt 85 */ - Reserved86_IRQn = 70, /**< Reserved interrupt 86 */ - FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ - DAC1_IRQn = 72, /**< DAC1 interrupt */ - ADC1_IRQn = 73, /**< ADC1 interrupt */ - Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */ - Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */ - Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */ - Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */ - Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */ - Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */ - Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */ - Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */ - Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */ - Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */ - Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */ - Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK22F51212.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_EARS_REG(base) ((base)->EARS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) -#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Register_Masks FB Register Masks - * @{ - */ - -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFA_FCNFG_REG(base) ((base)->FCNFG) -#define FTFA_FSEC_REG(base) ((base)->FSEC) -#define FTFA_FOPT_REG(base) ((base)->FOPT) -#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFA_FPROT3_REG(base) ((base)->FPROT3) -#define FTFA_FPROT2_REG(base) ((base)->FPROT2) -#define FTFA_FPROT1_REG(base) ((base)->FPROT1) -#define FTFA_FPROT0_REG(base) ((base)->FPROT0) -#define FTFA_XACCH3_REG(base) ((base)->XACCH3) -#define FTFA_XACCH2_REG(base) ((base)->XACCH2) -#define FTFA_XACCH1_REG(base) ((base)->XACCH1) -#define FTFA_XACCH0_REG(base) ((base)->XACCH0) -#define FTFA_XACCL3_REG(base) ((base)->XACCL3) -#define FTFA_XACCL2_REG(base) ((base)->XACCL2) -#define FTFA_XACCL1_REG(base) ((base)->XACCL1) -#define FTFA_XACCL0_REG(base) ((base)->XACCL0) -#define FTFA_SACCH3_REG(base) ((base)->SACCH3) -#define FTFA_SACCH2_REG(base) ((base)->SACCH2) -#define FTFA_SACCH1_REG(base) ((base)->SACCH1) -#define FTFA_SACCH0_REG(base) ((base)->SACCH0) -#define FTFA_SACCL3_REG(base) ((base)->SACCL3) -#define FTFA_SACCL2_REG(base) ((base)->SACCL2) -#define FTFA_SACCL1_REG(base) ((base)->SACCL1) -#define FTFA_SACCL0_REG(base) ((base)->SACCL0) -#define FTFA_FACSS_REG(base) ((base)->FACSS) -#define FTFA_FACSN_REG(base) ((base)->FACSN) - -/*! - * @} - */ /* end of group FTFA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTFA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFA_Register_Masks FTFA Register Masks - * @{ - */ - -/* FSTAT Bit Fields */ -#define FTFA_FSTAT_MGSTAT0_MASK 0x1u -#define FTFA_FSTAT_MGSTAT0_SHIFT 0 -#define FTFA_FSTAT_FPVIOL_MASK 0x10u -#define FTFA_FSTAT_FPVIOL_SHIFT 4 -#define FTFA_FSTAT_ACCERR_MASK 0x20u -#define FTFA_FSTAT_ACCERR_SHIFT 5 -#define FTFA_FSTAT_RDCOLERR_MASK 0x40u -#define FTFA_FSTAT_RDCOLERR_SHIFT 6 -#define FTFA_FSTAT_CCIF_MASK 0x80u -#define FTFA_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFA_FCNFG_ERSSUSP_MASK 0x10u -#define FTFA_FCNFG_ERSSUSP_SHIFT 4 -#define FTFA_FCNFG_ERSAREQ_MASK 0x20u -#define FTFA_FCNFG_ERSAREQ_SHIFT 5 -#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFA_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFA_FCNFG_CCIE_MASK 0x80u -#define FTFA_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFA_FSEC_SEC_MASK 0x3u -#define FTFA_FSEC_SEC_SHIFT 0 -#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTM_Register_Masks FTM Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<BAUD) -#define LPUART_STAT_REG(base) ((base)->STAT) -#define LPUART_CTRL_REG(base) ((base)->CTRL) -#define LPUART_DATA_REG(base) ((base)->DATA) -#define LPUART_MATCH_REG(base) ((base)->MATCH) -#define LPUART_MODIR_REG(base) ((base)->MODIR) - -/*! - * @} - */ /* end of group LPUART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/* BAUD Bit Fields */ -#define LPUART_BAUD_SBR_MASK 0x1FFFu -#define LPUART_BAUD_SBR_SHIFT 0 -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_PLACR_REG(base) ((base)->PLACR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_CPO_REG(base) ((base)->CPO) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) -#define OSC_DIV_REG(base) ((base)->DIV) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 -/* DIV Bit Fields */ -#define OSC_DIV_ERPS_MASK 0xC0u -#define OSC_DIV_ERPS_SHIFT 6 -#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PDB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Masks PDB Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) -#define RCM_SSRS0_REG(base) ((base)->SSRS0) -#define RCM_SSRS1_REG(base) ((base)->SSRS1) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFVBAT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_HA_MASK 0x2u -#define RNG_CR_HA_SHIFT 1 -#define RNG_CR_INTM_MASK 0x4u -#define RNG_CR_INTM_SHIFT 2 -#define RNG_CR_CLRI_MASK 0x8u -#define RNG_CR_CLRI_SHIFT 3 -#define RNG_CR_SLP_MASK 0x10u -#define RNG_CR_SLP_SHIFT 4 -/* SR Bit Fields */ -#define RNG_SR_SECV_MASK 0x1u -#define RNG_SR_SECV_SHIFT 0 -#define RNG_SR_LRS_MASK 0x2u -#define RNG_SR_LRS_SHIFT 1 -#define RNG_SR_ORU_MASK 0x4u -#define RNG_SR_ORU_SHIFT 2 -#define RNG_SR_ERRI_MASK 0x8u -#define RNG_SR_ERRI_SHIFT 3 -#define RNG_SR_SLP_MASK 0x10u -#define RNG_SR_SLP_SHIFT 4 -#define RNG_SR_OREG_LVL_MASK 0xFF00u -#define RNG_SR_OREG_LVL_SHIFT 8 -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SOPT8_REG(base) ((base)->SOPT8) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -#define SMC_PMPROT_AHSRUN_MASK 0x80u -#define SMC_PMPROT_AHSRUN_SHIFT 7 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816_REG(base) ((base)->WP7816) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) -#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) -#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) -#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) -#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) -#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) -#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) -#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<&HW_ADC(ADC0_BASE). */ -#define HW_ADC(x) (*(hw_adc_t *)(x)) - -#endif /* __HW_ADC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h deleted file mode 100644 index cda0b16db6a..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h +++ /dev/null @@ -1,13604 +0,0 @@ -/* - * Copyright (c) 2013, Freescale Semiconductor, Inc. - * All rights reserved. - * - * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - */ -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_AIPS_REGISTERS_H__ -#define __HW_AIPS_REGISTERS_H__ - -#include "regs.h" - -/* - * MK22F51212 AIPS - * - * AIPS-Lite Bridge - * - * Registers defined in this header file: - * - HW_AIPS_MPRA - Master Privilege Register A - * - HW_AIPS_PACRA - Peripheral Access Control Register - * - HW_AIPS_PACRB - Peripheral Access Control Register - * - HW_AIPS_PACRC - Peripheral Access Control Register - * - HW_AIPS_PACRD - Peripheral Access Control Register - * - HW_AIPS_PACRE - Peripheral Access Control Register - * - HW_AIPS_PACRF - Peripheral Access Control Register - * - HW_AIPS_PACRG - Peripheral Access Control Register - * - HW_AIPS_PACRH - Peripheral Access Control Register - * - HW_AIPS_PACRI - Peripheral Access Control Register - * - HW_AIPS_PACRJ - Peripheral Access Control Register - * - HW_AIPS_PACRK - Peripheral Access Control Register - * - HW_AIPS_PACRL - Peripheral Access Control Register - * - HW_AIPS_PACRM - Peripheral Access Control Register - * - HW_AIPS_PACRN - Peripheral Access Control Register - * - HW_AIPS_PACRO - Peripheral Access Control Register - * - HW_AIPS_PACRP - Peripheral Access Control Register - * - HW_AIPS_PACRU - Peripheral Access Control Register - * - * - hw_aips_t - Struct containing all module registers. - */ - -//! @name Module base addresses -//@{ -#ifndef REGS_AIPS_BASE -#define HW_AIPS_INSTANCE_COUNT (1U) //!< Number of instances of the AIPS module. -#define HW_AIPS0 (0U) //!< Instance number for AIPS0. -#define REGS_AIPS0_BASE (0x40000000U) //!< Base address for AIPS0. - -//! @brief Table of base addresses for AIPS instances. -static const uint32_t __g_regs_AIPS_base_addresses[] = { - REGS_AIPS0_BASE, - }; - -//! @brief Get the base address of AIPS by instance number. -//! @param x AIPS instance number, from 0 through 0. -#define REGS_AIPS_BASE(x) (__g_regs_AIPS_base_addresses[(x)]) - -//! @brief Get the instance number given a base address. -//! @param b Base address for an instance of AIPS. -#define REGS_AIPS_INSTANCE(b) ((b) == REGS_AIPS0_BASE ? HW_AIPS0 : 0) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_MPRA - Master Privilege Register A -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_MPRA - Master Privilege Register A (RW) - * - * Reset value: 0x00000000U - * - * The MPRA specifies identical 4-bit fields defining the access-privilege level - * associated with a bus master to various peripherals on the chip. The register - * provides one field per bus master. At reset, the default value loaded into - * the MPRA fields is chip-specific. See the chip configuration details for the - * value of a particular device. A register field that maps to an unimplemented - * master or peripheral behaves as read-only-zero. Each master is assigned a logical - * ID from 0 to 15. See the master logical ID assignement table in the AIPS - * chip-specific information. - */ -typedef union _hw_aips_mpra -{ - uint32_t U; - struct _hw_aips_mpra_bitfields - { - uint32_t RESERVED0 : 32; //!< [31:0] - } B; -} hw_aips_mpra_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_MPRA register - */ -//@{ -#define HW_AIPS_MPRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x0U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x)) -#define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U) -#define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v)) -#define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v))) -#define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v))) -#define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_MPRA bitfields - */ - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRA - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral's PACR field in - * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 - * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 - * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 - * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 - * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 - * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 - * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 - * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 - * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 - * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 - * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 - * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C - * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, - * which control peripheral slots 0 - 31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacra -{ - uint32_t U; - struct _hw_aips_pacra_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write protect - uint32_t SP4 : 1; //!< [14] Supervisor Protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted protect - uint32_t WP3 : 1; //!< [17] Write Protect - uint32_t SP3 : 1; //!< [18] Supervisor protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted Protect - uint32_t WP2 : 1; //!< [21] Write protect - uint32_t SP2 : 1; //!< [22] Supervisor Protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted Protect - uint32_t WP0 : 1; //!< [29] Write protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacra_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRA register - */ -//@{ -#define HW_AIPS_PACRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x20U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x)) -#define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U) -#define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v)) -#define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v))) -#define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v))) -#define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRA bitfields - */ - -/*! - * @name Register AIPS_PACRA, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP7 (0U) //!< Bit position for AIPS_PACRA_TP7. -#define BM_AIPS_PACRA_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRA_TP7. -#define BS_AIPS_PACRA_TP7 (1U) //!< Bit field size in bits for AIPS_PACRA_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP7 field. -#define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP7. -#define BF_AIPS_PACRA_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP7), uint32_t) & BM_AIPS_PACRA_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP7 (1U) //!< Bit position for AIPS_PACRA_WP7. -#define BM_AIPS_PACRA_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRA_WP7. -#define BS_AIPS_PACRA_WP7 (1U) //!< Bit field size in bits for AIPS_PACRA_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP7 field. -#define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP7. -#define BF_AIPS_PACRA_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP7), uint32_t) & BM_AIPS_PACRA_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP7 (2U) //!< Bit position for AIPS_PACRA_SP7. -#define BM_AIPS_PACRA_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRA_SP7. -#define BS_AIPS_PACRA_SP7 (1U) //!< Bit field size in bits for AIPS_PACRA_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP7 field. -#define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP7. -#define BF_AIPS_PACRA_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP7), uint32_t) & BM_AIPS_PACRA_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP6 (4U) //!< Bit position for AIPS_PACRA_TP6. -#define BM_AIPS_PACRA_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRA_TP6. -#define BS_AIPS_PACRA_TP6 (1U) //!< Bit field size in bits for AIPS_PACRA_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP6 field. -#define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP6. -#define BF_AIPS_PACRA_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP6), uint32_t) & BM_AIPS_PACRA_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP6 (5U) //!< Bit position for AIPS_PACRA_WP6. -#define BM_AIPS_PACRA_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRA_WP6. -#define BS_AIPS_PACRA_WP6 (1U) //!< Bit field size in bits for AIPS_PACRA_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP6 field. -#define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP6. -#define BF_AIPS_PACRA_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP6), uint32_t) & BM_AIPS_PACRA_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP6 (6U) //!< Bit position for AIPS_PACRA_SP6. -#define BM_AIPS_PACRA_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRA_SP6. -#define BS_AIPS_PACRA_SP6 (1U) //!< Bit field size in bits for AIPS_PACRA_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP6 field. -#define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP6. -#define BF_AIPS_PACRA_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP6), uint32_t) & BM_AIPS_PACRA_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP5 (8U) //!< Bit position for AIPS_PACRA_TP5. -#define BM_AIPS_PACRA_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRA_TP5. -#define BS_AIPS_PACRA_TP5 (1U) //!< Bit field size in bits for AIPS_PACRA_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP5 field. -#define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP5. -#define BF_AIPS_PACRA_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP5), uint32_t) & BM_AIPS_PACRA_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP5 (9U) //!< Bit position for AIPS_PACRA_WP5. -#define BM_AIPS_PACRA_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRA_WP5. -#define BS_AIPS_PACRA_WP5 (1U) //!< Bit field size in bits for AIPS_PACRA_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP5 field. -#define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP5. -#define BF_AIPS_PACRA_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP5), uint32_t) & BM_AIPS_PACRA_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP5 (10U) //!< Bit position for AIPS_PACRA_SP5. -#define BM_AIPS_PACRA_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRA_SP5. -#define BS_AIPS_PACRA_SP5 (1U) //!< Bit field size in bits for AIPS_PACRA_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP5 field. -#define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP5. -#define BF_AIPS_PACRA_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP5), uint32_t) & BM_AIPS_PACRA_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP4 (12U) //!< Bit position for AIPS_PACRA_TP4. -#define BM_AIPS_PACRA_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRA_TP4. -#define BS_AIPS_PACRA_TP4 (1U) //!< Bit field size in bits for AIPS_PACRA_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP4 field. -#define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP4. -#define BF_AIPS_PACRA_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP4), uint32_t) & BM_AIPS_PACRA_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP4 (13U) //!< Bit position for AIPS_PACRA_WP4. -#define BM_AIPS_PACRA_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRA_WP4. -#define BS_AIPS_PACRA_WP4 (1U) //!< Bit field size in bits for AIPS_PACRA_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP4 field. -#define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP4. -#define BF_AIPS_PACRA_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP4), uint32_t) & BM_AIPS_PACRA_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP4 (14U) //!< Bit position for AIPS_PACRA_SP4. -#define BM_AIPS_PACRA_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRA_SP4. -#define BS_AIPS_PACRA_SP4 (1U) //!< Bit field size in bits for AIPS_PACRA_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP4 field. -#define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP4. -#define BF_AIPS_PACRA_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP4), uint32_t) & BM_AIPS_PACRA_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP3 (16U) //!< Bit position for AIPS_PACRA_TP3. -#define BM_AIPS_PACRA_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRA_TP3. -#define BS_AIPS_PACRA_TP3 (1U) //!< Bit field size in bits for AIPS_PACRA_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP3 field. -#define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP3. -#define BF_AIPS_PACRA_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP3), uint32_t) & BM_AIPS_PACRA_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP3 (17U) //!< Bit position for AIPS_PACRA_WP3. -#define BM_AIPS_PACRA_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRA_WP3. -#define BS_AIPS_PACRA_WP3 (1U) //!< Bit field size in bits for AIPS_PACRA_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP3 field. -#define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP3. -#define BF_AIPS_PACRA_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP3), uint32_t) & BM_AIPS_PACRA_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP3 (18U) //!< Bit position for AIPS_PACRA_SP3. -#define BM_AIPS_PACRA_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRA_SP3. -#define BS_AIPS_PACRA_SP3 (1U) //!< Bit field size in bits for AIPS_PACRA_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP3 field. -#define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP3. -#define BF_AIPS_PACRA_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP3), uint32_t) & BM_AIPS_PACRA_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP2 (20U) //!< Bit position for AIPS_PACRA_TP2. -#define BM_AIPS_PACRA_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRA_TP2. -#define BS_AIPS_PACRA_TP2 (1U) //!< Bit field size in bits for AIPS_PACRA_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP2 field. -#define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP2. -#define BF_AIPS_PACRA_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP2), uint32_t) & BM_AIPS_PACRA_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP2 (21U) //!< Bit position for AIPS_PACRA_WP2. -#define BM_AIPS_PACRA_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRA_WP2. -#define BS_AIPS_PACRA_WP2 (1U) //!< Bit field size in bits for AIPS_PACRA_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP2 field. -#define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP2. -#define BF_AIPS_PACRA_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP2), uint32_t) & BM_AIPS_PACRA_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP2 (22U) //!< Bit position for AIPS_PACRA_SP2. -#define BM_AIPS_PACRA_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRA_SP2. -#define BS_AIPS_PACRA_SP2 (1U) //!< Bit field size in bits for AIPS_PACRA_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP2 field. -#define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP2. -#define BF_AIPS_PACRA_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP2), uint32_t) & BM_AIPS_PACRA_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP1 (24U) //!< Bit position for AIPS_PACRA_TP1. -#define BM_AIPS_PACRA_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRA_TP1. -#define BS_AIPS_PACRA_TP1 (1U) //!< Bit field size in bits for AIPS_PACRA_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP1 field. -#define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP1. -#define BF_AIPS_PACRA_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP1), uint32_t) & BM_AIPS_PACRA_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP1 (25U) //!< Bit position for AIPS_PACRA_WP1. -#define BM_AIPS_PACRA_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRA_WP1. -#define BS_AIPS_PACRA_WP1 (1U) //!< Bit field size in bits for AIPS_PACRA_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP1 field. -#define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP1. -#define BF_AIPS_PACRA_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP1), uint32_t) & BM_AIPS_PACRA_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP1 (26U) //!< Bit position for AIPS_PACRA_SP1. -#define BM_AIPS_PACRA_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRA_SP1. -#define BS_AIPS_PACRA_SP1 (1U) //!< Bit field size in bits for AIPS_PACRA_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP1 field. -#define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP1. -#define BF_AIPS_PACRA_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP1), uint32_t) & BM_AIPS_PACRA_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRA_TP0 (28U) //!< Bit position for AIPS_PACRA_TP0. -#define BM_AIPS_PACRA_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRA_TP0. -#define BS_AIPS_PACRA_TP0 (1U) //!< Bit field size in bits for AIPS_PACRA_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_TP0 field. -#define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_TP0. -#define BF_AIPS_PACRA_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP0), uint32_t) & BM_AIPS_PACRA_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRA_WP0 (29U) //!< Bit position for AIPS_PACRA_WP0. -#define BM_AIPS_PACRA_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRA_WP0. -#define BS_AIPS_PACRA_WP0 (1U) //!< Bit field size in bits for AIPS_PACRA_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_WP0 field. -#define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_WP0. -#define BF_AIPS_PACRA_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP0), uint32_t) & BM_AIPS_PACRA_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRA, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRA_SP0 (30U) //!< Bit position for AIPS_PACRA_SP0. -#define BM_AIPS_PACRA_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRA_SP0. -#define BS_AIPS_PACRA_SP0 (1U) //!< Bit field size in bits for AIPS_PACRA_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRA_SP0 field. -#define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRA_SP0. -#define BF_AIPS_PACRA_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP0), uint32_t) & BM_AIPS_PACRA_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRB - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral's PACR field in - * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 - * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 - * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 - * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 - * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 - * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 - * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 - * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 - * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 - * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 - * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 - * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C - * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, - * which control peripheral slots 0 - 31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacrb -{ - uint32_t U; - struct _hw_aips_pacrb_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write protect - uint32_t SP4 : 1; //!< [14] Supervisor Protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted protect - uint32_t WP3 : 1; //!< [17] Write Protect - uint32_t SP3 : 1; //!< [18] Supervisor protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted Protect - uint32_t WP2 : 1; //!< [21] Write protect - uint32_t SP2 : 1; //!< [22] Supervisor Protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted Protect - uint32_t WP0 : 1; //!< [29] Write protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrb_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRB register - */ -//@{ -#define HW_AIPS_PACRB_ADDR(x) (REGS_AIPS_BASE(x) + 0x24U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x)) -#define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U) -#define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v)) -#define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v))) -#define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v))) -#define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRB bitfields - */ - -/*! - * @name Register AIPS_PACRB, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP7 (0U) //!< Bit position for AIPS_PACRB_TP7. -#define BM_AIPS_PACRB_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRB_TP7. -#define BS_AIPS_PACRB_TP7 (1U) //!< Bit field size in bits for AIPS_PACRB_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP7 field. -#define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP7. -#define BF_AIPS_PACRB_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP7), uint32_t) & BM_AIPS_PACRB_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP7 (1U) //!< Bit position for AIPS_PACRB_WP7. -#define BM_AIPS_PACRB_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRB_WP7. -#define BS_AIPS_PACRB_WP7 (1U) //!< Bit field size in bits for AIPS_PACRB_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP7 field. -#define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP7. -#define BF_AIPS_PACRB_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP7), uint32_t) & BM_AIPS_PACRB_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP7 (2U) //!< Bit position for AIPS_PACRB_SP7. -#define BM_AIPS_PACRB_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRB_SP7. -#define BS_AIPS_PACRB_SP7 (1U) //!< Bit field size in bits for AIPS_PACRB_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP7 field. -#define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP7. -#define BF_AIPS_PACRB_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP7), uint32_t) & BM_AIPS_PACRB_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP6 (4U) //!< Bit position for AIPS_PACRB_TP6. -#define BM_AIPS_PACRB_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRB_TP6. -#define BS_AIPS_PACRB_TP6 (1U) //!< Bit field size in bits for AIPS_PACRB_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP6 field. -#define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP6. -#define BF_AIPS_PACRB_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP6), uint32_t) & BM_AIPS_PACRB_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP6 (5U) //!< Bit position for AIPS_PACRB_WP6. -#define BM_AIPS_PACRB_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRB_WP6. -#define BS_AIPS_PACRB_WP6 (1U) //!< Bit field size in bits for AIPS_PACRB_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP6 field. -#define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP6. -#define BF_AIPS_PACRB_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP6), uint32_t) & BM_AIPS_PACRB_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP6 (6U) //!< Bit position for AIPS_PACRB_SP6. -#define BM_AIPS_PACRB_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRB_SP6. -#define BS_AIPS_PACRB_SP6 (1U) //!< Bit field size in bits for AIPS_PACRB_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP6 field. -#define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP6. -#define BF_AIPS_PACRB_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP6), uint32_t) & BM_AIPS_PACRB_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP5 (8U) //!< Bit position for AIPS_PACRB_TP5. -#define BM_AIPS_PACRB_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRB_TP5. -#define BS_AIPS_PACRB_TP5 (1U) //!< Bit field size in bits for AIPS_PACRB_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP5 field. -#define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP5. -#define BF_AIPS_PACRB_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP5), uint32_t) & BM_AIPS_PACRB_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP5 (9U) //!< Bit position for AIPS_PACRB_WP5. -#define BM_AIPS_PACRB_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRB_WP5. -#define BS_AIPS_PACRB_WP5 (1U) //!< Bit field size in bits for AIPS_PACRB_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP5 field. -#define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP5. -#define BF_AIPS_PACRB_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP5), uint32_t) & BM_AIPS_PACRB_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP5 (10U) //!< Bit position for AIPS_PACRB_SP5. -#define BM_AIPS_PACRB_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRB_SP5. -#define BS_AIPS_PACRB_SP5 (1U) //!< Bit field size in bits for AIPS_PACRB_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP5 field. -#define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP5. -#define BF_AIPS_PACRB_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP5), uint32_t) & BM_AIPS_PACRB_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP4 (12U) //!< Bit position for AIPS_PACRB_TP4. -#define BM_AIPS_PACRB_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRB_TP4. -#define BS_AIPS_PACRB_TP4 (1U) //!< Bit field size in bits for AIPS_PACRB_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP4 field. -#define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP4. -#define BF_AIPS_PACRB_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP4), uint32_t) & BM_AIPS_PACRB_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP4 (13U) //!< Bit position for AIPS_PACRB_WP4. -#define BM_AIPS_PACRB_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRB_WP4. -#define BS_AIPS_PACRB_WP4 (1U) //!< Bit field size in bits for AIPS_PACRB_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP4 field. -#define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP4. -#define BF_AIPS_PACRB_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP4), uint32_t) & BM_AIPS_PACRB_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP4 (14U) //!< Bit position for AIPS_PACRB_SP4. -#define BM_AIPS_PACRB_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRB_SP4. -#define BS_AIPS_PACRB_SP4 (1U) //!< Bit field size in bits for AIPS_PACRB_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP4 field. -#define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP4. -#define BF_AIPS_PACRB_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP4), uint32_t) & BM_AIPS_PACRB_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP3 (16U) //!< Bit position for AIPS_PACRB_TP3. -#define BM_AIPS_PACRB_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRB_TP3. -#define BS_AIPS_PACRB_TP3 (1U) //!< Bit field size in bits for AIPS_PACRB_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP3 field. -#define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP3. -#define BF_AIPS_PACRB_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP3), uint32_t) & BM_AIPS_PACRB_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP3 (17U) //!< Bit position for AIPS_PACRB_WP3. -#define BM_AIPS_PACRB_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRB_WP3. -#define BS_AIPS_PACRB_WP3 (1U) //!< Bit field size in bits for AIPS_PACRB_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP3 field. -#define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP3. -#define BF_AIPS_PACRB_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP3), uint32_t) & BM_AIPS_PACRB_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP3 (18U) //!< Bit position for AIPS_PACRB_SP3. -#define BM_AIPS_PACRB_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRB_SP3. -#define BS_AIPS_PACRB_SP3 (1U) //!< Bit field size in bits for AIPS_PACRB_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP3 field. -#define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP3. -#define BF_AIPS_PACRB_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP3), uint32_t) & BM_AIPS_PACRB_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP2 (20U) //!< Bit position for AIPS_PACRB_TP2. -#define BM_AIPS_PACRB_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRB_TP2. -#define BS_AIPS_PACRB_TP2 (1U) //!< Bit field size in bits for AIPS_PACRB_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP2 field. -#define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP2. -#define BF_AIPS_PACRB_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP2), uint32_t) & BM_AIPS_PACRB_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP2 (21U) //!< Bit position for AIPS_PACRB_WP2. -#define BM_AIPS_PACRB_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRB_WP2. -#define BS_AIPS_PACRB_WP2 (1U) //!< Bit field size in bits for AIPS_PACRB_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP2 field. -#define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP2. -#define BF_AIPS_PACRB_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP2), uint32_t) & BM_AIPS_PACRB_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP2 (22U) //!< Bit position for AIPS_PACRB_SP2. -#define BM_AIPS_PACRB_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRB_SP2. -#define BS_AIPS_PACRB_SP2 (1U) //!< Bit field size in bits for AIPS_PACRB_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP2 field. -#define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP2. -#define BF_AIPS_PACRB_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP2), uint32_t) & BM_AIPS_PACRB_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP1 (24U) //!< Bit position for AIPS_PACRB_TP1. -#define BM_AIPS_PACRB_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRB_TP1. -#define BS_AIPS_PACRB_TP1 (1U) //!< Bit field size in bits for AIPS_PACRB_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP1 field. -#define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP1. -#define BF_AIPS_PACRB_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP1), uint32_t) & BM_AIPS_PACRB_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP1 (25U) //!< Bit position for AIPS_PACRB_WP1. -#define BM_AIPS_PACRB_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRB_WP1. -#define BS_AIPS_PACRB_WP1 (1U) //!< Bit field size in bits for AIPS_PACRB_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP1 field. -#define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP1. -#define BF_AIPS_PACRB_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP1), uint32_t) & BM_AIPS_PACRB_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP1 (26U) //!< Bit position for AIPS_PACRB_SP1. -#define BM_AIPS_PACRB_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRB_SP1. -#define BS_AIPS_PACRB_SP1 (1U) //!< Bit field size in bits for AIPS_PACRB_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP1 field. -#define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP1. -#define BF_AIPS_PACRB_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP1), uint32_t) & BM_AIPS_PACRB_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRB_TP0 (28U) //!< Bit position for AIPS_PACRB_TP0. -#define BM_AIPS_PACRB_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRB_TP0. -#define BS_AIPS_PACRB_TP0 (1U) //!< Bit field size in bits for AIPS_PACRB_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_TP0 field. -#define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_TP0. -#define BF_AIPS_PACRB_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP0), uint32_t) & BM_AIPS_PACRB_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRB_WP0 (29U) //!< Bit position for AIPS_PACRB_WP0. -#define BM_AIPS_PACRB_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRB_WP0. -#define BS_AIPS_PACRB_WP0 (1U) //!< Bit field size in bits for AIPS_PACRB_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_WP0 field. -#define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_WP0. -#define BF_AIPS_PACRB_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP0), uint32_t) & BM_AIPS_PACRB_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRB, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRB_SP0 (30U) //!< Bit position for AIPS_PACRB_SP0. -#define BM_AIPS_PACRB_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRB_SP0. -#define BS_AIPS_PACRB_SP0 (1U) //!< Bit field size in bits for AIPS_PACRB_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRB_SP0 field. -#define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRB_SP0. -#define BF_AIPS_PACRB_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP0), uint32_t) & BM_AIPS_PACRB_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRC - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral's PACR field in - * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 - * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 - * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 - * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 - * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 - * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 - * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 - * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 - * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 - * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 - * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 - * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C - * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, - * which control peripheral slots 0 - 31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacrc -{ - uint32_t U; - struct _hw_aips_pacrc_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write protect - uint32_t SP4 : 1; //!< [14] Supervisor Protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted protect - uint32_t WP3 : 1; //!< [17] Write Protect - uint32_t SP3 : 1; //!< [18] Supervisor protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted Protect - uint32_t WP2 : 1; //!< [21] Write protect - uint32_t SP2 : 1; //!< [22] Supervisor Protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted Protect - uint32_t WP0 : 1; //!< [29] Write protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrc_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRC register - */ -//@{ -#define HW_AIPS_PACRC_ADDR(x) (REGS_AIPS_BASE(x) + 0x28U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x)) -#define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U) -#define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v)) -#define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v))) -#define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v))) -#define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRC bitfields - */ - -/*! - * @name Register AIPS_PACRC, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP7 (0U) //!< Bit position for AIPS_PACRC_TP7. -#define BM_AIPS_PACRC_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRC_TP7. -#define BS_AIPS_PACRC_TP7 (1U) //!< Bit field size in bits for AIPS_PACRC_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP7 field. -#define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP7. -#define BF_AIPS_PACRC_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP7), uint32_t) & BM_AIPS_PACRC_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP7 (1U) //!< Bit position for AIPS_PACRC_WP7. -#define BM_AIPS_PACRC_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRC_WP7. -#define BS_AIPS_PACRC_WP7 (1U) //!< Bit field size in bits for AIPS_PACRC_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP7 field. -#define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP7. -#define BF_AIPS_PACRC_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP7), uint32_t) & BM_AIPS_PACRC_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP7 (2U) //!< Bit position for AIPS_PACRC_SP7. -#define BM_AIPS_PACRC_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRC_SP7. -#define BS_AIPS_PACRC_SP7 (1U) //!< Bit field size in bits for AIPS_PACRC_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP7 field. -#define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP7. -#define BF_AIPS_PACRC_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP7), uint32_t) & BM_AIPS_PACRC_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP6 (4U) //!< Bit position for AIPS_PACRC_TP6. -#define BM_AIPS_PACRC_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRC_TP6. -#define BS_AIPS_PACRC_TP6 (1U) //!< Bit field size in bits for AIPS_PACRC_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP6 field. -#define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP6. -#define BF_AIPS_PACRC_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP6), uint32_t) & BM_AIPS_PACRC_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP6 (5U) //!< Bit position for AIPS_PACRC_WP6. -#define BM_AIPS_PACRC_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRC_WP6. -#define BS_AIPS_PACRC_WP6 (1U) //!< Bit field size in bits for AIPS_PACRC_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP6 field. -#define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP6. -#define BF_AIPS_PACRC_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP6), uint32_t) & BM_AIPS_PACRC_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP6 (6U) //!< Bit position for AIPS_PACRC_SP6. -#define BM_AIPS_PACRC_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRC_SP6. -#define BS_AIPS_PACRC_SP6 (1U) //!< Bit field size in bits for AIPS_PACRC_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP6 field. -#define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP6. -#define BF_AIPS_PACRC_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP6), uint32_t) & BM_AIPS_PACRC_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP5 (8U) //!< Bit position for AIPS_PACRC_TP5. -#define BM_AIPS_PACRC_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRC_TP5. -#define BS_AIPS_PACRC_TP5 (1U) //!< Bit field size in bits for AIPS_PACRC_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP5 field. -#define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP5. -#define BF_AIPS_PACRC_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP5), uint32_t) & BM_AIPS_PACRC_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP5 (9U) //!< Bit position for AIPS_PACRC_WP5. -#define BM_AIPS_PACRC_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRC_WP5. -#define BS_AIPS_PACRC_WP5 (1U) //!< Bit field size in bits for AIPS_PACRC_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP5 field. -#define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP5. -#define BF_AIPS_PACRC_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP5), uint32_t) & BM_AIPS_PACRC_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP5 (10U) //!< Bit position for AIPS_PACRC_SP5. -#define BM_AIPS_PACRC_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRC_SP5. -#define BS_AIPS_PACRC_SP5 (1U) //!< Bit field size in bits for AIPS_PACRC_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP5 field. -#define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP5. -#define BF_AIPS_PACRC_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP5), uint32_t) & BM_AIPS_PACRC_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP4 (12U) //!< Bit position for AIPS_PACRC_TP4. -#define BM_AIPS_PACRC_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRC_TP4. -#define BS_AIPS_PACRC_TP4 (1U) //!< Bit field size in bits for AIPS_PACRC_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP4 field. -#define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP4. -#define BF_AIPS_PACRC_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP4), uint32_t) & BM_AIPS_PACRC_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP4 (13U) //!< Bit position for AIPS_PACRC_WP4. -#define BM_AIPS_PACRC_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRC_WP4. -#define BS_AIPS_PACRC_WP4 (1U) //!< Bit field size in bits for AIPS_PACRC_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP4 field. -#define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP4. -#define BF_AIPS_PACRC_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP4), uint32_t) & BM_AIPS_PACRC_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP4 (14U) //!< Bit position for AIPS_PACRC_SP4. -#define BM_AIPS_PACRC_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRC_SP4. -#define BS_AIPS_PACRC_SP4 (1U) //!< Bit field size in bits for AIPS_PACRC_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP4 field. -#define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP4. -#define BF_AIPS_PACRC_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP4), uint32_t) & BM_AIPS_PACRC_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP3 (16U) //!< Bit position for AIPS_PACRC_TP3. -#define BM_AIPS_PACRC_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRC_TP3. -#define BS_AIPS_PACRC_TP3 (1U) //!< Bit field size in bits for AIPS_PACRC_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP3 field. -#define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP3. -#define BF_AIPS_PACRC_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP3), uint32_t) & BM_AIPS_PACRC_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP3 (17U) //!< Bit position for AIPS_PACRC_WP3. -#define BM_AIPS_PACRC_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRC_WP3. -#define BS_AIPS_PACRC_WP3 (1U) //!< Bit field size in bits for AIPS_PACRC_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP3 field. -#define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP3. -#define BF_AIPS_PACRC_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP3), uint32_t) & BM_AIPS_PACRC_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP3 (18U) //!< Bit position for AIPS_PACRC_SP3. -#define BM_AIPS_PACRC_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRC_SP3. -#define BS_AIPS_PACRC_SP3 (1U) //!< Bit field size in bits for AIPS_PACRC_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP3 field. -#define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP3. -#define BF_AIPS_PACRC_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP3), uint32_t) & BM_AIPS_PACRC_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP2 (20U) //!< Bit position for AIPS_PACRC_TP2. -#define BM_AIPS_PACRC_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRC_TP2. -#define BS_AIPS_PACRC_TP2 (1U) //!< Bit field size in bits for AIPS_PACRC_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP2 field. -#define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP2. -#define BF_AIPS_PACRC_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP2), uint32_t) & BM_AIPS_PACRC_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP2 (21U) //!< Bit position for AIPS_PACRC_WP2. -#define BM_AIPS_PACRC_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRC_WP2. -#define BS_AIPS_PACRC_WP2 (1U) //!< Bit field size in bits for AIPS_PACRC_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP2 field. -#define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP2. -#define BF_AIPS_PACRC_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP2), uint32_t) & BM_AIPS_PACRC_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP2 (22U) //!< Bit position for AIPS_PACRC_SP2. -#define BM_AIPS_PACRC_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRC_SP2. -#define BS_AIPS_PACRC_SP2 (1U) //!< Bit field size in bits for AIPS_PACRC_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP2 field. -#define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP2. -#define BF_AIPS_PACRC_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP2), uint32_t) & BM_AIPS_PACRC_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP1 (24U) //!< Bit position for AIPS_PACRC_TP1. -#define BM_AIPS_PACRC_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRC_TP1. -#define BS_AIPS_PACRC_TP1 (1U) //!< Bit field size in bits for AIPS_PACRC_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP1 field. -#define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP1. -#define BF_AIPS_PACRC_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP1), uint32_t) & BM_AIPS_PACRC_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP1 (25U) //!< Bit position for AIPS_PACRC_WP1. -#define BM_AIPS_PACRC_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRC_WP1. -#define BS_AIPS_PACRC_WP1 (1U) //!< Bit field size in bits for AIPS_PACRC_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP1 field. -#define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP1. -#define BF_AIPS_PACRC_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP1), uint32_t) & BM_AIPS_PACRC_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP1 (26U) //!< Bit position for AIPS_PACRC_SP1. -#define BM_AIPS_PACRC_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRC_SP1. -#define BS_AIPS_PACRC_SP1 (1U) //!< Bit field size in bits for AIPS_PACRC_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP1 field. -#define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP1. -#define BF_AIPS_PACRC_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP1), uint32_t) & BM_AIPS_PACRC_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRC_TP0 (28U) //!< Bit position for AIPS_PACRC_TP0. -#define BM_AIPS_PACRC_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRC_TP0. -#define BS_AIPS_PACRC_TP0 (1U) //!< Bit field size in bits for AIPS_PACRC_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_TP0 field. -#define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_TP0. -#define BF_AIPS_PACRC_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP0), uint32_t) & BM_AIPS_PACRC_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRC_WP0 (29U) //!< Bit position for AIPS_PACRC_WP0. -#define BM_AIPS_PACRC_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRC_WP0. -#define BS_AIPS_PACRC_WP0 (1U) //!< Bit field size in bits for AIPS_PACRC_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_WP0 field. -#define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_WP0. -#define BF_AIPS_PACRC_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP0), uint32_t) & BM_AIPS_PACRC_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRC, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRC_SP0 (30U) //!< Bit position for AIPS_PACRC_SP0. -#define BM_AIPS_PACRC_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRC_SP0. -#define BS_AIPS_PACRC_SP0 (1U) //!< Bit field size in bits for AIPS_PACRC_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRC_SP0 field. -#define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRC_SP0. -#define BF_AIPS_PACRC_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP0), uint32_t) & BM_AIPS_PACRC_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRD - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral's PACR field in - * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 - * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 - * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 - * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 - * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 - * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 - * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 - * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 - * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 - * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 - * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 - * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C - * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, - * which control peripheral slots 0 - 31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacrd -{ - uint32_t U; - struct _hw_aips_pacrd_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write protect - uint32_t SP4 : 1; //!< [14] Supervisor Protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted protect - uint32_t WP3 : 1; //!< [17] Write Protect - uint32_t SP3 : 1; //!< [18] Supervisor protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted Protect - uint32_t WP2 : 1; //!< [21] Write protect - uint32_t SP2 : 1; //!< [22] Supervisor Protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted Protect - uint32_t WP0 : 1; //!< [29] Write protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrd_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRD register - */ -//@{ -#define HW_AIPS_PACRD_ADDR(x) (REGS_AIPS_BASE(x) + 0x2CU) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x)) -#define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U) -#define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v)) -#define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v))) -#define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v))) -#define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRD bitfields - */ - -/*! - * @name Register AIPS_PACRD, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP7 (0U) //!< Bit position for AIPS_PACRD_TP7. -#define BM_AIPS_PACRD_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRD_TP7. -#define BS_AIPS_PACRD_TP7 (1U) //!< Bit field size in bits for AIPS_PACRD_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP7 field. -#define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP7. -#define BF_AIPS_PACRD_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP7), uint32_t) & BM_AIPS_PACRD_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP7 (1U) //!< Bit position for AIPS_PACRD_WP7. -#define BM_AIPS_PACRD_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRD_WP7. -#define BS_AIPS_PACRD_WP7 (1U) //!< Bit field size in bits for AIPS_PACRD_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP7 field. -#define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP7. -#define BF_AIPS_PACRD_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP7), uint32_t) & BM_AIPS_PACRD_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP7 (2U) //!< Bit position for AIPS_PACRD_SP7. -#define BM_AIPS_PACRD_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRD_SP7. -#define BS_AIPS_PACRD_SP7 (1U) //!< Bit field size in bits for AIPS_PACRD_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP7 field. -#define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP7. -#define BF_AIPS_PACRD_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP7), uint32_t) & BM_AIPS_PACRD_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP6 (4U) //!< Bit position for AIPS_PACRD_TP6. -#define BM_AIPS_PACRD_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRD_TP6. -#define BS_AIPS_PACRD_TP6 (1U) //!< Bit field size in bits for AIPS_PACRD_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP6 field. -#define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP6. -#define BF_AIPS_PACRD_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP6), uint32_t) & BM_AIPS_PACRD_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP6 (5U) //!< Bit position for AIPS_PACRD_WP6. -#define BM_AIPS_PACRD_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRD_WP6. -#define BS_AIPS_PACRD_WP6 (1U) //!< Bit field size in bits for AIPS_PACRD_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP6 field. -#define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP6. -#define BF_AIPS_PACRD_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP6), uint32_t) & BM_AIPS_PACRD_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP6 (6U) //!< Bit position for AIPS_PACRD_SP6. -#define BM_AIPS_PACRD_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRD_SP6. -#define BS_AIPS_PACRD_SP6 (1U) //!< Bit field size in bits for AIPS_PACRD_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP6 field. -#define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP6. -#define BF_AIPS_PACRD_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP6), uint32_t) & BM_AIPS_PACRD_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP5 (8U) //!< Bit position for AIPS_PACRD_TP5. -#define BM_AIPS_PACRD_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRD_TP5. -#define BS_AIPS_PACRD_TP5 (1U) //!< Bit field size in bits for AIPS_PACRD_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP5 field. -#define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP5. -#define BF_AIPS_PACRD_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP5), uint32_t) & BM_AIPS_PACRD_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP5 (9U) //!< Bit position for AIPS_PACRD_WP5. -#define BM_AIPS_PACRD_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRD_WP5. -#define BS_AIPS_PACRD_WP5 (1U) //!< Bit field size in bits for AIPS_PACRD_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP5 field. -#define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP5. -#define BF_AIPS_PACRD_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP5), uint32_t) & BM_AIPS_PACRD_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP5 (10U) //!< Bit position for AIPS_PACRD_SP5. -#define BM_AIPS_PACRD_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRD_SP5. -#define BS_AIPS_PACRD_SP5 (1U) //!< Bit field size in bits for AIPS_PACRD_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP5 field. -#define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP5. -#define BF_AIPS_PACRD_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP5), uint32_t) & BM_AIPS_PACRD_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP4 (12U) //!< Bit position for AIPS_PACRD_TP4. -#define BM_AIPS_PACRD_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRD_TP4. -#define BS_AIPS_PACRD_TP4 (1U) //!< Bit field size in bits for AIPS_PACRD_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP4 field. -#define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP4. -#define BF_AIPS_PACRD_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP4), uint32_t) & BM_AIPS_PACRD_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP4 (13U) //!< Bit position for AIPS_PACRD_WP4. -#define BM_AIPS_PACRD_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRD_WP4. -#define BS_AIPS_PACRD_WP4 (1U) //!< Bit field size in bits for AIPS_PACRD_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP4 field. -#define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP4. -#define BF_AIPS_PACRD_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP4), uint32_t) & BM_AIPS_PACRD_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP4 (14U) //!< Bit position for AIPS_PACRD_SP4. -#define BM_AIPS_PACRD_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRD_SP4. -#define BS_AIPS_PACRD_SP4 (1U) //!< Bit field size in bits for AIPS_PACRD_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP4 field. -#define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP4. -#define BF_AIPS_PACRD_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP4), uint32_t) & BM_AIPS_PACRD_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP3 (16U) //!< Bit position for AIPS_PACRD_TP3. -#define BM_AIPS_PACRD_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRD_TP3. -#define BS_AIPS_PACRD_TP3 (1U) //!< Bit field size in bits for AIPS_PACRD_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP3 field. -#define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP3. -#define BF_AIPS_PACRD_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP3), uint32_t) & BM_AIPS_PACRD_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP3 (17U) //!< Bit position for AIPS_PACRD_WP3. -#define BM_AIPS_PACRD_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRD_WP3. -#define BS_AIPS_PACRD_WP3 (1U) //!< Bit field size in bits for AIPS_PACRD_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP3 field. -#define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP3. -#define BF_AIPS_PACRD_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP3), uint32_t) & BM_AIPS_PACRD_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP3 (18U) //!< Bit position for AIPS_PACRD_SP3. -#define BM_AIPS_PACRD_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRD_SP3. -#define BS_AIPS_PACRD_SP3 (1U) //!< Bit field size in bits for AIPS_PACRD_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP3 field. -#define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP3. -#define BF_AIPS_PACRD_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP3), uint32_t) & BM_AIPS_PACRD_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP2 (20U) //!< Bit position for AIPS_PACRD_TP2. -#define BM_AIPS_PACRD_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRD_TP2. -#define BS_AIPS_PACRD_TP2 (1U) //!< Bit field size in bits for AIPS_PACRD_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP2 field. -#define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP2. -#define BF_AIPS_PACRD_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP2), uint32_t) & BM_AIPS_PACRD_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP2 (21U) //!< Bit position for AIPS_PACRD_WP2. -#define BM_AIPS_PACRD_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRD_WP2. -#define BS_AIPS_PACRD_WP2 (1U) //!< Bit field size in bits for AIPS_PACRD_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP2 field. -#define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP2. -#define BF_AIPS_PACRD_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP2), uint32_t) & BM_AIPS_PACRD_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP2 (22U) //!< Bit position for AIPS_PACRD_SP2. -#define BM_AIPS_PACRD_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRD_SP2. -#define BS_AIPS_PACRD_SP2 (1U) //!< Bit field size in bits for AIPS_PACRD_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP2 field. -#define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP2. -#define BF_AIPS_PACRD_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP2), uint32_t) & BM_AIPS_PACRD_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP1 (24U) //!< Bit position for AIPS_PACRD_TP1. -#define BM_AIPS_PACRD_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRD_TP1. -#define BS_AIPS_PACRD_TP1 (1U) //!< Bit field size in bits for AIPS_PACRD_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP1 field. -#define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP1. -#define BF_AIPS_PACRD_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP1), uint32_t) & BM_AIPS_PACRD_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP1 (25U) //!< Bit position for AIPS_PACRD_WP1. -#define BM_AIPS_PACRD_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRD_WP1. -#define BS_AIPS_PACRD_WP1 (1U) //!< Bit field size in bits for AIPS_PACRD_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP1 field. -#define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP1. -#define BF_AIPS_PACRD_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP1), uint32_t) & BM_AIPS_PACRD_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP1 (26U) //!< Bit position for AIPS_PACRD_SP1. -#define BM_AIPS_PACRD_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRD_SP1. -#define BS_AIPS_PACRD_SP1 (1U) //!< Bit field size in bits for AIPS_PACRD_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP1 field. -#define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP1. -#define BF_AIPS_PACRD_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP1), uint32_t) & BM_AIPS_PACRD_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRD_TP0 (28U) //!< Bit position for AIPS_PACRD_TP0. -#define BM_AIPS_PACRD_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRD_TP0. -#define BS_AIPS_PACRD_TP0 (1U) //!< Bit field size in bits for AIPS_PACRD_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_TP0 field. -#define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_TP0. -#define BF_AIPS_PACRD_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP0), uint32_t) & BM_AIPS_PACRD_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRD_WP0 (29U) //!< Bit position for AIPS_PACRD_WP0. -#define BM_AIPS_PACRD_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRD_WP0. -#define BS_AIPS_PACRD_WP0 (1U) //!< Bit field size in bits for AIPS_PACRD_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_WP0 field. -#define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_WP0. -#define BF_AIPS_PACRD_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP0), uint32_t) & BM_AIPS_PACRD_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRD, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRD_SP0 (30U) //!< Bit position for AIPS_PACRD_SP0. -#define BM_AIPS_PACRD_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRD_SP0. -#define BS_AIPS_PACRD_SP0 (1U) //!< Bit field size in bits for AIPS_PACRD_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRD_SP0 field. -#define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRD_SP0. -#define BF_AIPS_PACRD_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP0), uint32_t) & BM_AIPS_PACRD_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRE - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacre -{ - uint32_t U; - struct _hw_aips_pacre_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacre_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRE register - */ -//@{ -#define HW_AIPS_PACRE_ADDR(x) (REGS_AIPS_BASE(x) + 0x40U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x)) -#define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U) -#define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v)) -#define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v))) -#define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v))) -#define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRE bitfields - */ - -/*! - * @name Register AIPS_PACRE, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP7 (0U) //!< Bit position for AIPS_PACRE_TP7. -#define BM_AIPS_PACRE_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRE_TP7. -#define BS_AIPS_PACRE_TP7 (1U) //!< Bit field size in bits for AIPS_PACRE_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP7 field. -#define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP7. -#define BF_AIPS_PACRE_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP7), uint32_t) & BM_AIPS_PACRE_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP7 (1U) //!< Bit position for AIPS_PACRE_WP7. -#define BM_AIPS_PACRE_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRE_WP7. -#define BS_AIPS_PACRE_WP7 (1U) //!< Bit field size in bits for AIPS_PACRE_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP7 field. -#define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP7. -#define BF_AIPS_PACRE_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP7), uint32_t) & BM_AIPS_PACRE_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP7 (2U) //!< Bit position for AIPS_PACRE_SP7. -#define BM_AIPS_PACRE_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRE_SP7. -#define BS_AIPS_PACRE_SP7 (1U) //!< Bit field size in bits for AIPS_PACRE_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP7 field. -#define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP7. -#define BF_AIPS_PACRE_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP7), uint32_t) & BM_AIPS_PACRE_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP6 (4U) //!< Bit position for AIPS_PACRE_TP6. -#define BM_AIPS_PACRE_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRE_TP6. -#define BS_AIPS_PACRE_TP6 (1U) //!< Bit field size in bits for AIPS_PACRE_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP6 field. -#define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP6. -#define BF_AIPS_PACRE_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP6), uint32_t) & BM_AIPS_PACRE_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP6 (5U) //!< Bit position for AIPS_PACRE_WP6. -#define BM_AIPS_PACRE_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRE_WP6. -#define BS_AIPS_PACRE_WP6 (1U) //!< Bit field size in bits for AIPS_PACRE_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP6 field. -#define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP6. -#define BF_AIPS_PACRE_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP6), uint32_t) & BM_AIPS_PACRE_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP6 (6U) //!< Bit position for AIPS_PACRE_SP6. -#define BM_AIPS_PACRE_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRE_SP6. -#define BS_AIPS_PACRE_SP6 (1U) //!< Bit field size in bits for AIPS_PACRE_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP6 field. -#define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP6. -#define BF_AIPS_PACRE_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP6), uint32_t) & BM_AIPS_PACRE_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP5 (8U) //!< Bit position for AIPS_PACRE_TP5. -#define BM_AIPS_PACRE_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRE_TP5. -#define BS_AIPS_PACRE_TP5 (1U) //!< Bit field size in bits for AIPS_PACRE_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP5 field. -#define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP5. -#define BF_AIPS_PACRE_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP5), uint32_t) & BM_AIPS_PACRE_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP5 (9U) //!< Bit position for AIPS_PACRE_WP5. -#define BM_AIPS_PACRE_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRE_WP5. -#define BS_AIPS_PACRE_WP5 (1U) //!< Bit field size in bits for AIPS_PACRE_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP5 field. -#define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP5. -#define BF_AIPS_PACRE_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP5), uint32_t) & BM_AIPS_PACRE_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP5 (10U) //!< Bit position for AIPS_PACRE_SP5. -#define BM_AIPS_PACRE_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRE_SP5. -#define BS_AIPS_PACRE_SP5 (1U) //!< Bit field size in bits for AIPS_PACRE_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP5 field. -#define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP5. -#define BF_AIPS_PACRE_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP5), uint32_t) & BM_AIPS_PACRE_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP4 (12U) //!< Bit position for AIPS_PACRE_TP4. -#define BM_AIPS_PACRE_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRE_TP4. -#define BS_AIPS_PACRE_TP4 (1U) //!< Bit field size in bits for AIPS_PACRE_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP4 field. -#define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP4. -#define BF_AIPS_PACRE_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP4), uint32_t) & BM_AIPS_PACRE_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP4 (13U) //!< Bit position for AIPS_PACRE_WP4. -#define BM_AIPS_PACRE_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRE_WP4. -#define BS_AIPS_PACRE_WP4 (1U) //!< Bit field size in bits for AIPS_PACRE_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP4 field. -#define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP4. -#define BF_AIPS_PACRE_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP4), uint32_t) & BM_AIPS_PACRE_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP4 (14U) //!< Bit position for AIPS_PACRE_SP4. -#define BM_AIPS_PACRE_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRE_SP4. -#define BS_AIPS_PACRE_SP4 (1U) //!< Bit field size in bits for AIPS_PACRE_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP4 field. -#define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP4. -#define BF_AIPS_PACRE_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP4), uint32_t) & BM_AIPS_PACRE_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP3 (16U) //!< Bit position for AIPS_PACRE_TP3. -#define BM_AIPS_PACRE_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRE_TP3. -#define BS_AIPS_PACRE_TP3 (1U) //!< Bit field size in bits for AIPS_PACRE_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP3 field. -#define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP3. -#define BF_AIPS_PACRE_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP3), uint32_t) & BM_AIPS_PACRE_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP3 (17U) //!< Bit position for AIPS_PACRE_WP3. -#define BM_AIPS_PACRE_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRE_WP3. -#define BS_AIPS_PACRE_WP3 (1U) //!< Bit field size in bits for AIPS_PACRE_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP3 field. -#define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP3. -#define BF_AIPS_PACRE_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP3), uint32_t) & BM_AIPS_PACRE_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP3 (18U) //!< Bit position for AIPS_PACRE_SP3. -#define BM_AIPS_PACRE_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRE_SP3. -#define BS_AIPS_PACRE_SP3 (1U) //!< Bit field size in bits for AIPS_PACRE_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP3 field. -#define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP3. -#define BF_AIPS_PACRE_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP3), uint32_t) & BM_AIPS_PACRE_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP2 (20U) //!< Bit position for AIPS_PACRE_TP2. -#define BM_AIPS_PACRE_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRE_TP2. -#define BS_AIPS_PACRE_TP2 (1U) //!< Bit field size in bits for AIPS_PACRE_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP2 field. -#define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP2. -#define BF_AIPS_PACRE_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP2), uint32_t) & BM_AIPS_PACRE_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP2 (21U) //!< Bit position for AIPS_PACRE_WP2. -#define BM_AIPS_PACRE_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRE_WP2. -#define BS_AIPS_PACRE_WP2 (1U) //!< Bit field size in bits for AIPS_PACRE_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP2 field. -#define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP2. -#define BF_AIPS_PACRE_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP2), uint32_t) & BM_AIPS_PACRE_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP2 (22U) //!< Bit position for AIPS_PACRE_SP2. -#define BM_AIPS_PACRE_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRE_SP2. -#define BS_AIPS_PACRE_SP2 (1U) //!< Bit field size in bits for AIPS_PACRE_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP2 field. -#define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP2. -#define BF_AIPS_PACRE_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP2), uint32_t) & BM_AIPS_PACRE_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP1 (24U) //!< Bit position for AIPS_PACRE_TP1. -#define BM_AIPS_PACRE_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRE_TP1. -#define BS_AIPS_PACRE_TP1 (1U) //!< Bit field size in bits for AIPS_PACRE_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP1 field. -#define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP1. -#define BF_AIPS_PACRE_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP1), uint32_t) & BM_AIPS_PACRE_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP1 (25U) //!< Bit position for AIPS_PACRE_WP1. -#define BM_AIPS_PACRE_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRE_WP1. -#define BS_AIPS_PACRE_WP1 (1U) //!< Bit field size in bits for AIPS_PACRE_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP1 field. -#define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP1. -#define BF_AIPS_PACRE_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP1), uint32_t) & BM_AIPS_PACRE_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP1 (26U) //!< Bit position for AIPS_PACRE_SP1. -#define BM_AIPS_PACRE_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRE_SP1. -#define BS_AIPS_PACRE_SP1 (1U) //!< Bit field size in bits for AIPS_PACRE_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP1 field. -#define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP1. -#define BF_AIPS_PACRE_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP1), uint32_t) & BM_AIPS_PACRE_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRE_TP0 (28U) //!< Bit position for AIPS_PACRE_TP0. -#define BM_AIPS_PACRE_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRE_TP0. -#define BS_AIPS_PACRE_TP0 (1U) //!< Bit field size in bits for AIPS_PACRE_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_TP0 field. -#define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_TP0. -#define BF_AIPS_PACRE_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP0), uint32_t) & BM_AIPS_PACRE_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRE_WP0 (29U) //!< Bit position for AIPS_PACRE_WP0. -#define BM_AIPS_PACRE_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRE_WP0. -#define BS_AIPS_PACRE_WP0 (1U) //!< Bit field size in bits for AIPS_PACRE_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_WP0 field. -#define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_WP0. -#define BF_AIPS_PACRE_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP0), uint32_t) & BM_AIPS_PACRE_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRE, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRE_SP0 (30U) //!< Bit position for AIPS_PACRE_SP0. -#define BM_AIPS_PACRE_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRE_SP0. -#define BS_AIPS_PACRE_SP0 (1U) //!< Bit field size in bits for AIPS_PACRE_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRE_SP0 field. -#define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRE_SP0. -#define BF_AIPS_PACRE_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP0), uint32_t) & BM_AIPS_PACRE_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRF - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrf -{ - uint32_t U; - struct _hw_aips_pacrf_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrf_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRF register - */ -//@{ -#define HW_AIPS_PACRF_ADDR(x) (REGS_AIPS_BASE(x) + 0x44U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x)) -#define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U) -#define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v)) -#define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v))) -#define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v))) -#define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRF bitfields - */ - -/*! - * @name Register AIPS_PACRF, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP7 (0U) //!< Bit position for AIPS_PACRF_TP7. -#define BM_AIPS_PACRF_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRF_TP7. -#define BS_AIPS_PACRF_TP7 (1U) //!< Bit field size in bits for AIPS_PACRF_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP7 field. -#define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP7. -#define BF_AIPS_PACRF_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP7), uint32_t) & BM_AIPS_PACRF_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP7 (1U) //!< Bit position for AIPS_PACRF_WP7. -#define BM_AIPS_PACRF_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRF_WP7. -#define BS_AIPS_PACRF_WP7 (1U) //!< Bit field size in bits for AIPS_PACRF_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP7 field. -#define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP7. -#define BF_AIPS_PACRF_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP7), uint32_t) & BM_AIPS_PACRF_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP7 (2U) //!< Bit position for AIPS_PACRF_SP7. -#define BM_AIPS_PACRF_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRF_SP7. -#define BS_AIPS_PACRF_SP7 (1U) //!< Bit field size in bits for AIPS_PACRF_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP7 field. -#define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP7. -#define BF_AIPS_PACRF_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP7), uint32_t) & BM_AIPS_PACRF_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP6 (4U) //!< Bit position for AIPS_PACRF_TP6. -#define BM_AIPS_PACRF_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRF_TP6. -#define BS_AIPS_PACRF_TP6 (1U) //!< Bit field size in bits for AIPS_PACRF_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP6 field. -#define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP6. -#define BF_AIPS_PACRF_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP6), uint32_t) & BM_AIPS_PACRF_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP6 (5U) //!< Bit position for AIPS_PACRF_WP6. -#define BM_AIPS_PACRF_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRF_WP6. -#define BS_AIPS_PACRF_WP6 (1U) //!< Bit field size in bits for AIPS_PACRF_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP6 field. -#define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP6. -#define BF_AIPS_PACRF_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP6), uint32_t) & BM_AIPS_PACRF_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP6 (6U) //!< Bit position for AIPS_PACRF_SP6. -#define BM_AIPS_PACRF_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRF_SP6. -#define BS_AIPS_PACRF_SP6 (1U) //!< Bit field size in bits for AIPS_PACRF_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP6 field. -#define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP6. -#define BF_AIPS_PACRF_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP6), uint32_t) & BM_AIPS_PACRF_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP5 (8U) //!< Bit position for AIPS_PACRF_TP5. -#define BM_AIPS_PACRF_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRF_TP5. -#define BS_AIPS_PACRF_TP5 (1U) //!< Bit field size in bits for AIPS_PACRF_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP5 field. -#define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP5. -#define BF_AIPS_PACRF_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP5), uint32_t) & BM_AIPS_PACRF_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP5 (9U) //!< Bit position for AIPS_PACRF_WP5. -#define BM_AIPS_PACRF_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRF_WP5. -#define BS_AIPS_PACRF_WP5 (1U) //!< Bit field size in bits for AIPS_PACRF_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP5 field. -#define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP5. -#define BF_AIPS_PACRF_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP5), uint32_t) & BM_AIPS_PACRF_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP5 (10U) //!< Bit position for AIPS_PACRF_SP5. -#define BM_AIPS_PACRF_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRF_SP5. -#define BS_AIPS_PACRF_SP5 (1U) //!< Bit field size in bits for AIPS_PACRF_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP5 field. -#define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP5. -#define BF_AIPS_PACRF_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP5), uint32_t) & BM_AIPS_PACRF_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP4 (12U) //!< Bit position for AIPS_PACRF_TP4. -#define BM_AIPS_PACRF_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRF_TP4. -#define BS_AIPS_PACRF_TP4 (1U) //!< Bit field size in bits for AIPS_PACRF_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP4 field. -#define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP4. -#define BF_AIPS_PACRF_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP4), uint32_t) & BM_AIPS_PACRF_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP4 (13U) //!< Bit position for AIPS_PACRF_WP4. -#define BM_AIPS_PACRF_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRF_WP4. -#define BS_AIPS_PACRF_WP4 (1U) //!< Bit field size in bits for AIPS_PACRF_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP4 field. -#define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP4. -#define BF_AIPS_PACRF_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP4), uint32_t) & BM_AIPS_PACRF_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP4 (14U) //!< Bit position for AIPS_PACRF_SP4. -#define BM_AIPS_PACRF_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRF_SP4. -#define BS_AIPS_PACRF_SP4 (1U) //!< Bit field size in bits for AIPS_PACRF_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP4 field. -#define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP4. -#define BF_AIPS_PACRF_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP4), uint32_t) & BM_AIPS_PACRF_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP3 (16U) //!< Bit position for AIPS_PACRF_TP3. -#define BM_AIPS_PACRF_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRF_TP3. -#define BS_AIPS_PACRF_TP3 (1U) //!< Bit field size in bits for AIPS_PACRF_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP3 field. -#define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP3. -#define BF_AIPS_PACRF_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP3), uint32_t) & BM_AIPS_PACRF_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP3 (17U) //!< Bit position for AIPS_PACRF_WP3. -#define BM_AIPS_PACRF_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRF_WP3. -#define BS_AIPS_PACRF_WP3 (1U) //!< Bit field size in bits for AIPS_PACRF_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP3 field. -#define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP3. -#define BF_AIPS_PACRF_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP3), uint32_t) & BM_AIPS_PACRF_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP3 (18U) //!< Bit position for AIPS_PACRF_SP3. -#define BM_AIPS_PACRF_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRF_SP3. -#define BS_AIPS_PACRF_SP3 (1U) //!< Bit field size in bits for AIPS_PACRF_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP3 field. -#define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP3. -#define BF_AIPS_PACRF_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP3), uint32_t) & BM_AIPS_PACRF_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP2 (20U) //!< Bit position for AIPS_PACRF_TP2. -#define BM_AIPS_PACRF_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRF_TP2. -#define BS_AIPS_PACRF_TP2 (1U) //!< Bit field size in bits for AIPS_PACRF_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP2 field. -#define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP2. -#define BF_AIPS_PACRF_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP2), uint32_t) & BM_AIPS_PACRF_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP2 (21U) //!< Bit position for AIPS_PACRF_WP2. -#define BM_AIPS_PACRF_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRF_WP2. -#define BS_AIPS_PACRF_WP2 (1U) //!< Bit field size in bits for AIPS_PACRF_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP2 field. -#define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP2. -#define BF_AIPS_PACRF_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP2), uint32_t) & BM_AIPS_PACRF_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP2 (22U) //!< Bit position for AIPS_PACRF_SP2. -#define BM_AIPS_PACRF_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRF_SP2. -#define BS_AIPS_PACRF_SP2 (1U) //!< Bit field size in bits for AIPS_PACRF_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP2 field. -#define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP2. -#define BF_AIPS_PACRF_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP2), uint32_t) & BM_AIPS_PACRF_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP1 (24U) //!< Bit position for AIPS_PACRF_TP1. -#define BM_AIPS_PACRF_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRF_TP1. -#define BS_AIPS_PACRF_TP1 (1U) //!< Bit field size in bits for AIPS_PACRF_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP1 field. -#define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP1. -#define BF_AIPS_PACRF_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP1), uint32_t) & BM_AIPS_PACRF_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP1 (25U) //!< Bit position for AIPS_PACRF_WP1. -#define BM_AIPS_PACRF_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRF_WP1. -#define BS_AIPS_PACRF_WP1 (1U) //!< Bit field size in bits for AIPS_PACRF_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP1 field. -#define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP1. -#define BF_AIPS_PACRF_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP1), uint32_t) & BM_AIPS_PACRF_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP1 (26U) //!< Bit position for AIPS_PACRF_SP1. -#define BM_AIPS_PACRF_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRF_SP1. -#define BS_AIPS_PACRF_SP1 (1U) //!< Bit field size in bits for AIPS_PACRF_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP1 field. -#define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP1. -#define BF_AIPS_PACRF_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP1), uint32_t) & BM_AIPS_PACRF_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRF_TP0 (28U) //!< Bit position for AIPS_PACRF_TP0. -#define BM_AIPS_PACRF_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRF_TP0. -#define BS_AIPS_PACRF_TP0 (1U) //!< Bit field size in bits for AIPS_PACRF_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_TP0 field. -#define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_TP0. -#define BF_AIPS_PACRF_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP0), uint32_t) & BM_AIPS_PACRF_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRF_WP0 (29U) //!< Bit position for AIPS_PACRF_WP0. -#define BM_AIPS_PACRF_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRF_WP0. -#define BS_AIPS_PACRF_WP0 (1U) //!< Bit field size in bits for AIPS_PACRF_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_WP0 field. -#define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_WP0. -#define BF_AIPS_PACRF_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP0), uint32_t) & BM_AIPS_PACRF_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRF, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRF_SP0 (30U) //!< Bit position for AIPS_PACRF_SP0. -#define BM_AIPS_PACRF_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRF_SP0. -#define BS_AIPS_PACRF_SP0 (1U) //!< Bit field size in bits for AIPS_PACRF_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRF_SP0 field. -#define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRF_SP0. -#define BF_AIPS_PACRF_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP0), uint32_t) & BM_AIPS_PACRF_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRG - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrg -{ - uint32_t U; - struct _hw_aips_pacrg_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrg_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRG register - */ -//@{ -#define HW_AIPS_PACRG_ADDR(x) (REGS_AIPS_BASE(x) + 0x48U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x)) -#define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U) -#define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v)) -#define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v))) -#define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v))) -#define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRG bitfields - */ - -/*! - * @name Register AIPS_PACRG, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP7 (0U) //!< Bit position for AIPS_PACRG_TP7. -#define BM_AIPS_PACRG_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRG_TP7. -#define BS_AIPS_PACRG_TP7 (1U) //!< Bit field size in bits for AIPS_PACRG_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP7 field. -#define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP7. -#define BF_AIPS_PACRG_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP7), uint32_t) & BM_AIPS_PACRG_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP7 (1U) //!< Bit position for AIPS_PACRG_WP7. -#define BM_AIPS_PACRG_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRG_WP7. -#define BS_AIPS_PACRG_WP7 (1U) //!< Bit field size in bits for AIPS_PACRG_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP7 field. -#define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP7. -#define BF_AIPS_PACRG_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP7), uint32_t) & BM_AIPS_PACRG_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP7 (2U) //!< Bit position for AIPS_PACRG_SP7. -#define BM_AIPS_PACRG_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRG_SP7. -#define BS_AIPS_PACRG_SP7 (1U) //!< Bit field size in bits for AIPS_PACRG_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP7 field. -#define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP7. -#define BF_AIPS_PACRG_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP7), uint32_t) & BM_AIPS_PACRG_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP6 (4U) //!< Bit position for AIPS_PACRG_TP6. -#define BM_AIPS_PACRG_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRG_TP6. -#define BS_AIPS_PACRG_TP6 (1U) //!< Bit field size in bits for AIPS_PACRG_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP6 field. -#define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP6. -#define BF_AIPS_PACRG_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP6), uint32_t) & BM_AIPS_PACRG_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP6 (5U) //!< Bit position for AIPS_PACRG_WP6. -#define BM_AIPS_PACRG_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRG_WP6. -#define BS_AIPS_PACRG_WP6 (1U) //!< Bit field size in bits for AIPS_PACRG_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP6 field. -#define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP6. -#define BF_AIPS_PACRG_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP6), uint32_t) & BM_AIPS_PACRG_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP6 (6U) //!< Bit position for AIPS_PACRG_SP6. -#define BM_AIPS_PACRG_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRG_SP6. -#define BS_AIPS_PACRG_SP6 (1U) //!< Bit field size in bits for AIPS_PACRG_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP6 field. -#define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP6. -#define BF_AIPS_PACRG_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP6), uint32_t) & BM_AIPS_PACRG_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP5 (8U) //!< Bit position for AIPS_PACRG_TP5. -#define BM_AIPS_PACRG_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRG_TP5. -#define BS_AIPS_PACRG_TP5 (1U) //!< Bit field size in bits for AIPS_PACRG_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP5 field. -#define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP5. -#define BF_AIPS_PACRG_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP5), uint32_t) & BM_AIPS_PACRG_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP5 (9U) //!< Bit position for AIPS_PACRG_WP5. -#define BM_AIPS_PACRG_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRG_WP5. -#define BS_AIPS_PACRG_WP5 (1U) //!< Bit field size in bits for AIPS_PACRG_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP5 field. -#define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP5. -#define BF_AIPS_PACRG_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP5), uint32_t) & BM_AIPS_PACRG_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP5 (10U) //!< Bit position for AIPS_PACRG_SP5. -#define BM_AIPS_PACRG_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRG_SP5. -#define BS_AIPS_PACRG_SP5 (1U) //!< Bit field size in bits for AIPS_PACRG_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP5 field. -#define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP5. -#define BF_AIPS_PACRG_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP5), uint32_t) & BM_AIPS_PACRG_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP4 (12U) //!< Bit position for AIPS_PACRG_TP4. -#define BM_AIPS_PACRG_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRG_TP4. -#define BS_AIPS_PACRG_TP4 (1U) //!< Bit field size in bits for AIPS_PACRG_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP4 field. -#define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP4. -#define BF_AIPS_PACRG_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP4), uint32_t) & BM_AIPS_PACRG_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP4 (13U) //!< Bit position for AIPS_PACRG_WP4. -#define BM_AIPS_PACRG_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRG_WP4. -#define BS_AIPS_PACRG_WP4 (1U) //!< Bit field size in bits for AIPS_PACRG_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP4 field. -#define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP4. -#define BF_AIPS_PACRG_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP4), uint32_t) & BM_AIPS_PACRG_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP4 (14U) //!< Bit position for AIPS_PACRG_SP4. -#define BM_AIPS_PACRG_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRG_SP4. -#define BS_AIPS_PACRG_SP4 (1U) //!< Bit field size in bits for AIPS_PACRG_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP4 field. -#define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP4. -#define BF_AIPS_PACRG_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP4), uint32_t) & BM_AIPS_PACRG_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP3 (16U) //!< Bit position for AIPS_PACRG_TP3. -#define BM_AIPS_PACRG_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRG_TP3. -#define BS_AIPS_PACRG_TP3 (1U) //!< Bit field size in bits for AIPS_PACRG_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP3 field. -#define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP3. -#define BF_AIPS_PACRG_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP3), uint32_t) & BM_AIPS_PACRG_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP3 (17U) //!< Bit position for AIPS_PACRG_WP3. -#define BM_AIPS_PACRG_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRG_WP3. -#define BS_AIPS_PACRG_WP3 (1U) //!< Bit field size in bits for AIPS_PACRG_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP3 field. -#define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP3. -#define BF_AIPS_PACRG_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP3), uint32_t) & BM_AIPS_PACRG_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP3 (18U) //!< Bit position for AIPS_PACRG_SP3. -#define BM_AIPS_PACRG_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRG_SP3. -#define BS_AIPS_PACRG_SP3 (1U) //!< Bit field size in bits for AIPS_PACRG_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP3 field. -#define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP3. -#define BF_AIPS_PACRG_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP3), uint32_t) & BM_AIPS_PACRG_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP2 (20U) //!< Bit position for AIPS_PACRG_TP2. -#define BM_AIPS_PACRG_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRG_TP2. -#define BS_AIPS_PACRG_TP2 (1U) //!< Bit field size in bits for AIPS_PACRG_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP2 field. -#define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP2. -#define BF_AIPS_PACRG_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP2), uint32_t) & BM_AIPS_PACRG_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP2 (21U) //!< Bit position for AIPS_PACRG_WP2. -#define BM_AIPS_PACRG_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRG_WP2. -#define BS_AIPS_PACRG_WP2 (1U) //!< Bit field size in bits for AIPS_PACRG_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP2 field. -#define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP2. -#define BF_AIPS_PACRG_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP2), uint32_t) & BM_AIPS_PACRG_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP2 (22U) //!< Bit position for AIPS_PACRG_SP2. -#define BM_AIPS_PACRG_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRG_SP2. -#define BS_AIPS_PACRG_SP2 (1U) //!< Bit field size in bits for AIPS_PACRG_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP2 field. -#define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP2. -#define BF_AIPS_PACRG_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP2), uint32_t) & BM_AIPS_PACRG_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP1 (24U) //!< Bit position for AIPS_PACRG_TP1. -#define BM_AIPS_PACRG_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRG_TP1. -#define BS_AIPS_PACRG_TP1 (1U) //!< Bit field size in bits for AIPS_PACRG_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP1 field. -#define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP1. -#define BF_AIPS_PACRG_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP1), uint32_t) & BM_AIPS_PACRG_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP1 (25U) //!< Bit position for AIPS_PACRG_WP1. -#define BM_AIPS_PACRG_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRG_WP1. -#define BS_AIPS_PACRG_WP1 (1U) //!< Bit field size in bits for AIPS_PACRG_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP1 field. -#define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP1. -#define BF_AIPS_PACRG_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP1), uint32_t) & BM_AIPS_PACRG_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP1 (26U) //!< Bit position for AIPS_PACRG_SP1. -#define BM_AIPS_PACRG_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRG_SP1. -#define BS_AIPS_PACRG_SP1 (1U) //!< Bit field size in bits for AIPS_PACRG_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP1 field. -#define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP1. -#define BF_AIPS_PACRG_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP1), uint32_t) & BM_AIPS_PACRG_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRG_TP0 (28U) //!< Bit position for AIPS_PACRG_TP0. -#define BM_AIPS_PACRG_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRG_TP0. -#define BS_AIPS_PACRG_TP0 (1U) //!< Bit field size in bits for AIPS_PACRG_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_TP0 field. -#define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_TP0. -#define BF_AIPS_PACRG_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP0), uint32_t) & BM_AIPS_PACRG_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRG_WP0 (29U) //!< Bit position for AIPS_PACRG_WP0. -#define BM_AIPS_PACRG_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRG_WP0. -#define BS_AIPS_PACRG_WP0 (1U) //!< Bit field size in bits for AIPS_PACRG_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_WP0 field. -#define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_WP0. -#define BF_AIPS_PACRG_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP0), uint32_t) & BM_AIPS_PACRG_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRG, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRG_SP0 (30U) //!< Bit position for AIPS_PACRG_SP0. -#define BM_AIPS_PACRG_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRG_SP0. -#define BS_AIPS_PACRG_SP0 (1U) //!< Bit field size in bits for AIPS_PACRG_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRG_SP0 field. -#define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRG_SP0. -#define BF_AIPS_PACRG_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP0), uint32_t) & BM_AIPS_PACRG_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRH - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrh -{ - uint32_t U; - struct _hw_aips_pacrh_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrh_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRH register - */ -//@{ -#define HW_AIPS_PACRH_ADDR(x) (REGS_AIPS_BASE(x) + 0x4CU) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x)) -#define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U) -#define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v)) -#define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v))) -#define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v))) -#define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRH bitfields - */ - -/*! - * @name Register AIPS_PACRH, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP7 (0U) //!< Bit position for AIPS_PACRH_TP7. -#define BM_AIPS_PACRH_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRH_TP7. -#define BS_AIPS_PACRH_TP7 (1U) //!< Bit field size in bits for AIPS_PACRH_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP7 field. -#define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP7. -#define BF_AIPS_PACRH_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP7), uint32_t) & BM_AIPS_PACRH_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP7 (1U) //!< Bit position for AIPS_PACRH_WP7. -#define BM_AIPS_PACRH_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRH_WP7. -#define BS_AIPS_PACRH_WP7 (1U) //!< Bit field size in bits for AIPS_PACRH_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP7 field. -#define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP7. -#define BF_AIPS_PACRH_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP7), uint32_t) & BM_AIPS_PACRH_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP7 (2U) //!< Bit position for AIPS_PACRH_SP7. -#define BM_AIPS_PACRH_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRH_SP7. -#define BS_AIPS_PACRH_SP7 (1U) //!< Bit field size in bits for AIPS_PACRH_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP7 field. -#define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP7. -#define BF_AIPS_PACRH_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP7), uint32_t) & BM_AIPS_PACRH_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP6 (4U) //!< Bit position for AIPS_PACRH_TP6. -#define BM_AIPS_PACRH_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRH_TP6. -#define BS_AIPS_PACRH_TP6 (1U) //!< Bit field size in bits for AIPS_PACRH_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP6 field. -#define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP6. -#define BF_AIPS_PACRH_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP6), uint32_t) & BM_AIPS_PACRH_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP6 (5U) //!< Bit position for AIPS_PACRH_WP6. -#define BM_AIPS_PACRH_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRH_WP6. -#define BS_AIPS_PACRH_WP6 (1U) //!< Bit field size in bits for AIPS_PACRH_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP6 field. -#define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP6. -#define BF_AIPS_PACRH_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP6), uint32_t) & BM_AIPS_PACRH_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP6 (6U) //!< Bit position for AIPS_PACRH_SP6. -#define BM_AIPS_PACRH_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRH_SP6. -#define BS_AIPS_PACRH_SP6 (1U) //!< Bit field size in bits for AIPS_PACRH_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP6 field. -#define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP6. -#define BF_AIPS_PACRH_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP6), uint32_t) & BM_AIPS_PACRH_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP5 (8U) //!< Bit position for AIPS_PACRH_TP5. -#define BM_AIPS_PACRH_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRH_TP5. -#define BS_AIPS_PACRH_TP5 (1U) //!< Bit field size in bits for AIPS_PACRH_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP5 field. -#define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP5. -#define BF_AIPS_PACRH_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP5), uint32_t) & BM_AIPS_PACRH_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP5 (9U) //!< Bit position for AIPS_PACRH_WP5. -#define BM_AIPS_PACRH_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRH_WP5. -#define BS_AIPS_PACRH_WP5 (1U) //!< Bit field size in bits for AIPS_PACRH_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP5 field. -#define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP5. -#define BF_AIPS_PACRH_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP5), uint32_t) & BM_AIPS_PACRH_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP5 (10U) //!< Bit position for AIPS_PACRH_SP5. -#define BM_AIPS_PACRH_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRH_SP5. -#define BS_AIPS_PACRH_SP5 (1U) //!< Bit field size in bits for AIPS_PACRH_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP5 field. -#define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP5. -#define BF_AIPS_PACRH_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP5), uint32_t) & BM_AIPS_PACRH_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP4 (12U) //!< Bit position for AIPS_PACRH_TP4. -#define BM_AIPS_PACRH_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRH_TP4. -#define BS_AIPS_PACRH_TP4 (1U) //!< Bit field size in bits for AIPS_PACRH_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP4 field. -#define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP4. -#define BF_AIPS_PACRH_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP4), uint32_t) & BM_AIPS_PACRH_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP4 (13U) //!< Bit position for AIPS_PACRH_WP4. -#define BM_AIPS_PACRH_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRH_WP4. -#define BS_AIPS_PACRH_WP4 (1U) //!< Bit field size in bits for AIPS_PACRH_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP4 field. -#define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP4. -#define BF_AIPS_PACRH_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP4), uint32_t) & BM_AIPS_PACRH_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP4 (14U) //!< Bit position for AIPS_PACRH_SP4. -#define BM_AIPS_PACRH_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRH_SP4. -#define BS_AIPS_PACRH_SP4 (1U) //!< Bit field size in bits for AIPS_PACRH_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP4 field. -#define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP4. -#define BF_AIPS_PACRH_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP4), uint32_t) & BM_AIPS_PACRH_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP3 (16U) //!< Bit position for AIPS_PACRH_TP3. -#define BM_AIPS_PACRH_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRH_TP3. -#define BS_AIPS_PACRH_TP3 (1U) //!< Bit field size in bits for AIPS_PACRH_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP3 field. -#define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP3. -#define BF_AIPS_PACRH_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP3), uint32_t) & BM_AIPS_PACRH_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP3 (17U) //!< Bit position for AIPS_PACRH_WP3. -#define BM_AIPS_PACRH_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRH_WP3. -#define BS_AIPS_PACRH_WP3 (1U) //!< Bit field size in bits for AIPS_PACRH_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP3 field. -#define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP3. -#define BF_AIPS_PACRH_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP3), uint32_t) & BM_AIPS_PACRH_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP3 (18U) //!< Bit position for AIPS_PACRH_SP3. -#define BM_AIPS_PACRH_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRH_SP3. -#define BS_AIPS_PACRH_SP3 (1U) //!< Bit field size in bits for AIPS_PACRH_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP3 field. -#define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP3. -#define BF_AIPS_PACRH_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP3), uint32_t) & BM_AIPS_PACRH_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP2 (20U) //!< Bit position for AIPS_PACRH_TP2. -#define BM_AIPS_PACRH_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRH_TP2. -#define BS_AIPS_PACRH_TP2 (1U) //!< Bit field size in bits for AIPS_PACRH_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP2 field. -#define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP2. -#define BF_AIPS_PACRH_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP2), uint32_t) & BM_AIPS_PACRH_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP2 (21U) //!< Bit position for AIPS_PACRH_WP2. -#define BM_AIPS_PACRH_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRH_WP2. -#define BS_AIPS_PACRH_WP2 (1U) //!< Bit field size in bits for AIPS_PACRH_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP2 field. -#define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP2. -#define BF_AIPS_PACRH_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP2), uint32_t) & BM_AIPS_PACRH_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP2 (22U) //!< Bit position for AIPS_PACRH_SP2. -#define BM_AIPS_PACRH_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRH_SP2. -#define BS_AIPS_PACRH_SP2 (1U) //!< Bit field size in bits for AIPS_PACRH_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP2 field. -#define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP2. -#define BF_AIPS_PACRH_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP2), uint32_t) & BM_AIPS_PACRH_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP1 (24U) //!< Bit position for AIPS_PACRH_TP1. -#define BM_AIPS_PACRH_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRH_TP1. -#define BS_AIPS_PACRH_TP1 (1U) //!< Bit field size in bits for AIPS_PACRH_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP1 field. -#define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP1. -#define BF_AIPS_PACRH_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP1), uint32_t) & BM_AIPS_PACRH_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP1 (25U) //!< Bit position for AIPS_PACRH_WP1. -#define BM_AIPS_PACRH_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRH_WP1. -#define BS_AIPS_PACRH_WP1 (1U) //!< Bit field size in bits for AIPS_PACRH_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP1 field. -#define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP1. -#define BF_AIPS_PACRH_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP1), uint32_t) & BM_AIPS_PACRH_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP1 (26U) //!< Bit position for AIPS_PACRH_SP1. -#define BM_AIPS_PACRH_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRH_SP1. -#define BS_AIPS_PACRH_SP1 (1U) //!< Bit field size in bits for AIPS_PACRH_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP1 field. -#define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP1. -#define BF_AIPS_PACRH_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP1), uint32_t) & BM_AIPS_PACRH_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRH_TP0 (28U) //!< Bit position for AIPS_PACRH_TP0. -#define BM_AIPS_PACRH_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRH_TP0. -#define BS_AIPS_PACRH_TP0 (1U) //!< Bit field size in bits for AIPS_PACRH_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_TP0 field. -#define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_TP0. -#define BF_AIPS_PACRH_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP0), uint32_t) & BM_AIPS_PACRH_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRH_WP0 (29U) //!< Bit position for AIPS_PACRH_WP0. -#define BM_AIPS_PACRH_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRH_WP0. -#define BS_AIPS_PACRH_WP0 (1U) //!< Bit field size in bits for AIPS_PACRH_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_WP0 field. -#define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_WP0. -#define BF_AIPS_PACRH_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP0), uint32_t) & BM_AIPS_PACRH_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRH, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRH_SP0 (30U) //!< Bit position for AIPS_PACRH_SP0. -#define BM_AIPS_PACRH_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRH_SP0. -#define BS_AIPS_PACRH_SP0 (1U) //!< Bit field size in bits for AIPS_PACRH_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRH_SP0 field. -#define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRH_SP0. -#define BF_AIPS_PACRH_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP0), uint32_t) & BM_AIPS_PACRH_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRI - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacri -{ - uint32_t U; - struct _hw_aips_pacri_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacri_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRI register - */ -//@{ -#define HW_AIPS_PACRI_ADDR(x) (REGS_AIPS_BASE(x) + 0x50U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x)) -#define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U) -#define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v)) -#define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v))) -#define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v))) -#define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRI bitfields - */ - -/*! - * @name Register AIPS_PACRI, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP7 (0U) //!< Bit position for AIPS_PACRI_TP7. -#define BM_AIPS_PACRI_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRI_TP7. -#define BS_AIPS_PACRI_TP7 (1U) //!< Bit field size in bits for AIPS_PACRI_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP7 field. -#define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP7. -#define BF_AIPS_PACRI_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP7), uint32_t) & BM_AIPS_PACRI_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP7 (1U) //!< Bit position for AIPS_PACRI_WP7. -#define BM_AIPS_PACRI_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRI_WP7. -#define BS_AIPS_PACRI_WP7 (1U) //!< Bit field size in bits for AIPS_PACRI_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP7 field. -#define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP7. -#define BF_AIPS_PACRI_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP7), uint32_t) & BM_AIPS_PACRI_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP7 (2U) //!< Bit position for AIPS_PACRI_SP7. -#define BM_AIPS_PACRI_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRI_SP7. -#define BS_AIPS_PACRI_SP7 (1U) //!< Bit field size in bits for AIPS_PACRI_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP7 field. -#define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP7. -#define BF_AIPS_PACRI_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP7), uint32_t) & BM_AIPS_PACRI_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP6 (4U) //!< Bit position for AIPS_PACRI_TP6. -#define BM_AIPS_PACRI_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRI_TP6. -#define BS_AIPS_PACRI_TP6 (1U) //!< Bit field size in bits for AIPS_PACRI_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP6 field. -#define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP6. -#define BF_AIPS_PACRI_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP6), uint32_t) & BM_AIPS_PACRI_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP6 (5U) //!< Bit position for AIPS_PACRI_WP6. -#define BM_AIPS_PACRI_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRI_WP6. -#define BS_AIPS_PACRI_WP6 (1U) //!< Bit field size in bits for AIPS_PACRI_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP6 field. -#define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP6. -#define BF_AIPS_PACRI_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP6), uint32_t) & BM_AIPS_PACRI_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP6 (6U) //!< Bit position for AIPS_PACRI_SP6. -#define BM_AIPS_PACRI_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRI_SP6. -#define BS_AIPS_PACRI_SP6 (1U) //!< Bit field size in bits for AIPS_PACRI_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP6 field. -#define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP6. -#define BF_AIPS_PACRI_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP6), uint32_t) & BM_AIPS_PACRI_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP5 (8U) //!< Bit position for AIPS_PACRI_TP5. -#define BM_AIPS_PACRI_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRI_TP5. -#define BS_AIPS_PACRI_TP5 (1U) //!< Bit field size in bits for AIPS_PACRI_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP5 field. -#define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP5. -#define BF_AIPS_PACRI_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP5), uint32_t) & BM_AIPS_PACRI_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP5 (9U) //!< Bit position for AIPS_PACRI_WP5. -#define BM_AIPS_PACRI_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRI_WP5. -#define BS_AIPS_PACRI_WP5 (1U) //!< Bit field size in bits for AIPS_PACRI_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP5 field. -#define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP5. -#define BF_AIPS_PACRI_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP5), uint32_t) & BM_AIPS_PACRI_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP5 (10U) //!< Bit position for AIPS_PACRI_SP5. -#define BM_AIPS_PACRI_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRI_SP5. -#define BS_AIPS_PACRI_SP5 (1U) //!< Bit field size in bits for AIPS_PACRI_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP5 field. -#define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP5. -#define BF_AIPS_PACRI_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP5), uint32_t) & BM_AIPS_PACRI_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP4 (12U) //!< Bit position for AIPS_PACRI_TP4. -#define BM_AIPS_PACRI_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRI_TP4. -#define BS_AIPS_PACRI_TP4 (1U) //!< Bit field size in bits for AIPS_PACRI_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP4 field. -#define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP4. -#define BF_AIPS_PACRI_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP4), uint32_t) & BM_AIPS_PACRI_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP4 (13U) //!< Bit position for AIPS_PACRI_WP4. -#define BM_AIPS_PACRI_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRI_WP4. -#define BS_AIPS_PACRI_WP4 (1U) //!< Bit field size in bits for AIPS_PACRI_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP4 field. -#define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP4. -#define BF_AIPS_PACRI_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP4), uint32_t) & BM_AIPS_PACRI_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP4 (14U) //!< Bit position for AIPS_PACRI_SP4. -#define BM_AIPS_PACRI_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRI_SP4. -#define BS_AIPS_PACRI_SP4 (1U) //!< Bit field size in bits for AIPS_PACRI_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP4 field. -#define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP4. -#define BF_AIPS_PACRI_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP4), uint32_t) & BM_AIPS_PACRI_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP3 (16U) //!< Bit position for AIPS_PACRI_TP3. -#define BM_AIPS_PACRI_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRI_TP3. -#define BS_AIPS_PACRI_TP3 (1U) //!< Bit field size in bits for AIPS_PACRI_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP3 field. -#define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP3. -#define BF_AIPS_PACRI_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP3), uint32_t) & BM_AIPS_PACRI_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP3 (17U) //!< Bit position for AIPS_PACRI_WP3. -#define BM_AIPS_PACRI_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRI_WP3. -#define BS_AIPS_PACRI_WP3 (1U) //!< Bit field size in bits for AIPS_PACRI_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP3 field. -#define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP3. -#define BF_AIPS_PACRI_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP3), uint32_t) & BM_AIPS_PACRI_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP3 (18U) //!< Bit position for AIPS_PACRI_SP3. -#define BM_AIPS_PACRI_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRI_SP3. -#define BS_AIPS_PACRI_SP3 (1U) //!< Bit field size in bits for AIPS_PACRI_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP3 field. -#define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP3. -#define BF_AIPS_PACRI_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP3), uint32_t) & BM_AIPS_PACRI_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP2 (20U) //!< Bit position for AIPS_PACRI_TP2. -#define BM_AIPS_PACRI_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRI_TP2. -#define BS_AIPS_PACRI_TP2 (1U) //!< Bit field size in bits for AIPS_PACRI_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP2 field. -#define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP2. -#define BF_AIPS_PACRI_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP2), uint32_t) & BM_AIPS_PACRI_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP2 (21U) //!< Bit position for AIPS_PACRI_WP2. -#define BM_AIPS_PACRI_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRI_WP2. -#define BS_AIPS_PACRI_WP2 (1U) //!< Bit field size in bits for AIPS_PACRI_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP2 field. -#define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP2. -#define BF_AIPS_PACRI_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP2), uint32_t) & BM_AIPS_PACRI_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP2 (22U) //!< Bit position for AIPS_PACRI_SP2. -#define BM_AIPS_PACRI_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRI_SP2. -#define BS_AIPS_PACRI_SP2 (1U) //!< Bit field size in bits for AIPS_PACRI_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP2 field. -#define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP2. -#define BF_AIPS_PACRI_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP2), uint32_t) & BM_AIPS_PACRI_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP1 (24U) //!< Bit position for AIPS_PACRI_TP1. -#define BM_AIPS_PACRI_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRI_TP1. -#define BS_AIPS_PACRI_TP1 (1U) //!< Bit field size in bits for AIPS_PACRI_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP1 field. -#define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP1. -#define BF_AIPS_PACRI_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP1), uint32_t) & BM_AIPS_PACRI_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP1 (25U) //!< Bit position for AIPS_PACRI_WP1. -#define BM_AIPS_PACRI_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRI_WP1. -#define BS_AIPS_PACRI_WP1 (1U) //!< Bit field size in bits for AIPS_PACRI_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP1 field. -#define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP1. -#define BF_AIPS_PACRI_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP1), uint32_t) & BM_AIPS_PACRI_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP1 (26U) //!< Bit position for AIPS_PACRI_SP1. -#define BM_AIPS_PACRI_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRI_SP1. -#define BS_AIPS_PACRI_SP1 (1U) //!< Bit field size in bits for AIPS_PACRI_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP1 field. -#define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP1. -#define BF_AIPS_PACRI_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP1), uint32_t) & BM_AIPS_PACRI_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRI_TP0 (28U) //!< Bit position for AIPS_PACRI_TP0. -#define BM_AIPS_PACRI_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRI_TP0. -#define BS_AIPS_PACRI_TP0 (1U) //!< Bit field size in bits for AIPS_PACRI_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_TP0 field. -#define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_TP0. -#define BF_AIPS_PACRI_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP0), uint32_t) & BM_AIPS_PACRI_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRI_WP0 (29U) //!< Bit position for AIPS_PACRI_WP0. -#define BM_AIPS_PACRI_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRI_WP0. -#define BS_AIPS_PACRI_WP0 (1U) //!< Bit field size in bits for AIPS_PACRI_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_WP0 field. -#define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_WP0. -#define BF_AIPS_PACRI_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP0), uint32_t) & BM_AIPS_PACRI_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRI, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRI_SP0 (30U) //!< Bit position for AIPS_PACRI_SP0. -#define BM_AIPS_PACRI_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRI_SP0. -#define BS_AIPS_PACRI_SP0 (1U) //!< Bit field size in bits for AIPS_PACRI_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRI_SP0 field. -#define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRI_SP0. -#define BF_AIPS_PACRI_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP0), uint32_t) & BM_AIPS_PACRI_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRJ - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrj -{ - uint32_t U; - struct _hw_aips_pacrj_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrj_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRJ register - */ -//@{ -#define HW_AIPS_PACRJ_ADDR(x) (REGS_AIPS_BASE(x) + 0x54U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x)) -#define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U) -#define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v)) -#define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v))) -#define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v))) -#define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRJ bitfields - */ - -/*! - * @name Register AIPS_PACRJ, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP7 (0U) //!< Bit position for AIPS_PACRJ_TP7. -#define BM_AIPS_PACRJ_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRJ_TP7. -#define BS_AIPS_PACRJ_TP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP7 field. -#define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP7. -#define BF_AIPS_PACRJ_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP7), uint32_t) & BM_AIPS_PACRJ_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP7 (1U) //!< Bit position for AIPS_PACRJ_WP7. -#define BM_AIPS_PACRJ_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRJ_WP7. -#define BS_AIPS_PACRJ_WP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP7 field. -#define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP7. -#define BF_AIPS_PACRJ_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP7), uint32_t) & BM_AIPS_PACRJ_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP7 (2U) //!< Bit position for AIPS_PACRJ_SP7. -#define BM_AIPS_PACRJ_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRJ_SP7. -#define BS_AIPS_PACRJ_SP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP7 field. -#define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP7. -#define BF_AIPS_PACRJ_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP7), uint32_t) & BM_AIPS_PACRJ_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP6 (4U) //!< Bit position for AIPS_PACRJ_TP6. -#define BM_AIPS_PACRJ_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRJ_TP6. -#define BS_AIPS_PACRJ_TP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP6 field. -#define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP6. -#define BF_AIPS_PACRJ_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP6), uint32_t) & BM_AIPS_PACRJ_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP6 (5U) //!< Bit position for AIPS_PACRJ_WP6. -#define BM_AIPS_PACRJ_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRJ_WP6. -#define BS_AIPS_PACRJ_WP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP6 field. -#define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP6. -#define BF_AIPS_PACRJ_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP6), uint32_t) & BM_AIPS_PACRJ_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP6 (6U) //!< Bit position for AIPS_PACRJ_SP6. -#define BM_AIPS_PACRJ_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRJ_SP6. -#define BS_AIPS_PACRJ_SP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP6 field. -#define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP6. -#define BF_AIPS_PACRJ_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP6), uint32_t) & BM_AIPS_PACRJ_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP5 (8U) //!< Bit position for AIPS_PACRJ_TP5. -#define BM_AIPS_PACRJ_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRJ_TP5. -#define BS_AIPS_PACRJ_TP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP5 field. -#define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP5. -#define BF_AIPS_PACRJ_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP5), uint32_t) & BM_AIPS_PACRJ_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP5 (9U) //!< Bit position for AIPS_PACRJ_WP5. -#define BM_AIPS_PACRJ_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRJ_WP5. -#define BS_AIPS_PACRJ_WP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP5 field. -#define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP5. -#define BF_AIPS_PACRJ_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP5), uint32_t) & BM_AIPS_PACRJ_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP5 (10U) //!< Bit position for AIPS_PACRJ_SP5. -#define BM_AIPS_PACRJ_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRJ_SP5. -#define BS_AIPS_PACRJ_SP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP5 field. -#define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP5. -#define BF_AIPS_PACRJ_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP5), uint32_t) & BM_AIPS_PACRJ_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP4 (12U) //!< Bit position for AIPS_PACRJ_TP4. -#define BM_AIPS_PACRJ_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRJ_TP4. -#define BS_AIPS_PACRJ_TP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP4 field. -#define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP4. -#define BF_AIPS_PACRJ_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP4), uint32_t) & BM_AIPS_PACRJ_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP4 (13U) //!< Bit position for AIPS_PACRJ_WP4. -#define BM_AIPS_PACRJ_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRJ_WP4. -#define BS_AIPS_PACRJ_WP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP4 field. -#define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP4. -#define BF_AIPS_PACRJ_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP4), uint32_t) & BM_AIPS_PACRJ_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP4 (14U) //!< Bit position for AIPS_PACRJ_SP4. -#define BM_AIPS_PACRJ_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRJ_SP4. -#define BS_AIPS_PACRJ_SP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP4 field. -#define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP4. -#define BF_AIPS_PACRJ_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP4), uint32_t) & BM_AIPS_PACRJ_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP3 (16U) //!< Bit position for AIPS_PACRJ_TP3. -#define BM_AIPS_PACRJ_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRJ_TP3. -#define BS_AIPS_PACRJ_TP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP3 field. -#define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP3. -#define BF_AIPS_PACRJ_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP3), uint32_t) & BM_AIPS_PACRJ_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP3 (17U) //!< Bit position for AIPS_PACRJ_WP3. -#define BM_AIPS_PACRJ_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRJ_WP3. -#define BS_AIPS_PACRJ_WP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP3 field. -#define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP3. -#define BF_AIPS_PACRJ_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP3), uint32_t) & BM_AIPS_PACRJ_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP3 (18U) //!< Bit position for AIPS_PACRJ_SP3. -#define BM_AIPS_PACRJ_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRJ_SP3. -#define BS_AIPS_PACRJ_SP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP3 field. -#define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP3. -#define BF_AIPS_PACRJ_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP3), uint32_t) & BM_AIPS_PACRJ_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP2 (20U) //!< Bit position for AIPS_PACRJ_TP2. -#define BM_AIPS_PACRJ_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRJ_TP2. -#define BS_AIPS_PACRJ_TP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP2 field. -#define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP2. -#define BF_AIPS_PACRJ_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP2), uint32_t) & BM_AIPS_PACRJ_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP2 (21U) //!< Bit position for AIPS_PACRJ_WP2. -#define BM_AIPS_PACRJ_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRJ_WP2. -#define BS_AIPS_PACRJ_WP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP2 field. -#define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP2. -#define BF_AIPS_PACRJ_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP2), uint32_t) & BM_AIPS_PACRJ_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP2 (22U) //!< Bit position for AIPS_PACRJ_SP2. -#define BM_AIPS_PACRJ_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRJ_SP2. -#define BS_AIPS_PACRJ_SP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP2 field. -#define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP2. -#define BF_AIPS_PACRJ_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP2), uint32_t) & BM_AIPS_PACRJ_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP1 (24U) //!< Bit position for AIPS_PACRJ_TP1. -#define BM_AIPS_PACRJ_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRJ_TP1. -#define BS_AIPS_PACRJ_TP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP1 field. -#define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP1. -#define BF_AIPS_PACRJ_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP1), uint32_t) & BM_AIPS_PACRJ_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP1 (25U) //!< Bit position for AIPS_PACRJ_WP1. -#define BM_AIPS_PACRJ_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRJ_WP1. -#define BS_AIPS_PACRJ_WP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP1 field. -#define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP1. -#define BF_AIPS_PACRJ_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP1), uint32_t) & BM_AIPS_PACRJ_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP1 (26U) //!< Bit position for AIPS_PACRJ_SP1. -#define BM_AIPS_PACRJ_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRJ_SP1. -#define BS_AIPS_PACRJ_SP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP1 field. -#define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP1. -#define BF_AIPS_PACRJ_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP1), uint32_t) & BM_AIPS_PACRJ_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRJ_TP0 (28U) //!< Bit position for AIPS_PACRJ_TP0. -#define BM_AIPS_PACRJ_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRJ_TP0. -#define BS_AIPS_PACRJ_TP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_TP0 field. -#define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_TP0. -#define BF_AIPS_PACRJ_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP0), uint32_t) & BM_AIPS_PACRJ_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRJ_WP0 (29U) //!< Bit position for AIPS_PACRJ_WP0. -#define BM_AIPS_PACRJ_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRJ_WP0. -#define BS_AIPS_PACRJ_WP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_WP0 field. -#define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_WP0. -#define BF_AIPS_PACRJ_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP0), uint32_t) & BM_AIPS_PACRJ_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRJ, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRJ_SP0 (30U) //!< Bit position for AIPS_PACRJ_SP0. -#define BM_AIPS_PACRJ_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRJ_SP0. -#define BS_AIPS_PACRJ_SP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRJ_SP0 field. -#define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRJ_SP0. -#define BF_AIPS_PACRJ_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP0), uint32_t) & BM_AIPS_PACRJ_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRK - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrk -{ - uint32_t U; - struct _hw_aips_pacrk_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrk_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRK register - */ -//@{ -#define HW_AIPS_PACRK_ADDR(x) (REGS_AIPS_BASE(x) + 0x58U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x)) -#define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U) -#define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v)) -#define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v))) -#define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v))) -#define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRK bitfields - */ - -/*! - * @name Register AIPS_PACRK, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP7 (0U) //!< Bit position for AIPS_PACRK_TP7. -#define BM_AIPS_PACRK_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRK_TP7. -#define BS_AIPS_PACRK_TP7 (1U) //!< Bit field size in bits for AIPS_PACRK_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP7 field. -#define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP7. -#define BF_AIPS_PACRK_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP7), uint32_t) & BM_AIPS_PACRK_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP7 (1U) //!< Bit position for AIPS_PACRK_WP7. -#define BM_AIPS_PACRK_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRK_WP7. -#define BS_AIPS_PACRK_WP7 (1U) //!< Bit field size in bits for AIPS_PACRK_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP7 field. -#define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP7. -#define BF_AIPS_PACRK_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP7), uint32_t) & BM_AIPS_PACRK_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP7 (2U) //!< Bit position for AIPS_PACRK_SP7. -#define BM_AIPS_PACRK_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRK_SP7. -#define BS_AIPS_PACRK_SP7 (1U) //!< Bit field size in bits for AIPS_PACRK_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP7 field. -#define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP7. -#define BF_AIPS_PACRK_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP7), uint32_t) & BM_AIPS_PACRK_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP6 (4U) //!< Bit position for AIPS_PACRK_TP6. -#define BM_AIPS_PACRK_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRK_TP6. -#define BS_AIPS_PACRK_TP6 (1U) //!< Bit field size in bits for AIPS_PACRK_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP6 field. -#define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP6. -#define BF_AIPS_PACRK_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP6), uint32_t) & BM_AIPS_PACRK_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP6 (5U) //!< Bit position for AIPS_PACRK_WP6. -#define BM_AIPS_PACRK_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRK_WP6. -#define BS_AIPS_PACRK_WP6 (1U) //!< Bit field size in bits for AIPS_PACRK_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP6 field. -#define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP6. -#define BF_AIPS_PACRK_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP6), uint32_t) & BM_AIPS_PACRK_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP6 (6U) //!< Bit position for AIPS_PACRK_SP6. -#define BM_AIPS_PACRK_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRK_SP6. -#define BS_AIPS_PACRK_SP6 (1U) //!< Bit field size in bits for AIPS_PACRK_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP6 field. -#define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP6. -#define BF_AIPS_PACRK_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP6), uint32_t) & BM_AIPS_PACRK_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP5 (8U) //!< Bit position for AIPS_PACRK_TP5. -#define BM_AIPS_PACRK_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRK_TP5. -#define BS_AIPS_PACRK_TP5 (1U) //!< Bit field size in bits for AIPS_PACRK_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP5 field. -#define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP5. -#define BF_AIPS_PACRK_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP5), uint32_t) & BM_AIPS_PACRK_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP5 (9U) //!< Bit position for AIPS_PACRK_WP5. -#define BM_AIPS_PACRK_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRK_WP5. -#define BS_AIPS_PACRK_WP5 (1U) //!< Bit field size in bits for AIPS_PACRK_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP5 field. -#define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP5. -#define BF_AIPS_PACRK_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP5), uint32_t) & BM_AIPS_PACRK_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP5 (10U) //!< Bit position for AIPS_PACRK_SP5. -#define BM_AIPS_PACRK_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRK_SP5. -#define BS_AIPS_PACRK_SP5 (1U) //!< Bit field size in bits for AIPS_PACRK_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP5 field. -#define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP5. -#define BF_AIPS_PACRK_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP5), uint32_t) & BM_AIPS_PACRK_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP4 (12U) //!< Bit position for AIPS_PACRK_TP4. -#define BM_AIPS_PACRK_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRK_TP4. -#define BS_AIPS_PACRK_TP4 (1U) //!< Bit field size in bits for AIPS_PACRK_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP4 field. -#define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP4. -#define BF_AIPS_PACRK_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP4), uint32_t) & BM_AIPS_PACRK_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP4 (13U) //!< Bit position for AIPS_PACRK_WP4. -#define BM_AIPS_PACRK_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRK_WP4. -#define BS_AIPS_PACRK_WP4 (1U) //!< Bit field size in bits for AIPS_PACRK_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP4 field. -#define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP4. -#define BF_AIPS_PACRK_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP4), uint32_t) & BM_AIPS_PACRK_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP4 (14U) //!< Bit position for AIPS_PACRK_SP4. -#define BM_AIPS_PACRK_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRK_SP4. -#define BS_AIPS_PACRK_SP4 (1U) //!< Bit field size in bits for AIPS_PACRK_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP4 field. -#define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP4. -#define BF_AIPS_PACRK_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP4), uint32_t) & BM_AIPS_PACRK_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP3 (16U) //!< Bit position for AIPS_PACRK_TP3. -#define BM_AIPS_PACRK_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRK_TP3. -#define BS_AIPS_PACRK_TP3 (1U) //!< Bit field size in bits for AIPS_PACRK_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP3 field. -#define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP3. -#define BF_AIPS_PACRK_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP3), uint32_t) & BM_AIPS_PACRK_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP3 (17U) //!< Bit position for AIPS_PACRK_WP3. -#define BM_AIPS_PACRK_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRK_WP3. -#define BS_AIPS_PACRK_WP3 (1U) //!< Bit field size in bits for AIPS_PACRK_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP3 field. -#define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP3. -#define BF_AIPS_PACRK_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP3), uint32_t) & BM_AIPS_PACRK_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP3 (18U) //!< Bit position for AIPS_PACRK_SP3. -#define BM_AIPS_PACRK_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRK_SP3. -#define BS_AIPS_PACRK_SP3 (1U) //!< Bit field size in bits for AIPS_PACRK_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP3 field. -#define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP3. -#define BF_AIPS_PACRK_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP3), uint32_t) & BM_AIPS_PACRK_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP2 (20U) //!< Bit position for AIPS_PACRK_TP2. -#define BM_AIPS_PACRK_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRK_TP2. -#define BS_AIPS_PACRK_TP2 (1U) //!< Bit field size in bits for AIPS_PACRK_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP2 field. -#define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP2. -#define BF_AIPS_PACRK_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP2), uint32_t) & BM_AIPS_PACRK_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP2 (21U) //!< Bit position for AIPS_PACRK_WP2. -#define BM_AIPS_PACRK_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRK_WP2. -#define BS_AIPS_PACRK_WP2 (1U) //!< Bit field size in bits for AIPS_PACRK_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP2 field. -#define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP2. -#define BF_AIPS_PACRK_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP2), uint32_t) & BM_AIPS_PACRK_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP2 (22U) //!< Bit position for AIPS_PACRK_SP2. -#define BM_AIPS_PACRK_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRK_SP2. -#define BS_AIPS_PACRK_SP2 (1U) //!< Bit field size in bits for AIPS_PACRK_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP2 field. -#define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP2. -#define BF_AIPS_PACRK_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP2), uint32_t) & BM_AIPS_PACRK_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP1 (24U) //!< Bit position for AIPS_PACRK_TP1. -#define BM_AIPS_PACRK_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRK_TP1. -#define BS_AIPS_PACRK_TP1 (1U) //!< Bit field size in bits for AIPS_PACRK_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP1 field. -#define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP1. -#define BF_AIPS_PACRK_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP1), uint32_t) & BM_AIPS_PACRK_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP1 (25U) //!< Bit position for AIPS_PACRK_WP1. -#define BM_AIPS_PACRK_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRK_WP1. -#define BS_AIPS_PACRK_WP1 (1U) //!< Bit field size in bits for AIPS_PACRK_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP1 field. -#define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP1. -#define BF_AIPS_PACRK_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP1), uint32_t) & BM_AIPS_PACRK_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP1 (26U) //!< Bit position for AIPS_PACRK_SP1. -#define BM_AIPS_PACRK_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRK_SP1. -#define BS_AIPS_PACRK_SP1 (1U) //!< Bit field size in bits for AIPS_PACRK_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP1 field. -#define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP1. -#define BF_AIPS_PACRK_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP1), uint32_t) & BM_AIPS_PACRK_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRK_TP0 (28U) //!< Bit position for AIPS_PACRK_TP0. -#define BM_AIPS_PACRK_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRK_TP0. -#define BS_AIPS_PACRK_TP0 (1U) //!< Bit field size in bits for AIPS_PACRK_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_TP0 field. -#define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_TP0. -#define BF_AIPS_PACRK_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP0), uint32_t) & BM_AIPS_PACRK_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRK_WP0 (29U) //!< Bit position for AIPS_PACRK_WP0. -#define BM_AIPS_PACRK_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRK_WP0. -#define BS_AIPS_PACRK_WP0 (1U) //!< Bit field size in bits for AIPS_PACRK_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_WP0 field. -#define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_WP0. -#define BF_AIPS_PACRK_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP0), uint32_t) & BM_AIPS_PACRK_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRK, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRK_SP0 (30U) //!< Bit position for AIPS_PACRK_SP0. -#define BM_AIPS_PACRK_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRK_SP0. -#define BS_AIPS_PACRK_SP0 (1U) //!< Bit field size in bits for AIPS_PACRK_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRK_SP0 field. -#define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRK_SP0. -#define BF_AIPS_PACRK_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP0), uint32_t) & BM_AIPS_PACRK_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRL - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrl -{ - uint32_t U; - struct _hw_aips_pacrl_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrl_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRL register - */ -//@{ -#define HW_AIPS_PACRL_ADDR(x) (REGS_AIPS_BASE(x) + 0x5CU) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x)) -#define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U) -#define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v)) -#define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v))) -#define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v))) -#define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRL bitfields - */ - -/*! - * @name Register AIPS_PACRL, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP7 (0U) //!< Bit position for AIPS_PACRL_TP7. -#define BM_AIPS_PACRL_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRL_TP7. -#define BS_AIPS_PACRL_TP7 (1U) //!< Bit field size in bits for AIPS_PACRL_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP7 field. -#define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP7. -#define BF_AIPS_PACRL_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP7), uint32_t) & BM_AIPS_PACRL_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP7 (1U) //!< Bit position for AIPS_PACRL_WP7. -#define BM_AIPS_PACRL_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRL_WP7. -#define BS_AIPS_PACRL_WP7 (1U) //!< Bit field size in bits for AIPS_PACRL_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP7 field. -#define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP7. -#define BF_AIPS_PACRL_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP7), uint32_t) & BM_AIPS_PACRL_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP7 (2U) //!< Bit position for AIPS_PACRL_SP7. -#define BM_AIPS_PACRL_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRL_SP7. -#define BS_AIPS_PACRL_SP7 (1U) //!< Bit field size in bits for AIPS_PACRL_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP7 field. -#define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP7. -#define BF_AIPS_PACRL_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP7), uint32_t) & BM_AIPS_PACRL_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP6 (4U) //!< Bit position for AIPS_PACRL_TP6. -#define BM_AIPS_PACRL_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRL_TP6. -#define BS_AIPS_PACRL_TP6 (1U) //!< Bit field size in bits for AIPS_PACRL_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP6 field. -#define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP6. -#define BF_AIPS_PACRL_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP6), uint32_t) & BM_AIPS_PACRL_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP6 (5U) //!< Bit position for AIPS_PACRL_WP6. -#define BM_AIPS_PACRL_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRL_WP6. -#define BS_AIPS_PACRL_WP6 (1U) //!< Bit field size in bits for AIPS_PACRL_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP6 field. -#define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP6. -#define BF_AIPS_PACRL_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP6), uint32_t) & BM_AIPS_PACRL_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP6 (6U) //!< Bit position for AIPS_PACRL_SP6. -#define BM_AIPS_PACRL_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRL_SP6. -#define BS_AIPS_PACRL_SP6 (1U) //!< Bit field size in bits for AIPS_PACRL_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP6 field. -#define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP6. -#define BF_AIPS_PACRL_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP6), uint32_t) & BM_AIPS_PACRL_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP5 (8U) //!< Bit position for AIPS_PACRL_TP5. -#define BM_AIPS_PACRL_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRL_TP5. -#define BS_AIPS_PACRL_TP5 (1U) //!< Bit field size in bits for AIPS_PACRL_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP5 field. -#define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP5. -#define BF_AIPS_PACRL_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP5), uint32_t) & BM_AIPS_PACRL_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP5 (9U) //!< Bit position for AIPS_PACRL_WP5. -#define BM_AIPS_PACRL_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRL_WP5. -#define BS_AIPS_PACRL_WP5 (1U) //!< Bit field size in bits for AIPS_PACRL_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP5 field. -#define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP5. -#define BF_AIPS_PACRL_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP5), uint32_t) & BM_AIPS_PACRL_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP5 (10U) //!< Bit position for AIPS_PACRL_SP5. -#define BM_AIPS_PACRL_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRL_SP5. -#define BS_AIPS_PACRL_SP5 (1U) //!< Bit field size in bits for AIPS_PACRL_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP5 field. -#define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP5. -#define BF_AIPS_PACRL_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP5), uint32_t) & BM_AIPS_PACRL_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP4 (12U) //!< Bit position for AIPS_PACRL_TP4. -#define BM_AIPS_PACRL_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRL_TP4. -#define BS_AIPS_PACRL_TP4 (1U) //!< Bit field size in bits for AIPS_PACRL_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP4 field. -#define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP4. -#define BF_AIPS_PACRL_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP4), uint32_t) & BM_AIPS_PACRL_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP4 (13U) //!< Bit position for AIPS_PACRL_WP4. -#define BM_AIPS_PACRL_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRL_WP4. -#define BS_AIPS_PACRL_WP4 (1U) //!< Bit field size in bits for AIPS_PACRL_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP4 field. -#define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP4. -#define BF_AIPS_PACRL_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP4), uint32_t) & BM_AIPS_PACRL_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP4 (14U) //!< Bit position for AIPS_PACRL_SP4. -#define BM_AIPS_PACRL_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRL_SP4. -#define BS_AIPS_PACRL_SP4 (1U) //!< Bit field size in bits for AIPS_PACRL_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP4 field. -#define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP4. -#define BF_AIPS_PACRL_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP4), uint32_t) & BM_AIPS_PACRL_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP3 (16U) //!< Bit position for AIPS_PACRL_TP3. -#define BM_AIPS_PACRL_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRL_TP3. -#define BS_AIPS_PACRL_TP3 (1U) //!< Bit field size in bits for AIPS_PACRL_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP3 field. -#define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP3. -#define BF_AIPS_PACRL_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP3), uint32_t) & BM_AIPS_PACRL_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP3 (17U) //!< Bit position for AIPS_PACRL_WP3. -#define BM_AIPS_PACRL_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRL_WP3. -#define BS_AIPS_PACRL_WP3 (1U) //!< Bit field size in bits for AIPS_PACRL_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP3 field. -#define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP3. -#define BF_AIPS_PACRL_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP3), uint32_t) & BM_AIPS_PACRL_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP3 (18U) //!< Bit position for AIPS_PACRL_SP3. -#define BM_AIPS_PACRL_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRL_SP3. -#define BS_AIPS_PACRL_SP3 (1U) //!< Bit field size in bits for AIPS_PACRL_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP3 field. -#define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP3. -#define BF_AIPS_PACRL_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP3), uint32_t) & BM_AIPS_PACRL_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP2 (20U) //!< Bit position for AIPS_PACRL_TP2. -#define BM_AIPS_PACRL_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRL_TP2. -#define BS_AIPS_PACRL_TP2 (1U) //!< Bit field size in bits for AIPS_PACRL_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP2 field. -#define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP2. -#define BF_AIPS_PACRL_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP2), uint32_t) & BM_AIPS_PACRL_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP2 (21U) //!< Bit position for AIPS_PACRL_WP2. -#define BM_AIPS_PACRL_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRL_WP2. -#define BS_AIPS_PACRL_WP2 (1U) //!< Bit field size in bits for AIPS_PACRL_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP2 field. -#define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP2. -#define BF_AIPS_PACRL_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP2), uint32_t) & BM_AIPS_PACRL_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP2 (22U) //!< Bit position for AIPS_PACRL_SP2. -#define BM_AIPS_PACRL_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRL_SP2. -#define BS_AIPS_PACRL_SP2 (1U) //!< Bit field size in bits for AIPS_PACRL_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP2 field. -#define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP2. -#define BF_AIPS_PACRL_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP2), uint32_t) & BM_AIPS_PACRL_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP1 (24U) //!< Bit position for AIPS_PACRL_TP1. -#define BM_AIPS_PACRL_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRL_TP1. -#define BS_AIPS_PACRL_TP1 (1U) //!< Bit field size in bits for AIPS_PACRL_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP1 field. -#define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP1. -#define BF_AIPS_PACRL_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP1), uint32_t) & BM_AIPS_PACRL_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP1 (25U) //!< Bit position for AIPS_PACRL_WP1. -#define BM_AIPS_PACRL_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRL_WP1. -#define BS_AIPS_PACRL_WP1 (1U) //!< Bit field size in bits for AIPS_PACRL_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP1 field. -#define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP1. -#define BF_AIPS_PACRL_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP1), uint32_t) & BM_AIPS_PACRL_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP1 (26U) //!< Bit position for AIPS_PACRL_SP1. -#define BM_AIPS_PACRL_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRL_SP1. -#define BS_AIPS_PACRL_SP1 (1U) //!< Bit field size in bits for AIPS_PACRL_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP1 field. -#define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP1. -#define BF_AIPS_PACRL_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP1), uint32_t) & BM_AIPS_PACRL_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRL_TP0 (28U) //!< Bit position for AIPS_PACRL_TP0. -#define BM_AIPS_PACRL_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRL_TP0. -#define BS_AIPS_PACRL_TP0 (1U) //!< Bit field size in bits for AIPS_PACRL_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_TP0 field. -#define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_TP0. -#define BF_AIPS_PACRL_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP0), uint32_t) & BM_AIPS_PACRL_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRL_WP0 (29U) //!< Bit position for AIPS_PACRL_WP0. -#define BM_AIPS_PACRL_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRL_WP0. -#define BS_AIPS_PACRL_WP0 (1U) //!< Bit field size in bits for AIPS_PACRL_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_WP0 field. -#define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_WP0. -#define BF_AIPS_PACRL_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP0), uint32_t) & BM_AIPS_PACRL_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRL, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRL_SP0 (30U) //!< Bit position for AIPS_PACRL_SP0. -#define BM_AIPS_PACRL_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRL_SP0. -#define BS_AIPS_PACRL_SP0 (1U) //!< Bit field size in bits for AIPS_PACRL_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRL_SP0 field. -#define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRL_SP0. -#define BF_AIPS_PACRL_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP0), uint32_t) & BM_AIPS_PACRL_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRM - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrm -{ - uint32_t U; - struct _hw_aips_pacrm_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrm_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRM register - */ -//@{ -#define HW_AIPS_PACRM_ADDR(x) (REGS_AIPS_BASE(x) + 0x60U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x)) -#define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U) -#define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v)) -#define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v))) -#define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v))) -#define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRM bitfields - */ - -/*! - * @name Register AIPS_PACRM, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP7 (0U) //!< Bit position for AIPS_PACRM_TP7. -#define BM_AIPS_PACRM_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRM_TP7. -#define BS_AIPS_PACRM_TP7 (1U) //!< Bit field size in bits for AIPS_PACRM_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP7 field. -#define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP7. -#define BF_AIPS_PACRM_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP7), uint32_t) & BM_AIPS_PACRM_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP7 (1U) //!< Bit position for AIPS_PACRM_WP7. -#define BM_AIPS_PACRM_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRM_WP7. -#define BS_AIPS_PACRM_WP7 (1U) //!< Bit field size in bits for AIPS_PACRM_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP7 field. -#define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP7. -#define BF_AIPS_PACRM_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP7), uint32_t) & BM_AIPS_PACRM_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP7 (2U) //!< Bit position for AIPS_PACRM_SP7. -#define BM_AIPS_PACRM_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRM_SP7. -#define BS_AIPS_PACRM_SP7 (1U) //!< Bit field size in bits for AIPS_PACRM_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP7 field. -#define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP7. -#define BF_AIPS_PACRM_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP7), uint32_t) & BM_AIPS_PACRM_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP6 (4U) //!< Bit position for AIPS_PACRM_TP6. -#define BM_AIPS_PACRM_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRM_TP6. -#define BS_AIPS_PACRM_TP6 (1U) //!< Bit field size in bits for AIPS_PACRM_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP6 field. -#define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP6. -#define BF_AIPS_PACRM_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP6), uint32_t) & BM_AIPS_PACRM_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP6 (5U) //!< Bit position for AIPS_PACRM_WP6. -#define BM_AIPS_PACRM_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRM_WP6. -#define BS_AIPS_PACRM_WP6 (1U) //!< Bit field size in bits for AIPS_PACRM_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP6 field. -#define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP6. -#define BF_AIPS_PACRM_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP6), uint32_t) & BM_AIPS_PACRM_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP6 (6U) //!< Bit position for AIPS_PACRM_SP6. -#define BM_AIPS_PACRM_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRM_SP6. -#define BS_AIPS_PACRM_SP6 (1U) //!< Bit field size in bits for AIPS_PACRM_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP6 field. -#define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP6. -#define BF_AIPS_PACRM_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP6), uint32_t) & BM_AIPS_PACRM_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP5 (8U) //!< Bit position for AIPS_PACRM_TP5. -#define BM_AIPS_PACRM_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRM_TP5. -#define BS_AIPS_PACRM_TP5 (1U) //!< Bit field size in bits for AIPS_PACRM_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP5 field. -#define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP5. -#define BF_AIPS_PACRM_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP5), uint32_t) & BM_AIPS_PACRM_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP5 (9U) //!< Bit position for AIPS_PACRM_WP5. -#define BM_AIPS_PACRM_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRM_WP5. -#define BS_AIPS_PACRM_WP5 (1U) //!< Bit field size in bits for AIPS_PACRM_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP5 field. -#define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP5. -#define BF_AIPS_PACRM_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP5), uint32_t) & BM_AIPS_PACRM_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP5 (10U) //!< Bit position for AIPS_PACRM_SP5. -#define BM_AIPS_PACRM_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRM_SP5. -#define BS_AIPS_PACRM_SP5 (1U) //!< Bit field size in bits for AIPS_PACRM_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP5 field. -#define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP5. -#define BF_AIPS_PACRM_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP5), uint32_t) & BM_AIPS_PACRM_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP4 (12U) //!< Bit position for AIPS_PACRM_TP4. -#define BM_AIPS_PACRM_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRM_TP4. -#define BS_AIPS_PACRM_TP4 (1U) //!< Bit field size in bits for AIPS_PACRM_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP4 field. -#define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP4. -#define BF_AIPS_PACRM_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP4), uint32_t) & BM_AIPS_PACRM_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP4 (13U) //!< Bit position for AIPS_PACRM_WP4. -#define BM_AIPS_PACRM_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRM_WP4. -#define BS_AIPS_PACRM_WP4 (1U) //!< Bit field size in bits for AIPS_PACRM_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP4 field. -#define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP4. -#define BF_AIPS_PACRM_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP4), uint32_t) & BM_AIPS_PACRM_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP4 (14U) //!< Bit position for AIPS_PACRM_SP4. -#define BM_AIPS_PACRM_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRM_SP4. -#define BS_AIPS_PACRM_SP4 (1U) //!< Bit field size in bits for AIPS_PACRM_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP4 field. -#define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP4. -#define BF_AIPS_PACRM_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP4), uint32_t) & BM_AIPS_PACRM_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP3 (16U) //!< Bit position for AIPS_PACRM_TP3. -#define BM_AIPS_PACRM_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRM_TP3. -#define BS_AIPS_PACRM_TP3 (1U) //!< Bit field size in bits for AIPS_PACRM_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP3 field. -#define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP3. -#define BF_AIPS_PACRM_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP3), uint32_t) & BM_AIPS_PACRM_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP3 (17U) //!< Bit position for AIPS_PACRM_WP3. -#define BM_AIPS_PACRM_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRM_WP3. -#define BS_AIPS_PACRM_WP3 (1U) //!< Bit field size in bits for AIPS_PACRM_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP3 field. -#define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP3. -#define BF_AIPS_PACRM_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP3), uint32_t) & BM_AIPS_PACRM_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP3 (18U) //!< Bit position for AIPS_PACRM_SP3. -#define BM_AIPS_PACRM_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRM_SP3. -#define BS_AIPS_PACRM_SP3 (1U) //!< Bit field size in bits for AIPS_PACRM_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP3 field. -#define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP3. -#define BF_AIPS_PACRM_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP3), uint32_t) & BM_AIPS_PACRM_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP2 (20U) //!< Bit position for AIPS_PACRM_TP2. -#define BM_AIPS_PACRM_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRM_TP2. -#define BS_AIPS_PACRM_TP2 (1U) //!< Bit field size in bits for AIPS_PACRM_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP2 field. -#define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP2. -#define BF_AIPS_PACRM_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP2), uint32_t) & BM_AIPS_PACRM_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP2 (21U) //!< Bit position for AIPS_PACRM_WP2. -#define BM_AIPS_PACRM_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRM_WP2. -#define BS_AIPS_PACRM_WP2 (1U) //!< Bit field size in bits for AIPS_PACRM_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP2 field. -#define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP2. -#define BF_AIPS_PACRM_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP2), uint32_t) & BM_AIPS_PACRM_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP2 (22U) //!< Bit position for AIPS_PACRM_SP2. -#define BM_AIPS_PACRM_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRM_SP2. -#define BS_AIPS_PACRM_SP2 (1U) //!< Bit field size in bits for AIPS_PACRM_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP2 field. -#define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP2. -#define BF_AIPS_PACRM_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP2), uint32_t) & BM_AIPS_PACRM_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP1 (24U) //!< Bit position for AIPS_PACRM_TP1. -#define BM_AIPS_PACRM_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRM_TP1. -#define BS_AIPS_PACRM_TP1 (1U) //!< Bit field size in bits for AIPS_PACRM_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP1 field. -#define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP1. -#define BF_AIPS_PACRM_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP1), uint32_t) & BM_AIPS_PACRM_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP1 (25U) //!< Bit position for AIPS_PACRM_WP1. -#define BM_AIPS_PACRM_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRM_WP1. -#define BS_AIPS_PACRM_WP1 (1U) //!< Bit field size in bits for AIPS_PACRM_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP1 field. -#define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP1. -#define BF_AIPS_PACRM_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP1), uint32_t) & BM_AIPS_PACRM_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP1 (26U) //!< Bit position for AIPS_PACRM_SP1. -#define BM_AIPS_PACRM_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRM_SP1. -#define BS_AIPS_PACRM_SP1 (1U) //!< Bit field size in bits for AIPS_PACRM_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP1 field. -#define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP1. -#define BF_AIPS_PACRM_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP1), uint32_t) & BM_AIPS_PACRM_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRM_TP0 (28U) //!< Bit position for AIPS_PACRM_TP0. -#define BM_AIPS_PACRM_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRM_TP0. -#define BS_AIPS_PACRM_TP0 (1U) //!< Bit field size in bits for AIPS_PACRM_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_TP0 field. -#define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_TP0. -#define BF_AIPS_PACRM_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP0), uint32_t) & BM_AIPS_PACRM_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRM_WP0 (29U) //!< Bit position for AIPS_PACRM_WP0. -#define BM_AIPS_PACRM_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRM_WP0. -#define BS_AIPS_PACRM_WP0 (1U) //!< Bit field size in bits for AIPS_PACRM_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_WP0 field. -#define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_WP0. -#define BF_AIPS_PACRM_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP0), uint32_t) & BM_AIPS_PACRM_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRM, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRM_SP0 (30U) //!< Bit position for AIPS_PACRM_SP0. -#define BM_AIPS_PACRM_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRM_SP0. -#define BS_AIPS_PACRM_SP0 (1U) //!< Bit field size in bits for AIPS_PACRM_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRM_SP0 field. -#define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRM_SP0. -#define BF_AIPS_PACRM_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP0), uint32_t) & BM_AIPS_PACRM_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRN - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrn -{ - uint32_t U; - struct _hw_aips_pacrn_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrn_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRN register - */ -//@{ -#define HW_AIPS_PACRN_ADDR(x) (REGS_AIPS_BASE(x) + 0x64U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x)) -#define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U) -#define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v)) -#define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v))) -#define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v))) -#define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRN bitfields - */ - -/*! - * @name Register AIPS_PACRN, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP7 (0U) //!< Bit position for AIPS_PACRN_TP7. -#define BM_AIPS_PACRN_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRN_TP7. -#define BS_AIPS_PACRN_TP7 (1U) //!< Bit field size in bits for AIPS_PACRN_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP7 field. -#define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP7. -#define BF_AIPS_PACRN_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP7), uint32_t) & BM_AIPS_PACRN_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP7 (1U) //!< Bit position for AIPS_PACRN_WP7. -#define BM_AIPS_PACRN_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRN_WP7. -#define BS_AIPS_PACRN_WP7 (1U) //!< Bit field size in bits for AIPS_PACRN_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP7 field. -#define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP7. -#define BF_AIPS_PACRN_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP7), uint32_t) & BM_AIPS_PACRN_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP7 (2U) //!< Bit position for AIPS_PACRN_SP7. -#define BM_AIPS_PACRN_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRN_SP7. -#define BS_AIPS_PACRN_SP7 (1U) //!< Bit field size in bits for AIPS_PACRN_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP7 field. -#define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP7. -#define BF_AIPS_PACRN_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP7), uint32_t) & BM_AIPS_PACRN_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP6 (4U) //!< Bit position for AIPS_PACRN_TP6. -#define BM_AIPS_PACRN_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRN_TP6. -#define BS_AIPS_PACRN_TP6 (1U) //!< Bit field size in bits for AIPS_PACRN_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP6 field. -#define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP6. -#define BF_AIPS_PACRN_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP6), uint32_t) & BM_AIPS_PACRN_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP6 (5U) //!< Bit position for AIPS_PACRN_WP6. -#define BM_AIPS_PACRN_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRN_WP6. -#define BS_AIPS_PACRN_WP6 (1U) //!< Bit field size in bits for AIPS_PACRN_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP6 field. -#define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP6. -#define BF_AIPS_PACRN_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP6), uint32_t) & BM_AIPS_PACRN_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP6 (6U) //!< Bit position for AIPS_PACRN_SP6. -#define BM_AIPS_PACRN_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRN_SP6. -#define BS_AIPS_PACRN_SP6 (1U) //!< Bit field size in bits for AIPS_PACRN_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP6 field. -#define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP6. -#define BF_AIPS_PACRN_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP6), uint32_t) & BM_AIPS_PACRN_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP5 (8U) //!< Bit position for AIPS_PACRN_TP5. -#define BM_AIPS_PACRN_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRN_TP5. -#define BS_AIPS_PACRN_TP5 (1U) //!< Bit field size in bits for AIPS_PACRN_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP5 field. -#define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP5. -#define BF_AIPS_PACRN_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP5), uint32_t) & BM_AIPS_PACRN_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP5 (9U) //!< Bit position for AIPS_PACRN_WP5. -#define BM_AIPS_PACRN_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRN_WP5. -#define BS_AIPS_PACRN_WP5 (1U) //!< Bit field size in bits for AIPS_PACRN_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP5 field. -#define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP5. -#define BF_AIPS_PACRN_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP5), uint32_t) & BM_AIPS_PACRN_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP5 (10U) //!< Bit position for AIPS_PACRN_SP5. -#define BM_AIPS_PACRN_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRN_SP5. -#define BS_AIPS_PACRN_SP5 (1U) //!< Bit field size in bits for AIPS_PACRN_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP5 field. -#define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP5. -#define BF_AIPS_PACRN_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP5), uint32_t) & BM_AIPS_PACRN_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP4 (12U) //!< Bit position for AIPS_PACRN_TP4. -#define BM_AIPS_PACRN_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRN_TP4. -#define BS_AIPS_PACRN_TP4 (1U) //!< Bit field size in bits for AIPS_PACRN_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP4 field. -#define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP4. -#define BF_AIPS_PACRN_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP4), uint32_t) & BM_AIPS_PACRN_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP4 (13U) //!< Bit position for AIPS_PACRN_WP4. -#define BM_AIPS_PACRN_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRN_WP4. -#define BS_AIPS_PACRN_WP4 (1U) //!< Bit field size in bits for AIPS_PACRN_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP4 field. -#define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP4. -#define BF_AIPS_PACRN_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP4), uint32_t) & BM_AIPS_PACRN_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP4 (14U) //!< Bit position for AIPS_PACRN_SP4. -#define BM_AIPS_PACRN_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRN_SP4. -#define BS_AIPS_PACRN_SP4 (1U) //!< Bit field size in bits for AIPS_PACRN_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP4 field. -#define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP4. -#define BF_AIPS_PACRN_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP4), uint32_t) & BM_AIPS_PACRN_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP3 (16U) //!< Bit position for AIPS_PACRN_TP3. -#define BM_AIPS_PACRN_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRN_TP3. -#define BS_AIPS_PACRN_TP3 (1U) //!< Bit field size in bits for AIPS_PACRN_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP3 field. -#define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP3. -#define BF_AIPS_PACRN_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP3), uint32_t) & BM_AIPS_PACRN_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP3 (17U) //!< Bit position for AIPS_PACRN_WP3. -#define BM_AIPS_PACRN_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRN_WP3. -#define BS_AIPS_PACRN_WP3 (1U) //!< Bit field size in bits for AIPS_PACRN_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP3 field. -#define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP3. -#define BF_AIPS_PACRN_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP3), uint32_t) & BM_AIPS_PACRN_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP3 (18U) //!< Bit position for AIPS_PACRN_SP3. -#define BM_AIPS_PACRN_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRN_SP3. -#define BS_AIPS_PACRN_SP3 (1U) //!< Bit field size in bits for AIPS_PACRN_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP3 field. -#define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP3. -#define BF_AIPS_PACRN_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP3), uint32_t) & BM_AIPS_PACRN_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP2 (20U) //!< Bit position for AIPS_PACRN_TP2. -#define BM_AIPS_PACRN_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRN_TP2. -#define BS_AIPS_PACRN_TP2 (1U) //!< Bit field size in bits for AIPS_PACRN_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP2 field. -#define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP2. -#define BF_AIPS_PACRN_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP2), uint32_t) & BM_AIPS_PACRN_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP2 (21U) //!< Bit position for AIPS_PACRN_WP2. -#define BM_AIPS_PACRN_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRN_WP2. -#define BS_AIPS_PACRN_WP2 (1U) //!< Bit field size in bits for AIPS_PACRN_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP2 field. -#define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP2. -#define BF_AIPS_PACRN_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP2), uint32_t) & BM_AIPS_PACRN_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP2 (22U) //!< Bit position for AIPS_PACRN_SP2. -#define BM_AIPS_PACRN_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRN_SP2. -#define BS_AIPS_PACRN_SP2 (1U) //!< Bit field size in bits for AIPS_PACRN_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP2 field. -#define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP2. -#define BF_AIPS_PACRN_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP2), uint32_t) & BM_AIPS_PACRN_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP1 (24U) //!< Bit position for AIPS_PACRN_TP1. -#define BM_AIPS_PACRN_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRN_TP1. -#define BS_AIPS_PACRN_TP1 (1U) //!< Bit field size in bits for AIPS_PACRN_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP1 field. -#define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP1. -#define BF_AIPS_PACRN_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP1), uint32_t) & BM_AIPS_PACRN_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP1 (25U) //!< Bit position for AIPS_PACRN_WP1. -#define BM_AIPS_PACRN_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRN_WP1. -#define BS_AIPS_PACRN_WP1 (1U) //!< Bit field size in bits for AIPS_PACRN_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP1 field. -#define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP1. -#define BF_AIPS_PACRN_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP1), uint32_t) & BM_AIPS_PACRN_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP1 (26U) //!< Bit position for AIPS_PACRN_SP1. -#define BM_AIPS_PACRN_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRN_SP1. -#define BS_AIPS_PACRN_SP1 (1U) //!< Bit field size in bits for AIPS_PACRN_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP1 field. -#define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP1. -#define BF_AIPS_PACRN_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP1), uint32_t) & BM_AIPS_PACRN_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRN_TP0 (28U) //!< Bit position for AIPS_PACRN_TP0. -#define BM_AIPS_PACRN_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRN_TP0. -#define BS_AIPS_PACRN_TP0 (1U) //!< Bit field size in bits for AIPS_PACRN_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_TP0 field. -#define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_TP0. -#define BF_AIPS_PACRN_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP0), uint32_t) & BM_AIPS_PACRN_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRN_WP0 (29U) //!< Bit position for AIPS_PACRN_WP0. -#define BM_AIPS_PACRN_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRN_WP0. -#define BS_AIPS_PACRN_WP0 (1U) //!< Bit field size in bits for AIPS_PACRN_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_WP0 field. -#define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_WP0. -#define BF_AIPS_PACRN_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP0), uint32_t) & BM_AIPS_PACRN_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRN, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRN_SP0 (30U) //!< Bit position for AIPS_PACRN_SP0. -#define BM_AIPS_PACRN_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRN_SP0. -#define BS_AIPS_PACRN_SP0 (1U) //!< Bit field size in bits for AIPS_PACRN_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRN_SP0 field. -#define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRN_SP0. -#define BF_AIPS_PACRN_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP0), uint32_t) & BM_AIPS_PACRN_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRO - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacro -{ - uint32_t U; - struct _hw_aips_pacro_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacro_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRO register - */ -//@{ -#define HW_AIPS_PACRO_ADDR(x) (REGS_AIPS_BASE(x) + 0x68U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x)) -#define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U) -#define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v)) -#define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v))) -#define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v))) -#define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRO bitfields - */ - -/*! - * @name Register AIPS_PACRO, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP7 (0U) //!< Bit position for AIPS_PACRO_TP7. -#define BM_AIPS_PACRO_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRO_TP7. -#define BS_AIPS_PACRO_TP7 (1U) //!< Bit field size in bits for AIPS_PACRO_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP7 field. -#define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP7. -#define BF_AIPS_PACRO_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP7), uint32_t) & BM_AIPS_PACRO_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP7 (1U) //!< Bit position for AIPS_PACRO_WP7. -#define BM_AIPS_PACRO_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRO_WP7. -#define BS_AIPS_PACRO_WP7 (1U) //!< Bit field size in bits for AIPS_PACRO_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP7 field. -#define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP7. -#define BF_AIPS_PACRO_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP7), uint32_t) & BM_AIPS_PACRO_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP7 (2U) //!< Bit position for AIPS_PACRO_SP7. -#define BM_AIPS_PACRO_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRO_SP7. -#define BS_AIPS_PACRO_SP7 (1U) //!< Bit field size in bits for AIPS_PACRO_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP7 field. -#define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP7. -#define BF_AIPS_PACRO_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP7), uint32_t) & BM_AIPS_PACRO_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP6 (4U) //!< Bit position for AIPS_PACRO_TP6. -#define BM_AIPS_PACRO_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRO_TP6. -#define BS_AIPS_PACRO_TP6 (1U) //!< Bit field size in bits for AIPS_PACRO_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP6 field. -#define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP6. -#define BF_AIPS_PACRO_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP6), uint32_t) & BM_AIPS_PACRO_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP6 (5U) //!< Bit position for AIPS_PACRO_WP6. -#define BM_AIPS_PACRO_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRO_WP6. -#define BS_AIPS_PACRO_WP6 (1U) //!< Bit field size in bits for AIPS_PACRO_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP6 field. -#define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP6. -#define BF_AIPS_PACRO_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP6), uint32_t) & BM_AIPS_PACRO_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP6 (6U) //!< Bit position for AIPS_PACRO_SP6. -#define BM_AIPS_PACRO_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRO_SP6. -#define BS_AIPS_PACRO_SP6 (1U) //!< Bit field size in bits for AIPS_PACRO_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP6 field. -#define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP6. -#define BF_AIPS_PACRO_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP6), uint32_t) & BM_AIPS_PACRO_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP5 (8U) //!< Bit position for AIPS_PACRO_TP5. -#define BM_AIPS_PACRO_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRO_TP5. -#define BS_AIPS_PACRO_TP5 (1U) //!< Bit field size in bits for AIPS_PACRO_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP5 field. -#define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP5. -#define BF_AIPS_PACRO_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP5), uint32_t) & BM_AIPS_PACRO_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP5 (9U) //!< Bit position for AIPS_PACRO_WP5. -#define BM_AIPS_PACRO_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRO_WP5. -#define BS_AIPS_PACRO_WP5 (1U) //!< Bit field size in bits for AIPS_PACRO_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP5 field. -#define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP5. -#define BF_AIPS_PACRO_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP5), uint32_t) & BM_AIPS_PACRO_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP5 (10U) //!< Bit position for AIPS_PACRO_SP5. -#define BM_AIPS_PACRO_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRO_SP5. -#define BS_AIPS_PACRO_SP5 (1U) //!< Bit field size in bits for AIPS_PACRO_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP5 field. -#define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP5. -#define BF_AIPS_PACRO_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP5), uint32_t) & BM_AIPS_PACRO_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP4 (12U) //!< Bit position for AIPS_PACRO_TP4. -#define BM_AIPS_PACRO_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRO_TP4. -#define BS_AIPS_PACRO_TP4 (1U) //!< Bit field size in bits for AIPS_PACRO_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP4 field. -#define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP4. -#define BF_AIPS_PACRO_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP4), uint32_t) & BM_AIPS_PACRO_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP4 (13U) //!< Bit position for AIPS_PACRO_WP4. -#define BM_AIPS_PACRO_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRO_WP4. -#define BS_AIPS_PACRO_WP4 (1U) //!< Bit field size in bits for AIPS_PACRO_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP4 field. -#define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP4. -#define BF_AIPS_PACRO_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP4), uint32_t) & BM_AIPS_PACRO_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP4 (14U) //!< Bit position for AIPS_PACRO_SP4. -#define BM_AIPS_PACRO_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRO_SP4. -#define BS_AIPS_PACRO_SP4 (1U) //!< Bit field size in bits for AIPS_PACRO_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP4 field. -#define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP4. -#define BF_AIPS_PACRO_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP4), uint32_t) & BM_AIPS_PACRO_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP3 (16U) //!< Bit position for AIPS_PACRO_TP3. -#define BM_AIPS_PACRO_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRO_TP3. -#define BS_AIPS_PACRO_TP3 (1U) //!< Bit field size in bits for AIPS_PACRO_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP3 field. -#define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP3. -#define BF_AIPS_PACRO_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP3), uint32_t) & BM_AIPS_PACRO_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP3 (17U) //!< Bit position for AIPS_PACRO_WP3. -#define BM_AIPS_PACRO_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRO_WP3. -#define BS_AIPS_PACRO_WP3 (1U) //!< Bit field size in bits for AIPS_PACRO_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP3 field. -#define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP3. -#define BF_AIPS_PACRO_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP3), uint32_t) & BM_AIPS_PACRO_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP3 (18U) //!< Bit position for AIPS_PACRO_SP3. -#define BM_AIPS_PACRO_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRO_SP3. -#define BS_AIPS_PACRO_SP3 (1U) //!< Bit field size in bits for AIPS_PACRO_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP3 field. -#define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP3. -#define BF_AIPS_PACRO_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP3), uint32_t) & BM_AIPS_PACRO_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP2 (20U) //!< Bit position for AIPS_PACRO_TP2. -#define BM_AIPS_PACRO_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRO_TP2. -#define BS_AIPS_PACRO_TP2 (1U) //!< Bit field size in bits for AIPS_PACRO_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP2 field. -#define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP2. -#define BF_AIPS_PACRO_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP2), uint32_t) & BM_AIPS_PACRO_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP2 (21U) //!< Bit position for AIPS_PACRO_WP2. -#define BM_AIPS_PACRO_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRO_WP2. -#define BS_AIPS_PACRO_WP2 (1U) //!< Bit field size in bits for AIPS_PACRO_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP2 field. -#define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP2. -#define BF_AIPS_PACRO_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP2), uint32_t) & BM_AIPS_PACRO_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP2 (22U) //!< Bit position for AIPS_PACRO_SP2. -#define BM_AIPS_PACRO_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRO_SP2. -#define BS_AIPS_PACRO_SP2 (1U) //!< Bit field size in bits for AIPS_PACRO_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP2 field. -#define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP2. -#define BF_AIPS_PACRO_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP2), uint32_t) & BM_AIPS_PACRO_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP1 (24U) //!< Bit position for AIPS_PACRO_TP1. -#define BM_AIPS_PACRO_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRO_TP1. -#define BS_AIPS_PACRO_TP1 (1U) //!< Bit field size in bits for AIPS_PACRO_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP1 field. -#define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP1. -#define BF_AIPS_PACRO_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP1), uint32_t) & BM_AIPS_PACRO_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP1 (25U) //!< Bit position for AIPS_PACRO_WP1. -#define BM_AIPS_PACRO_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRO_WP1. -#define BS_AIPS_PACRO_WP1 (1U) //!< Bit field size in bits for AIPS_PACRO_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP1 field. -#define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP1. -#define BF_AIPS_PACRO_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP1), uint32_t) & BM_AIPS_PACRO_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP1 (26U) //!< Bit position for AIPS_PACRO_SP1. -#define BM_AIPS_PACRO_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRO_SP1. -#define BS_AIPS_PACRO_SP1 (1U) //!< Bit field size in bits for AIPS_PACRO_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP1 field. -#define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP1. -#define BF_AIPS_PACRO_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP1), uint32_t) & BM_AIPS_PACRO_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRO_TP0 (28U) //!< Bit position for AIPS_PACRO_TP0. -#define BM_AIPS_PACRO_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRO_TP0. -#define BS_AIPS_PACRO_TP0 (1U) //!< Bit field size in bits for AIPS_PACRO_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_TP0 field. -#define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_TP0. -#define BF_AIPS_PACRO_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP0), uint32_t) & BM_AIPS_PACRO_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRO_WP0 (29U) //!< Bit position for AIPS_PACRO_WP0. -#define BM_AIPS_PACRO_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRO_WP0. -#define BS_AIPS_PACRO_WP0 (1U) //!< Bit field size in bits for AIPS_PACRO_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_WP0 field. -#define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_WP0. -#define BF_AIPS_PACRO_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP0), uint32_t) & BM_AIPS_PACRO_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRO, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRO_SP0 (30U) //!< Bit position for AIPS_PACRO_SP0. -#define BM_AIPS_PACRO_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRO_SP0. -#define BS_AIPS_PACRO_SP0 (1U) //!< Bit field size in bits for AIPS_PACRO_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRO_SP0 field. -#define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRO_SP0. -#define BF_AIPS_PACRO_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP0), uint32_t) & BM_AIPS_PACRO_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRP - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * This section describes PACR registers E - P, which control peripheral slots - * 32 - 127. See PACRPeripheral Access Control Register for the description of - * these registers. - */ -typedef union _hw_aips_pacrp -{ - uint32_t U; - struct _hw_aips_pacrp_bitfields - { - uint32_t TP7 : 1; //!< [0] Trusted Protect - uint32_t WP7 : 1; //!< [1] Write Protect - uint32_t SP7 : 1; //!< [2] Supervisor Protect - uint32_t RESERVED0 : 1; //!< [3] - uint32_t TP6 : 1; //!< [4] Trusted Protect - uint32_t WP6 : 1; //!< [5] Write Protect - uint32_t SP6 : 1; //!< [6] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [7] - uint32_t TP5 : 1; //!< [8] Trusted Protect - uint32_t WP5 : 1; //!< [9] Write Protect - uint32_t SP5 : 1; //!< [10] Supervisor Protect - uint32_t RESERVED2 : 1; //!< [11] - uint32_t TP4 : 1; //!< [12] Trusted protect - uint32_t WP4 : 1; //!< [13] Write Protect - uint32_t SP4 : 1; //!< [14] Supervisor protect - uint32_t RESERVED3 : 1; //!< [15] - uint32_t TP3 : 1; //!< [16] Trusted Protect - uint32_t WP3 : 1; //!< [17] Write protect - uint32_t SP3 : 1; //!< [18] Supervisor Protect - uint32_t RESERVED4 : 1; //!< [19] - uint32_t TP2 : 1; //!< [20] Trusted protect - uint32_t WP2 : 1; //!< [21] Write Protect - uint32_t SP2 : 1; //!< [22] Supervisor protect - uint32_t RESERVED5 : 1; //!< [23] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write Protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED6 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor Protect - uint32_t RESERVED7 : 1; //!< [31] - } B; -} hw_aips_pacrp_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRP register - */ -//@{ -#define HW_AIPS_PACRP_ADDR(x) (REGS_AIPS_BASE(x) + 0x6CU) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x)) -#define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U) -#define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v)) -#define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v))) -#define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v))) -#define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRP bitfields - */ - -/*! - * @name Register AIPS_PACRP, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP7 (0U) //!< Bit position for AIPS_PACRP_TP7. -#define BM_AIPS_PACRP_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRP_TP7. -#define BS_AIPS_PACRP_TP7 (1U) //!< Bit field size in bits for AIPS_PACRP_TP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP7 field. -#define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP7. -#define BF_AIPS_PACRP_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP7), uint32_t) & BM_AIPS_PACRP_TP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP7 field to a new value. -#define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP7 (1U) //!< Bit position for AIPS_PACRP_WP7. -#define BM_AIPS_PACRP_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRP_WP7. -#define BS_AIPS_PACRP_WP7 (1U) //!< Bit field size in bits for AIPS_PACRP_WP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP7 field. -#define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP7. -#define BF_AIPS_PACRP_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP7), uint32_t) & BM_AIPS_PACRP_WP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP7 field to a new value. -#define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP7 (2U) //!< Bit position for AIPS_PACRP_SP7. -#define BM_AIPS_PACRP_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRP_SP7. -#define BS_AIPS_PACRP_SP7 (1U) //!< Bit field size in bits for AIPS_PACRP_SP7. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP7 field. -#define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP7. -#define BF_AIPS_PACRP_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP7), uint32_t) & BM_AIPS_PACRP_SP7) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP7 field to a new value. -#define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP6 (4U) //!< Bit position for AIPS_PACRP_TP6. -#define BM_AIPS_PACRP_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRP_TP6. -#define BS_AIPS_PACRP_TP6 (1U) //!< Bit field size in bits for AIPS_PACRP_TP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP6 field. -#define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP6. -#define BF_AIPS_PACRP_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP6), uint32_t) & BM_AIPS_PACRP_TP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP6 field to a new value. -#define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP6 (5U) //!< Bit position for AIPS_PACRP_WP6. -#define BM_AIPS_PACRP_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRP_WP6. -#define BS_AIPS_PACRP_WP6 (1U) //!< Bit field size in bits for AIPS_PACRP_WP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP6 field. -#define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP6. -#define BF_AIPS_PACRP_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP6), uint32_t) & BM_AIPS_PACRP_WP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP6 field to a new value. -#define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP6 (6U) //!< Bit position for AIPS_PACRP_SP6. -#define BM_AIPS_PACRP_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRP_SP6. -#define BS_AIPS_PACRP_SP6 (1U) //!< Bit field size in bits for AIPS_PACRP_SP6. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP6 field. -#define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP6. -#define BF_AIPS_PACRP_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP6), uint32_t) & BM_AIPS_PACRP_SP6) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP6 field to a new value. -#define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP5 (8U) //!< Bit position for AIPS_PACRP_TP5. -#define BM_AIPS_PACRP_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRP_TP5. -#define BS_AIPS_PACRP_TP5 (1U) //!< Bit field size in bits for AIPS_PACRP_TP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP5 field. -#define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP5. -#define BF_AIPS_PACRP_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP5), uint32_t) & BM_AIPS_PACRP_TP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP5 field to a new value. -#define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP5 (9U) //!< Bit position for AIPS_PACRP_WP5. -#define BM_AIPS_PACRP_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRP_WP5. -#define BS_AIPS_PACRP_WP5 (1U) //!< Bit field size in bits for AIPS_PACRP_WP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP5 field. -#define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP5. -#define BF_AIPS_PACRP_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP5), uint32_t) & BM_AIPS_PACRP_WP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP5 field to a new value. -#define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP5 (10U) //!< Bit position for AIPS_PACRP_SP5. -#define BM_AIPS_PACRP_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRP_SP5. -#define BS_AIPS_PACRP_SP5 (1U) //!< Bit field size in bits for AIPS_PACRP_SP5. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP5 field. -#define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP5. -#define BF_AIPS_PACRP_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP5), uint32_t) & BM_AIPS_PACRP_SP5) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP5 field to a new value. -#define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP4 (12U) //!< Bit position for AIPS_PACRP_TP4. -#define BM_AIPS_PACRP_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRP_TP4. -#define BS_AIPS_PACRP_TP4 (1U) //!< Bit field size in bits for AIPS_PACRP_TP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP4 field. -#define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP4. -#define BF_AIPS_PACRP_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP4), uint32_t) & BM_AIPS_PACRP_TP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP4 field to a new value. -#define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP4 (13U) //!< Bit position for AIPS_PACRP_WP4. -#define BM_AIPS_PACRP_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRP_WP4. -#define BS_AIPS_PACRP_WP4 (1U) //!< Bit field size in bits for AIPS_PACRP_WP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP4 field. -#define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP4. -#define BF_AIPS_PACRP_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP4), uint32_t) & BM_AIPS_PACRP_WP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP4 field to a new value. -#define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP4 (14U) //!< Bit position for AIPS_PACRP_SP4. -#define BM_AIPS_PACRP_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRP_SP4. -#define BS_AIPS_PACRP_SP4 (1U) //!< Bit field size in bits for AIPS_PACRP_SP4. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP4 field. -#define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP4. -#define BF_AIPS_PACRP_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP4), uint32_t) & BM_AIPS_PACRP_SP4) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP4 field to a new value. -#define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP3 (16U) //!< Bit position for AIPS_PACRP_TP3. -#define BM_AIPS_PACRP_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRP_TP3. -#define BS_AIPS_PACRP_TP3 (1U) //!< Bit field size in bits for AIPS_PACRP_TP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP3 field. -#define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP3. -#define BF_AIPS_PACRP_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP3), uint32_t) & BM_AIPS_PACRP_TP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP3 field to a new value. -#define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP3 (17U) //!< Bit position for AIPS_PACRP_WP3. -#define BM_AIPS_PACRP_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRP_WP3. -#define BS_AIPS_PACRP_WP3 (1U) //!< Bit field size in bits for AIPS_PACRP_WP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP3 field. -#define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP3. -#define BF_AIPS_PACRP_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP3), uint32_t) & BM_AIPS_PACRP_WP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP3 field to a new value. -#define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP3 (18U) //!< Bit position for AIPS_PACRP_SP3. -#define BM_AIPS_PACRP_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRP_SP3. -#define BS_AIPS_PACRP_SP3 (1U) //!< Bit field size in bits for AIPS_PACRP_SP3. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP3 field. -#define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP3. -#define BF_AIPS_PACRP_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP3), uint32_t) & BM_AIPS_PACRP_SP3) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP3 field to a new value. -#define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP2 (20U) //!< Bit position for AIPS_PACRP_TP2. -#define BM_AIPS_PACRP_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRP_TP2. -#define BS_AIPS_PACRP_TP2 (1U) //!< Bit field size in bits for AIPS_PACRP_TP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP2 field. -#define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP2. -#define BF_AIPS_PACRP_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP2), uint32_t) & BM_AIPS_PACRP_TP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP2 field to a new value. -#define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP2 (21U) //!< Bit position for AIPS_PACRP_WP2. -#define BM_AIPS_PACRP_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRP_WP2. -#define BS_AIPS_PACRP_WP2 (1U) //!< Bit field size in bits for AIPS_PACRP_WP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP2 field. -#define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP2. -#define BF_AIPS_PACRP_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP2), uint32_t) & BM_AIPS_PACRP_WP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP2 field to a new value. -#define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for - * the master must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP2 (22U) //!< Bit position for AIPS_PACRP_SP2. -#define BM_AIPS_PACRP_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRP_SP2. -#define BS_AIPS_PACRP_SP2 (1U) //!< Bit field size in bits for AIPS_PACRP_SP2. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP2 field. -#define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP2. -#define BF_AIPS_PACRP_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP2), uint32_t) & BM_AIPS_PACRP_SP2) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP2 field to a new value. -#define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP1 (24U) //!< Bit position for AIPS_PACRP_TP1. -#define BM_AIPS_PACRP_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRP_TP1. -#define BS_AIPS_PACRP_TP1 (1U) //!< Bit field size in bits for AIPS_PACRP_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP1 field. -#define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP1. -#define BF_AIPS_PACRP_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP1), uint32_t) & BM_AIPS_PACRP_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP1 (25U) //!< Bit position for AIPS_PACRP_WP1. -#define BM_AIPS_PACRP_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRP_WP1. -#define BS_AIPS_PACRP_WP1 (1U) //!< Bit field size in bits for AIPS_PACRP_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP1 field. -#define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP1. -#define BF_AIPS_PACRP_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP1), uint32_t) & BM_AIPS_PACRP_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP1 (26U) //!< Bit position for AIPS_PACRP_SP1. -#define BM_AIPS_PACRP_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRP_SP1. -#define BS_AIPS_PACRP_SP1 (1U) //!< Bit field size in bits for AIPS_PACRP_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP1 field. -#define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP1. -#define BF_AIPS_PACRP_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP1), uint32_t) & BM_AIPS_PACRP_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRP_TP0 (28U) //!< Bit position for AIPS_PACRP_TP0. -#define BM_AIPS_PACRP_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRP_TP0. -#define BS_AIPS_PACRP_TP0 (1U) //!< Bit field size in bits for AIPS_PACRP_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_TP0 field. -#define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_TP0. -#define BF_AIPS_PACRP_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP0), uint32_t) & BM_AIPS_PACRP_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRP_WP0 (29U) //!< Bit position for AIPS_PACRP_WP0. -#define BM_AIPS_PACRP_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRP_WP0. -#define BS_AIPS_PACRP_WP0 (1U) //!< Bit field size in bits for AIPS_PACRP_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_WP0 field. -#define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_WP0. -#define BF_AIPS_PACRP_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP0), uint32_t) & BM_AIPS_PACRP_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRP, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRP_SP0 (30U) //!< Bit position for AIPS_PACRP_SP0. -#define BM_AIPS_PACRP_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRP_SP0. -#define BS_AIPS_PACRP_SP0 (1U) //!< Bit field size in bits for AIPS_PACRP_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRP_SP0 field. -#define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRP_SP0. -#define BF_AIPS_PACRP_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP0), uint32_t) & BM_AIPS_PACRP_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// HW_AIPS_PACRU - Peripheral Access Control Register -//------------------------------------------------------------------------------------------- - -#ifndef __LANGUAGE_ASM__ -/*! - * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * PACRU defines the access levels for the two global spaces. - */ -typedef union _hw_aips_pacru -{ - uint32_t U; - struct _hw_aips_pacru_bitfields - { - uint32_t RESERVED0 : 24; //!< [23:0] - uint32_t TP1 : 1; //!< [24] Trusted Protect - uint32_t WP1 : 1; //!< [25] Write protect - uint32_t SP1 : 1; //!< [26] Supervisor Protect - uint32_t RESERVED1 : 1; //!< [27] - uint32_t TP0 : 1; //!< [28] Trusted Protect - uint32_t WP0 : 1; //!< [29] Write Protect - uint32_t SP0 : 1; //!< [30] Supervisor protect - uint32_t RESERVED2 : 1; //!< [31] - } B; -} hw_aips_pacru_t; -#endif - -/*! - * @name Constants and macros for entire AIPS_PACRU register - */ -//@{ -#define HW_AIPS_PACRU_ADDR(x) (REGS_AIPS_BASE(x) + 0x80U) - -#ifndef __LANGUAGE_ASM__ -#define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x)) -#define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U) -#define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v)) -#define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v))) -#define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v))) -#define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v))) -#endif -//@} - -/* - * Constants & macros for individual AIPS_PACRU bitfields - */ - -/*! - * @name Register AIPS_PACRU, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRU_TP1 (24U) //!< Bit position for AIPS_PACRU_TP1. -#define BM_AIPS_PACRU_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRU_TP1. -#define BS_AIPS_PACRU_TP1 (1U) //!< Bit field size in bits for AIPS_PACRU_TP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRU_TP1 field. -#define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRU_TP1. -#define BF_AIPS_PACRU_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP1), uint32_t) & BM_AIPS_PACRU_TP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP1 field to a new value. -#define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRU, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRU_WP1 (25U) //!< Bit position for AIPS_PACRU_WP1. -#define BM_AIPS_PACRU_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRU_WP1. -#define BS_AIPS_PACRU_WP1 (1U) //!< Bit field size in bits for AIPS_PACRU_WP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRU_WP1 field. -#define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRU_WP1. -#define BF_AIPS_PACRU_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP1), uint32_t) & BM_AIPS_PACRU_WP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP1 field to a new value. -#define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRU, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control field for the master - * must be set. If not, access terminates with an error response and no - * peripheral access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRU_SP1 (26U) //!< Bit position for AIPS_PACRU_SP1. -#define BM_AIPS_PACRU_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRU_SP1. -#define BS_AIPS_PACRU_SP1 (1U) //!< Bit field size in bits for AIPS_PACRU_SP1. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRU_SP1 field. -#define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1)) -#endif - -//! @brief Format value for bitfield AIPS_PACRU_SP1. -#define BF_AIPS_PACRU_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP1), uint32_t) & BM_AIPS_PACRU_SP1) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP1 field to a new value. -#define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRU, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates . - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -//@{ -#define BP_AIPS_PACRU_TP0 (28U) //!< Bit position for AIPS_PACRU_TP0. -#define BM_AIPS_PACRU_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRU_TP0. -#define BS_AIPS_PACRU_TP0 (1U) //!< Bit field size in bits for AIPS_PACRU_TP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRU_TP0 field. -#define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRU_TP0. -#define BF_AIPS_PACRU_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP0), uint32_t) & BM_AIPS_PACRU_TP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the TP0 field to a new value. -#define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRU, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accessses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates . - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -//@{ -#define BP_AIPS_PACRU_WP0 (29U) //!< Bit position for AIPS_PACRU_WP0. -#define BM_AIPS_PACRU_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRU_WP0. -#define BS_AIPS_PACRU_WP0 (1U) //!< Bit field size in bits for AIPS_PACRU_WP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRU_WP0 field. -#define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRU_WP0. -#define BF_AIPS_PACRU_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP0), uint32_t) & BM_AIPS_PACRU_WP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the WP0 field to a new value. -#define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v)) -#endif -//@} - -/*! - * @name Register AIPS_PACRU, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates . - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -//@{ -#define BP_AIPS_PACRU_SP0 (30U) //!< Bit position for AIPS_PACRU_SP0. -#define BM_AIPS_PACRU_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRU_SP0. -#define BS_AIPS_PACRU_SP0 (1U) //!< Bit field size in bits for AIPS_PACRU_SP0. - -#ifndef __LANGUAGE_ASM__ -//! @brief Read current value of the AIPS_PACRU_SP0 field. -#define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0)) -#endif - -//! @brief Format value for bitfield AIPS_PACRU_SP0. -#define BF_AIPS_PACRU_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP0), uint32_t) & BM_AIPS_PACRU_SP0) - -#ifndef __LANGUAGE_ASM__ -//! @brief Set the SP0 field to a new value. -#define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v)) -#endif -//@} - -//------------------------------------------------------------------------------------------- -// hw_aips_t - module struct -//------------------------------------------------------------------------------------------- -/*! - * @brief All AIPS module registers. - */ -#ifndef __LANGUAGE_ASM__ -#pragma pack(1) -typedef struct _hw_aips -{ - __IO hw_aips_mpra_t MPRA; //!< [0x0] Master Privilege Register A - uint8_t _reserved0[28]; - __IO hw_aips_pacra_t PACRA; //!< [0x20] Peripheral Access Control Register - __IO hw_aips_pacrb_t PACRB; //!< [0x24] Peripheral Access Control Register - __IO hw_aips_pacrc_t PACRC; //!< [0x28] Peripheral Access Control Register - __IO hw_aips_pacrd_t PACRD; //!< [0x2C] Peripheral Access Control Register - uint8_t _reserved1[16]; - __IO hw_aips_pacre_t PACRE; //!< [0x40] Peripheral Access Control Register - __IO hw_aips_pacrf_t PACRF; //!< [0x44] Peripheral Access Control Register - __IO hw_aips_pacrg_t PACRG; //!< [0x48] Peripheral Access Control Register - __IO hw_aips_pacrh_t PACRH; //!< [0x4C] Peripheral Access Control Register - __IO hw_aips_pacri_t PACRI; //!< [0x50] Peripheral Access Control Register - __IO hw_aips_pacrj_t PACRJ; //!< [0x54] Peripheral Access Control Register - __IO hw_aips_pacrk_t PACRK; //!< [0x58] Peripheral Access Control Register - __IO hw_aips_pacrl_t PACRL; //!< [0x5C] Peripheral Access Control Register - __IO hw_aips_pacrm_t PACRM; //!< [0x60] Peripheral Access Control Register - __IO hw_aips_pacrn_t PACRN; //!< [0x64] Peripheral Access Control Register - __IO hw_aips_pacro_t PACRO; //!< [0x68] Peripheral Access Control Register - __IO hw_aips_pacrp_t PACRP; //!< [0x6C] Peripheral Access Control Register - uint8_t _reserved2[16]; - __IO hw_aips_pacru_t PACRU; //!< [0x80] Peripheral Access Control Register -} hw_aips_t; -#pragma pack() - -//! @brief Macro to access all AIPS registers. -//! @param x AIPS instance number. -//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, -//! use the '&' operator, like &HW_AIPS(0). -#define HW_AIPS(x) (*(hw_aips_t *) REGS_AIPS_BASE(x)) -#endif - -#endif // __HW_AIPS_REGISTERS_H__ -// v22/130726/0.9 -// EOF diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h deleted file mode 100644 index 27d65af091c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h +++ /dev/null @@ -1,940 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CMP_REGISTERS_H__ -#define __HW_CMP_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 CMP - * - * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) - * - * Registers defined in this header file: - * - HW_CMP_CR0 - CMP Control Register 0 - * - HW_CMP_CR1 - CMP Control Register 1 - * - HW_CMP_FPR - CMP Filter Period Register - * - HW_CMP_SCR - CMP Status and Control Register - * - HW_CMP_DACCR - DAC Control Register - * - HW_CMP_MUXCR - MUX Control Register - * - * - hw_cmp_t - Struct containing all module registers. - */ - -#define HW_CMP_INSTANCE_COUNT (2U) /*!< Number of instances of the CMP module. */ -#define HW_CMP0 (0U) /*!< Instance number for CMP0. */ -#define HW_CMP1 (1U) /*!< Instance number for CMP1. */ - -/******************************************************************************* - * HW_CMP_CR0 - CMP Control Register 0 - ******************************************************************************/ - -/*! - * @brief HW_CMP_CR0 - CMP Control Register 0 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_cr0 -{ - uint8_t U; - struct _hw_cmp_cr0_bitfields - { - uint8_t HYSTCTR : 2; /*!< [1:0] Comparator hard block hysteresis - * control */ - uint8_t RESERVED0 : 2; /*!< [3:2] */ - uint8_t FILTER_CNT : 3; /*!< [6:4] Filter Sample Count */ - uint8_t RESERVED1 : 1; /*!< [7] */ - } B; -} hw_cmp_cr0_t; - -/*! - * @name Constants and macros for entire CMP_CR0 register - */ -/*@{*/ -#define HW_CMP_CR0_ADDR(x) ((x) + 0x0U) - -#define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x)) -#define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U) -#define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v)) -#define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v))) -#define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v))) -#define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_CR0 bitfields - */ - -/*! - * @name Register CMP_CR0, field HYSTCTR[1:0] (RW) - * - * Defines the programmable hysteresis level. The hysteresis values associated - * with each level are device-specific. See the Data Sheet of the device for the - * exact values. - * - * Values: - * - 00 - Level 0 - * - 01 - Level 1 - * - 10 - Level 2 - * - 11 - Level 3 - */ -/*@{*/ -#define BP_CMP_CR0_HYSTCTR (0U) /*!< Bit position for CMP_CR0_HYSTCTR. */ -#define BM_CMP_CR0_HYSTCTR (0x03U) /*!< Bit mask for CMP_CR0_HYSTCTR. */ -#define BS_CMP_CR0_HYSTCTR (2U) /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */ - -/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */ -#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR) - -/*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */ -#define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR) - -/*! @brief Set the HYSTCTR field to a new value. */ -#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v))) -/*@}*/ - -/*! - * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW) - * - * Represents the number of consecutive samples that must agree prior to the - * comparator ouput filter accepting a new output state. For information regarding - * filter programming and latency, see the Functional descriptionThe CMP module - * can be used to compare two analog input voltages applied to INP and INM. . - * - * Values: - * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a - * legal state, and is not recommended. If SE = 0, COUT = COUTA. - * - 001 - One sample must agree. The comparator output is simply sampled. - * - 010 - 2 consecutive samples must agree. - * - 011 - 3 consecutive samples must agree. - * - 100 - 4 consecutive samples must agree. - * - 101 - 5 consecutive samples must agree. - * - 110 - 6 consecutive samples must agree. - * - 111 - 7 consecutive samples must agree. - */ -/*@{*/ -#define BP_CMP_CR0_FILTER_CNT (4U) /*!< Bit position for CMP_CR0_FILTER_CNT. */ -#define BM_CMP_CR0_FILTER_CNT (0x70U) /*!< Bit mask for CMP_CR0_FILTER_CNT. */ -#define BS_CMP_CR0_FILTER_CNT (3U) /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */ - -/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */ -#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT) - -/*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */ -#define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT) - -/*! @brief Set the FILTER_CNT field to a new value. */ -#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_CMP_CR1 - CMP Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_CMP_CR1 - CMP Control Register 1 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_cr1 -{ - uint8_t U; - struct _hw_cmp_cr1_bitfields - { - uint8_t EN : 1; /*!< [0] Comparator Module Enable */ - uint8_t OPE : 1; /*!< [1] Comparator Output Pin Enable */ - uint8_t COS : 1; /*!< [2] Comparator Output Select */ - uint8_t INV : 1; /*!< [3] Comparator INVERT */ - uint8_t PMODE : 1; /*!< [4] Power Mode Select */ - uint8_t TRIGM : 1; /*!< [5] Trigger Mode Enable */ - uint8_t WE : 1; /*!< [6] Windowing Enable */ - uint8_t SE : 1; /*!< [7] Sample Enable */ - } B; -} hw_cmp_cr1_t; - -/*! - * @name Constants and macros for entire CMP_CR1 register - */ -/*@{*/ -#define HW_CMP_CR1_ADDR(x) ((x) + 0x1U) - -#define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x)) -#define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U) -#define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v)) -#define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v))) -#define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v))) -#define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_CR1 bitfields - */ - -/*! - * @name Register CMP_CR1, field EN[0] (RW) - * - * Enables the Analog Comparator module. When the module is not enabled, it - * remains in the off state, and consumes no power. When the user selects the same - * input from analog mux to the positive and negative port, the comparator is - * disabled automatically. - * - * Values: - * - 0 - Analog Comparator is disabled. - * - 1 - Analog Comparator is enabled. - */ -/*@{*/ -#define BP_CMP_CR1_EN (0U) /*!< Bit position for CMP_CR1_EN. */ -#define BM_CMP_CR1_EN (0x01U) /*!< Bit mask for CMP_CR1_EN. */ -#define BS_CMP_CR1_EN (1U) /*!< Bit field size in bits for CMP_CR1_EN. */ - -/*! @brief Read current value of the CMP_CR1_EN field. */ -#define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN)) - -/*! @brief Format value for bitfield CMP_CR1_EN. */ -#define BF_CMP_CR1_EN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN) - -/*! @brief Set the EN field to a new value. */ -#define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field OPE[1] (RW) - * - * Values: - * - 0 - CMPO is not available on the associated CMPO output pin. If the - * comparator does not own the pin, this field has no effect. - * - 1 - CMPO is available on the associated CMPO output pin. The comparator - * output (CMPO) is driven out on the associated CMPO output pin if the - * comparator owns the pin. If the comparator does not own the field, this bit has no - * effect. - */ -/*@{*/ -#define BP_CMP_CR1_OPE (1U) /*!< Bit position for CMP_CR1_OPE. */ -#define BM_CMP_CR1_OPE (0x02U) /*!< Bit mask for CMP_CR1_OPE. */ -#define BS_CMP_CR1_OPE (1U) /*!< Bit field size in bits for CMP_CR1_OPE. */ - -/*! @brief Read current value of the CMP_CR1_OPE field. */ -#define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE)) - -/*! @brief Format value for bitfield CMP_CR1_OPE. */ -#define BF_CMP_CR1_OPE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE) - -/*! @brief Set the OPE field to a new value. */ -#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field COS[2] (RW) - * - * Values: - * - 0 - Set the filtered comparator output (CMPO) to equal COUT. - * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA. - */ -/*@{*/ -#define BP_CMP_CR1_COS (2U) /*!< Bit position for CMP_CR1_COS. */ -#define BM_CMP_CR1_COS (0x04U) /*!< Bit mask for CMP_CR1_COS. */ -#define BS_CMP_CR1_COS (1U) /*!< Bit field size in bits for CMP_CR1_COS. */ - -/*! @brief Read current value of the CMP_CR1_COS field. */ -#define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS)) - -/*! @brief Format value for bitfield CMP_CR1_COS. */ -#define BF_CMP_CR1_COS(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS) - -/*! @brief Set the COS field to a new value. */ -#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field INV[3] (RW) - * - * Allows selection of the polarity of the analog comparator function. It is - * also driven to the COUT output, on both the device pin and as SCR[COUT], when - * OPE=0. - * - * Values: - * - 0 - Does not invert the comparator output. - * - 1 - Inverts the comparator output. - */ -/*@{*/ -#define BP_CMP_CR1_INV (3U) /*!< Bit position for CMP_CR1_INV. */ -#define BM_CMP_CR1_INV (0x08U) /*!< Bit mask for CMP_CR1_INV. */ -#define BS_CMP_CR1_INV (1U) /*!< Bit field size in bits for CMP_CR1_INV. */ - -/*! @brief Read current value of the CMP_CR1_INV field. */ -#define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV)) - -/*! @brief Format value for bitfield CMP_CR1_INV. */ -#define BF_CMP_CR1_INV(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV) - -/*! @brief Set the INV field to a new value. */ -#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field PMODE[4] (RW) - * - * See the electrical specifications table in the device Data Sheet for details. - * - * Values: - * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower - * output propagation delay and lower current consumption. - * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster - * output propagation delay and higher current consumption. - */ -/*@{*/ -#define BP_CMP_CR1_PMODE (4U) /*!< Bit position for CMP_CR1_PMODE. */ -#define BM_CMP_CR1_PMODE (0x10U) /*!< Bit mask for CMP_CR1_PMODE. */ -#define BS_CMP_CR1_PMODE (1U) /*!< Bit field size in bits for CMP_CR1_PMODE. */ - -/*! @brief Read current value of the CMP_CR1_PMODE field. */ -#define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE)) - -/*! @brief Format value for bitfield CMP_CR1_PMODE. */ -#define BF_CMP_CR1_PMODE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE) - -/*! @brief Set the PMODE field to a new value. */ -#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field TRIGM[5] (RW) - * - * CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to - * 1. In addition, the CMP should be enabled. If the DAC is to be used as a - * reference to the CMP, it should also be enabled. CMP Trigger mode depends on an - * external timer resource to periodically enable the CMP and 6-bit DAC in order to - * generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed - * in a standby state until an external timer resource trigger is received. See - * the chip configuration for details about the external timer resource. - * - * Values: - * - 0 - Trigger mode is disabled. - * - 1 - Trigger mode is enabled. - */ -/*@{*/ -#define BP_CMP_CR1_TRIGM (5U) /*!< Bit position for CMP_CR1_TRIGM. */ -#define BM_CMP_CR1_TRIGM (0x20U) /*!< Bit mask for CMP_CR1_TRIGM. */ -#define BS_CMP_CR1_TRIGM (1U) /*!< Bit field size in bits for CMP_CR1_TRIGM. */ - -/*! @brief Read current value of the CMP_CR1_TRIGM field. */ -#define BR_CMP_CR1_TRIGM(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM)) - -/*! @brief Format value for bitfield CMP_CR1_TRIGM. */ -#define BF_CMP_CR1_TRIGM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_TRIGM) & BM_CMP_CR1_TRIGM) - -/*! @brief Set the TRIGM field to a new value. */ -#define BW_CMP_CR1_TRIGM(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field WE[6] (RW) - * - * At any given time, either SE or WE can be set. If a write to this register - * attempts to set both, then SE is set and WE is cleared. However, avoid writing - * 1s to both field locations because this "11" case is reserved and may change in - * future implementations. - * - * Values: - * - 0 - Windowing mode is not selected. - * - 1 - Windowing mode is selected. - */ -/*@{*/ -#define BP_CMP_CR1_WE (6U) /*!< Bit position for CMP_CR1_WE. */ -#define BM_CMP_CR1_WE (0x40U) /*!< Bit mask for CMP_CR1_WE. */ -#define BS_CMP_CR1_WE (1U) /*!< Bit field size in bits for CMP_CR1_WE. */ - -/*! @brief Read current value of the CMP_CR1_WE field. */ -#define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE)) - -/*! @brief Format value for bitfield CMP_CR1_WE. */ -#define BF_CMP_CR1_WE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE) - -/*! @brief Set the WE field to a new value. */ -#define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field SE[7] (RW) - * - * At any given time, either SE or WE can be set. If a write to this register - * attempts to set both, then SE is set and WE is cleared. However, avoid writing - * 1s to both field locations because this "11" case is reserved and may change in - * future implementations. - * - * Values: - * - 0 - Sampling mode is not selected. - * - 1 - Sampling mode is selected. - */ -/*@{*/ -#define BP_CMP_CR1_SE (7U) /*!< Bit position for CMP_CR1_SE. */ -#define BM_CMP_CR1_SE (0x80U) /*!< Bit mask for CMP_CR1_SE. */ -#define BS_CMP_CR1_SE (1U) /*!< Bit field size in bits for CMP_CR1_SE. */ - -/*! @brief Read current value of the CMP_CR1_SE field. */ -#define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE)) - -/*! @brief Format value for bitfield CMP_CR1_SE. */ -#define BF_CMP_CR1_SE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE) - -/*! @brief Set the SE field to a new value. */ -#define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_FPR - CMP Filter Period Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_FPR - CMP Filter Period Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_fpr -{ - uint8_t U; - struct _hw_cmp_fpr_bitfields - { - uint8_t FILT_PER : 8; /*!< [7:0] Filter Sample Period */ - } B; -} hw_cmp_fpr_t; - -/*! - * @name Constants and macros for entire CMP_FPR register - */ -/*@{*/ -#define HW_CMP_FPR_ADDR(x) ((x) + 0x2U) - -#define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x)) -#define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U) -#define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v)) -#define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v))) -#define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v))) -#define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_FPR bitfields - */ - -/*! - * @name Register CMP_FPR, field FILT_PER[7:0] (RW) - * - * Specifies the sampling period, in bus clock cycles, of the comparator output - * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter - * programming and latency details appear in the Functional descriptionThe CMP - * module can be used to compare two analog input voltages applied to INP and INM. . - * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE - * signal is used to determine the sampling period. - */ -/*@{*/ -#define BP_CMP_FPR_FILT_PER (0U) /*!< Bit position for CMP_FPR_FILT_PER. */ -#define BM_CMP_FPR_FILT_PER (0xFFU) /*!< Bit mask for CMP_FPR_FILT_PER. */ -#define BS_CMP_FPR_FILT_PER (8U) /*!< Bit field size in bits for CMP_FPR_FILT_PER. */ - -/*! @brief Read current value of the CMP_FPR_FILT_PER field. */ -#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U) - -/*! @brief Format value for bitfield CMP_FPR_FILT_PER. */ -#define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER) - -/*! @brief Set the FILT_PER field to a new value. */ -#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_SCR - CMP Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_SCR - CMP Status and Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_scr -{ - uint8_t U; - struct _hw_cmp_scr_bitfields - { - uint8_t COUT : 1; /*!< [0] Analog Comparator Output */ - uint8_t CFF : 1; /*!< [1] Analog Comparator Flag Falling */ - uint8_t CFR : 1; /*!< [2] Analog Comparator Flag Rising */ - uint8_t IEF : 1; /*!< [3] Comparator Interrupt Enable Falling */ - uint8_t IER : 1; /*!< [4] Comparator Interrupt Enable Rising */ - uint8_t RESERVED0 : 1; /*!< [5] */ - uint8_t DMAEN : 1; /*!< [6] DMA Enable Control */ - uint8_t RESERVED1 : 1; /*!< [7] */ - } B; -} hw_cmp_scr_t; - -/*! - * @name Constants and macros for entire CMP_SCR register - */ -/*@{*/ -#define HW_CMP_SCR_ADDR(x) ((x) + 0x3U) - -#define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x)) -#define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U) -#define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v)) -#define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v))) -#define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v))) -#define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_SCR bitfields - */ - -/*! - * @name Register CMP_SCR, field COUT[0] (RO) - * - * Returns the current value of the Analog Comparator output, when read. The - * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module - * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored. - */ -/*@{*/ -#define BP_CMP_SCR_COUT (0U) /*!< Bit position for CMP_SCR_COUT. */ -#define BM_CMP_SCR_COUT (0x01U) /*!< Bit mask for CMP_SCR_COUT. */ -#define BS_CMP_SCR_COUT (1U) /*!< Bit field size in bits for CMP_SCR_COUT. */ - -/*! @brief Read current value of the CMP_SCR_COUT field. */ -#define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field CFF[1] (W1C) - * - * Detects a falling-edge on COUT, when set, during normal operation. CFF is - * cleared by writing 1 to it. During Stop modes, CFF is level sensitive . - * - * Values: - * - 0 - Falling-edge on COUT has not been detected. - * - 1 - Falling-edge on COUT has occurred. - */ -/*@{*/ -#define BP_CMP_SCR_CFF (1U) /*!< Bit position for CMP_SCR_CFF. */ -#define BM_CMP_SCR_CFF (0x02U) /*!< Bit mask for CMP_SCR_CFF. */ -#define BS_CMP_SCR_CFF (1U) /*!< Bit field size in bits for CMP_SCR_CFF. */ - -/*! @brief Read current value of the CMP_SCR_CFF field. */ -#define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF)) - -/*! @brief Format value for bitfield CMP_SCR_CFF. */ -#define BF_CMP_SCR_CFF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF) - -/*! @brief Set the CFF field to a new value. */ -#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field CFR[2] (W1C) - * - * Detects a rising-edge on COUT, when set, during normal operation. CFR is - * cleared by writing 1 to it. During Stop modes, CFR is level sensitive . - * - * Values: - * - 0 - Rising-edge on COUT has not been detected. - * - 1 - Rising-edge on COUT has occurred. - */ -/*@{*/ -#define BP_CMP_SCR_CFR (2U) /*!< Bit position for CMP_SCR_CFR. */ -#define BM_CMP_SCR_CFR (0x04U) /*!< Bit mask for CMP_SCR_CFR. */ -#define BS_CMP_SCR_CFR (1U) /*!< Bit field size in bits for CMP_SCR_CFR. */ - -/*! @brief Read current value of the CMP_SCR_CFR field. */ -#define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR)) - -/*! @brief Format value for bitfield CMP_SCR_CFR. */ -#define BF_CMP_SCR_CFR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR) - -/*! @brief Set the CFR field to a new value. */ -#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field IEF[3] (RW) - * - * Enables the CFF interrupt from the CMP. When this field is set, an interrupt - * will be asserted when CFF is set. - * - * Values: - * - 0 - Interrupt is disabled. - * - 1 - Interrupt is enabled. - */ -/*@{*/ -#define BP_CMP_SCR_IEF (3U) /*!< Bit position for CMP_SCR_IEF. */ -#define BM_CMP_SCR_IEF (0x08U) /*!< Bit mask for CMP_SCR_IEF. */ -#define BS_CMP_SCR_IEF (1U) /*!< Bit field size in bits for CMP_SCR_IEF. */ - -/*! @brief Read current value of the CMP_SCR_IEF field. */ -#define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF)) - -/*! @brief Format value for bitfield CMP_SCR_IEF. */ -#define BF_CMP_SCR_IEF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF) - -/*! @brief Set the IEF field to a new value. */ -#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field IER[4] (RW) - * - * Enables the CFR interrupt from the CMP. When this field is set, an interrupt - * will be asserted when CFR is set. - * - * Values: - * - 0 - Interrupt is disabled. - * - 1 - Interrupt is enabled. - */ -/*@{*/ -#define BP_CMP_SCR_IER (4U) /*!< Bit position for CMP_SCR_IER. */ -#define BM_CMP_SCR_IER (0x10U) /*!< Bit mask for CMP_SCR_IER. */ -#define BS_CMP_SCR_IER (1U) /*!< Bit field size in bits for CMP_SCR_IER. */ - -/*! @brief Read current value of the CMP_SCR_IER field. */ -#define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER)) - -/*! @brief Format value for bitfield CMP_SCR_IER. */ -#define BF_CMP_SCR_IER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER) - -/*! @brief Set the IER field to a new value. */ -#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field DMAEN[6] (RW) - * - * Enables the DMA transfer triggered from the CMP module. When this field is - * set, a DMA request is asserted when CFR or CFF is set. - * - * Values: - * - 0 - DMA is disabled. - * - 1 - DMA is enabled. - */ -/*@{*/ -#define BP_CMP_SCR_DMAEN (6U) /*!< Bit position for CMP_SCR_DMAEN. */ -#define BM_CMP_SCR_DMAEN (0x40U) /*!< Bit mask for CMP_SCR_DMAEN. */ -#define BS_CMP_SCR_DMAEN (1U) /*!< Bit field size in bits for CMP_SCR_DMAEN. */ - -/*! @brief Read current value of the CMP_SCR_DMAEN field. */ -#define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN)) - -/*! @brief Format value for bitfield CMP_SCR_DMAEN. */ -#define BF_CMP_SCR_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_DACCR - DAC Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_DACCR - DAC Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_daccr -{ - uint8_t U; - struct _hw_cmp_daccr_bitfields - { - uint8_t VOSEL : 6; /*!< [5:0] DAC Output Voltage Select */ - uint8_t VRSEL : 1; /*!< [6] Supply Voltage Reference Source Select */ - uint8_t DACEN : 1; /*!< [7] DAC Enable */ - } B; -} hw_cmp_daccr_t; - -/*! - * @name Constants and macros for entire CMP_DACCR register - */ -/*@{*/ -#define HW_CMP_DACCR_ADDR(x) ((x) + 0x4U) - -#define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x)) -#define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U) -#define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v)) -#define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v))) -#define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v))) -#define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_DACCR bitfields - */ - -/*! - * @name Register CMP_DACCR, field VOSEL[5:0] (RW) - * - * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) * - * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in . - */ -/*@{*/ -#define BP_CMP_DACCR_VOSEL (0U) /*!< Bit position for CMP_DACCR_VOSEL. */ -#define BM_CMP_DACCR_VOSEL (0x3FU) /*!< Bit mask for CMP_DACCR_VOSEL. */ -#define BS_CMP_DACCR_VOSEL (6U) /*!< Bit field size in bits for CMP_DACCR_VOSEL. */ - -/*! @brief Read current value of the CMP_DACCR_VOSEL field. */ -#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL) - -/*! @brief Format value for bitfield CMP_DACCR_VOSEL. */ -#define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL) - -/*! @brief Set the VOSEL field to a new value. */ -#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v))) -/*@}*/ - -/*! - * @name Register CMP_DACCR, field VRSEL[6] (RW) - * - * Values: - * - 0 - V is selected as resistor ladder network supply reference V. in1 in - * - 1 - V is selected as resistor ladder network supply reference V. in2 in - */ -/*@{*/ -#define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */ -#define BM_CMP_DACCR_VRSEL (0x40U) /*!< Bit mask for CMP_DACCR_VRSEL. */ -#define BS_CMP_DACCR_VRSEL (1U) /*!< Bit field size in bits for CMP_DACCR_VRSEL. */ - -/*! @brief Read current value of the CMP_DACCR_VRSEL field. */ -#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL)) - -/*! @brief Format value for bitfield CMP_DACCR_VRSEL. */ -#define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL) - -/*! @brief Set the VRSEL field to a new value. */ -#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v)) -/*@}*/ - -/*! - * @name Register CMP_DACCR, field DACEN[7] (RW) - * - * Enables the DAC. When the DAC is disabled, it is powered down to conserve - * power. - * - * Values: - * - 0 - DAC is disabled. - * - 1 - DAC is enabled. - */ -/*@{*/ -#define BP_CMP_DACCR_DACEN (7U) /*!< Bit position for CMP_DACCR_DACEN. */ -#define BM_CMP_DACCR_DACEN (0x80U) /*!< Bit mask for CMP_DACCR_DACEN. */ -#define BS_CMP_DACCR_DACEN (1U) /*!< Bit field size in bits for CMP_DACCR_DACEN. */ - -/*! @brief Read current value of the CMP_DACCR_DACEN field. */ -#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN)) - -/*! @brief Format value for bitfield CMP_DACCR_DACEN. */ -#define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN) - -/*! @brief Set the DACEN field to a new value. */ -#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_MUXCR - MUX Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_MUXCR - MUX Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_muxcr -{ - uint8_t U; - struct _hw_cmp_muxcr_bitfields - { - uint8_t MSEL : 3; /*!< [2:0] Minus Input Mux Control */ - uint8_t PSEL : 3; /*!< [5:3] Plus Input Mux Control */ - uint8_t RESERVED0 : 2; /*!< [7:6] Bit can be programmed to zero only - * . */ - } B; -} hw_cmp_muxcr_t; - -/*! - * @name Constants and macros for entire CMP_MUXCR register - */ -/*@{*/ -#define HW_CMP_MUXCR_ADDR(x) ((x) + 0x5U) - -#define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x)) -#define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U) -#define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v)) -#define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v))) -#define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v))) -#define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_MUXCR bitfields - */ - -/*! - * @name Register CMP_MUXCR, field MSEL[2:0] (RW) - * - * Determines which input is selected for the minus input of the comparator. For - * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate - * operation selects the same input for both muxes, the comparator automatically - * shuts down to prevent itself from becoming a noise generator. - * - * Values: - * - 000 - IN0 - * - 001 - IN1 - * - 010 - IN2 - * - 011 - IN3 - * - 100 - IN4 - * - 101 - IN5 - * - 110 - IN6 - * - 111 - IN7 - */ -/*@{*/ -#define BP_CMP_MUXCR_MSEL (0U) /*!< Bit position for CMP_MUXCR_MSEL. */ -#define BM_CMP_MUXCR_MSEL (0x07U) /*!< Bit mask for CMP_MUXCR_MSEL. */ -#define BS_CMP_MUXCR_MSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_MSEL. */ - -/*! @brief Read current value of the CMP_MUXCR_MSEL field. */ -#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL) - -/*! @brief Format value for bitfield CMP_MUXCR_MSEL. */ -#define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL) - -/*! @brief Set the MSEL field to a new value. */ -#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v))) -/*@}*/ - -/*! - * @name Register CMP_MUXCR, field PSEL[5:3] (RW) - * - * Determines which input is selected for the plus input of the comparator. For - * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate - * operation selects the same input for both muxes, the comparator automatically - * shuts down to prevent itself from becoming a noise generator. - * - * Values: - * - 000 - IN0 - * - 001 - IN1 - * - 010 - IN2 - * - 011 - IN3 - * - 100 - IN4 - * - 101 - IN5 - * - 110 - IN6 - * - 111 - IN7 - */ -/*@{*/ -#define BP_CMP_MUXCR_PSEL (3U) /*!< Bit position for CMP_MUXCR_PSEL. */ -#define BM_CMP_MUXCR_PSEL (0x38U) /*!< Bit mask for CMP_MUXCR_PSEL. */ -#define BS_CMP_MUXCR_PSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_PSEL. */ - -/*! @brief Read current value of the CMP_MUXCR_PSEL field. */ -#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL) - -/*! @brief Format value for bitfield CMP_MUXCR_PSEL. */ -#define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL) - -/*! @brief Set the PSEL field to a new value. */ -#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v))) -/*@}*/ - -/******************************************************************************* - * hw_cmp_t - module struct - ******************************************************************************/ -/*! - * @brief All CMP module registers. - */ -#pragma pack(1) -typedef struct _hw_cmp -{ - __IO hw_cmp_cr0_t CR0; /*!< [0x0] CMP Control Register 0 */ - __IO hw_cmp_cr1_t CR1; /*!< [0x1] CMP Control Register 1 */ - __IO hw_cmp_fpr_t FPR; /*!< [0x2] CMP Filter Period Register */ - __IO hw_cmp_scr_t SCR; /*!< [0x3] CMP Status and Control Register */ - __IO hw_cmp_daccr_t DACCR; /*!< [0x4] DAC Control Register */ - __IO hw_cmp_muxcr_t MUXCR; /*!< [0x5] MUX Control Register */ -} hw_cmp_t; -#pragma pack() - -/*! @brief Macro to access all CMP registers. */ -/*! @param x CMP module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CMP(CMP0_BASE). */ -#define HW_CMP(x) (*(hw_cmp_t *)(x)) - -#endif /* __HW_CMP_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h deleted file mode 100644 index 00f2a723abe..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h +++ /dev/null @@ -1,1406 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CRC_REGISTERS_H__ -#define __HW_CRC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 CRC - * - * Cyclic Redundancy Check - * - * Registers defined in this header file: - * - HW_CRC_DATAL - CRC_DATAL register. - * - HW_CRC_DATAH - CRC_DATAH register. - * - HW_CRC_DATALL - CRC_DATALL register. - * - HW_CRC_DATALU - CRC_DATALU register. - * - HW_CRC_DATAHL - CRC_DATAHL register. - * - HW_CRC_DATAHU - CRC_DATAHU register. - * - HW_CRC_DATA - CRC Data register - * - HW_CRC_GPOLY - CRC Polynomial register - * - HW_CRC_GPOLYL - CRC_GPOLYL register. - * - HW_CRC_GPOLYH - CRC_GPOLYH register. - * - HW_CRC_GPOLYLL - CRC_GPOLYLL register. - * - HW_CRC_GPOLYLU - CRC_GPOLYLU register. - * - HW_CRC_GPOLYHL - CRC_GPOLYHL register. - * - HW_CRC_GPOLYHU - CRC_GPOLYHU register. - * - HW_CRC_CTRL - CRC Control register - * - HW_CRC_CTRLHU - CRC_CTRLHU register. - * - * - hw_crc_t - Struct containing all module registers. - */ - -#define HW_CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */ - -/******************************************************************************* - * HW_CRC_DATAL - CRC_DATAL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAL - CRC_DATAL register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_datal -{ - uint16_t U; - struct _hw_crc_datal_bitfields - { - uint16_t DATAL : 16; /*!< [15:0] DATAL stores the lower 16 bits of - * the 16/32 bit CRC */ - } B; -} hw_crc_datal_t; - -/*! - * @name Constants and macros for entire CRC_DATAL register - */ -/*@{*/ -#define HW_CRC_DATAL_ADDR(x) ((x) + 0x0U) - -#define HW_CRC_DATAL(x) (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR(x)) -#define HW_CRC_DATAL_RD(x) (HW_CRC_DATAL(x).U) -#define HW_CRC_DATAL_WR(x, v) (HW_CRC_DATAL(x).U = (v)) -#define HW_CRC_DATAL_SET(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) | (v))) -#define HW_CRC_DATAL_CLR(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v))) -#define HW_CRC_DATAL_TOG(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAL bitfields - */ - -/*! - * @name Register CRC_DATAL, field DATAL[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAL_DATAL (0U) /*!< Bit position for CRC_DATAL_DATAL. */ -#define BM_CRC_DATAL_DATAL (0xFFFFU) /*!< Bit mask for CRC_DATAL_DATAL. */ -#define BS_CRC_DATAL_DATAL (16U) /*!< Bit field size in bits for CRC_DATAL_DATAL. */ - -/*! @brief Read current value of the CRC_DATAL_DATAL field. */ -#define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U) - -/*! @brief Format value for bitfield CRC_DATAL_DATAL. */ -#define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL) - -/*! @brief Set the DATAL field to a new value. */ -#define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATAH - CRC_DATAH register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAH - CRC_DATAH register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_datah -{ - uint16_t U; - struct _hw_crc_datah_bitfields - { - uint16_t DATAH : 16; /*!< [15:0] DATAH stores the high 16 bits of the - * 16/32 bit CRC */ - } B; -} hw_crc_datah_t; - -/*! - * @name Constants and macros for entire CRC_DATAH register - */ -/*@{*/ -#define HW_CRC_DATAH_ADDR(x) ((x) + 0x2U) - -#define HW_CRC_DATAH(x) (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR(x)) -#define HW_CRC_DATAH_RD(x) (HW_CRC_DATAH(x).U) -#define HW_CRC_DATAH_WR(x, v) (HW_CRC_DATAH(x).U = (v)) -#define HW_CRC_DATAH_SET(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) | (v))) -#define HW_CRC_DATAH_CLR(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v))) -#define HW_CRC_DATAH_TOG(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAH bitfields - */ - -/*! - * @name Register CRC_DATAH, field DATAH[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAH_DATAH (0U) /*!< Bit position for CRC_DATAH_DATAH. */ -#define BM_CRC_DATAH_DATAH (0xFFFFU) /*!< Bit mask for CRC_DATAH_DATAH. */ -#define BS_CRC_DATAH_DATAH (16U) /*!< Bit field size in bits for CRC_DATAH_DATAH. */ - -/*! @brief Read current value of the CRC_DATAH_DATAH field. */ -#define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U) - -/*! @brief Format value for bitfield CRC_DATAH_DATAH. */ -#define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH) - -/*! @brief Set the DATAH field to a new value. */ -#define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATALL - CRC_DATALL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATALL - CRC_DATALL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datall -{ - uint8_t U; - struct _hw_crc_datall_bitfields - { - uint8_t DATALL : 8; /*!< [7:0] CRCLL stores the first 8 bits of the - * 32 bit DATA */ - } B; -} hw_crc_datall_t; - -/*! - * @name Constants and macros for entire CRC_DATALL register - */ -/*@{*/ -#define HW_CRC_DATALL_ADDR(x) ((x) + 0x0U) - -#define HW_CRC_DATALL(x) (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR(x)) -#define HW_CRC_DATALL_RD(x) (HW_CRC_DATALL(x).U) -#define HW_CRC_DATALL_WR(x, v) (HW_CRC_DATALL(x).U = (v)) -#define HW_CRC_DATALL_SET(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) | (v))) -#define HW_CRC_DATALL_CLR(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v))) -#define HW_CRC_DATALL_TOG(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATALL bitfields - */ - -/*! - * @name Register CRC_DATALL, field DATALL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATALL_DATALL (0U) /*!< Bit position for CRC_DATALL_DATALL. */ -#define BM_CRC_DATALL_DATALL (0xFFU) /*!< Bit mask for CRC_DATALL_DATALL. */ -#define BS_CRC_DATALL_DATALL (8U) /*!< Bit field size in bits for CRC_DATALL_DATALL. */ - -/*! @brief Read current value of the CRC_DATALL_DATALL field. */ -#define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U) - -/*! @brief Format value for bitfield CRC_DATALL_DATALL. */ -#define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL) - -/*! @brief Set the DATALL field to a new value. */ -#define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATALU - CRC_DATALU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATALU - CRC_DATALU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datalu -{ - uint8_t U; - struct _hw_crc_datalu_bitfields - { - uint8_t DATALU : 8; /*!< [7:0] DATALL stores the second 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_datalu_t; - -/*! - * @name Constants and macros for entire CRC_DATALU register - */ -/*@{*/ -#define HW_CRC_DATALU_ADDR(x) ((x) + 0x1U) - -#define HW_CRC_DATALU(x) (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR(x)) -#define HW_CRC_DATALU_RD(x) (HW_CRC_DATALU(x).U) -#define HW_CRC_DATALU_WR(x, v) (HW_CRC_DATALU(x).U = (v)) -#define HW_CRC_DATALU_SET(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) | (v))) -#define HW_CRC_DATALU_CLR(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v))) -#define HW_CRC_DATALU_TOG(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATALU bitfields - */ - -/*! - * @name Register CRC_DATALU, field DATALU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATALU_DATALU (0U) /*!< Bit position for CRC_DATALU_DATALU. */ -#define BM_CRC_DATALU_DATALU (0xFFU) /*!< Bit mask for CRC_DATALU_DATALU. */ -#define BS_CRC_DATALU_DATALU (8U) /*!< Bit field size in bits for CRC_DATALU_DATALU. */ - -/*! @brief Read current value of the CRC_DATALU_DATALU field. */ -#define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U) - -/*! @brief Format value for bitfield CRC_DATALU_DATALU. */ -#define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU) - -/*! @brief Set the DATALU field to a new value. */ -#define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATAHL - CRC_DATAHL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datahl -{ - uint8_t U; - struct _hw_crc_datahl_bitfields - { - uint8_t DATAHL : 8; /*!< [7:0] DATAHL stores the third 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_datahl_t; - -/*! - * @name Constants and macros for entire CRC_DATAHL register - */ -/*@{*/ -#define HW_CRC_DATAHL_ADDR(x) ((x) + 0x2U) - -#define HW_CRC_DATAHL(x) (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR(x)) -#define HW_CRC_DATAHL_RD(x) (HW_CRC_DATAHL(x).U) -#define HW_CRC_DATAHL_WR(x, v) (HW_CRC_DATAHL(x).U = (v)) -#define HW_CRC_DATAHL_SET(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) | (v))) -#define HW_CRC_DATAHL_CLR(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v))) -#define HW_CRC_DATAHL_TOG(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAHL bitfields - */ - -/*! - * @name Register CRC_DATAHL, field DATAHL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAHL_DATAHL (0U) /*!< Bit position for CRC_DATAHL_DATAHL. */ -#define BM_CRC_DATAHL_DATAHL (0xFFU) /*!< Bit mask for CRC_DATAHL_DATAHL. */ -#define BS_CRC_DATAHL_DATAHL (8U) /*!< Bit field size in bits for CRC_DATAHL_DATAHL. */ - -/*! @brief Read current value of the CRC_DATAHL_DATAHL field. */ -#define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U) - -/*! @brief Format value for bitfield CRC_DATAHL_DATAHL. */ -#define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL) - -/*! @brief Set the DATAHL field to a new value. */ -#define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATAHU - CRC_DATAHU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datahu -{ - uint8_t U; - struct _hw_crc_datahu_bitfields - { - uint8_t DATAHU : 8; /*!< [7:0] DATAHU stores the fourth 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_datahu_t; - -/*! - * @name Constants and macros for entire CRC_DATAHU register - */ -/*@{*/ -#define HW_CRC_DATAHU_ADDR(x) ((x) + 0x3U) - -#define HW_CRC_DATAHU(x) (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR(x)) -#define HW_CRC_DATAHU_RD(x) (HW_CRC_DATAHU(x).U) -#define HW_CRC_DATAHU_WR(x, v) (HW_CRC_DATAHU(x).U = (v)) -#define HW_CRC_DATAHU_SET(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) | (v))) -#define HW_CRC_DATAHU_CLR(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v))) -#define HW_CRC_DATAHU_TOG(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAHU bitfields - */ - -/*! - * @name Register CRC_DATAHU, field DATAHU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAHU_DATAHU (0U) /*!< Bit position for CRC_DATAHU_DATAHU. */ -#define BM_CRC_DATAHU_DATAHU (0xFFU) /*!< Bit mask for CRC_DATAHU_DATAHU. */ -#define BS_CRC_DATAHU_DATAHU (8U) /*!< Bit field size in bits for CRC_DATAHU_DATAHU. */ - -/*! @brief Read current value of the CRC_DATAHU_DATAHU field. */ -#define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U) - -/*! @brief Format value for bitfield CRC_DATAHU_DATAHU. */ -#define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU) - -/*! @brief Set the DATAHU field to a new value. */ -#define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATA - CRC Data register - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATA - CRC Data register (RW) - * - * Reset value: 0xFFFFFFFFU - * - * The CRC Data register contains the value of the seed, data, and checksum. - * When CTRL[WAS] is set, any write to the data register is regarded as the seed - * value. When CTRL[WAS] is cleared, any write to the data register is regarded as - * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are - * not used for programming the seed value, and reads of these fields return an - * indeterminate value. In 32-bit CRC mode, all fields are used for programming - * the seed value. When programming data values, the values can be written 8 bits, - * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of - * data value written first. After all data values are written, the CRC result - * can be read from this data register. In 16-bit CRC mode, the CRC result is - * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the - * result. Reads of this register at any time return the intermediate CRC value, - * provided the CRC module is configured. - */ -typedef union _hw_crc_data -{ - uint32_t U; - struct _hw_crc_data_bitfields - { - uint32_t LL : 8; /*!< [7:0] CRC Low Lower Byte */ - uint32_t LU : 8; /*!< [15:8] CRC Low Upper Byte */ - uint32_t HL : 8; /*!< [23:16] CRC High Lower Byte */ - uint32_t HU : 8; /*!< [31:24] CRC High Upper Byte */ - } B; -} hw_crc_data_t; - -/*! - * @name Constants and macros for entire CRC_DATA register - */ -/*@{*/ -#define HW_CRC_DATA_ADDR(x) ((x) + 0x0U) - -#define HW_CRC_DATA(x) (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR(x)) -#define HW_CRC_DATA_RD(x) (HW_CRC_DATA(x).U) -#define HW_CRC_DATA_WR(x, v) (HW_CRC_DATA(x).U = (v)) -#define HW_CRC_DATA_SET(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) | (v))) -#define HW_CRC_DATA_CLR(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v))) -#define HW_CRC_DATA_TOG(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATA bitfields - */ - -/*! - * @name Register CRC_DATA, field LL[7:0] (RW) - * - * When CTRL[WAS] is 1, values written to this field are part of the seed value. - * When CTRL[WAS] is 0, data written to this field is used for CRC checksum - * generation. - */ -/*@{*/ -#define BP_CRC_DATA_LL (0U) /*!< Bit position for CRC_DATA_LL. */ -#define BM_CRC_DATA_LL (0x000000FFU) /*!< Bit mask for CRC_DATA_LL. */ -#define BS_CRC_DATA_LL (8U) /*!< Bit field size in bits for CRC_DATA_LL. */ - -/*! @brief Read current value of the CRC_DATA_LL field. */ -#define BR_CRC_DATA_LL(x) (HW_CRC_DATA(x).B.LL) - -/*! @brief Format value for bitfield CRC_DATA_LL. */ -#define BF_CRC_DATA_LL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL) - -/*! @brief Set the LL field to a new value. */ -#define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v))) -/*@}*/ - -/*! - * @name Register CRC_DATA, field LU[15:8] (RW) - * - * When CTRL[WAS] is 1, values written to this field are part of the seed value. - * When CTRL[WAS] is 0, data written to this field is used for CRC checksum - * generation. - */ -/*@{*/ -#define BP_CRC_DATA_LU (8U) /*!< Bit position for CRC_DATA_LU. */ -#define BM_CRC_DATA_LU (0x0000FF00U) /*!< Bit mask for CRC_DATA_LU. */ -#define BS_CRC_DATA_LU (8U) /*!< Bit field size in bits for CRC_DATA_LU. */ - -/*! @brief Read current value of the CRC_DATA_LU field. */ -#define BR_CRC_DATA_LU(x) (HW_CRC_DATA(x).B.LU) - -/*! @brief Format value for bitfield CRC_DATA_LU. */ -#define BF_CRC_DATA_LU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU) - -/*! @brief Set the LU field to a new value. */ -#define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v))) -/*@}*/ - -/*! - * @name Register CRC_DATA, field HL[23:16] (RW) - * - * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming - * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this - * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data - * written to this field is used for CRC checksum generation in both 16-bit and - * 32-bit CRC modes. - */ -/*@{*/ -#define BP_CRC_DATA_HL (16U) /*!< Bit position for CRC_DATA_HL. */ -#define BM_CRC_DATA_HL (0x00FF0000U) /*!< Bit mask for CRC_DATA_HL. */ -#define BS_CRC_DATA_HL (8U) /*!< Bit field size in bits for CRC_DATA_HL. */ - -/*! @brief Read current value of the CRC_DATA_HL field. */ -#define BR_CRC_DATA_HL(x) (HW_CRC_DATA(x).B.HL) - -/*! @brief Format value for bitfield CRC_DATA_HL. */ -#define BF_CRC_DATA_HL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL) - -/*! @brief Set the HL field to a new value. */ -#define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v))) -/*@}*/ - -/*! - * @name Register CRC_DATA, field HU[31:24] (RW) - * - * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming - * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this - * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data - * written to this field is used for CRC checksum generation in both 16-bit and - * 32-bit CRC modes. - */ -/*@{*/ -#define BP_CRC_DATA_HU (24U) /*!< Bit position for CRC_DATA_HU. */ -#define BM_CRC_DATA_HU (0xFF000000U) /*!< Bit mask for CRC_DATA_HU. */ -#define BS_CRC_DATA_HU (8U) /*!< Bit field size in bits for CRC_DATA_HU. */ - -/*! @brief Read current value of the CRC_DATA_HU field. */ -#define BR_CRC_DATA_HU(x) (HW_CRC_DATA(x).B.HU) - -/*! @brief Format value for bitfield CRC_DATA_HU. */ -#define BF_CRC_DATA_HU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU) - -/*! @brief Set the HU field to a new value. */ -#define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v))) -/*@}*/ - -/******************************************************************************* - * HW_CRC_GPOLY - CRC Polynomial register - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLY - CRC Polynomial register (RW) - * - * Reset value: 0x00001021U - * - * This register contains the value of the polynomial for the CRC calculation. - * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used - * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC - * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are - * used in both 16- and 32-bit CRC modes. - */ -typedef union _hw_crc_gpoly -{ - uint32_t U; - struct _hw_crc_gpoly_bitfields - { - uint32_t LOW : 16; /*!< [15:0] Low Polynominal Half-word */ - uint32_t HIGH : 16; /*!< [31:16] High Polynominal Half-word */ - } B; -} hw_crc_gpoly_t; - -/*! - * @name Constants and macros for entire CRC_GPOLY register - */ -/*@{*/ -#define HW_CRC_GPOLY_ADDR(x) ((x) + 0x4U) - -#define HW_CRC_GPOLY(x) (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR(x)) -#define HW_CRC_GPOLY_RD(x) (HW_CRC_GPOLY(x).U) -#define HW_CRC_GPOLY_WR(x, v) (HW_CRC_GPOLY(x).U = (v)) -#define HW_CRC_GPOLY_SET(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) | (v))) -#define HW_CRC_GPOLY_CLR(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v))) -#define HW_CRC_GPOLY_TOG(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLY bitfields - */ - -/*! - * @name Register CRC_GPOLY, field LOW[15:0] (RW) - * - * Writable and readable in both 32-bit and 16-bit CRC modes. - */ -/*@{*/ -#define BP_CRC_GPOLY_LOW (0U) /*!< Bit position for CRC_GPOLY_LOW. */ -#define BM_CRC_GPOLY_LOW (0x0000FFFFU) /*!< Bit mask for CRC_GPOLY_LOW. */ -#define BS_CRC_GPOLY_LOW (16U) /*!< Bit field size in bits for CRC_GPOLY_LOW. */ - -/*! @brief Read current value of the CRC_GPOLY_LOW field. */ -#define BR_CRC_GPOLY_LOW(x) (HW_CRC_GPOLY(x).B.LOW) - -/*! @brief Format value for bitfield CRC_GPOLY_LOW. */ -#define BF_CRC_GPOLY_LOW(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW) - -/*! @brief Set the LOW field to a new value. */ -#define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v))) -/*@}*/ - -/*! - * @name Register CRC_GPOLY, field HIGH[31:16] (RW) - * - * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not - * writable in 16-bit CRC mode (CTRL[TCRC] is 0). - */ -/*@{*/ -#define BP_CRC_GPOLY_HIGH (16U) /*!< Bit position for CRC_GPOLY_HIGH. */ -#define BM_CRC_GPOLY_HIGH (0xFFFF0000U) /*!< Bit mask for CRC_GPOLY_HIGH. */ -#define BS_CRC_GPOLY_HIGH (16U) /*!< Bit field size in bits for CRC_GPOLY_HIGH. */ - -/*! @brief Read current value of the CRC_GPOLY_HIGH field. */ -#define BR_CRC_GPOLY_HIGH(x) (HW_CRC_GPOLY(x).B.HIGH) - -/*! @brief Format value for bitfield CRC_GPOLY_HIGH. */ -#define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH) - -/*! @brief Set the HIGH field to a new value. */ -#define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v))) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYL - CRC_GPOLYL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_gpolyl -{ - uint16_t U; - struct _hw_crc_gpolyl_bitfields - { - uint16_t GPOLYL : 16; /*!< [15:0] POLYL stores the lower 16 bits of - * the 16/32 bit CRC polynomial value */ - } B; -} hw_crc_gpolyl_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYL register - */ -/*@{*/ -#define HW_CRC_GPOLYL_ADDR(x) ((x) + 0x4U) - -#define HW_CRC_GPOLYL(x) (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR(x)) -#define HW_CRC_GPOLYL_RD(x) (HW_CRC_GPOLYL(x).U) -#define HW_CRC_GPOLYL_WR(x, v) (HW_CRC_GPOLYL(x).U = (v)) -#define HW_CRC_GPOLYL_SET(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) | (v))) -#define HW_CRC_GPOLYL_CLR(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v))) -#define HW_CRC_GPOLYL_TOG(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYL bitfields - */ - -/*! - * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYL_GPOLYL (0U) /*!< Bit position for CRC_GPOLYL_GPOLYL. */ -#define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) /*!< Bit mask for CRC_GPOLYL_GPOLYL. */ -#define BS_CRC_GPOLYL_GPOLYL (16U) /*!< Bit field size in bits for CRC_GPOLYL_GPOLYL. */ - -/*! @brief Read current value of the CRC_GPOLYL_GPOLYL field. */ -#define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. */ -#define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL) - -/*! @brief Set the GPOLYL field to a new value. */ -#define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYH - CRC_GPOLYH register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_gpolyh -{ - uint16_t U; - struct _hw_crc_gpolyh_bitfields - { - uint16_t GPOLYH : 16; /*!< [15:0] POLYH stores the high 16 bits of - * the 16/32 bit CRC polynomial value */ - } B; -} hw_crc_gpolyh_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYH register - */ -/*@{*/ -#define HW_CRC_GPOLYH_ADDR(x) ((x) + 0x6U) - -#define HW_CRC_GPOLYH(x) (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR(x)) -#define HW_CRC_GPOLYH_RD(x) (HW_CRC_GPOLYH(x).U) -#define HW_CRC_GPOLYH_WR(x, v) (HW_CRC_GPOLYH(x).U = (v)) -#define HW_CRC_GPOLYH_SET(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) | (v))) -#define HW_CRC_GPOLYH_CLR(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v))) -#define HW_CRC_GPOLYH_TOG(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYH bitfields - */ - -/*! - * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYH_GPOLYH (0U) /*!< Bit position for CRC_GPOLYH_GPOLYH. */ -#define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) /*!< Bit mask for CRC_GPOLYH_GPOLYH. */ -#define BS_CRC_GPOLYH_GPOLYH (16U) /*!< Bit field size in bits for CRC_GPOLYH_GPOLYH. */ - -/*! @brief Read current value of the CRC_GPOLYH_GPOLYH field. */ -#define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. */ -#define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH) - -/*! @brief Set the GPOLYH field to a new value. */ -#define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYLL - CRC_GPOLYLL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolyll -{ - uint8_t U; - struct _hw_crc_gpolyll_bitfields - { - uint8_t GPOLYLL : 8; /*!< [7:0] POLYLL stores the first 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_gpolyll_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYLL register - */ -/*@{*/ -#define HW_CRC_GPOLYLL_ADDR(x) ((x) + 0x4U) - -#define HW_CRC_GPOLYLL(x) (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR(x)) -#define HW_CRC_GPOLYLL_RD(x) (HW_CRC_GPOLYLL(x).U) -#define HW_CRC_GPOLYLL_WR(x, v) (HW_CRC_GPOLYLL(x).U = (v)) -#define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) | (v))) -#define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v))) -#define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYLL bitfields - */ - -/*! - * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYLL_GPOLYLL (0U) /*!< Bit position for CRC_GPOLYLL_GPOLYLL. */ -#define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) /*!< Bit mask for CRC_GPOLYLL_GPOLYLL. */ -#define BS_CRC_GPOLYLL_GPOLYLL (8U) /*!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. */ - -/*! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. */ -#define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. */ -#define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL) - -/*! @brief Set the GPOLYLL field to a new value. */ -#define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYLU - CRC_GPOLYLU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolylu -{ - uint8_t U; - struct _hw_crc_gpolylu_bitfields - { - uint8_t GPOLYLU : 8; /*!< [7:0] POLYLL stores the second 8 bits of - * the 32 bit CRC */ - } B; -} hw_crc_gpolylu_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYLU register - */ -/*@{*/ -#define HW_CRC_GPOLYLU_ADDR(x) ((x) + 0x5U) - -#define HW_CRC_GPOLYLU(x) (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR(x)) -#define HW_CRC_GPOLYLU_RD(x) (HW_CRC_GPOLYLU(x).U) -#define HW_CRC_GPOLYLU_WR(x, v) (HW_CRC_GPOLYLU(x).U = (v)) -#define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) | (v))) -#define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v))) -#define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYLU bitfields - */ - -/*! - * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYLU_GPOLYLU (0U) /*!< Bit position for CRC_GPOLYLU_GPOLYLU. */ -#define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) /*!< Bit mask for CRC_GPOLYLU_GPOLYLU. */ -#define BS_CRC_GPOLYLU_GPOLYLU (8U) /*!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. */ - -/*! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. */ -#define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. */ -#define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU) - -/*! @brief Set the GPOLYLU field to a new value. */ -#define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYHL - CRC_GPOLYHL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolyhl -{ - uint8_t U; - struct _hw_crc_gpolyhl_bitfields - { - uint8_t GPOLYHL : 8; /*!< [7:0] POLYHL stores the third 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_gpolyhl_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYHL register - */ -/*@{*/ -#define HW_CRC_GPOLYHL_ADDR(x) ((x) + 0x6U) - -#define HW_CRC_GPOLYHL(x) (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR(x)) -#define HW_CRC_GPOLYHL_RD(x) (HW_CRC_GPOLYHL(x).U) -#define HW_CRC_GPOLYHL_WR(x, v) (HW_CRC_GPOLYHL(x).U = (v)) -#define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) | (v))) -#define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v))) -#define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYHL bitfields - */ - -/*! - * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYHL_GPOLYHL (0U) /*!< Bit position for CRC_GPOLYHL_GPOLYHL. */ -#define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) /*!< Bit mask for CRC_GPOLYHL_GPOLYHL. */ -#define BS_CRC_GPOLYHL_GPOLYHL (8U) /*!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. */ - -/*! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. */ -#define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. */ -#define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL) - -/*! @brief Set the GPOLYHL field to a new value. */ -#define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYHU - CRC_GPOLYHU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolyhu -{ - uint8_t U; - struct _hw_crc_gpolyhu_bitfields - { - uint8_t GPOLYHU : 8; /*!< [7:0] POLYHU stores the fourth 8 bits of - * the 32 bit CRC */ - } B; -} hw_crc_gpolyhu_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYHU register - */ -/*@{*/ -#define HW_CRC_GPOLYHU_ADDR(x) ((x) + 0x7U) - -#define HW_CRC_GPOLYHU(x) (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR(x)) -#define HW_CRC_GPOLYHU_RD(x) (HW_CRC_GPOLYHU(x).U) -#define HW_CRC_GPOLYHU_WR(x, v) (HW_CRC_GPOLYHU(x).U = (v)) -#define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) | (v))) -#define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v))) -#define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYHU bitfields - */ - -/*! - * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYHU_GPOLYHU (0U) /*!< Bit position for CRC_GPOLYHU_GPOLYHU. */ -#define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) /*!< Bit mask for CRC_GPOLYHU_GPOLYHU. */ -#define BS_CRC_GPOLYHU_GPOLYHU (8U) /*!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. */ - -/*! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. */ -#define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. */ -#define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU) - -/*! @brief Set the GPOLYHU field to a new value. */ -#define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CRC_CTRL - CRC Control register - ******************************************************************************/ - -/*! - * @brief HW_CRC_CTRL - CRC Control register (RW) - * - * Reset value: 0x00000000U - * - * This register controls the configuration and working of the CRC module. - * Appropriate bits must be set before starting a new CRC calculation. A new CRC - * calculation is initialized by asserting CTRL[WAS] and then writing the seed into - * the CRC data register. - */ -typedef union _hw_crc_ctrl -{ - uint32_t U; - struct _hw_crc_ctrl_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t TCRC : 1; /*!< [24] */ - uint32_t WAS : 1; /*!< [25] Write CRC Data Register As Seed */ - uint32_t FXOR : 1; /*!< [26] Complement Read Of CRC Data Register */ - uint32_t RESERVED1 : 1; /*!< [27] */ - uint32_t TOTR : 2; /*!< [29:28] Type Of Transpose For Read */ - uint32_t TOT : 2; /*!< [31:30] Type Of Transpose For Writes */ - } B; -} hw_crc_ctrl_t; - -/*! - * @name Constants and macros for entire CRC_CTRL register - */ -/*@{*/ -#define HW_CRC_CTRL_ADDR(x) ((x) + 0x8U) - -#define HW_CRC_CTRL(x) (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR(x)) -#define HW_CRC_CTRL_RD(x) (HW_CRC_CTRL(x).U) -#define HW_CRC_CTRL_WR(x, v) (HW_CRC_CTRL(x).U = (v)) -#define HW_CRC_CTRL_SET(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) | (v))) -#define HW_CRC_CTRL_CLR(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v))) -#define HW_CRC_CTRL_TOG(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_CTRL bitfields - */ - -/*! - * @name Register CRC_CTRL, field TCRC[24] (RW) - * - * Width of CRC protocol. - * - * Values: - * - 0 - 16-bit CRC protocol. - * - 1 - 32-bit CRC protocol. - */ -/*@{*/ -#define BP_CRC_CTRL_TCRC (24U) /*!< Bit position for CRC_CTRL_TCRC. */ -#define BM_CRC_CTRL_TCRC (0x01000000U) /*!< Bit mask for CRC_CTRL_TCRC. */ -#define BS_CRC_CTRL_TCRC (1U) /*!< Bit field size in bits for CRC_CTRL_TCRC. */ - -/*! @brief Read current value of the CRC_CTRL_TCRC field. */ -#define BR_CRC_CTRL_TCRC(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC)) - -/*! @brief Format value for bitfield CRC_CTRL_TCRC. */ -#define BF_CRC_CTRL_TCRC(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC) - -/*! @brief Set the TCRC field to a new value. */ -#define BW_CRC_CTRL_TCRC(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field WAS[25] (RW) - * - * When asserted, a value written to the CRC data register is considered a seed - * value. When deasserted, a value written to the CRC data register is taken as - * data for CRC computation. - * - * Values: - * - 0 - Writes to the CRC data register are data values. - * - 1 - Writes to the CRC data register are seed values. - */ -/*@{*/ -#define BP_CRC_CTRL_WAS (25U) /*!< Bit position for CRC_CTRL_WAS. */ -#define BM_CRC_CTRL_WAS (0x02000000U) /*!< Bit mask for CRC_CTRL_WAS. */ -#define BS_CRC_CTRL_WAS (1U) /*!< Bit field size in bits for CRC_CTRL_WAS. */ - -/*! @brief Read current value of the CRC_CTRL_WAS field. */ -#define BR_CRC_CTRL_WAS(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS)) - -/*! @brief Format value for bitfield CRC_CTRL_WAS. */ -#define BF_CRC_CTRL_WAS(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS) - -/*! @brief Set the WAS field to a new value. */ -#define BW_CRC_CTRL_WAS(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field FXOR[26] (RW) - * - * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or - * 0xFFFF. Asserting this bit enables on the fly complementing of read data. - * - * Values: - * - 0 - No XOR on reading. - * - 1 - Invert or complement the read value of the CRC Data register. - */ -/*@{*/ -#define BP_CRC_CTRL_FXOR (26U) /*!< Bit position for CRC_CTRL_FXOR. */ -#define BM_CRC_CTRL_FXOR (0x04000000U) /*!< Bit mask for CRC_CTRL_FXOR. */ -#define BS_CRC_CTRL_FXOR (1U) /*!< Bit field size in bits for CRC_CTRL_FXOR. */ - -/*! @brief Read current value of the CRC_CTRL_FXOR field. */ -#define BR_CRC_CTRL_FXOR(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR)) - -/*! @brief Format value for bitfield CRC_CTRL_FXOR. */ -#define BF_CRC_CTRL_FXOR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR) - -/*! @brief Set the FXOR field to a new value. */ -#define BW_CRC_CTRL_FXOR(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field TOTR[29:28] (RW) - * - * Identifies the transpose configuration of the value read from the CRC Data - * register. See the description of the transpose feature for the available - * transpose options. - * - * Values: - * - 00 - No transposition. - * - 01 - Bits in bytes are transposed; bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRL_TOTR (28U) /*!< Bit position for CRC_CTRL_TOTR. */ -#define BM_CRC_CTRL_TOTR (0x30000000U) /*!< Bit mask for CRC_CTRL_TOTR. */ -#define BS_CRC_CTRL_TOTR (2U) /*!< Bit field size in bits for CRC_CTRL_TOTR. */ - -/*! @brief Read current value of the CRC_CTRL_TOTR field. */ -#define BR_CRC_CTRL_TOTR(x) (HW_CRC_CTRL(x).B.TOTR) - -/*! @brief Format value for bitfield CRC_CTRL_TOTR. */ -#define BF_CRC_CTRL_TOTR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR) - -/*! @brief Set the TOTR field to a new value. */ -#define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v))) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field TOT[31:30] (RW) - * - * Defines the transpose configuration of the data written to the CRC data - * register. See the description of the transpose feature for the available transpose - * options. - * - * Values: - * - 00 - No transposition. - * - 01 - Bits in bytes are transposed; bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRL_TOT (30U) /*!< Bit position for CRC_CTRL_TOT. */ -#define BM_CRC_CTRL_TOT (0xC0000000U) /*!< Bit mask for CRC_CTRL_TOT. */ -#define BS_CRC_CTRL_TOT (2U) /*!< Bit field size in bits for CRC_CTRL_TOT. */ - -/*! @brief Read current value of the CRC_CTRL_TOT field. */ -#define BR_CRC_CTRL_TOT(x) (HW_CRC_CTRL(x).B.TOT) - -/*! @brief Format value for bitfield CRC_CTRL_TOT. */ -#define BF_CRC_CTRL_TOT(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT) - -/*! @brief Set the TOT field to a new value. */ -#define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v))) -/*@}*/ -/******************************************************************************* - * HW_CRC_CTRLHU - CRC_CTRLHU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_crc_ctrlhu -{ - uint8_t U; - struct _hw_crc_ctrlhu_bitfields - { - uint8_t TCRC : 1; /*!< [0] */ - uint8_t WAS : 1; /*!< [1] */ - uint8_t FXOR : 1; /*!< [2] */ - uint8_t RESERVED0 : 1; /*!< [3] */ - uint8_t TOTR : 2; /*!< [5:4] */ - uint8_t TOT : 2; /*!< [7:6] */ - } B; -} hw_crc_ctrlhu_t; - -/*! - * @name Constants and macros for entire CRC_CTRLHU register - */ -/*@{*/ -#define HW_CRC_CTRLHU_ADDR(x) ((x) + 0xBU) - -#define HW_CRC_CTRLHU(x) (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR(x)) -#define HW_CRC_CTRLHU_RD(x) (HW_CRC_CTRLHU(x).U) -#define HW_CRC_CTRLHU_WR(x, v) (HW_CRC_CTRLHU(x).U = (v)) -#define HW_CRC_CTRLHU_SET(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) | (v))) -#define HW_CRC_CTRLHU_CLR(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v))) -#define HW_CRC_CTRLHU_TOG(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_CTRLHU bitfields - */ - -/*! - * @name Register CRC_CTRLHU, field TCRC[0] (RW) - * - * Values: - * - 0 - 16-bit CRC protocol. - * - 1 - 32-bit CRC protocol. - */ -/*@{*/ -#define BP_CRC_CTRLHU_TCRC (0U) /*!< Bit position for CRC_CTRLHU_TCRC. */ -#define BM_CRC_CTRLHU_TCRC (0x01U) /*!< Bit mask for CRC_CTRLHU_TCRC. */ -#define BS_CRC_CTRLHU_TCRC (1U) /*!< Bit field size in bits for CRC_CTRLHU_TCRC. */ - -/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */ -#define BR_CRC_CTRLHU_TCRC(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC)) - -/*! @brief Format value for bitfield CRC_CTRLHU_TCRC. */ -#define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC) - -/*! @brief Set the TCRC field to a new value. */ -#define BW_CRC_CTRLHU_TCRC(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field WAS[1] (RW) - * - * Values: - * - 0 - Writes to CRC data register are data values. - * - 1 - Writes to CRC data reguster are seed values. - */ -/*@{*/ -#define BP_CRC_CTRLHU_WAS (1U) /*!< Bit position for CRC_CTRLHU_WAS. */ -#define BM_CRC_CTRLHU_WAS (0x02U) /*!< Bit mask for CRC_CTRLHU_WAS. */ -#define BS_CRC_CTRLHU_WAS (1U) /*!< Bit field size in bits for CRC_CTRLHU_WAS. */ - -/*! @brief Read current value of the CRC_CTRLHU_WAS field. */ -#define BR_CRC_CTRLHU_WAS(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS)) - -/*! @brief Format value for bitfield CRC_CTRLHU_WAS. */ -#define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS) - -/*! @brief Set the WAS field to a new value. */ -#define BW_CRC_CTRLHU_WAS(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field FXOR[2] (RW) - * - * Values: - * - 0 - No XOR on reading. - * - 1 - Invert or complement the read value of CRC data register. - */ -/*@{*/ -#define BP_CRC_CTRLHU_FXOR (2U) /*!< Bit position for CRC_CTRLHU_FXOR. */ -#define BM_CRC_CTRLHU_FXOR (0x04U) /*!< Bit mask for CRC_CTRLHU_FXOR. */ -#define BS_CRC_CTRLHU_FXOR (1U) /*!< Bit field size in bits for CRC_CTRLHU_FXOR. */ - -/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */ -#define BR_CRC_CTRLHU_FXOR(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR)) - -/*! @brief Format value for bitfield CRC_CTRLHU_FXOR. */ -#define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR) - -/*! @brief Set the FXOR field to a new value. */ -#define BW_CRC_CTRLHU_FXOR(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field TOTR[5:4] (RW) - * - * Values: - * - 00 - No Transposition. - * - 01 - Bits in bytes are transposed, bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRLHU_TOTR (4U) /*!< Bit position for CRC_CTRLHU_TOTR. */ -#define BM_CRC_CTRLHU_TOTR (0x30U) /*!< Bit mask for CRC_CTRLHU_TOTR. */ -#define BS_CRC_CTRLHU_TOTR (2U) /*!< Bit field size in bits for CRC_CTRLHU_TOTR. */ - -/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */ -#define BR_CRC_CTRLHU_TOTR(x) (HW_CRC_CTRLHU(x).B.TOTR) - -/*! @brief Format value for bitfield CRC_CTRLHU_TOTR. */ -#define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR) - -/*! @brief Set the TOTR field to a new value. */ -#define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v))) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field TOT[7:6] (RW) - * - * Values: - * - 00 - No Transposition. - * - 01 - Bits in bytes are transposed, bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRLHU_TOT (6U) /*!< Bit position for CRC_CTRLHU_TOT. */ -#define BM_CRC_CTRLHU_TOT (0xC0U) /*!< Bit mask for CRC_CTRLHU_TOT. */ -#define BS_CRC_CTRLHU_TOT (2U) /*!< Bit field size in bits for CRC_CTRLHU_TOT. */ - -/*! @brief Read current value of the CRC_CTRLHU_TOT field. */ -#define BR_CRC_CTRLHU_TOT(x) (HW_CRC_CTRLHU(x).B.TOT) - -/*! @brief Format value for bitfield CRC_CTRLHU_TOT. */ -#define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT) - -/*! @brief Set the TOT field to a new value. */ -#define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v))) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_crc_t - module struct - ******************************************************************************/ -/*! - * @brief All CRC module registers. - */ -#pragma pack(1) -typedef struct _hw_crc -{ - union { - struct { - __IO hw_crc_datal_t DATAL; /*!< [0x0] CRC_DATAL register. */ - __IO hw_crc_datah_t DATAH; /*!< [0x2] CRC_DATAH register. */ - } ACCESS16BIT; - struct { - __IO hw_crc_datall_t DATALL; /*!< [0x0] CRC_DATALL register. */ - __IO hw_crc_datalu_t DATALU; /*!< [0x1] CRC_DATALU register. */ - __IO hw_crc_datahl_t DATAHL; /*!< [0x2] CRC_DATAHL register. */ - __IO hw_crc_datahu_t DATAHU; /*!< [0x3] CRC_DATAHU register. */ - } ACCESS8BIT; - __IO hw_crc_data_t DATA; /*!< [0x0] CRC Data register */ - }; - union { - __IO hw_crc_gpoly_t GPOLY; /*!< [0x4] CRC Polynomial register */ - struct { - __IO hw_crc_gpolyl_t GPOLYL; /*!< [0x4] CRC_GPOLYL register. */ - __IO hw_crc_gpolyh_t GPOLYH; /*!< [0x6] CRC_GPOLYH register. */ - } GPOLY_ACCESS16BIT; - struct { - __IO hw_crc_gpolyll_t GPOLYLL; /*!< [0x4] CRC_GPOLYLL register. */ - __IO hw_crc_gpolylu_t GPOLYLU; /*!< [0x5] CRC_GPOLYLU register. */ - __IO hw_crc_gpolyhl_t GPOLYHL; /*!< [0x6] CRC_GPOLYHL register. */ - __IO hw_crc_gpolyhu_t GPOLYHU; /*!< [0x7] CRC_GPOLYHU register. */ - } GPOLY_ACCESS8BIT; - }; - union { - __IO hw_crc_ctrl_t CTRL; /*!< [0x8] CRC Control register */ - struct { - uint8_t _reserved0[3]; - __IO hw_crc_ctrlhu_t CTRLHU; /*!< [0xB] CRC_CTRLHU register. */ - } CTRL_ACCESS8BIT; - }; -} hw_crc_t; -#pragma pack() - -/*! @brief Macro to access all CRC registers. */ -/*! @param x CRC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CRC(CRC_BASE). */ -#define HW_CRC(x) (*(hw_crc_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_CRC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h deleted file mode 100644 index 87d4272df02..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h +++ /dev/null @@ -1,837 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_DAC_REGISTERS_H__ -#define __HW_DAC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 DAC - * - * 12-Bit Digital-to-Analog Converter - * - * Registers defined in this header file: - * - HW_DAC_DATnL - DAC Data Low Register - * - HW_DAC_DATnH - DAC Data High Register - * - HW_DAC_SR - DAC Status Register - * - HW_DAC_C0 - DAC Control Register - * - HW_DAC_C1 - DAC Control Register 1 - * - HW_DAC_C2 - DAC Control Register 2 - * - * - hw_dac_t - Struct containing all module registers. - */ - -#define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */ -#define HW_DAC0 (0U) /*!< Instance number for DAC0. */ -#define HW_DAC1 (1U) /*!< Instance number for DAC1. */ - -/******************************************************************************* - * HW_DAC_DATnL - DAC Data Low Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_DATnL - DAC Data Low Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_dac_datnl -{ - uint8_t U; - struct _hw_dac_datnl_bitfields - { - uint8_t DATA0 : 8; /*!< [7:0] */ - } B; -} hw_dac_datnl_t; - -/*! - * @name Constants and macros for entire DAC_DATnL register - */ -/*@{*/ -#define HW_DAC_DATnL_COUNT (16U) - -#define HW_DAC_DATnL_ADDR(x, n) ((x) + 0x0U + (0x2U * (n))) - -#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n)) -#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U) -#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v)) -#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v))) -#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v))) -#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_DATnL bitfields - */ - -/*! - * @name Register DAC_DATnL, field DATA0[7:0] (RW) - * - * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage - * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the - * DAC buffer is enabled, DATA is mapped to the 16-word buffer. - */ -/*@{*/ -#define BP_DAC_DATnL_DATA0 (0U) /*!< Bit position for DAC_DATnL_DATA0. */ -#define BM_DAC_DATnL_DATA0 (0xFFU) /*!< Bit mask for DAC_DATnL_DATA0. */ -#define BS_DAC_DATnL_DATA0 (8U) /*!< Bit field size in bits for DAC_DATnL_DATA0. */ - -/*! @brief Read current value of the DAC_DATnL_DATA0 field. */ -#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U) - -/*! @brief Format value for bitfield DAC_DATnL_DATA0. */ -#define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0) - -/*! @brief Set the DATA0 field to a new value. */ -#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DAC_DATnH - DAC Data High Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_DATnH - DAC Data High Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_dac_datnh -{ - uint8_t U; - struct _hw_dac_datnh_bitfields - { - uint8_t DATA1 : 4; /*!< [3:0] */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_dac_datnh_t; - -/*! - * @name Constants and macros for entire DAC_DATnH register - */ -/*@{*/ -#define HW_DAC_DATnH_COUNT (16U) - -#define HW_DAC_DATnH_ADDR(x, n) ((x) + 0x1U + (0x2U * (n))) - -#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n)) -#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U) -#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v)) -#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v))) -#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v))) -#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_DATnH bitfields - */ - -/*! - * @name Register DAC_DATnH, field DATA1[3:0] (RW) - * - * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage - * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the - * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. - */ -/*@{*/ -#define BP_DAC_DATnH_DATA1 (0U) /*!< Bit position for DAC_DATnH_DATA1. */ -#define BM_DAC_DATnH_DATA1 (0x0FU) /*!< Bit mask for DAC_DATnH_DATA1. */ -#define BS_DAC_DATnH_DATA1 (4U) /*!< Bit field size in bits for DAC_DATnH_DATA1. */ - -/*! @brief Read current value of the DAC_DATnH_DATA1 field. */ -#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1) - -/*! @brief Format value for bitfield DAC_DATnH_DATA1. */ -#define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1) - -/*! @brief Set the DATA1 field to a new value. */ -#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v))) -/*@}*/ - -/******************************************************************************* - * HW_DAC_SR - DAC Status Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_SR - DAC Status Register (RW) - * - * Reset value: 0x02U - * - * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA - * request is done. Writing 0 to a field clears it whereas writing 1 has no - * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed. - * The flags are set only when the data buffer status is changed. - */ -typedef union _hw_dac_sr -{ - uint8_t U; - struct _hw_dac_sr_bitfields - { - uint8_t DACBFRPBF : 1; /*!< [0] DAC Buffer Read Pointer Bottom - * Position Flag */ - uint8_t DACBFRPTF : 1; /*!< [1] DAC Buffer Read Pointer Top Position - * Flag */ - uint8_t DACBFWMF : 1; /*!< [2] DAC Buffer Watermark Flag */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_dac_sr_t; - -/*! - * @name Constants and macros for entire DAC_SR register - */ -/*@{*/ -#define HW_DAC_SR_ADDR(x) ((x) + 0x20U) - -#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x)) -#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U) -#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v)) -#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v))) -#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v))) -#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_SR bitfields - */ - -/*! - * @name Register DAC_SR, field DACBFRPBF[0] (RW) - * - * In FIFO mode, it is FIFO FULL status bit. It means FIFO read pointer equals - * Write Pointer because of Write Pointer increase. If this bit is set, any write - * to FIFO from either DMA or CPU is ignored by DAC. It is cleared if there is - * any DAC trigger making the DAC read pointer increase. Write to this bit is - * ignored in FIFO mode. - * - * Values: - * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP]. - * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP]. - */ -/*@{*/ -#define BP_DAC_SR_DACBFRPBF (0U) /*!< Bit position for DAC_SR_DACBFRPBF. */ -#define BM_DAC_SR_DACBFRPBF (0x01U) /*!< Bit mask for DAC_SR_DACBFRPBF. */ -#define BS_DAC_SR_DACBFRPBF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */ - -/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */ -#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF)) - -/*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */ -#define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF) - -/*! @brief Set the DACBFRPBF field to a new value. */ -#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v)) -/*@}*/ - -/*! - * @name Register DAC_SR, field DACBFRPTF[1] (RW) - * - * In FIFO mode, it is FIFO nearly empty flag. It is set when only one data - * remains in FIFO. Any DAC trigger does not increase the Read Pointer if this bit is - * set to avoid any possible glitch or abrupt change at DAC output. It is - * cleared automatically if FIFO is not empty. - * - * Values: - * - 0 - The DAC buffer read pointer is not zero. - * - 1 - The DAC buffer read pointer is zero. - */ -/*@{*/ -#define BP_DAC_SR_DACBFRPTF (1U) /*!< Bit position for DAC_SR_DACBFRPTF. */ -#define BM_DAC_SR_DACBFRPTF (0x02U) /*!< Bit mask for DAC_SR_DACBFRPTF. */ -#define BS_DAC_SR_DACBFRPTF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */ - -/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */ -#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF)) - -/*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */ -#define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF) - -/*! @brief Set the DACBFRPTF field to a new value. */ -#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v)) -/*@}*/ - -/*! - * @name Register DAC_SR, field DACBFWMF[2] (RW) - * - * This bit is set if the remaining FIFO data is less than the watermark - * setting. It is cleared automatically by writing data into FIFO by DMA or CPU. Write - * to this bit is ignored in FIFO mode. - * - * Values: - * - 0 - The DAC buffer read pointer has not reached the watermark level. - * - 1 - The DAC buffer read pointer has reached the watermark level. - */ -/*@{*/ -#define BP_DAC_SR_DACBFWMF (2U) /*!< Bit position for DAC_SR_DACBFWMF. */ -#define BM_DAC_SR_DACBFWMF (0x04U) /*!< Bit mask for DAC_SR_DACBFWMF. */ -#define BS_DAC_SR_DACBFWMF (1U) /*!< Bit field size in bits for DAC_SR_DACBFWMF. */ - -/*! @brief Read current value of the DAC_SR_DACBFWMF field. */ -#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF)) - -/*! @brief Format value for bitfield DAC_SR_DACBFWMF. */ -#define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF) - -/*! @brief Set the DACBFWMF field to a new value. */ -#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DAC_C0 - DAC Control Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_C0 - DAC Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_dac_c0 -{ - uint8_t U; - struct _hw_dac_c0_bitfields - { - uint8_t DACBBIEN : 1; /*!< [0] DAC Buffer Read Pointer Bottom Flag - * Interrupt Enable */ - uint8_t DACBTIEN : 1; /*!< [1] DAC Buffer Read Pointer Top Flag - * Interrupt Enable */ - uint8_t DACBWIEN : 1; /*!< [2] DAC Buffer Watermark Interrupt Enable - * */ - uint8_t LPEN : 1; /*!< [3] DAC Low Power Control */ - uint8_t DACSWTRG : 1; /*!< [4] DAC Software Trigger */ - uint8_t DACTRGSEL : 1; /*!< [5] DAC Trigger Select */ - uint8_t DACRFS : 1; /*!< [6] DAC Reference Select */ - uint8_t DACEN : 1; /*!< [7] DAC Enable */ - } B; -} hw_dac_c0_t; - -/*! - * @name Constants and macros for entire DAC_C0 register - */ -/*@{*/ -#define HW_DAC_C0_ADDR(x) ((x) + 0x21U) - -#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x)) -#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U) -#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v)) -#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v))) -#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v))) -#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_C0 bitfields - */ - -/*! - * @name Register DAC_C0, field DACBBIEN[0] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled. - * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACBBIEN (0U) /*!< Bit position for DAC_C0_DACBBIEN. */ -#define BM_DAC_C0_DACBBIEN (0x01U) /*!< Bit mask for DAC_C0_DACBBIEN. */ -#define BS_DAC_C0_DACBBIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBBIEN. */ - -/*! @brief Read current value of the DAC_C0_DACBBIEN field. */ -#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN)) - -/*! @brief Format value for bitfield DAC_C0_DACBBIEN. */ -#define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN) - -/*! @brief Set the DACBBIEN field to a new value. */ -#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACBTIEN[1] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer top flag interrupt is disabled. - * - 1 - The DAC buffer read pointer top flag interrupt is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACBTIEN (1U) /*!< Bit position for DAC_C0_DACBTIEN. */ -#define BM_DAC_C0_DACBTIEN (0x02U) /*!< Bit mask for DAC_C0_DACBTIEN. */ -#define BS_DAC_C0_DACBTIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBTIEN. */ - -/*! @brief Read current value of the DAC_C0_DACBTIEN field. */ -#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN)) - -/*! @brief Format value for bitfield DAC_C0_DACBTIEN. */ -#define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN) - -/*! @brief Set the DACBTIEN field to a new value. */ -#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACBWIEN[2] (RW) - * - * Values: - * - 0 - The DAC buffer watermark interrupt is disabled. - * - 1 - The DAC buffer watermark interrupt is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACBWIEN (2U) /*!< Bit position for DAC_C0_DACBWIEN. */ -#define BM_DAC_C0_DACBWIEN (0x04U) /*!< Bit mask for DAC_C0_DACBWIEN. */ -#define BS_DAC_C0_DACBWIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBWIEN. */ - -/*! @brief Read current value of the DAC_C0_DACBWIEN field. */ -#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN)) - -/*! @brief Format value for bitfield DAC_C0_DACBWIEN. */ -#define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN) - -/*! @brief Set the DACBWIEN field to a new value. */ -#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field LPEN[3] (RW) - * - * See the 12-bit DAC electrical characteristics of the device data sheet for - * details on the impact of the modes below. - * - * Values: - * - 0 - High-Power mode - * - 1 - Low-Power mode - */ -/*@{*/ -#define BP_DAC_C0_LPEN (3U) /*!< Bit position for DAC_C0_LPEN. */ -#define BM_DAC_C0_LPEN (0x08U) /*!< Bit mask for DAC_C0_LPEN. */ -#define BS_DAC_C0_LPEN (1U) /*!< Bit field size in bits for DAC_C0_LPEN. */ - -/*! @brief Read current value of the DAC_C0_LPEN field. */ -#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN)) - -/*! @brief Format value for bitfield DAC_C0_LPEN. */ -#define BF_DAC_C0_LPEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN) - -/*! @brief Set the LPEN field to a new value. */ -#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACSWTRG[4] (WORZ) - * - * Active high. This is a write-only field, which always reads 0. If DAC - * software trigger is selected and buffer is enabled, writing 1 to this field will - * advance the buffer read pointer once. - * - * Values: - * - 0 - The DAC soft trigger is not valid. - * - 1 - The DAC soft trigger is valid. - */ -/*@{*/ -#define BP_DAC_C0_DACSWTRG (4U) /*!< Bit position for DAC_C0_DACSWTRG. */ -#define BM_DAC_C0_DACSWTRG (0x10U) /*!< Bit mask for DAC_C0_DACSWTRG. */ -#define BS_DAC_C0_DACSWTRG (1U) /*!< Bit field size in bits for DAC_C0_DACSWTRG. */ - -/*! @brief Format value for bitfield DAC_C0_DACSWTRG. */ -#define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG) - -/*! @brief Set the DACSWTRG field to a new value. */ -#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACTRGSEL[5] (RW) - * - * Values: - * - 0 - The DAC hardware trigger is selected. - * - 1 - The DAC software trigger is selected. - */ -/*@{*/ -#define BP_DAC_C0_DACTRGSEL (5U) /*!< Bit position for DAC_C0_DACTRGSEL. */ -#define BM_DAC_C0_DACTRGSEL (0x20U) /*!< Bit mask for DAC_C0_DACTRGSEL. */ -#define BS_DAC_C0_DACTRGSEL (1U) /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */ - -/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */ -#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL)) - -/*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */ -#define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL) - -/*! @brief Set the DACTRGSEL field to a new value. */ -#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACRFS[6] (RW) - * - * Values: - * - 0 - The DAC selects DACREF_1 as the reference voltage. - * - 1 - The DAC selects DACREF_2 as the reference voltage. - */ -/*@{*/ -#define BP_DAC_C0_DACRFS (6U) /*!< Bit position for DAC_C0_DACRFS. */ -#define BM_DAC_C0_DACRFS (0x40U) /*!< Bit mask for DAC_C0_DACRFS. */ -#define BS_DAC_C0_DACRFS (1U) /*!< Bit field size in bits for DAC_C0_DACRFS. */ - -/*! @brief Read current value of the DAC_C0_DACRFS field. */ -#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS)) - -/*! @brief Format value for bitfield DAC_C0_DACRFS. */ -#define BF_DAC_C0_DACRFS(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS) - -/*! @brief Set the DACRFS field to a new value. */ -#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACEN[7] (RW) - * - * Starts the Programmable Reference Generator operation. - * - * Values: - * - 0 - The DAC system is disabled. - * - 1 - The DAC system is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACEN (7U) /*!< Bit position for DAC_C0_DACEN. */ -#define BM_DAC_C0_DACEN (0x80U) /*!< Bit mask for DAC_C0_DACEN. */ -#define BS_DAC_C0_DACEN (1U) /*!< Bit field size in bits for DAC_C0_DACEN. */ - -/*! @brief Read current value of the DAC_C0_DACEN field. */ -#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN)) - -/*! @brief Format value for bitfield DAC_C0_DACEN. */ -#define BF_DAC_C0_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN) - -/*! @brief Set the DACEN field to a new value. */ -#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DAC_C1 - DAC Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_DAC_C1 - DAC Control Register 1 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_dac_c1 -{ - uint8_t U; - struct _hw_dac_c1_bitfields - { - uint8_t DACBFEN : 1; /*!< [0] DAC Buffer Enable */ - uint8_t DACBFMD : 2; /*!< [2:1] DAC Buffer Work Mode Select */ - uint8_t DACBFWM : 2; /*!< [4:3] DAC Buffer Watermark Select */ - uint8_t RESERVED0 : 2; /*!< [6:5] */ - uint8_t DMAEN : 1; /*!< [7] DMA Enable Select */ - } B; -} hw_dac_c1_t; - -/*! - * @name Constants and macros for entire DAC_C1 register - */ -/*@{*/ -#define HW_DAC_C1_ADDR(x) ((x) + 0x22U) - -#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x)) -#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U) -#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v)) -#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v))) -#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v))) -#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_C1 bitfields - */ - -/*! - * @name Register DAC_C1, field DACBFEN[0] (RW) - * - * Values: - * - 0 - Buffer read pointer is disabled. The converted data is always the first - * word of the buffer. - * - 1 - Buffer read pointer is enabled. The converted data is the word that the - * read pointer points to. It means converted data can be from any word of - * the buffer. - */ -/*@{*/ -#define BP_DAC_C1_DACBFEN (0U) /*!< Bit position for DAC_C1_DACBFEN. */ -#define BM_DAC_C1_DACBFEN (0x01U) /*!< Bit mask for DAC_C1_DACBFEN. */ -#define BS_DAC_C1_DACBFEN (1U) /*!< Bit field size in bits for DAC_C1_DACBFEN. */ - -/*! @brief Read current value of the DAC_C1_DACBFEN field. */ -#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN)) - -/*! @brief Format value for bitfield DAC_C1_DACBFEN. */ -#define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN) - -/*! @brief Set the DACBFEN field to a new value. */ -#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C1, field DACBFMD[2:1] (RW) - * - * Values: - * - 00 - Normal mode - * - 01 - Swing mode - * - 10 - One-Time Scan mode - * - 11 - FIFO mode - */ -/*@{*/ -#define BP_DAC_C1_DACBFMD (1U) /*!< Bit position for DAC_C1_DACBFMD. */ -#define BM_DAC_C1_DACBFMD (0x06U) /*!< Bit mask for DAC_C1_DACBFMD. */ -#define BS_DAC_C1_DACBFMD (2U) /*!< Bit field size in bits for DAC_C1_DACBFMD. */ - -/*! @brief Read current value of the DAC_C1_DACBFMD field. */ -#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD) - -/*! @brief Format value for bitfield DAC_C1_DACBFMD. */ -#define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD) - -/*! @brief Set the DACBFMD field to a new value. */ -#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v))) -/*@}*/ - -/*! - * @name Register DAC_C1, field DACBFWM[4:3] (RW) - * - * In normal mode it controls when SR[DACBFWMF] is set. When the DAC buffer read - * pointer reaches the word defined by this field, which is 1-4 words away from - * the upper limit (DACBUP), SR[DACBFWMF] will be set. This allows user - * configuration of the watermark interrupt. In FIFO mode, it is FIFO watermark select - * field. - * - * Values: - * - 00 - In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining - * in FIFO will set watermark status bit. - * - 01 - In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data - * remaining in FIFO will set watermark status bit. - * - 10 - In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data - * remaining in FIFO will set watermark status bit. - * - 11 - In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data - * remaining in FIFO will set watermark status bit. - */ -/*@{*/ -#define BP_DAC_C1_DACBFWM (3U) /*!< Bit position for DAC_C1_DACBFWM. */ -#define BM_DAC_C1_DACBFWM (0x18U) /*!< Bit mask for DAC_C1_DACBFWM. */ -#define BS_DAC_C1_DACBFWM (2U) /*!< Bit field size in bits for DAC_C1_DACBFWM. */ - -/*! @brief Read current value of the DAC_C1_DACBFWM field. */ -#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM) - -/*! @brief Format value for bitfield DAC_C1_DACBFWM. */ -#define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM) - -/*! @brief Set the DACBFWM field to a new value. */ -#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v))) -/*@}*/ - -/*! - * @name Register DAC_C1, field DMAEN[7] (RW) - * - * Values: - * - 0 - DMA is disabled. - * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated - * by original interrupts. The interrupts will not be presented on this - * module at the same time. - */ -/*@{*/ -#define BP_DAC_C1_DMAEN (7U) /*!< Bit position for DAC_C1_DMAEN. */ -#define BM_DAC_C1_DMAEN (0x80U) /*!< Bit mask for DAC_C1_DMAEN. */ -#define BS_DAC_C1_DMAEN (1U) /*!< Bit field size in bits for DAC_C1_DMAEN. */ - -/*! @brief Read current value of the DAC_C1_DMAEN field. */ -#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN)) - -/*! @brief Format value for bitfield DAC_C1_DMAEN. */ -#define BF_DAC_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DAC_C2 - DAC Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_DAC_C2 - DAC Control Register 2 (RW) - * - * Reset value: 0x0FU - */ -typedef union _hw_dac_c2 -{ - uint8_t U; - struct _hw_dac_c2_bitfields - { - uint8_t DACBFUP : 4; /*!< [3:0] DAC Buffer Upper Limit */ - uint8_t DACBFRP : 4; /*!< [7:4] DAC Buffer Read Pointer */ - } B; -} hw_dac_c2_t; - -/*! - * @name Constants and macros for entire DAC_C2 register - */ -/*@{*/ -#define HW_DAC_C2_ADDR(x) ((x) + 0x23U) - -#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x)) -#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U) -#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v)) -#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v))) -#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v))) -#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_C2 bitfields - */ - -/*! - * @name Register DAC_C2, field DACBFUP[3:0] (RW) - * - * In normal mode it selects the upper limit of the DAC buffer. The buffer read - * pointer cannot exceed it. In FIFO mode it is the FIFO write pointer. User - * cannot set Buffer Up limit in FIFO mode. In Normal mode its reset value is MAX. - * When IP is configured to FIFO mode, this register becomes Write_Pointer, and its - * value is initially set to equal READ_POINTER automatically, and the FIFO - * status is empty. It is writable and user can configure it to the same address to - * reset FIFO as empty. - */ -/*@{*/ -#define BP_DAC_C2_DACBFUP (0U) /*!< Bit position for DAC_C2_DACBFUP. */ -#define BM_DAC_C2_DACBFUP (0x0FU) /*!< Bit mask for DAC_C2_DACBFUP. */ -#define BS_DAC_C2_DACBFUP (4U) /*!< Bit field size in bits for DAC_C2_DACBFUP. */ - -/*! @brief Read current value of the DAC_C2_DACBFUP field. */ -#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP) - -/*! @brief Format value for bitfield DAC_C2_DACBFUP. */ -#define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP) - -/*! @brief Set the DACBFUP field to a new value. */ -#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v))) -/*@}*/ - -/*! - * @name Register DAC_C2, field DACBFRP[7:4] (RW) - * - * In normal mode it keeps the current value of the buffer read pointer. FIFO - * mode, it is the FIFO read pointer. It is writable in FIFO mode. User can - * configure it to same address to reset FIFO as empty. - */ -/*@{*/ -#define BP_DAC_C2_DACBFRP (4U) /*!< Bit position for DAC_C2_DACBFRP. */ -#define BM_DAC_C2_DACBFRP (0xF0U) /*!< Bit mask for DAC_C2_DACBFRP. */ -#define BS_DAC_C2_DACBFRP (4U) /*!< Bit field size in bits for DAC_C2_DACBFRP. */ - -/*! @brief Read current value of the DAC_C2_DACBFRP field. */ -#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP) - -/*! @brief Format value for bitfield DAC_C2_DACBFRP. */ -#define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP) - -/*! @brief Set the DACBFRP field to a new value. */ -#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v))) -/*@}*/ - -/******************************************************************************* - * hw_dac_t - module struct - ******************************************************************************/ -/*! - * @brief All DAC module registers. - */ -#pragma pack(1) -typedef struct _hw_dac -{ - struct { - __IO hw_dac_datnl_t DATnL; /*!< [0x0] DAC Data Low Register */ - __IO hw_dac_datnh_t DATnH; /*!< [0x1] DAC Data High Register */ - } DAT[16]; - __IO hw_dac_sr_t SR; /*!< [0x20] DAC Status Register */ - __IO hw_dac_c0_t C0; /*!< [0x21] DAC Control Register */ - __IO hw_dac_c1_t C1; /*!< [0x22] DAC Control Register 1 */ - __IO hw_dac_c2_t C2; /*!< [0x23] DAC Control Register 2 */ -} hw_dac_t; -#pragma pack() - -/*! @brief Macro to access all DAC registers. */ -/*! @param x DAC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_DAC(DAC0_BASE). */ -#define HW_DAC(x) (*(hw_dac_t *)(x)) - -#endif /* __HW_DAC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h deleted file mode 100644 index 689ef603298..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h +++ /dev/null @@ -1,5785 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_DMA_REGISTERS_H__ -#define __HW_DMA_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 DMA - * - * Enhanced direct memory access controller - * - * Registers defined in this header file: - * - HW_DMA_CR - Control Register - * - HW_DMA_ES - Error Status Register - * - HW_DMA_ERQ - Enable Request Register - * - HW_DMA_EEI - Enable Error Interrupt Register - * - HW_DMA_CEEI - Clear Enable Error Interrupt Register - * - HW_DMA_SEEI - Set Enable Error Interrupt Register - * - HW_DMA_CERQ - Clear Enable Request Register - * - HW_DMA_SERQ - Set Enable Request Register - * - HW_DMA_CDNE - Clear DONE Status Bit Register - * - HW_DMA_SSRT - Set START Bit Register - * - HW_DMA_CERR - Clear Error Register - * - HW_DMA_CINT - Clear Interrupt Request Register - * - HW_DMA_INT - Interrupt Request Register - * - HW_DMA_ERR - Error Register - * - HW_DMA_HRS - Hardware Request Status Register - * - HW_DMA_EARS - Enable Asynchronous Request in Stop Register - * - HW_DMA_DCHPRIn - Channel n Priority Register - * - HW_DMA_TCDn_SADDR - TCD Source Address - * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset - * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes - * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) - * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) - * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) - * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment - * - HW_DMA_TCDn_DADDR - TCD Destination Address - * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset - * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) - * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) - * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address - * - HW_DMA_TCDn_CSR - TCD Control and Status - * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) - * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) - * - * - hw_dma_t - Struct containing all module registers. - */ - -#define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */ - -/******************************************************************************* - * HW_DMA_CR - Control Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CR - Control Register (RW) - * - * Reset value: 0x00000000U - * - * The CR defines the basic operating configuration of the DMA. Arbitration can - * be configured to use either a fixed-priority or a round-robin scheme. For - * fixed-priority arbitration, the highest priority channel requesting service is - * selected to execute. The channel priority registers assign the priorities; see - * the DCHPRIn registers. For round-robin arbitration, the channel priorities are - * ignored and channels are cycled through (from high to low channel number) - * without regard to priority. For proper operation, writes to the CR register must be - * performed only when the DMA channels are inactive; that is, when - * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to - * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon - * minor loop completion. When minor loop offsets are enabled, the minor loop - * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final - * destination address (TCDn_DADDR), or to both prior to the addresses being - * written back into the TCD. If the major loop is complete, the minor loop offset is - * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are - * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop - * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 - * is used to specify multiple fields: a source enable bit (SMLOE) to specify the - * minor loop offset should be applied to the source address (TCDn_SADDR) upon - * minor loop completion, a destination enable bit (DMLOE) to specify the minor - * loop offset should be applied to the destination address (TCDn_DADDR) upon minor - * loop completion, and the sign extended minor loop offset value (MLOFF). The - * same offset value (MLOFF) is used for both source and destination minor loop - * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the - * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled - * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When - * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are - * assigned to the NBYTES field. - */ -typedef union _hw_dma_cr -{ - uint32_t U; - struct _hw_dma_cr_bitfields - { - uint32_t RESERVED0 : 1; /*!< [0] Reserved. */ - uint32_t EDBG : 1; /*!< [1] Enable Debug */ - uint32_t ERCA : 1; /*!< [2] Enable Round Robin Channel Arbitration */ - uint32_t RESERVED1 : 1; /*!< [3] Reserved. */ - uint32_t HOE : 1; /*!< [4] Halt On Error */ - uint32_t HALT : 1; /*!< [5] Halt DMA Operations */ - uint32_t CLM : 1; /*!< [6] Continuous Link Mode */ - uint32_t EMLM : 1; /*!< [7] Enable Minor Loop Mapping */ - uint32_t RESERVED2 : 8; /*!< [15:8] */ - uint32_t ECX : 1; /*!< [16] Error Cancel Transfer */ - uint32_t CX : 1; /*!< [17] Cancel Transfer */ - uint32_t RESERVED3 : 14; /*!< [31:18] */ - } B; -} hw_dma_cr_t; - -/*! - * @name Constants and macros for entire DMA_CR register - */ -/*@{*/ -#define HW_DMA_CR_ADDR(x) ((x) + 0x0U) - -#define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x)) -#define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U) -#define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v)) -#define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v))) -#define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v))) -#define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_CR bitfields - */ - -/*! - * @name Register DMA_CR, field EDBG[1] (RW) - * - * Values: - * - 0 - When in debug mode, the DMA continues to operate. - * - 1 - When in debug mode, the DMA stalls the start of a new channel. - * Executing channels are allowed to complete. Channel execution resumes when the - * system exits debug mode or the EDBG bit is cleared. - */ -/*@{*/ -#define BP_DMA_CR_EDBG (1U) /*!< Bit position for DMA_CR_EDBG. */ -#define BM_DMA_CR_EDBG (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */ -#define BS_DMA_CR_EDBG (1U) /*!< Bit field size in bits for DMA_CR_EDBG. */ - -/*! @brief Read current value of the DMA_CR_EDBG field. */ -#define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG)) - -/*! @brief Format value for bitfield DMA_CR_EDBG. */ -#define BF_DMA_CR_EDBG(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG) - -/*! @brief Set the EDBG field to a new value. */ -#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field ERCA[2] (RW) - * - * Values: - * - 0 - Fixed priority arbitration is used for channel selection . - * - 1 - Round robin arbitration is used for channel selection . - */ -/*@{*/ -#define BP_DMA_CR_ERCA (2U) /*!< Bit position for DMA_CR_ERCA. */ -#define BM_DMA_CR_ERCA (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */ -#define BS_DMA_CR_ERCA (1U) /*!< Bit field size in bits for DMA_CR_ERCA. */ - -/*! @brief Read current value of the DMA_CR_ERCA field. */ -#define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA)) - -/*! @brief Format value for bitfield DMA_CR_ERCA. */ -#define BF_DMA_CR_ERCA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA) - -/*! @brief Set the ERCA field to a new value. */ -#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field HOE[4] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Any error causes the HALT bit to set. Subsequently, all service - * requests are ignored until the HALT bit is cleared. - */ -/*@{*/ -#define BP_DMA_CR_HOE (4U) /*!< Bit position for DMA_CR_HOE. */ -#define BM_DMA_CR_HOE (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */ -#define BS_DMA_CR_HOE (1U) /*!< Bit field size in bits for DMA_CR_HOE. */ - -/*! @brief Read current value of the DMA_CR_HOE field. */ -#define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE)) - -/*! @brief Format value for bitfield DMA_CR_HOE. */ -#define BF_DMA_CR_HOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE) - -/*! @brief Set the HOE field to a new value. */ -#define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field HALT[5] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Stall the start of any new channels. Executing channels are allowed to - * complete. Channel execution resumes when this bit is cleared. - */ -/*@{*/ -#define BP_DMA_CR_HALT (5U) /*!< Bit position for DMA_CR_HALT. */ -#define BM_DMA_CR_HALT (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */ -#define BS_DMA_CR_HALT (1U) /*!< Bit field size in bits for DMA_CR_HALT. */ - -/*! @brief Read current value of the DMA_CR_HALT field. */ -#define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT)) - -/*! @brief Format value for bitfield DMA_CR_HALT. */ -#define BF_DMA_CR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT) - -/*! @brief Set the HALT field to a new value. */ -#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field CLM[6] (RW) - * - * Values: - * - 0 - A minor loop channel link made to itself goes through channel - * arbitration before being activated again. - * - 1 - A minor loop channel link made to itself does not go through channel - * arbitration before being activated again. Upon minor loop completion, the - * channel activates again if that channel has a minor loop channel link - * enabled and the link channel is itself. This effectively applies the minor loop - * offsets and restarts the next minor loop. - */ -/*@{*/ -#define BP_DMA_CR_CLM (6U) /*!< Bit position for DMA_CR_CLM. */ -#define BM_DMA_CR_CLM (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */ -#define BS_DMA_CR_CLM (1U) /*!< Bit field size in bits for DMA_CR_CLM. */ - -/*! @brief Read current value of the DMA_CR_CLM field. */ -#define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM)) - -/*! @brief Format value for bitfield DMA_CR_CLM. */ -#define BF_DMA_CR_CLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM) - -/*! @brief Set the CLM field to a new value. */ -#define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field EMLM[7] (RW) - * - * Values: - * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. - * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields, - * an offset field, and the NBYTES field. The individual enable fields allow - * the minor loop offset to be applied to the source address, the destination - * address, or both. The NBYTES field is reduced when either offset is - * enabled. - */ -/*@{*/ -#define BP_DMA_CR_EMLM (7U) /*!< Bit position for DMA_CR_EMLM. */ -#define BM_DMA_CR_EMLM (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */ -#define BS_DMA_CR_EMLM (1U) /*!< Bit field size in bits for DMA_CR_EMLM. */ - -/*! @brief Read current value of the DMA_CR_EMLM field. */ -#define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM)) - -/*! @brief Format value for bitfield DMA_CR_EMLM. */ -#define BF_DMA_CR_EMLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM) - -/*! @brief Set the EMLM field to a new value. */ -#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field ECX[16] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit. - * Stop the executing channel and force the minor loop to finish. The cancel - * takes effect after the last write of the current read/write sequence. The - * ECX bit clears itself after the cancel is honored. In addition to - * cancelling the transfer, ECX treats the cancel as an error condition, thus updating - * the Error Status register (DMAx_ES) and generating an optional error - * interrupt. - */ -/*@{*/ -#define BP_DMA_CR_ECX (16U) /*!< Bit position for DMA_CR_ECX. */ -#define BM_DMA_CR_ECX (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */ -#define BS_DMA_CR_ECX (1U) /*!< Bit field size in bits for DMA_CR_ECX. */ - -/*! @brief Read current value of the DMA_CR_ECX field. */ -#define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX)) - -/*! @brief Format value for bitfield DMA_CR_ECX. */ -#define BF_DMA_CR_ECX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX) - -/*! @brief Set the ECX field to a new value. */ -#define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field CX[17] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Cancel the remaining data transfer. Stop the executing channel and - * force the minor loop to finish. The cancel takes effect after the last write - * of the current read/write sequence. The CX bit clears itself after the - * cancel has been honored. This cancel retires the channel normally as if the - * minor loop was completed. - */ -/*@{*/ -#define BP_DMA_CR_CX (17U) /*!< Bit position for DMA_CR_CX. */ -#define BM_DMA_CR_CX (0x00020000U) /*!< Bit mask for DMA_CR_CX. */ -#define BS_DMA_CR_CX (1U) /*!< Bit field size in bits for DMA_CR_CX. */ - -/*! @brief Read current value of the DMA_CR_CX field. */ -#define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX)) - -/*! @brief Format value for bitfield DMA_CR_CX. */ -#define BF_DMA_CR_CX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX) - -/*! @brief Set the CX field to a new value. */ -#define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_ES - Error Status Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_ES - Error Status Register (RO) - * - * Reset value: 0x00000000U - * - * The ES provides information concerning the last recorded channel error. - * Channel errors can be caused by: A configuration error, that is: An illegal setting - * in the transfer-control descriptor, or An illegal priority register setting - * in fixed-arbitration An error termination to a bus master read or write cycle - * See the Error Reporting and Handling section for more details. - */ -typedef union _hw_dma_es -{ - uint32_t U; - struct _hw_dma_es_bitfields - { - uint32_t DBE : 1; /*!< [0] Destination Bus Error */ - uint32_t SBE : 1; /*!< [1] Source Bus Error */ - uint32_t SGE : 1; /*!< [2] Scatter/Gather Configuration Error */ - uint32_t NCE : 1; /*!< [3] NBYTES/CITER Configuration Error */ - uint32_t DOE : 1; /*!< [4] Destination Offset Error */ - uint32_t DAE : 1; /*!< [5] Destination Address Error */ - uint32_t SOE : 1; /*!< [6] Source Offset Error */ - uint32_t SAE : 1; /*!< [7] Source Address Error */ - uint32_t ERRCHN : 4; /*!< [11:8] Error Channel Number or Canceled - * Channel Number */ - uint32_t RESERVED0 : 2; /*!< [13:12] */ - uint32_t CPE : 1; /*!< [14] Channel Priority Error */ - uint32_t RESERVED1 : 1; /*!< [15] */ - uint32_t ECX : 1; /*!< [16] Transfer Canceled */ - uint32_t RESERVED2 : 14; /*!< [30:17] */ - uint32_t VLD : 1; /*!< [31] */ - } B; -} hw_dma_es_t; - -/*! - * @name Constants and macros for entire DMA_ES register - */ -/*@{*/ -#define HW_DMA_ES_ADDR(x) ((x) + 0x4U) - -#define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x)) -#define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U) -/*@}*/ - -/* - * Constants & macros for individual DMA_ES bitfields - */ - -/*! - * @name Register DMA_ES, field DBE[0] (RO) - * - * Values: - * - 0 - No destination bus error - * - 1 - The last recorded error was a bus error on a destination write - */ -/*@{*/ -#define BP_DMA_ES_DBE (0U) /*!< Bit position for DMA_ES_DBE. */ -#define BM_DMA_ES_DBE (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */ -#define BS_DMA_ES_DBE (1U) /*!< Bit field size in bits for DMA_ES_DBE. */ - -/*! @brief Read current value of the DMA_ES_DBE field. */ -#define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SBE[1] (RO) - * - * Values: - * - 0 - No source bus error - * - 1 - The last recorded error was a bus error on a source read - */ -/*@{*/ -#define BP_DMA_ES_SBE (1U) /*!< Bit position for DMA_ES_SBE. */ -#define BM_DMA_ES_SBE (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */ -#define BS_DMA_ES_SBE (1U) /*!< Bit field size in bits for DMA_ES_SBE. */ - -/*! @brief Read current value of the DMA_ES_SBE field. */ -#define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SGE[2] (RO) - * - * Values: - * - 0 - No scatter/gather configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather - * operation after major loop completion if TCDn_CSR[ESG] is enabled. - * TCDn_DLASTSGA is not on a 32 byte boundary. - */ -/*@{*/ -#define BP_DMA_ES_SGE (2U) /*!< Bit position for DMA_ES_SGE. */ -#define BM_DMA_ES_SGE (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */ -#define BS_DMA_ES_SGE (1U) /*!< Bit field size in bits for DMA_ES_SGE. */ - -/*! @brief Read current value of the DMA_ES_SGE field. */ -#define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field NCE[3] (RO) - * - * Values: - * - 0 - No NBYTES/CITER configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of - * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or - * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] - */ -/*@{*/ -#define BP_DMA_ES_NCE (3U) /*!< Bit position for DMA_ES_NCE. */ -#define BM_DMA_ES_NCE (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */ -#define BS_DMA_ES_NCE (1U) /*!< Bit field size in bits for DMA_ES_NCE. */ - -/*! @brief Read current value of the DMA_ES_NCE field. */ -#define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field DOE[4] (RO) - * - * Values: - * - 0 - No destination offset configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_DOE (4U) /*!< Bit position for DMA_ES_DOE. */ -#define BM_DMA_ES_DOE (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */ -#define BS_DMA_ES_DOE (1U) /*!< Bit field size in bits for DMA_ES_DOE. */ - -/*! @brief Read current value of the DMA_ES_DOE field. */ -#define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field DAE[5] (RO) - * - * Values: - * - 0 - No destination address configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_DAE (5U) /*!< Bit position for DMA_ES_DAE. */ -#define BM_DMA_ES_DAE (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */ -#define BS_DMA_ES_DAE (1U) /*!< Bit field size in bits for DMA_ES_DAE. */ - -/*! @brief Read current value of the DMA_ES_DAE field. */ -#define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SOE[6] (RO) - * - * Values: - * - 0 - No source offset configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_SOE (6U) /*!< Bit position for DMA_ES_SOE. */ -#define BM_DMA_ES_SOE (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */ -#define BS_DMA_ES_SOE (1U) /*!< Bit field size in bits for DMA_ES_SOE. */ - -/*! @brief Read current value of the DMA_ES_SOE field. */ -#define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SAE[7] (RO) - * - * Values: - * - 0 - No source address configuration error. - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_SAE (7U) /*!< Bit position for DMA_ES_SAE. */ -#define BM_DMA_ES_SAE (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */ -#define BS_DMA_ES_SAE (1U) /*!< Bit field size in bits for DMA_ES_SAE. */ - -/*! @brief Read current value of the DMA_ES_SAE field. */ -#define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field ERRCHN[11:8] (RO) - * - * The channel number of the last recorded error (excluding CPE errors) or last - * recorded error canceled transfer. - */ -/*@{*/ -#define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */ -#define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */ -#define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */ - -/*! @brief Read current value of the DMA_ES_ERRCHN field. */ -#define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN) -/*@}*/ - -/*! - * @name Register DMA_ES, field CPE[14] (RO) - * - * Values: - * - 0 - No channel priority error - * - 1 - The last recorded error was a configuration error in the channel - * priorities . Channel priorities are not unique. - */ -/*@{*/ -#define BP_DMA_ES_CPE (14U) /*!< Bit position for DMA_ES_CPE. */ -#define BM_DMA_ES_CPE (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */ -#define BS_DMA_ES_CPE (1U) /*!< Bit field size in bits for DMA_ES_CPE. */ - -/*! @brief Read current value of the DMA_ES_CPE field. */ -#define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field ECX[16] (RO) - * - * Values: - * - 0 - No canceled transfers - * - 1 - The last recorded entry was a canceled transfer by the error cancel - * transfer input - */ -/*@{*/ -#define BP_DMA_ES_ECX (16U) /*!< Bit position for DMA_ES_ECX. */ -#define BM_DMA_ES_ECX (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */ -#define BS_DMA_ES_ECX (1U) /*!< Bit field size in bits for DMA_ES_ECX. */ - -/*! @brief Read current value of the DMA_ES_ECX field. */ -#define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX)) -/*@}*/ - -/*! - * @name Register DMA_ES, field VLD[31] (RO) - * - * Logical OR of all ERR status bits - * - * Values: - * - 0 - No ERR bits are set - * - 1 - At least one ERR bit is set indicating a valid error exists that has - * not been cleared - */ -/*@{*/ -#define BP_DMA_ES_VLD (31U) /*!< Bit position for DMA_ES_VLD. */ -#define BM_DMA_ES_VLD (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */ -#define BS_DMA_ES_VLD (1U) /*!< Bit field size in bits for DMA_ES_VLD. */ - -/*! @brief Read current value of the DMA_ES_VLD field. */ -#define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_ERQ - Enable Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_ERQ - Enable Request Register (RW) - * - * Reset value: 0x00000000U - * - * The ERQ register provides a bit map for the 16 implemented channels to enable - * the request signal for each channel. The state of any given channel enable is - * directly affected by writes to this register; it is also affected by writes - * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable - * for a single channel can easily be modified without needing to perform a - * read-modify-write sequence to the ERQ. DMA request input signals and this enable - * request flag must be asserted before a channel's hardware service request is - * accepted. The state of the DMA enable request flag does not affect a channel - * service request made explicitly through software or a linked channel request. - */ -typedef union _hw_dma_erq -{ - uint32_t U; - struct _hw_dma_erq_bitfields - { - uint32_t ERQ0 : 1; /*!< [0] Enable DMA Request 0 */ - uint32_t ERQ1 : 1; /*!< [1] Enable DMA Request 1 */ - uint32_t ERQ2 : 1; /*!< [2] Enable DMA Request 2 */ - uint32_t ERQ3 : 1; /*!< [3] Enable DMA Request 3 */ - uint32_t ERQ4 : 1; /*!< [4] Enable DMA Request 4 */ - uint32_t ERQ5 : 1; /*!< [5] Enable DMA Request 5 */ - uint32_t ERQ6 : 1; /*!< [6] Enable DMA Request 6 */ - uint32_t ERQ7 : 1; /*!< [7] Enable DMA Request 7 */ - uint32_t ERQ8 : 1; /*!< [8] Enable DMA Request 8 */ - uint32_t ERQ9 : 1; /*!< [9] Enable DMA Request 9 */ - uint32_t ERQ10 : 1; /*!< [10] Enable DMA Request 10 */ - uint32_t ERQ11 : 1; /*!< [11] Enable DMA Request 11 */ - uint32_t ERQ12 : 1; /*!< [12] Enable DMA Request 12 */ - uint32_t ERQ13 : 1; /*!< [13] Enable DMA Request 13 */ - uint32_t ERQ14 : 1; /*!< [14] Enable DMA Request 14 */ - uint32_t ERQ15 : 1; /*!< [15] Enable DMA Request 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_erq_t; - -/*! - * @name Constants and macros for entire DMA_ERQ register - */ -/*@{*/ -#define HW_DMA_ERQ_ADDR(x) ((x) + 0xCU) - -#define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x)) -#define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U) -#define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v)) -#define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v))) -#define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v))) -#define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_ERQ bitfields - */ - -/*! - * @name Register DMA_ERQ, field ERQ0[0] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ0 (0U) /*!< Bit position for DMA_ERQ_ERQ0. */ -#define BM_DMA_ERQ_ERQ0 (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */ -#define BS_DMA_ERQ_ERQ0 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ0. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */ -#define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ0. */ -#define BF_DMA_ERQ_ERQ0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0) - -/*! @brief Set the ERQ0 field to a new value. */ -#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ1[1] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ1 (1U) /*!< Bit position for DMA_ERQ_ERQ1. */ -#define BM_DMA_ERQ_ERQ1 (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */ -#define BS_DMA_ERQ_ERQ1 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ1. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */ -#define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ1. */ -#define BF_DMA_ERQ_ERQ1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1) - -/*! @brief Set the ERQ1 field to a new value. */ -#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ2[2] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ2 (2U) /*!< Bit position for DMA_ERQ_ERQ2. */ -#define BM_DMA_ERQ_ERQ2 (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */ -#define BS_DMA_ERQ_ERQ2 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ2. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */ -#define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ2. */ -#define BF_DMA_ERQ_ERQ2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2) - -/*! @brief Set the ERQ2 field to a new value. */ -#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ3[3] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ3 (3U) /*!< Bit position for DMA_ERQ_ERQ3. */ -#define BM_DMA_ERQ_ERQ3 (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */ -#define BS_DMA_ERQ_ERQ3 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ3. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */ -#define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ3. */ -#define BF_DMA_ERQ_ERQ3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3) - -/*! @brief Set the ERQ3 field to a new value. */ -#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ4[4] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */ -#define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */ -#define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */ -#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ4. */ -#define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4) - -/*! @brief Set the ERQ4 field to a new value. */ -#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ5[5] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */ -#define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */ -#define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */ -#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ5. */ -#define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5) - -/*! @brief Set the ERQ5 field to a new value. */ -#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ6[6] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */ -#define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */ -#define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */ -#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ6. */ -#define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6) - -/*! @brief Set the ERQ6 field to a new value. */ -#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ7[7] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */ -#define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */ -#define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */ -#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ7. */ -#define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7) - -/*! @brief Set the ERQ7 field to a new value. */ -#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ8[8] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */ -#define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */ -#define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */ -#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ8. */ -#define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8) - -/*! @brief Set the ERQ8 field to a new value. */ -#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ9[9] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */ -#define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */ -#define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */ -#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ9. */ -#define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9) - -/*! @brief Set the ERQ9 field to a new value. */ -#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ10[10] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */ -#define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */ -#define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */ -#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ10. */ -#define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10) - -/*! @brief Set the ERQ10 field to a new value. */ -#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ11[11] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */ -#define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */ -#define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */ -#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ11. */ -#define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11) - -/*! @brief Set the ERQ11 field to a new value. */ -#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ12[12] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */ -#define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */ -#define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */ -#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ12. */ -#define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12) - -/*! @brief Set the ERQ12 field to a new value. */ -#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ13[13] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */ -#define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */ -#define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */ -#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ13. */ -#define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13) - -/*! @brief Set the ERQ13 field to a new value. */ -#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ14[14] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */ -#define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */ -#define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */ -#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ14. */ -#define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14) - -/*! @brief Set the ERQ14 field to a new value. */ -#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ15[15] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */ -#define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */ -#define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */ -#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ15. */ -#define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15) - -/*! @brief Set the ERQ15 field to a new value. */ -#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_EEI - Enable Error Interrupt Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW) - * - * Reset value: 0x00000000U - * - * The EEI register provides a bit map for the 16 channels to enable the error - * interrupt signal for each channel. The state of any given channel's error - * interrupt enable is directly affected by writes to this register; it is also - * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error - * interrupt enable for a single channel can easily be modified without the need to - * perform a read-modify-write sequence to the EEI register. The DMA error - * indicator and the error interrupt enable flag must be asserted before an error - * interrupt request for a given channel is asserted to the interrupt controller. - */ -typedef union _hw_dma_eei -{ - uint32_t U; - struct _hw_dma_eei_bitfields - { - uint32_t EEI0 : 1; /*!< [0] Enable Error Interrupt 0 */ - uint32_t EEI1 : 1; /*!< [1] Enable Error Interrupt 1 */ - uint32_t EEI2 : 1; /*!< [2] Enable Error Interrupt 2 */ - uint32_t EEI3 : 1; /*!< [3] Enable Error Interrupt 3 */ - uint32_t EEI4 : 1; /*!< [4] Enable Error Interrupt 4 */ - uint32_t EEI5 : 1; /*!< [5] Enable Error Interrupt 5 */ - uint32_t EEI6 : 1; /*!< [6] Enable Error Interrupt 6 */ - uint32_t EEI7 : 1; /*!< [7] Enable Error Interrupt 7 */ - uint32_t EEI8 : 1; /*!< [8] Enable Error Interrupt 8 */ - uint32_t EEI9 : 1; /*!< [9] Enable Error Interrupt 9 */ - uint32_t EEI10 : 1; /*!< [10] Enable Error Interrupt 10 */ - uint32_t EEI11 : 1; /*!< [11] Enable Error Interrupt 11 */ - uint32_t EEI12 : 1; /*!< [12] Enable Error Interrupt 12 */ - uint32_t EEI13 : 1; /*!< [13] Enable Error Interrupt 13 */ - uint32_t EEI14 : 1; /*!< [14] Enable Error Interrupt 14 */ - uint32_t EEI15 : 1; /*!< [15] Enable Error Interrupt 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_eei_t; - -/*! - * @name Constants and macros for entire DMA_EEI register - */ -/*@{*/ -#define HW_DMA_EEI_ADDR(x) ((x) + 0x14U) - -#define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x)) -#define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U) -#define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v)) -#define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v))) -#define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v))) -#define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_EEI bitfields - */ - -/*! - * @name Register DMA_EEI, field EEI0[0] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI0 (0U) /*!< Bit position for DMA_EEI_EEI0. */ -#define BM_DMA_EEI_EEI0 (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */ -#define BS_DMA_EEI_EEI0 (1U) /*!< Bit field size in bits for DMA_EEI_EEI0. */ - -/*! @brief Read current value of the DMA_EEI_EEI0 field. */ -#define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0)) - -/*! @brief Format value for bitfield DMA_EEI_EEI0. */ -#define BF_DMA_EEI_EEI0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0) - -/*! @brief Set the EEI0 field to a new value. */ -#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI1[1] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI1 (1U) /*!< Bit position for DMA_EEI_EEI1. */ -#define BM_DMA_EEI_EEI1 (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */ -#define BS_DMA_EEI_EEI1 (1U) /*!< Bit field size in bits for DMA_EEI_EEI1. */ - -/*! @brief Read current value of the DMA_EEI_EEI1 field. */ -#define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1)) - -/*! @brief Format value for bitfield DMA_EEI_EEI1. */ -#define BF_DMA_EEI_EEI1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1) - -/*! @brief Set the EEI1 field to a new value. */ -#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI2[2] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI2 (2U) /*!< Bit position for DMA_EEI_EEI2. */ -#define BM_DMA_EEI_EEI2 (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */ -#define BS_DMA_EEI_EEI2 (1U) /*!< Bit field size in bits for DMA_EEI_EEI2. */ - -/*! @brief Read current value of the DMA_EEI_EEI2 field. */ -#define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2)) - -/*! @brief Format value for bitfield DMA_EEI_EEI2. */ -#define BF_DMA_EEI_EEI2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2) - -/*! @brief Set the EEI2 field to a new value. */ -#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI3[3] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI3 (3U) /*!< Bit position for DMA_EEI_EEI3. */ -#define BM_DMA_EEI_EEI3 (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */ -#define BS_DMA_EEI_EEI3 (1U) /*!< Bit field size in bits for DMA_EEI_EEI3. */ - -/*! @brief Read current value of the DMA_EEI_EEI3 field. */ -#define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3)) - -/*! @brief Format value for bitfield DMA_EEI_EEI3. */ -#define BF_DMA_EEI_EEI3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3) - -/*! @brief Set the EEI3 field to a new value. */ -#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI4[4] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */ -#define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */ -#define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */ - -/*! @brief Read current value of the DMA_EEI_EEI4 field. */ -#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4)) - -/*! @brief Format value for bitfield DMA_EEI_EEI4. */ -#define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4) - -/*! @brief Set the EEI4 field to a new value. */ -#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI5[5] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */ -#define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */ -#define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */ - -/*! @brief Read current value of the DMA_EEI_EEI5 field. */ -#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5)) - -/*! @brief Format value for bitfield DMA_EEI_EEI5. */ -#define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5) - -/*! @brief Set the EEI5 field to a new value. */ -#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI6[6] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */ -#define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */ -#define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */ - -/*! @brief Read current value of the DMA_EEI_EEI6 field. */ -#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6)) - -/*! @brief Format value for bitfield DMA_EEI_EEI6. */ -#define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6) - -/*! @brief Set the EEI6 field to a new value. */ -#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI7[7] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */ -#define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */ -#define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */ - -/*! @brief Read current value of the DMA_EEI_EEI7 field. */ -#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7)) - -/*! @brief Format value for bitfield DMA_EEI_EEI7. */ -#define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7) - -/*! @brief Set the EEI7 field to a new value. */ -#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI8[8] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */ -#define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */ -#define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */ - -/*! @brief Read current value of the DMA_EEI_EEI8 field. */ -#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8)) - -/*! @brief Format value for bitfield DMA_EEI_EEI8. */ -#define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8) - -/*! @brief Set the EEI8 field to a new value. */ -#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI9[9] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */ -#define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */ -#define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */ - -/*! @brief Read current value of the DMA_EEI_EEI9 field. */ -#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9)) - -/*! @brief Format value for bitfield DMA_EEI_EEI9. */ -#define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9) - -/*! @brief Set the EEI9 field to a new value. */ -#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI10[10] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */ -#define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */ -#define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */ - -/*! @brief Read current value of the DMA_EEI_EEI10 field. */ -#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10)) - -/*! @brief Format value for bitfield DMA_EEI_EEI10. */ -#define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10) - -/*! @brief Set the EEI10 field to a new value. */ -#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI11[11] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */ -#define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */ -#define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */ - -/*! @brief Read current value of the DMA_EEI_EEI11 field. */ -#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11)) - -/*! @brief Format value for bitfield DMA_EEI_EEI11. */ -#define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11) - -/*! @brief Set the EEI11 field to a new value. */ -#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI12[12] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */ -#define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */ -#define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */ - -/*! @brief Read current value of the DMA_EEI_EEI12 field. */ -#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12)) - -/*! @brief Format value for bitfield DMA_EEI_EEI12. */ -#define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12) - -/*! @brief Set the EEI12 field to a new value. */ -#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI13[13] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */ -#define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */ -#define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */ - -/*! @brief Read current value of the DMA_EEI_EEI13 field. */ -#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13)) - -/*! @brief Format value for bitfield DMA_EEI_EEI13. */ -#define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13) - -/*! @brief Set the EEI13 field to a new value. */ -#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI14[14] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */ -#define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */ -#define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */ - -/*! @brief Read current value of the DMA_EEI_EEI14 field. */ -#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14)) - -/*! @brief Format value for bitfield DMA_EEI_EEI14. */ -#define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14) - -/*! @brief Set the EEI14 field to a new value. */ -#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI15[15] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */ -#define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */ -#define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */ - -/*! @brief Read current value of the DMA_EEI_EEI15 field. */ -#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15)) - -/*! @brief Format value for bitfield DMA_EEI_EEI15. */ -#define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15) - -/*! @brief Set the EEI15 field to a new value. */ -#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CEEI - Clear Enable Error Interrupt Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO) - * - * Reset value: 0x00U - * - * The CEEI provides a simple memory-mapped mechanism to clear a given bit in - * the EEI to disable the error interrupt for a given channel. The data value on a - * register write causes the corresponding bit in the EEI to be cleared. Setting - * the CAEE bit provides a global clear function, forcing the EEI contents to be - * cleared, disabling all DMA request inputs. If the NOP bit is set, the command - * is ignored. This allows you to write multiple-byte registers as a 32-bit word. - * Reads of this register return all zeroes. - */ -typedef union _hw_dma_ceei -{ - uint8_t U; - struct _hw_dma_ceei_bitfields - { - uint8_t CEEI : 4; /*!< [3:0] Clear Enable Error Interrupt */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAEE : 1; /*!< [6] Clear All Enable Error Interrupts */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_ceei_t; - -/*! - * @name Constants and macros for entire DMA_CEEI register - */ -/*@{*/ -#define HW_DMA_CEEI_ADDR(x) ((x) + 0x18U) - -#define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x)) -#define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U) -#define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CEEI bitfields - */ - -/*! - * @name Register DMA_CEEI, field CEEI[3:0] (WORZ) - * - * Clears the corresponding bit in EEI - */ -/*@{*/ -#define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */ -#define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */ -#define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */ - -/*! @brief Format value for bitfield DMA_CEEI_CEEI. */ -#define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI) - -/*! @brief Set the CEEI field to a new value. */ -#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v))) -/*@}*/ - -/*! - * @name Register DMA_CEEI, field CAEE[6] (WORZ) - * - * Values: - * - 0 - Clear only the EEI bit specified in the CEEI field - * - 1 - Clear all bits in EEI - */ -/*@{*/ -#define BP_DMA_CEEI_CAEE (6U) /*!< Bit position for DMA_CEEI_CAEE. */ -#define BM_DMA_CEEI_CAEE (0x40U) /*!< Bit mask for DMA_CEEI_CAEE. */ -#define BS_DMA_CEEI_CAEE (1U) /*!< Bit field size in bits for DMA_CEEI_CAEE. */ - -/*! @brief Format value for bitfield DMA_CEEI_CAEE. */ -#define BF_DMA_CEEI_CAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE) - -/*! @brief Set the CAEE field to a new value. */ -#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CEEI, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CEEI_NOP (7U) /*!< Bit position for DMA_CEEI_NOP. */ -#define BM_DMA_CEEI_NOP (0x80U) /*!< Bit mask for DMA_CEEI_NOP. */ -#define BS_DMA_CEEI_NOP (1U) /*!< Bit field size in bits for DMA_CEEI_NOP. */ - -/*! @brief Format value for bitfield DMA_CEEI_NOP. */ -#define BF_DMA_CEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_SEEI - Set Enable Error Interrupt Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO) - * - * Reset value: 0x00U - * - * The SEEI provides a simple memory-mapped mechanism to set a given bit in the - * EEI to enable the error interrupt for a given channel. The data value on a - * register write causes the corresponding bit in the EEI to be set. Setting the - * SAEE bit provides a global set function, forcing the entire EEI contents to be - * set. If the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all - * zeroes. - */ -typedef union _hw_dma_seei -{ - uint8_t U; - struct _hw_dma_seei_bitfields - { - uint8_t SEEI : 4; /*!< [3:0] Set Enable Error Interrupt */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t SAEE : 1; /*!< [6] Sets All Enable Error Interrupts */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_seei_t; - -/*! - * @name Constants and macros for entire DMA_SEEI register - */ -/*@{*/ -#define HW_DMA_SEEI_ADDR(x) ((x) + 0x19U) - -#define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x)) -#define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U) -#define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_SEEI bitfields - */ - -/*! - * @name Register DMA_SEEI, field SEEI[3:0] (WORZ) - * - * Sets the corresponding bit in EEI - */ -/*@{*/ -#define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */ -#define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */ -#define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */ - -/*! @brief Format value for bitfield DMA_SEEI_SEEI. */ -#define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI) - -/*! @brief Set the SEEI field to a new value. */ -#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v))) -/*@}*/ - -/*! - * @name Register DMA_SEEI, field SAEE[6] (WORZ) - * - * Values: - * - 0 - Set only the EEI bit specified in the SEEI field. - * - 1 - Sets all bits in EEI - */ -/*@{*/ -#define BP_DMA_SEEI_SAEE (6U) /*!< Bit position for DMA_SEEI_SAEE. */ -#define BM_DMA_SEEI_SAEE (0x40U) /*!< Bit mask for DMA_SEEI_SAEE. */ -#define BS_DMA_SEEI_SAEE (1U) /*!< Bit field size in bits for DMA_SEEI_SAEE. */ - -/*! @brief Format value for bitfield DMA_SEEI_SAEE. */ -#define BF_DMA_SEEI_SAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE) - -/*! @brief Set the SAEE field to a new value. */ -#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_SEEI, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_SEEI_NOP (7U) /*!< Bit position for DMA_SEEI_NOP. */ -#define BM_DMA_SEEI_NOP (0x80U) /*!< Bit mask for DMA_SEEI_NOP. */ -#define BS_DMA_SEEI_NOP (1U) /*!< Bit field size in bits for DMA_SEEI_NOP. */ - -/*! @brief Format value for bitfield DMA_SEEI_NOP. */ -#define BF_DMA_SEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CERQ - Clear Enable Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CERQ - Clear Enable Request Register (WO) - * - * Reset value: 0x00U - * - * The CERQ provides a simple memory-mapped mechanism to clear a given bit in - * the ERQ to disable the DMA request for a given channel. The data value on a - * register write causes the corresponding bit in the ERQ to be cleared. Setting the - * CAER bit provides a global clear function, forcing the entire contents of the - * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the - * command is ignored. This allows you to write multiple-byte registers as a 32-bit - * word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_cerq -{ - uint8_t U; - struct _hw_dma_cerq_bitfields - { - uint8_t CERQ : 4; /*!< [3:0] Clear Enable Request */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAER : 1; /*!< [6] Clear All Enable Requests */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cerq_t; - -/*! - * @name Constants and macros for entire DMA_CERQ register - */ -/*@{*/ -#define HW_DMA_CERQ_ADDR(x) ((x) + 0x1AU) - -#define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x)) -#define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U) -#define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CERQ bitfields - */ - -/*! - * @name Register DMA_CERQ, field CERQ[3:0] (WORZ) - * - * Clears the corresponding bit in ERQ - */ -/*@{*/ -#define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */ -#define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */ -#define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */ - -/*! @brief Format value for bitfield DMA_CERQ_CERQ. */ -#define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ) - -/*! @brief Set the CERQ field to a new value. */ -#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v))) -/*@}*/ - -/*! - * @name Register DMA_CERQ, field CAER[6] (WORZ) - * - * Values: - * - 0 - Clear only the ERQ bit specified in the CERQ field - * - 1 - Clear all bits in ERQ - */ -/*@{*/ -#define BP_DMA_CERQ_CAER (6U) /*!< Bit position for DMA_CERQ_CAER. */ -#define BM_DMA_CERQ_CAER (0x40U) /*!< Bit mask for DMA_CERQ_CAER. */ -#define BS_DMA_CERQ_CAER (1U) /*!< Bit field size in bits for DMA_CERQ_CAER. */ - -/*! @brief Format value for bitfield DMA_CERQ_CAER. */ -#define BF_DMA_CERQ_CAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER) - -/*! @brief Set the CAER field to a new value. */ -#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CERQ, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CERQ_NOP (7U) /*!< Bit position for DMA_CERQ_NOP. */ -#define BM_DMA_CERQ_NOP (0x80U) /*!< Bit mask for DMA_CERQ_NOP. */ -#define BS_DMA_CERQ_NOP (1U) /*!< Bit field size in bits for DMA_CERQ_NOP. */ - -/*! @brief Format value for bitfield DMA_CERQ_NOP. */ -#define BF_DMA_CERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_SERQ - Set Enable Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_SERQ - Set Enable Request Register (WO) - * - * Reset value: 0x00U - * - * The SERQ provides a simple memory-mapped mechanism to set a given bit in the - * ERQ to enable the DMA request for a given channel. The data value on a - * register write causes the corresponding bit in the ERQ to be set. Setting the SAER - * bit provides a global set function, forcing the entire contents of ERQ to be - * set. If the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_serq -{ - uint8_t U; - struct _hw_dma_serq_bitfields - { - uint8_t SERQ : 4; /*!< [3:0] Set enable request */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t SAER : 1; /*!< [6] Set All Enable Requests */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_serq_t; - -/*! - * @name Constants and macros for entire DMA_SERQ register - */ -/*@{*/ -#define HW_DMA_SERQ_ADDR(x) ((x) + 0x1BU) - -#define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x)) -#define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U) -#define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_SERQ bitfields - */ - -/*! - * @name Register DMA_SERQ, field SERQ[3:0] (WORZ) - * - * Sets the corresponding bit in ERQ - */ -/*@{*/ -#define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */ -#define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */ -#define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */ - -/*! @brief Format value for bitfield DMA_SERQ_SERQ. */ -#define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ) - -/*! @brief Set the SERQ field to a new value. */ -#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v))) -/*@}*/ - -/*! - * @name Register DMA_SERQ, field SAER[6] (WORZ) - * - * Values: - * - 0 - Set only the ERQ bit specified in the SERQ field - * - 1 - Set all bits in ERQ - */ -/*@{*/ -#define BP_DMA_SERQ_SAER (6U) /*!< Bit position for DMA_SERQ_SAER. */ -#define BM_DMA_SERQ_SAER (0x40U) /*!< Bit mask for DMA_SERQ_SAER. */ -#define BS_DMA_SERQ_SAER (1U) /*!< Bit field size in bits for DMA_SERQ_SAER. */ - -/*! @brief Format value for bitfield DMA_SERQ_SAER. */ -#define BF_DMA_SERQ_SAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER) - -/*! @brief Set the SAER field to a new value. */ -#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v)) -/*@}*/ - -/*! - * @name Register DMA_SERQ, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_SERQ_NOP (7U) /*!< Bit position for DMA_SERQ_NOP. */ -#define BM_DMA_SERQ_NOP (0x80U) /*!< Bit mask for DMA_SERQ_NOP. */ -#define BS_DMA_SERQ_NOP (1U) /*!< Bit field size in bits for DMA_SERQ_NOP. */ - -/*! @brief Format value for bitfield DMA_SERQ_NOP. */ -#define BF_DMA_SERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CDNE - Clear DONE Status Bit Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO) - * - * Reset value: 0x00U - * - * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in - * the TCD of the given channel. The data value on a register write causes the - * DONE bit in the corresponding transfer control descriptor to be cleared. Setting - * the CADN bit provides a global clear function, forcing all DONE bits to be - * cleared. If the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all - * zeroes. - */ -typedef union _hw_dma_cdne -{ - uint8_t U; - struct _hw_dma_cdne_bitfields - { - uint8_t CDNE : 4; /*!< [3:0] Clear DONE Bit */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CADN : 1; /*!< [6] Clears All DONE Bits */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cdne_t; - -/*! - * @name Constants and macros for entire DMA_CDNE register - */ -/*@{*/ -#define HW_DMA_CDNE_ADDR(x) ((x) + 0x1CU) - -#define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x)) -#define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U) -#define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CDNE bitfields - */ - -/*! - * @name Register DMA_CDNE, field CDNE[3:0] (WORZ) - * - * Clears the corresponding bit in TCDn_CSR[DONE] - */ -/*@{*/ -#define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */ -#define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */ -#define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */ - -/*! @brief Format value for bitfield DMA_CDNE_CDNE. */ -#define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE) - -/*! @brief Set the CDNE field to a new value. */ -#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v))) -/*@}*/ - -/*! - * @name Register DMA_CDNE, field CADN[6] (WORZ) - * - * Values: - * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field - * - 1 - Clears all bits in TCDn_CSR[DONE] - */ -/*@{*/ -#define BP_DMA_CDNE_CADN (6U) /*!< Bit position for DMA_CDNE_CADN. */ -#define BM_DMA_CDNE_CADN (0x40U) /*!< Bit mask for DMA_CDNE_CADN. */ -#define BS_DMA_CDNE_CADN (1U) /*!< Bit field size in bits for DMA_CDNE_CADN. */ - -/*! @brief Format value for bitfield DMA_CDNE_CADN. */ -#define BF_DMA_CDNE_CADN(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN) - -/*! @brief Set the CADN field to a new value. */ -#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CDNE, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CDNE_NOP (7U) /*!< Bit position for DMA_CDNE_NOP. */ -#define BM_DMA_CDNE_NOP (0x80U) /*!< Bit mask for DMA_CDNE_NOP. */ -#define BS_DMA_CDNE_NOP (1U) /*!< Bit field size in bits for DMA_CDNE_NOP. */ - -/*! @brief Format value for bitfield DMA_CDNE_NOP. */ -#define BF_DMA_CDNE_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_SSRT - Set START Bit Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_SSRT - Set START Bit Register (WO) - * - * Reset value: 0x00U - * - * The SSRT provides a simple memory-mapped mechanism to set the START bit in - * the TCD of the given channel. The data value on a register write causes the - * START bit in the corresponding transfer control descriptor to be set. Setting the - * SAST bit provides a global set function, forcing all START bits to be set. If - * the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_ssrt -{ - uint8_t U; - struct _hw_dma_ssrt_bitfields - { - uint8_t SSRT : 4; /*!< [3:0] Set START Bit */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t SAST : 1; /*!< [6] Set All START Bits (activates all - * channels) */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_ssrt_t; - -/*! - * @name Constants and macros for entire DMA_SSRT register - */ -/*@{*/ -#define HW_DMA_SSRT_ADDR(x) ((x) + 0x1DU) - -#define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x)) -#define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U) -#define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_SSRT bitfields - */ - -/*! - * @name Register DMA_SSRT, field SSRT[3:0] (WORZ) - * - * Sets the corresponding bit in TCDn_CSR[START] - */ -/*@{*/ -#define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */ -#define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */ -#define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */ - -/*! @brief Format value for bitfield DMA_SSRT_SSRT. */ -#define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT) - -/*! @brief Set the SSRT field to a new value. */ -#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v))) -/*@}*/ - -/*! - * @name Register DMA_SSRT, field SAST[6] (WORZ) - * - * Values: - * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field - * - 1 - Set all bits in TCDn_CSR[START] - */ -/*@{*/ -#define BP_DMA_SSRT_SAST (6U) /*!< Bit position for DMA_SSRT_SAST. */ -#define BM_DMA_SSRT_SAST (0x40U) /*!< Bit mask for DMA_SSRT_SAST. */ -#define BS_DMA_SSRT_SAST (1U) /*!< Bit field size in bits for DMA_SSRT_SAST. */ - -/*! @brief Format value for bitfield DMA_SSRT_SAST. */ -#define BF_DMA_SSRT_SAST(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST) - -/*! @brief Set the SAST field to a new value. */ -#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v)) -/*@}*/ - -/*! - * @name Register DMA_SSRT, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_SSRT_NOP (7U) /*!< Bit position for DMA_SSRT_NOP. */ -#define BM_DMA_SSRT_NOP (0x80U) /*!< Bit mask for DMA_SSRT_NOP. */ -#define BS_DMA_SSRT_NOP (1U) /*!< Bit field size in bits for DMA_SSRT_NOP. */ - -/*! @brief Format value for bitfield DMA_SSRT_NOP. */ -#define BF_DMA_SSRT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CERR - Clear Error Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CERR - Clear Error Register (WO) - * - * Reset value: 0x00U - * - * The CERR provides a simple memory-mapped mechanism to clear a given bit in - * the ERR to disable the error condition flag for a given channel. The given value - * on a register write causes the corresponding bit in the ERR to be cleared. - * Setting the CAEI bit provides a global clear function, forcing the ERR contents - * to be cleared, clearing all channel error indicators. If the NOP bit is set, - * the command is ignored. This allows you to write multiple-byte registers as a - * 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_cerr -{ - uint8_t U; - struct _hw_dma_cerr_bitfields - { - uint8_t CERR : 4; /*!< [3:0] Clear Error Indicator */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAEI : 1; /*!< [6] Clear All Error Indicators */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cerr_t; - -/*! - * @name Constants and macros for entire DMA_CERR register - */ -/*@{*/ -#define HW_DMA_CERR_ADDR(x) ((x) + 0x1EU) - -#define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x)) -#define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U) -#define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CERR bitfields - */ - -/*! - * @name Register DMA_CERR, field CERR[3:0] (WORZ) - * - * Clears the corresponding bit in ERR - */ -/*@{*/ -#define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */ -#define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */ -#define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */ - -/*! @brief Format value for bitfield DMA_CERR_CERR. */ -#define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR) - -/*! @brief Set the CERR field to a new value. */ -#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v))) -/*@}*/ - -/*! - * @name Register DMA_CERR, field CAEI[6] (WORZ) - * - * Values: - * - 0 - Clear only the ERR bit specified in the CERR field - * - 1 - Clear all bits in ERR - */ -/*@{*/ -#define BP_DMA_CERR_CAEI (6U) /*!< Bit position for DMA_CERR_CAEI. */ -#define BM_DMA_CERR_CAEI (0x40U) /*!< Bit mask for DMA_CERR_CAEI. */ -#define BS_DMA_CERR_CAEI (1U) /*!< Bit field size in bits for DMA_CERR_CAEI. */ - -/*! @brief Format value for bitfield DMA_CERR_CAEI. */ -#define BF_DMA_CERR_CAEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI) - -/*! @brief Set the CAEI field to a new value. */ -#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CERR, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CERR_NOP (7U) /*!< Bit position for DMA_CERR_NOP. */ -#define BM_DMA_CERR_NOP (0x80U) /*!< Bit mask for DMA_CERR_NOP. */ -#define BS_DMA_CERR_NOP (1U) /*!< Bit field size in bits for DMA_CERR_NOP. */ - -/*! @brief Format value for bitfield DMA_CERR_NOP. */ -#define BF_DMA_CERR_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CINT - Clear Interrupt Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO) - * - * Reset value: 0x00U - * - * The CINT provides a simple, memory-mapped mechanism to clear a given bit in - * the INT to disable the interrupt request for a given channel. The given value - * on a register write causes the corresponding bit in the INT to be cleared. - * Setting the CAIR bit provides a global clear function, forcing the entire contents - * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP - * bit is set, the command is ignored. This allows you to write multiple-byte - * registers as a 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_cint -{ - uint8_t U; - struct _hw_dma_cint_bitfields - { - uint8_t CINT : 4; /*!< [3:0] Clear Interrupt Request */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAIR : 1; /*!< [6] Clear All Interrupt Requests */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cint_t; - -/*! - * @name Constants and macros for entire DMA_CINT register - */ -/*@{*/ -#define HW_DMA_CINT_ADDR(x) ((x) + 0x1FU) - -#define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x)) -#define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U) -#define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CINT bitfields - */ - -/*! - * @name Register DMA_CINT, field CINT[3:0] (WORZ) - * - * Clears the corresponding bit in INT - */ -/*@{*/ -#define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */ -#define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */ -#define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */ - -/*! @brief Format value for bitfield DMA_CINT_CINT. */ -#define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT) - -/*! @brief Set the CINT field to a new value. */ -#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v))) -/*@}*/ - -/*! - * @name Register DMA_CINT, field CAIR[6] (WORZ) - * - * Values: - * - 0 - Clear only the INT bit specified in the CINT field - * - 1 - Clear all bits in INT - */ -/*@{*/ -#define BP_DMA_CINT_CAIR (6U) /*!< Bit position for DMA_CINT_CAIR. */ -#define BM_DMA_CINT_CAIR (0x40U) /*!< Bit mask for DMA_CINT_CAIR. */ -#define BS_DMA_CINT_CAIR (1U) /*!< Bit field size in bits for DMA_CINT_CAIR. */ - -/*! @brief Format value for bitfield DMA_CINT_CAIR. */ -#define BF_DMA_CINT_CAIR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR) - -/*! @brief Set the CAIR field to a new value. */ -#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CINT, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CINT_NOP (7U) /*!< Bit position for DMA_CINT_NOP. */ -#define BM_DMA_CINT_NOP (0x80U) /*!< Bit mask for DMA_CINT_NOP. */ -#define BS_DMA_CINT_NOP (1U) /*!< Bit field size in bits for DMA_CINT_NOP. */ - -/*! @brief Format value for bitfield DMA_CINT_NOP. */ -#define BF_DMA_CINT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_INT - Interrupt Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_INT - Interrupt Request Register (RW) - * - * Reset value: 0x00000000U - * - * The INT register provides a bit map for the 16 channels signaling the - * presence of an interrupt request for each channel. Depending on the appropriate bit - * setting in the transfer-control descriptors, the eDMA engine generates an - * interrupt on data transfer completion. The outputs of this register are directly - * routed to the interrupt controller (INTC). During the interrupt-service routine - * associated with any given channel, it is the software's responsibility to - * clear the appropriate bit, negating the interrupt request. Typically, a write to - * the CINT register in the interrupt service routine is used for this purpose. - * The state of any given channel's interrupt request is directly affected by - * writes to this register; it is also affected by writes to the CINT register. On - * writes to INT, a 1 in any bit position clears the corresponding channel's - * interrupt request. A zero in any bit position has no affect on the corresponding - * channel's current interrupt status. The CINT register is provided so the interrupt - * request for a single channel can easily be cleared without the need to - * perform a read-modify-write sequence to the INT register. - */ -typedef union _hw_dma_int -{ - uint32_t U; - struct _hw_dma_int_bitfields - { - uint32_t INT0 : 1; /*!< [0] Interrupt Request 0 */ - uint32_t INT1 : 1; /*!< [1] Interrupt Request 1 */ - uint32_t INT2 : 1; /*!< [2] Interrupt Request 2 */ - uint32_t INT3 : 1; /*!< [3] Interrupt Request 3 */ - uint32_t INT4 : 1; /*!< [4] Interrupt Request 4 */ - uint32_t INT5 : 1; /*!< [5] Interrupt Request 5 */ - uint32_t INT6 : 1; /*!< [6] Interrupt Request 6 */ - uint32_t INT7 : 1; /*!< [7] Interrupt Request 7 */ - uint32_t INT8 : 1; /*!< [8] Interrupt Request 8 */ - uint32_t INT9 : 1; /*!< [9] Interrupt Request 9 */ - uint32_t INT10 : 1; /*!< [10] Interrupt Request 10 */ - uint32_t INT11 : 1; /*!< [11] Interrupt Request 11 */ - uint32_t INT12 : 1; /*!< [12] Interrupt Request 12 */ - uint32_t INT13 : 1; /*!< [13] Interrupt Request 13 */ - uint32_t INT14 : 1; /*!< [14] Interrupt Request 14 */ - uint32_t INT15 : 1; /*!< [15] Interrupt Request 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_int_t; - -/*! - * @name Constants and macros for entire DMA_INT register - */ -/*@{*/ -#define HW_DMA_INT_ADDR(x) ((x) + 0x24U) - -#define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x)) -#define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U) -#define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v)) -#define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v))) -#define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v))) -#define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_INT bitfields - */ - -/*! - * @name Register DMA_INT, field INT0[0] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT0 (0U) /*!< Bit position for DMA_INT_INT0. */ -#define BM_DMA_INT_INT0 (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */ -#define BS_DMA_INT_INT0 (1U) /*!< Bit field size in bits for DMA_INT_INT0. */ - -/*! @brief Read current value of the DMA_INT_INT0 field. */ -#define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0)) - -/*! @brief Format value for bitfield DMA_INT_INT0. */ -#define BF_DMA_INT_INT0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0) - -/*! @brief Set the INT0 field to a new value. */ -#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT1[1] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT1 (1U) /*!< Bit position for DMA_INT_INT1. */ -#define BM_DMA_INT_INT1 (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */ -#define BS_DMA_INT_INT1 (1U) /*!< Bit field size in bits for DMA_INT_INT1. */ - -/*! @brief Read current value of the DMA_INT_INT1 field. */ -#define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1)) - -/*! @brief Format value for bitfield DMA_INT_INT1. */ -#define BF_DMA_INT_INT1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1) - -/*! @brief Set the INT1 field to a new value. */ -#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT2[2] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT2 (2U) /*!< Bit position for DMA_INT_INT2. */ -#define BM_DMA_INT_INT2 (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */ -#define BS_DMA_INT_INT2 (1U) /*!< Bit field size in bits for DMA_INT_INT2. */ - -/*! @brief Read current value of the DMA_INT_INT2 field. */ -#define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2)) - -/*! @brief Format value for bitfield DMA_INT_INT2. */ -#define BF_DMA_INT_INT2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2) - -/*! @brief Set the INT2 field to a new value. */ -#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT3[3] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT3 (3U) /*!< Bit position for DMA_INT_INT3. */ -#define BM_DMA_INT_INT3 (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */ -#define BS_DMA_INT_INT3 (1U) /*!< Bit field size in bits for DMA_INT_INT3. */ - -/*! @brief Read current value of the DMA_INT_INT3 field. */ -#define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3)) - -/*! @brief Format value for bitfield DMA_INT_INT3. */ -#define BF_DMA_INT_INT3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3) - -/*! @brief Set the INT3 field to a new value. */ -#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT4[4] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */ -#define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */ -#define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */ - -/*! @brief Read current value of the DMA_INT_INT4 field. */ -#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4)) - -/*! @brief Format value for bitfield DMA_INT_INT4. */ -#define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4) - -/*! @brief Set the INT4 field to a new value. */ -#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT5[5] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */ -#define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */ -#define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */ - -/*! @brief Read current value of the DMA_INT_INT5 field. */ -#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5)) - -/*! @brief Format value for bitfield DMA_INT_INT5. */ -#define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5) - -/*! @brief Set the INT5 field to a new value. */ -#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT6[6] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */ -#define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */ -#define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */ - -/*! @brief Read current value of the DMA_INT_INT6 field. */ -#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6)) - -/*! @brief Format value for bitfield DMA_INT_INT6. */ -#define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6) - -/*! @brief Set the INT6 field to a new value. */ -#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT7[7] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */ -#define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */ -#define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */ - -/*! @brief Read current value of the DMA_INT_INT7 field. */ -#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7)) - -/*! @brief Format value for bitfield DMA_INT_INT7. */ -#define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7) - -/*! @brief Set the INT7 field to a new value. */ -#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT8[8] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */ -#define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */ -#define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */ - -/*! @brief Read current value of the DMA_INT_INT8 field. */ -#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8)) - -/*! @brief Format value for bitfield DMA_INT_INT8. */ -#define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8) - -/*! @brief Set the INT8 field to a new value. */ -#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT9[9] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */ -#define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */ -#define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */ - -/*! @brief Read current value of the DMA_INT_INT9 field. */ -#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9)) - -/*! @brief Format value for bitfield DMA_INT_INT9. */ -#define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9) - -/*! @brief Set the INT9 field to a new value. */ -#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT10[10] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */ -#define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */ -#define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */ - -/*! @brief Read current value of the DMA_INT_INT10 field. */ -#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10)) - -/*! @brief Format value for bitfield DMA_INT_INT10. */ -#define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10) - -/*! @brief Set the INT10 field to a new value. */ -#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT11[11] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */ -#define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */ -#define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */ - -/*! @brief Read current value of the DMA_INT_INT11 field. */ -#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11)) - -/*! @brief Format value for bitfield DMA_INT_INT11. */ -#define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11) - -/*! @brief Set the INT11 field to a new value. */ -#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT12[12] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */ -#define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */ -#define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */ - -/*! @brief Read current value of the DMA_INT_INT12 field. */ -#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12)) - -/*! @brief Format value for bitfield DMA_INT_INT12. */ -#define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12) - -/*! @brief Set the INT12 field to a new value. */ -#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT13[13] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */ -#define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */ -#define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */ - -/*! @brief Read current value of the DMA_INT_INT13 field. */ -#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13)) - -/*! @brief Format value for bitfield DMA_INT_INT13. */ -#define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13) - -/*! @brief Set the INT13 field to a new value. */ -#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT14[14] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */ -#define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */ -#define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */ - -/*! @brief Read current value of the DMA_INT_INT14 field. */ -#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14)) - -/*! @brief Format value for bitfield DMA_INT_INT14. */ -#define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14) - -/*! @brief Set the INT14 field to a new value. */ -#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT15[15] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */ -#define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */ -#define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */ - -/*! @brief Read current value of the DMA_INT_INT15 field. */ -#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15)) - -/*! @brief Format value for bitfield DMA_INT_INT15. */ -#define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15) - -/*! @brief Set the INT15 field to a new value. */ -#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_ERR - Error Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_ERR - Error Register (RW) - * - * Reset value: 0x00000000U - * - * The ERR provides a bit map for the 16 channels, signaling the presence of an - * error for each channel. The eDMA engine signals the occurrence of an error - * condition by setting the appropriate bit in this register. The outputs of this - * register are enabled by the contents of the EEI, and then routed to the - * interrupt controller. During the execution of the interrupt-service routine associated - * with any DMA errors, it is software's responsibility to clear the appropriate - * bit, negating the error-interrupt request. Typically, a write to the CERR in - * the interrupt-service routine is used for this purpose. The normal DMA channel - * completion indicators (setting the transfer control descriptor DONE flag and - * the possible assertion of an interrupt request) are not affected when an error - * is detected. The contents of this register can also be polled because a - * non-zero value indicates the presence of a channel error regardless of the state of - * the EEI. The state of any given channel's error indicators is affected by - * writes to this register; it is also affected by writes to the CERR. On writes to - * the ERR, a one in any bit position clears the corresponding channel's error - * status. A zero in any bit position has no affect on the corresponding channel's - * current error status. The CERR is provided so the error indicator for a single - * channel can easily be cleared. - */ -typedef union _hw_dma_err -{ - uint32_t U; - struct _hw_dma_err_bitfields - { - uint32_t ERR0 : 1; /*!< [0] Error In Channel 0 */ - uint32_t ERR1 : 1; /*!< [1] Error In Channel 1 */ - uint32_t ERR2 : 1; /*!< [2] Error In Channel 2 */ - uint32_t ERR3 : 1; /*!< [3] Error In Channel 3 */ - uint32_t ERR4 : 1; /*!< [4] Error In Channel 4 */ - uint32_t ERR5 : 1; /*!< [5] Error In Channel 5 */ - uint32_t ERR6 : 1; /*!< [6] Error In Channel 6 */ - uint32_t ERR7 : 1; /*!< [7] Error In Channel 7 */ - uint32_t ERR8 : 1; /*!< [8] Error In Channel 8 */ - uint32_t ERR9 : 1; /*!< [9] Error In Channel 9 */ - uint32_t ERR10 : 1; /*!< [10] Error In Channel 10 */ - uint32_t ERR11 : 1; /*!< [11] Error In Channel 11 */ - uint32_t ERR12 : 1; /*!< [12] Error In Channel 12 */ - uint32_t ERR13 : 1; /*!< [13] Error In Channel 13 */ - uint32_t ERR14 : 1; /*!< [14] Error In Channel 14 */ - uint32_t ERR15 : 1; /*!< [15] Error In Channel 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_err_t; - -/*! - * @name Constants and macros for entire DMA_ERR register - */ -/*@{*/ -#define HW_DMA_ERR_ADDR(x) ((x) + 0x2CU) - -#define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x)) -#define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U) -#define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v)) -#define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v))) -#define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v))) -#define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_ERR bitfields - */ - -/*! - * @name Register DMA_ERR, field ERR0[0] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR0 (0U) /*!< Bit position for DMA_ERR_ERR0. */ -#define BM_DMA_ERR_ERR0 (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */ -#define BS_DMA_ERR_ERR0 (1U) /*!< Bit field size in bits for DMA_ERR_ERR0. */ - -/*! @brief Read current value of the DMA_ERR_ERR0 field. */ -#define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0)) - -/*! @brief Format value for bitfield DMA_ERR_ERR0. */ -#define BF_DMA_ERR_ERR0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0) - -/*! @brief Set the ERR0 field to a new value. */ -#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR1[1] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR1 (1U) /*!< Bit position for DMA_ERR_ERR1. */ -#define BM_DMA_ERR_ERR1 (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */ -#define BS_DMA_ERR_ERR1 (1U) /*!< Bit field size in bits for DMA_ERR_ERR1. */ - -/*! @brief Read current value of the DMA_ERR_ERR1 field. */ -#define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1)) - -/*! @brief Format value for bitfield DMA_ERR_ERR1. */ -#define BF_DMA_ERR_ERR1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1) - -/*! @brief Set the ERR1 field to a new value. */ -#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR2[2] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR2 (2U) /*!< Bit position for DMA_ERR_ERR2. */ -#define BM_DMA_ERR_ERR2 (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */ -#define BS_DMA_ERR_ERR2 (1U) /*!< Bit field size in bits for DMA_ERR_ERR2. */ - -/*! @brief Read current value of the DMA_ERR_ERR2 field. */ -#define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2)) - -/*! @brief Format value for bitfield DMA_ERR_ERR2. */ -#define BF_DMA_ERR_ERR2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2) - -/*! @brief Set the ERR2 field to a new value. */ -#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR3[3] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR3 (3U) /*!< Bit position for DMA_ERR_ERR3. */ -#define BM_DMA_ERR_ERR3 (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */ -#define BS_DMA_ERR_ERR3 (1U) /*!< Bit field size in bits for DMA_ERR_ERR3. */ - -/*! @brief Read current value of the DMA_ERR_ERR3 field. */ -#define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3)) - -/*! @brief Format value for bitfield DMA_ERR_ERR3. */ -#define BF_DMA_ERR_ERR3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3) - -/*! @brief Set the ERR3 field to a new value. */ -#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR4[4] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */ -#define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */ -#define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */ - -/*! @brief Read current value of the DMA_ERR_ERR4 field. */ -#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4)) - -/*! @brief Format value for bitfield DMA_ERR_ERR4. */ -#define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4) - -/*! @brief Set the ERR4 field to a new value. */ -#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR5[5] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */ -#define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */ -#define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */ - -/*! @brief Read current value of the DMA_ERR_ERR5 field. */ -#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5)) - -/*! @brief Format value for bitfield DMA_ERR_ERR5. */ -#define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5) - -/*! @brief Set the ERR5 field to a new value. */ -#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR6[6] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */ -#define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */ -#define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */ - -/*! @brief Read current value of the DMA_ERR_ERR6 field. */ -#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6)) - -/*! @brief Format value for bitfield DMA_ERR_ERR6. */ -#define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6) - -/*! @brief Set the ERR6 field to a new value. */ -#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR7[7] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */ -#define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */ -#define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */ - -/*! @brief Read current value of the DMA_ERR_ERR7 field. */ -#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7)) - -/*! @brief Format value for bitfield DMA_ERR_ERR7. */ -#define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7) - -/*! @brief Set the ERR7 field to a new value. */ -#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR8[8] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */ -#define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */ -#define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */ - -/*! @brief Read current value of the DMA_ERR_ERR8 field. */ -#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8)) - -/*! @brief Format value for bitfield DMA_ERR_ERR8. */ -#define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8) - -/*! @brief Set the ERR8 field to a new value. */ -#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR9[9] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */ -#define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */ -#define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */ - -/*! @brief Read current value of the DMA_ERR_ERR9 field. */ -#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9)) - -/*! @brief Format value for bitfield DMA_ERR_ERR9. */ -#define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9) - -/*! @brief Set the ERR9 field to a new value. */ -#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR10[10] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */ -#define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */ -#define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */ - -/*! @brief Read current value of the DMA_ERR_ERR10 field. */ -#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10)) - -/*! @brief Format value for bitfield DMA_ERR_ERR10. */ -#define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10) - -/*! @brief Set the ERR10 field to a new value. */ -#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR11[11] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */ -#define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */ -#define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */ - -/*! @brief Read current value of the DMA_ERR_ERR11 field. */ -#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11)) - -/*! @brief Format value for bitfield DMA_ERR_ERR11. */ -#define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11) - -/*! @brief Set the ERR11 field to a new value. */ -#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR12[12] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */ -#define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */ -#define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */ - -/*! @brief Read current value of the DMA_ERR_ERR12 field. */ -#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12)) - -/*! @brief Format value for bitfield DMA_ERR_ERR12. */ -#define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12) - -/*! @brief Set the ERR12 field to a new value. */ -#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR13[13] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */ -#define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */ -#define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */ - -/*! @brief Read current value of the DMA_ERR_ERR13 field. */ -#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13)) - -/*! @brief Format value for bitfield DMA_ERR_ERR13. */ -#define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13) - -/*! @brief Set the ERR13 field to a new value. */ -#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR14[14] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */ -#define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */ -#define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */ - -/*! @brief Read current value of the DMA_ERR_ERR14 field. */ -#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14)) - -/*! @brief Format value for bitfield DMA_ERR_ERR14. */ -#define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14) - -/*! @brief Set the ERR14 field to a new value. */ -#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR15[15] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */ -#define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */ -#define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */ - -/*! @brief Read current value of the DMA_ERR_ERR15 field. */ -#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15)) - -/*! @brief Format value for bitfield DMA_ERR_ERR15. */ -#define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15) - -/*! @brief Set the ERR15 field to a new value. */ -#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_HRS - Hardware Request Status Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_HRS - Hardware Request Status Register (RO) - * - * Reset value: 0x00000000U - * - * The HRS register provides a bit map for the DMA channels, signaling the - * presence of a hardware request for each channel. The hardware request status bits - * reflect the current state of the register and qualified (via the ERQ fields) - * DMA request signals as seen by the DMA's arbitration logic. This view into the - * hardware request signals may be used for debug purposes. These bits reflect the - * state of the request as seen by the arbitration logic. Therefore, this status - * is affected by the ERQ bits. - */ -typedef union _hw_dma_hrs -{ - uint32_t U; - struct _hw_dma_hrs_bitfields - { - uint32_t HRS0 : 1; /*!< [0] Hardware Request Status Channel 0 */ - uint32_t HRS1 : 1; /*!< [1] Hardware Request Status Channel 1 */ - uint32_t HRS2 : 1; /*!< [2] Hardware Request Status Channel 2 */ - uint32_t HRS3 : 1; /*!< [3] Hardware Request Status Channel 3 */ - uint32_t HRS4 : 1; /*!< [4] Hardware Request Status Channel 4 */ - uint32_t HRS5 : 1; /*!< [5] Hardware Request Status Channel 5 */ - uint32_t HRS6 : 1; /*!< [6] Hardware Request Status Channel 6 */ - uint32_t HRS7 : 1; /*!< [7] Hardware Request Status Channel 7 */ - uint32_t HRS8 : 1; /*!< [8] Hardware Request Status Channel 8 */ - uint32_t HRS9 : 1; /*!< [9] Hardware Request Status Channel 9 */ - uint32_t HRS10 : 1; /*!< [10] Hardware Request Status Channel 10 */ - uint32_t HRS11 : 1; /*!< [11] Hardware Request Status Channel 11 */ - uint32_t HRS12 : 1; /*!< [12] Hardware Request Status Channel 12 */ - uint32_t HRS13 : 1; /*!< [13] Hardware Request Status Channel 13 */ - uint32_t HRS14 : 1; /*!< [14] Hardware Request Status Channel 14 */ - uint32_t HRS15 : 1; /*!< [15] Hardware Request Status Channel 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] Reserved */ - } B; -} hw_dma_hrs_t; - -/*! - * @name Constants and macros for entire DMA_HRS register - */ -/*@{*/ -#define HW_DMA_HRS_ADDR(x) ((x) + 0x34U) - -#define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x)) -#define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U) -/*@}*/ - -/* - * Constants & macros for individual DMA_HRS bitfields - */ - -/*! - * @name Register DMA_HRS, field HRS0[0] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 0 is not present - * - 1 - A hardware service request for channel 0 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS0 (0U) /*!< Bit position for DMA_HRS_HRS0. */ -#define BM_DMA_HRS_HRS0 (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */ -#define BS_DMA_HRS_HRS0 (1U) /*!< Bit field size in bits for DMA_HRS_HRS0. */ - -/*! @brief Read current value of the DMA_HRS_HRS0 field. */ -#define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS1[1] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 1 is not present - * - 1 - A hardware service request for channel 1 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS1 (1U) /*!< Bit position for DMA_HRS_HRS1. */ -#define BM_DMA_HRS_HRS1 (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */ -#define BS_DMA_HRS_HRS1 (1U) /*!< Bit field size in bits for DMA_HRS_HRS1. */ - -/*! @brief Read current value of the DMA_HRS_HRS1 field. */ -#define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS2[2] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 2 is not present - * - 1 - A hardware service request for channel 2 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS2 (2U) /*!< Bit position for DMA_HRS_HRS2. */ -#define BM_DMA_HRS_HRS2 (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */ -#define BS_DMA_HRS_HRS2 (1U) /*!< Bit field size in bits for DMA_HRS_HRS2. */ - -/*! @brief Read current value of the DMA_HRS_HRS2 field. */ -#define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS3[3] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 3 is not present - * - 1 - A hardware service request for channel 3 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS3 (3U) /*!< Bit position for DMA_HRS_HRS3. */ -#define BM_DMA_HRS_HRS3 (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */ -#define BS_DMA_HRS_HRS3 (1U) /*!< Bit field size in bits for DMA_HRS_HRS3. */ - -/*! @brief Read current value of the DMA_HRS_HRS3 field. */ -#define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS4[4] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 4 is not present - * - 1 - A hardware service request for channel 4 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */ -#define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */ -#define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */ - -/*! @brief Read current value of the DMA_HRS_HRS4 field. */ -#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS5[5] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 5 is not present - * - 1 - A hardware service request for channel 5 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */ -#define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */ -#define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */ - -/*! @brief Read current value of the DMA_HRS_HRS5 field. */ -#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS6[6] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 6 is not present - * - 1 - A hardware service request for channel 6 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */ -#define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */ -#define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */ - -/*! @brief Read current value of the DMA_HRS_HRS6 field. */ -#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS7[7] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 7 is not present - * - 1 - A hardware service request for channel 7 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */ -#define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */ -#define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */ - -/*! @brief Read current value of the DMA_HRS_HRS7 field. */ -#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS8[8] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 8 is not present - * - 1 - A hardware service request for channel 8 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */ -#define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */ -#define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */ - -/*! @brief Read current value of the DMA_HRS_HRS8 field. */ -#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS9[9] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 9 is not present - * - 1 - A hardware service request for channel 9 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */ -#define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */ -#define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */ - -/*! @brief Read current value of the DMA_HRS_HRS9 field. */ -#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS10[10] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 10 is not present - * - 1 - A hardware service request for channel 10 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */ -#define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */ -#define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */ - -/*! @brief Read current value of the DMA_HRS_HRS10 field. */ -#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS11[11] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 11 is not present - * - 1 - A hardware service request for channel 11 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */ -#define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */ -#define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */ - -/*! @brief Read current value of the DMA_HRS_HRS11 field. */ -#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS12[12] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 12 is not present - * - 1 - A hardware service request for channel 12 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */ -#define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */ -#define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */ - -/*! @brief Read current value of the DMA_HRS_HRS12 field. */ -#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS13[13] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 13 is not present - * - 1 - A hardware service request for channel 13 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */ -#define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */ -#define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */ - -/*! @brief Read current value of the DMA_HRS_HRS13 field. */ -#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS14[14] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 14 is not present - * - 1 - A hardware service request for channel 14 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */ -#define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */ -#define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */ - -/*! @brief Read current value of the DMA_HRS_HRS14 field. */ -#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS15[15] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 15 is not present - * - 1 - A hardware service request for channel 15 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */ -#define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */ -#define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */ - -/*! @brief Read current value of the DMA_HRS_HRS15 field. */ -#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_EARS - Enable Asynchronous Request in Stop Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_EARS - Enable Asynchronous Request in Stop Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_ears -{ - uint32_t U; - struct _hw_dma_ears_bitfields - { - uint32_t EDREQ_0 : 1; /*!< [0] Enable asynchronous DMA request in - * stop for channel 0. */ - uint32_t EDREQ_1 : 1; /*!< [1] Enable asynchronous DMA request in - * stop for channel 1. */ - uint32_t EDREQ_2 : 1; /*!< [2] Enable asynchronous DMA request in - * stop for channel 2. */ - uint32_t EDREQ_3 : 1; /*!< [3] Enable asynchronous DMA request in - * stop for channel 3. */ - uint32_t EDREQ_4 : 1; /*!< [4] Enable asynchronous DMA request in - * stop for channel 4 */ - uint32_t EDREQ_5 : 1; /*!< [5] Enable asynchronous DMA request in - * stop for channel 5 */ - uint32_t EDREQ_6 : 1; /*!< [6] Enable asynchronous DMA request in - * stop for channel 6 */ - uint32_t EDREQ_7 : 1; /*!< [7] Enable asynchronous DMA request in - * stop for channel 7 */ - uint32_t EDREQ_8 : 1; /*!< [8] Enable asynchronous DMA request in - * stop for channel 8 */ - uint32_t EDREQ_9 : 1; /*!< [9] Enable asynchronous DMA request in - * stop for channel 9 */ - uint32_t EDREQ_10 : 1; /*!< [10] Enable asynchronous DMA request in - * stop for channel 10 */ - uint32_t EDREQ_11 : 1; /*!< [11] Enable asynchronous DMA request in - * stop for channel 11 */ - uint32_t EDREQ_12 : 1; /*!< [12] Enable asynchronous DMA request in - * stop for channel 12 */ - uint32_t EDREQ_13 : 1; /*!< [13] Enable asynchronous DMA request in - * stop for channel 13 */ - uint32_t EDREQ_14 : 1; /*!< [14] Enable asynchronous DMA request in - * stop for channel 14 */ - uint32_t EDREQ_15 : 1; /*!< [15] Enable asynchronous DMA request in - * stop for channel 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] Reserved. */ - } B; -} hw_dma_ears_t; - -/*! - * @name Constants and macros for entire DMA_EARS register - */ -/*@{*/ -#define HW_DMA_EARS_ADDR(x) ((x) + 0x44U) - -#define HW_DMA_EARS(x) (*(__IO hw_dma_ears_t *) HW_DMA_EARS_ADDR(x)) -#define HW_DMA_EARS_RD(x) (HW_DMA_EARS(x).U) -#define HW_DMA_EARS_WR(x, v) (HW_DMA_EARS(x).U = (v)) -#define HW_DMA_EARS_SET(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) | (v))) -#define HW_DMA_EARS_CLR(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) & ~(v))) -#define HW_DMA_EARS_TOG(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_EARS bitfields - */ - -/*! - * @name Register DMA_EARS, field EDREQ_0[0] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 0. - * - 1 - Enable asynchronous DMA request for channel 0. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_0 (0U) /*!< Bit position for DMA_EARS_EDREQ_0. */ -#define BM_DMA_EARS_EDREQ_0 (0x00000001U) /*!< Bit mask for DMA_EARS_EDREQ_0. */ -#define BS_DMA_EARS_EDREQ_0 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_0. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_0 field. */ -#define BR_DMA_EARS_EDREQ_0(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_0)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_0. */ -#define BF_DMA_EARS_EDREQ_0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_0) & BM_DMA_EARS_EDREQ_0) - -/*! @brief Set the EDREQ_0 field to a new value. */ -#define BW_DMA_EARS_EDREQ_0(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_1[1] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 1 - * - 1 - Enable asynchronous DMA request for channel 1. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_1 (1U) /*!< Bit position for DMA_EARS_EDREQ_1. */ -#define BM_DMA_EARS_EDREQ_1 (0x00000002U) /*!< Bit mask for DMA_EARS_EDREQ_1. */ -#define BS_DMA_EARS_EDREQ_1 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_1. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_1 field. */ -#define BR_DMA_EARS_EDREQ_1(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_1)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_1. */ -#define BF_DMA_EARS_EDREQ_1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_1) & BM_DMA_EARS_EDREQ_1) - -/*! @brief Set the EDREQ_1 field to a new value. */ -#define BW_DMA_EARS_EDREQ_1(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_2[2] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 2. - * - 1 - Enable asynchronous DMA request for channel 2. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_2 (2U) /*!< Bit position for DMA_EARS_EDREQ_2. */ -#define BM_DMA_EARS_EDREQ_2 (0x00000004U) /*!< Bit mask for DMA_EARS_EDREQ_2. */ -#define BS_DMA_EARS_EDREQ_2 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_2. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_2 field. */ -#define BR_DMA_EARS_EDREQ_2(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_2)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_2. */ -#define BF_DMA_EARS_EDREQ_2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_2) & BM_DMA_EARS_EDREQ_2) - -/*! @brief Set the EDREQ_2 field to a new value. */ -#define BW_DMA_EARS_EDREQ_2(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_3[3] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 3. - * - 1 - Enable asynchronous DMA request for channel 3. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_3 (3U) /*!< Bit position for DMA_EARS_EDREQ_3. */ -#define BM_DMA_EARS_EDREQ_3 (0x00000008U) /*!< Bit mask for DMA_EARS_EDREQ_3. */ -#define BS_DMA_EARS_EDREQ_3 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_3. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_3 field. */ -#define BR_DMA_EARS_EDREQ_3(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_3. */ -#define BF_DMA_EARS_EDREQ_3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_3) & BM_DMA_EARS_EDREQ_3) - -/*! @brief Set the EDREQ_3 field to a new value. */ -#define BW_DMA_EARS_EDREQ_3(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_4[4] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 4. - * - 1 - Enable asynchronous DMA request for channel 4. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_4 (4U) /*!< Bit position for DMA_EARS_EDREQ_4. */ -#define BM_DMA_EARS_EDREQ_4 (0x00000010U) /*!< Bit mask for DMA_EARS_EDREQ_4. */ -#define BS_DMA_EARS_EDREQ_4 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_4. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_4 field. */ -#define BR_DMA_EARS_EDREQ_4(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_4. */ -#define BF_DMA_EARS_EDREQ_4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_4) & BM_DMA_EARS_EDREQ_4) - -/*! @brief Set the EDREQ_4 field to a new value. */ -#define BW_DMA_EARS_EDREQ_4(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_5[5] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 5. - * - 1 - Enable asynchronous DMA request for channel 5. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_5 (5U) /*!< Bit position for DMA_EARS_EDREQ_5. */ -#define BM_DMA_EARS_EDREQ_5 (0x00000020U) /*!< Bit mask for DMA_EARS_EDREQ_5. */ -#define BS_DMA_EARS_EDREQ_5 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_5. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_5 field. */ -#define BR_DMA_EARS_EDREQ_5(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_5. */ -#define BF_DMA_EARS_EDREQ_5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_5) & BM_DMA_EARS_EDREQ_5) - -/*! @brief Set the EDREQ_5 field to a new value. */ -#define BW_DMA_EARS_EDREQ_5(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_6[6] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 6. - * - 1 - Enable asynchronous DMA request for channel 6. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_6 (6U) /*!< Bit position for DMA_EARS_EDREQ_6. */ -#define BM_DMA_EARS_EDREQ_6 (0x00000040U) /*!< Bit mask for DMA_EARS_EDREQ_6. */ -#define BS_DMA_EARS_EDREQ_6 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_6. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_6 field. */ -#define BR_DMA_EARS_EDREQ_6(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_6. */ -#define BF_DMA_EARS_EDREQ_6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_6) & BM_DMA_EARS_EDREQ_6) - -/*! @brief Set the EDREQ_6 field to a new value. */ -#define BW_DMA_EARS_EDREQ_6(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_7[7] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 7. - * - 1 - Enable asynchronous DMA request for channel 7. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_7 (7U) /*!< Bit position for DMA_EARS_EDREQ_7. */ -#define BM_DMA_EARS_EDREQ_7 (0x00000080U) /*!< Bit mask for DMA_EARS_EDREQ_7. */ -#define BS_DMA_EARS_EDREQ_7 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_7. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_7 field. */ -#define BR_DMA_EARS_EDREQ_7(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_7. */ -#define BF_DMA_EARS_EDREQ_7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_7) & BM_DMA_EARS_EDREQ_7) - -/*! @brief Set the EDREQ_7 field to a new value. */ -#define BW_DMA_EARS_EDREQ_7(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_8[8] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 8. - * - 1 - Enable asynchronous DMA request for channel 8. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_8 (8U) /*!< Bit position for DMA_EARS_EDREQ_8. */ -#define BM_DMA_EARS_EDREQ_8 (0x00000100U) /*!< Bit mask for DMA_EARS_EDREQ_8. */ -#define BS_DMA_EARS_EDREQ_8 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_8. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_8 field. */ -#define BR_DMA_EARS_EDREQ_8(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_8. */ -#define BF_DMA_EARS_EDREQ_8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_8) & BM_DMA_EARS_EDREQ_8) - -/*! @brief Set the EDREQ_8 field to a new value. */ -#define BW_DMA_EARS_EDREQ_8(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_9[9] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 9. - * - 1 - Enable asynchronous DMA request for channel 9. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_9 (9U) /*!< Bit position for DMA_EARS_EDREQ_9. */ -#define BM_DMA_EARS_EDREQ_9 (0x00000200U) /*!< Bit mask for DMA_EARS_EDREQ_9. */ -#define BS_DMA_EARS_EDREQ_9 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_9. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_9 field. */ -#define BR_DMA_EARS_EDREQ_9(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_9. */ -#define BF_DMA_EARS_EDREQ_9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_9) & BM_DMA_EARS_EDREQ_9) - -/*! @brief Set the EDREQ_9 field to a new value. */ -#define BW_DMA_EARS_EDREQ_9(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_10[10] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 10. - * - 1 - Enable asynchronous DMA request for channel 10. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_10 (10U) /*!< Bit position for DMA_EARS_EDREQ_10. */ -#define BM_DMA_EARS_EDREQ_10 (0x00000400U) /*!< Bit mask for DMA_EARS_EDREQ_10. */ -#define BS_DMA_EARS_EDREQ_10 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_10. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_10 field. */ -#define BR_DMA_EARS_EDREQ_10(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_10. */ -#define BF_DMA_EARS_EDREQ_10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_10) & BM_DMA_EARS_EDREQ_10) - -/*! @brief Set the EDREQ_10 field to a new value. */ -#define BW_DMA_EARS_EDREQ_10(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_11[11] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 11. - * - 1 - Enable asynchronous DMA request for channel 11. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_11 (11U) /*!< Bit position for DMA_EARS_EDREQ_11. */ -#define BM_DMA_EARS_EDREQ_11 (0x00000800U) /*!< Bit mask for DMA_EARS_EDREQ_11. */ -#define BS_DMA_EARS_EDREQ_11 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_11. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_11 field. */ -#define BR_DMA_EARS_EDREQ_11(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_11. */ -#define BF_DMA_EARS_EDREQ_11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_11) & BM_DMA_EARS_EDREQ_11) - -/*! @brief Set the EDREQ_11 field to a new value. */ -#define BW_DMA_EARS_EDREQ_11(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_12[12] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 12. - * - 1 - Enable asynchronous DMA request for channel 12. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_12 (12U) /*!< Bit position for DMA_EARS_EDREQ_12. */ -#define BM_DMA_EARS_EDREQ_12 (0x00001000U) /*!< Bit mask for DMA_EARS_EDREQ_12. */ -#define BS_DMA_EARS_EDREQ_12 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_12. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_12 field. */ -#define BR_DMA_EARS_EDREQ_12(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_12. */ -#define BF_DMA_EARS_EDREQ_12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_12) & BM_DMA_EARS_EDREQ_12) - -/*! @brief Set the EDREQ_12 field to a new value. */ -#define BW_DMA_EARS_EDREQ_12(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_13[13] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 13. - * - 1 - Enable asynchronous DMA request for channel 13. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_13 (13U) /*!< Bit position for DMA_EARS_EDREQ_13. */ -#define BM_DMA_EARS_EDREQ_13 (0x00002000U) /*!< Bit mask for DMA_EARS_EDREQ_13. */ -#define BS_DMA_EARS_EDREQ_13 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_13. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_13 field. */ -#define BR_DMA_EARS_EDREQ_13(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_13. */ -#define BF_DMA_EARS_EDREQ_13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_13) & BM_DMA_EARS_EDREQ_13) - -/*! @brief Set the EDREQ_13 field to a new value. */ -#define BW_DMA_EARS_EDREQ_13(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_14[14] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 14. - * - 1 - Enable asynchronous DMA request for channel 14. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_14 (14U) /*!< Bit position for DMA_EARS_EDREQ_14. */ -#define BM_DMA_EARS_EDREQ_14 (0x00004000U) /*!< Bit mask for DMA_EARS_EDREQ_14. */ -#define BS_DMA_EARS_EDREQ_14 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_14. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_14 field. */ -#define BR_DMA_EARS_EDREQ_14(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_14. */ -#define BF_DMA_EARS_EDREQ_14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_14) & BM_DMA_EARS_EDREQ_14) - -/*! @brief Set the EDREQ_14 field to a new value. */ -#define BW_DMA_EARS_EDREQ_14(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EARS, field EDREQ_15[15] (RW) - * - * Values: - * - 0 - Disable asynchronous DMA request for channel 15. - * - 1 - Enable asynchronous DMA request for channel 15. - */ -/*@{*/ -#define BP_DMA_EARS_EDREQ_15 (15U) /*!< Bit position for DMA_EARS_EDREQ_15. */ -#define BM_DMA_EARS_EDREQ_15 (0x00008000U) /*!< Bit mask for DMA_EARS_EDREQ_15. */ -#define BS_DMA_EARS_EDREQ_15 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_15. */ - -/*! @brief Read current value of the DMA_EARS_EDREQ_15 field. */ -#define BR_DMA_EARS_EDREQ_15(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15)) - -/*! @brief Format value for bitfield DMA_EARS_EDREQ_15. */ -#define BF_DMA_EARS_EDREQ_15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_15) & BM_DMA_EARS_EDREQ_15) - -/*! @brief Set the EDREQ_15 field to a new value. */ -#define BW_DMA_EARS_EDREQ_15(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_DCHPRIn - Channel n Priority Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW) - * - * Reset value: 0x00U - * - * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the - * contents of these registers define the unique priorities associated with each - * channel . The channel priorities are evaluated by numeric value; for example, 0 is - * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must - * program the channel priorities with unique values; otherwise, a configuration - * error is reported. The range of the priority value is limited to the values of 0 - * through 15. - */ -typedef union _hw_dma_dchprin -{ - uint8_t U; - struct _hw_dma_dchprin_bitfields - { - uint8_t CHPRI : 4; /*!< [3:0] Channel n Arbitration Priority */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t DPA : 1; /*!< [6] Disable Preempt Ability */ - uint8_t ECP : 1; /*!< [7] Enable Channel Preemption */ - } B; -} hw_dma_dchprin_t; - -/*! - * @name Constants and macros for entire DMA_DCHPRIn register - */ -/*@{*/ -#define HW_DMA_DCHPRIn_COUNT (16U) - -#define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n))) - -/* DMA channel index to DMA channel priority register array index conversion macro */ -#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U))) - -#define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n)) -#define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U) -#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v)) -#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v))) -#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v))) -#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_DCHPRIn bitfields - */ - -/*! - * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW) - * - * Channel priority when fixed-priority arbitration is enabled Reset value for - * the channel priority fields, CHPRI, is equal to the corresponding channel - * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. - */ -/*@{*/ -#define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */ -#define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */ -#define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */ - -/*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */ -#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI) - -/*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */ -#define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI) - -/*! @brief Set the CHPRI field to a new value. */ -#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v))) -/*@}*/ - -/*! - * @name Register DMA_DCHPRIn, field DPA[6] (RW) - * - * Values: - * - 0 - Channel n can suspend a lower priority channel - * - 1 - Channel n cannot suspend any channel, regardless of channel priority - */ -/*@{*/ -#define BP_DMA_DCHPRIn_DPA (6U) /*!< Bit position for DMA_DCHPRIn_DPA. */ -#define BM_DMA_DCHPRIn_DPA (0x40U) /*!< Bit mask for DMA_DCHPRIn_DPA. */ -#define BS_DMA_DCHPRIn_DPA (1U) /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */ - -/*! @brief Read current value of the DMA_DCHPRIn_DPA field. */ -#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA)) - -/*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */ -#define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA) - -/*! @brief Set the DPA field to a new value. */ -#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v)) -/*@}*/ - -/*! - * @name Register DMA_DCHPRIn, field ECP[7] (RW) - * - * Values: - * - 0 - Channel n cannot be suspended by a higher priority channel's service - * request - * - 1 - Channel n can be temporarily suspended by the service request of a - * higher priority channel - */ -/*@{*/ -#define BP_DMA_DCHPRIn_ECP (7U) /*!< Bit position for DMA_DCHPRIn_ECP. */ -#define BM_DMA_DCHPRIn_ECP (0x80U) /*!< Bit mask for DMA_DCHPRIn_ECP. */ -#define BS_DMA_DCHPRIn_ECP (1U) /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */ - -/*! @brief Read current value of the DMA_DCHPRIn_ECP field. */ -#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP)) - -/*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */ -#define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP) - -/*! @brief Set the ECP field to a new value. */ -#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_TCDn_SADDR - TCD Source Address - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_saddr -{ - uint32_t U; - struct _hw_dma_tcdn_saddr_bitfields - { - uint32_t SADDR : 32; /*!< [31:0] Source Address */ - } B; -} hw_dma_tcdn_saddr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_SADDR register - */ -/*@{*/ -#define HW_DMA_TCDn_SADDR_COUNT (16U) - -#define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n))) - -#define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n)) -#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U) -#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v)) -#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v))) -#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_SADDR bitfields - */ - -/*! - * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW) - * - * Memory address pointing to the source data. - */ -/*@{*/ -#define BP_DMA_TCDn_SADDR_SADDR (0U) /*!< Bit position for DMA_TCDn_SADDR_SADDR. */ -#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */ -#define BS_DMA_TCDn_SADDR_SADDR (32U) /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */ - -/*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */ -#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */ -#define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR) - -/*! @brief Set the SADDR field to a new value. */ -#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_soff -{ - uint16_t U; - struct _hw_dma_tcdn_soff_bitfields - { - uint16_t SOFF : 16; /*!< [15:0] Source address signed offset */ - } B; -} hw_dma_tcdn_soff_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_SOFF register - */ -/*@{*/ -#define HW_DMA_TCDn_SOFF_COUNT (16U) - -#define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n))) - -#define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n)) -#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U) -#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v)) -#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v))) -#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_SOFF bitfields - */ - -/*! - * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW) - * - * Sign-extended offset applied to the current source address to form the - * next-state value as each source read is completed. - */ -/*@{*/ -#define BP_DMA_TCDn_SOFF_SOFF (0U) /*!< Bit position for DMA_TCDn_SOFF_SOFF. */ -#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */ -#define BS_DMA_TCDn_SOFF_SOFF (16U) /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */ - -/*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */ -#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */ -#define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF) - -/*! @brief Set the SOFF field to a new value. */ -#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_ATTR - TCD Transfer Attributes - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_attr -{ - uint16_t U; - struct _hw_dma_tcdn_attr_bitfields - { - uint16_t DSIZE : 3; /*!< [2:0] Destination Data Transfer Size */ - uint16_t DMOD : 5; /*!< [7:3] Destination Address Modulo */ - uint16_t SSIZE : 3; /*!< [10:8] Source data transfer size */ - uint16_t SMOD : 5; /*!< [15:11] Source Address Modulo. */ - } B; -} hw_dma_tcdn_attr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_ATTR register - */ -/*@{*/ -#define HW_DMA_TCDn_ATTR_COUNT (16U) - -#define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n))) - -#define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n)) -#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U) -#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v)) -#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v))) -#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_ATTR bitfields - */ - -/*! - * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW) - * - * See the SSIZE definition - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_DSIZE (0U) /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */ -#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */ -#define BS_DMA_TCDn_ATTR_DSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */ -#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */ -#define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE) - -/*! @brief Set the DSIZE field to a new value. */ -#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW) - * - * See the SMOD definition - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_DMOD (3U) /*!< Bit position for DMA_TCDn_ATTR_DMOD. */ -#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */ -#define BS_DMA_TCDn_ATTR_DMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */ -#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */ -#define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD) - -/*! @brief Set the DMOD field to a new value. */ -#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW) - * - * The attempted use of a Reserved encoding causes a configuration error. - * - * Values: - * - 000 - 8-bit - * - 001 - 16-bit - * - 010 - 32-bit - * - 011 - Reserved - * - 100 - 16-byte - * - 101 - 32-byte - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_SSIZE (8U) /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */ -#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */ -#define BS_DMA_TCDn_ATTR_SSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */ -#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */ -#define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE) - -/*! @brief Set the SSIZE field to a new value. */ -#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW) - * - * Values: - * - 0 - Source address modulo feature is disabled - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_SMOD (11U) /*!< Bit position for DMA_TCDn_ATTR_SMOD. */ -#define BM_DMA_TCDn_ATTR_SMOD (0xF800U) /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */ -#define BS_DMA_TCDn_ATTR_SMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */ -#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */ -#define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD) - -/*! @brief Set the SMOD field to a new value. */ -#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v))) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW) - * - * Reset value: 0x00000000U - * - * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO, - * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which - * register to use depends on whether minor loop mapping is disabled, enabled but not - * used for this channel, or enabled and used. TCD word 2 is defined as follows - * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is - * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions - * for TCD word 2's definition. - */ -typedef union _hw_dma_tcdn_nbytes_mlno -{ - uint32_t U; - struct _hw_dma_tcdn_nbytes_mlno_bitfields - { - uint32_t NBYTES : 32; /*!< [31:0] Minor Byte Transfer Count */ - } B; -} hw_dma_tcdn_nbytes_mlno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register - */ -/*@{*/ -#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U) - -#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) - -#define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n)) -#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U) -#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v)) -#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields - */ - -/*! - * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW) - * - * Number of bytes to be transferred in each service request of the channel. As - * a channel activates, the appropriate TCD contents load into the eDMA engine, - * and the appropriate reads and writes perform until the minor byte transfer - * count has transferred. This is an indivisible operation and cannot be halted. - * (Although, it may be stalled by using the bandwidth control field, or via - * preemption.) After the minor count is exhausted, the SADDR and DADDR values are - * written back into the TCD memory, the major iteration count is decremented and - * restored to the TCD memory. If the major iteration count is completed, additional - * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4 - * GB transfer. - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */ -#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */ -#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */ -#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */ -#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES) - -/*! @brief Set the NBYTES field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW) - * - * Reset value: 0x00000000U - * - * One of three registers (this register, TCD_NBYTES_MLNO, or - * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use - * depends on whether minor loop mapping is disabled, enabled but not used for - * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor - * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor - * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the - * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to - * the TCD_NBYTES_MLNO register description. - */ -typedef union _hw_dma_tcdn_nbytes_mloffno -{ - uint32_t U; - struct _hw_dma_tcdn_nbytes_mloffno_bitfields - { - uint32_t NBYTES : 30; /*!< [29:0] Minor Byte Transfer Count */ - uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */ - uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */ - } B; -} hw_dma_tcdn_nbytes_mloffno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register - */ -/*@{*/ -#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U) - -#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) - -#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n)) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v)) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields - */ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW) - * - * Number of bytes to be transferred in each service request of the channel. As - * a channel activates, the appropriate TCD contents load into the eDMA engine, - * and the appropriate reads and writes perform until the minor byte transfer - * count has transferred. This is an indivisible operation and cannot be halted; - * although, it may be stalled by using the bandwidth control field, or via - * preemption. After the minor count is exhausted, the SADDR and DADDR values are written - * back into the TCD memory, the major iteration count is decremented and - * restored to the TCD memory. If the major iteration count is completed, additional - * processing is performed. - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ -#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ -#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ -#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) - -/*! @brief Set the NBYTES field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW) - * - * Selects whether the minor loop offset is applied to the destination address - * upon minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the DADDR - * - 1 - The minor loop offset is applied to the DADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) - -/*! @brief Set the DMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW) - * - * Selects whether the minor loop offset is applied to the source address upon - * minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the SADDR - * - 1 - The minor loop offset is applied to the SADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) - -/*! @brief Set the SMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW) - * - * Reset value: 0x00000000U - * - * One of three registers (this register, TCD_NBYTES_MLNO, or - * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use - * depends on whether minor loop mapping is disabled, enabled but not used for - * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor - * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE - * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared, - * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop - * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. - */ -typedef union _hw_dma_tcdn_nbytes_mloffyes -{ - uint32_t U; - struct _hw_dma_tcdn_nbytes_mloffyes_bitfields - { - uint32_t NBYTES : 10; /*!< [9:0] Minor Byte Transfer Count */ - uint32_t MLOFF : 20; /*!< [29:10] If SMLOE or DMLOE is set, this - * field represents a sign-extended offset applied to the source or destination - * address to form the next-state value after the minor loop completes. */ - uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */ - uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */ - } B; -} hw_dma_tcdn_nbytes_mloffyes_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register - */ -/*@{*/ -#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U) - -#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) - -#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n)) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v)) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v))) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields - */ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW) - * - * Number of bytes to be transferred in each service request of the channel. As - * a channel activates, the appropriate TCD contents load into the eDMA engine, - * and the appropriate reads and writes perform until the minor byte transfer - * count has transferred. This is an indivisible operation and cannot be halted. - * (Although, it may be stalled by using the bandwidth control field, or via - * preemption.) After the minor count is exhausted, the SADDR and DADDR values are - * written back into the TCD memory, the major iteration count is decremented and - * restored to the TCD memory. If the major iteration count is completed, additional - * processing is performed. - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) - -/*! @brief Set the NBYTES field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW) - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) - -/*! @brief Set the MLOFF field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW) - * - * Selects whether the minor loop offset is applied to the destination address - * upon minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the DADDR - * - 1 - The minor loop offset is applied to the DADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) - -/*! @brief Set the DMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW) - * - * Selects whether the minor loop offset is applied to the source address upon - * minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the SADDR - * - 1 - The minor loop offset is applied to the SADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) - -/*! @brief Set the SMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_slast -{ - uint32_t U; - struct _hw_dma_tcdn_slast_bitfields - { - uint32_t SLAST : 32; /*!< [31:0] Last source Address Adjustment */ - } B; -} hw_dma_tcdn_slast_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_SLAST register - */ -/*@{*/ -#define HW_DMA_TCDn_SLAST_COUNT (16U) - -#define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n))) - -#define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n)) -#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U) -#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v)) -#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v))) -#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_SLAST bitfields - */ - -/*! - * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW) - * - * Adjustment value added to the source address at the completion of the major - * iteration count. This value can be applied to restore the source address to the - * initial value, or adjust the address to reference the next data structure. - * This register uses two's complement notation; the overflow bit is discarded. - */ -/*@{*/ -#define BP_DMA_TCDn_SLAST_SLAST (0U) /*!< Bit position for DMA_TCDn_SLAST_SLAST. */ -#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */ -#define BS_DMA_TCDn_SLAST_SLAST (32U) /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */ - -/*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */ -#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */ -#define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST) - -/*! @brief Set the SLAST field to a new value. */ -#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_DADDR - TCD Destination Address - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_daddr -{ - uint32_t U; - struct _hw_dma_tcdn_daddr_bitfields - { - uint32_t DADDR : 32; /*!< [31:0] Destination Address */ - } B; -} hw_dma_tcdn_daddr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_DADDR register - */ -/*@{*/ -#define HW_DMA_TCDn_DADDR_COUNT (16U) - -#define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n))) - -#define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n)) -#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U) -#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v)) -#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v))) -#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_DADDR bitfields - */ - -/*! - * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW) - * - * Memory address pointing to the destination data. - */ -/*@{*/ -#define BP_DMA_TCDn_DADDR_DADDR (0U) /*!< Bit position for DMA_TCDn_DADDR_DADDR. */ -#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */ -#define BS_DMA_TCDn_DADDR_DADDR (32U) /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */ - -/*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */ -#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */ -#define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR) - -/*! @brief Set the DADDR field to a new value. */ -#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_doff -{ - uint16_t U; - struct _hw_dma_tcdn_doff_bitfields - { - uint16_t DOFF : 16; /*!< [15:0] Destination Address Signed offset */ - } B; -} hw_dma_tcdn_doff_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_DOFF register - */ -/*@{*/ -#define HW_DMA_TCDn_DOFF_COUNT (16U) - -#define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n))) - -#define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n)) -#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U) -#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v)) -#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v))) -#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_DOFF bitfields - */ - -/*! - * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW) - * - * Sign-extended offset applied to the current destination address to form the - * next-state value as each destination write is completed. - */ -/*@{*/ -#define BP_DMA_TCDn_DOFF_DOFF (0U) /*!< Bit position for DMA_TCDn_DOFF_DOFF. */ -#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */ -#define BS_DMA_TCDn_DOFF_DOFF (16U) /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */ - -/*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */ -#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */ -#define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF) - -/*! @brief Set the DOFF field to a new value. */ -#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW) - * - * Reset value: 0x0000U - * - * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as - * follows. - */ -typedef union _hw_dma_tcdn_citer_elinkno -{ - uint16_t U; - struct _hw_dma_tcdn_citer_elinkno_bitfields - { - uint16_t CITER : 15; /*!< [14:0] Current Major Iteration Count */ - uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on - * minor-loop complete */ - } B; -} hw_dma_tcdn_citer_elinkno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register - */ -/*@{*/ -#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U) - -#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n))) - -#define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n)) -#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U) -#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v)) -#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields - */ - -/*! - * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW) - * - * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current - * major loop count for the channel. It is decremented each time the minor loop is - * completed and updated in the transfer control descriptor memory. After the - * major iteration count is exhausted, the channel performs a number of operations - * (e.g., final source and destination address calculations), optionally generating - * an interrupt to signal channel completion before reloading the CITER field - * from the beginning iteration count (BITER) field. When the CITER field is - * initially loaded by software, it must be set to the same value as that contained in - * the BITER field. If the channel is configured to execute a single service - * request, the initial values of BITER and CITER should be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */ -#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */ -#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */ -#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */ -#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER) - -/*! @brief Set the CITER field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables linking to another - * channel, defined by the LINKCH field. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking is disabled, the CITER value - * is extended to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK - * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a - * configuration error is reported. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */ -#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */ -#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */ -#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */ -#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW) - * - * Reset value: 0x0000U - * - * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. - */ -typedef union _hw_dma_tcdn_citer_elinkyes -{ - uint16_t U; - struct _hw_dma_tcdn_citer_elinkyes_bitfields - { - uint16_t CITER : 9; /*!< [8:0] Current Major Iteration Count */ - uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */ - uint16_t RESERVED0 : 2; /*!< [14:13] */ - uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on - * minor-loop complete */ - } B; -} hw_dma_tcdn_citer_elinkyes_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register - */ -/*@{*/ -#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U) - -#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n))) - -#define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n)) -#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U) -#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v)) -#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v))) -#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields - */ - -/*! - * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW) - * - * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current - * major loop count for the channel. It is decremented each time the minor loop is - * completed and updated in the transfer control descriptor memory. After the - * major iteration count is exhausted, the channel performs a number of operations - * (e.g., final source and destination address calculations), optionally generating - * an interrupt to signal channel completion before reloading the CITER field - * from the beginning iteration count (BITER) field. When the CITER field is - * initially loaded by software, it must be set to the same value as that contained in - * the BITER field. If the channel is configured to execute a single service - * request, the initial values of BITER and CITER should be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */ -#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */ -#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */ -#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */ -#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER) - -/*! @brief Set the CITER field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW) - * - * If channel-to-channel linking is enabled (ELINK = 1), then after the minor - * loop is exhausted, the eDMA engine initiates a channel service request to the - * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit. - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */ -#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH) - -/*! @brief Set the LINKCH field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables linking to another - * channel, defined by the LINKCH field. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking is disabled, the CITER value - * is extended to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK - * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a - * configuration error is reported. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */ -#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */ -#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */ -#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */ -#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_dlastsga -{ - uint32_t U; - struct _hw_dma_tcdn_dlastsga_bitfields - { - uint32_t DLASTSGA : 32; /*!< [31:0] */ - } B; -} hw_dma_tcdn_dlastsga_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_DLASTSGA register - */ -/*@{*/ -#define HW_DMA_TCDn_DLASTSGA_COUNT (16U) - -#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n))) - -#define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n)) -#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U) -#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v)) -#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v))) -#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields - */ - -/*! - * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW) - * - * Destination last address adjustment or the memory address for the next - * transfer control descriptor to be loaded into this channel (scatter/gather). If - * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at - * the completion of the major iteration count. This value can apply to restore the - * destination address to the initial value or adjust the address to reference - * the next data structure. This field uses two's complement notation for the - * final destination address adjustment. Otherwise: This address points to the - * beginning of a 0-modulo-32-byte region containing the next transfer control - * descriptor to be loaded into this channel. This channel reload is performed as the - * major iteration count completes. The scatter/gather address must be - * 0-modulo-32-byte, else a configuration error is reported. - */ -/*@{*/ -#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */ -#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */ -#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */ - -/*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */ -#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */ -#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA) - -/*! @brief Set the DLASTSGA field to a new value. */ -#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_CSR - TCD Control and Status - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_csr -{ - uint16_t U; - struct _hw_dma_tcdn_csr_bitfields - { - uint16_t START : 1; /*!< [0] Channel Start */ - uint16_t INTMAJOR : 1; /*!< [1] Enable an interrupt when major - * iteration count completes */ - uint16_t INTHALF : 1; /*!< [2] Enable an interrupt when major counter - * is half complete. */ - uint16_t DREQ : 1; /*!< [3] Disable Request */ - uint16_t ESG : 1; /*!< [4] Enable Scatter/Gather Processing */ - uint16_t MAJORELINK : 1; /*!< [5] Enable channel-to-channel linking - * on major loop complete */ - uint16_t ACTIVE : 1; /*!< [6] Channel Active */ - uint16_t DONE : 1; /*!< [7] Channel Done */ - uint16_t MAJORLINKCH : 4; /*!< [11:8] Link Channel Number */ - uint16_t RESERVED0 : 2; /*!< [13:12] */ - uint16_t BWC : 2; /*!< [15:14] Bandwidth Control */ - } B; -} hw_dma_tcdn_csr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_CSR register - */ -/*@{*/ -#define HW_DMA_TCDn_CSR_COUNT (16U) - -#define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n))) - -#define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n)) -#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U) -#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v)) -#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v))) -#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_CSR bitfields - */ - -/*! - * @name Register DMA_TCDn_CSR, field START[0] (RW) - * - * If this flag is set, the channel is requesting service. The eDMA hardware - * automatically clears this flag after the channel begins execution. - * - * Values: - * - 0 - The channel is not explicitly started - * - 1 - The channel is explicitly started via a software initiated service - * request - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_START (0U) /*!< Bit position for DMA_TCDn_CSR_START. */ -#define BM_DMA_TCDn_CSR_START (0x0001U) /*!< Bit mask for DMA_TCDn_CSR_START. */ -#define BS_DMA_TCDn_CSR_START (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_START. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_START field. */ -#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_START. */ -#define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START) - -/*! @brief Set the START field to a new value. */ -#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW) - * - * If this flag is set, the channel generates an interrupt request by setting - * the appropriate bit in the INT when the current major iteration count reaches - * zero. - * - * Values: - * - 0 - The end-of-major loop interrupt is disabled - * - 1 - The end-of-major loop interrupt is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */ -#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */ -#define BS_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */ -#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */ -#define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR) - -/*! @brief Set the INTMAJOR field to a new value. */ -#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW) - * - * If this flag is set, the channel generates an interrupt request by setting - * the appropriate bit in the INT register when the current major iteration count - * reaches the halfway point. Specifically, the comparison performed by the eDMA - * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is - * provided to support double-buffered (aka ping-pong) schemes or other types of data - * movement where the processor needs an early indication of the transfer's - * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead. - * - * Values: - * - 0 - The half-point interrupt is disabled - * - 1 - The half-point interrupt is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_INTHALF (2U) /*!< Bit position for DMA_TCDn_CSR_INTHALF. */ -#define BM_DMA_TCDn_CSR_INTHALF (0x0004U) /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */ -#define BS_DMA_TCDn_CSR_INTHALF (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */ -#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */ -#define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF) - -/*! @brief Set the INTHALF field to a new value. */ -#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field DREQ[3] (RW) - * - * If this flag is set, the eDMA hardware automatically clears the corresponding - * ERQ bit when the current major iteration count reaches zero. - * - * Values: - * - 0 - The channel's ERQ bit is not affected - * - 1 - The channel's ERQ bit is cleared when the major loop is complete - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_DREQ (3U) /*!< Bit position for DMA_TCDn_CSR_DREQ. */ -#define BM_DMA_TCDn_CSR_DREQ (0x0008U) /*!< Bit mask for DMA_TCDn_CSR_DREQ. */ -#define BS_DMA_TCDn_CSR_DREQ (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */ -#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */ -#define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ) - -/*! @brief Set the DREQ field to a new value. */ -#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field ESG[4] (RW) - * - * As the channel completes the major loop, this flag enables scatter/gather - * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a - * memory pointer to a 0-modulo-32 address containing a 32-byte data structure - * loaded as the transfer control descriptor into the local memory. To support the - * dynamic scatter/gather coherency model, this field is forced to zero when - * written to while the TCDn_CSR[DONE] bit is set. - * - * Values: - * - 0 - The current channel's TCD is normal format. - * - 1 - The current channel's TCD specifies a scatter gather format. The - * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this - * channel after the major loop completes its execution. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_ESG (4U) /*!< Bit position for DMA_TCDn_CSR_ESG. */ -#define BM_DMA_TCDn_CSR_ESG (0x0010U) /*!< Bit mask for DMA_TCDn_CSR_ESG. */ -#define BS_DMA_TCDn_CSR_ESG (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */ -#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */ -#define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG) - -/*! @brief Set the ESG field to a new value. */ -#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW) - * - * As the channel completes the major loop, this flag enables the linking to - * another channel, defined by MAJORLINKCH. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. To support the dynamic linking coherency model, - * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_MAJORELINK (5U) /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */ -#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */ -#define BS_DMA_TCDn_CSR_MAJORELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */ -#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */ -#define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK) - -/*! @brief Set the MAJORELINK field to a new value. */ -#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW) - * - * This flag signals the channel is currently in execution. It is set when - * channel service begins, and the eDMA clears it as the minor loop completes or if - * any error condition is detected. This bit resets to zero. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_ACTIVE (6U) /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */ -#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */ -#define BS_DMA_TCDn_CSR_ACTIVE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */ -#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */ -#define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE) - -/*! @brief Set the ACTIVE field to a new value. */ -#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field DONE[7] (RW) - * - * This flag indicates the eDMA has completed the major loop. The eDMA engine - * sets it as the CITER count reaches zero; The software clears it, or the hardware - * when the channel is activated. This bit must be cleared to write the - * MAJORELINK or ESG bits. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_DONE (7U) /*!< Bit position for DMA_TCDn_CSR_DONE. */ -#define BM_DMA_TCDn_CSR_DONE (0x0080U) /*!< Bit mask for DMA_TCDn_CSR_DONE. */ -#define BS_DMA_TCDn_CSR_DONE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */ -#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */ -#define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE) - -/*! @brief Set the DONE field to a new value. */ -#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW) - * - * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is - * performed after the major loop counter is exhausted. else After the major loop - * counter is exhausted, the eDMA engine initiates a channel service request at the - * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */ -#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */ -#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */ -#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */ -#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH) - -/*! @brief Set the MAJORLINKCH field to a new value. */ -#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW) - * - * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as - * the eDMA processes the minor loop, it continuously generates read/write - * sequences until the minor count is exhausted. This field forces the eDMA to stall - * after the completion of each read/write access to control the bus request - * bandwidth seen by the crossbar switch. If the source and destination sizes are equal, - * this field is ignored between the first and second transfers and after the - * last write of each minor loop. This behavior is a side effect of reducing - * start-up latency. - * - * Values: - * - 00 - No eDMA engine stalls - * - 01 - Reserved - * - 10 - eDMA engine stalls for 4 cycles after each r/w - * - 11 - eDMA engine stalls for 8 cycles after each r/w - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_BWC (14U) /*!< Bit position for DMA_TCDn_CSR_BWC. */ -#define BM_DMA_TCDn_CSR_BWC (0xC000U) /*!< Bit mask for DMA_TCDn_CSR_BWC. */ -#define BS_DMA_TCDn_CSR_BWC (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */ -#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */ -#define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC) - -/*! @brief Set the BWC field to a new value. */ -#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v))) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW) - * - * Reset value: 0x0000U - * - * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined - * as follows. - */ -typedef union _hw_dma_tcdn_biter_elinkno -{ - uint16_t U; - struct _hw_dma_tcdn_biter_elinkno_bitfields - { - uint16_t BITER : 15; /*!< [14:0] Starting Major Iteration Count */ - uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on - * minor loop complete */ - } B; -} hw_dma_tcdn_biter_elinkno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register - */ -/*@{*/ -#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U) - -#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n))) - -#define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n)) -#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U) -#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v)) -#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields - */ - -/*! - * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW) - * - * As the transfer control descriptor is first loaded by software, this 9-bit - * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER - * field. As the major iteration count is exhausted, the contents of this field - * are reloaded into the CITER field. When the software loads the TCD, this field - * must be set equal to the corresponding CITER field; otherwise, a configuration - * error is reported. As the major iteration count is exhausted, the contents of - * this field is reloaded into the CITER field. If the channel is configured to - * execute a single service request, the initial values of BITER and CITER should - * be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */ -#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */ -#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */ -#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */ -#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER) - -/*! @brief Set the BITER field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables the linking to - * another channel, defined by BITER[LINKCH]. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking is disabled, the BITER value - * extends to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel - * linking. When the software loads the TCD, this field must be set equal to the - * corresponding CITER field; otherwise, a configuration error is reported. As the - * major iteration count is exhausted, the contents of this field is reloaded - * into the CITER field. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */ -#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */ -#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */ -#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */ -#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW) - * - * Reset value: 0x0000U - * - * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as - * follows. - */ -typedef union _hw_dma_tcdn_biter_elinkyes -{ - uint16_t U; - struct _hw_dma_tcdn_biter_elinkyes_bitfields - { - uint16_t BITER : 9; /*!< [8:0] Starting Major Iteration Count */ - uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */ - uint16_t RESERVED0 : 2; /*!< [14:13] */ - uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on - * minor loop complete */ - } B; -} hw_dma_tcdn_biter_elinkyes_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register - */ -/*@{*/ -#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U) - -#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n))) - -#define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n)) -#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U) -#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v)) -#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v))) -#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields - */ - -/*! - * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW) - * - * As the transfer control descriptor is first loaded by software, this 9-bit - * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER - * field. As the major iteration count is exhausted, the contents of this field - * are reloaded into the CITER field. When the software loads the TCD, this field - * must be set equal to the corresponding CITER field; otherwise, a configuration - * error is reported. As the major iteration count is exhausted, the contents of - * this field is reloaded into the CITER field. If the channel is configured to - * execute a single service request, the initial values of BITER and CITER should - * be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */ -#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */ -#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */ -#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */ -#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER) - -/*! @brief Set the BITER field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW) - * - * If channel-to-channel linking is enabled (ELINK = 1), then after the minor - * loop is exhausted, the eDMA engine initiates a channel service request at the - * channel defined by these four bits by setting that channel's TCDn_CSR[START] - * bit. When the software loads the TCD, this field must be set equal to the - * corresponding CITER field; otherwise, a configuration error is reported. As the major - * iteration count is exhausted, the contents of this field is reloaded into the - * CITER field. - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */ -#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH) - -/*! @brief Set the LINKCH field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables the linking to - * another channel, defined by BITER[LINKCH]. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking disables, the BITER value - * extends to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel - * linking. When the software loads the TCD, this field must be set equal to the - * corresponding CITER field; otherwise, a configuration error is reported. As the - * major iteration count is exhausted, the contents of this field is reloaded into - * the CITER field. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */ -#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */ -#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */ -#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */ -#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v)) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_dma_t - module struct - ******************************************************************************/ -/*! - * @brief All DMA module registers. - */ -#pragma pack(1) -typedef struct _hw_dma -{ - __IO hw_dma_cr_t CR; /*!< [0x0] Control Register */ - __I hw_dma_es_t ES; /*!< [0x4] Error Status Register */ - uint8_t _reserved0[4]; - __IO hw_dma_erq_t ERQ; /*!< [0xC] Enable Request Register */ - uint8_t _reserved1[4]; - __IO hw_dma_eei_t EEI; /*!< [0x14] Enable Error Interrupt Register */ - __O hw_dma_ceei_t CEEI; /*!< [0x18] Clear Enable Error Interrupt Register */ - __O hw_dma_seei_t SEEI; /*!< [0x19] Set Enable Error Interrupt Register */ - __O hw_dma_cerq_t CERQ; /*!< [0x1A] Clear Enable Request Register */ - __O hw_dma_serq_t SERQ; /*!< [0x1B] Set Enable Request Register */ - __O hw_dma_cdne_t CDNE; /*!< [0x1C] Clear DONE Status Bit Register */ - __O hw_dma_ssrt_t SSRT; /*!< [0x1D] Set START Bit Register */ - __O hw_dma_cerr_t CERR; /*!< [0x1E] Clear Error Register */ - __O hw_dma_cint_t CINT; /*!< [0x1F] Clear Interrupt Request Register */ - uint8_t _reserved2[4]; - __IO hw_dma_int_t INT; /*!< [0x24] Interrupt Request Register */ - uint8_t _reserved3[4]; - __IO hw_dma_err_t ERR; /*!< [0x2C] Error Register */ - uint8_t _reserved4[4]; - __I hw_dma_hrs_t HRS; /*!< [0x34] Hardware Request Status Register */ - uint8_t _reserved5[12]; - __IO hw_dma_ears_t EARS; /*!< [0x44] Enable Asynchronous Request in Stop Register */ - uint8_t _reserved6[184]; - __IO hw_dma_dchprin_t DCHPRIn[16]; /*!< [0x100] Channel n Priority Register */ - uint8_t _reserved7[3824]; - struct { - __IO hw_dma_tcdn_saddr_t TCDn_SADDR; /*!< [0x1000] TCD Source Address */ - __IO hw_dma_tcdn_soff_t TCDn_SOFF; /*!< [0x1004] TCD Signed Source Address Offset */ - __IO hw_dma_tcdn_attr_t TCDn_ATTR; /*!< [0x1006] TCD Transfer Attributes */ - union { - __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */ - __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ - __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ - }; - __IO hw_dma_tcdn_slast_t TCDn_SLAST; /*!< [0x100C] TCD Last Source Address Adjustment */ - __IO hw_dma_tcdn_daddr_t TCDn_DADDR; /*!< [0x1010] TCD Destination Address */ - __IO hw_dma_tcdn_doff_t TCDn_DOFF; /*!< [0x1014] TCD Signed Destination Address Offset */ - union { - __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ - __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ - }; - __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */ - __IO hw_dma_tcdn_csr_t TCDn_CSR; /*!< [0x101C] TCD Control and Status */ - union { - __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ - __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ - }; - } TCD[16]; -} hw_dma_t; -#pragma pack() - -/*! @brief Macro to access all DMA registers. */ -/*! @param x DMA module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_DMA(DMA_BASE). */ -#define HW_DMA(x) (*(hw_dma_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_DMA_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h deleted file mode 100644 index 90d577099ce..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h +++ /dev/null @@ -1,237 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_DMAMUX_REGISTERS_H__ -#define __HW_DMAMUX_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 DMAMUX - * - * DMA channel multiplexor - * - * Registers defined in this header file: - * - HW_DMAMUX_CHCFGn - Channel Configuration register - * - * - hw_dmamux_t - Struct containing all module registers. - */ - -#define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */ - -/******************************************************************************* - * HW_DMAMUX_CHCFGn - Channel Configuration register - ******************************************************************************/ - -/*! - * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW) - * - * Reset value: 0x00U - * - * Each of the DMA channels can be independently enabled/disabled and associated - * with one of the DMA slots (peripheral slots or always-on slots) in the - * system. Setting multiple CHCFG registers with the same source value will result in - * unpredictable behavior. Before changing the trigger or source settings, a DMA - * channel must be disabled via CHCFGn[ENBL]. - */ -typedef union _hw_dmamux_chcfgn -{ - uint8_t U; - struct _hw_dmamux_chcfgn_bitfields - { - uint8_t SOURCE : 6; /*!< [5:0] DMA Channel Source (Slot) */ - uint8_t TRIG : 1; /*!< [6] DMA Channel Trigger Enable */ - uint8_t ENBL : 1; /*!< [7] DMA Channel Enable */ - } B; -} hw_dmamux_chcfgn_t; - -/*! - * @name Constants and macros for entire DMAMUX_CHCFGn register - */ -/*@{*/ -#define HW_DMAMUX_CHCFGn_COUNT (16U) - -#define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n))) - -#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n)) -#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U) -#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v)) -#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v))) -#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v))) -#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMAMUX_CHCFGn bitfields - */ - -/*! - * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW) - * - * Specifies which DMA source, if any, is routed to a particular DMA channel. - * See your device's chip configuration details for information about the - * peripherals and their slot numbers. - */ -/*@{*/ -#define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */ -#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */ -#define BS_DMAMUX_CHCFGn_SOURCE (6U) /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */ - -/*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */ -#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE) - -/*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */ -#define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE) - -/*! @brief Set the SOURCE field to a new value. */ -#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v))) -/*@}*/ - -/*! - * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW) - * - * Enables the periodic trigger capability for the triggered DMA channel. - * - * Values: - * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the - * DMA Channel will simply route the specified source to the DMA channel. - * (Normal mode) - * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the - * DMAMUX is in Periodic Trigger mode. - */ -/*@{*/ -#define BP_DMAMUX_CHCFGn_TRIG (6U) /*!< Bit position for DMAMUX_CHCFGn_TRIG. */ -#define BM_DMAMUX_CHCFGn_TRIG (0x40U) /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */ -#define BS_DMAMUX_CHCFGn_TRIG (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */ - -/*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */ -#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG)) - -/*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */ -#define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG) - -/*! @brief Set the TRIG field to a new value. */ -#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v)) -/*@}*/ - -/*! - * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW) - * - * Enables the DMA channel. - * - * Values: - * - 0 - DMA channel is disabled. This mode is primarily used during - * configuration of the DMAMux. The DMA has separate channel enables/disables, which - * should be used to disable or reconfigure a DMA channel. - * - 1 - DMA channel is enabled - */ -/*@{*/ -#define BP_DMAMUX_CHCFGn_ENBL (7U) /*!< Bit position for DMAMUX_CHCFGn_ENBL. */ -#define BM_DMAMUX_CHCFGn_ENBL (0x80U) /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */ -#define BS_DMAMUX_CHCFGn_ENBL (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */ - -/*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */ -#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL)) - -/*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */ -#define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL) - -/*! @brief Set the ENBL field to a new value. */ -#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_dmamux_t - module struct - ******************************************************************************/ -/*! - * @brief All DMAMUX module registers. - */ -#pragma pack(1) -typedef struct _hw_dmamux -{ - __IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */ -} hw_dmamux_t; -#pragma pack() - -/*! @brief Macro to access all DMAMUX registers. */ -/*! @param x DMAMUX module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_DMAMUX(DMAMUX_BASE). */ -#define HW_DMAMUX(x) (*(hw_dmamux_t *)(x)) - -#endif /* __HW_DMAMUX_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h deleted file mode 100644 index 085a5d4cc99..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h +++ /dev/null @@ -1,504 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_EWM_REGISTERS_H__ -#define __HW_EWM_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 EWM - * - * External Watchdog Monitor - * - * Registers defined in this header file: - * - HW_EWM_CTRL - Control Register - * - HW_EWM_SERV - Service Register - * - HW_EWM_CMPL - Compare Low Register - * - HW_EWM_CMPH - Compare High Register - * - HW_EWM_CLKPRESCALER - Clock Prescaler Register - * - * - hw_ewm_t - Struct containing all module registers. - */ - -#define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */ - -/******************************************************************************* - * HW_EWM_CTRL - Control Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CTRL - Control Register (RW) - * - * Reset value: 0x00U - * - * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be - * written once after a CPU reset. Modifying these bits more than once, generates - * a bus transfer error. - */ -typedef union _hw_ewm_ctrl -{ - uint8_t U; - struct _hw_ewm_ctrl_bitfields - { - uint8_t EWMEN : 1; /*!< [0] EWM enable. */ - uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */ - uint8_t INEN : 1; /*!< [2] Input Enable. */ - uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_ewm_ctrl_t; - -/*! - * @name Constants and macros for entire EWM_CTRL register - */ -/*@{*/ -#define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U) - -#define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x)) -#define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U) -#define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v)) -#define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v))) -#define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v))) -#define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CTRL bitfields - */ - -/*! - * @name Register EWM_CTRL, field EWMEN[0] (RW) - * - * This bit when set, enables the EWM module. This resets the EWM counter to - * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and - * therefore it cannot be enabled until a reset occurs, due to the write-once - * nature of this bit. - */ -/*@{*/ -#define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */ -#define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */ -#define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */ - -/*! @brief Read current value of the EWM_CTRL_EWMEN field. */ -#define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN)) - -/*! @brief Format value for bitfield EWM_CTRL_EWMEN. */ -#define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN) - -/*! @brief Set the EWMEN field to a new value. */ -#define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v)) -/*@}*/ - -/*! - * @name Register EWM_CTRL, field ASSIN[1] (RW) - * - * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit - * inverts the assert state to a logic one. - */ -/*@{*/ -#define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */ -#define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */ -#define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */ - -/*! @brief Read current value of the EWM_CTRL_ASSIN field. */ -#define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN)) - -/*! @brief Format value for bitfield EWM_CTRL_ASSIN. */ -#define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN) - -/*! @brief Set the ASSIN field to a new value. */ -#define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v)) -/*@}*/ - -/*! - * @name Register EWM_CTRL, field INEN[2] (RW) - * - * This bit when set, enables the EWM_in port. - */ -/*@{*/ -#define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */ -#define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */ -#define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */ - -/*! @brief Read current value of the EWM_CTRL_INEN field. */ -#define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN)) - -/*! @brief Format value for bitfield EWM_CTRL_INEN. */ -#define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN) - -/*! @brief Set the INEN field to a new value. */ -#define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v)) -/*@}*/ - -/*! - * @name Register EWM_CTRL, field INTEN[3] (RW) - * - * This bit when set and EWM_out is asserted, an interrupt request is generated. - * To de-assert interrupt request, user should clear this bit by writing 0. - */ -/*@{*/ -#define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */ -#define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */ -#define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */ - -/*! @brief Read current value of the EWM_CTRL_INTEN field. */ -#define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN)) - -/*! @brief Format value for bitfield EWM_CTRL_INTEN. */ -#define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN) - -/*! @brief Set the INTEN field to a new value. */ -#define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_SERV - Service Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_SERV - Service Register (WORZ) - * - * Reset value: 0x00U - * - * The SERV register provides the interface from the CPU to the EWM module. It - * is write-only and reads of this register return zero. - */ -typedef union _hw_ewm_serv -{ - uint8_t U; - struct _hw_ewm_serv_bitfields - { - uint8_t SERVICE : 8; /*!< [7:0] */ - } B; -} hw_ewm_serv_t; - -/*! - * @name Constants and macros for entire EWM_SERV register - */ -/*@{*/ -#define HW_EWM_SERV_ADDR(x) ((x) + 0x1U) - -#define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x)) -#define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U) -#define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual EWM_SERV bitfields - */ - -/*! - * @name Register EWM_SERV, field SERVICE[7:0] (WORZ) - * - * The EWM service mechanism requires the CPU to write two values to the SERV - * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The - * EWM service is illegal if either of the following conditions is true. The - * first or second data byte is not written correctly. The second data byte is not - * written within a fixed number of peripheral bus cycles of the first data byte. - * This fixed number of cycles is called EWM_service_time. - */ -/*@{*/ -#define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */ -#define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */ -#define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */ - -/*! @brief Format value for bitfield EWM_SERV_SERVICE. */ -#define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE) - -/*! @brief Set the SERVICE field to a new value. */ -#define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_CMPL - Compare Low Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CMPL - Compare Low Register (RW) - * - * Reset value: 0x00U - * - * The CMPL register is reset to zero after a CPU reset. This provides no - * minimum time for the CPU to service the EWM counter. This register can be written - * only once after a CPU reset. Writing this register more than once generates a - * bus transfer error. - */ -typedef union _hw_ewm_cmpl -{ - uint8_t U; - struct _hw_ewm_cmpl_bitfields - { - uint8_t COMPAREL : 8; /*!< [7:0] */ - } B; -} hw_ewm_cmpl_t; - -/*! - * @name Constants and macros for entire EWM_CMPL register - */ -/*@{*/ -#define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U) - -#define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x)) -#define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U) -#define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v)) -#define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v))) -#define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v))) -#define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CMPL bitfields - */ - -/*! - * @name Register EWM_CMPL, field COMPAREL[7:0] (RW) - * - * To prevent runaway code from changing this field, software should write to - * this field after a CPU reset even if the (default) minimum service time is - * required. - */ -/*@{*/ -#define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */ -#define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */ -#define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */ - -/*! @brief Read current value of the EWM_CMPL_COMPAREL field. */ -#define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U) - -/*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */ -#define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL) - -/*! @brief Set the COMPAREL field to a new value. */ -#define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_CMPH - Compare High Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CMPH - Compare High Register (RW) - * - * Reset value: 0xFFU - * - * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum - * of 256 clocks time, for the CPU to service the EWM counter. This register can - * be written only once after a CPU reset. Writing this register more than once - * generates a bus transfer error. The valid values for CMPH are up to 0xFE - * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only - * if EWM counter is greater than CMPH. - */ -typedef union _hw_ewm_cmph -{ - uint8_t U; - struct _hw_ewm_cmph_bitfields - { - uint8_t COMPAREH : 8; /*!< [7:0] */ - } B; -} hw_ewm_cmph_t; - -/*! - * @name Constants and macros for entire EWM_CMPH register - */ -/*@{*/ -#define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U) - -#define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x)) -#define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U) -#define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v)) -#define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v))) -#define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v))) -#define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CMPH bitfields - */ - -/*! - * @name Register EWM_CMPH, field COMPAREH[7:0] (RW) - * - * To prevent runaway code from changing this field, software should write to - * this field after a CPU reset even if the (default) maximum service time is - * required. - */ -/*@{*/ -#define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */ -#define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */ -#define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */ - -/*! @brief Read current value of the EWM_CMPH_COMPAREH field. */ -#define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U) - -/*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */ -#define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH) - -/*! @brief Set the COMPAREH field to a new value. */ -#define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_CLKPRESCALER - Clock Prescaler Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CLKPRESCALER - Clock Prescaler Register (RW) - * - * Reset value: 0x00U - * - * This CLKPRESCALER register is reset to 0x00 after a CPU reset. This register - * can be written only once after a CPU reset. Writing this register more than - * once generates a bus transfer error. Write the required prescaler value before - * enabling the EWM. The implementation of this register is chip-specific. See the - * Chip Configuration details. - */ -typedef union _hw_ewm_clkprescaler -{ - uint8_t U; - struct _hw_ewm_clkprescaler_bitfields - { - uint8_t CLK_DIV : 8; /*!< [7:0] */ - } B; -} hw_ewm_clkprescaler_t; - -/*! - * @name Constants and macros for entire EWM_CLKPRESCALER register - */ -/*@{*/ -#define HW_EWM_CLKPRESCALER_ADDR(x) ((x) + 0x5U) - -#define HW_EWM_CLKPRESCALER(x) (*(__IO hw_ewm_clkprescaler_t *) HW_EWM_CLKPRESCALER_ADDR(x)) -#define HW_EWM_CLKPRESCALER_RD(x) (HW_EWM_CLKPRESCALER(x).U) -#define HW_EWM_CLKPRESCALER_WR(x, v) (HW_EWM_CLKPRESCALER(x).U = (v)) -#define HW_EWM_CLKPRESCALER_SET(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) | (v))) -#define HW_EWM_CLKPRESCALER_CLR(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) & ~(v))) -#define HW_EWM_CLKPRESCALER_TOG(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CLKPRESCALER bitfields - */ - -/*! - * @name Register EWM_CLKPRESCALER, field CLK_DIV[7:0] (RW) - * - * Selected low power source for running the EWM counter can be prescaled as - * below. Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK_DIV - * ) - */ -/*@{*/ -#define BP_EWM_CLKPRESCALER_CLK_DIV (0U) /*!< Bit position for EWM_CLKPRESCALER_CLK_DIV. */ -#define BM_EWM_CLKPRESCALER_CLK_DIV (0xFFU) /*!< Bit mask for EWM_CLKPRESCALER_CLK_DIV. */ -#define BS_EWM_CLKPRESCALER_CLK_DIV (8U) /*!< Bit field size in bits for EWM_CLKPRESCALER_CLK_DIV. */ - -/*! @brief Read current value of the EWM_CLKPRESCALER_CLK_DIV field. */ -#define BR_EWM_CLKPRESCALER_CLK_DIV(x) (HW_EWM_CLKPRESCALER(x).U) - -/*! @brief Format value for bitfield EWM_CLKPRESCALER_CLK_DIV. */ -#define BF_EWM_CLKPRESCALER_CLK_DIV(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CLKPRESCALER_CLK_DIV) & BM_EWM_CLKPRESCALER_CLK_DIV) - -/*! @brief Set the CLK_DIV field to a new value. */ -#define BW_EWM_CLKPRESCALER_CLK_DIV(x, v) (HW_EWM_CLKPRESCALER_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_ewm_t - module struct - ******************************************************************************/ -/*! - * @brief All EWM module registers. - */ -#pragma pack(1) -typedef struct _hw_ewm -{ - __IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */ - __O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */ - __IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */ - __IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */ - uint8_t _reserved0[1]; - __IO hw_ewm_clkprescaler_t CLKPRESCALER; /*!< [0x5] Clock Prescaler Register */ -} hw_ewm_t; -#pragma pack() - -/*! @brief Macro to access all EWM registers. */ -/*! @param x EWM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_EWM(EWM_BASE). */ -#define HW_EWM(x) (*(hw_ewm_t *)(x)) - -#endif /* __HW_EWM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h deleted file mode 100644 index c079b4f2377..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h +++ /dev/null @@ -1,904 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FB_REGISTERS_H__ -#define __HW_FB_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 FB - * - * FlexBus external bus interface - * - * Registers defined in this header file: - * - HW_FB_CSARn - Chip Select Address Register - * - HW_FB_CSMRn - Chip Select Mask Register - * - HW_FB_CSCRn - Chip Select Control Register - * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register - * - * - hw_fb_t - Struct containing all module registers. - */ - -#define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */ - -/******************************************************************************* - * HW_FB_CSARn - Chip Select Address Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSARn - Chip Select Address Register (RW) - * - * Reset value: 0x00000000U - * - * Specifies the associated chip-select's base address. - */ -typedef union _hw_fb_csarn -{ - uint32_t U; - struct _hw_fb_csarn_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t BA : 16; /*!< [31:16] Base Address */ - } B; -} hw_fb_csarn_t; - -/*! - * @name Constants and macros for entire FB_CSARn register - */ -/*@{*/ -#define HW_FB_CSARn_COUNT (6U) - -#define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n))) - -#define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n)) -#define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U) -#define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v)) -#define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v))) -#define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v))) -#define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSARn bitfields - */ - -/*! - * @name Register FB_CSARn, field BA[31:16] (RW) - * - * Defines the base address for memory dedicated to the associated chip-select. - * BA is compared to bits 31-16 on the internal address bus to determine if the - * associated chip-select's memory is being accessed. Because the FlexBus module - * is one of the slaves connected to the crossbar switch, it is only accessible - * within a certain memory range. See the chip memory map for the applicable - * FlexBus "expansion" address range for which the chip-selects can be active. Set the - * CSARn and CSMRn registers appropriately before accessing this region. - */ -/*@{*/ -#define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */ -#define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */ -#define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */ - -/*! @brief Read current value of the FB_CSARn_BA field. */ -#define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA) - -/*! @brief Format value for bitfield FB_CSARn_BA. */ -#define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA) - -/*! @brief Set the BA field to a new value. */ -#define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v))) -/*@}*/ -/******************************************************************************* - * HW_FB_CSMRn - Chip Select Mask Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSMRn - Chip Select Mask Register (RW) - * - * Reset value: 0x00000000U - * - * Specifies the address mask and allowable access types for the associated - * chip-select. - */ -typedef union _hw_fb_csmrn -{ - uint32_t U; - struct _hw_fb_csmrn_bitfields - { - uint32_t V : 1; /*!< [0] Valid */ - uint32_t RESERVED0 : 7; /*!< [7:1] */ - uint32_t WP : 1; /*!< [8] Write Protect */ - uint32_t RESERVED1 : 7; /*!< [15:9] */ - uint32_t BAM : 16; /*!< [31:16] Base Address Mask */ - } B; -} hw_fb_csmrn_t; - -/*! - * @name Constants and macros for entire FB_CSMRn register - */ -/*@{*/ -#define HW_FB_CSMRn_COUNT (6U) - -#define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n))) - -#define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n)) -#define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U) -#define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v)) -#define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v))) -#define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v))) -#define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSMRn bitfields - */ - -/*! - * @name Register FB_CSMRn, field V[0] (RW) - * - * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. - * Programmed chip-selects do not assert until the V bit is 1b (except for - * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any - * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip - * select initialization sequence to allow other chip selects to function as - * programmed. - * - * Values: - * - 0 - Chip-select is invalid. - * - 1 - Chip-select is valid. - */ -/*@{*/ -#define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */ -#define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */ -#define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */ - -/*! @brief Read current value of the FB_CSMRn_V field. */ -#define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V)) - -/*! @brief Format value for bitfield FB_CSMRn_V. */ -#define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V) - -/*! @brief Set the V field to a new value. */ -#define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSMRn, field WP[8] (RW) - * - * Controls write accesses to the address range in the corresponding CSAR. - * - * Values: - * - 0 - Write accesses are allowed. - * - 1 - Write accesses are not allowed. Attempting to write to the range of - * addresses for which the WP bit is set results in a bus error termination of - * the internal cycle and no external cycle. - */ -/*@{*/ -#define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */ -#define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */ -#define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */ - -/*! @brief Read current value of the FB_CSMRn_WP field. */ -#define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP)) - -/*! @brief Format value for bitfield FB_CSMRn_WP. */ -#define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP) - -/*! @brief Set the WP field to a new value. */ -#define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSMRn, field BAM[31:16] (RW) - * - * Defines the associated chip-select's block size by masking address bits. - * - * Values: - * - 0 - The corresponding address bit in CSAR is used in the chip-select decode. - * - 1 - The corresponding address bit in CSAR is a don't care in the - * chip-select decode. - */ -/*@{*/ -#define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */ -#define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */ -#define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */ - -/*! @brief Read current value of the FB_CSMRn_BAM field. */ -#define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM) - -/*! @brief Format value for bitfield FB_CSMRn_BAM. */ -#define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM) - -/*! @brief Set the BAM field to a new value. */ -#define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v))) -/*@}*/ -/******************************************************************************* - * HW_FB_CSCRn - Chip Select Control Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSCRn - Chip Select Control Register (RW) - * - * Reset value: 0x003FFC00U - * - * Controls the auto-acknowledge, address setup and hold times, port size, burst - * capability, and number of wait states for the associated chip select. To - * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the - * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3 - * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your - * particular chip for information on the exact CSCR0 reset value. - */ -typedef union _hw_fb_cscrn -{ - uint32_t U; - struct _hw_fb_cscrn_bitfields - { - uint32_t RESERVED0 : 3; /*!< [2:0] */ - uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */ - uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */ - uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */ - uint32_t PS : 2; /*!< [7:6] Port Size */ - uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */ - uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */ - uint32_t WS : 6; /*!< [15:10] Wait States */ - uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */ - uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */ - uint32_t ASET : 2; /*!< [21:20] Address Setup */ - uint32_t EXTS : 1; /*!< [22] */ - uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */ - uint32_t RESERVED1 : 2; /*!< [25:24] */ - uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */ - } B; -} hw_fb_cscrn_t; - -/*! - * @name Constants and macros for entire FB_CSCRn register - */ -/*@{*/ -#define HW_FB_CSCRn_COUNT (6U) - -#define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n))) - -#define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n)) -#define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U) -#define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v)) -#define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v))) -#define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v))) -#define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSCRn bitfields - */ - -/*! - * @name Register FB_CSCRn, field BSTW[3] (RW) - * - * Specifies whether burst writes are enabled for memory associated with each - * chip select. - * - * Values: - * - 0 - Disabled. Data exceeding the specified port size is broken into - * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit - * port takes four byte writes. - * - 1 - Enabled. Enables burst write of data larger than the specified port - * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit - * ports, and line writes to 8-, 16-, and 32-bit ports. - */ -/*@{*/ -#define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */ -#define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */ -#define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */ - -/*! @brief Read current value of the FB_CSCRn_BSTW field. */ -#define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW)) - -/*! @brief Format value for bitfield FB_CSCRn_BSTW. */ -#define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW) - -/*! @brief Set the BSTW field to a new value. */ -#define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field BSTR[4] (RW) - * - * Specifies whether burst reads are enabled for memory associated with each - * chip select. - * - * Values: - * - 0 - Disabled. Data exceeding the specified port size is broken into - * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit - * port is broken into four 8-bit reads. - * - 1 - Enabled. Enables data burst reads larger than the specified port size, - * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit - * ports, and line reads from 8-, 16-, and 32-bit ports. - */ -/*@{*/ -#define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */ -#define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */ -#define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */ - -/*! @brief Read current value of the FB_CSCRn_BSTR field. */ -#define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR)) - -/*! @brief Format value for bitfield FB_CSCRn_BSTR. */ -#define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR) - -/*! @brief Set the BSTR field to a new value. */ -#define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field BEM[5] (RW) - * - * Specifies whether the corresponding FB_BE is asserted for read accesses. - * Certain memories have byte enables that must be asserted during reads and writes. - * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode - * of byte enable support for these SRAMs. - * - * Values: - * - 0 - FB_BE is asserted for data write only. - * - 1 - FB_BE is asserted for data read and write accesses. - */ -/*@{*/ -#define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */ -#define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */ -#define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */ - -/*! @brief Read current value of the FB_CSCRn_BEM field. */ -#define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM)) - -/*! @brief Format value for bitfield FB_CSCRn_BEM. */ -#define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM) - -/*! @brief Set the BEM field to a new value. */ -#define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field PS[7:6] (RW) - * - * Specifies the data port width of the associated chip-select, and determines - * where data is driven during write cycles and where data is sampled during read - * cycles. - * - * Values: - * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. - * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when - * BLS is 0b, or FB_D[7:0] when BLS is 1b. - */ -/*@{*/ -#define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */ -#define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */ -#define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */ - -/*! @brief Read current value of the FB_CSCRn_PS field. */ -#define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS) - -/*! @brief Format value for bitfield FB_CSCRn_PS. */ -#define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS) - -/*! @brief Set the PS field to a new value. */ -#define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field AA[8] (RW) - * - * Asserts the internal transfer acknowledge for accesses specified by the - * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system - * asserts an external FB_TA before the wait-state countdown asserts the - * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus - * between each internal termination. This field must be 1b if CSPMCR disables FB_TA. - * - * Values: - * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is - * terminated externally. - * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS. - */ -/*@{*/ -#define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */ -#define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */ -#define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */ - -/*! @brief Read current value of the FB_CSCRn_AA field. */ -#define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA)) - -/*! @brief Format value for bitfield FB_CSCRn_AA. */ -#define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA) - -/*! @brief Set the AA field to a new value. */ -#define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field BLS[9] (RW) - * - * Specifies if data on FB_AD appears left-aligned or right-aligned during the - * data phase of a FlexBus access. - * - * Values: - * - 0 - Not shifted. Data is left-aligned on FB_AD. - * - 1 - Shifted. Data is right-aligned on FB_AD. - */ -/*@{*/ -#define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */ -#define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */ -#define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */ - -/*! @brief Read current value of the FB_CSCRn_BLS field. */ -#define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS)) - -/*! @brief Format value for bitfield FB_CSCRn_BLS. */ -#define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS) - -/*! @brief Set the BLS field to a new value. */ -#define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field WS[15:10] (RW) - * - * Specifies the number of wait states inserted after FlexBus asserts the - * associated chip-select and before an internal transfer acknowledge is generated (WS - * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states). - */ -/*@{*/ -#define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */ -#define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */ -#define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */ - -/*! @brief Read current value of the FB_CSCRn_WS field. */ -#define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS) - -/*! @brief Format value for bitfield FB_CSCRn_WS. */ -#define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS) - -/*! @brief Set the WS field to a new value. */ -#define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field WRAH[17:16] (RW) - * - * Controls the address, data, and attribute hold time after the termination of - * a write cycle that hits in the associated chip-select's address space. The - * hold time applies only at the end of a transfer. Therefore, during a burst - * transfer or a transfer to a port size smaller than the transfer size, the hold time - * is only added after the last bus cycle. - * - * Values: - * - 00 - 1 cycle (default for all but FB_CS0 ) - * - 01 - 2 cycles - * - 10 - 3 cycles - * - 11 - 4 cycles (default for FB_CS0 ) - */ -/*@{*/ -#define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */ -#define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */ -#define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */ - -/*! @brief Read current value of the FB_CSCRn_WRAH field. */ -#define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH) - -/*! @brief Format value for bitfield FB_CSCRn_WRAH. */ -#define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH) - -/*! @brief Set the WRAH field to a new value. */ -#define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field RDAH[19:18] (RW) - * - * Controls the address and attribute hold time after the termination during a - * read cycle that hits in the associated chip-select's address space. The hold - * time applies only at the end of a transfer. Therefore, during a burst transfer - * or a transfer to a port size smaller than the transfer size, the hold time is - * only added after the last bus cycle. The number of cycles the address and - * attributes are held after FB_CSn deassertion depends on the value of the AA bit. - * - * Values: - * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. - * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. - * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. - * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. - */ -/*@{*/ -#define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */ -#define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */ -#define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */ - -/*! @brief Read current value of the FB_CSCRn_RDAH field. */ -#define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH) - -/*! @brief Format value for bitfield FB_CSCRn_RDAH. */ -#define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH) - -/*! @brief Set the RDAH field to a new value. */ -#define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field ASET[21:20] (RW) - * - * Controls when the chip-select is asserted with respect to assertion of a - * valid address and attributes. - * - * Values: - * - 00 - Assert FB_CSn on the first rising clock edge after the address is - * asserted (default for all but FB_CS0 ). - * - 01 - Assert FB_CSn on the second rising clock edge after the address is - * asserted. - * - 10 - Assert FB_CSn on the third rising clock edge after the address is - * asserted. - * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is - * asserted (default for FB_CS0 ). - */ -/*@{*/ -#define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */ -#define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */ -#define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */ - -/*! @brief Read current value of the FB_CSCRn_ASET field. */ -#define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET) - -/*! @brief Format value for bitfield FB_CSCRn_ASET. */ -#define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET) - -/*! @brief Set the ASET field to a new value. */ -#define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field EXTS[22] (RW) - * - * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS - * /FB_ALE is asserted. - * - * Values: - * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. - * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock - * edge after FB_CSn asserts. - */ -/*@{*/ -#define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */ -#define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */ -#define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */ - -/*! @brief Read current value of the FB_CSCRn_EXTS field. */ -#define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS)) - -/*! @brief Format value for bitfield FB_CSCRn_EXTS. */ -#define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS) - -/*! @brief Set the EXTS field to a new value. */ -#define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field SWSEN[23] (RW) - * - * Values: - * - 0 - Disabled. A number of wait states (specified by WS) are inserted before - * an internal transfer acknowledge is generated for all transfers. - * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before - * an internal transfer acknowledge is generated for burst transfer - * secondary terminations. - */ -/*@{*/ -#define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */ -#define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */ -#define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */ - -/*! @brief Read current value of the FB_CSCRn_SWSEN field. */ -#define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN)) - -/*! @brief Format value for bitfield FB_CSCRn_SWSEN. */ -#define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN) - -/*! @brief Set the SWSEN field to a new value. */ -#define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field SWS[31:26] (RW) - * - * Used only when the SWSEN bit is 1b. Specifies the number of wait states - * inserted before an internal transfer acknowledge is generated for a burst transfer - * (except for the first termination, which is controlled by WS). - */ -/*@{*/ -#define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */ -#define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */ -#define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */ - -/*! @brief Read current value of the FB_CSCRn_SWS field. */ -#define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS) - -/*! @brief Format value for bitfield FB_CSCRn_SWS. */ -#define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS) - -/*! @brief Set the SWS field to a new value. */ -#define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v))) -/*@}*/ - -/******************************************************************************* - * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW) - * - * Reset value: 0x00000000U - * - * Controls the multiplexing of the FlexBus signals. A bus error occurs when you - * do any of the following: Write to a reserved address Write to a reserved - * field in this register, or Access this register using a size other than 32 bits. - */ -typedef union _hw_fb_cspmcr -{ - uint32_t U; - struct _hw_fb_cspmcr_bitfields - { - uint32_t RESERVED0 : 12; /*!< [11:0] */ - uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex - * control */ - uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex - * control */ - uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex - * control */ - uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex - * control */ - uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex - * control */ - } B; -} hw_fb_cspmcr_t; - -/*! - * @name Constants and macros for entire FB_CSPMCR register - */ -/*@{*/ -#define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U) - -#define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x)) -#define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U) -#define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v)) -#define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v))) -#define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v))) -#define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSPMCR bitfields - */ - -/*! - * @name Register FB_CSPMCR, field GROUP5[15:12] (RW) - * - * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When - * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the - * bus hangs during a transfer. - * - * Values: - * - 0000 - FB_TA - * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA]. - * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA]. - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */ -#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */ -#define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */ -#define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */ -#define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5) - -/*! @brief Set the GROUP5 field to a new value. */ -#define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP4[19:16] (RW) - * - * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals. - * - * Values: - * - 0000 - FB_TBST - * - 0001 - FB_CS2 - * - 0010 - FB_BE_15_8 - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */ -#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */ -#define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */ -#define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */ -#define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4) - -/*! @brief Set the GROUP4 field to a new value. */ -#define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP3[23:20] (RW) - * - * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals. - * - * Values: - * - 0000 - FB_CS5 - * - 0001 - FB_TSIZ1 - * - 0010 - FB_BE_23_16 - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */ -#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */ -#define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */ -#define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */ -#define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3) - -/*! @brief Set the GROUP3 field to a new value. */ -#define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP2[27:24] (RW) - * - * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals. - * - * Values: - * - 0000 - FB_CS4 - * - 0001 - FB_TSIZ0 - * - 0010 - FB_BE_31_24 - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */ -#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */ -#define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */ -#define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */ -#define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2) - -/*! @brief Set the GROUP2 field to a new value. */ -#define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP1[31:28] (RW) - * - * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals. - * - * Values: - * - 0000 - FB_ALE - * - 0001 - FB_CS1 - * - 0010 - FB_TS - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */ -#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */ -#define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */ -#define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */ -#define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1) - -/*! @brief Set the GROUP1 field to a new value. */ -#define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v))) -/*@}*/ - -/******************************************************************************* - * hw_fb_t - module struct - ******************************************************************************/ -/*! - * @brief All FB module registers. - */ -#pragma pack(1) -typedef struct _hw_fb -{ - struct { - __IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */ - __IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */ - __IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */ - } CS[6]; - uint8_t _reserved0[24]; - __IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */ -} hw_fb_t; -#pragma pack() - -/*! @brief Macro to access all FB registers. */ -/*! @param x FB module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FB(FB_BASE). */ -#define HW_FB(x) (*(hw_fb_t *)(x)) - -#endif /* __HW_FB_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h deleted file mode 100644 index b18bbf2be4c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h +++ /dev/null @@ -1,1979 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FMC_REGISTERS_H__ -#define __HW_FMC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 FMC - * - * Flash Memory Controller - * - * Registers defined in this header file: - * - HW_FMC_PFAPR - Flash Access Protection Register - * - HW_FMC_PFB0CR - Flash Bank 0 Control Register - * - HW_FMC_PFB1CR - Flash Bank 1 Control Register - * - HW_FMC_TAGVDW0Sn - Cache Tag Storage - * - HW_FMC_TAGVDW1Sn - Cache Tag Storage - * - HW_FMC_TAGVDW2Sn - Cache Tag Storage - * - HW_FMC_TAGVDW3Sn - Cache Tag Storage - * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word) - * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word) - * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word) - * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word) - * - * - hw_fmc_t - Struct containing all module registers. - */ - -#define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */ - -/******************************************************************************* - * HW_FMC_PFAPR - Flash Access Protection Register - ******************************************************************************/ - -/*! - * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW) - * - * Reset value: 0x00F8003FU - */ -typedef union _hw_fmc_pfapr -{ - uint32_t U; - struct _hw_fmc_pfapr_bitfields - { - uint32_t M0AP : 2; /*!< [1:0] Master 0 Access Protection */ - uint32_t M1AP : 2; /*!< [3:2] Master 1 Access Protection */ - uint32_t M2AP : 2; /*!< [5:4] Master 2 Access Protection */ - uint32_t M3AP : 2; /*!< [7:6] Master 3 Access Protection */ - uint32_t M4AP : 2; /*!< [9:8] Master 4 Access Protection */ - uint32_t M5AP : 2; /*!< [11:10] Master 5 Access Protection */ - uint32_t M6AP : 2; /*!< [13:12] Master 6 Access Protection */ - uint32_t M7AP : 2; /*!< [15:14] Master 7 Access Protection */ - uint32_t M0PFD : 1; /*!< [16] Master 0 Prefetch Disable */ - uint32_t M1PFD : 1; /*!< [17] Master 1 Prefetch Disable */ - uint32_t M2PFD : 1; /*!< [18] Master 2 Prefetch Disable */ - uint32_t M3PFD : 1; /*!< [19] Master 3 Prefetch Disable */ - uint32_t M4PFD : 1; /*!< [20] Master 4 Prefetch Disable */ - uint32_t M5PFD : 1; /*!< [21] Master 5 Prefetch Disable */ - uint32_t M6PFD : 1; /*!< [22] Master 6 Prefetch Disable */ - uint32_t M7PFD : 1; /*!< [23] Master 7 Prefetch Disable */ - uint32_t RESERVED0 : 8; /*!< [31:24] */ - } B; -} hw_fmc_pfapr_t; - -/*! - * @name Constants and macros for entire FMC_PFAPR register - */ -/*@{*/ -#define HW_FMC_PFAPR_ADDR(x) ((x) + 0x0U) - -#define HW_FMC_PFAPR(x) (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x)) -#define HW_FMC_PFAPR_RD(x) (HW_FMC_PFAPR(x).U) -#define HW_FMC_PFAPR_WR(x, v) (HW_FMC_PFAPR(x).U = (v)) -#define HW_FMC_PFAPR_SET(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) | (v))) -#define HW_FMC_PFAPR_CLR(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v))) -#define HW_FMC_PFAPR_TOG(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_PFAPR bitfields - */ - -/*! - * @name Register FMC_PFAPR, field M0AP[1:0] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M0AP (0U) /*!< Bit position for FMC_PFAPR_M0AP. */ -#define BM_FMC_PFAPR_M0AP (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */ -#define BS_FMC_PFAPR_M0AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M0AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M0AP field. */ -#define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M0AP. */ -#define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP) - -/*! @brief Set the M0AP field to a new value. */ -#define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M1AP[3:2] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M1AP (2U) /*!< Bit position for FMC_PFAPR_M1AP. */ -#define BM_FMC_PFAPR_M1AP (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */ -#define BS_FMC_PFAPR_M1AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M1AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M1AP field. */ -#define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M1AP. */ -#define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP) - -/*! @brief Set the M1AP field to a new value. */ -#define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M2AP[5:4] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M2AP (4U) /*!< Bit position for FMC_PFAPR_M2AP. */ -#define BM_FMC_PFAPR_M2AP (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */ -#define BS_FMC_PFAPR_M2AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M2AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M2AP field. */ -#define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M2AP. */ -#define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP) - -/*! @brief Set the M2AP field to a new value. */ -#define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M3AP[7:6] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M3AP (6U) /*!< Bit position for FMC_PFAPR_M3AP. */ -#define BM_FMC_PFAPR_M3AP (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */ -#define BS_FMC_PFAPR_M3AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M3AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M3AP field. */ -#define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M3AP. */ -#define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP) - -/*! @brief Set the M3AP field to a new value. */ -#define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M4AP[9:8] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M4AP (8U) /*!< Bit position for FMC_PFAPR_M4AP. */ -#define BM_FMC_PFAPR_M4AP (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */ -#define BS_FMC_PFAPR_M4AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M4AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M4AP field. */ -#define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M4AP. */ -#define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP) - -/*! @brief Set the M4AP field to a new value. */ -#define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M5AP[11:10] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M5AP (10U) /*!< Bit position for FMC_PFAPR_M5AP. */ -#define BM_FMC_PFAPR_M5AP (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */ -#define BS_FMC_PFAPR_M5AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M5AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M5AP field. */ -#define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M5AP. */ -#define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP) - -/*! @brief Set the M5AP field to a new value. */ -#define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M6AP[13:12] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M6AP (12U) /*!< Bit position for FMC_PFAPR_M6AP. */ -#define BM_FMC_PFAPR_M6AP (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */ -#define BS_FMC_PFAPR_M6AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M6AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M6AP field. */ -#define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M6AP. */ -#define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP) - -/*! @brief Set the M6AP field to a new value. */ -#define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M7AP[15:14] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master. - * - 01 - Only read accesses may be performed by this master. - * - 10 - Only write accesses may be performed by this master. - * - 11 - Both read and write accesses may be performed by this master. - */ -/*@{*/ -#define BP_FMC_PFAPR_M7AP (14U) /*!< Bit position for FMC_PFAPR_M7AP. */ -#define BM_FMC_PFAPR_M7AP (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */ -#define BS_FMC_PFAPR_M7AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M7AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M7AP field. */ -#define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M7AP. */ -#define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP) - -/*! @brief Set the M7AP field to a new value. */ -#define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M0PFD[16] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M0PFD (16U) /*!< Bit position for FMC_PFAPR_M0PFD. */ -#define BM_FMC_PFAPR_M0PFD (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */ -#define BS_FMC_PFAPR_M0PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */ -#define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */ -#define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD) - -/*! @brief Set the M0PFD field to a new value. */ -#define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M1PFD[17] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M1PFD (17U) /*!< Bit position for FMC_PFAPR_M1PFD. */ -#define BM_FMC_PFAPR_M1PFD (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */ -#define BS_FMC_PFAPR_M1PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */ -#define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */ -#define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD) - -/*! @brief Set the M1PFD field to a new value. */ -#define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M2PFD[18] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M2PFD (18U) /*!< Bit position for FMC_PFAPR_M2PFD. */ -#define BM_FMC_PFAPR_M2PFD (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */ -#define BS_FMC_PFAPR_M2PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */ -#define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */ -#define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD) - -/*! @brief Set the M2PFD field to a new value. */ -#define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M3PFD[19] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M3PFD (19U) /*!< Bit position for FMC_PFAPR_M3PFD. */ -#define BM_FMC_PFAPR_M3PFD (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */ -#define BS_FMC_PFAPR_M3PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */ -#define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */ -#define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD) - -/*! @brief Set the M3PFD field to a new value. */ -#define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M4PFD[20] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M4PFD (20U) /*!< Bit position for FMC_PFAPR_M4PFD. */ -#define BM_FMC_PFAPR_M4PFD (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */ -#define BS_FMC_PFAPR_M4PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */ -#define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */ -#define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD) - -/*! @brief Set the M4PFD field to a new value. */ -#define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M5PFD[21] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M5PFD (21U) /*!< Bit position for FMC_PFAPR_M5PFD. */ -#define BM_FMC_PFAPR_M5PFD (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */ -#define BS_FMC_PFAPR_M5PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */ -#define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */ -#define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD) - -/*! @brief Set the M5PFD field to a new value. */ -#define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M6PFD[22] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M6PFD (22U) /*!< Bit position for FMC_PFAPR_M6PFD. */ -#define BM_FMC_PFAPR_M6PFD (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */ -#define BS_FMC_PFAPR_M6PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */ -#define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */ -#define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD) - -/*! @brief Set the M6PFD field to a new value. */ -#define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M7PFD[23] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M7PFD (23U) /*!< Bit position for FMC_PFAPR_M7PFD. */ -#define BM_FMC_PFAPR_M7PFD (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */ -#define BS_FMC_PFAPR_M7PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */ -#define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */ -#define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD) - -/*! @brief Set the M7PFD field to a new value. */ -#define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_PFB0CR - Flash Bank 0 Control Register - ******************************************************************************/ - -/*! - * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW) - * - * Reset value: 0x3002001FU - */ -typedef union _hw_fmc_pfb0cr -{ - uint32_t U; - struct _hw_fmc_pfb0cr_bitfields - { - uint32_t B0SEBE : 1; /*!< [0] Bank 0 Single Entry Buffer Enable */ - uint32_t B0IPE : 1; /*!< [1] Bank 0 Instruction Prefetch Enable */ - uint32_t B0DPE : 1; /*!< [2] Bank 0 Data Prefetch Enable */ - uint32_t B0ICE : 1; /*!< [3] Bank 0 Instruction Cache Enable */ - uint32_t B0DCE : 1; /*!< [4] Bank 0 Data Cache Enable */ - uint32_t CRC : 3; /*!< [7:5] Cache Replacement Control */ - uint32_t RESERVED0 : 9; /*!< [16:8] */ - uint32_t B0MW : 2; /*!< [18:17] Bank 0 Memory Width */ - uint32_t S_B_INV : 1; /*!< [19] Invalidate Prefetch Speculation - * Buffer */ - uint32_t CINV_WAY : 4; /*!< [23:20] Cache Invalidate Way x */ - uint32_t CLCK_WAY : 4; /*!< [27:24] Cache Lock Way x */ - uint32_t B0RWSC : 4; /*!< [31:28] Bank 0 Read Wait State Control */ - } B; -} hw_fmc_pfb0cr_t; - -/*! - * @name Constants and macros for entire FMC_PFB0CR register - */ -/*@{*/ -#define HW_FMC_PFB0CR_ADDR(x) ((x) + 0x4U) - -#define HW_FMC_PFB0CR(x) (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x)) -#define HW_FMC_PFB0CR_RD(x) (HW_FMC_PFB0CR(x).U) -#define HW_FMC_PFB0CR_WR(x, v) (HW_FMC_PFB0CR(x).U = (v)) -#define HW_FMC_PFB0CR_SET(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) | (v))) -#define HW_FMC_PFB0CR_CLR(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v))) -#define HW_FMC_PFB0CR_TOG(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_PFB0CR bitfields - */ - -/*! - * @name Register FMC_PFB0CR, field B0SEBE[0] (RW) - * - * This bit controls whether the single entry page buffer is enabled in response - * to flash read accesses. Its operation is independent from bank 1's cache. A - * high-to-low transition of this enable forces the page buffer to be invalidated. - * - * Values: - * - 0 - Single entry buffer is disabled. - * - 1 - Single entry buffer is enabled. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0SEBE (0U) /*!< Bit position for FMC_PFB0CR_B0SEBE. */ -#define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */ -#define BS_FMC_PFB0CR_B0SEBE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */ -#define BR_FMC_PFB0CR_B0SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */ -#define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE) - -/*! @brief Set the B0SEBE field to a new value. */ -#define BW_FMC_PFB0CR_B0SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0IPE[1] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to instruction fetches. - * - * Values: - * - 0 - Do not prefetch in response to instruction fetches. - * - 1 - Enable prefetches in response to instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0IPE (1U) /*!< Bit position for FMC_PFB0CR_B0IPE. */ -#define BM_FMC_PFB0CR_B0IPE (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */ -#define BS_FMC_PFB0CR_B0IPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */ -#define BR_FMC_PFB0CR_B0IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */ -#define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE) - -/*! @brief Set the B0IPE field to a new value. */ -#define BW_FMC_PFB0CR_B0IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0DPE[2] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to data references. - * - * Values: - * - 0 - Do not prefetch in response to data references. - * - 1 - Enable prefetches in response to data references. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0DPE (2U) /*!< Bit position for FMC_PFB0CR_B0DPE. */ -#define BM_FMC_PFB0CR_B0DPE (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */ -#define BS_FMC_PFB0CR_B0DPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */ -#define BR_FMC_PFB0CR_B0DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */ -#define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE) - -/*! @brief Set the B0DPE field to a new value. */ -#define BW_FMC_PFB0CR_B0DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0ICE[3] (RW) - * - * This bit controls whether instruction fetches are loaded into the cache. - * - * Values: - * - 0 - Do not cache instruction fetches. - * - 1 - Cache instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0ICE (3U) /*!< Bit position for FMC_PFB0CR_B0ICE. */ -#define BM_FMC_PFB0CR_B0ICE (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */ -#define BS_FMC_PFB0CR_B0ICE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */ -#define BR_FMC_PFB0CR_B0ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */ -#define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE) - -/*! @brief Set the B0ICE field to a new value. */ -#define BW_FMC_PFB0CR_B0ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0DCE[4] (RW) - * - * This bit controls whether data references are loaded into the cache. - * - * Values: - * - 0 - Do not cache data references. - * - 1 - Cache data references. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0DCE (4U) /*!< Bit position for FMC_PFB0CR_B0DCE. */ -#define BM_FMC_PFB0CR_B0DCE (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */ -#define BS_FMC_PFB0CR_B0DCE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */ -#define BR_FMC_PFB0CR_B0DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */ -#define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE) - -/*! @brief Set the B0DCE field to a new value. */ -#define BW_FMC_PFB0CR_B0DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field CRC[7:5] (RW) - * - * This 3-bit field defines the replacement algorithm for accesses that are - * cached. - * - * Values: - * - 000 - LRU replacement algorithm per set across all four ways - * - 001 - Reserved - * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data - * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data - * - 1xx - Reserved - */ -/*@{*/ -#define BP_FMC_PFB0CR_CRC (5U) /*!< Bit position for FMC_PFB0CR_CRC. */ -#define BM_FMC_PFB0CR_CRC (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */ -#define BS_FMC_PFB0CR_CRC (3U) /*!< Bit field size in bits for FMC_PFB0CR_CRC. */ - -/*! @brief Read current value of the FMC_PFB0CR_CRC field. */ -#define BR_FMC_PFB0CR_CRC(x) (HW_FMC_PFB0CR(x).B.CRC) - -/*! @brief Format value for bitfield FMC_PFB0CR_CRC. */ -#define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC) - -/*! @brief Set the CRC field to a new value. */ -#define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v))) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0MW[18:17] (RO) - * - * This read-only field defines the width of the bank 0 memory. - * - * Values: - * - 00 - 32 bits - * - 01 - 64 bits - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0MW (17U) /*!< Bit position for FMC_PFB0CR_B0MW. */ -#define BM_FMC_PFB0CR_B0MW (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */ -#define BS_FMC_PFB0CR_B0MW (2U) /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */ -#define BR_FMC_PFB0CR_B0MW(x) (HW_FMC_PFB0CR(x).B.B0MW) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ) - * - * This bit determines if the FMC's prefetch speculation buffer and the single - * entry page buffer are to be invalidated (cleared). When this bit is written, - * the speculation buffer and single entry buffer are immediately cleared. This bit - * always reads as zero. - * - * Values: - * - 0 - Speculation buffer and single entry buffer are not affected. - * - 1 - Invalidate (clear) speculation buffer and single entry buffer. - */ -/*@{*/ -#define BP_FMC_PFB0CR_S_B_INV (19U) /*!< Bit position for FMC_PFB0CR_S_B_INV. */ -#define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */ -#define BS_FMC_PFB0CR_S_B_INV (1U) /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */ - -/*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */ -#define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV) - -/*! @brief Set the S_B_INV field to a new value. */ -#define BW_FMC_PFB0CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ) - * - * These bits determine if the given cache way is to be invalidated (cleared). - * When a bit within this field is written, the corresponding cache way is - * immediately invalidated: the way's tag, data, and valid contents are cleared. This - * field always reads as zero. Cache invalidation takes precedence over locking. - * The cache is invalidated by system reset. System software is required to - * maintain memory coherency when any segment of the flash memory is programmed or - * erased. Accordingly, cache invalidations must occur after a programming or erase - * event is completed and before the new memory image is accessed. The bit setting - * definitions are for each bit in the field. - * - * Values: - * - 0 - No cache way invalidation for the corresponding cache - * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data, - * and vld bits of ways selected - */ -/*@{*/ -#define BP_FMC_PFB0CR_CINV_WAY (20U) /*!< Bit position for FMC_PFB0CR_CINV_WAY. */ -#define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */ -#define BS_FMC_PFB0CR_CINV_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */ - -/*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */ -#define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY) - -/*! @brief Set the CINV_WAY field to a new value. */ -#define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v))) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW) - * - * These bits determine if the given cache way is locked such that its contents - * will not be displaced by future misses. The bit setting definitions are for - * each bit in the field. - * - * Values: - * - 0 - Cache way is unlocked and may be displaced - * - 1 - Cache way is locked and its contents are not displaced - */ -/*@{*/ -#define BP_FMC_PFB0CR_CLCK_WAY (24U) /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */ -#define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */ -#define BS_FMC_PFB0CR_CLCK_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */ - -/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */ -#define BR_FMC_PFB0CR_CLCK_WAY(x) (HW_FMC_PFB0CR(x).B.CLCK_WAY) - -/*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */ -#define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY) - -/*! @brief Set the CLCK_WAY field to a new value. */ -#define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v))) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO) - * - * This read-only field defines the number of wait states required to access the - * bank 0 flash memory. The relationship between the read access time of the - * flash array (expressed in system clock cycles) and RWSC is defined as: Access - * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates - * this value based on the ratio of the system clock speed to the flash clock - * speed. For example, when this ratio is 4:1, the field's value is 3h. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0RWSC (28U) /*!< Bit position for FMC_PFB0CR_B0RWSC. */ -#define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */ -#define BS_FMC_PFB0CR_B0RWSC (4U) /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */ -#define BR_FMC_PFB0CR_B0RWSC(x) (HW_FMC_PFB0CR(x).B.B0RWSC) -/*@}*/ - -/******************************************************************************* - * HW_FMC_PFB1CR - Flash Bank 1 Control Register - ******************************************************************************/ - -/*! - * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW) - * - * Reset value: 0x3002001FU - * - * This register has a format similar to that for PFB0CR, except it controls the - * operation of flash bank 1, and the "global" cache control fields are empty. - */ -typedef union _hw_fmc_pfb1cr -{ - uint32_t U; - struct _hw_fmc_pfb1cr_bitfields - { - uint32_t B1SEBE : 1; /*!< [0] Bank 1 Single Entry Buffer Enable */ - uint32_t B1IPE : 1; /*!< [1] Bank 1 Instruction Prefetch Enable */ - uint32_t B1DPE : 1; /*!< [2] Bank 1 Data Prefetch Enable */ - uint32_t B1ICE : 1; /*!< [3] Bank 1 Instruction Cache Enable */ - uint32_t B1DCE : 1; /*!< [4] Bank 1 Data Cache Enable */ - uint32_t RESERVED0 : 12; /*!< [16:5] */ - uint32_t B1MW : 2; /*!< [18:17] Bank 1 Memory Width */ - uint32_t RESERVED1 : 9; /*!< [27:19] */ - uint32_t B1RWSC : 4; /*!< [31:28] Bank 1 Read Wait State Control */ - } B; -} hw_fmc_pfb1cr_t; - -/*! - * @name Constants and macros for entire FMC_PFB1CR register - */ -/*@{*/ -#define HW_FMC_PFB1CR_ADDR(x) ((x) + 0x8U) - -#define HW_FMC_PFB1CR(x) (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x)) -#define HW_FMC_PFB1CR_RD(x) (HW_FMC_PFB1CR(x).U) -#define HW_FMC_PFB1CR_WR(x, v) (HW_FMC_PFB1CR(x).U = (v)) -#define HW_FMC_PFB1CR_SET(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) | (v))) -#define HW_FMC_PFB1CR_CLR(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v))) -#define HW_FMC_PFB1CR_TOG(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_PFB1CR bitfields - */ - -/*! - * @name Register FMC_PFB1CR, field B1SEBE[0] (RW) - * - * This bit controls whether the single entry buffer is enabled in response to - * flash read accesses. Its operation is independent from bank 0's cache. A - * high-to-low transition of this enable forces the page buffer to be invalidated. - * - * Values: - * - 0 - Single entry buffer is disabled. - * - 1 - Single entry buffer is enabled. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1SEBE (0U) /*!< Bit position for FMC_PFB1CR_B1SEBE. */ -#define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */ -#define BS_FMC_PFB1CR_B1SEBE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */ -#define BR_FMC_PFB1CR_B1SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */ -#define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE) - -/*! @brief Set the B1SEBE field to a new value. */ -#define BW_FMC_PFB1CR_B1SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1IPE[1] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to instruction fetches. - * - * Values: - * - 0 - Do not prefetch in response to instruction fetches. - * - 1 - Enable prefetches in response to instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1IPE (1U) /*!< Bit position for FMC_PFB1CR_B1IPE. */ -#define BM_FMC_PFB1CR_B1IPE (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */ -#define BS_FMC_PFB1CR_B1IPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */ -#define BR_FMC_PFB1CR_B1IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */ -#define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE) - -/*! @brief Set the B1IPE field to a new value. */ -#define BW_FMC_PFB1CR_B1IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1DPE[2] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to data references. - * - * Values: - * - 0 - Do not prefetch in response to data references. - * - 1 - Enable prefetches in response to data references. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1DPE (2U) /*!< Bit position for FMC_PFB1CR_B1DPE. */ -#define BM_FMC_PFB1CR_B1DPE (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */ -#define BS_FMC_PFB1CR_B1DPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */ -#define BR_FMC_PFB1CR_B1DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */ -#define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE) - -/*! @brief Set the B1DPE field to a new value. */ -#define BW_FMC_PFB1CR_B1DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1ICE[3] (RW) - * - * This bit controls whether instruction fetches are loaded into the cache. - * - * Values: - * - 0 - Do not cache instruction fetches. - * - 1 - Cache instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1ICE (3U) /*!< Bit position for FMC_PFB1CR_B1ICE. */ -#define BM_FMC_PFB1CR_B1ICE (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */ -#define BS_FMC_PFB1CR_B1ICE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */ -#define BR_FMC_PFB1CR_B1ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */ -#define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE) - -/*! @brief Set the B1ICE field to a new value. */ -#define BW_FMC_PFB1CR_B1ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1DCE[4] (RW) - * - * This bit controls whether data references are loaded into the cache. - * - * Values: - * - 0 - Do not cache data references. - * - 1 - Cache data references. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1DCE (4U) /*!< Bit position for FMC_PFB1CR_B1DCE. */ -#define BM_FMC_PFB1CR_B1DCE (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */ -#define BS_FMC_PFB1CR_B1DCE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */ -#define BR_FMC_PFB1CR_B1DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */ -#define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE) - -/*! @brief Set the B1DCE field to a new value. */ -#define BW_FMC_PFB1CR_B1DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1MW[18:17] (RO) - * - * This read-only field defines the width of the bank 1 memory. - * - * Values: - * - 00 - 32 bits - * - 01 - 64 bits - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1MW (17U) /*!< Bit position for FMC_PFB1CR_B1MW. */ -#define BM_FMC_PFB1CR_B1MW (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */ -#define BS_FMC_PFB1CR_B1MW (2U) /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */ -#define BR_FMC_PFB1CR_B1MW(x) (HW_FMC_PFB1CR(x).B.B1MW) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO) - * - * This read-only field defines the number of wait states required to access the - * bank 1 flash memory. The relationship between the read access time of the - * flash array (expressed in system clock cycles) and RWSC is defined as: Access - * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates - * this value based on the ratio of the system clock speed to the flash clock - * speed. For example, when this ratio is 4:1, the field's value is 3h. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1RWSC (28U) /*!< Bit position for FMC_PFB1CR_B1RWSC. */ -#define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */ -#define BS_FMC_PFB1CR_B1RWSC (4U) /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */ -#define BR_FMC_PFB1CR_B1RWSC(x) (HW_FMC_PFB1CR(x).B.B1RWSC) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW0Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 8 sets. The ways are - * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw0sn -{ - uint32_t U; - struct _hw_fmc_tagvdw0sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw0sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW0Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW0Sn_COUNT (8U) - -#define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n))) - -#define HW_FMC_TAGVDW0Sn(x, n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U) -#define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW0Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW0Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW0Sn_valid (0U) /*!< Bit position for FMC_TAGVDW0Sn_valid. */ -#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */ -#define BS_FMC_TAGVDW0Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */ -#define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */ -#define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW0Sn_tag (5U) /*!< Bit position for FMC_TAGVDW0Sn_tag. */ -#define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */ -#define BS_FMC_TAGVDW0Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */ -#define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */ -#define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW1Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 8 sets. The ways are - * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw1sn -{ - uint32_t U; - struct _hw_fmc_tagvdw1sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw1sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW1Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW1Sn_COUNT (8U) - -#define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n))) - -#define HW_FMC_TAGVDW1Sn(x, n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U) -#define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW1Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW1Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW1Sn_valid (0U) /*!< Bit position for FMC_TAGVDW1Sn_valid. */ -#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */ -#define BS_FMC_TAGVDW1Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */ -#define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */ -#define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW1Sn_tag (5U) /*!< Bit position for FMC_TAGVDW1Sn_tag. */ -#define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */ -#define BS_FMC_TAGVDW1Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */ -#define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */ -#define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW2Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 8 sets. The ways are - * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw2sn -{ - uint32_t U; - struct _hw_fmc_tagvdw2sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw2sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW2Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW2Sn_COUNT (8U) - -#define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x140U + (0x4U * (n))) - -#define HW_FMC_TAGVDW2Sn(x, n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U) -#define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW2Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW2Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW2Sn_valid (0U) /*!< Bit position for FMC_TAGVDW2Sn_valid. */ -#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */ -#define BS_FMC_TAGVDW2Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */ -#define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */ -#define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW2Sn_tag (5U) /*!< Bit position for FMC_TAGVDW2Sn_tag. */ -#define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */ -#define BS_FMC_TAGVDW2Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */ -#define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */ -#define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW3Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 8 sets. The ways are - * numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw3sn -{ - uint32_t U; - struct _hw_fmc_tagvdw3sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw3sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW3Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW3Sn_COUNT (8U) - -#define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x160U + (0x4U * (n))) - -#define HW_FMC_TAGVDW3Sn(x, n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U) -#define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW3Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW3Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW3Sn_valid (0U) /*!< Bit position for FMC_TAGVDW3Sn_valid. */ -#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */ -#define BS_FMC_TAGVDW3Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */ -#define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */ -#define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW3Sn_tag (5U) /*!< Bit position for FMC_TAGVDW3Sn_tag. */ -#define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */ -#define BS_FMC_TAGVDW3Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */ -#define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */ -#define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW0SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw0snu -{ - uint32_t U; - struct _hw_fmc_dataw0snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw0snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW0SnU register - */ -/*@{*/ -#define HW_FMC_DATAW0SnU_COUNT (8U) - -#define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n))) - -#define HW_FMC_DATAW0SnU(x, n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n)) -#define HW_FMC_DATAW0SnU_RD(x, n) (HW_FMC_DATAW0SnU(x, n).U) -#define HW_FMC_DATAW0SnU_WR(x, n, v) (HW_FMC_DATAW0SnU(x, n).U = (v)) -#define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW0SnU bitfields - */ - -/*! - * @name Register FMC_DATAW0SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW0SnU_data (0U) /*!< Bit position for FMC_DATAW0SnU_data. */ -#define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */ -#define BS_FMC_DATAW0SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW0SnU_data field. */ -#define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW0SnU_data. */ -#define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW0SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw0snl -{ - uint32_t U; - struct _hw_fmc_dataw0snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw0snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW0SnL register - */ -/*@{*/ -#define HW_FMC_DATAW0SnL_COUNT (8U) - -#define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n))) - -#define HW_FMC_DATAW0SnL(x, n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n)) -#define HW_FMC_DATAW0SnL_RD(x, n) (HW_FMC_DATAW0SnL(x, n).U) -#define HW_FMC_DATAW0SnL_WR(x, n, v) (HW_FMC_DATAW0SnL(x, n).U = (v)) -#define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW0SnL bitfields - */ - -/*! - * @name Register FMC_DATAW0SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW0SnL_data (0U) /*!< Bit position for FMC_DATAW0SnL_data. */ -#define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */ -#define BS_FMC_DATAW0SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW0SnL_data field. */ -#define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW0SnL_data. */ -#define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW1SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw1snu -{ - uint32_t U; - struct _hw_fmc_dataw1snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw1snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW1SnU register - */ -/*@{*/ -#define HW_FMC_DATAW1SnU_COUNT (8U) - -#define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n))) - -#define HW_FMC_DATAW1SnU(x, n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n)) -#define HW_FMC_DATAW1SnU_RD(x, n) (HW_FMC_DATAW1SnU(x, n).U) -#define HW_FMC_DATAW1SnU_WR(x, n, v) (HW_FMC_DATAW1SnU(x, n).U = (v)) -#define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW1SnU bitfields - */ - -/*! - * @name Register FMC_DATAW1SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW1SnU_data (0U) /*!< Bit position for FMC_DATAW1SnU_data. */ -#define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */ -#define BS_FMC_DATAW1SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW1SnU_data field. */ -#define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW1SnU_data. */ -#define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW1SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw1snl -{ - uint32_t U; - struct _hw_fmc_dataw1snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw1snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW1SnL register - */ -/*@{*/ -#define HW_FMC_DATAW1SnL_COUNT (8U) - -#define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n))) - -#define HW_FMC_DATAW1SnL(x, n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n)) -#define HW_FMC_DATAW1SnL_RD(x, n) (HW_FMC_DATAW1SnL(x, n).U) -#define HW_FMC_DATAW1SnL_WR(x, n, v) (HW_FMC_DATAW1SnL(x, n).U = (v)) -#define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW1SnL bitfields - */ - -/*! - * @name Register FMC_DATAW1SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW1SnL_data (0U) /*!< Bit position for FMC_DATAW1SnL_data. */ -#define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */ -#define BS_FMC_DATAW1SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW1SnL_data field. */ -#define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW1SnL_data. */ -#define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW2SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw2snu -{ - uint32_t U; - struct _hw_fmc_dataw2snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw2snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW2SnU register - */ -/*@{*/ -#define HW_FMC_DATAW2SnU_COUNT (8U) - -#define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x280U + (0x8U * (n))) - -#define HW_FMC_DATAW2SnU(x, n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n)) -#define HW_FMC_DATAW2SnU_RD(x, n) (HW_FMC_DATAW2SnU(x, n).U) -#define HW_FMC_DATAW2SnU_WR(x, n, v) (HW_FMC_DATAW2SnU(x, n).U = (v)) -#define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW2SnU bitfields - */ - -/*! - * @name Register FMC_DATAW2SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW2SnU_data (0U) /*!< Bit position for FMC_DATAW2SnU_data. */ -#define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */ -#define BS_FMC_DATAW2SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW2SnU_data field. */ -#define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW2SnU_data. */ -#define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW2SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw2snl -{ - uint32_t U; - struct _hw_fmc_dataw2snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw2snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW2SnL register - */ -/*@{*/ -#define HW_FMC_DATAW2SnL_COUNT (8U) - -#define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x284U + (0x8U * (n))) - -#define HW_FMC_DATAW2SnL(x, n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n)) -#define HW_FMC_DATAW2SnL_RD(x, n) (HW_FMC_DATAW2SnL(x, n).U) -#define HW_FMC_DATAW2SnL_WR(x, n, v) (HW_FMC_DATAW2SnL(x, n).U = (v)) -#define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW2SnL bitfields - */ - -/*! - * @name Register FMC_DATAW2SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW2SnL_data (0U) /*!< Bit position for FMC_DATAW2SnL_data. */ -#define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */ -#define BS_FMC_DATAW2SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW2SnL_data field. */ -#define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW2SnL_data. */ -#define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW3SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw3snu -{ - uint32_t U; - struct _hw_fmc_dataw3snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw3snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW3SnU register - */ -/*@{*/ -#define HW_FMC_DATAW3SnU_COUNT (8U) - -#define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x2C0U + (0x8U * (n))) - -#define HW_FMC_DATAW3SnU(x, n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n)) -#define HW_FMC_DATAW3SnU_RD(x, n) (HW_FMC_DATAW3SnU(x, n).U) -#define HW_FMC_DATAW3SnU_WR(x, n, v) (HW_FMC_DATAW3SnU(x, n).U = (v)) -#define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW3SnU bitfields - */ - -/*! - * @name Register FMC_DATAW3SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW3SnU_data (0U) /*!< Bit position for FMC_DATAW3SnU_data. */ -#define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */ -#define BS_FMC_DATAW3SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW3SnU_data field. */ -#define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW3SnU_data. */ -#define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW3SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. - * The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw3snl -{ - uint32_t U; - struct _hw_fmc_dataw3snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw3snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW3SnL register - */ -/*@{*/ -#define HW_FMC_DATAW3SnL_COUNT (8U) - -#define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x2C4U + (0x8U * (n))) - -#define HW_FMC_DATAW3SnL(x, n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n)) -#define HW_FMC_DATAW3SnL_RD(x, n) (HW_FMC_DATAW3SnL(x, n).U) -#define HW_FMC_DATAW3SnL_WR(x, n, v) (HW_FMC_DATAW3SnL(x, n).U = (v)) -#define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW3SnL bitfields - */ - -/*! - * @name Register FMC_DATAW3SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW3SnL_data (0U) /*!< Bit position for FMC_DATAW3SnL_data. */ -#define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */ -#define BS_FMC_DATAW3SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW3SnL_data field. */ -#define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW3SnL_data. */ -#define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * hw_fmc_t - module struct - ******************************************************************************/ -/*! - * @brief All FMC module registers. - */ -#pragma pack(1) -typedef struct _hw_fmc -{ - __IO hw_fmc_pfapr_t PFAPR; /*!< [0x0] Flash Access Protection Register */ - __IO hw_fmc_pfb0cr_t PFB0CR; /*!< [0x4] Flash Bank 0 Control Register */ - __IO hw_fmc_pfb1cr_t PFB1CR; /*!< [0x8] Flash Bank 1 Control Register */ - uint8_t _reserved0[244]; - __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[8]; /*!< [0x100] Cache Tag Storage */ - __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[8]; /*!< [0x120] Cache Tag Storage */ - __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[8]; /*!< [0x140] Cache Tag Storage */ - __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[8]; /*!< [0x160] Cache Tag Storage */ - uint8_t _reserved1[128]; - struct { - __IO hw_fmc_dataw0snu_t DATAW0SnU; /*!< [0x200] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw0snl_t DATAW0SnL; /*!< [0x204] Cache Data Storage (lower word) */ - } DATAW0Sn[8]; - struct { - __IO hw_fmc_dataw1snu_t DATAW1SnU; /*!< [0x240] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw1snl_t DATAW1SnL; /*!< [0x244] Cache Data Storage (lower word) */ - } DATAW1Sn[8]; - struct { - __IO hw_fmc_dataw2snu_t DATAW2SnU; /*!< [0x280] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw2snl_t DATAW2SnL; /*!< [0x284] Cache Data Storage (lower word) */ - } DATAW2Sn[8]; - struct { - __IO hw_fmc_dataw3snu_t DATAW3SnU; /*!< [0x2C0] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw3snl_t DATAW3SnL; /*!< [0x2C4] Cache Data Storage (lower word) */ - } DATAW3Sn[8]; -} hw_fmc_t; -#pragma pack() - -/*! @brief Macro to access all FMC registers. */ -/*! @param x FMC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FMC(FMC_BASE). */ -#define HW_FMC(x) (*(hw_fmc_t *)(x)) - -#endif /* __HW_FMC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h deleted file mode 100644 index c4059bba447..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h +++ /dev/null @@ -1,3194 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FTFA_REGISTERS_H__ -#define __HW_FTFA_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 FTFA - * - * Flash Memory Interface - * - * Registers defined in this header file: - * - HW_FTFA_FSTAT - Flash Status Register - * - HW_FTFA_FCNFG - Flash Configuration Register - * - HW_FTFA_FSEC - Flash Security Register - * - HW_FTFA_FOPT - Flash Option Register - * - HW_FTFA_FCCOB3 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB2 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB1 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB0 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB7 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB6 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB5 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB4 - Flash Common Command Object Registers - * - HW_FTFA_FCCOBB - Flash Common Command Object Registers - * - HW_FTFA_FCCOBA - Flash Common Command Object Registers - * - HW_FTFA_FCCOB9 - Flash Common Command Object Registers - * - HW_FTFA_FCCOB8 - Flash Common Command Object Registers - * - HW_FTFA_FPROT3 - Program Flash Protection Registers - * - HW_FTFA_FPROT2 - Program Flash Protection Registers - * - HW_FTFA_FPROT1 - Program Flash Protection Registers - * - HW_FTFA_FPROT0 - Program Flash Protection Registers - * - HW_FTFA_XACCH3 - Execute-only Access Registers - * - HW_FTFA_XACCH2 - Execute-only Access Registers - * - HW_FTFA_XACCH1 - Execute-only Access Registers - * - HW_FTFA_XACCH0 - Execute-only Access Registers - * - HW_FTFA_XACCL3 - Execute-only Access Registers - * - HW_FTFA_XACCL2 - Execute-only Access Registers - * - HW_FTFA_XACCL1 - Execute-only Access Registers - * - HW_FTFA_XACCL0 - Execute-only Access Registers - * - HW_FTFA_SACCH3 - Supervisor-only Access Registers - * - HW_FTFA_SACCH2 - Supervisor-only Access Registers - * - HW_FTFA_SACCH1 - Supervisor-only Access Registers - * - HW_FTFA_SACCH0 - Supervisor-only Access Registers - * - HW_FTFA_SACCL3 - Supervisor-only Access Registers - * - HW_FTFA_SACCL2 - Supervisor-only Access Registers - * - HW_FTFA_SACCL1 - Supervisor-only Access Registers - * - HW_FTFA_SACCL0 - Supervisor-only Access Registers - * - HW_FTFA_FACSS - Flash Access Segment Size Register - * - HW_FTFA_FACSN - Flash Access Segment Number Register - * - * - hw_ftfa_t - Struct containing all module registers. - */ - -#define HW_FTFA_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFA module. */ - -/******************************************************************************* - * HW_FTFA_FSTAT - Flash Status Register - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FSTAT - Flash Status Register (RW) - * - * Reset value: 0x00U - * - * The FSTAT register reports the operational status of the flash memory module. - * The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The - * MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. When - * set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in - * this register prevent the launch of any more commands until the flag is - * cleared (by writing a one to it). - */ -typedef union _hw_ftfa_fstat -{ - uint8_t U; - struct _hw_ftfa_fstat_bitfields - { - uint8_t MGSTAT0 : 1; /*!< [0] Memory Controller Command Completion - * Status Flag */ - uint8_t RESERVED0 : 3; /*!< [3:1] */ - uint8_t FPVIOL : 1; /*!< [4] Flash Protection Violation Flag */ - uint8_t ACCERR : 1; /*!< [5] Flash Access Error Flag */ - uint8_t RDCOLERR : 1; /*!< [6] Flash Read Collision Error Flag */ - uint8_t CCIF : 1; /*!< [7] Command Complete Interrupt Flag */ - } B; -} hw_ftfa_fstat_t; - -/*! - * @name Constants and macros for entire FTFA_FSTAT register - */ -/*@{*/ -#define HW_FTFA_FSTAT_ADDR(x) ((x) + 0x0U) - -#define HW_FTFA_FSTAT(x) (*(__IO hw_ftfa_fstat_t *) HW_FTFA_FSTAT_ADDR(x)) -#define HW_FTFA_FSTAT_RD(x) (HW_FTFA_FSTAT(x).U) -#define HW_FTFA_FSTAT_WR(x, v) (HW_FTFA_FSTAT(x).U = (v)) -#define HW_FTFA_FSTAT_SET(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) | (v))) -#define HW_FTFA_FSTAT_CLR(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) & ~(v))) -#define HW_FTFA_FSTAT_TOG(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FSTAT bitfields - */ - -/*! - * @name Register FTFA_FSTAT, field MGSTAT0[0] (RO) - * - * The MGSTAT0 status flag is set if an error is detected during execution of a - * flash command or during the flash reset sequence. As a status flag, this field - * cannot (and need not) be cleared by the user like the other error flags in - * this register. The value of the MGSTAT0 bit for "command-N" is valid only at the - * end of the "command-N" execution when CCIF=1 and before the next command has - * been launched. At some point during the execution of "command-N+1," the - * previous result is discarded and any previous error is cleared. - */ -/*@{*/ -#define BP_FTFA_FSTAT_MGSTAT0 (0U) /*!< Bit position for FTFA_FSTAT_MGSTAT0. */ -#define BM_FTFA_FSTAT_MGSTAT0 (0x01U) /*!< Bit mask for FTFA_FSTAT_MGSTAT0. */ -#define BS_FTFA_FSTAT_MGSTAT0 (1U) /*!< Bit field size in bits for FTFA_FSTAT_MGSTAT0. */ - -/*! @brief Read current value of the FTFA_FSTAT_MGSTAT0 field. */ -#define BR_FTFA_FSTAT_MGSTAT0(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_MGSTAT0)) -/*@}*/ - -/*! - * @name Register FTFA_FSTAT, field FPVIOL[4] (W1C) - * - * Indicates an attempt was made to program or erase an address in a protected - * area of program flash memory during a command write sequence . While FPVIOL is - * set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is - * cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect. - * - * Values: - * - 0 - No protection violation detected - * - 1 - Protection violation detected - */ -/*@{*/ -#define BP_FTFA_FSTAT_FPVIOL (4U) /*!< Bit position for FTFA_FSTAT_FPVIOL. */ -#define BM_FTFA_FSTAT_FPVIOL (0x10U) /*!< Bit mask for FTFA_FSTAT_FPVIOL. */ -#define BS_FTFA_FSTAT_FPVIOL (1U) /*!< Bit field size in bits for FTFA_FSTAT_FPVIOL. */ - -/*! @brief Read current value of the FTFA_FSTAT_FPVIOL field. */ -#define BR_FTFA_FSTAT_FPVIOL(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_FPVIOL)) - -/*! @brief Format value for bitfield FTFA_FSTAT_FPVIOL. */ -#define BF_FTFA_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_FPVIOL) & BM_FTFA_FSTAT_FPVIOL) - -/*! @brief Set the FPVIOL field to a new value. */ -#define BW_FTFA_FSTAT_FPVIOL(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_FPVIOL) = (v)) -/*@}*/ - -/*! - * @name Register FTFA_FSTAT, field ACCERR[5] (W1C) - * - * Indicates an illegal access has occurred to a flash memory resource caused by - * a violation of the command write sequence or issuing an illegal flash - * command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. - * The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit - * has no effect. - * - * Values: - * - 0 - No access error detected - * - 1 - Access error detected - */ -/*@{*/ -#define BP_FTFA_FSTAT_ACCERR (5U) /*!< Bit position for FTFA_FSTAT_ACCERR. */ -#define BM_FTFA_FSTAT_ACCERR (0x20U) /*!< Bit mask for FTFA_FSTAT_ACCERR. */ -#define BS_FTFA_FSTAT_ACCERR (1U) /*!< Bit field size in bits for FTFA_FSTAT_ACCERR. */ - -/*! @brief Read current value of the FTFA_FSTAT_ACCERR field. */ -#define BR_FTFA_FSTAT_ACCERR(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_ACCERR)) - -/*! @brief Format value for bitfield FTFA_FSTAT_ACCERR. */ -#define BF_FTFA_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_ACCERR) & BM_FTFA_FSTAT_ACCERR) - -/*! @brief Set the ACCERR field to a new value. */ -#define BW_FTFA_FSTAT_ACCERR(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_ACCERR) = (v)) -/*@}*/ - -/*! - * @name Register FTFA_FSTAT, field RDCOLERR[6] (W1C) - * - * Indicates that the MCU attempted a read from a flash memory resource that was - * being manipulated by a flash command (CCIF=0). Any simultaneous access is - * detected as a collision error by the block arbitration logic. The read data in - * this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to - * it. Writing a 0 to RDCOLERR has no effect. - * - * Values: - * - 0 - No collision error detected - * - 1 - Collision error detected - */ -/*@{*/ -#define BP_FTFA_FSTAT_RDCOLERR (6U) /*!< Bit position for FTFA_FSTAT_RDCOLERR. */ -#define BM_FTFA_FSTAT_RDCOLERR (0x40U) /*!< Bit mask for FTFA_FSTAT_RDCOLERR. */ -#define BS_FTFA_FSTAT_RDCOLERR (1U) /*!< Bit field size in bits for FTFA_FSTAT_RDCOLERR. */ - -/*! @brief Read current value of the FTFA_FSTAT_RDCOLERR field. */ -#define BR_FTFA_FSTAT_RDCOLERR(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_RDCOLERR)) - -/*! @brief Format value for bitfield FTFA_FSTAT_RDCOLERR. */ -#define BF_FTFA_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_RDCOLERR) & BM_FTFA_FSTAT_RDCOLERR) - -/*! @brief Set the RDCOLERR field to a new value. */ -#define BW_FTFA_FSTAT_RDCOLERR(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_RDCOLERR) = (v)) -/*@}*/ - -/*! - * @name Register FTFA_FSTAT, field CCIF[7] (W1C) - * - * Indicates that a flash command has completed. The CCIF flag is cleared by - * writing a 1 to CCIF to launch a command, and CCIF stays low until command - * completion or command violation. CCIF is reset to 0 but is set to 1 by the memory - * controller at the end of the reset initialization sequence. Depending on how - * quickly the read occurs after reset release, the user may or may not see the 0 - * hardware reset value. - * - * Values: - * - 0 - Flash command in progress - * - 1 - Flash command has completed - */ -/*@{*/ -#define BP_FTFA_FSTAT_CCIF (7U) /*!< Bit position for FTFA_FSTAT_CCIF. */ -#define BM_FTFA_FSTAT_CCIF (0x80U) /*!< Bit mask for FTFA_FSTAT_CCIF. */ -#define BS_FTFA_FSTAT_CCIF (1U) /*!< Bit field size in bits for FTFA_FSTAT_CCIF. */ - -/*! @brief Read current value of the FTFA_FSTAT_CCIF field. */ -#define BR_FTFA_FSTAT_CCIF(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_CCIF)) - -/*! @brief Format value for bitfield FTFA_FSTAT_CCIF. */ -#define BF_FTFA_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_CCIF) & BM_FTFA_FSTAT_CCIF) - -/*! @brief Set the CCIF field to a new value. */ -#define BW_FTFA_FSTAT_CCIF(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_CCIF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCNFG - Flash Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCNFG - Flash Configuration Register (RW) - * - * Reset value: 0x00U - * - * This register provides information on the current functional state of the - * flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write - * restrictions. The unassigned bits read as noted and are not writable. - */ -typedef union _hw_ftfa_fcnfg -{ - uint8_t U; - struct _hw_ftfa_fcnfg_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t ERSSUSP : 1; /*!< [4] Erase Suspend */ - uint8_t ERSAREQ : 1; /*!< [5] Erase All Request */ - uint8_t RDCOLLIE : 1; /*!< [6] Read Collision Error Interrupt Enable - * */ - uint8_t CCIE : 1; /*!< [7] Command Complete Interrupt Enable */ - } B; -} hw_ftfa_fcnfg_t; - -/*! - * @name Constants and macros for entire FTFA_FCNFG register - */ -/*@{*/ -#define HW_FTFA_FCNFG_ADDR(x) ((x) + 0x1U) - -#define HW_FTFA_FCNFG(x) (*(__IO hw_ftfa_fcnfg_t *) HW_FTFA_FCNFG_ADDR(x)) -#define HW_FTFA_FCNFG_RD(x) (HW_FTFA_FCNFG(x).U) -#define HW_FTFA_FCNFG_WR(x, v) (HW_FTFA_FCNFG(x).U = (v)) -#define HW_FTFA_FCNFG_SET(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) | (v))) -#define HW_FTFA_FCNFG_CLR(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) & ~(v))) -#define HW_FTFA_FCNFG_TOG(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCNFG bitfields - */ - -/*! - * @name Register FTFA_FCNFG, field ERSSUSP[4] (RW) - * - * Allows the user to suspend (interrupt) the Erase Flash Sector command while - * it is executing. - * - * Values: - * - 0 - No suspend requested - * - 1 - Suspend the current Erase Flash Sector command execution. - */ -/*@{*/ -#define BP_FTFA_FCNFG_ERSSUSP (4U) /*!< Bit position for FTFA_FCNFG_ERSSUSP. */ -#define BM_FTFA_FCNFG_ERSSUSP (0x10U) /*!< Bit mask for FTFA_FCNFG_ERSSUSP. */ -#define BS_FTFA_FCNFG_ERSSUSP (1U) /*!< Bit field size in bits for FTFA_FCNFG_ERSSUSP. */ - -/*! @brief Read current value of the FTFA_FCNFG_ERSSUSP field. */ -#define BR_FTFA_FCNFG_ERSSUSP(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSSUSP)) - -/*! @brief Format value for bitfield FTFA_FCNFG_ERSSUSP. */ -#define BF_FTFA_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_ERSSUSP) & BM_FTFA_FCNFG_ERSSUSP) - -/*! @brief Set the ERSSUSP field to a new value. */ -#define BW_FTFA_FCNFG_ERSSUSP(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSSUSP) = (v)) -/*@}*/ - -/*! - * @name Register FTFA_FCNFG, field ERSAREQ[5] (RO) - * - * Issues a request to the memory controller to execute the Erase All Blocks - * command and release security. ERSAREQ is not directly writable but is under - * indirect user control. Refer to the device's Chip Configuration details on how to - * request this command. ERSAREQ sets when an erase all request is triggered - * external to the flash memory module and CCIF is set (no command is currently being - * executed). ERSAREQ is cleared by the flash memory module when the operation - * completes. - * - * Values: - * - 0 - No request or request complete - * - 1 - Request to: run the Erase All Blocks command, verify the erased state, - * program the security byte in the Flash Configuration Field to the unsecure - * state, and release MCU security by setting the FSEC[SEC] field to the - * unsecure state. - */ -/*@{*/ -#define BP_FTFA_FCNFG_ERSAREQ (5U) /*!< Bit position for FTFA_FCNFG_ERSAREQ. */ -#define BM_FTFA_FCNFG_ERSAREQ (0x20U) /*!< Bit mask for FTFA_FCNFG_ERSAREQ. */ -#define BS_FTFA_FCNFG_ERSAREQ (1U) /*!< Bit field size in bits for FTFA_FCNFG_ERSAREQ. */ - -/*! @brief Read current value of the FTFA_FCNFG_ERSAREQ field. */ -#define BR_FTFA_FCNFG_ERSAREQ(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSAREQ)) -/*@}*/ - -/*! - * @name Register FTFA_FCNFG, field RDCOLLIE[6] (RW) - * - * Controls interrupt generation when a flash memory read collision error occurs. - * - * Values: - * - 0 - Read collision error interrupt disabled - * - 1 - Read collision error interrupt enabled. An interrupt request is - * generated whenever a flash memory read collision error is detected (see the - * description of FSTAT[RDCOLERR]). - */ -/*@{*/ -#define BP_FTFA_FCNFG_RDCOLLIE (6U) /*!< Bit position for FTFA_FCNFG_RDCOLLIE. */ -#define BM_FTFA_FCNFG_RDCOLLIE (0x40U) /*!< Bit mask for FTFA_FCNFG_RDCOLLIE. */ -#define BS_FTFA_FCNFG_RDCOLLIE (1U) /*!< Bit field size in bits for FTFA_FCNFG_RDCOLLIE. */ - -/*! @brief Read current value of the FTFA_FCNFG_RDCOLLIE field. */ -#define BR_FTFA_FCNFG_RDCOLLIE(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_RDCOLLIE)) - -/*! @brief Format value for bitfield FTFA_FCNFG_RDCOLLIE. */ -#define BF_FTFA_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_RDCOLLIE) & BM_FTFA_FCNFG_RDCOLLIE) - -/*! @brief Set the RDCOLLIE field to a new value. */ -#define BW_FTFA_FCNFG_RDCOLLIE(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_RDCOLLIE) = (v)) -/*@}*/ - -/*! - * @name Register FTFA_FCNFG, field CCIE[7] (RW) - * - * Controls interrupt generation when a flash command completes. - * - * Values: - * - 0 - Command complete interrupt disabled - * - 1 - Command complete interrupt enabled. An interrupt request is generated - * whenever the FSTAT[CCIF] flag is set. - */ -/*@{*/ -#define BP_FTFA_FCNFG_CCIE (7U) /*!< Bit position for FTFA_FCNFG_CCIE. */ -#define BM_FTFA_FCNFG_CCIE (0x80U) /*!< Bit mask for FTFA_FCNFG_CCIE. */ -#define BS_FTFA_FCNFG_CCIE (1U) /*!< Bit field size in bits for FTFA_FCNFG_CCIE. */ - -/*! @brief Read current value of the FTFA_FCNFG_CCIE field. */ -#define BR_FTFA_FCNFG_CCIE(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_CCIE)) - -/*! @brief Format value for bitfield FTFA_FCNFG_CCIE. */ -#define BF_FTFA_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_CCIE) & BM_FTFA_FCNFG_CCIE) - -/*! @brief Set the CCIE field to a new value. */ -#define BW_FTFA_FCNFG_CCIE(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_CCIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FSEC - Flash Security Register - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FSEC - Flash Security Register (RO) - * - * Reset value: 0x00U - * - * This read-only register holds all bits associated with the security of the - * MCU and flash memory module. During the reset sequence, the register is loaded - * with the contents of the flash security byte in the Flash Configuration Field - * located in program flash memory. The flash basis for the values is signified by - * X in the reset value. - */ -typedef union _hw_ftfa_fsec -{ - uint8_t U; - struct _hw_ftfa_fsec_bitfields - { - uint8_t SEC : 2; /*!< [1:0] Flash Security */ - uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code - * */ - uint8_t MEEN : 2; /*!< [5:4] Mass Erase Enable Bits */ - uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */ - } B; -} hw_ftfa_fsec_t; - -/*! - * @name Constants and macros for entire FTFA_FSEC register - */ -/*@{*/ -#define HW_FTFA_FSEC_ADDR(x) ((x) + 0x2U) - -#define HW_FTFA_FSEC(x) (*(__I hw_ftfa_fsec_t *) HW_FTFA_FSEC_ADDR(x)) -#define HW_FTFA_FSEC_RD(x) (HW_FTFA_FSEC(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FSEC bitfields - */ - -/*! - * @name Register FTFA_FSEC, field SEC[1:0] (RO) - * - * Defines the security state of the MCU. In the secure state, the MCU limits - * access to flash memory module resources. The limitations are defined per device - * and are detailed in the Chip Configuration details. If the flash memory module - * is unsecured using backdoor key access, SEC is forced to 10b. - * - * Values: - * - 00 - MCU security status is secure. - * - 01 - MCU security status is secure. - * - 10 - MCU security status is unsecure. (The standard shipping condition of - * the flash memory module is unsecure.) - * - 11 - MCU security status is secure. - */ -/*@{*/ -#define BP_FTFA_FSEC_SEC (0U) /*!< Bit position for FTFA_FSEC_SEC. */ -#define BM_FTFA_FSEC_SEC (0x03U) /*!< Bit mask for FTFA_FSEC_SEC. */ -#define BS_FTFA_FSEC_SEC (2U) /*!< Bit field size in bits for FTFA_FSEC_SEC. */ - -/*! @brief Read current value of the FTFA_FSEC_SEC field. */ -#define BR_FTFA_FSEC_SEC(x) (HW_FTFA_FSEC(x).B.SEC) -/*@}*/ - -/*! - * @name Register FTFA_FSEC, field FSLACC[3:2] (RO) - * - * Enables or disables access to the flash memory contents during returned part - * failure analysis at Freescale. When SEC is secure and FSLACC is denied, access - * to the program flash contents is denied and any failure analysis performed by - * Freescale factory test must begin with a full erase to unsecure the part. - * When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), - * Freescale factory testing has visibility of the current flash contents. The - * state of the FSLACC bits is only relevant when SEC is set to secure. When SEC - * is set to unsecure, the FSLACC setting does not matter. - * - * Values: - * - 00 - Freescale factory access granted - * - 01 - Freescale factory access denied - * - 10 - Freescale factory access denied - * - 11 - Freescale factory access granted - */ -/*@{*/ -#define BP_FTFA_FSEC_FSLACC (2U) /*!< Bit position for FTFA_FSEC_FSLACC. */ -#define BM_FTFA_FSEC_FSLACC (0x0CU) /*!< Bit mask for FTFA_FSEC_FSLACC. */ -#define BS_FTFA_FSEC_FSLACC (2U) /*!< Bit field size in bits for FTFA_FSEC_FSLACC. */ - -/*! @brief Read current value of the FTFA_FSEC_FSLACC field. */ -#define BR_FTFA_FSEC_FSLACC(x) (HW_FTFA_FSEC(x).B.FSLACC) -/*@}*/ - -/*! - * @name Register FTFA_FSEC, field MEEN[5:4] (RO) - * - * Enables and disables mass erase capability of the flash memory module. The - * state of this field is relevant only when SEC is set to secure outside of NVM - * Normal Mode. When SEC is set to unsecure, the MEEN setting does not matter. - * - * Values: - * - 00 - Mass erase is enabled - * - 01 - Mass erase is enabled - * - 10 - Mass erase is disabled - * - 11 - Mass erase is enabled - */ -/*@{*/ -#define BP_FTFA_FSEC_MEEN (4U) /*!< Bit position for FTFA_FSEC_MEEN. */ -#define BM_FTFA_FSEC_MEEN (0x30U) /*!< Bit mask for FTFA_FSEC_MEEN. */ -#define BS_FTFA_FSEC_MEEN (2U) /*!< Bit field size in bits for FTFA_FSEC_MEEN. */ - -/*! @brief Read current value of the FTFA_FSEC_MEEN field. */ -#define BR_FTFA_FSEC_MEEN(x) (HW_FTFA_FSEC(x).B.MEEN) -/*@}*/ - -/*! - * @name Register FTFA_FSEC, field KEYEN[7:6] (RO) - * - * Enables or disables backdoor key access to the flash memory module. - * - * Values: - * - 00 - Backdoor key access disabled - * - 01 - Backdoor key access disabled (preferred KEYEN state to disable - * backdoor key access) - * - 10 - Backdoor key access enabled - * - 11 - Backdoor key access disabled - */ -/*@{*/ -#define BP_FTFA_FSEC_KEYEN (6U) /*!< Bit position for FTFA_FSEC_KEYEN. */ -#define BM_FTFA_FSEC_KEYEN (0xC0U) /*!< Bit mask for FTFA_FSEC_KEYEN. */ -#define BS_FTFA_FSEC_KEYEN (2U) /*!< Bit field size in bits for FTFA_FSEC_KEYEN. */ - -/*! @brief Read current value of the FTFA_FSEC_KEYEN field. */ -#define BR_FTFA_FSEC_KEYEN(x) (HW_FTFA_FSEC(x).B.KEYEN) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FOPT - Flash Option Register - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FOPT - Flash Option Register (RO) - * - * Reset value: 0x00U - * - * The flash option register allows the MCU to customize its operations by - * examining the state of these read-only bits, which are loaded from NVM at reset. - * The function of the bits is defined in the device's Chip Configuration details. - * All bits in the register are read-only . During the reset sequence, the - * register is loaded from the flash nonvolatile option byte in the Flash Configuration - * Field located in program flash memory. The flash basis for the values is - * signified by X in the reset value. However, the register is written to 0xFF if the - * contents of the flash nonvolatile option byte are 0x00. - */ -typedef union _hw_ftfa_fopt -{ - uint8_t U; - struct _hw_ftfa_fopt_bitfields - { - uint8_t OPT : 8; /*!< [7:0] Nonvolatile Option */ - } B; -} hw_ftfa_fopt_t; - -/*! - * @name Constants and macros for entire FTFA_FOPT register - */ -/*@{*/ -#define HW_FTFA_FOPT_ADDR(x) ((x) + 0x3U) - -#define HW_FTFA_FOPT(x) (*(__I hw_ftfa_fopt_t *) HW_FTFA_FOPT_ADDR(x)) -#define HW_FTFA_FOPT_RD(x) (HW_FTFA_FOPT(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FOPT bitfields - */ - -/*! - * @name Register FTFA_FOPT, field OPT[7:0] (RO) - * - * These bits are loaded from flash to this register at reset. Refer to the - * device's Chip Configuration details for the definition and use of these bits. - */ -/*@{*/ -#define BP_FTFA_FOPT_OPT (0U) /*!< Bit position for FTFA_FOPT_OPT. */ -#define BM_FTFA_FOPT_OPT (0xFFU) /*!< Bit mask for FTFA_FOPT_OPT. */ -#define BS_FTFA_FOPT_OPT (8U) /*!< Bit field size in bits for FTFA_FOPT_OPT. */ - -/*! @brief Read current value of the FTFA_FOPT_OPT field. */ -#define BR_FTFA_FOPT_OPT(x) (HW_FTFA_FOPT(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB3 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB3 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob3 -{ - uint8_t U; - struct _hw_ftfa_fccob3_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob3_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB3 register - */ -/*@{*/ -#define HW_FTFA_FCCOB3_ADDR(x) ((x) + 0x4U) - -#define HW_FTFA_FCCOB3(x) (*(__IO hw_ftfa_fccob3_t *) HW_FTFA_FCCOB3_ADDR(x)) -#define HW_FTFA_FCCOB3_RD(x) (HW_FTFA_FCCOB3(x).U) -#define HW_FTFA_FCCOB3_WR(x, v) (HW_FTFA_FCCOB3(x).U = (v)) -#define HW_FTFA_FCCOB3_SET(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) | (v))) -#define HW_FTFA_FCCOB3_CLR(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) & ~(v))) -#define HW_FTFA_FCCOB3_TOG(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB3 bitfields - */ - -/*! - * @name Register FTFA_FCCOB3, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB3_CCOBn (0U) /*!< Bit position for FTFA_FCCOB3_CCOBn. */ -#define BM_FTFA_FCCOB3_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB3_CCOBn. */ -#define BS_FTFA_FCCOB3_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB3_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB3_CCOBn field. */ -#define BR_FTFA_FCCOB3_CCOBn(x) (HW_FTFA_FCCOB3(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB3_CCOBn. */ -#define BF_FTFA_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB3_CCOBn) & BM_FTFA_FCCOB3_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB3_CCOBn(x, v) (HW_FTFA_FCCOB3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB2 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB2 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob2 -{ - uint8_t U; - struct _hw_ftfa_fccob2_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob2_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB2 register - */ -/*@{*/ -#define HW_FTFA_FCCOB2_ADDR(x) ((x) + 0x5U) - -#define HW_FTFA_FCCOB2(x) (*(__IO hw_ftfa_fccob2_t *) HW_FTFA_FCCOB2_ADDR(x)) -#define HW_FTFA_FCCOB2_RD(x) (HW_FTFA_FCCOB2(x).U) -#define HW_FTFA_FCCOB2_WR(x, v) (HW_FTFA_FCCOB2(x).U = (v)) -#define HW_FTFA_FCCOB2_SET(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) | (v))) -#define HW_FTFA_FCCOB2_CLR(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) & ~(v))) -#define HW_FTFA_FCCOB2_TOG(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB2 bitfields - */ - -/*! - * @name Register FTFA_FCCOB2, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB2_CCOBn (0U) /*!< Bit position for FTFA_FCCOB2_CCOBn. */ -#define BM_FTFA_FCCOB2_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB2_CCOBn. */ -#define BS_FTFA_FCCOB2_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB2_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB2_CCOBn field. */ -#define BR_FTFA_FCCOB2_CCOBn(x) (HW_FTFA_FCCOB2(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB2_CCOBn. */ -#define BF_FTFA_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB2_CCOBn) & BM_FTFA_FCCOB2_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB2_CCOBn(x, v) (HW_FTFA_FCCOB2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB1 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB1 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob1 -{ - uint8_t U; - struct _hw_ftfa_fccob1_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob1_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB1 register - */ -/*@{*/ -#define HW_FTFA_FCCOB1_ADDR(x) ((x) + 0x6U) - -#define HW_FTFA_FCCOB1(x) (*(__IO hw_ftfa_fccob1_t *) HW_FTFA_FCCOB1_ADDR(x)) -#define HW_FTFA_FCCOB1_RD(x) (HW_FTFA_FCCOB1(x).U) -#define HW_FTFA_FCCOB1_WR(x, v) (HW_FTFA_FCCOB1(x).U = (v)) -#define HW_FTFA_FCCOB1_SET(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) | (v))) -#define HW_FTFA_FCCOB1_CLR(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) & ~(v))) -#define HW_FTFA_FCCOB1_TOG(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB1 bitfields - */ - -/*! - * @name Register FTFA_FCCOB1, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB1_CCOBn (0U) /*!< Bit position for FTFA_FCCOB1_CCOBn. */ -#define BM_FTFA_FCCOB1_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB1_CCOBn. */ -#define BS_FTFA_FCCOB1_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB1_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB1_CCOBn field. */ -#define BR_FTFA_FCCOB1_CCOBn(x) (HW_FTFA_FCCOB1(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB1_CCOBn. */ -#define BF_FTFA_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB1_CCOBn) & BM_FTFA_FCCOB1_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB1_CCOBn(x, v) (HW_FTFA_FCCOB1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB0 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB0 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob0 -{ - uint8_t U; - struct _hw_ftfa_fccob0_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob0_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB0 register - */ -/*@{*/ -#define HW_FTFA_FCCOB0_ADDR(x) ((x) + 0x7U) - -#define HW_FTFA_FCCOB0(x) (*(__IO hw_ftfa_fccob0_t *) HW_FTFA_FCCOB0_ADDR(x)) -#define HW_FTFA_FCCOB0_RD(x) (HW_FTFA_FCCOB0(x).U) -#define HW_FTFA_FCCOB0_WR(x, v) (HW_FTFA_FCCOB0(x).U = (v)) -#define HW_FTFA_FCCOB0_SET(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) | (v))) -#define HW_FTFA_FCCOB0_CLR(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) & ~(v))) -#define HW_FTFA_FCCOB0_TOG(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB0 bitfields - */ - -/*! - * @name Register FTFA_FCCOB0, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB0_CCOBn (0U) /*!< Bit position for FTFA_FCCOB0_CCOBn. */ -#define BM_FTFA_FCCOB0_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB0_CCOBn. */ -#define BS_FTFA_FCCOB0_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB0_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB0_CCOBn field. */ -#define BR_FTFA_FCCOB0_CCOBn(x) (HW_FTFA_FCCOB0(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB0_CCOBn. */ -#define BF_FTFA_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB0_CCOBn) & BM_FTFA_FCCOB0_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB0_CCOBn(x, v) (HW_FTFA_FCCOB0_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB7 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB7 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob7 -{ - uint8_t U; - struct _hw_ftfa_fccob7_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob7_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB7 register - */ -/*@{*/ -#define HW_FTFA_FCCOB7_ADDR(x) ((x) + 0x8U) - -#define HW_FTFA_FCCOB7(x) (*(__IO hw_ftfa_fccob7_t *) HW_FTFA_FCCOB7_ADDR(x)) -#define HW_FTFA_FCCOB7_RD(x) (HW_FTFA_FCCOB7(x).U) -#define HW_FTFA_FCCOB7_WR(x, v) (HW_FTFA_FCCOB7(x).U = (v)) -#define HW_FTFA_FCCOB7_SET(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) | (v))) -#define HW_FTFA_FCCOB7_CLR(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) & ~(v))) -#define HW_FTFA_FCCOB7_TOG(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB7 bitfields - */ - -/*! - * @name Register FTFA_FCCOB7, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB7_CCOBn (0U) /*!< Bit position for FTFA_FCCOB7_CCOBn. */ -#define BM_FTFA_FCCOB7_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB7_CCOBn. */ -#define BS_FTFA_FCCOB7_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB7_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB7_CCOBn field. */ -#define BR_FTFA_FCCOB7_CCOBn(x) (HW_FTFA_FCCOB7(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB7_CCOBn. */ -#define BF_FTFA_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB7_CCOBn) & BM_FTFA_FCCOB7_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB7_CCOBn(x, v) (HW_FTFA_FCCOB7_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB6 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB6 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob6 -{ - uint8_t U; - struct _hw_ftfa_fccob6_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob6_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB6 register - */ -/*@{*/ -#define HW_FTFA_FCCOB6_ADDR(x) ((x) + 0x9U) - -#define HW_FTFA_FCCOB6(x) (*(__IO hw_ftfa_fccob6_t *) HW_FTFA_FCCOB6_ADDR(x)) -#define HW_FTFA_FCCOB6_RD(x) (HW_FTFA_FCCOB6(x).U) -#define HW_FTFA_FCCOB6_WR(x, v) (HW_FTFA_FCCOB6(x).U = (v)) -#define HW_FTFA_FCCOB6_SET(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) | (v))) -#define HW_FTFA_FCCOB6_CLR(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) & ~(v))) -#define HW_FTFA_FCCOB6_TOG(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB6 bitfields - */ - -/*! - * @name Register FTFA_FCCOB6, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB6_CCOBn (0U) /*!< Bit position for FTFA_FCCOB6_CCOBn. */ -#define BM_FTFA_FCCOB6_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB6_CCOBn. */ -#define BS_FTFA_FCCOB6_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB6_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB6_CCOBn field. */ -#define BR_FTFA_FCCOB6_CCOBn(x) (HW_FTFA_FCCOB6(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB6_CCOBn. */ -#define BF_FTFA_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB6_CCOBn) & BM_FTFA_FCCOB6_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB6_CCOBn(x, v) (HW_FTFA_FCCOB6_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB5 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB5 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob5 -{ - uint8_t U; - struct _hw_ftfa_fccob5_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob5_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB5 register - */ -/*@{*/ -#define HW_FTFA_FCCOB5_ADDR(x) ((x) + 0xAU) - -#define HW_FTFA_FCCOB5(x) (*(__IO hw_ftfa_fccob5_t *) HW_FTFA_FCCOB5_ADDR(x)) -#define HW_FTFA_FCCOB5_RD(x) (HW_FTFA_FCCOB5(x).U) -#define HW_FTFA_FCCOB5_WR(x, v) (HW_FTFA_FCCOB5(x).U = (v)) -#define HW_FTFA_FCCOB5_SET(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) | (v))) -#define HW_FTFA_FCCOB5_CLR(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) & ~(v))) -#define HW_FTFA_FCCOB5_TOG(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB5 bitfields - */ - -/*! - * @name Register FTFA_FCCOB5, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB5_CCOBn (0U) /*!< Bit position for FTFA_FCCOB5_CCOBn. */ -#define BM_FTFA_FCCOB5_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB5_CCOBn. */ -#define BS_FTFA_FCCOB5_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB5_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB5_CCOBn field. */ -#define BR_FTFA_FCCOB5_CCOBn(x) (HW_FTFA_FCCOB5(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB5_CCOBn. */ -#define BF_FTFA_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB5_CCOBn) & BM_FTFA_FCCOB5_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB5_CCOBn(x, v) (HW_FTFA_FCCOB5_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB4 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB4 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob4 -{ - uint8_t U; - struct _hw_ftfa_fccob4_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob4_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB4 register - */ -/*@{*/ -#define HW_FTFA_FCCOB4_ADDR(x) ((x) + 0xBU) - -#define HW_FTFA_FCCOB4(x) (*(__IO hw_ftfa_fccob4_t *) HW_FTFA_FCCOB4_ADDR(x)) -#define HW_FTFA_FCCOB4_RD(x) (HW_FTFA_FCCOB4(x).U) -#define HW_FTFA_FCCOB4_WR(x, v) (HW_FTFA_FCCOB4(x).U = (v)) -#define HW_FTFA_FCCOB4_SET(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) | (v))) -#define HW_FTFA_FCCOB4_CLR(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) & ~(v))) -#define HW_FTFA_FCCOB4_TOG(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB4 bitfields - */ - -/*! - * @name Register FTFA_FCCOB4, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB4_CCOBn (0U) /*!< Bit position for FTFA_FCCOB4_CCOBn. */ -#define BM_FTFA_FCCOB4_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB4_CCOBn. */ -#define BS_FTFA_FCCOB4_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB4_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB4_CCOBn field. */ -#define BR_FTFA_FCCOB4_CCOBn(x) (HW_FTFA_FCCOB4(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB4_CCOBn. */ -#define BF_FTFA_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB4_CCOBn) & BM_FTFA_FCCOB4_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB4_CCOBn(x, v) (HW_FTFA_FCCOB4_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOBB - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOBB - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccobb -{ - uint8_t U; - struct _hw_ftfa_fccobb_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccobb_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOBB register - */ -/*@{*/ -#define HW_FTFA_FCCOBB_ADDR(x) ((x) + 0xCU) - -#define HW_FTFA_FCCOBB(x) (*(__IO hw_ftfa_fccobb_t *) HW_FTFA_FCCOBB_ADDR(x)) -#define HW_FTFA_FCCOBB_RD(x) (HW_FTFA_FCCOBB(x).U) -#define HW_FTFA_FCCOBB_WR(x, v) (HW_FTFA_FCCOBB(x).U = (v)) -#define HW_FTFA_FCCOBB_SET(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) | (v))) -#define HW_FTFA_FCCOBB_CLR(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) & ~(v))) -#define HW_FTFA_FCCOBB_TOG(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOBB bitfields - */ - -/*! - * @name Register FTFA_FCCOBB, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOBB_CCOBn (0U) /*!< Bit position for FTFA_FCCOBB_CCOBn. */ -#define BM_FTFA_FCCOBB_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOBB_CCOBn. */ -#define BS_FTFA_FCCOBB_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOBB_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOBB_CCOBn field. */ -#define BR_FTFA_FCCOBB_CCOBn(x) (HW_FTFA_FCCOBB(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOBB_CCOBn. */ -#define BF_FTFA_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOBB_CCOBn) & BM_FTFA_FCCOBB_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOBB_CCOBn(x, v) (HW_FTFA_FCCOBB_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOBA - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOBA - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccoba -{ - uint8_t U; - struct _hw_ftfa_fccoba_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccoba_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOBA register - */ -/*@{*/ -#define HW_FTFA_FCCOBA_ADDR(x) ((x) + 0xDU) - -#define HW_FTFA_FCCOBA(x) (*(__IO hw_ftfa_fccoba_t *) HW_FTFA_FCCOBA_ADDR(x)) -#define HW_FTFA_FCCOBA_RD(x) (HW_FTFA_FCCOBA(x).U) -#define HW_FTFA_FCCOBA_WR(x, v) (HW_FTFA_FCCOBA(x).U = (v)) -#define HW_FTFA_FCCOBA_SET(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) | (v))) -#define HW_FTFA_FCCOBA_CLR(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) & ~(v))) -#define HW_FTFA_FCCOBA_TOG(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOBA bitfields - */ - -/*! - * @name Register FTFA_FCCOBA, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOBA_CCOBn (0U) /*!< Bit position for FTFA_FCCOBA_CCOBn. */ -#define BM_FTFA_FCCOBA_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOBA_CCOBn. */ -#define BS_FTFA_FCCOBA_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOBA_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOBA_CCOBn field. */ -#define BR_FTFA_FCCOBA_CCOBn(x) (HW_FTFA_FCCOBA(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOBA_CCOBn. */ -#define BF_FTFA_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOBA_CCOBn) & BM_FTFA_FCCOBA_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOBA_CCOBn(x, v) (HW_FTFA_FCCOBA_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB9 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB9 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob9 -{ - uint8_t U; - struct _hw_ftfa_fccob9_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob9_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB9 register - */ -/*@{*/ -#define HW_FTFA_FCCOB9_ADDR(x) ((x) + 0xEU) - -#define HW_FTFA_FCCOB9(x) (*(__IO hw_ftfa_fccob9_t *) HW_FTFA_FCCOB9_ADDR(x)) -#define HW_FTFA_FCCOB9_RD(x) (HW_FTFA_FCCOB9(x).U) -#define HW_FTFA_FCCOB9_WR(x, v) (HW_FTFA_FCCOB9(x).U = (v)) -#define HW_FTFA_FCCOB9_SET(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) | (v))) -#define HW_FTFA_FCCOB9_CLR(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) & ~(v))) -#define HW_FTFA_FCCOB9_TOG(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB9 bitfields - */ - -/*! - * @name Register FTFA_FCCOB9, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB9_CCOBn (0U) /*!< Bit position for FTFA_FCCOB9_CCOBn. */ -#define BM_FTFA_FCCOB9_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB9_CCOBn. */ -#define BS_FTFA_FCCOB9_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB9_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB9_CCOBn field. */ -#define BR_FTFA_FCCOB9_CCOBn(x) (HW_FTFA_FCCOB9(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB9_CCOBn. */ -#define BF_FTFA_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB9_CCOBn) & BM_FTFA_FCCOB9_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB9_CCOBn(x, v) (HW_FTFA_FCCOB9_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FCCOB8 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FCCOB8 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfa_fccob8 -{ - uint8_t U; - struct _hw_ftfa_fccob8_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfa_fccob8_t; - -/*! - * @name Constants and macros for entire FTFA_FCCOB8 register - */ -/*@{*/ -#define HW_FTFA_FCCOB8_ADDR(x) ((x) + 0xFU) - -#define HW_FTFA_FCCOB8(x) (*(__IO hw_ftfa_fccob8_t *) HW_FTFA_FCCOB8_ADDR(x)) -#define HW_FTFA_FCCOB8_RD(x) (HW_FTFA_FCCOB8(x).U) -#define HW_FTFA_FCCOB8_WR(x, v) (HW_FTFA_FCCOB8(x).U = (v)) -#define HW_FTFA_FCCOB8_SET(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) | (v))) -#define HW_FTFA_FCCOB8_CLR(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) & ~(v))) -#define HW_FTFA_FCCOB8_TOG(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FCCOB8 bitfields - */ - -/*! - * @name Register FTFA_FCCOB8, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic flash command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific flash - * command, typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register - * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that - * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 - * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 - * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The - * FCCOB register group uses a big endian addressing convention. For all command - * parameter fields larger than 1 byte, the most significant data resides in the - * lowest FCCOB register number. - */ -/*@{*/ -#define BP_FTFA_FCCOB8_CCOBn (0U) /*!< Bit position for FTFA_FCCOB8_CCOBn. */ -#define BM_FTFA_FCCOB8_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB8_CCOBn. */ -#define BS_FTFA_FCCOB8_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB8_CCOBn. */ - -/*! @brief Read current value of the FTFA_FCCOB8_CCOBn field. */ -#define BR_FTFA_FCCOB8_CCOBn(x) (HW_FTFA_FCCOB8(x).U) - -/*! @brief Format value for bitfield FTFA_FCCOB8_CCOBn. */ -#define BF_FTFA_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB8_CCOBn) & BM_FTFA_FCCOB8_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFA_FCCOB8_CCOBn(x, v) (HW_FTFA_FCCOB8_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FPROT3 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FPROT3 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which logical program flash regions are protected - * from program and erase operations. Protected flash regions cannot have their - * content changed; that is, these regions cannot be programmed and cannot be - * erased by any flash command. Unprotected regions can be changed by program and - * erase operations. The four FPROT registers allow up to 32 protectable regions. - * Each bit protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit - * protects 1 KB . For configurations with 24 KB of program flash memory or less, - * FPROT0 is not used. For configurations with 16 KB of program flash memory or - * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, - * FPROT2 is not used. The bitfields are defined in each register as follows: - * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] - * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset - * sequence, the FPROT registers are loaded with the contents of the program flash - * protection bytes in the Flash Configuration Field as indicated in the following - * table. Program flash protection register Flash Configuration Field offset - * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the - * program flash protection that is loaded during the reset sequence, unprotect the - * sector of program flash memory that contains the Flash Configuration Field. Then, - * reprogram the program flash protection byte. - */ -typedef union _hw_ftfa_fprot3 -{ - uint8_t U; - struct _hw_ftfa_fprot3_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfa_fprot3_t; - -/*! - * @name Constants and macros for entire FTFA_FPROT3 register - */ -/*@{*/ -#define HW_FTFA_FPROT3_ADDR(x) ((x) + 0x10U) - -#define HW_FTFA_FPROT3(x) (*(__IO hw_ftfa_fprot3_t *) HW_FTFA_FPROT3_ADDR(x)) -#define HW_FTFA_FPROT3_RD(x) (HW_FTFA_FPROT3(x).U) -#define HW_FTFA_FPROT3_WR(x, v) (HW_FTFA_FPROT3(x).U = (v)) -#define HW_FTFA_FPROT3_SET(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) | (v))) -#define HW_FTFA_FPROT3_CLR(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) & ~(v))) -#define HW_FTFA_FPROT3_TOG(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FPROT3 bitfields - */ - -/*! - * @name Register FTFA_FPROT3, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. Each bit in the 32-bit protection - * register represents 1/32 of the total program flash except for configurations where - * program flash memory is less than 32 KB. For configurations with less than 32 - * KB of program flash memory, each assigned bit represents 1 KB. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFA_FPROT3_PROT (0U) /*!< Bit position for FTFA_FPROT3_PROT. */ -#define BM_FTFA_FPROT3_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT3_PROT. */ -#define BS_FTFA_FPROT3_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT3_PROT. */ - -/*! @brief Read current value of the FTFA_FPROT3_PROT field. */ -#define BR_FTFA_FPROT3_PROT(x) (HW_FTFA_FPROT3(x).U) - -/*! @brief Format value for bitfield FTFA_FPROT3_PROT. */ -#define BF_FTFA_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT3_PROT) & BM_FTFA_FPROT3_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFA_FPROT3_PROT(x, v) (HW_FTFA_FPROT3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FPROT2 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FPROT2 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which logical program flash regions are protected - * from program and erase operations. Protected flash regions cannot have their - * content changed; that is, these regions cannot be programmed and cannot be - * erased by any flash command. Unprotected regions can be changed by program and - * erase operations. The four FPROT registers allow up to 32 protectable regions. - * Each bit protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit - * protects 1 KB . For configurations with 24 KB of program flash memory or less, - * FPROT0 is not used. For configurations with 16 KB of program flash memory or - * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, - * FPROT2 is not used. The bitfields are defined in each register as follows: - * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] - * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset - * sequence, the FPROT registers are loaded with the contents of the program flash - * protection bytes in the Flash Configuration Field as indicated in the following - * table. Program flash protection register Flash Configuration Field offset - * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the - * program flash protection that is loaded during the reset sequence, unprotect the - * sector of program flash memory that contains the Flash Configuration Field. Then, - * reprogram the program flash protection byte. - */ -typedef union _hw_ftfa_fprot2 -{ - uint8_t U; - struct _hw_ftfa_fprot2_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfa_fprot2_t; - -/*! - * @name Constants and macros for entire FTFA_FPROT2 register - */ -/*@{*/ -#define HW_FTFA_FPROT2_ADDR(x) ((x) + 0x11U) - -#define HW_FTFA_FPROT2(x) (*(__IO hw_ftfa_fprot2_t *) HW_FTFA_FPROT2_ADDR(x)) -#define HW_FTFA_FPROT2_RD(x) (HW_FTFA_FPROT2(x).U) -#define HW_FTFA_FPROT2_WR(x, v) (HW_FTFA_FPROT2(x).U = (v)) -#define HW_FTFA_FPROT2_SET(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) | (v))) -#define HW_FTFA_FPROT2_CLR(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) & ~(v))) -#define HW_FTFA_FPROT2_TOG(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FPROT2 bitfields - */ - -/*! - * @name Register FTFA_FPROT2, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. Each bit in the 32-bit protection - * register represents 1/32 of the total program flash except for configurations where - * program flash memory is less than 32 KB. For configurations with less than 32 - * KB of program flash memory, each assigned bit represents 1 KB. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFA_FPROT2_PROT (0U) /*!< Bit position for FTFA_FPROT2_PROT. */ -#define BM_FTFA_FPROT2_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT2_PROT. */ -#define BS_FTFA_FPROT2_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT2_PROT. */ - -/*! @brief Read current value of the FTFA_FPROT2_PROT field. */ -#define BR_FTFA_FPROT2_PROT(x) (HW_FTFA_FPROT2(x).U) - -/*! @brief Format value for bitfield FTFA_FPROT2_PROT. */ -#define BF_FTFA_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT2_PROT) & BM_FTFA_FPROT2_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFA_FPROT2_PROT(x, v) (HW_FTFA_FPROT2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FPROT1 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FPROT1 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which logical program flash regions are protected - * from program and erase operations. Protected flash regions cannot have their - * content changed; that is, these regions cannot be programmed and cannot be - * erased by any flash command. Unprotected regions can be changed by program and - * erase operations. The four FPROT registers allow up to 32 protectable regions. - * Each bit protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit - * protects 1 KB . For configurations with 24 KB of program flash memory or less, - * FPROT0 is not used. For configurations with 16 KB of program flash memory or - * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, - * FPROT2 is not used. The bitfields are defined in each register as follows: - * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] - * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset - * sequence, the FPROT registers are loaded with the contents of the program flash - * protection bytes in the Flash Configuration Field as indicated in the following - * table. Program flash protection register Flash Configuration Field offset - * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the - * program flash protection that is loaded during the reset sequence, unprotect the - * sector of program flash memory that contains the Flash Configuration Field. Then, - * reprogram the program flash protection byte. - */ -typedef union _hw_ftfa_fprot1 -{ - uint8_t U; - struct _hw_ftfa_fprot1_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfa_fprot1_t; - -/*! - * @name Constants and macros for entire FTFA_FPROT1 register - */ -/*@{*/ -#define HW_FTFA_FPROT1_ADDR(x) ((x) + 0x12U) - -#define HW_FTFA_FPROT1(x) (*(__IO hw_ftfa_fprot1_t *) HW_FTFA_FPROT1_ADDR(x)) -#define HW_FTFA_FPROT1_RD(x) (HW_FTFA_FPROT1(x).U) -#define HW_FTFA_FPROT1_WR(x, v) (HW_FTFA_FPROT1(x).U = (v)) -#define HW_FTFA_FPROT1_SET(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) | (v))) -#define HW_FTFA_FPROT1_CLR(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) & ~(v))) -#define HW_FTFA_FPROT1_TOG(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FPROT1 bitfields - */ - -/*! - * @name Register FTFA_FPROT1, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. Each bit in the 32-bit protection - * register represents 1/32 of the total program flash except for configurations where - * program flash memory is less than 32 KB. For configurations with less than 32 - * KB of program flash memory, each assigned bit represents 1 KB. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFA_FPROT1_PROT (0U) /*!< Bit position for FTFA_FPROT1_PROT. */ -#define BM_FTFA_FPROT1_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT1_PROT. */ -#define BS_FTFA_FPROT1_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT1_PROT. */ - -/*! @brief Read current value of the FTFA_FPROT1_PROT field. */ -#define BR_FTFA_FPROT1_PROT(x) (HW_FTFA_FPROT1(x).U) - -/*! @brief Format value for bitfield FTFA_FPROT1_PROT. */ -#define BF_FTFA_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT1_PROT) & BM_FTFA_FPROT1_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFA_FPROT1_PROT(x, v) (HW_FTFA_FPROT1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FPROT0 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FPROT0 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which logical program flash regions are protected - * from program and erase operations. Protected flash regions cannot have their - * content changed; that is, these regions cannot be programmed and cannot be - * erased by any flash command. Unprotected regions can be changed by program and - * erase operations. The four FPROT registers allow up to 32 protectable regions. - * Each bit protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit - * protects 1 KB . For configurations with 24 KB of program flash memory or less, - * FPROT0 is not used. For configurations with 16 KB of program flash memory or - * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, - * FPROT2 is not used. The bitfields are defined in each register as follows: - * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] - * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset - * sequence, the FPROT registers are loaded with the contents of the program flash - * protection bytes in the Flash Configuration Field as indicated in the following - * table. Program flash protection register Flash Configuration Field offset - * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the - * program flash protection that is loaded during the reset sequence, unprotect the - * sector of program flash memory that contains the Flash Configuration Field. Then, - * reprogram the program flash protection byte. - */ -typedef union _hw_ftfa_fprot0 -{ - uint8_t U; - struct _hw_ftfa_fprot0_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfa_fprot0_t; - -/*! - * @name Constants and macros for entire FTFA_FPROT0 register - */ -/*@{*/ -#define HW_FTFA_FPROT0_ADDR(x) ((x) + 0x13U) - -#define HW_FTFA_FPROT0(x) (*(__IO hw_ftfa_fprot0_t *) HW_FTFA_FPROT0_ADDR(x)) -#define HW_FTFA_FPROT0_RD(x) (HW_FTFA_FPROT0(x).U) -#define HW_FTFA_FPROT0_WR(x, v) (HW_FTFA_FPROT0(x).U = (v)) -#define HW_FTFA_FPROT0_SET(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) | (v))) -#define HW_FTFA_FPROT0_CLR(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) & ~(v))) -#define HW_FTFA_FPROT0_TOG(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FPROT0 bitfields - */ - -/*! - * @name Register FTFA_FPROT0, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. Each bit in the 32-bit protection - * register represents 1/32 of the total program flash except for configurations where - * program flash memory is less than 32 KB. For configurations with less than 32 - * KB of program flash memory, each assigned bit represents 1 KB. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFA_FPROT0_PROT (0U) /*!< Bit position for FTFA_FPROT0_PROT. */ -#define BM_FTFA_FPROT0_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT0_PROT. */ -#define BS_FTFA_FPROT0_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT0_PROT. */ - -/*! @brief Read current value of the FTFA_FPROT0_PROT field. */ -#define BR_FTFA_FPROT0_PROT(x) (HW_FTFA_FPROT0(x).U) - -/*! @brief Format value for bitfield FTFA_FPROT0_PROT. */ -#define BF_FTFA_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT0_PROT) & BM_FTFA_FPROT0_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFA_FPROT0_PROT(x, v) (HW_FTFA_FPROT0_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCH3 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCH3 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xacch3 -{ - uint8_t U; - struct _hw_ftfa_xacch3_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xacch3_t; - -/*! - * @name Constants and macros for entire FTFA_XACCH3 register - */ -/*@{*/ -#define HW_FTFA_XACCH3_ADDR(x) ((x) + 0x18U) - -#define HW_FTFA_XACCH3(x) (*(__I hw_ftfa_xacch3_t *) HW_FTFA_XACCH3_ADDR(x)) -#define HW_FTFA_XACCH3_RD(x) (HW_FTFA_XACCH3(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCH3 bitfields - */ - -/*! - * @name Register FTFA_XACCH3, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCH3_XA (0U) /*!< Bit position for FTFA_XACCH3_XA. */ -#define BM_FTFA_XACCH3_XA (0xFFU) /*!< Bit mask for FTFA_XACCH3_XA. */ -#define BS_FTFA_XACCH3_XA (8U) /*!< Bit field size in bits for FTFA_XACCH3_XA. */ - -/*! @brief Read current value of the FTFA_XACCH3_XA field. */ -#define BR_FTFA_XACCH3_XA(x) (HW_FTFA_XACCH3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCH2 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCH2 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xacch2 -{ - uint8_t U; - struct _hw_ftfa_xacch2_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xacch2_t; - -/*! - * @name Constants and macros for entire FTFA_XACCH2 register - */ -/*@{*/ -#define HW_FTFA_XACCH2_ADDR(x) ((x) + 0x19U) - -#define HW_FTFA_XACCH2(x) (*(__I hw_ftfa_xacch2_t *) HW_FTFA_XACCH2_ADDR(x)) -#define HW_FTFA_XACCH2_RD(x) (HW_FTFA_XACCH2(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCH2 bitfields - */ - -/*! - * @name Register FTFA_XACCH2, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCH2_XA (0U) /*!< Bit position for FTFA_XACCH2_XA. */ -#define BM_FTFA_XACCH2_XA (0xFFU) /*!< Bit mask for FTFA_XACCH2_XA. */ -#define BS_FTFA_XACCH2_XA (8U) /*!< Bit field size in bits for FTFA_XACCH2_XA. */ - -/*! @brief Read current value of the FTFA_XACCH2_XA field. */ -#define BR_FTFA_XACCH2_XA(x) (HW_FTFA_XACCH2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCH1 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCH1 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xacch1 -{ - uint8_t U; - struct _hw_ftfa_xacch1_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xacch1_t; - -/*! - * @name Constants and macros for entire FTFA_XACCH1 register - */ -/*@{*/ -#define HW_FTFA_XACCH1_ADDR(x) ((x) + 0x1AU) - -#define HW_FTFA_XACCH1(x) (*(__I hw_ftfa_xacch1_t *) HW_FTFA_XACCH1_ADDR(x)) -#define HW_FTFA_XACCH1_RD(x) (HW_FTFA_XACCH1(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCH1 bitfields - */ - -/*! - * @name Register FTFA_XACCH1, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCH1_XA (0U) /*!< Bit position for FTFA_XACCH1_XA. */ -#define BM_FTFA_XACCH1_XA (0xFFU) /*!< Bit mask for FTFA_XACCH1_XA. */ -#define BS_FTFA_XACCH1_XA (8U) /*!< Bit field size in bits for FTFA_XACCH1_XA. */ - -/*! @brief Read current value of the FTFA_XACCH1_XA field. */ -#define BR_FTFA_XACCH1_XA(x) (HW_FTFA_XACCH1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCH0 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCH0 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xacch0 -{ - uint8_t U; - struct _hw_ftfa_xacch0_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xacch0_t; - -/*! - * @name Constants and macros for entire FTFA_XACCH0 register - */ -/*@{*/ -#define HW_FTFA_XACCH0_ADDR(x) ((x) + 0x1BU) - -#define HW_FTFA_XACCH0(x) (*(__I hw_ftfa_xacch0_t *) HW_FTFA_XACCH0_ADDR(x)) -#define HW_FTFA_XACCH0_RD(x) (HW_FTFA_XACCH0(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCH0 bitfields - */ - -/*! - * @name Register FTFA_XACCH0, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCH0_XA (0U) /*!< Bit position for FTFA_XACCH0_XA. */ -#define BM_FTFA_XACCH0_XA (0xFFU) /*!< Bit mask for FTFA_XACCH0_XA. */ -#define BS_FTFA_XACCH0_XA (8U) /*!< Bit field size in bits for FTFA_XACCH0_XA. */ - -/*! @brief Read current value of the FTFA_XACCH0_XA field. */ -#define BR_FTFA_XACCH0_XA(x) (HW_FTFA_XACCH0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCL3 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCL3 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xaccl3 -{ - uint8_t U; - struct _hw_ftfa_xaccl3_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xaccl3_t; - -/*! - * @name Constants and macros for entire FTFA_XACCL3 register - */ -/*@{*/ -#define HW_FTFA_XACCL3_ADDR(x) ((x) + 0x1CU) - -#define HW_FTFA_XACCL3(x) (*(__I hw_ftfa_xaccl3_t *) HW_FTFA_XACCL3_ADDR(x)) -#define HW_FTFA_XACCL3_RD(x) (HW_FTFA_XACCL3(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCL3 bitfields - */ - -/*! - * @name Register FTFA_XACCL3, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCL3_XA (0U) /*!< Bit position for FTFA_XACCL3_XA. */ -#define BM_FTFA_XACCL3_XA (0xFFU) /*!< Bit mask for FTFA_XACCL3_XA. */ -#define BS_FTFA_XACCL3_XA (8U) /*!< Bit field size in bits for FTFA_XACCL3_XA. */ - -/*! @brief Read current value of the FTFA_XACCL3_XA field. */ -#define BR_FTFA_XACCL3_XA(x) (HW_FTFA_XACCL3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCL2 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCL2 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xaccl2 -{ - uint8_t U; - struct _hw_ftfa_xaccl2_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xaccl2_t; - -/*! - * @name Constants and macros for entire FTFA_XACCL2 register - */ -/*@{*/ -#define HW_FTFA_XACCL2_ADDR(x) ((x) + 0x1DU) - -#define HW_FTFA_XACCL2(x) (*(__I hw_ftfa_xaccl2_t *) HW_FTFA_XACCL2_ADDR(x)) -#define HW_FTFA_XACCL2_RD(x) (HW_FTFA_XACCL2(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCL2 bitfields - */ - -/*! - * @name Register FTFA_XACCL2, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCL2_XA (0U) /*!< Bit position for FTFA_XACCL2_XA. */ -#define BM_FTFA_XACCL2_XA (0xFFU) /*!< Bit mask for FTFA_XACCL2_XA. */ -#define BS_FTFA_XACCL2_XA (8U) /*!< Bit field size in bits for FTFA_XACCL2_XA. */ - -/*! @brief Read current value of the FTFA_XACCL2_XA field. */ -#define BR_FTFA_XACCL2_XA(x) (HW_FTFA_XACCL2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCL1 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCL1 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xaccl1 -{ - uint8_t U; - struct _hw_ftfa_xaccl1_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xaccl1_t; - -/*! - * @name Constants and macros for entire FTFA_XACCL1 register - */ -/*@{*/ -#define HW_FTFA_XACCL1_ADDR(x) ((x) + 0x1EU) - -#define HW_FTFA_XACCL1(x) (*(__I hw_ftfa_xaccl1_t *) HW_FTFA_XACCL1_ADDR(x)) -#define HW_FTFA_XACCL1_RD(x) (HW_FTFA_XACCL1(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCL1 bitfields - */ - -/*! - * @name Register FTFA_XACCL1, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCL1_XA (0U) /*!< Bit position for FTFA_XACCL1_XA. */ -#define BM_FTFA_XACCL1_XA (0xFFU) /*!< Bit mask for FTFA_XACCL1_XA. */ -#define BS_FTFA_XACCL1_XA (8U) /*!< Bit field size in bits for FTFA_XACCL1_XA. */ - -/*! @brief Read current value of the FTFA_XACCL1_XA field. */ -#define BR_FTFA_XACCL1_XA(x) (HW_FTFA_XACCL1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_XACCL0 - Execute-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_XACCL0 - Execute-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The XACC registers define which logical program flash segments are restricted - * to data read or execute only or both data and instruction fetches. The eight - * XACC registers allow up to 64 restricted segments of equal memory size. - * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] - * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 - * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC - * registers are loaded with the logical AND of Program Flash IFR addresses A and B - * as indicated in the following table. Execute-only access register Program - * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA - * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 - * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the - * execute-only access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_xaccl0 -{ - uint8_t U; - struct _hw_ftfa_xaccl0_bitfields - { - uint8_t XA : 8; /*!< [7:0] Execute-only access control */ - } B; -} hw_ftfa_xaccl0_t; - -/*! - * @name Constants and macros for entire FTFA_XACCL0 register - */ -/*@{*/ -#define HW_FTFA_XACCL0_ADDR(x) ((x) + 0x1FU) - -#define HW_FTFA_XACCL0(x) (*(__I hw_ftfa_xaccl0_t *) HW_FTFA_XACCL0_ADDR(x)) -#define HW_FTFA_XACCL0_RD(x) (HW_FTFA_XACCL0(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_XACCL0 bitfields - */ - -/*! - * @name Register FTFA_XACCL0, field XA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in execute mode only (as an - * instruction fetch) - * - 1 - Associated segment is accessible as data or in execute mode - */ -/*@{*/ -#define BP_FTFA_XACCL0_XA (0U) /*!< Bit position for FTFA_XACCL0_XA. */ -#define BM_FTFA_XACCL0_XA (0xFFU) /*!< Bit mask for FTFA_XACCL0_XA. */ -#define BS_FTFA_XACCL0_XA (8U) /*!< Bit field size in bits for FTFA_XACCL0_XA. */ - -/*! @brief Read current value of the FTFA_XACCL0_XA field. */ -#define BR_FTFA_XACCL0_XA(x) (HW_FTFA_XACCL0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCH3 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCH3 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_sacch3 -{ - uint8_t U; - struct _hw_ftfa_sacch3_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_sacch3_t; - -/*! - * @name Constants and macros for entire FTFA_SACCH3 register - */ -/*@{*/ -#define HW_FTFA_SACCH3_ADDR(x) ((x) + 0x20U) - -#define HW_FTFA_SACCH3(x) (*(__I hw_ftfa_sacch3_t *) HW_FTFA_SACCH3_ADDR(x)) -#define HW_FTFA_SACCH3_RD(x) (HW_FTFA_SACCH3(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCH3 bitfields - */ - -/*! - * @name Register FTFA_SACCH3, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCH3_SA (0U) /*!< Bit position for FTFA_SACCH3_SA. */ -#define BM_FTFA_SACCH3_SA (0xFFU) /*!< Bit mask for FTFA_SACCH3_SA. */ -#define BS_FTFA_SACCH3_SA (8U) /*!< Bit field size in bits for FTFA_SACCH3_SA. */ - -/*! @brief Read current value of the FTFA_SACCH3_SA field. */ -#define BR_FTFA_SACCH3_SA(x) (HW_FTFA_SACCH3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCH2 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCH2 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_sacch2 -{ - uint8_t U; - struct _hw_ftfa_sacch2_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_sacch2_t; - -/*! - * @name Constants and macros for entire FTFA_SACCH2 register - */ -/*@{*/ -#define HW_FTFA_SACCH2_ADDR(x) ((x) + 0x21U) - -#define HW_FTFA_SACCH2(x) (*(__I hw_ftfa_sacch2_t *) HW_FTFA_SACCH2_ADDR(x)) -#define HW_FTFA_SACCH2_RD(x) (HW_FTFA_SACCH2(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCH2 bitfields - */ - -/*! - * @name Register FTFA_SACCH2, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCH2_SA (0U) /*!< Bit position for FTFA_SACCH2_SA. */ -#define BM_FTFA_SACCH2_SA (0xFFU) /*!< Bit mask for FTFA_SACCH2_SA. */ -#define BS_FTFA_SACCH2_SA (8U) /*!< Bit field size in bits for FTFA_SACCH2_SA. */ - -/*! @brief Read current value of the FTFA_SACCH2_SA field. */ -#define BR_FTFA_SACCH2_SA(x) (HW_FTFA_SACCH2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCH1 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCH1 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_sacch1 -{ - uint8_t U; - struct _hw_ftfa_sacch1_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_sacch1_t; - -/*! - * @name Constants and macros for entire FTFA_SACCH1 register - */ -/*@{*/ -#define HW_FTFA_SACCH1_ADDR(x) ((x) + 0x22U) - -#define HW_FTFA_SACCH1(x) (*(__I hw_ftfa_sacch1_t *) HW_FTFA_SACCH1_ADDR(x)) -#define HW_FTFA_SACCH1_RD(x) (HW_FTFA_SACCH1(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCH1 bitfields - */ - -/*! - * @name Register FTFA_SACCH1, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCH1_SA (0U) /*!< Bit position for FTFA_SACCH1_SA. */ -#define BM_FTFA_SACCH1_SA (0xFFU) /*!< Bit mask for FTFA_SACCH1_SA. */ -#define BS_FTFA_SACCH1_SA (8U) /*!< Bit field size in bits for FTFA_SACCH1_SA. */ - -/*! @brief Read current value of the FTFA_SACCH1_SA field. */ -#define BR_FTFA_SACCH1_SA(x) (HW_FTFA_SACCH1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCH0 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCH0 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_sacch0 -{ - uint8_t U; - struct _hw_ftfa_sacch0_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_sacch0_t; - -/*! - * @name Constants and macros for entire FTFA_SACCH0 register - */ -/*@{*/ -#define HW_FTFA_SACCH0_ADDR(x) ((x) + 0x23U) - -#define HW_FTFA_SACCH0(x) (*(__I hw_ftfa_sacch0_t *) HW_FTFA_SACCH0_ADDR(x)) -#define HW_FTFA_SACCH0_RD(x) (HW_FTFA_SACCH0(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCH0 bitfields - */ - -/*! - * @name Register FTFA_SACCH0, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCH0_SA (0U) /*!< Bit position for FTFA_SACCH0_SA. */ -#define BM_FTFA_SACCH0_SA (0xFFU) /*!< Bit mask for FTFA_SACCH0_SA. */ -#define BS_FTFA_SACCH0_SA (8U) /*!< Bit field size in bits for FTFA_SACCH0_SA. */ - -/*! @brief Read current value of the FTFA_SACCH0_SA field. */ -#define BR_FTFA_SACCH0_SA(x) (HW_FTFA_SACCH0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCL3 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCL3 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_saccl3 -{ - uint8_t U; - struct _hw_ftfa_saccl3_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_saccl3_t; - -/*! - * @name Constants and macros for entire FTFA_SACCL3 register - */ -/*@{*/ -#define HW_FTFA_SACCL3_ADDR(x) ((x) + 0x24U) - -#define HW_FTFA_SACCL3(x) (*(__I hw_ftfa_saccl3_t *) HW_FTFA_SACCL3_ADDR(x)) -#define HW_FTFA_SACCL3_RD(x) (HW_FTFA_SACCL3(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCL3 bitfields - */ - -/*! - * @name Register FTFA_SACCL3, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCL3_SA (0U) /*!< Bit position for FTFA_SACCL3_SA. */ -#define BM_FTFA_SACCL3_SA (0xFFU) /*!< Bit mask for FTFA_SACCL3_SA. */ -#define BS_FTFA_SACCL3_SA (8U) /*!< Bit field size in bits for FTFA_SACCL3_SA. */ - -/*! @brief Read current value of the FTFA_SACCL3_SA field. */ -#define BR_FTFA_SACCL3_SA(x) (HW_FTFA_SACCL3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCL2 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCL2 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_saccl2 -{ - uint8_t U; - struct _hw_ftfa_saccl2_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_saccl2_t; - -/*! - * @name Constants and macros for entire FTFA_SACCL2 register - */ -/*@{*/ -#define HW_FTFA_SACCL2_ADDR(x) ((x) + 0x25U) - -#define HW_FTFA_SACCL2(x) (*(__I hw_ftfa_saccl2_t *) HW_FTFA_SACCL2_ADDR(x)) -#define HW_FTFA_SACCL2_RD(x) (HW_FTFA_SACCL2(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCL2 bitfields - */ - -/*! - * @name Register FTFA_SACCL2, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCL2_SA (0U) /*!< Bit position for FTFA_SACCL2_SA. */ -#define BM_FTFA_SACCL2_SA (0xFFU) /*!< Bit mask for FTFA_SACCL2_SA. */ -#define BS_FTFA_SACCL2_SA (8U) /*!< Bit field size in bits for FTFA_SACCL2_SA. */ - -/*! @brief Read current value of the FTFA_SACCL2_SA field. */ -#define BR_FTFA_SACCL2_SA(x) (HW_FTFA_SACCL2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCL1 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCL1 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_saccl1 -{ - uint8_t U; - struct _hw_ftfa_saccl1_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_saccl1_t; - -/*! - * @name Constants and macros for entire FTFA_SACCL1 register - */ -/*@{*/ -#define HW_FTFA_SACCL1_ADDR(x) ((x) + 0x26U) - -#define HW_FTFA_SACCL1(x) (*(__I hw_ftfa_saccl1_t *) HW_FTFA_SACCL1_ADDR(x)) -#define HW_FTFA_SACCL1_RD(x) (HW_FTFA_SACCL1(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCL1 bitfields - */ - -/*! - * @name Register FTFA_SACCL1, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCL1_SA (0U) /*!< Bit position for FTFA_SACCL1_SA. */ -#define BM_FTFA_SACCL1_SA (0xFFU) /*!< Bit mask for FTFA_SACCL1_SA. */ -#define BS_FTFA_SACCL1_SA (8U) /*!< Bit field size in bits for FTFA_SACCL1_SA. */ - -/*! @brief Read current value of the FTFA_SACCL1_SA field. */ -#define BR_FTFA_SACCL1_SA(x) (HW_FTFA_SACCL1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_SACCL0 - Supervisor-only Access Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFA_SACCL0 - Supervisor-only Access Registers (RO) - * - * Reset value: 0x00U - * - * The SACC registers define which logical program flash segments are restricted - * to supervisor only or user and supervisor access. The eight SACC registers - * allow up to 64 restricted segments of equal memory size. Supervisor-only access - * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 - * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] - * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are - * loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Supervisor-only access register Program Flash IFR - * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 - * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD - * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only - * access control fields that are loaded during the reset sequence. - */ -typedef union _hw_ftfa_saccl0 -{ - uint8_t U; - struct _hw_ftfa_saccl0_bitfields - { - uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */ - } B; -} hw_ftfa_saccl0_t; - -/*! - * @name Constants and macros for entire FTFA_SACCL0 register - */ -/*@{*/ -#define HW_FTFA_SACCL0_ADDR(x) ((x) + 0x27U) - -#define HW_FTFA_SACCL0(x) (*(__I hw_ftfa_saccl0_t *) HW_FTFA_SACCL0_ADDR(x)) -#define HW_FTFA_SACCL0_RD(x) (HW_FTFA_SACCL0(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_SACCL0 bitfields - */ - -/*! - * @name Register FTFA_SACCL0, field SA[7:0] (RO) - * - * Values: - * - 0 - Associated segment is accessible in supervisor mode only - * - 1 - Associated segment is accessible in user or supervisor mode - */ -/*@{*/ -#define BP_FTFA_SACCL0_SA (0U) /*!< Bit position for FTFA_SACCL0_SA. */ -#define BM_FTFA_SACCL0_SA (0xFFU) /*!< Bit mask for FTFA_SACCL0_SA. */ -#define BS_FTFA_SACCL0_SA (8U) /*!< Bit field size in bits for FTFA_SACCL0_SA. */ - -/*! @brief Read current value of the FTFA_SACCL0_SA field. */ -#define BR_FTFA_SACCL0_SA(x) (HW_FTFA_SACCL0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FACSS - Flash Access Segment Size Register - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FACSS - Flash Access Segment Size Register (RO) - * - * Reset value: 0x00U - * - * The flash access segment size register determines which bits in the address - * are used to index into the SACC and XACC bitmaps to get the appropriate - * permission flags. All bits in the register are read-only. The contents of this - * register are loaded during the reset sequence. - */ -typedef union _hw_ftfa_facss -{ - uint8_t U; - struct _hw_ftfa_facss_bitfields - { - uint8_t SGSIZE : 8; /*!< [7:0] Segment Size */ - } B; -} hw_ftfa_facss_t; - -/*! - * @name Constants and macros for entire FTFA_FACSS register - */ -/*@{*/ -#define HW_FTFA_FACSS_ADDR(x) ((x) + 0x28U) - -#define HW_FTFA_FACSS(x) (*(__I hw_ftfa_facss_t *) HW_FTFA_FACSS_ADDR(x)) -#define HW_FTFA_FACSS_RD(x) (HW_FTFA_FACSS(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FACSS bitfields - */ - -/*! - * @name Register FTFA_FACSS, field SGSIZE[7:0] (RO) - * - * The segment size is a fixed value based on the available program flash size - * divided by NUMSG. Program Flash Size Segment Size Segment Size Encoding 64 - * KBytes 2 KBytes 0x3 128 KBytes 4 KBytes 0x4 160 KBytes 4 KBytes 0x4 256 KBytes 4 - * KBytes 0x4 512 KBytes 8 KBytes 0x5 - */ -/*@{*/ -#define BP_FTFA_FACSS_SGSIZE (0U) /*!< Bit position for FTFA_FACSS_SGSIZE. */ -#define BM_FTFA_FACSS_SGSIZE (0xFFU) /*!< Bit mask for FTFA_FACSS_SGSIZE. */ -#define BS_FTFA_FACSS_SGSIZE (8U) /*!< Bit field size in bits for FTFA_FACSS_SGSIZE. */ - -/*! @brief Read current value of the FTFA_FACSS_SGSIZE field. */ -#define BR_FTFA_FACSS_SGSIZE(x) (HW_FTFA_FACSS(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFA_FACSN - Flash Access Segment Number Register - ******************************************************************************/ - -/*! - * @brief HW_FTFA_FACSN - Flash Access Segment Number Register (RO) - * - * Reset value: 0x00U - * - * The flash access segment number register provides the number of program flash - * segments that are available for XACC and SACC permissions. All bits in the - * register are read-only. The contents of this register are loaded during the - * reset sequence. - */ -typedef union _hw_ftfa_facsn -{ - uint8_t U; - struct _hw_ftfa_facsn_bitfields - { - uint8_t NUMSG : 8; /*!< [7:0] Number of Segments Indicator */ - } B; -} hw_ftfa_facsn_t; - -/*! - * @name Constants and macros for entire FTFA_FACSN register - */ -/*@{*/ -#define HW_FTFA_FACSN_ADDR(x) ((x) + 0x2BU) - -#define HW_FTFA_FACSN(x) (*(__I hw_ftfa_facsn_t *) HW_FTFA_FACSN_ADDR(x)) -#define HW_FTFA_FACSN_RD(x) (HW_FTFA_FACSN(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFA_FACSN bitfields - */ - -/*! - * @name Register FTFA_FACSN, field NUMSG[7:0] (RO) - * - * The NUMSG field indicates the number of equal-sized segments in the program - * flash. - * - * Values: - * - 100000 - Program flash memory is divided into 32 segments (64 Kbytes, 128 - * Kbytes) - * - 101000 - Program flash memory is divided into 40 segments (160 Kbytes) - * - 1000000 - Program flash memory is divided into 64 segments (256 Kbytes, 512 - * Kbytes) - */ -/*@{*/ -#define BP_FTFA_FACSN_NUMSG (0U) /*!< Bit position for FTFA_FACSN_NUMSG. */ -#define BM_FTFA_FACSN_NUMSG (0xFFU) /*!< Bit mask for FTFA_FACSN_NUMSG. */ -#define BS_FTFA_FACSN_NUMSG (8U) /*!< Bit field size in bits for FTFA_FACSN_NUMSG. */ - -/*! @brief Read current value of the FTFA_FACSN_NUMSG field. */ -#define BR_FTFA_FACSN_NUMSG(x) (HW_FTFA_FACSN(x).U) -/*@}*/ - -/******************************************************************************* - * hw_ftfa_t - module struct - ******************************************************************************/ -/*! - * @brief All FTFA module registers. - */ -#pragma pack(1) -typedef struct _hw_ftfa -{ - __IO hw_ftfa_fstat_t FSTAT; /*!< [0x0] Flash Status Register */ - __IO hw_ftfa_fcnfg_t FCNFG; /*!< [0x1] Flash Configuration Register */ - __I hw_ftfa_fsec_t FSEC; /*!< [0x2] Flash Security Register */ - __I hw_ftfa_fopt_t FOPT; /*!< [0x3] Flash Option Register */ - __IO hw_ftfa_fccob3_t FCCOB3; /*!< [0x4] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob2_t FCCOB2; /*!< [0x5] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob1_t FCCOB1; /*!< [0x6] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob0_t FCCOB0; /*!< [0x7] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob7_t FCCOB7; /*!< [0x8] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob6_t FCCOB6; /*!< [0x9] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob5_t FCCOB5; /*!< [0xA] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob4_t FCCOB4; /*!< [0xB] Flash Common Command Object Registers */ - __IO hw_ftfa_fccobb_t FCCOBB; /*!< [0xC] Flash Common Command Object Registers */ - __IO hw_ftfa_fccoba_t FCCOBA; /*!< [0xD] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob9_t FCCOB9; /*!< [0xE] Flash Common Command Object Registers */ - __IO hw_ftfa_fccob8_t FCCOB8; /*!< [0xF] Flash Common Command Object Registers */ - __IO hw_ftfa_fprot3_t FPROT3; /*!< [0x10] Program Flash Protection Registers */ - __IO hw_ftfa_fprot2_t FPROT2; /*!< [0x11] Program Flash Protection Registers */ - __IO hw_ftfa_fprot1_t FPROT1; /*!< [0x12] Program Flash Protection Registers */ - __IO hw_ftfa_fprot0_t FPROT0; /*!< [0x13] Program Flash Protection Registers */ - uint8_t _reserved0[4]; - __I hw_ftfa_xacch3_t XACCH3; /*!< [0x18] Execute-only Access Registers */ - __I hw_ftfa_xacch2_t XACCH2; /*!< [0x19] Execute-only Access Registers */ - __I hw_ftfa_xacch1_t XACCH1; /*!< [0x1A] Execute-only Access Registers */ - __I hw_ftfa_xacch0_t XACCH0; /*!< [0x1B] Execute-only Access Registers */ - __I hw_ftfa_xaccl3_t XACCL3; /*!< [0x1C] Execute-only Access Registers */ - __I hw_ftfa_xaccl2_t XACCL2; /*!< [0x1D] Execute-only Access Registers */ - __I hw_ftfa_xaccl1_t XACCL1; /*!< [0x1E] Execute-only Access Registers */ - __I hw_ftfa_xaccl0_t XACCL0; /*!< [0x1F] Execute-only Access Registers */ - __I hw_ftfa_sacch3_t SACCH3; /*!< [0x20] Supervisor-only Access Registers */ - __I hw_ftfa_sacch2_t SACCH2; /*!< [0x21] Supervisor-only Access Registers */ - __I hw_ftfa_sacch1_t SACCH1; /*!< [0x22] Supervisor-only Access Registers */ - __I hw_ftfa_sacch0_t SACCH0; /*!< [0x23] Supervisor-only Access Registers */ - __I hw_ftfa_saccl3_t SACCL3; /*!< [0x24] Supervisor-only Access Registers */ - __I hw_ftfa_saccl2_t SACCL2; /*!< [0x25] Supervisor-only Access Registers */ - __I hw_ftfa_saccl1_t SACCL1; /*!< [0x26] Supervisor-only Access Registers */ - __I hw_ftfa_saccl0_t SACCL0; /*!< [0x27] Supervisor-only Access Registers */ - __I hw_ftfa_facss_t FACSS; /*!< [0x28] Flash Access Segment Size Register */ - uint8_t _reserved1[2]; - __I hw_ftfa_facsn_t FACSN; /*!< [0x2B] Flash Access Segment Number Register */ -} hw_ftfa_t; -#pragma pack() - -/*! @brief Macro to access all FTFA registers. */ -/*! @param x FTFA module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FTFA(FTFA_BASE). */ -#define HW_FTFA(x) (*(hw_ftfa_t *)(x)) - -#endif /* __HW_FTFA_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h deleted file mode 100644 index 3607a001aaa..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h +++ /dev/null @@ -1,5936 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FTM_REGISTERS_H__ -#define __HW_FTM_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 FTM - * - * FlexTimer Module - * - * Registers defined in this header file: - * - HW_FTM_SC - Status And Control - * - HW_FTM_CNT - Counter - * - HW_FTM_MOD - Modulo - * - HW_FTM_CnSC - Channel (n) Status And Control - * - HW_FTM_CnV - Channel (n) Value - * - HW_FTM_CNTIN - Counter Initial Value - * - HW_FTM_STATUS - Capture And Compare Status - * - HW_FTM_MODE - Features Mode Selection - * - HW_FTM_SYNC - Synchronization - * - HW_FTM_OUTINIT - Initial State For Channels Output - * - HW_FTM_OUTMASK - Output Mask - * - HW_FTM_COMBINE - Function For Linked Channels - * - HW_FTM_DEADTIME - Deadtime Insertion Control - * - HW_FTM_EXTTRIG - FTM External Trigger - * - HW_FTM_POL - Channels Polarity - * - HW_FTM_FMS - Fault Mode Status - * - HW_FTM_FILTER - Input Capture Filter Control - * - HW_FTM_FLTCTRL - Fault Control - * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status - * - HW_FTM_CONF - Configuration - * - HW_FTM_FLTPOL - FTM Fault Input Polarity - * - HW_FTM_SYNCONF - Synchronization Configuration - * - HW_FTM_INVCTRL - FTM Inverting Control - * - HW_FTM_SWOCTRL - FTM Software Output Control - * - HW_FTM_PWMLOAD - FTM PWM Load - * - * - hw_ftm_t - Struct containing all module registers. - */ - -#define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */ -#define HW_FTM0 (0U) /*!< Instance number for FTM0. */ -#define HW_FTM1 (1U) /*!< Instance number for FTM1. */ -#define HW_FTM2 (2U) /*!< Instance number for FTM2. */ -#define HW_FTM3 (3U) /*!< Instance number for FTM3. */ - -/******************************************************************************* - * HW_FTM_SC - Status And Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_SC - Status And Control (RW) - * - * Reset value: 0x00000000U - * - * SC contains the overflow status flag and control bits used to configure the - * interrupt enable, FTM configuration, clock source, and prescaler factor. These - * controls relate to all channels within this module. - */ -typedef union _hw_ftm_sc -{ - uint32_t U; - struct _hw_ftm_sc_bitfields - { - uint32_t PS : 3; /*!< [2:0] Prescale Factor Selection */ - uint32_t CLKS : 2; /*!< [4:3] Clock Source Selection */ - uint32_t CPWMS : 1; /*!< [5] Center-Aligned PWM Select */ - uint32_t TOIE : 1; /*!< [6] Timer Overflow Interrupt Enable */ - uint32_t TOF : 1; /*!< [7] Timer Overflow Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_sc_t; - -/*! - * @name Constants and macros for entire FTM_SC register - */ -/*@{*/ -#define HW_FTM_SC_ADDR(x) ((x) + 0x0U) - -#define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x)) -#define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U) -#define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v)) -#define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v))) -#define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v))) -#define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SC bitfields - */ - -/*! - * @name Register FTM_SC, field PS[2:0] (RW) - * - * Selects one of 8 division factors for the clock source selected by CLKS. The - * new prescaler factor affects the clock source on the next system clock cycle - * after the new value is updated into the register bits. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 000 - Divide by 1 - * - 001 - Divide by 2 - * - 010 - Divide by 4 - * - 011 - Divide by 8 - * - 100 - Divide by 16 - * - 101 - Divide by 32 - * - 110 - Divide by 64 - * - 111 - Divide by 128 - */ -/*@{*/ -#define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */ -#define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */ -#define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */ - -/*! @brief Read current value of the FTM_SC_PS field. */ -#define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS) - -/*! @brief Format value for bitfield FTM_SC_PS. */ -#define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS) - -/*! @brief Set the PS field to a new value. */ -#define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v))) -/*@}*/ - -/*! - * @name Register FTM_SC, field CLKS[4:3] (RW) - * - * Selects one of the three FTM counter clock sources. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 00 - No clock selected. This in effect disables the FTM counter. - * - 01 - System clock - * - 10 - Fixed frequency clock - * - 11 - External clock - */ -/*@{*/ -#define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */ -#define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */ -#define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */ - -/*! @brief Read current value of the FTM_SC_CLKS field. */ -#define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS) - -/*! @brief Format value for bitfield FTM_SC_CLKS. */ -#define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS) - -/*! @brief Set the CLKS field to a new value. */ -#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v))) -/*@}*/ - -/*! - * @name Register FTM_SC, field CPWMS[5] (RW) - * - * Selects CPWM mode. This mode configures the FTM to operate in Up-Down - * Counting mode. This field is write protected. It can be written only when MODE[WPDIS] - * = 1. - * - * Values: - * - 0 - FTM counter operates in Up Counting mode. - * - 1 - FTM counter operates in Up-Down Counting mode. - */ -/*@{*/ -#define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */ -#define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */ -#define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */ - -/*! @brief Read current value of the FTM_SC_CPWMS field. */ -#define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS)) - -/*! @brief Format value for bitfield FTM_SC_CPWMS. */ -#define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS) - -/*! @brief Set the CPWMS field to a new value. */ -#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SC, field TOIE[6] (RW) - * - * Enables FTM overflow interrupts. - * - * Values: - * - 0 - Disable TOF interrupts. Use software polling. - * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one. - */ -/*@{*/ -#define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */ -#define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */ -#define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */ - -/*! @brief Read current value of the FTM_SC_TOIE field. */ -#define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE)) - -/*! @brief Format value for bitfield FTM_SC_TOIE. */ -#define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE) - -/*! @brief Set the TOIE field to a new value. */ -#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SC, field TOF[7] (ROWZ) - * - * Set by hardware when the FTM counter passes the value in the MOD register. - * The TOF bit is cleared by reading the SC register while TOF is set and then - * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow - * occurs between the read and write operations, the write operation has no - * effect; therefore, TOF remains set indicating an overflow has occurred. In this - * case, a TOF interrupt request is not lost due to the clearing sequence for a - * previous TOF. - * - * Values: - * - 0 - FTM counter has not overflowed. - * - 1 - FTM counter has overflowed. - */ -/*@{*/ -#define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */ -#define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */ -#define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */ - -/*! @brief Read current value of the FTM_SC_TOF field. */ -#define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF)) - -/*! @brief Format value for bitfield FTM_SC_TOF. */ -#define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF) - -/*! @brief Set the TOF field to a new value. */ -#define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CNT - Counter - ******************************************************************************/ - -/*! - * @brief HW_FTM_CNT - Counter (RW) - * - * Reset value: 0x00000000U - * - * The CNT register contains the FTM counter value. Reset clears the CNT - * register. Writing any value to COUNT updates the counter with its initial value, - * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you - * may read. - */ -typedef union _hw_ftm_cnt -{ - uint32_t U; - struct _hw_ftm_cnt_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Counter Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_cnt_t; - -/*! - * @name Constants and macros for entire FTM_CNT register - */ -/*@{*/ -#define HW_FTM_CNT_ADDR(x) ((x) + 0x4U) - -#define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x)) -#define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U) -#define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v)) -#define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v))) -#define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v))) -#define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CNT bitfields - */ - -/*! - * @name Register FTM_CNT, field COUNT[15:0] (RW) - */ -/*@{*/ -#define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */ -#define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */ -#define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */ - -/*! @brief Read current value of the FTM_CNT_COUNT field. */ -#define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT) - -/*! @brief Format value for bitfield FTM_CNT_COUNT. */ -#define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT) - -/*! @brief Set the COUNT field to a new value. */ -#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_MOD - Modulo - ******************************************************************************/ - -/*! - * @brief HW_FTM_MOD - Modulo (RW) - * - * Reset value: 0x00000000U - * - * The Modulo register contains the modulo value for the FTM counter. After the - * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at - * the next clock, and the next value of FTM counter depends on the selected - * counting method; see Counter. Writing to the MOD register latches the value into a - * buffer. The MOD register is updated with the value of its write buffer - * according to Registers updated from write buffers. If FTMEN = 0, this write coherency - * mechanism may be manually reset by writing to the SC register whether BDM is - * active or not. Initialize the FTM counter, by writing to CNT, before writing - * to the MOD register to avoid confusion about when the first counter overflow - * will occur. - */ -typedef union _hw_ftm_mod -{ - uint32_t U; - struct _hw_ftm_mod_bitfields - { - uint32_t MOD : 16; /*!< [15:0] */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_mod_t; - -/*! - * @name Constants and macros for entire FTM_MOD register - */ -/*@{*/ -#define HW_FTM_MOD_ADDR(x) ((x) + 0x8U) - -#define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x)) -#define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U) -#define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v)) -#define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v))) -#define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v))) -#define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_MOD bitfields - */ - -/*! - * @name Register FTM_MOD, field MOD[15:0] (RW) - * - * Modulo Value - */ -/*@{*/ -#define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */ -#define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */ -#define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */ - -/*! @brief Read current value of the FTM_MOD_MOD field. */ -#define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD) - -/*! @brief Format value for bitfield FTM_MOD_MOD. */ -#define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD) - -/*! @brief Set the MOD field to a new value. */ -#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CnSC - Channel (n) Status And Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW) - * - * Reset value: 0x00000000U - * - * CnSC contains the channel-interrupt-status flag and control bits used to - * configure the interrupt enable, channel configuration, and pin function. Mode, - * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode - * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general - * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising - * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge - * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set - * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match) - * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true - * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1 - * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on - * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set - * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual - * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge - * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected - * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1 - * Enabled Rising and falling edges - */ -typedef union _hw_ftm_cnsc -{ - uint32_t U; - struct _hw_ftm_cnsc_bitfields - { - uint32_t DMA : 1; /*!< [0] DMA Enable */ - uint32_t ICRST : 1; /*!< [1] FTM counter reset by the selected input - * capture event. */ - uint32_t ELSA : 1; /*!< [2] Edge or Level Select */ - uint32_t ELSB : 1; /*!< [3] Edge or Level Select */ - uint32_t MSA : 1; /*!< [4] Channel Mode Select */ - uint32_t MSB : 1; /*!< [5] Channel Mode Select */ - uint32_t CHIE : 1; /*!< [6] Channel Interrupt Enable */ - uint32_t CHF : 1; /*!< [7] Channel Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_cnsc_t; - -/*! - * @name Constants and macros for entire FTM_CnSC register - */ -/*@{*/ -#define HW_FTM_CnSC_COUNT (8U) - -#define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n))) - -#define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n)) -#define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U) -#define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v)) -#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v))) -#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v))) -#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CnSC bitfields - */ - -/*! - * @name Register FTM_CnSC, field DMA[0] (RW) - * - * Enables DMA transfers for the channel. - * - * Values: - * - 0 - Disable DMA transfers. - * - 1 - Enable DMA transfers. - */ -/*@{*/ -#define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */ -#define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */ -#define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */ - -/*! @brief Read current value of the FTM_CnSC_DMA field. */ -#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA)) - -/*! @brief Format value for bitfield FTM_CnSC_DMA. */ -#define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA) - -/*! @brief Set the DMA field to a new value. */ -#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field ICRST[1] (RW) - * - * FTM counter reset is driven by the selected event of the channel (n) in the - * Input Capture mode. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - FTM counter is not reset when the selected channel (n) input event is - * detected. - * - 1 - FTM counter is reset when the selected channel (n) input event is - * detected. - */ -/*@{*/ -#define BP_FTM_CnSC_ICRST (1U) /*!< Bit position for FTM_CnSC_ICRST. */ -#define BM_FTM_CnSC_ICRST (0x00000002U) /*!< Bit mask for FTM_CnSC_ICRST. */ -#define BS_FTM_CnSC_ICRST (1U) /*!< Bit field size in bits for FTM_CnSC_ICRST. */ - -/*! @brief Read current value of the FTM_CnSC_ICRST field. */ -#define BR_FTM_CnSC_ICRST(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ICRST)) - -/*! @brief Format value for bitfield FTM_CnSC_ICRST. */ -#define BF_FTM_CnSC_ICRST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ICRST) & BM_FTM_CnSC_ICRST) - -/*! @brief Set the ICRST field to a new value. */ -#define BW_FTM_CnSC_ICRST(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ICRST) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field ELSA[2] (RW) - * - * The functionality of ELSB and ELSA depends on the channel mode. See - * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS] - * = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */ -#define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */ -#define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */ - -/*! @brief Read current value of the FTM_CnSC_ELSA field. */ -#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA)) - -/*! @brief Format value for bitfield FTM_CnSC_ELSA. */ -#define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA) - -/*! @brief Set the ELSA field to a new value. */ -#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field ELSB[3] (RW) - * - * The functionality of ELSB and ELSA depends on the channel mode. See - * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS] - * = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */ -#define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */ -#define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */ - -/*! @brief Read current value of the FTM_CnSC_ELSB field. */ -#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB)) - -/*! @brief Format value for bitfield FTM_CnSC_ELSB. */ -#define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB) - -/*! @brief Set the ELSB field to a new value. */ -#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field MSA[4] (RW) - * - * Used for further selections in the channel logic. Its functionality is - * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */ -#define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */ -#define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */ - -/*! @brief Read current value of the FTM_CnSC_MSA field. */ -#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA)) - -/*! @brief Format value for bitfield FTM_CnSC_MSA. */ -#define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA) - -/*! @brief Set the MSA field to a new value. */ -#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field MSB[5] (RW) - * - * Used for further selections in the channel logic. Its functionality is - * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */ -#define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */ -#define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */ - -/*! @brief Read current value of the FTM_CnSC_MSB field. */ -#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB)) - -/*! @brief Format value for bitfield FTM_CnSC_MSB. */ -#define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB) - -/*! @brief Set the MSB field to a new value. */ -#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field CHIE[6] (RW) - * - * Enables channel interrupts. - * - * Values: - * - 0 - Disable channel interrupts. Use software polling. - * - 1 - Enable channel interrupts. - */ -/*@{*/ -#define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */ -#define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */ -#define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */ - -/*! @brief Read current value of the FTM_CnSC_CHIE field. */ -#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE)) - -/*! @brief Format value for bitfield FTM_CnSC_CHIE. */ -#define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE) - -/*! @brief Set the CHIE field to a new value. */ -#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field CHF[7] (ROWZ) - * - * Set by hardware when an event occurs on the channel. CHF is cleared by - * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit. - * Writing a 1 to CHF has no effect. If another event occurs between the read and - * write operations, the write operation has no effect; therefore, CHF remains set - * indicating an event has occurred. In this case a CHF interrupt request is not - * lost due to the clearing sequence for a previous CHF. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */ -#define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */ -#define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */ - -/*! @brief Read current value of the FTM_CnSC_CHF field. */ -#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF)) - -/*! @brief Format value for bitfield FTM_CnSC_CHF. */ -#define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF) - -/*! @brief Set the CHF field to a new value. */ -#define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v)) -/*@}*/ -/******************************************************************************* - * HW_FTM_CnV - Channel (n) Value - ******************************************************************************/ - -/*! - * @brief HW_FTM_CnV - Channel (n) Value (RW) - * - * Reset value: 0x00000000U - * - * These registers contain the captured FTM counter value for the input modes or - * the match value for the output modes. In Input Capture, Capture Test, and - * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes, - * writing to a CnV register latches the value into a buffer. A CnV register is - * updated with the value of its write buffer according to Registers updated from - * write buffers. If FTMEN = 0, this write coherency mechanism may be manually - * reset by writing to the CnSC register whether BDM mode is active or not. - */ -typedef union _hw_ftm_cnv -{ - uint32_t U; - struct _hw_ftm_cnv_bitfields - { - uint32_t VAL : 16; /*!< [15:0] Channel Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_cnv_t; - -/*! - * @name Constants and macros for entire FTM_CnV register - */ -/*@{*/ -#define HW_FTM_CnV_COUNT (8U) - -#define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n))) - -#define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n)) -#define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U) -#define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v)) -#define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v))) -#define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v))) -#define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CnV bitfields - */ - -/*! - * @name Register FTM_CnV, field VAL[15:0] (RW) - * - * Captured FTM counter value of the input modes or the match value for the - * output modes - */ -/*@{*/ -#define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */ -#define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */ -#define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */ - -/*! @brief Read current value of the FTM_CnV_VAL field. */ -#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL) - -/*! @brief Format value for bitfield FTM_CnV_VAL. */ -#define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL) - -/*! @brief Set the VAL field to a new value. */ -#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CNTIN - Counter Initial Value - ******************************************************************************/ - -/*! - * @brief HW_FTM_CNTIN - Counter Initial Value (RW) - * - * Reset value: 0x00000000U - * - * The Counter Initial Value register contains the initial value for the FTM - * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN - * register is updated with the value of its write buffer according to Registers - * updated from write buffers. When the FTM clock is initially selected, by - * writing a non-zero value to the CLKS bits, the FTM counter starts with the value - * 0x0000. To avoid this behavior, before the first write to select the FTM clock, - * write the new value to the the CNTIN register and then initialize the FTM - * counter by writing any value to the CNT register. - */ -typedef union _hw_ftm_cntin -{ - uint32_t U; - struct _hw_ftm_cntin_bitfields - { - uint32_t INIT : 16; /*!< [15:0] */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_cntin_t; - -/*! - * @name Constants and macros for entire FTM_CNTIN register - */ -/*@{*/ -#define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU) - -#define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x)) -#define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U) -#define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v)) -#define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v))) -#define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v))) -#define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CNTIN bitfields - */ - -/*! - * @name Register FTM_CNTIN, field INIT[15:0] (RW) - * - * Initial Value Of The FTM Counter - */ -/*@{*/ -#define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */ -#define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */ -#define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */ - -/*! @brief Read current value of the FTM_CNTIN_INIT field. */ -#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT) - -/*! @brief Format value for bitfield FTM_CNTIN_INIT. */ -#define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT) - -/*! @brief Set the INIT field to a new value. */ -#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_STATUS - Capture And Compare Status - ******************************************************************************/ - -/*! - * @brief HW_FTM_STATUS - Capture And Compare Status (RW) - * - * Reset value: 0x00000000U - * - * The STATUS register contains a copy of the status flag CHnF bit in CnSC for - * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror - * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of - * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to - * STATUS. Hardware sets the individual channel flags when an event occurs on the - * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing - * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event - * occurs between the read and write operations, the write operation has no effect; - * therefore, CHnF remains set indicating an event has occurred. In this case, a - * CHnF interrupt request is not lost due to the clearing sequence for a previous - * CHnF. The STATUS register should be used only in Combine mode. - */ -typedef union _hw_ftm_status -{ - uint32_t U; - struct _hw_ftm_status_bitfields - { - uint32_t CH0F : 1; /*!< [0] Channel 0 Flag */ - uint32_t CH1F : 1; /*!< [1] Channel 1 Flag */ - uint32_t CH2F : 1; /*!< [2] Channel 2 Flag */ - uint32_t CH3F : 1; /*!< [3] Channel 3 Flag */ - uint32_t CH4F : 1; /*!< [4] Channel 4 Flag */ - uint32_t CH5F : 1; /*!< [5] Channel 5 Flag */ - uint32_t CH6F : 1; /*!< [6] Channel 6 Flag */ - uint32_t CH7F : 1; /*!< [7] Channel 7 Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_status_t; - -/*! - * @name Constants and macros for entire FTM_STATUS register - */ -/*@{*/ -#define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U) - -#define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x)) -#define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U) -#define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v)) -#define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v))) -#define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v))) -#define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_STATUS bitfields - */ - -/*! - * @name Register FTM_STATUS, field CH0F[0] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */ -#define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */ -#define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */ - -/*! @brief Read current value of the FTM_STATUS_CH0F field. */ -#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH0F. */ -#define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F) - -/*! @brief Set the CH0F field to a new value. */ -#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH1F[1] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */ -#define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */ -#define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */ - -/*! @brief Read current value of the FTM_STATUS_CH1F field. */ -#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH1F. */ -#define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F) - -/*! @brief Set the CH1F field to a new value. */ -#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH2F[2] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */ -#define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */ -#define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */ - -/*! @brief Read current value of the FTM_STATUS_CH2F field. */ -#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH2F. */ -#define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F) - -/*! @brief Set the CH2F field to a new value. */ -#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH3F[3] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */ -#define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */ -#define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */ - -/*! @brief Read current value of the FTM_STATUS_CH3F field. */ -#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH3F. */ -#define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F) - -/*! @brief Set the CH3F field to a new value. */ -#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH4F[4] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */ -#define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */ -#define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */ - -/*! @brief Read current value of the FTM_STATUS_CH4F field. */ -#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH4F. */ -#define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F) - -/*! @brief Set the CH4F field to a new value. */ -#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH5F[5] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */ -#define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */ -#define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */ - -/*! @brief Read current value of the FTM_STATUS_CH5F field. */ -#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH5F. */ -#define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F) - -/*! @brief Set the CH5F field to a new value. */ -#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH6F[6] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */ -#define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */ -#define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */ - -/*! @brief Read current value of the FTM_STATUS_CH6F field. */ -#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH6F. */ -#define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F) - -/*! @brief Set the CH6F field to a new value. */ -#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH7F[7] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */ -#define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */ -#define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */ - -/*! @brief Read current value of the FTM_STATUS_CH7F field. */ -#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH7F. */ -#define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F) - -/*! @brief Set the CH7F field to a new value. */ -#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_MODE - Features Mode Selection - ******************************************************************************/ - -/*! - * @brief HW_FTM_MODE - Features Mode Selection (RW) - * - * Reset value: 0x00000004U - * - * This register contains the global enable bit for FTM-specific features and - * the control bits used to configure: Fault control mode and interrupt Capture - * Test mode PWM synchronization Write protection Channel output initialization - * These controls relate to all channels within this module. - */ -typedef union _hw_ftm_mode -{ - uint32_t U; - struct _hw_ftm_mode_bitfields - { - uint32_t FTMEN : 1; /*!< [0] FTM Enable */ - uint32_t INIT : 1; /*!< [1] Initialize The Channels Output */ - uint32_t WPDIS : 1; /*!< [2] Write Protection Disable */ - uint32_t PWMSYNC : 1; /*!< [3] PWM Synchronization Mode */ - uint32_t CAPTEST : 1; /*!< [4] Capture Test Mode Enable */ - uint32_t FAULTM : 2; /*!< [6:5] Fault Control Mode */ - uint32_t FAULTIE : 1; /*!< [7] Fault Interrupt Enable */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_mode_t; - -/*! - * @name Constants and macros for entire FTM_MODE register - */ -/*@{*/ -#define HW_FTM_MODE_ADDR(x) ((x) + 0x54U) - -#define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x)) -#define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U) -#define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v)) -#define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v))) -#define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v))) -#define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_MODE bitfields - */ - -/*! - * @name Register FTM_MODE, field FTMEN[0] (RW) - * - * This field is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Only the TPM-compatible registers (first set of registers) can be used - * without any restriction. Do not use the FTM-specific registers. - * - 1 - All registers including the FTM-specific registers (second set of - * registers) are available for use with no restrictions. - */ -/*@{*/ -#define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */ -#define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */ -#define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */ - -/*! @brief Read current value of the FTM_MODE_FTMEN field. */ -#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN)) - -/*! @brief Format value for bitfield FTM_MODE_FTMEN. */ -#define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN) - -/*! @brief Set the FTMEN field to a new value. */ -#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field INIT[1] (RW) - * - * When a 1 is written to INIT bit the channels output is initialized according - * to the state of their corresponding bit in the OUTINIT register. Writing a 0 - * to INIT bit has no effect. The INIT bit is always read as 0. - */ -/*@{*/ -#define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */ -#define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */ -#define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */ - -/*! @brief Read current value of the FTM_MODE_INIT field. */ -#define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT)) - -/*! @brief Format value for bitfield FTM_MODE_INIT. */ -#define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT) - -/*! @brief Set the INIT field to a new value. */ -#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field WPDIS[2] (RW) - * - * When write protection is enabled (WPDIS = 0), write protected bits cannot be - * written. When write protection is disabled (WPDIS = 1), write protected bits - * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared - * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then - * 1 is written to WPDIS. Writing 0 to WPDIS has no effect. - * - * Values: - * - 0 - Write protection is enabled. - * - 1 - Write protection is disabled. - */ -/*@{*/ -#define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */ -#define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */ -#define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */ - -/*! @brief Read current value of the FTM_MODE_WPDIS field. */ -#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS)) - -/*! @brief Format value for bitfield FTM_MODE_WPDIS. */ -#define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS) - -/*! @brief Set the WPDIS field to a new value. */ -#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field PWMSYNC[3] (RW) - * - * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter - * synchronization. See PWM synchronization. The PWMSYNC bit configures the - * synchronization when SYNCMODE is 0. - * - * Values: - * - 0 - No restrictions. Software and hardware triggers can be used by MOD, - * CnV, OUTMASK, and FTM counter synchronization. - * - 1 - Software trigger can only be used by MOD and CnV synchronization, and - * hardware triggers can only be used by OUTMASK and FTM counter - * synchronization. - */ -/*@{*/ -#define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */ -#define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */ -#define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */ - -/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */ -#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC)) - -/*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */ -#define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC) - -/*! @brief Set the PWMSYNC field to a new value. */ -#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field CAPTEST[4] (RW) - * - * Enables the capture test mode. This field is write protected. It can be - * written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Capture test mode is disabled. - * - 1 - Capture test mode is enabled. - */ -/*@{*/ -#define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */ -#define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */ -#define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */ - -/*! @brief Read current value of the FTM_MODE_CAPTEST field. */ -#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST)) - -/*! @brief Format value for bitfield FTM_MODE_CAPTEST. */ -#define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST) - -/*! @brief Set the CAPTEST field to a new value. */ -#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field FAULTM[6:5] (RW) - * - * Defines the FTM fault control mode. This field is write protected. It can be - * written only when MODE[WPDIS] = 1. - * - * Values: - * - 00 - Fault control is disabled for all channels. - * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and - * 6), and the selected mode is the manual fault clearing. - * - 10 - Fault control is enabled for all channels, and the selected mode is - * the manual fault clearing. - * - 11 - Fault control is enabled for all channels, and the selected mode is - * the automatic fault clearing. - */ -/*@{*/ -#define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */ -#define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */ -#define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */ - -/*! @brief Read current value of the FTM_MODE_FAULTM field. */ -#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM) - -/*! @brief Format value for bitfield FTM_MODE_FAULTM. */ -#define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM) - -/*! @brief Set the FAULTM field to a new value. */ -#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v))) -/*@}*/ - -/*! - * @name Register FTM_MODE, field FAULTIE[7] (RW) - * - * Enables the generation of an interrupt when a fault is detected by FTM and - * the FTM fault control is enabled. - * - * Values: - * - 0 - Fault control interrupt is disabled. - * - 1 - Fault control interrupt is enabled. - */ -/*@{*/ -#define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */ -#define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */ -#define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */ - -/*! @brief Read current value of the FTM_MODE_FAULTIE field. */ -#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE)) - -/*! @brief Format value for bitfield FTM_MODE_FAULTIE. */ -#define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE) - -/*! @brief Set the FAULTIE field to a new value. */ -#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_SYNC - Synchronization - ******************************************************************************/ - -/*! - * @brief HW_FTM_SYNC - Synchronization (RW) - * - * Reset value: 0x00000000U - * - * This register configures the PWM synchronization. A synchronization event can - * perform the synchronized update of MOD, CV, and OUTMASK registers with the - * value of their write buffer and the FTM counter initialization. The software - * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a - * potential conflict if used together when SYNCMODE = 0. Use only hardware or - * software triggers but not both at the same time, otherwise unpredictable behavior - * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN - * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across - * all enabled channels simultaneously. The use of the loading point selection - * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2 - * bits, is likely to result in unpredictable behavior. The synchronization - * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF - * register) bits. See PWM synchronization. - */ -typedef union _hw_ftm_sync -{ - uint32_t U; - struct _hw_ftm_sync_bitfields - { - uint32_t CNTMIN : 1; /*!< [0] Minimum Loading Point Enable */ - uint32_t CNTMAX : 1; /*!< [1] Maximum Loading Point Enable */ - uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By - * Synchronization (FTM counter synchronization) */ - uint32_t SYNCHOM : 1; /*!< [3] Output Mask Synchronization */ - uint32_t TRIG0 : 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */ - uint32_t TRIG1 : 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */ - uint32_t TRIG2 : 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */ - uint32_t SWSYNC : 1; /*!< [7] PWM Synchronization Software Trigger */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_sync_t; - -/*! - * @name Constants and macros for entire FTM_SYNC register - */ -/*@{*/ -#define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U) - -#define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x)) -#define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U) -#define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v)) -#define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v))) -#define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v))) -#define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SYNC bitfields - */ - -/*! - * @name Register FTM_SYNC, field CNTMIN[0] (RW) - * - * Selects the minimum loading point to PWM synchronization. See Boundary cycle - * and loading points. If CNTMIN is one, the selected loading point is when the - * FTM counter reaches its minimum value (CNTIN register). - * - * Values: - * - 0 - The minimum loading point is disabled. - * - 1 - The minimum loading point is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */ -#define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */ -#define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */ - -/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */ -#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN)) - -/*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */ -#define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN) - -/*! @brief Set the CNTMIN field to a new value. */ -#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field CNTMAX[1] (RW) - * - * Selects the maximum loading point to PWM synchronization. See Boundary cycle - * and loading points. If CNTMAX is 1, the selected loading point is when the FTM - * counter reaches its maximum value (MOD register). - * - * Values: - * - 0 - The maximum loading point is disabled. - * - 1 - The maximum loading point is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */ -#define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */ -#define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */ - -/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */ -#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX)) - -/*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */ -#define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX) - -/*! @brief Set the CNTMAX field to a new value. */ -#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field REINIT[2] (RW) - * - * Determines if the FTM counter is reinitialized when the selected trigger for - * the synchronization is detected. The REINIT bit configures the synchronization - * when SYNCMODE is zero. - * - * Values: - * - 0 - FTM counter continues to count normally. - * - 1 - FTM counter is updated with its initial value when the selected trigger - * is detected. - */ -/*@{*/ -#define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */ -#define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */ -#define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */ - -/*! @brief Read current value of the FTM_SYNC_REINIT field. */ -#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT)) - -/*! @brief Format value for bitfield FTM_SYNC_REINIT. */ -#define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT) - -/*! @brief Set the REINIT field to a new value. */ -#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field SYNCHOM[3] (RW) - * - * Selects when the OUTMASK register is updated with the value of its buffer. - * - * Values: - * - 0 - OUTMASK register is updated with the value of its buffer in all rising - * edges of the system clock. - * - 1 - OUTMASK register is updated with the value of its buffer only by the - * PWM synchronization. - */ -/*@{*/ -#define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */ -#define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */ -#define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */ - -/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */ -#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM)) - -/*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */ -#define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM) - -/*! @brief Set the SYNCHOM field to a new value. */ -#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field TRIG0[4] (RW) - * - * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0 - * occurs when a rising edge is detected at the trigger 0 input signal. - * - * Values: - * - 0 - Trigger is disabled. - * - 1 - Trigger is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */ -#define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */ -#define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */ - -/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */ -#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0)) - -/*! @brief Format value for bitfield FTM_SYNC_TRIG0. */ -#define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0) - -/*! @brief Set the TRIG0 field to a new value. */ -#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field TRIG1[5] (RW) - * - * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 - * happens when a rising edge is detected at the trigger 1 input signal. - * - * Values: - * - 0 - Trigger is disabled. - * - 1 - Trigger is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */ -#define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */ -#define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */ - -/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */ -#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1)) - -/*! @brief Format value for bitfield FTM_SYNC_TRIG1. */ -#define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1) - -/*! @brief Set the TRIG1 field to a new value. */ -#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field TRIG2[6] (RW) - * - * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 - * happens when a rising edge is detected at the trigger 2 input signal. - * - * Values: - * - 0 - Trigger is disabled. - * - 1 - Trigger is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */ -#define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */ -#define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */ - -/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */ -#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2)) - -/*! @brief Format value for bitfield FTM_SYNC_TRIG2. */ -#define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2) - -/*! @brief Set the TRIG2 field to a new value. */ -#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field SWSYNC[7] (RW) - * - * Selects the software trigger as the PWM synchronization trigger. The software - * trigger happens when a 1 is written to SWSYNC bit. - * - * Values: - * - 0 - Software trigger is not selected. - * - 1 - Software trigger is selected. - */ -/*@{*/ -#define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */ -#define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */ -#define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */ - -/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */ -#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC)) - -/*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */ -#define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC) - -/*! @brief Set the SWSYNC field to a new value. */ -#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_OUTINIT - Initial State For Channels Output - ******************************************************************************/ - -/*! - * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_ftm_outinit -{ - uint32_t U; - struct _hw_ftm_outinit_bitfields - { - uint32_t CH0OI : 1; /*!< [0] Channel 0 Output Initialization Value */ - uint32_t CH1OI : 1; /*!< [1] Channel 1 Output Initialization Value */ - uint32_t CH2OI : 1; /*!< [2] Channel 2 Output Initialization Value */ - uint32_t CH3OI : 1; /*!< [3] Channel 3 Output Initialization Value */ - uint32_t CH4OI : 1; /*!< [4] Channel 4 Output Initialization Value */ - uint32_t CH5OI : 1; /*!< [5] Channel 5 Output Initialization Value */ - uint32_t CH6OI : 1; /*!< [6] Channel 6 Output Initialization Value */ - uint32_t CH7OI : 1; /*!< [7] Channel 7 Output Initialization Value */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_outinit_t; - -/*! - * @name Constants and macros for entire FTM_OUTINIT register - */ -/*@{*/ -#define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU) - -#define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x)) -#define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U) -#define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v)) -#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v))) -#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v))) -#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_OUTINIT bitfields - */ - -/*! - * @name Register FTM_OUTINIT, field CH0OI[0] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */ -#define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */ -#define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */ -#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */ -#define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI) - -/*! @brief Set the CH0OI field to a new value. */ -#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH1OI[1] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */ -#define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */ -#define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */ -#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */ -#define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI) - -/*! @brief Set the CH1OI field to a new value. */ -#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH2OI[2] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */ -#define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */ -#define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */ -#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */ -#define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI) - -/*! @brief Set the CH2OI field to a new value. */ -#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH3OI[3] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */ -#define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */ -#define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */ -#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */ -#define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI) - -/*! @brief Set the CH3OI field to a new value. */ -#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH4OI[4] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */ -#define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */ -#define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */ -#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */ -#define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI) - -/*! @brief Set the CH4OI field to a new value. */ -#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH5OI[5] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */ -#define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */ -#define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */ -#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */ -#define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI) - -/*! @brief Set the CH5OI field to a new value. */ -#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH6OI[6] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */ -#define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */ -#define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */ -#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */ -#define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI) - -/*! @brief Set the CH6OI field to a new value. */ -#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH7OI[7] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */ -#define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */ -#define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */ -#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */ -#define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI) - -/*! @brief Set the CH7OI field to a new value. */ -#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_OUTMASK - Output Mask - ******************************************************************************/ - -/*! - * @brief HW_FTM_OUTMASK - Output Mask (RW) - * - * Reset value: 0x00000000U - * - * This register provides a mask for each FTM channel. The mask of a channel - * determines if its output responds, that is, it is masked or not, when a match - * occurs. This feature is used for BLDC control where the PWM signal is presented - * to an electric motor at specific times to provide electronic commutation. Any - * write to the OUTMASK register, stores the value in its write buffer. The - * register is updated with the value of its write buffer according to PWM - * synchronization. - */ -typedef union _hw_ftm_outmask -{ - uint32_t U; - struct _hw_ftm_outmask_bitfields - { - uint32_t CH0OM : 1; /*!< [0] Channel 0 Output Mask */ - uint32_t CH1OM : 1; /*!< [1] Channel 1 Output Mask */ - uint32_t CH2OM : 1; /*!< [2] Channel 2 Output Mask */ - uint32_t CH3OM : 1; /*!< [3] Channel 3 Output Mask */ - uint32_t CH4OM : 1; /*!< [4] Channel 4 Output Mask */ - uint32_t CH5OM : 1; /*!< [5] Channel 5 Output Mask */ - uint32_t CH6OM : 1; /*!< [6] Channel 6 Output Mask */ - uint32_t CH7OM : 1; /*!< [7] Channel 7 Output Mask */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_outmask_t; - -/*! - * @name Constants and macros for entire FTM_OUTMASK register - */ -/*@{*/ -#define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U) - -#define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x)) -#define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U) -#define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v)) -#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v))) -#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v))) -#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_OUTMASK bitfields - */ - -/*! - * @name Register FTM_OUTMASK, field CH0OM[0] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */ -#define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */ -#define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */ -#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */ -#define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM) - -/*! @brief Set the CH0OM field to a new value. */ -#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH1OM[1] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */ -#define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */ -#define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */ -#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */ -#define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM) - -/*! @brief Set the CH1OM field to a new value. */ -#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH2OM[2] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */ -#define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */ -#define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */ -#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */ -#define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM) - -/*! @brief Set the CH2OM field to a new value. */ -#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH3OM[3] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */ -#define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */ -#define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */ -#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */ -#define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM) - -/*! @brief Set the CH3OM field to a new value. */ -#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH4OM[4] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */ -#define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */ -#define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */ -#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */ -#define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM) - -/*! @brief Set the CH4OM field to a new value. */ -#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH5OM[5] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */ -#define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */ -#define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */ -#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */ -#define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM) - -/*! @brief Set the CH5OM field to a new value. */ -#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH6OM[6] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */ -#define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */ -#define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */ -#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */ -#define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM) - -/*! @brief Set the CH6OM field to a new value. */ -#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH7OM[7] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */ -#define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */ -#define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */ -#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */ -#define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM) - -/*! @brief Set the CH7OM field to a new value. */ -#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_COMBINE - Function For Linked Channels - ******************************************************************************/ - -/*! - * @brief HW_FTM_COMBINE - Function For Linked Channels (RW) - * - * Reset value: 0x00000000U - * - * This register contains the control bits used to configure the fault control, - * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary, - * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, - * 4, and 6. - */ -typedef union _hw_ftm_combine -{ - uint32_t U; - struct _hw_ftm_combine_bitfields - { - uint32_t COMBINE0 : 1; /*!< [0] Combine Channels For n = 0 */ - uint32_t COMP0 : 1; /*!< [1] Complement Of Channel (n) For n = 0 */ - uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n = - * 0 */ - uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n = - * 0 */ - uint32_t DTEN0 : 1; /*!< [4] Deadtime Enable For n = 0 */ - uint32_t SYNCEN0 : 1; /*!< [5] Synchronization Enable For n = 0 */ - uint32_t FAULTEN0 : 1; /*!< [6] Fault Control Enable For n = 0 */ - uint32_t RESERVED0 : 1; /*!< [7] */ - uint32_t COMBINE1 : 1; /*!< [8] Combine Channels For n = 2 */ - uint32_t COMP1 : 1; /*!< [9] Complement Of Channel (n) For n = 2 */ - uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n - * = 2 */ - uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n - * = 2 */ - uint32_t DTEN1 : 1; /*!< [12] Deadtime Enable For n = 2 */ - uint32_t SYNCEN1 : 1; /*!< [13] Synchronization Enable For n = 2 */ - uint32_t FAULTEN1 : 1; /*!< [14] Fault Control Enable For n = 2 */ - uint32_t RESERVED1 : 1; /*!< [15] */ - uint32_t COMBINE2 : 1; /*!< [16] Combine Channels For n = 4 */ - uint32_t COMP2 : 1; /*!< [17] Complement Of Channel (n) For n = 4 */ - uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n - * = 4 */ - uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n - * = 4 */ - uint32_t DTEN2 : 1; /*!< [20] Deadtime Enable For n = 4 */ - uint32_t SYNCEN2 : 1; /*!< [21] Synchronization Enable For n = 4 */ - uint32_t FAULTEN2 : 1; /*!< [22] Fault Control Enable For n = 4 */ - uint32_t RESERVED2 : 1; /*!< [23] */ - uint32_t COMBINE3 : 1; /*!< [24] Combine Channels For n = 6 */ - uint32_t COMP3 : 1; /*!< [25] Complement Of Channel (n) for n = 6 */ - uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n - * = 6 */ - uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n - * = 6 */ - uint32_t DTEN3 : 1; /*!< [28] Deadtime Enable For n = 6 */ - uint32_t SYNCEN3 : 1; /*!< [29] Synchronization Enable For n = 6 */ - uint32_t FAULTEN3 : 1; /*!< [30] Fault Control Enable For n = 6 */ - uint32_t RESERVED3 : 1; /*!< [31] */ - } B; -} hw_ftm_combine_t; - -/*! - * @name Constants and macros for entire FTM_COMBINE register - */ -/*@{*/ -#define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U) - -#define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x)) -#define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U) -#define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v)) -#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v))) -#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v))) -#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_COMBINE bitfields - */ - -/*! - * @name Register FTM_COMBINE, field COMBINE0[0] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */ -#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */ -#define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */ -#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */ -#define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0) - -/*! @brief Set the COMBINE0 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP0[1] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */ -#define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */ -#define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */ -#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP0. */ -#define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0) - -/*! @brief Set the COMP0 field to a new value. */ -#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN0[2] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */ -#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */ -#define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */ -#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */ -#define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0) - -/*! @brief Set the DECAPEN0 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP0[3] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if dual edge capture - one-shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */ -#define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */ -#define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */ -#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */ -#define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0) - -/*! @brief Set the DECAP0 field to a new value. */ -#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN0[4] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */ -#define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */ -#define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */ -#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */ -#define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0) - -/*! @brief Set the DTEN0 field to a new value. */ -#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN0[5] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */ -#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */ -#define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */ -#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */ -#define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0) - -/*! @brief Set the SYNCEN0 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN0[6] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */ -#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */ -#define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */ -#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */ -#define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0) - -/*! @brief Set the FAULTEN0 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMBINE1[8] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */ -#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */ -#define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */ -#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */ -#define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1) - -/*! @brief Set the COMBINE1 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP1[9] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */ -#define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */ -#define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */ -#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP1. */ -#define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1) - -/*! @brief Set the COMP1 field to a new value. */ -#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN1[10] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */ -#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */ -#define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */ -#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */ -#define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1) - -/*! @brief Set the DECAPEN1 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP1[11] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */ -#define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */ -#define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */ -#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */ -#define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1) - -/*! @brief Set the DECAP1 field to a new value. */ -#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN1[12] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */ -#define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */ -#define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */ -#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */ -#define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1) - -/*! @brief Set the DTEN1 field to a new value. */ -#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN1[13] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */ -#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */ -#define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */ -#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */ -#define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1) - -/*! @brief Set the SYNCEN1 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN1[14] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */ -#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */ -#define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */ -#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */ -#define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1) - -/*! @brief Set the FAULTEN1 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMBINE2[16] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */ -#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */ -#define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */ -#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */ -#define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2) - -/*! @brief Set the COMBINE2 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP2[17] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */ -#define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */ -#define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */ -#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP2. */ -#define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2) - -/*! @brief Set the COMP2 field to a new value. */ -#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN2[18] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */ -#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */ -#define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */ -#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */ -#define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2) - -/*! @brief Set the DECAPEN2 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP2[19] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if dual edge capture - one-shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */ -#define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */ -#define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */ -#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */ -#define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2) - -/*! @brief Set the DECAP2 field to a new value. */ -#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN2[20] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */ -#define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */ -#define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */ -#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */ -#define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2) - -/*! @brief Set the DTEN2 field to a new value. */ -#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN2[21] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */ -#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */ -#define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */ -#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */ -#define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2) - -/*! @brief Set the SYNCEN2 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN2[22] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */ -#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */ -#define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */ -#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */ -#define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2) - -/*! @brief Set the FAULTEN2 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMBINE3[24] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */ -#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */ -#define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */ -#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */ -#define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3) - -/*! @brief Set the COMBINE3 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP3[25] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */ -#define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */ -#define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */ -#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP3. */ -#define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3) - -/*! @brief Set the COMP3 field to a new value. */ -#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN3[26] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */ -#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */ -#define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */ -#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */ -#define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3) - -/*! @brief Set the DECAPEN3 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP3[27] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if dual edge capture - one-shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */ -#define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */ -#define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */ -#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */ -#define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3) - -/*! @brief Set the DECAP3 field to a new value. */ -#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN3[28] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */ -#define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */ -#define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */ -#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */ -#define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3) - -/*! @brief Set the DTEN3 field to a new value. */ -#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN3[29] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */ -#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */ -#define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */ -#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */ -#define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3) - -/*! @brief Set the SYNCEN3 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN3[30] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */ -#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */ -#define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */ -#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */ -#define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3) - -/*! @brief Set the FAULTEN3 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_DEADTIME - Deadtime Insertion Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW) - * - * Reset value: 0x00000000U - * - * This register selects the deadtime prescaler factor and deadtime value. All - * FTM channels use this clock prescaler and this deadtime value for the deadtime - * insertion. - */ -typedef union _hw_ftm_deadtime -{ - uint32_t U; - struct _hw_ftm_deadtime_bitfields - { - uint32_t DTVAL : 6; /*!< [5:0] Deadtime Value */ - uint32_t DTPS : 2; /*!< [7:6] Deadtime Prescaler Value */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_deadtime_t; - -/*! - * @name Constants and macros for entire FTM_DEADTIME register - */ -/*@{*/ -#define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U) - -#define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x)) -#define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U) -#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v)) -#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v))) -#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v))) -#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_DEADTIME bitfields - */ - -/*! - * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW) - * - * Selects the deadtime insertion value for the deadtime counter. The deadtime - * counter is clocked by a scaled version of the system clock. See the description - * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of - * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted. - * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted. - * This pattern continues up to a possible 63 counts. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - */ -/*@{*/ -#define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */ -#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */ -#define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */ - -/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */ -#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL) - -/*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */ -#define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL) - -/*! @brief Set the DTVAL field to a new value. */ -#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_DEADTIME, field DTPS[7:6] (RW) - * - * Selects the division factor of the system clock. This prescaled clock is used - * by the deadtime counter. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0x - Divide the system clock by 1. - * - 10 - Divide the system clock by 4. - * - 11 - Divide the system clock by 16. - */ -/*@{*/ -#define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */ -#define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */ -#define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */ - -/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */ -#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS) - -/*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */ -#define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS) - -/*! @brief Set the DTPS field to a new value. */ -#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_EXTTRIG - FTM External Trigger - ******************************************************************************/ - -/*! - * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW) - * - * Reset value: 0x00000000U - * - * This register: Indicates when a channel trigger was generated Enables the - * generation of a trigger when the FTM counter is equal to its initial value - * Selects which channels are used in the generation of the channel triggers Several - * channels can be selected to generate multiple triggers in one PWM period. - * Channels 6 and 7 are not used to generate channel triggers. - */ -typedef union _hw_ftm_exttrig -{ - uint32_t U; - struct _hw_ftm_exttrig_bitfields - { - uint32_t CH2TRIG : 1; /*!< [0] Channel 2 Trigger Enable */ - uint32_t CH3TRIG : 1; /*!< [1] Channel 3 Trigger Enable */ - uint32_t CH4TRIG : 1; /*!< [2] Channel 4 Trigger Enable */ - uint32_t CH5TRIG : 1; /*!< [3] Channel 5 Trigger Enable */ - uint32_t CH0TRIG : 1; /*!< [4] Channel 0 Trigger Enable */ - uint32_t CH1TRIG : 1; /*!< [5] Channel 1 Trigger Enable */ - uint32_t INITTRIGEN : 1; /*!< [6] Initialization Trigger Enable */ - uint32_t TRIGF : 1; /*!< [7] Channel Trigger Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_exttrig_t; - -/*! - * @name Constants and macros for entire FTM_EXTTRIG register - */ -/*@{*/ -#define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU) - -#define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x)) -#define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U) -#define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v)) -#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v))) -#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v))) -#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_EXTTRIG bitfields - */ - -/*! - * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */ -#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */ -#define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */ -#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */ -#define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG) - -/*! @brief Set the CH2TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */ -#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */ -#define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */ -#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */ -#define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG) - -/*! @brief Set the CH3TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */ -#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */ -#define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */ -#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */ -#define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG) - -/*! @brief Set the CH4TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */ -#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */ -#define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */ -#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */ -#define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG) - -/*! @brief Set the CH5TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */ -#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */ -#define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */ -#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */ -#define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG) - -/*! @brief Set the CH0TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */ -#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */ -#define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */ -#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */ -#define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG) - -/*! @brief Set the CH1TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW) - * - * Enables the generation of the trigger when the FTM counter is equal to the - * CNTIN register. - * - * Values: - * - 0 - The generation of initialization trigger is disabled. - * - 1 - The generation of initialization trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */ -#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */ -#define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */ - -/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */ -#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */ -#define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN) - -/*! @brief Set the INITTRIGEN field to a new value. */ -#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ) - * - * Set by hardware when a channel trigger is generated. Clear TRIGF by reading - * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF - * has no effect. If another channel trigger is generated before the clearing - * sequence is completed, the sequence is reset so TRIGF remains set after the clear - * sequence is completed for the earlier TRIGF. - * - * Values: - * - 0 - No channel trigger was generated. - * - 1 - A channel trigger was generated. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */ -#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */ -#define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */ - -/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */ -#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */ -#define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF) - -/*! @brief Set the TRIGF field to a new value. */ -#define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_POL - Channels Polarity - ******************************************************************************/ - -/*! - * @brief HW_FTM_POL - Channels Polarity (RW) - * - * Reset value: 0x00000000U - * - * This register defines the output polarity of the FTM channels. The safe value - * that is driven in a channel output when the fault control is enabled and a - * fault condition is detected is the inactive state of the channel. That is, the - * safe value of a channel is the value of its POL bit. - */ -typedef union _hw_ftm_pol -{ - uint32_t U; - struct _hw_ftm_pol_bitfields - { - uint32_t POL0 : 1; /*!< [0] Channel 0 Polarity */ - uint32_t POL1 : 1; /*!< [1] Channel 1 Polarity */ - uint32_t POL2 : 1; /*!< [2] Channel 2 Polarity */ - uint32_t POL3 : 1; /*!< [3] Channel 3 Polarity */ - uint32_t POL4 : 1; /*!< [4] Channel 4 Polarity */ - uint32_t POL5 : 1; /*!< [5] Channel 5 Polarity */ - uint32_t POL6 : 1; /*!< [6] Channel 6 Polarity */ - uint32_t POL7 : 1; /*!< [7] Channel 7 Polarity */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_pol_t; - -/*! - * @name Constants and macros for entire FTM_POL register - */ -/*@{*/ -#define HW_FTM_POL_ADDR(x) ((x) + 0x70U) - -#define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x)) -#define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U) -#define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v)) -#define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v))) -#define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v))) -#define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_POL bitfields - */ - -/*! - * @name Register FTM_POL, field POL0[0] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */ -#define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */ -#define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */ - -/*! @brief Read current value of the FTM_POL_POL0 field. */ -#define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0)) - -/*! @brief Format value for bitfield FTM_POL_POL0. */ -#define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0) - -/*! @brief Set the POL0 field to a new value. */ -#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL1[1] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */ -#define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */ -#define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */ - -/*! @brief Read current value of the FTM_POL_POL1 field. */ -#define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1)) - -/*! @brief Format value for bitfield FTM_POL_POL1. */ -#define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1) - -/*! @brief Set the POL1 field to a new value. */ -#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL2[2] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */ -#define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */ -#define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */ - -/*! @brief Read current value of the FTM_POL_POL2 field. */ -#define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2)) - -/*! @brief Format value for bitfield FTM_POL_POL2. */ -#define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2) - -/*! @brief Set the POL2 field to a new value. */ -#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL3[3] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */ -#define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */ -#define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */ - -/*! @brief Read current value of the FTM_POL_POL3 field. */ -#define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3)) - -/*! @brief Format value for bitfield FTM_POL_POL3. */ -#define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3) - -/*! @brief Set the POL3 field to a new value. */ -#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL4[4] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */ -#define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */ -#define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */ - -/*! @brief Read current value of the FTM_POL_POL4 field. */ -#define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4)) - -/*! @brief Format value for bitfield FTM_POL_POL4. */ -#define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4) - -/*! @brief Set the POL4 field to a new value. */ -#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL5[5] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */ -#define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */ -#define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */ - -/*! @brief Read current value of the FTM_POL_POL5 field. */ -#define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5)) - -/*! @brief Format value for bitfield FTM_POL_POL5. */ -#define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5) - -/*! @brief Set the POL5 field to a new value. */ -#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL6[6] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */ -#define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */ -#define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */ - -/*! @brief Read current value of the FTM_POL_POL6 field. */ -#define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6)) - -/*! @brief Format value for bitfield FTM_POL_POL6. */ -#define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6) - -/*! @brief Set the POL6 field to a new value. */ -#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL7[7] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */ -#define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */ -#define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */ - -/*! @brief Read current value of the FTM_POL_POL7 field. */ -#define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7)) - -/*! @brief Format value for bitfield FTM_POL_POL7. */ -#define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7) - -/*! @brief Set the POL7 field to a new value. */ -#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FMS - Fault Mode Status - ******************************************************************************/ - -/*! - * @brief HW_FTM_FMS - Fault Mode Status (RW) - * - * Reset value: 0x00000000U - * - * This register contains the fault detection flags, write protection enable - * bit, and the logic OR of the enabled fault inputs. - */ -typedef union _hw_ftm_fms -{ - uint32_t U; - struct _hw_ftm_fms_bitfields - { - uint32_t FAULTF0 : 1; /*!< [0] Fault Detection Flag 0 */ - uint32_t FAULTF1 : 1; /*!< [1] Fault Detection Flag 1 */ - uint32_t FAULTF2 : 1; /*!< [2] Fault Detection Flag 2 */ - uint32_t FAULTF3 : 1; /*!< [3] Fault Detection Flag 3 */ - uint32_t RESERVED0 : 1; /*!< [4] */ - uint32_t FAULTIN : 1; /*!< [5] Fault Inputs */ - uint32_t WPEN : 1; /*!< [6] Write Protection Enable */ - uint32_t FAULTF : 1; /*!< [7] Fault Detection Flag */ - uint32_t RESERVED1 : 24; /*!< [31:8] */ - } B; -} hw_ftm_fms_t; - -/*! - * @name Constants and macros for entire FTM_FMS register - */ -/*@{*/ -#define HW_FTM_FMS_ADDR(x) ((x) + 0x74U) - -#define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x)) -#define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U) -#define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v)) -#define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v))) -#define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v))) -#define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FMS bitfields - */ - -/*! - * @name Register FTM_FMS, field FAULTF0[0] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF0 - * by reading the FMS register while FAULTF0 is set and then writing a 0 to - * FAULTF0 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF0 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */ -#define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */ -#define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */ -#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF0. */ -#define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0) - -/*! @brief Set the FAULTF0 field to a new value. */ -#define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF1[1] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF1 - * by reading the FMS register while FAULTF1 is set and then writing a 0 to - * FAULTF1 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF1 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */ -#define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */ -#define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */ -#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF1. */ -#define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1) - -/*! @brief Set the FAULTF1 field to a new value. */ -#define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF2[2] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF2 - * by reading the FMS register while FAULTF2 is set and then writing a 0 to - * FAULTF2 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF2 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */ -#define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */ -#define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */ -#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF2. */ -#define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2) - -/*! @brief Set the FAULTF2 field to a new value. */ -#define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF3[3] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF3 - * by reading the FMS register while FAULTF3 is set and then writing a 0 to - * FAULTF3 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF3 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */ -#define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */ -#define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */ -#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF3. */ -#define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3) - -/*! @brief Set the FAULTF3 field to a new value. */ -#define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTIN[5] (RO) - * - * Represents the logic OR of the enabled fault inputs after their filter (if - * their filter is enabled) when fault control is enabled. - * - * Values: - * - 0 - The logic OR of the enabled fault inputs is 0. - * - 1 - The logic OR of the enabled fault inputs is 1. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */ -#define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */ -#define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */ - -/*! @brief Read current value of the FTM_FMS_FAULTIN field. */ -#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field WPEN[6] (RW) - * - * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written - * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to - * WPDIS. Writing 0 to WPEN has no effect. - * - * Values: - * - 0 - Write protection is disabled. Write protected bits can be written. - * - 1 - Write protection is enabled. Write protected bits cannot be written. - */ -/*@{*/ -#define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */ -#define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */ -#define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */ - -/*! @brief Read current value of the FTM_FMS_WPEN field. */ -#define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN)) - -/*! @brief Format value for bitfield FTM_FMS_WPEN. */ -#define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN) - -/*! @brief Set the WPEN field to a new value. */ -#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF[7] (ROWZ) - * - * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0. - * Clear FAULTF by reading the FMS register while FAULTF is set and then writing - * a 0 to FAULTF while there is no existing fault condition at the enabled fault - * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is - * detected in an enabled fault input before the clearing sequence is completed, the - * sequence is reset so FAULTF remains set after the clearing sequence is - * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits - * are cleared individually. - * - * Values: - * - 0 - No fault condition was detected. - * - 1 - A fault condition was detected. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */ -#define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */ -#define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF field. */ -#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF. */ -#define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF) - -/*! @brief Set the FAULTF field to a new value. */ -#define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FILTER - Input Capture Filter Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_FILTER - Input Capture Filter Control (RW) - * - * Reset value: 0x00000000U - * - * This register selects the filter value for the inputs of channels. Channels - * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has - * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not - * in input modes. Failure to do this could result in a missing valid signal. - */ -typedef union _hw_ftm_filter -{ - uint32_t U; - struct _hw_ftm_filter_bitfields - { - uint32_t CH0FVAL : 4; /*!< [3:0] Channel 0 Input Filter */ - uint32_t CH1FVAL : 4; /*!< [7:4] Channel 1 Input Filter */ - uint32_t CH2FVAL : 4; /*!< [11:8] Channel 2 Input Filter */ - uint32_t CH3FVAL : 4; /*!< [15:12] Channel 3 Input Filter */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_filter_t; - -/*! - * @name Constants and macros for entire FTM_FILTER register - */ -/*@{*/ -#define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U) - -#define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x)) -#define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U) -#define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v)) -#define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v))) -#define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v))) -#define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FILTER bitfields - */ - -/*! - * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */ -#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */ -#define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */ -#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */ -#define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL) - -/*! @brief Set the CH0FVAL field to a new value. */ -#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */ -#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */ -#define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */ -#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */ -#define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL) - -/*! @brief Set the CH1FVAL field to a new value. */ -#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */ -#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */ -#define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */ -#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */ -#define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL) - -/*! @brief Set the CH2FVAL field to a new value. */ -#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */ -#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */ -#define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */ -#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */ -#define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL) - -/*! @brief Set the CH3FVAL field to a new value. */ -#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FLTCTRL - Fault Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_FLTCTRL - Fault Control (RW) - * - * Reset value: 0x00000000U - * - * This register selects the filter value for the fault inputs, enables the - * fault inputs and the fault inputs filter. - */ -typedef union _hw_ftm_fltctrl -{ - uint32_t U; - struct _hw_ftm_fltctrl_bitfields - { - uint32_t FAULT0EN : 1; /*!< [0] Fault Input 0 Enable */ - uint32_t FAULT1EN : 1; /*!< [1] Fault Input 1 Enable */ - uint32_t FAULT2EN : 1; /*!< [2] Fault Input 2 Enable */ - uint32_t FAULT3EN : 1; /*!< [3] Fault Input 3 Enable */ - uint32_t FFLTR0EN : 1; /*!< [4] Fault Input 0 Filter Enable */ - uint32_t FFLTR1EN : 1; /*!< [5] Fault Input 1 Filter Enable */ - uint32_t FFLTR2EN : 1; /*!< [6] Fault Input 2 Filter Enable */ - uint32_t FFLTR3EN : 1; /*!< [7] Fault Input 3 Filter Enable */ - uint32_t FFVAL : 4; /*!< [11:8] Fault Input Filter */ - uint32_t RESERVED0 : 20; /*!< [31:12] */ - } B; -} hw_ftm_fltctrl_t; - -/*! - * @name Constants and macros for entire FTM_FLTCTRL register - */ -/*@{*/ -#define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU) - -#define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x)) -#define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U) -#define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v)) -#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v))) -#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v))) -#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FLTCTRL bitfields - */ - -/*! - * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */ -#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */ -#define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */ -#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */ -#define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN) - -/*! @brief Set the FAULT0EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */ -#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */ -#define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */ -#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */ -#define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN) - -/*! @brief Set the FAULT1EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */ -#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */ -#define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */ -#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */ -#define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN) - -/*! @brief Set the FAULT2EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */ -#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */ -#define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */ -#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */ -#define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN) - -/*! @brief Set the FAULT3EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */ -#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */ -#define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */ -#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */ -#define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN) - -/*! @brief Set the FFLTR0EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */ -#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */ -#define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */ -#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */ -#define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN) - -/*! @brief Set the FFLTR1EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */ -#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */ -#define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */ -#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */ -#define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN) - -/*! @brief Set the FFLTR2EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */ -#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */ -#define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */ -#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */ -#define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN) - -/*! @brief Set the FFLTR3EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW) - * - * Selects the filter value for the fault inputs. The fault filter is disabled - * when the value is zero. Writing to this field has immediate effect and must be - * done only when the fault control or all fault inputs are disabled. Failure to - * do this could result in a missing fault detection. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */ -#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */ -#define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */ -#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */ -#define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL) - -/*! @brief Set the FFVAL field to a new value. */ -#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_QDCTRL - Quadrature Decoder Control And Status - ******************************************************************************/ - -/*! - * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW) - * - * Reset value: 0x00000000U - * - * This register has the control and status bits for the Quadrature Decoder mode. - */ -typedef union _hw_ftm_qdctrl -{ - uint32_t U; - struct _hw_ftm_qdctrl_bitfields - { - uint32_t QUADEN : 1; /*!< [0] Quadrature Decoder Mode Enable */ - uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature - * Decoder Mode */ - uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature - * Decoder Mode */ - uint32_t QUADMODE : 1; /*!< [3] Quadrature Decoder Mode */ - uint32_t PHBPOL : 1; /*!< [4] Phase B Input Polarity */ - uint32_t PHAPOL : 1; /*!< [5] Phase A Input Polarity */ - uint32_t PHBFLTREN : 1; /*!< [6] Phase B Input Filter Enable */ - uint32_t PHAFLTREN : 1; /*!< [7] Phase A Input Filter Enable */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_qdctrl_t; - -/*! - * @name Constants and macros for entire FTM_QDCTRL register - */ -/*@{*/ -#define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U) - -#define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x)) -#define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U) -#define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v)) -#define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v))) -#define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v))) -#define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_QDCTRL bitfields - */ - -/*! - * @name Register FTM_QDCTRL, field QUADEN[0] (RW) - * - * Enables the Quadrature Decoder mode. In this mode, the phase A and B input - * signals control the FTM counter direction. The Quadrature Decoder mode has - * precedence over the other modes. See #ModeSel1Table. This field is write protected. - * It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Quadrature Decoder mode is disabled. - * - 1 - Quadrature Decoder mode is enabled. - */ -/*@{*/ -#define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */ -#define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */ -#define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */ - -/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */ -#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN)) - -/*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */ -#define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN) - -/*! @brief Set the QUADEN field to a new value. */ -#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field TOFDIR[1] (RO) - * - * Indicates if the TOF bit was set on the top or the bottom of counting. - * - * Values: - * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter - * decrement and FTM counter changes from its minimum value (CNTIN register) to - * its maximum value (MOD register). - * - 1 - TOF bit was set on the top of counting. There was an FTM counter - * increment and FTM counter changes from its maximum value (MOD register) to its - * minimum value (CNTIN register). - */ -/*@{*/ -#define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */ -#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */ -#define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */ - -/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */ -#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field QUADIR[2] (RO) - * - * Indicates the counting direction. - * - * Values: - * - 0 - Counting direction is decreasing (FTM counter decrement). - * - 1 - Counting direction is increasing (FTM counter increment). - */ -/*@{*/ -#define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */ -#define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */ -#define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */ - -/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */ -#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field QUADMODE[3] (RW) - * - * Selects the encoding mode used in the Quadrature Decoder mode. - * - * Values: - * - 0 - Phase A and phase B encoding mode. - * - 1 - Count and direction encoding mode. - */ -/*@{*/ -#define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */ -#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */ -#define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */ - -/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */ -#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE)) - -/*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */ -#define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE) - -/*! @brief Set the QUADMODE field to a new value. */ -#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHBPOL[4] (RW) - * - * Selects the polarity for the quadrature decoder phase B input. - * - * Values: - * - 0 - Normal polarity. Phase B input signal is not inverted before - * identifying the rising and falling edges of this signal. - * - 1 - Inverted polarity. Phase B input signal is inverted before identifying - * the rising and falling edges of this signal. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */ -#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */ -#define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */ -#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */ -#define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL) - -/*! @brief Set the PHBPOL field to a new value. */ -#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHAPOL[5] (RW) - * - * Selects the polarity for the quadrature decoder phase A input. - * - * Values: - * - 0 - Normal polarity. Phase A input signal is not inverted before - * identifying the rising and falling edges of this signal. - * - 1 - Inverted polarity. Phase A input signal is inverted before identifying - * the rising and falling edges of this signal. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */ -#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */ -#define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */ -#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */ -#define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL) - -/*! @brief Set the PHAPOL field to a new value. */ -#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW) - * - * Enables the filter for the quadrature decoder phase B input. The filter value - * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B - * filter is also disabled when CH1FVAL is zero. - * - * Values: - * - 0 - Phase B input filter is disabled. - * - 1 - Phase B input filter is enabled. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */ -#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */ -#define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */ -#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */ -#define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN) - -/*! @brief Set the PHBFLTREN field to a new value. */ -#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW) - * - * Enables the filter for the quadrature decoder phase A input. The filter value - * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A - * filter is also disabled when CH0FVAL is zero. - * - * Values: - * - 0 - Phase A input filter is disabled. - * - 1 - Phase A input filter is enabled. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */ -#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */ -#define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */ -#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */ -#define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN) - -/*! @brief Set the PHAFLTREN field to a new value. */ -#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CONF - Configuration - ******************************************************************************/ - -/*! - * @brief HW_FTM_CONF - Configuration (RW) - * - * Reset value: 0x00000000U - * - * This register selects the number of times that the FTM counter overflow - * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use - * of an external global time base, and the global time base signal generation. - */ -typedef union _hw_ftm_conf -{ - uint32_t U; - struct _hw_ftm_conf_bitfields - { - uint32_t NUMTOF : 5; /*!< [4:0] TOF Frequency */ - uint32_t RESERVED0 : 1; /*!< [5] */ - uint32_t BDMMODE : 2; /*!< [7:6] BDM Mode */ - uint32_t RESERVED1 : 1; /*!< [8] */ - uint32_t GTBEEN : 1; /*!< [9] Global Time Base Enable */ - uint32_t GTBEOUT : 1; /*!< [10] Global Time Base Output */ - uint32_t RESERVED2 : 21; /*!< [31:11] */ - } B; -} hw_ftm_conf_t; - -/*! - * @name Constants and macros for entire FTM_CONF register - */ -/*@{*/ -#define HW_FTM_CONF_ADDR(x) ((x) + 0x84U) - -#define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x)) -#define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U) -#define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v)) -#define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v))) -#define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v))) -#define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CONF bitfields - */ - -/*! - * @name Register FTM_CONF, field NUMTOF[4:0] (RW) - * - * Selects the ratio between the number of counter overflows to the number of - * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter - * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for - * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter - * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the - * first counter overflow but not for the next 3 overflows. This pattern continues - * up to a maximum of 31. - */ -/*@{*/ -#define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */ -#define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */ -#define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */ - -/*! @brief Read current value of the FTM_CONF_NUMTOF field. */ -#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF) - -/*! @brief Format value for bitfield FTM_CONF_NUMTOF. */ -#define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF) - -/*! @brief Set the NUMTOF field to a new value. */ -#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v))) -/*@}*/ - -/*! - * @name Register FTM_CONF, field BDMMODE[7:6] (RW) - * - * Selects the FTM behavior in BDM mode. See BDM mode. - */ -/*@{*/ -#define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */ -#define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */ -#define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */ - -/*! @brief Read current value of the FTM_CONF_BDMMODE field. */ -#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE) - -/*! @brief Format value for bitfield FTM_CONF_BDMMODE. */ -#define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE) - -/*! @brief Set the BDMMODE field to a new value. */ -#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v))) -/*@}*/ - -/*! - * @name Register FTM_CONF, field GTBEEN[9] (RW) - * - * Configures the FTM to use an external global time base signal that is - * generated by another FTM. - * - * Values: - * - 0 - Use of an external global time base is disabled. - * - 1 - Use of an external global time base is enabled. - */ -/*@{*/ -#define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */ -#define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */ -#define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */ - -/*! @brief Read current value of the FTM_CONF_GTBEEN field. */ -#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN)) - -/*! @brief Format value for bitfield FTM_CONF_GTBEEN. */ -#define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN) - -/*! @brief Set the GTBEEN field to a new value. */ -#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CONF, field GTBEOUT[10] (RW) - * - * Enables the global time base signal generation to other FTMs. - * - * Values: - * - 0 - A global time base signal generation is disabled. - * - 1 - A global time base signal generation is enabled. - */ -/*@{*/ -#define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */ -#define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */ -#define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */ - -/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */ -#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT)) - -/*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */ -#define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT) - -/*! @brief Set the GTBEOUT field to a new value. */ -#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FLTPOL - FTM Fault Input Polarity - ******************************************************************************/ - -/*! - * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW) - * - * Reset value: 0x00000000U - * - * This register defines the fault inputs polarity. - */ -typedef union _hw_ftm_fltpol -{ - uint32_t U; - struct _hw_ftm_fltpol_bitfields - { - uint32_t FLT0POL : 1; /*!< [0] Fault Input 0 Polarity */ - uint32_t FLT1POL : 1; /*!< [1] Fault Input 1 Polarity */ - uint32_t FLT2POL : 1; /*!< [2] Fault Input 2 Polarity */ - uint32_t FLT3POL : 1; /*!< [3] Fault Input 3 Polarity */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_ftm_fltpol_t; - -/*! - * @name Constants and macros for entire FTM_FLTPOL register - */ -/*@{*/ -#define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U) - -#define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x)) -#define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U) -#define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v)) -#define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v))) -#define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v))) -#define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FLTPOL bitfields - */ - -/*! - * @name Register FTM_FLTPOL, field FLT0POL[0] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */ -#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */ -#define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */ -#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */ -#define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL) - -/*! @brief Set the FLT0POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTPOL, field FLT1POL[1] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */ -#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */ -#define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */ -#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */ -#define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL) - -/*! @brief Set the FLT1POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTPOL, field FLT2POL[2] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */ -#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */ -#define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */ -#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */ -#define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL) - -/*! @brief Set the FLT2POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTPOL, field FLT3POL[3] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */ -#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */ -#define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */ -#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */ -#define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL) - -/*! @brief Set the FLT3POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_SYNCONF - Synchronization Configuration - ******************************************************************************/ - -/*! - * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW) - * - * Reset value: 0x00000000U - * - * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL - * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = - * 0, 1, 2, when the hardware trigger j is detected. - */ -typedef union _hw_ftm_synconf -{ - uint32_t U; - struct _hw_ftm_synconf_bitfields - { - uint32_t HWTRIGMODE : 1; /*!< [0] Hardware Trigger Mode */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t CNTINC : 1; /*!< [2] CNTIN Register Synchronization */ - uint32_t RESERVED1 : 1; /*!< [3] */ - uint32_t INVC : 1; /*!< [4] INVCTRL Register Synchronization */ - uint32_t SWOC : 1; /*!< [5] SWOCTRL Register Synchronization */ - uint32_t RESERVED2 : 1; /*!< [6] */ - uint32_t SYNCMODE : 1; /*!< [7] Synchronization Mode */ - uint32_t SWRSTCNT : 1; /*!< [8] */ - uint32_t SWWRBUF : 1; /*!< [9] */ - uint32_t SWOM : 1; /*!< [10] */ - uint32_t SWINVC : 1; /*!< [11] */ - uint32_t SWSOC : 1; /*!< [12] */ - uint32_t RESERVED3 : 3; /*!< [15:13] */ - uint32_t HWRSTCNT : 1; /*!< [16] */ - uint32_t HWWRBUF : 1; /*!< [17] */ - uint32_t HWOM : 1; /*!< [18] */ - uint32_t HWINVC : 1; /*!< [19] */ - uint32_t HWSOC : 1; /*!< [20] */ - uint32_t RESERVED4 : 11; /*!< [31:21] */ - } B; -} hw_ftm_synconf_t; - -/*! - * @name Constants and macros for entire FTM_SYNCONF register - */ -/*@{*/ -#define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU) - -#define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x)) -#define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U) -#define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v)) -#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v))) -#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v))) -#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SYNCONF bitfields - */ - -/*! - * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW) - * - * Values: - * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where - * j = 0, 1,2. - * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is - * detected, where j = 0, 1,2. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */ -#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */ -#define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */ -#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */ -#define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE) - -/*! @brief Set the HWTRIGMODE field to a new value. */ -#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field CNTINC[2] (RW) - * - * Values: - * - 0 - CNTIN register is updated with its buffer value at all rising edges of - * system clock. - * - 1 - CNTIN register is updated with its buffer value by the PWM - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */ -#define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */ -#define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */ - -/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */ -#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */ -#define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC) - -/*! @brief Set the CNTINC field to a new value. */ -#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field INVC[4] (RW) - * - * Values: - * - 0 - INVCTRL register is updated with its buffer value at all rising edges - * of system clock. - * - 1 - INVCTRL register is updated with its buffer value by the PWM - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */ -#define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */ -#define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */ - -/*! @brief Read current value of the FTM_SYNCONF_INVC field. */ -#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_INVC. */ -#define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC) - -/*! @brief Set the INVC field to a new value. */ -#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWOC[5] (RW) - * - * Values: - * - 0 - SWOCTRL register is updated with its buffer value at all rising edges - * of system clock. - * - 1 - SWOCTRL register is updated with its buffer value by the PWM - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */ -#define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */ -#define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */ -#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */ -#define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC) - -/*! @brief Set the SWOC field to a new value. */ -#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW) - * - * Selects the PWM Synchronization mode. - * - * Values: - * - 0 - Legacy PWM synchronization is selected. - * - 1 - Enhanced PWM synchronization is selected. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */ -#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */ -#define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */ - -/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */ -#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */ -#define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE) - -/*! @brief Set the SYNCMODE field to a new value. */ -#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW) - * - * FTM counter synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the FTM counter synchronization. - * - 1 - The software trigger activates the FTM counter synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */ -#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */ -#define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */ -#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */ -#define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT) - -/*! @brief Set the SWRSTCNT field to a new value. */ -#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW) - * - * MOD, CNTIN, and CV registers synchronization is activated by the software - * trigger. - * - * Values: - * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers - * synchronization. - * - 1 - The software trigger activates MOD, CNTIN, and CV registers - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */ -#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */ -#define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */ -#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */ -#define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF) - -/*! @brief Set the SWWRBUF field to a new value. */ -#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWOM[10] (RW) - * - * Output mask synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the OUTMASK register - * synchronization. - * - 1 - The software trigger activates the OUTMASK register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */ -#define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */ -#define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */ -#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */ -#define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM) - -/*! @brief Set the SWOM field to a new value. */ -#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWINVC[11] (RW) - * - * Inverting control synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the INVCTRL register - * synchronization. - * - 1 - The software trigger activates the INVCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */ -#define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */ -#define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */ -#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */ -#define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC) - -/*! @brief Set the SWINVC field to a new value. */ -#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWSOC[12] (RW) - * - * Software output control synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the SWOCTRL register - * synchronization. - * - 1 - The software trigger activates the SWOCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */ -#define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */ -#define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */ -#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */ -#define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC) - -/*! @brief Set the SWSOC field to a new value. */ -#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW) - * - * FTM counter synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the FTM counter synchronization. - * - 1 - A hardware trigger activates the FTM counter synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */ -#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */ -#define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */ -#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */ -#define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT) - -/*! @brief Set the HWRSTCNT field to a new value. */ -#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW) - * - * MOD, CNTIN, and CV registers synchronization is activated by a hardware - * trigger. - * - * Values: - * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers - * synchronization. - * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */ -#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */ -#define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */ -#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */ -#define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF) - -/*! @brief Set the HWWRBUF field to a new value. */ -#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWOM[18] (RW) - * - * Output mask synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the OUTMASK register - * synchronization. - * - 1 - A hardware trigger activates the OUTMASK register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */ -#define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */ -#define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */ -#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */ -#define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM) - -/*! @brief Set the HWOM field to a new value. */ -#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWINVC[19] (RW) - * - * Inverting control synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the INVCTRL register - * synchronization. - * - 1 - A hardware trigger activates the INVCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */ -#define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */ -#define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */ -#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */ -#define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC) - -/*! @brief Set the HWINVC field to a new value. */ -#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWSOC[20] (RW) - * - * Software output control synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the SWOCTRL register - * synchronization. - * - 1 - A hardware trigger activates the SWOCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */ -#define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */ -#define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */ -#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */ -#define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC) - -/*! @brief Set the HWSOC field to a new value. */ -#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_INVCTRL - FTM Inverting Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW) - * - * Reset value: 0x00000000U - * - * This register controls when the channel (n) output becomes the channel (n+1) - * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN - * bit enables the inverting operation for the corresponding pair channels m. This - * register has a write buffer. The INVmEN bit is updated by the INVCTRL - * register synchronization. - */ -typedef union _hw_ftm_invctrl -{ - uint32_t U; - struct _hw_ftm_invctrl_bitfields - { - uint32_t INV0EN : 1; /*!< [0] Pair Channels 0 Inverting Enable */ - uint32_t INV1EN : 1; /*!< [1] Pair Channels 1 Inverting Enable */ - uint32_t INV2EN : 1; /*!< [2] Pair Channels 2 Inverting Enable */ - uint32_t INV3EN : 1; /*!< [3] Pair Channels 3 Inverting Enable */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_ftm_invctrl_t; - -/*! - * @name Constants and macros for entire FTM_INVCTRL register - */ -/*@{*/ -#define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U) - -#define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x)) -#define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U) -#define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v)) -#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v))) -#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v))) -#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_INVCTRL bitfields - */ - -/*! - * @name Register FTM_INVCTRL, field INV0EN[0] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */ -#define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */ -#define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */ -#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */ -#define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN) - -/*! @brief Set the INV0EN field to a new value. */ -#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_INVCTRL, field INV1EN[1] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */ -#define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */ -#define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */ -#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */ -#define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN) - -/*! @brief Set the INV1EN field to a new value. */ -#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_INVCTRL, field INV2EN[2] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */ -#define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */ -#define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */ -#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */ -#define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN) - -/*! @brief Set the INV2EN field to a new value. */ -#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_INVCTRL, field INV3EN[3] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */ -#define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */ -#define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */ -#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */ -#define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN) - -/*! @brief Set the INV3EN field to a new value. */ -#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_SWOCTRL - FTM Software Output Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW) - * - * Reset value: 0x00000000U - * - * This register enables software control of channel (n) output and defines the - * value forced to the channel (n) output: The CHnOC bits enable the control of - * the corresponding channel (n) output by software. The CHnOCV bits select the - * value that is forced at the corresponding channel (n) output. This register has - * a write buffer. The fields are updated by the SWOCTRL register synchronization. - */ -typedef union _hw_ftm_swoctrl -{ - uint32_t U; - struct _hw_ftm_swoctrl_bitfields - { - uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable - * */ - uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable - * */ - uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable - * */ - uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable - * */ - uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable - * */ - uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable - * */ - uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable - * */ - uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable - * */ - uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value - * */ - uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value - * */ - uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control - * Value */ - uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control - * Value */ - uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control - * Value */ - uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control - * Value */ - uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control - * Value */ - uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control - * Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_swoctrl_t; - -/*! - * @name Constants and macros for entire FTM_SWOCTRL register - */ -/*@{*/ -#define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U) - -#define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x)) -#define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U) -#define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v)) -#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v))) -#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v))) -#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SWOCTRL bitfields - */ - -/*! - * @name Register FTM_SWOCTRL, field CH0OC[0] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */ -#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */ -#define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */ -#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */ -#define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC) - -/*! @brief Set the CH0OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH1OC[1] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */ -#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */ -#define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */ -#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */ -#define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC) - -/*! @brief Set the CH1OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH2OC[2] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */ -#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */ -#define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */ -#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */ -#define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC) - -/*! @brief Set the CH2OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH3OC[3] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */ -#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */ -#define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */ -#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */ -#define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC) - -/*! @brief Set the CH3OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH4OC[4] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */ -#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */ -#define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */ -#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */ -#define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC) - -/*! @brief Set the CH4OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH5OC[5] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */ -#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */ -#define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */ -#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */ -#define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC) - -/*! @brief Set the CH5OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH6OC[6] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */ -#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */ -#define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */ -#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */ -#define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC) - -/*! @brief Set the CH6OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH7OC[7] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */ -#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */ -#define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */ -#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */ -#define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC) - -/*! @brief Set the CH7OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */ -#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */ -#define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */ -#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */ -#define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV) - -/*! @brief Set the CH0OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */ -#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */ -#define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */ -#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */ -#define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV) - -/*! @brief Set the CH1OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */ -#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */ -#define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */ -#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */ -#define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV) - -/*! @brief Set the CH2OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */ -#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */ -#define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */ -#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */ -#define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV) - -/*! @brief Set the CH3OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */ -#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */ -#define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */ -#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */ -#define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV) - -/*! @brief Set the CH4OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */ -#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */ -#define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */ -#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */ -#define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV) - -/*! @brief Set the CH5OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */ -#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */ -#define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */ -#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */ -#define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV) - -/*! @brief Set the CH6OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */ -#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */ -#define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */ -#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */ -#define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV) - -/*! @brief Set the CH7OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_PWMLOAD - FTM PWM Load - ******************************************************************************/ - -/*! - * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW) - * - * Reset value: 0x00000000U - * - * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the - * values of their write buffers when the FTM counter changes from the MOD - * register value to its next value or when a channel (j) match occurs. A match occurs - * for the channel (j) when FTM counter = C(j)V. - */ -typedef union _hw_ftm_pwmload -{ - uint32_t U; - struct _hw_ftm_pwmload_bitfields - { - uint32_t CH0SEL : 1; /*!< [0] Channel 0 Select */ - uint32_t CH1SEL : 1; /*!< [1] Channel 1 Select */ - uint32_t CH2SEL : 1; /*!< [2] Channel 2 Select */ - uint32_t CH3SEL : 1; /*!< [3] Channel 3 Select */ - uint32_t CH4SEL : 1; /*!< [4] Channel 4 Select */ - uint32_t CH5SEL : 1; /*!< [5] Channel 5 Select */ - uint32_t CH6SEL : 1; /*!< [6] Channel 6 Select */ - uint32_t CH7SEL : 1; /*!< [7] Channel 7 Select */ - uint32_t RESERVED0 : 1; /*!< [8] */ - uint32_t LDOK : 1; /*!< [9] Load Enable */ - uint32_t RESERVED1 : 22; /*!< [31:10] */ - } B; -} hw_ftm_pwmload_t; - -/*! - * @name Constants and macros for entire FTM_PWMLOAD register - */ -/*@{*/ -#define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U) - -#define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x)) -#define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U) -#define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v)) -#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v))) -#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v))) -#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_PWMLOAD bitfields - */ - -/*! - * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */ -#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */ -#define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */ -#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */ -#define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL) - -/*! @brief Set the CH0SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */ -#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */ -#define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */ -#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */ -#define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL) - -/*! @brief Set the CH1SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */ -#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */ -#define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */ -#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */ -#define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL) - -/*! @brief Set the CH2SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */ -#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */ -#define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */ -#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */ -#define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL) - -/*! @brief Set the CH3SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */ -#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */ -#define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */ -#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */ -#define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL) - -/*! @brief Set the CH4SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */ -#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */ -#define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */ -#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */ -#define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL) - -/*! @brief Set the CH5SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */ -#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */ -#define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */ -#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */ -#define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL) - -/*! @brief Set the CH6SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */ -#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */ -#define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */ -#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */ -#define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL) - -/*! @brief Set the CH7SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field LDOK[9] (RW) - * - * Enables the loading of the MOD, CNTIN, and CV registers with the values of - * their write buffers. - * - * Values: - * - 0 - Loading updated values is disabled. - * - 1 - Loading updated values is enabled. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */ -#define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */ -#define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */ - -/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */ -#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */ -#define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK) - -/*! @brief Set the LDOK field to a new value. */ -#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_ftm_t - module struct - ******************************************************************************/ -/*! - * @brief All FTM module registers. - */ -#pragma pack(1) -typedef struct _hw_ftm -{ - __IO hw_ftm_sc_t SC; /*!< [0x0] Status And Control */ - __IO hw_ftm_cnt_t CNT; /*!< [0x4] Counter */ - __IO hw_ftm_mod_t MOD; /*!< [0x8] Modulo */ - struct { - __IO hw_ftm_cnsc_t CnSC; /*!< [0xC] Channel (n) Status And Control */ - __IO hw_ftm_cnv_t CnV; /*!< [0x10] Channel (n) Value */ - } CONTROLS[8]; - __IO hw_ftm_cntin_t CNTIN; /*!< [0x4C] Counter Initial Value */ - __IO hw_ftm_status_t STATUS; /*!< [0x50] Capture And Compare Status */ - __IO hw_ftm_mode_t MODE; /*!< [0x54] Features Mode Selection */ - __IO hw_ftm_sync_t SYNC; /*!< [0x58] Synchronization */ - __IO hw_ftm_outinit_t OUTINIT; /*!< [0x5C] Initial State For Channels Output */ - __IO hw_ftm_outmask_t OUTMASK; /*!< [0x60] Output Mask */ - __IO hw_ftm_combine_t COMBINE; /*!< [0x64] Function For Linked Channels */ - __IO hw_ftm_deadtime_t DEADTIME; /*!< [0x68] Deadtime Insertion Control */ - __IO hw_ftm_exttrig_t EXTTRIG; /*!< [0x6C] FTM External Trigger */ - __IO hw_ftm_pol_t POL; /*!< [0x70] Channels Polarity */ - __IO hw_ftm_fms_t FMS; /*!< [0x74] Fault Mode Status */ - __IO hw_ftm_filter_t FILTER; /*!< [0x78] Input Capture Filter Control */ - __IO hw_ftm_fltctrl_t FLTCTRL; /*!< [0x7C] Fault Control */ - __IO hw_ftm_qdctrl_t QDCTRL; /*!< [0x80] Quadrature Decoder Control And Status */ - __IO hw_ftm_conf_t CONF; /*!< [0x84] Configuration */ - __IO hw_ftm_fltpol_t FLTPOL; /*!< [0x88] FTM Fault Input Polarity */ - __IO hw_ftm_synconf_t SYNCONF; /*!< [0x8C] Synchronization Configuration */ - __IO hw_ftm_invctrl_t INVCTRL; /*!< [0x90] FTM Inverting Control */ - __IO hw_ftm_swoctrl_t SWOCTRL; /*!< [0x94] FTM Software Output Control */ - __IO hw_ftm_pwmload_t PWMLOAD; /*!< [0x98] FTM PWM Load */ -} hw_ftm_t; -#pragma pack() - -/*! @brief Macro to access all FTM registers. */ -/*! @param x FTM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FTM(FTM0_BASE). */ -#define HW_FTM(x) (*(hw_ftm_t *)(x)) - -#endif /* __HW_FTM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h deleted file mode 100644 index 24e3b452a14..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h +++ /dev/null @@ -1,487 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_GPIO_REGISTERS_H__ -#define __HW_GPIO_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 GPIO - * - * General Purpose Input/Output - * - * Registers defined in this header file: - * - HW_GPIO_PDOR - Port Data Output Register - * - HW_GPIO_PSOR - Port Set Output Register - * - HW_GPIO_PCOR - Port Clear Output Register - * - HW_GPIO_PTOR - Port Toggle Output Register - * - HW_GPIO_PDIR - Port Data Input Register - * - HW_GPIO_PDDR - Port Data Direction Register - * - * - hw_gpio_t - Struct containing all module registers. - */ - -#define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */ -#define HW_GPIOA (0U) /*!< Instance number for GPIOA. */ -#define HW_GPIOB (1U) /*!< Instance number for GPIOB. */ -#define HW_GPIOC (2U) /*!< Instance number for GPIOC. */ -#define HW_GPIOD (3U) /*!< Instance number for GPIOD. */ -#define HW_GPIOE (4U) /*!< Instance number for GPIOE. */ - -/******************************************************************************* - * HW_GPIO_PDOR - Port Data Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PDOR - Port Data Output Register (RW) - * - * Reset value: 0x00000000U - * - * This register configures the logic levels that are driven on each - * general-purpose output pins. Do not modify pin configuration registers associated with - * pins not available in your selected package. All unbonded pins not available in - * your package will default to DISABLE state for lowest power consumption. - */ -typedef union _hw_gpio_pdor -{ - uint32_t U; - struct _hw_gpio_pdor_bitfields - { - uint32_t PDO : 32; /*!< [31:0] Port Data Output */ - } B; -} hw_gpio_pdor_t; - -/*! - * @name Constants and macros for entire GPIO_PDOR register - */ -/*@{*/ -#define HW_GPIO_PDOR_ADDR(x) ((x) + 0x0U) - -#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x)) -#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U) -#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v)) -#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v))) -#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v))) -#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PDOR bitfields - */ - -/*! - * @name Register GPIO_PDOR, field PDO[31:0] (RW) - * - * Register bits for unbonded pins return a undefined value when read. - * - * Values: - * - 0 - Logic level 0 is driven on pin, provided pin is configured for - * general-purpose output. - * - 1 - Logic level 1 is driven on pin, provided pin is configured for - * general-purpose output. - */ -/*@{*/ -#define BP_GPIO_PDOR_PDO (0U) /*!< Bit position for GPIO_PDOR_PDO. */ -#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */ -#define BS_GPIO_PDOR_PDO (32U) /*!< Bit field size in bits for GPIO_PDOR_PDO. */ - -/*! @brief Read current value of the GPIO_PDOR_PDO field. */ -#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U) - -/*! @brief Format value for bitfield GPIO_PDOR_PDO. */ -#define BF_GPIO_PDOR_PDO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO) - -/*! @brief Set the PDO field to a new value. */ -#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PSOR - Port Set Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ) - * - * Reset value: 0x00000000U - * - * This register configures whether to set the fields of the PDOR. - */ -typedef union _hw_gpio_psor -{ - uint32_t U; - struct _hw_gpio_psor_bitfields - { - uint32_t PTSO : 32; /*!< [31:0] Port Set Output */ - } B; -} hw_gpio_psor_t; - -/*! - * @name Constants and macros for entire GPIO_PSOR register - */ -/*@{*/ -#define HW_GPIO_PSOR_ADDR(x) ((x) + 0x4U) - -#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x)) -#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U) -#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PSOR bitfields - */ - -/*! - * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ) - * - * Writing to this register will update the contents of the corresponding bit in - * the PDOR as follows: - * - * Values: - * - 0 - Corresponding bit in PDORn does not change. - * - 1 - Corresponding bit in PDORn is set to logic 1. - */ -/*@{*/ -#define BP_GPIO_PSOR_PTSO (0U) /*!< Bit position for GPIO_PSOR_PTSO. */ -#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */ -#define BS_GPIO_PSOR_PTSO (32U) /*!< Bit field size in bits for GPIO_PSOR_PTSO. */ - -/*! @brief Format value for bitfield GPIO_PSOR_PTSO. */ -#define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO) - -/*! @brief Set the PTSO field to a new value. */ -#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PCOR - Port Clear Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ) - * - * Reset value: 0x00000000U - * - * This register configures whether to clear the fields of PDOR. - */ -typedef union _hw_gpio_pcor -{ - uint32_t U; - struct _hw_gpio_pcor_bitfields - { - uint32_t PTCO : 32; /*!< [31:0] Port Clear Output */ - } B; -} hw_gpio_pcor_t; - -/*! - * @name Constants and macros for entire GPIO_PCOR register - */ -/*@{*/ -#define HW_GPIO_PCOR_ADDR(x) ((x) + 0x8U) - -#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x)) -#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U) -#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PCOR bitfields - */ - -/*! - * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ) - * - * Writing to this register will update the contents of the corresponding bit in - * the Port Data Output Register (PDOR) as follows: - * - * Values: - * - 0 - Corresponding bit in PDORn does not change. - * - 1 - Corresponding bit in PDORn is cleared to logic 0. - */ -/*@{*/ -#define BP_GPIO_PCOR_PTCO (0U) /*!< Bit position for GPIO_PCOR_PTCO. */ -#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */ -#define BS_GPIO_PCOR_PTCO (32U) /*!< Bit field size in bits for GPIO_PCOR_PTCO. */ - -/*! @brief Format value for bitfield GPIO_PCOR_PTCO. */ -#define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO) - -/*! @brief Set the PTCO field to a new value. */ -#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PTOR - Port Toggle Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ) - * - * Reset value: 0x00000000U - */ -typedef union _hw_gpio_ptor -{ - uint32_t U; - struct _hw_gpio_ptor_bitfields - { - uint32_t PTTO : 32; /*!< [31:0] Port Toggle Output */ - } B; -} hw_gpio_ptor_t; - -/*! - * @name Constants and macros for entire GPIO_PTOR register - */ -/*@{*/ -#define HW_GPIO_PTOR_ADDR(x) ((x) + 0xCU) - -#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x)) -#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U) -#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PTOR bitfields - */ - -/*! - * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ) - * - * Writing to this register will update the contents of the corresponding bit in - * the PDOR as follows: - * - * Values: - * - 0 - Corresponding bit in PDORn does not change. - * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic - * state. - */ -/*@{*/ -#define BP_GPIO_PTOR_PTTO (0U) /*!< Bit position for GPIO_PTOR_PTTO. */ -#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */ -#define BS_GPIO_PTOR_PTTO (32U) /*!< Bit field size in bits for GPIO_PTOR_PTTO. */ - -/*! @brief Format value for bitfield GPIO_PTOR_PTTO. */ -#define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO) - -/*! @brief Set the PTTO field to a new value. */ -#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PDIR - Port Data Input Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PDIR - Port Data Input Register (RO) - * - * Reset value: 0x00000000U - * - * Do not modify pin configuration registers associated with pins not available - * in your selected package. All unbonded pins not available in your package will - * default to DISABLE state for lowest power consumption. - */ -typedef union _hw_gpio_pdir -{ - uint32_t U; - struct _hw_gpio_pdir_bitfields - { - uint32_t PDI : 32; /*!< [31:0] Port Data Input */ - } B; -} hw_gpio_pdir_t; - -/*! - * @name Constants and macros for entire GPIO_PDIR register - */ -/*@{*/ -#define HW_GPIO_PDIR_ADDR(x) ((x) + 0x10U) - -#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x)) -#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PDIR bitfields - */ - -/*! - * @name Register GPIO_PDIR, field PDI[31:0] (RO) - * - * Reads 0 at the unimplemented pins for a particular device. Pins that are not - * configured for a digital function read 0. If the Port Control and Interrupt - * module is disabled, then the corresponding bit in PDIR does not update. - * - * Values: - * - 0 - Pin logic level is logic 0, or is not configured for use by digital - * function. - * - 1 - Pin logic level is logic 1. - */ -/*@{*/ -#define BP_GPIO_PDIR_PDI (0U) /*!< Bit position for GPIO_PDIR_PDI. */ -#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */ -#define BS_GPIO_PDIR_PDI (32U) /*!< Bit field size in bits for GPIO_PDIR_PDI. */ - -/*! @brief Read current value of the GPIO_PDIR_PDI field. */ -#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PDDR - Port Data Direction Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PDDR - Port Data Direction Register (RW) - * - * Reset value: 0x00000000U - * - * The PDDR configures the individual port pins for input or output. - */ -typedef union _hw_gpio_pddr -{ - uint32_t U; - struct _hw_gpio_pddr_bitfields - { - uint32_t PDD : 32; /*!< [31:0] Port Data Direction */ - } B; -} hw_gpio_pddr_t; - -/*! - * @name Constants and macros for entire GPIO_PDDR register - */ -/*@{*/ -#define HW_GPIO_PDDR_ADDR(x) ((x) + 0x14U) - -#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x)) -#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U) -#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v)) -#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v))) -#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v))) -#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PDDR bitfields - */ - -/*! - * @name Register GPIO_PDDR, field PDD[31:0] (RW) - * - * Configures individual port pins for input or output. - * - * Values: - * - 0 - Pin is configured as general-purpose input, for the GPIO function. - * - 1 - Pin is configured as general-purpose output, for the GPIO function. - */ -/*@{*/ -#define BP_GPIO_PDDR_PDD (0U) /*!< Bit position for GPIO_PDDR_PDD. */ -#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */ -#define BS_GPIO_PDDR_PDD (32U) /*!< Bit field size in bits for GPIO_PDDR_PDD. */ - -/*! @brief Read current value of the GPIO_PDDR_PDD field. */ -#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U) - -/*! @brief Format value for bitfield GPIO_PDDR_PDD. */ -#define BF_GPIO_PDDR_PDD(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD) - -/*! @brief Set the PDD field to a new value. */ -#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_gpio_t - module struct - ******************************************************************************/ -/*! - * @brief All GPIO module registers. - */ -#pragma pack(1) -typedef struct _hw_gpio -{ - __IO hw_gpio_pdor_t PDOR; /*!< [0x0] Port Data Output Register */ - __O hw_gpio_psor_t PSOR; /*!< [0x4] Port Set Output Register */ - __O hw_gpio_pcor_t PCOR; /*!< [0x8] Port Clear Output Register */ - __O hw_gpio_ptor_t PTOR; /*!< [0xC] Port Toggle Output Register */ - __I hw_gpio_pdir_t PDIR; /*!< [0x10] Port Data Input Register */ - __IO hw_gpio_pddr_t PDDR; /*!< [0x14] Port Data Direction Register */ -} hw_gpio_t; -#pragma pack() - -/*! @brief Macro to access all GPIO registers. */ -/*! @param x GPIO module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_GPIO(GPIOA_BASE). */ -#define HW_GPIO(x) (*(hw_gpio_t *)(x)) - -#endif /* __HW_GPIO_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h deleted file mode 100644 index 70868704ce7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h +++ /dev/null @@ -1,1724 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_I2C_REGISTERS_H__ -#define __HW_I2C_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 I2C - * - * Inter-Integrated Circuit - * - * Registers defined in this header file: - * - HW_I2C_A1 - I2C Address Register 1 - * - HW_I2C_F - I2C Frequency Divider register - * - HW_I2C_C1 - I2C Control Register 1 - * - HW_I2C_S - I2C Status register - * - HW_I2C_D - I2C Data I/O register - * - HW_I2C_C2 - I2C Control Register 2 - * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register - * - HW_I2C_RA - I2C Range Address register - * - HW_I2C_SMB - I2C SMBus Control and Status register - * - HW_I2C_A2 - I2C Address Register 2 - * - HW_I2C_SLTH - I2C SCL Low Timeout Register High - * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low - * - * - hw_i2c_t - Struct containing all module registers. - */ - -#define HW_I2C_INSTANCE_COUNT (2U) /*!< Number of instances of the I2C module. */ -#define HW_I2C0 (0U) /*!< Instance number for I2C0. */ -#define HW_I2C1 (1U) /*!< Instance number for I2C1. */ - -/******************************************************************************* - * HW_I2C_A1 - I2C Address Register 1 - ******************************************************************************/ - -/*! - * @brief HW_I2C_A1 - I2C Address Register 1 (RW) - * - * Reset value: 0x00U - * - * This register contains the slave address to be used by the I2C module. - */ -typedef union _hw_i2c_a1 -{ - uint8_t U; - struct _hw_i2c_a1_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t AD : 7; /*!< [7:1] Address */ - } B; -} hw_i2c_a1_t; - -/*! - * @name Constants and macros for entire I2C_A1 register - */ -/*@{*/ -#define HW_I2C_A1_ADDR(x) ((x) + 0x0U) - -#define HW_I2C_A1(x) (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x)) -#define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U) -#define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v)) -#define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) | (v))) -#define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v))) -#define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_A1 bitfields - */ - -/*! - * @name Register I2C_A1, field AD[7:1] (RW) - * - * Contains the primary slave address used by the I2C module when it is - * addressed as a slave. This field is used in the 7-bit address scheme and the lower - * seven bits in the 10-bit address scheme. - */ -/*@{*/ -#define BP_I2C_A1_AD (1U) /*!< Bit position for I2C_A1_AD. */ -#define BM_I2C_A1_AD (0xFEU) /*!< Bit mask for I2C_A1_AD. */ -#define BS_I2C_A1_AD (7U) /*!< Bit field size in bits for I2C_A1_AD. */ - -/*! @brief Read current value of the I2C_A1_AD field. */ -#define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD) - -/*! @brief Format value for bitfield I2C_A1_AD. */ -#define BF_I2C_A1_AD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_A1_AD) & BM_I2C_A1_AD) - -/*! @brief Set the AD field to a new value. */ -#define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_F - I2C Frequency Divider register - ******************************************************************************/ - -/*! - * @brief HW_I2C_F - I2C Frequency Divider register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_f -{ - uint8_t U; - struct _hw_i2c_f_bitfields - { - uint8_t ICR : 6; /*!< [5:0] ClockRate */ - uint8_t MULT : 2; /*!< [7:6] Multiplier Factor */ - } B; -} hw_i2c_f_t; - -/*! - * @name Constants and macros for entire I2C_F register - */ -/*@{*/ -#define HW_I2C_F_ADDR(x) ((x) + 0x1U) - -#define HW_I2C_F(x) (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x)) -#define HW_I2C_F_RD(x) (HW_I2C_F(x).U) -#define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v)) -#define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) | (v))) -#define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v))) -#define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_F bitfields - */ - -/*! - * @name Register I2C_F, field ICR[5:0] (RW) - * - * Prescales the I2C module clock for bit rate selection. This field and the - * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold - * time, and the SCL stop hold time. For a list of values corresponding to each ICR - * setting, see I2C divider and hold values. The SCL divider multiplied by - * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module - * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the - * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time = - * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is - * the delay from the falling edge of SDA (I2C data) while SCL is high (start - * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C - * module clock period (s) * mul * SCL start hold value The SCL stop hold time is - * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C - * data) while SCL is high (stop condition). SCL stop hold time = I2C module - * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock - * speed is 8 MHz, the following table shows the possible hold time values with - * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s. - * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h - * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h - * 1.125 4.750 5.125 - */ -/*@{*/ -#define BP_I2C_F_ICR (0U) /*!< Bit position for I2C_F_ICR. */ -#define BM_I2C_F_ICR (0x3FU) /*!< Bit mask for I2C_F_ICR. */ -#define BS_I2C_F_ICR (6U) /*!< Bit field size in bits for I2C_F_ICR. */ - -/*! @brief Read current value of the I2C_F_ICR field. */ -#define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR) - -/*! @brief Format value for bitfield I2C_F_ICR. */ -#define BF_I2C_F_ICR(v) ((uint8_t)((uint8_t)(v) << BP_I2C_F_ICR) & BM_I2C_F_ICR) - -/*! @brief Set the ICR field to a new value. */ -#define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v))) -/*@}*/ - -/*! - * @name Register I2C_F, field MULT[7:6] (RW) - * - * Defines the multiplier factor (mul). This factor is used along with the SCL - * divider to generate the I2C baud rate. - * - * Values: - * - 00 - mul = 1 - * - 01 - mul = 2 - * - 10 - mul = 4 - * - 11 - Reserved - */ -/*@{*/ -#define BP_I2C_F_MULT (6U) /*!< Bit position for I2C_F_MULT. */ -#define BM_I2C_F_MULT (0xC0U) /*!< Bit mask for I2C_F_MULT. */ -#define BS_I2C_F_MULT (2U) /*!< Bit field size in bits for I2C_F_MULT. */ - -/*! @brief Read current value of the I2C_F_MULT field. */ -#define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT) - -/*! @brief Format value for bitfield I2C_F_MULT. */ -#define BF_I2C_F_MULT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_F_MULT) & BM_I2C_F_MULT) - -/*! @brief Set the MULT field to a new value. */ -#define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_C1 - I2C Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_I2C_C1 - I2C Control Register 1 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_c1 -{ - uint8_t U; - struct _hw_i2c_c1_bitfields - { - uint8_t DMAEN : 1; /*!< [0] DMA Enable */ - uint8_t WUEN : 1; /*!< [1] Wakeup Enable */ - uint8_t RSTA : 1; /*!< [2] Repeat START */ - uint8_t TXAK : 1; /*!< [3] Transmit Acknowledge Enable */ - uint8_t TX : 1; /*!< [4] Transmit Mode Select */ - uint8_t MST : 1; /*!< [5] Master Mode Select */ - uint8_t IICIE : 1; /*!< [6] I2C Interrupt Enable */ - uint8_t IICEN : 1; /*!< [7] I2C Enable */ - } B; -} hw_i2c_c1_t; - -/*! - * @name Constants and macros for entire I2C_C1 register - */ -/*@{*/ -#define HW_I2C_C1_ADDR(x) ((x) + 0x2U) - -#define HW_I2C_C1(x) (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x)) -#define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U) -#define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v)) -#define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) | (v))) -#define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v))) -#define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_C1 bitfields - */ - -/*! - * @name Register I2C_C1, field DMAEN[0] (RW) - * - * Enables or disables the DMA function. - * - * Values: - * - 0 - All DMA signalling disabled. - * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions - * trigger the DMA request: a data byte is received, and either address or - * data is transmitted. (ACK/NACK is automatic) the first byte received matches - * the A1 register or is a general call address. If any address matching - * occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known - * from master to slave, then it is not required to check S[SRW]. With this - * assumption, DMA can also be used in this case. In other cases, if the master - * reads data from the slave, then it is required to rewrite the C1 register - * operation. With this assumption, DMA cannot be used. When FACK = 1, an - * address or a data byte is transmitted. - */ -/*@{*/ -#define BP_I2C_C1_DMAEN (0U) /*!< Bit position for I2C_C1_DMAEN. */ -#define BM_I2C_C1_DMAEN (0x01U) /*!< Bit mask for I2C_C1_DMAEN. */ -#define BS_I2C_C1_DMAEN (1U) /*!< Bit field size in bits for I2C_C1_DMAEN. */ - -/*! @brief Read current value of the I2C_C1_DMAEN field. */ -#define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN)) - -/*! @brief Format value for bitfield I2C_C1_DMAEN. */ -#define BF_I2C_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_DMAEN) & BM_I2C_C1_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field WUEN[1] (RW) - * - * The I2C module can wake the MCU from low power mode with no peripheral bus - * running when slave address matching occurs. - * - * Values: - * - 0 - Normal operation. No interrupt generated when address matching in low - * power mode. - * - 1 - Enables the wakeup function in low power mode. - */ -/*@{*/ -#define BP_I2C_C1_WUEN (1U) /*!< Bit position for I2C_C1_WUEN. */ -#define BM_I2C_C1_WUEN (0x02U) /*!< Bit mask for I2C_C1_WUEN. */ -#define BS_I2C_C1_WUEN (1U) /*!< Bit field size in bits for I2C_C1_WUEN. */ - -/*! @brief Read current value of the I2C_C1_WUEN field. */ -#define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN)) - -/*! @brief Format value for bitfield I2C_C1_WUEN. */ -#define BF_I2C_C1_WUEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_WUEN) & BM_I2C_C1_WUEN) - -/*! @brief Set the WUEN field to a new value. */ -#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field RSTA[2] (WORZ) - * - * Writing 1 to this bit generates a repeated START condition provided it is the - * current master. This bit will always be read as 0. Attempting a repeat at the - * wrong time results in loss of arbitration. - */ -/*@{*/ -#define BP_I2C_C1_RSTA (2U) /*!< Bit position for I2C_C1_RSTA. */ -#define BM_I2C_C1_RSTA (0x04U) /*!< Bit mask for I2C_C1_RSTA. */ -#define BS_I2C_C1_RSTA (1U) /*!< Bit field size in bits for I2C_C1_RSTA. */ - -/*! @brief Format value for bitfield I2C_C1_RSTA. */ -#define BF_I2C_C1_RSTA(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_RSTA) & BM_I2C_C1_RSTA) - -/*! @brief Set the RSTA field to a new value. */ -#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field TXAK[3] (RW) - * - * Specifies the value driven onto the SDA during data acknowledge cycles for - * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK - * generation. SCL is held low until TXAK is written. - * - * Values: - * - 0 - An acknowledge signal is sent to the bus on the following receiving - * byte (if FACK is cleared) or the current receiving byte (if FACK is set). - * - 1 - No acknowledge signal is sent to the bus on the following receiving - * data byte (if FACK is cleared) or the current receiving data byte (if FACK is - * set). - */ -/*@{*/ -#define BP_I2C_C1_TXAK (3U) /*!< Bit position for I2C_C1_TXAK. */ -#define BM_I2C_C1_TXAK (0x08U) /*!< Bit mask for I2C_C1_TXAK. */ -#define BS_I2C_C1_TXAK (1U) /*!< Bit field size in bits for I2C_C1_TXAK. */ - -/*! @brief Read current value of the I2C_C1_TXAK field. */ -#define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK)) - -/*! @brief Format value for bitfield I2C_C1_TXAK. */ -#define BF_I2C_C1_TXAK(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TXAK) & BM_I2C_C1_TXAK) - -/*! @brief Set the TXAK field to a new value. */ -#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field TX[4] (RW) - * - * Selects the direction of master and slave transfers. In master mode this bit - * must be set according to the type of transfer required. Therefore, for address - * cycles, this bit is always set. When addressed as a slave this bit must be - * set by software according to the SRW bit in the status register. - * - * Values: - * - 0 - Receive - * - 1 - Transmit - */ -/*@{*/ -#define BP_I2C_C1_TX (4U) /*!< Bit position for I2C_C1_TX. */ -#define BM_I2C_C1_TX (0x10U) /*!< Bit mask for I2C_C1_TX. */ -#define BS_I2C_C1_TX (1U) /*!< Bit field size in bits for I2C_C1_TX. */ - -/*! @brief Read current value of the I2C_C1_TX field. */ -#define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX)) - -/*! @brief Format value for bitfield I2C_C1_TX. */ -#define BF_I2C_C1_TX(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TX) & BM_I2C_C1_TX) - -/*! @brief Set the TX field to a new value. */ -#define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field MST[5] (RW) - * - * When MST is changed from 0 to 1, a START signal is generated on the bus and - * master mode is selected. When this bit changes from 1 to 0, a STOP signal is - * generated and the mode of operation changes from master to slave. - * - * Values: - * - 0 - Slave mode - * - 1 - Master mode - */ -/*@{*/ -#define BP_I2C_C1_MST (5U) /*!< Bit position for I2C_C1_MST. */ -#define BM_I2C_C1_MST (0x20U) /*!< Bit mask for I2C_C1_MST. */ -#define BS_I2C_C1_MST (1U) /*!< Bit field size in bits for I2C_C1_MST. */ - -/*! @brief Read current value of the I2C_C1_MST field. */ -#define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST)) - -/*! @brief Format value for bitfield I2C_C1_MST. */ -#define BF_I2C_C1_MST(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_MST) & BM_I2C_C1_MST) - -/*! @brief Set the MST field to a new value. */ -#define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field IICIE[6] (RW) - * - * Enables I2C interrupt requests. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_I2C_C1_IICIE (6U) /*!< Bit position for I2C_C1_IICIE. */ -#define BM_I2C_C1_IICIE (0x40U) /*!< Bit mask for I2C_C1_IICIE. */ -#define BS_I2C_C1_IICIE (1U) /*!< Bit field size in bits for I2C_C1_IICIE. */ - -/*! @brief Read current value of the I2C_C1_IICIE field. */ -#define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE)) - -/*! @brief Format value for bitfield I2C_C1_IICIE. */ -#define BF_I2C_C1_IICIE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICIE) & BM_I2C_C1_IICIE) - -/*! @brief Set the IICIE field to a new value. */ -#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field IICEN[7] (RW) - * - * Enables I2C module operation. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_I2C_C1_IICEN (7U) /*!< Bit position for I2C_C1_IICEN. */ -#define BM_I2C_C1_IICEN (0x80U) /*!< Bit mask for I2C_C1_IICEN. */ -#define BS_I2C_C1_IICEN (1U) /*!< Bit field size in bits for I2C_C1_IICEN. */ - -/*! @brief Read current value of the I2C_C1_IICEN field. */ -#define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN)) - -/*! @brief Format value for bitfield I2C_C1_IICEN. */ -#define BF_I2C_C1_IICEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICEN) & BM_I2C_C1_IICEN) - -/*! @brief Set the IICEN field to a new value. */ -#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_S - I2C Status register - ******************************************************************************/ - -/*! - * @brief HW_I2C_S - I2C Status register (RW) - * - * Reset value: 0x80U - */ -typedef union _hw_i2c_s -{ - uint8_t U; - struct _hw_i2c_s_bitfields - { - uint8_t RXAK : 1; /*!< [0] Receive Acknowledge */ - uint8_t IICIF : 1; /*!< [1] Interrupt Flag */ - uint8_t SRW : 1; /*!< [2] Slave Read/Write */ - uint8_t RAM : 1; /*!< [3] Range Address Match */ - uint8_t ARBL : 1; /*!< [4] Arbitration Lost */ - uint8_t BUSY : 1; /*!< [5] Bus Busy */ - uint8_t IAAS : 1; /*!< [6] Addressed As A Slave */ - uint8_t TCF : 1; /*!< [7] Transfer Complete Flag */ - } B; -} hw_i2c_s_t; - -/*! - * @name Constants and macros for entire I2C_S register - */ -/*@{*/ -#define HW_I2C_S_ADDR(x) ((x) + 0x3U) - -#define HW_I2C_S(x) (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x)) -#define HW_I2C_S_RD(x) (HW_I2C_S(x).U) -#define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v)) -#define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) | (v))) -#define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v))) -#define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_S bitfields - */ - -/*! - * @name Register I2C_S, field RXAK[0] (RO) - * - * Values: - * - 0 - Acknowledge signal was received after the completion of one byte of - * data transmission on the bus - * - 1 - No acknowledge signal detected - */ -/*@{*/ -#define BP_I2C_S_RXAK (0U) /*!< Bit position for I2C_S_RXAK. */ -#define BM_I2C_S_RXAK (0x01U) /*!< Bit mask for I2C_S_RXAK. */ -#define BS_I2C_S_RXAK (1U) /*!< Bit field size in bits for I2C_S_RXAK. */ - -/*! @brief Read current value of the I2C_S_RXAK field. */ -#define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK)) -/*@}*/ - -/*! - * @name Register I2C_S, field IICIF[1] (W1C) - * - * This bit sets when an interrupt is pending. This bit must be cleared by - * software by writing 1 to it, such as in the interrupt routine. One of the following - * events can set this bit: One byte transfer, including ACK/NACK bit, completes - * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK - * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit, - * completes if FACK is 1. Match of slave address to calling address including - * primary slave address, range slave address , alert response address, second - * slave address, or general call address. Arbitration lost In SMBus mode, any - * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the - * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or - * start detection interrupt: In the interrupt service routine, first clear the - * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and - * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is - * asserted again. - * - * Values: - * - 0 - No interrupt pending - * - 1 - Interrupt pending - */ -/*@{*/ -#define BP_I2C_S_IICIF (1U) /*!< Bit position for I2C_S_IICIF. */ -#define BM_I2C_S_IICIF (0x02U) /*!< Bit mask for I2C_S_IICIF. */ -#define BS_I2C_S_IICIF (1U) /*!< Bit field size in bits for I2C_S_IICIF. */ - -/*! @brief Read current value of the I2C_S_IICIF field. */ -#define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF)) - -/*! @brief Format value for bitfield I2C_S_IICIF. */ -#define BF_I2C_S_IICIF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_IICIF) & BM_I2C_S_IICIF) - -/*! @brief Set the IICIF field to a new value. */ -#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field SRW[2] (RO) - * - * When addressed as a slave, SRW indicates the value of the R/W command bit of - * the calling address sent to the master. - * - * Values: - * - 0 - Slave receive, master writing to slave - * - 1 - Slave transmit, master reading from slave - */ -/*@{*/ -#define BP_I2C_S_SRW (2U) /*!< Bit position for I2C_S_SRW. */ -#define BM_I2C_S_SRW (0x04U) /*!< Bit mask for I2C_S_SRW. */ -#define BS_I2C_S_SRW (1U) /*!< Bit field size in bits for I2C_S_SRW. */ - -/*! @brief Read current value of the I2C_S_SRW field. */ -#define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW)) -/*@}*/ - -/*! - * @name Register I2C_S, field RAM[3] (RW) - * - * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1: - * Any nonzero calling address is received that matches the address in the RA - * register. The calling address is within the range of values of the A1 and RA - * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1. - * Writing the C1 register with any value clears this bit to 0. - * - * Values: - * - 0 - Not addressed - * - 1 - Addressed as a slave - */ -/*@{*/ -#define BP_I2C_S_RAM (3U) /*!< Bit position for I2C_S_RAM. */ -#define BM_I2C_S_RAM (0x08U) /*!< Bit mask for I2C_S_RAM. */ -#define BS_I2C_S_RAM (1U) /*!< Bit field size in bits for I2C_S_RAM. */ - -/*! @brief Read current value of the I2C_S_RAM field. */ -#define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM)) - -/*! @brief Format value for bitfield I2C_S_RAM. */ -#define BF_I2C_S_RAM(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_RAM) & BM_I2C_S_RAM) - -/*! @brief Set the RAM field to a new value. */ -#define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field ARBL[4] (W1C) - * - * This bit is set by hardware when the arbitration procedure is lost. The ARBL - * bit must be cleared by software, by writing 1 to it. - * - * Values: - * - 0 - Standard bus operation. - * - 1 - Loss of arbitration. - */ -/*@{*/ -#define BP_I2C_S_ARBL (4U) /*!< Bit position for I2C_S_ARBL. */ -#define BM_I2C_S_ARBL (0x10U) /*!< Bit mask for I2C_S_ARBL. */ -#define BS_I2C_S_ARBL (1U) /*!< Bit field size in bits for I2C_S_ARBL. */ - -/*! @brief Read current value of the I2C_S_ARBL field. */ -#define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL)) - -/*! @brief Format value for bitfield I2C_S_ARBL. */ -#define BF_I2C_S_ARBL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_ARBL) & BM_I2C_S_ARBL) - -/*! @brief Set the ARBL field to a new value. */ -#define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field BUSY[5] (RO) - * - * Indicates the status of the bus regardless of slave or master mode. This bit - * is set when a START signal is detected and cleared when a STOP signal is - * detected. - * - * Values: - * - 0 - Bus is idle - * - 1 - Bus is busy - */ -/*@{*/ -#define BP_I2C_S_BUSY (5U) /*!< Bit position for I2C_S_BUSY. */ -#define BM_I2C_S_BUSY (0x20U) /*!< Bit mask for I2C_S_BUSY. */ -#define BS_I2C_S_BUSY (1U) /*!< Bit field size in bits for I2C_S_BUSY. */ - -/*! @brief Read current value of the I2C_S_BUSY field. */ -#define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY)) -/*@}*/ - -/*! - * @name Register I2C_S, field IAAS[6] (RW) - * - * This bit is set by one of the following conditions: The calling address - * matches the programmed primary slave address in the A1 register, or matches the - * range address in the RA register (which must be set to a nonzero value and under - * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is - * received. SMB[SIICAEN] is set and the calling address matches the second programmed - * slave address. ALERTEN is set and an SMBus alert response address is received - * RMEN is set and an address is received that is within the range between the - * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must - * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any - * value clears this bit. - * - * Values: - * - 0 - Not addressed - * - 1 - Addressed as a slave - */ -/*@{*/ -#define BP_I2C_S_IAAS (6U) /*!< Bit position for I2C_S_IAAS. */ -#define BM_I2C_S_IAAS (0x40U) /*!< Bit mask for I2C_S_IAAS. */ -#define BS_I2C_S_IAAS (1U) /*!< Bit field size in bits for I2C_S_IAAS. */ - -/*! @brief Read current value of the I2C_S_IAAS field. */ -#define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS)) - -/*! @brief Format value for bitfield I2C_S_IAAS. */ -#define BF_I2C_S_IAAS(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_IAAS) & BM_I2C_S_IAAS) - -/*! @brief Set the IAAS field to a new value. */ -#define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field TCF[7] (RO) - * - * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer. - * This bit is valid only during or immediately following a transfer to or from - * the I2C module. TCF is cleared by reading the I2C data register in receive mode - * or by writing to the I2C data register in transmit mode. - * - * Values: - * - 0 - Transfer in progress - * - 1 - Transfer complete - */ -/*@{*/ -#define BP_I2C_S_TCF (7U) /*!< Bit position for I2C_S_TCF. */ -#define BM_I2C_S_TCF (0x80U) /*!< Bit mask for I2C_S_TCF. */ -#define BS_I2C_S_TCF (1U) /*!< Bit field size in bits for I2C_S_TCF. */ - -/*! @brief Read current value of the I2C_S_TCF field. */ -#define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_D - I2C Data I/O register - ******************************************************************************/ - -/*! - * @brief HW_I2C_D - I2C Data I/O register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_d -{ - uint8_t U; - struct _hw_i2c_d_bitfields - { - uint8_t DATA : 8; /*!< [7:0] Data */ - } B; -} hw_i2c_d_t; - -/*! - * @name Constants and macros for entire I2C_D register - */ -/*@{*/ -#define HW_I2C_D_ADDR(x) ((x) + 0x4U) - -#define HW_I2C_D(x) (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x)) -#define HW_I2C_D_RD(x) (HW_I2C_D(x).U) -#define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v)) -#define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) | (v))) -#define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v))) -#define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_D bitfields - */ - -/*! - * @name Register I2C_D, field DATA[7:0] (RW) - * - * In master transmit mode, when data is written to this register, a data - * transfer is initiated. The most significant bit is sent first. In master receive - * mode, reading this register initiates receiving of the next byte of data. When - * making the transition out of master receive mode, switch the I2C mode before - * reading the Data register to prevent an inadvertent initiation of a master - * receive data transfer. In slave mode, the same functions are available after an - * address match occurs. The C1[TX] bit must correctly reflect the desired direction - * of transfer in master and slave modes for the transmission to begin. For - * example, if the I2C module is configured for master transmit but a master receive - * is desired, reading the Data register does not initiate the receive. Reading - * the Data register returns the last byte received while the I2C module is - * configured in master receive or slave receive mode. The Data register does not - * reflect every byte that is transmitted on the I2C bus, and neither can software - * verify that a byte has been written to the Data register correctly by reading it - * back. In master transmit mode, the first byte of data written to the Data - * register following assertion of MST (start bit) or assertion of RSTA (repeated - * start bit) is used for the address transfer and must consist of the calling - * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0). - */ -/*@{*/ -#define BP_I2C_D_DATA (0U) /*!< Bit position for I2C_D_DATA. */ -#define BM_I2C_D_DATA (0xFFU) /*!< Bit mask for I2C_D_DATA. */ -#define BS_I2C_D_DATA (8U) /*!< Bit field size in bits for I2C_D_DATA. */ - -/*! @brief Read current value of the I2C_D_DATA field. */ -#define BR_I2C_D_DATA(x) (HW_I2C_D(x).U) - -/*! @brief Format value for bitfield I2C_D_DATA. */ -#define BF_I2C_D_DATA(v) ((uint8_t)((uint8_t)(v) << BP_I2C_D_DATA) & BM_I2C_D_DATA) - -/*! @brief Set the DATA field to a new value. */ -#define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_C2 - I2C Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_I2C_C2 - I2C Control Register 2 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_c2 -{ - uint8_t U; - struct _hw_i2c_c2_bitfields - { - uint8_t AD : 3; /*!< [2:0] Slave Address */ - uint8_t RMEN : 1; /*!< [3] Range Address Matching Enable */ - uint8_t SBRC : 1; /*!< [4] Slave Baud Rate Control */ - uint8_t HDRS : 1; /*!< [5] High Drive Select */ - uint8_t ADEXT : 1; /*!< [6] Address Extension */ - uint8_t GCAEN : 1; /*!< [7] General Call Address Enable */ - } B; -} hw_i2c_c2_t; - -/*! - * @name Constants and macros for entire I2C_C2 register - */ -/*@{*/ -#define HW_I2C_C2_ADDR(x) ((x) + 0x5U) - -#define HW_I2C_C2(x) (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x)) -#define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U) -#define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v)) -#define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) | (v))) -#define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v))) -#define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_C2 bitfields - */ - -/*! - * @name Register I2C_C2, field AD[2:0] (RW) - * - * Contains the upper three bits of the slave address in the 10-bit address - * scheme. This field is valid only while the ADEXT bit is set. - */ -/*@{*/ -#define BP_I2C_C2_AD (0U) /*!< Bit position for I2C_C2_AD. */ -#define BM_I2C_C2_AD (0x07U) /*!< Bit mask for I2C_C2_AD. */ -#define BS_I2C_C2_AD (3U) /*!< Bit field size in bits for I2C_C2_AD. */ - -/*! @brief Read current value of the I2C_C2_AD field. */ -#define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD) - -/*! @brief Format value for bitfield I2C_C2_AD. */ -#define BF_I2C_C2_AD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_AD) & BM_I2C_C2_AD) - -/*! @brief Set the AD field to a new value. */ -#define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v))) -/*@}*/ - -/*! - * @name Register I2C_C2, field RMEN[3] (RW) - * - * This bit controls the slave address matching for addresses between the values - * of the A1 and RA registers. When this bit is set, a slave address matching - * occurs for any address greater than the value of the A1 register and less than - * or equal to the value of the RA register. - * - * Values: - * - 0 - Range mode disabled. No address matching occurs for an address within - * the range of values of the A1 and RA registers. - * - 1 - Range mode enabled. Address matching occurs when a slave receives an - * address within the range of values of the A1 and RA registers. - */ -/*@{*/ -#define BP_I2C_C2_RMEN (3U) /*!< Bit position for I2C_C2_RMEN. */ -#define BM_I2C_C2_RMEN (0x08U) /*!< Bit mask for I2C_C2_RMEN. */ -#define BS_I2C_C2_RMEN (1U) /*!< Bit field size in bits for I2C_C2_RMEN. */ - -/*! @brief Read current value of the I2C_C2_RMEN field. */ -#define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN)) - -/*! @brief Format value for bitfield I2C_C2_RMEN. */ -#define BF_I2C_C2_RMEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_RMEN) & BM_I2C_C2_RMEN) - -/*! @brief Set the RMEN field to a new value. */ -#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field SBRC[4] (RW) - * - * Enables independent slave mode baud rate at maximum frequency, which forces - * clock stretching on SCL in very fast I2C modes. To a slave, an example of a - * "very fast" mode is when the master transfers at 40 kbit/s but the slave can - * capture the master's data at only 10 kbit/s. - * - * Values: - * - 0 - The slave baud rate follows the master baud rate and clock stretching - * may occur - * - 1 - Slave baud rate is independent of the master baud rate - */ -/*@{*/ -#define BP_I2C_C2_SBRC (4U) /*!< Bit position for I2C_C2_SBRC. */ -#define BM_I2C_C2_SBRC (0x10U) /*!< Bit mask for I2C_C2_SBRC. */ -#define BS_I2C_C2_SBRC (1U) /*!< Bit field size in bits for I2C_C2_SBRC. */ - -/*! @brief Read current value of the I2C_C2_SBRC field. */ -#define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC)) - -/*! @brief Format value for bitfield I2C_C2_SBRC. */ -#define BF_I2C_C2_SBRC(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_SBRC) & BM_I2C_C2_SBRC) - -/*! @brief Set the SBRC field to a new value. */ -#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field HDRS[5] (RW) - * - * Controls the drive capability of the I2C pads. - * - * Values: - * - 0 - Normal drive mode - * - 1 - High drive mode - */ -/*@{*/ -#define BP_I2C_C2_HDRS (5U) /*!< Bit position for I2C_C2_HDRS. */ -#define BM_I2C_C2_HDRS (0x20U) /*!< Bit mask for I2C_C2_HDRS. */ -#define BS_I2C_C2_HDRS (1U) /*!< Bit field size in bits for I2C_C2_HDRS. */ - -/*! @brief Read current value of the I2C_C2_HDRS field. */ -#define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS)) - -/*! @brief Format value for bitfield I2C_C2_HDRS. */ -#define BF_I2C_C2_HDRS(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_HDRS) & BM_I2C_C2_HDRS) - -/*! @brief Set the HDRS field to a new value. */ -#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field ADEXT[6] (RW) - * - * Controls the number of bits used for the slave address. - * - * Values: - * - 0 - 7-bit address scheme - * - 1 - 10-bit address scheme - */ -/*@{*/ -#define BP_I2C_C2_ADEXT (6U) /*!< Bit position for I2C_C2_ADEXT. */ -#define BM_I2C_C2_ADEXT (0x40U) /*!< Bit mask for I2C_C2_ADEXT. */ -#define BS_I2C_C2_ADEXT (1U) /*!< Bit field size in bits for I2C_C2_ADEXT. */ - -/*! @brief Read current value of the I2C_C2_ADEXT field. */ -#define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT)) - -/*! @brief Format value for bitfield I2C_C2_ADEXT. */ -#define BF_I2C_C2_ADEXT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_ADEXT) & BM_I2C_C2_ADEXT) - -/*! @brief Set the ADEXT field to a new value. */ -#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field GCAEN[7] (RW) - * - * Enables general call address. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_I2C_C2_GCAEN (7U) /*!< Bit position for I2C_C2_GCAEN. */ -#define BM_I2C_C2_GCAEN (0x80U) /*!< Bit mask for I2C_C2_GCAEN. */ -#define BS_I2C_C2_GCAEN (1U) /*!< Bit field size in bits for I2C_C2_GCAEN. */ - -/*! @brief Read current value of the I2C_C2_GCAEN field. */ -#define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN)) - -/*! @brief Format value for bitfield I2C_C2_GCAEN. */ -#define BF_I2C_C2_GCAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_GCAEN) & BM_I2C_C2_GCAEN) - -/*! @brief Set the GCAEN field to a new value. */ -#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_FLT - I2C Programmable Input Glitch Filter register - ******************************************************************************/ - -/*! - * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_flt -{ - uint8_t U; - struct _hw_i2c_flt_bitfields - { - uint8_t FLT : 4; /*!< [3:0] I2C Programmable Filter Factor */ - uint8_t STARTF : 1; /*!< [4] I2C Bus Start Detect Flag */ - uint8_t SSIE : 1; /*!< [5] I2C Bus Stop or Start Interrupt Enable */ - uint8_t STOPF : 1; /*!< [6] I2C Bus Stop Detect Flag */ - uint8_t SHEN : 1; /*!< [7] Stop Hold Enable */ - } B; -} hw_i2c_flt_t; - -/*! - * @name Constants and macros for entire I2C_FLT register - */ -/*@{*/ -#define HW_I2C_FLT_ADDR(x) ((x) + 0x6U) - -#define HW_I2C_FLT(x) (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x)) -#define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U) -#define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v)) -#define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) | (v))) -#define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v))) -#define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_FLT bitfields - */ - -/*! - * @name Register I2C_FLT, field FLT[3:0] (RW) - * - * Controls the width of the glitch, in terms of I2C module clock cycles, that - * the filter must absorb. For any glitch whose size is less than or equal to this - * width setting, the filter does not allow the glitch to pass. - * - * Values: - * - 0 - No filter/bypass - */ -/*@{*/ -#define BP_I2C_FLT_FLT (0U) /*!< Bit position for I2C_FLT_FLT. */ -#define BM_I2C_FLT_FLT (0x0FU) /*!< Bit mask for I2C_FLT_FLT. */ -#define BS_I2C_FLT_FLT (4U) /*!< Bit field size in bits for I2C_FLT_FLT. */ - -/*! @brief Read current value of the I2C_FLT_FLT field. */ -#define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT) - -/*! @brief Format value for bitfield I2C_FLT_FLT. */ -#define BF_I2C_FLT_FLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_FLT) & BM_I2C_FLT_FLT) - -/*! @brief Set the FLT field to a new value. */ -#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v))) -/*@}*/ - -/*! - * @name Register I2C_FLT, field STARTF[4] (W1C) - * - * Hardware sets this bit when the I2C bus's start status is detected. The - * STARTF bit must be cleared by writing 1 to it. - * - * Values: - * - 0 - No start happens on I2C bus - * - 1 - Start detected on I2C bus - */ -/*@{*/ -#define BP_I2C_FLT_STARTF (4U) /*!< Bit position for I2C_FLT_STARTF. */ -#define BM_I2C_FLT_STARTF (0x10U) /*!< Bit mask for I2C_FLT_STARTF. */ -#define BS_I2C_FLT_STARTF (1U) /*!< Bit field size in bits for I2C_FLT_STARTF. */ - -/*! @brief Read current value of the I2C_FLT_STARTF field. */ -#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF)) - -/*! @brief Format value for bitfield I2C_FLT_STARTF. */ -#define BF_I2C_FLT_STARTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STARTF) & BM_I2C_FLT_STARTF) - -/*! @brief Set the STARTF field to a new value. */ -#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_FLT, field SSIE[5] (RW) - * - * This bit enables the interrupt for I2C bus stop or start detection. To clear - * the I2C bus stop or start detection interrupt: In the interrupt service - * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the - * IICIF bit in the status register. If this sequence is reversed, the IICIF bit - * is asserted again. - * - * Values: - * - 0 - Stop or start detection interrupt is disabled - * - 1 - Stop or start detection interrupt is enabled - */ -/*@{*/ -#define BP_I2C_FLT_SSIE (5U) /*!< Bit position for I2C_FLT_SSIE. */ -#define BM_I2C_FLT_SSIE (0x20U) /*!< Bit mask for I2C_FLT_SSIE. */ -#define BS_I2C_FLT_SSIE (1U) /*!< Bit field size in bits for I2C_FLT_SSIE. */ - -/*! @brief Read current value of the I2C_FLT_SSIE field. */ -#define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE)) - -/*! @brief Format value for bitfield I2C_FLT_SSIE. */ -#define BF_I2C_FLT_SSIE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SSIE) & BM_I2C_FLT_SSIE) - -/*! @brief Set the SSIE field to a new value. */ -#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v)) -/*@}*/ - -/*! - * @name Register I2C_FLT, field STOPF[6] (W1C) - * - * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF - * bit must be cleared by writing 1 to it. - * - * Values: - * - 0 - No stop happens on I2C bus - * - 1 - Stop detected on I2C bus - */ -/*@{*/ -#define BP_I2C_FLT_STOPF (6U) /*!< Bit position for I2C_FLT_STOPF. */ -#define BM_I2C_FLT_STOPF (0x40U) /*!< Bit mask for I2C_FLT_STOPF. */ -#define BS_I2C_FLT_STOPF (1U) /*!< Bit field size in bits for I2C_FLT_STOPF. */ - -/*! @brief Read current value of the I2C_FLT_STOPF field. */ -#define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF)) - -/*! @brief Format value for bitfield I2C_FLT_STOPF. */ -#define BF_I2C_FLT_STOPF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STOPF) & BM_I2C_FLT_STOPF) - -/*! @brief Set the STOPF field to a new value. */ -#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_FLT, field SHEN[7] (RW) - * - * Set this bit to hold off entry to stop mode when any data transmission or - * reception is occurring. The following scenario explains the holdoff - * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set - * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The - * byte currently being transferred, including both address and data, completes - * its transfer. The I2C slave or master acknowledges that the in-transfer byte - * completed its transfer and acknowledges the request to enter stop mode. After - * receiving the I2C module's acknowledgment of the request to enter stop mode, - * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit - * is set to 1 and the I2C module is in an idle or disabled state when the MCU - * signals to enter stop mode, the module immediately acknowledges the request to - * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or - * reception that was suspended by stop mode entry was incomplete: To resume the - * overall transmission or reception after the MCU exits stop mode, software must - * reinitialize the transfer by resending the address of the slave. If the I2C - * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, - * system software will receive the interrupt triggered by the I2C Status Register's - * TCF bit after the MCU wakes from the stop mode. - * - * Values: - * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated. - * - 1 - Stop holdoff is enabled. - */ -/*@{*/ -#define BP_I2C_FLT_SHEN (7U) /*!< Bit position for I2C_FLT_SHEN. */ -#define BM_I2C_FLT_SHEN (0x80U) /*!< Bit mask for I2C_FLT_SHEN. */ -#define BS_I2C_FLT_SHEN (1U) /*!< Bit field size in bits for I2C_FLT_SHEN. */ - -/*! @brief Read current value of the I2C_FLT_SHEN field. */ -#define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN)) - -/*! @brief Format value for bitfield I2C_FLT_SHEN. */ -#define BF_I2C_FLT_SHEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SHEN) & BM_I2C_FLT_SHEN) - -/*! @brief Set the SHEN field to a new value. */ -#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_RA - I2C Range Address register - ******************************************************************************/ - -/*! - * @brief HW_I2C_RA - I2C Range Address register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_ra -{ - uint8_t U; - struct _hw_i2c_ra_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t RAD : 7; /*!< [7:1] Range Slave Address */ - } B; -} hw_i2c_ra_t; - -/*! - * @name Constants and macros for entire I2C_RA register - */ -/*@{*/ -#define HW_I2C_RA_ADDR(x) ((x) + 0x7U) - -#define HW_I2C_RA(x) (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x)) -#define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U) -#define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v)) -#define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) | (v))) -#define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v))) -#define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_RA bitfields - */ - -/*! - * @name Register I2C_RA, field RAD[7:1] (RW) - * - * This field contains the slave address to be used by the I2C module. The field - * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero - * value write enables this register. This register value can be considered as a - * maximum boundary in the range matching mode. - */ -/*@{*/ -#define BP_I2C_RA_RAD (1U) /*!< Bit position for I2C_RA_RAD. */ -#define BM_I2C_RA_RAD (0xFEU) /*!< Bit mask for I2C_RA_RAD. */ -#define BS_I2C_RA_RAD (7U) /*!< Bit field size in bits for I2C_RA_RAD. */ - -/*! @brief Read current value of the I2C_RA_RAD field. */ -#define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD) - -/*! @brief Format value for bitfield I2C_RA_RAD. */ -#define BF_I2C_RA_RAD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_RA_RAD) & BM_I2C_RA_RAD) - -/*! @brief Set the RAD field to a new value. */ -#define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_SMB - I2C SMBus Control and Status register - ******************************************************************************/ - -/*! - * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW) - * - * Reset value: 0x00U - * - * When the SCL and SDA signals are held high for a length of time greater than - * the high timeout period, the SHTF1 flag sets. Before reaching this threshold, - * while the system is detecting how long these signals are being held high, a - * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the - * bus transmission process with the idle bus state. When the TCKSEL bit is set, - * there is no need to monitor the SHTF1 bit because the bus speed is too high to - * match the protocol of SMBus. - */ -typedef union _hw_i2c_smb -{ - uint8_t U; - struct _hw_i2c_smb_bitfields - { - uint8_t SHTF2IE : 1; /*!< [0] SHTF2 Interrupt Enable */ - uint8_t SHTF2 : 1; /*!< [1] SCL High Timeout Flag 2 */ - uint8_t SHTF1 : 1; /*!< [2] SCL High Timeout Flag 1 */ - uint8_t SLTF : 1; /*!< [3] SCL Low Timeout Flag */ - uint8_t TCKSEL : 1; /*!< [4] Timeout Counter Clock Select */ - uint8_t SIICAEN : 1; /*!< [5] Second I2C Address Enable */ - uint8_t ALERTEN : 1; /*!< [6] SMBus Alert Response Address Enable */ - uint8_t FACK : 1; /*!< [7] Fast NACK/ACK Enable */ - } B; -} hw_i2c_smb_t; - -/*! - * @name Constants and macros for entire I2C_SMB register - */ -/*@{*/ -#define HW_I2C_SMB_ADDR(x) ((x) + 0x8U) - -#define HW_I2C_SMB(x) (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x)) -#define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U) -#define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v)) -#define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) | (v))) -#define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v))) -#define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_SMB bitfields - */ - -/*! - * @name Register I2C_SMB, field SHTF2IE[0] (RW) - * - * Enables SCL high and SDA low timeout interrupt. - * - * Values: - * - 0 - SHTF2 interrupt is disabled - * - 1 - SHTF2 interrupt is enabled - */ -/*@{*/ -#define BP_I2C_SMB_SHTF2IE (0U) /*!< Bit position for I2C_SMB_SHTF2IE. */ -#define BM_I2C_SMB_SHTF2IE (0x01U) /*!< Bit mask for I2C_SMB_SHTF2IE. */ -#define BS_I2C_SMB_SHTF2IE (1U) /*!< Bit field size in bits for I2C_SMB_SHTF2IE. */ - -/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */ -#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE)) - -/*! @brief Format value for bitfield I2C_SMB_SHTF2IE. */ -#define BF_I2C_SMB_SHTF2IE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2IE) & BM_I2C_SMB_SHTF2IE) - -/*! @brief Set the SHTF2IE field to a new value. */ -#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SHTF2[1] (W1C) - * - * This bit sets when SCL is held high and SDA is held low more than clock * - * LoValue / 512. Software clears this bit by writing 1 to it. - * - * Values: - * - 0 - No SCL high and SDA low timeout occurs - * - 1 - SCL high and SDA low timeout occurs - */ -/*@{*/ -#define BP_I2C_SMB_SHTF2 (1U) /*!< Bit position for I2C_SMB_SHTF2. */ -#define BM_I2C_SMB_SHTF2 (0x02U) /*!< Bit mask for I2C_SMB_SHTF2. */ -#define BS_I2C_SMB_SHTF2 (1U) /*!< Bit field size in bits for I2C_SMB_SHTF2. */ - -/*! @brief Read current value of the I2C_SMB_SHTF2 field. */ -#define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2)) - -/*! @brief Format value for bitfield I2C_SMB_SHTF2. */ -#define BF_I2C_SMB_SHTF2(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2) & BM_I2C_SMB_SHTF2) - -/*! @brief Set the SHTF2 field to a new value. */ -#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SHTF1[2] (RO) - * - * This read-only bit sets when SCL and SDA are held high more than clock * - * LoValue / 512, which indicates the bus is free. This bit is cleared automatically. - * - * Values: - * - 0 - No SCL high and SDA high timeout occurs - * - 1 - SCL high and SDA high timeout occurs - */ -/*@{*/ -#define BP_I2C_SMB_SHTF1 (2U) /*!< Bit position for I2C_SMB_SHTF1. */ -#define BM_I2C_SMB_SHTF1 (0x04U) /*!< Bit mask for I2C_SMB_SHTF1. */ -#define BS_I2C_SMB_SHTF1 (1U) /*!< Bit field size in bits for I2C_SMB_SHTF1. */ - -/*! @brief Read current value of the I2C_SMB_SHTF1 field. */ -#define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SLTF[3] (W1C) - * - * This bit is set when the SLT register (consisting of the SLTH and SLTL - * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs. - * Software clears this bit by writing a logic 1 to it. The low timeout function - * is disabled when the SLT register's value is 0. - * - * Values: - * - 0 - No low timeout occurs - * - 1 - Low timeout occurs - */ -/*@{*/ -#define BP_I2C_SMB_SLTF (3U) /*!< Bit position for I2C_SMB_SLTF. */ -#define BM_I2C_SMB_SLTF (0x08U) /*!< Bit mask for I2C_SMB_SLTF. */ -#define BS_I2C_SMB_SLTF (1U) /*!< Bit field size in bits for I2C_SMB_SLTF. */ - -/*! @brief Read current value of the I2C_SMB_SLTF field. */ -#define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF)) - -/*! @brief Format value for bitfield I2C_SMB_SLTF. */ -#define BF_I2C_SMB_SLTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SLTF) & BM_I2C_SMB_SLTF) - -/*! @brief Set the SLTF field to a new value. */ -#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field TCKSEL[4] (RW) - * - * Selects the clock source of the timeout counter. - * - * Values: - * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64 - * - 1 - Timeout counter counts at the frequency of the I2C module clock - */ -/*@{*/ -#define BP_I2C_SMB_TCKSEL (4U) /*!< Bit position for I2C_SMB_TCKSEL. */ -#define BM_I2C_SMB_TCKSEL (0x10U) /*!< Bit mask for I2C_SMB_TCKSEL. */ -#define BS_I2C_SMB_TCKSEL (1U) /*!< Bit field size in bits for I2C_SMB_TCKSEL. */ - -/*! @brief Read current value of the I2C_SMB_TCKSEL field. */ -#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL)) - -/*! @brief Format value for bitfield I2C_SMB_TCKSEL. */ -#define BF_I2C_SMB_TCKSEL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_TCKSEL) & BM_I2C_SMB_TCKSEL) - -/*! @brief Set the TCKSEL field to a new value. */ -#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SIICAEN[5] (RW) - * - * Enables or disables SMBus device default address. - * - * Values: - * - 0 - I2C address register 2 matching is disabled - * - 1 - I2C address register 2 matching is enabled - */ -/*@{*/ -#define BP_I2C_SMB_SIICAEN (5U) /*!< Bit position for I2C_SMB_SIICAEN. */ -#define BM_I2C_SMB_SIICAEN (0x20U) /*!< Bit mask for I2C_SMB_SIICAEN. */ -#define BS_I2C_SMB_SIICAEN (1U) /*!< Bit field size in bits for I2C_SMB_SIICAEN. */ - -/*! @brief Read current value of the I2C_SMB_SIICAEN field. */ -#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN)) - -/*! @brief Format value for bitfield I2C_SMB_SIICAEN. */ -#define BF_I2C_SMB_SIICAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SIICAEN) & BM_I2C_SMB_SIICAEN) - -/*! @brief Set the SIICAEN field to a new value. */ -#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field ALERTEN[6] (RW) - * - * Enables or disables SMBus alert response address matching. After the host - * responds to a device that used the alert response address, you must use software - * to put the device's address on the bus. The alert protocol is described in the - * SMBus specification. - * - * Values: - * - 0 - SMBus alert response address matching is disabled - * - 1 - SMBus alert response address matching is enabled - */ -/*@{*/ -#define BP_I2C_SMB_ALERTEN (6U) /*!< Bit position for I2C_SMB_ALERTEN. */ -#define BM_I2C_SMB_ALERTEN (0x40U) /*!< Bit mask for I2C_SMB_ALERTEN. */ -#define BS_I2C_SMB_ALERTEN (1U) /*!< Bit field size in bits for I2C_SMB_ALERTEN. */ - -/*! @brief Read current value of the I2C_SMB_ALERTEN field. */ -#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN)) - -/*! @brief Format value for bitfield I2C_SMB_ALERTEN. */ -#define BF_I2C_SMB_ALERTEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_ALERTEN) & BM_I2C_SMB_ALERTEN) - -/*! @brief Set the ALERTEN field to a new value. */ -#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field FACK[7] (RW) - * - * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK - * according to the result of receiving data byte. - * - * Values: - * - 0 - An ACK or NACK is sent on the following receiving data byte - * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing - * 1 to TXAK after receiving a data byte generates a NACK. - */ -/*@{*/ -#define BP_I2C_SMB_FACK (7U) /*!< Bit position for I2C_SMB_FACK. */ -#define BM_I2C_SMB_FACK (0x80U) /*!< Bit mask for I2C_SMB_FACK. */ -#define BS_I2C_SMB_FACK (1U) /*!< Bit field size in bits for I2C_SMB_FACK. */ - -/*! @brief Read current value of the I2C_SMB_FACK field. */ -#define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK)) - -/*! @brief Format value for bitfield I2C_SMB_FACK. */ -#define BF_I2C_SMB_FACK(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_FACK) & BM_I2C_SMB_FACK) - -/*! @brief Set the FACK field to a new value. */ -#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_A2 - I2C Address Register 2 - ******************************************************************************/ - -/*! - * @brief HW_I2C_A2 - I2C Address Register 2 (RW) - * - * Reset value: 0xC2U - */ -typedef union _hw_i2c_a2 -{ - uint8_t U; - struct _hw_i2c_a2_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t SAD : 7; /*!< [7:1] SMBus Address */ - } B; -} hw_i2c_a2_t; - -/*! - * @name Constants and macros for entire I2C_A2 register - */ -/*@{*/ -#define HW_I2C_A2_ADDR(x) ((x) + 0x9U) - -#define HW_I2C_A2(x) (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x)) -#define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U) -#define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v)) -#define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) | (v))) -#define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v))) -#define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_A2 bitfields - */ - -/*! - * @name Register I2C_A2, field SAD[7:1] (RW) - * - * Contains the slave address used by the SMBus. This field is used on the - * device default address or other related addresses. - */ -/*@{*/ -#define BP_I2C_A2_SAD (1U) /*!< Bit position for I2C_A2_SAD. */ -#define BM_I2C_A2_SAD (0xFEU) /*!< Bit mask for I2C_A2_SAD. */ -#define BS_I2C_A2_SAD (7U) /*!< Bit field size in bits for I2C_A2_SAD. */ - -/*! @brief Read current value of the I2C_A2_SAD field. */ -#define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD) - -/*! @brief Format value for bitfield I2C_A2_SAD. */ -#define BF_I2C_A2_SAD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_A2_SAD) & BM_I2C_A2_SAD) - -/*! @brief Set the SAD field to a new value. */ -#define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_SLTH - I2C SCL Low Timeout Register High - ******************************************************************************/ - -/*! - * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_slth -{ - uint8_t U; - struct _hw_i2c_slth_bitfields - { - uint8_t SSLT : 8; /*!< [7:0] */ - } B; -} hw_i2c_slth_t; - -/*! - * @name Constants and macros for entire I2C_SLTH register - */ -/*@{*/ -#define HW_I2C_SLTH_ADDR(x) ((x) + 0xAU) - -#define HW_I2C_SLTH(x) (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x)) -#define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U) -#define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v)) -#define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) | (v))) -#define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v))) -#define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_SLTH bitfields - */ - -/*! - * @name Register I2C_SLTH, field SSLT[7:0] (RW) - * - * Most significant byte of SCL low timeout value that determines the timeout - * period of SCL low. - */ -/*@{*/ -#define BP_I2C_SLTH_SSLT (0U) /*!< Bit position for I2C_SLTH_SSLT. */ -#define BM_I2C_SLTH_SSLT (0xFFU) /*!< Bit mask for I2C_SLTH_SSLT. */ -#define BS_I2C_SLTH_SSLT (8U) /*!< Bit field size in bits for I2C_SLTH_SSLT. */ - -/*! @brief Read current value of the I2C_SLTH_SSLT field. */ -#define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U) - -/*! @brief Format value for bitfield I2C_SLTH_SSLT. */ -#define BF_I2C_SLTH_SSLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SLTH_SSLT) & BM_I2C_SLTH_SSLT) - -/*! @brief Set the SSLT field to a new value. */ -#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_SLTL - I2C SCL Low Timeout Register Low - ******************************************************************************/ - -/*! - * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_sltl -{ - uint8_t U; - struct _hw_i2c_sltl_bitfields - { - uint8_t SSLT : 8; /*!< [7:0] */ - } B; -} hw_i2c_sltl_t; - -/*! - * @name Constants and macros for entire I2C_SLTL register - */ -/*@{*/ -#define HW_I2C_SLTL_ADDR(x) ((x) + 0xBU) - -#define HW_I2C_SLTL(x) (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x)) -#define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U) -#define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v)) -#define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) | (v))) -#define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v))) -#define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_SLTL bitfields - */ - -/*! - * @name Register I2C_SLTL, field SSLT[7:0] (RW) - * - * Least significant byte of SCL low timeout value that determines the timeout - * period of SCL low. - */ -/*@{*/ -#define BP_I2C_SLTL_SSLT (0U) /*!< Bit position for I2C_SLTL_SSLT. */ -#define BM_I2C_SLTL_SSLT (0xFFU) /*!< Bit mask for I2C_SLTL_SSLT. */ -#define BS_I2C_SLTL_SSLT (8U) /*!< Bit field size in bits for I2C_SLTL_SSLT. */ - -/*! @brief Read current value of the I2C_SLTL_SSLT field. */ -#define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U) - -/*! @brief Format value for bitfield I2C_SLTL_SSLT. */ -#define BF_I2C_SLTL_SSLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SLTL_SSLT) & BM_I2C_SLTL_SSLT) - -/*! @brief Set the SSLT field to a new value. */ -#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_i2c_t - module struct - ******************************************************************************/ -/*! - * @brief All I2C module registers. - */ -#pragma pack(1) -typedef struct _hw_i2c -{ - __IO hw_i2c_a1_t A1; /*!< [0x0] I2C Address Register 1 */ - __IO hw_i2c_f_t F; /*!< [0x1] I2C Frequency Divider register */ - __IO hw_i2c_c1_t C1; /*!< [0x2] I2C Control Register 1 */ - __IO hw_i2c_s_t S; /*!< [0x3] I2C Status register */ - __IO hw_i2c_d_t D; /*!< [0x4] I2C Data I/O register */ - __IO hw_i2c_c2_t C2; /*!< [0x5] I2C Control Register 2 */ - __IO hw_i2c_flt_t FLT; /*!< [0x6] I2C Programmable Input Glitch Filter register */ - __IO hw_i2c_ra_t RA; /*!< [0x7] I2C Range Address register */ - __IO hw_i2c_smb_t SMB; /*!< [0x8] I2C SMBus Control and Status register */ - __IO hw_i2c_a2_t A2; /*!< [0x9] I2C Address Register 2 */ - __IO hw_i2c_slth_t SLTH; /*!< [0xA] I2C SCL Low Timeout Register High */ - __IO hw_i2c_sltl_t SLTL; /*!< [0xB] I2C SCL Low Timeout Register Low */ -} hw_i2c_t; -#pragma pack() - -/*! @brief Macro to access all I2C registers. */ -/*! @param x I2C module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_I2C(I2C0_BASE). */ -#define HW_I2C(x) (*(hw_i2c_t *)(x)) - -#endif /* __HW_I2C_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h deleted file mode 100644 index a8ae4de2616..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h +++ /dev/null @@ -1,3270 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_I2S_REGISTERS_H__ -#define __HW_I2S_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 I2S - * - * Inter-IC Sound / Synchronous Audio Interface - * - * Registers defined in this header file: - * - HW_I2S_TCSR - SAI Transmit Control Register - * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register - * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register - * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register - * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register - * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register - * - HW_I2S_TDRn - SAI Transmit Data Register - * - HW_I2S_TFRn - SAI Transmit FIFO Register - * - HW_I2S_TMR - SAI Transmit Mask Register - * - HW_I2S_RCSR - SAI Receive Control Register - * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register - * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register - * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register - * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register - * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register - * - HW_I2S_RDRn - SAI Receive Data Register - * - HW_I2S_RFRn - SAI Receive FIFO Register - * - HW_I2S_RMR - SAI Receive Mask Register - * - HW_I2S_MCR - SAI MCLK Control Register - * - HW_I2S_MDR - SAI MCLK Divide Register - * - * - hw_i2s_t - Struct containing all module registers. - */ - -#define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */ - -/******************************************************************************* - * HW_I2S_TCSR - SAI Transmit Control Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tcsr -{ - uint32_t U; - struct _hw_i2s_tcsr_bitfields - { - uint32_t FRDE : 1; /*!< [0] FIFO Request DMA Enable */ - uint32_t FWDE : 1; /*!< [1] FIFO Warning DMA Enable */ - uint32_t RESERVED0 : 6; /*!< [7:2] */ - uint32_t FRIE : 1; /*!< [8] FIFO Request Interrupt Enable */ - uint32_t FWIE : 1; /*!< [9] FIFO Warning Interrupt Enable */ - uint32_t FEIE : 1; /*!< [10] FIFO Error Interrupt Enable */ - uint32_t SEIE : 1; /*!< [11] Sync Error Interrupt Enable */ - uint32_t WSIE : 1; /*!< [12] Word Start Interrupt Enable */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t FRF : 1; /*!< [16] FIFO Request Flag */ - uint32_t FWF : 1; /*!< [17] FIFO Warning Flag */ - uint32_t FEF : 1; /*!< [18] FIFO Error Flag */ - uint32_t SEF : 1; /*!< [19] Sync Error Flag */ - uint32_t WSF : 1; /*!< [20] Word Start Flag */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t SR : 1; /*!< [24] Software Reset */ - uint32_t FR : 1; /*!< [25] FIFO Reset */ - uint32_t RESERVED3 : 2; /*!< [27:26] */ - uint32_t BCE : 1; /*!< [28] Bit Clock Enable */ - uint32_t DBGE : 1; /*!< [29] Debug Enable */ - uint32_t STOPE : 1; /*!< [30] Stop Enable */ - uint32_t TE : 1; /*!< [31] Transmitter Enable */ - } B; -} hw_i2s_tcsr_t; - -/*! - * @name Constants and macros for entire I2S_TCSR register - */ -/*@{*/ -#define HW_I2S_TCSR_ADDR(x) ((x) + 0x0U) - -#define HW_I2S_TCSR(x) (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x)) -#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U) -#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v)) -#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) | (v))) -#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v))) -#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCSR bitfields - */ - -/*! - * @name Register I2S_TCSR, field FRDE[0] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_TCSR_FRDE (0U) /*!< Bit position for I2S_TCSR_FRDE. */ -#define BM_I2S_TCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */ -#define BS_I2S_TCSR_FRDE (1U) /*!< Bit field size in bits for I2S_TCSR_FRDE. */ - -/*! @brief Read current value of the I2S_TCSR_FRDE field. */ -#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE)) - -/*! @brief Format value for bitfield I2S_TCSR_FRDE. */ -#define BF_I2S_TCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE) - -/*! @brief Set the FRDE field to a new value. */ -#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FWDE[1] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_TCSR_FWDE (1U) /*!< Bit position for I2S_TCSR_FWDE. */ -#define BM_I2S_TCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */ -#define BS_I2S_TCSR_FWDE (1U) /*!< Bit field size in bits for I2S_TCSR_FWDE. */ - -/*! @brief Read current value of the I2S_TCSR_FWDE field. */ -#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE)) - -/*! @brief Format value for bitfield I2S_TCSR_FWDE. */ -#define BF_I2S_TCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE) - -/*! @brief Set the FWDE field to a new value. */ -#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FRIE[8] (RW) - * - * Enables/disables FIFO request interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_FRIE (8U) /*!< Bit position for I2S_TCSR_FRIE. */ -#define BM_I2S_TCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */ -#define BS_I2S_TCSR_FRIE (1U) /*!< Bit field size in bits for I2S_TCSR_FRIE. */ - -/*! @brief Read current value of the I2S_TCSR_FRIE field. */ -#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE)) - -/*! @brief Format value for bitfield I2S_TCSR_FRIE. */ -#define BF_I2S_TCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE) - -/*! @brief Set the FRIE field to a new value. */ -#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FWIE[9] (RW) - * - * Enables/disables FIFO warning interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_FWIE (9U) /*!< Bit position for I2S_TCSR_FWIE. */ -#define BM_I2S_TCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */ -#define BS_I2S_TCSR_FWIE (1U) /*!< Bit field size in bits for I2S_TCSR_FWIE. */ - -/*! @brief Read current value of the I2S_TCSR_FWIE field. */ -#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE)) - -/*! @brief Format value for bitfield I2S_TCSR_FWIE. */ -#define BF_I2S_TCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE) - -/*! @brief Set the FWIE field to a new value. */ -#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FEIE[10] (RW) - * - * Enables/disables FIFO error interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_FEIE (10U) /*!< Bit position for I2S_TCSR_FEIE. */ -#define BM_I2S_TCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */ -#define BS_I2S_TCSR_FEIE (1U) /*!< Bit field size in bits for I2S_TCSR_FEIE. */ - -/*! @brief Read current value of the I2S_TCSR_FEIE field. */ -#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE)) - -/*! @brief Format value for bitfield I2S_TCSR_FEIE. */ -#define BF_I2S_TCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field SEIE[11] (RW) - * - * Enables/disables sync error interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_SEIE (11U) /*!< Bit position for I2S_TCSR_SEIE. */ -#define BM_I2S_TCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */ -#define BS_I2S_TCSR_SEIE (1U) /*!< Bit field size in bits for I2S_TCSR_SEIE. */ - -/*! @brief Read current value of the I2S_TCSR_SEIE field. */ -#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE)) - -/*! @brief Format value for bitfield I2S_TCSR_SEIE. */ -#define BF_I2S_TCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE) - -/*! @brief Set the SEIE field to a new value. */ -#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field WSIE[12] (RW) - * - * Enables/disables word start interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_WSIE (12U) /*!< Bit position for I2S_TCSR_WSIE. */ -#define BM_I2S_TCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */ -#define BS_I2S_TCSR_WSIE (1U) /*!< Bit field size in bits for I2S_TCSR_WSIE. */ - -/*! @brief Read current value of the I2S_TCSR_WSIE field. */ -#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE)) - -/*! @brief Format value for bitfield I2S_TCSR_WSIE. */ -#define BF_I2S_TCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE) - -/*! @brief Set the WSIE field to a new value. */ -#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FRF[16] (RO) - * - * Indicates that the number of words in an enabled transmit channel FIFO is - * less than or equal to the transmit FIFO watermark. - * - * Values: - * - 0 - Transmit FIFO watermark has not been reached. - * - 1 - Transmit FIFO watermark has been reached. - */ -/*@{*/ -#define BP_I2S_TCSR_FRF (16U) /*!< Bit position for I2S_TCSR_FRF. */ -#define BM_I2S_TCSR_FRF (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */ -#define BS_I2S_TCSR_FRF (1U) /*!< Bit field size in bits for I2S_TCSR_FRF. */ - -/*! @brief Read current value of the I2S_TCSR_FRF field. */ -#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FWF[17] (RO) - * - * Indicates that an enabled transmit FIFO is empty. - * - * Values: - * - 0 - No enabled transmit FIFO is empty. - * - 1 - Enabled transmit FIFO is empty. - */ -/*@{*/ -#define BP_I2S_TCSR_FWF (17U) /*!< Bit position for I2S_TCSR_FWF. */ -#define BM_I2S_TCSR_FWF (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */ -#define BS_I2S_TCSR_FWF (1U) /*!< Bit field size in bits for I2S_TCSR_FWF. */ - -/*! @brief Read current value of the I2S_TCSR_FWF field. */ -#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FEF[18] (W1C) - * - * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this - * field to clear this flag. - * - * Values: - * - 0 - Transmit underrun not detected. - * - 1 - Transmit underrun detected. - */ -/*@{*/ -#define BP_I2S_TCSR_FEF (18U) /*!< Bit position for I2S_TCSR_FEF. */ -#define BM_I2S_TCSR_FEF (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */ -#define BS_I2S_TCSR_FEF (1U) /*!< Bit field size in bits for I2S_TCSR_FEF. */ - -/*! @brief Read current value of the I2S_TCSR_FEF field. */ -#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF)) - -/*! @brief Format value for bitfield I2S_TCSR_FEF. */ -#define BF_I2S_TCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF) - -/*! @brief Set the FEF field to a new value. */ -#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field SEF[19] (W1C) - * - * Indicates that an error in the externally-generated frame sync has been - * detected. Write a logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Sync error not detected. - * - 1 - Frame sync error detected. - */ -/*@{*/ -#define BP_I2S_TCSR_SEF (19U) /*!< Bit position for I2S_TCSR_SEF. */ -#define BM_I2S_TCSR_SEF (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */ -#define BS_I2S_TCSR_SEF (1U) /*!< Bit field size in bits for I2S_TCSR_SEF. */ - -/*! @brief Read current value of the I2S_TCSR_SEF field. */ -#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF)) - -/*! @brief Format value for bitfield I2S_TCSR_SEF. */ -#define BF_I2S_TCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF) - -/*! @brief Set the SEF field to a new value. */ -#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field WSF[20] (W1C) - * - * Indicates that the start of the configured word has been detected. Write a - * logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Start of word not detected. - * - 1 - Start of word detected. - */ -/*@{*/ -#define BP_I2S_TCSR_WSF (20U) /*!< Bit position for I2S_TCSR_WSF. */ -#define BM_I2S_TCSR_WSF (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */ -#define BS_I2S_TCSR_WSF (1U) /*!< Bit field size in bits for I2S_TCSR_WSF. */ - -/*! @brief Read current value of the I2S_TCSR_WSF field. */ -#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF)) - -/*! @brief Format value for bitfield I2S_TCSR_WSF. */ -#define BF_I2S_TCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF) - -/*! @brief Set the WSF field to a new value. */ -#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field SR[24] (RW) - * - * When set, resets the internal transmitter logic including the FIFO pointers. - * Software-visible registers are not affected, except for the status registers. - * - * Values: - * - 0 - No effect. - * - 1 - Software reset. - */ -/*@{*/ -#define BP_I2S_TCSR_SR (24U) /*!< Bit position for I2S_TCSR_SR. */ -#define BM_I2S_TCSR_SR (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */ -#define BS_I2S_TCSR_SR (1U) /*!< Bit field size in bits for I2S_TCSR_SR. */ - -/*! @brief Read current value of the I2S_TCSR_SR field. */ -#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR)) - -/*! @brief Format value for bitfield I2S_TCSR_SR. */ -#define BF_I2S_TCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR) - -/*! @brief Set the SR field to a new value. */ -#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FR[25] (WORZ) - * - * Resets the FIFO pointers. Reading this field will always return zero. FIFO - * pointers should only be reset when the transmitter is disabled or the FIFO error - * flag is set. - * - * Values: - * - 0 - No effect. - * - 1 - FIFO reset. - */ -/*@{*/ -#define BP_I2S_TCSR_FR (25U) /*!< Bit position for I2S_TCSR_FR. */ -#define BM_I2S_TCSR_FR (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */ -#define BS_I2S_TCSR_FR (1U) /*!< Bit field size in bits for I2S_TCSR_FR. */ - -/*! @brief Format value for bitfield I2S_TCSR_FR. */ -#define BF_I2S_TCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR) - -/*! @brief Set the FR field to a new value. */ -#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field BCE[28] (RW) - * - * Enables the transmit bit clock, separately from the TE. This field is - * automatically set whenever TE is set. When software clears this field, the transmit - * bit clock remains enabled, and this bit remains set, until the end of the - * current frame. - * - * Values: - * - 0 - Transmit bit clock is disabled. - * - 1 - Transmit bit clock is enabled. - */ -/*@{*/ -#define BP_I2S_TCSR_BCE (28U) /*!< Bit position for I2S_TCSR_BCE. */ -#define BM_I2S_TCSR_BCE (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */ -#define BS_I2S_TCSR_BCE (1U) /*!< Bit field size in bits for I2S_TCSR_BCE. */ - -/*! @brief Read current value of the I2S_TCSR_BCE field. */ -#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE)) - -/*! @brief Format value for bitfield I2S_TCSR_BCE. */ -#define BF_I2S_TCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE) - -/*! @brief Set the BCE field to a new value. */ -#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field DBGE[29] (RW) - * - * Enables/disables transmitter operation in Debug mode. The transmit bit clock - * is not affected by debug mode. - * - * Values: - * - 0 - Transmitter is disabled in Debug mode, after completing the current - * frame. - * - 1 - Transmitter is enabled in Debug mode. - */ -/*@{*/ -#define BP_I2S_TCSR_DBGE (29U) /*!< Bit position for I2S_TCSR_DBGE. */ -#define BM_I2S_TCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */ -#define BS_I2S_TCSR_DBGE (1U) /*!< Bit field size in bits for I2S_TCSR_DBGE. */ - -/*! @brief Read current value of the I2S_TCSR_DBGE field. */ -#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE)) - -/*! @brief Format value for bitfield I2S_TCSR_DBGE. */ -#define BF_I2S_TCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE) - -/*! @brief Set the DBGE field to a new value. */ -#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field STOPE[30] (RW) - * - * Configures transmitter operation in Stop mode. This field is ignored and the - * transmitter is disabled in all low-leakage stop modes. - * - * Values: - * - 0 - Transmitter disabled in Stop mode. - * - 1 - Transmitter enabled in Stop mode. - */ -/*@{*/ -#define BP_I2S_TCSR_STOPE (30U) /*!< Bit position for I2S_TCSR_STOPE. */ -#define BM_I2S_TCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */ -#define BS_I2S_TCSR_STOPE (1U) /*!< Bit field size in bits for I2S_TCSR_STOPE. */ - -/*! @brief Read current value of the I2S_TCSR_STOPE field. */ -#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE)) - -/*! @brief Format value for bitfield I2S_TCSR_STOPE. */ -#define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE) - -/*! @brief Set the STOPE field to a new value. */ -#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field TE[31] (RW) - * - * Enables/disables the transmitter. When software clears this field, the - * transmitter remains enabled, and this bit remains set, until the end of the current - * frame. - * - * Values: - * - 0 - Transmitter is disabled. - * - 1 - Transmitter is enabled, or transmitter has been disabled and has not - * yet reached end of frame. - */ -/*@{*/ -#define BP_I2S_TCSR_TE (31U) /*!< Bit position for I2S_TCSR_TE. */ -#define BM_I2S_TCSR_TE (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */ -#define BS_I2S_TCSR_TE (1U) /*!< Bit field size in bits for I2S_TCSR_TE. */ - -/*! @brief Read current value of the I2S_TCSR_TE field. */ -#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE)) - -/*! @brief Format value for bitfield I2S_TCSR_TE. */ -#define BF_I2S_TCSR_TE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE) - -/*! @brief Set the TE field to a new value. */ -#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tcr1 -{ - uint32_t U; - struct _hw_i2s_tcr1_bitfields - { - uint32_t TFW : 3; /*!< [2:0] Transmit FIFO Watermark */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_i2s_tcr1_t; - -/*! - * @name Constants and macros for entire I2S_TCR1 register - */ -/*@{*/ -#define HW_I2S_TCR1_ADDR(x) ((x) + 0x4U) - -#define HW_I2S_TCR1(x) (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x)) -#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U) -#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v)) -#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) | (v))) -#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v))) -#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR1 bitfields - */ - -/*! - * @name Register I2S_TCR1, field TFW[2:0] (RW) - * - * Configures the watermark level for all enabled transmit channels. - */ -/*@{*/ -#define BP_I2S_TCR1_TFW (0U) /*!< Bit position for I2S_TCR1_TFW. */ -#define BM_I2S_TCR1_TFW (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */ -#define BS_I2S_TCR1_TFW (3U) /*!< Bit field size in bits for I2S_TCR1_TFW. */ - -/*! @brief Read current value of the I2S_TCR1_TFW field. */ -#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW) - -/*! @brief Format value for bitfield I2S_TCR1_TFW. */ -#define BF_I2S_TCR1_TFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW) - -/*! @brief Set the TFW field to a new value. */ -#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr2 -{ - uint32_t U; - struct _hw_i2s_tcr2_bitfields - { - uint32_t DIV : 8; /*!< [7:0] Bit Clock Divide */ - uint32_t RESERVED0 : 16; /*!< [23:8] */ - uint32_t BCD : 1; /*!< [24] Bit Clock Direction */ - uint32_t BCP : 1; /*!< [25] Bit Clock Polarity */ - uint32_t MSEL : 2; /*!< [27:26] MCLK Select */ - uint32_t BCI : 1; /*!< [28] Bit Clock Input */ - uint32_t BCS : 1; /*!< [29] Bit Clock Swap */ - uint32_t SYNC : 2; /*!< [31:30] Synchronous Mode */ - } B; -} hw_i2s_tcr2_t; - -/*! - * @name Constants and macros for entire I2S_TCR2 register - */ -/*@{*/ -#define HW_I2S_TCR2_ADDR(x) ((x) + 0x8U) - -#define HW_I2S_TCR2(x) (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x)) -#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U) -#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v)) -#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) | (v))) -#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v))) -#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR2 bitfields - */ - -/*! - * @name Register I2S_TCR2, field DIV[7:0] (RW) - * - * Divides down the audio master clock to generate the bit clock when configured - * for an internal bit clock. The division value is (DIV + 1) * 2. - */ -/*@{*/ -#define BP_I2S_TCR2_DIV (0U) /*!< Bit position for I2S_TCR2_DIV. */ -#define BM_I2S_TCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */ -#define BS_I2S_TCR2_DIV (8U) /*!< Bit field size in bits for I2S_TCR2_DIV. */ - -/*! @brief Read current value of the I2S_TCR2_DIV field. */ -#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV) - -/*! @brief Format value for bitfield I2S_TCR2_DIV. */ -#define BF_I2S_TCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV) - -/*! @brief Set the DIV field to a new value. */ -#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCD[24] (RW) - * - * Configures the direction of the bit clock. - * - * Values: - * - 0 - Bit clock is generated externally in Slave mode. - * - 1 - Bit clock is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_TCR2_BCD (24U) /*!< Bit position for I2S_TCR2_BCD. */ -#define BM_I2S_TCR2_BCD (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */ -#define BS_I2S_TCR2_BCD (1U) /*!< Bit field size in bits for I2S_TCR2_BCD. */ - -/*! @brief Read current value of the I2S_TCR2_BCD field. */ -#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD)) - -/*! @brief Format value for bitfield I2S_TCR2_BCD. */ -#define BF_I2S_TCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD) - -/*! @brief Set the BCD field to a new value. */ -#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCP[25] (RW) - * - * Configures the polarity of the bit clock. - * - * Values: - * - 0 - Bit clock is active high with drive outputs on rising edge and sample - * inputs on falling edge. - * - 1 - Bit clock is active low with drive outputs on falling edge and sample - * inputs on rising edge. - */ -/*@{*/ -#define BP_I2S_TCR2_BCP (25U) /*!< Bit position for I2S_TCR2_BCP. */ -#define BM_I2S_TCR2_BCP (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */ -#define BS_I2S_TCR2_BCP (1U) /*!< Bit field size in bits for I2S_TCR2_BCP. */ - -/*! @brief Read current value of the I2S_TCR2_BCP field. */ -#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP)) - -/*! @brief Format value for bitfield I2S_TCR2_BCP. */ -#define BF_I2S_TCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP) - -/*! @brief Set the BCP field to a new value. */ -#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field MSEL[27:26] (RW) - * - * Selects the audio Master Clock option used to generate an internally - * generated bit clock. This field has no effect when configured for an externally - * generated bit clock. Depending on the device, some Master Clock options might not be - * available. See the chip configuration details for the availability and - * chip-specific meaning of each option. - * - * Values: - * - 00 - Bus Clock selected. - * - 01 - Master Clock (MCLK) 1 option selected. - * - 10 - Master Clock (MCLK) 2 option selected. - * - 11 - Master Clock (MCLK) 3 option selected. - */ -/*@{*/ -#define BP_I2S_TCR2_MSEL (26U) /*!< Bit position for I2S_TCR2_MSEL. */ -#define BM_I2S_TCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */ -#define BS_I2S_TCR2_MSEL (2U) /*!< Bit field size in bits for I2S_TCR2_MSEL. */ - -/*! @brief Read current value of the I2S_TCR2_MSEL field. */ -#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL) - -/*! @brief Format value for bitfield I2S_TCR2_MSEL. */ -#define BF_I2S_TCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL) - -/*! @brief Set the MSEL field to a new value. */ -#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCI[28] (RW) - * - * When this field is set and using an internally generated bit clock in either - * synchronous or asynchronous mode, the bit clock actually used by the - * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad - * input as if the clock was externally generated). This has the effect of - * decreasing the data input setup time, but increasing the data output valid time. The - * slave mode timing from the datasheet should be used for the transmitter when - * this bit is set. In synchronous mode, this bit allows the transmitter to use - * the slave mode timing from the datasheet, while the receiver uses the master - * mode timing. This field has no effect when configured for an externally generated - * bit clock . - * - * Values: - * - 0 - No effect. - * - 1 - Internal logic is clocked as if bit clock was externally generated. - */ -/*@{*/ -#define BP_I2S_TCR2_BCI (28U) /*!< Bit position for I2S_TCR2_BCI. */ -#define BM_I2S_TCR2_BCI (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */ -#define BS_I2S_TCR2_BCI (1U) /*!< Bit field size in bits for I2S_TCR2_BCI. */ - -/*! @brief Read current value of the I2S_TCR2_BCI field. */ -#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI)) - -/*! @brief Format value for bitfield I2S_TCR2_BCI. */ -#define BF_I2S_TCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI) - -/*! @brief Set the BCI field to a new value. */ -#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCS[29] (RW) - * - * This field swaps the bit clock used by the transmitter. When the transmitter - * is configured in asynchronous mode and this bit is set, the transmitter is - * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and - * receiver to share the same bit clock, but the transmitter continues to use the - * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in - * synchronous mode, the transmitter BCS field and receiver BCS field must be set to - * the same value. When both are set, the transmitter and receiver are both - * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync - * (SAI_RX_SYNC). - * - * Values: - * - 0 - Use the normal bit clock source. - * - 1 - Swap the bit clock source. - */ -/*@{*/ -#define BP_I2S_TCR2_BCS (29U) /*!< Bit position for I2S_TCR2_BCS. */ -#define BM_I2S_TCR2_BCS (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */ -#define BS_I2S_TCR2_BCS (1U) /*!< Bit field size in bits for I2S_TCR2_BCS. */ - -/*! @brief Read current value of the I2S_TCR2_BCS field. */ -#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS)) - -/*! @brief Format value for bitfield I2S_TCR2_BCS. */ -#define BF_I2S_TCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS) - -/*! @brief Set the BCS field to a new value. */ -#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field SYNC[31:30] (RW) - * - * Configures between asynchronous and synchronous modes of operation. When - * configured for a synchronous mode of operation, the receiver must be configured - * for asynchronous operation. - * - * Values: - * - 00 - Asynchronous mode. - * - 01 - Synchronous with receiver. - * - 10 - Synchronous with another SAI transmitter. - * - 11 - Synchronous with another SAI receiver. - */ -/*@{*/ -#define BP_I2S_TCR2_SYNC (30U) /*!< Bit position for I2S_TCR2_SYNC. */ -#define BM_I2S_TCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */ -#define BS_I2S_TCR2_SYNC (2U) /*!< Bit field size in bits for I2S_TCR2_SYNC. */ - -/*! @brief Read current value of the I2S_TCR2_SYNC field. */ -#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC) - -/*! @brief Format value for bitfield I2S_TCR2_SYNC. */ -#define BF_I2S_TCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC) - -/*! @brief Set the SYNC field to a new value. */ -#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tcr3 -{ - uint32_t U; - struct _hw_i2s_tcr3_bitfields - { - uint32_t WDFL : 4; /*!< [3:0] Word Flag Configuration */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t TCE : 1; /*!< [16] Transmit Channel Enable */ - uint32_t RESERVED1 : 15; /*!< [31:17] */ - } B; -} hw_i2s_tcr3_t; - -/*! - * @name Constants and macros for entire I2S_TCR3 register - */ -/*@{*/ -#define HW_I2S_TCR3_ADDR(x) ((x) + 0xCU) - -#define HW_I2S_TCR3(x) (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x)) -#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U) -#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v)) -#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) | (v))) -#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v))) -#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR3 bitfields - */ - -/*! - * @name Register I2S_TCR3, field WDFL[3:0] (RW) - * - * Configures which word sets the start of word flag. The value written must be - * one less than the word number. For example, writing 0 configures the first - * word in the frame. When configured to a value greater than TCR4[FRSZ], then the - * start of word flag is never set. - */ -/*@{*/ -#define BP_I2S_TCR3_WDFL (0U) /*!< Bit position for I2S_TCR3_WDFL. */ -#define BM_I2S_TCR3_WDFL (0x0000000FU) /*!< Bit mask for I2S_TCR3_WDFL. */ -#define BS_I2S_TCR3_WDFL (4U) /*!< Bit field size in bits for I2S_TCR3_WDFL. */ - -/*! @brief Read current value of the I2S_TCR3_WDFL field. */ -#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL) - -/*! @brief Format value for bitfield I2S_TCR3_WDFL. */ -#define BF_I2S_TCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL) - -/*! @brief Set the WDFL field to a new value. */ -#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR3, field TCE[16] (RW) - * - * Enables the corresponding data channel for transmit operation. A channel must - * be enabled before its FIFO is accessed. Changing this field will take effect - * immediately for generating the FIFO request and warning flags, but at the end - * of each frame for transmit operation. - * - * Values: - * - 0 - Transmit data channel N is disabled. - * - 1 - Transmit data channel N is enabled. - */ -/*@{*/ -#define BP_I2S_TCR3_TCE (16U) /*!< Bit position for I2S_TCR3_TCE. */ -#define BM_I2S_TCR3_TCE (0x00010000U) /*!< Bit mask for I2S_TCR3_TCE. */ -#define BS_I2S_TCR3_TCE (1U) /*!< Bit field size in bits for I2S_TCR3_TCE. */ - -/*! @brief Read current value of the I2S_TCR3_TCE field. */ -#define BR_I2S_TCR3_TCE(x) (BITBAND_ACCESS32(HW_I2S_TCR3_ADDR(x), BP_I2S_TCR3_TCE)) - -/*! @brief Format value for bitfield I2S_TCR3_TCE. */ -#define BF_I2S_TCR3_TCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE) - -/*! @brief Set the TCE field to a new value. */ -#define BW_I2S_TCR3_TCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR3_ADDR(x), BP_I2S_TCR3_TCE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr4 -{ - uint32_t U; - struct _hw_i2s_tcr4_bitfields - { - uint32_t FSD : 1; /*!< [0] Frame Sync Direction */ - uint32_t FSP : 1; /*!< [1] Frame Sync Polarity */ - uint32_t ONDEM : 1; /*!< [2] On Demand Mode */ - uint32_t FSE : 1; /*!< [3] Frame Sync Early */ - uint32_t MF : 1; /*!< [4] MSB First */ - uint32_t RESERVED0 : 3; /*!< [7:5] */ - uint32_t SYWD : 5; /*!< [12:8] Sync Width */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t FRSZ : 4; /*!< [19:16] Frame size */ - uint32_t RESERVED2 : 4; /*!< [23:20] */ - uint32_t FPACK : 2; /*!< [25:24] FIFO Packing Mode */ - uint32_t RESERVED3 : 2; /*!< [27:26] */ - uint32_t FCONT : 1; /*!< [28] FIFO Continue on Error */ - uint32_t RESERVED4 : 3; /*!< [31:29] */ - } B; -} hw_i2s_tcr4_t; - -/*! - * @name Constants and macros for entire I2S_TCR4 register - */ -/*@{*/ -#define HW_I2S_TCR4_ADDR(x) ((x) + 0x10U) - -#define HW_I2S_TCR4(x) (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x)) -#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U) -#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v)) -#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) | (v))) -#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v))) -#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR4 bitfields - */ - -/*! - * @name Register I2S_TCR4, field FSD[0] (RW) - * - * Configures the direction of the frame sync. - * - * Values: - * - 0 - Frame sync is generated externally in Slave mode. - * - 1 - Frame sync is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_TCR4_FSD (0U) /*!< Bit position for I2S_TCR4_FSD. */ -#define BM_I2S_TCR4_FSD (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */ -#define BS_I2S_TCR4_FSD (1U) /*!< Bit field size in bits for I2S_TCR4_FSD. */ - -/*! @brief Read current value of the I2S_TCR4_FSD field. */ -#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD)) - -/*! @brief Format value for bitfield I2S_TCR4_FSD. */ -#define BF_I2S_TCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD) - -/*! @brief Set the FSD field to a new value. */ -#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FSP[1] (RW) - * - * Configures the polarity of the frame sync. - * - * Values: - * - 0 - Frame sync is active high. - * - 1 - Frame sync is active low. - */ -/*@{*/ -#define BP_I2S_TCR4_FSP (1U) /*!< Bit position for I2S_TCR4_FSP. */ -#define BM_I2S_TCR4_FSP (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */ -#define BS_I2S_TCR4_FSP (1U) /*!< Bit field size in bits for I2S_TCR4_FSP. */ - -/*! @brief Read current value of the I2S_TCR4_FSP field. */ -#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP)) - -/*! @brief Format value for bitfield I2S_TCR4_FSP. */ -#define BF_I2S_TCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP) - -/*! @brief Set the FSP field to a new value. */ -#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field ONDEM[2] (RW) - * - * When set, and the frame sync is generated internally, a frame sync is only - * generated when the FIFO warning flag is clear. - * - * Values: - * - 0 - Internal frame sync is generated continuously. - * - 1 - Internal frame sync is generated when the FIFO warning flag is clear. - */ -/*@{*/ -#define BP_I2S_TCR4_ONDEM (2U) /*!< Bit position for I2S_TCR4_ONDEM. */ -#define BM_I2S_TCR4_ONDEM (0x00000004U) /*!< Bit mask for I2S_TCR4_ONDEM. */ -#define BS_I2S_TCR4_ONDEM (1U) /*!< Bit field size in bits for I2S_TCR4_ONDEM. */ - -/*! @brief Read current value of the I2S_TCR4_ONDEM field. */ -#define BR_I2S_TCR4_ONDEM(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_ONDEM)) - -/*! @brief Format value for bitfield I2S_TCR4_ONDEM. */ -#define BF_I2S_TCR4_ONDEM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_ONDEM) & BM_I2S_TCR4_ONDEM) - -/*! @brief Set the ONDEM field to a new value. */ -#define BW_I2S_TCR4_ONDEM(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_ONDEM) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FSE[3] (RW) - * - * Values: - * - 0 - Frame sync asserts with the first bit of the frame. - * - 1 - Frame sync asserts one bit before the first bit of the frame. - */ -/*@{*/ -#define BP_I2S_TCR4_FSE (3U) /*!< Bit position for I2S_TCR4_FSE. */ -#define BM_I2S_TCR4_FSE (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */ -#define BS_I2S_TCR4_FSE (1U) /*!< Bit field size in bits for I2S_TCR4_FSE. */ - -/*! @brief Read current value of the I2S_TCR4_FSE field. */ -#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE)) - -/*! @brief Format value for bitfield I2S_TCR4_FSE. */ -#define BF_I2S_TCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE) - -/*! @brief Set the FSE field to a new value. */ -#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field MF[4] (RW) - * - * Configures whether the LSB or the MSB is transmitted first. - * - * Values: - * - 0 - LSB is transmitted first. - * - 1 - MSB is transmitted first. - */ -/*@{*/ -#define BP_I2S_TCR4_MF (4U) /*!< Bit position for I2S_TCR4_MF. */ -#define BM_I2S_TCR4_MF (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */ -#define BS_I2S_TCR4_MF (1U) /*!< Bit field size in bits for I2S_TCR4_MF. */ - -/*! @brief Read current value of the I2S_TCR4_MF field. */ -#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF)) - -/*! @brief Format value for bitfield I2S_TCR4_MF. */ -#define BF_I2S_TCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF) - -/*! @brief Set the MF field to a new value. */ -#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field SYWD[12:8] (RW) - * - * Configures the length of the frame sync in number of bit clocks. The value - * written must be one less than the number of bit clocks. For example, write 0 for - * the frame sync to assert for one bit clock only. The sync width cannot be - * configured longer than the first word of the frame. - */ -/*@{*/ -#define BP_I2S_TCR4_SYWD (8U) /*!< Bit position for I2S_TCR4_SYWD. */ -#define BM_I2S_TCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */ -#define BS_I2S_TCR4_SYWD (5U) /*!< Bit field size in bits for I2S_TCR4_SYWD. */ - -/*! @brief Read current value of the I2S_TCR4_SYWD field. */ -#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD) - -/*! @brief Format value for bitfield I2S_TCR4_SYWD. */ -#define BF_I2S_TCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD) - -/*! @brief Set the SYWD field to a new value. */ -#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FRSZ[19:16] (RW) - * - * Configures the number of words in each frame. The value written must be one - * less than the number of words in the frame. For example, write 0 for one word - * per frame. The maximum supported frame size is 16 words. - */ -/*@{*/ -#define BP_I2S_TCR4_FRSZ (16U) /*!< Bit position for I2S_TCR4_FRSZ. */ -#define BM_I2S_TCR4_FRSZ (0x000F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */ -#define BS_I2S_TCR4_FRSZ (4U) /*!< Bit field size in bits for I2S_TCR4_FRSZ. */ - -/*! @brief Read current value of the I2S_TCR4_FRSZ field. */ -#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ) - -/*! @brief Format value for bitfield I2S_TCR4_FRSZ. */ -#define BF_I2S_TCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ) - -/*! @brief Set the FRSZ field to a new value. */ -#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FPACK[25:24] (RW) - * - * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If - * the word size is greater than 8-bit or 16-bit then only the first 8-bit or - * 16-bits are loaded from the FIFO. The first word in each frame always starts with - * a new 32-bit FIFO word and the first bit shifted must be configured within the - * first packed word. When FIFO packing is enabled, the FIFO write pointer will - * only increment when the full 32-bit FIFO word has been written by software. - * - * Values: - * - 00 - FIFO packing is disabled - * - 01 - Reserved - * - 10 - 8-bit FIFO packing is enabled - * - 11 - 16-bit FIFO packing is enabled - */ -/*@{*/ -#define BP_I2S_TCR4_FPACK (24U) /*!< Bit position for I2S_TCR4_FPACK. */ -#define BM_I2S_TCR4_FPACK (0x03000000U) /*!< Bit mask for I2S_TCR4_FPACK. */ -#define BS_I2S_TCR4_FPACK (2U) /*!< Bit field size in bits for I2S_TCR4_FPACK. */ - -/*! @brief Read current value of the I2S_TCR4_FPACK field. */ -#define BR_I2S_TCR4_FPACK(x) (HW_I2S_TCR4(x).B.FPACK) - -/*! @brief Format value for bitfield I2S_TCR4_FPACK. */ -#define BF_I2S_TCR4_FPACK(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FPACK) & BM_I2S_TCR4_FPACK) - -/*! @brief Set the FPACK field to a new value. */ -#define BW_I2S_TCR4_FPACK(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FPACK) | BF_I2S_TCR4_FPACK(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FCONT[28] (RW) - * - * Configures when the SAI will continue transmitting after a FIFO error has - * been detected. - * - * Values: - * - 0 - On FIFO error, the SAI will continue from the start of the next frame - * after the FIFO error flag has been cleared. - * - 1 - On FIFO error, the SAI will continue from the same word that caused the - * FIFO error to set after the FIFO warning flag has been cleared. - */ -/*@{*/ -#define BP_I2S_TCR4_FCONT (28U) /*!< Bit position for I2S_TCR4_FCONT. */ -#define BM_I2S_TCR4_FCONT (0x10000000U) /*!< Bit mask for I2S_TCR4_FCONT. */ -#define BS_I2S_TCR4_FCONT (1U) /*!< Bit field size in bits for I2S_TCR4_FCONT. */ - -/*! @brief Read current value of the I2S_TCR4_FCONT field. */ -#define BR_I2S_TCR4_FCONT(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FCONT)) - -/*! @brief Format value for bitfield I2S_TCR4_FCONT. */ -#define BF_I2S_TCR4_FCONT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FCONT) & BM_I2S_TCR4_FCONT) - -/*! @brief Set the FCONT field to a new value. */ -#define BW_I2S_TCR4_FCONT(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FCONT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr5 -{ - uint32_t U; - struct _hw_i2s_tcr5_bitfields - { - uint32_t RESERVED0 : 8; /*!< [7:0] */ - uint32_t FBT : 5; /*!< [12:8] First Bit Shifted */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t W0W : 5; /*!< [20:16] Word 0 Width */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t WNW : 5; /*!< [28:24] Word N Width */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_i2s_tcr5_t; - -/*! - * @name Constants and macros for entire I2S_TCR5 register - */ -/*@{*/ -#define HW_I2S_TCR5_ADDR(x) ((x) + 0x14U) - -#define HW_I2S_TCR5(x) (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x)) -#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U) -#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v)) -#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) | (v))) -#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v))) -#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR5 bitfields - */ - -/*! - * @name Register I2S_TCR5, field FBT[12:8] (RW) - * - * Configures the bit index for the first bit transmitted for each word in the - * frame. If configured for MSB First, the index of the next bit transmitted is - * one less than the current bit transmitted. If configured for LSB First, the - * index of the next bit transmitted is one more than the current bit transmitted. - * The value written must be greater than or equal to the word width when - * configured for MSB First. The value written must be less than or equal to 31-word width - * when configured for LSB First. - */ -/*@{*/ -#define BP_I2S_TCR5_FBT (8U) /*!< Bit position for I2S_TCR5_FBT. */ -#define BM_I2S_TCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */ -#define BS_I2S_TCR5_FBT (5U) /*!< Bit field size in bits for I2S_TCR5_FBT. */ - -/*! @brief Read current value of the I2S_TCR5_FBT field. */ -#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT) - -/*! @brief Format value for bitfield I2S_TCR5_FBT. */ -#define BF_I2S_TCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT) - -/*! @brief Set the FBT field to a new value. */ -#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR5, field W0W[20:16] (RW) - * - * Configures the number of bits in the first word in each frame. The value - * written must be one less than the number of bits in the first word. Word width of - * less than 8 bits is not supported if there is only one word per frame. - */ -/*@{*/ -#define BP_I2S_TCR5_W0W (16U) /*!< Bit position for I2S_TCR5_W0W. */ -#define BM_I2S_TCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */ -#define BS_I2S_TCR5_W0W (5U) /*!< Bit field size in bits for I2S_TCR5_W0W. */ - -/*! @brief Read current value of the I2S_TCR5_W0W field. */ -#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W) - -/*! @brief Format value for bitfield I2S_TCR5_W0W. */ -#define BF_I2S_TCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W) - -/*! @brief Set the W0W field to a new value. */ -#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR5, field WNW[28:24] (RW) - * - * Configures the number of bits in each word, for each word except the first in - * the frame. The value written must be one less than the number of bits per - * word. Word width of less than 8 bits is not supported. - */ -/*@{*/ -#define BP_I2S_TCR5_WNW (24U) /*!< Bit position for I2S_TCR5_WNW. */ -#define BM_I2S_TCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */ -#define BS_I2S_TCR5_WNW (5U) /*!< Bit field size in bits for I2S_TCR5_WNW. */ - -/*! @brief Read current value of the I2S_TCR5_WNW field. */ -#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW) - -/*! @brief Format value for bitfield I2S_TCR5_WNW. */ -#define BF_I2S_TCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW) - -/*! @brief Set the WNW field to a new value. */ -#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TDRn - SAI Transmit Data Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tdrn -{ - uint32_t U; - struct _hw_i2s_tdrn_bitfields - { - uint32_t TDR : 32; /*!< [31:0] Transmit Data Register */ - } B; -} hw_i2s_tdrn_t; - -/*! - * @name Constants and macros for entire I2S_TDRn register - */ -/*@{*/ -#define HW_I2S_TDRn_COUNT (1U) - -#define HW_I2S_TDRn_ADDR(x, n) ((x) + 0x20U + (0x4U * (n))) - -#define HW_I2S_TDRn(x, n) (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n)) -#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U) -#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual I2S_TDRn bitfields - */ - -/*! - * @name Register I2S_TDRn, field TDR[31:0] (WORZ) - * - * The corresponding TCR3[TCE] bit must be set before accessing the channel's - * transmit data register. Writes to this register when the transmit FIFO is not - * full will push the data written into the transmit data FIFO. Writes to this - * register when the transmit FIFO is full are ignored. - */ -/*@{*/ -#define BP_I2S_TDRn_TDR (0U) /*!< Bit position for I2S_TDRn_TDR. */ -#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */ -#define BS_I2S_TDRn_TDR (32U) /*!< Bit field size in bits for I2S_TDRn_TDR. */ - -/*! @brief Format value for bitfield I2S_TDRn_TDR. */ -#define BF_I2S_TDRn_TDR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR) - -/*! @brief Set the TDR field to a new value. */ -#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TFRn - SAI Transmit FIFO Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO) - * - * Reset value: 0x00000000U - * - * The MSB of the read and write pointers is used to distinguish between FIFO - * full and empty conditions. If the read and write pointers are identical, then - * the FIFO is empty. If the read and write pointers are identical except for the - * MSB, then the FIFO is full. - */ -typedef union _hw_i2s_tfrn -{ - uint32_t U; - struct _hw_i2s_tfrn_bitfields - { - uint32_t RFP : 4; /*!< [3:0] Read FIFO Pointer */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t WFP : 4; /*!< [19:16] Write FIFO Pointer */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_i2s_tfrn_t; - -/*! - * @name Constants and macros for entire I2S_TFRn register - */ -/*@{*/ -#define HW_I2S_TFRn_COUNT (1U) - -#define HW_I2S_TFRn_ADDR(x, n) ((x) + 0x40U + (0x4U * (n))) - -#define HW_I2S_TFRn(x, n) (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n)) -#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual I2S_TFRn bitfields - */ - -/*! - * @name Register I2S_TFRn, field RFP[3:0] (RO) - * - * FIFO read pointer for transmit data channel. - */ -/*@{*/ -#define BP_I2S_TFRn_RFP (0U) /*!< Bit position for I2S_TFRn_RFP. */ -#define BM_I2S_TFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */ -#define BS_I2S_TFRn_RFP (4U) /*!< Bit field size in bits for I2S_TFRn_RFP. */ - -/*! @brief Read current value of the I2S_TFRn_RFP field. */ -#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP) -/*@}*/ - -/*! - * @name Register I2S_TFRn, field WFP[19:16] (RO) - * - * FIFO write pointer for transmit data channel. - */ -/*@{*/ -#define BP_I2S_TFRn_WFP (16U) /*!< Bit position for I2S_TFRn_WFP. */ -#define BM_I2S_TFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */ -#define BS_I2S_TFRn_WFP (4U) /*!< Bit field size in bits for I2S_TFRn_WFP. */ - -/*! @brief Read current value of the I2S_TFRn_WFP field. */ -#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TMR - SAI Transmit Mask Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW) - * - * Reset value: 0x00000000U - * - * This register is double-buffered and updates: When TCSR[TE] is first set At - * the end of each frame. This allows the masked words in each frame to change - * from frame to frame. - */ -typedef union _hw_i2s_tmr -{ - uint32_t U; - struct _hw_i2s_tmr_bitfields - { - uint32_t TWM : 16; /*!< [15:0] Transmit Word Mask */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_i2s_tmr_t; - -/*! - * @name Constants and macros for entire I2S_TMR register - */ -/*@{*/ -#define HW_I2S_TMR_ADDR(x) ((x) + 0x60U) - -#define HW_I2S_TMR(x) (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x)) -#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U) -#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v)) -#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) | (v))) -#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v))) -#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TMR bitfields - */ - -/*! - * @name Register I2S_TMR, field TWM[15:0] (RW) - * - * Configures whether the transmit word is masked (transmit data pin tristated - * and transmit data not read from FIFO) for the corresponding word in the frame. - * - * Values: - * - 0 - Word N is enabled. - * - 1 - Word N is masked. The transmit data pins are tri-stated when masked. - */ -/*@{*/ -#define BP_I2S_TMR_TWM (0U) /*!< Bit position for I2S_TMR_TWM. */ -#define BM_I2S_TMR_TWM (0x0000FFFFU) /*!< Bit mask for I2S_TMR_TWM. */ -#define BS_I2S_TMR_TWM (16U) /*!< Bit field size in bits for I2S_TMR_TWM. */ - -/*! @brief Read current value of the I2S_TMR_TWM field. */ -#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).B.TWM) - -/*! @brief Format value for bitfield I2S_TMR_TWM. */ -#define BF_I2S_TMR_TWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM) - -/*! @brief Set the TWM field to a new value. */ -#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, (HW_I2S_TMR_RD(x) & ~BM_I2S_TMR_TWM) | BF_I2S_TMR_TWM(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCSR - SAI Receive Control Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCSR - SAI Receive Control Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_rcsr -{ - uint32_t U; - struct _hw_i2s_rcsr_bitfields - { - uint32_t FRDE : 1; /*!< [0] FIFO Request DMA Enable */ - uint32_t FWDE : 1; /*!< [1] FIFO Warning DMA Enable */ - uint32_t RESERVED0 : 6; /*!< [7:2] */ - uint32_t FRIE : 1; /*!< [8] FIFO Request Interrupt Enable */ - uint32_t FWIE : 1; /*!< [9] FIFO Warning Interrupt Enable */ - uint32_t FEIE : 1; /*!< [10] FIFO Error Interrupt Enable */ - uint32_t SEIE : 1; /*!< [11] Sync Error Interrupt Enable */ - uint32_t WSIE : 1; /*!< [12] Word Start Interrupt Enable */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t FRF : 1; /*!< [16] FIFO Request Flag */ - uint32_t FWF : 1; /*!< [17] FIFO Warning Flag */ - uint32_t FEF : 1; /*!< [18] FIFO Error Flag */ - uint32_t SEF : 1; /*!< [19] Sync Error Flag */ - uint32_t WSF : 1; /*!< [20] Word Start Flag */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t SR : 1; /*!< [24] Software Reset */ - uint32_t FR : 1; /*!< [25] FIFO Reset */ - uint32_t RESERVED3 : 2; /*!< [27:26] */ - uint32_t BCE : 1; /*!< [28] Bit Clock Enable */ - uint32_t DBGE : 1; /*!< [29] Debug Enable */ - uint32_t STOPE : 1; /*!< [30] Stop Enable */ - uint32_t RE : 1; /*!< [31] Receiver Enable */ - } B; -} hw_i2s_rcsr_t; - -/*! - * @name Constants and macros for entire I2S_RCSR register - */ -/*@{*/ -#define HW_I2S_RCSR_ADDR(x) ((x) + 0x80U) - -#define HW_I2S_RCSR(x) (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x)) -#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U) -#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v)) -#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) | (v))) -#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v))) -#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCSR bitfields - */ - -/*! - * @name Register I2S_RCSR, field FRDE[0] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_RCSR_FRDE (0U) /*!< Bit position for I2S_RCSR_FRDE. */ -#define BM_I2S_RCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */ -#define BS_I2S_RCSR_FRDE (1U) /*!< Bit field size in bits for I2S_RCSR_FRDE. */ - -/*! @brief Read current value of the I2S_RCSR_FRDE field. */ -#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE)) - -/*! @brief Format value for bitfield I2S_RCSR_FRDE. */ -#define BF_I2S_RCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE) - -/*! @brief Set the FRDE field to a new value. */ -#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FWDE[1] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_RCSR_FWDE (1U) /*!< Bit position for I2S_RCSR_FWDE. */ -#define BM_I2S_RCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */ -#define BS_I2S_RCSR_FWDE (1U) /*!< Bit field size in bits for I2S_RCSR_FWDE. */ - -/*! @brief Read current value of the I2S_RCSR_FWDE field. */ -#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE)) - -/*! @brief Format value for bitfield I2S_RCSR_FWDE. */ -#define BF_I2S_RCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE) - -/*! @brief Set the FWDE field to a new value. */ -#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FRIE[8] (RW) - * - * Enables/disables FIFO request interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_FRIE (8U) /*!< Bit position for I2S_RCSR_FRIE. */ -#define BM_I2S_RCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */ -#define BS_I2S_RCSR_FRIE (1U) /*!< Bit field size in bits for I2S_RCSR_FRIE. */ - -/*! @brief Read current value of the I2S_RCSR_FRIE field. */ -#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE)) - -/*! @brief Format value for bitfield I2S_RCSR_FRIE. */ -#define BF_I2S_RCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE) - -/*! @brief Set the FRIE field to a new value. */ -#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FWIE[9] (RW) - * - * Enables/disables FIFO warning interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_FWIE (9U) /*!< Bit position for I2S_RCSR_FWIE. */ -#define BM_I2S_RCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */ -#define BS_I2S_RCSR_FWIE (1U) /*!< Bit field size in bits for I2S_RCSR_FWIE. */ - -/*! @brief Read current value of the I2S_RCSR_FWIE field. */ -#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE)) - -/*! @brief Format value for bitfield I2S_RCSR_FWIE. */ -#define BF_I2S_RCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE) - -/*! @brief Set the FWIE field to a new value. */ -#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FEIE[10] (RW) - * - * Enables/disables FIFO error interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_FEIE (10U) /*!< Bit position for I2S_RCSR_FEIE. */ -#define BM_I2S_RCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */ -#define BS_I2S_RCSR_FEIE (1U) /*!< Bit field size in bits for I2S_RCSR_FEIE. */ - -/*! @brief Read current value of the I2S_RCSR_FEIE field. */ -#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE)) - -/*! @brief Format value for bitfield I2S_RCSR_FEIE. */ -#define BF_I2S_RCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field SEIE[11] (RW) - * - * Enables/disables sync error interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_SEIE (11U) /*!< Bit position for I2S_RCSR_SEIE. */ -#define BM_I2S_RCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */ -#define BS_I2S_RCSR_SEIE (1U) /*!< Bit field size in bits for I2S_RCSR_SEIE. */ - -/*! @brief Read current value of the I2S_RCSR_SEIE field. */ -#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE)) - -/*! @brief Format value for bitfield I2S_RCSR_SEIE. */ -#define BF_I2S_RCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE) - -/*! @brief Set the SEIE field to a new value. */ -#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field WSIE[12] (RW) - * - * Enables/disables word start interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_WSIE (12U) /*!< Bit position for I2S_RCSR_WSIE. */ -#define BM_I2S_RCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */ -#define BS_I2S_RCSR_WSIE (1U) /*!< Bit field size in bits for I2S_RCSR_WSIE. */ - -/*! @brief Read current value of the I2S_RCSR_WSIE field. */ -#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE)) - -/*! @brief Format value for bitfield I2S_RCSR_WSIE. */ -#define BF_I2S_RCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE) - -/*! @brief Set the WSIE field to a new value. */ -#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FRF[16] (RO) - * - * Indicates that the number of words in an enabled receive channel FIFO is - * greater than the receive FIFO watermark. - * - * Values: - * - 0 - Receive FIFO watermark not reached. - * - 1 - Receive FIFO watermark has been reached. - */ -/*@{*/ -#define BP_I2S_RCSR_FRF (16U) /*!< Bit position for I2S_RCSR_FRF. */ -#define BM_I2S_RCSR_FRF (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */ -#define BS_I2S_RCSR_FRF (1U) /*!< Bit field size in bits for I2S_RCSR_FRF. */ - -/*! @brief Read current value of the I2S_RCSR_FRF field. */ -#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FWF[17] (RO) - * - * Indicates that an enabled receive FIFO is full. - * - * Values: - * - 0 - No enabled receive FIFO is full. - * - 1 - Enabled receive FIFO is full. - */ -/*@{*/ -#define BP_I2S_RCSR_FWF (17U) /*!< Bit position for I2S_RCSR_FWF. */ -#define BM_I2S_RCSR_FWF (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */ -#define BS_I2S_RCSR_FWF (1U) /*!< Bit field size in bits for I2S_RCSR_FWF. */ - -/*! @brief Read current value of the I2S_RCSR_FWF field. */ -#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FEF[18] (W1C) - * - * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to - * this field to clear this flag. - * - * Values: - * - 0 - Receive overflow not detected. - * - 1 - Receive overflow detected. - */ -/*@{*/ -#define BP_I2S_RCSR_FEF (18U) /*!< Bit position for I2S_RCSR_FEF. */ -#define BM_I2S_RCSR_FEF (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */ -#define BS_I2S_RCSR_FEF (1U) /*!< Bit field size in bits for I2S_RCSR_FEF. */ - -/*! @brief Read current value of the I2S_RCSR_FEF field. */ -#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF)) - -/*! @brief Format value for bitfield I2S_RCSR_FEF. */ -#define BF_I2S_RCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF) - -/*! @brief Set the FEF field to a new value. */ -#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field SEF[19] (W1C) - * - * Indicates that an error in the externally-generated frame sync has been - * detected. Write a logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Sync error not detected. - * - 1 - Frame sync error detected. - */ -/*@{*/ -#define BP_I2S_RCSR_SEF (19U) /*!< Bit position for I2S_RCSR_SEF. */ -#define BM_I2S_RCSR_SEF (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */ -#define BS_I2S_RCSR_SEF (1U) /*!< Bit field size in bits for I2S_RCSR_SEF. */ - -/*! @brief Read current value of the I2S_RCSR_SEF field. */ -#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF)) - -/*! @brief Format value for bitfield I2S_RCSR_SEF. */ -#define BF_I2S_RCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF) - -/*! @brief Set the SEF field to a new value. */ -#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field WSF[20] (W1C) - * - * Indicates that the start of the configured word has been detected. Write a - * logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Start of word not detected. - * - 1 - Start of word detected. - */ -/*@{*/ -#define BP_I2S_RCSR_WSF (20U) /*!< Bit position for I2S_RCSR_WSF. */ -#define BM_I2S_RCSR_WSF (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */ -#define BS_I2S_RCSR_WSF (1U) /*!< Bit field size in bits for I2S_RCSR_WSF. */ - -/*! @brief Read current value of the I2S_RCSR_WSF field. */ -#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF)) - -/*! @brief Format value for bitfield I2S_RCSR_WSF. */ -#define BF_I2S_RCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF) - -/*! @brief Set the WSF field to a new value. */ -#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field SR[24] (RW) - * - * Resets the internal receiver logic including the FIFO pointers. - * Software-visible registers are not affected, except for the status registers. - * - * Values: - * - 0 - No effect. - * - 1 - Software reset. - */ -/*@{*/ -#define BP_I2S_RCSR_SR (24U) /*!< Bit position for I2S_RCSR_SR. */ -#define BM_I2S_RCSR_SR (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */ -#define BS_I2S_RCSR_SR (1U) /*!< Bit field size in bits for I2S_RCSR_SR. */ - -/*! @brief Read current value of the I2S_RCSR_SR field. */ -#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR)) - -/*! @brief Format value for bitfield I2S_RCSR_SR. */ -#define BF_I2S_RCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR) - -/*! @brief Set the SR field to a new value. */ -#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FR[25] (WORZ) - * - * Resets the FIFO pointers. Reading this field will always return zero. FIFO - * pointers should only be reset when the receiver is disabled or the FIFO error - * flag is set. - * - * Values: - * - 0 - No effect. - * - 1 - FIFO reset. - */ -/*@{*/ -#define BP_I2S_RCSR_FR (25U) /*!< Bit position for I2S_RCSR_FR. */ -#define BM_I2S_RCSR_FR (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */ -#define BS_I2S_RCSR_FR (1U) /*!< Bit field size in bits for I2S_RCSR_FR. */ - -/*! @brief Format value for bitfield I2S_RCSR_FR. */ -#define BF_I2S_RCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR) - -/*! @brief Set the FR field to a new value. */ -#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field BCE[28] (RW) - * - * Enables the receive bit clock, separately from RE. This field is - * automatically set whenever RE is set. When software clears this field, the receive bit - * clock remains enabled, and this field remains set, until the end of the current - * frame. - * - * Values: - * - 0 - Receive bit clock is disabled. - * - 1 - Receive bit clock is enabled. - */ -/*@{*/ -#define BP_I2S_RCSR_BCE (28U) /*!< Bit position for I2S_RCSR_BCE. */ -#define BM_I2S_RCSR_BCE (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */ -#define BS_I2S_RCSR_BCE (1U) /*!< Bit field size in bits for I2S_RCSR_BCE. */ - -/*! @brief Read current value of the I2S_RCSR_BCE field. */ -#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE)) - -/*! @brief Format value for bitfield I2S_RCSR_BCE. */ -#define BF_I2S_RCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE) - -/*! @brief Set the BCE field to a new value. */ -#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field DBGE[29] (RW) - * - * Enables/disables receiver operation in Debug mode. The receive bit clock is - * not affected by Debug mode. - * - * Values: - * - 0 - Receiver is disabled in Debug mode, after completing the current frame. - * - 1 - Receiver is enabled in Debug mode. - */ -/*@{*/ -#define BP_I2S_RCSR_DBGE (29U) /*!< Bit position for I2S_RCSR_DBGE. */ -#define BM_I2S_RCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */ -#define BS_I2S_RCSR_DBGE (1U) /*!< Bit field size in bits for I2S_RCSR_DBGE. */ - -/*! @brief Read current value of the I2S_RCSR_DBGE field. */ -#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE)) - -/*! @brief Format value for bitfield I2S_RCSR_DBGE. */ -#define BF_I2S_RCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE) - -/*! @brief Set the DBGE field to a new value. */ -#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field STOPE[30] (RW) - * - * Configures receiver operation in Stop mode. This bit is ignored and the - * receiver is disabled in all low-leakage stop modes. - * - * Values: - * - 0 - Receiver disabled in Stop mode. - * - 1 - Receiver enabled in Stop mode. - */ -/*@{*/ -#define BP_I2S_RCSR_STOPE (30U) /*!< Bit position for I2S_RCSR_STOPE. */ -#define BM_I2S_RCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */ -#define BS_I2S_RCSR_STOPE (1U) /*!< Bit field size in bits for I2S_RCSR_STOPE. */ - -/*! @brief Read current value of the I2S_RCSR_STOPE field. */ -#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE)) - -/*! @brief Format value for bitfield I2S_RCSR_STOPE. */ -#define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE) - -/*! @brief Set the STOPE field to a new value. */ -#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field RE[31] (RW) - * - * Enables/disables the receiver. When software clears this field, the receiver - * remains enabled, and this bit remains set, until the end of the current frame. - * - * Values: - * - 0 - Receiver is disabled. - * - 1 - Receiver is enabled, or receiver has been disabled and has not yet - * reached end of frame. - */ -/*@{*/ -#define BP_I2S_RCSR_RE (31U) /*!< Bit position for I2S_RCSR_RE. */ -#define BM_I2S_RCSR_RE (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */ -#define BS_I2S_RCSR_RE (1U) /*!< Bit field size in bits for I2S_RCSR_RE. */ - -/*! @brief Read current value of the I2S_RCSR_RE field. */ -#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE)) - -/*! @brief Format value for bitfield I2S_RCSR_RE. */ -#define BF_I2S_RCSR_RE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE) - -/*! @brief Set the RE field to a new value. */ -#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR1 - SAI Receive Configuration 1 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_rcr1 -{ - uint32_t U; - struct _hw_i2s_rcr1_bitfields - { - uint32_t RFW : 3; /*!< [2:0] Receive FIFO Watermark */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_i2s_rcr1_t; - -/*! - * @name Constants and macros for entire I2S_RCR1 register - */ -/*@{*/ -#define HW_I2S_RCR1_ADDR(x) ((x) + 0x84U) - -#define HW_I2S_RCR1(x) (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x)) -#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U) -#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v)) -#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) | (v))) -#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v))) -#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR1 bitfields - */ - -/*! - * @name Register I2S_RCR1, field RFW[2:0] (RW) - * - * Configures the watermark level for all enabled receiver channels. - */ -/*@{*/ -#define BP_I2S_RCR1_RFW (0U) /*!< Bit position for I2S_RCR1_RFW. */ -#define BM_I2S_RCR1_RFW (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */ -#define BS_I2S_RCR1_RFW (3U) /*!< Bit field size in bits for I2S_RCR1_RFW. */ - -/*! @brief Read current value of the I2S_RCR1_RFW field. */ -#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW) - -/*! @brief Format value for bitfield I2S_RCR1_RFW. */ -#define BF_I2S_RCR1_RFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW) - -/*! @brief Set the RFW field to a new value. */ -#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR2 - SAI Receive Configuration 2 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr2 -{ - uint32_t U; - struct _hw_i2s_rcr2_bitfields - { - uint32_t DIV : 8; /*!< [7:0] Bit Clock Divide */ - uint32_t RESERVED0 : 16; /*!< [23:8] */ - uint32_t BCD : 1; /*!< [24] Bit Clock Direction */ - uint32_t BCP : 1; /*!< [25] Bit Clock Polarity */ - uint32_t MSEL : 2; /*!< [27:26] MCLK Select */ - uint32_t BCI : 1; /*!< [28] Bit Clock Input */ - uint32_t BCS : 1; /*!< [29] Bit Clock Swap */ - uint32_t SYNC : 2; /*!< [31:30] Synchronous Mode */ - } B; -} hw_i2s_rcr2_t; - -/*! - * @name Constants and macros for entire I2S_RCR2 register - */ -/*@{*/ -#define HW_I2S_RCR2_ADDR(x) ((x) + 0x88U) - -#define HW_I2S_RCR2(x) (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x)) -#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U) -#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v)) -#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) | (v))) -#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v))) -#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR2 bitfields - */ - -/*! - * @name Register I2S_RCR2, field DIV[7:0] (RW) - * - * Divides down the audio master clock to generate the bit clock when configured - * for an internal bit clock. The division value is (DIV + 1) * 2. - */ -/*@{*/ -#define BP_I2S_RCR2_DIV (0U) /*!< Bit position for I2S_RCR2_DIV. */ -#define BM_I2S_RCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */ -#define BS_I2S_RCR2_DIV (8U) /*!< Bit field size in bits for I2S_RCR2_DIV. */ - -/*! @brief Read current value of the I2S_RCR2_DIV field. */ -#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV) - -/*! @brief Format value for bitfield I2S_RCR2_DIV. */ -#define BF_I2S_RCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV) - -/*! @brief Set the DIV field to a new value. */ -#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCD[24] (RW) - * - * Configures the direction of the bit clock. - * - * Values: - * - 0 - Bit clock is generated externally in Slave mode. - * - 1 - Bit clock is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_RCR2_BCD (24U) /*!< Bit position for I2S_RCR2_BCD. */ -#define BM_I2S_RCR2_BCD (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */ -#define BS_I2S_RCR2_BCD (1U) /*!< Bit field size in bits for I2S_RCR2_BCD. */ - -/*! @brief Read current value of the I2S_RCR2_BCD field. */ -#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD)) - -/*! @brief Format value for bitfield I2S_RCR2_BCD. */ -#define BF_I2S_RCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD) - -/*! @brief Set the BCD field to a new value. */ -#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCP[25] (RW) - * - * Configures the polarity of the bit clock. - * - * Values: - * - 0 - Bit Clock is active high with drive outputs on rising edge and sample - * inputs on falling edge. - * - 1 - Bit Clock is active low with drive outputs on falling edge and sample - * inputs on rising edge. - */ -/*@{*/ -#define BP_I2S_RCR2_BCP (25U) /*!< Bit position for I2S_RCR2_BCP. */ -#define BM_I2S_RCR2_BCP (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */ -#define BS_I2S_RCR2_BCP (1U) /*!< Bit field size in bits for I2S_RCR2_BCP. */ - -/*! @brief Read current value of the I2S_RCR2_BCP field. */ -#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP)) - -/*! @brief Format value for bitfield I2S_RCR2_BCP. */ -#define BF_I2S_RCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP) - -/*! @brief Set the BCP field to a new value. */ -#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field MSEL[27:26] (RW) - * - * Selects the audio Master Clock option used to generate an internally - * generated bit clock. This field has no effect when configured for an externally - * generated bit clock. Depending on the device, some Master Clock options might not be - * available. See the chip configuration details for the availability and - * chip-specific meaning of each option. - * - * Values: - * - 00 - Bus Clock selected. - * - 01 - Master Clock (MCLK) 1 option selected. - * - 10 - Master Clock (MCLK) 2 option selected. - * - 11 - Master Clock (MCLK) 3 option selected. - */ -/*@{*/ -#define BP_I2S_RCR2_MSEL (26U) /*!< Bit position for I2S_RCR2_MSEL. */ -#define BM_I2S_RCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */ -#define BS_I2S_RCR2_MSEL (2U) /*!< Bit field size in bits for I2S_RCR2_MSEL. */ - -/*! @brief Read current value of the I2S_RCR2_MSEL field. */ -#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL) - -/*! @brief Format value for bitfield I2S_RCR2_MSEL. */ -#define BF_I2S_RCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL) - -/*! @brief Set the MSEL field to a new value. */ -#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCI[28] (RW) - * - * When this field is set and using an internally generated bit clock in either - * synchronous or asynchronous mode, the bit clock actually used by the receiver - * is delayed by the pad output delay (the receiver is clocked by the pad input - * as if the clock was externally generated). This has the effect of decreasing - * the data input setup time, but increasing the data output valid time. The slave - * mode timing from the datasheet should be used for the receiver when this bit - * is set. In synchronous mode, this bit allows the receiver to use the slave mode - * timing from the datasheet, while the transmitter uses the master mode timing. - * This field has no effect when configured for an externally generated bit - * clock . - * - * Values: - * - 0 - No effect. - * - 1 - Internal logic is clocked as if bit clock was externally generated. - */ -/*@{*/ -#define BP_I2S_RCR2_BCI (28U) /*!< Bit position for I2S_RCR2_BCI. */ -#define BM_I2S_RCR2_BCI (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */ -#define BS_I2S_RCR2_BCI (1U) /*!< Bit field size in bits for I2S_RCR2_BCI. */ - -/*! @brief Read current value of the I2S_RCR2_BCI field. */ -#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI)) - -/*! @brief Format value for bitfield I2S_RCR2_BCI. */ -#define BF_I2S_RCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI) - -/*! @brief Set the BCI field to a new value. */ -#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCS[29] (RW) - * - * This field swaps the bit clock used by the receiver. When the receiver is - * configured in asynchronous mode and this bit is set, the receiver is clocked by - * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and - * receiver to share the same bit clock, but the receiver continues to use the receiver - * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous - * mode, the transmitter BCS field and receiver BCS field must be set to the same - * value. When both are set, the transmitter and receiver are both clocked by the - * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync - * (SAI_TX_SYNC). - * - * Values: - * - 0 - Use the normal bit clock source. - * - 1 - Swap the bit clock source. - */ -/*@{*/ -#define BP_I2S_RCR2_BCS (29U) /*!< Bit position for I2S_RCR2_BCS. */ -#define BM_I2S_RCR2_BCS (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */ -#define BS_I2S_RCR2_BCS (1U) /*!< Bit field size in bits for I2S_RCR2_BCS. */ - -/*! @brief Read current value of the I2S_RCR2_BCS field. */ -#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS)) - -/*! @brief Format value for bitfield I2S_RCR2_BCS. */ -#define BF_I2S_RCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS) - -/*! @brief Set the BCS field to a new value. */ -#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field SYNC[31:30] (RW) - * - * Configures between asynchronous and synchronous modes of operation. When - * configured for a synchronous mode of operation, the transmitter must be configured - * for asynchronous operation. - * - * Values: - * - 00 - Asynchronous mode. - * - 01 - Synchronous with transmitter. - * - 10 - Synchronous with another SAI receiver. - * - 11 - Synchronous with another SAI transmitter. - */ -/*@{*/ -#define BP_I2S_RCR2_SYNC (30U) /*!< Bit position for I2S_RCR2_SYNC. */ -#define BM_I2S_RCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */ -#define BS_I2S_RCR2_SYNC (2U) /*!< Bit field size in bits for I2S_RCR2_SYNC. */ - -/*! @brief Read current value of the I2S_RCR2_SYNC field. */ -#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC) - -/*! @brief Format value for bitfield I2S_RCR2_SYNC. */ -#define BF_I2S_RCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC) - -/*! @brief Set the SYNC field to a new value. */ -#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR3 - SAI Receive Configuration 3 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_rcr3 -{ - uint32_t U; - struct _hw_i2s_rcr3_bitfields - { - uint32_t WDFL : 4; /*!< [3:0] Word Flag Configuration */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t RCE : 1; /*!< [16] Receive Channel Enable */ - uint32_t RESERVED1 : 15; /*!< [31:17] */ - } B; -} hw_i2s_rcr3_t; - -/*! - * @name Constants and macros for entire I2S_RCR3 register - */ -/*@{*/ -#define HW_I2S_RCR3_ADDR(x) ((x) + 0x8CU) - -#define HW_I2S_RCR3(x) (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x)) -#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U) -#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v)) -#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) | (v))) -#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v))) -#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR3 bitfields - */ - -/*! - * @name Register I2S_RCR3, field WDFL[3:0] (RW) - * - * Configures which word the start of word flag is set. The value written should - * be one less than the word number (for example, write zero to configure for - * the first word in the frame). When configured to a value greater than the Frame - * Size field, then the start of word flag is never set. - */ -/*@{*/ -#define BP_I2S_RCR3_WDFL (0U) /*!< Bit position for I2S_RCR3_WDFL. */ -#define BM_I2S_RCR3_WDFL (0x0000000FU) /*!< Bit mask for I2S_RCR3_WDFL. */ -#define BS_I2S_RCR3_WDFL (4U) /*!< Bit field size in bits for I2S_RCR3_WDFL. */ - -/*! @brief Read current value of the I2S_RCR3_WDFL field. */ -#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL) - -/*! @brief Format value for bitfield I2S_RCR3_WDFL. */ -#define BF_I2S_RCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL) - -/*! @brief Set the WDFL field to a new value. */ -#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR3, field RCE[16] (RW) - * - * Enables the corresponding data channel for receive operation. A channel must - * be enabled before its FIFO is accessed. Changing this field will take effect - * immediately for generating the FIFO request and warning flags, but at the end - * of each frame for receive operation. - * - * Values: - * - 0 - Receive data channel N is disabled. - * - 1 - Receive data channel N is enabled. - */ -/*@{*/ -#define BP_I2S_RCR3_RCE (16U) /*!< Bit position for I2S_RCR3_RCE. */ -#define BM_I2S_RCR3_RCE (0x00010000U) /*!< Bit mask for I2S_RCR3_RCE. */ -#define BS_I2S_RCR3_RCE (1U) /*!< Bit field size in bits for I2S_RCR3_RCE. */ - -/*! @brief Read current value of the I2S_RCR3_RCE field. */ -#define BR_I2S_RCR3_RCE(x) (BITBAND_ACCESS32(HW_I2S_RCR3_ADDR(x), BP_I2S_RCR3_RCE)) - -/*! @brief Format value for bitfield I2S_RCR3_RCE. */ -#define BF_I2S_RCR3_RCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE) - -/*! @brief Set the RCE field to a new value. */ -#define BW_I2S_RCR3_RCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR3_ADDR(x), BP_I2S_RCR3_RCE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR4 - SAI Receive Configuration 4 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr4 -{ - uint32_t U; - struct _hw_i2s_rcr4_bitfields - { - uint32_t FSD : 1; /*!< [0] Frame Sync Direction */ - uint32_t FSP : 1; /*!< [1] Frame Sync Polarity */ - uint32_t ONDEM : 1; /*!< [2] On Demand Mode */ - uint32_t FSE : 1; /*!< [3] Frame Sync Early */ - uint32_t MF : 1; /*!< [4] MSB First */ - uint32_t RESERVED0 : 3; /*!< [7:5] */ - uint32_t SYWD : 5; /*!< [12:8] Sync Width */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t FRSZ : 4; /*!< [19:16] Frame Size */ - uint32_t RESERVED2 : 4; /*!< [23:20] */ - uint32_t FPACK : 2; /*!< [25:24] FIFO Packing Mode */ - uint32_t RESERVED3 : 2; /*!< [27:26] */ - uint32_t FCONT : 1; /*!< [28] FIFO Continue on Error */ - uint32_t RESERVED4 : 3; /*!< [31:29] */ - } B; -} hw_i2s_rcr4_t; - -/*! - * @name Constants and macros for entire I2S_RCR4 register - */ -/*@{*/ -#define HW_I2S_RCR4_ADDR(x) ((x) + 0x90U) - -#define HW_I2S_RCR4(x) (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x)) -#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U) -#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v)) -#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) | (v))) -#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v))) -#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR4 bitfields - */ - -/*! - * @name Register I2S_RCR4, field FSD[0] (RW) - * - * Configures the direction of the frame sync. - * - * Values: - * - 0 - Frame Sync is generated externally in Slave mode. - * - 1 - Frame Sync is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_RCR4_FSD (0U) /*!< Bit position for I2S_RCR4_FSD. */ -#define BM_I2S_RCR4_FSD (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */ -#define BS_I2S_RCR4_FSD (1U) /*!< Bit field size in bits for I2S_RCR4_FSD. */ - -/*! @brief Read current value of the I2S_RCR4_FSD field. */ -#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD)) - -/*! @brief Format value for bitfield I2S_RCR4_FSD. */ -#define BF_I2S_RCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD) - -/*! @brief Set the FSD field to a new value. */ -#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FSP[1] (RW) - * - * Configures the polarity of the frame sync. - * - * Values: - * - 0 - Frame sync is active high. - * - 1 - Frame sync is active low. - */ -/*@{*/ -#define BP_I2S_RCR4_FSP (1U) /*!< Bit position for I2S_RCR4_FSP. */ -#define BM_I2S_RCR4_FSP (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */ -#define BS_I2S_RCR4_FSP (1U) /*!< Bit field size in bits for I2S_RCR4_FSP. */ - -/*! @brief Read current value of the I2S_RCR4_FSP field. */ -#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP)) - -/*! @brief Format value for bitfield I2S_RCR4_FSP. */ -#define BF_I2S_RCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP) - -/*! @brief Set the FSP field to a new value. */ -#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field ONDEM[2] (RW) - * - * When set, and the frame sync is generated internally, a frame sync is only - * generated when the FIFO warning flag is clear. - * - * Values: - * - 0 - Internal frame sync is generated continuously. - * - 1 - Internal frame sync is generated when the FIFO warning flag is clear. - */ -/*@{*/ -#define BP_I2S_RCR4_ONDEM (2U) /*!< Bit position for I2S_RCR4_ONDEM. */ -#define BM_I2S_RCR4_ONDEM (0x00000004U) /*!< Bit mask for I2S_RCR4_ONDEM. */ -#define BS_I2S_RCR4_ONDEM (1U) /*!< Bit field size in bits for I2S_RCR4_ONDEM. */ - -/*! @brief Read current value of the I2S_RCR4_ONDEM field. */ -#define BR_I2S_RCR4_ONDEM(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_ONDEM)) - -/*! @brief Format value for bitfield I2S_RCR4_ONDEM. */ -#define BF_I2S_RCR4_ONDEM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_ONDEM) & BM_I2S_RCR4_ONDEM) - -/*! @brief Set the ONDEM field to a new value. */ -#define BW_I2S_RCR4_ONDEM(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_ONDEM) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FSE[3] (RW) - * - * Values: - * - 0 - Frame sync asserts with the first bit of the frame. - * - 1 - Frame sync asserts one bit before the first bit of the frame. - */ -/*@{*/ -#define BP_I2S_RCR4_FSE (3U) /*!< Bit position for I2S_RCR4_FSE. */ -#define BM_I2S_RCR4_FSE (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */ -#define BS_I2S_RCR4_FSE (1U) /*!< Bit field size in bits for I2S_RCR4_FSE. */ - -/*! @brief Read current value of the I2S_RCR4_FSE field. */ -#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE)) - -/*! @brief Format value for bitfield I2S_RCR4_FSE. */ -#define BF_I2S_RCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE) - -/*! @brief Set the FSE field to a new value. */ -#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field MF[4] (RW) - * - * Configures whether the LSB or the MSB is received first. - * - * Values: - * - 0 - LSB is received first. - * - 1 - MSB is received first. - */ -/*@{*/ -#define BP_I2S_RCR4_MF (4U) /*!< Bit position for I2S_RCR4_MF. */ -#define BM_I2S_RCR4_MF (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */ -#define BS_I2S_RCR4_MF (1U) /*!< Bit field size in bits for I2S_RCR4_MF. */ - -/*! @brief Read current value of the I2S_RCR4_MF field. */ -#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF)) - -/*! @brief Format value for bitfield I2S_RCR4_MF. */ -#define BF_I2S_RCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF) - -/*! @brief Set the MF field to a new value. */ -#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field SYWD[12:8] (RW) - * - * Configures the length of the frame sync in number of bit clocks. The value - * written must be one less than the number of bit clocks. For example, write 0 for - * the frame sync to assert for one bit clock only. The sync width cannot be - * configured longer than the first word of the frame. - */ -/*@{*/ -#define BP_I2S_RCR4_SYWD (8U) /*!< Bit position for I2S_RCR4_SYWD. */ -#define BM_I2S_RCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */ -#define BS_I2S_RCR4_SYWD (5U) /*!< Bit field size in bits for I2S_RCR4_SYWD. */ - -/*! @brief Read current value of the I2S_RCR4_SYWD field. */ -#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD) - -/*! @brief Format value for bitfield I2S_RCR4_SYWD. */ -#define BF_I2S_RCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD) - -/*! @brief Set the SYWD field to a new value. */ -#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FRSZ[19:16] (RW) - * - * Configures the number of words in each frame. The value written must be one - * less than the number of words in the frame. For example, write 0 for one word - * per frame. The maximum supported frame size is 16 words. - */ -/*@{*/ -#define BP_I2S_RCR4_FRSZ (16U) /*!< Bit position for I2S_RCR4_FRSZ. */ -#define BM_I2S_RCR4_FRSZ (0x000F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */ -#define BS_I2S_RCR4_FRSZ (4U) /*!< Bit field size in bits for I2S_RCR4_FRSZ. */ - -/*! @brief Read current value of the I2S_RCR4_FRSZ field. */ -#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ) - -/*! @brief Format value for bitfield I2S_RCR4_FRSZ. */ -#define BF_I2S_RCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ) - -/*! @brief Set the FRSZ field to a new value. */ -#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FPACK[25:24] (RW) - * - * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If - * the word size is greater than 8-bit or 16-bit then only the first 8-bit or - * 16-bits are stored to the FIFO. The first word in each frame always starts with a - * new 32-bit FIFO word and the first bit shifted must be configured within the - * first packed word. When FIFO packing is enabled, the FIFO read pointer will - * only increment when the full 32-bit FIFO word has been read by software. - * - * Values: - * - 00 - FIFO packing is disabled - * - 01 - Reserved. - * - 10 - 8-bit FIFO packing is enabled - * - 11 - 16-bit FIFO packing is enabled - */ -/*@{*/ -#define BP_I2S_RCR4_FPACK (24U) /*!< Bit position for I2S_RCR4_FPACK. */ -#define BM_I2S_RCR4_FPACK (0x03000000U) /*!< Bit mask for I2S_RCR4_FPACK. */ -#define BS_I2S_RCR4_FPACK (2U) /*!< Bit field size in bits for I2S_RCR4_FPACK. */ - -/*! @brief Read current value of the I2S_RCR4_FPACK field. */ -#define BR_I2S_RCR4_FPACK(x) (HW_I2S_RCR4(x).B.FPACK) - -/*! @brief Format value for bitfield I2S_RCR4_FPACK. */ -#define BF_I2S_RCR4_FPACK(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FPACK) & BM_I2S_RCR4_FPACK) - -/*! @brief Set the FPACK field to a new value. */ -#define BW_I2S_RCR4_FPACK(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FPACK) | BF_I2S_RCR4_FPACK(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FCONT[28] (RW) - * - * Configures when the SAI will continue receiving after a FIFO error has been - * detected. - * - * Values: - * - 0 - On FIFO error, the SAI will continue from the start of the next frame - * after the FIFO error flag has been cleared. - * - 1 - On FIFO error, the SAI will continue from the same word that caused the - * FIFO error to set after the FIFO warning flag has been cleared. - */ -/*@{*/ -#define BP_I2S_RCR4_FCONT (28U) /*!< Bit position for I2S_RCR4_FCONT. */ -#define BM_I2S_RCR4_FCONT (0x10000000U) /*!< Bit mask for I2S_RCR4_FCONT. */ -#define BS_I2S_RCR4_FCONT (1U) /*!< Bit field size in bits for I2S_RCR4_FCONT. */ - -/*! @brief Read current value of the I2S_RCR4_FCONT field. */ -#define BR_I2S_RCR4_FCONT(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FCONT)) - -/*! @brief Format value for bitfield I2S_RCR4_FCONT. */ -#define BF_I2S_RCR4_FCONT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FCONT) & BM_I2S_RCR4_FCONT) - -/*! @brief Set the FCONT field to a new value. */ -#define BW_I2S_RCR4_FCONT(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FCONT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR5 - SAI Receive Configuration 5 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr5 -{ - uint32_t U; - struct _hw_i2s_rcr5_bitfields - { - uint32_t RESERVED0 : 8; /*!< [7:0] */ - uint32_t FBT : 5; /*!< [12:8] First Bit Shifted */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t W0W : 5; /*!< [20:16] Word 0 Width */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t WNW : 5; /*!< [28:24] Word N Width */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_i2s_rcr5_t; - -/*! - * @name Constants and macros for entire I2S_RCR5 register - */ -/*@{*/ -#define HW_I2S_RCR5_ADDR(x) ((x) + 0x94U) - -#define HW_I2S_RCR5(x) (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x)) -#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U) -#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v)) -#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) | (v))) -#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v))) -#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR5 bitfields - */ - -/*! - * @name Register I2S_RCR5, field FBT[12:8] (RW) - * - * Configures the bit index for the first bit received for each word in the - * frame. If configured for MSB First, the index of the next bit received is one less - * than the current bit received. If configured for LSB First, the index of the - * next bit received is one more than the current bit received. The value written - * must be greater than or equal to the word width when configured for MSB - * First. The value written must be less than or equal to 31-word width when - * configured for LSB First. - */ -/*@{*/ -#define BP_I2S_RCR5_FBT (8U) /*!< Bit position for I2S_RCR5_FBT. */ -#define BM_I2S_RCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */ -#define BS_I2S_RCR5_FBT (5U) /*!< Bit field size in bits for I2S_RCR5_FBT. */ - -/*! @brief Read current value of the I2S_RCR5_FBT field. */ -#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT) - -/*! @brief Format value for bitfield I2S_RCR5_FBT. */ -#define BF_I2S_RCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT) - -/*! @brief Set the FBT field to a new value. */ -#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR5, field W0W[20:16] (RW) - * - * Configures the number of bits in the first word in each frame. The value - * written must be one less than the number of bits in the first word. Word width of - * less than 8 bits is not supported if there is only one word per frame. - */ -/*@{*/ -#define BP_I2S_RCR5_W0W (16U) /*!< Bit position for I2S_RCR5_W0W. */ -#define BM_I2S_RCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */ -#define BS_I2S_RCR5_W0W (5U) /*!< Bit field size in bits for I2S_RCR5_W0W. */ - -/*! @brief Read current value of the I2S_RCR5_W0W field. */ -#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W) - -/*! @brief Format value for bitfield I2S_RCR5_W0W. */ -#define BF_I2S_RCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W) - -/*! @brief Set the W0W field to a new value. */ -#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR5, field WNW[28:24] (RW) - * - * Configures the number of bits in each word, for each word except the first in - * the frame. The value written must be one less than the number of bits per - * word. Word width of less than 8 bits is not supported. - */ -/*@{*/ -#define BP_I2S_RCR5_WNW (24U) /*!< Bit position for I2S_RCR5_WNW. */ -#define BM_I2S_RCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */ -#define BS_I2S_RCR5_WNW (5U) /*!< Bit field size in bits for I2S_RCR5_WNW. */ - -/*! @brief Read current value of the I2S_RCR5_WNW field. */ -#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW) - -/*! @brief Format value for bitfield I2S_RCR5_WNW. */ -#define BF_I2S_RCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW) - -/*! @brief Set the WNW field to a new value. */ -#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RDRn - SAI Receive Data Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RDRn - SAI Receive Data Register (RO) - * - * Reset value: 0x00000000U - * - * Reading this register introduces one additional peripheral clock wait state - * on each read. - */ -typedef union _hw_i2s_rdrn -{ - uint32_t U; - struct _hw_i2s_rdrn_bitfields - { - uint32_t RDR : 32; /*!< [31:0] Receive Data Register */ - } B; -} hw_i2s_rdrn_t; - -/*! - * @name Constants and macros for entire I2S_RDRn register - */ -/*@{*/ -#define HW_I2S_RDRn_COUNT (1U) - -#define HW_I2S_RDRn_ADDR(x, n) ((x) + 0xA0U + (0x4U * (n))) - -#define HW_I2S_RDRn(x, n) (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n)) -#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual I2S_RDRn bitfields - */ - -/*! - * @name Register I2S_RDRn, field RDR[31:0] (RO) - * - * The corresponding RCR3[RCE] bit must be set before accessing the channel's - * receive data register. Reads from this register when the receive FIFO is not - * empty will return the data from the top of the receive FIFO. Reads from this - * register when the receive FIFO is empty are ignored. - */ -/*@{*/ -#define BP_I2S_RDRn_RDR (0U) /*!< Bit position for I2S_RDRn_RDR. */ -#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */ -#define BS_I2S_RDRn_RDR (32U) /*!< Bit field size in bits for I2S_RDRn_RDR. */ - -/*! @brief Read current value of the I2S_RDRn_RDR field. */ -#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RFRn - SAI Receive FIFO Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO) - * - * Reset value: 0x00000000U - * - * The MSB of the read and write pointers is used to distinguish between FIFO - * full and empty conditions. If the read and write pointers are identical, then - * the FIFO is empty. If the read and write pointers are identical except for the - * MSB, then the FIFO is full. - */ -typedef union _hw_i2s_rfrn -{ - uint32_t U; - struct _hw_i2s_rfrn_bitfields - { - uint32_t RFP : 4; /*!< [3:0] Read FIFO Pointer */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t WFP : 4; /*!< [19:16] Write FIFO Pointer */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_i2s_rfrn_t; - -/*! - * @name Constants and macros for entire I2S_RFRn register - */ -/*@{*/ -#define HW_I2S_RFRn_COUNT (1U) - -#define HW_I2S_RFRn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n))) - -#define HW_I2S_RFRn(x, n) (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n)) -#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual I2S_RFRn bitfields - */ - -/*! - * @name Register I2S_RFRn, field RFP[3:0] (RO) - * - * FIFO read pointer for receive data channel. - */ -/*@{*/ -#define BP_I2S_RFRn_RFP (0U) /*!< Bit position for I2S_RFRn_RFP. */ -#define BM_I2S_RFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */ -#define BS_I2S_RFRn_RFP (4U) /*!< Bit field size in bits for I2S_RFRn_RFP. */ - -/*! @brief Read current value of the I2S_RFRn_RFP field. */ -#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP) -/*@}*/ - -/*! - * @name Register I2S_RFRn, field WFP[19:16] (RO) - * - * FIFO write pointer for receive data channel. - */ -/*@{*/ -#define BP_I2S_RFRn_WFP (16U) /*!< Bit position for I2S_RFRn_WFP. */ -#define BM_I2S_RFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */ -#define BS_I2S_RFRn_WFP (4U) /*!< Bit field size in bits for I2S_RFRn_WFP. */ - -/*! @brief Read current value of the I2S_RFRn_WFP field. */ -#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RMR - SAI Receive Mask Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RMR - SAI Receive Mask Register (RW) - * - * Reset value: 0x00000000U - * - * This register is double-buffered and updates: When RCSR[RE] is first set At - * the end of each frame This allows the masked words in each frame to change from - * frame to frame. - */ -typedef union _hw_i2s_rmr -{ - uint32_t U; - struct _hw_i2s_rmr_bitfields - { - uint32_t RWM : 16; /*!< [15:0] Receive Word Mask */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_i2s_rmr_t; - -/*! - * @name Constants and macros for entire I2S_RMR register - */ -/*@{*/ -#define HW_I2S_RMR_ADDR(x) ((x) + 0xE0U) - -#define HW_I2S_RMR(x) (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x)) -#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U) -#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v)) -#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) | (v))) -#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v))) -#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RMR bitfields - */ - -/*! - * @name Register I2S_RMR, field RWM[15:0] (RW) - * - * Configures whether the receive word is masked (received data ignored and not - * written to receive FIFO) for the corresponding word in the frame. - * - * Values: - * - 0 - Word N is enabled. - * - 1 - Word N is masked. - */ -/*@{*/ -#define BP_I2S_RMR_RWM (0U) /*!< Bit position for I2S_RMR_RWM. */ -#define BM_I2S_RMR_RWM (0x0000FFFFU) /*!< Bit mask for I2S_RMR_RWM. */ -#define BS_I2S_RMR_RWM (16U) /*!< Bit field size in bits for I2S_RMR_RWM. */ - -/*! @brief Read current value of the I2S_RMR_RWM field. */ -#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).B.RWM) - -/*! @brief Format value for bitfield I2S_RMR_RWM. */ -#define BF_I2S_RMR_RWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM) - -/*! @brief Set the RWM field to a new value. */ -#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, (HW_I2S_RMR_RD(x) & ~BM_I2S_RMR_RWM) | BF_I2S_RMR_RWM(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_MCR - SAI MCLK Control Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_MCR - SAI MCLK Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MCLK Control Register (MCR) controls the clock source and direction of - * the audio master clock. - */ -typedef union _hw_i2s_mcr -{ - uint32_t U; - struct _hw_i2s_mcr_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t MICS : 2; /*!< [25:24] MCLK Input Clock Select */ - uint32_t RESERVED1 : 4; /*!< [29:26] */ - uint32_t MOE : 1; /*!< [30] MCLK Output Enable */ - uint32_t DUF : 1; /*!< [31] Divider Update Flag */ - } B; -} hw_i2s_mcr_t; - -/*! - * @name Constants and macros for entire I2S_MCR register - */ -/*@{*/ -#define HW_I2S_MCR_ADDR(x) ((x) + 0x100U) - -#define HW_I2S_MCR(x) (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x)) -#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U) -#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v)) -#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) | (v))) -#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v))) -#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_MCR bitfields - */ - -/*! - * @name Register I2S_MCR, field MICS[25:24] (RW) - * - * Selects the clock input to the MCLK divider. This field cannot be changed - * while the MCLK divider is enabled. See the chip configuration details for - * information about the connections to these inputs. - * - * Values: - * - 00 - MCLK divider input clock 0 selected. - * - 01 - MCLK divider input clock 1 selected. - * - 10 - MCLK divider input clock 2 selected. - * - 11 - MCLK divider input clock 3 selected. - */ -/*@{*/ -#define BP_I2S_MCR_MICS (24U) /*!< Bit position for I2S_MCR_MICS. */ -#define BM_I2S_MCR_MICS (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */ -#define BS_I2S_MCR_MICS (2U) /*!< Bit field size in bits for I2S_MCR_MICS. */ - -/*! @brief Read current value of the I2S_MCR_MICS field. */ -#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS) - -/*! @brief Format value for bitfield I2S_MCR_MICS. */ -#define BF_I2S_MCR_MICS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS) - -/*! @brief Set the MICS field to a new value. */ -#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v))) -/*@}*/ - -/*! - * @name Register I2S_MCR, field MOE[30] (RW) - * - * Enables the MCLK divider and configures the MCLK signal pin as an output. - * When software clears this field, it remains set until the MCLK divider is fully - * disabled. - * - * Values: - * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK - * divider. - * - 1 - MCLK signal pin is configured as an output from the MCLK divider and - * the MCLK divider is enabled. - */ -/*@{*/ -#define BP_I2S_MCR_MOE (30U) /*!< Bit position for I2S_MCR_MOE. */ -#define BM_I2S_MCR_MOE (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */ -#define BS_I2S_MCR_MOE (1U) /*!< Bit field size in bits for I2S_MCR_MOE. */ - -/*! @brief Read current value of the I2S_MCR_MOE field. */ -#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE)) - -/*! @brief Format value for bitfield I2S_MCR_MOE. */ -#define BF_I2S_MCR_MOE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE) - -/*! @brief Set the MOE field to a new value. */ -#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_MCR, field DUF[31] (RO) - * - * Provides the status of on-the-fly updates to the MCLK divider ratio. - * - * Values: - * - 0 - MCLK divider ratio is not being updated currently. - * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK - * divider ratio are blocked while this flag remains set. - */ -/*@{*/ -#define BP_I2S_MCR_DUF (31U) /*!< Bit position for I2S_MCR_DUF. */ -#define BM_I2S_MCR_DUF (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */ -#define BS_I2S_MCR_DUF (1U) /*!< Bit field size in bits for I2S_MCR_DUF. */ - -/*! @brief Read current value of the I2S_MCR_DUF field. */ -#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_MDR - SAI MCLK Divide Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW) - * - * Reset value: 0x00000000U - * - * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the - * MDR can be changed when the MCLK divider clock is enabled, additional writes - * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK - * divided clock is disabled do not set MCR[DUF]. - */ -typedef union _hw_i2s_mdr -{ - uint32_t U; - struct _hw_i2s_mdr_bitfields - { - uint32_t DIVIDE : 12; /*!< [11:0] MCLK Divide */ - uint32_t FRACT : 8; /*!< [19:12] MCLK Fraction */ - uint32_t RESERVED0 : 12; /*!< [31:20] */ - } B; -} hw_i2s_mdr_t; - -/*! - * @name Constants and macros for entire I2S_MDR register - */ -/*@{*/ -#define HW_I2S_MDR_ADDR(x) ((x) + 0x104U) - -#define HW_I2S_MDR(x) (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x)) -#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U) -#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v)) -#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) | (v))) -#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v))) -#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_MDR bitfields - */ - -/*! - * @name Register I2S_MDR, field DIVIDE[11:0] (RW) - * - * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + - * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the - * DIVIDE field. - */ -/*@{*/ -#define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */ -#define BM_I2S_MDR_DIVIDE (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */ -#define BS_I2S_MDR_DIVIDE (12U) /*!< Bit field size in bits for I2S_MDR_DIVIDE. */ - -/*! @brief Read current value of the I2S_MDR_DIVIDE field. */ -#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE) - -/*! @brief Format value for bitfield I2S_MDR_DIVIDE. */ -#define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE) - -/*! @brief Set the DIVIDE field to a new value. */ -#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v))) -/*@}*/ - -/*! - * @name Register I2S_MDR, field FRACT[19:12] (RW) - * - * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + - * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the - * DIVIDE field. - */ -/*@{*/ -#define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */ -#define BM_I2S_MDR_FRACT (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */ -#define BS_I2S_MDR_FRACT (8U) /*!< Bit field size in bits for I2S_MDR_FRACT. */ - -/*! @brief Read current value of the I2S_MDR_FRACT field. */ -#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT) - -/*! @brief Format value for bitfield I2S_MDR_FRACT. */ -#define BF_I2S_MDR_FRACT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT) - -/*! @brief Set the FRACT field to a new value. */ -#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v))) -/*@}*/ - -/******************************************************************************* - * hw_i2s_t - module struct - ******************************************************************************/ -/*! - * @brief All I2S module registers. - */ -#pragma pack(1) -typedef struct _hw_i2s -{ - __IO hw_i2s_tcsr_t TCSR; /*!< [0x0] SAI Transmit Control Register */ - __IO hw_i2s_tcr1_t TCR1; /*!< [0x4] SAI Transmit Configuration 1 Register */ - __IO hw_i2s_tcr2_t TCR2; /*!< [0x8] SAI Transmit Configuration 2 Register */ - __IO hw_i2s_tcr3_t TCR3; /*!< [0xC] SAI Transmit Configuration 3 Register */ - __IO hw_i2s_tcr4_t TCR4; /*!< [0x10] SAI Transmit Configuration 4 Register */ - __IO hw_i2s_tcr5_t TCR5; /*!< [0x14] SAI Transmit Configuration 5 Register */ - uint8_t _reserved0[8]; - __O hw_i2s_tdrn_t TDRn[1]; /*!< [0x20] SAI Transmit Data Register */ - uint8_t _reserved1[28]; - __I hw_i2s_tfrn_t TFRn[1]; /*!< [0x40] SAI Transmit FIFO Register */ - uint8_t _reserved2[28]; - __IO hw_i2s_tmr_t TMR; /*!< [0x60] SAI Transmit Mask Register */ - uint8_t _reserved3[28]; - __IO hw_i2s_rcsr_t RCSR; /*!< [0x80] SAI Receive Control Register */ - __IO hw_i2s_rcr1_t RCR1; /*!< [0x84] SAI Receive Configuration 1 Register */ - __IO hw_i2s_rcr2_t RCR2; /*!< [0x88] SAI Receive Configuration 2 Register */ - __IO hw_i2s_rcr3_t RCR3; /*!< [0x8C] SAI Receive Configuration 3 Register */ - __IO hw_i2s_rcr4_t RCR4; /*!< [0x90] SAI Receive Configuration 4 Register */ - __IO hw_i2s_rcr5_t RCR5; /*!< [0x94] SAI Receive Configuration 5 Register */ - uint8_t _reserved4[8]; - __I hw_i2s_rdrn_t RDRn[1]; /*!< [0xA0] SAI Receive Data Register */ - uint8_t _reserved5[28]; - __I hw_i2s_rfrn_t RFRn[1]; /*!< [0xC0] SAI Receive FIFO Register */ - uint8_t _reserved6[28]; - __IO hw_i2s_rmr_t RMR; /*!< [0xE0] SAI Receive Mask Register */ - uint8_t _reserved7[28]; - __IO hw_i2s_mcr_t MCR; /*!< [0x100] SAI MCLK Control Register */ - __IO hw_i2s_mdr_t MDR; /*!< [0x104] SAI MCLK Divide Register */ -} hw_i2s_t; -#pragma pack() - -/*! @brief Macro to access all I2S registers. */ -/*! @param x I2S module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_I2S(I2S0_BASE). */ -#define HW_I2S(x) (*(hw_i2s_t *)(x)) - -#endif /* __HW_I2S_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h deleted file mode 100644 index 2cba21397cd..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h +++ /dev/null @@ -1,1950 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_LLWU_REGISTERS_H__ -#define __HW_LLWU_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 LLWU - * - * Low leakage wakeup unit - * - * Registers defined in this header file: - * - HW_LLWU_PE1 - LLWU Pin Enable 1 register - * - HW_LLWU_PE2 - LLWU Pin Enable 2 register - * - HW_LLWU_PE3 - LLWU Pin Enable 3 register - * - HW_LLWU_PE4 - LLWU Pin Enable 4 register - * - HW_LLWU_ME - LLWU Module Enable register - * - HW_LLWU_F1 - LLWU Flag 1 register - * - HW_LLWU_F2 - LLWU Flag 2 register - * - HW_LLWU_F3 - LLWU Flag 3 register - * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register - * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register - * - * - hw_llwu_t - Struct containing all module registers. - */ - -#define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */ - -/******************************************************************************* - * HW_LLWU_PE1 - LLWU Pin Enable 1 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE1 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module - * (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe1 -{ - uint8_t U; - struct _hw_llwu_pe1_bitfields - { - uint8_t WUPE0 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */ - uint8_t WUPE1 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */ - uint8_t WUPE2 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */ - uint8_t WUPE3 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */ - } B; -} hw_llwu_pe1_t; - -/*! - * @name Constants and macros for entire LLWU_PE1 register - */ -/*@{*/ -#define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U) - -#define HW_LLWU_PE1(x) (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x)) -#define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U) -#define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v)) -#define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) | (v))) -#define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v))) -#define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE1 bitfields - */ - -/*! - * @name Register LLWU_PE1, field WUPE0[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE0 (0U) /*!< Bit position for LLWU_PE1_WUPE0. */ -#define BM_LLWU_PE1_WUPE0 (0x03U) /*!< Bit mask for LLWU_PE1_WUPE0. */ -#define BS_LLWU_PE1_WUPE0 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE0. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */ -#define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE0. */ -#define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0) - -/*! @brief Set the WUPE0 field to a new value. */ -#define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE1, field WUPE1[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE1 (2U) /*!< Bit position for LLWU_PE1_WUPE1. */ -#define BM_LLWU_PE1_WUPE1 (0x0CU) /*!< Bit mask for LLWU_PE1_WUPE1. */ -#define BS_LLWU_PE1_WUPE1 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE1. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */ -#define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE1. */ -#define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1) - -/*! @brief Set the WUPE1 field to a new value. */ -#define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE1, field WUPE2[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE2 (4U) /*!< Bit position for LLWU_PE1_WUPE2. */ -#define BM_LLWU_PE1_WUPE2 (0x30U) /*!< Bit mask for LLWU_PE1_WUPE2. */ -#define BS_LLWU_PE1_WUPE2 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE2. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */ -#define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE2. */ -#define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2) - -/*! @brief Set the WUPE2 field to a new value. */ -#define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE1, field WUPE3[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE3 (6U) /*!< Bit position for LLWU_PE1_WUPE3. */ -#define BM_LLWU_PE1_WUPE3 (0xC0U) /*!< Bit mask for LLWU_PE1_WUPE3. */ -#define BS_LLWU_PE1_WUPE3 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE3. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */ -#define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE3. */ -#define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3) - -/*! @brief Set the WUPE3 field to a new value. */ -#define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_PE2 - LLWU Pin Enable 2 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE2 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module - * (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe2 -{ - uint8_t U; - struct _hw_llwu_pe2_bitfields - { - uint8_t WUPE4 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */ - uint8_t WUPE5 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */ - uint8_t WUPE6 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */ - uint8_t WUPE7 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */ - } B; -} hw_llwu_pe2_t; - -/*! - * @name Constants and macros for entire LLWU_PE2 register - */ -/*@{*/ -#define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U) - -#define HW_LLWU_PE2(x) (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x)) -#define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U) -#define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v)) -#define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) | (v))) -#define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v))) -#define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE2 bitfields - */ - -/*! - * @name Register LLWU_PE2, field WUPE4[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE4 (0U) /*!< Bit position for LLWU_PE2_WUPE4. */ -#define BM_LLWU_PE2_WUPE4 (0x03U) /*!< Bit mask for LLWU_PE2_WUPE4. */ -#define BS_LLWU_PE2_WUPE4 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE4. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */ -#define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE4. */ -#define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4) - -/*! @brief Set the WUPE4 field to a new value. */ -#define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE2, field WUPE5[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE5 (2U) /*!< Bit position for LLWU_PE2_WUPE5. */ -#define BM_LLWU_PE2_WUPE5 (0x0CU) /*!< Bit mask for LLWU_PE2_WUPE5. */ -#define BS_LLWU_PE2_WUPE5 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE5. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */ -#define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE5. */ -#define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5) - -/*! @brief Set the WUPE5 field to a new value. */ -#define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE2, field WUPE6[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE6 (4U) /*!< Bit position for LLWU_PE2_WUPE6. */ -#define BM_LLWU_PE2_WUPE6 (0x30U) /*!< Bit mask for LLWU_PE2_WUPE6. */ -#define BS_LLWU_PE2_WUPE6 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE6. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */ -#define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE6. */ -#define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6) - -/*! @brief Set the WUPE6 field to a new value. */ -#define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE2, field WUPE7[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE7 (6U) /*!< Bit position for LLWU_PE2_WUPE7. */ -#define BM_LLWU_PE2_WUPE7 (0xC0U) /*!< Bit mask for LLWU_PE2_WUPE7. */ -#define BS_LLWU_PE2_WUPE7 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE7. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */ -#define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE7. */ -#define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7) - -/*! @brief Set the WUPE7 field to a new value. */ -#define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_PE3 - LLWU Pin Enable 3 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE3 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module - * (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe3 -{ - uint8_t U; - struct _hw_llwu_pe3_bitfields - { - uint8_t WUPE8 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */ - uint8_t WUPE9 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */ - uint8_t WUPE10 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */ - uint8_t WUPE11 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */ - } B; -} hw_llwu_pe3_t; - -/*! - * @name Constants and macros for entire LLWU_PE3 register - */ -/*@{*/ -#define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U) - -#define HW_LLWU_PE3(x) (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x)) -#define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U) -#define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v)) -#define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) | (v))) -#define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v))) -#define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE3 bitfields - */ - -/*! - * @name Register LLWU_PE3, field WUPE8[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE8 (0U) /*!< Bit position for LLWU_PE3_WUPE8. */ -#define BM_LLWU_PE3_WUPE8 (0x03U) /*!< Bit mask for LLWU_PE3_WUPE8. */ -#define BS_LLWU_PE3_WUPE8 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE8. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */ -#define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE8. */ -#define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8) - -/*! @brief Set the WUPE8 field to a new value. */ -#define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE3, field WUPE9[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE9 (2U) /*!< Bit position for LLWU_PE3_WUPE9. */ -#define BM_LLWU_PE3_WUPE9 (0x0CU) /*!< Bit mask for LLWU_PE3_WUPE9. */ -#define BS_LLWU_PE3_WUPE9 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE9. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */ -#define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE9. */ -#define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9) - -/*! @brief Set the WUPE9 field to a new value. */ -#define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE3, field WUPE10[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE10 (4U) /*!< Bit position for LLWU_PE3_WUPE10. */ -#define BM_LLWU_PE3_WUPE10 (0x30U) /*!< Bit mask for LLWU_PE3_WUPE10. */ -#define BS_LLWU_PE3_WUPE10 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE10. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */ -#define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE10. */ -#define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10) - -/*! @brief Set the WUPE10 field to a new value. */ -#define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE3, field WUPE11[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE11 (6U) /*!< Bit position for LLWU_PE3_WUPE11. */ -#define BM_LLWU_PE3_WUPE11 (0xC0U) /*!< Bit mask for LLWU_PE3_WUPE11. */ -#define BS_LLWU_PE3_WUPE11 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE11. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */ -#define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE11. */ -#define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11) - -/*! @brief Set the WUPE11 field to a new value. */ -#define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_PE4 - LLWU Pin Enable 4 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE4 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe4 -{ - uint8_t U; - struct _hw_llwu_pe4_bitfields - { - uint8_t WUPE12 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */ - uint8_t WUPE13 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */ - uint8_t WUPE14 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */ - uint8_t WUPE15 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */ - } B; -} hw_llwu_pe4_t; - -/*! - * @name Constants and macros for entire LLWU_PE4 register - */ -/*@{*/ -#define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U) - -#define HW_LLWU_PE4(x) (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x)) -#define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U) -#define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v)) -#define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) | (v))) -#define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v))) -#define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE4 bitfields - */ - -/*! - * @name Register LLWU_PE4, field WUPE12[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE12 (0U) /*!< Bit position for LLWU_PE4_WUPE12. */ -#define BM_LLWU_PE4_WUPE12 (0x03U) /*!< Bit mask for LLWU_PE4_WUPE12. */ -#define BS_LLWU_PE4_WUPE12 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE12. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */ -#define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE12. */ -#define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12) - -/*! @brief Set the WUPE12 field to a new value. */ -#define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE4, field WUPE13[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE13 (2U) /*!< Bit position for LLWU_PE4_WUPE13. */ -#define BM_LLWU_PE4_WUPE13 (0x0CU) /*!< Bit mask for LLWU_PE4_WUPE13. */ -#define BS_LLWU_PE4_WUPE13 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE13. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */ -#define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE13. */ -#define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13) - -/*! @brief Set the WUPE13 field to a new value. */ -#define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE4, field WUPE14[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE14 (4U) /*!< Bit position for LLWU_PE4_WUPE14. */ -#define BM_LLWU_PE4_WUPE14 (0x30U) /*!< Bit mask for LLWU_PE4_WUPE14. */ -#define BS_LLWU_PE4_WUPE14 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE14. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */ -#define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE14. */ -#define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14) - -/*! @brief Set the WUPE14 field to a new value. */ -#define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE4, field WUPE15[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE15 (6U) /*!< Bit position for LLWU_PE4_WUPE15. */ -#define BM_LLWU_PE4_WUPE15 (0xC0U) /*!< Bit mask for LLWU_PE4_WUPE15. */ -#define BS_LLWU_PE4_WUPE15 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE15. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */ -#define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE15. */ -#define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15) - -/*! @brief Set the WUPE15 field to a new value. */ -#define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_ME - LLWU Module Enable register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_ME - LLWU Module Enable register (RW) - * - * Reset value: 0x00U - * - * LLWU_ME contains the bits to enable the internal module flag as a wakeup - * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS - * and by reset types that trigger Chip Reset not VLLS. It is unaffected by - * reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The - * RCM implements many of the reset functions for the chip. See the chip's reset - * chapter for more information. details for more information. - */ -typedef union _hw_llwu_me -{ - uint8_t U; - struct _hw_llwu_me_bitfields - { - uint8_t WUME0 : 1; /*!< [0] Wakeup Module Enable For Module 0 */ - uint8_t WUME1 : 1; /*!< [1] Wakeup Module Enable for Module 1 */ - uint8_t WUME2 : 1; /*!< [2] Wakeup Module Enable For Module 2 */ - uint8_t WUME3 : 1; /*!< [3] Wakeup Module Enable For Module 3 */ - uint8_t WUME4 : 1; /*!< [4] Wakeup Module Enable For Module 4 */ - uint8_t WUME5 : 1; /*!< [5] Wakeup Module Enable For Module 5 */ - uint8_t WUME6 : 1; /*!< [6] Wakeup Module Enable For Module 6 */ - uint8_t WUME7 : 1; /*!< [7] Wakeup Module Enable For Module 7 */ - } B; -} hw_llwu_me_t; - -/*! - * @name Constants and macros for entire LLWU_ME register - */ -/*@{*/ -#define HW_LLWU_ME_ADDR(x) ((x) + 0x4U) - -#define HW_LLWU_ME(x) (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x)) -#define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U) -#define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v)) -#define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) | (v))) -#define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v))) -#define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_ME bitfields - */ - -/*! - * @name Register LLWU_ME, field WUME0[0] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME0 (0U) /*!< Bit position for LLWU_ME_WUME0. */ -#define BM_LLWU_ME_WUME0 (0x01U) /*!< Bit mask for LLWU_ME_WUME0. */ -#define BS_LLWU_ME_WUME0 (1U) /*!< Bit field size in bits for LLWU_ME_WUME0. */ - -/*! @brief Read current value of the LLWU_ME_WUME0 field. */ -#define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0)) - -/*! @brief Format value for bitfield LLWU_ME_WUME0. */ -#define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0) - -/*! @brief Set the WUME0 field to a new value. */ -#define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME1[1] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME1 (1U) /*!< Bit position for LLWU_ME_WUME1. */ -#define BM_LLWU_ME_WUME1 (0x02U) /*!< Bit mask for LLWU_ME_WUME1. */ -#define BS_LLWU_ME_WUME1 (1U) /*!< Bit field size in bits for LLWU_ME_WUME1. */ - -/*! @brief Read current value of the LLWU_ME_WUME1 field. */ -#define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1)) - -/*! @brief Format value for bitfield LLWU_ME_WUME1. */ -#define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1) - -/*! @brief Set the WUME1 field to a new value. */ -#define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME2[2] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME2 (2U) /*!< Bit position for LLWU_ME_WUME2. */ -#define BM_LLWU_ME_WUME2 (0x04U) /*!< Bit mask for LLWU_ME_WUME2. */ -#define BS_LLWU_ME_WUME2 (1U) /*!< Bit field size in bits for LLWU_ME_WUME2. */ - -/*! @brief Read current value of the LLWU_ME_WUME2 field. */ -#define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2)) - -/*! @brief Format value for bitfield LLWU_ME_WUME2. */ -#define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2) - -/*! @brief Set the WUME2 field to a new value. */ -#define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME3[3] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME3 (3U) /*!< Bit position for LLWU_ME_WUME3. */ -#define BM_LLWU_ME_WUME3 (0x08U) /*!< Bit mask for LLWU_ME_WUME3. */ -#define BS_LLWU_ME_WUME3 (1U) /*!< Bit field size in bits for LLWU_ME_WUME3. */ - -/*! @brief Read current value of the LLWU_ME_WUME3 field. */ -#define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3)) - -/*! @brief Format value for bitfield LLWU_ME_WUME3. */ -#define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3) - -/*! @brief Set the WUME3 field to a new value. */ -#define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME4[4] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME4 (4U) /*!< Bit position for LLWU_ME_WUME4. */ -#define BM_LLWU_ME_WUME4 (0x10U) /*!< Bit mask for LLWU_ME_WUME4. */ -#define BS_LLWU_ME_WUME4 (1U) /*!< Bit field size in bits for LLWU_ME_WUME4. */ - -/*! @brief Read current value of the LLWU_ME_WUME4 field. */ -#define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4)) - -/*! @brief Format value for bitfield LLWU_ME_WUME4. */ -#define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4) - -/*! @brief Set the WUME4 field to a new value. */ -#define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME5[5] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME5 (5U) /*!< Bit position for LLWU_ME_WUME5. */ -#define BM_LLWU_ME_WUME5 (0x20U) /*!< Bit mask for LLWU_ME_WUME5. */ -#define BS_LLWU_ME_WUME5 (1U) /*!< Bit field size in bits for LLWU_ME_WUME5. */ - -/*! @brief Read current value of the LLWU_ME_WUME5 field. */ -#define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5)) - -/*! @brief Format value for bitfield LLWU_ME_WUME5. */ -#define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5) - -/*! @brief Set the WUME5 field to a new value. */ -#define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME6[6] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME6 (6U) /*!< Bit position for LLWU_ME_WUME6. */ -#define BM_LLWU_ME_WUME6 (0x40U) /*!< Bit mask for LLWU_ME_WUME6. */ -#define BS_LLWU_ME_WUME6 (1U) /*!< Bit field size in bits for LLWU_ME_WUME6. */ - -/*! @brief Read current value of the LLWU_ME_WUME6 field. */ -#define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6)) - -/*! @brief Format value for bitfield LLWU_ME_WUME6. */ -#define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6) - -/*! @brief Set the WUME6 field to a new value. */ -#define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME7[7] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME7 (7U) /*!< Bit position for LLWU_ME_WUME7. */ -#define BM_LLWU_ME_WUME7 (0x80U) /*!< Bit mask for LLWU_ME_WUME7. */ -#define BS_LLWU_ME_WUME7 (1U) /*!< Bit field size in bits for LLWU_ME_WUME7. */ - -/*! @brief Read current value of the LLWU_ME_WUME7 field. */ -#define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7)) - -/*! @brief Format value for bitfield LLWU_ME_WUME7. */ -#define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7) - -/*! @brief Set the WUME7 field to a new value. */ -#define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_F1 - LLWU Flag 1 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C) - * - * Reset value: 0x00U - * - * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the - * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU - * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The - * external wakeup flags are read-only and clearing a flag is accomplished by a write - * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will - * remain set if the associated WUPEx bit is cleared. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_f1 -{ - uint8_t U; - struct _hw_llwu_f1_bitfields - { - uint8_t WUF0 : 1; /*!< [0] Wakeup Flag For LLWU_P0 */ - uint8_t WUF1 : 1; /*!< [1] Wakeup Flag For LLWU_P1 */ - uint8_t WUF2 : 1; /*!< [2] Wakeup Flag For LLWU_P2 */ - uint8_t WUF3 : 1; /*!< [3] Wakeup Flag For LLWU_P3 */ - uint8_t WUF4 : 1; /*!< [4] Wakeup Flag For LLWU_P4 */ - uint8_t WUF5 : 1; /*!< [5] Wakeup Flag For LLWU_P5 */ - uint8_t WUF6 : 1; /*!< [6] Wakeup Flag For LLWU_P6 */ - uint8_t WUF7 : 1; /*!< [7] Wakeup Flag For LLWU_P7 */ - } B; -} hw_llwu_f1_t; - -/*! - * @name Constants and macros for entire LLWU_F1 register - */ -/*@{*/ -#define HW_LLWU_F1_ADDR(x) ((x) + 0x5U) - -#define HW_LLWU_F1(x) (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x)) -#define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U) -#define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v)) -#define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) | (v))) -#define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v))) -#define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_F1 bitfields - */ - -/*! - * @name Register LLWU_F1, field WUF0[0] (W1C) - * - * Indicates that an enabled external wake-up pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF0. - * - * Values: - * - 0 - LLWU_P0 input was not a wakeup source - * - 1 - LLWU_P0 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF0 (0U) /*!< Bit position for LLWU_F1_WUF0. */ -#define BM_LLWU_F1_WUF0 (0x01U) /*!< Bit mask for LLWU_F1_WUF0. */ -#define BS_LLWU_F1_WUF0 (1U) /*!< Bit field size in bits for LLWU_F1_WUF0. */ - -/*! @brief Read current value of the LLWU_F1_WUF0 field. */ -#define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0)) - -/*! @brief Format value for bitfield LLWU_F1_WUF0. */ -#define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0) - -/*! @brief Set the WUF0 field to a new value. */ -#define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF1[1] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF1. - * - * Values: - * - 0 - LLWU_P1 input was not a wakeup source - * - 1 - LLWU_P1 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF1 (1U) /*!< Bit position for LLWU_F1_WUF1. */ -#define BM_LLWU_F1_WUF1 (0x02U) /*!< Bit mask for LLWU_F1_WUF1. */ -#define BS_LLWU_F1_WUF1 (1U) /*!< Bit field size in bits for LLWU_F1_WUF1. */ - -/*! @brief Read current value of the LLWU_F1_WUF1 field. */ -#define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1)) - -/*! @brief Format value for bitfield LLWU_F1_WUF1. */ -#define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1) - -/*! @brief Set the WUF1 field to a new value. */ -#define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF2[2] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF2. - * - * Values: - * - 0 - LLWU_P2 input was not a wakeup source - * - 1 - LLWU_P2 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF2 (2U) /*!< Bit position for LLWU_F1_WUF2. */ -#define BM_LLWU_F1_WUF2 (0x04U) /*!< Bit mask for LLWU_F1_WUF2. */ -#define BS_LLWU_F1_WUF2 (1U) /*!< Bit field size in bits for LLWU_F1_WUF2. */ - -/*! @brief Read current value of the LLWU_F1_WUF2 field. */ -#define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2)) - -/*! @brief Format value for bitfield LLWU_F1_WUF2. */ -#define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2) - -/*! @brief Set the WUF2 field to a new value. */ -#define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF3[3] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF3. - * - * Values: - * - 0 - LLWU_P3 input was not a wake-up source - * - 1 - LLWU_P3 input was a wake-up source - */ -/*@{*/ -#define BP_LLWU_F1_WUF3 (3U) /*!< Bit position for LLWU_F1_WUF3. */ -#define BM_LLWU_F1_WUF3 (0x08U) /*!< Bit mask for LLWU_F1_WUF3. */ -#define BS_LLWU_F1_WUF3 (1U) /*!< Bit field size in bits for LLWU_F1_WUF3. */ - -/*! @brief Read current value of the LLWU_F1_WUF3 field. */ -#define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3)) - -/*! @brief Format value for bitfield LLWU_F1_WUF3. */ -#define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3) - -/*! @brief Set the WUF3 field to a new value. */ -#define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF4[4] (W1C) - * - * Indicates that an enabled external wake-up pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF4. - * - * Values: - * - 0 - LLWU_P4 input was not a wakeup source - * - 1 - LLWU_P4 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF4 (4U) /*!< Bit position for LLWU_F1_WUF4. */ -#define BM_LLWU_F1_WUF4 (0x10U) /*!< Bit mask for LLWU_F1_WUF4. */ -#define BS_LLWU_F1_WUF4 (1U) /*!< Bit field size in bits for LLWU_F1_WUF4. */ - -/*! @brief Read current value of the LLWU_F1_WUF4 field. */ -#define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4)) - -/*! @brief Format value for bitfield LLWU_F1_WUF4. */ -#define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4) - -/*! @brief Set the WUF4 field to a new value. */ -#define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF5[5] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF5. - * - * Values: - * - 0 - LLWU_P5 input was not a wakeup source - * - 1 - LLWU_P5 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF5 (5U) /*!< Bit position for LLWU_F1_WUF5. */ -#define BM_LLWU_F1_WUF5 (0x20U) /*!< Bit mask for LLWU_F1_WUF5. */ -#define BS_LLWU_F1_WUF5 (1U) /*!< Bit field size in bits for LLWU_F1_WUF5. */ - -/*! @brief Read current value of the LLWU_F1_WUF5 field. */ -#define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5)) - -/*! @brief Format value for bitfield LLWU_F1_WUF5. */ -#define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5) - -/*! @brief Set the WUF5 field to a new value. */ -#define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF6[6] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF6. - * - * Values: - * - 0 - LLWU_P6 input was not a wakeup source - * - 1 - LLWU_P6 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF6 (6U) /*!< Bit position for LLWU_F1_WUF6. */ -#define BM_LLWU_F1_WUF6 (0x40U) /*!< Bit mask for LLWU_F1_WUF6. */ -#define BS_LLWU_F1_WUF6 (1U) /*!< Bit field size in bits for LLWU_F1_WUF6. */ - -/*! @brief Read current value of the LLWU_F1_WUF6 field. */ -#define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6)) - -/*! @brief Format value for bitfield LLWU_F1_WUF6. */ -#define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6) - -/*! @brief Set the WUF6 field to a new value. */ -#define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF7[7] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF7. - * - * Values: - * - 0 - LLWU_P7 input was not a wakeup source - * - 1 - LLWU_P7 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF7 (7U) /*!< Bit position for LLWU_F1_WUF7. */ -#define BM_LLWU_F1_WUF7 (0x80U) /*!< Bit mask for LLWU_F1_WUF7. */ -#define BS_LLWU_F1_WUF7 (1U) /*!< Bit field size in bits for LLWU_F1_WUF7. */ - -/*! @brief Read current value of the LLWU_F1_WUF7 field. */ -#define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7)) - -/*! @brief Format value for bitfield LLWU_F1_WUF7. */ -#define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7) - -/*! @brief Set the WUF7 field to a new value. */ -#define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_F2 - LLWU Flag 2 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C) - * - * Reset value: 0x00U - * - * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the - * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU - * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The - * external wakeup flags are read-only and clearing a flag is accomplished by a write - * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will - * remain set if the associated WUPEx bit is cleared. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_f2 -{ - uint8_t U; - struct _hw_llwu_f2_bitfields - { - uint8_t WUF8 : 1; /*!< [0] Wakeup Flag For LLWU_P8 */ - uint8_t WUF9 : 1; /*!< [1] Wakeup Flag For LLWU_P9 */ - uint8_t WUF10 : 1; /*!< [2] Wakeup Flag For LLWU_P10 */ - uint8_t WUF11 : 1; /*!< [3] Wakeup Flag For LLWU_P11 */ - uint8_t WUF12 : 1; /*!< [4] Wakeup Flag For LLWU_P12 */ - uint8_t WUF13 : 1; /*!< [5] Wakeup Flag For LLWU_P13 */ - uint8_t WUF14 : 1; /*!< [6] Wakeup Flag For LLWU_P14 */ - uint8_t WUF15 : 1; /*!< [7] Wakeup Flag For LLWU_P15 */ - } B; -} hw_llwu_f2_t; - -/*! - * @name Constants and macros for entire LLWU_F2 register - */ -/*@{*/ -#define HW_LLWU_F2_ADDR(x) ((x) + 0x6U) - -#define HW_LLWU_F2(x) (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x)) -#define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U) -#define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v)) -#define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) | (v))) -#define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v))) -#define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_F2 bitfields - */ - -/*! - * @name Register LLWU_F2, field WUF8[0] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF8. - * - * Values: - * - 0 - LLWU_P8 input was not a wakeup source - * - 1 - LLWU_P8 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF8 (0U) /*!< Bit position for LLWU_F2_WUF8. */ -#define BM_LLWU_F2_WUF8 (0x01U) /*!< Bit mask for LLWU_F2_WUF8. */ -#define BS_LLWU_F2_WUF8 (1U) /*!< Bit field size in bits for LLWU_F2_WUF8. */ - -/*! @brief Read current value of the LLWU_F2_WUF8 field. */ -#define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8)) - -/*! @brief Format value for bitfield LLWU_F2_WUF8. */ -#define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8) - -/*! @brief Set the WUF8 field to a new value. */ -#define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF9[1] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF9. - * - * Values: - * - 0 - LLWU_P9 input was not a wakeup source - * - 1 - LLWU_P9 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF9 (1U) /*!< Bit position for LLWU_F2_WUF9. */ -#define BM_LLWU_F2_WUF9 (0x02U) /*!< Bit mask for LLWU_F2_WUF9. */ -#define BS_LLWU_F2_WUF9 (1U) /*!< Bit field size in bits for LLWU_F2_WUF9. */ - -/*! @brief Read current value of the LLWU_F2_WUF9 field. */ -#define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9)) - -/*! @brief Format value for bitfield LLWU_F2_WUF9. */ -#define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9) - -/*! @brief Set the WUF9 field to a new value. */ -#define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF10[2] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF10. - * - * Values: - * - 0 - LLWU_P10 input was not a wakeup source - * - 1 - LLWU_P10 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF10 (2U) /*!< Bit position for LLWU_F2_WUF10. */ -#define BM_LLWU_F2_WUF10 (0x04U) /*!< Bit mask for LLWU_F2_WUF10. */ -#define BS_LLWU_F2_WUF10 (1U) /*!< Bit field size in bits for LLWU_F2_WUF10. */ - -/*! @brief Read current value of the LLWU_F2_WUF10 field. */ -#define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10)) - -/*! @brief Format value for bitfield LLWU_F2_WUF10. */ -#define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10) - -/*! @brief Set the WUF10 field to a new value. */ -#define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF11[3] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF11. - * - * Values: - * - 0 - LLWU_P11 input was not a wakeup source - * - 1 - LLWU_P11 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF11 (3U) /*!< Bit position for LLWU_F2_WUF11. */ -#define BM_LLWU_F2_WUF11 (0x08U) /*!< Bit mask for LLWU_F2_WUF11. */ -#define BS_LLWU_F2_WUF11 (1U) /*!< Bit field size in bits for LLWU_F2_WUF11. */ - -/*! @brief Read current value of the LLWU_F2_WUF11 field. */ -#define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11)) - -/*! @brief Format value for bitfield LLWU_F2_WUF11. */ -#define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11) - -/*! @brief Set the WUF11 field to a new value. */ -#define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF12[4] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF12. - * - * Values: - * - 0 - LLWU_P12 input was not a wakeup source - * - 1 - LLWU_P12 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF12 (4U) /*!< Bit position for LLWU_F2_WUF12. */ -#define BM_LLWU_F2_WUF12 (0x10U) /*!< Bit mask for LLWU_F2_WUF12. */ -#define BS_LLWU_F2_WUF12 (1U) /*!< Bit field size in bits for LLWU_F2_WUF12. */ - -/*! @brief Read current value of the LLWU_F2_WUF12 field. */ -#define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12)) - -/*! @brief Format value for bitfield LLWU_F2_WUF12. */ -#define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12) - -/*! @brief Set the WUF12 field to a new value. */ -#define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF13[5] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF13. - * - * Values: - * - 0 - LLWU_P13 input was not a wakeup source - * - 1 - LLWU_P13 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF13 (5U) /*!< Bit position for LLWU_F2_WUF13. */ -#define BM_LLWU_F2_WUF13 (0x20U) /*!< Bit mask for LLWU_F2_WUF13. */ -#define BS_LLWU_F2_WUF13 (1U) /*!< Bit field size in bits for LLWU_F2_WUF13. */ - -/*! @brief Read current value of the LLWU_F2_WUF13 field. */ -#define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13)) - -/*! @brief Format value for bitfield LLWU_F2_WUF13. */ -#define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13) - -/*! @brief Set the WUF13 field to a new value. */ -#define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF14[6] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF14. - * - * Values: - * - 0 - LLWU_P14 input was not a wakeup source - * - 1 - LLWU_P14 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF14 (6U) /*!< Bit position for LLWU_F2_WUF14. */ -#define BM_LLWU_F2_WUF14 (0x40U) /*!< Bit mask for LLWU_F2_WUF14. */ -#define BS_LLWU_F2_WUF14 (1U) /*!< Bit field size in bits for LLWU_F2_WUF14. */ - -/*! @brief Read current value of the LLWU_F2_WUF14 field. */ -#define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14)) - -/*! @brief Format value for bitfield LLWU_F2_WUF14. */ -#define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14) - -/*! @brief Set the WUF14 field to a new value. */ -#define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF15[7] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF15. - * - * Values: - * - 0 - LLWU_P15 input was not a wakeup source - * - 1 - LLWU_P15 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF15 (7U) /*!< Bit position for LLWU_F2_WUF15. */ -#define BM_LLWU_F2_WUF15 (0x80U) /*!< Bit mask for LLWU_F2_WUF15. */ -#define BS_LLWU_F2_WUF15 (1U) /*!< Bit field size in bits for LLWU_F2_WUF15. */ - -/*! @brief Read current value of the LLWU_F2_WUF15 field. */ -#define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15)) - -/*! @brief Format value for bitfield LLWU_F2_WUF15. */ -#define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15) - -/*! @brief Set the WUF15 field to a new value. */ -#define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_F3 - LLWU Flag 3 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO) - * - * Reset value: 0x00U - * - * LLWU_F3 contains the wakeup flags indicating which internal wakeup source - * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the - * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. - * For internal peripherals that are capable of running in a low-leakage power - * mode, such as a real time clock module or CMP module, the flag from the - * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared - * in the peripheral instead of writing a 1 to the MWUFx bit. This register is - * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not - * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See - * the IntroductionInformation found here describes the registers of the Reset - * Control Module (RCM). The RCM implements many of the reset functions for the - * chip. See the chip's reset chapter for more information. details for more - * information. - */ -typedef union _hw_llwu_f3 -{ - uint8_t U; - struct _hw_llwu_f3_bitfields - { - uint8_t MWUF0 : 1; /*!< [0] Wakeup flag For module 0 */ - uint8_t MWUF1 : 1; /*!< [1] Wakeup flag For module 1 */ - uint8_t MWUF2 : 1; /*!< [2] Wakeup flag For module 2 */ - uint8_t MWUF3 : 1; /*!< [3] Wakeup flag For module 3 */ - uint8_t MWUF4 : 1; /*!< [4] Wakeup flag For module 4 */ - uint8_t MWUF5 : 1; /*!< [5] Wakeup flag For module 5 */ - uint8_t MWUF6 : 1; /*!< [6] Wakeup flag For module 6 */ - uint8_t MWUF7 : 1; /*!< [7] Wakeup flag For module 7 */ - } B; -} hw_llwu_f3_t; - -/*! - * @name Constants and macros for entire LLWU_F3 register - */ -/*@{*/ -#define HW_LLWU_F3_ADDR(x) ((x) + 0x7U) - -#define HW_LLWU_F3(x) (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x)) -#define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U) -/*@}*/ - -/* - * Constants & macros for individual LLWU_F3 bitfields - */ - -/*! - * @name Register LLWU_F3, field MWUF0[0] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 0 input was not a wakeup source - * - 1 - Module 0 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF0 (0U) /*!< Bit position for LLWU_F3_MWUF0. */ -#define BM_LLWU_F3_MWUF0 (0x01U) /*!< Bit mask for LLWU_F3_MWUF0. */ -#define BS_LLWU_F3_MWUF0 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF0. */ - -/*! @brief Read current value of the LLWU_F3_MWUF0 field. */ -#define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF1[1] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 1 input was not a wakeup source - * - 1 - Module 1 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF1 (1U) /*!< Bit position for LLWU_F3_MWUF1. */ -#define BM_LLWU_F3_MWUF1 (0x02U) /*!< Bit mask for LLWU_F3_MWUF1. */ -#define BS_LLWU_F3_MWUF1 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF1. */ - -/*! @brief Read current value of the LLWU_F3_MWUF1 field. */ -#define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF2[2] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 2 input was not a wakeup source - * - 1 - Module 2 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF2 (2U) /*!< Bit position for LLWU_F3_MWUF2. */ -#define BM_LLWU_F3_MWUF2 (0x04U) /*!< Bit mask for LLWU_F3_MWUF2. */ -#define BS_LLWU_F3_MWUF2 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF2. */ - -/*! @brief Read current value of the LLWU_F3_MWUF2 field. */ -#define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF3[3] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 3 input was not a wakeup source - * - 1 - Module 3 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF3 (3U) /*!< Bit position for LLWU_F3_MWUF3. */ -#define BM_LLWU_F3_MWUF3 (0x08U) /*!< Bit mask for LLWU_F3_MWUF3. */ -#define BS_LLWU_F3_MWUF3 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF3. */ - -/*! @brief Read current value of the LLWU_F3_MWUF3 field. */ -#define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF4[4] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 4 input was not a wakeup source - * - 1 - Module 4 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF4 (4U) /*!< Bit position for LLWU_F3_MWUF4. */ -#define BM_LLWU_F3_MWUF4 (0x10U) /*!< Bit mask for LLWU_F3_MWUF4. */ -#define BS_LLWU_F3_MWUF4 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF4. */ - -/*! @brief Read current value of the LLWU_F3_MWUF4 field. */ -#define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF5[5] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 5 input was not a wakeup source - * - 1 - Module 5 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF5 (5U) /*!< Bit position for LLWU_F3_MWUF5. */ -#define BM_LLWU_F3_MWUF5 (0x20U) /*!< Bit mask for LLWU_F3_MWUF5. */ -#define BS_LLWU_F3_MWUF5 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF5. */ - -/*! @brief Read current value of the LLWU_F3_MWUF5 field. */ -#define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF6[6] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 6 input was not a wakeup source - * - 1 - Module 6 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF6 (6U) /*!< Bit position for LLWU_F3_MWUF6. */ -#define BM_LLWU_F3_MWUF6 (0x40U) /*!< Bit mask for LLWU_F3_MWUF6. */ -#define BS_LLWU_F3_MWUF6 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF6. */ - -/*! @brief Read current value of the LLWU_F3_MWUF6 field. */ -#define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF7[7] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 7 input was not a wakeup source - * - 1 - Module 7 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF7 (7U) /*!< Bit position for LLWU_F3_MWUF7. */ -#define BM_LLWU_F3_MWUF7 (0x80U) /*!< Bit mask for LLWU_F3_MWUF7. */ -#define BS_LLWU_F3_MWUF7 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF7. */ - -/*! @brief Read current value of the LLWU_F3_MWUF7 field. */ -#define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_FILT1 - LLWU Pin Filter 1 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW) - * - * Reset value: 0x00U - * - * LLWU_FILT1 is a control and status register that is used to enable/disable - * the digital filter 1 features for an external pin. This register is reset on - * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See - * the chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_filt1 -{ - uint8_t U; - struct _hw_llwu_filt1_bitfields - { - uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */ - uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */ - } B; -} hw_llwu_filt1_t; - -/*! - * @name Constants and macros for entire LLWU_FILT1 register - */ -/*@{*/ -#define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U) - -#define HW_LLWU_FILT1(x) (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x)) -#define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U) -#define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v)) -#define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) | (v))) -#define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v))) -#define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_FILT1 bitfields - */ - -/*! - * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW) - * - * Selects 1 out of the 16 wakeup pins to be muxed into the filter. - * - * Values: - * - 0000 - Select LLWU_P0 for filter - * - 1111 - Select LLWU_P15 for filter - */ -/*@{*/ -#define BP_LLWU_FILT1_FILTSEL (0U) /*!< Bit position for LLWU_FILT1_FILTSEL. */ -#define BM_LLWU_FILT1_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT1_FILTSEL. */ -#define BS_LLWU_FILT1_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */ - -/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */ -#define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL) - -/*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */ -#define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL) - -/*! @brief Set the FILTSEL field to a new value. */ -#define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT1, field FILTE[6:5] (RW) - * - * Controls the digital filter options for the external pin detect. - * - * Values: - * - 00 - Filter disabled - * - 01 - Filter posedge detect enabled - * - 10 - Filter negedge detect enabled - * - 11 - Filter any edge detect enabled - */ -/*@{*/ -#define BP_LLWU_FILT1_FILTE (5U) /*!< Bit position for LLWU_FILT1_FILTE. */ -#define BM_LLWU_FILT1_FILTE (0x60U) /*!< Bit mask for LLWU_FILT1_FILTE. */ -#define BS_LLWU_FILT1_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT1_FILTE. */ - -/*! @brief Read current value of the LLWU_FILT1_FILTE field. */ -#define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE) - -/*! @brief Format value for bitfield LLWU_FILT1_FILTE. */ -#define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE) - -/*! @brief Set the FILTE field to a new value. */ -#define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT1, field FILTF[7] (W1C) - * - * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a - * source of exiting a low-leakage power mode. To clear the flag write a one to - * FILTF. - * - * Values: - * - 0 - Pin Filter 1 was not a wakeup source - * - 1 - Pin Filter 1 was a wakeup source - */ -/*@{*/ -#define BP_LLWU_FILT1_FILTF (7U) /*!< Bit position for LLWU_FILT1_FILTF. */ -#define BM_LLWU_FILT1_FILTF (0x80U) /*!< Bit mask for LLWU_FILT1_FILTF. */ -#define BS_LLWU_FILT1_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT1_FILTF. */ - -/*! @brief Read current value of the LLWU_FILT1_FILTF field. */ -#define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF)) - -/*! @brief Format value for bitfield LLWU_FILT1_FILTF. */ -#define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF) - -/*! @brief Set the FILTF field to a new value. */ -#define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_FILT2 - LLWU Pin Filter 2 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW) - * - * Reset value: 0x00U - * - * LLWU_FILT2 is a control and status register that is used to enable/disable - * the digital filter 2 features for an external pin. This register is reset on - * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See - * the chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_filt2 -{ - uint8_t U; - struct _hw_llwu_filt2_bitfields - { - uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */ - uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */ - } B; -} hw_llwu_filt2_t; - -/*! - * @name Constants and macros for entire LLWU_FILT2 register - */ -/*@{*/ -#define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U) - -#define HW_LLWU_FILT2(x) (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x)) -#define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U) -#define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v)) -#define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) | (v))) -#define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v))) -#define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_FILT2 bitfields - */ - -/*! - * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW) - * - * Selects 1 out of the 16 wakeup pins to be muxed into the filter. - * - * Values: - * - 0000 - Select LLWU_P0 for filter - * - 1111 - Select LLWU_P15 for filter - */ -/*@{*/ -#define BP_LLWU_FILT2_FILTSEL (0U) /*!< Bit position for LLWU_FILT2_FILTSEL. */ -#define BM_LLWU_FILT2_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT2_FILTSEL. */ -#define BS_LLWU_FILT2_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */ - -/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */ -#define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL) - -/*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */ -#define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL) - -/*! @brief Set the FILTSEL field to a new value. */ -#define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT2, field FILTE[6:5] (RW) - * - * Controls the digital filter options for the external pin detect. - * - * Values: - * - 00 - Filter disabled - * - 01 - Filter posedge detect enabled - * - 10 - Filter negedge detect enabled - * - 11 - Filter any edge detect enabled - */ -/*@{*/ -#define BP_LLWU_FILT2_FILTE (5U) /*!< Bit position for LLWU_FILT2_FILTE. */ -#define BM_LLWU_FILT2_FILTE (0x60U) /*!< Bit mask for LLWU_FILT2_FILTE. */ -#define BS_LLWU_FILT2_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT2_FILTE. */ - -/*! @brief Read current value of the LLWU_FILT2_FILTE field. */ -#define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE) - -/*! @brief Format value for bitfield LLWU_FILT2_FILTE. */ -#define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE) - -/*! @brief Set the FILTE field to a new value. */ -#define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT2, field FILTF[7] (W1C) - * - * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a - * source of exiting a low-leakage power mode. To clear the flag write a one to - * FILTF. - * - * Values: - * - 0 - Pin Filter 2 was not a wakeup source - * - 1 - Pin Filter 2 was a wakeup source - */ -/*@{*/ -#define BP_LLWU_FILT2_FILTF (7U) /*!< Bit position for LLWU_FILT2_FILTF. */ -#define BM_LLWU_FILT2_FILTF (0x80U) /*!< Bit mask for LLWU_FILT2_FILTF. */ -#define BS_LLWU_FILT2_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT2_FILTF. */ - -/*! @brief Read current value of the LLWU_FILT2_FILTF field. */ -#define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF)) - -/*! @brief Format value for bitfield LLWU_FILT2_FILTF. */ -#define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF) - -/*! @brief Set the FILTF field to a new value. */ -#define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_llwu_t - module struct - ******************************************************************************/ -/*! - * @brief All LLWU module registers. - */ -#pragma pack(1) -typedef struct _hw_llwu -{ - __IO hw_llwu_pe1_t PE1; /*!< [0x0] LLWU Pin Enable 1 register */ - __IO hw_llwu_pe2_t PE2; /*!< [0x1] LLWU Pin Enable 2 register */ - __IO hw_llwu_pe3_t PE3; /*!< [0x2] LLWU Pin Enable 3 register */ - __IO hw_llwu_pe4_t PE4; /*!< [0x3] LLWU Pin Enable 4 register */ - __IO hw_llwu_me_t ME; /*!< [0x4] LLWU Module Enable register */ - __IO hw_llwu_f1_t F1; /*!< [0x5] LLWU Flag 1 register */ - __IO hw_llwu_f2_t F2; /*!< [0x6] LLWU Flag 2 register */ - __I hw_llwu_f3_t F3; /*!< [0x7] LLWU Flag 3 register */ - __IO hw_llwu_filt1_t FILT1; /*!< [0x8] LLWU Pin Filter 1 register */ - __IO hw_llwu_filt2_t FILT2; /*!< [0x9] LLWU Pin Filter 2 register */ -} hw_llwu_t; -#pragma pack() - -/*! @brief Macro to access all LLWU registers. */ -/*! @param x LLWU module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_LLWU(LLWU_BASE). */ -#define HW_LLWU(x) (*(hw_llwu_t *)(x)) - -#endif /* __HW_LLWU_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h deleted file mode 100644 index 4a12976cbaa..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h +++ /dev/null @@ -1,614 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_LPTMR_REGISTERS_H__ -#define __HW_LPTMR_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 LPTMR - * - * Low Power Timer - * - * Registers defined in this header file: - * - HW_LPTMR_CSR - Low Power Timer Control Status Register - * - HW_LPTMR_PSR - Low Power Timer Prescale Register - * - HW_LPTMR_CMR - Low Power Timer Compare Register - * - HW_LPTMR_CNR - Low Power Timer Counter Register - * - * - hw_lptmr_t - Struct containing all module registers. - */ - -#define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */ - -/******************************************************************************* - * HW_LPTMR_CSR - Low Power Timer Control Status Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_csr -{ - uint32_t U; - struct _hw_lptmr_csr_bitfields - { - uint32_t TEN : 1; /*!< [0] Timer Enable */ - uint32_t TMS : 1; /*!< [1] Timer Mode Select */ - uint32_t TFC : 1; /*!< [2] Timer Free-Running Counter */ - uint32_t TPP : 1; /*!< [3] Timer Pin Polarity */ - uint32_t TPS : 2; /*!< [5:4] Timer Pin Select */ - uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */ - uint32_t TCF : 1; /*!< [7] Timer Compare Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_lptmr_csr_t; - -/*! - * @name Constants and macros for entire LPTMR_CSR register - */ -/*@{*/ -#define HW_LPTMR_CSR_ADDR(x) ((x) + 0x0U) - -#define HW_LPTMR_CSR(x) (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x)) -#define HW_LPTMR_CSR_RD(x) (HW_LPTMR_CSR(x).U) -#define HW_LPTMR_CSR_WR(x, v) (HW_LPTMR_CSR(x).U = (v)) -#define HW_LPTMR_CSR_SET(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) | (v))) -#define HW_LPTMR_CSR_CLR(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v))) -#define HW_LPTMR_CSR_TOG(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_CSR bitfields - */ - -/*! - * @name Register LPTMR_CSR, field TEN[0] (RW) - * - * When TEN is clear, it resets the LPTMR internal logic, including the CNR and - * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field, - * CSR[5:1] must not be altered. - * - * Values: - * - 0 - LPTMR is disabled and internal logic is reset. - * - 1 - LPTMR is enabled. - */ -/*@{*/ -#define BP_LPTMR_CSR_TEN (0U) /*!< Bit position for LPTMR_CSR_TEN. */ -#define BM_LPTMR_CSR_TEN (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */ -#define BS_LPTMR_CSR_TEN (1U) /*!< Bit field size in bits for LPTMR_CSR_TEN. */ - -/*! @brief Read current value of the LPTMR_CSR_TEN field. */ -#define BR_LPTMR_CSR_TEN(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN)) - -/*! @brief Format value for bitfield LPTMR_CSR_TEN. */ -#define BF_LPTMR_CSR_TEN(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN) - -/*! @brief Set the TEN field to a new value. */ -#define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TMS[1] (RW) - * - * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is - * disabled. - * - * Values: - * - 0 - Time Counter mode. - * - 1 - Pulse Counter mode. - */ -/*@{*/ -#define BP_LPTMR_CSR_TMS (1U) /*!< Bit position for LPTMR_CSR_TMS. */ -#define BM_LPTMR_CSR_TMS (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */ -#define BS_LPTMR_CSR_TMS (1U) /*!< Bit field size in bits for LPTMR_CSR_TMS. */ - -/*! @brief Read current value of the LPTMR_CSR_TMS field. */ -#define BR_LPTMR_CSR_TMS(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS)) - -/*! @brief Format value for bitfield LPTMR_CSR_TMS. */ -#define BF_LPTMR_CSR_TMS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS) - -/*! @brief Set the TMS field to a new value. */ -#define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TFC[2] (RW) - * - * When clear, TFC configures the CNR to reset whenever TCF is set. When set, - * TFC configures the CNR to reset on overflow. TFC must be altered only when the - * LPTMR is disabled. - * - * Values: - * - 0 - CNR is reset whenever TCF is set. - * - 1 - CNR is reset on overflow. - */ -/*@{*/ -#define BP_LPTMR_CSR_TFC (2U) /*!< Bit position for LPTMR_CSR_TFC. */ -#define BM_LPTMR_CSR_TFC (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */ -#define BS_LPTMR_CSR_TFC (1U) /*!< Bit field size in bits for LPTMR_CSR_TFC. */ - -/*! @brief Read current value of the LPTMR_CSR_TFC field. */ -#define BR_LPTMR_CSR_TFC(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC)) - -/*! @brief Format value for bitfield LPTMR_CSR_TFC. */ -#define BF_LPTMR_CSR_TFC(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC) - -/*! @brief Set the TFC field to a new value. */ -#define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TPP[3] (RW) - * - * Configures the polarity of the input source in Pulse Counter mode. TPP must - * be changed only when the LPTMR is disabled. - * - * Values: - * - 0 - Pulse Counter input source is active-high, and the CNR will increment - * on the rising-edge. - * - 1 - Pulse Counter input source is active-low, and the CNR will increment on - * the falling-edge. - */ -/*@{*/ -#define BP_LPTMR_CSR_TPP (3U) /*!< Bit position for LPTMR_CSR_TPP. */ -#define BM_LPTMR_CSR_TPP (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */ -#define BS_LPTMR_CSR_TPP (1U) /*!< Bit field size in bits for LPTMR_CSR_TPP. */ - -/*! @brief Read current value of the LPTMR_CSR_TPP field. */ -#define BR_LPTMR_CSR_TPP(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP)) - -/*! @brief Format value for bitfield LPTMR_CSR_TPP. */ -#define BF_LPTMR_CSR_TPP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP) - -/*! @brief Set the TPP field to a new value. */ -#define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TPS[5:4] (RW) - * - * Configures the input source to be used in Pulse Counter mode. TPS must be - * altered only when the LPTMR is disabled. The input connections vary by device. - * See the chip configuration details for information on the connections to these - * inputs. - * - * Values: - * - 00 - Pulse counter input 0 is selected. - * - 01 - Pulse counter input 1 is selected. - * - 10 - Pulse counter input 2 is selected. - * - 11 - Pulse counter input 3 is selected. - */ -/*@{*/ -#define BP_LPTMR_CSR_TPS (4U) /*!< Bit position for LPTMR_CSR_TPS. */ -#define BM_LPTMR_CSR_TPS (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */ -#define BS_LPTMR_CSR_TPS (2U) /*!< Bit field size in bits for LPTMR_CSR_TPS. */ - -/*! @brief Read current value of the LPTMR_CSR_TPS field. */ -#define BR_LPTMR_CSR_TPS(x) (HW_LPTMR_CSR(x).B.TPS) - -/*! @brief Format value for bitfield LPTMR_CSR_TPS. */ -#define BF_LPTMR_CSR_TPS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS) - -/*! @brief Set the TPS field to a new value. */ -#define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v))) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TIE[6] (RW) - * - * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set. - * - * Values: - * - 0 - Timer interrupt disabled. - * - 1 - Timer interrupt enabled. - */ -/*@{*/ -#define BP_LPTMR_CSR_TIE (6U) /*!< Bit position for LPTMR_CSR_TIE. */ -#define BM_LPTMR_CSR_TIE (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */ -#define BS_LPTMR_CSR_TIE (1U) /*!< Bit field size in bits for LPTMR_CSR_TIE. */ - -/*! @brief Read current value of the LPTMR_CSR_TIE field. */ -#define BR_LPTMR_CSR_TIE(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE)) - -/*! @brief Format value for bitfield LPTMR_CSR_TIE. */ -#define BF_LPTMR_CSR_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TCF[7] (W1C) - * - * TCF is set when the LPTMR is enabled and the CNR equals the CMR and - * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it. - * - * Values: - * - 0 - The value of CNR is not equal to CMR and increments. - * - 1 - The value of CNR is equal to CMR and increments. - */ -/*@{*/ -#define BP_LPTMR_CSR_TCF (7U) /*!< Bit position for LPTMR_CSR_TCF. */ -#define BM_LPTMR_CSR_TCF (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */ -#define BS_LPTMR_CSR_TCF (1U) /*!< Bit field size in bits for LPTMR_CSR_TCF. */ - -/*! @brief Read current value of the LPTMR_CSR_TCF field. */ -#define BR_LPTMR_CSR_TCF(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF)) - -/*! @brief Format value for bitfield LPTMR_CSR_TCF. */ -#define BF_LPTMR_CSR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF) - -/*! @brief Set the TCF field to a new value. */ -#define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LPTMR_PSR - Low Power Timer Prescale Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_psr -{ - uint32_t U; - struct _hw_lptmr_psr_bitfields - { - uint32_t PCS : 2; /*!< [1:0] Prescaler Clock Select */ - uint32_t PBYP : 1; /*!< [2] Prescaler Bypass */ - uint32_t PRESCALE : 4; /*!< [6:3] Prescale Value */ - uint32_t RESERVED0 : 25; /*!< [31:7] */ - } B; -} hw_lptmr_psr_t; - -/*! - * @name Constants and macros for entire LPTMR_PSR register - */ -/*@{*/ -#define HW_LPTMR_PSR_ADDR(x) ((x) + 0x4U) - -#define HW_LPTMR_PSR(x) (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x)) -#define HW_LPTMR_PSR_RD(x) (HW_LPTMR_PSR(x).U) -#define HW_LPTMR_PSR_WR(x, v) (HW_LPTMR_PSR(x).U = (v)) -#define HW_LPTMR_PSR_SET(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) | (v))) -#define HW_LPTMR_PSR_CLR(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v))) -#define HW_LPTMR_PSR_TOG(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_PSR bitfields - */ - -/*! - * @name Register LPTMR_PSR, field PCS[1:0] (RW) - * - * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must - * be altered only when the LPTMR is disabled. The clock connections vary by - * device. See the chip configuration details for information on the connections to - * these inputs. - * - * Values: - * - 00 - Prescaler/glitch filter clock 0 selected. - * - 01 - Prescaler/glitch filter clock 1 selected. - * - 10 - Prescaler/glitch filter clock 2 selected. - * - 11 - Prescaler/glitch filter clock 3 selected. - */ -/*@{*/ -#define BP_LPTMR_PSR_PCS (0U) /*!< Bit position for LPTMR_PSR_PCS. */ -#define BM_LPTMR_PSR_PCS (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */ -#define BS_LPTMR_PSR_PCS (2U) /*!< Bit field size in bits for LPTMR_PSR_PCS. */ - -/*! @brief Read current value of the LPTMR_PSR_PCS field. */ -#define BR_LPTMR_PSR_PCS(x) (HW_LPTMR_PSR(x).B.PCS) - -/*! @brief Format value for bitfield LPTMR_PSR_PCS. */ -#define BF_LPTMR_PSR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS) - -/*! @brief Set the PCS field to a new value. */ -#define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v))) -/*@}*/ - -/*! - * @name Register LPTMR_PSR, field PBYP[2] (RW) - * - * When PBYP is set, the selected prescaler clock in Time Counter mode or - * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is - * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP - * must be altered only when the LPTMR is disabled. - * - * Values: - * - 0 - Prescaler/glitch filter is enabled. - * - 1 - Prescaler/glitch filter is bypassed. - */ -/*@{*/ -#define BP_LPTMR_PSR_PBYP (2U) /*!< Bit position for LPTMR_PSR_PBYP. */ -#define BM_LPTMR_PSR_PBYP (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */ -#define BS_LPTMR_PSR_PBYP (1U) /*!< Bit field size in bits for LPTMR_PSR_PBYP. */ - -/*! @brief Read current value of the LPTMR_PSR_PBYP field. */ -#define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP)) - -/*! @brief Format value for bitfield LPTMR_PSR_PBYP. */ -#define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP) - -/*! @brief Set the PBYP field to a new value. */ -#define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW) - * - * Configures the size of the Prescaler in Time Counter mode or width of the - * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR - * is disabled. - * - * Values: - * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not - * support this configuration. - * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes - * change on input pin after 2 rising clock edges. - * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes - * change on input pin after 4 rising clock edges. - * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter - * recognizes change on input pin after 8 rising clock edges. - * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter - * recognizes change on input pin after 16 rising clock edges. - * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter - * recognizes change on input pin after 32 rising clock edges. - * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter - * recognizes change on input pin after 64 rising clock edges. - * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter - * recognizes change on input pin after 128 rising clock edges. - * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter - * recognizes change on input pin after 256 rising clock edges. - * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter - * recognizes change on input pin after 512 rising clock edges. - * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter - * recognizes change on input pin after 1024 rising clock edges. - * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter - * recognizes change on input pin after 2048 rising clock edges. - * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter - * recognizes change on input pin after 4096 rising clock edges. - * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter - * recognizes change on input pin after 8192 rising clock edges. - * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter - * recognizes change on input pin after 16,384 rising clock edges. - * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter - * recognizes change on input pin after 32,768 rising clock edges. - */ -/*@{*/ -#define BP_LPTMR_PSR_PRESCALE (3U) /*!< Bit position for LPTMR_PSR_PRESCALE. */ -#define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */ -#define BS_LPTMR_PSR_PRESCALE (4U) /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */ - -/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */ -#define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE) - -/*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */ -#define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE) - -/*! @brief Set the PRESCALE field to a new value. */ -#define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v))) -/*@}*/ - -/******************************************************************************* - * HW_LPTMR_CMR - Low Power Timer Compare Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_cmr -{ - uint32_t U; - struct _hw_lptmr_cmr_bitfields - { - uint32_t COMPARE : 16; /*!< [15:0] Compare Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_lptmr_cmr_t; - -/*! - * @name Constants and macros for entire LPTMR_CMR register - */ -/*@{*/ -#define HW_LPTMR_CMR_ADDR(x) ((x) + 0x8U) - -#define HW_LPTMR_CMR(x) (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x)) -#define HW_LPTMR_CMR_RD(x) (HW_LPTMR_CMR(x).U) -#define HW_LPTMR_CMR_WR(x, v) (HW_LPTMR_CMR(x).U = (v)) -#define HW_LPTMR_CMR_SET(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) | (v))) -#define HW_LPTMR_CMR_CLR(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v))) -#define HW_LPTMR_CMR_TOG(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_CMR bitfields - */ - -/*! - * @name Register LPTMR_CMR, field COMPARE[15:0] (RW) - * - * When the LPTMR is enabled and the CNR equals the value in the CMR and - * increments, TCF is set and the hardware trigger asserts until the next time the CNR - * increments. If the CMR is 0, the hardware trigger will remain asserted until - * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only - * when TCF is set. - */ -/*@{*/ -#define BP_LPTMR_CMR_COMPARE (0U) /*!< Bit position for LPTMR_CMR_COMPARE. */ -#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */ -#define BS_LPTMR_CMR_COMPARE (16U) /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */ - -/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */ -#define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE) - -/*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */ -#define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE) - -/*! @brief Set the COMPARE field to a new value. */ -#define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v))) -/*@}*/ - -/******************************************************************************* - * HW_LPTMR_CNR - Low Power Timer Counter Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_cnr -{ - uint32_t U; - struct _hw_lptmr_cnr_bitfields - { - uint32_t COUNTER : 16; /*!< [15:0] Counter Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_lptmr_cnr_t; - -/*! - * @name Constants and macros for entire LPTMR_CNR register - */ -/*@{*/ -#define HW_LPTMR_CNR_ADDR(x) ((x) + 0xCU) - -#define HW_LPTMR_CNR(x) (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x)) -#define HW_LPTMR_CNR_RD(x) (HW_LPTMR_CNR(x).U) -#define HW_LPTMR_CNR_WR(x, v) (HW_LPTMR_CNR(x).U = (v)) -#define HW_LPTMR_CNR_SET(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) | (v))) -#define HW_LPTMR_CNR_CLR(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v))) -#define HW_LPTMR_CNR_TOG(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_CNR bitfields - */ - -/*! - * @name Register LPTMR_CNR, field COUNTER[15:0] (RW) - */ -/*@{*/ -#define BP_LPTMR_CNR_COUNTER (0U) /*!< Bit position for LPTMR_CNR_COUNTER. */ -#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */ -#define BS_LPTMR_CNR_COUNTER (16U) /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */ - -/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */ -#define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER) - -/*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */ -#define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER) - -/*! @brief Set the COUNTER field to a new value. */ -#define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v))) -/*@}*/ - -/******************************************************************************* - * hw_lptmr_t - module struct - ******************************************************************************/ -/*! - * @brief All LPTMR module registers. - */ -#pragma pack(1) -typedef struct _hw_lptmr -{ - __IO hw_lptmr_csr_t CSR; /*!< [0x0] Low Power Timer Control Status Register */ - __IO hw_lptmr_psr_t PSR; /*!< [0x4] Low Power Timer Prescale Register */ - __IO hw_lptmr_cmr_t CMR; /*!< [0x8] Low Power Timer Compare Register */ - __IO hw_lptmr_cnr_t CNR; /*!< [0xC] Low Power Timer Counter Register */ -} hw_lptmr_t; -#pragma pack() - -/*! @brief Macro to access all LPTMR registers. */ -/*! @param x LPTMR module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_LPTMR(LPTMR0_BASE). */ -#define HW_LPTMR(x) (*(hw_lptmr_t *)(x)) - -#endif /* __HW_LPTMR_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h deleted file mode 100644 index 68ec95a4f65..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h +++ /dev/null @@ -1,2519 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_LPUART_REGISTERS_H__ -#define __HW_LPUART_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 LPUART - * - * Universal Asynchronous Receiver/Transmitter - * - * Registers defined in this header file: - * - HW_LPUART_BAUD - LPUART Baud Rate Register - * - HW_LPUART_STAT - LPUART Status Register - * - HW_LPUART_CTRL - LPUART Control Register - * - HW_LPUART_DATA - LPUART Data Register - * - HW_LPUART_MATCH - LPUART Match Address Register - * - HW_LPUART_MODIR - LPUART Modem IrDA Register - * - * - hw_lpuart_t - Struct containing all module registers. - */ - -#define HW_LPUART_INSTANCE_COUNT (1U) /*!< Number of instances of the LPUART module. */ - -/******************************************************************************* - * HW_LPUART_BAUD - LPUART Baud Rate Register - ******************************************************************************/ - -/*! - * @brief HW_LPUART_BAUD - LPUART Baud Rate Register (RW) - * - * Reset value: 0x0F000004U - */ -typedef union _hw_lpuart_baud -{ - uint32_t U; - struct _hw_lpuart_baud_bitfields - { - uint32_t SBR : 13; /*!< [12:0] Baud Rate Modulo Divisor. */ - uint32_t SBNS : 1; /*!< [13] Stop Bit Number Select */ - uint32_t RXEDGIE : 1; /*!< [14] RX Input Active Edge Interrupt Enable - * */ - uint32_t LBKDIE : 1; /*!< [15] LIN Break Detect Interrupt Enable */ - uint32_t RESYNCDIS : 1; /*!< [16] Resynchronization Disable */ - uint32_t BOTHEDGE : 1; /*!< [17] Both Edge Sampling */ - uint32_t MATCFG : 2; /*!< [19:18] Match Configuration */ - uint32_t RESERVED0 : 1; /*!< [20] */ - uint32_t RDMAE : 1; /*!< [21] Receiver Full DMA Enable */ - uint32_t RESERVED1 : 1; /*!< [22] */ - uint32_t TDMAE : 1; /*!< [23] Transmitter DMA Enable */ - uint32_t OSR : 5; /*!< [28:24] Over Sampling Ratio */ - uint32_t M10 : 1; /*!< [29] 10-bit Mode select */ - uint32_t MAEN2 : 1; /*!< [30] Match Address Mode Enable 2 */ - uint32_t MAEN1 : 1; /*!< [31] Match Address Mode Enable 1 */ - } B; -} hw_lpuart_baud_t; - -/*! - * @name Constants and macros for entire LPUART_BAUD register - */ -/*@{*/ -#define HW_LPUART_BAUD_ADDR(x) ((x) + 0x0U) - -#define HW_LPUART_BAUD(x) (*(__IO hw_lpuart_baud_t *) HW_LPUART_BAUD_ADDR(x)) -#define HW_LPUART_BAUD_RD(x) (HW_LPUART_BAUD(x).U) -#define HW_LPUART_BAUD_WR(x, v) (HW_LPUART_BAUD(x).U = (v)) -#define HW_LPUART_BAUD_SET(x, v) (HW_LPUART_BAUD_WR(x, HW_LPUART_BAUD_RD(x) | (v))) -#define HW_LPUART_BAUD_CLR(x, v) (HW_LPUART_BAUD_WR(x, HW_LPUART_BAUD_RD(x) & ~(v))) -#define HW_LPUART_BAUD_TOG(x, v) (HW_LPUART_BAUD_WR(x, HW_LPUART_BAUD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPUART_BAUD bitfields - */ - -/*! - * @name Register LPUART_BAUD, field SBR[12:0] (RW) - * - * The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate - * generator. When SBR is 1 - 8191, the baud rate equals "baud clock / ((OSR+1) * SBR)". - * The 13-bit baud rate setting [SBR12:SBR0] must only be updated when the - * transmitter and receiver are both disabled (LPUART_CTRL[RE] and LPUART_CTRL[TE] are - * both 0). - */ -/*@{*/ -#define BP_LPUART_BAUD_SBR (0U) /*!< Bit position for LPUART_BAUD_SBR. */ -#define BM_LPUART_BAUD_SBR (0x00001FFFU) /*!< Bit mask for LPUART_BAUD_SBR. */ -#define BS_LPUART_BAUD_SBR (13U) /*!< Bit field size in bits for LPUART_BAUD_SBR. */ - -/*! @brief Read current value of the LPUART_BAUD_SBR field. */ -#define BR_LPUART_BAUD_SBR(x) (HW_LPUART_BAUD(x).B.SBR) - -/*! @brief Format value for bitfield LPUART_BAUD_SBR. */ -#define BF_LPUART_BAUD_SBR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_SBR) & BM_LPUART_BAUD_SBR) - -/*! @brief Set the SBR field to a new value. */ -#define BW_LPUART_BAUD_SBR(x, v) (HW_LPUART_BAUD_WR(x, (HW_LPUART_BAUD_RD(x) & ~BM_LPUART_BAUD_SBR) | BF_LPUART_BAUD_SBR(v))) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field SBNS[13] (RW) - * - * SBNS determines whether data characters are one or two stop bits. This bit - * should only be changed when the transmitter and receiver are both disabled. - * - * Values: - * - 0 - One stop bit. - * - 1 - Two stop bits. - */ -/*@{*/ -#define BP_LPUART_BAUD_SBNS (13U) /*!< Bit position for LPUART_BAUD_SBNS. */ -#define BM_LPUART_BAUD_SBNS (0x00002000U) /*!< Bit mask for LPUART_BAUD_SBNS. */ -#define BS_LPUART_BAUD_SBNS (1U) /*!< Bit field size in bits for LPUART_BAUD_SBNS. */ - -/*! @brief Read current value of the LPUART_BAUD_SBNS field. */ -#define BR_LPUART_BAUD_SBNS(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_SBNS)) - -/*! @brief Format value for bitfield LPUART_BAUD_SBNS. */ -#define BF_LPUART_BAUD_SBNS(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_SBNS) & BM_LPUART_BAUD_SBNS) - -/*! @brief Set the SBNS field to a new value. */ -#define BW_LPUART_BAUD_SBNS(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_SBNS) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field RXEDGIE[14] (RW) - * - * Enables the receive input active edge, RXEDGIF, to generate interrupt - * requests. Changing CTRL[LOOP] or CTRL[RSRC] when RXEDGIE is set can cause the RXEDGIF - * to set. - * - * Values: - * - 0 - Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). - * - 1 - Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. - */ -/*@{*/ -#define BP_LPUART_BAUD_RXEDGIE (14U) /*!< Bit position for LPUART_BAUD_RXEDGIE. */ -#define BM_LPUART_BAUD_RXEDGIE (0x00004000U) /*!< Bit mask for LPUART_BAUD_RXEDGIE. */ -#define BS_LPUART_BAUD_RXEDGIE (1U) /*!< Bit field size in bits for LPUART_BAUD_RXEDGIE. */ - -/*! @brief Read current value of the LPUART_BAUD_RXEDGIE field. */ -#define BR_LPUART_BAUD_RXEDGIE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RXEDGIE)) - -/*! @brief Format value for bitfield LPUART_BAUD_RXEDGIE. */ -#define BF_LPUART_BAUD_RXEDGIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_RXEDGIE) & BM_LPUART_BAUD_RXEDGIE) - -/*! @brief Set the RXEDGIE field to a new value. */ -#define BW_LPUART_BAUD_RXEDGIE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RXEDGIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field LBKDIE[15] (RW) - * - * LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt - * requests. - * - * Values: - * - 0 - Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). - * - 1 - Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. - */ -/*@{*/ -#define BP_LPUART_BAUD_LBKDIE (15U) /*!< Bit position for LPUART_BAUD_LBKDIE. */ -#define BM_LPUART_BAUD_LBKDIE (0x00008000U) /*!< Bit mask for LPUART_BAUD_LBKDIE. */ -#define BS_LPUART_BAUD_LBKDIE (1U) /*!< Bit field size in bits for LPUART_BAUD_LBKDIE. */ - -/*! @brief Read current value of the LPUART_BAUD_LBKDIE field. */ -#define BR_LPUART_BAUD_LBKDIE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_LBKDIE)) - -/*! @brief Format value for bitfield LPUART_BAUD_LBKDIE. */ -#define BF_LPUART_BAUD_LBKDIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_LBKDIE) & BM_LPUART_BAUD_LBKDIE) - -/*! @brief Set the LBKDIE field to a new value. */ -#define BW_LPUART_BAUD_LBKDIE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_LBKDIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field RESYNCDIS[16] (RW) - * - * When set, disables the resynchronization of the received data word when a - * data one followed by data zero transition is detected. This bit should only be - * changed when the receiver is disabled. - * - * Values: - * - 0 - Resynchronization during received data word is supported - * - 1 - Resynchronization during received data word is disabled - */ -/*@{*/ -#define BP_LPUART_BAUD_RESYNCDIS (16U) /*!< Bit position for LPUART_BAUD_RESYNCDIS. */ -#define BM_LPUART_BAUD_RESYNCDIS (0x00010000U) /*!< Bit mask for LPUART_BAUD_RESYNCDIS. */ -#define BS_LPUART_BAUD_RESYNCDIS (1U) /*!< Bit field size in bits for LPUART_BAUD_RESYNCDIS. */ - -/*! @brief Read current value of the LPUART_BAUD_RESYNCDIS field. */ -#define BR_LPUART_BAUD_RESYNCDIS(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RESYNCDIS)) - -/*! @brief Format value for bitfield LPUART_BAUD_RESYNCDIS. */ -#define BF_LPUART_BAUD_RESYNCDIS(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_RESYNCDIS) & BM_LPUART_BAUD_RESYNCDIS) - -/*! @brief Set the RESYNCDIS field to a new value. */ -#define BW_LPUART_BAUD_RESYNCDIS(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RESYNCDIS) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field BOTHEDGE[17] (RW) - * - * Enables sampling of the received data on both edges of the baud rate clock, - * effectively doubling the number of times the receiver samples the input data - * for a given oversampling ratio. This bit must be set for oversampling ratios - * between x4 and x7 and is optional for higher oversampling ratios. This bit should - * only be changed when the receiver is disabled. - * - * Values: - * - 0 - Receiver samples input data using the rising edge of the baud rate - * clock. - * - 1 - Receiver samples input data using the rising and falling edge of the - * baud rate clock. - */ -/*@{*/ -#define BP_LPUART_BAUD_BOTHEDGE (17U) /*!< Bit position for LPUART_BAUD_BOTHEDGE. */ -#define BM_LPUART_BAUD_BOTHEDGE (0x00020000U) /*!< Bit mask for LPUART_BAUD_BOTHEDGE. */ -#define BS_LPUART_BAUD_BOTHEDGE (1U) /*!< Bit field size in bits for LPUART_BAUD_BOTHEDGE. */ - -/*! @brief Read current value of the LPUART_BAUD_BOTHEDGE field. */ -#define BR_LPUART_BAUD_BOTHEDGE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_BOTHEDGE)) - -/*! @brief Format value for bitfield LPUART_BAUD_BOTHEDGE. */ -#define BF_LPUART_BAUD_BOTHEDGE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_BOTHEDGE) & BM_LPUART_BAUD_BOTHEDGE) - -/*! @brief Set the BOTHEDGE field to a new value. */ -#define BW_LPUART_BAUD_BOTHEDGE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_BOTHEDGE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field MATCFG[19:18] (RW) - * - * Configures the match addressing mode used. - * - * Values: - * - 00 - Address Match Wakeup - * - 01 - Idle Match Wakeup - * - 10 - Match On and Match Off - * - 11 - Enables RWU on Data Match and Match On/Off for transmitter CTS input - */ -/*@{*/ -#define BP_LPUART_BAUD_MATCFG (18U) /*!< Bit position for LPUART_BAUD_MATCFG. */ -#define BM_LPUART_BAUD_MATCFG (0x000C0000U) /*!< Bit mask for LPUART_BAUD_MATCFG. */ -#define BS_LPUART_BAUD_MATCFG (2U) /*!< Bit field size in bits for LPUART_BAUD_MATCFG. */ - -/*! @brief Read current value of the LPUART_BAUD_MATCFG field. */ -#define BR_LPUART_BAUD_MATCFG(x) (HW_LPUART_BAUD(x).B.MATCFG) - -/*! @brief Format value for bitfield LPUART_BAUD_MATCFG. */ -#define BF_LPUART_BAUD_MATCFG(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_MATCFG) & BM_LPUART_BAUD_MATCFG) - -/*! @brief Set the MATCFG field to a new value. */ -#define BW_LPUART_BAUD_MATCFG(x, v) (HW_LPUART_BAUD_WR(x, (HW_LPUART_BAUD_RD(x) & ~BM_LPUART_BAUD_MATCFG) | BF_LPUART_BAUD_MATCFG(v))) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field RDMAE[21] (RW) - * - * RDMAE configures the receiver data register full flag, LPUART_STAT[RDRF], to - * generate a DMA request. - * - * Values: - * - 0 - DMA request disabled. - * - 1 - DMA request enabled. - */ -/*@{*/ -#define BP_LPUART_BAUD_RDMAE (21U) /*!< Bit position for LPUART_BAUD_RDMAE. */ -#define BM_LPUART_BAUD_RDMAE (0x00200000U) /*!< Bit mask for LPUART_BAUD_RDMAE. */ -#define BS_LPUART_BAUD_RDMAE (1U) /*!< Bit field size in bits for LPUART_BAUD_RDMAE. */ - -/*! @brief Read current value of the LPUART_BAUD_RDMAE field. */ -#define BR_LPUART_BAUD_RDMAE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RDMAE)) - -/*! @brief Format value for bitfield LPUART_BAUD_RDMAE. */ -#define BF_LPUART_BAUD_RDMAE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_RDMAE) & BM_LPUART_BAUD_RDMAE) - -/*! @brief Set the RDMAE field to a new value. */ -#define BW_LPUART_BAUD_RDMAE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RDMAE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field TDMAE[23] (RW) - * - * TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to - * generate a DMA request. - * - * Values: - * - 0 - DMA request disabled. - * - 1 - DMA request enabled. - */ -/*@{*/ -#define BP_LPUART_BAUD_TDMAE (23U) /*!< Bit position for LPUART_BAUD_TDMAE. */ -#define BM_LPUART_BAUD_TDMAE (0x00800000U) /*!< Bit mask for LPUART_BAUD_TDMAE. */ -#define BS_LPUART_BAUD_TDMAE (1U) /*!< Bit field size in bits for LPUART_BAUD_TDMAE. */ - -/*! @brief Read current value of the LPUART_BAUD_TDMAE field. */ -#define BR_LPUART_BAUD_TDMAE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_TDMAE)) - -/*! @brief Format value for bitfield LPUART_BAUD_TDMAE. */ -#define BF_LPUART_BAUD_TDMAE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_TDMAE) & BM_LPUART_BAUD_TDMAE) - -/*! @brief Set the TDMAE field to a new value. */ -#define BW_LPUART_BAUD_TDMAE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_TDMAE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field OSR[28:24] (RW) - * - * This field configures the oversampling ratio for the receiver between 4x - * (00011) and 32x (11111). Writing an invalid oversampling ratio will default to an - * oversampling ratio of 16 (01111). This field should only be changed when the - * transmitter and receiver are both disabled. - */ -/*@{*/ -#define BP_LPUART_BAUD_OSR (24U) /*!< Bit position for LPUART_BAUD_OSR. */ -#define BM_LPUART_BAUD_OSR (0x1F000000U) /*!< Bit mask for LPUART_BAUD_OSR. */ -#define BS_LPUART_BAUD_OSR (5U) /*!< Bit field size in bits for LPUART_BAUD_OSR. */ - -/*! @brief Read current value of the LPUART_BAUD_OSR field. */ -#define BR_LPUART_BAUD_OSR(x) (HW_LPUART_BAUD(x).B.OSR) - -/*! @brief Format value for bitfield LPUART_BAUD_OSR. */ -#define BF_LPUART_BAUD_OSR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_OSR) & BM_LPUART_BAUD_OSR) - -/*! @brief Set the OSR field to a new value. */ -#define BW_LPUART_BAUD_OSR(x, v) (HW_LPUART_BAUD_WR(x, (HW_LPUART_BAUD_RD(x) & ~BM_LPUART_BAUD_OSR) | BF_LPUART_BAUD_OSR(v))) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field M10[29] (RW) - * - * The M10 bit causes a tenth bit to be part of the serial transmission. This - * bit should only be changed when the transmitter and receiver are both disabled. - * - * Values: - * - 0 - Receiver and transmitter use 8-bit or 9-bit data characters. - * - 1 - Receiver and transmitter use 10-bit data characters. - */ -/*@{*/ -#define BP_LPUART_BAUD_M10 (29U) /*!< Bit position for LPUART_BAUD_M10. */ -#define BM_LPUART_BAUD_M10 (0x20000000U) /*!< Bit mask for LPUART_BAUD_M10. */ -#define BS_LPUART_BAUD_M10 (1U) /*!< Bit field size in bits for LPUART_BAUD_M10. */ - -/*! @brief Read current value of the LPUART_BAUD_M10 field. */ -#define BR_LPUART_BAUD_M10(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_M10)) - -/*! @brief Format value for bitfield LPUART_BAUD_M10. */ -#define BF_LPUART_BAUD_M10(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_M10) & BM_LPUART_BAUD_M10) - -/*! @brief Set the M10 field to a new value. */ -#define BW_LPUART_BAUD_M10(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_M10) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field MAEN2[30] (RW) - * - * Values: - * - 0 - Normal operation. - * - 1 - Enables automatic address matching or data matching mode for MATCH[MA2]. - */ -/*@{*/ -#define BP_LPUART_BAUD_MAEN2 (30U) /*!< Bit position for LPUART_BAUD_MAEN2. */ -#define BM_LPUART_BAUD_MAEN2 (0x40000000U) /*!< Bit mask for LPUART_BAUD_MAEN2. */ -#define BS_LPUART_BAUD_MAEN2 (1U) /*!< Bit field size in bits for LPUART_BAUD_MAEN2. */ - -/*! @brief Read current value of the LPUART_BAUD_MAEN2 field. */ -#define BR_LPUART_BAUD_MAEN2(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN2)) - -/*! @brief Format value for bitfield LPUART_BAUD_MAEN2. */ -#define BF_LPUART_BAUD_MAEN2(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_MAEN2) & BM_LPUART_BAUD_MAEN2) - -/*! @brief Set the MAEN2 field to a new value. */ -#define BW_LPUART_BAUD_MAEN2(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN2) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_BAUD, field MAEN1[31] (RW) - * - * Values: - * - 0 - Normal operation. - * - 1 - Enables automatic address matching or data matching mode for MATCH[MA1]. - */ -/*@{*/ -#define BP_LPUART_BAUD_MAEN1 (31U) /*!< Bit position for LPUART_BAUD_MAEN1. */ -#define BM_LPUART_BAUD_MAEN1 (0x80000000U) /*!< Bit mask for LPUART_BAUD_MAEN1. */ -#define BS_LPUART_BAUD_MAEN1 (1U) /*!< Bit field size in bits for LPUART_BAUD_MAEN1. */ - -/*! @brief Read current value of the LPUART_BAUD_MAEN1 field. */ -#define BR_LPUART_BAUD_MAEN1(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN1)) - -/*! @brief Format value for bitfield LPUART_BAUD_MAEN1. */ -#define BF_LPUART_BAUD_MAEN1(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_MAEN1) & BM_LPUART_BAUD_MAEN1) - -/*! @brief Set the MAEN1 field to a new value. */ -#define BW_LPUART_BAUD_MAEN1(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN1) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LPUART_STAT - LPUART Status Register - ******************************************************************************/ - -/*! - * @brief HW_LPUART_STAT - LPUART Status Register (RW) - * - * Reset value: 0x00C00000U - */ -typedef union _hw_lpuart_stat -{ - uint32_t U; - struct _hw_lpuart_stat_bitfields - { - uint32_t RESERVED0 : 14; /*!< [13:0] */ - uint32_t MA2F : 1; /*!< [14] Match 2 Flag */ - uint32_t MA1F : 1; /*!< [15] Match 1 Flag */ - uint32_t PF : 1; /*!< [16] Parity Error Flag */ - uint32_t FE : 1; /*!< [17] Framing Error Flag */ - uint32_t NF : 1; /*!< [18] Noise Flag */ - uint32_t OR : 1; /*!< [19] Receiver Overrun Flag */ - uint32_t IDLE : 1; /*!< [20] Idle Line Flag */ - uint32_t RDRF : 1; /*!< [21] Receive Data Register Full Flag */ - uint32_t TC : 1; /*!< [22] Transmission Complete Flag */ - uint32_t TDRE : 1; /*!< [23] Transmit Data Register Empty Flag */ - uint32_t RAF : 1; /*!< [24] Receiver Active Flag */ - uint32_t LBKDE : 1; /*!< [25] LIN Break Detection Enable */ - uint32_t BRK13 : 1; /*!< [26] Break Character Generation Length */ - uint32_t RWUID : 1; /*!< [27] Receive Wake Up Idle Detect */ - uint32_t RXINV : 1; /*!< [28] Receive Data Inversion */ - uint32_t MSBF : 1; /*!< [29] MSB First */ - uint32_t RXEDGIF : 1; /*!< [30] LPUART_RX Pin Active Edge Interrupt - * Flag */ - uint32_t LBKDIF : 1; /*!< [31] LIN Break Detect Interrupt Flag */ - } B; -} hw_lpuart_stat_t; - -/*! - * @name Constants and macros for entire LPUART_STAT register - */ -/*@{*/ -#define HW_LPUART_STAT_ADDR(x) ((x) + 0x4U) - -#define HW_LPUART_STAT(x) (*(__IO hw_lpuart_stat_t *) HW_LPUART_STAT_ADDR(x)) -#define HW_LPUART_STAT_RD(x) (HW_LPUART_STAT(x).U) -#define HW_LPUART_STAT_WR(x, v) (HW_LPUART_STAT(x).U = (v)) -#define HW_LPUART_STAT_SET(x, v) (HW_LPUART_STAT_WR(x, HW_LPUART_STAT_RD(x) | (v))) -#define HW_LPUART_STAT_CLR(x, v) (HW_LPUART_STAT_WR(x, HW_LPUART_STAT_RD(x) & ~(v))) -#define HW_LPUART_STAT_TOG(x, v) (HW_LPUART_STAT_WR(x, HW_LPUART_STAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPUART_STAT bitfields - */ - -/*! - * @name Register LPUART_STAT, field MA2F[14] (W1C) - * - * MA2F is set whenever the next character to be read from LPUART_DATA matches - * MA2. To clear MA2F, write a logic one to the MA2F. - * - * Values: - * - 0 - Received data is not equal to MA2 - * - 1 - Received data is equal to MA2 - */ -/*@{*/ -#define BP_LPUART_STAT_MA2F (14U) /*!< Bit position for LPUART_STAT_MA2F. */ -#define BM_LPUART_STAT_MA2F (0x00004000U) /*!< Bit mask for LPUART_STAT_MA2F. */ -#define BS_LPUART_STAT_MA2F (1U) /*!< Bit field size in bits for LPUART_STAT_MA2F. */ - -/*! @brief Read current value of the LPUART_STAT_MA2F field. */ -#define BR_LPUART_STAT_MA2F(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA2F)) - -/*! @brief Format value for bitfield LPUART_STAT_MA2F. */ -#define BF_LPUART_STAT_MA2F(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_MA2F) & BM_LPUART_STAT_MA2F) - -/*! @brief Set the MA2F field to a new value. */ -#define BW_LPUART_STAT_MA2F(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA2F) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field MA1F[15] (W1C) - * - * MA1F is set whenever the next character to be read from LPUART_DATA matches - * MA1. To clear MA1F, write a logic one to the MA1F. - * - * Values: - * - 0 - Received data is not equal to MA1 - * - 1 - Received data is equal to MA1 - */ -/*@{*/ -#define BP_LPUART_STAT_MA1F (15U) /*!< Bit position for LPUART_STAT_MA1F. */ -#define BM_LPUART_STAT_MA1F (0x00008000U) /*!< Bit mask for LPUART_STAT_MA1F. */ -#define BS_LPUART_STAT_MA1F (1U) /*!< Bit field size in bits for LPUART_STAT_MA1F. */ - -/*! @brief Read current value of the LPUART_STAT_MA1F field. */ -#define BR_LPUART_STAT_MA1F(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA1F)) - -/*! @brief Format value for bitfield LPUART_STAT_MA1F. */ -#define BF_LPUART_STAT_MA1F(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_MA1F) & BM_LPUART_STAT_MA1F) - -/*! @brief Set the MA1F field to a new value. */ -#define BW_LPUART_STAT_MA1F(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA1F) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field PF[16] (W1C) - * - * PF is set whenever the next character to be read from LPUART_DATA was - * received when parity is enabled (PE = 1) and the parity bit in the received character - * does not agree with the expected parity value. To clear PF, write a logic one - * to the PF. - * - * Values: - * - 0 - No parity error. - * - 1 - Parity error. - */ -/*@{*/ -#define BP_LPUART_STAT_PF (16U) /*!< Bit position for LPUART_STAT_PF. */ -#define BM_LPUART_STAT_PF (0x00010000U) /*!< Bit mask for LPUART_STAT_PF. */ -#define BS_LPUART_STAT_PF (1U) /*!< Bit field size in bits for LPUART_STAT_PF. */ - -/*! @brief Read current value of the LPUART_STAT_PF field. */ -#define BR_LPUART_STAT_PF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_PF)) - -/*! @brief Format value for bitfield LPUART_STAT_PF. */ -#define BF_LPUART_STAT_PF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_PF) & BM_LPUART_STAT_PF) - -/*! @brief Set the PF field to a new value. */ -#define BW_LPUART_STAT_PF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_PF) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field FE[17] (W1C) - * - * FE is set whenever the next character to be read from LPUART_DATA was - * received with logic 0 detected where a stop bit was expected. To clear NF, write - * logic one to the NF. - * - * Values: - * - 0 - No framing error detected. This does not guarantee the framing is - * correct. - * - 1 - Framing error. - */ -/*@{*/ -#define BP_LPUART_STAT_FE (17U) /*!< Bit position for LPUART_STAT_FE. */ -#define BM_LPUART_STAT_FE (0x00020000U) /*!< Bit mask for LPUART_STAT_FE. */ -#define BS_LPUART_STAT_FE (1U) /*!< Bit field size in bits for LPUART_STAT_FE. */ - -/*! @brief Read current value of the LPUART_STAT_FE field. */ -#define BR_LPUART_STAT_FE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_FE)) - -/*! @brief Format value for bitfield LPUART_STAT_FE. */ -#define BF_LPUART_STAT_FE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_FE) & BM_LPUART_STAT_FE) - -/*! @brief Set the FE field to a new value. */ -#define BW_LPUART_STAT_FE(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_FE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field NF[18] (W1C) - * - * The advanced sampling technique used in the receiver takes three samples in - * each of the received bits. If any of these samples disagrees with the rest of - * the samples within any bit time in the frame then noise is detected for that - * character. NF is set whenever the next character to be read from LPUART_DATA was - * received with noise detected within the character. To clear NF, write logic - * one to the NF. - * - * Values: - * - 0 - No noise detected. - * - 1 - Noise detected in the received character in LPUART_DATA. - */ -/*@{*/ -#define BP_LPUART_STAT_NF (18U) /*!< Bit position for LPUART_STAT_NF. */ -#define BM_LPUART_STAT_NF (0x00040000U) /*!< Bit mask for LPUART_STAT_NF. */ -#define BS_LPUART_STAT_NF (1U) /*!< Bit field size in bits for LPUART_STAT_NF. */ - -/*! @brief Read current value of the LPUART_STAT_NF field. */ -#define BR_LPUART_STAT_NF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_NF)) - -/*! @brief Format value for bitfield LPUART_STAT_NF. */ -#define BF_LPUART_STAT_NF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_NF) & BM_LPUART_STAT_NF) - -/*! @brief Set the NF field to a new value. */ -#define BW_LPUART_STAT_NF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_NF) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field OR[19] (W1C) - * - * OR is set when software fails to prevent the receive data register from - * overflowing with data. The OR bit is set immediately after the stop bit has been - * completely received for the dataword that overflows the buffer and all the other - * error flags (FE, NF, and PF) are prevented from setting. The data in the - * shift register is lost, but the data already in the LPUART data registers is not - * affected. If LBKDE is enabled and a LIN Break is detected, the OR field asserts - * if LBKDIF is not cleared before the next data character is received. While - * the OR flag is set, no additional data is stored in the data buffer even if - * sufficient room exists. To clear OR, write logic 1 to the OR flag. - * - * Values: - * - 0 - No overrun. - * - 1 - Receive overrun (new LPUART data lost). - */ -/*@{*/ -#define BP_LPUART_STAT_OR (19U) /*!< Bit position for LPUART_STAT_OR. */ -#define BM_LPUART_STAT_OR (0x00080000U) /*!< Bit mask for LPUART_STAT_OR. */ -#define BS_LPUART_STAT_OR (1U) /*!< Bit field size in bits for LPUART_STAT_OR. */ - -/*! @brief Read current value of the LPUART_STAT_OR field. */ -#define BR_LPUART_STAT_OR(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_OR)) - -/*! @brief Format value for bitfield LPUART_STAT_OR. */ -#define BF_LPUART_STAT_OR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_OR) & BM_LPUART_STAT_OR) - -/*! @brief Set the OR field to a new value. */ -#define BW_LPUART_STAT_OR(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_OR) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field IDLE[20] (W1C) - * - * IDLE is set when the LPUART receive line becomes idle for a full character - * time after a period of activity. When ILT is cleared, the receiver starts - * counting idle bit times after the start bit. If the receive character is all 1s, - * these bit times and the stop bits time count toward the full character time of - * logic high, 10 to 13 bit times, needed for the receiver to detect an idle line. - * When ILT is set, the receiver doesn't start counting idle bit times until - * after the stop bits. The stop bits and any logic high bit times at the end of the - * previous character do not count toward the full character time of logic high - * needed for the receiver to detect an idle line. To clear IDLE, write logic 1 to - * the IDLE flag. After IDLE has been cleared, it cannot become set again until - * after a new character has been stored in the receive buffer or a LIN break - * character has set the LBKDIF flag . IDLE is set only once even if the receive - * line remains idle for an extended period. - * - * Values: - * - 0 - No idle line detected. - * - 1 - Idle line was detected. - */ -/*@{*/ -#define BP_LPUART_STAT_IDLE (20U) /*!< Bit position for LPUART_STAT_IDLE. */ -#define BM_LPUART_STAT_IDLE (0x00100000U) /*!< Bit mask for LPUART_STAT_IDLE. */ -#define BS_LPUART_STAT_IDLE (1U) /*!< Bit field size in bits for LPUART_STAT_IDLE. */ - -/*! @brief Read current value of the LPUART_STAT_IDLE field. */ -#define BR_LPUART_STAT_IDLE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_IDLE)) - -/*! @brief Format value for bitfield LPUART_STAT_IDLE. */ -#define BF_LPUART_STAT_IDLE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_IDLE) & BM_LPUART_STAT_IDLE) - -/*! @brief Set the IDLE field to a new value. */ -#define BW_LPUART_STAT_IDLE(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_IDLE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field RDRF[21] (RO) - * - * RDRF is set when the receive buffer (LPUART_DATA) is full. To clear RDRF, - * read the LPUART_DATA register. A character that is in the process of being - * received does not cause a change in RDRF until the entire character is received. - * Even if RDRF is set, the character will continue to be received until an overrun - * condition occurs once the entire character is received. - * - * Values: - * - 0 - Receive data buffer empty. - * - 1 - Receive data buffer full. - */ -/*@{*/ -#define BP_LPUART_STAT_RDRF (21U) /*!< Bit position for LPUART_STAT_RDRF. */ -#define BM_LPUART_STAT_RDRF (0x00200000U) /*!< Bit mask for LPUART_STAT_RDRF. */ -#define BS_LPUART_STAT_RDRF (1U) /*!< Bit field size in bits for LPUART_STAT_RDRF. */ - -/*! @brief Read current value of the LPUART_STAT_RDRF field. */ -#define BR_LPUART_STAT_RDRF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RDRF)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field TC[22] (RO) - * - * TC is cleared when there is a transmission in progress or when a preamble or - * break character is loaded. TC is set when the transmit buffer is empty and no - * data, preamble, or break character is being transmitted. When TC is set, the - * transmit data output signal becomes idle (logic 1). TC is cleared by writing to - * LPUART_DATA to transmit new data, queuing a preamble by clearing and then - * setting LPUART_CTRL[TE], queuing a break character by writing 1 to - * LPUART_CTRL[SBK]. - * - * Values: - * - 0 - Transmitter active (sending data, a preamble, or a break). - * - 1 - Transmitter idle (transmission activity complete). - */ -/*@{*/ -#define BP_LPUART_STAT_TC (22U) /*!< Bit position for LPUART_STAT_TC. */ -#define BM_LPUART_STAT_TC (0x00400000U) /*!< Bit mask for LPUART_STAT_TC. */ -#define BS_LPUART_STAT_TC (1U) /*!< Bit field size in bits for LPUART_STAT_TC. */ - -/*! @brief Read current value of the LPUART_STAT_TC field. */ -#define BR_LPUART_STAT_TC(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_TC)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field TDRE[23] (RO) - * - * TDRE will set when the transmit data register (LPUART_DATA) is empty. To - * clear TDRE, write to the LPUART data register (LPUART_DATA). TDRE is not affected - * by a character that is in the process of being transmitted, it is updated at - * the start of each transmitted character. - * - * Values: - * - 0 - Transmit data buffer full. - * - 1 - Transmit data buffer empty. - */ -/*@{*/ -#define BP_LPUART_STAT_TDRE (23U) /*!< Bit position for LPUART_STAT_TDRE. */ -#define BM_LPUART_STAT_TDRE (0x00800000U) /*!< Bit mask for LPUART_STAT_TDRE. */ -#define BS_LPUART_STAT_TDRE (1U) /*!< Bit field size in bits for LPUART_STAT_TDRE. */ - -/*! @brief Read current value of the LPUART_STAT_TDRE field. */ -#define BR_LPUART_STAT_TDRE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_TDRE)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field RAF[24] (RO) - * - * RAF is set when the receiver detects the beginning of a valid start bit, and - * RAF is cleared automatically when the receiver detects an idle line. - * - * Values: - * - 0 - LPUART receiver idle waiting for a start bit. - * - 1 - LPUART receiver active (LPUART_RX input not idle). - */ -/*@{*/ -#define BP_LPUART_STAT_RAF (24U) /*!< Bit position for LPUART_STAT_RAF. */ -#define BM_LPUART_STAT_RAF (0x01000000U) /*!< Bit mask for LPUART_STAT_RAF. */ -#define BS_LPUART_STAT_RAF (1U) /*!< Bit field size in bits for LPUART_STAT_RAF. */ - -/*! @brief Read current value of the LPUART_STAT_RAF field. */ -#define BR_LPUART_STAT_RAF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RAF)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field LBKDE[25] (RW) - * - * LBKDE selects a longer break character detection length. While LBKDE is set, - * receive data is not stored in the receive data buffer. - * - * Values: - * - 0 - Break character is detected at length 10 bit times (if M = 0, SBNS = 0) - * or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 - * or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). - * - 1 - Break character is detected at length of 11 bit times (if M = 0, SBNS = - * 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = - * 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). - */ -/*@{*/ -#define BP_LPUART_STAT_LBKDE (25U) /*!< Bit position for LPUART_STAT_LBKDE. */ -#define BM_LPUART_STAT_LBKDE (0x02000000U) /*!< Bit mask for LPUART_STAT_LBKDE. */ -#define BS_LPUART_STAT_LBKDE (1U) /*!< Bit field size in bits for LPUART_STAT_LBKDE. */ - -/*! @brief Read current value of the LPUART_STAT_LBKDE field. */ -#define BR_LPUART_STAT_LBKDE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDE)) - -/*! @brief Format value for bitfield LPUART_STAT_LBKDE. */ -#define BF_LPUART_STAT_LBKDE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_LBKDE) & BM_LPUART_STAT_LBKDE) - -/*! @brief Set the LBKDE field to a new value. */ -#define BW_LPUART_STAT_LBKDE(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field BRK13[26] (RW) - * - * BRK13 selects a longer transmitted break character length. Detection of a - * framing error is not affected by the state of this bit. This bit should only be - * changed when the transmitter is disabled. - * - * Values: - * - 0 - Break character is transmitted with length of 10 bit times (if M = 0, - * SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, - * SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). - * - 1 - Break character is transmitted with length of 13 bit times (if M = 0, - * SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, - * SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). - */ -/*@{*/ -#define BP_LPUART_STAT_BRK13 (26U) /*!< Bit position for LPUART_STAT_BRK13. */ -#define BM_LPUART_STAT_BRK13 (0x04000000U) /*!< Bit mask for LPUART_STAT_BRK13. */ -#define BS_LPUART_STAT_BRK13 (1U) /*!< Bit field size in bits for LPUART_STAT_BRK13. */ - -/*! @brief Read current value of the LPUART_STAT_BRK13 field. */ -#define BR_LPUART_STAT_BRK13(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_BRK13)) - -/*! @brief Format value for bitfield LPUART_STAT_BRK13. */ -#define BF_LPUART_STAT_BRK13(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_BRK13) & BM_LPUART_STAT_BRK13) - -/*! @brief Set the BRK13 field to a new value. */ -#define BW_LPUART_STAT_BRK13(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_BRK13) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field RWUID[27] (RW) - * - * For RWU on idle character, RWUID controls whether the idle character that - * wakes up the receiver sets the IDLE bit. For address match wakeup, RWUID controls - * if the IDLE bit is set when the address does not match. This bit should only - * be changed when the receiver is disabled. - * - * Values: - * - 0 - During receive standby state (RWU = 1), the IDLE bit does not get set - * upon detection of an idle character. During address match wakeup, the IDLE - * bit does not get set when an address does not match. - * - 1 - During receive standby state (RWU = 1), the IDLE bit gets set upon - * detection of an idle character. During address match wakeup, the IDLE bit does - * get set when an address does not match. - */ -/*@{*/ -#define BP_LPUART_STAT_RWUID (27U) /*!< Bit position for LPUART_STAT_RWUID. */ -#define BM_LPUART_STAT_RWUID (0x08000000U) /*!< Bit mask for LPUART_STAT_RWUID. */ -#define BS_LPUART_STAT_RWUID (1U) /*!< Bit field size in bits for LPUART_STAT_RWUID. */ - -/*! @brief Read current value of the LPUART_STAT_RWUID field. */ -#define BR_LPUART_STAT_RWUID(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RWUID)) - -/*! @brief Format value for bitfield LPUART_STAT_RWUID. */ -#define BF_LPUART_STAT_RWUID(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_RWUID) & BM_LPUART_STAT_RWUID) - -/*! @brief Set the RWUID field to a new value. */ -#define BW_LPUART_STAT_RWUID(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RWUID) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field RXINV[28] (RW) - * - * Setting this bit reverses the polarity of the received data input. Setting - * RXINV inverts the LPUART_RX input for all cases: data bits, start and stop bits, - * break, and idle. - * - * Values: - * - 0 - Receive data not inverted. - * - 1 - Receive data inverted. - */ -/*@{*/ -#define BP_LPUART_STAT_RXINV (28U) /*!< Bit position for LPUART_STAT_RXINV. */ -#define BM_LPUART_STAT_RXINV (0x10000000U) /*!< Bit mask for LPUART_STAT_RXINV. */ -#define BS_LPUART_STAT_RXINV (1U) /*!< Bit field size in bits for LPUART_STAT_RXINV. */ - -/*! @brief Read current value of the LPUART_STAT_RXINV field. */ -#define BR_LPUART_STAT_RXINV(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXINV)) - -/*! @brief Format value for bitfield LPUART_STAT_RXINV. */ -#define BF_LPUART_STAT_RXINV(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_RXINV) & BM_LPUART_STAT_RXINV) - -/*! @brief Set the RXINV field to a new value. */ -#define BW_LPUART_STAT_RXINV(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXINV) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field MSBF[29] (RW) - * - * Setting this bit reverses the order of the bits that are transmitted and - * received on the wire. This bit does not affect the polarity of the bits, the - * location of the parity bit or the location of the start or stop bits. This bit - * should only be changed when the transmitter and receiver are both disabled. - * - * Values: - * - 0 - LSB (bit0) is the first bit that is transmitted following the start - * bit. Further, the first bit received after the start bit is identified as - * bit0. - * - 1 - MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted - * following the start bit depending on the setting of CTRL[M], CTRL[PE] and - * BAUD[M10]. Further, the first bit received after the start bit is identified - * as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and - * CTRL[PE]. - */ -/*@{*/ -#define BP_LPUART_STAT_MSBF (29U) /*!< Bit position for LPUART_STAT_MSBF. */ -#define BM_LPUART_STAT_MSBF (0x20000000U) /*!< Bit mask for LPUART_STAT_MSBF. */ -#define BS_LPUART_STAT_MSBF (1U) /*!< Bit field size in bits for LPUART_STAT_MSBF. */ - -/*! @brief Read current value of the LPUART_STAT_MSBF field. */ -#define BR_LPUART_STAT_MSBF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MSBF)) - -/*! @brief Format value for bitfield LPUART_STAT_MSBF. */ -#define BF_LPUART_STAT_MSBF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_MSBF) & BM_LPUART_STAT_MSBF) - -/*! @brief Set the MSBF field to a new value. */ -#define BW_LPUART_STAT_MSBF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MSBF) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field RXEDGIF[30] (W1C) - * - * RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, - * on the LPUART_RX pin occurs. RXEDGIF is cleared by writing a 1 to it. - * - * Values: - * - 0 - No active edge on the receive pin has occurred. - * - 1 - An active edge on the receive pin has occurred. - */ -/*@{*/ -#define BP_LPUART_STAT_RXEDGIF (30U) /*!< Bit position for LPUART_STAT_RXEDGIF. */ -#define BM_LPUART_STAT_RXEDGIF (0x40000000U) /*!< Bit mask for LPUART_STAT_RXEDGIF. */ -#define BS_LPUART_STAT_RXEDGIF (1U) /*!< Bit field size in bits for LPUART_STAT_RXEDGIF. */ - -/*! @brief Read current value of the LPUART_STAT_RXEDGIF field. */ -#define BR_LPUART_STAT_RXEDGIF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXEDGIF)) - -/*! @brief Format value for bitfield LPUART_STAT_RXEDGIF. */ -#define BF_LPUART_STAT_RXEDGIF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_RXEDGIF) & BM_LPUART_STAT_RXEDGIF) - -/*! @brief Set the RXEDGIF field to a new value. */ -#define BW_LPUART_STAT_RXEDGIF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXEDGIF) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_STAT, field LBKDIF[31] (W1C) - * - * LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break - * character is detected. LBKDIF is cleared by writing a 1 to it. - * - * Values: - * - 0 - No LIN break character has been detected. - * - 1 - LIN break character has been detected. - */ -/*@{*/ -#define BP_LPUART_STAT_LBKDIF (31U) /*!< Bit position for LPUART_STAT_LBKDIF. */ -#define BM_LPUART_STAT_LBKDIF (0x80000000U) /*!< Bit mask for LPUART_STAT_LBKDIF. */ -#define BS_LPUART_STAT_LBKDIF (1U) /*!< Bit field size in bits for LPUART_STAT_LBKDIF. */ - -/*! @brief Read current value of the LPUART_STAT_LBKDIF field. */ -#define BR_LPUART_STAT_LBKDIF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDIF)) - -/*! @brief Format value for bitfield LPUART_STAT_LBKDIF. */ -#define BF_LPUART_STAT_LBKDIF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_LBKDIF) & BM_LPUART_STAT_LBKDIF) - -/*! @brief Set the LBKDIF field to a new value. */ -#define BW_LPUART_STAT_LBKDIF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDIF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LPUART_CTRL - LPUART Control Register - ******************************************************************************/ - -/*! - * @brief HW_LPUART_CTRL - LPUART Control Register (RW) - * - * Reset value: 0x00000000U - * - * This read/write register controls various optional features of the LPUART - * system. This register should only be altered when the transmitter and receiver - * are both disabled. - */ -typedef union _hw_lpuart_ctrl -{ - uint32_t U; - struct _hw_lpuart_ctrl_bitfields - { - uint32_t PT : 1; /*!< [0] Parity Type */ - uint32_t PE : 1; /*!< [1] Parity Enable */ - uint32_t ILT : 1; /*!< [2] Idle Line Type Select */ - uint32_t WAKE : 1; /*!< [3] Receiver Wakeup Method Select */ - uint32_t M : 1; /*!< [4] 9-Bit or 8-Bit Mode Select */ - uint32_t RSRC : 1; /*!< [5] Receiver Source Select */ - uint32_t DOZEEN : 1; /*!< [6] Doze Enable */ - uint32_t LOOPS : 1; /*!< [7] Loop Mode Select */ - uint32_t IDLECFG : 3; /*!< [10:8] Idle Configuration */ - uint32_t RESERVED0 : 3; /*!< [13:11] */ - uint32_t MA2IE : 1; /*!< [14] Match 2 Interrupt Enable */ - uint32_t MA1IE : 1; /*!< [15] Match 1 Interrupt Enable */ - uint32_t SBK : 1; /*!< [16] Send Break */ - uint32_t RWU : 1; /*!< [17] Receiver Wakeup Control */ - uint32_t RE : 1; /*!< [18] Receiver Enable */ - uint32_t TE : 1; /*!< [19] Transmitter Enable */ - uint32_t ILIE : 1; /*!< [20] Idle Line Interrupt Enable */ - uint32_t RIE : 1; /*!< [21] Receiver Interrupt Enable */ - uint32_t TCIE : 1; /*!< [22] Transmission Complete Interrupt Enable - * for */ - uint32_t TIE : 1; /*!< [23] Transmit Interrupt Enable */ - uint32_t PEIE : 1; /*!< [24] Parity Error Interrupt Enable */ - uint32_t FEIE : 1; /*!< [25] Framing Error Interrupt Enable */ - uint32_t NEIE : 1; /*!< [26] Noise Error Interrupt Enable */ - uint32_t ORIE : 1; /*!< [27] Overrun Interrupt Enable */ - uint32_t TXINV : 1; /*!< [28] Transmit Data Inversion */ - uint32_t TXDIR : 1; /*!< [29] LPUART_TX Pin Direction in Single-Wire - * Mode */ - uint32_t R9T8 : 1; /*!< [30] Receive Bit 9 / Transmit Bit 8 */ - uint32_t R8T9 : 1; /*!< [31] Receive Bit 8 / Transmit Bit 9 */ - } B; -} hw_lpuart_ctrl_t; - -/*! - * @name Constants and macros for entire LPUART_CTRL register - */ -/*@{*/ -#define HW_LPUART_CTRL_ADDR(x) ((x) + 0x8U) - -#define HW_LPUART_CTRL(x) (*(__IO hw_lpuart_ctrl_t *) HW_LPUART_CTRL_ADDR(x)) -#define HW_LPUART_CTRL_RD(x) (HW_LPUART_CTRL(x).U) -#define HW_LPUART_CTRL_WR(x, v) (HW_LPUART_CTRL(x).U = (v)) -#define HW_LPUART_CTRL_SET(x, v) (HW_LPUART_CTRL_WR(x, HW_LPUART_CTRL_RD(x) | (v))) -#define HW_LPUART_CTRL_CLR(x, v) (HW_LPUART_CTRL_WR(x, HW_LPUART_CTRL_RD(x) & ~(v))) -#define HW_LPUART_CTRL_TOG(x, v) (HW_LPUART_CTRL_WR(x, HW_LPUART_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPUART_CTRL bitfields - */ - -/*! - * @name Register LPUART_CTRL, field PT[0] (RW) - * - * Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd - * parity means the total number of 1s in the data character, including the - * parity bit, is odd. Even parity means the total number of 1s in the data - * character, including the parity bit, is even. - * - * Values: - * - 0 - Even parity. - * - 1 - Odd parity. - */ -/*@{*/ -#define BP_LPUART_CTRL_PT (0U) /*!< Bit position for LPUART_CTRL_PT. */ -#define BM_LPUART_CTRL_PT (0x00000001U) /*!< Bit mask for LPUART_CTRL_PT. */ -#define BS_LPUART_CTRL_PT (1U) /*!< Bit field size in bits for LPUART_CTRL_PT. */ - -/*! @brief Read current value of the LPUART_CTRL_PT field. */ -#define BR_LPUART_CTRL_PT(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PT)) - -/*! @brief Format value for bitfield LPUART_CTRL_PT. */ -#define BF_LPUART_CTRL_PT(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_PT) & BM_LPUART_CTRL_PT) - -/*! @brief Set the PT field to a new value. */ -#define BW_LPUART_CTRL_PT(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PT) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field PE[1] (RW) - * - * Enables hardware parity generation and checking. When parity is enabled, the - * bit immediately before the stop bit is treated as the parity bit. - * - * Values: - * - 0 - No hardware parity generation or checking. - * - 1 - Parity enabled. - */ -/*@{*/ -#define BP_LPUART_CTRL_PE (1U) /*!< Bit position for LPUART_CTRL_PE. */ -#define BM_LPUART_CTRL_PE (0x00000002U) /*!< Bit mask for LPUART_CTRL_PE. */ -#define BS_LPUART_CTRL_PE (1U) /*!< Bit field size in bits for LPUART_CTRL_PE. */ - -/*! @brief Read current value of the LPUART_CTRL_PE field. */ -#define BR_LPUART_CTRL_PE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PE)) - -/*! @brief Format value for bitfield LPUART_CTRL_PE. */ -#define BF_LPUART_CTRL_PE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_PE) & BM_LPUART_CTRL_PE) - -/*! @brief Set the PE field to a new value. */ -#define BW_LPUART_CTRL_PE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field ILT[2] (RW) - * - * Determines when the receiver starts counting logic 1s as idle character bits. - * The count begins either after a valid start bit or after the stop bit. If the - * count begins after the start bit, then a string of logic 1s preceding the - * stop bit can cause false recognition of an idle character. Beginning the count - * after the stop bit avoids false idle character recognition, but requires - * properly synchronized transmissions. In case the LPUART is programmed with ILT = 1, a - * logic 0 is automatically shifted after a received stop bit, therefore - * resetting the idle count. - * - * Values: - * - 0 - Idle character bit count starts after start bit. - * - 1 - Idle character bit count starts after stop bit. - */ -/*@{*/ -#define BP_LPUART_CTRL_ILT (2U) /*!< Bit position for LPUART_CTRL_ILT. */ -#define BM_LPUART_CTRL_ILT (0x00000004U) /*!< Bit mask for LPUART_CTRL_ILT. */ -#define BS_LPUART_CTRL_ILT (1U) /*!< Bit field size in bits for LPUART_CTRL_ILT. */ - -/*! @brief Read current value of the LPUART_CTRL_ILT field. */ -#define BR_LPUART_CTRL_ILT(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILT)) - -/*! @brief Format value for bitfield LPUART_CTRL_ILT. */ -#define BF_LPUART_CTRL_ILT(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_ILT) & BM_LPUART_CTRL_ILT) - -/*! @brief Set the ILT field to a new value. */ -#define BW_LPUART_CTRL_ILT(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILT) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field WAKE[3] (RW) - * - * Determines which condition wakes the LPUART when RWU=1: Address mark in the - * most significant bit position of a received data character, or An idle - * condition on the receive pin input signal. - * - * Values: - * - 0 - Configures RWU for idle-line wakeup. - * - 1 - Configures RWU with address-mark wakeup. - */ -/*@{*/ -#define BP_LPUART_CTRL_WAKE (3U) /*!< Bit position for LPUART_CTRL_WAKE. */ -#define BM_LPUART_CTRL_WAKE (0x00000008U) /*!< Bit mask for LPUART_CTRL_WAKE. */ -#define BS_LPUART_CTRL_WAKE (1U) /*!< Bit field size in bits for LPUART_CTRL_WAKE. */ - -/*! @brief Read current value of the LPUART_CTRL_WAKE field. */ -#define BR_LPUART_CTRL_WAKE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_WAKE)) - -/*! @brief Format value for bitfield LPUART_CTRL_WAKE. */ -#define BF_LPUART_CTRL_WAKE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_WAKE) & BM_LPUART_CTRL_WAKE) - -/*! @brief Set the WAKE field to a new value. */ -#define BW_LPUART_CTRL_WAKE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_WAKE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field M[4] (RW) - * - * Values: - * - 0 - Receiver and transmitter use 8-bit data characters. - * - 1 - Receiver and transmitter use 9-bit data characters. - */ -/*@{*/ -#define BP_LPUART_CTRL_M (4U) /*!< Bit position for LPUART_CTRL_M. */ -#define BM_LPUART_CTRL_M (0x00000010U) /*!< Bit mask for LPUART_CTRL_M. */ -#define BS_LPUART_CTRL_M (1U) /*!< Bit field size in bits for LPUART_CTRL_M. */ - -/*! @brief Read current value of the LPUART_CTRL_M field. */ -#define BR_LPUART_CTRL_M(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_M)) - -/*! @brief Format value for bitfield LPUART_CTRL_M. */ -#define BF_LPUART_CTRL_M(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_M) & BM_LPUART_CTRL_M) - -/*! @brief Set the M field to a new value. */ -#define BW_LPUART_CTRL_M(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_M) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field RSRC[5] (RW) - * - * This field has no meaning or effect unless the LOOPS field is set. When LOOPS - * is set, the RSRC field determines the source for the receiver shift register - * input. - * - * Values: - * - 0 - Provided LOOPS is set, RSRC is cleared, selects internal loop back mode - * and the LPUART does not use the LPUART_RX pin. - * - 1 - Single-wire LPUART mode where the LPUART_TX pin is connected to the - * transmitter output and receiver input. - */ -/*@{*/ -#define BP_LPUART_CTRL_RSRC (5U) /*!< Bit position for LPUART_CTRL_RSRC. */ -#define BM_LPUART_CTRL_RSRC (0x00000020U) /*!< Bit mask for LPUART_CTRL_RSRC. */ -#define BS_LPUART_CTRL_RSRC (1U) /*!< Bit field size in bits for LPUART_CTRL_RSRC. */ - -/*! @brief Read current value of the LPUART_CTRL_RSRC field. */ -#define BR_LPUART_CTRL_RSRC(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RSRC)) - -/*! @brief Format value for bitfield LPUART_CTRL_RSRC. */ -#define BF_LPUART_CTRL_RSRC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RSRC) & BM_LPUART_CTRL_RSRC) - -/*! @brief Set the RSRC field to a new value. */ -#define BW_LPUART_CTRL_RSRC(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RSRC) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field DOZEEN[6] (RW) - * - * Values: - * - 0 - LPUART is enabled in Doze mode. - * - 1 - LPUART is disabled in Doze mode. - */ -/*@{*/ -#define BP_LPUART_CTRL_DOZEEN (6U) /*!< Bit position for LPUART_CTRL_DOZEEN. */ -#define BM_LPUART_CTRL_DOZEEN (0x00000040U) /*!< Bit mask for LPUART_CTRL_DOZEEN. */ -#define BS_LPUART_CTRL_DOZEEN (1U) /*!< Bit field size in bits for LPUART_CTRL_DOZEEN. */ - -/*! @brief Read current value of the LPUART_CTRL_DOZEEN field. */ -#define BR_LPUART_CTRL_DOZEEN(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_DOZEEN)) - -/*! @brief Format value for bitfield LPUART_CTRL_DOZEEN. */ -#define BF_LPUART_CTRL_DOZEEN(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_DOZEEN) & BM_LPUART_CTRL_DOZEEN) - -/*! @brief Set the DOZEEN field to a new value. */ -#define BW_LPUART_CTRL_DOZEEN(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_DOZEEN) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field LOOPS[7] (RW) - * - * When LOOPS is set, the LPUART_RX pin is disconnected from the LPUART and the - * transmitter output is internally connected to the receiver input. The - * transmitter and the receiver must be enabled to use the loop function. - * - * Values: - * - 0 - Normal operation - LPUART_RX and LPUART_TX use separate pins. - * - 1 - Loop mode or single-wire mode where transmitter outputs are internally - * connected to receiver input (see RSRC bit). - */ -/*@{*/ -#define BP_LPUART_CTRL_LOOPS (7U) /*!< Bit position for LPUART_CTRL_LOOPS. */ -#define BM_LPUART_CTRL_LOOPS (0x00000080U) /*!< Bit mask for LPUART_CTRL_LOOPS. */ -#define BS_LPUART_CTRL_LOOPS (1U) /*!< Bit field size in bits for LPUART_CTRL_LOOPS. */ - -/*! @brief Read current value of the LPUART_CTRL_LOOPS field. */ -#define BR_LPUART_CTRL_LOOPS(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_LOOPS)) - -/*! @brief Format value for bitfield LPUART_CTRL_LOOPS. */ -#define BF_LPUART_CTRL_LOOPS(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_LOOPS) & BM_LPUART_CTRL_LOOPS) - -/*! @brief Set the LOOPS field to a new value. */ -#define BW_LPUART_CTRL_LOOPS(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_LOOPS) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field IDLECFG[10:8] (RW) - * - * Configures the number of idle characters that must be received before the - * IDLE flag is set. - * - * Values: - * - 000 - 1 idle character - * - 001 - 2 idle characters - * - 010 - 4 idle characters - * - 011 - 8 idle characters - * - 100 - 16 idle characters - * - 101 - 32 idle characters - * - 110 - 64 idle characters - * - 111 - 128 idle characters - */ -/*@{*/ -#define BP_LPUART_CTRL_IDLECFG (8U) /*!< Bit position for LPUART_CTRL_IDLECFG. */ -#define BM_LPUART_CTRL_IDLECFG (0x00000700U) /*!< Bit mask for LPUART_CTRL_IDLECFG. */ -#define BS_LPUART_CTRL_IDLECFG (3U) /*!< Bit field size in bits for LPUART_CTRL_IDLECFG. */ - -/*! @brief Read current value of the LPUART_CTRL_IDLECFG field. */ -#define BR_LPUART_CTRL_IDLECFG(x) (HW_LPUART_CTRL(x).B.IDLECFG) - -/*! @brief Format value for bitfield LPUART_CTRL_IDLECFG. */ -#define BF_LPUART_CTRL_IDLECFG(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_IDLECFG) & BM_LPUART_CTRL_IDLECFG) - -/*! @brief Set the IDLECFG field to a new value. */ -#define BW_LPUART_CTRL_IDLECFG(x, v) (HW_LPUART_CTRL_WR(x, (HW_LPUART_CTRL_RD(x) & ~BM_LPUART_CTRL_IDLECFG) | BF_LPUART_CTRL_IDLECFG(v))) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field MA2IE[14] (RW) - * - * Values: - * - 0 - MA2F interrupt disabled - * - 1 - MA2F interrupt enabled - */ -/*@{*/ -#define BP_LPUART_CTRL_MA2IE (14U) /*!< Bit position for LPUART_CTRL_MA2IE. */ -#define BM_LPUART_CTRL_MA2IE (0x00004000U) /*!< Bit mask for LPUART_CTRL_MA2IE. */ -#define BS_LPUART_CTRL_MA2IE (1U) /*!< Bit field size in bits for LPUART_CTRL_MA2IE. */ - -/*! @brief Read current value of the LPUART_CTRL_MA2IE field. */ -#define BR_LPUART_CTRL_MA2IE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA2IE)) - -/*! @brief Format value for bitfield LPUART_CTRL_MA2IE. */ -#define BF_LPUART_CTRL_MA2IE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_MA2IE) & BM_LPUART_CTRL_MA2IE) - -/*! @brief Set the MA2IE field to a new value. */ -#define BW_LPUART_CTRL_MA2IE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA2IE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field MA1IE[15] (RW) - * - * Values: - * - 0 - MA1F interrupt disabled - * - 1 - MA1F interrupt enabled - */ -/*@{*/ -#define BP_LPUART_CTRL_MA1IE (15U) /*!< Bit position for LPUART_CTRL_MA1IE. */ -#define BM_LPUART_CTRL_MA1IE (0x00008000U) /*!< Bit mask for LPUART_CTRL_MA1IE. */ -#define BS_LPUART_CTRL_MA1IE (1U) /*!< Bit field size in bits for LPUART_CTRL_MA1IE. */ - -/*! @brief Read current value of the LPUART_CTRL_MA1IE field. */ -#define BR_LPUART_CTRL_MA1IE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA1IE)) - -/*! @brief Format value for bitfield LPUART_CTRL_MA1IE. */ -#define BF_LPUART_CTRL_MA1IE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_MA1IE) & BM_LPUART_CTRL_MA1IE) - -/*! @brief Set the MA1IE field to a new value. */ -#define BW_LPUART_CTRL_MA1IE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA1IE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field SBK[16] (RW) - * - * Writing a 1 and then a 0 to SBK queues a break character in the transmit data - * stream. Additional break characters of 10 to 13, or 13 to 16 if - * LPUART_STATBRK13] is set, bit times of logic 0 are queued as long as SBK is set. Depending - * on the timing of the set and clear of SBK relative to the information - * currently being transmitted, a second break character may be queued before software - * clears SBK. - * - * Values: - * - 0 - Normal transmitter operation. - * - 1 - Queue break character(s) to be sent. - */ -/*@{*/ -#define BP_LPUART_CTRL_SBK (16U) /*!< Bit position for LPUART_CTRL_SBK. */ -#define BM_LPUART_CTRL_SBK (0x00010000U) /*!< Bit mask for LPUART_CTRL_SBK. */ -#define BS_LPUART_CTRL_SBK (1U) /*!< Bit field size in bits for LPUART_CTRL_SBK. */ - -/*! @brief Read current value of the LPUART_CTRL_SBK field. */ -#define BR_LPUART_CTRL_SBK(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_SBK)) - -/*! @brief Format value for bitfield LPUART_CTRL_SBK. */ -#define BF_LPUART_CTRL_SBK(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_SBK) & BM_LPUART_CTRL_SBK) - -/*! @brief Set the SBK field to a new value. */ -#define BW_LPUART_CTRL_SBK(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_SBK) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field RWU[17] (RW) - * - * This field can be set to place the LPUART receiver in a standby state. RWU - * automatically clears when an RWU event occurs, that is, an IDLE event when - * CTRL[WAKE] is clear or an address match when CTRL[WAKE] is set with STAT[RWUID] is - * clear. RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the - * channel is currently not idle. This can be determined by STAT[RAF]. If the flag is - * set to wake up an IDLE event and the channel is already idle, it is possible - * that the LPUART will discard data. This is because the data must be received or - * a LIN break detected after an IDLE is detected before IDLE is allowed to - * reasserted. - * - * Values: - * - 0 - Normal receiver operation. - * - 1 - LPUART receiver in standby waiting for wakeup condition. - */ -/*@{*/ -#define BP_LPUART_CTRL_RWU (17U) /*!< Bit position for LPUART_CTRL_RWU. */ -#define BM_LPUART_CTRL_RWU (0x00020000U) /*!< Bit mask for LPUART_CTRL_RWU. */ -#define BS_LPUART_CTRL_RWU (1U) /*!< Bit field size in bits for LPUART_CTRL_RWU. */ - -/*! @brief Read current value of the LPUART_CTRL_RWU field. */ -#define BR_LPUART_CTRL_RWU(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RWU)) - -/*! @brief Format value for bitfield LPUART_CTRL_RWU. */ -#define BF_LPUART_CTRL_RWU(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RWU) & BM_LPUART_CTRL_RWU) - -/*! @brief Set the RWU field to a new value. */ -#define BW_LPUART_CTRL_RWU(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RWU) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field RE[18] (RW) - * - * Enables the LPUART receiver. When RE is written to 0, this register bit will - * read as 1 until the receiver finishes receiving the current character (if any). - * - * Values: - * - 0 - Receiver disabled. - * - 1 - Receiver enabled. - */ -/*@{*/ -#define BP_LPUART_CTRL_RE (18U) /*!< Bit position for LPUART_CTRL_RE. */ -#define BM_LPUART_CTRL_RE (0x00040000U) /*!< Bit mask for LPUART_CTRL_RE. */ -#define BS_LPUART_CTRL_RE (1U) /*!< Bit field size in bits for LPUART_CTRL_RE. */ - -/*! @brief Read current value of the LPUART_CTRL_RE field. */ -#define BR_LPUART_CTRL_RE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RE)) - -/*! @brief Format value for bitfield LPUART_CTRL_RE. */ -#define BF_LPUART_CTRL_RE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RE) & BM_LPUART_CTRL_RE) - -/*! @brief Set the RE field to a new value. */ -#define BW_LPUART_CTRL_RE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field TE[19] (RW) - * - * Enables the LPUART transmitter. TE can also be used to queue an idle preamble - * by clearing and then setting TE. When TE is cleared, this register bit will - * read as 1 until the transmitter has completed the current character and the - * LPUART_TX pin is tristated. - * - * Values: - * - 0 - Transmitter disabled. - * - 1 - Transmitter enabled. - */ -/*@{*/ -#define BP_LPUART_CTRL_TE (19U) /*!< Bit position for LPUART_CTRL_TE. */ -#define BM_LPUART_CTRL_TE (0x00080000U) /*!< Bit mask for LPUART_CTRL_TE. */ -#define BS_LPUART_CTRL_TE (1U) /*!< Bit field size in bits for LPUART_CTRL_TE. */ - -/*! @brief Read current value of the LPUART_CTRL_TE field. */ -#define BR_LPUART_CTRL_TE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TE)) - -/*! @brief Format value for bitfield LPUART_CTRL_TE. */ -#define BF_LPUART_CTRL_TE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TE) & BM_LPUART_CTRL_TE) - -/*! @brief Set the TE field to a new value. */ -#define BW_LPUART_CTRL_TE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field ILIE[20] (RW) - * - * ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests. - * - * Values: - * - 0 - Hardware interrupts from IDLE disabled; use polling. - * - 1 - Hardware interrupt requested when IDLE flag is 1. - */ -/*@{*/ -#define BP_LPUART_CTRL_ILIE (20U) /*!< Bit position for LPUART_CTRL_ILIE. */ -#define BM_LPUART_CTRL_ILIE (0x00100000U) /*!< Bit mask for LPUART_CTRL_ILIE. */ -#define BS_LPUART_CTRL_ILIE (1U) /*!< Bit field size in bits for LPUART_CTRL_ILIE. */ - -/*! @brief Read current value of the LPUART_CTRL_ILIE field. */ -#define BR_LPUART_CTRL_ILIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_ILIE. */ -#define BF_LPUART_CTRL_ILIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_ILIE) & BM_LPUART_CTRL_ILIE) - -/*! @brief Set the ILIE field to a new value. */ -#define BW_LPUART_CTRL_ILIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field RIE[21] (RW) - * - * Enables STAT[RDRF] to generate interrupt requests. - * - * Values: - * - 0 - Hardware interrupts from RDRF disabled; use polling. - * - 1 - Hardware interrupt requested when RDRF flag is 1. - */ -/*@{*/ -#define BP_LPUART_CTRL_RIE (21U) /*!< Bit position for LPUART_CTRL_RIE. */ -#define BM_LPUART_CTRL_RIE (0x00200000U) /*!< Bit mask for LPUART_CTRL_RIE. */ -#define BS_LPUART_CTRL_RIE (1U) /*!< Bit field size in bits for LPUART_CTRL_RIE. */ - -/*! @brief Read current value of the LPUART_CTRL_RIE field. */ -#define BR_LPUART_CTRL_RIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_RIE. */ -#define BF_LPUART_CTRL_RIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RIE) & BM_LPUART_CTRL_RIE) - -/*! @brief Set the RIE field to a new value. */ -#define BW_LPUART_CTRL_RIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field TCIE[22] (RW) - * - * TCIE enables the transmission complete flag, TC, to generate interrupt - * requests. - * - * Values: - * - 0 - Hardware interrupts from TC disabled; use polling. - * - 1 - Hardware interrupt requested when TC flag is 1. - */ -/*@{*/ -#define BP_LPUART_CTRL_TCIE (22U) /*!< Bit position for LPUART_CTRL_TCIE. */ -#define BM_LPUART_CTRL_TCIE (0x00400000U) /*!< Bit mask for LPUART_CTRL_TCIE. */ -#define BS_LPUART_CTRL_TCIE (1U) /*!< Bit field size in bits for LPUART_CTRL_TCIE. */ - -/*! @brief Read current value of the LPUART_CTRL_TCIE field. */ -#define BR_LPUART_CTRL_TCIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TCIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_TCIE. */ -#define BF_LPUART_CTRL_TCIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TCIE) & BM_LPUART_CTRL_TCIE) - -/*! @brief Set the TCIE field to a new value. */ -#define BW_LPUART_CTRL_TCIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TCIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field TIE[23] (RW) - * - * Enables STAT[TDRE] to generate interrupt requests. - * - * Values: - * - 0 - Hardware interrupts from TDRE disabled; use polling. - * - 1 - Hardware interrupt requested when TDRE flag is 1. - */ -/*@{*/ -#define BP_LPUART_CTRL_TIE (23U) /*!< Bit position for LPUART_CTRL_TIE. */ -#define BM_LPUART_CTRL_TIE (0x00800000U) /*!< Bit mask for LPUART_CTRL_TIE. */ -#define BS_LPUART_CTRL_TIE (1U) /*!< Bit field size in bits for LPUART_CTRL_TIE. */ - -/*! @brief Read current value of the LPUART_CTRL_TIE field. */ -#define BR_LPUART_CTRL_TIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_TIE. */ -#define BF_LPUART_CTRL_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TIE) & BM_LPUART_CTRL_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_LPUART_CTRL_TIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field PEIE[24] (RW) - * - * This bit enables the parity error flag (PF) to generate hardware interrupt - * requests. - * - * Values: - * - 0 - PF interrupts disabled; use polling). - * - 1 - Hardware interrupt requested when PF is set. - */ -/*@{*/ -#define BP_LPUART_CTRL_PEIE (24U) /*!< Bit position for LPUART_CTRL_PEIE. */ -#define BM_LPUART_CTRL_PEIE (0x01000000U) /*!< Bit mask for LPUART_CTRL_PEIE. */ -#define BS_LPUART_CTRL_PEIE (1U) /*!< Bit field size in bits for LPUART_CTRL_PEIE. */ - -/*! @brief Read current value of the LPUART_CTRL_PEIE field. */ -#define BR_LPUART_CTRL_PEIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PEIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_PEIE. */ -#define BF_LPUART_CTRL_PEIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_PEIE) & BM_LPUART_CTRL_PEIE) - -/*! @brief Set the PEIE field to a new value. */ -#define BW_LPUART_CTRL_PEIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PEIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field FEIE[25] (RW) - * - * This bit enables the framing error flag (FE) to generate hardware interrupt - * requests. - * - * Values: - * - 0 - FE interrupts disabled; use polling. - * - 1 - Hardware interrupt requested when FE is set. - */ -/*@{*/ -#define BP_LPUART_CTRL_FEIE (25U) /*!< Bit position for LPUART_CTRL_FEIE. */ -#define BM_LPUART_CTRL_FEIE (0x02000000U) /*!< Bit mask for LPUART_CTRL_FEIE. */ -#define BS_LPUART_CTRL_FEIE (1U) /*!< Bit field size in bits for LPUART_CTRL_FEIE. */ - -/*! @brief Read current value of the LPUART_CTRL_FEIE field. */ -#define BR_LPUART_CTRL_FEIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_FEIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_FEIE. */ -#define BF_LPUART_CTRL_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_FEIE) & BM_LPUART_CTRL_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_LPUART_CTRL_FEIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field NEIE[26] (RW) - * - * This bit enables the noise flag (NF) to generate hardware interrupt requests. - * - * Values: - * - 0 - NF interrupts disabled; use polling. - * - 1 - Hardware interrupt requested when NF is set. - */ -/*@{*/ -#define BP_LPUART_CTRL_NEIE (26U) /*!< Bit position for LPUART_CTRL_NEIE. */ -#define BM_LPUART_CTRL_NEIE (0x04000000U) /*!< Bit mask for LPUART_CTRL_NEIE. */ -#define BS_LPUART_CTRL_NEIE (1U) /*!< Bit field size in bits for LPUART_CTRL_NEIE. */ - -/*! @brief Read current value of the LPUART_CTRL_NEIE field. */ -#define BR_LPUART_CTRL_NEIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_NEIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_NEIE. */ -#define BF_LPUART_CTRL_NEIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_NEIE) & BM_LPUART_CTRL_NEIE) - -/*! @brief Set the NEIE field to a new value. */ -#define BW_LPUART_CTRL_NEIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_NEIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field ORIE[27] (RW) - * - * This bit enables the overrun flag (OR) to generate hardware interrupt - * requests. - * - * Values: - * - 0 - OR interrupts disabled; use polling. - * - 1 - Hardware interrupt requested when OR is set. - */ -/*@{*/ -#define BP_LPUART_CTRL_ORIE (27U) /*!< Bit position for LPUART_CTRL_ORIE. */ -#define BM_LPUART_CTRL_ORIE (0x08000000U) /*!< Bit mask for LPUART_CTRL_ORIE. */ -#define BS_LPUART_CTRL_ORIE (1U) /*!< Bit field size in bits for LPUART_CTRL_ORIE. */ - -/*! @brief Read current value of the LPUART_CTRL_ORIE field. */ -#define BR_LPUART_CTRL_ORIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ORIE)) - -/*! @brief Format value for bitfield LPUART_CTRL_ORIE. */ -#define BF_LPUART_CTRL_ORIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_ORIE) & BM_LPUART_CTRL_ORIE) - -/*! @brief Set the ORIE field to a new value. */ -#define BW_LPUART_CTRL_ORIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ORIE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field TXINV[28] (RW) - * - * Setting this bit reverses the polarity of the transmitted data output. - * Setting TXINV inverts the LPUART_TX output for all cases: data bits, start and stop - * bits, break, and idle. - * - * Values: - * - 0 - Transmit data not inverted. - * - 1 - Transmit data inverted. - */ -/*@{*/ -#define BP_LPUART_CTRL_TXINV (28U) /*!< Bit position for LPUART_CTRL_TXINV. */ -#define BM_LPUART_CTRL_TXINV (0x10000000U) /*!< Bit mask for LPUART_CTRL_TXINV. */ -#define BS_LPUART_CTRL_TXINV (1U) /*!< Bit field size in bits for LPUART_CTRL_TXINV. */ - -/*! @brief Read current value of the LPUART_CTRL_TXINV field. */ -#define BR_LPUART_CTRL_TXINV(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXINV)) - -/*! @brief Format value for bitfield LPUART_CTRL_TXINV. */ -#define BF_LPUART_CTRL_TXINV(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TXINV) & BM_LPUART_CTRL_TXINV) - -/*! @brief Set the TXINV field to a new value. */ -#define BW_LPUART_CTRL_TXINV(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXINV) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field TXDIR[29] (RW) - * - * When the LPUART is configured for single-wire half-duplex operation (LOOPS = - * RSRC = 1), this bit determines the direction of data at the LPUART_TX pin. - * When clearing TXDIR, the transmitter will finish receiving the current character - * (if any) before the receiver starts receiving data from the LPUART_TX pin. - * - * Values: - * - 0 - LPUART_TX pin is an input in single-wire mode. - * - 1 - LPUART_TX pin is an output in single-wire mode. - */ -/*@{*/ -#define BP_LPUART_CTRL_TXDIR (29U) /*!< Bit position for LPUART_CTRL_TXDIR. */ -#define BM_LPUART_CTRL_TXDIR (0x20000000U) /*!< Bit mask for LPUART_CTRL_TXDIR. */ -#define BS_LPUART_CTRL_TXDIR (1U) /*!< Bit field size in bits for LPUART_CTRL_TXDIR. */ - -/*! @brief Read current value of the LPUART_CTRL_TXDIR field. */ -#define BR_LPUART_CTRL_TXDIR(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXDIR)) - -/*! @brief Format value for bitfield LPUART_CTRL_TXDIR. */ -#define BF_LPUART_CTRL_TXDIR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TXDIR) & BM_LPUART_CTRL_TXDIR) - -/*! @brief Set the TXDIR field to a new value. */ -#define BW_LPUART_CTRL_TXDIR(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXDIR) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field R9T8[30] (RW) - * - * R9 is the tenth data bit received when the LPUART is configured for 10-bit - * data formats. When reading 10-bit data, read R9 before reading LPUART_DATA T8 is - * the ninth data bit received when the LPUART is configured for 9-bit or 10-bit - * data formats. When writing 9-bit or 10-bit data, write T8 before writing - * LPUART_DATA. If T8 does not need to change from its previous value, such as when - * it is used to generate address mark or parity, they it need not be written each - * time LPUART_DATA is written. - */ -/*@{*/ -#define BP_LPUART_CTRL_R9T8 (30U) /*!< Bit position for LPUART_CTRL_R9T8. */ -#define BM_LPUART_CTRL_R9T8 (0x40000000U) /*!< Bit mask for LPUART_CTRL_R9T8. */ -#define BS_LPUART_CTRL_R9T8 (1U) /*!< Bit field size in bits for LPUART_CTRL_R9T8. */ - -/*! @brief Read current value of the LPUART_CTRL_R9T8 field. */ -#define BR_LPUART_CTRL_R9T8(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R9T8)) - -/*! @brief Format value for bitfield LPUART_CTRL_R9T8. */ -#define BF_LPUART_CTRL_R9T8(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_R9T8) & BM_LPUART_CTRL_R9T8) - -/*! @brief Set the R9T8 field to a new value. */ -#define BW_LPUART_CTRL_R9T8(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R9T8) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_CTRL, field R8T9[31] (RW) - * - * R8 is the ninth data bit received when the LPUART is configured for 9-bit or - * 10-bit data formats. When reading 9-bit or 10-bit data, read R8 before reading - * LPUART_DATA. T9 is the tenth data bit received when the LPUART is configured - * for 10-bit data formats. When writing 10-bit data, write T9 before writing - * LPUART_DATA. If T9 does not need to change from its previous value, such as when - * it is used to generate address mark or parity, they it need not be written - * each time LPUART_DATA is written. - */ -/*@{*/ -#define BP_LPUART_CTRL_R8T9 (31U) /*!< Bit position for LPUART_CTRL_R8T9. */ -#define BM_LPUART_CTRL_R8T9 (0x80000000U) /*!< Bit mask for LPUART_CTRL_R8T9. */ -#define BS_LPUART_CTRL_R8T9 (1U) /*!< Bit field size in bits for LPUART_CTRL_R8T9. */ - -/*! @brief Read current value of the LPUART_CTRL_R8T9 field. */ -#define BR_LPUART_CTRL_R8T9(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R8T9)) - -/*! @brief Format value for bitfield LPUART_CTRL_R8T9. */ -#define BF_LPUART_CTRL_R8T9(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_R8T9) & BM_LPUART_CTRL_R8T9) - -/*! @brief Set the R8T9 field to a new value. */ -#define BW_LPUART_CTRL_R8T9(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R8T9) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LPUART_DATA - LPUART Data Register - ******************************************************************************/ - -/*! - * @brief HW_LPUART_DATA - LPUART Data Register (RW) - * - * Reset value: 0x00001000U - * - * This register is actually two separate registers. Reads return the contents - * of the read-only receive data buffer and writes go to the write-only transmit - * data buffer. Reads and writes of this register are also involved in the - * automatic flag clearing mechanisms for some of the LPUART status flags. - */ -typedef union _hw_lpuart_data -{ - uint32_t U; - struct _hw_lpuart_data_bitfields - { - uint32_t R0T0 : 1; /*!< [0] */ - uint32_t R1T1 : 1; /*!< [1] */ - uint32_t R2T2 : 1; /*!< [2] */ - uint32_t R3T3 : 1; /*!< [3] */ - uint32_t R4T4 : 1; /*!< [4] */ - uint32_t R5T5 : 1; /*!< [5] */ - uint32_t R6T6 : 1; /*!< [6] */ - uint32_t R7T7 : 1; /*!< [7] */ - uint32_t R8T8 : 1; /*!< [8] */ - uint32_t R9T9 : 1; /*!< [9] */ - uint32_t RESERVED0 : 1; /*!< [10] */ - uint32_t IDLINE : 1; /*!< [11] Idle Line */ - uint32_t RXEMPT : 1; /*!< [12] Receive Buffer Empty */ - uint32_t FRETSC : 1; /*!< [13] Frame Error / Transmit Special - * Character */ - uint32_t PARITYE : 1; /*!< [14] */ - uint32_t NOISY : 1; /*!< [15] */ - uint32_t RESERVED1 : 16; /*!< [31:16] */ - } B; -} hw_lpuart_data_t; - -/*! - * @name Constants and macros for entire LPUART_DATA register - */ -/*@{*/ -#define HW_LPUART_DATA_ADDR(x) ((x) + 0xCU) - -#define HW_LPUART_DATA(x) (*(__IO hw_lpuart_data_t *) HW_LPUART_DATA_ADDR(x)) -#define HW_LPUART_DATA_RD(x) (HW_LPUART_DATA(x).U) -#define HW_LPUART_DATA_WR(x, v) (HW_LPUART_DATA(x).U = (v)) -#define HW_LPUART_DATA_SET(x, v) (HW_LPUART_DATA_WR(x, HW_LPUART_DATA_RD(x) | (v))) -#define HW_LPUART_DATA_CLR(x, v) (HW_LPUART_DATA_WR(x, HW_LPUART_DATA_RD(x) & ~(v))) -#define HW_LPUART_DATA_TOG(x, v) (HW_LPUART_DATA_WR(x, HW_LPUART_DATA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPUART_DATA bitfields - */ - -/*! - * @name Register LPUART_DATA, field R0T0[0] (RW) - * - * Read receive data buffer 0 or write transmit data buffer 0. - */ -/*@{*/ -#define BP_LPUART_DATA_R0T0 (0U) /*!< Bit position for LPUART_DATA_R0T0. */ -#define BM_LPUART_DATA_R0T0 (0x00000001U) /*!< Bit mask for LPUART_DATA_R0T0. */ -#define BS_LPUART_DATA_R0T0 (1U) /*!< Bit field size in bits for LPUART_DATA_R0T0. */ - -/*! @brief Read current value of the LPUART_DATA_R0T0 field. */ -#define BR_LPUART_DATA_R0T0(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R0T0)) - -/*! @brief Format value for bitfield LPUART_DATA_R0T0. */ -#define BF_LPUART_DATA_R0T0(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R0T0) & BM_LPUART_DATA_R0T0) - -/*! @brief Set the R0T0 field to a new value. */ -#define BW_LPUART_DATA_R0T0(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R0T0) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R1T1[1] (RW) - * - * Read receive data buffer 1 or write transmit data buffer 1. - */ -/*@{*/ -#define BP_LPUART_DATA_R1T1 (1U) /*!< Bit position for LPUART_DATA_R1T1. */ -#define BM_LPUART_DATA_R1T1 (0x00000002U) /*!< Bit mask for LPUART_DATA_R1T1. */ -#define BS_LPUART_DATA_R1T1 (1U) /*!< Bit field size in bits for LPUART_DATA_R1T1. */ - -/*! @brief Read current value of the LPUART_DATA_R1T1 field. */ -#define BR_LPUART_DATA_R1T1(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R1T1)) - -/*! @brief Format value for bitfield LPUART_DATA_R1T1. */ -#define BF_LPUART_DATA_R1T1(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R1T1) & BM_LPUART_DATA_R1T1) - -/*! @brief Set the R1T1 field to a new value. */ -#define BW_LPUART_DATA_R1T1(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R1T1) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R2T2[2] (RW) - * - * Read receive data buffer 2 or write transmit data buffer 2. - */ -/*@{*/ -#define BP_LPUART_DATA_R2T2 (2U) /*!< Bit position for LPUART_DATA_R2T2. */ -#define BM_LPUART_DATA_R2T2 (0x00000004U) /*!< Bit mask for LPUART_DATA_R2T2. */ -#define BS_LPUART_DATA_R2T2 (1U) /*!< Bit field size in bits for LPUART_DATA_R2T2. */ - -/*! @brief Read current value of the LPUART_DATA_R2T2 field. */ -#define BR_LPUART_DATA_R2T2(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R2T2)) - -/*! @brief Format value for bitfield LPUART_DATA_R2T2. */ -#define BF_LPUART_DATA_R2T2(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R2T2) & BM_LPUART_DATA_R2T2) - -/*! @brief Set the R2T2 field to a new value. */ -#define BW_LPUART_DATA_R2T2(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R2T2) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R3T3[3] (RW) - * - * Read receive data buffer 3 or write transmit data buffer 3. - */ -/*@{*/ -#define BP_LPUART_DATA_R3T3 (3U) /*!< Bit position for LPUART_DATA_R3T3. */ -#define BM_LPUART_DATA_R3T3 (0x00000008U) /*!< Bit mask for LPUART_DATA_R3T3. */ -#define BS_LPUART_DATA_R3T3 (1U) /*!< Bit field size in bits for LPUART_DATA_R3T3. */ - -/*! @brief Read current value of the LPUART_DATA_R3T3 field. */ -#define BR_LPUART_DATA_R3T3(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R3T3)) - -/*! @brief Format value for bitfield LPUART_DATA_R3T3. */ -#define BF_LPUART_DATA_R3T3(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R3T3) & BM_LPUART_DATA_R3T3) - -/*! @brief Set the R3T3 field to a new value. */ -#define BW_LPUART_DATA_R3T3(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R3T3) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R4T4[4] (RW) - * - * Read receive data buffer 4 or write transmit data buffer 4. - */ -/*@{*/ -#define BP_LPUART_DATA_R4T4 (4U) /*!< Bit position for LPUART_DATA_R4T4. */ -#define BM_LPUART_DATA_R4T4 (0x00000010U) /*!< Bit mask for LPUART_DATA_R4T4. */ -#define BS_LPUART_DATA_R4T4 (1U) /*!< Bit field size in bits for LPUART_DATA_R4T4. */ - -/*! @brief Read current value of the LPUART_DATA_R4T4 field. */ -#define BR_LPUART_DATA_R4T4(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R4T4)) - -/*! @brief Format value for bitfield LPUART_DATA_R4T4. */ -#define BF_LPUART_DATA_R4T4(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R4T4) & BM_LPUART_DATA_R4T4) - -/*! @brief Set the R4T4 field to a new value. */ -#define BW_LPUART_DATA_R4T4(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R4T4) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R5T5[5] (RW) - * - * Read receive data buffer 5 or write transmit data buffer 5. - */ -/*@{*/ -#define BP_LPUART_DATA_R5T5 (5U) /*!< Bit position for LPUART_DATA_R5T5. */ -#define BM_LPUART_DATA_R5T5 (0x00000020U) /*!< Bit mask for LPUART_DATA_R5T5. */ -#define BS_LPUART_DATA_R5T5 (1U) /*!< Bit field size in bits for LPUART_DATA_R5T5. */ - -/*! @brief Read current value of the LPUART_DATA_R5T5 field. */ -#define BR_LPUART_DATA_R5T5(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R5T5)) - -/*! @brief Format value for bitfield LPUART_DATA_R5T5. */ -#define BF_LPUART_DATA_R5T5(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R5T5) & BM_LPUART_DATA_R5T5) - -/*! @brief Set the R5T5 field to a new value. */ -#define BW_LPUART_DATA_R5T5(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R5T5) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R6T6[6] (RW) - * - * Read receive data buffer 6 or write transmit data buffer 6. - */ -/*@{*/ -#define BP_LPUART_DATA_R6T6 (6U) /*!< Bit position for LPUART_DATA_R6T6. */ -#define BM_LPUART_DATA_R6T6 (0x00000040U) /*!< Bit mask for LPUART_DATA_R6T6. */ -#define BS_LPUART_DATA_R6T6 (1U) /*!< Bit field size in bits for LPUART_DATA_R6T6. */ - -/*! @brief Read current value of the LPUART_DATA_R6T6 field. */ -#define BR_LPUART_DATA_R6T6(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R6T6)) - -/*! @brief Format value for bitfield LPUART_DATA_R6T6. */ -#define BF_LPUART_DATA_R6T6(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R6T6) & BM_LPUART_DATA_R6T6) - -/*! @brief Set the R6T6 field to a new value. */ -#define BW_LPUART_DATA_R6T6(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R6T6) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R7T7[7] (RW) - * - * Read receive data buffer 7 or write transmit data buffer 7. - */ -/*@{*/ -#define BP_LPUART_DATA_R7T7 (7U) /*!< Bit position for LPUART_DATA_R7T7. */ -#define BM_LPUART_DATA_R7T7 (0x00000080U) /*!< Bit mask for LPUART_DATA_R7T7. */ -#define BS_LPUART_DATA_R7T7 (1U) /*!< Bit field size in bits for LPUART_DATA_R7T7. */ - -/*! @brief Read current value of the LPUART_DATA_R7T7 field. */ -#define BR_LPUART_DATA_R7T7(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R7T7)) - -/*! @brief Format value for bitfield LPUART_DATA_R7T7. */ -#define BF_LPUART_DATA_R7T7(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R7T7) & BM_LPUART_DATA_R7T7) - -/*! @brief Set the R7T7 field to a new value. */ -#define BW_LPUART_DATA_R7T7(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R7T7) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R8T8[8] (RW) - * - * Read receive data buffer 8 or write transmit data buffer 8. - */ -/*@{*/ -#define BP_LPUART_DATA_R8T8 (8U) /*!< Bit position for LPUART_DATA_R8T8. */ -#define BM_LPUART_DATA_R8T8 (0x00000100U) /*!< Bit mask for LPUART_DATA_R8T8. */ -#define BS_LPUART_DATA_R8T8 (1U) /*!< Bit field size in bits for LPUART_DATA_R8T8. */ - -/*! @brief Read current value of the LPUART_DATA_R8T8 field. */ -#define BR_LPUART_DATA_R8T8(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R8T8)) - -/*! @brief Format value for bitfield LPUART_DATA_R8T8. */ -#define BF_LPUART_DATA_R8T8(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R8T8) & BM_LPUART_DATA_R8T8) - -/*! @brief Set the R8T8 field to a new value. */ -#define BW_LPUART_DATA_R8T8(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R8T8) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field R9T9[9] (RW) - * - * Read receive data buffer 9 or write transmit data buffer 9. - */ -/*@{*/ -#define BP_LPUART_DATA_R9T9 (9U) /*!< Bit position for LPUART_DATA_R9T9. */ -#define BM_LPUART_DATA_R9T9 (0x00000200U) /*!< Bit mask for LPUART_DATA_R9T9. */ -#define BS_LPUART_DATA_R9T9 (1U) /*!< Bit field size in bits for LPUART_DATA_R9T9. */ - -/*! @brief Read current value of the LPUART_DATA_R9T9 field. */ -#define BR_LPUART_DATA_R9T9(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R9T9)) - -/*! @brief Format value for bitfield LPUART_DATA_R9T9. */ -#define BF_LPUART_DATA_R9T9(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R9T9) & BM_LPUART_DATA_R9T9) - -/*! @brief Set the R9T9 field to a new value. */ -#define BW_LPUART_DATA_R9T9(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R9T9) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field IDLINE[11] (RO) - * - * Indicates the receiver line was idle before receiving the character in - * DATA[9:0]. Unlike the IDLE flag, this bit can set for the first character received - * when the receiver is first enabled. - * - * Values: - * - 0 - Receiver was not idle before receiving this character. - * - 1 - Receiver was idle before receiving this character. - */ -/*@{*/ -#define BP_LPUART_DATA_IDLINE (11U) /*!< Bit position for LPUART_DATA_IDLINE. */ -#define BM_LPUART_DATA_IDLINE (0x00000800U) /*!< Bit mask for LPUART_DATA_IDLINE. */ -#define BS_LPUART_DATA_IDLINE (1U) /*!< Bit field size in bits for LPUART_DATA_IDLINE. */ - -/*! @brief Read current value of the LPUART_DATA_IDLINE field. */ -#define BR_LPUART_DATA_IDLINE(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_IDLINE)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field RXEMPT[12] (RO) - * - * Asserts when there is no data in the receive buffer. This field does not take - * into account data that is in the receive shift register. - * - * Values: - * - 0 - Receive buffer contains valid data. - * - 1 - Receive buffer is empty, data returned on read is not valid. - */ -/*@{*/ -#define BP_LPUART_DATA_RXEMPT (12U) /*!< Bit position for LPUART_DATA_RXEMPT. */ -#define BM_LPUART_DATA_RXEMPT (0x00001000U) /*!< Bit mask for LPUART_DATA_RXEMPT. */ -#define BS_LPUART_DATA_RXEMPT (1U) /*!< Bit field size in bits for LPUART_DATA_RXEMPT. */ - -/*! @brief Read current value of the LPUART_DATA_RXEMPT field. */ -#define BR_LPUART_DATA_RXEMPT(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_RXEMPT)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field FRETSC[13] (RW) - * - * For reads, indicates the current received dataword contained in DATA[R9:R0] - * was received with a frame error. For writes, indicates a break or idle - * character is to be transmitted instead of the contents in DATA[T9:T0]. T9 is used to - * indicate a break character when 0 and a idle character when 1, he contents of - * DATA[T8:T0] should be zero. - * - * Values: - * - 0 - The dataword was received without a frame error on read, transmit a - * normal character on write. - * - 1 - The dataword was received with a frame error, transmit an idle or break - * character on transmit. - */ -/*@{*/ -#define BP_LPUART_DATA_FRETSC (13U) /*!< Bit position for LPUART_DATA_FRETSC. */ -#define BM_LPUART_DATA_FRETSC (0x00002000U) /*!< Bit mask for LPUART_DATA_FRETSC. */ -#define BS_LPUART_DATA_FRETSC (1U) /*!< Bit field size in bits for LPUART_DATA_FRETSC. */ - -/*! @brief Read current value of the LPUART_DATA_FRETSC field. */ -#define BR_LPUART_DATA_FRETSC(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_FRETSC)) - -/*! @brief Format value for bitfield LPUART_DATA_FRETSC. */ -#define BF_LPUART_DATA_FRETSC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_FRETSC) & BM_LPUART_DATA_FRETSC) - -/*! @brief Set the FRETSC field to a new value. */ -#define BW_LPUART_DATA_FRETSC(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_FRETSC) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field PARITYE[14] (RO) - * - * The current received dataword contained in DATA[R9:R0] was received with a - * parity error. - * - * Values: - * - 0 - The dataword was received without a parity error. - * - 1 - The dataword was received with a parity error. - */ -/*@{*/ -#define BP_LPUART_DATA_PARITYE (14U) /*!< Bit position for LPUART_DATA_PARITYE. */ -#define BM_LPUART_DATA_PARITYE (0x00004000U) /*!< Bit mask for LPUART_DATA_PARITYE. */ -#define BS_LPUART_DATA_PARITYE (1U) /*!< Bit field size in bits for LPUART_DATA_PARITYE. */ - -/*! @brief Read current value of the LPUART_DATA_PARITYE field. */ -#define BR_LPUART_DATA_PARITYE(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_PARITYE)) -/*@}*/ - -/*! - * @name Register LPUART_DATA, field NOISY[15] (RO) - * - * The current received dataword contained in DATA[R9:R0] was received with - * noise. - * - * Values: - * - 0 - The dataword was received without noise. - * - 1 - The data was received with noise. - */ -/*@{*/ -#define BP_LPUART_DATA_NOISY (15U) /*!< Bit position for LPUART_DATA_NOISY. */ -#define BM_LPUART_DATA_NOISY (0x00008000U) /*!< Bit mask for LPUART_DATA_NOISY. */ -#define BS_LPUART_DATA_NOISY (1U) /*!< Bit field size in bits for LPUART_DATA_NOISY. */ - -/*! @brief Read current value of the LPUART_DATA_NOISY field. */ -#define BR_LPUART_DATA_NOISY(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_NOISY)) -/*@}*/ - -/******************************************************************************* - * HW_LPUART_MATCH - LPUART Match Address Register - ******************************************************************************/ - -/*! - * @brief HW_LPUART_MATCH - LPUART Match Address Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lpuart_match -{ - uint32_t U; - struct _hw_lpuart_match_bitfields - { - uint32_t MA1 : 10; /*!< [9:0] Match Address 1 */ - uint32_t RESERVED0 : 6; /*!< [15:10] */ - uint32_t MA2 : 10; /*!< [25:16] Match Address 2 */ - uint32_t RESERVED1 : 6; /*!< [31:26] */ - } B; -} hw_lpuart_match_t; - -/*! - * @name Constants and macros for entire LPUART_MATCH register - */ -/*@{*/ -#define HW_LPUART_MATCH_ADDR(x) ((x) + 0x10U) - -#define HW_LPUART_MATCH(x) (*(__IO hw_lpuart_match_t *) HW_LPUART_MATCH_ADDR(x)) -#define HW_LPUART_MATCH_RD(x) (HW_LPUART_MATCH(x).U) -#define HW_LPUART_MATCH_WR(x, v) (HW_LPUART_MATCH(x).U = (v)) -#define HW_LPUART_MATCH_SET(x, v) (HW_LPUART_MATCH_WR(x, HW_LPUART_MATCH_RD(x) | (v))) -#define HW_LPUART_MATCH_CLR(x, v) (HW_LPUART_MATCH_WR(x, HW_LPUART_MATCH_RD(x) & ~(v))) -#define HW_LPUART_MATCH_TOG(x, v) (HW_LPUART_MATCH_WR(x, HW_LPUART_MATCH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPUART_MATCH bitfields - */ - -/*! - * @name Register LPUART_MATCH, field MA1[9:0] (RW) - * - * The MA1 and MA2 registers are compared to input data addresses when the most - * significant bit is set and the associated BAUD[MAEN] bit is set. If a match - * occurs, the following data is transferred to the data register. If a match - * fails, the following data is discarded. Software should only write a MA register - * when the associated BAUD[MAEN] bit is clear. - */ -/*@{*/ -#define BP_LPUART_MATCH_MA1 (0U) /*!< Bit position for LPUART_MATCH_MA1. */ -#define BM_LPUART_MATCH_MA1 (0x000003FFU) /*!< Bit mask for LPUART_MATCH_MA1. */ -#define BS_LPUART_MATCH_MA1 (10U) /*!< Bit field size in bits for LPUART_MATCH_MA1. */ - -/*! @brief Read current value of the LPUART_MATCH_MA1 field. */ -#define BR_LPUART_MATCH_MA1(x) (HW_LPUART_MATCH(x).B.MA1) - -/*! @brief Format value for bitfield LPUART_MATCH_MA1. */ -#define BF_LPUART_MATCH_MA1(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MATCH_MA1) & BM_LPUART_MATCH_MA1) - -/*! @brief Set the MA1 field to a new value. */ -#define BW_LPUART_MATCH_MA1(x, v) (HW_LPUART_MATCH_WR(x, (HW_LPUART_MATCH_RD(x) & ~BM_LPUART_MATCH_MA1) | BF_LPUART_MATCH_MA1(v))) -/*@}*/ - -/*! - * @name Register LPUART_MATCH, field MA2[25:16] (RW) - * - * The MA1 and MA2 registers are compared to input data addresses when the most - * significant bit is set and the associated BAUD[MAEN] bit is set. If a match - * occurs, the following data is transferred to the data register. If a match - * fails, the following data is discarded. Software should only write a MA register - * when the associated BAUD[MAEN] bit is clear. - */ -/*@{*/ -#define BP_LPUART_MATCH_MA2 (16U) /*!< Bit position for LPUART_MATCH_MA2. */ -#define BM_LPUART_MATCH_MA2 (0x03FF0000U) /*!< Bit mask for LPUART_MATCH_MA2. */ -#define BS_LPUART_MATCH_MA2 (10U) /*!< Bit field size in bits for LPUART_MATCH_MA2. */ - -/*! @brief Read current value of the LPUART_MATCH_MA2 field. */ -#define BR_LPUART_MATCH_MA2(x) (HW_LPUART_MATCH(x).B.MA2) - -/*! @brief Format value for bitfield LPUART_MATCH_MA2. */ -#define BF_LPUART_MATCH_MA2(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MATCH_MA2) & BM_LPUART_MATCH_MA2) - -/*! @brief Set the MA2 field to a new value. */ -#define BW_LPUART_MATCH_MA2(x, v) (HW_LPUART_MATCH_WR(x, (HW_LPUART_MATCH_RD(x) & ~BM_LPUART_MATCH_MA2) | BF_LPUART_MATCH_MA2(v))) -/*@}*/ - -/******************************************************************************* - * HW_LPUART_MODIR - LPUART Modem IrDA Register - ******************************************************************************/ - -/*! - * @brief HW_LPUART_MODIR - LPUART Modem IrDA Register (RW) - * - * Reset value: 0x00000000U - * - * The MODEM register controls options for setting the modem configuration. - */ -typedef union _hw_lpuart_modir -{ - uint32_t U; - struct _hw_lpuart_modir_bitfields - { - uint32_t TXCTSE : 1; /*!< [0] Transmitter clear-to-send enable */ - uint32_t TXRTSE : 1; /*!< [1] Transmitter request-to-send enable */ - uint32_t TXRTSPOL : 1; /*!< [2] Transmitter request-to-send polarity - * */ - uint32_t RXRTSE : 1; /*!< [3] Receiver request-to-send enable */ - uint32_t TXCTSC : 1; /*!< [4] Transmit CTS Configuration */ - uint32_t TXCTSSRC : 1; /*!< [5] Transmit CTS Source */ - uint32_t RESERVED0 : 10; /*!< [15:6] */ - uint32_t TNP : 2; /*!< [17:16] Transmitter narrow pulse */ - uint32_t IREN : 1; /*!< [18] Infrared enable */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_lpuart_modir_t; - -/*! - * @name Constants and macros for entire LPUART_MODIR register - */ -/*@{*/ -#define HW_LPUART_MODIR_ADDR(x) ((x) + 0x14U) - -#define HW_LPUART_MODIR(x) (*(__IO hw_lpuart_modir_t *) HW_LPUART_MODIR_ADDR(x)) -#define HW_LPUART_MODIR_RD(x) (HW_LPUART_MODIR(x).U) -#define HW_LPUART_MODIR_WR(x, v) (HW_LPUART_MODIR(x).U = (v)) -#define HW_LPUART_MODIR_SET(x, v) (HW_LPUART_MODIR_WR(x, HW_LPUART_MODIR_RD(x) | (v))) -#define HW_LPUART_MODIR_CLR(x, v) (HW_LPUART_MODIR_WR(x, HW_LPUART_MODIR_RD(x) & ~(v))) -#define HW_LPUART_MODIR_TOG(x, v) (HW_LPUART_MODIR_WR(x, HW_LPUART_MODIR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPUART_MODIR bitfields - */ - -/*! - * @name Register LPUART_MODIR, field TXCTSE[0] (RW) - * - * TXCTSE controls the operation of the transmitter. TXCTSE can be set - * independently from the state of TXRTSE and RXRTSE. - * - * Values: - * - 0 - CTS has no effect on the transmitter. - * - 1 - Enables clear-to-send operation. The transmitter checks the state of - * CTS each time it is ready to send a character. If CTS is asserted, the - * character is sent. If CTS is deasserted, the signal TXD remains in the mark - * state and transmission is delayed until CTS is asserted. Changes in CTS as a - * character is being sent do not affect its transmission. - */ -/*@{*/ -#define BP_LPUART_MODIR_TXCTSE (0U) /*!< Bit position for LPUART_MODIR_TXCTSE. */ -#define BM_LPUART_MODIR_TXCTSE (0x00000001U) /*!< Bit mask for LPUART_MODIR_TXCTSE. */ -#define BS_LPUART_MODIR_TXCTSE (1U) /*!< Bit field size in bits for LPUART_MODIR_TXCTSE. */ - -/*! @brief Read current value of the LPUART_MODIR_TXCTSE field. */ -#define BR_LPUART_MODIR_TXCTSE(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSE)) - -/*! @brief Format value for bitfield LPUART_MODIR_TXCTSE. */ -#define BF_LPUART_MODIR_TXCTSE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXCTSE) & BM_LPUART_MODIR_TXCTSE) - -/*! @brief Set the TXCTSE field to a new value. */ -#define BW_LPUART_MODIR_TXCTSE(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field TXRTSE[1] (RW) - * - * Controls RTS before and after a transmission. - * - * Values: - * - 0 - The transmitter has no effect on RTS. - * - 1 - When a character is placed into an empty transmitter data buffer , RTS - * asserts one bit time before the start bit is transmitted. RTS deasserts - * one bit time after all characters in the transmitter data buffer and shift - * register are completely sent, including the last stop bit. - */ -/*@{*/ -#define BP_LPUART_MODIR_TXRTSE (1U) /*!< Bit position for LPUART_MODIR_TXRTSE. */ -#define BM_LPUART_MODIR_TXRTSE (0x00000002U) /*!< Bit mask for LPUART_MODIR_TXRTSE. */ -#define BS_LPUART_MODIR_TXRTSE (1U) /*!< Bit field size in bits for LPUART_MODIR_TXRTSE. */ - -/*! @brief Read current value of the LPUART_MODIR_TXRTSE field. */ -#define BR_LPUART_MODIR_TXRTSE(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSE)) - -/*! @brief Format value for bitfield LPUART_MODIR_TXRTSE. */ -#define BF_LPUART_MODIR_TXRTSE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXRTSE) & BM_LPUART_MODIR_TXRTSE) - -/*! @brief Set the TXRTSE field to a new value. */ -#define BW_LPUART_MODIR_TXRTSE(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field TXRTSPOL[2] (RW) - * - * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the - * polarity of the receiver RTS. RTS will remain negated in the active low state - * unless TXRTSE is set. - * - * Values: - * - 0 - Transmitter RTS is active low. - * - 1 - Transmitter RTS is active high. - */ -/*@{*/ -#define BP_LPUART_MODIR_TXRTSPOL (2U) /*!< Bit position for LPUART_MODIR_TXRTSPOL. */ -#define BM_LPUART_MODIR_TXRTSPOL (0x00000004U) /*!< Bit mask for LPUART_MODIR_TXRTSPOL. */ -#define BS_LPUART_MODIR_TXRTSPOL (1U) /*!< Bit field size in bits for LPUART_MODIR_TXRTSPOL. */ - -/*! @brief Read current value of the LPUART_MODIR_TXRTSPOL field. */ -#define BR_LPUART_MODIR_TXRTSPOL(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSPOL)) - -/*! @brief Format value for bitfield LPUART_MODIR_TXRTSPOL. */ -#define BF_LPUART_MODIR_TXRTSPOL(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXRTSPOL) & BM_LPUART_MODIR_TXRTSPOL) - -/*! @brief Set the TXRTSPOL field to a new value. */ -#define BW_LPUART_MODIR_TXRTSPOL(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSPOL) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field RXRTSE[3] (RW) - * - * Allows the RTS output to control the CTS input of the transmitting device to - * prevent receiver overrun. Do not set both RXRTSE and TXRTSE. - * - * Values: - * - 0 - The receiver has no effect on RTS. - * - 1 - RTS is deasserted if the receiver data register is full or a start bit - * has been detected that would cause the receiver data register to become - * full. RTS is asserted if the receiver data register is not full and has not - * detected a start bit that would cause the receiver data register to become - * full. - */ -/*@{*/ -#define BP_LPUART_MODIR_RXRTSE (3U) /*!< Bit position for LPUART_MODIR_RXRTSE. */ -#define BM_LPUART_MODIR_RXRTSE (0x00000008U) /*!< Bit mask for LPUART_MODIR_RXRTSE. */ -#define BS_LPUART_MODIR_RXRTSE (1U) /*!< Bit field size in bits for LPUART_MODIR_RXRTSE. */ - -/*! @brief Read current value of the LPUART_MODIR_RXRTSE field. */ -#define BR_LPUART_MODIR_RXRTSE(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_RXRTSE)) - -/*! @brief Format value for bitfield LPUART_MODIR_RXRTSE. */ -#define BF_LPUART_MODIR_RXRTSE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_RXRTSE) & BM_LPUART_MODIR_RXRTSE) - -/*! @brief Set the RXRTSE field to a new value. */ -#define BW_LPUART_MODIR_RXRTSE(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_RXRTSE) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field TXCTSC[4] (RW) - * - * Configures if the CTS state is checked at the start of each character or only - * when the transmitter is idle. - * - * Values: - * - 0 - CTS input is sampled at the start of each character. - * - 1 - CTS input is sampled when the transmitter is idle. - */ -/*@{*/ -#define BP_LPUART_MODIR_TXCTSC (4U) /*!< Bit position for LPUART_MODIR_TXCTSC. */ -#define BM_LPUART_MODIR_TXCTSC (0x00000010U) /*!< Bit mask for LPUART_MODIR_TXCTSC. */ -#define BS_LPUART_MODIR_TXCTSC (1U) /*!< Bit field size in bits for LPUART_MODIR_TXCTSC. */ - -/*! @brief Read current value of the LPUART_MODIR_TXCTSC field. */ -#define BR_LPUART_MODIR_TXCTSC(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSC)) - -/*! @brief Format value for bitfield LPUART_MODIR_TXCTSC. */ -#define BF_LPUART_MODIR_TXCTSC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXCTSC) & BM_LPUART_MODIR_TXCTSC) - -/*! @brief Set the TXCTSC field to a new value. */ -#define BW_LPUART_MODIR_TXCTSC(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSC) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field TXCTSSRC[5] (RW) - * - * Configures the source of the CTS input. - * - * Values: - * - 0 - CTS input is the LPUART_CTS pin. - * - 1 - CTS input is the inverted Receiver Match result. - */ -/*@{*/ -#define BP_LPUART_MODIR_TXCTSSRC (5U) /*!< Bit position for LPUART_MODIR_TXCTSSRC. */ -#define BM_LPUART_MODIR_TXCTSSRC (0x00000020U) /*!< Bit mask for LPUART_MODIR_TXCTSSRC. */ -#define BS_LPUART_MODIR_TXCTSSRC (1U) /*!< Bit field size in bits for LPUART_MODIR_TXCTSSRC. */ - -/*! @brief Read current value of the LPUART_MODIR_TXCTSSRC field. */ -#define BR_LPUART_MODIR_TXCTSSRC(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSSRC)) - -/*! @brief Format value for bitfield LPUART_MODIR_TXCTSSRC. */ -#define BF_LPUART_MODIR_TXCTSSRC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXCTSSRC) & BM_LPUART_MODIR_TXCTSSRC) - -/*! @brief Set the TXCTSSRC field to a new value. */ -#define BW_LPUART_MODIR_TXCTSSRC(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSSRC) = (v)) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field TNP[17:16] (RW) - * - * Enables whether the LPUART transmits a 1/OSR, 2/OSR, 3/OSR or 4/OSR narrow - * pulse. - * - * Values: - * - 00 - 1/OSR. - * - 01 - 2/OSR. - * - 10 - 3/OSR. - * - 11 - 4/OSR. - */ -/*@{*/ -#define BP_LPUART_MODIR_TNP (16U) /*!< Bit position for LPUART_MODIR_TNP. */ -#define BM_LPUART_MODIR_TNP (0x00030000U) /*!< Bit mask for LPUART_MODIR_TNP. */ -#define BS_LPUART_MODIR_TNP (2U) /*!< Bit field size in bits for LPUART_MODIR_TNP. */ - -/*! @brief Read current value of the LPUART_MODIR_TNP field. */ -#define BR_LPUART_MODIR_TNP(x) (HW_LPUART_MODIR(x).B.TNP) - -/*! @brief Format value for bitfield LPUART_MODIR_TNP. */ -#define BF_LPUART_MODIR_TNP(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TNP) & BM_LPUART_MODIR_TNP) - -/*! @brief Set the TNP field to a new value. */ -#define BW_LPUART_MODIR_TNP(x, v) (HW_LPUART_MODIR_WR(x, (HW_LPUART_MODIR_RD(x) & ~BM_LPUART_MODIR_TNP) | BF_LPUART_MODIR_TNP(v))) -/*@}*/ - -/*! - * @name Register LPUART_MODIR, field IREN[18] (RW) - * - * Enables/disables the infrared modulation/demodulation. - * - * Values: - * - 0 - IR disabled. - * - 1 - IR enabled. - */ -/*@{*/ -#define BP_LPUART_MODIR_IREN (18U) /*!< Bit position for LPUART_MODIR_IREN. */ -#define BM_LPUART_MODIR_IREN (0x00040000U) /*!< Bit mask for LPUART_MODIR_IREN. */ -#define BS_LPUART_MODIR_IREN (1U) /*!< Bit field size in bits for LPUART_MODIR_IREN. */ - -/*! @brief Read current value of the LPUART_MODIR_IREN field. */ -#define BR_LPUART_MODIR_IREN(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_IREN)) - -/*! @brief Format value for bitfield LPUART_MODIR_IREN. */ -#define BF_LPUART_MODIR_IREN(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_IREN) & BM_LPUART_MODIR_IREN) - -/*! @brief Set the IREN field to a new value. */ -#define BW_LPUART_MODIR_IREN(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_IREN) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_lpuart_t - module struct - ******************************************************************************/ -/*! - * @brief All LPUART module registers. - */ -#pragma pack(1) -typedef struct _hw_lpuart -{ - __IO hw_lpuart_baud_t BAUD; /*!< [0x0] LPUART Baud Rate Register */ - __IO hw_lpuart_stat_t STAT; /*!< [0x4] LPUART Status Register */ - __IO hw_lpuart_ctrl_t CTRL; /*!< [0x8] LPUART Control Register */ - __IO hw_lpuart_data_t DATA; /*!< [0xC] LPUART Data Register */ - __IO hw_lpuart_match_t MATCH; /*!< [0x10] LPUART Match Address Register */ - __IO hw_lpuart_modir_t MODIR; /*!< [0x14] LPUART Modem IrDA Register */ -} hw_lpuart_t; -#pragma pack() - -/*! @brief Macro to access all LPUART registers. */ -/*! @param x LPUART module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_LPUART(LPUART0_BASE). */ -#define HW_LPUART(x) (*(hw_lpuart_t *)(x)) - -#endif /* __HW_LPUART_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h deleted file mode 100644 index a2a04fc80b8..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h +++ /dev/null @@ -1,1779 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_MCG_REGISTERS_H__ -#define __HW_MCG_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 MCG - * - * Multipurpose Clock Generator module - * - * Registers defined in this header file: - * - HW_MCG_C1 - MCG Control 1 Register - * - HW_MCG_C2 - MCG Control 2 Register - * - HW_MCG_C3 - MCG Control 3 Register - * - HW_MCG_C4 - MCG Control 4 Register - * - HW_MCG_C5 - MCG Control 5 Register - * - HW_MCG_C6 - MCG Control 6 Register - * - HW_MCG_S - MCG Status Register - * - HW_MCG_SC - MCG Status and Control Register - * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register - * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register - * - HW_MCG_C7 - MCG Control 7 Register - * - HW_MCG_C8 - MCG Control 8 Register - * - * - hw_mcg_t - Struct containing all module registers. - */ - -#define HW_MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */ - -/******************************************************************************* - * HW_MCG_C1 - MCG Control 1 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C1 - MCG Control 1 Register (RW) - * - * Reset value: 0x04U - */ -typedef union _hw_mcg_c1 -{ - uint8_t U; - struct _hw_mcg_c1_bitfields - { - uint8_t IREFSTEN : 1; /*!< [0] Internal Reference Stop Enable */ - uint8_t IRCLKEN : 1; /*!< [1] Internal Reference Clock Enable */ - uint8_t IREFS : 1; /*!< [2] Internal Reference Select */ - uint8_t FRDIV : 3; /*!< [5:3] FLL External Reference Divider */ - uint8_t CLKS : 2; /*!< [7:6] Clock Source Select */ - } B; -} hw_mcg_c1_t; - -/*! - * @name Constants and macros for entire MCG_C1 register - */ -/*@{*/ -#define HW_MCG_C1_ADDR(x) ((x) + 0x0U) - -#define HW_MCG_C1(x) (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR(x)) -#define HW_MCG_C1_RD(x) (HW_MCG_C1(x).U) -#define HW_MCG_C1_WR(x, v) (HW_MCG_C1(x).U = (v)) -#define HW_MCG_C1_SET(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) | (v))) -#define HW_MCG_C1_CLR(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) & ~(v))) -#define HW_MCG_C1_TOG(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C1 bitfields - */ - -/*! - * @name Register MCG_C1, field IREFSTEN[0] (RW) - * - * Controls whether or not the internal reference clock remains enabled when the - * MCG enters Stop mode. - * - * Values: - * - 0 - Internal reference clock is disabled in Stop mode. - * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or - * if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. - */ -/*@{*/ -#define BP_MCG_C1_IREFSTEN (0U) /*!< Bit position for MCG_C1_IREFSTEN. */ -#define BM_MCG_C1_IREFSTEN (0x01U) /*!< Bit mask for MCG_C1_IREFSTEN. */ -#define BS_MCG_C1_IREFSTEN (1U) /*!< Bit field size in bits for MCG_C1_IREFSTEN. */ - -/*! @brief Read current value of the MCG_C1_IREFSTEN field. */ -#define BR_MCG_C1_IREFSTEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN)) - -/*! @brief Format value for bitfield MCG_C1_IREFSTEN. */ -#define BF_MCG_C1_IREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFSTEN) & BM_MCG_C1_IREFSTEN) - -/*! @brief Set the IREFSTEN field to a new value. */ -#define BW_MCG_C1_IREFSTEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C1, field IRCLKEN[1] (RW) - * - * Enables the internal reference clock for use as MCGIRCLK. - * - * Values: - * - 0 - MCGIRCLK inactive. - * - 1 - MCGIRCLK active. - */ -/*@{*/ -#define BP_MCG_C1_IRCLKEN (1U) /*!< Bit position for MCG_C1_IRCLKEN. */ -#define BM_MCG_C1_IRCLKEN (0x02U) /*!< Bit mask for MCG_C1_IRCLKEN. */ -#define BS_MCG_C1_IRCLKEN (1U) /*!< Bit field size in bits for MCG_C1_IRCLKEN. */ - -/*! @brief Read current value of the MCG_C1_IRCLKEN field. */ -#define BR_MCG_C1_IRCLKEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN)) - -/*! @brief Format value for bitfield MCG_C1_IRCLKEN. */ -#define BF_MCG_C1_IRCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IRCLKEN) & BM_MCG_C1_IRCLKEN) - -/*! @brief Set the IRCLKEN field to a new value. */ -#define BW_MCG_C1_IRCLKEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C1, field IREFS[2] (RW) - * - * Selects the reference clock source for the FLL. - * - * Values: - * - 0 - External reference clock is selected. - * - 1 - The slow internal reference clock is selected. - */ -/*@{*/ -#define BP_MCG_C1_IREFS (2U) /*!< Bit position for MCG_C1_IREFS. */ -#define BM_MCG_C1_IREFS (0x04U) /*!< Bit mask for MCG_C1_IREFS. */ -#define BS_MCG_C1_IREFS (1U) /*!< Bit field size in bits for MCG_C1_IREFS. */ - -/*! @brief Read current value of the MCG_C1_IREFS field. */ -#define BR_MCG_C1_IREFS(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS)) - -/*! @brief Format value for bitfield MCG_C1_IREFS. */ -#define BF_MCG_C1_IREFS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFS) & BM_MCG_C1_IREFS) - -/*! @brief Set the IREFS field to a new value. */ -#define BW_MCG_C1_IREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C1, field FRDIV[5:3] (RW) - * - * Selects the amount to divide down the external reference clock for the FLL. - * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is - * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is - * not required to meet this range, but it is recommended in the cases when trying - * to enter a FLL mode from FBE). - * - * Values: - * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE - * values, Divide Factor is 32. - * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE - * values, Divide Factor is 64. - * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE - * values, Divide Factor is 128. - * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE - * values, Divide Factor is 256. - * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE - * values, Divide Factor is 512. - * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE - * values, Divide Factor is 1024. - * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE - * values, Divide Factor is 1280 . - * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE - * values, Divide Factor is 1536 . - */ -/*@{*/ -#define BP_MCG_C1_FRDIV (3U) /*!< Bit position for MCG_C1_FRDIV. */ -#define BM_MCG_C1_FRDIV (0x38U) /*!< Bit mask for MCG_C1_FRDIV. */ -#define BS_MCG_C1_FRDIV (3U) /*!< Bit field size in bits for MCG_C1_FRDIV. */ - -/*! @brief Read current value of the MCG_C1_FRDIV field. */ -#define BR_MCG_C1_FRDIV(x) (HW_MCG_C1(x).B.FRDIV) - -/*! @brief Format value for bitfield MCG_C1_FRDIV. */ -#define BF_MCG_C1_FRDIV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_FRDIV) & BM_MCG_C1_FRDIV) - -/*! @brief Set the FRDIV field to a new value. */ -#define BW_MCG_C1_FRDIV(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v))) -/*@}*/ - -/*! - * @name Register MCG_C1, field CLKS[7:6] (RW) - * - * Selects the clock source for MCGOUTCLK . - * - * Values: - * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control - * bit). - * - 01 - Encoding 1 - Internal reference clock is selected. - * - 10 - Encoding 2 - External reference clock is selected. - * - 11 - Encoding 3 - Reserved. - */ -/*@{*/ -#define BP_MCG_C1_CLKS (6U) /*!< Bit position for MCG_C1_CLKS. */ -#define BM_MCG_C1_CLKS (0xC0U) /*!< Bit mask for MCG_C1_CLKS. */ -#define BS_MCG_C1_CLKS (2U) /*!< Bit field size in bits for MCG_C1_CLKS. */ - -/*! @brief Read current value of the MCG_C1_CLKS field. */ -#define BR_MCG_C1_CLKS(x) (HW_MCG_C1(x).B.CLKS) - -/*! @brief Format value for bitfield MCG_C1_CLKS. */ -#define BF_MCG_C1_CLKS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_CLKS) & BM_MCG_C1_CLKS) - -/*! @brief Set the CLKS field to a new value. */ -#define BW_MCG_C1_CLKS(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C2 - MCG Control 2 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C2 - MCG Control 2 Register (RW) - * - * Reset value: 0x80U - */ -typedef union _hw_mcg_c2 -{ - uint8_t U; - struct _hw_mcg_c2_bitfields - { - uint8_t IRCS : 1; /*!< [0] Internal Reference Clock Select */ - uint8_t LP : 1; /*!< [1] Low Power Select */ - uint8_t EREFS : 1; /*!< [2] External Reference Select */ - uint8_t HGO : 1; /*!< [3] High Gain Oscillator Select */ - uint8_t RANGE : 2; /*!< [5:4] Frequency Range Select */ - uint8_t FCFTRIM : 1; /*!< [6] Fast Internal Reference Clock Fine Trim - * */ - uint8_t LOCRE0 : 1; /*!< [7] Loss of Clock Reset Enable */ - } B; -} hw_mcg_c2_t; - -/*! - * @name Constants and macros for entire MCG_C2 register - */ -/*@{*/ -#define HW_MCG_C2_ADDR(x) ((x) + 0x1U) - -#define HW_MCG_C2(x) (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR(x)) -#define HW_MCG_C2_RD(x) (HW_MCG_C2(x).U) -#define HW_MCG_C2_WR(x, v) (HW_MCG_C2(x).U = (v)) -#define HW_MCG_C2_SET(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) | (v))) -#define HW_MCG_C2_CLR(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) & ~(v))) -#define HW_MCG_C2_TOG(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C2 bitfields - */ - -/*! - * @name Register MCG_C2, field IRCS[0] (RW) - * - * Selects between the fast or slow internal reference clock source. - * - * Values: - * - 0 - Slow internal reference clock selected. - * - 1 - Fast internal reference clock selected. - */ -/*@{*/ -#define BP_MCG_C2_IRCS (0U) /*!< Bit position for MCG_C2_IRCS. */ -#define BM_MCG_C2_IRCS (0x01U) /*!< Bit mask for MCG_C2_IRCS. */ -#define BS_MCG_C2_IRCS (1U) /*!< Bit field size in bits for MCG_C2_IRCS. */ - -/*! @brief Read current value of the MCG_C2_IRCS field. */ -#define BR_MCG_C2_IRCS(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS)) - -/*! @brief Format value for bitfield MCG_C2_IRCS. */ -#define BF_MCG_C2_IRCS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_IRCS) & BM_MCG_C2_IRCS) - -/*! @brief Set the IRCS field to a new value. */ -#define BW_MCG_C2_IRCS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field LP[1] (RW) - * - * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or - * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in - * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any - * other MCG mode, LP bit has no affect. - * - * Values: - * - 0 - FLL or PLL is not disabled in bypass modes. - * - 1 - FLL or PLL is disabled in bypass modes (lower power) - */ -/*@{*/ -#define BP_MCG_C2_LP (1U) /*!< Bit position for MCG_C2_LP. */ -#define BM_MCG_C2_LP (0x02U) /*!< Bit mask for MCG_C2_LP. */ -#define BS_MCG_C2_LP (1U) /*!< Bit field size in bits for MCG_C2_LP. */ - -/*! @brief Read current value of the MCG_C2_LP field. */ -#define BR_MCG_C2_LP(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP)) - -/*! @brief Format value for bitfield MCG_C2_LP. */ -#define BF_MCG_C2_LP(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LP) & BM_MCG_C2_LP) - -/*! @brief Set the LP field to a new value. */ -#define BW_MCG_C2_LP(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field EREFS[2] (RW) - * - * Selects the source for the external reference clock. See the Oscillator (OSC) - * chapter for more details. - * - * Values: - * - 0 - External reference clock requested. - * - 1 - Oscillator requested. - */ -/*@{*/ -#define BP_MCG_C2_EREFS (2U) /*!< Bit position for MCG_C2_EREFS. */ -#define BM_MCG_C2_EREFS (0x04U) /*!< Bit mask for MCG_C2_EREFS. */ -#define BS_MCG_C2_EREFS (1U) /*!< Bit field size in bits for MCG_C2_EREFS. */ - -/*! @brief Read current value of the MCG_C2_EREFS field. */ -#define BR_MCG_C2_EREFS(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS)) - -/*! @brief Format value for bitfield MCG_C2_EREFS. */ -#define BF_MCG_C2_EREFS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_EREFS) & BM_MCG_C2_EREFS) - -/*! @brief Set the EREFS field to a new value. */ -#define BW_MCG_C2_EREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field HGO[3] (RW) - * - * Controls the crystal oscillator mode of operation. See the Oscillator (OSC) - * chapter for more details. - * - * Values: - * - 0 - Configure crystal oscillator for low-power operation. - * - 1 - Configure crystal oscillator for high-gain operation. - */ -/*@{*/ -#define BP_MCG_C2_HGO (3U) /*!< Bit position for MCG_C2_HGO. */ -#define BM_MCG_C2_HGO (0x08U) /*!< Bit mask for MCG_C2_HGO. */ -#define BS_MCG_C2_HGO (1U) /*!< Bit field size in bits for MCG_C2_HGO. */ - -/*! @brief Read current value of the MCG_C2_HGO field. */ -#define BR_MCG_C2_HGO(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO)) - -/*! @brief Format value for bitfield MCG_C2_HGO. */ -#define BF_MCG_C2_HGO(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_HGO) & BM_MCG_C2_HGO) - -/*! @brief Set the HGO field to a new value. */ -#define BW_MCG_C2_HGO(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field RANGE[5:4] (RW) - * - * Selects the frequency range for the crystal oscillator or external clock - * source. See the Oscillator (OSC) chapter for more details and the device data - * sheet for the frequency ranges used. - * - * Values: - * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator . - * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator . - */ -/*@{*/ -#define BP_MCG_C2_RANGE (4U) /*!< Bit position for MCG_C2_RANGE. */ -#define BM_MCG_C2_RANGE (0x30U) /*!< Bit mask for MCG_C2_RANGE. */ -#define BS_MCG_C2_RANGE (2U) /*!< Bit field size in bits for MCG_C2_RANGE. */ - -/*! @brief Read current value of the MCG_C2_RANGE field. */ -#define BR_MCG_C2_RANGE(x) (HW_MCG_C2(x).B.RANGE) - -/*! @brief Format value for bitfield MCG_C2_RANGE. */ -#define BF_MCG_C2_RANGE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_RANGE) & BM_MCG_C2_RANGE) - -/*! @brief Set the RANGE field to a new value. */ -#define BW_MCG_C2_RANGE(x, v) (HW_MCG_C2_WR(x, (HW_MCG_C2_RD(x) & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v))) -/*@}*/ - -/*! - * @name Register MCG_C2, field FCFTRIM[6] (RW) - * - * FCFTRIM controls the smallest adjustment of the fast internal reference clock - * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM - * decreases the period by the smallest amount possible. If an FCFTRIM value stored in - * nonvolatile memory is to be used, it is your responsibility to copy that value - * from the nonvolatile memory location to this bit. - */ -/*@{*/ -#define BP_MCG_C2_FCFTRIM (6U) /*!< Bit position for MCG_C2_FCFTRIM. */ -#define BM_MCG_C2_FCFTRIM (0x40U) /*!< Bit mask for MCG_C2_FCFTRIM. */ -#define BS_MCG_C2_FCFTRIM (1U) /*!< Bit field size in bits for MCG_C2_FCFTRIM. */ - -/*! @brief Read current value of the MCG_C2_FCFTRIM field. */ -#define BR_MCG_C2_FCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM)) - -/*! @brief Format value for bitfield MCG_C2_FCFTRIM. */ -#define BF_MCG_C2_FCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_FCFTRIM) & BM_MCG_C2_FCFTRIM) - -/*! @brief Set the FCFTRIM field to a new value. */ -#define BW_MCG_C2_FCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field LOCRE0[7] (RW) - * - * Determines whether an interrupt or a reset request is made following a loss - * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is - * set. - * - * Values: - * - 0 - Interrupt request is generated on a loss of OSC0 external reference - * clock. - * - 1 - Generate a reset request on a loss of OSC0 external reference clock. - */ -/*@{*/ -#define BP_MCG_C2_LOCRE0 (7U) /*!< Bit position for MCG_C2_LOCRE0. */ -#define BM_MCG_C2_LOCRE0 (0x80U) /*!< Bit mask for MCG_C2_LOCRE0. */ -#define BS_MCG_C2_LOCRE0 (1U) /*!< Bit field size in bits for MCG_C2_LOCRE0. */ - -/*! @brief Read current value of the MCG_C2_LOCRE0 field. */ -#define BR_MCG_C2_LOCRE0(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0)) - -/*! @brief Format value for bitfield MCG_C2_LOCRE0. */ -#define BF_MCG_C2_LOCRE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LOCRE0) & BM_MCG_C2_LOCRE0) - -/*! @brief Set the LOCRE0 field to a new value. */ -#define BW_MCG_C2_LOCRE0(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C3 - MCG Control 3 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C3 - MCG Control 3 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c3 -{ - uint8_t U; - struct _hw_mcg_c3_bitfields - { - uint8_t SCTRIM : 8; /*!< [7:0] Slow Internal Reference Clock Trim - * Setting */ - } B; -} hw_mcg_c3_t; - -/*! - * @name Constants and macros for entire MCG_C3 register - */ -/*@{*/ -#define HW_MCG_C3_ADDR(x) ((x) + 0x2U) - -#define HW_MCG_C3(x) (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR(x)) -#define HW_MCG_C3_RD(x) (HW_MCG_C3(x).U) -#define HW_MCG_C3_WR(x, v) (HW_MCG_C3(x).U = (v)) -#define HW_MCG_C3_SET(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) | (v))) -#define HW_MCG_C3_CLR(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) & ~(v))) -#define HW_MCG_C3_TOG(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C3 bitfields - */ - -/*! - * @name Register MCG_C3, field SCTRIM[7:0] (RW) - * - * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed - * location. controls the slow internal reference clock frequency by controlling - * the slow internal reference clock period. The SCTRIM bits are binary weighted, - * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value - * increases the period, and decreasing the value decreases the period. An additional - * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, - * this value is loaded with a factory trim value. If an SCTRIM value stored in - * nonvolatile memory is to be used, it is your responsibility to copy that value - * from the nonvolatile memory location to this register. - */ -/*@{*/ -#define BP_MCG_C3_SCTRIM (0U) /*!< Bit position for MCG_C3_SCTRIM. */ -#define BM_MCG_C3_SCTRIM (0xFFU) /*!< Bit mask for MCG_C3_SCTRIM. */ -#define BS_MCG_C3_SCTRIM (8U) /*!< Bit field size in bits for MCG_C3_SCTRIM. */ - -/*! @brief Read current value of the MCG_C3_SCTRIM field. */ -#define BR_MCG_C3_SCTRIM(x) (HW_MCG_C3(x).U) - -/*! @brief Format value for bitfield MCG_C3_SCTRIM. */ -#define BF_MCG_C3_SCTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C3_SCTRIM) & BM_MCG_C3_SCTRIM) - -/*! @brief Set the SCTRIM field to a new value. */ -#define BW_MCG_C3_SCTRIM(x, v) (HW_MCG_C3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C4 - MCG Control 4 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C4 - MCG Control 4 Register (RW) - * - * Reset value: 0x00U - * - * Reset values for DRST and DMX32 bits are 0. - */ -typedef union _hw_mcg_c4 -{ - uint8_t U; - struct _hw_mcg_c4_bitfields - { - uint8_t SCFTRIM : 1; /*!< [0] Slow Internal Reference Clock Fine Trim - * */ - uint8_t FCTRIM : 4; /*!< [4:1] Fast Internal Reference Clock Trim - * Setting */ - uint8_t DRST_DRS : 2; /*!< [6:5] DCO Range Select */ - uint8_t DMX32 : 1; /*!< [7] DCO Maximum Frequency with 32.768 kHz - * Reference */ - } B; -} hw_mcg_c4_t; - -/*! - * @name Constants and macros for entire MCG_C4 register - */ -/*@{*/ -#define HW_MCG_C4_ADDR(x) ((x) + 0x3U) - -#define HW_MCG_C4(x) (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR(x)) -#define HW_MCG_C4_RD(x) (HW_MCG_C4(x).U) -#define HW_MCG_C4_WR(x, v) (HW_MCG_C4(x).U = (v)) -#define HW_MCG_C4_SET(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) | (v))) -#define HW_MCG_C4_CLR(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) & ~(v))) -#define HW_MCG_C4_TOG(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C4 bitfields - */ - -/*! - * @name Register MCG_C4, field SCFTRIM[0] (RW) - * - * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed - * location . controls the smallest adjustment of the slow internal reference - * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM - * decreases the period by the smallest amount possible. If an SCFTRIM value stored in - * nonvolatile memory is to be used, it is your responsibility to copy that value - * from the nonvolatile memory location to this bit. - */ -/*@{*/ -#define BP_MCG_C4_SCFTRIM (0U) /*!< Bit position for MCG_C4_SCFTRIM. */ -#define BM_MCG_C4_SCFTRIM (0x01U) /*!< Bit mask for MCG_C4_SCFTRIM. */ -#define BS_MCG_C4_SCFTRIM (1U) /*!< Bit field size in bits for MCG_C4_SCFTRIM. */ - -/*! @brief Read current value of the MCG_C4_SCFTRIM field. */ -#define BR_MCG_C4_SCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM)) - -/*! @brief Format value for bitfield MCG_C4_SCFTRIM. */ -#define BF_MCG_C4_SCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_SCFTRIM) & BM_MCG_C4_SCFTRIM) - -/*! @brief Set the SCFTRIM field to a new value. */ -#define BW_MCG_C4_SCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C4, field FCTRIM[4:1] (RW) - * - * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed - * location. controls the fast internal reference clock frequency by controlling - * the fast internal reference clock period. The FCTRIM bits are binary weighted, - * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value - * increases the period, and decreasing the value decreases the period. If an - * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your - * responsibility to copy that value from the nonvolatile memory location to this register. - */ -/*@{*/ -#define BP_MCG_C4_FCTRIM (1U) /*!< Bit position for MCG_C4_FCTRIM. */ -#define BM_MCG_C4_FCTRIM (0x1EU) /*!< Bit mask for MCG_C4_FCTRIM. */ -#define BS_MCG_C4_FCTRIM (4U) /*!< Bit field size in bits for MCG_C4_FCTRIM. */ - -/*! @brief Read current value of the MCG_C4_FCTRIM field. */ -#define BR_MCG_C4_FCTRIM(x) (HW_MCG_C4(x).B.FCTRIM) - -/*! @brief Format value for bitfield MCG_C4_FCTRIM. */ -#define BF_MCG_C4_FCTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_FCTRIM) & BM_MCG_C4_FCTRIM) - -/*! @brief Set the FCTRIM field to a new value. */ -#define BW_MCG_C4_FCTRIM(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v))) -/*@}*/ - -/*! - * @name Register MCG_C4, field DRST_DRS[6:5] (RW) - * - * The DRS bits select the frequency range for the FLL output, DCOOUT. When the - * LP bit is set, writes to the DRS bits are ignored. The DRST read field - * indicates the current frequency range for DCOOUT. The DRST field does not update - * immediately after a write to the DRS field due to internal synchronization between - * clock domains. See the DCO Frequency Range table for more details. - * - * Values: - * - 00 - Encoding 0 - Low range (reset default). - * - 01 - Encoding 1 - Mid range. - * - 10 - Encoding 2 - Mid-high range. - * - 11 - Encoding 3 - High range. - */ -/*@{*/ -#define BP_MCG_C4_DRST_DRS (5U) /*!< Bit position for MCG_C4_DRST_DRS. */ -#define BM_MCG_C4_DRST_DRS (0x60U) /*!< Bit mask for MCG_C4_DRST_DRS. */ -#define BS_MCG_C4_DRST_DRS (2U) /*!< Bit field size in bits for MCG_C4_DRST_DRS. */ - -/*! @brief Read current value of the MCG_C4_DRST_DRS field. */ -#define BR_MCG_C4_DRST_DRS(x) (HW_MCG_C4(x).B.DRST_DRS) - -/*! @brief Format value for bitfield MCG_C4_DRST_DRS. */ -#define BF_MCG_C4_DRST_DRS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DRST_DRS) & BM_MCG_C4_DRST_DRS) - -/*! @brief Set the DRST_DRS field to a new value. */ -#define BW_MCG_C4_DRST_DRS(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v))) -/*@}*/ - -/*! - * @name Register MCG_C4, field DMX32[7] (RW) - * - * The DMX32 bit controls whether the DCO frequency range is narrowed to its - * maximum frequency with a 32.768 kHz reference. The following table identifies - * settings for the DCO frequency range. The system clocks derived from this source - * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL - * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz - * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0 - * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560 - * 80-100 MHz 1 32.768 kHz 2929 96 MHz - * - * Values: - * - 0 - DCO has a default range of 25%. - * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference. - */ -/*@{*/ -#define BP_MCG_C4_DMX32 (7U) /*!< Bit position for MCG_C4_DMX32. */ -#define BM_MCG_C4_DMX32 (0x80U) /*!< Bit mask for MCG_C4_DMX32. */ -#define BS_MCG_C4_DMX32 (1U) /*!< Bit field size in bits for MCG_C4_DMX32. */ - -/*! @brief Read current value of the MCG_C4_DMX32 field. */ -#define BR_MCG_C4_DMX32(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32)) - -/*! @brief Format value for bitfield MCG_C4_DMX32. */ -#define BF_MCG_C4_DMX32(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DMX32) & BM_MCG_C4_DMX32) - -/*! @brief Set the DMX32 field to a new value. */ -#define BW_MCG_C4_DMX32(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C5 - MCG Control 5 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C5 - MCG Control 5 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c5 -{ - uint8_t U; - struct _hw_mcg_c5_bitfields - { - uint8_t PRDIV0 : 5; /*!< [4:0] PLL External Reference Divider */ - uint8_t PLLSTEN0 : 1; /*!< [5] PLL Stop Enable */ - uint8_t PLLCLKEN0 : 1; /*!< [6] PLL Clock Enable */ - uint8_t RESERVED0 : 1; /*!< [7] */ - } B; -} hw_mcg_c5_t; - -/*! - * @name Constants and macros for entire MCG_C5 register - */ -/*@{*/ -#define HW_MCG_C5_ADDR(x) ((x) + 0x4U) - -#define HW_MCG_C5(x) (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x)) -#define HW_MCG_C5_RD(x) (HW_MCG_C5(x).U) -#define HW_MCG_C5_WR(x, v) (HW_MCG_C5(x).U = (v)) -#define HW_MCG_C5_SET(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) | (v))) -#define HW_MCG_C5_CLR(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v))) -#define HW_MCG_C5_TOG(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C5 bitfields - */ - -/*! - * @name Register MCG_C5, field PRDIV0[4:0] (RW) - * - * Selects the amount to divide down the external reference clock for the PLL. - * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL - * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not - * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0 - * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor - * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved - * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved - * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101 - * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111 - * Reserved - */ -/*@{*/ -#define BP_MCG_C5_PRDIV0 (0U) /*!< Bit position for MCG_C5_PRDIV0. */ -#define BM_MCG_C5_PRDIV0 (0x1FU) /*!< Bit mask for MCG_C5_PRDIV0. */ -#define BS_MCG_C5_PRDIV0 (5U) /*!< Bit field size in bits for MCG_C5_PRDIV0. */ - -/*! @brief Read current value of the MCG_C5_PRDIV0 field. */ -#define BR_MCG_C5_PRDIV0(x) (HW_MCG_C5(x).B.PRDIV0) - -/*! @brief Format value for bitfield MCG_C5_PRDIV0. */ -#define BF_MCG_C5_PRDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0) - -/*! @brief Set the PRDIV0 field to a new value. */ -#define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v))) -/*@}*/ - -/*! - * @name Register MCG_C5, field PLLSTEN0[5] (RW) - * - * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL - * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit - * has no affect and does not enable the PLL Clock to run if it is written to 1. - * - * Values: - * - 0 - MCGPLLCLK is disabled in any of the Stop modes. - * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode. - */ -/*@{*/ -#define BP_MCG_C5_PLLSTEN0 (5U) /*!< Bit position for MCG_C5_PLLSTEN0. */ -#define BM_MCG_C5_PLLSTEN0 (0x20U) /*!< Bit mask for MCG_C5_PLLSTEN0. */ -#define BS_MCG_C5_PLLSTEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */ - -/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */ -#define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0)) - -/*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */ -#define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0) - -/*! @brief Set the PLLSTEN0 field to a new value. */ -#define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C5, field PLLCLKEN0[6] (RW) - * - * Enables the PLL independent of PLLS and enables the PLL clock for use as - * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a - * PLL reference clock in the range of 2 - 4 MHz range prior to setting the - * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not - * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, - * and the external oscillator is being used as the reference clock, the OSCINIT 0 - * bit should be checked to make sure it is set. - * - * Values: - * - 0 - MCGPLLCLK is inactive. - * - 1 - MCGPLLCLK is active. - */ -/*@{*/ -#define BP_MCG_C5_PLLCLKEN0 (6U) /*!< Bit position for MCG_C5_PLLCLKEN0. */ -#define BM_MCG_C5_PLLCLKEN0 (0x40U) /*!< Bit mask for MCG_C5_PLLCLKEN0. */ -#define BS_MCG_C5_PLLCLKEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */ - -/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */ -#define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0)) - -/*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */ -#define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0) - -/*! @brief Set the PLLCLKEN0 field to a new value. */ -#define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C6 - MCG Control 6 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C6 - MCG Control 6 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c6 -{ - uint8_t U; - struct _hw_mcg_c6_bitfields - { - uint8_t VDIV0 : 5; /*!< [4:0] VCO 0 Divider */ - uint8_t CME0 : 1; /*!< [5] Clock Monitor Enable */ - uint8_t PLLS : 1; /*!< [6] PLL Select */ - uint8_t LOLIE0 : 1; /*!< [7] Loss of Lock Interrrupt Enable */ - } B; -} hw_mcg_c6_t; - -/*! - * @name Constants and macros for entire MCG_C6 register - */ -/*@{*/ -#define HW_MCG_C6_ADDR(x) ((x) + 0x5U) - -#define HW_MCG_C6(x) (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR(x)) -#define HW_MCG_C6_RD(x) (HW_MCG_C6(x).U) -#define HW_MCG_C6_WR(x, v) (HW_MCG_C6(x).U = (v)) -#define HW_MCG_C6_SET(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) | (v))) -#define HW_MCG_C6_CLR(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) & ~(v))) -#define HW_MCG_C6_TOG(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C6 bitfields - */ - -/*! - * @name Register MCG_C6, field VDIV0[4:0] (RW) - * - * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits - * establish the multiplication factor (M) applied to the reference clock frequency. - * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0 - * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0 - * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply - * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49 - * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 - * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 - * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 - */ -/*@{*/ -#define BP_MCG_C6_VDIV0 (0U) /*!< Bit position for MCG_C6_VDIV0. */ -#define BM_MCG_C6_VDIV0 (0x1FU) /*!< Bit mask for MCG_C6_VDIV0. */ -#define BS_MCG_C6_VDIV0 (5U) /*!< Bit field size in bits for MCG_C6_VDIV0. */ - -/*! @brief Read current value of the MCG_C6_VDIV0 field. */ -#define BR_MCG_C6_VDIV0(x) (HW_MCG_C6(x).B.VDIV0) - -/*! @brief Format value for bitfield MCG_C6_VDIV0. */ -#define BF_MCG_C6_VDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0) - -/*! @brief Set the VDIV0 field to a new value. */ -#define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v))) -/*@}*/ - -/*! - * @name Register MCG_C6, field CME0[5] (RW) - * - * Enables the loss of clock monitoring circuit for the OSC0 external reference - * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is - * generated following a loss of OSC0 indication. The CME0 bit must only be set - * to a logic 1 when the MCG is in an operational mode that uses the external - * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, - * the value of the RANGE0 bits in the C2 register should not be changed. CME0 - * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a - * reset request may occur while in Stop mode. CME0 should also be set to a - * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. - * - * Values: - * - 0 - External clock monitor is disabled for OSC0. - * - 1 - External clock monitor is enabled for OSC0. - */ -/*@{*/ -#define BP_MCG_C6_CME0 (5U) /*!< Bit position for MCG_C6_CME0. */ -#define BM_MCG_C6_CME0 (0x20U) /*!< Bit mask for MCG_C6_CME0. */ -#define BS_MCG_C6_CME0 (1U) /*!< Bit field size in bits for MCG_C6_CME0. */ - -/*! @brief Read current value of the MCG_C6_CME0 field. */ -#define BR_MCG_C6_CME0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0)) - -/*! @brief Format value for bitfield MCG_C6_CME0. */ -#define BF_MCG_C6_CME0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0) - -/*! @brief Set the CME0 field to a new value. */ -#define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C6, field PLLS[6] (RW) - * - * Controls whether the PLL or FLL output is selected as the MCG source when - * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is - * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. - * - * Values: - * - 0 - FLL is selected. - * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider - * to generate a PLL reference clock in the range of 2-4 MHz prior to setting - * the PLLS bit). - */ -/*@{*/ -#define BP_MCG_C6_PLLS (6U) /*!< Bit position for MCG_C6_PLLS. */ -#define BM_MCG_C6_PLLS (0x40U) /*!< Bit mask for MCG_C6_PLLS. */ -#define BS_MCG_C6_PLLS (1U) /*!< Bit field size in bits for MCG_C6_PLLS. */ - -/*! @brief Read current value of the MCG_C6_PLLS field. */ -#define BR_MCG_C6_PLLS(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS)) - -/*! @brief Format value for bitfield MCG_C6_PLLS. */ -#define BF_MCG_C6_PLLS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS) - -/*! @brief Set the PLLS field to a new value. */ -#define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C6, field LOLIE0[7] (RW) - * - * Determines if an interrupt request is made following a loss of lock - * indication. This bit only has an effect when LOLS 0 is set. - * - * Values: - * - 0 - No interrupt request is generated on loss of lock. - * - 1 - Generate an interrupt request on loss of lock. - */ -/*@{*/ -#define BP_MCG_C6_LOLIE0 (7U) /*!< Bit position for MCG_C6_LOLIE0. */ -#define BM_MCG_C6_LOLIE0 (0x80U) /*!< Bit mask for MCG_C6_LOLIE0. */ -#define BS_MCG_C6_LOLIE0 (1U) /*!< Bit field size in bits for MCG_C6_LOLIE0. */ - -/*! @brief Read current value of the MCG_C6_LOLIE0 field. */ -#define BR_MCG_C6_LOLIE0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0)) - -/*! @brief Format value for bitfield MCG_C6_LOLIE0. */ -#define BF_MCG_C6_LOLIE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0) - -/*! @brief Set the LOLIE0 field to a new value. */ -#define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_S - MCG Status Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_S - MCG Status Register (RW) - * - * Reset value: 0x10U - */ -typedef union _hw_mcg_s -{ - uint8_t U; - struct _hw_mcg_s_bitfields - { - uint8_t IRCST : 1; /*!< [0] Internal Reference Clock Status */ - uint8_t OSCINIT0 : 1; /*!< [1] OSC Initialization */ - uint8_t CLKST : 2; /*!< [3:2] Clock Mode Status */ - uint8_t IREFST : 1; /*!< [4] Internal Reference Status */ - uint8_t PLLST : 1; /*!< [5] PLL Select Status */ - uint8_t LOCK0 : 1; /*!< [6] Lock Status */ - uint8_t LOLS0 : 1; /*!< [7] Loss of Lock Status */ - } B; -} hw_mcg_s_t; - -/*! - * @name Constants and macros for entire MCG_S register - */ -/*@{*/ -#define HW_MCG_S_ADDR(x) ((x) + 0x6U) - -#define HW_MCG_S(x) (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x)) -#define HW_MCG_S_RD(x) (HW_MCG_S(x).U) -#define HW_MCG_S_WR(x, v) (HW_MCG_S(x).U = (v)) -#define HW_MCG_S_SET(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) | (v))) -#define HW_MCG_S_CLR(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v))) -#define HW_MCG_S_TOG(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_S bitfields - */ - -/*! - * @name Register MCG_S, field IRCST[0] (RO) - * - * The IRCST bit indicates the current source for the internal reference clock - * select clock (IRCSCLK). The IRCST bit does not update immediately after a write - * to the IRCS bit due to internal synchronization between clock domains. The - * IRCST bit will only be updated if the internal reference clock is enabled, - * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] - * bit . - * - * Values: - * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC). - * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC). - */ -/*@{*/ -#define BP_MCG_S_IRCST (0U) /*!< Bit position for MCG_S_IRCST. */ -#define BM_MCG_S_IRCST (0x01U) /*!< Bit mask for MCG_S_IRCST. */ -#define BS_MCG_S_IRCST (1U) /*!< Bit field size in bits for MCG_S_IRCST. */ - -/*! @brief Read current value of the MCG_S_IRCST field. */ -#define BR_MCG_S_IRCST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IRCST)) -/*@}*/ - -/*! - * @name Register MCG_S, field OSCINIT0[1] (RO) - * - * This bit, which resets to 0, is set to 1 after the initialization cycles of - * the crystal oscillator clock have completed. After being set, the bit is - * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed - * description for more information. - */ -/*@{*/ -#define BP_MCG_S_OSCINIT0 (1U) /*!< Bit position for MCG_S_OSCINIT0. */ -#define BM_MCG_S_OSCINIT0 (0x02U) /*!< Bit mask for MCG_S_OSCINIT0. */ -#define BS_MCG_S_OSCINIT0 (1U) /*!< Bit field size in bits for MCG_S_OSCINIT0. */ - -/*! @brief Read current value of the MCG_S_OSCINIT0 field. */ -#define BR_MCG_S_OSCINIT0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_OSCINIT0)) -/*@}*/ - -/*! - * @name Register MCG_S, field CLKST[3:2] (RO) - * - * These bits indicate the current clock mode. The CLKST bits do not update - * immediately after a write to the CLKS bits due to internal synchronization between - * clock domains. - * - * Values: - * - 00 - Encoding 0 - Output of the FLL is selected (reset default). - * - 01 - Encoding 1 - Internal reference clock is selected. - * - 10 - Encoding 2 - External reference clock is selected. - * - 11 - Encoding 3 - Output of the PLL is selected. - */ -/*@{*/ -#define BP_MCG_S_CLKST (2U) /*!< Bit position for MCG_S_CLKST. */ -#define BM_MCG_S_CLKST (0x0CU) /*!< Bit mask for MCG_S_CLKST. */ -#define BS_MCG_S_CLKST (2U) /*!< Bit field size in bits for MCG_S_CLKST. */ - -/*! @brief Read current value of the MCG_S_CLKST field. */ -#define BR_MCG_S_CLKST(x) (HW_MCG_S(x).B.CLKST) -/*@}*/ - -/*! - * @name Register MCG_S, field IREFST[4] (RO) - * - * This bit indicates the current source for the FLL reference clock. The IREFST - * bit does not update immediately after a write to the IREFS bit due to - * internal synchronization between clock domains. - * - * Values: - * - 0 - Source of FLL reference clock is the external reference clock. - * - 1 - Source of FLL reference clock is the internal reference clock. - */ -/*@{*/ -#define BP_MCG_S_IREFST (4U) /*!< Bit position for MCG_S_IREFST. */ -#define BM_MCG_S_IREFST (0x10U) /*!< Bit mask for MCG_S_IREFST. */ -#define BS_MCG_S_IREFST (1U) /*!< Bit field size in bits for MCG_S_IREFST. */ - -/*! @brief Read current value of the MCG_S_IREFST field. */ -#define BR_MCG_S_IREFST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST)) -/*@}*/ - -/*! - * @name Register MCG_S, field PLLST[5] (RO) - * - * This bit indicates the clock source selected by PLLS . The PLLST bit does not - * update immediately after a write to the PLLS bit due to internal - * synchronization between clock domains. - * - * Values: - * - 0 - Source of PLLS clock is FLL clock. - * - 1 - Source of PLLS clock is PLL output clock. - */ -/*@{*/ -#define BP_MCG_S_PLLST (5U) /*!< Bit position for MCG_S_PLLST. */ -#define BM_MCG_S_PLLST (0x20U) /*!< Bit mask for MCG_S_PLLST. */ -#define BS_MCG_S_PLLST (1U) /*!< Bit field size in bits for MCG_S_PLLST. */ - -/*! @brief Read current value of the MCG_S_PLLST field. */ -#define BR_MCG_S_PLLST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST)) -/*@}*/ - -/*! - * @name Register MCG_S, field LOCK0[6] (RO) - * - * This bit indicates whether the PLL has acquired lock. Lock detection is only - * enabled when the PLL is enabled (either through clock mode selection or - * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the - * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. - * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in - * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock - * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL - * reference clock will also cause the LOCK0 bit to clear until the PLL has - * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes - * the lock status bit to clear and stay cleared until the Stop mode is exited - * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit - * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted - * again. - * - * Values: - * - 0 - PLL is currently unlocked. - * - 1 - PLL is currently locked. - */ -/*@{*/ -#define BP_MCG_S_LOCK0 (6U) /*!< Bit position for MCG_S_LOCK0. */ -#define BM_MCG_S_LOCK0 (0x40U) /*!< Bit mask for MCG_S_LOCK0. */ -#define BS_MCG_S_LOCK0 (1U) /*!< Bit field size in bits for MCG_S_LOCK0. */ - -/*! @brief Read current value of the MCG_S_LOCK0 field. */ -#define BR_MCG_S_LOCK0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0)) -/*@}*/ - -/*! - * @name Register MCG_S, field LOLS0[7] (W1C) - * - * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set - * if after acquiring lock, the PLL output frequency has fallen outside the lock - * exit frequency tolerance, D unl . LOLIE determines whether an interrupt - * request is made when LOLS is set. LOLRE determines whether a reset request is made - * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it - * when set. Writing a logic 0 to this bit has no effect. - * - * Values: - * - 0 - PLL has not lost lock since LOLS 0 was last cleared. - * - 1 - PLL has lost lock since LOLS 0 was last cleared. - */ -/*@{*/ -#define BP_MCG_S_LOLS0 (7U) /*!< Bit position for MCG_S_LOLS0. */ -#define BM_MCG_S_LOLS0 (0x80U) /*!< Bit mask for MCG_S_LOLS0. */ -#define BS_MCG_S_LOLS0 (1U) /*!< Bit field size in bits for MCG_S_LOLS0. */ - -/*! @brief Read current value of the MCG_S_LOLS0 field. */ -#define BR_MCG_S_LOLS0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0)) - -/*! @brief Format value for bitfield MCG_S_LOLS0. */ -#define BF_MCG_S_LOLS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0) - -/*! @brief Set the LOLS0 field to a new value. */ -#define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_SC - MCG Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_SC - MCG Status and Control Register (RW) - * - * Reset value: 0x02U - */ -typedef union _hw_mcg_sc -{ - uint8_t U; - struct _hw_mcg_sc_bitfields - { - uint8_t LOCS0 : 1; /*!< [0] OSC0 Loss of Clock Status */ - uint8_t FCRDIV : 3; /*!< [3:1] Fast Clock Internal Reference Divider - * */ - uint8_t FLTPRSRV : 1; /*!< [4] FLL Filter Preserve Enable */ - uint8_t ATMF : 1; /*!< [5] Automatic Trim Machine Fail Flag */ - uint8_t ATMS : 1; /*!< [6] Automatic Trim Machine Select */ - uint8_t ATME : 1; /*!< [7] Automatic Trim Machine Enable */ - } B; -} hw_mcg_sc_t; - -/*! - * @name Constants and macros for entire MCG_SC register - */ -/*@{*/ -#define HW_MCG_SC_ADDR(x) ((x) + 0x8U) - -#define HW_MCG_SC(x) (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR(x)) -#define HW_MCG_SC_RD(x) (HW_MCG_SC(x).U) -#define HW_MCG_SC_WR(x, v) (HW_MCG_SC(x).U = (v)) -#define HW_MCG_SC_SET(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) | (v))) -#define HW_MCG_SC_CLR(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) & ~(v))) -#define HW_MCG_SC_TOG(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_SC bitfields - */ - -/*! - * @name Register MCG_SC, field LOCS0[0] (W1C) - * - * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The - * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a - * logic 1 to it when set. - * - * Values: - * - 0 - Loss of OSC0 has not occurred. - * - 1 - Loss of OSC0 has occurred. - */ -/*@{*/ -#define BP_MCG_SC_LOCS0 (0U) /*!< Bit position for MCG_SC_LOCS0. */ -#define BM_MCG_SC_LOCS0 (0x01U) /*!< Bit mask for MCG_SC_LOCS0. */ -#define BS_MCG_SC_LOCS0 (1U) /*!< Bit field size in bits for MCG_SC_LOCS0. */ - -/*! @brief Read current value of the MCG_SC_LOCS0 field. */ -#define BR_MCG_SC_LOCS0(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0)) - -/*! @brief Format value for bitfield MCG_SC_LOCS0. */ -#define BF_MCG_SC_LOCS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_LOCS0) & BM_MCG_SC_LOCS0) - -/*! @brief Set the LOCS0 field to a new value. */ -#define BW_MCG_SC_LOCS0(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field FCRDIV[3:1] (RW) - * - * Selects the amount to divide down the fast internal reference clock. The - * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the - * divider when the Fast IRC is enabled is not supported). - * - * Values: - * - 000 - Divide Factor is 1 - * - 001 - Divide Factor is 2. - * - 010 - Divide Factor is 4. - * - 011 - Divide Factor is 8. - * - 100 - Divide Factor is 16 - * - 101 - Divide Factor is 32 - * - 110 - Divide Factor is 64 - * - 111 - Divide Factor is 128. - */ -/*@{*/ -#define BP_MCG_SC_FCRDIV (1U) /*!< Bit position for MCG_SC_FCRDIV. */ -#define BM_MCG_SC_FCRDIV (0x0EU) /*!< Bit mask for MCG_SC_FCRDIV. */ -#define BS_MCG_SC_FCRDIV (3U) /*!< Bit field size in bits for MCG_SC_FCRDIV. */ - -/*! @brief Read current value of the MCG_SC_FCRDIV field. */ -#define BR_MCG_SC_FCRDIV(x) (HW_MCG_SC(x).B.FCRDIV) - -/*! @brief Format value for bitfield MCG_SC_FCRDIV. */ -#define BF_MCG_SC_FCRDIV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FCRDIV) & BM_MCG_SC_FCRDIV) - -/*! @brief Set the FCRDIV field to a new value. */ -#define BW_MCG_SC_FCRDIV(x, v) (HW_MCG_SC_WR(x, (HW_MCG_SC_RD(x) & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v))) -/*@}*/ - -/*! - * @name Register MCG_SC, field FLTPRSRV[4] (RW) - * - * This bit will prevent the FLL filter values from resetting allowing the FLL - * output frequency to remain the same during clock mode changes where the FLL/DCO - * output is still valid. (Note: This requires that the FLL reference frequency - * to remain the same as what it was prior to the new clock mode switch. - * Otherwise FLL filter and frequency values will change.) - * - * Values: - * - 0 - FLL filter and FLL frequency will reset on changes to currect clock - * mode. - * - 1 - Fll filter and FLL frequency retain their previous values during new - * clock mode change. - */ -/*@{*/ -#define BP_MCG_SC_FLTPRSRV (4U) /*!< Bit position for MCG_SC_FLTPRSRV. */ -#define BM_MCG_SC_FLTPRSRV (0x10U) /*!< Bit mask for MCG_SC_FLTPRSRV. */ -#define BS_MCG_SC_FLTPRSRV (1U) /*!< Bit field size in bits for MCG_SC_FLTPRSRV. */ - -/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */ -#define BR_MCG_SC_FLTPRSRV(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV)) - -/*! @brief Format value for bitfield MCG_SC_FLTPRSRV. */ -#define BF_MCG_SC_FLTPRSRV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FLTPRSRV) & BM_MCG_SC_FLTPRSRV) - -/*! @brief Set the FLTPRSRV field to a new value. */ -#define BW_MCG_SC_FLTPRSRV(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field ATMF[5] (RW) - * - * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the - * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC - * registers is detected or the MCG enters into any Stop mode. A write to ATMF - * clears the flag. - * - * Values: - * - 0 - Automatic Trim Machine completed normally. - * - 1 - Automatic Trim Machine failed. - */ -/*@{*/ -#define BP_MCG_SC_ATMF (5U) /*!< Bit position for MCG_SC_ATMF. */ -#define BM_MCG_SC_ATMF (0x20U) /*!< Bit mask for MCG_SC_ATMF. */ -#define BS_MCG_SC_ATMF (1U) /*!< Bit field size in bits for MCG_SC_ATMF. */ - -/*! @brief Read current value of the MCG_SC_ATMF field. */ -#define BR_MCG_SC_ATMF(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF)) - -/*! @brief Format value for bitfield MCG_SC_ATMF. */ -#define BF_MCG_SC_ATMF(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMF) & BM_MCG_SC_ATMF) - -/*! @brief Set the ATMF field to a new value. */ -#define BW_MCG_SC_ATMF(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field ATMS[6] (RW) - * - * Selects the IRCS clock for Auto Trim Test. - * - * Values: - * - 0 - 32 kHz Internal Reference Clock selected. - * - 1 - 4 MHz Internal Reference Clock selected. - */ -/*@{*/ -#define BP_MCG_SC_ATMS (6U) /*!< Bit position for MCG_SC_ATMS. */ -#define BM_MCG_SC_ATMS (0x40U) /*!< Bit mask for MCG_SC_ATMS. */ -#define BS_MCG_SC_ATMS (1U) /*!< Bit field size in bits for MCG_SC_ATMS. */ - -/*! @brief Read current value of the MCG_SC_ATMS field. */ -#define BR_MCG_SC_ATMS(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS)) - -/*! @brief Format value for bitfield MCG_SC_ATMS. */ -#define BF_MCG_SC_ATMS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMS) & BM_MCG_SC_ATMS) - -/*! @brief Set the ATMS field to a new value. */ -#define BW_MCG_SC_ATMS(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field ATME[7] (RW) - * - * Enables the Auto Trim Machine to start automatically trimming the selected - * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has - * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing - * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim - * operation and clears this bit. - * - * Values: - * - 0 - Auto Trim Machine disabled. - * - 1 - Auto Trim Machine enabled. - */ -/*@{*/ -#define BP_MCG_SC_ATME (7U) /*!< Bit position for MCG_SC_ATME. */ -#define BM_MCG_SC_ATME (0x80U) /*!< Bit mask for MCG_SC_ATME. */ -#define BS_MCG_SC_ATME (1U) /*!< Bit field size in bits for MCG_SC_ATME. */ - -/*! @brief Read current value of the MCG_SC_ATME field. */ -#define BR_MCG_SC_ATME(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME)) - -/*! @brief Format value for bitfield MCG_SC_ATME. */ -#define BF_MCG_SC_ATME(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATME) & BM_MCG_SC_ATME) - -/*! @brief Set the ATME field to a new value. */ -#define BW_MCG_SC_ATME(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_atcvh -{ - uint8_t U; - struct _hw_mcg_atcvh_bitfields - { - uint8_t ATCVH : 8; /*!< [7:0] ATM Compare Value High */ - } B; -} hw_mcg_atcvh_t; - -/*! - * @name Constants and macros for entire MCG_ATCVH register - */ -/*@{*/ -#define HW_MCG_ATCVH_ADDR(x) ((x) + 0xAU) - -#define HW_MCG_ATCVH(x) (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR(x)) -#define HW_MCG_ATCVH_RD(x) (HW_MCG_ATCVH(x).U) -#define HW_MCG_ATCVH_WR(x, v) (HW_MCG_ATCVH(x).U = (v)) -#define HW_MCG_ATCVH_SET(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) | (v))) -#define HW_MCG_ATCVH_CLR(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) & ~(v))) -#define HW_MCG_ATCVH_TOG(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_ATCVH bitfields - */ - -/*! - * @name Register MCG_ATCVH, field ATCVH[7:0] (RW) - * - * Values are used by Auto Trim Machine to compare and adjust Internal Reference - * trim values during ATM SAR conversion. - */ -/*@{*/ -#define BP_MCG_ATCVH_ATCVH (0U) /*!< Bit position for MCG_ATCVH_ATCVH. */ -#define BM_MCG_ATCVH_ATCVH (0xFFU) /*!< Bit mask for MCG_ATCVH_ATCVH. */ -#define BS_MCG_ATCVH_ATCVH (8U) /*!< Bit field size in bits for MCG_ATCVH_ATCVH. */ - -/*! @brief Read current value of the MCG_ATCVH_ATCVH field. */ -#define BR_MCG_ATCVH_ATCVH(x) (HW_MCG_ATCVH(x).U) - -/*! @brief Format value for bitfield MCG_ATCVH_ATCVH. */ -#define BF_MCG_ATCVH_ATCVH(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVH_ATCVH) & BM_MCG_ATCVH_ATCVH) - -/*! @brief Set the ATCVH field to a new value. */ -#define BW_MCG_ATCVH_ATCVH(x, v) (HW_MCG_ATCVH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_atcvl -{ - uint8_t U; - struct _hw_mcg_atcvl_bitfields - { - uint8_t ATCVL : 8; /*!< [7:0] ATM Compare Value Low */ - } B; -} hw_mcg_atcvl_t; - -/*! - * @name Constants and macros for entire MCG_ATCVL register - */ -/*@{*/ -#define HW_MCG_ATCVL_ADDR(x) ((x) + 0xBU) - -#define HW_MCG_ATCVL(x) (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR(x)) -#define HW_MCG_ATCVL_RD(x) (HW_MCG_ATCVL(x).U) -#define HW_MCG_ATCVL_WR(x, v) (HW_MCG_ATCVL(x).U = (v)) -#define HW_MCG_ATCVL_SET(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) | (v))) -#define HW_MCG_ATCVL_CLR(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) & ~(v))) -#define HW_MCG_ATCVL_TOG(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_ATCVL bitfields - */ - -/*! - * @name Register MCG_ATCVL, field ATCVL[7:0] (RW) - * - * Values are used by Auto Trim Machine to compare and adjust Internal Reference - * trim values during ATM SAR conversion. - */ -/*@{*/ -#define BP_MCG_ATCVL_ATCVL (0U) /*!< Bit position for MCG_ATCVL_ATCVL. */ -#define BM_MCG_ATCVL_ATCVL (0xFFU) /*!< Bit mask for MCG_ATCVL_ATCVL. */ -#define BS_MCG_ATCVL_ATCVL (8U) /*!< Bit field size in bits for MCG_ATCVL_ATCVL. */ - -/*! @brief Read current value of the MCG_ATCVL_ATCVL field. */ -#define BR_MCG_ATCVL_ATCVL(x) (HW_MCG_ATCVL(x).U) - -/*! @brief Format value for bitfield MCG_ATCVL_ATCVL. */ -#define BF_MCG_ATCVL_ATCVL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVL_ATCVL) & BM_MCG_ATCVL_ATCVL) - -/*! @brief Set the ATCVL field to a new value. */ -#define BW_MCG_ATCVL_ATCVL(x, v) (HW_MCG_ATCVL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C7 - MCG Control 7 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C7 - MCG Control 7 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c7 -{ - uint8_t U; - struct _hw_mcg_c7_bitfields - { - uint8_t OSCSEL : 2; /*!< [1:0] MCG OSC Clock Select */ - uint8_t RESERVED0 : 6; /*!< [7:2] */ - } B; -} hw_mcg_c7_t; - -/*! - * @name Constants and macros for entire MCG_C7 register - */ -/*@{*/ -#define HW_MCG_C7_ADDR(x) ((x) + 0xCU) - -#define HW_MCG_C7(x) (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR(x)) -#define HW_MCG_C7_RD(x) (HW_MCG_C7(x).U) -#define HW_MCG_C7_WR(x, v) (HW_MCG_C7(x).U = (v)) -#define HW_MCG_C7_SET(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) | (v))) -#define HW_MCG_C7_CLR(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) & ~(v))) -#define HW_MCG_C7_TOG(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C7 bitfields - */ - -/*! - * @name Register MCG_C7, field OSCSEL[1:0] (RW) - * - * Selects the MCG FLL external reference clock - * - * Values: - * - 00 - Selects Oscillator (OSCCLK0). - * - 01 - Selects 32 kHz RTC Oscillator. - * - 10 - Selects Oscillator (OSCCLK1). - * - 11 - RESERVED - */ -/*@{*/ -#define BP_MCG_C7_OSCSEL (0U) /*!< Bit position for MCG_C7_OSCSEL. */ -#define BM_MCG_C7_OSCSEL (0x03U) /*!< Bit mask for MCG_C7_OSCSEL. */ -#define BS_MCG_C7_OSCSEL (2U) /*!< Bit field size in bits for MCG_C7_OSCSEL. */ - -/*! @brief Read current value of the MCG_C7_OSCSEL field. */ -#define BR_MCG_C7_OSCSEL(x) (HW_MCG_C7(x).B.OSCSEL) - -/*! @brief Format value for bitfield MCG_C7_OSCSEL. */ -#define BF_MCG_C7_OSCSEL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C7_OSCSEL) & BM_MCG_C7_OSCSEL) - -/*! @brief Set the OSCSEL field to a new value. */ -#define BW_MCG_C7_OSCSEL(x, v) (HW_MCG_C7_WR(x, (HW_MCG_C7_RD(x) & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C8 - MCG Control 8 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C8 - MCG Control 8 Register (RW) - * - * Reset value: 0x80U - */ -typedef union _hw_mcg_c8 -{ - uint8_t U; - struct _hw_mcg_c8_bitfields - { - uint8_t LOCS1 : 1; /*!< [0] RTC Loss of Clock Status */ - uint8_t RESERVED0 : 4; /*!< [4:1] */ - uint8_t CME1 : 1; /*!< [5] Clock Monitor Enable1 */ - uint8_t LOLRE : 1; /*!< [6] PLL Loss of Lock Reset Enable */ - uint8_t LOCRE1 : 1; /*!< [7] Loss of Clock Reset Enable */ - } B; -} hw_mcg_c8_t; - -/*! - * @name Constants and macros for entire MCG_C8 register - */ -/*@{*/ -#define HW_MCG_C8_ADDR(x) ((x) + 0xDU) - -#define HW_MCG_C8(x) (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR(x)) -#define HW_MCG_C8_RD(x) (HW_MCG_C8(x).U) -#define HW_MCG_C8_WR(x, v) (HW_MCG_C8(x).U = (v)) -#define HW_MCG_C8_SET(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) | (v))) -#define HW_MCG_C8_CLR(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) & ~(v))) -#define HW_MCG_C8_TOG(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C8 bitfields - */ - -/*! - * @name Register MCG_C8, field LOCS1[0] (W1C) - * - * This bit indicates when a loss of clock has occurred. This bit is cleared by - * writing a logic 1 to it when set. - * - * Values: - * - 0 - Loss of RTC has not occur. - * - 1 - Loss of RTC has occur - */ -/*@{*/ -#define BP_MCG_C8_LOCS1 (0U) /*!< Bit position for MCG_C8_LOCS1. */ -#define BM_MCG_C8_LOCS1 (0x01U) /*!< Bit mask for MCG_C8_LOCS1. */ -#define BS_MCG_C8_LOCS1 (1U) /*!< Bit field size in bits for MCG_C8_LOCS1. */ - -/*! @brief Read current value of the MCG_C8_LOCS1 field. */ -#define BR_MCG_C8_LOCS1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1)) - -/*! @brief Format value for bitfield MCG_C8_LOCS1. */ -#define BF_MCG_C8_LOCS1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCS1) & BM_MCG_C8_LOCS1) - -/*! @brief Set the LOCS1 field to a new value. */ -#define BW_MCG_C8_LOCS1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C8, field CME1[5] (RW) - * - * Enables the loss of clock monitoring circuit for the output of the RTC - * external reference clock. The LOCRE1 bit will determine whether an interrupt or a - * reset request is generated following a loss of RTC clock indication. The CME1 - * bit should be set to a logic 1 when the MCG is in an operational mode that uses - * the RTC as its external reference clock or if the RTC is operational. CME1 bit - * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a - * reset request may occur when in Stop mode. CME1 should also be set to a logic 0 - * before entering VLPR or VLPW power modes. - * - * Values: - * - 0 - External clock monitor is disabled for RTC clock. - * - 1 - External clock monitor is enabled for RTC clock. - */ -/*@{*/ -#define BP_MCG_C8_CME1 (5U) /*!< Bit position for MCG_C8_CME1. */ -#define BM_MCG_C8_CME1 (0x20U) /*!< Bit mask for MCG_C8_CME1. */ -#define BS_MCG_C8_CME1 (1U) /*!< Bit field size in bits for MCG_C8_CME1. */ - -/*! @brief Read current value of the MCG_C8_CME1 field. */ -#define BR_MCG_C8_CME1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1)) - -/*! @brief Format value for bitfield MCG_C8_CME1. */ -#define BF_MCG_C8_CME1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_CME1) & BM_MCG_C8_CME1) - -/*! @brief Set the CME1 field to a new value. */ -#define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C8, field LOLRE[6] (RW) - * - * Determines if an interrupt or a reset request is made following a PLL loss of - * lock. - * - * Values: - * - 0 - Interrupt request is generated on a PLL loss of lock indication. The - * PLL loss of lock interrupt enable bit must also be set to generate the - * interrupt request. - * - 1 - Generate a reset request on a PLL loss of lock indication. - */ -/*@{*/ -#define BP_MCG_C8_LOLRE (6U) /*!< Bit position for MCG_C8_LOLRE. */ -#define BM_MCG_C8_LOLRE (0x40U) /*!< Bit mask for MCG_C8_LOLRE. */ -#define BS_MCG_C8_LOLRE (1U) /*!< Bit field size in bits for MCG_C8_LOLRE. */ - -/*! @brief Read current value of the MCG_C8_LOLRE field. */ -#define BR_MCG_C8_LOLRE(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE)) - -/*! @brief Format value for bitfield MCG_C8_LOLRE. */ -#define BF_MCG_C8_LOLRE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE) - -/*! @brief Set the LOLRE field to a new value. */ -#define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C8, field LOCRE1[7] (RW) - * - * Determines if a interrupt or a reset request is made following a loss of RTC - * external reference clock. The LOCRE1 only has an affect when CME1 is set. - * - * Values: - * - 0 - Interrupt request is generated on a loss of RTC external reference - * clock. - * - 1 - Generate a reset request on a loss of RTC external reference clock - */ -/*@{*/ -#define BP_MCG_C8_LOCRE1 (7U) /*!< Bit position for MCG_C8_LOCRE1. */ -#define BM_MCG_C8_LOCRE1 (0x80U) /*!< Bit mask for MCG_C8_LOCRE1. */ -#define BS_MCG_C8_LOCRE1 (1U) /*!< Bit field size in bits for MCG_C8_LOCRE1. */ - -/*! @brief Read current value of the MCG_C8_LOCRE1 field. */ -#define BR_MCG_C8_LOCRE1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1)) - -/*! @brief Format value for bitfield MCG_C8_LOCRE1. */ -#define BF_MCG_C8_LOCRE1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCRE1) & BM_MCG_C8_LOCRE1) - -/*! @brief Set the LOCRE1 field to a new value. */ -#define BW_MCG_C8_LOCRE1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_mcg_t - module struct - ******************************************************************************/ -/*! - * @brief All MCG module registers. - */ -#pragma pack(1) -typedef struct _hw_mcg -{ - __IO hw_mcg_c1_t C1; /*!< [0x0] MCG Control 1 Register */ - __IO hw_mcg_c2_t C2; /*!< [0x1] MCG Control 2 Register */ - __IO hw_mcg_c3_t C3; /*!< [0x2] MCG Control 3 Register */ - __IO hw_mcg_c4_t C4; /*!< [0x3] MCG Control 4 Register */ - __IO hw_mcg_c5_t C5; /*!< [0x4] MCG Control 5 Register */ - __IO hw_mcg_c6_t C6; /*!< [0x5] MCG Control 6 Register */ - __IO hw_mcg_s_t S; /*!< [0x6] MCG Status Register */ - uint8_t _reserved0[1]; - __IO hw_mcg_sc_t SC; /*!< [0x8] MCG Status and Control Register */ - uint8_t _reserved1[1]; - __IO hw_mcg_atcvh_t ATCVH; /*!< [0xA] MCG Auto Trim Compare Value High Register */ - __IO hw_mcg_atcvl_t ATCVL; /*!< [0xB] MCG Auto Trim Compare Value Low Register */ - __IO hw_mcg_c7_t C7; /*!< [0xC] MCG Control 7 Register */ - __IO hw_mcg_c8_t C8; /*!< [0xD] MCG Control 8 Register */ -} hw_mcg_t; -#pragma pack() - -/*! @brief Macro to access all MCG registers. */ -/*! @param x MCG module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_MCG(MCG_BASE). */ -#define HW_MCG(x) (*(hw_mcg_t *)(x)) - -#endif /* __HW_MCG_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h deleted file mode 100644 index c32804d007a..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h +++ /dev/null @@ -1,713 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_MCM_REGISTERS_H__ -#define __HW_MCM_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 MCM - * - * Core Platform Miscellaneous Control Module - * - * Registers defined in this header file: - * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration - * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration - * - HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register - * - HW_MCM_ISCR - Interrupt Status and Control Register - * - HW_MCM_CPO - Compute Operation Control Register - * - * - hw_mcm_t - Struct containing all module registers. - */ - -#define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */ - -/******************************************************************************* - * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration - ******************************************************************************/ - -/*! - * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO) - * - * Reset value: 0x001FU - * - * PLASC is a 16-bit read-only register identifying the presence/absence of bus - * slave connections to the device's crossbar switch. - */ -typedef union _hw_mcm_plasc -{ - uint16_t U; - struct _hw_mcm_plasc_bitfields - { - uint16_t ASC : 8; /*!< [7:0] Each bit in the ASC field indicates - * whether there is a corresponding connection to the crossbar switch's slave - * input port. */ - uint16_t RESERVED0 : 8; /*!< [15:8] */ - } B; -} hw_mcm_plasc_t; - -/*! - * @name Constants and macros for entire MCM_PLASC register - */ -/*@{*/ -#define HW_MCM_PLASC_ADDR(x) ((x) + 0x8U) - -#define HW_MCM_PLASC(x) (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x)) -#define HW_MCM_PLASC_RD(x) (HW_MCM_PLASC(x).U) -/*@}*/ - -/* - * Constants & macros for individual MCM_PLASC bitfields - */ - -/*! - * @name Register MCM_PLASC, field ASC[7:0] (RO) - * - * Values: - * - 0 - A bus slave connection to AXBS input port n is absent - * - 1 - A bus slave connection to AXBS input port n is present - */ -/*@{*/ -#define BP_MCM_PLASC_ASC (0U) /*!< Bit position for MCM_PLASC_ASC. */ -#define BM_MCM_PLASC_ASC (0x00FFU) /*!< Bit mask for MCM_PLASC_ASC. */ -#define BS_MCM_PLASC_ASC (8U) /*!< Bit field size in bits for MCM_PLASC_ASC. */ - -/*! @brief Read current value of the MCM_PLASC_ASC field. */ -#define BR_MCM_PLASC_ASC(x) (HW_MCM_PLASC(x).B.ASC) -/*@}*/ - -/******************************************************************************* - * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration - ******************************************************************************/ - -/*! - * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO) - * - * Reset value: 0x0017U - * - * PLAMC is a 16-bit read-only register identifying the presence/absence of bus - * master connections to the device's crossbar switch. - */ -typedef union _hw_mcm_plamc -{ - uint16_t U; - struct _hw_mcm_plamc_bitfields - { - uint16_t AMC : 8; /*!< [7:0] Each bit in the AMC field indicates - * whether there is a corresponding connection to the AXBS master input port. */ - uint16_t RESERVED0 : 8; /*!< [15:8] */ - } B; -} hw_mcm_plamc_t; - -/*! - * @name Constants and macros for entire MCM_PLAMC register - */ -/*@{*/ -#define HW_MCM_PLAMC_ADDR(x) ((x) + 0xAU) - -#define HW_MCM_PLAMC(x) (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x)) -#define HW_MCM_PLAMC_RD(x) (HW_MCM_PLAMC(x).U) -/*@}*/ - -/* - * Constants & macros for individual MCM_PLAMC bitfields - */ - -/*! - * @name Register MCM_PLAMC, field AMC[7:0] (RO) - * - * Values: - * - 0 - A bus master connection to AXBS input port n is absent - * - 1 - A bus master connection to AXBS input port n is present - */ -/*@{*/ -#define BP_MCM_PLAMC_AMC (0U) /*!< Bit position for MCM_PLAMC_AMC. */ -#define BM_MCM_PLAMC_AMC (0x00FFU) /*!< Bit mask for MCM_PLAMC_AMC. */ -#define BS_MCM_PLAMC_AMC (8U) /*!< Bit field size in bits for MCM_PLAMC_AMC. */ - -/*! @brief Read current value of the MCM_PLAMC_AMC field. */ -#define BR_MCM_PLAMC_AMC(x) (HW_MCM_PLAMC(x).B.AMC) -/*@}*/ - -/******************************************************************************* - * HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register - ******************************************************************************/ - -/*! - * @brief HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register (RW) - * - * Reset value: 0x00000000U - * - * The PLACR register selects the arbitration policy for the crossbar masters. - */ -typedef union _hw_mcm_placr -{ - uint32_t U; - struct _hw_mcm_placr_bitfields - { - uint32_t RESERVED0 : 9; /*!< [8:0] */ - uint32_t ARB : 1; /*!< [9] Arbitration select */ - uint32_t RESERVED1 : 22; /*!< [31:10] */ - } B; -} hw_mcm_placr_t; - -/*! - * @name Constants and macros for entire MCM_PLACR register - */ -/*@{*/ -#define HW_MCM_PLACR_ADDR(x) ((x) + 0xCU) - -#define HW_MCM_PLACR(x) (*(__IO hw_mcm_placr_t *) HW_MCM_PLACR_ADDR(x)) -#define HW_MCM_PLACR_RD(x) (HW_MCM_PLACR(x).U) -#define HW_MCM_PLACR_WR(x, v) (HW_MCM_PLACR(x).U = (v)) -#define HW_MCM_PLACR_SET(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) | (v))) -#define HW_MCM_PLACR_CLR(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) & ~(v))) -#define HW_MCM_PLACR_TOG(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_PLACR bitfields - */ - -/*! - * @name Register MCM_PLACR, field ARB[9] (RW) - * - * Values: - * - 0 - Fixed-priority arbitration for the crossbar masters - * - 1 - Round-robin arbitration for the crossbar masters - */ -/*@{*/ -#define BP_MCM_PLACR_ARB (9U) /*!< Bit position for MCM_PLACR_ARB. */ -#define BM_MCM_PLACR_ARB (0x00000200U) /*!< Bit mask for MCM_PLACR_ARB. */ -#define BS_MCM_PLACR_ARB (1U) /*!< Bit field size in bits for MCM_PLACR_ARB. */ - -/*! @brief Read current value of the MCM_PLACR_ARB field. */ -#define BR_MCM_PLACR_ARB(x) (HW_MCM_PLACR(x).B.ARB) - -/*! @brief Format value for bitfield MCM_PLACR_ARB. */ -#define BF_MCM_PLACR_ARB(v) ((uint32_t)((uint32_t)(v) << BP_MCM_PLACR_ARB) & BM_MCM_PLACR_ARB) - -/*! @brief Set the ARB field to a new value. */ -#define BW_MCM_PLACR_ARB(x, v) (HW_MCM_PLACR_WR(x, (HW_MCM_PLACR_RD(x) & ~BM_MCM_PLACR_ARB) | BF_MCM_PLACR_ARB(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCM_ISCR - Interrupt Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_MCM_ISCR - Interrupt Status and Control Register (RW) - * - * Reset value: 0x00020000U - * - * The MCM_ISCR register includes the enable and status bits associated with the - * core's floating-point exceptions. The individual event indicators are first - * qualified with their exception enables and then logically summed to form an - * interrupt request sent to the core's NVIC. Bits 15-8 are read-only indicator - * flags based on the processor's FPSCR register. Attempted writes to these bits are - * ignored. Once set, the flags remain asserted until software clears the - * corresponding FPSCR bit. - */ -typedef union _hw_mcm_iscr -{ - uint32_t U; - struct _hw_mcm_iscr_bitfields - { - uint32_t RESERVED0 : 8; /*!< [7:0] */ - uint32_t FIOC : 1; /*!< [8] FPU invalid operation interrupt status */ - uint32_t FDZC : 1; /*!< [9] FPU divide-by-zero interrupt status */ - uint32_t FOFC : 1; /*!< [10] FPU overflow interrupt status */ - uint32_t FUFC : 1; /*!< [11] FPU underflow interrupt status */ - uint32_t FIXC : 1; /*!< [12] FPU inexact interrupt status */ - uint32_t RESERVED1 : 2; /*!< [14:13] */ - uint32_t FIDC : 1; /*!< [15] FPU input denormal interrupt status */ - uint32_t RESERVED2 : 8; /*!< [23:16] */ - uint32_t FIOCE : 1; /*!< [24] FPU invalid operation interrupt enable - * */ - uint32_t FDZCE : 1; /*!< [25] FPU divide-by-zero interrupt enable */ - uint32_t FOFCE : 1; /*!< [26] FPU overflow interrupt enable */ - uint32_t FUFCE : 1; /*!< [27] FPU underflow interrupt enable */ - uint32_t FIXCE : 1; /*!< [28] FPU inexact interrupt enable */ - uint32_t RESERVED3 : 2; /*!< [30:29] */ - uint32_t FIDCE : 1; /*!< [31] FPU input denormal interrupt enable */ - } B; -} hw_mcm_iscr_t; - -/*! - * @name Constants and macros for entire MCM_ISCR register - */ -/*@{*/ -#define HW_MCM_ISCR_ADDR(x) ((x) + 0x10U) - -#define HW_MCM_ISCR(x) (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x)) -#define HW_MCM_ISCR_RD(x) (HW_MCM_ISCR(x).U) -#define HW_MCM_ISCR_WR(x, v) (HW_MCM_ISCR(x).U = (v)) -#define HW_MCM_ISCR_SET(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) | (v))) -#define HW_MCM_ISCR_CLR(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v))) -#define HW_MCM_ISCR_TOG(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_ISCR bitfields - */ - -/*! - * @name Register MCM_ISCR, field FIOC[8] (RO) - * - * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an - * illegal operation has been detected in the processor's FPU. Once set, this bit - * remains set until software clears the FPSCR[IOC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FIOC (8U) /*!< Bit position for MCM_ISCR_FIOC. */ -#define BM_MCM_ISCR_FIOC (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */ -#define BS_MCM_ISCR_FIOC (1U) /*!< Bit field size in bits for MCM_ISCR_FIOC. */ - -/*! @brief Read current value of the MCM_ISCR_FIOC field. */ -#define BR_MCM_ISCR_FIOC(x) (HW_MCM_ISCR(x).B.FIOC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FDZC[9] (RO) - * - * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a - * divide by zero has been detected in the processor's FPU. Once set, this bit remains - * set until software clears the FPSCR[DZC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FDZC (9U) /*!< Bit position for MCM_ISCR_FDZC. */ -#define BM_MCM_ISCR_FDZC (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */ -#define BS_MCM_ISCR_FDZC (1U) /*!< Bit field size in bits for MCM_ISCR_FDZC. */ - -/*! @brief Read current value of the MCM_ISCR_FDZC field. */ -#define BR_MCM_ISCR_FDZC(x) (HW_MCM_ISCR(x).B.FDZC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FOFC[10] (RO) - * - * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an - * overflow has been detected in the processor's FPU. Once set, this bit remains set - * until software clears the FPSCR[OFC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FOFC (10U) /*!< Bit position for MCM_ISCR_FOFC. */ -#define BM_MCM_ISCR_FOFC (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */ -#define BS_MCM_ISCR_FOFC (1U) /*!< Bit field size in bits for MCM_ISCR_FOFC. */ - -/*! @brief Read current value of the MCM_ISCR_FOFC field. */ -#define BR_MCM_ISCR_FOFC(x) (HW_MCM_ISCR(x).B.FOFC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FUFC[11] (RO) - * - * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an - * underflow has been detected in the processor's FPU. Once set, this bit remains set - * until software clears the FPSCR[UFC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FUFC (11U) /*!< Bit position for MCM_ISCR_FUFC. */ -#define BM_MCM_ISCR_FUFC (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */ -#define BS_MCM_ISCR_FUFC (1U) /*!< Bit field size in bits for MCM_ISCR_FUFC. */ - -/*! @brief Read current value of the MCM_ISCR_FUFC field. */ -#define BR_MCM_ISCR_FUFC(x) (HW_MCM_ISCR(x).B.FUFC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIXC[12] (RO) - * - * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an - * inexact number has been detected in the processor's FPU. Once set, this bit - * remains set until software clears the FPSCR[IXC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FIXC (12U) /*!< Bit position for MCM_ISCR_FIXC. */ -#define BM_MCM_ISCR_FIXC (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */ -#define BS_MCM_ISCR_FIXC (1U) /*!< Bit field size in bits for MCM_ISCR_FIXC. */ - -/*! @brief Read current value of the MCM_ISCR_FIXC field. */ -#define BR_MCM_ISCR_FIXC(x) (HW_MCM_ISCR(x).B.FIXC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIDC[15] (RO) - * - * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input - * denormalized number has been detected in the processor's FPU. Once set, this - * bit remains set until software clears the FPSCR[IDC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FIDC (15U) /*!< Bit position for MCM_ISCR_FIDC. */ -#define BM_MCM_ISCR_FIDC (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */ -#define BS_MCM_ISCR_FIDC (1U) /*!< Bit field size in bits for MCM_ISCR_FIDC. */ - -/*! @brief Read current value of the MCM_ISCR_FIDC field. */ -#define BR_MCM_ISCR_FIDC(x) (HW_MCM_ISCR(x).B.FIDC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIOCE[24] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FIOCE (24U) /*!< Bit position for MCM_ISCR_FIOCE. */ -#define BM_MCM_ISCR_FIOCE (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */ -#define BS_MCM_ISCR_FIOCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIOCE. */ - -/*! @brief Read current value of the MCM_ISCR_FIOCE field. */ -#define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE) - -/*! @brief Format value for bitfield MCM_ISCR_FIOCE. */ -#define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE) - -/*! @brief Set the FIOCE field to a new value. */ -#define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FDZCE[25] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FDZCE (25U) /*!< Bit position for MCM_ISCR_FDZCE. */ -#define BM_MCM_ISCR_FDZCE (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */ -#define BS_MCM_ISCR_FDZCE (1U) /*!< Bit field size in bits for MCM_ISCR_FDZCE. */ - -/*! @brief Read current value of the MCM_ISCR_FDZCE field. */ -#define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE) - -/*! @brief Format value for bitfield MCM_ISCR_FDZCE. */ -#define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE) - -/*! @brief Set the FDZCE field to a new value. */ -#define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FOFCE[26] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FOFCE (26U) /*!< Bit position for MCM_ISCR_FOFCE. */ -#define BM_MCM_ISCR_FOFCE (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */ -#define BS_MCM_ISCR_FOFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FOFCE. */ - -/*! @brief Read current value of the MCM_ISCR_FOFCE field. */ -#define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE) - -/*! @brief Format value for bitfield MCM_ISCR_FOFCE. */ -#define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE) - -/*! @brief Set the FOFCE field to a new value. */ -#define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FUFCE[27] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FUFCE (27U) /*!< Bit position for MCM_ISCR_FUFCE. */ -#define BM_MCM_ISCR_FUFCE (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */ -#define BS_MCM_ISCR_FUFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FUFCE. */ - -/*! @brief Read current value of the MCM_ISCR_FUFCE field. */ -#define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE) - -/*! @brief Format value for bitfield MCM_ISCR_FUFCE. */ -#define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE) - -/*! @brief Set the FUFCE field to a new value. */ -#define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIXCE[28] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FIXCE (28U) /*!< Bit position for MCM_ISCR_FIXCE. */ -#define BM_MCM_ISCR_FIXCE (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */ -#define BS_MCM_ISCR_FIXCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIXCE. */ - -/*! @brief Read current value of the MCM_ISCR_FIXCE field. */ -#define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE) - -/*! @brief Format value for bitfield MCM_ISCR_FIXCE. */ -#define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE) - -/*! @brief Set the FIXCE field to a new value. */ -#define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIDCE[31] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FIDCE (31U) /*!< Bit position for MCM_ISCR_FIDCE. */ -#define BM_MCM_ISCR_FIDCE (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */ -#define BS_MCM_ISCR_FIDCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIDCE. */ - -/*! @brief Read current value of the MCM_ISCR_FIDCE field. */ -#define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE) - -/*! @brief Format value for bitfield MCM_ISCR_FIDCE. */ -#define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE) - -/*! @brief Set the FIDCE field to a new value. */ -#define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCM_CPO - Compute Operation Control Register - ******************************************************************************/ - -/*! - * @brief HW_MCM_CPO - Compute Operation Control Register (RW) - * - * Reset value: 0x00000000U - * - * This register controls the Compute Operation. - */ -typedef union _hw_mcm_cpo -{ - uint32_t U; - struct _hw_mcm_cpo_bitfields - { - uint32_t CPOREQ : 1; /*!< [0] Compute Operation request */ - uint32_t CPOACK : 1; /*!< [1] Compute Operation acknowledge */ - uint32_t CPOWOI : 1; /*!< [2] Compute Operation wakeup on interrupt */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_mcm_cpo_t; - -/*! - * @name Constants and macros for entire MCM_CPO register - */ -/*@{*/ -#define HW_MCM_CPO_ADDR(x) ((x) + 0x40U) - -#define HW_MCM_CPO(x) (*(__IO hw_mcm_cpo_t *) HW_MCM_CPO_ADDR(x)) -#define HW_MCM_CPO_RD(x) (HW_MCM_CPO(x).U) -#define HW_MCM_CPO_WR(x, v) (HW_MCM_CPO(x).U = (v)) -#define HW_MCM_CPO_SET(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) | (v))) -#define HW_MCM_CPO_CLR(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) & ~(v))) -#define HW_MCM_CPO_TOG(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_CPO bitfields - */ - -/*! - * @name Register MCM_CPO, field CPOREQ[0] (RW) - * - * This bit is auto-cleared by vector fetching if CPOWOI = 1. - * - * Values: - * - 0 - Request is cleared. - * - 1 - Request Compute Operation. - */ -/*@{*/ -#define BP_MCM_CPO_CPOREQ (0U) /*!< Bit position for MCM_CPO_CPOREQ. */ -#define BM_MCM_CPO_CPOREQ (0x00000001U) /*!< Bit mask for MCM_CPO_CPOREQ. */ -#define BS_MCM_CPO_CPOREQ (1U) /*!< Bit field size in bits for MCM_CPO_CPOREQ. */ - -/*! @brief Read current value of the MCM_CPO_CPOREQ field. */ -#define BR_MCM_CPO_CPOREQ(x) (HW_MCM_CPO(x).B.CPOREQ) - -/*! @brief Format value for bitfield MCM_CPO_CPOREQ. */ -#define BF_MCM_CPO_CPOREQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOREQ) & BM_MCM_CPO_CPOREQ) - -/*! @brief Set the CPOREQ field to a new value. */ -#define BW_MCM_CPO_CPOREQ(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOREQ) | BF_MCM_CPO_CPOREQ(v))) -/*@}*/ - -/*! - * @name Register MCM_CPO, field CPOACK[1] (RO) - * - * Values: - * - 0 - Compute operation entry has not completed or compute operation exit has - * completed. - * - 1 - Compute operation entry has completed or compute operation exit has not - * completed. - */ -/*@{*/ -#define BP_MCM_CPO_CPOACK (1U) /*!< Bit position for MCM_CPO_CPOACK. */ -#define BM_MCM_CPO_CPOACK (0x00000002U) /*!< Bit mask for MCM_CPO_CPOACK. */ -#define BS_MCM_CPO_CPOACK (1U) /*!< Bit field size in bits for MCM_CPO_CPOACK. */ - -/*! @brief Read current value of the MCM_CPO_CPOACK field. */ -#define BR_MCM_CPO_CPOACK(x) (HW_MCM_CPO(x).B.CPOACK) -/*@}*/ - -/*! - * @name Register MCM_CPO, field CPOWOI[2] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - When set, the CPOREQ is cleared on any interrupt or exception vector - * fetch. - */ -/*@{*/ -#define BP_MCM_CPO_CPOWOI (2U) /*!< Bit position for MCM_CPO_CPOWOI. */ -#define BM_MCM_CPO_CPOWOI (0x00000004U) /*!< Bit mask for MCM_CPO_CPOWOI. */ -#define BS_MCM_CPO_CPOWOI (1U) /*!< Bit field size in bits for MCM_CPO_CPOWOI. */ - -/*! @brief Read current value of the MCM_CPO_CPOWOI field. */ -#define BR_MCM_CPO_CPOWOI(x) (HW_MCM_CPO(x).B.CPOWOI) - -/*! @brief Format value for bitfield MCM_CPO_CPOWOI. */ -#define BF_MCM_CPO_CPOWOI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOWOI) & BM_MCM_CPO_CPOWOI) - -/*! @brief Set the CPOWOI field to a new value. */ -#define BW_MCM_CPO_CPOWOI(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOWOI) | BF_MCM_CPO_CPOWOI(v))) -/*@}*/ - -/******************************************************************************* - * hw_mcm_t - module struct - ******************************************************************************/ -/*! - * @brief All MCM module registers. - */ -#pragma pack(1) -typedef struct _hw_mcm -{ - uint8_t _reserved0[8]; - __I hw_mcm_plasc_t PLASC; /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */ - __I hw_mcm_plamc_t PLAMC; /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */ - __IO hw_mcm_placr_t PLACR; /*!< [0xC] Crossbar Switch (AXBS) Control Register */ - __IO hw_mcm_iscr_t ISCR; /*!< [0x10] Interrupt Status and Control Register */ - uint8_t _reserved1[44]; - __IO hw_mcm_cpo_t CPO; /*!< [0x40] Compute Operation Control Register */ -} hw_mcm_t; -#pragma pack() - -/*! @brief Macro to access all MCM registers. */ -/*! @param x MCM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_MCM(MCM_BASE). */ -#define HW_MCM(x) (*(hw_mcm_t *)(x)) - -#endif /* __HW_MCM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h deleted file mode 100644 index 579cb563752..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h +++ /dev/null @@ -1,869 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_NV_REGISTERS_H__ -#define __HW_NV_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 NV - * - * Flash configuration field - * - * Registers defined in this header file: - * - HW_NV_BACKKEY3 - Backdoor Comparison Key 3. - * - HW_NV_BACKKEY2 - Backdoor Comparison Key 2. - * - HW_NV_BACKKEY1 - Backdoor Comparison Key 1. - * - HW_NV_BACKKEY0 - Backdoor Comparison Key 0. - * - HW_NV_BACKKEY7 - Backdoor Comparison Key 7. - * - HW_NV_BACKKEY6 - Backdoor Comparison Key 6. - * - HW_NV_BACKKEY5 - Backdoor Comparison Key 5. - * - HW_NV_BACKKEY4 - Backdoor Comparison Key 4. - * - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register - * - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register - * - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register - * - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register - * - HW_NV_FSEC - Non-volatile Flash Security Register - * - HW_NV_FOPT - Non-volatile Flash Option Register - * - * - hw_nv_t - Struct containing all module registers. - */ - -#define HW_NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */ - -/******************************************************************************* - * HW_NV_BACKKEY3 - Backdoor Comparison Key 3. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey3 -{ - uint8_t U; - struct _hw_nv_backkey3_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey3_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY3 register - */ -/*@{*/ -#define HW_NV_BACKKEY3_ADDR(x) ((x) + 0x0U) - -#define HW_NV_BACKKEY3(x) (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR(x)) -#define HW_NV_BACKKEY3_RD(x) (HW_NV_BACKKEY3(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY3 bitfields - */ - -/*! - * @name Register NV_BACKKEY3, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY3_KEY (0U) /*!< Bit position for NV_BACKKEY3_KEY. */ -#define BM_NV_BACKKEY3_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY3_KEY. */ -#define BS_NV_BACKKEY3_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY3_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY3_KEY field. */ -#define BR_NV_BACKKEY3_KEY(x) (HW_NV_BACKKEY3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY2 - Backdoor Comparison Key 2. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey2 -{ - uint8_t U; - struct _hw_nv_backkey2_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey2_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY2 register - */ -/*@{*/ -#define HW_NV_BACKKEY2_ADDR(x) ((x) + 0x1U) - -#define HW_NV_BACKKEY2(x) (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR(x)) -#define HW_NV_BACKKEY2_RD(x) (HW_NV_BACKKEY2(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY2 bitfields - */ - -/*! - * @name Register NV_BACKKEY2, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY2_KEY (0U) /*!< Bit position for NV_BACKKEY2_KEY. */ -#define BM_NV_BACKKEY2_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY2_KEY. */ -#define BS_NV_BACKKEY2_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY2_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY2_KEY field. */ -#define BR_NV_BACKKEY2_KEY(x) (HW_NV_BACKKEY2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY1 - Backdoor Comparison Key 1. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey1 -{ - uint8_t U; - struct _hw_nv_backkey1_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey1_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY1 register - */ -/*@{*/ -#define HW_NV_BACKKEY1_ADDR(x) ((x) + 0x2U) - -#define HW_NV_BACKKEY1(x) (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR(x)) -#define HW_NV_BACKKEY1_RD(x) (HW_NV_BACKKEY1(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY1 bitfields - */ - -/*! - * @name Register NV_BACKKEY1, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY1_KEY (0U) /*!< Bit position for NV_BACKKEY1_KEY. */ -#define BM_NV_BACKKEY1_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY1_KEY. */ -#define BS_NV_BACKKEY1_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY1_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY1_KEY field. */ -#define BR_NV_BACKKEY1_KEY(x) (HW_NV_BACKKEY1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY0 - Backdoor Comparison Key 0. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey0 -{ - uint8_t U; - struct _hw_nv_backkey0_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey0_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY0 register - */ -/*@{*/ -#define HW_NV_BACKKEY0_ADDR(x) ((x) + 0x3U) - -#define HW_NV_BACKKEY0(x) (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR(x)) -#define HW_NV_BACKKEY0_RD(x) (HW_NV_BACKKEY0(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY0 bitfields - */ - -/*! - * @name Register NV_BACKKEY0, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY0_KEY (0U) /*!< Bit position for NV_BACKKEY0_KEY. */ -#define BM_NV_BACKKEY0_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY0_KEY. */ -#define BS_NV_BACKKEY0_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY0_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY0_KEY field. */ -#define BR_NV_BACKKEY0_KEY(x) (HW_NV_BACKKEY0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY7 - Backdoor Comparison Key 7. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey7 -{ - uint8_t U; - struct _hw_nv_backkey7_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey7_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY7 register - */ -/*@{*/ -#define HW_NV_BACKKEY7_ADDR(x) ((x) + 0x4U) - -#define HW_NV_BACKKEY7(x) (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR(x)) -#define HW_NV_BACKKEY7_RD(x) (HW_NV_BACKKEY7(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY7 bitfields - */ - -/*! - * @name Register NV_BACKKEY7, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY7_KEY (0U) /*!< Bit position for NV_BACKKEY7_KEY. */ -#define BM_NV_BACKKEY7_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY7_KEY. */ -#define BS_NV_BACKKEY7_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY7_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY7_KEY field. */ -#define BR_NV_BACKKEY7_KEY(x) (HW_NV_BACKKEY7(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY6 - Backdoor Comparison Key 6. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey6 -{ - uint8_t U; - struct _hw_nv_backkey6_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey6_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY6 register - */ -/*@{*/ -#define HW_NV_BACKKEY6_ADDR(x) ((x) + 0x5U) - -#define HW_NV_BACKKEY6(x) (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR(x)) -#define HW_NV_BACKKEY6_RD(x) (HW_NV_BACKKEY6(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY6 bitfields - */ - -/*! - * @name Register NV_BACKKEY6, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY6_KEY (0U) /*!< Bit position for NV_BACKKEY6_KEY. */ -#define BM_NV_BACKKEY6_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY6_KEY. */ -#define BS_NV_BACKKEY6_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY6_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY6_KEY field. */ -#define BR_NV_BACKKEY6_KEY(x) (HW_NV_BACKKEY6(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY5 - Backdoor Comparison Key 5. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey5 -{ - uint8_t U; - struct _hw_nv_backkey5_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey5_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY5 register - */ -/*@{*/ -#define HW_NV_BACKKEY5_ADDR(x) ((x) + 0x6U) - -#define HW_NV_BACKKEY5(x) (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR(x)) -#define HW_NV_BACKKEY5_RD(x) (HW_NV_BACKKEY5(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY5 bitfields - */ - -/*! - * @name Register NV_BACKKEY5, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY5_KEY (0U) /*!< Bit position for NV_BACKKEY5_KEY. */ -#define BM_NV_BACKKEY5_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY5_KEY. */ -#define BS_NV_BACKKEY5_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY5_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY5_KEY field. */ -#define BR_NV_BACKKEY5_KEY(x) (HW_NV_BACKKEY5(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY4 - Backdoor Comparison Key 4. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey4 -{ - uint8_t U; - struct _hw_nv_backkey4_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey4_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY4 register - */ -/*@{*/ -#define HW_NV_BACKKEY4_ADDR(x) ((x) + 0x7U) - -#define HW_NV_BACKKEY4(x) (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR(x)) -#define HW_NV_BACKKEY4_RD(x) (HW_NV_BACKKEY4(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY4 bitfields - */ - -/*! - * @name Register NV_BACKKEY4, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY4_KEY (0U) /*!< Bit position for NV_BACKKEY4_KEY. */ -#define BM_NV_BACKKEY4_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY4_KEY. */ -#define BS_NV_BACKKEY4_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY4_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY4_KEY field. */ -#define BR_NV_BACKKEY4_KEY(x) (HW_NV_BACKKEY4(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot3 -{ - uint8_t U; - struct _hw_nv_fprot3_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot3_t; - -/*! - * @name Constants and macros for entire NV_FPROT3 register - */ -/*@{*/ -#define HW_NV_FPROT3_ADDR(x) ((x) + 0x8U) - -#define HW_NV_FPROT3(x) (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR(x)) -#define HW_NV_FPROT3_RD(x) (HW_NV_FPROT3(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT3 bitfields - */ - -/*! - * @name Register NV_FPROT3, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT3_PROT (0U) /*!< Bit position for NV_FPROT3_PROT. */ -#define BM_NV_FPROT3_PROT (0xFFU) /*!< Bit mask for NV_FPROT3_PROT. */ -#define BS_NV_FPROT3_PROT (8U) /*!< Bit field size in bits for NV_FPROT3_PROT. */ - -/*! @brief Read current value of the NV_FPROT3_PROT field. */ -#define BR_NV_FPROT3_PROT(x) (HW_NV_FPROT3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot2 -{ - uint8_t U; - struct _hw_nv_fprot2_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot2_t; - -/*! - * @name Constants and macros for entire NV_FPROT2 register - */ -/*@{*/ -#define HW_NV_FPROT2_ADDR(x) ((x) + 0x9U) - -#define HW_NV_FPROT2(x) (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR(x)) -#define HW_NV_FPROT2_RD(x) (HW_NV_FPROT2(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT2 bitfields - */ - -/*! - * @name Register NV_FPROT2, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT2_PROT (0U) /*!< Bit position for NV_FPROT2_PROT. */ -#define BM_NV_FPROT2_PROT (0xFFU) /*!< Bit mask for NV_FPROT2_PROT. */ -#define BS_NV_FPROT2_PROT (8U) /*!< Bit field size in bits for NV_FPROT2_PROT. */ - -/*! @brief Read current value of the NV_FPROT2_PROT field. */ -#define BR_NV_FPROT2_PROT(x) (HW_NV_FPROT2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot1 -{ - uint8_t U; - struct _hw_nv_fprot1_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot1_t; - -/*! - * @name Constants and macros for entire NV_FPROT1 register - */ -/*@{*/ -#define HW_NV_FPROT1_ADDR(x) ((x) + 0xAU) - -#define HW_NV_FPROT1(x) (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR(x)) -#define HW_NV_FPROT1_RD(x) (HW_NV_FPROT1(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT1 bitfields - */ - -/*! - * @name Register NV_FPROT1, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT1_PROT (0U) /*!< Bit position for NV_FPROT1_PROT. */ -#define BM_NV_FPROT1_PROT (0xFFU) /*!< Bit mask for NV_FPROT1_PROT. */ -#define BS_NV_FPROT1_PROT (8U) /*!< Bit field size in bits for NV_FPROT1_PROT. */ - -/*! @brief Read current value of the NV_FPROT1_PROT field. */ -#define BR_NV_FPROT1_PROT(x) (HW_NV_FPROT1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot0 -{ - uint8_t U; - struct _hw_nv_fprot0_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot0_t; - -/*! - * @name Constants and macros for entire NV_FPROT0 register - */ -/*@{*/ -#define HW_NV_FPROT0_ADDR(x) ((x) + 0xBU) - -#define HW_NV_FPROT0(x) (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR(x)) -#define HW_NV_FPROT0_RD(x) (HW_NV_FPROT0(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT0 bitfields - */ - -/*! - * @name Register NV_FPROT0, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT0_PROT (0U) /*!< Bit position for NV_FPROT0_PROT. */ -#define BM_NV_FPROT0_PROT (0xFFU) /*!< Bit mask for NV_FPROT0_PROT. */ -#define BS_NV_FPROT0_PROT (8U) /*!< Bit field size in bits for NV_FPROT0_PROT. */ - -/*! @brief Read current value of the NV_FPROT0_PROT field. */ -#define BR_NV_FPROT0_PROT(x) (HW_NV_FPROT0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FSEC - Non-volatile Flash Security Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO) - * - * Reset value: 0xFFU - * - * Allows the user to customize the operation of the MCU at boot time - */ -typedef union _hw_nv_fsec -{ - uint8_t U; - struct _hw_nv_fsec_bitfields - { - uint8_t SEC : 2; /*!< [1:0] Flash Security */ - uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code - * */ - uint8_t MEEN : 2; /*!< [5:4] */ - uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */ - } B; -} hw_nv_fsec_t; - -/*! - * @name Constants and macros for entire NV_FSEC register - */ -/*@{*/ -#define HW_NV_FSEC_ADDR(x) ((x) + 0xCU) - -#define HW_NV_FSEC(x) (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR(x)) -#define HW_NV_FSEC_RD(x) (HW_NV_FSEC(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FSEC bitfields - */ - -/*! - * @name Register NV_FSEC, field SEC[1:0] (RO) - * - * Values: - * - 10 - MCU security status is unsecure - * - 11 - MCU security status is secure - */ -/*@{*/ -#define BP_NV_FSEC_SEC (0U) /*!< Bit position for NV_FSEC_SEC. */ -#define BM_NV_FSEC_SEC (0x03U) /*!< Bit mask for NV_FSEC_SEC. */ -#define BS_NV_FSEC_SEC (2U) /*!< Bit field size in bits for NV_FSEC_SEC. */ - -/*! @brief Read current value of the NV_FSEC_SEC field. */ -#define BR_NV_FSEC_SEC(x) (HW_NV_FSEC(x).B.SEC) -/*@}*/ - -/*! - * @name Register NV_FSEC, field FSLACC[3:2] (RO) - * - * Values: - * - 10 - Freescale factory access denied - * - 11 - Freescale factory access granted - */ -/*@{*/ -#define BP_NV_FSEC_FSLACC (2U) /*!< Bit position for NV_FSEC_FSLACC. */ -#define BM_NV_FSEC_FSLACC (0x0CU) /*!< Bit mask for NV_FSEC_FSLACC. */ -#define BS_NV_FSEC_FSLACC (2U) /*!< Bit field size in bits for NV_FSEC_FSLACC. */ - -/*! @brief Read current value of the NV_FSEC_FSLACC field. */ -#define BR_NV_FSEC_FSLACC(x) (HW_NV_FSEC(x).B.FSLACC) -/*@}*/ - -/*! - * @name Register NV_FSEC, field MEEN[5:4] (RO) - * - * Values: - * - 10 - Mass erase is disabled - * - 11 - Mass erase is enabled - */ -/*@{*/ -#define BP_NV_FSEC_MEEN (4U) /*!< Bit position for NV_FSEC_MEEN. */ -#define BM_NV_FSEC_MEEN (0x30U) /*!< Bit mask for NV_FSEC_MEEN. */ -#define BS_NV_FSEC_MEEN (2U) /*!< Bit field size in bits for NV_FSEC_MEEN. */ - -/*! @brief Read current value of the NV_FSEC_MEEN field. */ -#define BR_NV_FSEC_MEEN(x) (HW_NV_FSEC(x).B.MEEN) -/*@}*/ - -/*! - * @name Register NV_FSEC, field KEYEN[7:6] (RO) - * - * Values: - * - 10 - Backdoor key access enabled - * - 11 - Backdoor key access disabled - */ -/*@{*/ -#define BP_NV_FSEC_KEYEN (6U) /*!< Bit position for NV_FSEC_KEYEN. */ -#define BM_NV_FSEC_KEYEN (0xC0U) /*!< Bit mask for NV_FSEC_KEYEN. */ -#define BS_NV_FSEC_KEYEN (2U) /*!< Bit field size in bits for NV_FSEC_KEYEN. */ - -/*! @brief Read current value of the NV_FSEC_KEYEN field. */ -#define BR_NV_FSEC_KEYEN(x) (HW_NV_FSEC(x).B.KEYEN) -/*@}*/ - -/******************************************************************************* - * HW_NV_FOPT - Non-volatile Flash Option Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fopt -{ - uint8_t U; - struct _hw_nv_fopt_bitfields - { - uint8_t LPBOOT : 1; /*!< [0] */ - uint8_t EZPORT_DIS : 1; /*!< [1] */ - uint8_t NMI_DIS : 1; /*!< [2] */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t FAST_INIT : 1; /*!< [5] */ - uint8_t RESERVED1 : 2; /*!< [7:6] */ - } B; -} hw_nv_fopt_t; - -/*! - * @name Constants and macros for entire NV_FOPT register - */ -/*@{*/ -#define HW_NV_FOPT_ADDR(x) ((x) + 0xDU) - -#define HW_NV_FOPT(x) (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR(x)) -#define HW_NV_FOPT_RD(x) (HW_NV_FOPT(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FOPT bitfields - */ - -/*! - * @name Register NV_FOPT, field LPBOOT[0] (RO) - * - * Values: - * - 00 - Low-power boot - * - 01 - Normal boot - */ -/*@{*/ -#define BP_NV_FOPT_LPBOOT (0U) /*!< Bit position for NV_FOPT_LPBOOT. */ -#define BM_NV_FOPT_LPBOOT (0x01U) /*!< Bit mask for NV_FOPT_LPBOOT. */ -#define BS_NV_FOPT_LPBOOT (1U) /*!< Bit field size in bits for NV_FOPT_LPBOOT. */ - -/*! @brief Read current value of the NV_FOPT_LPBOOT field. */ -#define BR_NV_FOPT_LPBOOT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_LPBOOT)) -/*@}*/ - -/*! - * @name Register NV_FOPT, field EZPORT_DIS[1] (RO) - */ -/*@{*/ -#define BP_NV_FOPT_EZPORT_DIS (1U) /*!< Bit position for NV_FOPT_EZPORT_DIS. */ -#define BM_NV_FOPT_EZPORT_DIS (0x02U) /*!< Bit mask for NV_FOPT_EZPORT_DIS. */ -#define BS_NV_FOPT_EZPORT_DIS (1U) /*!< Bit field size in bits for NV_FOPT_EZPORT_DIS. */ - -/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */ -#define BR_NV_FOPT_EZPORT_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_EZPORT_DIS)) -/*@}*/ - -/*! - * @name Register NV_FOPT, field NMI_DIS[2] (RO) - * - * Values: - * - 00 - NMI interrupts are always blocked - * - 01 - NMI_b pin/interrupts reset default to enabled - */ -/*@{*/ -#define BP_NV_FOPT_NMI_DIS (2U) /*!< Bit position for NV_FOPT_NMI_DIS. */ -#define BM_NV_FOPT_NMI_DIS (0x04U) /*!< Bit mask for NV_FOPT_NMI_DIS. */ -#define BS_NV_FOPT_NMI_DIS (1U) /*!< Bit field size in bits for NV_FOPT_NMI_DIS. */ - -/*! @brief Read current value of the NV_FOPT_NMI_DIS field. */ -#define BR_NV_FOPT_NMI_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_NMI_DIS)) -/*@}*/ - -/*! - * @name Register NV_FOPT, field FAST_INIT[5] (RO) - * - * Values: - * - 00 - Slower initialization - * - 01 - Fast Initialization - */ -/*@{*/ -#define BP_NV_FOPT_FAST_INIT (5U) /*!< Bit position for NV_FOPT_FAST_INIT. */ -#define BM_NV_FOPT_FAST_INIT (0x20U) /*!< Bit mask for NV_FOPT_FAST_INIT. */ -#define BS_NV_FOPT_FAST_INIT (1U) /*!< Bit field size in bits for NV_FOPT_FAST_INIT. */ - -/*! @brief Read current value of the NV_FOPT_FAST_INIT field. */ -#define BR_NV_FOPT_FAST_INIT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_FAST_INIT)) -/*@}*/ - -/******************************************************************************* - * hw_nv_t - module struct - ******************************************************************************/ -/*! - * @brief All NV module registers. - */ -#pragma pack(1) -typedef struct _hw_nv -{ - __I hw_nv_backkey3_t BACKKEY3; /*!< [0x0] Backdoor Comparison Key 3. */ - __I hw_nv_backkey2_t BACKKEY2; /*!< [0x1] Backdoor Comparison Key 2. */ - __I hw_nv_backkey1_t BACKKEY1; /*!< [0x2] Backdoor Comparison Key 1. */ - __I hw_nv_backkey0_t BACKKEY0; /*!< [0x3] Backdoor Comparison Key 0. */ - __I hw_nv_backkey7_t BACKKEY7; /*!< [0x4] Backdoor Comparison Key 7. */ - __I hw_nv_backkey6_t BACKKEY6; /*!< [0x5] Backdoor Comparison Key 6. */ - __I hw_nv_backkey5_t BACKKEY5; /*!< [0x6] Backdoor Comparison Key 5. */ - __I hw_nv_backkey4_t BACKKEY4; /*!< [0x7] Backdoor Comparison Key 4. */ - __I hw_nv_fprot3_t FPROT3; /*!< [0x8] Non-volatile P-Flash Protection 1 - Low Register */ - __I hw_nv_fprot2_t FPROT2; /*!< [0x9] Non-volatile P-Flash Protection 1 - High Register */ - __I hw_nv_fprot1_t FPROT1; /*!< [0xA] Non-volatile P-Flash Protection 0 - Low Register */ - __I hw_nv_fprot0_t FPROT0; /*!< [0xB] Non-volatile P-Flash Protection 0 - High Register */ - __I hw_nv_fsec_t FSEC; /*!< [0xC] Non-volatile Flash Security Register */ - __I hw_nv_fopt_t FOPT; /*!< [0xD] Non-volatile Flash Option Register */ -} hw_nv_t; -#pragma pack() - -/*! @brief Macro to access all NV registers. */ -/*! @param x NV module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_NV(FTFA_FlashConfig_BASE). */ -#define HW_NV(x) (*(hw_nv_t *)(x)) - -#endif /* __HW_NV_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h deleted file mode 100644 index 17df972a46c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h +++ /dev/null @@ -1,378 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_OSC_REGISTERS_H__ -#define __HW_OSC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 OSC - * - * Oscillator - * - * Registers defined in this header file: - * - HW_OSC_CR - OSC Control Register - * - HW_OSC_DIV - OSC_DIV - * - * - hw_osc_t - Struct containing all module registers. - */ - -#define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */ - -/******************************************************************************* - * HW_OSC_CR - OSC Control Register - ******************************************************************************/ - -/*! - * @brief HW_OSC_CR - OSC Control Register (RW) - * - * Reset value: 0x00U - * - * After OSC is enabled and starts generating the clocks, the configurations - * such as low power and frequency range, must not be changed. - */ -typedef union _hw_osc_cr -{ - uint8_t U; - struct _hw_osc_cr_bitfields - { - uint8_t SC16P : 1; /*!< [0] Oscillator 16 pF Capacitor Load Configure - * */ - uint8_t SC8P : 1; /*!< [1] Oscillator 8 pF Capacitor Load Configure */ - uint8_t SC4P : 1; /*!< [2] Oscillator 4 pF Capacitor Load Configure */ - uint8_t SC2P : 1; /*!< [3] Oscillator 2 pF Capacitor Load Configure */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t EREFSTEN : 1; /*!< [5] External Reference Stop Enable */ - uint8_t RESERVED1 : 1; /*!< [6] */ - uint8_t ERCLKEN : 1; /*!< [7] External Reference Enable */ - } B; -} hw_osc_cr_t; - -/*! - * @name Constants and macros for entire OSC_CR register - */ -/*@{*/ -#define HW_OSC_CR_ADDR(x) ((x) + 0x0U) - -#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x)) -#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U) -#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v)) -#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v))) -#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v))) -#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual OSC_CR bitfields - */ - -/*! - * @name Register OSC_CR, field SC16P[0] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 16 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC16P (0U) /*!< Bit position for OSC_CR_SC16P. */ -#define BM_OSC_CR_SC16P (0x01U) /*!< Bit mask for OSC_CR_SC16P. */ -#define BS_OSC_CR_SC16P (1U) /*!< Bit field size in bits for OSC_CR_SC16P. */ - -/*! @brief Read current value of the OSC_CR_SC16P field. */ -#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P)) - -/*! @brief Format value for bitfield OSC_CR_SC16P. */ -#define BF_OSC_CR_SC16P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P) - -/*! @brief Set the SC16P field to a new value. */ -#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field SC8P[1] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 8 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC8P (1U) /*!< Bit position for OSC_CR_SC8P. */ -#define BM_OSC_CR_SC8P (0x02U) /*!< Bit mask for OSC_CR_SC8P. */ -#define BS_OSC_CR_SC8P (1U) /*!< Bit field size in bits for OSC_CR_SC8P. */ - -/*! @brief Read current value of the OSC_CR_SC8P field. */ -#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P)) - -/*! @brief Format value for bitfield OSC_CR_SC8P. */ -#define BF_OSC_CR_SC8P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P) - -/*! @brief Set the SC8P field to a new value. */ -#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field SC4P[2] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 4 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC4P (2U) /*!< Bit position for OSC_CR_SC4P. */ -#define BM_OSC_CR_SC4P (0x04U) /*!< Bit mask for OSC_CR_SC4P. */ -#define BS_OSC_CR_SC4P (1U) /*!< Bit field size in bits for OSC_CR_SC4P. */ - -/*! @brief Read current value of the OSC_CR_SC4P field. */ -#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P)) - -/*! @brief Format value for bitfield OSC_CR_SC4P. */ -#define BF_OSC_CR_SC4P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P) - -/*! @brief Set the SC4P field to a new value. */ -#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field SC2P[3] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 2 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC2P (3U) /*!< Bit position for OSC_CR_SC2P. */ -#define BM_OSC_CR_SC2P (0x08U) /*!< Bit mask for OSC_CR_SC2P. */ -#define BS_OSC_CR_SC2P (1U) /*!< Bit field size in bits for OSC_CR_SC2P. */ - -/*! @brief Read current value of the OSC_CR_SC2P field. */ -#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P)) - -/*! @brief Format value for bitfield OSC_CR_SC2P. */ -#define BF_OSC_CR_SC2P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P) - -/*! @brief Set the SC2P field to a new value. */ -#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field EREFSTEN[5] (RW) - * - * Controls whether or not the external reference clock (OSCERCLK) remains - * enabled when MCU enters Stop mode. - * - * Values: - * - 0 - External reference clock is disabled in Stop mode. - * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set - * before entering Stop mode. - */ -/*@{*/ -#define BP_OSC_CR_EREFSTEN (5U) /*!< Bit position for OSC_CR_EREFSTEN. */ -#define BM_OSC_CR_EREFSTEN (0x20U) /*!< Bit mask for OSC_CR_EREFSTEN. */ -#define BS_OSC_CR_EREFSTEN (1U) /*!< Bit field size in bits for OSC_CR_EREFSTEN. */ - -/*! @brief Read current value of the OSC_CR_EREFSTEN field. */ -#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN)) - -/*! @brief Format value for bitfield OSC_CR_EREFSTEN. */ -#define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN) - -/*! @brief Set the EREFSTEN field to a new value. */ -#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field ERCLKEN[7] (RW) - * - * Enables external reference clock (OSCERCLK). - * - * Values: - * - 0 - External reference clock is inactive. - * - 1 - External reference clock is enabled. - */ -/*@{*/ -#define BP_OSC_CR_ERCLKEN (7U) /*!< Bit position for OSC_CR_ERCLKEN. */ -#define BM_OSC_CR_ERCLKEN (0x80U) /*!< Bit mask for OSC_CR_ERCLKEN. */ -#define BS_OSC_CR_ERCLKEN (1U) /*!< Bit field size in bits for OSC_CR_ERCLKEN. */ - -/*! @brief Read current value of the OSC_CR_ERCLKEN field. */ -#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN)) - -/*! @brief Format value for bitfield OSC_CR_ERCLKEN. */ -#define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN) - -/*! @brief Set the ERCLKEN field to a new value. */ -#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_OSC_DIV - OSC_DIV - ******************************************************************************/ - -/*! - * @brief HW_OSC_DIV - OSC_DIV (RW) - * - * Reset value: 0x00U - * - * OSC CLock divider register. - */ -typedef union _hw_osc_div -{ - uint8_t U; - struct _hw_osc_div_bitfields - { - uint8_t RESERVED0 : 6; /*!< [5:0] */ - uint8_t ERPS : 2; /*!< [7:6] */ - } B; -} hw_osc_div_t; - -/*! - * @name Constants and macros for entire OSC_DIV register - */ -/*@{*/ -#define HW_OSC_DIV_ADDR(x) ((x) + 0x2U) - -#define HW_OSC_DIV(x) (*(__IO hw_osc_div_t *) HW_OSC_DIV_ADDR(x)) -#define HW_OSC_DIV_RD(x) (HW_OSC_DIV(x).U) -#define HW_OSC_DIV_WR(x, v) (HW_OSC_DIV(x).U = (v)) -#define HW_OSC_DIV_SET(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) | (v))) -#define HW_OSC_DIV_CLR(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) & ~(v))) -#define HW_OSC_DIV_TOG(x, v) (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual OSC_DIV bitfields - */ - -/*! - * @name Register OSC_DIV, field ERPS[7:6] (RW) - * - * ERCLK prescaler. These two bits are used to divide the ERCLK output. The - * un-divided ERCLK output is not affected by these two bits. - * - * Values: - * - 00 - The divisor ratio is 1. - * - 01 - The divisor ratio is 2. - * - 10 - The divisor ratio is 4. - * - 11 - The divisor ratio is 8. - */ -/*@{*/ -#define BP_OSC_DIV_ERPS (6U) /*!< Bit position for OSC_DIV_ERPS. */ -#define BM_OSC_DIV_ERPS (0xC0U) /*!< Bit mask for OSC_DIV_ERPS. */ -#define BS_OSC_DIV_ERPS (2U) /*!< Bit field size in bits for OSC_DIV_ERPS. */ - -/*! @brief Read current value of the OSC_DIV_ERPS field. */ -#define BR_OSC_DIV_ERPS(x) (HW_OSC_DIV(x).B.ERPS) - -/*! @brief Format value for bitfield OSC_DIV_ERPS. */ -#define BF_OSC_DIV_ERPS(v) ((uint8_t)((uint8_t)(v) << BP_OSC_DIV_ERPS) & BM_OSC_DIV_ERPS) - -/*! @brief Set the ERPS field to a new value. */ -#define BW_OSC_DIV_ERPS(x, v) (HW_OSC_DIV_WR(x, (HW_OSC_DIV_RD(x) & ~BM_OSC_DIV_ERPS) | BF_OSC_DIV_ERPS(v))) -/*@}*/ - -/******************************************************************************* - * hw_osc_t - module struct - ******************************************************************************/ -/*! - * @brief All OSC module registers. - */ -#pragma pack(1) -typedef struct _hw_osc -{ - __IO hw_osc_cr_t CR; /*!< [0x0] OSC Control Register */ - uint8_t _reserved0[1]; - __IO hw_osc_div_t DIV; /*!< [0x2] OSC_DIV */ -} hw_osc_t; -#pragma pack() - -/*! @brief Macro to access all OSC registers. */ -/*! @param x OSC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_OSC(OSC_BASE). */ -#define HW_OSC(x) (*(hw_osc_t *)(x)) - -#endif /* __HW_OSC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h deleted file mode 100644 index abc00969531..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h +++ /dev/null @@ -1,1326 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PDB_REGISTERS_H__ -#define __HW_PDB_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 PDB - * - * Programmable Delay Block - * - * Registers defined in this header file: - * - HW_PDB_SC - Status and Control register - * - HW_PDB_MOD - Modulus register - * - HW_PDB_CNT - Counter register - * - HW_PDB_IDLY - Interrupt Delay register - * - HW_PDB_CHnC1 - Channel n Control register 1 - * - HW_PDB_CHnS - Channel n Status register - * - HW_PDB_CHnDLY0 - Channel n Delay 0 register - * - HW_PDB_CHnDLY1 - Channel n Delay 1 register - * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register - * - HW_PDB_DACINTn - DAC Interval n register - * - HW_PDB_POEN - Pulse-Out n Enable register - * - HW_PDB_POnDLY - Pulse-Out n Delay register - * - * - hw_pdb_t - Struct containing all module registers. - */ - -#define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */ - -/******************************************************************************* - * HW_PDB_SC - Status and Control register - ******************************************************************************/ - -/*! - * @brief HW_PDB_SC - Status and Control register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_sc -{ - uint32_t U; - struct _hw_pdb_sc_bitfields - { - uint32_t LDOK : 1; /*!< [0] Load OK */ - uint32_t CONT : 1; /*!< [1] Continuous Mode Enable */ - uint32_t MULT : 2; /*!< [3:2] Multiplication Factor Select for - * Prescaler */ - uint32_t RESERVED0 : 1; /*!< [4] */ - uint32_t PDBIE : 1; /*!< [5] PDB Interrupt Enable */ - uint32_t PDBIF : 1; /*!< [6] PDB Interrupt Flag */ - uint32_t PDBEN : 1; /*!< [7] PDB Enable */ - uint32_t TRGSEL : 4; /*!< [11:8] Trigger Input Source Select */ - uint32_t PRESCALER : 3; /*!< [14:12] Prescaler Divider Select */ - uint32_t DMAEN : 1; /*!< [15] DMA Enable */ - uint32_t SWTRIG : 1; /*!< [16] Software Trigger */ - uint32_t PDBEIE : 1; /*!< [17] PDB Sequence Error Interrupt Enable */ - uint32_t LDMOD : 2; /*!< [19:18] Load Mode Select */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_pdb_sc_t; - -/*! - * @name Constants and macros for entire PDB_SC register - */ -/*@{*/ -#define HW_PDB_SC_ADDR(x) ((x) + 0x0U) - -#define HW_PDB_SC(x) (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x)) -#define HW_PDB_SC_RD(x) (HW_PDB_SC(x).U) -#define HW_PDB_SC_WR(x, v) (HW_PDB_SC(x).U = (v)) -#define HW_PDB_SC_SET(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) | (v))) -#define HW_PDB_SC_CLR(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v))) -#define HW_PDB_SC_TOG(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_SC bitfields - */ - -/*! - * @name Register PDB_SC, field LDOK[0] (RW) - * - * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm, - * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY, - * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is - * written to the LDOK field, the values in the buffers of above registers are - * not effective and the buffers cannot be written until the values in buffers are - * loaded into their internal registers. LDOK can be written only when PDBEN is - * set or it can be written at the same time with PDBEN being written to 1. It is - * automatically cleared when the values in buffers are loaded into the internal - * registers or the PDBEN is cleared. Writing 0 to it has no effect. - */ -/*@{*/ -#define BP_PDB_SC_LDOK (0U) /*!< Bit position for PDB_SC_LDOK. */ -#define BM_PDB_SC_LDOK (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */ -#define BS_PDB_SC_LDOK (1U) /*!< Bit field size in bits for PDB_SC_LDOK. */ - -/*! @brief Read current value of the PDB_SC_LDOK field. */ -#define BR_PDB_SC_LDOK(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK)) - -/*! @brief Format value for bitfield PDB_SC_LDOK. */ -#define BF_PDB_SC_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK) - -/*! @brief Set the LDOK field to a new value. */ -#define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field CONT[1] (RW) - * - * Enables the PDB operation in Continuous mode. - * - * Values: - * - 0 - PDB operation in One-Shot mode - * - 1 - PDB operation in Continuous mode - */ -/*@{*/ -#define BP_PDB_SC_CONT (1U) /*!< Bit position for PDB_SC_CONT. */ -#define BM_PDB_SC_CONT (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */ -#define BS_PDB_SC_CONT (1U) /*!< Bit field size in bits for PDB_SC_CONT. */ - -/*! @brief Read current value of the PDB_SC_CONT field. */ -#define BR_PDB_SC_CONT(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT)) - -/*! @brief Format value for bitfield PDB_SC_CONT. */ -#define BF_PDB_SC_CONT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT) - -/*! @brief Set the CONT field to a new value. */ -#define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field MULT[3:2] (RW) - * - * Selects the multiplication factor of the prescaler divider for the counter - * clock. - * - * Values: - * - 00 - Multiplication factor is 1. - * - 01 - Multiplication factor is 10. - * - 10 - Multiplication factor is 20. - * - 11 - Multiplication factor is 40. - */ -/*@{*/ -#define BP_PDB_SC_MULT (2U) /*!< Bit position for PDB_SC_MULT. */ -#define BM_PDB_SC_MULT (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */ -#define BS_PDB_SC_MULT (2U) /*!< Bit field size in bits for PDB_SC_MULT. */ - -/*! @brief Read current value of the PDB_SC_MULT field. */ -#define BR_PDB_SC_MULT(x) (HW_PDB_SC(x).B.MULT) - -/*! @brief Format value for bitfield PDB_SC_MULT. */ -#define BF_PDB_SC_MULT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT) - -/*! @brief Set the MULT field to a new value. */ -#define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v))) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBIE[5] (RW) - * - * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF - * generates a PDB interrupt. - * - * Values: - * - 0 - PDB interrupt disabled. - * - 1 - PDB interrupt enabled. - */ -/*@{*/ -#define BP_PDB_SC_PDBIE (5U) /*!< Bit position for PDB_SC_PDBIE. */ -#define BM_PDB_SC_PDBIE (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */ -#define BS_PDB_SC_PDBIE (1U) /*!< Bit field size in bits for PDB_SC_PDBIE. */ - -/*! @brief Read current value of the PDB_SC_PDBIE field. */ -#define BR_PDB_SC_PDBIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE)) - -/*! @brief Format value for bitfield PDB_SC_PDBIE. */ -#define BF_PDB_SC_PDBIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE) - -/*! @brief Set the PDBIE field to a new value. */ -#define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBIF[6] (RW) - * - * This field is set when the counter value is equal to the IDLY register. - * Writing zero clears this field. - */ -/*@{*/ -#define BP_PDB_SC_PDBIF (6U) /*!< Bit position for PDB_SC_PDBIF. */ -#define BM_PDB_SC_PDBIF (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */ -#define BS_PDB_SC_PDBIF (1U) /*!< Bit field size in bits for PDB_SC_PDBIF. */ - -/*! @brief Read current value of the PDB_SC_PDBIF field. */ -#define BR_PDB_SC_PDBIF(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF)) - -/*! @brief Format value for bitfield PDB_SC_PDBIF. */ -#define BF_PDB_SC_PDBIF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF) - -/*! @brief Set the PDBIF field to a new value. */ -#define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBEN[7] (RW) - * - * Values: - * - 0 - PDB disabled. Counter is off. - * - 1 - PDB enabled. - */ -/*@{*/ -#define BP_PDB_SC_PDBEN (7U) /*!< Bit position for PDB_SC_PDBEN. */ -#define BM_PDB_SC_PDBEN (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */ -#define BS_PDB_SC_PDBEN (1U) /*!< Bit field size in bits for PDB_SC_PDBEN. */ - -/*! @brief Read current value of the PDB_SC_PDBEN field. */ -#define BR_PDB_SC_PDBEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN)) - -/*! @brief Format value for bitfield PDB_SC_PDBEN. */ -#define BF_PDB_SC_PDBEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN) - -/*! @brief Set the PDBEN field to a new value. */ -#define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field TRGSEL[11:8] (RW) - * - * Selects the trigger input source for the PDB. The trigger input source can be - * internal or external (EXTRG pin), or the software trigger. Refer to chip - * configuration details for the actual PDB input trigger connections. - * - * Values: - * - 0000 - Trigger-In 0 is selected. - * - 0001 - Trigger-In 1 is selected. - * - 0010 - Trigger-In 2 is selected. - * - 0011 - Trigger-In 3 is selected. - * - 0100 - Trigger-In 4 is selected. - * - 0101 - Trigger-In 5 is selected. - * - 0110 - Trigger-In 6 is selected. - * - 0111 - Trigger-In 7 is selected. - * - 1000 - Trigger-In 8 is selected. - * - 1001 - Trigger-In 9 is selected. - * - 1010 - Trigger-In 10 is selected. - * - 1011 - Trigger-In 11 is selected. - * - 1100 - Trigger-In 12 is selected. - * - 1101 - Trigger-In 13 is selected. - * - 1110 - Trigger-In 14 is selected. - * - 1111 - Software trigger is selected. - */ -/*@{*/ -#define BP_PDB_SC_TRGSEL (8U) /*!< Bit position for PDB_SC_TRGSEL. */ -#define BM_PDB_SC_TRGSEL (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */ -#define BS_PDB_SC_TRGSEL (4U) /*!< Bit field size in bits for PDB_SC_TRGSEL. */ - -/*! @brief Read current value of the PDB_SC_TRGSEL field. */ -#define BR_PDB_SC_TRGSEL(x) (HW_PDB_SC(x).B.TRGSEL) - -/*! @brief Format value for bitfield PDB_SC_TRGSEL. */ -#define BF_PDB_SC_TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL) - -/*! @brief Set the TRGSEL field to a new value. */ -#define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v))) -/*@}*/ - -/*! - * @name Register PDB_SC, field PRESCALER[14:12] (RW) - * - * Values: - * - 000 - Counting uses the peripheral clock divided by multiplication factor - * selected by MULT. - * - 001 - Counting uses the peripheral clock divided by twice of the - * multiplication factor selected by MULT. - * - 010 - Counting uses the peripheral clock divided by four times of the - * multiplication factor selected by MULT. - * - 011 - Counting uses the peripheral clock divided by eight times of the - * multiplication factor selected by MULT. - * - 100 - Counting uses the peripheral clock divided by 16 times of the - * multiplication factor selected by MULT. - * - 101 - Counting uses the peripheral clock divided by 32 times of the - * multiplication factor selected by MULT. - * - 110 - Counting uses the peripheral clock divided by 64 times of the - * multiplication factor selected by MULT. - * - 111 - Counting uses the peripheral clock divided by 128 times of the - * multiplication factor selected by MULT. - */ -/*@{*/ -#define BP_PDB_SC_PRESCALER (12U) /*!< Bit position for PDB_SC_PRESCALER. */ -#define BM_PDB_SC_PRESCALER (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */ -#define BS_PDB_SC_PRESCALER (3U) /*!< Bit field size in bits for PDB_SC_PRESCALER. */ - -/*! @brief Read current value of the PDB_SC_PRESCALER field. */ -#define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER) - -/*! @brief Format value for bitfield PDB_SC_PRESCALER. */ -#define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER) - -/*! @brief Set the PRESCALER field to a new value. */ -#define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v))) -/*@}*/ - -/*! - * @name Register PDB_SC, field DMAEN[15] (RW) - * - * When DMA is enabled, the PDBIF flag generates a DMA request instead of an - * interrupt. - * - * Values: - * - 0 - DMA disabled. - * - 1 - DMA enabled. - */ -/*@{*/ -#define BP_PDB_SC_DMAEN (15U) /*!< Bit position for PDB_SC_DMAEN. */ -#define BM_PDB_SC_DMAEN (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */ -#define BS_PDB_SC_DMAEN (1U) /*!< Bit field size in bits for PDB_SC_DMAEN. */ - -/*! @brief Read current value of the PDB_SC_DMAEN field. */ -#define BR_PDB_SC_DMAEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN)) - -/*! @brief Format value for bitfield PDB_SC_DMAEN. */ -#define BF_PDB_SC_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field SWTRIG[16] (WORZ) - * - * When PDB is enabled and the software trigger is selected as the trigger input - * source, writing 1 to this field resets and restarts the counter. Writing 0 to - * this field has no effect. Reading this field results 0. - */ -/*@{*/ -#define BP_PDB_SC_SWTRIG (16U) /*!< Bit position for PDB_SC_SWTRIG. */ -#define BM_PDB_SC_SWTRIG (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */ -#define BS_PDB_SC_SWTRIG (1U) /*!< Bit field size in bits for PDB_SC_SWTRIG. */ - -/*! @brief Format value for bitfield PDB_SC_SWTRIG. */ -#define BF_PDB_SC_SWTRIG(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG) - -/*! @brief Set the SWTRIG field to a new value. */ -#define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBEIE[17] (RW) - * - * Enables the PDB sequence error interrupt. When this field is set, any of the - * PDB channel sequence error flags generates a PDB sequence error interrupt. - * - * Values: - * - 0 - PDB sequence error interrupt disabled. - * - 1 - PDB sequence error interrupt enabled. - */ -/*@{*/ -#define BP_PDB_SC_PDBEIE (17U) /*!< Bit position for PDB_SC_PDBEIE. */ -#define BM_PDB_SC_PDBEIE (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */ -#define BS_PDB_SC_PDBEIE (1U) /*!< Bit field size in bits for PDB_SC_PDBEIE. */ - -/*! @brief Read current value of the PDB_SC_PDBEIE field. */ -#define BR_PDB_SC_PDBEIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE)) - -/*! @brief Format value for bitfield PDB_SC_PDBEIE. */ -#define BF_PDB_SC_PDBEIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE) - -/*! @brief Set the PDBEIE field to a new value. */ -#define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field LDMOD[19:18] (RW) - * - * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, - * after 1 is written to LDOK. - * - * Values: - * - 00 - The internal registers are loaded with the values from their buffers - * immediately after 1 is written to LDOK. - * - 01 - The internal registers are loaded with the values from their buffers - * when the PDB counter reaches the MOD register value after 1 is written to - * LDOK. - * - 10 - The internal registers are loaded with the values from their buffers - * when a trigger input event is detected after 1 is written to LDOK. - * - 11 - The internal registers are loaded with the values from their buffers - * when either the PDB counter reaches the MOD register value or a trigger - * input event is detected, after 1 is written to LDOK. - */ -/*@{*/ -#define BP_PDB_SC_LDMOD (18U) /*!< Bit position for PDB_SC_LDMOD. */ -#define BM_PDB_SC_LDMOD (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */ -#define BS_PDB_SC_LDMOD (2U) /*!< Bit field size in bits for PDB_SC_LDMOD. */ - -/*! @brief Read current value of the PDB_SC_LDMOD field. */ -#define BR_PDB_SC_LDMOD(x) (HW_PDB_SC(x).B.LDMOD) - -/*! @brief Format value for bitfield PDB_SC_LDMOD. */ -#define BF_PDB_SC_LDMOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD) - -/*! @brief Set the LDMOD field to a new value. */ -#define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_MOD - Modulus register - ******************************************************************************/ - -/*! - * @brief HW_PDB_MOD - Modulus register (RW) - * - * Reset value: 0x0000FFFFU - */ -typedef union _hw_pdb_mod -{ - uint32_t U; - struct _hw_pdb_mod_bitfields - { - uint32_t MOD : 16; /*!< [15:0] PDB Modulus */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_mod_t; - -/*! - * @name Constants and macros for entire PDB_MOD register - */ -/*@{*/ -#define HW_PDB_MOD_ADDR(x) ((x) + 0x4U) - -#define HW_PDB_MOD(x) (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x)) -#define HW_PDB_MOD_RD(x) (HW_PDB_MOD(x).U) -#define HW_PDB_MOD_WR(x, v) (HW_PDB_MOD(x).U = (v)) -#define HW_PDB_MOD_SET(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) | (v))) -#define HW_PDB_MOD_CLR(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v))) -#define HW_PDB_MOD_TOG(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_MOD bitfields - */ - -/*! - * @name Register PDB_MOD, field MOD[15:0] (RW) - * - * Specifies the period of the counter. When the counter reaches this value, it - * will be reset back to zero. If the PDB is in Continuous mode, the count begins - * anew. Reading this field returns the value of the internal register that is - * effective for the current cycle of PDB. - */ -/*@{*/ -#define BP_PDB_MOD_MOD (0U) /*!< Bit position for PDB_MOD_MOD. */ -#define BM_PDB_MOD_MOD (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */ -#define BS_PDB_MOD_MOD (16U) /*!< Bit field size in bits for PDB_MOD_MOD. */ - -/*! @brief Read current value of the PDB_MOD_MOD field. */ -#define BR_PDB_MOD_MOD(x) (HW_PDB_MOD(x).B.MOD) - -/*! @brief Format value for bitfield PDB_MOD_MOD. */ -#define BF_PDB_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD) - -/*! @brief Set the MOD field to a new value. */ -#define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_CNT - Counter register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CNT - Counter register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_cnt -{ - uint32_t U; - struct _hw_pdb_cnt_bitfields - { - uint32_t CNT : 16; /*!< [15:0] PDB Counter */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_cnt_t; - -/*! - * @name Constants and macros for entire PDB_CNT register - */ -/*@{*/ -#define HW_PDB_CNT_ADDR(x) ((x) + 0x8U) - -#define HW_PDB_CNT(x) (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x)) -#define HW_PDB_CNT_RD(x) (HW_PDB_CNT(x).U) -/*@}*/ - -/* - * Constants & macros for individual PDB_CNT bitfields - */ - -/*! - * @name Register PDB_CNT, field CNT[15:0] (RO) - * - * Contains the current value of the counter. - */ -/*@{*/ -#define BP_PDB_CNT_CNT (0U) /*!< Bit position for PDB_CNT_CNT. */ -#define BM_PDB_CNT_CNT (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */ -#define BS_PDB_CNT_CNT (16U) /*!< Bit field size in bits for PDB_CNT_CNT. */ - -/*! @brief Read current value of the PDB_CNT_CNT field. */ -#define BR_PDB_CNT_CNT(x) (HW_PDB_CNT(x).B.CNT) -/*@}*/ - -/******************************************************************************* - * HW_PDB_IDLY - Interrupt Delay register - ******************************************************************************/ - -/*! - * @brief HW_PDB_IDLY - Interrupt Delay register (RW) - * - * Reset value: 0x0000FFFFU - */ -typedef union _hw_pdb_idly -{ - uint32_t U; - struct _hw_pdb_idly_bitfields - { - uint32_t IDLY : 16; /*!< [15:0] PDB Interrupt Delay */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_idly_t; - -/*! - * @name Constants and macros for entire PDB_IDLY register - */ -/*@{*/ -#define HW_PDB_IDLY_ADDR(x) ((x) + 0xCU) - -#define HW_PDB_IDLY(x) (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x)) -#define HW_PDB_IDLY_RD(x) (HW_PDB_IDLY(x).U) -#define HW_PDB_IDLY_WR(x, v) (HW_PDB_IDLY(x).U = (v)) -#define HW_PDB_IDLY_SET(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) | (v))) -#define HW_PDB_IDLY_CLR(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v))) -#define HW_PDB_IDLY_TOG(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_IDLY bitfields - */ - -/*! - * @name Register PDB_IDLY, field IDLY[15:0] (RW) - * - * Specifies the delay value to schedule the PDB interrupt. It can be used to - * schedule an independent interrupt at some point in the PDB cycle. If enabled, a - * PDB interrupt is generated, when the counter is equal to the IDLY. Reading - * this field returns the value of internal register that is effective for the - * current cycle of the PDB. - */ -/*@{*/ -#define BP_PDB_IDLY_IDLY (0U) /*!< Bit position for PDB_IDLY_IDLY. */ -#define BM_PDB_IDLY_IDLY (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */ -#define BS_PDB_IDLY_IDLY (16U) /*!< Bit field size in bits for PDB_IDLY_IDLY. */ - -/*! @brief Read current value of the PDB_IDLY_IDLY field. */ -#define BR_PDB_IDLY_IDLY(x) (HW_PDB_IDLY(x).B.IDLY) - -/*! @brief Format value for bitfield PDB_IDLY_IDLY. */ -#define BF_PDB_IDLY_IDLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY) - -/*! @brief Set the IDLY field to a new value. */ -#define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_CHnC1 - Channel n Control register 1 - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW) - * - * Reset value: 0x00000000U - * - * Each PDB channel has one control register, CHnC1. The bits in this register - * control the functionality of each PDB channel operation. - */ -typedef union _hw_pdb_chnc1 -{ - uint32_t U; - struct _hw_pdb_chnc1_bitfields - { - uint32_t EN : 8; /*!< [7:0] PDB Channel Pre-Trigger Enable */ - uint32_t TOS : 8; /*!< [15:8] PDB Channel Pre-Trigger Output Select */ - uint32_t BB : 8; /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back - * Operation Enable */ - uint32_t RESERVED0 : 8; /*!< [31:24] */ - } B; -} hw_pdb_chnc1_t; - -/*! - * @name Constants and macros for entire PDB_CHnC1 register - */ -/*@{*/ -#define HW_PDB_CHnC1_COUNT (2U) - -#define HW_PDB_CHnC1_ADDR(x, n) ((x) + 0x10U + (0x28U * (n))) - -#define HW_PDB_CHnC1(x, n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n)) -#define HW_PDB_CHnC1_RD(x, n) (HW_PDB_CHnC1(x, n).U) -#define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v)) -#define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) | (v))) -#define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v))) -#define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnC1 bitfields - */ - -/*! - * @name Register PDB_CHnC1, field EN[7:0] (RW) - * - * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger - * bits are implemented in this MCU. - * - * Values: - * - 0 - PDB channel's corresponding pre-trigger disabled. - * - 1 - PDB channel's corresponding pre-trigger enabled. - */ -/*@{*/ -#define BP_PDB_CHnC1_EN (0U) /*!< Bit position for PDB_CHnC1_EN. */ -#define BM_PDB_CHnC1_EN (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */ -#define BS_PDB_CHnC1_EN (8U) /*!< Bit field size in bits for PDB_CHnC1_EN. */ - -/*! @brief Read current value of the PDB_CHnC1_EN field. */ -#define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN) - -/*! @brief Format value for bitfield PDB_CHnC1_EN. */ -#define BF_PDB_CHnC1_EN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN) - -/*! @brief Set the EN field to a new value. */ -#define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v))) -/*@}*/ - -/*! - * @name Register PDB_CHnC1, field TOS[15:8] (RW) - * - * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are - * implemented in this MCU. - * - * Values: - * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The - * pre-trigger asserts one peripheral clock cycle after a rising edge is detected - * on selected trigger input source or software trigger is selected and SWTRIG - * is written with 1. - * - 1 - PDB channel's corresponding pre-trigger asserts when the counter - * reaches the channel delay register and one peripheral clock cycle after a rising - * edge is detected on selected trigger input source or software trigger is - * selected and SETRIG is written with 1. - */ -/*@{*/ -#define BP_PDB_CHnC1_TOS (8U) /*!< Bit position for PDB_CHnC1_TOS. */ -#define BM_PDB_CHnC1_TOS (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */ -#define BS_PDB_CHnC1_TOS (8U) /*!< Bit field size in bits for PDB_CHnC1_TOS. */ - -/*! @brief Read current value of the PDB_CHnC1_TOS field. */ -#define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS) - -/*! @brief Format value for bitfield PDB_CHnC1_TOS. */ -#define BF_PDB_CHnC1_TOS(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS) - -/*! @brief Set the TOS field to a new value. */ -#define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v))) -/*@}*/ - -/*! - * @name Register PDB_CHnC1, field BB[23:16] (RW) - * - * These bits enable the PDB ADC pre-trigger operation as back-to-back mode. - * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation - * enables the ADC conversions complete to trigger the next PDB channel - * pre-trigger and trigger output, so that the ADC conversions can be triggered on next - * set of configuration and results registers. Application code must only enable - * the back-to-back operation of the PDB pre-triggers at the leading of the - * back-to-back connection chain. - * - * Values: - * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled. - * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled. - */ -/*@{*/ -#define BP_PDB_CHnC1_BB (16U) /*!< Bit position for PDB_CHnC1_BB. */ -#define BM_PDB_CHnC1_BB (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */ -#define BS_PDB_CHnC1_BB (8U) /*!< Bit field size in bits for PDB_CHnC1_BB. */ - -/*! @brief Read current value of the PDB_CHnC1_BB field. */ -#define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB) - -/*! @brief Format value for bitfield PDB_CHnC1_BB. */ -#define BF_PDB_CHnC1_BB(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB) - -/*! @brief Set the BB field to a new value. */ -#define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v))) -/*@}*/ -/******************************************************************************* - * HW_PDB_CHnS - Channel n Status register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnS - Channel n Status register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_chns -{ - uint32_t U; - struct _hw_pdb_chns_bitfields - { - uint32_t ERR : 8; /*!< [7:0] PDB Channel Sequence Error Flags */ - uint32_t RESERVED0 : 8; /*!< [15:8] */ - uint32_t CF : 8; /*!< [23:16] PDB Channel Flags */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ - } B; -} hw_pdb_chns_t; - -/*! - * @name Constants and macros for entire PDB_CHnS register - */ -/*@{*/ -#define HW_PDB_CHnS_COUNT (2U) - -#define HW_PDB_CHnS_ADDR(x, n) ((x) + 0x14U + (0x28U * (n))) - -#define HW_PDB_CHnS(x, n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n)) -#define HW_PDB_CHnS_RD(x, n) (HW_PDB_CHnS(x, n).U) -#define HW_PDB_CHnS_WR(x, n, v) (HW_PDB_CHnS(x, n).U = (v)) -#define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) | (v))) -#define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v))) -#define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnS bitfields - */ - -/*! - * @name Register PDB_CHnS, field ERR[7:0] (RW) - * - * Only the lower M bits are implemented in this MCU. - * - * Values: - * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger. - * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger. - * ADCn block can be triggered for a conversion by one pre-trigger from PDB - * channel n. When one conversion, which is triggered by one of the pre-triggers - * from PDB channel n, is in progress, new trigger from PDB channel's - * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. - * Writing 0's to clear the sequence error flags. - */ -/*@{*/ -#define BP_PDB_CHnS_ERR (0U) /*!< Bit position for PDB_CHnS_ERR. */ -#define BM_PDB_CHnS_ERR (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */ -#define BS_PDB_CHnS_ERR (8U) /*!< Bit field size in bits for PDB_CHnS_ERR. */ - -/*! @brief Read current value of the PDB_CHnS_ERR field. */ -#define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR) - -/*! @brief Format value for bitfield PDB_CHnS_ERR. */ -#define BF_PDB_CHnS_ERR(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR) - -/*! @brief Set the ERR field to a new value. */ -#define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v))) -/*@}*/ - -/*! - * @name Register PDB_CHnS, field CF[23:16] (RW) - * - * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to - * clear these bits. - */ -/*@{*/ -#define BP_PDB_CHnS_CF (16U) /*!< Bit position for PDB_CHnS_CF. */ -#define BM_PDB_CHnS_CF (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */ -#define BS_PDB_CHnS_CF (8U) /*!< Bit field size in bits for PDB_CHnS_CF. */ - -/*! @brief Read current value of the PDB_CHnS_CF field. */ -#define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF) - -/*! @brief Format value for bitfield PDB_CHnS_CF. */ -#define BF_PDB_CHnS_CF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF) - -/*! @brief Set the CF field to a new value. */ -#define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v))) -/*@}*/ -/******************************************************************************* - * HW_PDB_CHnDLY0 - Channel n Delay 0 register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_chndly0 -{ - uint32_t U; - struct _hw_pdb_chndly0_bitfields - { - uint32_t DLY : 16; /*!< [15:0] PDB Channel Delay */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_chndly0_t; - -/*! - * @name Constants and macros for entire PDB_CHnDLY0 register - */ -/*@{*/ -#define HW_PDB_CHnDLY0_COUNT (2U) - -#define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n))) - -#define HW_PDB_CHnDLY0(x, n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n)) -#define HW_PDB_CHnDLY0_RD(x, n) (HW_PDB_CHnDLY0(x, n).U) -#define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v)) -#define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) | (v))) -#define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v))) -#define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnDLY0 bitfields - */ - -/*! - * @name Register PDB_CHnDLY0, field DLY[15:0] (RW) - * - * Specifies the delay value for the channel's corresponding pre-trigger. The - * pre-trigger asserts when the counter is equal to DLY. Reading this field returns - * the value of internal register that is effective for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_CHnDLY0_DLY (0U) /*!< Bit position for PDB_CHnDLY0_DLY. */ -#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */ -#define BS_PDB_CHnDLY0_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */ - -/*! @brief Read current value of the PDB_CHnDLY0_DLY field. */ -#define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY) - -/*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */ -#define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY) - -/*! @brief Set the DLY field to a new value. */ -#define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v))) -/*@}*/ -/******************************************************************************* - * HW_PDB_CHnDLY1 - Channel n Delay 1 register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_chndly1 -{ - uint32_t U; - struct _hw_pdb_chndly1_bitfields - { - uint32_t DLY : 16; /*!< [15:0] PDB Channel Delay */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_chndly1_t; - -/*! - * @name Constants and macros for entire PDB_CHnDLY1 register - */ -/*@{*/ -#define HW_PDB_CHnDLY1_COUNT (2U) - -#define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n))) - -#define HW_PDB_CHnDLY1(x, n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n)) -#define HW_PDB_CHnDLY1_RD(x, n) (HW_PDB_CHnDLY1(x, n).U) -#define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v)) -#define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) | (v))) -#define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v))) -#define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnDLY1 bitfields - */ - -/*! - * @name Register PDB_CHnDLY1, field DLY[15:0] (RW) - * - * These bits specify the delay value for the channel's corresponding - * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these - * bits returns the value of internal register that is effective for the current PDB - * cycle. - */ -/*@{*/ -#define BP_PDB_CHnDLY1_DLY (0U) /*!< Bit position for PDB_CHnDLY1_DLY. */ -#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */ -#define BS_PDB_CHnDLY1_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */ - -/*! @brief Read current value of the PDB_CHnDLY1_DLY field. */ -#define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY) - -/*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */ -#define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY) - -/*! @brief Set the DLY field to a new value. */ -#define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_DACINTCn - DAC Interval Trigger n Control register - ******************************************************************************/ - -/*! - * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_dacintcn -{ - uint32_t U; - struct _hw_pdb_dacintcn_bitfields - { - uint32_t TOE : 1; /*!< [0] DAC Interval Trigger Enable */ - uint32_t EXT : 1; /*!< [1] DAC External Trigger Input Enable */ - uint32_t RESERVED0 : 30; /*!< [31:2] */ - } B; -} hw_pdb_dacintcn_t; - -/*! - * @name Constants and macros for entire PDB_DACINTCn register - */ -/*@{*/ -#define HW_PDB_DACINTCn_COUNT (2U) - -#define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n))) - -#define HW_PDB_DACINTCn(x, n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n)) -#define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U) -#define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v)) -#define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) | (v))) -#define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v))) -#define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_DACINTCn bitfields - */ - -/*! - * @name Register PDB_DACINTCn, field TOE[0] (RW) - * - * This bit enables the DAC interval trigger. - * - * Values: - * - 0 - DAC interval trigger disabled. - * - 1 - DAC interval trigger enabled. - */ -/*@{*/ -#define BP_PDB_DACINTCn_TOE (0U) /*!< Bit position for PDB_DACINTCn_TOE. */ -#define BM_PDB_DACINTCn_TOE (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */ -#define BS_PDB_DACINTCn_TOE (1U) /*!< Bit field size in bits for PDB_DACINTCn_TOE. */ - -/*! @brief Read current value of the PDB_DACINTCn_TOE field. */ -#define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE)) - -/*! @brief Format value for bitfield PDB_DACINTCn_TOE. */ -#define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE) - -/*! @brief Set the TOE field to a new value. */ -#define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v)) -/*@}*/ - -/*! - * @name Register PDB_DACINTCn, field EXT[1] (RW) - * - * Enables the external trigger for DAC interval counter. - * - * Values: - * - 0 - DAC external trigger input disabled. DAC interval counter is reset and - * counting starts when a rising edge is detected on selected trigger input - * source or software trigger is selected and SWTRIG is written with 1. - * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed - * and DAC external trigger input triggers the DAC interval trigger. - */ -/*@{*/ -#define BP_PDB_DACINTCn_EXT (1U) /*!< Bit position for PDB_DACINTCn_EXT. */ -#define BM_PDB_DACINTCn_EXT (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */ -#define BS_PDB_DACINTCn_EXT (1U) /*!< Bit field size in bits for PDB_DACINTCn_EXT. */ - -/*! @brief Read current value of the PDB_DACINTCn_EXT field. */ -#define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT)) - -/*! @brief Format value for bitfield PDB_DACINTCn_EXT. */ -#define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT) - -/*! @brief Set the EXT field to a new value. */ -#define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v)) -/*@}*/ -/******************************************************************************* - * HW_PDB_DACINTn - DAC Interval n register - ******************************************************************************/ - -/*! - * @brief HW_PDB_DACINTn - DAC Interval n register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_dacintn -{ - uint32_t U; - struct _hw_pdb_dacintn_bitfields - { - uint32_t INT : 16; /*!< [15:0] DAC Interval */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_dacintn_t; - -/*! - * @name Constants and macros for entire PDB_DACINTn register - */ -/*@{*/ -#define HW_PDB_DACINTn_COUNT (2U) - -#define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n))) - -#define HW_PDB_DACINTn(x, n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n)) -#define HW_PDB_DACINTn_RD(x, n) (HW_PDB_DACINTn(x, n).U) -#define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v)) -#define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) | (v))) -#define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v))) -#define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_DACINTn bitfields - */ - -/*! - * @name Register PDB_DACINTn, field INT[15:0] (RW) - * - * Specifies the interval value for DAC interval trigger. DAC interval trigger - * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. - * Reading this field returns the value of internal register that is effective - * for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */ -#define BM_PDB_DACINTn_INT (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */ -#define BS_PDB_DACINTn_INT (16U) /*!< Bit field size in bits for PDB_DACINTn_INT. */ - -/*! @brief Read current value of the PDB_DACINTn_INT field. */ -#define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT) - -/*! @brief Format value for bitfield PDB_DACINTn_INT. */ -#define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT) - -/*! @brief Set the INT field to a new value. */ -#define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_POEN - Pulse-Out n Enable register - ******************************************************************************/ - -/*! - * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_poen -{ - uint32_t U; - struct _hw_pdb_poen_bitfields - { - uint32_t POEN : 8; /*!< [7:0] PDB Pulse-Out Enable */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_pdb_poen_t; - -/*! - * @name Constants and macros for entire PDB_POEN register - */ -/*@{*/ -#define HW_PDB_POEN_ADDR(x) ((x) + 0x190U) - -#define HW_PDB_POEN(x) (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x)) -#define HW_PDB_POEN_RD(x) (HW_PDB_POEN(x).U) -#define HW_PDB_POEN_WR(x, v) (HW_PDB_POEN(x).U = (v)) -#define HW_PDB_POEN_SET(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) | (v))) -#define HW_PDB_POEN_CLR(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v))) -#define HW_PDB_POEN_TOG(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_POEN bitfields - */ - -/*! - * @name Register PDB_POEN, field POEN[7:0] (RW) - * - * Enables the pulse output. Only lower Y bits are implemented in this MCU. - * - * Values: - * - 0 - PDB Pulse-Out disabled - * - 1 - PDB Pulse-Out enabled - */ -/*@{*/ -#define BP_PDB_POEN_POEN (0U) /*!< Bit position for PDB_POEN_POEN. */ -#define BM_PDB_POEN_POEN (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */ -#define BS_PDB_POEN_POEN (8U) /*!< Bit field size in bits for PDB_POEN_POEN. */ - -/*! @brief Read current value of the PDB_POEN_POEN field. */ -#define BR_PDB_POEN_POEN(x) (HW_PDB_POEN(x).B.POEN) - -/*! @brief Format value for bitfield PDB_POEN_POEN. */ -#define BF_PDB_POEN_POEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN) - -/*! @brief Set the POEN field to a new value. */ -#define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_POnDLY - Pulse-Out n Delay register - ******************************************************************************/ - -/*! - * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_pondly -{ - uint32_t U; - struct _hw_pdb_pondly_bitfields - { - uint32_t DLY2 : 16; /*!< [15:0] PDB Pulse-Out Delay 2 */ - uint32_t DLY1 : 16; /*!< [31:16] PDB Pulse-Out Delay 1 */ - } B; -} hw_pdb_pondly_t; - -/*! - * @name Constants and macros for entire PDB_POnDLY register - */ -/*@{*/ -#define HW_PDB_POnDLY_COUNT (2U) - -#define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n))) - -#define HW_PDB_POnDLY(x, n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n)) -#define HW_PDB_POnDLY_RD(x, n) (HW_PDB_POnDLY(x, n).U) -#define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v)) -#define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) | (v))) -#define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v))) -#define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_POnDLY bitfields - */ - -/*! - * @name Register PDB_POnDLY, field DLY2[15:0] (RW) - * - * Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when - * the PDB counter is equal to the DLY2. Reading this field returns the value of - * internal register that is effective for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_POnDLY_DLY2 (0U) /*!< Bit position for PDB_POnDLY_DLY2. */ -#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */ -#define BS_PDB_POnDLY_DLY2 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY2. */ - -/*! @brief Read current value of the PDB_POnDLY_DLY2 field. */ -#define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2) - -/*! @brief Format value for bitfield PDB_POnDLY_DLY2. */ -#define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2) - -/*! @brief Set the DLY2 field to a new value. */ -#define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v))) -/*@}*/ - -/*! - * @name Register PDB_POnDLY, field DLY1[31:16] (RW) - * - * Specifies the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when - * the PDB counter is equal to the DLY1. Reading this field returns the value of - * internal register that is effective for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_POnDLY_DLY1 (16U) /*!< Bit position for PDB_POnDLY_DLY1. */ -#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */ -#define BS_PDB_POnDLY_DLY1 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY1. */ - -/*! @brief Read current value of the PDB_POnDLY_DLY1 field. */ -#define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1) - -/*! @brief Format value for bitfield PDB_POnDLY_DLY1. */ -#define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1) - -/*! @brief Set the DLY1 field to a new value. */ -#define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v))) -/*@}*/ - -/******************************************************************************* - * hw_pdb_t - module struct - ******************************************************************************/ -/*! - * @brief All PDB module registers. - */ -#pragma pack(1) -typedef struct _hw_pdb -{ - __IO hw_pdb_sc_t SC; /*!< [0x0] Status and Control register */ - __IO hw_pdb_mod_t MOD; /*!< [0x4] Modulus register */ - __I hw_pdb_cnt_t CNT; /*!< [0x8] Counter register */ - __IO hw_pdb_idly_t IDLY; /*!< [0xC] Interrupt Delay register */ - struct { - __IO hw_pdb_chnc1_t CHnC1; /*!< [0x10] Channel n Control register 1 */ - __IO hw_pdb_chns_t CHnS; /*!< [0x14] Channel n Status register */ - __IO hw_pdb_chndly0_t CHnDLY0; /*!< [0x18] Channel n Delay 0 register */ - __IO hw_pdb_chndly1_t CHnDLY1; /*!< [0x1C] Channel n Delay 1 register */ - uint8_t _reserved0[24]; - } CH[2]; - uint8_t _reserved0[240]; - struct { - __IO hw_pdb_dacintcn_t DACINTCn; /*!< [0x150] DAC Interval Trigger n Control register */ - __IO hw_pdb_dacintn_t DACINTn; /*!< [0x154] DAC Interval n register */ - } DAC[2]; - uint8_t _reserved1[48]; - __IO hw_pdb_poen_t POEN; /*!< [0x190] Pulse-Out n Enable register */ - __IO hw_pdb_pondly_t POnDLY[2]; /*!< [0x194] Pulse-Out n Delay register */ -} hw_pdb_t; -#pragma pack() - -/*! @brief Macro to access all PDB registers. */ -/*! @param x PDB module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PDB(PDB0_BASE). */ -#define HW_PDB(x) (*(hw_pdb_t *)(x)) - -#endif /* __HW_PDB_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h deleted file mode 100644 index ce537b1d82d..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h +++ /dev/null @@ -1,516 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PIT_REGISTERS_H__ -#define __HW_PIT_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 PIT - * - * Periodic Interrupt Timer - * - * Registers defined in this header file: - * - HW_PIT_MCR - PIT Module Control Register - * - HW_PIT_LDVALn - Timer Load Value Register - * - HW_PIT_CVALn - Current Timer Value Register - * - HW_PIT_TCTRLn - Timer Control Register - * - HW_PIT_TFLGn - Timer Flag Register - * - * - hw_pit_t - Struct containing all module registers. - */ - -#define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */ - -/******************************************************************************* - * HW_PIT_MCR - PIT Module Control Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_MCR - PIT Module Control Register (RW) - * - * Reset value: 0x00000006U - * - * This register enables or disables the PIT timer clocks and controls the - * timers when the PIT enters the Debug mode. - */ -typedef union _hw_pit_mcr -{ - uint32_t U; - struct _hw_pit_mcr_bitfields - { - uint32_t FRZ : 1; /*!< [0] Freeze */ - uint32_t MDIS : 1; /*!< [1] Module Disable - (PIT section) */ - uint32_t RESERVED0 : 30; /*!< [31:2] */ - } B; -} hw_pit_mcr_t; - -/*! - * @name Constants and macros for entire PIT_MCR register - */ -/*@{*/ -#define HW_PIT_MCR_ADDR(x) ((x) + 0x0U) - -#define HW_PIT_MCR(x) (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x)) -#define HW_PIT_MCR_RD(x) (HW_PIT_MCR(x).U) -#define HW_PIT_MCR_WR(x, v) (HW_PIT_MCR(x).U = (v)) -#define HW_PIT_MCR_SET(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) | (v))) -#define HW_PIT_MCR_CLR(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v))) -#define HW_PIT_MCR_TOG(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_MCR bitfields - */ - -/*! - * @name Register PIT_MCR, field FRZ[0] (RW) - * - * Allows the timers to be stopped when the device enters the Debug mode. - * - * Values: - * - 0 - Timers continue to run in Debug mode. - * - 1 - Timers are stopped in Debug mode. - */ -/*@{*/ -#define BP_PIT_MCR_FRZ (0U) /*!< Bit position for PIT_MCR_FRZ. */ -#define BM_PIT_MCR_FRZ (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */ -#define BS_PIT_MCR_FRZ (1U) /*!< Bit field size in bits for PIT_MCR_FRZ. */ - -/*! @brief Read current value of the PIT_MCR_FRZ field. */ -#define BR_PIT_MCR_FRZ(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ)) - -/*! @brief Format value for bitfield PIT_MCR_FRZ. */ -#define BF_PIT_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ) - -/*! @brief Set the FRZ field to a new value. */ -#define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v)) -/*@}*/ - -/*! - * @name Register PIT_MCR, field MDIS[1] (RW) - * - * Disables the standard timers. This field must be enabled before any other - * setup is done. - * - * Values: - * - 0 - Clock for standard PIT timers is enabled. - * - 1 - Clock for standard PIT timers is disabled. - */ -/*@{*/ -#define BP_PIT_MCR_MDIS (1U) /*!< Bit position for PIT_MCR_MDIS. */ -#define BM_PIT_MCR_MDIS (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */ -#define BS_PIT_MCR_MDIS (1U) /*!< Bit field size in bits for PIT_MCR_MDIS. */ - -/*! @brief Read current value of the PIT_MCR_MDIS field. */ -#define BR_PIT_MCR_MDIS(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS)) - -/*! @brief Format value for bitfield PIT_MCR_MDIS. */ -#define BF_PIT_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS) - -/*! @brief Set the MDIS field to a new value. */ -#define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_PIT_LDVALn - Timer Load Value Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_LDVALn - Timer Load Value Register (RW) - * - * Reset value: 0x00000000U - * - * These registers select the timeout period for the timer interrupts. - */ -typedef union _hw_pit_ldvaln -{ - uint32_t U; - struct _hw_pit_ldvaln_bitfields - { - uint32_t TSV : 32; /*!< [31:0] Timer Start Value */ - } B; -} hw_pit_ldvaln_t; - -/*! - * @name Constants and macros for entire PIT_LDVALn register - */ -/*@{*/ -#define HW_PIT_LDVALn_COUNT (4U) - -#define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n))) - -#define HW_PIT_LDVALn(x, n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n)) -#define HW_PIT_LDVALn_RD(x, n) (HW_PIT_LDVALn(x, n).U) -#define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v)) -#define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) | (v))) -#define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v))) -#define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_LDVALn bitfields - */ - -/*! - * @name Register PIT_LDVALn, field TSV[31:0] (RW) - * - * Sets the timer start value. The timer will count down until it reaches 0, - * then it will generate an interrupt and load this register value again. Writing a - * new value to this register will not restart the timer; instead the value will - * be loaded after the timer expires. To abort the current cycle and start a - * timer period with the new value, the timer must be disabled and enabled again. - */ -/*@{*/ -#define BP_PIT_LDVALn_TSV (0U) /*!< Bit position for PIT_LDVALn_TSV. */ -#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */ -#define BS_PIT_LDVALn_TSV (32U) /*!< Bit field size in bits for PIT_LDVALn_TSV. */ - -/*! @brief Read current value of the PIT_LDVALn_TSV field. */ -#define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U) - -/*! @brief Format value for bitfield PIT_LDVALn_TSV. */ -#define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV) - -/*! @brief Set the TSV field to a new value. */ -#define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_PIT_CVALn - Current Timer Value Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_CVALn - Current Timer Value Register (RO) - * - * Reset value: 0x00000000U - * - * These registers indicate the current timer position. - */ -typedef union _hw_pit_cvaln -{ - uint32_t U; - struct _hw_pit_cvaln_bitfields - { - uint32_t TVL : 32; /*!< [31:0] Current Timer Value */ - } B; -} hw_pit_cvaln_t; - -/*! - * @name Constants and macros for entire PIT_CVALn register - */ -/*@{*/ -#define HW_PIT_CVALn_COUNT (4U) - -#define HW_PIT_CVALn_ADDR(x, n) ((x) + 0x104U + (0x10U * (n))) - -#define HW_PIT_CVALn(x, n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n)) -#define HW_PIT_CVALn_RD(x, n) (HW_PIT_CVALn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual PIT_CVALn bitfields - */ - -/*! - * @name Register PIT_CVALn, field TVL[31:0] (RO) - * - * Represents the current timer value, if the timer is enabled. If the timer is - * disabled, do not use this field as its value is unreliable. The timer uses a - * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. - */ -/*@{*/ -#define BP_PIT_CVALn_TVL (0U) /*!< Bit position for PIT_CVALn_TVL. */ -#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */ -#define BS_PIT_CVALn_TVL (32U) /*!< Bit field size in bits for PIT_CVALn_TVL. */ - -/*! @brief Read current value of the PIT_CVALn_TVL field. */ -#define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U) -/*@}*/ -/******************************************************************************* - * HW_PIT_TCTRLn - Timer Control Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_TCTRLn - Timer Control Register (RW) - * - * Reset value: 0x00000000U - * - * These registers contain the control bits for each timer. - */ -typedef union _hw_pit_tctrln -{ - uint32_t U; - struct _hw_pit_tctrln_bitfields - { - uint32_t TEN : 1; /*!< [0] Timer Enable */ - uint32_t TIE : 1; /*!< [1] Timer Interrupt Enable */ - uint32_t CHN : 1; /*!< [2] Chain Mode */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_pit_tctrln_t; - -/*! - * @name Constants and macros for entire PIT_TCTRLn register - */ -/*@{*/ -#define HW_PIT_TCTRLn_COUNT (4U) - -#define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n))) - -#define HW_PIT_TCTRLn(x, n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n)) -#define HW_PIT_TCTRLn_RD(x, n) (HW_PIT_TCTRLn(x, n).U) -#define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v)) -#define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) | (v))) -#define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v))) -#define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_TCTRLn bitfields - */ - -/*! - * @name Register PIT_TCTRLn, field TEN[0] (RW) - * - * Enables or disables the timer. - * - * Values: - * - 0 - Timer n is disabled. - * - 1 - Timer n is enabled. - */ -/*@{*/ -#define BP_PIT_TCTRLn_TEN (0U) /*!< Bit position for PIT_TCTRLn_TEN. */ -#define BM_PIT_TCTRLn_TEN (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */ -#define BS_PIT_TCTRLn_TEN (1U) /*!< Bit field size in bits for PIT_TCTRLn_TEN. */ - -/*! @brief Read current value of the PIT_TCTRLn_TEN field. */ -#define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN)) - -/*! @brief Format value for bitfield PIT_TCTRLn_TEN. */ -#define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN) - -/*! @brief Set the TEN field to a new value. */ -#define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v)) -/*@}*/ - -/*! - * @name Register PIT_TCTRLn, field TIE[1] (RW) - * - * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt - * will immediately cause an interrupt event. To avoid this, the associated - * TFLGn[TIF] must be cleared first. - * - * Values: - * - 0 - Interrupt requests from Timer n are disabled. - * - 1 - Interrupt will be requested whenever TIF is set. - */ -/*@{*/ -#define BP_PIT_TCTRLn_TIE (1U) /*!< Bit position for PIT_TCTRLn_TIE. */ -#define BM_PIT_TCTRLn_TIE (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */ -#define BS_PIT_TCTRLn_TIE (1U) /*!< Bit field size in bits for PIT_TCTRLn_TIE. */ - -/*! @brief Read current value of the PIT_TCTRLn_TIE field. */ -#define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE)) - -/*! @brief Format value for bitfield PIT_TCTRLn_TIE. */ -#define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v)) -/*@}*/ - -/*! - * @name Register PIT_TCTRLn, field CHN[2] (RW) - * - * When activated, Timer n-1 needs to expire before timer n can decrement by 1. - * Timer 0 cannot be chained. - * - * Values: - * - 0 - Timer is not chained. - * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this - * field is set, Timer 2 is chained to Timer 1. - */ -/*@{*/ -#define BP_PIT_TCTRLn_CHN (2U) /*!< Bit position for PIT_TCTRLn_CHN. */ -#define BM_PIT_TCTRLn_CHN (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */ -#define BS_PIT_TCTRLn_CHN (1U) /*!< Bit field size in bits for PIT_TCTRLn_CHN. */ - -/*! @brief Read current value of the PIT_TCTRLn_CHN field. */ -#define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN)) - -/*! @brief Format value for bitfield PIT_TCTRLn_CHN. */ -#define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN) - -/*! @brief Set the CHN field to a new value. */ -#define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v)) -/*@}*/ -/******************************************************************************* - * HW_PIT_TFLGn - Timer Flag Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_TFLGn - Timer Flag Register (RW) - * - * Reset value: 0x00000000U - * - * These registers hold the PIT interrupt flags. - */ -typedef union _hw_pit_tflgn -{ - uint32_t U; - struct _hw_pit_tflgn_bitfields - { - uint32_t TIF : 1; /*!< [0] Timer Interrupt Flag */ - uint32_t RESERVED0 : 31; /*!< [31:1] */ - } B; -} hw_pit_tflgn_t; - -/*! - * @name Constants and macros for entire PIT_TFLGn register - */ -/*@{*/ -#define HW_PIT_TFLGn_COUNT (4U) - -#define HW_PIT_TFLGn_ADDR(x, n) ((x) + 0x10CU + (0x10U * (n))) - -#define HW_PIT_TFLGn(x, n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n)) -#define HW_PIT_TFLGn_RD(x, n) (HW_PIT_TFLGn(x, n).U) -#define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v)) -#define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) | (v))) -#define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v))) -#define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_TFLGn bitfields - */ - -/*! - * @name Register PIT_TFLGn, field TIF[0] (W1C) - * - * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. - * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an - * interrupt request. - * - * Values: - * - 0 - Timeout has not yet occurred. - * - 1 - Timeout has occurred. - */ -/*@{*/ -#define BP_PIT_TFLGn_TIF (0U) /*!< Bit position for PIT_TFLGn_TIF. */ -#define BM_PIT_TFLGn_TIF (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */ -#define BS_PIT_TFLGn_TIF (1U) /*!< Bit field size in bits for PIT_TFLGn_TIF. */ - -/*! @brief Read current value of the PIT_TFLGn_TIF field. */ -#define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF)) - -/*! @brief Format value for bitfield PIT_TFLGn_TIF. */ -#define BF_PIT_TFLGn_TIF(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF) - -/*! @brief Set the TIF field to a new value. */ -#define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_pit_t - module struct - ******************************************************************************/ -/*! - * @brief All PIT module registers. - */ -#pragma pack(1) -typedef struct _hw_pit -{ - __IO hw_pit_mcr_t MCR; /*!< [0x0] PIT Module Control Register */ - uint8_t _reserved0[252]; - struct { - __IO hw_pit_ldvaln_t LDVALn; /*!< [0x100] Timer Load Value Register */ - __I hw_pit_cvaln_t CVALn; /*!< [0x104] Current Timer Value Register */ - __IO hw_pit_tctrln_t TCTRLn; /*!< [0x108] Timer Control Register */ - __IO hw_pit_tflgn_t TFLGn; /*!< [0x10C] Timer Flag Register */ - } CHANNEL[4]; -} hw_pit_t; -#pragma pack() - -/*! @brief Macro to access all PIT registers. */ -/*! @param x PIT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PIT(PIT_BASE). */ -#define HW_PIT(x) (*(hw_pit_t *)(x)) - -#endif /* __HW_PIT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h deleted file mode 100644 index ceb62974cda..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h +++ /dev/null @@ -1,572 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PMC_REGISTERS_H__ -#define __HW_PMC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 PMC - * - * Power Management Controller - * - * Registers defined in this header file: - * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register - * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register - * - HW_PMC_REGSC - Regulator Status And Control register - * - * - hw_pmc_t - Struct containing all module registers. - */ - -#define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */ - -/******************************************************************************* - * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register - ******************************************************************************/ - -/*! - * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW) - * - * Reset value: 0x10U - * - * This register contains status and control bits to support the low voltage - * detect function. This register should be written during the reset initialization - * program to set the desired controls even if the desired settings are the same - * as the reset settings. While the device is in the very low power or low - * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect - * systems that must have LVD always on, configure the Power Mode Protection - * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or - * low leakage modes from being enabled. See the device's data sheet for the - * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The - * register's other bits are reset on Chip Reset Not VLLS. For more information - * about these reset types, refer to the Reset section details. - */ -typedef union _hw_pmc_lvdsc1 -{ - uint8_t U; - struct _hw_pmc_lvdsc1_bitfields - { - uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */ - uint8_t RESERVED0 : 2; /*!< [3:2] */ - uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */ - uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */ - uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */ - uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */ - } B; -} hw_pmc_lvdsc1_t; - -/*! - * @name Constants and macros for entire PMC_LVDSC1 register - */ -/*@{*/ -#define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U) - -#define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x)) -#define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U) -#define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v)) -#define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v))) -#define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v))) -#define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PMC_LVDSC1 bitfields - */ - -/*! - * @name Register PMC_LVDSC1, field LVDV[1:0] (RW) - * - * Selects the LVD trip point voltage (V LVD ). - * - * Values: - * - 00 - Low trip point selected (V LVD = V LVDL ) - * - 01 - High trip point selected (V LVD = V LVDH ) - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */ -#define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */ -#define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */ -#define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV) - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */ -#define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV) - -/*! @brief Set the LVDV field to a new value. */ -#define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v))) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDRE[4] (RW) - * - * This write-once bit enables LVDF events to generate a hardware reset. - * Additional writes are ignored. - * - * Values: - * - 0 - LVDF does not generate hardware resets - * - 1 - Force an MCU reset when LVDF = 1 - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */ -#define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */ -#define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */ -#define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE)) - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */ -#define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE) - -/*! @brief Set the LVDRE field to a new value. */ -#define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDIE[5] (RW) - * - * Enables hardware interrupt requests for LVDF. - * - * Values: - * - 0 - Hardware interrupt disabled (use polling) - * - 1 - Request a hardware interrupt when LVDF = 1 - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */ -#define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */ -#define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */ -#define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE)) - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */ -#define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE) - -/*! @brief Set the LVDIE field to a new value. */ -#define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ) - * - * This write-only field is used to acknowledge low voltage detection errors. - * Write 1 to clear LVDF. Reads always return 0. - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */ -#define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */ -#define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */ - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */ -#define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK) - -/*! @brief Set the LVDACK field to a new value. */ -#define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDF[7] (RO) - * - * This read-only status field indicates a low-voltage detect event. - * - * Values: - * - 0 - Low-voltage event not detected - * - 1 - Low-voltage event detected - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */ -#define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */ -#define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */ -#define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF)) -/*@}*/ - -/******************************************************************************* - * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register - ******************************************************************************/ - -/*! - * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW) - * - * Reset value: 0x00U - * - * This register contains status and control bits to support the low voltage - * warning function. While the device is in the very low power or low leakage modes, - * the LVD system is disabled regardless of LVDSC2 settings. See the device's - * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV - * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the - * register are reset on Chip Reset Not VLLS. For more information about these - * reset types, refer to the Reset section details. - */ -typedef union _hw_pmc_lvdsc2 -{ - uint8_t U; - struct _hw_pmc_lvdsc2_bitfields - { - uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */ - uint8_t RESERVED0 : 3; /*!< [4:2] */ - uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */ - uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */ - uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */ - } B; -} hw_pmc_lvdsc2_t; - -/*! - * @name Constants and macros for entire PMC_LVDSC2 register - */ -/*@{*/ -#define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U) - -#define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x)) -#define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U) -#define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v)) -#define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v))) -#define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v))) -#define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PMC_LVDSC2 bitfields - */ - -/*! - * @name Register PMC_LVDSC2, field LVWV[1:0] (RW) - * - * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning - * depends on LVDSC1[LVDV]. - * - * Values: - * - 00 - Low trip point selected (VLVW = VLVW1) - * - 01 - Mid 1 trip point selected (VLVW = VLVW2) - * - 10 - Mid 2 trip point selected (VLVW = VLVW3) - * - 11 - High trip point selected (VLVW = VLVW4) - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */ -#define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */ -#define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */ - -/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */ -#define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV) - -/*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */ -#define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV) - -/*! @brief Set the LVWV field to a new value. */ -#define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v))) -/*@}*/ - -/*! - * @name Register PMC_LVDSC2, field LVWIE[5] (RW) - * - * Enables hardware interrupt requests for LVWF. - * - * Values: - * - 0 - Hardware interrupt disabled (use polling) - * - 1 - Request a hardware interrupt when LVWF = 1 - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */ -#define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */ -#define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */ - -/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */ -#define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE)) - -/*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */ -#define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE) - -/*! @brief Set the LVWIE field to a new value. */ -#define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ) - * - * This write-only field is used to acknowledge low voltage warning errors. - * Write 1 to clear LVWF. Reads always return 0. - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */ -#define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */ -#define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */ - -/*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */ -#define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK) - -/*! @brief Set the LVWACK field to a new value. */ -#define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC2, field LVWF[7] (RO) - * - * This read-only status field indicates a low-voltage warning event. LVWF is - * set when VSupply transitions below the trip point, or after reset and VSupply is - * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW - * interrupt function, before enabling LVWIE, LVWF must be cleared by writing - * LVWACK first. - * - * Values: - * - 0 - Low-voltage warning event not detected - * - 1 - Low-voltage warning event detected - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */ -#define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */ -#define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */ - -/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */ -#define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF)) -/*@}*/ - -/******************************************************************************* - * HW_PMC_REGSC - Regulator Status And Control register - ******************************************************************************/ - -/*! - * @brief HW_PMC_REGSC - Regulator Status And Control register (RW) - * - * Reset value: 0x04U - * - * The PMC contains an internal voltage regulator. The voltage regulator design - * uses a bandgap reference that is also available through a buffer as input to - * certain internal peripherals, such as the CMP and ADC. The internal regulator - * provides a status bit (REGONS) indicating the regulator is in run regulation. - * This register is reset on Chip Reset Not VLLS and by reset types that trigger - * Chip Reset not VLLS. See the Reset section details for more information. - */ -typedef union _hw_pmc_regsc -{ - uint8_t U; - struct _hw_pmc_regsc_bitfields - { - uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */ - uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */ - uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_pmc_regsc_t; - -/*! - * @name Constants and macros for entire PMC_REGSC register - */ -/*@{*/ -#define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U) - -#define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x)) -#define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U) -#define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v)) -#define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v))) -#define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v))) -#define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PMC_REGSC bitfields - */ - -/*! - * @name Register PMC_REGSC, field BGBE[0] (RW) - * - * Enables the bandgap buffer. - * - * Values: - * - 0 - Bandgap buffer not enabled - * - 1 - Bandgap buffer enabled - */ -/*@{*/ -#define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */ -#define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */ -#define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */ - -/*! @brief Read current value of the PMC_REGSC_BGBE field. */ -#define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE)) - -/*! @brief Format value for bitfield PMC_REGSC_BGBE. */ -#define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE) - -/*! @brief Set the BGBE field to a new value. */ -#define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_REGSC, field REGONS[2] (RO) - * - * This read-only field provides the current status of the internal voltage - * regulator. - * - * Values: - * - 0 - Regulator is in stop regulation or in transition to/from it - * - 1 - Regulator is in run regulation - */ -/*@{*/ -#define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */ -#define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */ -#define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */ - -/*! @brief Read current value of the PMC_REGSC_REGONS field. */ -#define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS)) -/*@}*/ - -/*! - * @name Register PMC_REGSC, field ACKISO[3] (W1C) - * - * Reading this field indicates whether certain peripherals and the I/O pads are - * in a latched state as a result of having been in a VLLS mode. Writing 1 to - * this field when it is set releases the I/O pads and certain peripherals to their - * normal run mode state. After recovering from a VLLS mode, user should restore - * chip configuration before clearing ACKISO. In particular, pin configuration - * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from - * being falsely set when ACKISO is cleared. - * - * Values: - * - 0 - Peripherals and I/O pads are in normal run state. - * - 1 - Certain peripherals and I/O pads are in an isolated and latched state. - */ -/*@{*/ -#define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */ -#define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */ -#define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */ - -/*! @brief Read current value of the PMC_REGSC_ACKISO field. */ -#define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO)) - -/*! @brief Format value for bitfield PMC_REGSC_ACKISO. */ -#define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO) - -/*! @brief Set the ACKISO field to a new value. */ -#define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v)) -/*@}*/ - -/*! - * @name Register PMC_REGSC, field BGEN[4] (RW) - * - * BGEN controls whether the bandgap is enabled in lower power modes of - * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage - * reference in low power modes of operation, set BGEN to continue to enable the - * bandgap operation. When the bandgap voltage reference is not needed in low - * power modes, clear BGEN to avoid excess power consumption. - * - * Values: - * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. - * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. - */ -/*@{*/ -#define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */ -#define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */ -#define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */ - -/*! @brief Read current value of the PMC_REGSC_BGEN field. */ -#define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN)) - -/*! @brief Format value for bitfield PMC_REGSC_BGEN. */ -#define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN) - -/*! @brief Set the BGEN field to a new value. */ -#define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_pmc_t - module struct - ******************************************************************************/ -/*! - * @brief All PMC module registers. - */ -#pragma pack(1) -typedef struct _hw_pmc -{ - __IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */ - __IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */ - __IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */ -} hw_pmc_t; -#pragma pack() - -/*! @brief Macro to access all PMC registers. */ -/*! @param x PMC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PMC(PMC_BASE). */ -#define HW_PMC(x) (*(hw_pmc_t *)(x)) - -#endif /* __HW_PMC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h deleted file mode 100644 index 8c97a37ba37..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h +++ /dev/null @@ -1,892 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PORT_REGISTERS_H__ -#define __HW_PORT_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 PORT - * - * Pin Control and Interrupts - * - * Registers defined in this header file: - * - HW_PORT_PCRn - Pin Control Register n - * - HW_PORT_GPCLR - Global Pin Control Low Register - * - HW_PORT_GPCHR - Global Pin Control High Register - * - HW_PORT_ISFR - Interrupt Status Flag Register - * - HW_PORT_DFER - Digital Filter Enable Register - * - HW_PORT_DFCR - Digital Filter Clock Register - * - HW_PORT_DFWR - Digital Filter Width Register - * - * - hw_port_t - Struct containing all module registers. - */ - -#define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */ -#define HW_PORTA (0U) /*!< Instance number for PORTA. */ -#define HW_PORTB (1U) /*!< Instance number for PORTB. */ -#define HW_PORTC (2U) /*!< Instance number for PORTC. */ -#define HW_PORTD (3U) /*!< Instance number for PORTD. */ -#define HW_PORTE (4U) /*!< Instance number for PORTE. */ - -/******************************************************************************* - * HW_PORT_PCRn - Pin Control Register n - ******************************************************************************/ - -/*! - * @brief HW_PORT_PCRn - Pin Control Register n (RW) - * - * Reset value: 0x00000700U - * - * See the Signal Multiplexing and Pin Assignment chapter for the reset value of - * this device. See the GPIO Configuration section for details on the available - * functions for each pin. Do not modify pin configuration registers associated - * with pins not available in your selected package. All unbonded pins not - * available in your package will default to DISABLE state for lowest power consumption. - */ -typedef union _hw_port_pcrn -{ - uint32_t U; - struct _hw_port_pcrn_bitfields - { - uint32_t PS : 1; /*!< [0] Pull Select */ - uint32_t PE : 1; /*!< [1] Pull Enable */ - uint32_t SRE : 1; /*!< [2] Slew Rate Enable */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t PFE : 1; /*!< [4] Passive Filter Enable */ - uint32_t ODE : 1; /*!< [5] Open Drain Enable */ - uint32_t DSE : 1; /*!< [6] Drive Strength Enable */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */ - uint32_t RESERVED2 : 4; /*!< [14:11] */ - uint32_t LK : 1; /*!< [15] Lock Register */ - uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */ - uint32_t RESERVED3 : 4; /*!< [23:20] */ - uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */ - uint32_t RESERVED4 : 7; /*!< [31:25] */ - } B; -} hw_port_pcrn_t; - -/*! - * @name Constants and macros for entire PORT_PCRn register - */ -/*@{*/ -#define HW_PORT_PCRn_COUNT (32U) - -#define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n))) - -#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n)) -#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U) -#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v)) -#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v))) -#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v))) -#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_PCRn bitfields - */ - -/*! - * @name Register PORT_PCRn, field PS[0] (RW) - * - * Pull configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the - * corresponding PE field is set. - * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the - * corresponding PE field is set. - */ -/*@{*/ -#define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */ -#define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */ -#define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */ - -/*! @brief Read current value of the PORT_PCRn_PS field. */ -#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS)) - -/*! @brief Format value for bitfield PORT_PCRn_PS. */ -#define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS) - -/*! @brief Set the PS field to a new value. */ -#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field PE[1] (RW) - * - * Pull configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Internal pullup or pulldown resistor is not enabled on the - * corresponding pin. - * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding - * pin, if the pin is configured as a digital input. - */ -/*@{*/ -#define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */ -#define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */ -#define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */ - -/*! @brief Read current value of the PORT_PCRn_PE field. */ -#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE)) - -/*! @brief Format value for bitfield PORT_PCRn_PE. */ -#define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE) - -/*! @brief Set the PE field to a new value. */ -#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field SRE[2] (RW) - * - * Slew rate configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is - * configured as a digital output. - * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is - * configured as a digital output. - */ -/*@{*/ -#define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */ -#define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */ -#define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */ - -/*! @brief Read current value of the PORT_PCRn_SRE field. */ -#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE)) - -/*! @brief Format value for bitfield PORT_PCRn_SRE. */ -#define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE) - -/*! @brief Set the SRE field to a new value. */ -#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field PFE[4] (RW) - * - * Passive filter configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Passive input filter is disabled on the corresponding pin. - * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is - * configured as a digital input. Refer to the device data sheet for filter - * characteristics. - */ -/*@{*/ -#define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */ -#define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */ -#define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */ - -/*! @brief Read current value of the PORT_PCRn_PFE field. */ -#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE)) - -/*! @brief Format value for bitfield PORT_PCRn_PFE. */ -#define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE) - -/*! @brief Set the PFE field to a new value. */ -#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field ODE[5] (RW) - * - * Open drain configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Open drain output is disabled on the corresponding pin. - * - 1 - Open drain output is enabled on the corresponding pin, if the pin is - * configured as a digital output. - */ -/*@{*/ -#define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */ -#define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */ -#define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */ - -/*! @brief Read current value of the PORT_PCRn_ODE field. */ -#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE)) - -/*! @brief Format value for bitfield PORT_PCRn_ODE. */ -#define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE) - -/*! @brief Set the ODE field to a new value. */ -#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field DSE[6] (RW) - * - * Drive strength configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Low drive strength is configured on the corresponding pin, if pin is - * configured as a digital output. - * - 1 - High drive strength is configured on the corresponding pin, if pin is - * configured as a digital output. - */ -/*@{*/ -#define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */ -#define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */ -#define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */ - -/*! @brief Read current value of the PORT_PCRn_DSE field. */ -#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE)) - -/*! @brief Format value for bitfield PORT_PCRn_DSE. */ -#define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE) - -/*! @brief Set the DSE field to a new value. */ -#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field MUX[10:8] (RW) - * - * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are - * reserved and may result in configuring the pin for a different pin muxing - * slot. The corresponding pin is configured in the following pin muxing slot as - * follows: - * - * Values: - * - 000 - Pin disabled (analog). - * - 001 - Alternative 1 (GPIO). - * - 010 - Alternative 2 (chip-specific). - * - 011 - Alternative 3 (chip-specific). - * - 100 - Alternative 4 (chip-specific). - * - 101 - Alternative 5 (chip-specific). - * - 110 - Alternative 6 (chip-specific). - * - 111 - Alternative 7 (chip-specific). - */ -/*@{*/ -#define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */ -#define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */ -#define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */ - -/*! @brief Read current value of the PORT_PCRn_MUX field. */ -#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX) - -/*! @brief Format value for bitfield PORT_PCRn_MUX. */ -#define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX) - -/*! @brief Set the MUX field to a new value. */ -#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v))) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field LK[15] (RW) - * - * Values: - * - 0 - Pin Control Register fields [15:0] are not locked. - * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated - * until the next system reset. - */ -/*@{*/ -#define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */ -#define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */ -#define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */ - -/*! @brief Read current value of the PORT_PCRn_LK field. */ -#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK)) - -/*! @brief Format value for bitfield PORT_PCRn_LK. */ -#define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK) - -/*! @brief Set the LK field to a new value. */ -#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field IRQC[19:16] (RW) - * - * The pin interrupt configuration is valid in all digital pin muxing modes. The - * corresponding pin is configured to generate interrupt/DMA request as follows: - * - * Values: - * - 0000 - Interrupt/DMA request disabled. - * - 0001 - DMA request on rising edge. - * - 0010 - DMA request on falling edge. - * - 0011 - DMA request on either edge. - * - 1000 - Interrupt when logic 0. - * - 1001 - Interrupt on rising-edge. - * - 1010 - Interrupt on falling-edge. - * - 1011 - Interrupt on either edge. - * - 1100 - Interrupt when logic 1. - */ -/*@{*/ -#define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */ -#define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */ -#define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */ - -/*! @brief Read current value of the PORT_PCRn_IRQC field. */ -#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC) - -/*! @brief Format value for bitfield PORT_PCRn_IRQC. */ -#define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC) - -/*! @brief Set the IRQC field to a new value. */ -#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v))) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field ISF[24] (W1C) - * - * The pin interrupt configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Configured interrupt is not detected. - * - 1 - Configured interrupt is detected. If the pin is configured to generate - * a DMA request, then the corresponding flag will be cleared automatically - * at the completion of the requested DMA transfer. Otherwise, the flag - * remains set until a logic 1 is written to the flag. If the pin is configured for - * a level sensitive interrupt and the pin remains asserted, then the flag - * is set again immediately after it is cleared. - */ -/*@{*/ -#define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */ -#define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */ -#define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */ - -/*! @brief Read current value of the PORT_PCRn_ISF field. */ -#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF)) - -/*! @brief Format value for bitfield PORT_PCRn_ISF. */ -#define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF) - -/*! @brief Set the ISF field to a new value. */ -#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_GPCLR - Global Pin Control Low Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ) - * - * Reset value: 0x00000000U - * - * Only 32-bit writes are supported to this register. - */ -typedef union _hw_port_gpclr -{ - uint32_t U; - struct _hw_port_gpclr_bitfields - { - uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */ - uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */ - } B; -} hw_port_gpclr_t; - -/*! - * @name Constants and macros for entire PORT_GPCLR register - */ -/*@{*/ -#define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U) - -#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x)) -#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U) -#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual PORT_GPCLR bitfields - */ - -/*! - * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ) - * - * Write value that is written to all Pin Control Registers bits [15:0] that are - * selected by GPWE. - */ -/*@{*/ -#define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */ -#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */ -#define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */ - -/*! @brief Format value for bitfield PORT_GPCLR_GPWD. */ -#define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD) - -/*! @brief Set the GPWD field to a new value. */ -#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v))) -/*@}*/ - -/*! - * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ) - * - * Selects which Pin Control Registers (15 through 0) bits [15:0] update with - * the value in GPWD. If a selected Pin Control Register is locked then the write - * to that register is ignored. - * - * Values: - * - 0 - Corresponding Pin Control Register is not updated with the value in - * GPWD. - * - 1 - Corresponding Pin Control Register is updated with the value in GPWD. - */ -/*@{*/ -#define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */ -#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */ -#define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */ - -/*! @brief Format value for bitfield PORT_GPCLR_GPWE. */ -#define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE) - -/*! @brief Set the GPWE field to a new value. */ -#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v))) -/*@}*/ - -/******************************************************************************* - * HW_PORT_GPCHR - Global Pin Control High Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ) - * - * Reset value: 0x00000000U - * - * Only 32-bit writes are supported to this register. - */ -typedef union _hw_port_gpchr -{ - uint32_t U; - struct _hw_port_gpchr_bitfields - { - uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */ - uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */ - } B; -} hw_port_gpchr_t; - -/*! - * @name Constants and macros for entire PORT_GPCHR register - */ -/*@{*/ -#define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U) - -#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x)) -#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U) -#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual PORT_GPCHR bitfields - */ - -/*! - * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ) - * - * Write value that is written to all Pin Control Registers bits [15:0] that are - * selected by GPWE. - */ -/*@{*/ -#define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */ -#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */ -#define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */ - -/*! @brief Format value for bitfield PORT_GPCHR_GPWD. */ -#define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD) - -/*! @brief Set the GPWD field to a new value. */ -#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v))) -/*@}*/ - -/*! - * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ) - * - * Selects which Pin Control Registers (31 through 16) bits [15:0] update with - * the value in GPWD. If a selected Pin Control Register is locked then the write - * to that register is ignored. - * - * Values: - * - 0 - Corresponding Pin Control Register is not updated with the value in - * GPWD. - * - 1 - Corresponding Pin Control Register is updated with the value in GPWD. - */ -/*@{*/ -#define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */ -#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */ -#define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */ - -/*! @brief Format value for bitfield PORT_GPCHR_GPWE. */ -#define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE) - -/*! @brief Set the GPWE field to a new value. */ -#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v))) -/*@}*/ - -/******************************************************************************* - * HW_PORT_ISFR - Interrupt Status Flag Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C) - * - * Reset value: 0x00000000U - * - * The pin interrupt configuration is valid in all digital pin muxing modes. The - * Interrupt Status Flag for each pin is also visible in the corresponding Pin - * Control Register, and each flag can be cleared in either location. - */ -typedef union _hw_port_isfr -{ - uint32_t U; - struct _hw_port_isfr_bitfields - { - uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */ - } B; -} hw_port_isfr_t; - -/*! - * @name Constants and macros for entire PORT_ISFR register - */ -/*@{*/ -#define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U) - -#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x)) -#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U) -#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v)) -#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v))) -#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v))) -#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_ISFR bitfields - */ - -/*! - * @name Register PORT_ISFR, field ISF[31:0] (W1C) - * - * Each bit in the field indicates the detection of the configured interrupt of - * the same number as the field. - * - * Values: - * - 0 - Configured interrupt is not detected. - * - 1 - Configured interrupt is detected. If the pin is configured to generate - * a DMA request, then the corresponding flag will be cleared automatically - * at the completion of the requested DMA transfer. Otherwise, the flag - * remains set until a logic 1 is written to the flag. If the pin is configured for - * a level sensitive interrupt and the pin remains asserted, then the flag - * is set again immediately after it is cleared. - */ -/*@{*/ -#define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */ -#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */ -#define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */ - -/*! @brief Read current value of the PORT_ISFR_ISF field. */ -#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U) - -/*! @brief Format value for bitfield PORT_ISFR_ISF. */ -#define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF) - -/*! @brief Set the ISF field to a new value. */ -#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_DFER - Digital Filter Enable Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_DFER - Digital Filter Enable Register (RW) - * - * Reset value: 0x00000000U - * - * The corresponding bit is read only for pins that do not support a digital - * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for - * the pins that support digital filter. The digital filter configuration is valid - * in all digital pin muxing modes. - */ -typedef union _hw_port_dfer -{ - uint32_t U; - struct _hw_port_dfer_bitfields - { - uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */ - } B; -} hw_port_dfer_t; - -/*! - * @name Constants and macros for entire PORT_DFER register - */ -/*@{*/ -#define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U) - -#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x)) -#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U) -#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v)) -#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v))) -#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v))) -#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_DFER bitfields - */ - -/*! - * @name Register PORT_DFER, field DFE[31:0] (RW) - * - * The digital filter configuration is valid in all digital pin muxing modes. - * The output of each digital filter is reset to zero at system reset and whenever - * the digital filter is disabled. Each bit in the field enables the digital - * filter of the same number as the field. - * - * Values: - * - 0 - Digital filter is disabled on the corresponding pin and output of the - * digital filter is reset to zero. - * - 1 - Digital filter is enabled on the corresponding pin, if the pin is - * configured as a digital input. - */ -/*@{*/ -#define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */ -#define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */ -#define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */ - -/*! @brief Read current value of the PORT_DFER_DFE field. */ -#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U) - -/*! @brief Format value for bitfield PORT_DFER_DFE. */ -#define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE) - -/*! @brief Set the DFE field to a new value. */ -#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_DFCR - Digital Filter Clock Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW) - * - * Reset value: 0x00000000U - * - * This register is read only for ports that do not support a digital filter. - * The digital filter configuration is valid in all digital pin muxing modes. - */ -typedef union _hw_port_dfcr -{ - uint32_t U; - struct _hw_port_dfcr_bitfields - { - uint32_t CS : 1; /*!< [0] Clock Source */ - uint32_t RESERVED0 : 31; /*!< [31:1] */ - } B; -} hw_port_dfcr_t; - -/*! - * @name Constants and macros for entire PORT_DFCR register - */ -/*@{*/ -#define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U) - -#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x)) -#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U) -#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v)) -#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v))) -#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v))) -#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_DFCR bitfields - */ - -/*! - * @name Register PORT_DFCR, field CS[0] (RW) - * - * The digital filter configuration is valid in all digital pin muxing modes. - * Configures the clock source for the digital input filters. Changing the filter - * clock source must be done only when all digital filters are disabled. - * - * Values: - * - 0 - Digital filters are clocked by the bus clock. - * - 1 - Digital filters are clocked by the 1 kHz LPO clock. - */ -/*@{*/ -#define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */ -#define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */ -#define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */ - -/*! @brief Read current value of the PORT_DFCR_CS field. */ -#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS)) - -/*! @brief Format value for bitfield PORT_DFCR_CS. */ -#define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS) - -/*! @brief Set the CS field to a new value. */ -#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_DFWR - Digital Filter Width Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_DFWR - Digital Filter Width Register (RW) - * - * Reset value: 0x00000000U - * - * This register is read only for ports that do not support a digital filter. - * The digital filter configuration is valid in all digital pin muxing modes. - */ -typedef union _hw_port_dfwr -{ - uint32_t U; - struct _hw_port_dfwr_bitfields - { - uint32_t FILT : 5; /*!< [4:0] Filter Length */ - uint32_t RESERVED0 : 27; /*!< [31:5] */ - } B; -} hw_port_dfwr_t; - -/*! - * @name Constants and macros for entire PORT_DFWR register - */ -/*@{*/ -#define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U) - -#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x)) -#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U) -#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v)) -#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v))) -#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v))) -#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_DFWR bitfields - */ - -/*! - * @name Register PORT_DFWR, field FILT[4:0] (RW) - * - * The digital filter configuration is valid in all digital pin muxing modes. - * Configures the maximum size of the glitches, in clock cycles, that the digital - * filter absorbs for the enabled digital filters. Glitches that are longer than - * this register setting will pass through the digital filter, and glitches that - * are equal to or less than this register setting are filtered. Changing the - * filter length must be done only after all filters are disabled. - */ -/*@{*/ -#define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */ -#define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */ -#define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */ - -/*! @brief Read current value of the PORT_DFWR_FILT field. */ -#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT) - -/*! @brief Format value for bitfield PORT_DFWR_FILT. */ -#define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT) - -/*! @brief Set the FILT field to a new value. */ -#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v))) -/*@}*/ - -/******************************************************************************* - * hw_port_t - module struct - ******************************************************************************/ -/*! - * @brief All PORT module registers. - */ -#pragma pack(1) -typedef struct _hw_port -{ - __IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */ - __O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */ - __O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */ - uint8_t _reserved0[24]; - __IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */ - uint8_t _reserved1[28]; - __IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */ - __IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */ - __IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */ -} hw_port_t; -#pragma pack() - -/*! @brief Macro to access all PORT registers. */ -/*! @param x PORT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PORT(PORTA_BASE). */ -#define HW_PORT(x) (*(hw_port_t *)(x)) - -#endif /* __HW_PORT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h deleted file mode 100644 index c9da9ba5438..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h +++ /dev/null @@ -1,1154 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RCM_REGISTERS_H__ -#define __HW_RCM_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 RCM - * - * Reset Control Module - * - * Registers defined in this header file: - * - HW_RCM_SRS0 - System Reset Status Register 0 - * - HW_RCM_SRS1 - System Reset Status Register 1 - * - HW_RCM_RPFC - Reset Pin Filter Control register - * - HW_RCM_RPFW - Reset Pin Filter Width register - * - HW_RCM_MR - Mode Register - * - HW_RCM_SSRS0 - Sticky System Reset Status Register 0 - * - HW_RCM_SSRS1 - Sticky System Reset Status Register 1 - * - * - hw_rcm_t - Struct containing all module registers. - */ - -#define HW_RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */ - -/******************************************************************************* - * HW_RCM_SRS0 - System Reset Status Register 0 - ******************************************************************************/ - -/*! - * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO) - * - * Reset value: 0x82U - * - * This register includes read-only status flags to indicate the source of the - * most recent reset. The reset state of these bits depends on what caused the MCU - * to reset. The reset value of this register depends on the reset source: POR - * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET - * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other - * reset - a bit is set if its corresponding reset source caused the reset - */ -typedef union _hw_rcm_srs0 -{ - uint8_t U; - struct _hw_rcm_srs0_bitfields - { - uint8_t WAKEUP : 1; /*!< [0] Low Leakage Wakeup Reset */ - uint8_t LVD : 1; /*!< [1] Low-Voltage Detect Reset */ - uint8_t LOC : 1; /*!< [2] Loss-of-Clock Reset */ - uint8_t LOL : 1; /*!< [3] Loss-of-Lock Reset */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t WDOGb : 1; /*!< [5] Watchdog */ - uint8_t PIN : 1; /*!< [6] External Reset Pin */ - uint8_t POR : 1; /*!< [7] Power-On Reset */ - } B; -} hw_rcm_srs0_t; - -/*! - * @name Constants and macros for entire RCM_SRS0 register - */ -/*@{*/ -#define HW_RCM_SRS0_ADDR(x) ((x) + 0x0U) - -#define HW_RCM_SRS0(x) (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR(x)) -#define HW_RCM_SRS0_RD(x) (HW_RCM_SRS0(x).U) -/*@}*/ - -/* - * Constants & macros for individual RCM_SRS0 bitfields - */ - -/*! - * @name Register RCM_SRS0, field WAKEUP[0] (RO) - * - * Indicates a reset has been caused by an enabled LLWU module wakeup source - * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only - * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx - * mode causes a reset. This bit is cleared by any reset except WAKEUP. - * - * Values: - * - 0 - Reset not caused by LLWU module wakeup source - * - 1 - Reset caused by LLWU module wakeup source - */ -/*@{*/ -#define BP_RCM_SRS0_WAKEUP (0U) /*!< Bit position for RCM_SRS0_WAKEUP. */ -#define BM_RCM_SRS0_WAKEUP (0x01U) /*!< Bit mask for RCM_SRS0_WAKEUP. */ -#define BS_RCM_SRS0_WAKEUP (1U) /*!< Bit field size in bits for RCM_SRS0_WAKEUP. */ - -/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */ -#define BR_RCM_SRS0_WAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WAKEUP)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field LVD[1] (RO) - * - * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, - * an LVD reset occurs. This field is also set by POR. - * - * Values: - * - 0 - Reset not caused by LVD trip or POR - * - 1 - Reset caused by LVD trip or POR - */ -/*@{*/ -#define BP_RCM_SRS0_LVD (1U) /*!< Bit position for RCM_SRS0_LVD. */ -#define BM_RCM_SRS0_LVD (0x02U) /*!< Bit mask for RCM_SRS0_LVD. */ -#define BS_RCM_SRS0_LVD (1U) /*!< Bit field size in bits for RCM_SRS0_LVD. */ - -/*! @brief Read current value of the RCM_SRS0_LVD field. */ -#define BR_RCM_SRS0_LVD(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LVD)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field LOC[2] (RO) - * - * Indicates a reset has been caused by a loss of external clock. The MCG clock - * monitor must be enabled for a loss of clock to be detected. Refer to the - * detailed MCG description for information on enabling the clock monitor. - * - * Values: - * - 0 - Reset not caused by a loss of external clock. - * - 1 - Reset caused by a loss of external clock. - */ -/*@{*/ -#define BP_RCM_SRS0_LOC (2U) /*!< Bit position for RCM_SRS0_LOC. */ -#define BM_RCM_SRS0_LOC (0x04U) /*!< Bit mask for RCM_SRS0_LOC. */ -#define BS_RCM_SRS0_LOC (1U) /*!< Bit field size in bits for RCM_SRS0_LOC. */ - -/*! @brief Read current value of the RCM_SRS0_LOC field. */ -#define BR_RCM_SRS0_LOC(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field LOL[3] (RO) - * - * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the - * MCG description for information on the loss-of-clock event. - * - * Values: - * - 0 - Reset not caused by a loss of lock in the PLL - * - 1 - Reset caused by a loss of lock in the PLL - */ -/*@{*/ -#define BP_RCM_SRS0_LOL (3U) /*!< Bit position for RCM_SRS0_LOL. */ -#define BM_RCM_SRS0_LOL (0x08U) /*!< Bit mask for RCM_SRS0_LOL. */ -#define BS_RCM_SRS0_LOL (1U) /*!< Bit field size in bits for RCM_SRS0_LOL. */ - -/*! @brief Read current value of the RCM_SRS0_LOL field. */ -#define BR_RCM_SRS0_LOL(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field WDOG[5] (RO) - * - * Indicates a reset has been caused by the watchdog timer timing out. This - * reset source can be blocked by disabling the watchdog. - * - * Values: - * - 0 - Reset not caused by watchdog timeout - * - 1 - Reset caused by watchdog timeout - */ -/*@{*/ -#define BP_RCM_SRS0_WDOG (5U) /*!< Bit position for RCM_SRS0_WDOG. */ -#define BM_RCM_SRS0_WDOG (0x20U) /*!< Bit mask for RCM_SRS0_WDOG. */ -#define BS_RCM_SRS0_WDOG (1U) /*!< Bit field size in bits for RCM_SRS0_WDOG. */ - -/*! @brief Read current value of the RCM_SRS0_WDOG field. */ -#define BR_RCM_SRS0_WDOG(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WDOG)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field PIN[6] (RO) - * - * Indicates a reset has been caused by an active-low level on the external - * RESET pin. - * - * Values: - * - 0 - Reset not caused by external reset pin - * - 1 - Reset caused by external reset pin - */ -/*@{*/ -#define BP_RCM_SRS0_PIN (6U) /*!< Bit position for RCM_SRS0_PIN. */ -#define BM_RCM_SRS0_PIN (0x40U) /*!< Bit mask for RCM_SRS0_PIN. */ -#define BS_RCM_SRS0_PIN (1U) /*!< Bit field size in bits for RCM_SRS0_PIN. */ - -/*! @brief Read current value of the RCM_SRS0_PIN field. */ -#define BR_RCM_SRS0_PIN(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_PIN)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field POR[7] (RO) - * - * Indicates a reset has been caused by the power-on detection logic. Because - * the internal supply voltage was ramping up at the time, the low-voltage reset - * (LVD) status bit is also set to indicate that the reset occurred while the - * internal supply was below the LVD threshold. - * - * Values: - * - 0 - Reset not caused by POR - * - 1 - Reset caused by POR - */ -/*@{*/ -#define BP_RCM_SRS0_POR (7U) /*!< Bit position for RCM_SRS0_POR. */ -#define BM_RCM_SRS0_POR (0x80U) /*!< Bit mask for RCM_SRS0_POR. */ -#define BS_RCM_SRS0_POR (1U) /*!< Bit field size in bits for RCM_SRS0_POR. */ - -/*! @brief Read current value of the RCM_SRS0_POR field. */ -#define BR_RCM_SRS0_POR(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_POR)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_SRS1 - System Reset Status Register 1 - ******************************************************************************/ - -/*! - * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO) - * - * Reset value: 0x00U - * - * This register includes read-only status flags to indicate the source of the - * most recent reset. The reset state of these bits depends on what caused the MCU - * to reset. The reset value of this register depends on the reset source: POR - * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other - * reset - a bit is set if its corresponding reset source caused the reset - */ -typedef union _hw_rcm_srs1 -{ - uint8_t U; - struct _hw_rcm_srs1_bitfields - { - uint8_t JTAG : 1; /*!< [0] JTAG Generated Reset */ - uint8_t LOCKUP : 1; /*!< [1] Core Lockup */ - uint8_t SW : 1; /*!< [2] Software */ - uint8_t MDM_AP : 1; /*!< [3] MDM-AP System Reset Request */ - uint8_t EZPT : 1; /*!< [4] EzPort Reset */ - uint8_t SACKERR : 1; /*!< [5] Stop Mode Acknowledge Error Reset */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_rcm_srs1_t; - -/*! - * @name Constants and macros for entire RCM_SRS1 register - */ -/*@{*/ -#define HW_RCM_SRS1_ADDR(x) ((x) + 0x1U) - -#define HW_RCM_SRS1(x) (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR(x)) -#define HW_RCM_SRS1_RD(x) (HW_RCM_SRS1(x).U) -/*@}*/ - -/* - * Constants & macros for individual RCM_SRS1 bitfields - */ - -/*! - * @name Register RCM_SRS1, field JTAG[0] (RO) - * - * Indicates a reset has been caused by JTAG selection of certain IR codes: - * EZPORT, EXTEST, HIGHZ, and CLAMP. - * - * Values: - * - 0 - Reset not caused by JTAG - * - 1 - Reset caused by JTAG - */ -/*@{*/ -#define BP_RCM_SRS1_JTAG (0U) /*!< Bit position for RCM_SRS1_JTAG. */ -#define BM_RCM_SRS1_JTAG (0x01U) /*!< Bit mask for RCM_SRS1_JTAG. */ -#define BS_RCM_SRS1_JTAG (1U) /*!< Bit field size in bits for RCM_SRS1_JTAG. */ - -/*! @brief Read current value of the RCM_SRS1_JTAG field. */ -#define BR_RCM_SRS1_JTAG(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_JTAG)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field LOCKUP[1] (RO) - * - * Indicates a reset has been caused by the ARM core indication of a LOCKUP - * event. - * - * Values: - * - 0 - Reset not caused by core LOCKUP event - * - 1 - Reset caused by core LOCKUP event - */ -/*@{*/ -#define BP_RCM_SRS1_LOCKUP (1U) /*!< Bit position for RCM_SRS1_LOCKUP. */ -#define BM_RCM_SRS1_LOCKUP (0x02U) /*!< Bit mask for RCM_SRS1_LOCKUP. */ -#define BS_RCM_SRS1_LOCKUP (1U) /*!< Bit field size in bits for RCM_SRS1_LOCKUP. */ - -/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */ -#define BR_RCM_SRS1_LOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_LOCKUP)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field SW[2] (RO) - * - * Indicates a reset has been caused by software setting of SYSRESETREQ bit in - * Application Interrupt and Reset Control Register in the ARM core. - * - * Values: - * - 0 - Reset not caused by software setting of SYSRESETREQ bit - * - 1 - Reset caused by software setting of SYSRESETREQ bit - */ -/*@{*/ -#define BP_RCM_SRS1_SW (2U) /*!< Bit position for RCM_SRS1_SW. */ -#define BM_RCM_SRS1_SW (0x04U) /*!< Bit mask for RCM_SRS1_SW. */ -#define BS_RCM_SRS1_SW (1U) /*!< Bit field size in bits for RCM_SRS1_SW. */ - -/*! @brief Read current value of the RCM_SRS1_SW field. */ -#define BR_RCM_SRS1_SW(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SW)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field MDM_AP[3] (RO) - * - * Indicates a reset has been caused by the host debugger system setting of the - * System Reset Request bit in the MDM-AP Control Register. - * - * Values: - * - 0 - Reset not caused by host debugger system setting of the System Reset - * Request bit - * - 1 - Reset caused by host debugger system setting of the System Reset - * Request bit - */ -/*@{*/ -#define BP_RCM_SRS1_MDM_AP (3U) /*!< Bit position for RCM_SRS1_MDM_AP. */ -#define BM_RCM_SRS1_MDM_AP (0x08U) /*!< Bit mask for RCM_SRS1_MDM_AP. */ -#define BS_RCM_SRS1_MDM_AP (1U) /*!< Bit field size in bits for RCM_SRS1_MDM_AP. */ - -/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */ -#define BR_RCM_SRS1_MDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_MDM_AP)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field EZPT[4] (RO) - * - * Indicates a reset has been caused by EzPort receiving the RESET command while - * the device is in EzPort mode. - * - * Values: - * - 0 - Reset not caused by EzPort receiving the RESET command while the device - * is in EzPort mode - * - 1 - Reset caused by EzPort receiving the RESET command while the device is - * in EzPort mode - */ -/*@{*/ -#define BP_RCM_SRS1_EZPT (4U) /*!< Bit position for RCM_SRS1_EZPT. */ -#define BM_RCM_SRS1_EZPT (0x10U) /*!< Bit mask for RCM_SRS1_EZPT. */ -#define BS_RCM_SRS1_EZPT (1U) /*!< Bit field size in bits for RCM_SRS1_EZPT. */ - -/*! @brief Read current value of the RCM_SRS1_EZPT field. */ -#define BR_RCM_SRS1_EZPT(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_EZPT)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field SACKERR[5] (RO) - * - * Indicates that after an attempt to enter Stop mode, a reset has been caused - * by a failure of one or more peripherals to acknowledge within approximately one - * second to enter stop mode. - * - * Values: - * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter - * stop mode - * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop - * mode - */ -/*@{*/ -#define BP_RCM_SRS1_SACKERR (5U) /*!< Bit position for RCM_SRS1_SACKERR. */ -#define BM_RCM_SRS1_SACKERR (0x20U) /*!< Bit mask for RCM_SRS1_SACKERR. */ -#define BS_RCM_SRS1_SACKERR (1U) /*!< Bit field size in bits for RCM_SRS1_SACKERR. */ - -/*! @brief Read current value of the RCM_SRS1_SACKERR field. */ -#define BR_RCM_SRS1_SACKERR(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SACKERR)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_RPFC - Reset Pin Filter Control register - ******************************************************************************/ - -/*! - * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW) - * - * Reset value: 0x00U - * - * The reset values of bits 2-0 are for Chip POR only. They are unaffected by - * other reset types. The bus clock filter is reset when disabled or when entering - * stop mode. The LPO filter is reset when disabled . - */ -typedef union _hw_rcm_rpfc -{ - uint8_t U; - struct _hw_rcm_rpfc_bitfields - { - uint8_t RSTFLTSRW : 2; /*!< [1:0] Reset Pin Filter Select in Run and - * Wait Modes */ - uint8_t RSTFLTSS : 1; /*!< [2] Reset Pin Filter Select in Stop Mode */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_rcm_rpfc_t; - -/*! - * @name Constants and macros for entire RCM_RPFC register - */ -/*@{*/ -#define HW_RCM_RPFC_ADDR(x) ((x) + 0x4U) - -#define HW_RCM_RPFC(x) (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR(x)) -#define HW_RCM_RPFC_RD(x) (HW_RCM_RPFC(x).U) -#define HW_RCM_RPFC_WR(x, v) (HW_RCM_RPFC(x).U = (v)) -#define HW_RCM_RPFC_SET(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) | (v))) -#define HW_RCM_RPFC_CLR(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) & ~(v))) -#define HW_RCM_RPFC_TOG(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RCM_RPFC bitfields - */ - -/*! - * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW) - * - * Selects how the reset pin filter is enabled in run and wait modes. - * - * Values: - * - 00 - All filtering disabled - * - 01 - Bus clock filter enabled for normal operation - * - 10 - LPO clock filter enabled for normal operation - * - 11 - Reserved - */ -/*@{*/ -#define BP_RCM_RPFC_RSTFLTSRW (0U) /*!< Bit position for RCM_RPFC_RSTFLTSRW. */ -#define BM_RCM_RPFC_RSTFLTSRW (0x03U) /*!< Bit mask for RCM_RPFC_RSTFLTSRW. */ -#define BS_RCM_RPFC_RSTFLTSRW (2U) /*!< Bit field size in bits for RCM_RPFC_RSTFLTSRW. */ - -/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */ -#define BR_RCM_RPFC_RSTFLTSRW(x) (HW_RCM_RPFC(x).B.RSTFLTSRW) - -/*! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW. */ -#define BF_RCM_RPFC_RSTFLTSRW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSRW) & BM_RCM_RPFC_RSTFLTSRW) - -/*! @brief Set the RSTFLTSRW field to a new value. */ -#define BW_RCM_RPFC_RSTFLTSRW(x, v) (HW_RCM_RPFC_WR(x, (HW_RCM_RPFC_RD(x) & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v))) -/*@}*/ - -/*! - * @name Register RCM_RPFC, field RSTFLTSS[2] (RW) - * - * Selects how the reset pin filter is enabled in Stop and VLPS modes , and also - * during LLS and VLLS modes. On exit from VLLS mode, this bit should be - * reconfigured before clearing PMC_REGSC[ACKISO]. - * - * Values: - * - 0 - All filtering disabled - * - 1 - LPO clock filter enabled - */ -/*@{*/ -#define BP_RCM_RPFC_RSTFLTSS (2U) /*!< Bit position for RCM_RPFC_RSTFLTSS. */ -#define BM_RCM_RPFC_RSTFLTSS (0x04U) /*!< Bit mask for RCM_RPFC_RSTFLTSS. */ -#define BS_RCM_RPFC_RSTFLTSS (1U) /*!< Bit field size in bits for RCM_RPFC_RSTFLTSS. */ - -/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */ -#define BR_RCM_RPFC_RSTFLTSS(x) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS)) - -/*! @brief Format value for bitfield RCM_RPFC_RSTFLTSS. */ -#define BF_RCM_RPFC_RSTFLTSS(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSS) & BM_RCM_RPFC_RSTFLTSS) - -/*! @brief Set the RSTFLTSS field to a new value. */ -#define BW_RCM_RPFC_RSTFLTSS(x, v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_RPFW - Reset Pin Filter Width register - ******************************************************************************/ - -/*! - * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW) - * - * Reset value: 0x00U - * - * The reset values of the bits in the RSTFLTSEL field are for Chip POR only. - * They are unaffected by other reset types. - */ -typedef union _hw_rcm_rpfw -{ - uint8_t U; - struct _hw_rcm_rpfw_bitfields - { - uint8_t RSTFLTSEL : 5; /*!< [4:0] Reset Pin Filter Bus Clock Select */ - uint8_t RESERVED0 : 3; /*!< [7:5] */ - } B; -} hw_rcm_rpfw_t; - -/*! - * @name Constants and macros for entire RCM_RPFW register - */ -/*@{*/ -#define HW_RCM_RPFW_ADDR(x) ((x) + 0x5U) - -#define HW_RCM_RPFW(x) (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR(x)) -#define HW_RCM_RPFW_RD(x) (HW_RCM_RPFW(x).U) -#define HW_RCM_RPFW_WR(x, v) (HW_RCM_RPFW(x).U = (v)) -#define HW_RCM_RPFW_SET(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) | (v))) -#define HW_RCM_RPFW_CLR(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) & ~(v))) -#define HW_RCM_RPFW_TOG(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RCM_RPFW bitfields - */ - -/*! - * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW) - * - * Selects the reset pin bus clock filter width. - * - * Values: - * - 00000 - Bus clock filter count is 1 - * - 00001 - Bus clock filter count is 2 - * - 00010 - Bus clock filter count is 3 - * - 00011 - Bus clock filter count is 4 - * - 00100 - Bus clock filter count is 5 - * - 00101 - Bus clock filter count is 6 - * - 00110 - Bus clock filter count is 7 - * - 00111 - Bus clock filter count is 8 - * - 01000 - Bus clock filter count is 9 - * - 01001 - Bus clock filter count is 10 - * - 01010 - Bus clock filter count is 11 - * - 01011 - Bus clock filter count is 12 - * - 01100 - Bus clock filter count is 13 - * - 01101 - Bus clock filter count is 14 - * - 01110 - Bus clock filter count is 15 - * - 01111 - Bus clock filter count is 16 - * - 10000 - Bus clock filter count is 17 - * - 10001 - Bus clock filter count is 18 - * - 10010 - Bus clock filter count is 19 - * - 10011 - Bus clock filter count is 20 - * - 10100 - Bus clock filter count is 21 - * - 10101 - Bus clock filter count is 22 - * - 10110 - Bus clock filter count is 23 - * - 10111 - Bus clock filter count is 24 - * - 11000 - Bus clock filter count is 25 - * - 11001 - Bus clock filter count is 26 - * - 11010 - Bus clock filter count is 27 - * - 11011 - Bus clock filter count is 28 - * - 11100 - Bus clock filter count is 29 - * - 11101 - Bus clock filter count is 30 - * - 11110 - Bus clock filter count is 31 - * - 11111 - Bus clock filter count is 32 - */ -/*@{*/ -#define BP_RCM_RPFW_RSTFLTSEL (0U) /*!< Bit position for RCM_RPFW_RSTFLTSEL. */ -#define BM_RCM_RPFW_RSTFLTSEL (0x1FU) /*!< Bit mask for RCM_RPFW_RSTFLTSEL. */ -#define BS_RCM_RPFW_RSTFLTSEL (5U) /*!< Bit field size in bits for RCM_RPFW_RSTFLTSEL. */ - -/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */ -#define BR_RCM_RPFW_RSTFLTSEL(x) (HW_RCM_RPFW(x).B.RSTFLTSEL) - -/*! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL. */ -#define BF_RCM_RPFW_RSTFLTSEL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFW_RSTFLTSEL) & BM_RCM_RPFW_RSTFLTSEL) - -/*! @brief Set the RSTFLTSEL field to a new value. */ -#define BW_RCM_RPFW_RSTFLTSEL(x, v) (HW_RCM_RPFW_WR(x, (HW_RCM_RPFW_RD(x) & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v))) -/*@}*/ - -/******************************************************************************* - * HW_RCM_MR - Mode Register - ******************************************************************************/ - -/*! - * @brief HW_RCM_MR - Mode Register (RO) - * - * Reset value: 0x00U - * - * This register includes read-only status flags to indicate the state of the - * mode pins during the last Chip Reset. - */ -typedef union _hw_rcm_mr -{ - uint8_t U; - struct _hw_rcm_mr_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t EZP_MS : 1; /*!< [1] EZP_MS_B pin state */ - uint8_t RESERVED1 : 6; /*!< [7:2] */ - } B; -} hw_rcm_mr_t; - -/*! - * @name Constants and macros for entire RCM_MR register - */ -/*@{*/ -#define HW_RCM_MR_ADDR(x) ((x) + 0x7U) - -#define HW_RCM_MR(x) (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR(x)) -#define HW_RCM_MR_RD(x) (HW_RCM_MR(x).U) -/*@}*/ - -/* - * Constants & macros for individual RCM_MR bitfields - */ - -/*! - * @name Register RCM_MR, field EZP_MS[1] (RO) - * - * Reflects the state of the EZP_MS pin during the last Chip Reset - * - * Values: - * - 0 - Pin deasserted (logic 1) - * - 1 - Pin asserted (logic 0) - */ -/*@{*/ -#define BP_RCM_MR_EZP_MS (1U) /*!< Bit position for RCM_MR_EZP_MS. */ -#define BM_RCM_MR_EZP_MS (0x02U) /*!< Bit mask for RCM_MR_EZP_MS. */ -#define BS_RCM_MR_EZP_MS (1U) /*!< Bit field size in bits for RCM_MR_EZP_MS. */ - -/*! @brief Read current value of the RCM_MR_EZP_MS field. */ -#define BR_RCM_MR_EZP_MS(x) (BITBAND_ACCESS8(HW_RCM_MR_ADDR(x), BP_RCM_MR_EZP_MS)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_SSRS0 - Sticky System Reset Status Register 0 - ******************************************************************************/ - -/*! - * @brief HW_RCM_SSRS0 - Sticky System Reset Status Register 0 (RW) - * - * Reset value: 0x82U - * - * This register includes status flags to indicate all reset sources since the - * last POR, LVD or VLLS Wakeup that have not been cleared by software. Software - * can clear the status flags by writing a logic one to a flag. - */ -typedef union _hw_rcm_ssrs0 -{ - uint8_t U; - struct _hw_rcm_ssrs0_bitfields - { - uint8_t SWAKEUP : 1; /*!< [0] Sticky Low Leakage Wakeup Reset */ - uint8_t SLVD : 1; /*!< [1] Sticky Low-Voltage Detect Reset */ - uint8_t SLOC : 1; /*!< [2] Sticky Loss-of-Clock Reset */ - uint8_t SLOL : 1; /*!< [3] Sticky Loss-of-Lock Reset */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t SWDOG : 1; /*!< [5] Sticky Watchdog */ - uint8_t SPIN : 1; /*!< [6] Sticky External Reset Pin */ - uint8_t SPOR : 1; /*!< [7] Sticky Power-On Reset */ - } B; -} hw_rcm_ssrs0_t; - -/*! - * @name Constants and macros for entire RCM_SSRS0 register - */ -/*@{*/ -#define HW_RCM_SSRS0_ADDR(x) ((x) + 0x8U) - -#define HW_RCM_SSRS0(x) (*(__IO hw_rcm_ssrs0_t *) HW_RCM_SSRS0_ADDR(x)) -#define HW_RCM_SSRS0_RD(x) (HW_RCM_SSRS0(x).U) -#define HW_RCM_SSRS0_WR(x, v) (HW_RCM_SSRS0(x).U = (v)) -#define HW_RCM_SSRS0_SET(x, v) (HW_RCM_SSRS0_WR(x, HW_RCM_SSRS0_RD(x) | (v))) -#define HW_RCM_SSRS0_CLR(x, v) (HW_RCM_SSRS0_WR(x, HW_RCM_SSRS0_RD(x) & ~(v))) -#define HW_RCM_SSRS0_TOG(x, v) (HW_RCM_SSRS0_WR(x, HW_RCM_SSRS0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RCM_SSRS0 bitfields - */ - -/*! - * @name Register RCM_SSRS0, field SWAKEUP[0] (W1C) - * - * Indicates a reset has been caused by an enabled LLWU modulewakeup source - * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only - * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx - * mode causes a reset. - * - * Values: - * - 0 - Reset not caused by LLWU module wakeup source - * - 1 - Reset caused by LLWU module wakeup source - */ -/*@{*/ -#define BP_RCM_SSRS0_SWAKEUP (0U) /*!< Bit position for RCM_SSRS0_SWAKEUP. */ -#define BM_RCM_SSRS0_SWAKEUP (0x01U) /*!< Bit mask for RCM_SSRS0_SWAKEUP. */ -#define BS_RCM_SSRS0_SWAKEUP (1U) /*!< Bit field size in bits for RCM_SSRS0_SWAKEUP. */ - -/*! @brief Read current value of the RCM_SSRS0_SWAKEUP field. */ -#define BR_RCM_SSRS0_SWAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWAKEUP)) - -/*! @brief Format value for bitfield RCM_SSRS0_SWAKEUP. */ -#define BF_RCM_SSRS0_SWAKEUP(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SWAKEUP) & BM_RCM_SSRS0_SWAKEUP) - -/*! @brief Set the SWAKEUP field to a new value. */ -#define BW_RCM_SSRS0_SWAKEUP(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWAKEUP) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS0, field SLVD[1] (W1C) - * - * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, - * an LVD reset occurs. This field is also set by POR. - * - * Values: - * - 0 - Reset not caused by LVD trip or POR - * - 1 - Reset caused by LVD trip or POR - */ -/*@{*/ -#define BP_RCM_SSRS0_SLVD (1U) /*!< Bit position for RCM_SSRS0_SLVD. */ -#define BM_RCM_SSRS0_SLVD (0x02U) /*!< Bit mask for RCM_SSRS0_SLVD. */ -#define BS_RCM_SSRS0_SLVD (1U) /*!< Bit field size in bits for RCM_SSRS0_SLVD. */ - -/*! @brief Read current value of the RCM_SSRS0_SLVD field. */ -#define BR_RCM_SSRS0_SLVD(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLVD)) - -/*! @brief Format value for bitfield RCM_SSRS0_SLVD. */ -#define BF_RCM_SSRS0_SLVD(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLVD) & BM_RCM_SSRS0_SLVD) - -/*! @brief Set the SLVD field to a new value. */ -#define BW_RCM_SSRS0_SLVD(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLVD) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS0, field SLOC[2] (W1C) - * - * Indicates a reset has been caused by a loss of external clock. The MCG clock - * monitor must be enabled for a loss of clock to be detected. Refer to the - * detailed MCG description for information on enabling the clock monitor. - * - * Values: - * - 0 - Reset not caused by a loss of external clock. - * - 1 - Reset caused by a loss of external clock. - */ -/*@{*/ -#define BP_RCM_SSRS0_SLOC (2U) /*!< Bit position for RCM_SSRS0_SLOC. */ -#define BM_RCM_SSRS0_SLOC (0x04U) /*!< Bit mask for RCM_SSRS0_SLOC. */ -#define BS_RCM_SSRS0_SLOC (1U) /*!< Bit field size in bits for RCM_SSRS0_SLOC. */ - -/*! @brief Read current value of the RCM_SSRS0_SLOC field. */ -#define BR_RCM_SSRS0_SLOC(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC)) - -/*! @brief Format value for bitfield RCM_SSRS0_SLOC. */ -#define BF_RCM_SSRS0_SLOC(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLOC) & BM_RCM_SSRS0_SLOC) - -/*! @brief Set the SLOC field to a new value. */ -#define BW_RCM_SSRS0_SLOC(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS0, field SLOL[3] (W1C) - * - * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the - * MCG description for information on the loss-of-clock event. - * - * Values: - * - 0 - Reset not caused by a loss of lock in the PLL - * - 1 - Reset caused by a loss of lock in the PLL - */ -/*@{*/ -#define BP_RCM_SSRS0_SLOL (3U) /*!< Bit position for RCM_SSRS0_SLOL. */ -#define BM_RCM_SSRS0_SLOL (0x08U) /*!< Bit mask for RCM_SSRS0_SLOL. */ -#define BS_RCM_SSRS0_SLOL (1U) /*!< Bit field size in bits for RCM_SSRS0_SLOL. */ - -/*! @brief Read current value of the RCM_SSRS0_SLOL field. */ -#define BR_RCM_SSRS0_SLOL(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL)) - -/*! @brief Format value for bitfield RCM_SSRS0_SLOL. */ -#define BF_RCM_SSRS0_SLOL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLOL) & BM_RCM_SSRS0_SLOL) - -/*! @brief Set the SLOL field to a new value. */ -#define BW_RCM_SSRS0_SLOL(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS0, field SWDOG[5] (W1C) - * - * Indicates a reset has been caused by the watchdog timer timing out. This - * reset source can be blocked by disabling the watchdog. - * - * Values: - * - 0 - Reset not caused by watchdog timeout - * - 1 - Reset caused by watchdog timeout - */ -/*@{*/ -#define BP_RCM_SSRS0_SWDOG (5U) /*!< Bit position for RCM_SSRS0_SWDOG. */ -#define BM_RCM_SSRS0_SWDOG (0x20U) /*!< Bit mask for RCM_SSRS0_SWDOG. */ -#define BS_RCM_SSRS0_SWDOG (1U) /*!< Bit field size in bits for RCM_SSRS0_SWDOG. */ - -/*! @brief Read current value of the RCM_SSRS0_SWDOG field. */ -#define BR_RCM_SSRS0_SWDOG(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWDOG)) - -/*! @brief Format value for bitfield RCM_SSRS0_SWDOG. */ -#define BF_RCM_SSRS0_SWDOG(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SWDOG) & BM_RCM_SSRS0_SWDOG) - -/*! @brief Set the SWDOG field to a new value. */ -#define BW_RCM_SSRS0_SWDOG(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SWDOG) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS0, field SPIN[6] (W1C) - * - * Indicates a reset has been caused by an active-low level on the external - * RESET pin. - * - * Values: - * - 0 - Reset not caused by external reset pin - * - 1 - Reset caused by external reset pin - */ -/*@{*/ -#define BP_RCM_SSRS0_SPIN (6U) /*!< Bit position for RCM_SSRS0_SPIN. */ -#define BM_RCM_SSRS0_SPIN (0x40U) /*!< Bit mask for RCM_SSRS0_SPIN. */ -#define BS_RCM_SSRS0_SPIN (1U) /*!< Bit field size in bits for RCM_SSRS0_SPIN. */ - -/*! @brief Read current value of the RCM_SSRS0_SPIN field. */ -#define BR_RCM_SSRS0_SPIN(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPIN)) - -/*! @brief Format value for bitfield RCM_SSRS0_SPIN. */ -#define BF_RCM_SSRS0_SPIN(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SPIN) & BM_RCM_SSRS0_SPIN) - -/*! @brief Set the SPIN field to a new value. */ -#define BW_RCM_SSRS0_SPIN(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPIN) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS0, field SPOR[7] (W1C) - * - * Indicates a reset has been caused by the power-on detection logic. Because - * the internal supply voltage was ramping up at the time, the low-voltage reset - * (LVD) status bit is also set to indicate that the reset occurred while the - * internal supply was below the LVD threshold. - * - * Values: - * - 0 - Reset not caused by POR - * - 1 - Reset caused by POR - */ -/*@{*/ -#define BP_RCM_SSRS0_SPOR (7U) /*!< Bit position for RCM_SSRS0_SPOR. */ -#define BM_RCM_SSRS0_SPOR (0x80U) /*!< Bit mask for RCM_SSRS0_SPOR. */ -#define BS_RCM_SSRS0_SPOR (1U) /*!< Bit field size in bits for RCM_SSRS0_SPOR. */ - -/*! @brief Read current value of the RCM_SSRS0_SPOR field. */ -#define BR_RCM_SSRS0_SPOR(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPOR)) - -/*! @brief Format value for bitfield RCM_SSRS0_SPOR. */ -#define BF_RCM_SSRS0_SPOR(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SPOR) & BM_RCM_SSRS0_SPOR) - -/*! @brief Set the SPOR field to a new value. */ -#define BW_RCM_SSRS0_SPOR(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SPOR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_SSRS1 - Sticky System Reset Status Register 1 - ******************************************************************************/ - -/*! - * @brief HW_RCM_SSRS1 - Sticky System Reset Status Register 1 (RW) - * - * Reset value: 0x00U - * - * This register includes status flags to indicate all reset sources since the - * last POR, LVD or VLLS Wakeup that have not been cleared by software. Software - * can clear the status flags by writing a logic one to a flag. - */ -typedef union _hw_rcm_ssrs1 -{ - uint8_t U; - struct _hw_rcm_ssrs1_bitfields - { - uint8_t SJTAG : 1; /*!< [0] Sticky JTAG Generated Reset */ - uint8_t SLOCKUP : 1; /*!< [1] Sticky Core Lockup */ - uint8_t SSW : 1; /*!< [2] Sticky Software */ - uint8_t SMDM_AP : 1; /*!< [3] Sticky MDM-AP System Reset Request */ - uint8_t SEZPT : 1; /*!< [4] Sticky EzPort Reset */ - uint8_t SSACKERR : 1; /*!< [5] Sticky Stop Mode Acknowledge Error - * Reset */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_rcm_ssrs1_t; - -/*! - * @name Constants and macros for entire RCM_SSRS1 register - */ -/*@{*/ -#define HW_RCM_SSRS1_ADDR(x) ((x) + 0x9U) - -#define HW_RCM_SSRS1(x) (*(__IO hw_rcm_ssrs1_t *) HW_RCM_SSRS1_ADDR(x)) -#define HW_RCM_SSRS1_RD(x) (HW_RCM_SSRS1(x).U) -#define HW_RCM_SSRS1_WR(x, v) (HW_RCM_SSRS1(x).U = (v)) -#define HW_RCM_SSRS1_SET(x, v) (HW_RCM_SSRS1_WR(x, HW_RCM_SSRS1_RD(x) | (v))) -#define HW_RCM_SSRS1_CLR(x, v) (HW_RCM_SSRS1_WR(x, HW_RCM_SSRS1_RD(x) & ~(v))) -#define HW_RCM_SSRS1_TOG(x, v) (HW_RCM_SSRS1_WR(x, HW_RCM_SSRS1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RCM_SSRS1 bitfields - */ - -/*! - * @name Register RCM_SSRS1, field SJTAG[0] (W1C) - * - * Indicates a reset has been caused by JTAG selection of certain IR codes: - * EZPORT, EXTEST, HIGHZ, and CLAMP. - * - * Values: - * - 0 - Reset not caused by JTAG - * - 1 - Reset caused by JTAG - */ -/*@{*/ -#define BP_RCM_SSRS1_SJTAG (0U) /*!< Bit position for RCM_SSRS1_SJTAG. */ -#define BM_RCM_SSRS1_SJTAG (0x01U) /*!< Bit mask for RCM_SSRS1_SJTAG. */ -#define BS_RCM_SSRS1_SJTAG (1U) /*!< Bit field size in bits for RCM_SSRS1_SJTAG. */ - -/*! @brief Read current value of the RCM_SSRS1_SJTAG field. */ -#define BR_RCM_SSRS1_SJTAG(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SJTAG)) - -/*! @brief Format value for bitfield RCM_SSRS1_SJTAG. */ -#define BF_RCM_SSRS1_SJTAG(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SJTAG) & BM_RCM_SSRS1_SJTAG) - -/*! @brief Set the SJTAG field to a new value. */ -#define BW_RCM_SSRS1_SJTAG(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SJTAG) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS1, field SLOCKUP[1] (W1C) - * - * Indicates a reset has been caused by the ARM core indication of a LOCKUP - * event. - * - * Values: - * - 0 - Reset not caused by core LOCKUP event - * - 1 - Reset caused by core LOCKUP event - */ -/*@{*/ -#define BP_RCM_SSRS1_SLOCKUP (1U) /*!< Bit position for RCM_SSRS1_SLOCKUP. */ -#define BM_RCM_SSRS1_SLOCKUP (0x02U) /*!< Bit mask for RCM_SSRS1_SLOCKUP. */ -#define BS_RCM_SSRS1_SLOCKUP (1U) /*!< Bit field size in bits for RCM_SSRS1_SLOCKUP. */ - -/*! @brief Read current value of the RCM_SSRS1_SLOCKUP field. */ -#define BR_RCM_SSRS1_SLOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SLOCKUP)) - -/*! @brief Format value for bitfield RCM_SSRS1_SLOCKUP. */ -#define BF_RCM_SSRS1_SLOCKUP(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SLOCKUP) & BM_RCM_SSRS1_SLOCKUP) - -/*! @brief Set the SLOCKUP field to a new value. */ -#define BW_RCM_SSRS1_SLOCKUP(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SLOCKUP) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS1, field SSW[2] (W1C) - * - * Indicates a reset has been caused by software setting of SYSRESETREQ bit in - * Application Interrupt and Reset Control Register in the ARM core. - * - * Values: - * - 0 - Reset not caused by software setting of SYSRESETREQ bit - * - 1 - Reset caused by software setting of SYSRESETREQ bit - */ -/*@{*/ -#define BP_RCM_SSRS1_SSW (2U) /*!< Bit position for RCM_SSRS1_SSW. */ -#define BM_RCM_SSRS1_SSW (0x04U) /*!< Bit mask for RCM_SSRS1_SSW. */ -#define BS_RCM_SSRS1_SSW (1U) /*!< Bit field size in bits for RCM_SSRS1_SSW. */ - -/*! @brief Read current value of the RCM_SSRS1_SSW field. */ -#define BR_RCM_SSRS1_SSW(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSW)) - -/*! @brief Format value for bitfield RCM_SSRS1_SSW. */ -#define BF_RCM_SSRS1_SSW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SSW) & BM_RCM_SSRS1_SSW) - -/*! @brief Set the SSW field to a new value. */ -#define BW_RCM_SSRS1_SSW(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSW) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS1, field SMDM_AP[3] (W1C) - * - * Indicates a reset has been caused by the host debugger system setting of the - * System Reset Request bit in the MDM-AP Control Register. - * - * Values: - * - 0 - Reset not caused by host debugger system setting of the System Reset - * Request bit - * - 1 - Reset caused by host debugger system setting of the System Reset - * Request bit - */ -/*@{*/ -#define BP_RCM_SSRS1_SMDM_AP (3U) /*!< Bit position for RCM_SSRS1_SMDM_AP. */ -#define BM_RCM_SSRS1_SMDM_AP (0x08U) /*!< Bit mask for RCM_SSRS1_SMDM_AP. */ -#define BS_RCM_SSRS1_SMDM_AP (1U) /*!< Bit field size in bits for RCM_SSRS1_SMDM_AP. */ - -/*! @brief Read current value of the RCM_SSRS1_SMDM_AP field. */ -#define BR_RCM_SSRS1_SMDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SMDM_AP)) - -/*! @brief Format value for bitfield RCM_SSRS1_SMDM_AP. */ -#define BF_RCM_SSRS1_SMDM_AP(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SMDM_AP) & BM_RCM_SSRS1_SMDM_AP) - -/*! @brief Set the SMDM_AP field to a new value. */ -#define BW_RCM_SSRS1_SMDM_AP(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SMDM_AP) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS1, field SEZPT[4] (W1C) - * - * Indicates a reset has been caused by EzPort receiving the RESET command while - * the device is in EzPort mode. - * - * Values: - * - 0 - Reset not caused by EzPort receiving the RESET command while the device - * is in EzPort mode - * - 1 - Reset caused by EzPort receiving the RESET command while the device is - * in EzPort mode - */ -/*@{*/ -#define BP_RCM_SSRS1_SEZPT (4U) /*!< Bit position for RCM_SSRS1_SEZPT. */ -#define BM_RCM_SSRS1_SEZPT (0x10U) /*!< Bit mask for RCM_SSRS1_SEZPT. */ -#define BS_RCM_SSRS1_SEZPT (1U) /*!< Bit field size in bits for RCM_SSRS1_SEZPT. */ - -/*! @brief Read current value of the RCM_SSRS1_SEZPT field. */ -#define BR_RCM_SSRS1_SEZPT(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SEZPT)) - -/*! @brief Format value for bitfield RCM_SSRS1_SEZPT. */ -#define BF_RCM_SSRS1_SEZPT(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SEZPT) & BM_RCM_SSRS1_SEZPT) - -/*! @brief Set the SEZPT field to a new value. */ -#define BW_RCM_SSRS1_SEZPT(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SEZPT) = (v)) -/*@}*/ - -/*! - * @name Register RCM_SSRS1, field SSACKERR[5] (W1C) - * - * Indicates that after an attempt to enter Stop mode, a reset has been caused - * by a failure of one or more peripherals to acknowledge within approximately one - * second to enter stop mode. - * - * Values: - * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter - * stop mode - * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop - * mode - */ -/*@{*/ -#define BP_RCM_SSRS1_SSACKERR (5U) /*!< Bit position for RCM_SSRS1_SSACKERR. */ -#define BM_RCM_SSRS1_SSACKERR (0x20U) /*!< Bit mask for RCM_SSRS1_SSACKERR. */ -#define BS_RCM_SSRS1_SSACKERR (1U) /*!< Bit field size in bits for RCM_SSRS1_SSACKERR. */ - -/*! @brief Read current value of the RCM_SSRS1_SSACKERR field. */ -#define BR_RCM_SSRS1_SSACKERR(x) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSACKERR)) - -/*! @brief Format value for bitfield RCM_SSRS1_SSACKERR. */ -#define BF_RCM_SSRS1_SSACKERR(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS1_SSACKERR) & BM_RCM_SSRS1_SSACKERR) - -/*! @brief Set the SSACKERR field to a new value. */ -#define BW_RCM_SSRS1_SSACKERR(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS1_ADDR(x), BP_RCM_SSRS1_SSACKERR) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_rcm_t - module struct - ******************************************************************************/ -/*! - * @brief All RCM module registers. - */ -#pragma pack(1) -typedef struct _hw_rcm -{ - __I hw_rcm_srs0_t SRS0; /*!< [0x0] System Reset Status Register 0 */ - __I hw_rcm_srs1_t SRS1; /*!< [0x1] System Reset Status Register 1 */ - uint8_t _reserved0[2]; - __IO hw_rcm_rpfc_t RPFC; /*!< [0x4] Reset Pin Filter Control register */ - __IO hw_rcm_rpfw_t RPFW; /*!< [0x5] Reset Pin Filter Width register */ - uint8_t _reserved1[1]; - __I hw_rcm_mr_t MR; /*!< [0x7] Mode Register */ - __IO hw_rcm_ssrs0_t SSRS0; /*!< [0x8] Sticky System Reset Status Register 0 */ - __IO hw_rcm_ssrs1_t SSRS1; /*!< [0x9] Sticky System Reset Status Register 1 */ -} hw_rcm_t; -#pragma pack() - -/*! @brief Macro to access all RCM registers. */ -/*! @param x RCM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RCM(RCM_BASE). */ -#define HW_RCM(x) (*(hw_rcm_t *)(x)) - -#endif /* __HW_RCM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h deleted file mode 100644 index bcc4c095b0c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h +++ /dev/null @@ -1,239 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RFSYS_REGISTERS_H__ -#define __HW_RFSYS_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 RFSYS - * - * System register file - * - * Registers defined in this header file: - * - HW_RFSYS_REGn - Register file register - * - * - hw_rfsys_t - Struct containing all module registers. - */ - -#define HW_RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */ - -/******************************************************************************* - * HW_RFSYS_REGn - Register file register - ******************************************************************************/ - -/*! - * @brief HW_RFSYS_REGn - Register file register (RW) - * - * Reset value: 0x00000000U - * - * Each register can be accessed as 8-, 16-, or 32-bits. - */ -typedef union _hw_rfsys_regn -{ - uint32_t U; - struct _hw_rfsys_regn_bitfields - { - uint32_t LL : 8; /*!< [7:0] */ - uint32_t LH : 8; /*!< [15:8] */ - uint32_t HL : 8; /*!< [23:16] */ - uint32_t HH : 8; /*!< [31:24] */ - } B; -} hw_rfsys_regn_t; - -/*! - * @name Constants and macros for entire RFSYS_REGn register - */ -/*@{*/ -#define HW_RFSYS_REGn_COUNT (8U) - -#define HW_RFSYS_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n))) - -#define HW_RFSYS_REGn(x, n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(x, n)) -#define HW_RFSYS_REGn_RD(x, n) (HW_RFSYS_REGn(x, n).U) -#define HW_RFSYS_REGn_WR(x, n, v) (HW_RFSYS_REGn(x, n).U = (v)) -#define HW_RFSYS_REGn_SET(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) | (v))) -#define HW_RFSYS_REGn_CLR(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) & ~(v))) -#define HW_RFSYS_REGn_TOG(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RFSYS_REGn bitfields - */ - -/*! - * @name Register RFSYS_REGn, field LL[7:0] (RW) - * - * Low lower byte - */ -/*@{*/ -#define BP_RFSYS_REGn_LL (0U) /*!< Bit position for RFSYS_REGn_LL. */ -#define BM_RFSYS_REGn_LL (0x000000FFU) /*!< Bit mask for RFSYS_REGn_LL. */ -#define BS_RFSYS_REGn_LL (8U) /*!< Bit field size in bits for RFSYS_REGn_LL. */ - -/*! @brief Read current value of the RFSYS_REGn_LL field. */ -#define BR_RFSYS_REGn_LL(x, n) (HW_RFSYS_REGn(x, n).B.LL) - -/*! @brief Format value for bitfield RFSYS_REGn_LL. */ -#define BF_RFSYS_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LL) & BM_RFSYS_REGn_LL) - -/*! @brief Set the LL field to a new value. */ -#define BW_RFSYS_REGn_LL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v))) -/*@}*/ - -/*! - * @name Register RFSYS_REGn, field LH[15:8] (RW) - * - * Low higher byte - */ -/*@{*/ -#define BP_RFSYS_REGn_LH (8U) /*!< Bit position for RFSYS_REGn_LH. */ -#define BM_RFSYS_REGn_LH (0x0000FF00U) /*!< Bit mask for RFSYS_REGn_LH. */ -#define BS_RFSYS_REGn_LH (8U) /*!< Bit field size in bits for RFSYS_REGn_LH. */ - -/*! @brief Read current value of the RFSYS_REGn_LH field. */ -#define BR_RFSYS_REGn_LH(x, n) (HW_RFSYS_REGn(x, n).B.LH) - -/*! @brief Format value for bitfield RFSYS_REGn_LH. */ -#define BF_RFSYS_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LH) & BM_RFSYS_REGn_LH) - -/*! @brief Set the LH field to a new value. */ -#define BW_RFSYS_REGn_LH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v))) -/*@}*/ - -/*! - * @name Register RFSYS_REGn, field HL[23:16] (RW) - * - * High lower byte - */ -/*@{*/ -#define BP_RFSYS_REGn_HL (16U) /*!< Bit position for RFSYS_REGn_HL. */ -#define BM_RFSYS_REGn_HL (0x00FF0000U) /*!< Bit mask for RFSYS_REGn_HL. */ -#define BS_RFSYS_REGn_HL (8U) /*!< Bit field size in bits for RFSYS_REGn_HL. */ - -/*! @brief Read current value of the RFSYS_REGn_HL field. */ -#define BR_RFSYS_REGn_HL(x, n) (HW_RFSYS_REGn(x, n).B.HL) - -/*! @brief Format value for bitfield RFSYS_REGn_HL. */ -#define BF_RFSYS_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HL) & BM_RFSYS_REGn_HL) - -/*! @brief Set the HL field to a new value. */ -#define BW_RFSYS_REGn_HL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v))) -/*@}*/ - -/*! - * @name Register RFSYS_REGn, field HH[31:24] (RW) - * - * High higher byte - */ -/*@{*/ -#define BP_RFSYS_REGn_HH (24U) /*!< Bit position for RFSYS_REGn_HH. */ -#define BM_RFSYS_REGn_HH (0xFF000000U) /*!< Bit mask for RFSYS_REGn_HH. */ -#define BS_RFSYS_REGn_HH (8U) /*!< Bit field size in bits for RFSYS_REGn_HH. */ - -/*! @brief Read current value of the RFSYS_REGn_HH field. */ -#define BR_RFSYS_REGn_HH(x, n) (HW_RFSYS_REGn(x, n).B.HH) - -/*! @brief Format value for bitfield RFSYS_REGn_HH. */ -#define BF_RFSYS_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HH) & BM_RFSYS_REGn_HH) - -/*! @brief Set the HH field to a new value. */ -#define BW_RFSYS_REGn_HH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v))) -/*@}*/ - -/******************************************************************************* - * hw_rfsys_t - module struct - ******************************************************************************/ -/*! - * @brief All RFSYS module registers. - */ -#pragma pack(1) -typedef struct _hw_rfsys -{ - __IO hw_rfsys_regn_t REGn[8]; /*!< [0x0] Register file register */ -} hw_rfsys_t; -#pragma pack() - -/*! @brief Macro to access all RFSYS registers. */ -/*! @param x RFSYS module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RFSYS(RFSYS_BASE). */ -#define HW_RFSYS(x) (*(hw_rfsys_t *)(x)) - -#endif /* __HW_RFSYS_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h deleted file mode 100644 index 6b2fc876f19..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h +++ /dev/null @@ -1,239 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RFVBAT_REGISTERS_H__ -#define __HW_RFVBAT_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 RFVBAT - * - * VBAT register file - * - * Registers defined in this header file: - * - HW_RFVBAT_REGn - VBAT register file register - * - * - hw_rfvbat_t - Struct containing all module registers. - */ - -#define HW_RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */ - -/******************************************************************************* - * HW_RFVBAT_REGn - VBAT register file register - ******************************************************************************/ - -/*! - * @brief HW_RFVBAT_REGn - VBAT register file register (RW) - * - * Reset value: 0x00000000U - * - * Each register can be accessed as 8-, 16-, or 32-bits. - */ -typedef union _hw_rfvbat_regn -{ - uint32_t U; - struct _hw_rfvbat_regn_bitfields - { - uint32_t LL : 8; /*!< [7:0] */ - uint32_t LH : 8; /*!< [15:8] */ - uint32_t HL : 8; /*!< [23:16] */ - uint32_t HH : 8; /*!< [31:24] */ - } B; -} hw_rfvbat_regn_t; - -/*! - * @name Constants and macros for entire RFVBAT_REGn register - */ -/*@{*/ -#define HW_RFVBAT_REGn_COUNT (8U) - -#define HW_RFVBAT_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n))) - -#define HW_RFVBAT_REGn(x, n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(x, n)) -#define HW_RFVBAT_REGn_RD(x, n) (HW_RFVBAT_REGn(x, n).U) -#define HW_RFVBAT_REGn_WR(x, n, v) (HW_RFVBAT_REGn(x, n).U = (v)) -#define HW_RFVBAT_REGn_SET(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) | (v))) -#define HW_RFVBAT_REGn_CLR(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) & ~(v))) -#define HW_RFVBAT_REGn_TOG(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RFVBAT_REGn bitfields - */ - -/*! - * @name Register RFVBAT_REGn, field LL[7:0] (RW) - * - * Low lower byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_LL (0U) /*!< Bit position for RFVBAT_REGn_LL. */ -#define BM_RFVBAT_REGn_LL (0x000000FFU) /*!< Bit mask for RFVBAT_REGn_LL. */ -#define BS_RFVBAT_REGn_LL (8U) /*!< Bit field size in bits for RFVBAT_REGn_LL. */ - -/*! @brief Read current value of the RFVBAT_REGn_LL field. */ -#define BR_RFVBAT_REGn_LL(x, n) (HW_RFVBAT_REGn(x, n).B.LL) - -/*! @brief Format value for bitfield RFVBAT_REGn_LL. */ -#define BF_RFVBAT_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LL) & BM_RFVBAT_REGn_LL) - -/*! @brief Set the LL field to a new value. */ -#define BW_RFVBAT_REGn_LL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v))) -/*@}*/ - -/*! - * @name Register RFVBAT_REGn, field LH[15:8] (RW) - * - * Low higher byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_LH (8U) /*!< Bit position for RFVBAT_REGn_LH. */ -#define BM_RFVBAT_REGn_LH (0x0000FF00U) /*!< Bit mask for RFVBAT_REGn_LH. */ -#define BS_RFVBAT_REGn_LH (8U) /*!< Bit field size in bits for RFVBAT_REGn_LH. */ - -/*! @brief Read current value of the RFVBAT_REGn_LH field. */ -#define BR_RFVBAT_REGn_LH(x, n) (HW_RFVBAT_REGn(x, n).B.LH) - -/*! @brief Format value for bitfield RFVBAT_REGn_LH. */ -#define BF_RFVBAT_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LH) & BM_RFVBAT_REGn_LH) - -/*! @brief Set the LH field to a new value. */ -#define BW_RFVBAT_REGn_LH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v))) -/*@}*/ - -/*! - * @name Register RFVBAT_REGn, field HL[23:16] (RW) - * - * High lower byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_HL (16U) /*!< Bit position for RFVBAT_REGn_HL. */ -#define BM_RFVBAT_REGn_HL (0x00FF0000U) /*!< Bit mask for RFVBAT_REGn_HL. */ -#define BS_RFVBAT_REGn_HL (8U) /*!< Bit field size in bits for RFVBAT_REGn_HL. */ - -/*! @brief Read current value of the RFVBAT_REGn_HL field. */ -#define BR_RFVBAT_REGn_HL(x, n) (HW_RFVBAT_REGn(x, n).B.HL) - -/*! @brief Format value for bitfield RFVBAT_REGn_HL. */ -#define BF_RFVBAT_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HL) & BM_RFVBAT_REGn_HL) - -/*! @brief Set the HL field to a new value. */ -#define BW_RFVBAT_REGn_HL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v))) -/*@}*/ - -/*! - * @name Register RFVBAT_REGn, field HH[31:24] (RW) - * - * High higher byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_HH (24U) /*!< Bit position for RFVBAT_REGn_HH. */ -#define BM_RFVBAT_REGn_HH (0xFF000000U) /*!< Bit mask for RFVBAT_REGn_HH. */ -#define BS_RFVBAT_REGn_HH (8U) /*!< Bit field size in bits for RFVBAT_REGn_HH. */ - -/*! @brief Read current value of the RFVBAT_REGn_HH field. */ -#define BR_RFVBAT_REGn_HH(x, n) (HW_RFVBAT_REGn(x, n).B.HH) - -/*! @brief Format value for bitfield RFVBAT_REGn_HH. */ -#define BF_RFVBAT_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HH) & BM_RFVBAT_REGn_HH) - -/*! @brief Set the HH field to a new value. */ -#define BW_RFVBAT_REGn_HH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v))) -/*@}*/ - -/******************************************************************************* - * hw_rfvbat_t - module struct - ******************************************************************************/ -/*! - * @brief All RFVBAT module registers. - */ -#pragma pack(1) -typedef struct _hw_rfvbat -{ - __IO hw_rfvbat_regn_t REGn[8]; /*!< [0x0] VBAT register file register */ -} hw_rfvbat_t; -#pragma pack() - -/*! @brief Macro to access all RFVBAT registers. */ -/*! @param x RFVBAT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RFVBAT(RFVBAT_BASE). */ -#define HW_RFVBAT(x) (*(hw_rfvbat_t *)(x)) - -#endif /* __HW_RFVBAT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h deleted file mode 100644 index a0b13c986cb..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h +++ /dev/null @@ -1,587 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RNG_REGISTERS_H__ -#define __HW_RNG_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 RNG - * - * Random Number Generator Accelerator - * - * Registers defined in this header file: - * - HW_RNG_CR - RNGA Control Register - * - HW_RNG_SR - RNGA Status Register - * - HW_RNG_ER - RNGA Entropy Register - * - HW_RNG_OR - RNGA Output Register - * - * - hw_rng_t - Struct containing all module registers. - */ - -#define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */ - -/******************************************************************************* - * HW_RNG_CR - RNGA Control Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_CR - RNGA Control Register (RW) - * - * Reset value: 0x00000000U - * - * Controls the operation of RNGA. - */ -typedef union _hw_rng_cr -{ - uint32_t U; - struct _hw_rng_cr_bitfields - { - uint32_t GO : 1; /*!< [0] Go */ - uint32_t HA : 1; /*!< [1] High Assurance */ - uint32_t INTM : 1; /*!< [2] Interrupt Mask */ - uint32_t CLRI : 1; /*!< [3] Clear Interrupt */ - uint32_t SLP : 1; /*!< [4] Sleep */ - uint32_t RESERVED0 : 27; /*!< [31:5] */ - } B; -} hw_rng_cr_t; - -/*! - * @name Constants and macros for entire RNG_CR register - */ -/*@{*/ -#define HW_RNG_CR_ADDR(x) ((x) + 0x0U) - -#define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x)) -#define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U) -#define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v)) -#define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v))) -#define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v))) -#define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RNG_CR bitfields - */ - -/*! - * @name Register RNG_CR, field GO[0] (RW) - * - * Specifies whether random-data generation and loading (into OR[RANDOUT]) is - * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading - * OR[RANDOUT] with data. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */ -#define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */ -#define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */ - -/*! @brief Read current value of the RNG_CR_GO field. */ -#define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO)) - -/*! @brief Format value for bitfield RNG_CR_GO. */ -#define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO) - -/*! @brief Set the GO field to a new value. */ -#define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field HA[1] (RW) - * - * Enables notification of security violations (via SR[SECV]). A security - * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky. - * After enabling notification of security violations, you must reset RNGA to - * disable them again. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */ -#define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */ -#define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */ - -/*! @brief Read current value of the RNG_CR_HA field. */ -#define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA)) - -/*! @brief Format value for bitfield RNG_CR_HA. */ -#define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA) - -/*! @brief Set the HA field to a new value. */ -#define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field INTM[2] (RW) - * - * Masks the triggering of an error interrupt to the interrupt controller when - * an OR underflow condition occurs. An OR underflow condition occurs when you - * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description. - * - * Values: - * - 0 - Not masked - * - 1 - Masked - */ -/*@{*/ -#define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */ -#define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */ -#define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */ - -/*! @brief Read current value of the RNG_CR_INTM field. */ -#define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM)) - -/*! @brief Format value for bitfield RNG_CR_INTM. */ -#define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM) - -/*! @brief Set the INTM field to a new value. */ -#define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field CLRI[3] (WORZ) - * - * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]). - * - * Values: - * - 0 - Do not clear the interrupt. - * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets - * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0. - */ -/*@{*/ -#define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */ -#define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */ -#define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */ - -/*! @brief Format value for bitfield RNG_CR_CLRI. */ -#define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI) - -/*! @brief Set the CLRI field to a new value. */ -#define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field SLP[4] (RW) - * - * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep - * mode by asserting the DOZE signal. - * - * Values: - * - 0 - Normal mode - * - 1 - Sleep (low-power) mode - */ -/*@{*/ -#define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */ -#define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */ -#define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */ - -/*! @brief Read current value of the RNG_CR_SLP field. */ -#define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP)) - -/*! @brief Format value for bitfield RNG_CR_SLP. */ -#define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP) - -/*! @brief Set the SLP field to a new value. */ -#define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RNG_SR - RNGA Status Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_SR - RNGA Status Register (RO) - * - * Reset value: 0x00010000U - * - * Indicates the status of RNGA. This register is read-only. - */ -typedef union _hw_rng_sr -{ - uint32_t U; - struct _hw_rng_sr_bitfields - { - uint32_t SECV : 1; /*!< [0] Security Violation */ - uint32_t LRS : 1; /*!< [1] Last Read Status */ - uint32_t ORU : 1; /*!< [2] Output Register Underflow */ - uint32_t ERRI : 1; /*!< [3] Error Interrupt */ - uint32_t SLP : 1; /*!< [4] Sleep */ - uint32_t RESERVED0 : 3; /*!< [7:5] */ - uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */ - uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ - } B; -} hw_rng_sr_t; - -/*! - * @name Constants and macros for entire RNG_SR register - */ -/*@{*/ -#define HW_RNG_SR_ADDR(x) ((x) + 0x4U) - -#define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x)) -#define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U) -/*@}*/ - -/* - * Constants & macros for individual RNG_SR bitfields - */ - -/*! - * @name Register RNG_SR, field SECV[0] (RO) - * - * Used only when high assurance is enabled (CR[HA]). Indicates that a security - * violation has occurred.This field is sticky. To clear SR[SECV], you must reset - * RNGA. - * - * Values: - * - 0 - No security violation - * - 1 - Security violation - */ -/*@{*/ -#define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */ -#define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */ -#define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */ - -/*! @brief Read current value of the RNG_SR_SECV field. */ -#define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV)) -/*@}*/ - -/*! - * @name Register RNG_SR, field LRS[1] (RO) - * - * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow - * condition, regardless of whether the error interrupt is masked (CR[INTM]). An - * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. - * After you read this register, RNGA writes 0 to this field. - * - * Values: - * - 0 - No underflow - * - 1 - Underflow - */ -/*@{*/ -#define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */ -#define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */ -#define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */ - -/*! @brief Read current value of the RNG_SR_LRS field. */ -#define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS)) -/*@}*/ - -/*! - * @name Register RNG_SR, field ORU[2] (RO) - * - * Indicates whether an OR underflow condition has occurred since you last read - * this register (SR) or RNGA was reset, regardless of whether the error - * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read - * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this - * field. - * - * Values: - * - 0 - No underflow - * - 1 - Underflow - */ -/*@{*/ -#define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */ -#define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */ -#define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */ - -/*! @brief Read current value of the RNG_SR_ORU field. */ -#define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU)) -/*@}*/ - -/*! - * @name Register RNG_SR, field ERRI[3] (RO) - * - * Indicates whether an OR underflow condition has occurred since you last - * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the - * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when - * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt - * indicator (via CR[CLRI]), RNGA writes 0 to this field. - * - * Values: - * - 0 - No underflow - * - 1 - Underflow - */ -/*@{*/ -#define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */ -#define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */ -#define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */ - -/*! @brief Read current value of the RNG_SR_ERRI field. */ -#define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI)) -/*@}*/ - -/*! - * @name Register RNG_SR, field SLP[4] (RO) - * - * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep - * mode by asserting the DOZE signal. - * - * Values: - * - 0 - Normal mode - * - 1 - Sleep (low-power) mode - */ -/*@{*/ -#define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */ -#define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */ -#define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */ - -/*! @brief Read current value of the RNG_SR_SLP field. */ -#define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP)) -/*@}*/ - -/*! - * @name Register RNG_SR, field OREG_LVL[15:8] (RO) - * - * Indicates the number of random-data words that are in OR[RANDOUT], which - * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] - * is not 0, then the contents of a random number contained in OR[RANDOUT] are - * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. - * - * Values: - * - 0 - No words (empty) - * - 1 - One word (valid) - */ -/*@{*/ -#define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */ -#define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */ -#define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */ - -/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ -#define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL) -/*@}*/ - -/*! - * @name Register RNG_SR, field OREG_SIZE[23:16] (RO) - * - * Indicates the size of the Output (OR) register in terms of the number of - * 32-bit random-data words it can hold. - * - * Values: - * - 1 - One word (this value is fixed) - */ -/*@{*/ -#define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */ -#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */ -#define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */ - -/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */ -#define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE) -/*@}*/ - -/******************************************************************************* - * HW_RNG_ER - RNGA Entropy Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_ER - RNGA Entropy Register (WORZ) - * - * Reset value: 0x00000000U - * - * Specifies an entropy value that RNGA uses in addition to its ring oscillators - * to seed its pseudorandom algorithm. This is a write-only register; reads - * return all zeros. - */ -typedef union _hw_rng_er -{ - uint32_t U; - struct _hw_rng_er_bitfields - { - uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */ - } B; -} hw_rng_er_t; - -/*! - * @name Constants and macros for entire RNG_ER register - */ -/*@{*/ -#define HW_RNG_ER_ADDR(x) ((x) + 0x8U) - -#define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x)) -#define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U) -#define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual RNG_ER bitfields - */ - -/*! - * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ) - * - * Specifies an entropy value that RNGA uses in addition to its ring oscillators - * to seed its pseudorandom algorithm.Specifying a value for this field is - * optional but recommended. You can write to this field at any time during operation. - */ -/*@{*/ -#define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */ -#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */ -#define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */ - -/*! @brief Format value for bitfield RNG_ER_EXT_ENT. */ -#define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT) - -/*! @brief Set the EXT_ENT field to a new value. */ -#define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_RNG_OR - RNGA Output Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_OR - RNGA Output Register (RO) - * - * Reset value: 0x00000000U - * - * Stores a random-data word generated by RNGA. - */ -typedef union _hw_rng_or -{ - uint32_t U; - struct _hw_rng_or_bitfields - { - uint32_t RANDOUT : 32; /*!< [31:0] Random Output */ - } B; -} hw_rng_or_t; - -/*! - * @name Constants and macros for entire RNG_OR register - */ -/*@{*/ -#define HW_RNG_OR_ADDR(x) ((x) + 0xCU) - -#define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x)) -#define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U) -/*@}*/ - -/* - * Constants & macros for individual RNG_OR bitfields - */ - -/*! - * @name Register RNG_OR, field RANDOUT[31:0] (RO) - * - * Stores a random-data word generated by RNGA. This is a read-only field.Before - * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). - * - * Values: - * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is - * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error - * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt - * request to the interrupt controller). - */ -/*@{*/ -#define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */ -#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */ -#define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */ - -/*! @brief Read current value of the RNG_OR_RANDOUT field. */ -#define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U) -/*@}*/ - -/******************************************************************************* - * hw_rng_t - module struct - ******************************************************************************/ -/*! - * @brief All RNG module registers. - */ -#pragma pack(1) -typedef struct _hw_rng -{ - __IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */ - __I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */ - __O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */ - __I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */ -} hw_rng_t; -#pragma pack() - -/*! @brief Macro to access all RNG registers. */ -/*! @param x RNG module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RNG(RNG_BASE). */ -#define HW_RNG(x) (*(hw_rng_t *)(x)) - -#endif /* __HW_RNG_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h deleted file mode 100644 index 4afd6616dcc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h +++ /dev/null @@ -1,1659 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RTC_REGISTERS_H__ -#define __HW_RTC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 RTC - * - * Secure Real Time Clock - * - * Registers defined in this header file: - * - HW_RTC_TSR - RTC Time Seconds Register - * - HW_RTC_TPR - RTC Time Prescaler Register - * - HW_RTC_TAR - RTC Time Alarm Register - * - HW_RTC_TCR - RTC Time Compensation Register - * - HW_RTC_CR - RTC Control Register - * - HW_RTC_SR - RTC Status Register - * - HW_RTC_LR - RTC Lock Register - * - HW_RTC_IER - RTC Interrupt Enable Register - * - HW_RTC_WAR - RTC Write Access Register - * - HW_RTC_RAR - RTC Read Access Register - * - * - hw_rtc_t - Struct containing all module registers. - */ - -#define HW_RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */ - -/******************************************************************************* - * HW_RTC_TSR - RTC Time Seconds Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TSR - RTC Time Seconds Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tsr -{ - uint32_t U; - struct _hw_rtc_tsr_bitfields - { - uint32_t TSR : 32; /*!< [31:0] Time Seconds Register */ - } B; -} hw_rtc_tsr_t; - -/*! - * @name Constants and macros for entire RTC_TSR register - */ -/*@{*/ -#define HW_RTC_TSR_ADDR(x) ((x) + 0x0U) - -#define HW_RTC_TSR(x) (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR(x)) -#define HW_RTC_TSR_RD(x) (HW_RTC_TSR(x).U) -#define HW_RTC_TSR_WR(x, v) (HW_RTC_TSR(x).U = (v)) -#define HW_RTC_TSR_SET(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) | (v))) -#define HW_RTC_TSR_CLR(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) & ~(v))) -#define HW_RTC_TSR_TOG(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TSR bitfields - */ - -/*! - * @name Register RTC_TSR, field TSR[31:0] (RW) - * - * When the time counter is enabled, the TSR is read only and increments once a - * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as - * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the - * TSR can be read or written. Writing to the TSR when the time counter is - * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is - * supported, but not recommended because TSR will read as zero when SR[TIF] or - * SR[TOF] are set (indicating the time is invalid). - */ -/*@{*/ -#define BP_RTC_TSR_TSR (0U) /*!< Bit position for RTC_TSR_TSR. */ -#define BM_RTC_TSR_TSR (0xFFFFFFFFU) /*!< Bit mask for RTC_TSR_TSR. */ -#define BS_RTC_TSR_TSR (32U) /*!< Bit field size in bits for RTC_TSR_TSR. */ - -/*! @brief Read current value of the RTC_TSR_TSR field. */ -#define BR_RTC_TSR_TSR(x) (HW_RTC_TSR(x).U) - -/*! @brief Format value for bitfield RTC_TSR_TSR. */ -#define BF_RTC_TSR_TSR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TSR_TSR) & BM_RTC_TSR_TSR) - -/*! @brief Set the TSR field to a new value. */ -#define BW_RTC_TSR_TSR(x, v) (HW_RTC_TSR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_TPR - RTC Time Prescaler Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tpr -{ - uint32_t U; - struct _hw_rtc_tpr_bitfields - { - uint32_t TPR : 16; /*!< [15:0] Time Prescaler Register */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_rtc_tpr_t; - -/*! - * @name Constants and macros for entire RTC_TPR register - */ -/*@{*/ -#define HW_RTC_TPR_ADDR(x) ((x) + 0x4U) - -#define HW_RTC_TPR(x) (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR(x)) -#define HW_RTC_TPR_RD(x) (HW_RTC_TPR(x).U) -#define HW_RTC_TPR_WR(x, v) (HW_RTC_TPR(x).U = (v)) -#define HW_RTC_TPR_SET(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) | (v))) -#define HW_RTC_TPR_CLR(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) & ~(v))) -#define HW_RTC_TPR_TOG(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TPR bitfields - */ - -/*! - * @name Register RTC_TPR, field TPR[15:0] (RW) - * - * When the time counter is enabled, the TPR is read only and increments every - * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or - * SR[TIF] are set. When the time counter is disabled, the TPR can be read or - * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one - * to a logic zero. - */ -/*@{*/ -#define BP_RTC_TPR_TPR (0U) /*!< Bit position for RTC_TPR_TPR. */ -#define BM_RTC_TPR_TPR (0x0000FFFFU) /*!< Bit mask for RTC_TPR_TPR. */ -#define BS_RTC_TPR_TPR (16U) /*!< Bit field size in bits for RTC_TPR_TPR. */ - -/*! @brief Read current value of the RTC_TPR_TPR field. */ -#define BR_RTC_TPR_TPR(x) (HW_RTC_TPR(x).B.TPR) - -/*! @brief Format value for bitfield RTC_TPR_TPR. */ -#define BF_RTC_TPR_TPR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TPR_TPR) & BM_RTC_TPR_TPR) - -/*! @brief Set the TPR field to a new value. */ -#define BW_RTC_TPR_TPR(x, v) (HW_RTC_TPR_WR(x, (HW_RTC_TPR_RD(x) & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v))) -/*@}*/ - -/******************************************************************************* - * HW_RTC_TAR - RTC Time Alarm Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TAR - RTC Time Alarm Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tar -{ - uint32_t U; - struct _hw_rtc_tar_bitfields - { - uint32_t TAR : 32; /*!< [31:0] Time Alarm Register */ - } B; -} hw_rtc_tar_t; - -/*! - * @name Constants and macros for entire RTC_TAR register - */ -/*@{*/ -#define HW_RTC_TAR_ADDR(x) ((x) + 0x8U) - -#define HW_RTC_TAR(x) (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR(x)) -#define HW_RTC_TAR_RD(x) (HW_RTC_TAR(x).U) -#define HW_RTC_TAR_WR(x, v) (HW_RTC_TAR(x).U = (v)) -#define HW_RTC_TAR_SET(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) | (v))) -#define HW_RTC_TAR_CLR(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) & ~(v))) -#define HW_RTC_TAR_TOG(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TAR bitfields - */ - -/*! - * @name Register RTC_TAR, field TAR[31:0] (RW) - * - * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] - * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the - * SR[TAF]. - */ -/*@{*/ -#define BP_RTC_TAR_TAR (0U) /*!< Bit position for RTC_TAR_TAR. */ -#define BM_RTC_TAR_TAR (0xFFFFFFFFU) /*!< Bit mask for RTC_TAR_TAR. */ -#define BS_RTC_TAR_TAR (32U) /*!< Bit field size in bits for RTC_TAR_TAR. */ - -/*! @brief Read current value of the RTC_TAR_TAR field. */ -#define BR_RTC_TAR_TAR(x) (HW_RTC_TAR(x).U) - -/*! @brief Format value for bitfield RTC_TAR_TAR. */ -#define BF_RTC_TAR_TAR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TAR_TAR) & BM_RTC_TAR_TAR) - -/*! @brief Set the TAR field to a new value. */ -#define BW_RTC_TAR_TAR(x, v) (HW_RTC_TAR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_TCR - RTC Time Compensation Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TCR - RTC Time Compensation Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tcr -{ - uint32_t U; - struct _hw_rtc_tcr_bitfields - { - uint32_t TCR : 8; /*!< [7:0] Time Compensation Register */ - uint32_t CIR : 8; /*!< [15:8] Compensation Interval Register */ - uint32_t TCV : 8; /*!< [23:16] Time Compensation Value */ - uint32_t CIC : 8; /*!< [31:24] Compensation Interval Counter */ - } B; -} hw_rtc_tcr_t; - -/*! - * @name Constants and macros for entire RTC_TCR register - */ -/*@{*/ -#define HW_RTC_TCR_ADDR(x) ((x) + 0xCU) - -#define HW_RTC_TCR(x) (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR(x)) -#define HW_RTC_TCR_RD(x) (HW_RTC_TCR(x).U) -#define HW_RTC_TCR_WR(x, v) (HW_RTC_TCR(x).U = (v)) -#define HW_RTC_TCR_SET(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) | (v))) -#define HW_RTC_TCR_CLR(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) & ~(v))) -#define HW_RTC_TCR_TOG(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TCR bitfields - */ - -/*! - * @name Register RTC_TCR, field TCR[7:0] (RW) - * - * Configures the number of 32.768 kHz clock cycles in each second. This - * register is double buffered and writes do not take affect until the end of the - * current compensation interval. - * - * Values: - * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles. - * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles. - * - 0 - Time Prescaler Register overflows every 32768 clock cycles. - * - 1 - Time Prescaler Register overflows every 32767 clock cycles. - * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles. - */ -/*@{*/ -#define BP_RTC_TCR_TCR (0U) /*!< Bit position for RTC_TCR_TCR. */ -#define BM_RTC_TCR_TCR (0x000000FFU) /*!< Bit mask for RTC_TCR_TCR. */ -#define BS_RTC_TCR_TCR (8U) /*!< Bit field size in bits for RTC_TCR_TCR. */ - -/*! @brief Read current value of the RTC_TCR_TCR field. */ -#define BR_RTC_TCR_TCR(x) (HW_RTC_TCR(x).B.TCR) - -/*! @brief Format value for bitfield RTC_TCR_TCR. */ -#define BF_RTC_TCR_TCR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_TCR) & BM_RTC_TCR_TCR) - -/*! @brief Set the TCR field to a new value. */ -#define BW_RTC_TCR_TCR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v))) -/*@}*/ - -/*! - * @name Register RTC_TCR, field CIR[15:8] (RW) - * - * Configures the compensation interval in seconds from 1 to 256 to control how - * frequently the TCR should adjust the number of 32.768 kHz cycles in each - * second. The value written should be one less than the number of seconds. For - * example, write zero to configure for a compensation interval of one second. This - * register is double buffered and writes do not take affect until the end of the - * current compensation interval. - */ -/*@{*/ -#define BP_RTC_TCR_CIR (8U) /*!< Bit position for RTC_TCR_CIR. */ -#define BM_RTC_TCR_CIR (0x0000FF00U) /*!< Bit mask for RTC_TCR_CIR. */ -#define BS_RTC_TCR_CIR (8U) /*!< Bit field size in bits for RTC_TCR_CIR. */ - -/*! @brief Read current value of the RTC_TCR_CIR field. */ -#define BR_RTC_TCR_CIR(x) (HW_RTC_TCR(x).B.CIR) - -/*! @brief Format value for bitfield RTC_TCR_CIR. */ -#define BF_RTC_TCR_CIR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_CIR) & BM_RTC_TCR_CIR) - -/*! @brief Set the CIR field to a new value. */ -#define BW_RTC_TCR_CIR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v))) -/*@}*/ - -/*! - * @name Register RTC_TCR, field TCV[23:16] (RO) - * - * Current value used by the compensation logic for the present second interval. - * Updated once a second if the CIC equals 0 with the contents of the TCR field. - * If the CIC does not equal zero then it is loaded with zero (compensation is - * not enabled for that second increment). - */ -/*@{*/ -#define BP_RTC_TCR_TCV (16U) /*!< Bit position for RTC_TCR_TCV. */ -#define BM_RTC_TCR_TCV (0x00FF0000U) /*!< Bit mask for RTC_TCR_TCV. */ -#define BS_RTC_TCR_TCV (8U) /*!< Bit field size in bits for RTC_TCR_TCV. */ - -/*! @brief Read current value of the RTC_TCR_TCV field. */ -#define BR_RTC_TCR_TCV(x) (HW_RTC_TCR(x).B.TCV) -/*@}*/ - -/*! - * @name Register RTC_TCR, field CIC[31:24] (RO) - * - * Current value of the compensation interval counter. If the compensation - * interval counter equals zero then it is loaded with the contents of the CIR. If the - * CIC does not equal zero then it is decremented once a second. - */ -/*@{*/ -#define BP_RTC_TCR_CIC (24U) /*!< Bit position for RTC_TCR_CIC. */ -#define BM_RTC_TCR_CIC (0xFF000000U) /*!< Bit mask for RTC_TCR_CIC. */ -#define BS_RTC_TCR_CIC (8U) /*!< Bit field size in bits for RTC_TCR_CIC. */ - -/*! @brief Read current value of the RTC_TCR_CIC field. */ -#define BR_RTC_TCR_CIC(x) (HW_RTC_TCR(x).B.CIC) -/*@}*/ - -/******************************************************************************* - * HW_RTC_CR - RTC Control Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_CR - RTC Control Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_cr -{ - uint32_t U; - struct _hw_rtc_cr_bitfields - { - uint32_t SWR : 1; /*!< [0] Software Reset */ - uint32_t WPE : 1; /*!< [1] Wakeup Pin Enable */ - uint32_t SUP : 1; /*!< [2] Supervisor Access */ - uint32_t UM : 1; /*!< [3] Update Mode */ - uint32_t WPS : 1; /*!< [4] Wakeup Pin Select */ - uint32_t RESERVED0 : 3; /*!< [7:5] */ - uint32_t OSCE : 1; /*!< [8] Oscillator Enable */ - uint32_t CLKO : 1; /*!< [9] Clock Output */ - uint32_t SC16P : 1; /*!< [10] Oscillator 16pF Load Configure */ - uint32_t SC8P : 1; /*!< [11] Oscillator 8pF Load Configure */ - uint32_t SC4P : 1; /*!< [12] Oscillator 4pF Load Configure */ - uint32_t SC2P : 1; /*!< [13] Oscillator 2pF Load Configure */ - uint32_t RESERVED1 : 18; /*!< [31:14] */ - } B; -} hw_rtc_cr_t; - -/*! - * @name Constants and macros for entire RTC_CR register - */ -/*@{*/ -#define HW_RTC_CR_ADDR(x) ((x) + 0x10U) - -#define HW_RTC_CR(x) (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR(x)) -#define HW_RTC_CR_RD(x) (HW_RTC_CR(x).U) -#define HW_RTC_CR_WR(x, v) (HW_RTC_CR(x).U = (v)) -#define HW_RTC_CR_SET(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) | (v))) -#define HW_RTC_CR_CLR(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) & ~(v))) -#define HW_RTC_CR_TOG(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_CR bitfields - */ - -/*! - * @name Register RTC_CR, field SWR[0] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and - * RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software - * explicitly clearing it. - */ -/*@{*/ -#define BP_RTC_CR_SWR (0U) /*!< Bit position for RTC_CR_SWR. */ -#define BM_RTC_CR_SWR (0x00000001U) /*!< Bit mask for RTC_CR_SWR. */ -#define BS_RTC_CR_SWR (1U) /*!< Bit field size in bits for RTC_CR_SWR. */ - -/*! @brief Read current value of the RTC_CR_SWR field. */ -#define BR_RTC_CR_SWR(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR)) - -/*! @brief Format value for bitfield RTC_CR_SWR. */ -#define BF_RTC_CR_SWR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SWR) & BM_RTC_CR_SWR) - -/*! @brief Set the SWR field to a new value. */ -#define BW_RTC_CR_SWR(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field WPE[1] (RW) - * - * The wakeup pin is optional and not available on all devices. - * - * Values: - * - 0 - Wakeup pin is disabled. - * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt - * asserts or the wakeup pin is turned on. - */ -/*@{*/ -#define BP_RTC_CR_WPE (1U) /*!< Bit position for RTC_CR_WPE. */ -#define BM_RTC_CR_WPE (0x00000002U) /*!< Bit mask for RTC_CR_WPE. */ -#define BS_RTC_CR_WPE (1U) /*!< Bit field size in bits for RTC_CR_WPE. */ - -/*! @brief Read current value of the RTC_CR_WPE field. */ -#define BR_RTC_CR_WPE(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE)) - -/*! @brief Format value for bitfield RTC_CR_WPE. */ -#define BF_RTC_CR_WPE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPE) & BM_RTC_CR_WPE) - -/*! @brief Set the WPE field to a new value. */ -#define BW_RTC_CR_WPE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SUP[2] (RW) - * - * Values: - * - 0 - Non-supervisor mode write accesses are not supported and generate a bus - * error. - * - 1 - Non-supervisor mode write accesses are supported. - */ -/*@{*/ -#define BP_RTC_CR_SUP (2U) /*!< Bit position for RTC_CR_SUP. */ -#define BM_RTC_CR_SUP (0x00000004U) /*!< Bit mask for RTC_CR_SUP. */ -#define BS_RTC_CR_SUP (1U) /*!< Bit field size in bits for RTC_CR_SUP. */ - -/*! @brief Read current value of the RTC_CR_SUP field. */ -#define BR_RTC_CR_SUP(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP)) - -/*! @brief Format value for bitfield RTC_CR_SUP. */ -#define BF_RTC_CR_SUP(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SUP) & BM_RTC_CR_SUP) - -/*! @brief Set the SUP field to a new value. */ -#define BW_RTC_CR_SUP(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field UM[3] (RW) - * - * Allows SR[TCE] to be written even when the Status Register is locked. When - * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if - * the SR[TCE] is clear. - * - * Values: - * - 0 - Registers cannot be written when locked. - * - 1 - Registers can be written when locked under limited conditions. - */ -/*@{*/ -#define BP_RTC_CR_UM (3U) /*!< Bit position for RTC_CR_UM. */ -#define BM_RTC_CR_UM (0x00000008U) /*!< Bit mask for RTC_CR_UM. */ -#define BS_RTC_CR_UM (1U) /*!< Bit field size in bits for RTC_CR_UM. */ - -/*! @brief Read current value of the RTC_CR_UM field. */ -#define BR_RTC_CR_UM(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM)) - -/*! @brief Format value for bitfield RTC_CR_UM. */ -#define BF_RTC_CR_UM(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_UM) & BM_RTC_CR_UM) - -/*! @brief Set the UM field to a new value. */ -#define BW_RTC_CR_UM(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field WPS[4] (RW) - * - * The wakeup pin is optional and not available on all devices. - * - * Values: - * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt - * asserts or the wakeup pin is turned on. - * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin - * is turned on and the 32kHz clock is output to other peripherals. - */ -/*@{*/ -#define BP_RTC_CR_WPS (4U) /*!< Bit position for RTC_CR_WPS. */ -#define BM_RTC_CR_WPS (0x00000010U) /*!< Bit mask for RTC_CR_WPS. */ -#define BS_RTC_CR_WPS (1U) /*!< Bit field size in bits for RTC_CR_WPS. */ - -/*! @brief Read current value of the RTC_CR_WPS field. */ -#define BR_RTC_CR_WPS(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS)) - -/*! @brief Format value for bitfield RTC_CR_WPS. */ -#define BF_RTC_CR_WPS(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPS) & BM_RTC_CR_WPS) - -/*! @brief Set the WPS field to a new value. */ -#define BW_RTC_CR_WPS(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field OSCE[8] (RW) - * - * Values: - * - 0 - 32.768 kHz oscillator is disabled. - * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the - * oscillator startup time before enabling the time counter to allow the 32.768 - * kHz clock time to stabilize. - */ -/*@{*/ -#define BP_RTC_CR_OSCE (8U) /*!< Bit position for RTC_CR_OSCE. */ -#define BM_RTC_CR_OSCE (0x00000100U) /*!< Bit mask for RTC_CR_OSCE. */ -#define BS_RTC_CR_OSCE (1U) /*!< Bit field size in bits for RTC_CR_OSCE. */ - -/*! @brief Read current value of the RTC_CR_OSCE field. */ -#define BR_RTC_CR_OSCE(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE)) - -/*! @brief Format value for bitfield RTC_CR_OSCE. */ -#define BF_RTC_CR_OSCE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_OSCE) & BM_RTC_CR_OSCE) - -/*! @brief Set the OSCE field to a new value. */ -#define BW_RTC_CR_OSCE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field CLKO[9] (RW) - * - * Values: - * - 0 - The 32 kHz clock is output to other peripherals. - * - 1 - The 32 kHz clock is not output to other peripherals. - */ -/*@{*/ -#define BP_RTC_CR_CLKO (9U) /*!< Bit position for RTC_CR_CLKO. */ -#define BM_RTC_CR_CLKO (0x00000200U) /*!< Bit mask for RTC_CR_CLKO. */ -#define BS_RTC_CR_CLKO (1U) /*!< Bit field size in bits for RTC_CR_CLKO. */ - -/*! @brief Read current value of the RTC_CR_CLKO field. */ -#define BR_RTC_CR_CLKO(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO)) - -/*! @brief Format value for bitfield RTC_CR_CLKO. */ -#define BF_RTC_CR_CLKO(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_CLKO) & BM_RTC_CR_CLKO) - -/*! @brief Set the CLKO field to a new value. */ -#define BW_RTC_CR_CLKO(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC16P[10] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC16P (10U) /*!< Bit position for RTC_CR_SC16P. */ -#define BM_RTC_CR_SC16P (0x00000400U) /*!< Bit mask for RTC_CR_SC16P. */ -#define BS_RTC_CR_SC16P (1U) /*!< Bit field size in bits for RTC_CR_SC16P. */ - -/*! @brief Read current value of the RTC_CR_SC16P field. */ -#define BR_RTC_CR_SC16P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P)) - -/*! @brief Format value for bitfield RTC_CR_SC16P. */ -#define BF_RTC_CR_SC16P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC16P) & BM_RTC_CR_SC16P) - -/*! @brief Set the SC16P field to a new value. */ -#define BW_RTC_CR_SC16P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC8P[11] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC8P (11U) /*!< Bit position for RTC_CR_SC8P. */ -#define BM_RTC_CR_SC8P (0x00000800U) /*!< Bit mask for RTC_CR_SC8P. */ -#define BS_RTC_CR_SC8P (1U) /*!< Bit field size in bits for RTC_CR_SC8P. */ - -/*! @brief Read current value of the RTC_CR_SC8P field. */ -#define BR_RTC_CR_SC8P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P)) - -/*! @brief Format value for bitfield RTC_CR_SC8P. */ -#define BF_RTC_CR_SC8P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC8P) & BM_RTC_CR_SC8P) - -/*! @brief Set the SC8P field to a new value. */ -#define BW_RTC_CR_SC8P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC4P[12] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC4P (12U) /*!< Bit position for RTC_CR_SC4P. */ -#define BM_RTC_CR_SC4P (0x00001000U) /*!< Bit mask for RTC_CR_SC4P. */ -#define BS_RTC_CR_SC4P (1U) /*!< Bit field size in bits for RTC_CR_SC4P. */ - -/*! @brief Read current value of the RTC_CR_SC4P field. */ -#define BR_RTC_CR_SC4P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P)) - -/*! @brief Format value for bitfield RTC_CR_SC4P. */ -#define BF_RTC_CR_SC4P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC4P) & BM_RTC_CR_SC4P) - -/*! @brief Set the SC4P field to a new value. */ -#define BW_RTC_CR_SC4P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC2P[13] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC2P (13U) /*!< Bit position for RTC_CR_SC2P. */ -#define BM_RTC_CR_SC2P (0x00002000U) /*!< Bit mask for RTC_CR_SC2P. */ -#define BS_RTC_CR_SC2P (1U) /*!< Bit field size in bits for RTC_CR_SC2P. */ - -/*! @brief Read current value of the RTC_CR_SC2P field. */ -#define BR_RTC_CR_SC2P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P)) - -/*! @brief Format value for bitfield RTC_CR_SC2P. */ -#define BF_RTC_CR_SC2P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC2P) & BM_RTC_CR_SC2P) - -/*! @brief Set the SC2P field to a new value. */ -#define BW_RTC_CR_SC2P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_SR - RTC Status Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_SR - RTC Status Register (RW) - * - * Reset value: 0x00000001U - */ -typedef union _hw_rtc_sr -{ - uint32_t U; - struct _hw_rtc_sr_bitfields - { - uint32_t TIF : 1; /*!< [0] Time Invalid Flag */ - uint32_t TOF : 1; /*!< [1] Time Overflow Flag */ - uint32_t TAF : 1; /*!< [2] Time Alarm Flag */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TCE : 1; /*!< [4] Time Counter Enable */ - uint32_t RESERVED1 : 27; /*!< [31:5] */ - } B; -} hw_rtc_sr_t; - -/*! - * @name Constants and macros for entire RTC_SR register - */ -/*@{*/ -#define HW_RTC_SR_ADDR(x) ((x) + 0x14U) - -#define HW_RTC_SR(x) (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR(x)) -#define HW_RTC_SR_RD(x) (HW_RTC_SR(x).U) -#define HW_RTC_SR_WR(x, v) (HW_RTC_SR(x).U = (v)) -#define HW_RTC_SR_SET(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) | (v))) -#define HW_RTC_SR_CLR(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) & ~(v))) -#define HW_RTC_SR_TOG(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_SR bitfields - */ - -/*! - * @name Register RTC_SR, field TIF[0] (RO) - * - * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR - * do not increment and read as zero when this bit is set. This bit is cleared by - * writing the TSR register when the time counter is disabled. - * - * Values: - * - 0 - Time is valid. - * - 1 - Time is invalid and time counter is read as zero. - */ -/*@{*/ -#define BP_RTC_SR_TIF (0U) /*!< Bit position for RTC_SR_TIF. */ -#define BM_RTC_SR_TIF (0x00000001U) /*!< Bit mask for RTC_SR_TIF. */ -#define BS_RTC_SR_TIF (1U) /*!< Bit field size in bits for RTC_SR_TIF. */ - -/*! @brief Read current value of the RTC_SR_TIF field. */ -#define BR_RTC_SR_TIF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TIF)) -/*@}*/ - -/*! - * @name Register RTC_SR, field TOF[1] (RO) - * - * Time overflow flag is set when the time counter is enabled and overflows. The - * TSR and TPR do not increment and read as zero when this bit is set. This bit - * is cleared by writing the TSR register when the time counter is disabled. - * - * Values: - * - 0 - Time overflow has not occurred. - * - 1 - Time overflow has occurred and time counter is read as zero. - */ -/*@{*/ -#define BP_RTC_SR_TOF (1U) /*!< Bit position for RTC_SR_TOF. */ -#define BM_RTC_SR_TOF (0x00000002U) /*!< Bit mask for RTC_SR_TOF. */ -#define BS_RTC_SR_TOF (1U) /*!< Bit field size in bits for RTC_SR_TOF. */ - -/*! @brief Read current value of the RTC_SR_TOF field. */ -#define BR_RTC_SR_TOF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TOF)) -/*@}*/ - -/*! - * @name Register RTC_SR, field TAF[2] (RO) - * - * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] - * increments. This bit is cleared by writing the TAR register. - * - * Values: - * - 0 - Time alarm has not occurred. - * - 1 - Time alarm has occurred. - */ -/*@{*/ -#define BP_RTC_SR_TAF (2U) /*!< Bit position for RTC_SR_TAF. */ -#define BM_RTC_SR_TAF (0x00000004U) /*!< Bit mask for RTC_SR_TAF. */ -#define BS_RTC_SR_TAF (1U) /*!< Bit field size in bits for RTC_SR_TAF. */ - -/*! @brief Read current value of the RTC_SR_TAF field. */ -#define BR_RTC_SR_TAF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TAF)) -/*@}*/ - -/*! - * @name Register RTC_SR, field TCE[4] (RW) - * - * When time counter is disabled the TSR register and TPR register are - * writeable, but do not increment. When time counter is enabled the TSR register and TPR - * register are not writeable, but increment. - * - * Values: - * - 0 - Time counter is disabled. - * - 1 - Time counter is enabled. - */ -/*@{*/ -#define BP_RTC_SR_TCE (4U) /*!< Bit position for RTC_SR_TCE. */ -#define BM_RTC_SR_TCE (0x00000010U) /*!< Bit mask for RTC_SR_TCE. */ -#define BS_RTC_SR_TCE (1U) /*!< Bit field size in bits for RTC_SR_TCE. */ - -/*! @brief Read current value of the RTC_SR_TCE field. */ -#define BR_RTC_SR_TCE(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE)) - -/*! @brief Format value for bitfield RTC_SR_TCE. */ -#define BF_RTC_SR_TCE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_SR_TCE) & BM_RTC_SR_TCE) - -/*! @brief Set the TCE field to a new value. */ -#define BW_RTC_SR_TCE(x, v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_LR - RTC Lock Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_LR - RTC Lock Register (RW) - * - * Reset value: 0x000000FFU - */ -typedef union _hw_rtc_lr -{ - uint32_t U; - struct _hw_rtc_lr_bitfields - { - uint32_t RESERVED0 : 3; /*!< [2:0] */ - uint32_t TCL : 1; /*!< [3] Time Compensation Lock */ - uint32_t CRL : 1; /*!< [4] Control Register Lock */ - uint32_t SRL : 1; /*!< [5] Status Register Lock */ - uint32_t LRL : 1; /*!< [6] Lock Register Lock */ - uint32_t RESERVED1 : 25; /*!< [31:7] */ - } B; -} hw_rtc_lr_t; - -/*! - * @name Constants and macros for entire RTC_LR register - */ -/*@{*/ -#define HW_RTC_LR_ADDR(x) ((x) + 0x18U) - -#define HW_RTC_LR(x) (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR(x)) -#define HW_RTC_LR_RD(x) (HW_RTC_LR(x).U) -#define HW_RTC_LR_WR(x, v) (HW_RTC_LR(x).U = (v)) -#define HW_RTC_LR_SET(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) | (v))) -#define HW_RTC_LR_CLR(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) & ~(v))) -#define HW_RTC_LR_TOG(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_LR bitfields - */ - -/*! - * @name Register RTC_LR, field TCL[3] (RW) - * - * After being cleared, this bit can be set only by VBAT POR or software reset. - * - * Values: - * - 0 - Time Compensation Register is locked and writes are ignored. - * - 1 - Time Compensation Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_TCL (3U) /*!< Bit position for RTC_LR_TCL. */ -#define BM_RTC_LR_TCL (0x00000008U) /*!< Bit mask for RTC_LR_TCL. */ -#define BS_RTC_LR_TCL (1U) /*!< Bit field size in bits for RTC_LR_TCL. */ - -/*! @brief Read current value of the RTC_LR_TCL field. */ -#define BR_RTC_LR_TCL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL)) - -/*! @brief Format value for bitfield RTC_LR_TCL. */ -#define BF_RTC_LR_TCL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_TCL) & BM_RTC_LR_TCL) - -/*! @brief Set the TCL field to a new value. */ -#define BW_RTC_LR_TCL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL) = (v)) -/*@}*/ - -/*! - * @name Register RTC_LR, field CRL[4] (RW) - * - * After being cleared, this bit can only be set by VBAT POR. - * - * Values: - * - 0 - Control Register is locked and writes are ignored. - * - 1 - Control Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_CRL (4U) /*!< Bit position for RTC_LR_CRL. */ -#define BM_RTC_LR_CRL (0x00000010U) /*!< Bit mask for RTC_LR_CRL. */ -#define BS_RTC_LR_CRL (1U) /*!< Bit field size in bits for RTC_LR_CRL. */ - -/*! @brief Read current value of the RTC_LR_CRL field. */ -#define BR_RTC_LR_CRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL)) - -/*! @brief Format value for bitfield RTC_LR_CRL. */ -#define BF_RTC_LR_CRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_CRL) & BM_RTC_LR_CRL) - -/*! @brief Set the CRL field to a new value. */ -#define BW_RTC_LR_CRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL) = (v)) -/*@}*/ - -/*! - * @name Register RTC_LR, field SRL[5] (RW) - * - * After being cleared, this bit can be set only by VBAT POR or software reset. - * - * Values: - * - 0 - Status Register is locked and writes are ignored. - * - 1 - Status Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_SRL (5U) /*!< Bit position for RTC_LR_SRL. */ -#define BM_RTC_LR_SRL (0x00000020U) /*!< Bit mask for RTC_LR_SRL. */ -#define BS_RTC_LR_SRL (1U) /*!< Bit field size in bits for RTC_LR_SRL. */ - -/*! @brief Read current value of the RTC_LR_SRL field. */ -#define BR_RTC_LR_SRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL)) - -/*! @brief Format value for bitfield RTC_LR_SRL. */ -#define BF_RTC_LR_SRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_SRL) & BM_RTC_LR_SRL) - -/*! @brief Set the SRL field to a new value. */ -#define BW_RTC_LR_SRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL) = (v)) -/*@}*/ - -/*! - * @name Register RTC_LR, field LRL[6] (RW) - * - * After being cleared, this bit can be set only by VBAT POR or software reset. - * - * Values: - * - 0 - Lock Register is locked and writes are ignored. - * - 1 - Lock Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_LRL (6U) /*!< Bit position for RTC_LR_LRL. */ -#define BM_RTC_LR_LRL (0x00000040U) /*!< Bit mask for RTC_LR_LRL. */ -#define BS_RTC_LR_LRL (1U) /*!< Bit field size in bits for RTC_LR_LRL. */ - -/*! @brief Read current value of the RTC_LR_LRL field. */ -#define BR_RTC_LR_LRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL)) - -/*! @brief Format value for bitfield RTC_LR_LRL. */ -#define BF_RTC_LR_LRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_LRL) & BM_RTC_LR_LRL) - -/*! @brief Set the LRL field to a new value. */ -#define BW_RTC_LR_LRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_IER - RTC Interrupt Enable Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW) - * - * Reset value: 0x00000007U - */ -typedef union _hw_rtc_ier -{ - uint32_t U; - struct _hw_rtc_ier_bitfields - { - uint32_t TIIE : 1; /*!< [0] Time Invalid Interrupt Enable */ - uint32_t TOIE : 1; /*!< [1] Time Overflow Interrupt Enable */ - uint32_t TAIE : 1; /*!< [2] Time Alarm Interrupt Enable */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TSIE : 1; /*!< [4] Time Seconds Interrupt Enable */ - uint32_t RESERVED1 : 2; /*!< [6:5] */ - uint32_t WPON : 1; /*!< [7] Wakeup Pin On */ - uint32_t RESERVED2 : 24; /*!< [31:8] */ - } B; -} hw_rtc_ier_t; - -/*! - * @name Constants and macros for entire RTC_IER register - */ -/*@{*/ -#define HW_RTC_IER_ADDR(x) ((x) + 0x1CU) - -#define HW_RTC_IER(x) (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR(x)) -#define HW_RTC_IER_RD(x) (HW_RTC_IER(x).U) -#define HW_RTC_IER_WR(x, v) (HW_RTC_IER(x).U = (v)) -#define HW_RTC_IER_SET(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) | (v))) -#define HW_RTC_IER_CLR(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) & ~(v))) -#define HW_RTC_IER_TOG(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_IER bitfields - */ - -/*! - * @name Register RTC_IER, field TIIE[0] (RW) - * - * Values: - * - 0 - Time invalid flag does not generate an interrupt. - * - 1 - Time invalid flag does generate an interrupt. - */ -/*@{*/ -#define BP_RTC_IER_TIIE (0U) /*!< Bit position for RTC_IER_TIIE. */ -#define BM_RTC_IER_TIIE (0x00000001U) /*!< Bit mask for RTC_IER_TIIE. */ -#define BS_RTC_IER_TIIE (1U) /*!< Bit field size in bits for RTC_IER_TIIE. */ - -/*! @brief Read current value of the RTC_IER_TIIE field. */ -#define BR_RTC_IER_TIIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE)) - -/*! @brief Format value for bitfield RTC_IER_TIIE. */ -#define BF_RTC_IER_TIIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TIIE) & BM_RTC_IER_TIIE) - -/*! @brief Set the TIIE field to a new value. */ -#define BW_RTC_IER_TIIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field TOIE[1] (RW) - * - * Values: - * - 0 - Time overflow flag does not generate an interrupt. - * - 1 - Time overflow flag does generate an interrupt. - */ -/*@{*/ -#define BP_RTC_IER_TOIE (1U) /*!< Bit position for RTC_IER_TOIE. */ -#define BM_RTC_IER_TOIE (0x00000002U) /*!< Bit mask for RTC_IER_TOIE. */ -#define BS_RTC_IER_TOIE (1U) /*!< Bit field size in bits for RTC_IER_TOIE. */ - -/*! @brief Read current value of the RTC_IER_TOIE field. */ -#define BR_RTC_IER_TOIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE)) - -/*! @brief Format value for bitfield RTC_IER_TOIE. */ -#define BF_RTC_IER_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TOIE) & BM_RTC_IER_TOIE) - -/*! @brief Set the TOIE field to a new value. */ -#define BW_RTC_IER_TOIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field TAIE[2] (RW) - * - * Values: - * - 0 - Time alarm flag does not generate an interrupt. - * - 1 - Time alarm flag does generate an interrupt. - */ -/*@{*/ -#define BP_RTC_IER_TAIE (2U) /*!< Bit position for RTC_IER_TAIE. */ -#define BM_RTC_IER_TAIE (0x00000004U) /*!< Bit mask for RTC_IER_TAIE. */ -#define BS_RTC_IER_TAIE (1U) /*!< Bit field size in bits for RTC_IER_TAIE. */ - -/*! @brief Read current value of the RTC_IER_TAIE field. */ -#define BR_RTC_IER_TAIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE)) - -/*! @brief Format value for bitfield RTC_IER_TAIE. */ -#define BF_RTC_IER_TAIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TAIE) & BM_RTC_IER_TAIE) - -/*! @brief Set the TAIE field to a new value. */ -#define BW_RTC_IER_TAIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field TSIE[4] (RW) - * - * The seconds interrupt is an edge-sensitive interrupt with a dedicated - * interrupt vector. It is generated once a second and requires no software overhead - * (there is no corresponding status flag to clear). - * - * Values: - * - 0 - Seconds interrupt is disabled. - * - 1 - Seconds interrupt is enabled. - */ -/*@{*/ -#define BP_RTC_IER_TSIE (4U) /*!< Bit position for RTC_IER_TSIE. */ -#define BM_RTC_IER_TSIE (0x00000010U) /*!< Bit mask for RTC_IER_TSIE. */ -#define BS_RTC_IER_TSIE (1U) /*!< Bit field size in bits for RTC_IER_TSIE. */ - -/*! @brief Read current value of the RTC_IER_TSIE field. */ -#define BR_RTC_IER_TSIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE)) - -/*! @brief Format value for bitfield RTC_IER_TSIE. */ -#define BF_RTC_IER_TSIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TSIE) & BM_RTC_IER_TSIE) - -/*! @brief Set the TSIE field to a new value. */ -#define BW_RTC_IER_TSIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field WPON[7] (RW) - * - * The wakeup pin is optional and not available on all devices. Whenever the - * wakeup pin is enabled and this bit is set, the wakeup pin will assert. - * - * Values: - * - 0 - No effect. - * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert. - */ -/*@{*/ -#define BP_RTC_IER_WPON (7U) /*!< Bit position for RTC_IER_WPON. */ -#define BM_RTC_IER_WPON (0x00000080U) /*!< Bit mask for RTC_IER_WPON. */ -#define BS_RTC_IER_WPON (1U) /*!< Bit field size in bits for RTC_IER_WPON. */ - -/*! @brief Read current value of the RTC_IER_WPON field. */ -#define BR_RTC_IER_WPON(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON)) - -/*! @brief Format value for bitfield RTC_IER_WPON. */ -#define BF_RTC_IER_WPON(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_WPON) & BM_RTC_IER_WPON) - -/*! @brief Set the WPON field to a new value. */ -#define BW_RTC_IER_WPON(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_WAR - RTC Write Access Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_WAR - RTC Write Access Register (RW) - * - * Reset value: 0x000000FFU - */ -typedef union _hw_rtc_war -{ - uint32_t U; - struct _hw_rtc_war_bitfields - { - uint32_t TSRW : 1; /*!< [0] Time Seconds Register Write */ - uint32_t TPRW : 1; /*!< [1] Time Prescaler Register Write */ - uint32_t TARW : 1; /*!< [2] Time Alarm Register Write */ - uint32_t TCRW : 1; /*!< [3] Time Compensation Register Write */ - uint32_t CRW : 1; /*!< [4] Control Register Write */ - uint32_t SRW : 1; /*!< [5] Status Register Write */ - uint32_t LRW : 1; /*!< [6] Lock Register Write */ - uint32_t IERW : 1; /*!< [7] Interrupt Enable Register Write */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_rtc_war_t; - -/*! - * @name Constants and macros for entire RTC_WAR register - */ -/*@{*/ -#define HW_RTC_WAR_ADDR(x) ((x) + 0x800U) - -#define HW_RTC_WAR(x) (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR(x)) -#define HW_RTC_WAR_RD(x) (HW_RTC_WAR(x).U) -#define HW_RTC_WAR_WR(x, v) (HW_RTC_WAR(x).U = (v)) -#define HW_RTC_WAR_SET(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) | (v))) -#define HW_RTC_WAR_CLR(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) & ~(v))) -#define HW_RTC_WAR_TOG(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_WAR bitfields - */ - -/*! - * @name Register RTC_WAR, field TSRW[0] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Seconds Register are ignored. - * - 1 - Writes to the Time Seconds Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TSRW (0U) /*!< Bit position for RTC_WAR_TSRW. */ -#define BM_RTC_WAR_TSRW (0x00000001U) /*!< Bit mask for RTC_WAR_TSRW. */ -#define BS_RTC_WAR_TSRW (1U) /*!< Bit field size in bits for RTC_WAR_TSRW. */ - -/*! @brief Read current value of the RTC_WAR_TSRW field. */ -#define BR_RTC_WAR_TSRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW)) - -/*! @brief Format value for bitfield RTC_WAR_TSRW. */ -#define BF_RTC_WAR_TSRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TSRW) & BM_RTC_WAR_TSRW) - -/*! @brief Set the TSRW field to a new value. */ -#define BW_RTC_WAR_TSRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field TPRW[1] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Prescaler Register are ignored. - * - 1 - Writes to the Time Prescaler Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TPRW (1U) /*!< Bit position for RTC_WAR_TPRW. */ -#define BM_RTC_WAR_TPRW (0x00000002U) /*!< Bit mask for RTC_WAR_TPRW. */ -#define BS_RTC_WAR_TPRW (1U) /*!< Bit field size in bits for RTC_WAR_TPRW. */ - -/*! @brief Read current value of the RTC_WAR_TPRW field. */ -#define BR_RTC_WAR_TPRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW)) - -/*! @brief Format value for bitfield RTC_WAR_TPRW. */ -#define BF_RTC_WAR_TPRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TPRW) & BM_RTC_WAR_TPRW) - -/*! @brief Set the TPRW field to a new value. */ -#define BW_RTC_WAR_TPRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field TARW[2] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Alarm Register are ignored. - * - 1 - Writes to the Time Alarm Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TARW (2U) /*!< Bit position for RTC_WAR_TARW. */ -#define BM_RTC_WAR_TARW (0x00000004U) /*!< Bit mask for RTC_WAR_TARW. */ -#define BS_RTC_WAR_TARW (1U) /*!< Bit field size in bits for RTC_WAR_TARW. */ - -/*! @brief Read current value of the RTC_WAR_TARW field. */ -#define BR_RTC_WAR_TARW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW)) - -/*! @brief Format value for bitfield RTC_WAR_TARW. */ -#define BF_RTC_WAR_TARW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TARW) & BM_RTC_WAR_TARW) - -/*! @brief Set the TARW field to a new value. */ -#define BW_RTC_WAR_TARW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field TCRW[3] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Compensation Register are ignored. - * - 1 - Writes to the Time Compensation Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TCRW (3U) /*!< Bit position for RTC_WAR_TCRW. */ -#define BM_RTC_WAR_TCRW (0x00000008U) /*!< Bit mask for RTC_WAR_TCRW. */ -#define BS_RTC_WAR_TCRW (1U) /*!< Bit field size in bits for RTC_WAR_TCRW. */ - -/*! @brief Read current value of the RTC_WAR_TCRW field. */ -#define BR_RTC_WAR_TCRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW)) - -/*! @brief Format value for bitfield RTC_WAR_TCRW. */ -#define BF_RTC_WAR_TCRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TCRW) & BM_RTC_WAR_TCRW) - -/*! @brief Set the TCRW field to a new value. */ -#define BW_RTC_WAR_TCRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field CRW[4] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Control Register are ignored. - * - 1 - Writes to the Control Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_CRW (4U) /*!< Bit position for RTC_WAR_CRW. */ -#define BM_RTC_WAR_CRW (0x00000010U) /*!< Bit mask for RTC_WAR_CRW. */ -#define BS_RTC_WAR_CRW (1U) /*!< Bit field size in bits for RTC_WAR_CRW. */ - -/*! @brief Read current value of the RTC_WAR_CRW field. */ -#define BR_RTC_WAR_CRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW)) - -/*! @brief Format value for bitfield RTC_WAR_CRW. */ -#define BF_RTC_WAR_CRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_CRW) & BM_RTC_WAR_CRW) - -/*! @brief Set the CRW field to a new value. */ -#define BW_RTC_WAR_CRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field SRW[5] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Status Register are ignored. - * - 1 - Writes to the Status Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_SRW (5U) /*!< Bit position for RTC_WAR_SRW. */ -#define BM_RTC_WAR_SRW (0x00000020U) /*!< Bit mask for RTC_WAR_SRW. */ -#define BS_RTC_WAR_SRW (1U) /*!< Bit field size in bits for RTC_WAR_SRW. */ - -/*! @brief Read current value of the RTC_WAR_SRW field. */ -#define BR_RTC_WAR_SRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW)) - -/*! @brief Format value for bitfield RTC_WAR_SRW. */ -#define BF_RTC_WAR_SRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_SRW) & BM_RTC_WAR_SRW) - -/*! @brief Set the SRW field to a new value. */ -#define BW_RTC_WAR_SRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field LRW[6] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Lock Register are ignored. - * - 1 - Writes to the Lock Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_LRW (6U) /*!< Bit position for RTC_WAR_LRW. */ -#define BM_RTC_WAR_LRW (0x00000040U) /*!< Bit mask for RTC_WAR_LRW. */ -#define BS_RTC_WAR_LRW (1U) /*!< Bit field size in bits for RTC_WAR_LRW. */ - -/*! @brief Read current value of the RTC_WAR_LRW field. */ -#define BR_RTC_WAR_LRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW)) - -/*! @brief Format value for bitfield RTC_WAR_LRW. */ -#define BF_RTC_WAR_LRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_LRW) & BM_RTC_WAR_LRW) - -/*! @brief Set the LRW field to a new value. */ -#define BW_RTC_WAR_LRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field IERW[7] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Interupt Enable Register are ignored. - * - 1 - Writes to the Interrupt Enable Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_IERW (7U) /*!< Bit position for RTC_WAR_IERW. */ -#define BM_RTC_WAR_IERW (0x00000080U) /*!< Bit mask for RTC_WAR_IERW. */ -#define BS_RTC_WAR_IERW (1U) /*!< Bit field size in bits for RTC_WAR_IERW. */ - -/*! @brief Read current value of the RTC_WAR_IERW field. */ -#define BR_RTC_WAR_IERW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW)) - -/*! @brief Format value for bitfield RTC_WAR_IERW. */ -#define BF_RTC_WAR_IERW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_IERW) & BM_RTC_WAR_IERW) - -/*! @brief Set the IERW field to a new value. */ -#define BW_RTC_WAR_IERW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_RAR - RTC Read Access Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_RAR - RTC Read Access Register (RW) - * - * Reset value: 0x000000FFU - */ -typedef union _hw_rtc_rar -{ - uint32_t U; - struct _hw_rtc_rar_bitfields - { - uint32_t TSRR : 1; /*!< [0] Time Seconds Register Read */ - uint32_t TPRR : 1; /*!< [1] Time Prescaler Register Read */ - uint32_t TARR : 1; /*!< [2] Time Alarm Register Read */ - uint32_t TCRR : 1; /*!< [3] Time Compensation Register Read */ - uint32_t CRR : 1; /*!< [4] Control Register Read */ - uint32_t SRR : 1; /*!< [5] Status Register Read */ - uint32_t LRR : 1; /*!< [6] Lock Register Read */ - uint32_t IERR : 1; /*!< [7] Interrupt Enable Register Read */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_rtc_rar_t; - -/*! - * @name Constants and macros for entire RTC_RAR register - */ -/*@{*/ -#define HW_RTC_RAR_ADDR(x) ((x) + 0x804U) - -#define HW_RTC_RAR(x) (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR(x)) -#define HW_RTC_RAR_RD(x) (HW_RTC_RAR(x).U) -#define HW_RTC_RAR_WR(x, v) (HW_RTC_RAR(x).U = (v)) -#define HW_RTC_RAR_SET(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) | (v))) -#define HW_RTC_RAR_CLR(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) & ~(v))) -#define HW_RTC_RAR_TOG(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_RAR bitfields - */ - -/*! - * @name Register RTC_RAR, field TSRR[0] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Seconds Register are ignored. - * - 1 - Reads to the Time Seconds Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TSRR (0U) /*!< Bit position for RTC_RAR_TSRR. */ -#define BM_RTC_RAR_TSRR (0x00000001U) /*!< Bit mask for RTC_RAR_TSRR. */ -#define BS_RTC_RAR_TSRR (1U) /*!< Bit field size in bits for RTC_RAR_TSRR. */ - -/*! @brief Read current value of the RTC_RAR_TSRR field. */ -#define BR_RTC_RAR_TSRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR)) - -/*! @brief Format value for bitfield RTC_RAR_TSRR. */ -#define BF_RTC_RAR_TSRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TSRR) & BM_RTC_RAR_TSRR) - -/*! @brief Set the TSRR field to a new value. */ -#define BW_RTC_RAR_TSRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field TPRR[1] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Pprescaler Register are ignored. - * - 1 - Reads to the Time Prescaler Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TPRR (1U) /*!< Bit position for RTC_RAR_TPRR. */ -#define BM_RTC_RAR_TPRR (0x00000002U) /*!< Bit mask for RTC_RAR_TPRR. */ -#define BS_RTC_RAR_TPRR (1U) /*!< Bit field size in bits for RTC_RAR_TPRR. */ - -/*! @brief Read current value of the RTC_RAR_TPRR field. */ -#define BR_RTC_RAR_TPRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR)) - -/*! @brief Format value for bitfield RTC_RAR_TPRR. */ -#define BF_RTC_RAR_TPRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TPRR) & BM_RTC_RAR_TPRR) - -/*! @brief Set the TPRR field to a new value. */ -#define BW_RTC_RAR_TPRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field TARR[2] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Alarm Register are ignored. - * - 1 - Reads to the Time Alarm Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TARR (2U) /*!< Bit position for RTC_RAR_TARR. */ -#define BM_RTC_RAR_TARR (0x00000004U) /*!< Bit mask for RTC_RAR_TARR. */ -#define BS_RTC_RAR_TARR (1U) /*!< Bit field size in bits for RTC_RAR_TARR. */ - -/*! @brief Read current value of the RTC_RAR_TARR field. */ -#define BR_RTC_RAR_TARR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR)) - -/*! @brief Format value for bitfield RTC_RAR_TARR. */ -#define BF_RTC_RAR_TARR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TARR) & BM_RTC_RAR_TARR) - -/*! @brief Set the TARR field to a new value. */ -#define BW_RTC_RAR_TARR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field TCRR[3] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Compensation Register are ignored. - * - 1 - Reads to the Time Compensation Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TCRR (3U) /*!< Bit position for RTC_RAR_TCRR. */ -#define BM_RTC_RAR_TCRR (0x00000008U) /*!< Bit mask for RTC_RAR_TCRR. */ -#define BS_RTC_RAR_TCRR (1U) /*!< Bit field size in bits for RTC_RAR_TCRR. */ - -/*! @brief Read current value of the RTC_RAR_TCRR field. */ -#define BR_RTC_RAR_TCRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR)) - -/*! @brief Format value for bitfield RTC_RAR_TCRR. */ -#define BF_RTC_RAR_TCRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TCRR) & BM_RTC_RAR_TCRR) - -/*! @brief Set the TCRR field to a new value. */ -#define BW_RTC_RAR_TCRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field CRR[4] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Control Register are ignored. - * - 1 - Reads to the Control Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_CRR (4U) /*!< Bit position for RTC_RAR_CRR. */ -#define BM_RTC_RAR_CRR (0x00000010U) /*!< Bit mask for RTC_RAR_CRR. */ -#define BS_RTC_RAR_CRR (1U) /*!< Bit field size in bits for RTC_RAR_CRR. */ - -/*! @brief Read current value of the RTC_RAR_CRR field. */ -#define BR_RTC_RAR_CRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR)) - -/*! @brief Format value for bitfield RTC_RAR_CRR. */ -#define BF_RTC_RAR_CRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_CRR) & BM_RTC_RAR_CRR) - -/*! @brief Set the CRR field to a new value. */ -#define BW_RTC_RAR_CRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field SRR[5] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Status Register are ignored. - * - 1 - Reads to the Status Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_SRR (5U) /*!< Bit position for RTC_RAR_SRR. */ -#define BM_RTC_RAR_SRR (0x00000020U) /*!< Bit mask for RTC_RAR_SRR. */ -#define BS_RTC_RAR_SRR (1U) /*!< Bit field size in bits for RTC_RAR_SRR. */ - -/*! @brief Read current value of the RTC_RAR_SRR field. */ -#define BR_RTC_RAR_SRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR)) - -/*! @brief Format value for bitfield RTC_RAR_SRR. */ -#define BF_RTC_RAR_SRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_SRR) & BM_RTC_RAR_SRR) - -/*! @brief Set the SRR field to a new value. */ -#define BW_RTC_RAR_SRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field LRR[6] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Lock Register are ignored. - * - 1 - Reads to the Lock Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_LRR (6U) /*!< Bit position for RTC_RAR_LRR. */ -#define BM_RTC_RAR_LRR (0x00000040U) /*!< Bit mask for RTC_RAR_LRR. */ -#define BS_RTC_RAR_LRR (1U) /*!< Bit field size in bits for RTC_RAR_LRR. */ - -/*! @brief Read current value of the RTC_RAR_LRR field. */ -#define BR_RTC_RAR_LRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR)) - -/*! @brief Format value for bitfield RTC_RAR_LRR. */ -#define BF_RTC_RAR_LRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_LRR) & BM_RTC_RAR_LRR) - -/*! @brief Set the LRR field to a new value. */ -#define BW_RTC_RAR_LRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field IERR[7] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Interrupt Enable Register are ignored. - * - 1 - Reads to the Interrupt Enable Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_IERR (7U) /*!< Bit position for RTC_RAR_IERR. */ -#define BM_RTC_RAR_IERR (0x00000080U) /*!< Bit mask for RTC_RAR_IERR. */ -#define BS_RTC_RAR_IERR (1U) /*!< Bit field size in bits for RTC_RAR_IERR. */ - -/*! @brief Read current value of the RTC_RAR_IERR field. */ -#define BR_RTC_RAR_IERR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR)) - -/*! @brief Format value for bitfield RTC_RAR_IERR. */ -#define BF_RTC_RAR_IERR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_IERR) & BM_RTC_RAR_IERR) - -/*! @brief Set the IERR field to a new value. */ -#define BW_RTC_RAR_IERR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_rtc_t - module struct - ******************************************************************************/ -/*! - * @brief All RTC module registers. - */ -#pragma pack(1) -typedef struct _hw_rtc -{ - __IO hw_rtc_tsr_t TSR; /*!< [0x0] RTC Time Seconds Register */ - __IO hw_rtc_tpr_t TPR; /*!< [0x4] RTC Time Prescaler Register */ - __IO hw_rtc_tar_t TAR; /*!< [0x8] RTC Time Alarm Register */ - __IO hw_rtc_tcr_t TCR; /*!< [0xC] RTC Time Compensation Register */ - __IO hw_rtc_cr_t CR; /*!< [0x10] RTC Control Register */ - __IO hw_rtc_sr_t SR; /*!< [0x14] RTC Status Register */ - __IO hw_rtc_lr_t LR; /*!< [0x18] RTC Lock Register */ - __IO hw_rtc_ier_t IER; /*!< [0x1C] RTC Interrupt Enable Register */ - uint8_t _reserved0[2016]; - __IO hw_rtc_war_t WAR; /*!< [0x800] RTC Write Access Register */ - __IO hw_rtc_rar_t RAR; /*!< [0x804] RTC Read Access Register */ -} hw_rtc_t; -#pragma pack() - -/*! @brief Macro to access all RTC registers. */ -/*! @param x RTC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RTC(RTC_BASE). */ -#define HW_RTC(x) (*(hw_rtc_t *)(x)) - -#endif /* __HW_RTC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h deleted file mode 100644 index e476c5ca1bb..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h +++ /dev/null @@ -1,4023 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SIM_REGISTERS_H__ -#define __HW_SIM_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 SIM - * - * System Integration Module - * - * Registers defined in this header file: - * - HW_SIM_SOPT1 - System Options Register 1 - * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register - * - HW_SIM_SOPT2 - System Options Register 2 - * - HW_SIM_SOPT4 - System Options Register 4 - * - HW_SIM_SOPT5 - System Options Register 5 - * - HW_SIM_SOPT7 - System Options Register 7 - * - HW_SIM_SOPT8 - System Options Register 8 - * - HW_SIM_SDID - System Device Identification Register - * - HW_SIM_SCGC4 - System Clock Gating Control Register 4 - * - HW_SIM_SCGC5 - System Clock Gating Control Register 5 - * - HW_SIM_SCGC6 - System Clock Gating Control Register 6 - * - HW_SIM_SCGC7 - System Clock Gating Control Register 7 - * - HW_SIM_CLKDIV1 - System Clock Divider Register 1 - * - HW_SIM_CLKDIV2 - System Clock Divider Register 2 - * - HW_SIM_FCFG1 - Flash Configuration Register 1 - * - HW_SIM_FCFG2 - Flash Configuration Register 2 - * - HW_SIM_UIDH - Unique Identification Register High - * - HW_SIM_UIDMH - Unique Identification Register Mid-High - * - HW_SIM_UIDML - Unique Identification Register Mid Low - * - HW_SIM_UIDL - Unique Identification Register Low - * - * - hw_sim_t - Struct containing all module registers. - */ - -#define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */ - -/******************************************************************************* - * HW_SIM_SOPT1 - System Options Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT1 - System Options Register 1 (RW) - * - * Reset value: 0x80000000U - * - * The SOPT1 register is only reset on POR or LVD. - */ -typedef union _hw_sim_sopt1 -{ - uint32_t U; - struct _hw_sim_sopt1_bitfields - { - uint32_t RESERVED0 : 12; /*!< [11:0] */ - uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */ - uint32_t OSC32KOUT : 2; /*!< [17:16] 32K Oscillator Clock Output */ - uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */ - uint32_t RESERVED1 : 9; /*!< [28:20] */ - uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby - * mode during VLPR and VLPW modes */ - uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby - * mode during Stop, VLPS, LLS and VLLS modes. */ - uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */ - } B; -} hw_sim_sopt1_t; - -/*! - * @name Constants and macros for entire SIM_SOPT1 register - */ -/*@{*/ -#define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U) - -#define HW_SIM_SOPT1(x) (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x)) -#define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U) -#define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v)) -#define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) | (v))) -#define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v))) -#define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT1 bitfields - */ - -/*! - * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO) - * - * This field specifies the amount of system RAM available on the device. - * - * Values: - * - 0001 - 8 KB - * - 0011 - 16 KB - * - 0100 - 24 KB - * - 0101 - 32 KB - * - 0110 - 48 KB - * - 0111 - 64 KB - * - 1000 - 96 KB - * - 1001 - 128 KB - * - 1011 - 256 KB - */ -/*@{*/ -#define BP_SIM_SOPT1_RAMSIZE (12U) /*!< Bit position for SIM_SOPT1_RAMSIZE. */ -#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */ -#define BS_SIM_SOPT1_RAMSIZE (4U) /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */ - -/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */ -#define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field OSC32KOUT[17:16] (RW) - * - * Outputs the ERCLK32K on the selected pin in all modes of operation (including - * LLS/VLLS and System Reset), overriding the existing pin mux configuration for - * that pin. This field is reset only on POR/LVD. - * - * Values: - * - 00 - ERCLK32K is not output. - * - 01 - ERCLK32K is output on PTE0. - * - 10 - ERCLK32K is output on PTE26. - * - 11 - Reserved. - */ -/*@{*/ -#define BP_SIM_SOPT1_OSC32KOUT (16U) /*!< Bit position for SIM_SOPT1_OSC32KOUT. */ -#define BM_SIM_SOPT1_OSC32KOUT (0x00030000U) /*!< Bit mask for SIM_SOPT1_OSC32KOUT. */ -#define BS_SIM_SOPT1_OSC32KOUT (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KOUT. */ - -/*! @brief Read current value of the SIM_SOPT1_OSC32KOUT field. */ -#define BR_SIM_SOPT1_OSC32KOUT(x) (HW_SIM_SOPT1(x).B.OSC32KOUT) - -/*! @brief Format value for bitfield SIM_SOPT1_OSC32KOUT. */ -#define BF_SIM_SOPT1_OSC32KOUT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KOUT) & BM_SIM_SOPT1_OSC32KOUT) - -/*! @brief Set the OSC32KOUT field to a new value. */ -#define BW_SIM_SOPT1_OSC32KOUT(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KOUT) | BF_SIM_SOPT1_OSC32KOUT(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW) - * - * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset - * only on POR/LVD. - * - * Values: - * - 00 - System oscillator (OSC32KCLK) - * - 01 - Reserved - * - 10 - RTC 32.768kHz oscillator - * - 11 - LPO 1 kHz - */ -/*@{*/ -#define BP_SIM_SOPT1_OSC32KSEL (18U) /*!< Bit position for SIM_SOPT1_OSC32KSEL. */ -#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */ -#define BS_SIM_SOPT1_OSC32KSEL (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */ - -/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */ -#define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL) - -/*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */ -#define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL) - -/*! @brief Set the OSC32KSEL field to a new value. */ -#define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field USBVSTBY[29] (RW) - * - * Controls whether the USB voltage regulator is placed in standby mode during - * VLPR and VLPW modes. - * - * Values: - * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes. - * - 1 - USB voltage regulator in standby during VLPR and VLPW modes. - */ -/*@{*/ -#define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */ -#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */ -#define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */ - -/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */ -#define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY)) - -/*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */ -#define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY) - -/*! @brief Set the USBVSTBY field to a new value. */ -#define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field USBSSTBY[30] (RW) - * - * Controls whether the USB voltage regulator is placed in standby mode during - * Stop, VLPS, LLS and VLLS modes. - * - * Values: - * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS - * modes. - * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. - */ -/*@{*/ -#define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */ -#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */ -#define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */ - -/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */ -#define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY)) - -/*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */ -#define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY) - -/*! @brief Set the USBSSTBY field to a new value. */ -#define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field USBREGEN[31] (RW) - * - * Controls whether the USB voltage regulator is enabled. - * - * Values: - * - 0 - USB voltage regulator is disabled. - * - 1 - USB voltage regulator is enabled. - */ -/*@{*/ -#define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */ -#define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */ -#define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */ - -/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */ -#define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN)) - -/*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */ -#define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN) - -/*! @brief Set the USBREGEN field to a new value. */ -#define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT1CFG - SOPT1 Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW) - * - * Reset value: 0x00000000U - * - * The SOPT1CFG register is reset on System Reset not VLLS. - */ -typedef union _hw_sim_sopt1cfg -{ - uint32_t U; - struct _hw_sim_sopt1cfg_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write - * enable */ - uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write - * enable */ - uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby - * write enable */ - uint32_t RESERVED1 : 5; /*!< [31:27] */ - } B; -} hw_sim_sopt1cfg_t; - -/*! - * @name Constants and macros for entire SIM_SOPT1CFG register - */ -/*@{*/ -#define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U) - -#define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x)) -#define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U) -#define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v)) -#define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v))) -#define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v))) -#define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT1CFG bitfields - */ - -/*! - * @name Register SIM_SOPT1CFG, field URWE[24] (RW) - * - * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This - * register bit clears after a write to USBREGEN. - * - * Values: - * - 0 - SOPT1 USBREGEN cannot be written. - * - 1 - SOPT1 USBREGEN can be written. - */ -/*@{*/ -#define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */ -#define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */ -#define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */ - -/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */ -#define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE)) - -/*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */ -#define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE) - -/*! @brief Set the URWE field to a new value. */ -#define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW) - * - * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. - * This register bit clears after a write to USBVSTBY. - * - * Values: - * - 0 - SOPT1 USBVSTBY cannot be written. - * - 1 - SOPT1 USBVSTBY can be written. - */ -/*@{*/ -#define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */ -#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */ -#define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */ - -/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */ -#define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE)) - -/*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */ -#define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE) - -/*! @brief Set the UVSWE field to a new value. */ -#define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1CFG, field USSWE[26] (RW) - * - * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. - * This register bit clears after a write to USBSSTBY. - * - * Values: - * - 0 - SOPT1 USBSSTBY cannot be written. - * - 1 - SOPT1 USBSSTBY can be written. - */ -/*@{*/ -#define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */ -#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */ -#define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */ - -/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */ -#define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE)) - -/*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */ -#define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE) - -/*! @brief Set the USSWE field to a new value. */ -#define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT2 - System Options Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT2 - System Options Register 2 (RW) - * - * Reset value: 0x00001000U - * - * SOPT2 contains the controls for selecting many of the module clock source - * options on this device. See the Clock Distribution chapter for more information - * including clocking diagrams and definitions of device clocks. - */ -typedef union _hw_sim_sopt2 -{ - uint32_t U; - struct _hw_sim_sopt2_bitfields - { - uint32_t RESERVED0 : 4; /*!< [3:0] */ - uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */ - uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */ - uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */ - uint32_t RESERVED1 : 2; /*!< [11:10] */ - uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */ - uint32_t RESERVED2 : 3; /*!< [15:13] */ - uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */ - uint32_t USBSRC : 1; /*!< [18] USB clock source select */ - uint32_t RESERVED3 : 7; /*!< [25:19] */ - uint32_t LPUARTSRC : 2; /*!< [27:26] LPUART clock source select */ - uint32_t RESERVED4 : 4; /*!< [31:28] */ - } B; -} hw_sim_sopt2_t; - -/*! - * @name Constants and macros for entire SIM_SOPT2 register - */ -/*@{*/ -#define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U) - -#define HW_SIM_SOPT2(x) (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x)) -#define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U) -#define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v)) -#define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) | (v))) -#define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v))) -#define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT2 bitfields - */ - -/*! - * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW) - * - * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the - * RTC_CLKOUT pin. - * - * Values: - * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin. - * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin. - */ -/*@{*/ -#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */ -#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */ -#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */ -#define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL)) - -/*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */ -#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL) - -/*! @brief Set the RTCCLKOUTSEL field to a new value. */ -#define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW) - * - * Selects the clock to output on the CLKOUT pin. - * - * Values: - * - 000 - FlexBus CLKOUT - * - 001 - Reserved - * - 010 - Flash clock - * - 011 - LPO clock (1 kHz) - * - 100 - MCGIRCLK - * - 101 - RTC 32.768kHz clock - * - 110 - OSCERCLK0 - * - 111 - IRC 48 MHz clock - */ -/*@{*/ -#define BP_SIM_SOPT2_CLKOUTSEL (5U) /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */ -#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */ -#define BS_SIM_SOPT2_CLKOUTSEL (3U) /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */ -#define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL) - -/*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */ -#define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL) - -/*! @brief Set the CLKOUTSEL field to a new value. */ -#define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field FBSL[9:8] (RW) - * - * If flash security is enabled, then this field affects what CPU operations can - * access off-chip via the FlexBus interface. This field has no effect if flash - * security is not enabled. - * - * Values: - * - 00 - All off-chip accesses (instruction and data) via the FlexBus are - * disallowed. - * - 01 - All off-chip accesses (instruction and data) via the FlexBus are - * disallowed. - * - 10 - Off-chip instruction accesses are disallowed. Data accesses are - * allowed. - * - 11 - Off-chip instruction accesses and data accesses are allowed. - */ -/*@{*/ -#define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */ -#define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */ -#define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */ - -/*! @brief Read current value of the SIM_SOPT2_FBSL field. */ -#define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL) - -/*! @brief Format value for bitfield SIM_SOPT2_FBSL. */ -#define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL) - -/*! @brief Set the FBSL field to a new value. */ -#define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW) - * - * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace - * clock source. - * - * Values: - * - 0 - MCGOUTCLK - * - 1 - Core/system clock - */ -/*@{*/ -#define BP_SIM_SOPT2_TRACECLKSEL (12U) /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */ -#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */ -#define BS_SIM_SOPT2_TRACECLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */ -#define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */ -#define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL) - -/*! @brief Set the TRACECLKSEL field to a new value. */ -#define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW) - * - * Selects the high frequency clock for various peripheral clocking options. - * - * Values: - * - 00 - MCGFLLCLK clock - * - 01 - MCGPLLCLK clock - * - 10 - Reserved - * - 11 - IRC48 MHz clock - */ -/*@{*/ -#define BP_SIM_SOPT2_PLLFLLSEL (16U) /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */ -#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */ -#define BS_SIM_SOPT2_PLLFLLSEL (2U) /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */ -#define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL) - -/*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */ -#define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL) - -/*! @brief Set the PLLFLLSEL field to a new value. */ -#define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field USBSRC[18] (RW) - * - * Selects the clock source for the USB 48 MHz clock. - * - * Values: - * - 0 - External bypass clock (USB_CLKIN). - * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by - * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by - * SIM_CLKDIV2[USBFRAC, USBDIV]. - */ -/*@{*/ -#define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */ -#define BM_SIM_SOPT2_USBSRC (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBSRC. */ -#define BS_SIM_SOPT2_USBSRC (1U) /*!< Bit field size in bits for SIM_SOPT2_USBSRC. */ - -/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */ -#define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC)) - -/*! @brief Format value for bitfield SIM_SOPT2_USBSRC. */ -#define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC) - -/*! @brief Set the USBSRC field to a new value. */ -#define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field LPUARTSRC[27:26] (RW) - * - * Selects the clock source for the LPUART transmit and receive clock. - * - * Values: - * - 00 - Clock disabled - * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by - * SOPT2[PLLFLLSEL]. - * - 10 - OSCERCLK clock - * - 11 - MCGIRCLK clock - */ -/*@{*/ -#define BP_SIM_SOPT2_LPUARTSRC (26U) /*!< Bit position for SIM_SOPT2_LPUARTSRC. */ -#define BM_SIM_SOPT2_LPUARTSRC (0x0C000000U) /*!< Bit mask for SIM_SOPT2_LPUARTSRC. */ -#define BS_SIM_SOPT2_LPUARTSRC (2U) /*!< Bit field size in bits for SIM_SOPT2_LPUARTSRC. */ - -/*! @brief Read current value of the SIM_SOPT2_LPUARTSRC field. */ -#define BR_SIM_SOPT2_LPUARTSRC(x) (HW_SIM_SOPT2(x).B.LPUARTSRC) - -/*! @brief Format value for bitfield SIM_SOPT2_LPUARTSRC. */ -#define BF_SIM_SOPT2_LPUARTSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_LPUARTSRC) & BM_SIM_SOPT2_LPUARTSRC) - -/*! @brief Set the LPUARTSRC field to a new value. */ -#define BW_SIM_SOPT2_LPUARTSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_LPUARTSRC) | BF_SIM_SOPT2_LPUARTSRC(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT4 - System Options Register 4 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT4 - System Options Register 4 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt4 -{ - uint32_t U; - struct _hw_sim_sopt4_bitfields - { - uint32_t FTM0FLT0 : 1; /*!< [0] FTM0 Fault 0 Select */ - uint32_t FTM0FLT1 : 1; /*!< [1] FTM0 Fault 1 Select */ - uint32_t RESERVED0 : 2; /*!< [3:2] */ - uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */ - uint32_t RESERVED1 : 3; /*!< [7:5] */ - uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */ - uint32_t RESERVED2 : 3; /*!< [11:9] */ - uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */ - uint32_t RESERVED3 : 5; /*!< [17:13] */ - uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture - * source select */ - uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture - * source select */ - uint32_t FTM2CH1SRC : 1; /*!< [22] FTM2 channel 1 input capture - * source select */ - uint32_t RESERVED4 : 1; /*!< [23] */ - uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin - * Select */ - uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */ - uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin - * Select */ - uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin - * Select */ - uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0 - * Source Select */ - uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1 - * Source Select */ - uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0 - * Source Select */ - uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1 - * Source Select */ - } B; -} hw_sim_sopt4_t; - -/*! - * @name Constants and macros for entire SIM_SOPT4 register - */ -/*@{*/ -#define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU) - -#define HW_SIM_SOPT4(x) (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x)) -#define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U) -#define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v)) -#define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) | (v))) -#define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v))) -#define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT4 bitfields - */ - -/*! - * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW) - * - * Selects the source of FTM0 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM0_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0FLT0 (0U) /*!< Bit position for SIM_SOPT4_FTM0FLT0. */ -#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */ -#define BS_SIM_SOPT4_FTM0FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */ -#define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */ -#define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0) - -/*! @brief Set the FTM0FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW) - * - * Selects the source of FTM0 fault 1. The pin source for fault 1 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM0_FLT1 pin - * - 1 - CMP1 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit position for SIM_SOPT4_FTM0FLT1. */ -#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */ -#define BS_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */ -#define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */ -#define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1) - -/*! @brief Set the FTM0FLT1 field to a new value. */ -#define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW) - * - * Selects the source of FTM1 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM1_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM1FLT0 (4U) /*!< Bit position for SIM_SOPT4_FTM1FLT0. */ -#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */ -#define BS_SIM_SOPT4_FTM1FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */ -#define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */ -#define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0) - -/*! @brief Set the FTM1FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW) - * - * Selects the source of FTM2 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate PORTx pin - * control register. - * - * Values: - * - 0 - FTM2_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2FLT0 (8U) /*!< Bit position for SIM_SOPT4_FTM2FLT0. */ -#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */ -#define BS_SIM_SOPT4_FTM2FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */ -#define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */ -#define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0) - -/*! @brief Set the FTM2FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW) - * - * Selects the source of FTM3 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate PORTx pin - * control register. - * - * Values: - * - 0 - FTM3_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */ -#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */ -#define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */ -#define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */ -#define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0) - -/*! @brief Set the FTM3FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW) - * - * Selects the source for FTM1 channel 0 input capture. When the FTM is not in - * input capture mode, clear this field. - * - * Values: - * - 00 - FTM1_CH0 signal - * - 01 - CMP0 output - * - 10 - CMP1 output - * - 11 - USB start of frame pulse - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM1CH0SRC (18U) /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */ -#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */ -#define BS_SIM_SOPT4_FTM1CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */ -#define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */ -#define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC) - -/*! @brief Set the FTM1CH0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW) - * - * Selects the source for FTM2 channel 0 input capture. When the FTM is not in - * input capture mode, clear this field. - * - * Values: - * - 00 - FTM2_CH0 signal - * - 01 - CMP0 output - * - 10 - CMP1 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2CH0SRC (20U) /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */ -#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */ -#define BS_SIM_SOPT4_FTM2CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */ -#define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */ -#define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC) - -/*! @brief Set the FTM2CH0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2CH1SRC[22] (RW) - * - * Values: - * - 0 - FTM2_CH1 signal - * - 1 - Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1. - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2CH1SRC (22U) /*!< Bit position for SIM_SOPT4_FTM2CH1SRC. */ -#define BM_SIM_SOPT4_FTM2CH1SRC (0x00400000U) /*!< Bit mask for SIM_SOPT4_FTM2CH1SRC. */ -#define BS_SIM_SOPT4_FTM2CH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH1SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2CH1SRC field. */ -#define BR_SIM_SOPT4_FTM2CH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CH1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2CH1SRC. */ -#define BF_SIM_SOPT4_FTM2CH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH1SRC) & BM_SIM_SOPT4_FTM2CH1SRC) - -/*! @brief Set the FTM2CH1SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM2CH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CH1SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW) - * - * Selects the external pin used to drive the clock to the FTM0 module. The - * selected pin must also be configured for the FTM external clock function through - * the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM_CLK0 pin - * - 1 - FTM_CLK1 pin - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0CLKSEL (24U) /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */ -#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */ -#define BS_SIM_SOPT4_FTM0CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */ -#define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */ -#define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL) - -/*! @brief Set the FTM0CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW) - * - * Selects the external pin used to drive the clock to the FTM1 module. The - * selected pin must also be configured for the FTM external clock function through - * the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM_CLK0 pin - * - 1 - FTM_CLK1 pin - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM1CLKSEL (25U) /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */ -#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */ -#define BS_SIM_SOPT4_FTM1CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */ -#define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */ -#define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL) - -/*! @brief Set the FTM1CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW) - * - * Selects the external pin used to drive the clock to the FTM2 module. The - * selected pin must also be configured for the FTM2 module external clock function - * through the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM2 external clock driven by FTM_CLK0 pin. - * - 1 - FTM2 external clock driven by FTM_CLK1 pin. - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2CLKSEL (26U) /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */ -#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */ -#define BS_SIM_SOPT4_FTM2CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */ -#define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */ -#define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL) - -/*! @brief Set the FTM2CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW) - * - * Selects the external pin used to drive the clock to the FTM3 module. The - * selected pin must also be configured for the FTM3 module external clock function - * through the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM3 external clock driven by FTM_CLK0 pin. - * - 1 - FTM3 external clock driven by FTM_CLK1 pin. - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */ -#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */ -#define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */ -#define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */ -#define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL) - -/*! @brief Set the FTM3CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW) - * - * Selects the source of FTM0 hardware trigger 0. - * - * Values: - * - 0 - HSCMP0 output drives FTM0 hardware trigger 0 - * - 1 - FTM1 channel match drives FTM0 hardware trigger 0 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */ -#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */ -#define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */ -#define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */ -#define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC) - -/*! @brief Set the FTM0TRG0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW) - * - * Selects the source of FTM0 hardware trigger 1. - * - * Values: - * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1 - * - 1 - FTM2 channel match drives FTM0 hardware trigger 1 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */ -#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */ -#define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */ -#define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */ -#define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC) - -/*! @brief Set the FTM0TRG1SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW) - * - * Selects the source of FTM3 hardware trigger 0. - * - * Values: - * - 0 - Reserved - * - 1 - FTM1 channel match drives FTM3 hardware trigger 0 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */ -#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */ -#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */ -#define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */ -#define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC) - -/*! @brief Set the FTM3TRG0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW) - * - * Selects the source of FTM3 hardware trigger 1. - * - * Values: - * - 0 - Reserved - * - 1 - FTM2 channel match drives FTM3 hardware trigger 1 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */ -#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */ -#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */ -#define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */ -#define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC) - -/*! @brief Set the FTM3TRG1SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT5 - System Options Register 5 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT5 - System Options Register 5 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt5 -{ - uint32_t U; - struct _hw_sim_sopt5_bitfields - { - uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source - * select */ - uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select - * */ - uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source - * select */ - uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select - * */ - uint32_t RESERVED0 : 10; /*!< [17:8] */ - uint32_t LPUART0RXSRC : 2; /*!< [19:18] LPUART0 receive data source - * select */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_sim_sopt5_t; - -/*! - * @name Constants and macros for entire SIM_SOPT5 register - */ -/*@{*/ -#define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U) - -#define HW_SIM_SOPT5(x) (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x)) -#define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U) -#define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v)) -#define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) | (v))) -#define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v))) -#define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT5 bitfields - */ - -/*! - * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW) - * - * Selects the source for the UART 0 transmit data. - * - * Values: - * - 00 - UART0_TX pin - * - 01 - UART0_TX pin modulated with FTM1 channel 0 output - * - 10 - UART0_TX pin modulated with FTM2 channel 0 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART0TXSRC (0U) /*!< Bit position for SIM_SOPT5_UART0TXSRC. */ -#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */ -#define BS_SIM_SOPT5_UART0TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */ -#define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */ -#define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC) - -/*! @brief Set the UART0TXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW) - * - * Selects the source for the UART 0 receive data. - * - * Values: - * - 00 - UART0_RX pin - * - 01 - CMP0 - * - 10 - CMP1 - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit position for SIM_SOPT5_UART0RXSRC. */ -#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */ -#define BS_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */ -#define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */ -#define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC) - -/*! @brief Set the UART0RXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW) - * - * Selects the source for the UART 1 transmit data. - * - * Values: - * - 00 - UART1_TX pin - * - 01 - UART1_TX pin modulated with FTM1 channel 0 output - * - 10 - UART1_TX pin modulated with FTM2 channel 0 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART1TXSRC (4U) /*!< Bit position for SIM_SOPT5_UART1TXSRC. */ -#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */ -#define BS_SIM_SOPT5_UART1TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */ -#define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */ -#define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC) - -/*! @brief Set the UART1TXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW) - * - * Selects the source for the UART 1 receive data. - * - * Values: - * - 00 - UART1_RX pin - * - 01 - CMP0 - * - 10 - CMP1 - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART1RXSRC (6U) /*!< Bit position for SIM_SOPT5_UART1RXSRC. */ -#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */ -#define BS_SIM_SOPT5_UART1RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */ -#define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */ -#define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC) - -/*! @brief Set the UART1RXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field LPUART0RXSRC[19:18] (RW) - * - * Selects the source for the LPUART0 receive data. - * - * Values: - * - 00 - LPUART0_RX pin - * - 01 - CMP0 output - * - 10 - CMP1 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_LPUART0RXSRC (18U) /*!< Bit position for SIM_SOPT5_LPUART0RXSRC. */ -#define BM_SIM_SOPT5_LPUART0RXSRC (0x000C0000U) /*!< Bit mask for SIM_SOPT5_LPUART0RXSRC. */ -#define BS_SIM_SOPT5_LPUART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_LPUART0RXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_LPUART0RXSRC field. */ -#define BR_SIM_SOPT5_LPUART0RXSRC(x) (HW_SIM_SOPT5(x).B.LPUART0RXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_LPUART0RXSRC. */ -#define BF_SIM_SOPT5_LPUART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_LPUART0RXSRC) & BM_SIM_SOPT5_LPUART0RXSRC) - -/*! @brief Set the LPUART0RXSRC field to a new value. */ -#define BW_SIM_SOPT5_LPUART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_LPUART0RXSRC) | BF_SIM_SOPT5_LPUART0RXSRC(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT7 - System Options Register 7 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT7 - System Options Register 7 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt7 -{ - uint32_t U; - struct _hw_sim_sopt7_bitfields - { - uint32_t ADC0TRGSEL : 4; /*!< [3:0] ADC0 trigger select */ - uint32_t ADC0PRETRGSEL : 1; /*!< [4] ADC0 pretrigger select */ - uint32_t RESERVED0 : 2; /*!< [6:5] */ - uint32_t ADC0ALTTRGEN : 1; /*!< [7] ADC0 alternate trigger enable */ - uint32_t ADC1TRGSEL : 4; /*!< [11:8] ADC1 trigger select */ - uint32_t ADC1PRETRGSEL : 1; /*!< [12] ADC1 pre-trigger select */ - uint32_t RESERVED1 : 2; /*!< [14:13] */ - uint32_t ADC1ALTTRGEN : 1; /*!< [15] ADC1 alternate trigger enable */ - uint32_t RESERVED2 : 16; /*!< [31:16] */ - } B; -} hw_sim_sopt7_t; - -/*! - * @name Constants and macros for entire SIM_SOPT7 register - */ -/*@{*/ -#define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U) - -#define HW_SIM_SOPT7(x) (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x)) -#define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U) -#define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v)) -#define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) | (v))) -#define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v))) -#define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT7 bitfields - */ - -/*! - * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW) - * - * Selects the ADC0 trigger source when alternative triggers are functional in - * stop and VLPS modes. . - * - * Values: - * - 0000 - PDB external trigger pin input (PDB0_EXTRG) - * - 0001 - High speed comparator 0 output - * - 0010 - High speed comparator 1 output - * - 0011 - Reserved - * - 0100 - PIT trigger 0 - * - 0101 - PIT trigger 1 - * - 0110 - PIT trigger 2 - * - 0111 - PIT trigger 3 - * - 1000 - FTM0 trigger - * - 1001 - FTM1 trigger - * - 1010 - FTM2 trigger - * - 1011 - FTM3 trigger - * - 1100 - RTC alarm - * - 1101 - RTC seconds - * - 1110 - Low-power timer (LPTMR) trigger - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC0TRGSEL (0U) /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */ -#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */ -#define BS_SIM_SOPT7_ADC0TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */ -#define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */ -#define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL) - -/*! @brief Set the ADC0TRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW) - * - * Selects the ADC0 pre-trigger source when alternative triggers are enabled - * through ADC0ALTTRGEN. - * - * Values: - * - 0 - Pre-trigger A - * - 1 - Pre-trigger B - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */ -#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */ -#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */ -#define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */ -#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL) - -/*! @brief Set the ADC0PRETRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW) - * - * Enable alternative conversion triggers for ADC0. - * - * Values: - * - 0 - PDB trigger selected for ADC0. - * - 1 - Alternate trigger selected for ADC0. - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */ -#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */ -#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */ -#define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */ -#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN) - -/*! @brief Set the ADC0ALTTRGEN field to a new value. */ -#define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW) - * - * Selects the ADC1 trigger source when alternative triggers are functional in - * stop and VLPS modes. - * - * Values: - * - 0000 - PDB external trigger pin input (PDB0_EXTRG) - * - 0001 - High speed comparator 0 output - * - 0010 - High speed comparator 1 output - * - 0011 - Reserved - * - 0100 - PIT trigger 0 - * - 0101 - PIT trigger 1 - * - 0110 - PIT trigger 2 - * - 0111 - PIT trigger 3 - * - 1000 - FTM0 trigger - * - 1001 - FTM1 trigger - * - 1010 - FTM2 trigger - * - 1011 - FTM3 trigger - * - 1100 - RTC alarm - * - 1101 - RTC seconds - * - 1110 - Low-power timer (LPTMR) trigger - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC1TRGSEL (8U) /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */ -#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */ -#define BS_SIM_SOPT7_ADC1TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */ -#define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */ -#define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL) - -/*! @brief Set the ADC1TRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW) - * - * Selects the ADC1 pre-trigger source when alternative triggers are enabled - * through ADC1ALTTRGEN. - * - * Values: - * - 0 - Pre-trigger A selected for ADC1. - * - 1 - Pre-trigger B selected for ADC1. - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */ -#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */ -#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */ -#define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */ -#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL) - -/*! @brief Set the ADC1PRETRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW) - * - * Enable alternative conversion triggers for ADC1. - * - * Values: - * - 0 - PDB trigger selected for ADC1 - * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */ -#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */ -#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */ -#define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */ -#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN) - -/*! @brief Set the ADC1ALTTRGEN field to a new value. */ -#define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT8 - System Options Register 8 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT8 - System Options Register 8 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt8 -{ - uint32_t U; - struct _hw_sim_sopt8_bitfields - { - uint32_t FTM0SYNCBIT : 1; /*!< [0] FTM0 Hardware Trigger 0 Software - * Synchronization */ - uint32_t FTM1SYNCBIT : 1; /*!< [1] FTM1 Hardware Trigger 0 Software - * Synchronization */ - uint32_t FTM2SYNCBIT : 1; /*!< [2] FTM2 Hardware Trigger 0 Software - * Synchronization */ - uint32_t FTM3SYNCBIT : 1; /*!< [3] FTM3 Hardware Trigger 0 Software - * Synchronization */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t FTM0OCH0SRC : 1; /*!< [16] FTM0 channel 0 output source */ - uint32_t FTM0OCH1SRC : 1; /*!< [17] FTM0 channel 1 output source */ - uint32_t FTM0OCH2SRC : 1; /*!< [18] FTM0 channel 2 output source */ - uint32_t FTM0OCH3SRC : 1; /*!< [19] FTM0 channel 3 output source */ - uint32_t FTM0OCH4SRC : 1; /*!< [20] FTM0 channel 4 output source */ - uint32_t FTM0OCH5SRC : 1; /*!< [21] FTM0 channel 5 output source */ - uint32_t FTM0OCH6SRC : 1; /*!< [22] FTM0 channel 6 output source */ - uint32_t FTM0OCH7SRC : 1; /*!< [23] FTM0 channel 7 output source */ - uint32_t FTM3OCH0SRC : 1; /*!< [24] FTM3 channel 0 output source */ - uint32_t FTM3OCH1SRC : 1; /*!< [25] FTM3 channel 1 output source */ - uint32_t FTM3OCH2SRC : 1; /*!< [26] FTM3 channel 2 output source */ - uint32_t FTM3OCH3SRC : 1; /*!< [27] FTM3 channel 3 output source */ - uint32_t FTM3OCH4SRC : 1; /*!< [28] FTM3 channel 4 output source */ - uint32_t FTM3OCH5SRC : 1; /*!< [29] FTM3 channel 5 output source */ - uint32_t FTM3OCH6SRC : 1; /*!< [30] FTM3 channel 6 output source */ - uint32_t FTM3OCH7SRC : 1; /*!< [31] FTM3 channel 7 output source */ - } B; -} hw_sim_sopt8_t; - -/*! - * @name Constants and macros for entire SIM_SOPT8 register - */ -/*@{*/ -#define HW_SIM_SOPT8_ADDR(x) ((x) + 0x101CU) - -#define HW_SIM_SOPT8(x) (*(__IO hw_sim_sopt8_t *) HW_SIM_SOPT8_ADDR(x)) -#define HW_SIM_SOPT8_RD(x) (HW_SIM_SOPT8(x).U) -#define HW_SIM_SOPT8_WR(x, v) (HW_SIM_SOPT8(x).U = (v)) -#define HW_SIM_SOPT8_SET(x, v) (HW_SIM_SOPT8_WR(x, HW_SIM_SOPT8_RD(x) | (v))) -#define HW_SIM_SOPT8_CLR(x, v) (HW_SIM_SOPT8_WR(x, HW_SIM_SOPT8_RD(x) & ~(v))) -#define HW_SIM_SOPT8_TOG(x, v) (HW_SIM_SOPT8_WR(x, HW_SIM_SOPT8_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT8 bitfields - */ - -/*! - * @name Register SIM_SOPT8, field FTM0SYNCBIT[0] (RW) - * - * Values: - * - 0 - No effect - * - 1 - Write 1 to assert the TRIG0 input to FTM0, software must clear this bit - * to allow other trigger sources to assert. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0SYNCBIT (0U) /*!< Bit position for SIM_SOPT8_FTM0SYNCBIT. */ -#define BM_SIM_SOPT8_FTM0SYNCBIT (0x00000001U) /*!< Bit mask for SIM_SOPT8_FTM0SYNCBIT. */ -#define BS_SIM_SOPT8_FTM0SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0SYNCBIT. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0SYNCBIT field. */ -#define BR_SIM_SOPT8_FTM0SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0SYNCBIT)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0SYNCBIT. */ -#define BF_SIM_SOPT8_FTM0SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0SYNCBIT) & BM_SIM_SOPT8_FTM0SYNCBIT) - -/*! @brief Set the FTM0SYNCBIT field to a new value. */ -#define BW_SIM_SOPT8_FTM0SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0SYNCBIT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM1SYNCBIT[1] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - Write 1 to assert the TRIG0 input to FTM1, software must clear this bit - * to allow other trigger sources to assert. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM1SYNCBIT (1U) /*!< Bit position for SIM_SOPT8_FTM1SYNCBIT. */ -#define BM_SIM_SOPT8_FTM1SYNCBIT (0x00000002U) /*!< Bit mask for SIM_SOPT8_FTM1SYNCBIT. */ -#define BS_SIM_SOPT8_FTM1SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM1SYNCBIT. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM1SYNCBIT field. */ -#define BR_SIM_SOPT8_FTM1SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM1SYNCBIT)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM1SYNCBIT. */ -#define BF_SIM_SOPT8_FTM1SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM1SYNCBIT) & BM_SIM_SOPT8_FTM1SYNCBIT) - -/*! @brief Set the FTM1SYNCBIT field to a new value. */ -#define BW_SIM_SOPT8_FTM1SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM1SYNCBIT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM2SYNCBIT[2] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - Write 1 to assert the TRIG0 input to FTM2, software must clear this bit - * to allow other trigger sources to assert. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM2SYNCBIT (2U) /*!< Bit position for SIM_SOPT8_FTM2SYNCBIT. */ -#define BM_SIM_SOPT8_FTM2SYNCBIT (0x00000004U) /*!< Bit mask for SIM_SOPT8_FTM2SYNCBIT. */ -#define BS_SIM_SOPT8_FTM2SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM2SYNCBIT. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM2SYNCBIT field. */ -#define BR_SIM_SOPT8_FTM2SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM2SYNCBIT)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM2SYNCBIT. */ -#define BF_SIM_SOPT8_FTM2SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM2SYNCBIT) & BM_SIM_SOPT8_FTM2SYNCBIT) - -/*! @brief Set the FTM2SYNCBIT field to a new value. */ -#define BW_SIM_SOPT8_FTM2SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM2SYNCBIT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3SYNCBIT[3] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - Write 1 to assert the TRIG0 input to FTM3, software must clear this bit - * to allow other trigger sources to assert. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3SYNCBIT (3U) /*!< Bit position for SIM_SOPT8_FTM3SYNCBIT. */ -#define BM_SIM_SOPT8_FTM3SYNCBIT (0x00000008U) /*!< Bit mask for SIM_SOPT8_FTM3SYNCBIT. */ -#define BS_SIM_SOPT8_FTM3SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3SYNCBIT. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3SYNCBIT field. */ -#define BR_SIM_SOPT8_FTM3SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3SYNCBIT)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3SYNCBIT. */ -#define BF_SIM_SOPT8_FTM3SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3SYNCBIT) & BM_SIM_SOPT8_FTM3SYNCBIT) - -/*! @brief Set the FTM3SYNCBIT field to a new value. */ -#define BW_SIM_SOPT8_FTM3SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3SYNCBIT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH0SRC[16] (RW) - * - * Values: - * - 0 - FTM0_CH0 pin is output of FTM0 channel 0 output - * - 1 - FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH0SRC (16U) /*!< Bit position for SIM_SOPT8_FTM0OCH0SRC. */ -#define BM_SIM_SOPT8_FTM0OCH0SRC (0x00010000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH0SRC. */ -#define BS_SIM_SOPT8_FTM0OCH0SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH0SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH0SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH0SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH0SRC. */ -#define BF_SIM_SOPT8_FTM0OCH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH0SRC) & BM_SIM_SOPT8_FTM0OCH0SRC) - -/*! @brief Set the FTM0OCH0SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH0SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH1SRC[17] (RW) - * - * Values: - * - 0 - FTM0_CH1 pin is output of FTM0 channel 1 output - * - 1 - FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH1SRC (17U) /*!< Bit position for SIM_SOPT8_FTM0OCH1SRC. */ -#define BM_SIM_SOPT8_FTM0OCH1SRC (0x00020000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH1SRC. */ -#define BS_SIM_SOPT8_FTM0OCH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH1SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH1SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH1SRC. */ -#define BF_SIM_SOPT8_FTM0OCH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH1SRC) & BM_SIM_SOPT8_FTM0OCH1SRC) - -/*! @brief Set the FTM0OCH1SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH1SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH2SRC[18] (RW) - * - * Values: - * - 0 - FTM0_CH2 pin is output of FTM0 channel 2 output - * - 1 - FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH2SRC (18U) /*!< Bit position for SIM_SOPT8_FTM0OCH2SRC. */ -#define BM_SIM_SOPT8_FTM0OCH2SRC (0x00040000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH2SRC. */ -#define BS_SIM_SOPT8_FTM0OCH2SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH2SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH2SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH2SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH2SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH2SRC. */ -#define BF_SIM_SOPT8_FTM0OCH2SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH2SRC) & BM_SIM_SOPT8_FTM0OCH2SRC) - -/*! @brief Set the FTM0OCH2SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH2SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH2SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH3SRC[19] (RW) - * - * Values: - * - 0 - FTM0_CH3 pin is output of FTM0 channel 3 output - * - 1 - FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH3SRC (19U) /*!< Bit position for SIM_SOPT8_FTM0OCH3SRC. */ -#define BM_SIM_SOPT8_FTM0OCH3SRC (0x00080000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH3SRC. */ -#define BS_SIM_SOPT8_FTM0OCH3SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH3SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH3SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH3SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH3SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH3SRC. */ -#define BF_SIM_SOPT8_FTM0OCH3SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH3SRC) & BM_SIM_SOPT8_FTM0OCH3SRC) - -/*! @brief Set the FTM0OCH3SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH3SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH3SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH4SRC[20] (RW) - * - * Values: - * - 0 - FTM0_CH4 pin is output of FTM0 channel 4 output - * - 1 - FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH4SRC (20U) /*!< Bit position for SIM_SOPT8_FTM0OCH4SRC. */ -#define BM_SIM_SOPT8_FTM0OCH4SRC (0x00100000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH4SRC. */ -#define BS_SIM_SOPT8_FTM0OCH4SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH4SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH4SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH4SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH4SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH4SRC. */ -#define BF_SIM_SOPT8_FTM0OCH4SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH4SRC) & BM_SIM_SOPT8_FTM0OCH4SRC) - -/*! @brief Set the FTM0OCH4SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH4SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH4SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH5SRC[21] (RW) - * - * Values: - * - 0 - FTM0_CH5 pin is output of FTM0 channel 5 output - * - 1 - FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH5SRC (21U) /*!< Bit position for SIM_SOPT8_FTM0OCH5SRC. */ -#define BM_SIM_SOPT8_FTM0OCH5SRC (0x00200000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH5SRC. */ -#define BS_SIM_SOPT8_FTM0OCH5SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH5SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH5SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH5SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH5SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH5SRC. */ -#define BF_SIM_SOPT8_FTM0OCH5SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH5SRC) & BM_SIM_SOPT8_FTM0OCH5SRC) - -/*! @brief Set the FTM0OCH5SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH5SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH5SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH6SRC[22] (RW) - * - * Values: - * - 0 - FTM0_CH6 pin is output of FTM0 channel 6 output - * - 1 - FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH6SRC (22U) /*!< Bit position for SIM_SOPT8_FTM0OCH6SRC. */ -#define BM_SIM_SOPT8_FTM0OCH6SRC (0x00400000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH6SRC. */ -#define BS_SIM_SOPT8_FTM0OCH6SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH6SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH6SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH6SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH6SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH6SRC. */ -#define BF_SIM_SOPT8_FTM0OCH6SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH6SRC) & BM_SIM_SOPT8_FTM0OCH6SRC) - -/*! @brief Set the FTM0OCH6SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH6SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH6SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM0OCH7SRC[23] (RW) - * - * Values: - * - 0 - FTM0_CH7 pin is output of FTM0 channel 7 output - * - 1 - FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 - * channel 1 output - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM0OCH7SRC (23U) /*!< Bit position for SIM_SOPT8_FTM0OCH7SRC. */ -#define BM_SIM_SOPT8_FTM0OCH7SRC (0x00800000U) /*!< Bit mask for SIM_SOPT8_FTM0OCH7SRC. */ -#define BS_SIM_SOPT8_FTM0OCH7SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM0OCH7SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM0OCH7SRC field. */ -#define BR_SIM_SOPT8_FTM0OCH7SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH7SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM0OCH7SRC. */ -#define BF_SIM_SOPT8_FTM0OCH7SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM0OCH7SRC) & BM_SIM_SOPT8_FTM0OCH7SRC) - -/*! @brief Set the FTM0OCH7SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM0OCH7SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH7SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH0SRC[24] (RW) - * - * Values: - * - 0 - FTM3_CH0 pin is output of FTM3 channel 0 output - * - 1 - FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH0SRC (24U) /*!< Bit position for SIM_SOPT8_FTM3OCH0SRC. */ -#define BM_SIM_SOPT8_FTM3OCH0SRC (0x01000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH0SRC. */ -#define BS_SIM_SOPT8_FTM3OCH0SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH0SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH0SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH0SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH0SRC. */ -#define BF_SIM_SOPT8_FTM3OCH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH0SRC) & BM_SIM_SOPT8_FTM3OCH0SRC) - -/*! @brief Set the FTM3OCH0SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH0SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH1SRC[25] (RW) - * - * Values: - * - 0 - FTM3_CH1 pin is output of FTM3 channel 1 output - * - 1 - FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH1SRC (25U) /*!< Bit position for SIM_SOPT8_FTM3OCH1SRC. */ -#define BM_SIM_SOPT8_FTM3OCH1SRC (0x02000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH1SRC. */ -#define BS_SIM_SOPT8_FTM3OCH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH1SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH1SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH1SRC. */ -#define BF_SIM_SOPT8_FTM3OCH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH1SRC) & BM_SIM_SOPT8_FTM3OCH1SRC) - -/*! @brief Set the FTM3OCH1SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH1SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH2SRC[26] (RW) - * - * Values: - * - 0 - FTM3_CH2 pin is output of FTM3 channel 2 output - * - 1 - FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH2SRC (26U) /*!< Bit position for SIM_SOPT8_FTM3OCH2SRC. */ -#define BM_SIM_SOPT8_FTM3OCH2SRC (0x04000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH2SRC. */ -#define BS_SIM_SOPT8_FTM3OCH2SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH2SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH2SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH2SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH2SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH2SRC. */ -#define BF_SIM_SOPT8_FTM3OCH2SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH2SRC) & BM_SIM_SOPT8_FTM3OCH2SRC) - -/*! @brief Set the FTM3OCH2SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH2SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH2SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH3SRC[27] (RW) - * - * Values: - * - 0 - FTM3_CH3 pin is output of FTM3 channel 3 output - * - 1 - FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH3SRC (27U) /*!< Bit position for SIM_SOPT8_FTM3OCH3SRC. */ -#define BM_SIM_SOPT8_FTM3OCH3SRC (0x08000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH3SRC. */ -#define BS_SIM_SOPT8_FTM3OCH3SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH3SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH3SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH3SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH3SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH3SRC. */ -#define BF_SIM_SOPT8_FTM3OCH3SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH3SRC) & BM_SIM_SOPT8_FTM3OCH3SRC) - -/*! @brief Set the FTM3OCH3SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH3SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH3SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH4SRC[28] (RW) - * - * Values: - * - 0 - FTM3_CH4 pin is output of FTM3 channel 4 output - * - 1 - FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH4SRC (28U) /*!< Bit position for SIM_SOPT8_FTM3OCH4SRC. */ -#define BM_SIM_SOPT8_FTM3OCH4SRC (0x10000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH4SRC. */ -#define BS_SIM_SOPT8_FTM3OCH4SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH4SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH4SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH4SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH4SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH4SRC. */ -#define BF_SIM_SOPT8_FTM3OCH4SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH4SRC) & BM_SIM_SOPT8_FTM3OCH4SRC) - -/*! @brief Set the FTM3OCH4SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH4SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH4SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH5SRC[29] (RW) - * - * Values: - * - 0 - FTM3_CH5 pin is output of FTM3 channel 5 output - * - 1 - FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH5SRC (29U) /*!< Bit position for SIM_SOPT8_FTM3OCH5SRC. */ -#define BM_SIM_SOPT8_FTM3OCH5SRC (0x20000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH5SRC. */ -#define BS_SIM_SOPT8_FTM3OCH5SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH5SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH5SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH5SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH5SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH5SRC. */ -#define BF_SIM_SOPT8_FTM3OCH5SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH5SRC) & BM_SIM_SOPT8_FTM3OCH5SRC) - -/*! @brief Set the FTM3OCH5SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH5SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH5SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH6SRC[30] (RW) - * - * Values: - * - 0 - FTM3_CH6 pin is output of FTM3 channel 6 output - * - 1 - FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH6SRC (30U) /*!< Bit position for SIM_SOPT8_FTM3OCH6SRC. */ -#define BM_SIM_SOPT8_FTM3OCH6SRC (0x40000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH6SRC. */ -#define BS_SIM_SOPT8_FTM3OCH6SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH6SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH6SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH6SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH6SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH6SRC. */ -#define BF_SIM_SOPT8_FTM3OCH6SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH6SRC) & BM_SIM_SOPT8_FTM3OCH6SRC) - -/*! @brief Set the FTM3OCH6SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH6SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH6SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT8, field FTM3OCH7SRC[31] (RW) - * - * Values: - * - 0 - FTM3_CH7 pin is output of FTM3 channel 7 output - * - 1 - FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 - * channel 1 output. - */ -/*@{*/ -#define BP_SIM_SOPT8_FTM3OCH7SRC (31U) /*!< Bit position for SIM_SOPT8_FTM3OCH7SRC. */ -#define BM_SIM_SOPT8_FTM3OCH7SRC (0x80000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH7SRC. */ -#define BS_SIM_SOPT8_FTM3OCH7SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH7SRC. */ - -/*! @brief Read current value of the SIM_SOPT8_FTM3OCH7SRC field. */ -#define BR_SIM_SOPT8_FTM3OCH7SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH7SRC)) - -/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH7SRC. */ -#define BF_SIM_SOPT8_FTM3OCH7SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH7SRC) & BM_SIM_SOPT8_FTM3OCH7SRC) - -/*! @brief Set the FTM3OCH7SRC field to a new value. */ -#define BW_SIM_SOPT8_FTM3OCH7SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH7SRC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SDID - System Device Identification Register - ******************************************************************************/ - -/*! - * @brief HW_SIM_SDID - System Device Identification Register (RO) - * - * Reset value: 0x00000E80U - */ -typedef union _hw_sim_sdid -{ - uint32_t U; - struct _hw_sim_sdid_bitfields - { - uint32_t PINID : 4; /*!< [3:0] Pincount identification */ - uint32_t FAMID : 3; /*!< [6:4] Kinetis family identification */ - uint32_t DIEID : 5; /*!< [11:7] Device Die ID */ - uint32_t REVID : 4; /*!< [15:12] Device revision number */ - uint32_t RESERVED0 : 4; /*!< [19:16] */ - uint32_t SERIESID : 4; /*!< [23:20] Kinetis Series ID */ - uint32_t SUBFAMID : 4; /*!< [27:24] Kinetis Sub-Family ID */ - uint32_t FAMILYID : 4; /*!< [31:28] Kinetis Family ID */ - } B; -} hw_sim_sdid_t; - -/*! - * @name Constants and macros for entire SIM_SDID register - */ -/*@{*/ -#define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U) - -#define HW_SIM_SDID(x) (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x)) -#define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_SDID bitfields - */ - -/*! - * @name Register SIM_SDID, field PINID[3:0] (RO) - * - * Specifies the pincount of the device. - * - * Values: - * - 0000 - Reserved - * - 0001 - Reserved - * - 0010 - 32-pin - * - 0011 - Reserved - * - 0100 - 48-pin - * - 0101 - 64-pin - * - 0110 - 80-pin - * - 0111 - 81-pin or 121-pin - * - 1000 - 100-pin - * - 1001 - 121-pin - * - 1010 - 144-pin - * - 1011 - Custom pinout (WLCSP) - * - 1100 - 169-pin - * - 1101 - Reserved - * - 1110 - 256-pin - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SIM_SDID_PINID (0U) /*!< Bit position for SIM_SDID_PINID. */ -#define BM_SIM_SDID_PINID (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */ -#define BS_SIM_SDID_PINID (4U) /*!< Bit field size in bits for SIM_SDID_PINID. */ - -/*! @brief Read current value of the SIM_SDID_PINID field. */ -#define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field FAMID[6:4] (RO) - * - * This field is maintained for compatibility only, but has been superceded by - * the SERIESID, FAMILYID and SUBFAMID fields in this register. - * - * Values: - * - 000 - K1x Family (without tamper) - * - 001 - K2x Family (without tamper) - * - 010 - K3x Family or K1x/K6x Family (with tamper) - * - 011 - K4x Family or K2x Family (with tamper) - * - 100 - K6x Family (without tamper) - * - 101 - K7x Family - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SIM_SDID_FAMID (4U) /*!< Bit position for SIM_SDID_FAMID. */ -#define BM_SIM_SDID_FAMID (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */ -#define BS_SIM_SDID_FAMID (3U) /*!< Bit field size in bits for SIM_SDID_FAMID. */ - -/*! @brief Read current value of the SIM_SDID_FAMID field. */ -#define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field DIEID[11:7] (RO) - * - * Specifies the silicon feature set identication number for the device. - */ -/*@{*/ -#define BP_SIM_SDID_DIEID (7U) /*!< Bit position for SIM_SDID_DIEID. */ -#define BM_SIM_SDID_DIEID (0x00000F80U) /*!< Bit mask for SIM_SDID_DIEID. */ -#define BS_SIM_SDID_DIEID (5U) /*!< Bit field size in bits for SIM_SDID_DIEID. */ - -/*! @brief Read current value of the SIM_SDID_DIEID field. */ -#define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field REVID[15:12] (RO) - * - * Specifies the silicon implementation number for the device. - */ -/*@{*/ -#define BP_SIM_SDID_REVID (12U) /*!< Bit position for SIM_SDID_REVID. */ -#define BM_SIM_SDID_REVID (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */ -#define BS_SIM_SDID_REVID (4U) /*!< Bit field size in bits for SIM_SDID_REVID. */ - -/*! @brief Read current value of the SIM_SDID_REVID field. */ -#define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field SERIESID[23:20] (RO) - * - * Specifies the Kinetis series of the device. - * - * Values: - * - 0000 - Kinetis K series - * - 0001 - Kinetis L series - * - 0101 - Kinetis W series - * - 0110 - Kinetis V series - */ -/*@{*/ -#define BP_SIM_SDID_SERIESID (20U) /*!< Bit position for SIM_SDID_SERIESID. */ -#define BM_SIM_SDID_SERIESID (0x00F00000U) /*!< Bit mask for SIM_SDID_SERIESID. */ -#define BS_SIM_SDID_SERIESID (4U) /*!< Bit field size in bits for SIM_SDID_SERIESID. */ - -/*! @brief Read current value of the SIM_SDID_SERIESID field. */ -#define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field SUBFAMID[27:24] (RO) - * - * Specifies the Kinetis sub-family of the device. - * - * Values: - * - 0000 - Kx0 Subfamily - * - 0001 - Kx1 Subfamily (tamper detect) - * - 0010 - Kx2 Subfamily - * - 0011 - Kx3 Subfamily (tamper detect) - * - 0100 - Kx4 Subfamily - * - 0101 - Kx5 Subfamily (tamper detect) - * - 0110 - Kx6 Subfamily - */ -/*@{*/ -#define BP_SIM_SDID_SUBFAMID (24U) /*!< Bit position for SIM_SDID_SUBFAMID. */ -#define BM_SIM_SDID_SUBFAMID (0x0F000000U) /*!< Bit mask for SIM_SDID_SUBFAMID. */ -#define BS_SIM_SDID_SUBFAMID (4U) /*!< Bit field size in bits for SIM_SDID_SUBFAMID. */ - -/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */ -#define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field FAMILYID[31:28] (RO) - * - * Specifies the Kinetis family of the device. - * - * Values: - * - 0001 - K1x Family - * - 0010 - K2x Family - * - 0011 - K3x Family - * - 0100 - K4x Family - * - 0110 - K6x Family - * - 0111 - K7x Family - */ -/*@{*/ -#define BP_SIM_SDID_FAMILYID (28U) /*!< Bit position for SIM_SDID_FAMILYID. */ -#define BM_SIM_SDID_FAMILYID (0xF0000000U) /*!< Bit mask for SIM_SDID_FAMILYID. */ -#define BS_SIM_SDID_FAMILYID (4U) /*!< Bit field size in bits for SIM_SDID_FAMILYID. */ - -/*! @brief Read current value of the SIM_SDID_FAMILYID field. */ -#define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC4 - System Clock Gating Control Register 4 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW) - * - * Reset value: 0xF0100030U - */ -typedef union _hw_sim_scgc4 -{ - uint32_t U; - struct _hw_sim_scgc4_bitfields - { - uint32_t RESERVED0 : 1; /*!< [0] */ - uint32_t EWMb : 1; /*!< [1] EWM Clock Gate Control */ - uint32_t RESERVED1 : 4; /*!< [5:2] */ - uint32_t I2C0b : 1; /*!< [6] I2C0 Clock Gate Control */ - uint32_t I2C1b : 1; /*!< [7] I2C1 Clock Gate Control */ - uint32_t RESERVED2 : 2; /*!< [9:8] */ - uint32_t UART0b : 1; /*!< [10] UART0 Clock Gate Control */ - uint32_t UART1b : 1; /*!< [11] UART1 Clock Gate Control */ - uint32_t UART2b : 1; /*!< [12] UART2 Clock Gate Control */ - uint32_t RESERVED3 : 5; /*!< [17:13] */ - uint32_t USBOTG : 1; /*!< [18] USB Clock Gate Control */ - uint32_t CMP : 1; /*!< [19] Comparator Clock Gate Control */ - uint32_t VREFb : 1; /*!< [20] VREF Clock Gate Control */ - uint32_t RESERVED4 : 11; /*!< [31:21] */ - } B; -} hw_sim_scgc4_t; - -/*! - * @name Constants and macros for entire SIM_SCGC4 register - */ -/*@{*/ -#define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U) - -#define HW_SIM_SCGC4(x) (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x)) -#define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U) -#define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v)) -#define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) | (v))) -#define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v))) -#define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC4 bitfields - */ - -/*! - * @name Register SIM_SCGC4, field EWM[1] (RW) - * - * This bit controls the clock gate to the EWM module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_EWM (1U) /*!< Bit position for SIM_SCGC4_EWM. */ -#define BM_SIM_SCGC4_EWM (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */ -#define BS_SIM_SCGC4_EWM (1U) /*!< Bit field size in bits for SIM_SCGC4_EWM. */ - -/*! @brief Read current value of the SIM_SCGC4_EWM field. */ -#define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM)) - -/*! @brief Format value for bitfield SIM_SCGC4_EWM. */ -#define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM) - -/*! @brief Set the EWM field to a new value. */ -#define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field I2C0[6] (RW) - * - * This bit controls the clock gate to the I 2 C0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_I2C0 (6U) /*!< Bit position for SIM_SCGC4_I2C0. */ -#define BM_SIM_SCGC4_I2C0 (0x00000040U) /*!< Bit mask for SIM_SCGC4_I2C0. */ -#define BS_SIM_SCGC4_I2C0 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C0. */ - -/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */ -#define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0)) - -/*! @brief Format value for bitfield SIM_SCGC4_I2C0. */ -#define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0) - -/*! @brief Set the I2C0 field to a new value. */ -#define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field I2C1[7] (RW) - * - * This bit controls the clock gate to the I 2 C1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_I2C1 (7U) /*!< Bit position for SIM_SCGC4_I2C1. */ -#define BM_SIM_SCGC4_I2C1 (0x00000080U) /*!< Bit mask for SIM_SCGC4_I2C1. */ -#define BS_SIM_SCGC4_I2C1 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C1. */ - -/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */ -#define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1)) - -/*! @brief Format value for bitfield SIM_SCGC4_I2C1. */ -#define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1) - -/*! @brief Set the I2C1 field to a new value. */ -#define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART0[10] (RW) - * - * This bit controls the clock gate to the UART0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART0 (10U) /*!< Bit position for SIM_SCGC4_UART0. */ -#define BM_SIM_SCGC4_UART0 (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */ -#define BS_SIM_SCGC4_UART0 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART0. */ - -/*! @brief Read current value of the SIM_SCGC4_UART0 field. */ -#define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART0. */ -#define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0) - -/*! @brief Set the UART0 field to a new value. */ -#define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART1[11] (RW) - * - * This bit controls the clock gate to the UART1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART1 (11U) /*!< Bit position for SIM_SCGC4_UART1. */ -#define BM_SIM_SCGC4_UART1 (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */ -#define BS_SIM_SCGC4_UART1 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART1. */ - -/*! @brief Read current value of the SIM_SCGC4_UART1 field. */ -#define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART1. */ -#define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1) - -/*! @brief Set the UART1 field to a new value. */ -#define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART2[12] (RW) - * - * This bit controls the clock gate to the UART2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART2 (12U) /*!< Bit position for SIM_SCGC4_UART2. */ -#define BM_SIM_SCGC4_UART2 (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */ -#define BS_SIM_SCGC4_UART2 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART2. */ - -/*! @brief Read current value of the SIM_SCGC4_UART2 field. */ -#define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART2. */ -#define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2) - -/*! @brief Set the UART2 field to a new value. */ -#define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field USBOTG[18] (RW) - * - * This bit controls the clock gate to the USB module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_USBOTG (18U) /*!< Bit position for SIM_SCGC4_USBOTG. */ -#define BM_SIM_SCGC4_USBOTG (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBOTG. */ -#define BS_SIM_SCGC4_USBOTG (1U) /*!< Bit field size in bits for SIM_SCGC4_USBOTG. */ - -/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */ -#define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG)) - -/*! @brief Format value for bitfield SIM_SCGC4_USBOTG. */ -#define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG) - -/*! @brief Set the USBOTG field to a new value. */ -#define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field CMP[19] (RW) - * - * This bit controls the clock gate to the comparator module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_CMP (19U) /*!< Bit position for SIM_SCGC4_CMP. */ -#define BM_SIM_SCGC4_CMP (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */ -#define BS_SIM_SCGC4_CMP (1U) /*!< Bit field size in bits for SIM_SCGC4_CMP. */ - -/*! @brief Read current value of the SIM_SCGC4_CMP field. */ -#define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP)) - -/*! @brief Format value for bitfield SIM_SCGC4_CMP. */ -#define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP) - -/*! @brief Set the CMP field to a new value. */ -#define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field VREF[20] (RW) - * - * This bit controls the clock gate to the VREF module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_VREF (20U) /*!< Bit position for SIM_SCGC4_VREF. */ -#define BM_SIM_SCGC4_VREF (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */ -#define BS_SIM_SCGC4_VREF (1U) /*!< Bit field size in bits for SIM_SCGC4_VREF. */ - -/*! @brief Read current value of the SIM_SCGC4_VREF field. */ -#define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF)) - -/*! @brief Format value for bitfield SIM_SCGC4_VREF. */ -#define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF) - -/*! @brief Set the VREF field to a new value. */ -#define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC5 - System Clock Gating Control Register 5 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW) - * - * Reset value: 0x00040182U - */ -typedef union _hw_sim_scgc5 -{ - uint32_t U; - struct _hw_sim_scgc5_bitfields - { - uint32_t LPTMR : 1; /*!< [0] Low Power Timer Access Control */ - uint32_t RESERVED0 : 8; /*!< [8:1] */ - uint32_t PORTAb : 1; /*!< [9] Port A Clock Gate Control */ - uint32_t PORTBb : 1; /*!< [10] Port B Clock Gate Control */ - uint32_t PORTCb : 1; /*!< [11] Port C Clock Gate Control */ - uint32_t PORTDb : 1; /*!< [12] Port D Clock Gate Control */ - uint32_t PORTEb : 1; /*!< [13] Port E Clock Gate Control */ - uint32_t RESERVED1 : 18; /*!< [31:14] */ - } B; -} hw_sim_scgc5_t; - -/*! - * @name Constants and macros for entire SIM_SCGC5 register - */ -/*@{*/ -#define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U) - -#define HW_SIM_SCGC5(x) (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x)) -#define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U) -#define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v)) -#define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) | (v))) -#define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v))) -#define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC5 bitfields - */ - -/*! - * @name Register SIM_SCGC5, field LPTMR[0] (RW) - * - * This bit controls software access to the Low Power Timer module. - * - * Values: - * - 0 - Access disabled - * - 1 - Access enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_LPTMR (0U) /*!< Bit position for SIM_SCGC5_LPTMR. */ -#define BM_SIM_SCGC5_LPTMR (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTMR. */ -#define BS_SIM_SCGC5_LPTMR (1U) /*!< Bit field size in bits for SIM_SCGC5_LPTMR. */ - -/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */ -#define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR)) - -/*! @brief Format value for bitfield SIM_SCGC5_LPTMR. */ -#define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR) - -/*! @brief Set the LPTMR field to a new value. */ -#define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTA[9] (RW) - * - * This bit controls the clock gate to the Port A module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTA (9U) /*!< Bit position for SIM_SCGC5_PORTA. */ -#define BM_SIM_SCGC5_PORTA (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */ -#define BS_SIM_SCGC5_PORTA (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTA. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTA field. */ -#define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTA. */ -#define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA) - -/*! @brief Set the PORTA field to a new value. */ -#define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTB[10] (RW) - * - * This bit controls the clock gate to the Port B module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTB (10U) /*!< Bit position for SIM_SCGC5_PORTB. */ -#define BM_SIM_SCGC5_PORTB (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */ -#define BS_SIM_SCGC5_PORTB (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTB. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTB field. */ -#define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTB. */ -#define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB) - -/*! @brief Set the PORTB field to a new value. */ -#define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTC[11] (RW) - * - * This bit controls the clock gate to the Port C module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTC (11U) /*!< Bit position for SIM_SCGC5_PORTC. */ -#define BM_SIM_SCGC5_PORTC (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */ -#define BS_SIM_SCGC5_PORTC (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTC. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTC field. */ -#define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTC. */ -#define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC) - -/*! @brief Set the PORTC field to a new value. */ -#define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTD[12] (RW) - * - * This bit controls the clock gate to the Port D module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTD (12U) /*!< Bit position for SIM_SCGC5_PORTD. */ -#define BM_SIM_SCGC5_PORTD (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */ -#define BS_SIM_SCGC5_PORTD (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTD. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTD field. */ -#define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTD. */ -#define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD) - -/*! @brief Set the PORTD field to a new value. */ -#define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTE[13] (RW) - * - * This bit controls the clock gate to the Port E module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTE (13U) /*!< Bit position for SIM_SCGC5_PORTE. */ -#define BM_SIM_SCGC5_PORTE (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */ -#define BS_SIM_SCGC5_PORTE (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTE. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTE field. */ -#define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTE. */ -#define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE) - -/*! @brief Set the PORTE field to a new value. */ -#define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC6 - System Clock Gating Control Register 6 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW) - * - * Reset value: 0x40000001U - */ -typedef union _hw_sim_scgc6 -{ - uint32_t U; - struct _hw_sim_scgc6_bitfields - { - uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */ - uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */ - uint32_t RESERVED0 : 4; /*!< [5:2] */ - uint32_t FTM3b : 1; /*!< [6] FTM3 Clock Gate Control */ - uint32_t ADC1b : 1; /*!< [7] ADC1 Clock Gate Control */ - uint32_t DAC1b : 1; /*!< [8] DAC1 Clock Gate Control */ - uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */ - uint32_t LPUART0b : 1; /*!< [10] LPUART0 Clock Gate Control */ - uint32_t RESERVED1 : 1; /*!< [11] */ - uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */ - uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */ - uint32_t RESERVED2 : 1; /*!< [14] */ - uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */ - uint32_t RESERVED3 : 2; /*!< [17:16] */ - uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */ - uint32_t RESERVED4 : 3; /*!< [21:19] */ - uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */ - uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */ - uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */ - uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */ - uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */ - uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */ - uint32_t RESERVED5 : 1; /*!< [28] */ - uint32_t RTCb : 1; /*!< [29] RTC Access Control */ - uint32_t RESERVED6 : 1; /*!< [30] */ - uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */ - } B; -} hw_sim_scgc6_t; - -/*! - * @name Constants and macros for entire SIM_SCGC6 register - */ -/*@{*/ -#define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU) - -#define HW_SIM_SCGC6(x) (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x)) -#define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U) -#define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v)) -#define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) | (v))) -#define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v))) -#define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC6 bitfields - */ - -/*! - * @name Register SIM_SCGC6, field FTF[0] (RW) - * - * This bit controls the clock gate to the flash memory. Flash reads are still - * supported while the flash memory is clock gated, but entry into low power modes - * and HSRUN mode is blocked. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTF (0U) /*!< Bit position for SIM_SCGC6_FTF. */ -#define BM_SIM_SCGC6_FTF (0x00000001U) /*!< Bit mask for SIM_SCGC6_FTF. */ -#define BS_SIM_SCGC6_FTF (1U) /*!< Bit field size in bits for SIM_SCGC6_FTF. */ - -/*! @brief Read current value of the SIM_SCGC6_FTF field. */ -#define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTF. */ -#define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF) - -/*! @brief Set the FTF field to a new value. */ -#define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field DMAMUX[1] (RW) - * - * This bit controls the clock gate to the DMA Mux module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_DMAMUX (1U) /*!< Bit position for SIM_SCGC6_DMAMUX. */ -#define BM_SIM_SCGC6_DMAMUX (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX. */ -#define BS_SIM_SCGC6_DMAMUX (1U) /*!< Bit field size in bits for SIM_SCGC6_DMAMUX. */ - -/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */ -#define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX)) - -/*! @brief Format value for bitfield SIM_SCGC6_DMAMUX. */ -#define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX) - -/*! @brief Set the DMAMUX field to a new value. */ -#define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM3[6] (RW) - * - * This bit controls the clock gate to the FTM3 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM3 (6U) /*!< Bit position for SIM_SCGC6_FTM3. */ -#define BM_SIM_SCGC6_FTM3 (0x00000040U) /*!< Bit mask for SIM_SCGC6_FTM3. */ -#define BS_SIM_SCGC6_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM3. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM3 field. */ -#define BR_SIM_SCGC6_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM3)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM3. */ -#define BF_SIM_SCGC6_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM3) & BM_SIM_SCGC6_FTM3) - -/*! @brief Set the FTM3 field to a new value. */ -#define BW_SIM_SCGC6_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM3) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field ADC1[7] (RW) - * - * This bit controls the clock gate to the ADC1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_ADC1 (7U) /*!< Bit position for SIM_SCGC6_ADC1. */ -#define BM_SIM_SCGC6_ADC1 (0x00000080U) /*!< Bit mask for SIM_SCGC6_ADC1. */ -#define BS_SIM_SCGC6_ADC1 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC1. */ - -/*! @brief Read current value of the SIM_SCGC6_ADC1 field. */ -#define BR_SIM_SCGC6_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC1)) - -/*! @brief Format value for bitfield SIM_SCGC6_ADC1. */ -#define BF_SIM_SCGC6_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC1) & BM_SIM_SCGC6_ADC1) - -/*! @brief Set the ADC1 field to a new value. */ -#define BW_SIM_SCGC6_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field DAC1[8] (RW) - * - * This bit controls the clock gate to the DAC1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_DAC1 (8U) /*!< Bit position for SIM_SCGC6_DAC1. */ -#define BM_SIM_SCGC6_DAC1 (0x00000100U) /*!< Bit mask for SIM_SCGC6_DAC1. */ -#define BS_SIM_SCGC6_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC1. */ - -/*! @brief Read current value of the SIM_SCGC6_DAC1 field. */ -#define BR_SIM_SCGC6_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC1)) - -/*! @brief Format value for bitfield SIM_SCGC6_DAC1. */ -#define BF_SIM_SCGC6_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC1) & BM_SIM_SCGC6_DAC1) - -/*! @brief Set the DAC1 field to a new value. */ -#define BW_SIM_SCGC6_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field RNGA[9] (RW) - * - * This bit controls the clock gate to the RNGA module. - */ -/*@{*/ -#define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */ -#define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */ -#define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */ - -/*! @brief Read current value of the SIM_SCGC6_RNGA field. */ -#define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA)) - -/*! @brief Format value for bitfield SIM_SCGC6_RNGA. */ -#define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA) - -/*! @brief Set the RNGA field to a new value. */ -#define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field LPUART0[10] (RW) - * - * This bit controls the clock gate to the LPUART0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_LPUART0 (10U) /*!< Bit position for SIM_SCGC6_LPUART0. */ -#define BM_SIM_SCGC6_LPUART0 (0x00000400U) /*!< Bit mask for SIM_SCGC6_LPUART0. */ -#define BS_SIM_SCGC6_LPUART0 (1U) /*!< Bit field size in bits for SIM_SCGC6_LPUART0. */ - -/*! @brief Read current value of the SIM_SCGC6_LPUART0 field. */ -#define BR_SIM_SCGC6_LPUART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_LPUART0)) - -/*! @brief Format value for bitfield SIM_SCGC6_LPUART0. */ -#define BF_SIM_SCGC6_LPUART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_LPUART0) & BM_SIM_SCGC6_LPUART0) - -/*! @brief Set the LPUART0 field to a new value. */ -#define BW_SIM_SCGC6_LPUART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_LPUART0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field SPI0[12] (RW) - * - * This bit controls the clock gate to the SPI0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_SPI0 (12U) /*!< Bit position for SIM_SCGC6_SPI0. */ -#define BM_SIM_SCGC6_SPI0 (0x00001000U) /*!< Bit mask for SIM_SCGC6_SPI0. */ -#define BS_SIM_SCGC6_SPI0 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI0. */ - -/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */ -#define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0)) - -/*! @brief Format value for bitfield SIM_SCGC6_SPI0. */ -#define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0) - -/*! @brief Set the SPI0 field to a new value. */ -#define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field SPI1[13] (RW) - * - * This bit controls the clock gate to the SPI1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_SPI1 (13U) /*!< Bit position for SIM_SCGC6_SPI1. */ -#define BM_SIM_SCGC6_SPI1 (0x00002000U) /*!< Bit mask for SIM_SCGC6_SPI1. */ -#define BS_SIM_SCGC6_SPI1 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI1. */ - -/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */ -#define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1)) - -/*! @brief Format value for bitfield SIM_SCGC6_SPI1. */ -#define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1) - -/*! @brief Set the SPI1 field to a new value. */ -#define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field I2S[15] (RW) - * - * This bit controls the clock gate to the I 2 S module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_I2S (15U) /*!< Bit position for SIM_SCGC6_I2S. */ -#define BM_SIM_SCGC6_I2S (0x00008000U) /*!< Bit mask for SIM_SCGC6_I2S. */ -#define BS_SIM_SCGC6_I2S (1U) /*!< Bit field size in bits for SIM_SCGC6_I2S. */ - -/*! @brief Read current value of the SIM_SCGC6_I2S field. */ -#define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S)) - -/*! @brief Format value for bitfield SIM_SCGC6_I2S. */ -#define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S) - -/*! @brief Set the I2S field to a new value. */ -#define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field CRC[18] (RW) - * - * This bit controls the clock gate to the CRC module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_CRC (18U) /*!< Bit position for SIM_SCGC6_CRC. */ -#define BM_SIM_SCGC6_CRC (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */ -#define BS_SIM_SCGC6_CRC (1U) /*!< Bit field size in bits for SIM_SCGC6_CRC. */ - -/*! @brief Read current value of the SIM_SCGC6_CRC field. */ -#define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC)) - -/*! @brief Format value for bitfield SIM_SCGC6_CRC. */ -#define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC) - -/*! @brief Set the CRC field to a new value. */ -#define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field PDB[22] (RW) - * - * This bit controls the clock gate to the PDB module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_PDB (22U) /*!< Bit position for SIM_SCGC6_PDB. */ -#define BM_SIM_SCGC6_PDB (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */ -#define BS_SIM_SCGC6_PDB (1U) /*!< Bit field size in bits for SIM_SCGC6_PDB. */ - -/*! @brief Read current value of the SIM_SCGC6_PDB field. */ -#define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB)) - -/*! @brief Format value for bitfield SIM_SCGC6_PDB. */ -#define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB) - -/*! @brief Set the PDB field to a new value. */ -#define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field PIT[23] (RW) - * - * This bit controls the clock gate to the PIT module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_PIT (23U) /*!< Bit position for SIM_SCGC6_PIT. */ -#define BM_SIM_SCGC6_PIT (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */ -#define BS_SIM_SCGC6_PIT (1U) /*!< Bit field size in bits for SIM_SCGC6_PIT. */ - -/*! @brief Read current value of the SIM_SCGC6_PIT field. */ -#define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT)) - -/*! @brief Format value for bitfield SIM_SCGC6_PIT. */ -#define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT) - -/*! @brief Set the PIT field to a new value. */ -#define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM0[24] (RW) - * - * This bit controls the clock gate to the FTM0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM0 (24U) /*!< Bit position for SIM_SCGC6_FTM0. */ -#define BM_SIM_SCGC6_FTM0 (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */ -#define BS_SIM_SCGC6_FTM0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM0. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */ -#define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM0. */ -#define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0) - -/*! @brief Set the FTM0 field to a new value. */ -#define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM1[25] (RW) - * - * This bit controls the clock gate to the FTM1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM1 (25U) /*!< Bit position for SIM_SCGC6_FTM1. */ -#define BM_SIM_SCGC6_FTM1 (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */ -#define BS_SIM_SCGC6_FTM1 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM1. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */ -#define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM1. */ -#define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1) - -/*! @brief Set the FTM1 field to a new value. */ -#define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM2[26] (RW) - * - * This bit controls the clock gate to the FTM2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM2 (26U) /*!< Bit position for SIM_SCGC6_FTM2. */ -#define BM_SIM_SCGC6_FTM2 (0x04000000U) /*!< Bit mask for SIM_SCGC6_FTM2. */ -#define BS_SIM_SCGC6_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM2. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */ -#define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM2. */ -#define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2) - -/*! @brief Set the FTM2 field to a new value. */ -#define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field ADC0[27] (RW) - * - * This bit controls the clock gate to the ADC0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_ADC0 (27U) /*!< Bit position for SIM_SCGC6_ADC0. */ -#define BM_SIM_SCGC6_ADC0 (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */ -#define BS_SIM_SCGC6_ADC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC0. */ - -/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */ -#define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0)) - -/*! @brief Format value for bitfield SIM_SCGC6_ADC0. */ -#define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0) - -/*! @brief Set the ADC0 field to a new value. */ -#define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field RTC[29] (RW) - * - * This bit controls software access and interrupts to the RTC module. - * - * Values: - * - 0 - Access and interrupts disabled - * - 1 - Access and interrupts enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_RTC (29U) /*!< Bit position for SIM_SCGC6_RTC. */ -#define BM_SIM_SCGC6_RTC (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */ -#define BS_SIM_SCGC6_RTC (1U) /*!< Bit field size in bits for SIM_SCGC6_RTC. */ - -/*! @brief Read current value of the SIM_SCGC6_RTC field. */ -#define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC)) - -/*! @brief Format value for bitfield SIM_SCGC6_RTC. */ -#define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC) - -/*! @brief Set the RTC field to a new value. */ -#define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field DAC0[31] (RW) - * - * This bit controls the clock gate to the DAC0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_DAC0 (31U) /*!< Bit position for SIM_SCGC6_DAC0. */ -#define BM_SIM_SCGC6_DAC0 (0x80000000U) /*!< Bit mask for SIM_SCGC6_DAC0. */ -#define BS_SIM_SCGC6_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC0. */ - -/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */ -#define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0)) - -/*! @brief Format value for bitfield SIM_SCGC6_DAC0. */ -#define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0) - -/*! @brief Set the DAC0 field to a new value. */ -#define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC7 - System Clock Gating Control Register 7 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW) - * - * Reset value: 0x00000002U - */ -typedef union _hw_sim_scgc7 -{ - uint32_t U; - struct _hw_sim_scgc7_bitfields - { - uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */ - uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */ - uint32_t RESERVED0 : 30; /*!< [31:2] */ - } B; -} hw_sim_scgc7_t; - -/*! - * @name Constants and macros for entire SIM_SCGC7 register - */ -/*@{*/ -#define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U) - -#define HW_SIM_SCGC7(x) (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x)) -#define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U) -#define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v)) -#define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) | (v))) -#define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v))) -#define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC7 bitfields - */ - -/*! - * @name Register SIM_SCGC7, field FLEXBUS[0] (RW) - * - * This bit controls the clock gate to the FlexBus module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */ -#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */ -#define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */ - -/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */ -#define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS)) - -/*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */ -#define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS) - -/*! @brief Set the FLEXBUS field to a new value. */ -#define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC7, field DMA[1] (RW) - * - * This bit controls the clock gate to the DMA module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC7_DMA (1U) /*!< Bit position for SIM_SCGC7_DMA. */ -#define BM_SIM_SCGC7_DMA (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */ -#define BS_SIM_SCGC7_DMA (1U) /*!< Bit field size in bits for SIM_SCGC7_DMA. */ - -/*! @brief Read current value of the SIM_SCGC7_DMA field. */ -#define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA)) - -/*! @brief Format value for bitfield SIM_SCGC7_DMA. */ -#define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA) - -/*! @brief Set the DMA field to a new value. */ -#define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_CLKDIV1 - System Clock Divider Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW) - * - * Reset value: 0x00010000U - * - * When updating CLKDIV1, update all fields using the one write command. - * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the - * write to be ignored. The maximum divide ratio that can be programmed between - * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals - * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide - * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR - * mode. - */ -typedef union _hw_sim_clkdiv1 -{ - uint32_t U; - struct _hw_sim_clkdiv1_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */ - uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */ - uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */ - uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */ - } B; -} hw_sim_clkdiv1_t; - -/*! - * @name Constants and macros for entire SIM_CLKDIV1 register - */ -/*@{*/ -#define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U) - -#define HW_SIM_CLKDIV1(x) (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x)) -#define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U) -#define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v)) -#define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) | (v))) -#define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v))) -#define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_CLKDIV1 bitfields - */ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW) - * - * This field sets the divide value for the flash clock from MCGOUTCLK. At the - * end of reset, it is loaded with either 0001 or 1111 depending on - * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock - * frequency. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV4 (16U) /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */ -#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */ -#define BS_SIM_CLKDIV1_OUTDIV4 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */ -#define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */ -#define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4) - -/*! @brief Set the OUTDIV4 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v))) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW) - * - * This field sets the divide value for the FlexBus clock (external pin FB_CLK) - * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 - * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer - * divide of the system clock frequency. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */ -#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */ -#define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */ -#define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */ -#define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3) - -/*! @brief Set the OUTDIV3 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v))) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW) - * - * This field sets the divide value for the bus clock from MCGOUTCLK. At the end - * of reset, it is loaded with either 0000 or 0111 depending on - * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock - * frequency. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV2 (24U) /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */ -#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */ -#define BS_SIM_CLKDIV1_OUTDIV2 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */ -#define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */ -#define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2) - -/*! @brief Set the OUTDIV2 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v))) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW) - * - * This field sets the divide value for the core/system clock from MCGOUTCLK. At - * the end of reset, it is loaded with either 0000 or 0111 depending on - * FTF_FOPT[LPBOOT]. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV1 (28U) /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */ -#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */ -#define BS_SIM_CLKDIV1_OUTDIV1 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */ -#define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */ -#define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1) - -/*! @brief Set the OUTDIV1 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_CLKDIV2 - System Clock Divider Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_clkdiv2 -{ - uint32_t U; - struct _hw_sim_clkdiv2_bitfields - { - uint32_t USBFRAC : 1; /*!< [0] USB clock divider fraction */ - uint32_t USBDIV : 3; /*!< [3:1] USB clock divider divisor */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_sim_clkdiv2_t; - -/*! - * @name Constants and macros for entire SIM_CLKDIV2 register - */ -/*@{*/ -#define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U) - -#define HW_SIM_CLKDIV2(x) (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x)) -#define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U) -#define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v)) -#define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) | (v))) -#define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v))) -#define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_CLKDIV2 bitfields - */ - -/*! - * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW) - * - * This field sets the fraction multiply value for the fractional clock divider - * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = - * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] - */ -/*@{*/ -#define BP_SIM_CLKDIV2_USBFRAC (0U) /*!< Bit position for SIM_CLKDIV2_USBFRAC. */ -#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFRAC. */ -#define BS_SIM_CLKDIV2_USBFRAC (1U) /*!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. */ - -/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */ -#define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC)) - -/*! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. */ -#define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC) - -/*! @brief Set the USBFRAC field to a new value. */ -#define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW) - * - * This field sets the divide value for the fractional clock divider when the - * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider - * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] - */ -/*@{*/ -#define BP_SIM_CLKDIV2_USBDIV (1U) /*!< Bit position for SIM_CLKDIV2_USBDIV. */ -#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBDIV. */ -#define BS_SIM_CLKDIV2_USBDIV (3U) /*!< Bit field size in bits for SIM_CLKDIV2_USBDIV. */ - -/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */ -#define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV) - -/*! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. */ -#define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV) - -/*! @brief Set the USBDIV field to a new value. */ -#define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_FCFG1 - Flash Configuration Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW) - * - * Reset value: 0x0F0F0F00U - * - * The EESIZE and DEPART filelds are not applicable. - */ -typedef union _hw_sim_fcfg1 -{ - uint32_t U; - struct _hw_sim_fcfg1_bitfields - { - uint32_t FLASHDIS : 1; /*!< [0] Flash Disable */ - uint32_t FLASHDOZE : 1; /*!< [1] Flash Doze */ - uint32_t RESERVED0 : 22; /*!< [23:2] */ - uint32_t PFSIZE : 4; /*!< [27:24] Program flash size */ - uint32_t RESERVED1 : 4; /*!< [31:28] */ - } B; -} hw_sim_fcfg1_t; - -/*! - * @name Constants and macros for entire SIM_FCFG1 register - */ -/*@{*/ -#define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU) - -#define HW_SIM_FCFG1(x) (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x)) -#define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U) -#define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v)) -#define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) | (v))) -#define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v))) -#define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_FCFG1 bitfields - */ - -/*! - * @name Register SIM_FCFG1, field FLASHDIS[0] (RW) - * - * Flash accesses are disabled (and generate a bus error) and the Flash memory - * is placed in a low power state. This bit should not be changed during VLP - * modes. Relocate the interrupt vectors out of Flash memory before disabling the - * Flash. - * - * Values: - * - 0 - Flash is enabled - * - 1 - Flash is disabled - */ -/*@{*/ -#define BP_SIM_FCFG1_FLASHDIS (0U) /*!< Bit position for SIM_FCFG1_FLASHDIS. */ -#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /*!< Bit mask for SIM_FCFG1_FLASHDIS. */ -#define BS_SIM_FCFG1_FLASHDIS (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDIS. */ - -/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */ -#define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS)) - -/*! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. */ -#define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS) - -/*! @brief Set the FLASHDIS field to a new value. */ -#define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v)) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW) - * - * When set, Flash memory is disabled for the duration of Wait mode. An attempt - * by the DMA or other bus master to access the Flash when the Flash is disabled - * will result in a bus error. This bit should be clear during VLP modes. The - * Flash will be automatically enabled again at the end of Wait mode so interrupt - * vectors do not need to be relocated out of Flash memory. The wakeup time from - * Wait mode is extended when this bit is set. - * - * Values: - * - 0 - Flash remains enabled during Wait mode - * - 1 - Flash is disabled for the duration of Wait mode - */ -/*@{*/ -#define BP_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit position for SIM_FCFG1_FLASHDOZE. */ -#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /*!< Bit mask for SIM_FCFG1_FLASHDOZE. */ -#define BS_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. */ - -/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */ -#define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE)) - -/*! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. */ -#define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE) - -/*! @brief Set the FLASHDOZE field to a new value. */ -#define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v)) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO) - * - * This field specifies the amount of program flash memory available on the - * device . Undefined values are reserved. - * - * Values: - * - 0011 - 32 KB of program flash memory - * - 0101 - 64 KB of program flash memory - * - 0111 - 128 KB of program flash memory - * - 1001 - 256 KB of program flash memory - * - 1011 - 512 KB of program flash memory - * - 1101 - 1024 KB of program flash memory - * - 1111 - 512 KB of program flash memory - */ -/*@{*/ -#define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */ -#define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */ -#define BS_SIM_FCFG1_PFSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */ - -/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */ -#define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE) -/*@}*/ - -/******************************************************************************* - * HW_SIM_FCFG2 - Flash Configuration Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO) - * - * Reset value: 0x7FFF0000U - */ -typedef union _hw_sim_fcfg2 -{ - uint32_t U; - struct _hw_sim_fcfg2_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t MAXADDR1 : 7; /*!< [22:16] Max address block 1 */ - uint32_t RESERVED1 : 1; /*!< [23] */ - uint32_t MAXADDR0 : 7; /*!< [30:24] Max address block 0 */ - uint32_t RESERVED2 : 1; /*!< [31] */ - } B; -} hw_sim_fcfg2_t; - -/*! - * @name Constants and macros for entire SIM_FCFG2 register - */ -/*@{*/ -#define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U) - -#define HW_SIM_FCFG2(x) (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x)) -#define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_FCFG2 bitfields - */ - -/*! - * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO) - * - * This field equals zero if there is only one program flash block, otherwise it - * equals the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 - * = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. - * This would be the MAXADDR1 value for a device with 512 KB program flash memory - * across two flash blocks and no FlexNVM. - */ -/*@{*/ -#define BP_SIM_FCFG2_MAXADDR1 (16U) /*!< Bit position for SIM_FCFG2_MAXADDR1. */ -#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR1. */ -#define BS_SIM_FCFG2_MAXADDR1 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR1. */ - -/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */ -#define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1) -/*@}*/ - -/*! - * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO) - * - * This field concatenated with 13 trailing zeros indicates the first invalid - * address of each program flash block. For example, if MAXADDR0 = 0x20 the first - * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 - * value for a device with 256 KB program flash in flash block 0. - */ -/*@{*/ -#define BP_SIM_FCFG2_MAXADDR0 (24U) /*!< Bit position for SIM_FCFG2_MAXADDR0. */ -#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR0. */ -#define BS_SIM_FCFG2_MAXADDR0 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR0. */ - -/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */ -#define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDH - Unique Identification Register High - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDH - Unique Identification Register High (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidh -{ - uint32_t U; - struct _hw_sim_uidh_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidh_t; - -/*! - * @name Constants and macros for entire SIM_UIDH register - */ -/*@{*/ -#define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U) - -#define HW_SIM_UIDH(x) (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x)) -#define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDH bitfields - */ - -/*! - * @name Register SIM_UIDH, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDH_UID (0U) /*!< Bit position for SIM_UIDH_UID. */ -#define BM_SIM_UIDH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */ -#define BS_SIM_UIDH_UID (32U) /*!< Bit field size in bits for SIM_UIDH_UID. */ - -/*! @brief Read current value of the SIM_UIDH_UID field. */ -#define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDMH - Unique Identification Register Mid-High - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidmh -{ - uint32_t U; - struct _hw_sim_uidmh_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidmh_t; - -/*! - * @name Constants and macros for entire SIM_UIDMH register - */ -/*@{*/ -#define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U) - -#define HW_SIM_UIDMH(x) (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x)) -#define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDMH bitfields - */ - -/*! - * @name Register SIM_UIDMH, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDMH_UID (0U) /*!< Bit position for SIM_UIDMH_UID. */ -#define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */ -#define BS_SIM_UIDMH_UID (32U) /*!< Bit field size in bits for SIM_UIDMH_UID. */ - -/*! @brief Read current value of the SIM_UIDMH_UID field. */ -#define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDML - Unique Identification Register Mid Low - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidml -{ - uint32_t U; - struct _hw_sim_uidml_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidml_t; - -/*! - * @name Constants and macros for entire SIM_UIDML register - */ -/*@{*/ -#define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU) - -#define HW_SIM_UIDML(x) (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x)) -#define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDML bitfields - */ - -/*! - * @name Register SIM_UIDML, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDML_UID (0U) /*!< Bit position for SIM_UIDML_UID. */ -#define BM_SIM_UIDML_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */ -#define BS_SIM_UIDML_UID (32U) /*!< Bit field size in bits for SIM_UIDML_UID. */ - -/*! @brief Read current value of the SIM_UIDML_UID field. */ -#define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDL - Unique Identification Register Low - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDL - Unique Identification Register Low (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidl -{ - uint32_t U; - struct _hw_sim_uidl_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidl_t; - -/*! - * @name Constants and macros for entire SIM_UIDL register - */ -/*@{*/ -#define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U) - -#define HW_SIM_UIDL(x) (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x)) -#define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDL bitfields - */ - -/*! - * @name Register SIM_UIDL, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDL_UID (0U) /*!< Bit position for SIM_UIDL_UID. */ -#define BM_SIM_UIDL_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */ -#define BS_SIM_UIDL_UID (32U) /*!< Bit field size in bits for SIM_UIDL_UID. */ - -/*! @brief Read current value of the SIM_UIDL_UID field. */ -#define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U) -/*@}*/ - -/******************************************************************************* - * hw_sim_t - module struct - ******************************************************************************/ -/*! - * @brief All SIM module registers. - */ -#pragma pack(1) -typedef struct _hw_sim -{ - __IO hw_sim_sopt1_t SOPT1; /*!< [0x0] System Options Register 1 */ - __IO hw_sim_sopt1cfg_t SOPT1CFG; /*!< [0x4] SOPT1 Configuration Register */ - uint8_t _reserved0[4092]; - __IO hw_sim_sopt2_t SOPT2; /*!< [0x1004] System Options Register 2 */ - uint8_t _reserved1[4]; - __IO hw_sim_sopt4_t SOPT4; /*!< [0x100C] System Options Register 4 */ - __IO hw_sim_sopt5_t SOPT5; /*!< [0x1010] System Options Register 5 */ - uint8_t _reserved2[4]; - __IO hw_sim_sopt7_t SOPT7; /*!< [0x1018] System Options Register 7 */ - __IO hw_sim_sopt8_t SOPT8; /*!< [0x101C] System Options Register 8 */ - uint8_t _reserved3[4]; - __I hw_sim_sdid_t SDID; /*!< [0x1024] System Device Identification Register */ - uint8_t _reserved4[12]; - __IO hw_sim_scgc4_t SCGC4; /*!< [0x1034] System Clock Gating Control Register 4 */ - __IO hw_sim_scgc5_t SCGC5; /*!< [0x1038] System Clock Gating Control Register 5 */ - __IO hw_sim_scgc6_t SCGC6; /*!< [0x103C] System Clock Gating Control Register 6 */ - __IO hw_sim_scgc7_t SCGC7; /*!< [0x1040] System Clock Gating Control Register 7 */ - __IO hw_sim_clkdiv1_t CLKDIV1; /*!< [0x1044] System Clock Divider Register 1 */ - __IO hw_sim_clkdiv2_t CLKDIV2; /*!< [0x1048] System Clock Divider Register 2 */ - __IO hw_sim_fcfg1_t FCFG1; /*!< [0x104C] Flash Configuration Register 1 */ - __I hw_sim_fcfg2_t FCFG2; /*!< [0x1050] Flash Configuration Register 2 */ - __I hw_sim_uidh_t UIDH; /*!< [0x1054] Unique Identification Register High */ - __I hw_sim_uidmh_t UIDMH; /*!< [0x1058] Unique Identification Register Mid-High */ - __I hw_sim_uidml_t UIDML; /*!< [0x105C] Unique Identification Register Mid Low */ - __I hw_sim_uidl_t UIDL; /*!< [0x1060] Unique Identification Register Low */ -} hw_sim_t; -#pragma pack() - -/*! @brief Macro to access all SIM registers. */ -/*! @param x SIM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SIM(SIM_BASE). */ -#define HW_SIM(x) (*(hw_sim_t *)(x)) - -#endif /* __HW_SIM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h deleted file mode 100644 index b18565b003f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h +++ /dev/null @@ -1,597 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SMC_REGISTERS_H__ -#define __HW_SMC_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 SMC - * - * System Mode Controller - * - * Registers defined in this header file: - * - HW_SMC_PMPROT - Power Mode Protection register - * - HW_SMC_PMCTRL - Power Mode Control register - * - HW_SMC_STOPCTRL - Stop Control Register - * - HW_SMC_PMSTAT - Power Mode Status register - * - * - hw_smc_t - Struct containing all module registers. - */ - -#define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */ - -/******************************************************************************* - * HW_SMC_PMPROT - Power Mode Protection register - ******************************************************************************/ - -/*! - * @brief HW_SMC_PMPROT - Power Mode Protection register (RW) - * - * Reset value: 0x00U - * - * This register provides protection for entry into any low-power run or stop - * mode. The enabling of the low-power run or stop mode occurs by configuring the - * Power Mode Control register (PMCTRL). The PMPROT register can be written only - * once after any system reset. If the MCU is configured for a disallowed or - * reserved power mode, the MCU remains in its current power mode. For example, if the - * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using - * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is - * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by - * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types - * that do not trigger Chip Reset not VLLS. See the Reset section details for more - * information. - */ -typedef union _hw_smc_pmprot -{ - uint8_t U; - struct _hw_smc_pmprot_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */ - uint8_t RESERVED1 : 1; /*!< [2] */ - uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */ - uint8_t RESERVED2 : 1; /*!< [4] */ - uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */ - uint8_t RESERVED3 : 1; /*!< [6] */ - uint8_t AHSRUN : 1; /*!< [7] Allow High Speed Run mode */ - } B; -} hw_smc_pmprot_t; - -/*! - * @name Constants and macros for entire SMC_PMPROT register - */ -/*@{*/ -#define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U) - -#define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x)) -#define HW_SMC_PMPROT_RD(x) (HW_SMC_PMPROT(x).U) -#define HW_SMC_PMPROT_WR(x, v) (HW_SMC_PMPROT(x).U = (v)) -#define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v))) -#define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v))) -#define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SMC_PMPROT bitfields - */ - -/*! - * @name Register SMC_PMPROT, field AVLLS[1] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write once - * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). - * - * Values: - * - 0 - Any VLLSx mode is not allowed - * - 1 - Any VLLSx mode is allowed - */ -/*@{*/ -#define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */ -#define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */ -#define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */ - -/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */ -#define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS)) - -/*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */ -#define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS) - -/*! @brief Set the AVLLS field to a new value. */ -#define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v)) -/*@}*/ - -/*! - * @name Register SMC_PMPROT, field ALLS[3] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write-once - * field allows the MCU to enter any low-leakage stop mode (LLS). - * - * Values: - * - 0 - Any LLSx mode is not allowed - * - 1 - Any LLSx mode is allowed - */ -/*@{*/ -#define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */ -#define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */ -#define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */ - -/*! @brief Read current value of the SMC_PMPROT_ALLS field. */ -#define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS)) - -/*! @brief Format value for bitfield SMC_PMPROT_ALLS. */ -#define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS) - -/*! @brief Set the ALLS field to a new value. */ -#define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v)) -/*@}*/ - -/*! - * @name Register SMC_PMPROT, field AVLP[5] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write-once - * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). - * - * Values: - * - 0 - VLPR, VLPW, and VLPS are not allowed. - * - 1 - VLPR, VLPW, and VLPS are allowed. - */ -/*@{*/ -#define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */ -#define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */ -#define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */ - -/*! @brief Read current value of the SMC_PMPROT_AVLP field. */ -#define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP)) - -/*! @brief Format value for bitfield SMC_PMPROT_AVLP. */ -#define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP) - -/*! @brief Set the AVLP field to a new value. */ -#define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v)) -/*@}*/ - -/*! - * @name Register SMC_PMPROT, field AHSRUN[7] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write-once - * field allows the MCU to enter High Speed Run mode (HSRUN). - * - * Values: - * - 0 - HSRUN is not allowed - * - 1 - HSRUN is allowed - */ -/*@{*/ -#define BP_SMC_PMPROT_AHSRUN (7U) /*!< Bit position for SMC_PMPROT_AHSRUN. */ -#define BM_SMC_PMPROT_AHSRUN (0x80U) /*!< Bit mask for SMC_PMPROT_AHSRUN. */ -#define BS_SMC_PMPROT_AHSRUN (1U) /*!< Bit field size in bits for SMC_PMPROT_AHSRUN. */ - -/*! @brief Read current value of the SMC_PMPROT_AHSRUN field. */ -#define BR_SMC_PMPROT_AHSRUN(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN)) - -/*! @brief Format value for bitfield SMC_PMPROT_AHSRUN. */ -#define BF_SMC_PMPROT_AHSRUN(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AHSRUN) & BM_SMC_PMPROT_AHSRUN) - -/*! @brief Set the AHSRUN field to a new value. */ -#define BW_SMC_PMPROT_AHSRUN(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SMC_PMCTRL - Power Mode Control register - ******************************************************************************/ - -/*! - * @brief HW_SMC_PMCTRL - Power Mode Control register (RW) - * - * Reset value: 0x00U - * - * The PMCTRL register controls entry into low-power Run and Stop modes, - * provided that the selected power mode is allowed via an appropriate setting of the - * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by - * reset types that trigger Chip POR not VLLS. It is unaffected by reset types - * that do not trigger Chip POR not VLLS. See the Reset section details for more - * information. - */ -typedef union _hw_smc_pmctrl -{ - uint8_t U; - struct _hw_smc_pmctrl_bitfields - { - uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */ - uint8_t STOPA : 1; /*!< [3] Stop Aborted */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */ - uint8_t RESERVED1 : 1; /*!< [7] */ - } B; -} hw_smc_pmctrl_t; - -/*! - * @name Constants and macros for entire SMC_PMCTRL register - */ -/*@{*/ -#define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U) - -#define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x)) -#define HW_SMC_PMCTRL_RD(x) (HW_SMC_PMCTRL(x).U) -#define HW_SMC_PMCTRL_WR(x, v) (HW_SMC_PMCTRL(x).U = (v)) -#define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v))) -#define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v))) -#define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SMC_PMCTRL bitfields - */ - -/*! - * @name Register SMC_PMCTRL, field STOPM[2:0] (RW) - * - * When written, controls entry into the selected stop mode when Sleep-Now or - * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are - * blocked if the protection level has not been enabled using the PMPROT register. - * After any system reset, this field is cleared by hardware on any successful write - * to the PMPROT register. When set to VLLSxor LLSx, the LLSM in the STOPCTRL - * register is used to further select the particular VLLSor LLS submode which will - * be entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be - * used to select a Partial Stop mode if desired. - * - * Values: - * - 000 - Normal Stop (STOP) - * - 001 - Reserved - * - 010 - Very-Low-Power Stop (VLPS) - * - 011 - Low-Leakage Stop (LLSx) - * - 100 - Very-Low-Leakage Stop (VLLSx) - * - 101 - Reserved - * - 110 - Reseved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */ -#define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */ -#define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */ - -/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */ -#define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM) - -/*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */ -#define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM) - -/*! @brief Set the STOPM field to a new value. */ -#define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v))) -/*@}*/ - -/*! - * @name Register SMC_PMCTRL, field STOPA[3] (RO) - * - * When set, this read-only status bit indicates an interrupt occured during the - * previous stop mode entry sequence, preventing the system from entering that - * mode. This field is cleared by reset or by hardware at the beginning of any - * stop mode entry sequence and is set if the sequence was aborted. - * - * Values: - * - 0 - The previous stop mode entry was successsful. - * - 1 - The previous stop mode entry was aborted. - */ -/*@{*/ -#define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */ -#define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */ -#define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */ - -/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */ -#define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA)) -/*@}*/ - -/*! - * @name Register SMC_PMCTRL, field RUNM[6:5] (RW) - * - * When written, causes entry into the selected run mode. Writes to this field - * are blocked if the protection level has not been enabled using the PMPROT - * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to - * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. RUNM may be set to - * HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not - * be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not - * be attempted while RUNM=HSRUN or PMSTAT=HSRUN. - * - * Values: - * - 00 - Normal Run mode (RUN) - * - 01 - Reserved - * - 10 - Very-Low-Power Run mode (VLPR) - * - 11 - High Speed Run mode (HSRUN) - */ -/*@{*/ -#define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */ -#define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */ -#define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */ - -/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */ -#define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM) - -/*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */ -#define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM) - -/*! @brief Set the RUNM field to a new value. */ -#define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v))) -/*@}*/ - -/******************************************************************************* - * HW_SMC_STOPCTRL - Stop Control Register - ******************************************************************************/ - -/*! - * @brief HW_SMC_STOPCTRL - Stop Control Register (RW) - * - * Reset value: 0x03U - * - * The STOPCTRL register provides various control bits allowing the user to fine - * tune power consumption during the stop mode selected by the STOPM field. This - * register is reset on Chip POR not VLLS and by reset types that trigger Chip - * POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not - * VLLS. See the Reset section details for more information. - */ -typedef union _hw_smc_stopctrl -{ - uint8_t U; - struct _hw_smc_stopctrl_bitfields - { - uint8_t LLSM : 3; /*!< [2:0] LLS or VLLS Mode Control */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t PORPO : 1; /*!< [5] POR Power Option */ - uint8_t PSTOPO : 2; /*!< [7:6] Partial Stop Option */ - } B; -} hw_smc_stopctrl_t; - -/*! - * @name Constants and macros for entire SMC_STOPCTRL register - */ -/*@{*/ -#define HW_SMC_STOPCTRL_ADDR(x) ((x) + 0x2U) - -#define HW_SMC_STOPCTRL(x) (*(__IO hw_smc_stopctrl_t *) HW_SMC_STOPCTRL_ADDR(x)) -#define HW_SMC_STOPCTRL_RD(x) (HW_SMC_STOPCTRL(x).U) -#define HW_SMC_STOPCTRL_WR(x, v) (HW_SMC_STOPCTRL(x).U = (v)) -#define HW_SMC_STOPCTRL_SET(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) | (v))) -#define HW_SMC_STOPCTRL_CLR(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) & ~(v))) -#define HW_SMC_STOPCTRL_TOG(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SMC_STOPCTRL bitfields - */ - -/*! - * @name Register SMC_STOPCTRL, field LLSM[2:0] (RW) - * - * This field controls which LLS or VLLS sub-mode to enter if STOPM=LLSx or - * VLLSx. - * - * Values: - * - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx - * - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx - * - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx - * - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx - * - 100 - Reserved - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SMC_STOPCTRL_LLSM (0U) /*!< Bit position for SMC_STOPCTRL_LLSM. */ -#define BM_SMC_STOPCTRL_LLSM (0x07U) /*!< Bit mask for SMC_STOPCTRL_LLSM. */ -#define BS_SMC_STOPCTRL_LLSM (3U) /*!< Bit field size in bits for SMC_STOPCTRL_LLSM. */ - -/*! @brief Read current value of the SMC_STOPCTRL_LLSM field. */ -#define BR_SMC_STOPCTRL_LLSM(x) (HW_SMC_STOPCTRL(x).B.LLSM) - -/*! @brief Format value for bitfield SMC_STOPCTRL_LLSM. */ -#define BF_SMC_STOPCTRL_LLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_LLSM) & BM_SMC_STOPCTRL_LLSM) - -/*! @brief Set the LLSM field to a new value. */ -#define BW_SMC_STOPCTRL_LLSM(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_LLSM) | BF_SMC_STOPCTRL_LLSM(v))) -/*@}*/ - -/*! - * @name Register SMC_STOPCTRL, field PORPO[5] (RW) - * - * This bit controls whether the POR detect circuit is enabled in VLLS0 mode. - * - * Values: - * - 0 - POR detect circuit is enabled in VLLS0 - * - 1 - POR detect circuit is disabled in VLLS0 - */ -/*@{*/ -#define BP_SMC_STOPCTRL_PORPO (5U) /*!< Bit position for SMC_STOPCTRL_PORPO. */ -#define BM_SMC_STOPCTRL_PORPO (0x20U) /*!< Bit mask for SMC_STOPCTRL_PORPO. */ -#define BS_SMC_STOPCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_STOPCTRL_PORPO. */ - -/*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */ -#define BR_SMC_STOPCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO)) - -/*! @brief Format value for bitfield SMC_STOPCTRL_PORPO. */ -#define BF_SMC_STOPCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PORPO) & BM_SMC_STOPCTRL_PORPO) - -/*! @brief Set the PORPO field to a new value. */ -#define BW_SMC_STOPCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO) = (v)) -/*@}*/ - -/*! - * @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW) - * - * These bits control whether a Partial Stop mode is entered when STOPM=STOP. - * When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain - * fully powered, allowing the device to wakeup almost instantaneously at the - * expense of higher power consumption. In PSTOP2, only system clocks are gated - * allowing peripherals running on bus clock to remain fully functional. In PSTOP1, - * both system and bus clocks are gated. - * - * Values: - * - 00 - STOP - Normal Stop mode - * - 01 - PSTOP1 - Partial Stop with both system and bus clocks disabled - * - 10 - PSTOP2 - Partial Stop with system clock disabled and bus clock enabled - * - 11 - Reserved - */ -/*@{*/ -#define BP_SMC_STOPCTRL_PSTOPO (6U) /*!< Bit position for SMC_STOPCTRL_PSTOPO. */ -#define BM_SMC_STOPCTRL_PSTOPO (0xC0U) /*!< Bit mask for SMC_STOPCTRL_PSTOPO. */ -#define BS_SMC_STOPCTRL_PSTOPO (2U) /*!< Bit field size in bits for SMC_STOPCTRL_PSTOPO. */ - -/*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */ -#define BR_SMC_STOPCTRL_PSTOPO(x) (HW_SMC_STOPCTRL(x).B.PSTOPO) - -/*! @brief Format value for bitfield SMC_STOPCTRL_PSTOPO. */ -#define BF_SMC_STOPCTRL_PSTOPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PSTOPO) & BM_SMC_STOPCTRL_PSTOPO) - -/*! @brief Set the PSTOPO field to a new value. */ -#define BW_SMC_STOPCTRL_PSTOPO(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_PSTOPO) | BF_SMC_STOPCTRL_PSTOPO(v))) -/*@}*/ - -/******************************************************************************* - * HW_SMC_PMSTAT - Power Mode Status register - ******************************************************************************/ - -/*! - * @brief HW_SMC_PMSTAT - Power Mode Status register (RO) - * - * Reset value: 0x01U - * - * PMSTAT is a read-only, one-hot register which indicates the current power - * mode of the system. This register is reset on Chip POR not VLLS and by reset - * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not - * trigger Chip POR not VLLS. See the Reset section details for more information. - */ -typedef union _hw_smc_pmstat -{ - uint8_t U; - struct _hw_smc_pmstat_bitfields - { - uint8_t PMSTAT : 8; /*!< [7:0] */ - } B; -} hw_smc_pmstat_t; - -/*! - * @name Constants and macros for entire SMC_PMSTAT register - */ -/*@{*/ -#define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U) - -#define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x)) -#define HW_SMC_PMSTAT_RD(x) (HW_SMC_PMSTAT(x).U) -/*@}*/ - -/* - * Constants & macros for individual SMC_PMSTAT bitfields - */ - -/*! - * @name Register SMC_PMSTAT, field PMSTAT[7:0] (RO) - * - * When debug is enabled, the PMSTAT will not update to STOP or VLPS When a - * PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS - */ -/*@{*/ -#define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */ -#define BM_SMC_PMSTAT_PMSTAT (0xFFU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */ -#define BS_SMC_PMSTAT_PMSTAT (8U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */ - -/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */ -#define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).U) -/*@}*/ - -/******************************************************************************* - * hw_smc_t - module struct - ******************************************************************************/ -/*! - * @brief All SMC module registers. - */ -#pragma pack(1) -typedef struct _hw_smc -{ - __IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */ - __IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */ - __IO hw_smc_stopctrl_t STOPCTRL; /*!< [0x2] Stop Control Register */ - __I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */ -} hw_smc_t; -#pragma pack() - -/*! @brief Macro to access all SMC registers. */ -/*! @param x SMC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SMC(SMC_BASE). */ -#define HW_SMC(x) (*(hw_smc_t *)(x)) - -#endif /* __HW_SMC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h deleted file mode 100644 index ff5a2b4297e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h +++ /dev/null @@ -1,2239 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SPI_REGISTERS_H__ -#define __HW_SPI_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 SPI - * - * Serial Peripheral Interface - * - * Registers defined in this header file: - * - HW_SPI_MCR - Module Configuration Register - * - HW_SPI_TCR - Transfer Count Register - * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) - * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) - * - HW_SPI_SR - Status Register - * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register - * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode - * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode - * - HW_SPI_POPR - POP RX FIFO Register - * - HW_SPI_TXFRn - Transmit FIFO Registers - * - HW_SPI_RXFRn - Receive FIFO Registers - * - * - hw_spi_t - Struct containing all module registers. - */ - -#define HW_SPI_INSTANCE_COUNT (2U) /*!< Number of instances of the SPI module. */ -#define HW_SPI0 (0U) /*!< Instance number for SPI0. */ -#define HW_SPI1 (1U) /*!< Instance number for SPI1. */ - -/******************************************************************************* - * HW_SPI_MCR - Module Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_MCR - Module Configuration Register (RW) - * - * Reset value: 0x00004001U - * - * Contains bits to configure various attributes associated with the module - * operations. The HALT and MDIS bits can be changed at any time, but the effect - * takes place only on the next frame boundary. Only the HALT and MDIS bits in the - * MCR can be changed, while the module is in the Running state. - */ -typedef union _hw_spi_mcr -{ - uint32_t U; - struct _hw_spi_mcr_bitfields - { - uint32_t HALT : 1; /*!< [0] Halt */ - uint32_t RESERVED0 : 7; /*!< [7:1] */ - uint32_t SMPL_PT : 2; /*!< [9:8] Sample Point */ - uint32_t CLR_RXF : 1; /*!< [10] */ - uint32_t CLR_TXF : 1; /*!< [11] Clear TX FIFO */ - uint32_t DIS_RXF : 1; /*!< [12] Disable Receive FIFO */ - uint32_t DIS_TXF : 1; /*!< [13] Disable Transmit FIFO */ - uint32_t MDIS : 1; /*!< [14] Module Disable */ - uint32_t DOZE : 1; /*!< [15] Doze Enable */ - uint32_t PCSIS : 6; /*!< [21:16] Peripheral Chip Select x Inactive - * State */ - uint32_t RESERVED1 : 2; /*!< [23:22] */ - uint32_t ROOE : 1; /*!< [24] Receive FIFO Overflow Overwrite Enable */ - uint32_t PCSSE : 1; /*!< [25] Peripheral Chip Select Strobe Enable */ - uint32_t MTFE : 1; /*!< [26] Modified Timing Format Enable */ - uint32_t FRZ : 1; /*!< [27] Freeze */ - uint32_t DCONF : 2; /*!< [29:28] SPI Configuration. */ - uint32_t CONT_SCKE : 1; /*!< [30] Continuous SCK Enable */ - uint32_t MSTR : 1; /*!< [31] Master/Slave Mode Select */ - } B; -} hw_spi_mcr_t; - -/*! - * @name Constants and macros for entire SPI_MCR register - */ -/*@{*/ -#define HW_SPI_MCR_ADDR(x) ((x) + 0x0U) - -#define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x)) -#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U) -#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v)) -#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v))) -#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v))) -#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_MCR bitfields - */ - -/*! - * @name Register SPI_MCR, field HALT[0] (RW) - * - * The HALT bit starts and stops frame transfers. See Start and Stop of Module - * transfers - * - * Values: - * - 0 - Start transfers. - * - 1 - Stop transfers. - */ -/*@{*/ -#define BP_SPI_MCR_HALT (0U) /*!< Bit position for SPI_MCR_HALT. */ -#define BM_SPI_MCR_HALT (0x00000001U) /*!< Bit mask for SPI_MCR_HALT. */ -#define BS_SPI_MCR_HALT (1U) /*!< Bit field size in bits for SPI_MCR_HALT. */ - -/*! @brief Read current value of the SPI_MCR_HALT field. */ -#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT)) - -/*! @brief Format value for bitfield SPI_MCR_HALT. */ -#define BF_SPI_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT) - -/*! @brief Set the HALT field to a new value. */ -#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field SMPL_PT[9:8] (RW) - * - * Controls when the module master samples SIN in Modified Transfer Format. This - * field is valid only when CPHA bit in CTARn[CPHA] is 0. - * - * Values: - * - 00 - 0 protocol clock cycles between SCK edge and SIN sample - * - 01 - 1 protocol clock cycle between SCK edge and SIN sample - * - 10 - 2 protocol clock cycles between SCK edge and SIN sample - * - 11 - Reserved - */ -/*@{*/ -#define BP_SPI_MCR_SMPL_PT (8U) /*!< Bit position for SPI_MCR_SMPL_PT. */ -#define BM_SPI_MCR_SMPL_PT (0x00000300U) /*!< Bit mask for SPI_MCR_SMPL_PT. */ -#define BS_SPI_MCR_SMPL_PT (2U) /*!< Bit field size in bits for SPI_MCR_SMPL_PT. */ - -/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */ -#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT) - -/*! @brief Format value for bitfield SPI_MCR_SMPL_PT. */ -#define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT) - -/*! @brief Set the SMPL_PT field to a new value. */ -#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v))) -/*@}*/ - -/*! - * @name Register SPI_MCR, field CLR_RXF[10] (WORZ) - * - * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The - * CLR_RXF bit is always read as zero. - * - * Values: - * - 0 - Do not clear the RX FIFO counter. - * - 1 - Clear the RX FIFO counter. - */ -/*@{*/ -#define BP_SPI_MCR_CLR_RXF (10U) /*!< Bit position for SPI_MCR_CLR_RXF. */ -#define BM_SPI_MCR_CLR_RXF (0x00000400U) /*!< Bit mask for SPI_MCR_CLR_RXF. */ -#define BS_SPI_MCR_CLR_RXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_RXF. */ - -/*! @brief Format value for bitfield SPI_MCR_CLR_RXF. */ -#define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF) - -/*! @brief Set the CLR_RXF field to a new value. */ -#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field CLR_TXF[11] (WORZ) - * - * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The - * CLR_TXF bit is always read as zero. - * - * Values: - * - 0 - Do not clear the TX FIFO counter. - * - 1 - Clear the TX FIFO counter. - */ -/*@{*/ -#define BP_SPI_MCR_CLR_TXF (11U) /*!< Bit position for SPI_MCR_CLR_TXF. */ -#define BM_SPI_MCR_CLR_TXF (0x00000800U) /*!< Bit mask for SPI_MCR_CLR_TXF. */ -#define BS_SPI_MCR_CLR_TXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_TXF. */ - -/*! @brief Format value for bitfield SPI_MCR_CLR_TXF. */ -#define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF) - -/*! @brief Set the CLR_TXF field to a new value. */ -#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DIS_RXF[12] (RW) - * - * When the RX FIFO is disabled, the receive part of the module operates as a - * simplified double-buffered SPI. This bit can only be written when the MDIS bit - * is cleared. - * - * Values: - * - 0 - RX FIFO is enabled. - * - 1 - RX FIFO is disabled. - */ -/*@{*/ -#define BP_SPI_MCR_DIS_RXF (12U) /*!< Bit position for SPI_MCR_DIS_RXF. */ -#define BM_SPI_MCR_DIS_RXF (0x00001000U) /*!< Bit mask for SPI_MCR_DIS_RXF. */ -#define BS_SPI_MCR_DIS_RXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_RXF. */ - -/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */ -#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF)) - -/*! @brief Format value for bitfield SPI_MCR_DIS_RXF. */ -#define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF) - -/*! @brief Set the DIS_RXF field to a new value. */ -#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DIS_TXF[13] (RW) - * - * When the TX FIFO is disabled, the transmit part of the module operates as a - * simplified double-buffered SPI. This bit can be written only when the MDIS bit - * is cleared. - * - * Values: - * - 0 - TX FIFO is enabled. - * - 1 - TX FIFO is disabled. - */ -/*@{*/ -#define BP_SPI_MCR_DIS_TXF (13U) /*!< Bit position for SPI_MCR_DIS_TXF. */ -#define BM_SPI_MCR_DIS_TXF (0x00002000U) /*!< Bit mask for SPI_MCR_DIS_TXF. */ -#define BS_SPI_MCR_DIS_TXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_TXF. */ - -/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */ -#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF)) - -/*! @brief Format value for bitfield SPI_MCR_DIS_TXF. */ -#define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF) - -/*! @brief Set the DIS_TXF field to a new value. */ -#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field MDIS[14] (RW) - * - * Allows the clock to be stopped to the non-memory mapped logic in the module - * effectively putting it in a software-controlled power-saving state. The reset - * value of the MDIS bit is parameterized, with a default reset value of 0. When - * the module is used in Slave Mode, we recommend leaving this bit 0, because a - * slave doesn't have control over master transactions. - * - * Values: - * - 0 - Enables the module clocks. - * - 1 - Allows external logic to disable the module clocks. - */ -/*@{*/ -#define BP_SPI_MCR_MDIS (14U) /*!< Bit position for SPI_MCR_MDIS. */ -#define BM_SPI_MCR_MDIS (0x00004000U) /*!< Bit mask for SPI_MCR_MDIS. */ -#define BS_SPI_MCR_MDIS (1U) /*!< Bit field size in bits for SPI_MCR_MDIS. */ - -/*! @brief Read current value of the SPI_MCR_MDIS field. */ -#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS)) - -/*! @brief Format value for bitfield SPI_MCR_MDIS. */ -#define BF_SPI_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS) - -/*! @brief Set the MDIS field to a new value. */ -#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DOZE[15] (RW) - * - * Provides support for an externally controlled Doze mode power-saving - * mechanism. - * - * Values: - * - 0 - Doze mode has no effect on the module. - * - 1 - Doze mode disables the module. - */ -/*@{*/ -#define BP_SPI_MCR_DOZE (15U) /*!< Bit position for SPI_MCR_DOZE. */ -#define BM_SPI_MCR_DOZE (0x00008000U) /*!< Bit mask for SPI_MCR_DOZE. */ -#define BS_SPI_MCR_DOZE (1U) /*!< Bit field size in bits for SPI_MCR_DOZE. */ - -/*! @brief Read current value of the SPI_MCR_DOZE field. */ -#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE)) - -/*! @brief Format value for bitfield SPI_MCR_DOZE. */ -#define BF_SPI_MCR_DOZE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE) - -/*! @brief Set the DOZE field to a new value. */ -#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field PCSIS[21:16] (RW) - * - * Determines the inactive state of PCSx. - * - * Values: - * - 0 - The inactive state of PCSx is low. - * - 1 - The inactive state of PCSx is high. - */ -/*@{*/ -#define BP_SPI_MCR_PCSIS (16U) /*!< Bit position for SPI_MCR_PCSIS. */ -#define BM_SPI_MCR_PCSIS (0x003F0000U) /*!< Bit mask for SPI_MCR_PCSIS. */ -#define BS_SPI_MCR_PCSIS (6U) /*!< Bit field size in bits for SPI_MCR_PCSIS. */ - -/*! @brief Read current value of the SPI_MCR_PCSIS field. */ -#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS) - -/*! @brief Format value for bitfield SPI_MCR_PCSIS. */ -#define BF_SPI_MCR_PCSIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS) - -/*! @brief Set the PCSIS field to a new value. */ -#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v))) -/*@}*/ - -/*! - * @name Register SPI_MCR, field ROOE[24] (RW) - * - * In the RX FIFO overflow condition, configures the module to ignore the - * incoming serial data or overwrite existing data. If the RX FIFO is full and new data - * is received, the data from the transfer, generating the overflow, is ignored - * or shifted into the shift register. - * - * Values: - * - 0 - Incoming data is ignored. - * - 1 - Incoming data is shifted into the shift register. - */ -/*@{*/ -#define BP_SPI_MCR_ROOE (24U) /*!< Bit position for SPI_MCR_ROOE. */ -#define BM_SPI_MCR_ROOE (0x01000000U) /*!< Bit mask for SPI_MCR_ROOE. */ -#define BS_SPI_MCR_ROOE (1U) /*!< Bit field size in bits for SPI_MCR_ROOE. */ - -/*! @brief Read current value of the SPI_MCR_ROOE field. */ -#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE)) - -/*! @brief Format value for bitfield SPI_MCR_ROOE. */ -#define BF_SPI_MCR_ROOE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE) - -/*! @brief Set the ROOE field to a new value. */ -#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field PCSSE[25] (RW) - * - * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal. - * - * Values: - * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. - * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal. - */ -/*@{*/ -#define BP_SPI_MCR_PCSSE (25U) /*!< Bit position for SPI_MCR_PCSSE. */ -#define BM_SPI_MCR_PCSSE (0x02000000U) /*!< Bit mask for SPI_MCR_PCSSE. */ -#define BS_SPI_MCR_PCSSE (1U) /*!< Bit field size in bits for SPI_MCR_PCSSE. */ - -/*! @brief Read current value of the SPI_MCR_PCSSE field. */ -#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE)) - -/*! @brief Format value for bitfield SPI_MCR_PCSSE. */ -#define BF_SPI_MCR_PCSSE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE) - -/*! @brief Set the PCSSE field to a new value. */ -#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field MTFE[26] (RW) - * - * Enables a modified transfer format to be used. - * - * Values: - * - 0 - Modified SPI transfer format disabled. - * - 1 - Modified SPI transfer format enabled. - */ -/*@{*/ -#define BP_SPI_MCR_MTFE (26U) /*!< Bit position for SPI_MCR_MTFE. */ -#define BM_SPI_MCR_MTFE (0x04000000U) /*!< Bit mask for SPI_MCR_MTFE. */ -#define BS_SPI_MCR_MTFE (1U) /*!< Bit field size in bits for SPI_MCR_MTFE. */ - -/*! @brief Read current value of the SPI_MCR_MTFE field. */ -#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE)) - -/*! @brief Format value for bitfield SPI_MCR_MTFE. */ -#define BF_SPI_MCR_MTFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE) - -/*! @brief Set the MTFE field to a new value. */ -#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field FRZ[27] (RW) - * - * Enables transfers to be stopped on the next frame boundary when the device - * enters Debug mode. - * - * Values: - * - 0 - Do not halt serial transfers in Debug mode. - * - 1 - Halt serial transfers in Debug mode. - */ -/*@{*/ -#define BP_SPI_MCR_FRZ (27U) /*!< Bit position for SPI_MCR_FRZ. */ -#define BM_SPI_MCR_FRZ (0x08000000U) /*!< Bit mask for SPI_MCR_FRZ. */ -#define BS_SPI_MCR_FRZ (1U) /*!< Bit field size in bits for SPI_MCR_FRZ. */ - -/*! @brief Read current value of the SPI_MCR_FRZ field. */ -#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ)) - -/*! @brief Format value for bitfield SPI_MCR_FRZ. */ -#define BF_SPI_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ) - -/*! @brief Set the FRZ field to a new value. */ -#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DCONF[29:28] (RO) - * - * Selects among the different configurations of the module. - * - * Values: - * - 00 - SPI - * - 01 - Reserved - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_SPI_MCR_DCONF (28U) /*!< Bit position for SPI_MCR_DCONF. */ -#define BM_SPI_MCR_DCONF (0x30000000U) /*!< Bit mask for SPI_MCR_DCONF. */ -#define BS_SPI_MCR_DCONF (2U) /*!< Bit field size in bits for SPI_MCR_DCONF. */ - -/*! @brief Read current value of the SPI_MCR_DCONF field. */ -#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF) -/*@}*/ - -/*! - * @name Register SPI_MCR, field CONT_SCKE[30] (RW) - * - * Enables the Serial Communication Clock (SCK) to run continuously. - * - * Values: - * - 0 - Continuous SCK disabled. - * - 1 - Continuous SCK enabled. - */ -/*@{*/ -#define BP_SPI_MCR_CONT_SCKE (30U) /*!< Bit position for SPI_MCR_CONT_SCKE. */ -#define BM_SPI_MCR_CONT_SCKE (0x40000000U) /*!< Bit mask for SPI_MCR_CONT_SCKE. */ -#define BS_SPI_MCR_CONT_SCKE (1U) /*!< Bit field size in bits for SPI_MCR_CONT_SCKE. */ - -/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */ -#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE)) - -/*! @brief Format value for bitfield SPI_MCR_CONT_SCKE. */ -#define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE) - -/*! @brief Set the CONT_SCKE field to a new value. */ -#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field MSTR[31] (RW) - * - * Enables either Master mode (if supported) or Slave mode (if supported) - * operation. - * - * Values: - * - 0 - Enables Slave mode - * - 1 - Enables Master mode - */ -/*@{*/ -#define BP_SPI_MCR_MSTR (31U) /*!< Bit position for SPI_MCR_MSTR. */ -#define BM_SPI_MCR_MSTR (0x80000000U) /*!< Bit mask for SPI_MCR_MSTR. */ -#define BS_SPI_MCR_MSTR (1U) /*!< Bit field size in bits for SPI_MCR_MSTR. */ - -/*! @brief Read current value of the SPI_MCR_MSTR field. */ -#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR)) - -/*! @brief Format value for bitfield SPI_MCR_MSTR. */ -#define BF_SPI_MCR_MSTR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR) - -/*! @brief Set the MSTR field to a new value. */ -#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_TCR - Transfer Count Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_TCR - Transfer Count Register (RW) - * - * Reset value: 0x00000000U - * - * TCR contains a counter that indicates the number of SPI transfers made. The - * transfer counter is intended to assist in queue management. Do not write the - * TCR when the module is in the Running state. - */ -typedef union _hw_spi_tcr -{ - uint32_t U; - struct _hw_spi_tcr_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t SPI_TCNT : 16; /*!< [31:16] SPI Transfer Counter */ - } B; -} hw_spi_tcr_t; - -/*! - * @name Constants and macros for entire SPI_TCR register - */ -/*@{*/ -#define HW_SPI_TCR_ADDR(x) ((x) + 0x8U) - -#define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x)) -#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U) -#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v)) -#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v))) -#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v))) -#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_TCR bitfields - */ - -/*! - * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW) - * - * Counts the number of SPI transfers the module makes. The SPI_TCNT field - * increments every time the last bit of an SPI frame is transmitted. A value written - * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at - * the beginning of the frame when the CTCNT field is set in the executing SPI - * command. The Transfer Counter wraps around; incrementing the counter past 65535 - * resets the counter to zero. - */ -/*@{*/ -#define BP_SPI_TCR_SPI_TCNT (16U) /*!< Bit position for SPI_TCR_SPI_TCNT. */ -#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) /*!< Bit mask for SPI_TCR_SPI_TCNT. */ -#define BS_SPI_TCR_SPI_TCNT (16U) /*!< Bit field size in bits for SPI_TCR_SPI_TCNT. */ - -/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */ -#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT) - -/*! @brief Format value for bitfield SPI_TCR_SPI_TCNT. */ -#define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT) - -/*! @brief Set the SPI_TCNT field to a new value. */ -#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) - ******************************************************************************/ - -/*! - * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW) - * - * Reset value: 0x78000000U - * - * CTAR registers are used to define different transfer attributes. Do not write - * to the CTAR registers while the module is in the Running state. In Master - * mode, the CTAR registers define combinations of transfer attributes such as frame - * size, clock phase and polarity, data bit ordering, baud rate, and various - * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the - * slave transfer attributes. When the module is configured as an SPI master, the - * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR - * registers is used. When the module is configured as an SPI bus slave, it uses - * the CTAR0 register. - */ -typedef union _hw_spi_ctarn -{ - uint32_t U; - struct _hw_spi_ctarn_bitfields - { - uint32_t BR : 4; /*!< [3:0] Baud Rate Scaler */ - uint32_t DT : 4; /*!< [7:4] Delay After Transfer Scaler */ - uint32_t ASC : 4; /*!< [11:8] After SCK Delay Scaler */ - uint32_t CSSCK : 4; /*!< [15:12] PCS to SCK Delay Scaler */ - uint32_t PBR : 2; /*!< [17:16] Baud Rate Prescaler */ - uint32_t PDT : 2; /*!< [19:18] Delay after Transfer Prescaler */ - uint32_t PASC : 2; /*!< [21:20] After SCK Delay Prescaler */ - uint32_t PCSSCK : 2; /*!< [23:22] PCS to SCK Delay Prescaler */ - uint32_t LSBFE : 1; /*!< [24] LSB First */ - uint32_t CPHA : 1; /*!< [25] Clock Phase */ - uint32_t CPOL : 1; /*!< [26] Clock Polarity */ - uint32_t FMSZ : 4; /*!< [30:27] Frame Size */ - uint32_t DBR : 1; /*!< [31] Double Baud Rate */ - } B; -} hw_spi_ctarn_t; - -/*! - * @name Constants and macros for entire SPI_CTARn register - */ -/*@{*/ -#define HW_SPI_CTARn_COUNT (2U) - -#define HW_SPI_CTARn_ADDR(x, n) ((x) + 0xCU + (0x4U * (n))) - -#define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n)) -#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U) -#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v)) -#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v))) -#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v))) -#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_CTARn bitfields - */ - -/*! - * @name Register SPI_CTARn, field BR[3:0] (RW) - * - * Selects the scaler value for the baud rate. This field is used only in master - * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to - * generate the frequency of the SCK. The baud rate is computed according to the - * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table - * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler - * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 - * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 - */ -/*@{*/ -#define BP_SPI_CTARn_BR (0U) /*!< Bit position for SPI_CTARn_BR. */ -#define BM_SPI_CTARn_BR (0x0000000FU) /*!< Bit mask for SPI_CTARn_BR. */ -#define BS_SPI_CTARn_BR (4U) /*!< Bit field size in bits for SPI_CTARn_BR. */ - -/*! @brief Read current value of the SPI_CTARn_BR field. */ -#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR) - -/*! @brief Format value for bitfield SPI_CTARn_BR. */ -#define BF_SPI_CTARn_BR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR) - -/*! @brief Set the BR field to a new value. */ -#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field DT[7:4] (RW) - * - * Selects the Delay after Transfer Scaler. This field is used only in master - * mode. The Delay after Transfer is the time between the negation of the PCS - * signal at the end of a frame and the assertion of PCS at the beginning of the next - * frame. In the Continuous Serial Communications Clock operation, the DT value - * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the - * protocol clock period, and it is computed according to the following - * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit - * field description for scaler values. - */ -/*@{*/ -#define BP_SPI_CTARn_DT (4U) /*!< Bit position for SPI_CTARn_DT. */ -#define BM_SPI_CTARn_DT (0x000000F0U) /*!< Bit mask for SPI_CTARn_DT. */ -#define BS_SPI_CTARn_DT (4U) /*!< Bit field size in bits for SPI_CTARn_DT. */ - -/*! @brief Read current value of the SPI_CTARn_DT field. */ -#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT) - -/*! @brief Format value for bitfield SPI_CTARn_DT. */ -#define BF_SPI_CTARn_DT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT) - -/*! @brief Set the DT field to a new value. */ -#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field ASC[11:8] (RW) - * - * Selects the scaler value for the After SCK Delay. This field is used only in - * master mode. The After SCK Delay is the delay between the last edge of SCK and - * the negation of PCS. The delay is a multiple of the protocol clock period, - * and it is computed according to the following equation: t ASC = (1/fP) x PASC x - * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for - * scaler values. Refer After SCK Delay (tASC ) for more details. - */ -/*@{*/ -#define BP_SPI_CTARn_ASC (8U) /*!< Bit position for SPI_CTARn_ASC. */ -#define BM_SPI_CTARn_ASC (0x00000F00U) /*!< Bit mask for SPI_CTARn_ASC. */ -#define BS_SPI_CTARn_ASC (4U) /*!< Bit field size in bits for SPI_CTARn_ASC. */ - -/*! @brief Read current value of the SPI_CTARn_ASC field. */ -#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC) - -/*! @brief Format value for bitfield SPI_CTARn_ASC. */ -#define BF_SPI_CTARn_ASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC) - -/*! @brief Set the ASC field to a new value. */ -#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field CSSCK[15:12] (RW) - * - * Selects the scaler value for the PCS to SCK delay. This field is used only in - * master mode. The PCS to SCK Delay is the delay between the assertion of PCS - * and the first edge of the SCK. The delay is a multiple of the protocol clock - * period, and it is computed according to the following equation: t CSC = (1/fP ) - * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay - * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100 - * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192 - * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more - * details. - */ -/*@{*/ -#define BP_SPI_CTARn_CSSCK (12U) /*!< Bit position for SPI_CTARn_CSSCK. */ -#define BM_SPI_CTARn_CSSCK (0x0000F000U) /*!< Bit mask for SPI_CTARn_CSSCK. */ -#define BS_SPI_CTARn_CSSCK (4U) /*!< Bit field size in bits for SPI_CTARn_CSSCK. */ - -/*! @brief Read current value of the SPI_CTARn_CSSCK field. */ -#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK) - -/*! @brief Format value for bitfield SPI_CTARn_CSSCK. */ -#define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK) - -/*! @brief Set the CSSCK field to a new value. */ -#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PBR[17:16] (RW) - * - * Selects the prescaler value for the baud rate. This field is used only in - * master mode. The baud rate is the frequency of the SCK. The protocol clock is - * divided by the prescaler value before the baud rate selection takes place. See - * the BR field description for details on how to compute the baud rate. - * - * Values: - * - 00 - Baud Rate Prescaler value is 2. - * - 01 - Baud Rate Prescaler value is 3. - * - 10 - Baud Rate Prescaler value is 5. - * - 11 - Baud Rate Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PBR (16U) /*!< Bit position for SPI_CTARn_PBR. */ -#define BM_SPI_CTARn_PBR (0x00030000U) /*!< Bit mask for SPI_CTARn_PBR. */ -#define BS_SPI_CTARn_PBR (2U) /*!< Bit field size in bits for SPI_CTARn_PBR. */ - -/*! @brief Read current value of the SPI_CTARn_PBR field. */ -#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR) - -/*! @brief Format value for bitfield SPI_CTARn_PBR. */ -#define BF_SPI_CTARn_PBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR) - -/*! @brief Set the PBR field to a new value. */ -#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PDT[19:18] (RW) - * - * Selects the prescaler value for the delay between the negation of the PCS - * signal at the end of a frame and the assertion of PCS at the beginning of the - * next frame. The PDT field is only used in master mode. See the DT field - * description for details on how to compute the Delay after Transfer. Refer Delay after - * Transfer (tDT ) for more details. - * - * Values: - * - 00 - Delay after Transfer Prescaler value is 1. - * - 01 - Delay after Transfer Prescaler value is 3. - * - 10 - Delay after Transfer Prescaler value is 5. - * - 11 - Delay after Transfer Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PDT (18U) /*!< Bit position for SPI_CTARn_PDT. */ -#define BM_SPI_CTARn_PDT (0x000C0000U) /*!< Bit mask for SPI_CTARn_PDT. */ -#define BS_SPI_CTARn_PDT (2U) /*!< Bit field size in bits for SPI_CTARn_PDT. */ - -/*! @brief Read current value of the SPI_CTARn_PDT field. */ -#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT) - -/*! @brief Format value for bitfield SPI_CTARn_PDT. */ -#define BF_SPI_CTARn_PDT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT) - -/*! @brief Set the PDT field to a new value. */ -#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PASC[21:20] (RW) - * - * Selects the prescaler value for the delay between the last edge of SCK and - * the negation of PCS. See the ASC field description for information on how to - * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details. - * - * Values: - * - 00 - Delay after Transfer Prescaler value is 1. - * - 01 - Delay after Transfer Prescaler value is 3. - * - 10 - Delay after Transfer Prescaler value is 5. - * - 11 - Delay after Transfer Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PASC (20U) /*!< Bit position for SPI_CTARn_PASC. */ -#define BM_SPI_CTARn_PASC (0x00300000U) /*!< Bit mask for SPI_CTARn_PASC. */ -#define BS_SPI_CTARn_PASC (2U) /*!< Bit field size in bits for SPI_CTARn_PASC. */ - -/*! @brief Read current value of the SPI_CTARn_PASC field. */ -#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC) - -/*! @brief Format value for bitfield SPI_CTARn_PASC. */ -#define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC) - -/*! @brief Set the PASC field to a new value. */ -#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PCSSCK[23:22] (RW) - * - * Selects the prescaler value for the delay between assertion of PCS and the - * first edge of the SCK. See the CSSCK field description for information on how to - * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details. - * - * Values: - * - 00 - PCS to SCK Prescaler value is 1. - * - 01 - PCS to SCK Prescaler value is 3. - * - 10 - PCS to SCK Prescaler value is 5. - * - 11 - PCS to SCK Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PCSSCK (22U) /*!< Bit position for SPI_CTARn_PCSSCK. */ -#define BM_SPI_CTARn_PCSSCK (0x00C00000U) /*!< Bit mask for SPI_CTARn_PCSSCK. */ -#define BS_SPI_CTARn_PCSSCK (2U) /*!< Bit field size in bits for SPI_CTARn_PCSSCK. */ - -/*! @brief Read current value of the SPI_CTARn_PCSSCK field. */ -#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK) - -/*! @brief Format value for bitfield SPI_CTARn_PCSSCK. */ -#define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK) - -/*! @brief Set the PCSSCK field to a new value. */ -#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field LSBFE[24] (RW) - * - * Specifies whether the LSB or MSB of the frame is transferred first. - * - * Values: - * - 0 - Data is transferred MSB first. - * - 1 - Data is transferred LSB first. - */ -/*@{*/ -#define BP_SPI_CTARn_LSBFE (24U) /*!< Bit position for SPI_CTARn_LSBFE. */ -#define BM_SPI_CTARn_LSBFE (0x01000000U) /*!< Bit mask for SPI_CTARn_LSBFE. */ -#define BS_SPI_CTARn_LSBFE (1U) /*!< Bit field size in bits for SPI_CTARn_LSBFE. */ - -/*! @brief Read current value of the SPI_CTARn_LSBFE field. */ -#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE)) - -/*! @brief Format value for bitfield SPI_CTARn_LSBFE. */ -#define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE) - -/*! @brief Set the LSBFE field to a new value. */ -#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field CPHA[25] (RW) - * - * Selects which edge of SCK causes data to change and which edge causes data to - * be captured. This bit is used in both master and slave mode. For successful - * communication between serial devices, the devices must have identical clock - * phase settings. In Continuous SCK mode, the bit value is ignored and the - * transfers are done as if the CPHA bit is set to 1. - * - * Values: - * - 0 - Data is captured on the leading edge of SCK and changed on the - * following edge. - * - 1 - Data is changed on the leading edge of SCK and captured on the - * following edge. - */ -/*@{*/ -#define BP_SPI_CTARn_CPHA (25U) /*!< Bit position for SPI_CTARn_CPHA. */ -#define BM_SPI_CTARn_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_CPHA. */ -#define BS_SPI_CTARn_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_CPHA. */ - -/*! @brief Read current value of the SPI_CTARn_CPHA field. */ -#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA)) - -/*! @brief Format value for bitfield SPI_CTARn_CPHA. */ -#define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA) - -/*! @brief Set the CPHA field to a new value. */ -#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field CPOL[26] (RW) - * - * Selects the inactive state of the Serial Communications Clock (SCK). This bit - * is used in both master and slave mode. For successful communication between - * serial devices, the devices must have identical clock polarities. When the - * Continuous Selection Format is selected, switching between clock polarities - * without stopping the module can cause errors in the transfer due to the peripheral - * device interpreting the switch of clock polarity as a valid clock edge. In case - * of continous sck mode, when the module goes in low power mode(disabled), - * inactive state of sck is not guaranted. - * - * Values: - * - 0 - The inactive state value of SCK is low. - * - 1 - The inactive state value of SCK is high. - */ -/*@{*/ -#define BP_SPI_CTARn_CPOL (26U) /*!< Bit position for SPI_CTARn_CPOL. */ -#define BM_SPI_CTARn_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_CPOL. */ -#define BS_SPI_CTARn_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_CPOL. */ - -/*! @brief Read current value of the SPI_CTARn_CPOL field. */ -#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL)) - -/*! @brief Format value for bitfield SPI_CTARn_CPOL. */ -#define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL) - -/*! @brief Set the CPOL field to a new value. */ -#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field FMSZ[30:27] (RW) - * - * The number of bits transferred per frame is equal to the FMSZ value plus 1. - * Regardless of the transmission mode, the minimum valid frame size value is 4. - */ -/*@{*/ -#define BP_SPI_CTARn_FMSZ (27U) /*!< Bit position for SPI_CTARn_FMSZ. */ -#define BM_SPI_CTARn_FMSZ (0x78000000U) /*!< Bit mask for SPI_CTARn_FMSZ. */ -#define BS_SPI_CTARn_FMSZ (4U) /*!< Bit field size in bits for SPI_CTARn_FMSZ. */ - -/*! @brief Read current value of the SPI_CTARn_FMSZ field. */ -#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ) - -/*! @brief Format value for bitfield SPI_CTARn_FMSZ. */ -#define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ) - -/*! @brief Set the FMSZ field to a new value. */ -#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field DBR[31] (RW) - * - * Doubles the effective baud rate of the Serial Communications Clock (SCK). - * This field is used only in master mode. It effectively halves the Baud Rate - * division ratio, supporting faster frequencies, and odd division ratios for the - * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the - * Serial Communications Clock (SCK) depends on the value in the Baud Rate - * Prescaler and the Clock Phase bit as listed in the following table. See the BR field - * description for details on how to compute the baud rate. SPI SCK Duty Cycle - * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 - * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 - * - * Values: - * - 0 - The baud rate is computed normally with a 50/50 duty cycle. - * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate - * Prescaler. - */ -/*@{*/ -#define BP_SPI_CTARn_DBR (31U) /*!< Bit position for SPI_CTARn_DBR. */ -#define BM_SPI_CTARn_DBR (0x80000000U) /*!< Bit mask for SPI_CTARn_DBR. */ -#define BS_SPI_CTARn_DBR (1U) /*!< Bit field size in bits for SPI_CTARn_DBR. */ - -/*! @brief Read current value of the SPI_CTARn_DBR field. */ -#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR)) - -/*! @brief Format value for bitfield SPI_CTARn_DBR. */ -#define BF_SPI_CTARn_DBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR) - -/*! @brief Set the DBR field to a new value. */ -#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v)) -/*@}*/ -/******************************************************************************* - * HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) - ******************************************************************************/ - -/*! - * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW) - * - * Reset value: 0x78000000U - * - * When the module is configured as an SPI bus slave, the CTAR0 register is used. - */ -typedef union _hw_spi_ctarn_slave -{ - uint32_t U; - struct _hw_spi_ctarn_slave_bitfields - { - uint32_t RESERVED0 : 25; /*!< [24:0] */ - uint32_t CPHA : 1; /*!< [25] Clock Phase */ - uint32_t CPOL : 1; /*!< [26] Clock Polarity */ - uint32_t FMSZ : 5; /*!< [31:27] Frame Size */ - } B; -} hw_spi_ctarn_slave_t; - -/*! - * @name Constants and macros for entire SPI_CTARn_SLAVE register - */ -/*@{*/ -#define HW_SPI_CTARn_SLAVE_COUNT (1U) - -#define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n))) - -#define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n)) -#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U) -#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v)) -#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v))) -#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v))) -#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_CTARn_SLAVE bitfields - */ - -/*! - * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW) - * - * Selects which edge of SCK causes data to change and which edge causes data to - * be captured. This bit is used in both master and slave mode. For successful - * communication between serial devices, the devices must have identical clock - * phase settings. In Continuous SCK mode, the bit value is ignored and the - * transfers are done as if the CPHA bit is set to 1. - * - * Values: - * - 0 - Data is captured on the leading edge of SCK and changed on the - * following edge. - * - 1 - Data is changed on the leading edge of SCK and captured on the - * following edge. - */ -/*@{*/ -#define BP_SPI_CTARn_SLAVE_CPHA (25U) /*!< Bit position for SPI_CTARn_SLAVE_CPHA. */ -#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPHA. */ -#define BS_SPI_CTARn_SLAVE_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. */ - -/*! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. */ -#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA)) - -/*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. */ -#define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA) - -/*! @brief Set the CPHA field to a new value. */ -#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW) - * - * Selects the inactive state of the Serial Communications Clock (SCK). In case - * of continous sck mode, when the module goes in low power mode(disabled), - * inactive state of sck is not guaranted. - * - * Values: - * - 0 - The inactive state value of SCK is low. - * - 1 - The inactive state value of SCK is high. - */ -/*@{*/ -#define BP_SPI_CTARn_SLAVE_CPOL (26U) /*!< Bit position for SPI_CTARn_SLAVE_CPOL. */ -#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPOL. */ -#define BS_SPI_CTARn_SLAVE_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. */ - -/*! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. */ -#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL)) - -/*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. */ -#define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL) - -/*! @brief Set the CPOL field to a new value. */ -#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW) - * - * The number of bits transfered per frame is equal to the FMSZ field value plus - * 1. Note that the minimum valid value of frame size is 4. - */ -/*@{*/ -#define BP_SPI_CTARn_SLAVE_FMSZ (27U) /*!< Bit position for SPI_CTARn_SLAVE_FMSZ. */ -#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /*!< Bit mask for SPI_CTARn_SLAVE_FMSZ. */ -#define BS_SPI_CTARn_SLAVE_FMSZ (5U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. */ - -/*! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. */ -#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ) - -/*! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. */ -#define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ) - -/*! @brief Set the FMSZ field to a new value. */ -#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v))) -/*@}*/ - -/******************************************************************************* - * HW_SPI_SR - Status Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_SR - Status Register (RW) - * - * Reset value: 0x02000000U - * - * SR contains status and flag bits. The bits reflect the status of the module - * and indicate the occurrence of events that can generate interrupt or DMA - * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0 - * to a flag bit has no effect. This register may not be writable in Module - * Disable mode due to the use of power saving mechanisms. - */ -typedef union _hw_spi_sr -{ - uint32_t U; - struct _hw_spi_sr_bitfields - { - uint32_t POPNXTPTR : 4; /*!< [3:0] Pop Next Pointer */ - uint32_t RXCTR : 4; /*!< [7:4] RX FIFO Counter */ - uint32_t TXNXTPTR : 4; /*!< [11:8] Transmit Next Pointer */ - uint32_t TXCTR : 4; /*!< [15:12] TX FIFO Counter */ - uint32_t RESERVED0 : 1; /*!< [16] */ - uint32_t RFDF : 1; /*!< [17] Receive FIFO Drain Flag */ - uint32_t RESERVED1 : 1; /*!< [18] */ - uint32_t RFOF : 1; /*!< [19] Receive FIFO Overflow Flag */ - uint32_t RESERVED2 : 5; /*!< [24:20] */ - uint32_t TFFF : 1; /*!< [25] Transmit FIFO Fill Flag */ - uint32_t RESERVED3 : 1; /*!< [26] */ - uint32_t TFUF : 1; /*!< [27] Transmit FIFO Underflow Flag */ - uint32_t EOQF : 1; /*!< [28] End of Queue Flag */ - uint32_t RESERVED4 : 1; /*!< [29] */ - uint32_t TXRXS : 1; /*!< [30] TX and RX Status */ - uint32_t TCF : 1; /*!< [31] Transfer Complete Flag */ - } B; -} hw_spi_sr_t; - -/*! - * @name Constants and macros for entire SPI_SR register - */ -/*@{*/ -#define HW_SPI_SR_ADDR(x) ((x) + 0x2CU) - -#define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x)) -#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U) -#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v)) -#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v))) -#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v))) -#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_SR bitfields - */ - -/*! - * @name Register SPI_SR, field POPNXTPTR[3:0] (RO) - * - * Contains a pointer to the RX FIFO entry to be returned when the POPR is read. - * The POPNXTPTR is updated when the POPR is read. - */ -/*@{*/ -#define BP_SPI_SR_POPNXTPTR (0U) /*!< Bit position for SPI_SR_POPNXTPTR. */ -#define BM_SPI_SR_POPNXTPTR (0x0000000FU) /*!< Bit mask for SPI_SR_POPNXTPTR. */ -#define BS_SPI_SR_POPNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_POPNXTPTR. */ - -/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */ -#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field RXCTR[7:4] (RO) - * - * Indicates the number of entries in the RX FIFO. The RXCTR is decremented - * every time the POPR is read. The RXCTR is incremented every time data is - * transferred from the shift register to the RX FIFO. - */ -/*@{*/ -#define BP_SPI_SR_RXCTR (4U) /*!< Bit position for SPI_SR_RXCTR. */ -#define BM_SPI_SR_RXCTR (0x000000F0U) /*!< Bit mask for SPI_SR_RXCTR. */ -#define BS_SPI_SR_RXCTR (4U) /*!< Bit field size in bits for SPI_SR_RXCTR. */ - -/*! @brief Read current value of the SPI_SR_RXCTR field. */ -#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field TXNXTPTR[11:8] (RO) - * - * Indicates which TX FIFO entry is transmitted during the next transfer. The - * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to - * the shift register. - */ -/*@{*/ -#define BP_SPI_SR_TXNXTPTR (8U) /*!< Bit position for SPI_SR_TXNXTPTR. */ -#define BM_SPI_SR_TXNXTPTR (0x00000F00U) /*!< Bit mask for SPI_SR_TXNXTPTR. */ -#define BS_SPI_SR_TXNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_TXNXTPTR. */ - -/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */ -#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field TXCTR[15:12] (RO) - * - * Indicates the number of valid entries in the TX FIFO. The TXCTR is - * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI - * command is executed and the SPI data is transferred to the shift register. - */ -/*@{*/ -#define BP_SPI_SR_TXCTR (12U) /*!< Bit position for SPI_SR_TXCTR. */ -#define BM_SPI_SR_TXCTR (0x0000F000U) /*!< Bit mask for SPI_SR_TXCTR. */ -#define BS_SPI_SR_TXCTR (4U) /*!< Bit field size in bits for SPI_SR_TXCTR. */ - -/*! @brief Read current value of the SPI_SR_TXCTR field. */ -#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field RFDF[17] (W1C) - * - * Provides a method for the module to request that entries be removed from the - * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be - * cleared by writing 1 to it or by acknowledgement from the DMA controller when - * the RX FIFO is empty. - * - * Values: - * - 0 - RX FIFO is empty. - * - 1 - RX FIFO is not empty. - */ -/*@{*/ -#define BP_SPI_SR_RFDF (17U) /*!< Bit position for SPI_SR_RFDF. */ -#define BM_SPI_SR_RFDF (0x00020000U) /*!< Bit mask for SPI_SR_RFDF. */ -#define BS_SPI_SR_RFDF (1U) /*!< Bit field size in bits for SPI_SR_RFDF. */ - -/*! @brief Read current value of the SPI_SR_RFDF field. */ -#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF)) - -/*! @brief Format value for bitfield SPI_SR_RFDF. */ -#define BF_SPI_SR_RFDF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF) - -/*! @brief Set the RFDF field to a new value. */ -#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field RFOF[19] (W1C) - * - * Indicates an overflow condition in the RX FIFO. The field is set when the RX - * FIFO and shift register are full and a transfer is initiated. The bit remains - * set until it is cleared by writing a 1 to it. - * - * Values: - * - 0 - No Rx FIFO overflow. - * - 1 - Rx FIFO overflow has occurred. - */ -/*@{*/ -#define BP_SPI_SR_RFOF (19U) /*!< Bit position for SPI_SR_RFOF. */ -#define BM_SPI_SR_RFOF (0x00080000U) /*!< Bit mask for SPI_SR_RFOF. */ -#define BS_SPI_SR_RFOF (1U) /*!< Bit field size in bits for SPI_SR_RFOF. */ - -/*! @brief Read current value of the SPI_SR_RFOF field. */ -#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF)) - -/*! @brief Format value for bitfield SPI_SR_RFOF. */ -#define BF_SPI_SR_RFOF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF) - -/*! @brief Set the RFOF field to a new value. */ -#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TFFF[25] (W1C) - * - * Provides a method for the module to request more entries to be added to the - * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be - * cleared by writing 1 to it or by acknowledgement from the DMA controller to - * the TX FIFO full request. - * - * Values: - * - 0 - TX FIFO is full. - * - 1 - TX FIFO is not full. - */ -/*@{*/ -#define BP_SPI_SR_TFFF (25U) /*!< Bit position for SPI_SR_TFFF. */ -#define BM_SPI_SR_TFFF (0x02000000U) /*!< Bit mask for SPI_SR_TFFF. */ -#define BS_SPI_SR_TFFF (1U) /*!< Bit field size in bits for SPI_SR_TFFF. */ - -/*! @brief Read current value of the SPI_SR_TFFF field. */ -#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF)) - -/*! @brief Format value for bitfield SPI_SR_TFFF. */ -#define BF_SPI_SR_TFFF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF) - -/*! @brief Set the TFFF field to a new value. */ -#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TFUF[27] (W1C) - * - * Indicates an underflow condition in the TX FIFO. The transmit underflow - * condition is detected only for SPI blocks operating in Slave mode and SPI - * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode - * is empty and an external SPI master initiates a transfer. The TFUF bit remains - * set until cleared by writing 1 to it. - * - * Values: - * - 0 - No TX FIFO underflow. - * - 1 - TX FIFO underflow has occurred. - */ -/*@{*/ -#define BP_SPI_SR_TFUF (27U) /*!< Bit position for SPI_SR_TFUF. */ -#define BM_SPI_SR_TFUF (0x08000000U) /*!< Bit mask for SPI_SR_TFUF. */ -#define BS_SPI_SR_TFUF (1U) /*!< Bit field size in bits for SPI_SR_TFUF. */ - -/*! @brief Read current value of the SPI_SR_TFUF field. */ -#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF)) - -/*! @brief Format value for bitfield SPI_SR_TFUF. */ -#define BF_SPI_SR_TFUF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF) - -/*! @brief Set the TFUF field to a new value. */ -#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field EOQF[28] (W1C) - * - * Indicates that the last entry in a queue has been transmitted when the module - * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit - * set in the command halfword and the end of the transfer is reached. The EOQF - * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set, - * the TXRXS bit is automatically cleared. - * - * Values: - * - 0 - EOQ is not set in the executing command. - * - 1 - EOQ is set in the executing SPI command. - */ -/*@{*/ -#define BP_SPI_SR_EOQF (28U) /*!< Bit position for SPI_SR_EOQF. */ -#define BM_SPI_SR_EOQF (0x10000000U) /*!< Bit mask for SPI_SR_EOQF. */ -#define BS_SPI_SR_EOQF (1U) /*!< Bit field size in bits for SPI_SR_EOQF. */ - -/*! @brief Read current value of the SPI_SR_EOQF field. */ -#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF)) - -/*! @brief Format value for bitfield SPI_SR_EOQF. */ -#define BF_SPI_SR_EOQF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF) - -/*! @brief Set the EOQF field to a new value. */ -#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TXRXS[30] (W1C) - * - * Reflects the run status of the module. - * - * Values: - * - 0 - Transmit and receive operations are disabled (The module is in Stopped - * state). - * - 1 - Transmit and receive operations are enabled (The module is in Running - * state). - */ -/*@{*/ -#define BP_SPI_SR_TXRXS (30U) /*!< Bit position for SPI_SR_TXRXS. */ -#define BM_SPI_SR_TXRXS (0x40000000U) /*!< Bit mask for SPI_SR_TXRXS. */ -#define BS_SPI_SR_TXRXS (1U) /*!< Bit field size in bits for SPI_SR_TXRXS. */ - -/*! @brief Read current value of the SPI_SR_TXRXS field. */ -#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS)) - -/*! @brief Format value for bitfield SPI_SR_TXRXS. */ -#define BF_SPI_SR_TXRXS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS) - -/*! @brief Set the TXRXS field to a new value. */ -#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TCF[31] (W1C) - * - * Indicates that all bits in a frame have been shifted out. TCF remains set - * until it is cleared by writing a 1 to it. - * - * Values: - * - 0 - Transfer not complete. - * - 1 - Transfer complete. - */ -/*@{*/ -#define BP_SPI_SR_TCF (31U) /*!< Bit position for SPI_SR_TCF. */ -#define BM_SPI_SR_TCF (0x80000000U) /*!< Bit mask for SPI_SR_TCF. */ -#define BS_SPI_SR_TCF (1U) /*!< Bit field size in bits for SPI_SR_TCF. */ - -/*! @brief Read current value of the SPI_SR_TCF field. */ -#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF)) - -/*! @brief Format value for bitfield SPI_SR_TCF. */ -#define BF_SPI_SR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF) - -/*! @brief Set the TCF field to a new value. */ -#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW) - * - * Reset value: 0x00000000U - * - * RSER controls DMA and interrupt requests. Do not write to the RSER while the - * module is in the Running state. - */ -typedef union _hw_spi_rser -{ - uint32_t U; - struct _hw_spi_rser_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t RFDF_DIRS : 1; /*!< [16] Receive FIFO Drain DMA or Interrupt - * Request Select */ - uint32_t RFDF_RE : 1; /*!< [17] Receive FIFO Drain Request Enable */ - uint32_t RESERVED1 : 1; /*!< [18] */ - uint32_t RFOF_RE : 1; /*!< [19] Receive FIFO Overflow Request Enable - * */ - uint32_t RESERVED2 : 4; /*!< [23:20] */ - uint32_t TFFF_DIRS : 1; /*!< [24] Transmit FIFO Fill DMA or Interrupt - * Request Select */ - uint32_t TFFF_RE : 1; /*!< [25] Transmit FIFO Fill Request Enable */ - uint32_t RESERVED3 : 1; /*!< [26] */ - uint32_t TFUF_RE : 1; /*!< [27] Transmit FIFO Underflow Request - * Enable */ - uint32_t EOQF_RE : 1; /*!< [28] Finished Request Enable */ - uint32_t RESERVED4 : 2; /*!< [30:29] */ - uint32_t TCF_RE : 1; /*!< [31] Transmission Complete Request Enable */ - } B; -} hw_spi_rser_t; - -/*! - * @name Constants and macros for entire SPI_RSER register - */ -/*@{*/ -#define HW_SPI_RSER_ADDR(x) ((x) + 0x30U) - -#define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x)) -#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U) -#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v)) -#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v))) -#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v))) -#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_RSER bitfields - */ - -/*! - * @name Register SPI_RSER, field RFDF_DIRS[16] (RW) - * - * Selects between generating a DMA request or an interrupt request. When the - * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the - * RFDF_DIRS bit selects between generating an interrupt request or a DMA request. - * - * Values: - * - 0 - Interrupt request. - * - 1 - DMA request. - */ -/*@{*/ -#define BP_SPI_RSER_RFDF_DIRS (16U) /*!< Bit position for SPI_RSER_RFDF_DIRS. */ -#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /*!< Bit mask for SPI_RSER_RFDF_DIRS. */ -#define BS_SPI_RSER_RFDF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_DIRS. */ - -/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */ -#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS)) - -/*! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. */ -#define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS) - -/*! @brief Set the RFDF_DIRS field to a new value. */ -#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field RFDF_RE[17] (RW) - * - * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit - * selects between generating an interrupt request or a DMA request. - * - * Values: - * - 0 - RFDF interrupt or DMA requests are disabled. - * - 1 - RFDF interrupt or DMA requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_RFDF_RE (17U) /*!< Bit position for SPI_RSER_RFDF_RE. */ -#define BM_SPI_RSER_RFDF_RE (0x00020000U) /*!< Bit mask for SPI_RSER_RFDF_RE. */ -#define BS_SPI_RSER_RFDF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_RE. */ - -/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */ -#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_RFDF_RE. */ -#define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE) - -/*! @brief Set the RFDF_RE field to a new value. */ -#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field RFOF_RE[19] (RW) - * - * Enables the RFOF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - RFOF interrupt requests are disabled. - * - 1 - RFOF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_RFOF_RE (19U) /*!< Bit position for SPI_RSER_RFOF_RE. */ -#define BM_SPI_RSER_RFOF_RE (0x00080000U) /*!< Bit mask for SPI_RSER_RFOF_RE. */ -#define BS_SPI_RSER_RFOF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFOF_RE. */ - -/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */ -#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_RFOF_RE. */ -#define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE) - -/*! @brief Set the RFOF_RE field to a new value. */ -#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TFFF_DIRS[24] (RW) - * - * Selects between generating a DMA request or an interrupt request. When - * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an - * interrupt request or a DMA request. - * - * Values: - * - 0 - TFFF flag generates interrupt requests. - * - 1 - TFFF flag generates DMA requests. - */ -/*@{*/ -#define BP_SPI_RSER_TFFF_DIRS (24U) /*!< Bit position for SPI_RSER_TFFF_DIRS. */ -#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /*!< Bit mask for SPI_RSER_TFFF_DIRS. */ -#define BS_SPI_RSER_TFFF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_DIRS. */ - -/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */ -#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS)) - -/*! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. */ -#define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS) - -/*! @brief Set the TFFF_DIRS field to a new value. */ -#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TFFF_RE[25] (RW) - * - * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit - * selects between generating an interrupt request or a DMA request. - * - * Values: - * - 0 - TFFF interrupts or DMA requests are disabled. - * - 1 - TFFF interrupts or DMA requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_TFFF_RE (25U) /*!< Bit position for SPI_RSER_TFFF_RE. */ -#define BM_SPI_RSER_TFFF_RE (0x02000000U) /*!< Bit mask for SPI_RSER_TFFF_RE. */ -#define BS_SPI_RSER_TFFF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_RE. */ - -/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */ -#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_TFFF_RE. */ -#define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE) - -/*! @brief Set the TFFF_RE field to a new value. */ -#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TFUF_RE[27] (RW) - * - * Enables the TFUF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - TFUF interrupt requests are disabled. - * - 1 - TFUF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_TFUF_RE (27U) /*!< Bit position for SPI_RSER_TFUF_RE. */ -#define BM_SPI_RSER_TFUF_RE (0x08000000U) /*!< Bit mask for SPI_RSER_TFUF_RE. */ -#define BS_SPI_RSER_TFUF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFUF_RE. */ - -/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */ -#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_TFUF_RE. */ -#define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE) - -/*! @brief Set the TFUF_RE field to a new value. */ -#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field EOQF_RE[28] (RW) - * - * Enables the EOQF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - EOQF interrupt requests are disabled. - * - 1 - EOQF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_EOQF_RE (28U) /*!< Bit position for SPI_RSER_EOQF_RE. */ -#define BM_SPI_RSER_EOQF_RE (0x10000000U) /*!< Bit mask for SPI_RSER_EOQF_RE. */ -#define BS_SPI_RSER_EOQF_RE (1U) /*!< Bit field size in bits for SPI_RSER_EOQF_RE. */ - -/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */ -#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_EOQF_RE. */ -#define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE) - -/*! @brief Set the EOQF_RE field to a new value. */ -#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TCF_RE[31] (RW) - * - * Enables TCF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - TCF interrupt requests are disabled. - * - 1 - TCF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_TCF_RE (31U) /*!< Bit position for SPI_RSER_TCF_RE. */ -#define BM_SPI_RSER_TCF_RE (0x80000000U) /*!< Bit mask for SPI_RSER_TCF_RE. */ -#define BS_SPI_RSER_TCF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TCF_RE. */ - -/*! @brief Read current value of the SPI_RSER_TCF_RE field. */ -#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_TCF_RE. */ -#define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE) - -/*! @brief Set the TCF_RE field to a new value. */ -#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode - ******************************************************************************/ - -/*! - * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW) - * - * Reset value: 0x00000000U - * - * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access - * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers - * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits - * can be used as data, supporting up to 32-bit frame operation. A read access - * of PUSHR returns the topmost TX FIFO entry. When the module is disabled, - * writing to this register does not update the FIFO. Therefore, any reads performed - * while the module is disabled return the last PUSHR write performed while the - * module was still enabled. - */ -typedef union _hw_spi_pushr -{ - uint32_t U; - struct _hw_spi_pushr_bitfields - { - uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */ - uint32_t PCS : 6; /*!< [21:16] */ - uint32_t RESERVED0 : 4; /*!< [25:22] */ - uint32_t CTCNT : 1; /*!< [26] Clear Transfer Counter */ - uint32_t EOQ : 1; /*!< [27] End Of Queue */ - uint32_t CTAS : 3; /*!< [30:28] Clock and Transfer Attributes Select - * */ - uint32_t CONT : 1; /*!< [31] Continuous Peripheral Chip Select Enable - * */ - } B; -} hw_spi_pushr_t; - -/*! - * @name Constants and macros for entire SPI_PUSHR register - */ -/*@{*/ -#define HW_SPI_PUSHR_ADDR(x) ((x) + 0x34U) - -#define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x)) -#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U) -#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v)) -#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v))) -#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v))) -#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_PUSHR bitfields - */ - -/*! - * @name Register SPI_PUSHR, field TXDATA[15:0] (RW) - * - * Holds SPI data to be transferred according to the associated SPI command. - */ -/*@{*/ -#define BP_SPI_PUSHR_TXDATA (0U) /*!< Bit position for SPI_PUSHR_TXDATA. */ -#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_PUSHR_TXDATA. */ -#define BS_SPI_PUSHR_TXDATA (16U) /*!< Bit field size in bits for SPI_PUSHR_TXDATA. */ - -/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */ -#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA) - -/*! @brief Format value for bitfield SPI_PUSHR_TXDATA. */ -#define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA) - -/*! @brief Set the TXDATA field to a new value. */ -#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v))) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field PCS[21:16] (RW) - * - * Select which PCS signals are to be asserted for the transfer. Refer to the - * chip configuration details for the number of PCS signals used in this MCU. - * - * Values: - * - 0 - Negate the PCS[x] signal. - * - 1 - Assert the PCS[x] signal. - */ -/*@{*/ -#define BP_SPI_PUSHR_PCS (16U) /*!< Bit position for SPI_PUSHR_PCS. */ -#define BM_SPI_PUSHR_PCS (0x003F0000U) /*!< Bit mask for SPI_PUSHR_PCS. */ -#define BS_SPI_PUSHR_PCS (6U) /*!< Bit field size in bits for SPI_PUSHR_PCS. */ - -/*! @brief Read current value of the SPI_PUSHR_PCS field. */ -#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS) - -/*! @brief Format value for bitfield SPI_PUSHR_PCS. */ -#define BF_SPI_PUSHR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS) - -/*! @brief Set the PCS field to a new value. */ -#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v))) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field CTCNT[26] (RW) - * - * Clears the TCNT field in the TCR register. The TCNT field is cleared before - * the module starts transmitting the current SPI frame. - * - * Values: - * - 0 - Do not clear the TCR[TCNT] field. - * - 1 - Clear the TCR[TCNT] field. - */ -/*@{*/ -#define BP_SPI_PUSHR_CTCNT (26U) /*!< Bit position for SPI_PUSHR_CTCNT. */ -#define BM_SPI_PUSHR_CTCNT (0x04000000U) /*!< Bit mask for SPI_PUSHR_CTCNT. */ -#define BS_SPI_PUSHR_CTCNT (1U) /*!< Bit field size in bits for SPI_PUSHR_CTCNT. */ - -/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */ -#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT)) - -/*! @brief Format value for bitfield SPI_PUSHR_CTCNT. */ -#define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT) - -/*! @brief Set the CTCNT field to a new value. */ -#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v)) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field EOQ[27] (RW) - * - * Host software uses this bit to signal to the module that the current SPI - * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the - * SR is set. - * - * Values: - * - 0 - The SPI data is not the last data to transfer. - * - 1 - The SPI data is the last data to transfer. - */ -/*@{*/ -#define BP_SPI_PUSHR_EOQ (27U) /*!< Bit position for SPI_PUSHR_EOQ. */ -#define BM_SPI_PUSHR_EOQ (0x08000000U) /*!< Bit mask for SPI_PUSHR_EOQ. */ -#define BS_SPI_PUSHR_EOQ (1U) /*!< Bit field size in bits for SPI_PUSHR_EOQ. */ - -/*! @brief Read current value of the SPI_PUSHR_EOQ field. */ -#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ)) - -/*! @brief Format value for bitfield SPI_PUSHR_EOQ. */ -#define BF_SPI_PUSHR_EOQ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ) - -/*! @brief Set the EOQ field to a new value. */ -#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v)) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field CTAS[30:28] (RW) - * - * Selects which CTAR to use in master mode to specify the transfer attributes - * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip - * configuration details to determine how many CTARs this device has. You should - * not program a value in this field for a register that is not present. - * - * Values: - * - 000 - CTAR0 - * - 001 - CTAR1 - * - 010 - Reserved - * - 011 - Reserved - * - 100 - Reserved - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SPI_PUSHR_CTAS (28U) /*!< Bit position for SPI_PUSHR_CTAS. */ -#define BM_SPI_PUSHR_CTAS (0x70000000U) /*!< Bit mask for SPI_PUSHR_CTAS. */ -#define BS_SPI_PUSHR_CTAS (3U) /*!< Bit field size in bits for SPI_PUSHR_CTAS. */ - -/*! @brief Read current value of the SPI_PUSHR_CTAS field. */ -#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS) - -/*! @brief Format value for bitfield SPI_PUSHR_CTAS. */ -#define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS) - -/*! @brief Set the CTAS field to a new value. */ -#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v))) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field CONT[31] (RW) - * - * Selects a continuous selection format. The bit is used in SPI Master mode. - * The bit enables the selected PCS signals to remain asserted between transfers. - * - * Values: - * - 0 - Return PCSn signals to their inactive state between transfers. - * - 1 - Keep PCSn signals asserted between transfers. - */ -/*@{*/ -#define BP_SPI_PUSHR_CONT (31U) /*!< Bit position for SPI_PUSHR_CONT. */ -#define BM_SPI_PUSHR_CONT (0x80000000U) /*!< Bit mask for SPI_PUSHR_CONT. */ -#define BS_SPI_PUSHR_CONT (1U) /*!< Bit field size in bits for SPI_PUSHR_CONT. */ - -/*! @brief Read current value of the SPI_PUSHR_CONT field. */ -#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT)) - -/*! @brief Format value for bitfield SPI_PUSHR_CONT. */ -#define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT) - -/*! @brief Set the CONT field to a new value. */ -#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v)) -/*@}*/ -/******************************************************************************* - * HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode - ******************************************************************************/ - -/*! - * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW) - * - * Reset value: 0x00000000U - * - * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access - * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register - * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In - * slave mode, all 32 register bits can be used as data, supporting up to 32-bit - * SPI Frame operation. - */ -typedef union _hw_spi_pushr_slave -{ - uint32_t U; - struct _hw_spi_pushr_slave_bitfields - { - uint32_t TXDATA : 32; /*!< [31:0] Transmit Data */ - } B; -} hw_spi_pushr_slave_t; - -/*! - * @name Constants and macros for entire SPI_PUSHR_SLAVE register - */ -/*@{*/ -#define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U) - -#define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x)) -#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U) -#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v)) -#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v))) -#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v))) -#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_PUSHR_SLAVE bitfields - */ - -/*! - * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW) - * - * Holds SPI data to be transferred according to the associated SPI command. - */ -/*@{*/ -#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) /*!< Bit position for SPI_PUSHR_SLAVE_TXDATA. */ -#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. */ -#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) /*!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. */ - -/*! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. */ -#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U) - -/*! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. */ -#define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA) - -/*! @brief Set the TXDATA field to a new value. */ -#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_POPR - POP RX FIFO Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_POPR - POP RX FIFO Register (RO) - * - * Reset value: 0x00000000U - * - * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the - * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to - * this register will generate a Transfer Error. - */ -typedef union _hw_spi_popr -{ - uint32_t U; - struct _hw_spi_popr_bitfields - { - uint32_t RXDATA : 32; /*!< [31:0] Received Data */ - } B; -} hw_spi_popr_t; - -/*! - * @name Constants and macros for entire SPI_POPR register - */ -/*@{*/ -#define HW_SPI_POPR_ADDR(x) ((x) + 0x38U) - -#define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x)) -#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U) -/*@}*/ - -/* - * Constants & macros for individual SPI_POPR bitfields - */ - -/*! - * @name Register SPI_POPR, field RXDATA[31:0] (RO) - * - * Contains the SPI data from the RX FIFO entry to which the Pop Next Data - * Pointer points. - */ -/*@{*/ -#define BP_SPI_POPR_RXDATA (0U) /*!< Bit position for SPI_POPR_RXDATA. */ -#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_POPR_RXDATA. */ -#define BS_SPI_POPR_RXDATA (32U) /*!< Bit field size in bits for SPI_POPR_RXDATA. */ - -/*! @brief Read current value of the SPI_POPR_RXDATA field. */ -#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SPI_TXFRn - Transmit FIFO Registers - ******************************************************************************/ - -/*! - * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO) - * - * Reset value: 0x00000000U - * - * TXFRn registers provide visibility into the TX FIFO for debugging purposes. - * Each register is an entry in the TX FIFO. The registers are read-only and - * cannot be modified. Reading the TXFRx registers does not alter the state of the TX - * FIFO. - */ -typedef union _hw_spi_txfrn -{ - uint32_t U; - struct _hw_spi_txfrn_bitfields - { - uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */ - uint32_t TXCMD_TXDATA : 16; /*!< [31:16] Transmit Command or Transmit - * Data */ - } B; -} hw_spi_txfrn_t; - -/*! - * @name Constants and macros for entire SPI_TXFRn register - */ -/*@{*/ -#define HW_SPI_TXFRn_COUNT (4U) - -#define HW_SPI_TXFRn_ADDR(x, n) ((x) + 0x3CU + (0x4U * (n))) - -#define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n)) -#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual SPI_TXFRn bitfields - */ - -/*! - * @name Register SPI_TXFRn, field TXDATA[15:0] (RO) - * - * Contains the SPI data to be shifted out. - */ -/*@{*/ -#define BP_SPI_TXFRn_TXDATA (0U) /*!< Bit position for SPI_TXFRn_TXDATA. */ -#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_TXFRn_TXDATA. */ -#define BS_SPI_TXFRn_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXDATA. */ - -/*! @brief Read current value of the SPI_TXFRn_TXDATA field. */ -#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA) -/*@}*/ - -/*! - * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO) - * - * In Master mode the TXCMD field contains the command that sets the transfer - * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of - * the SPI data to be shifted out. - */ -/*@{*/ -#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit position for SPI_TXFRn_TXCMD_TXDATA. */ -#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /*!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. */ -#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. */ - -/*! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. */ -#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA) -/*@}*/ - -/******************************************************************************* - * HW_SPI_RXFRn - Receive FIFO Registers - ******************************************************************************/ - -/*! - * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO) - * - * Reset value: 0x00000000U - * - * RXFRn provide visibility into the RX FIFO for debugging purposes. Each - * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the - * RXFRx registers does not alter the state of the RX FIFO. - */ -typedef union _hw_spi_rxfrn -{ - uint32_t U; - struct _hw_spi_rxfrn_bitfields - { - uint32_t RXDATA : 32; /*!< [31:0] Receive Data */ - } B; -} hw_spi_rxfrn_t; - -/*! - * @name Constants and macros for entire SPI_RXFRn register - */ -/*@{*/ -#define HW_SPI_RXFRn_COUNT (4U) - -#define HW_SPI_RXFRn_ADDR(x, n) ((x) + 0x7CU + (0x4U * (n))) - -#define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n)) -#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual SPI_RXFRn bitfields - */ - -/*! - * @name Register SPI_RXFRn, field RXDATA[31:0] (RO) - * - * Contains the received SPI data. - */ -/*@{*/ -#define BP_SPI_RXFRn_RXDATA (0U) /*!< Bit position for SPI_RXFRn_RXDATA. */ -#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_RXFRn_RXDATA. */ -#define BS_SPI_RXFRn_RXDATA (32U) /*!< Bit field size in bits for SPI_RXFRn_RXDATA. */ - -/*! @brief Read current value of the SPI_RXFRn_RXDATA field. */ -#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_spi_t - module struct - ******************************************************************************/ -/*! - * @brief All SPI module registers. - */ -#pragma pack(1) -typedef struct _hw_spi -{ - __IO hw_spi_mcr_t MCR; /*!< [0x0] Module Configuration Register */ - uint8_t _reserved0[4]; - __IO hw_spi_tcr_t TCR; /*!< [0x8] Transfer Count Register */ - union { - __IO hw_spi_ctarn_t CTARn[2]; /*!< [0xC] Clock and Transfer Attributes Register (In Master Mode) */ - __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; /*!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) */ - }; - uint8_t _reserved1[24]; - __IO hw_spi_sr_t SR; /*!< [0x2C] Status Register */ - __IO hw_spi_rser_t RSER; /*!< [0x30] DMA/Interrupt Request Select and Enable Register */ - union { - __IO hw_spi_pushr_t PUSHR; /*!< [0x34] PUSH TX FIFO Register In Master Mode */ - __IO hw_spi_pushr_slave_t PUSHR_SLAVE; /*!< [0x34] PUSH TX FIFO Register In Slave Mode */ - }; - __I hw_spi_popr_t POPR; /*!< [0x38] POP RX FIFO Register */ - __I hw_spi_txfrn_t TXFRn[4]; /*!< [0x3C] Transmit FIFO Registers */ - uint8_t _reserved2[48]; - __I hw_spi_rxfrn_t RXFRn[4]; /*!< [0x7C] Receive FIFO Registers */ -} hw_spi_t; -#pragma pack() - -/*! @brief Macro to access all SPI registers. */ -/*! @param x SPI module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SPI(SPI0_BASE). */ -#define HW_SPI(x) (*(hw_spi_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_SPI_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h deleted file mode 100644 index f11f0435320..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h +++ /dev/null @@ -1,4876 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_UART_REGISTERS_H__ -#define __HW_UART_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 UART - * - * Serial Communication Interface - * - * Registers defined in this header file: - * - HW_UART_BDH - UART Baud Rate Registers: High - * - HW_UART_BDL - UART Baud Rate Registers: Low - * - HW_UART_C1 - UART Control Register 1 - * - HW_UART_C2 - UART Control Register 2 - * - HW_UART_S1 - UART Status Register 1 - * - HW_UART_S2 - UART Status Register 2 - * - HW_UART_C3 - UART Control Register 3 - * - HW_UART_D - UART Data Register - * - HW_UART_MA1 - UART Match Address Registers 1 - * - HW_UART_MA2 - UART Match Address Registers 2 - * - HW_UART_C4 - UART Control Register 4 - * - HW_UART_C5 - UART Control Register 5 - * - HW_UART_ED - UART Extended Data Register - * - HW_UART_MODEM - UART Modem Register - * - HW_UART_IR - UART Infrared Register - * - HW_UART_PFIFO - UART FIFO Parameters - * - HW_UART_CFIFO - UART FIFO Control Register - * - HW_UART_SFIFO - UART FIFO Status Register - * - HW_UART_TWFIFO - UART FIFO Transmit Watermark - * - HW_UART_TCFIFO - UART FIFO Transmit Count - * - HW_UART_RWFIFO - UART FIFO Receive Watermark - * - HW_UART_RCFIFO - UART FIFO Receive Count - * - HW_UART_C7816 - UART 7816 Control Register - * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register - * - HW_UART_IS7816 - UART 7816 Interrupt Status Register - * - HW_UART_WP7816 - UART 7816 Wait Parameter Register - * - HW_UART_WN7816 - UART 7816 Wait N Register - * - HW_UART_WF7816 - UART 7816 Wait FD Register - * - HW_UART_ET7816 - UART 7816 Error Threshold Register - * - HW_UART_TL7816 - UART 7816 Transmit Length Register - * - HW_UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A - * - HW_UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B - * - HW_UART_WP7816A_T0 - UART 7816 Wait Parameter Register A - * - HW_UART_WP7816B_T0 - UART 7816 Wait Parameter Register B - * - HW_UART_WP7816A_T1 - UART 7816 Wait Parameter Register A - * - HW_UART_WP7816B_T1 - UART 7816 Wait Parameter Register B - * - HW_UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register - * - HW_UART_WP7816C_T1 - UART 7816 Wait Parameter Register C - * - * - hw_uart_t - Struct containing all module registers. - */ - -#define HW_UART_INSTANCE_COUNT (3U) /*!< Number of instances of the UART module. */ -#define HW_UART0 (0U) /*!< Instance number for UART0. */ -#define HW_UART1 (1U) /*!< Instance number for UART1. */ -#define HW_UART2 (2U) /*!< Instance number for UART2. */ - -/******************************************************************************* - * HW_UART_BDH - UART Baud Rate Registers: High - ******************************************************************************/ - -/*! - * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW) - * - * Reset value: 0x00U - * - * This register, along with the BDL register, controls the prescale divisor for - * UART baud rate generation. To update the 13-bit baud rate setting - * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write - * to BDL. The working value in BDH does not change until BDL is written. BDL is - * reset to a nonzero value, but after reset, the baud rate generator remains - * disabled until the first time the receiver or transmitter is enabled, that is, - * when C2[RE] or C2[TE] is set. - */ -typedef union _hw_uart_bdh -{ - uint8_t U; - struct _hw_uart_bdh_bitfields - { - uint8_t SBR : 5; /*!< [4:0] UART Baud Rate Bits */ - uint8_t RESERVED0 : 1; /*!< [5] */ - uint8_t RXEDGIE : 1; /*!< [6] RxD Input Active Edge Interrupt Enable - * */ - uint8_t LBKDIE : 1; /*!< [7] LIN Break Detect Interrupt Enable */ - } B; -} hw_uart_bdh_t; - -/*! - * @name Constants and macros for entire UART_BDH register - */ -/*@{*/ -#define HW_UART_BDH_ADDR(x) ((x) + 0x0U) - -#define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x)) -#define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U) -#define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v)) -#define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v))) -#define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v))) -#define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_BDH bitfields - */ - -/*! - * @name Register UART_BDH, field SBR[4:0] (RW) - * - * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate - * generation for details. The baud rate generator is disabled until C2[TE] or - * C2[RE] is set for the first time after reset.The baud rate generator is disabled - * when SBR = 0. Writing to BDH has no effect without writing to BDL, because - * writing to BDH puts the data in a temporary location until BDL is written. - */ -/*@{*/ -#define BP_UART_BDH_SBR (0U) /*!< Bit position for UART_BDH_SBR. */ -#define BM_UART_BDH_SBR (0x1FU) /*!< Bit mask for UART_BDH_SBR. */ -#define BS_UART_BDH_SBR (5U) /*!< Bit field size in bits for UART_BDH_SBR. */ - -/*! @brief Read current value of the UART_BDH_SBR field. */ -#define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR) - -/*! @brief Format value for bitfield UART_BDH_SBR. */ -#define BF_UART_BDH_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR) - -/*! @brief Set the SBR field to a new value. */ -#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v))) -/*@}*/ - -/*! - * @name Register UART_BDH, field RXEDGIE[6] (RW) - * - * Enables the receive input active edge, RXEDGIF, to generate interrupt - * requests. - * - * Values: - * - 0 - Hardware interrupts from RXEDGIF disabled using polling. - * - 1 - RXEDGIF interrupt request enabled. - */ -/*@{*/ -#define BP_UART_BDH_RXEDGIE (6U) /*!< Bit position for UART_BDH_RXEDGIE. */ -#define BM_UART_BDH_RXEDGIE (0x40U) /*!< Bit mask for UART_BDH_RXEDGIE. */ -#define BS_UART_BDH_RXEDGIE (1U) /*!< Bit field size in bits for UART_BDH_RXEDGIE. */ - -/*! @brief Read current value of the UART_BDH_RXEDGIE field. */ -#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE)) - -/*! @brief Format value for bitfield UART_BDH_RXEDGIE. */ -#define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE) - -/*! @brief Set the RXEDGIE field to a new value. */ -#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_BDH, field LBKDIE[7] (RW) - * - * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests - * based on the state of LBKDDMAS. - * - * Values: - * - 0 - LBKDIF interrupt requests disabled. - * - 1 - LBKDIF interrupt requests enabled. - */ -/*@{*/ -#define BP_UART_BDH_LBKDIE (7U) /*!< Bit position for UART_BDH_LBKDIE. */ -#define BM_UART_BDH_LBKDIE (0x80U) /*!< Bit mask for UART_BDH_LBKDIE. */ -#define BS_UART_BDH_LBKDIE (1U) /*!< Bit field size in bits for UART_BDH_LBKDIE. */ - -/*! @brief Read current value of the UART_BDH_LBKDIE field. */ -#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE)) - -/*! @brief Format value for bitfield UART_BDH_LBKDIE. */ -#define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE) - -/*! @brief Set the LBKDIE field to a new value. */ -#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_BDL - UART Baud Rate Registers: Low - ******************************************************************************/ - -/*! - * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW) - * - * Reset value: 0x04U - * - * This register, along with the BDH register, controls the prescale divisor for - * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0], - * first write to BDH to buffer the high half of the new value and then write to - * BDL. The working value in BDH does not change until BDL is written. BDL is - * reset to a nonzero value, but after reset, the baud rate generator remains - * disabled until the first time the receiver or transmitter is enabled, that is, when - * C2[RE] or C2[TE] is set. - */ -typedef union _hw_uart_bdl -{ - uint8_t U; - struct _hw_uart_bdl_bitfields - { - uint8_t SBR : 8; /*!< [7:0] UART Baud Rate Bits */ - } B; -} hw_uart_bdl_t; - -/*! - * @name Constants and macros for entire UART_BDL register - */ -/*@{*/ -#define HW_UART_BDL_ADDR(x) ((x) + 0x1U) - -#define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x)) -#define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U) -#define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v)) -#define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v))) -#define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v))) -#define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_BDL bitfields - */ - -/*! - * @name Register UART_BDL, field SBR[7:0] (RW) - * - * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate - * generation for details. The baud rate generator is disabled until C2[TE] or - * C2[RE] is set for the first time after reset.The baud rate generator is disabled - * when SBR = 0. Writing to BDH has no effect without writing to BDL, because - * writing to BDH puts the data in a temporary location until BDL is written. When - * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate - * fields must be even, the least significant bit is 0. See MODEM register for more - * details. - */ -/*@{*/ -#define BP_UART_BDL_SBR (0U) /*!< Bit position for UART_BDL_SBR. */ -#define BM_UART_BDL_SBR (0xFFU) /*!< Bit mask for UART_BDL_SBR. */ -#define BS_UART_BDL_SBR (8U) /*!< Bit field size in bits for UART_BDL_SBR. */ - -/*! @brief Read current value of the UART_BDL_SBR field. */ -#define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U) - -/*! @brief Format value for bitfield UART_BDL_SBR. */ -#define BF_UART_BDL_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR) - -/*! @brief Set the SBR field to a new value. */ -#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C1 - UART Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_UART_C1 - UART Control Register 1 (RW) - * - * Reset value: 0x00U - * - * This read/write register controls various optional features of the UART - * system. - */ -typedef union _hw_uart_c1 -{ - uint8_t U; - struct _hw_uart_c1_bitfields - { - uint8_t PT : 1; /*!< [0] Parity Type */ - uint8_t PE : 1; /*!< [1] Parity Enable */ - uint8_t ILT : 1; /*!< [2] Idle Line Type Select */ - uint8_t WAKE : 1; /*!< [3] Receiver Wakeup Method Select */ - uint8_t M : 1; /*!< [4] 9-bit or 8-bit Mode Select */ - uint8_t RSRC : 1; /*!< [5] Receiver Source Select */ - uint8_t UARTSWAI : 1; /*!< [6] UART Stops in Wait Mode */ - uint8_t LOOPS : 1; /*!< [7] Loop Mode Select */ - } B; -} hw_uart_c1_t; - -/*! - * @name Constants and macros for entire UART_C1 register - */ -/*@{*/ -#define HW_UART_C1_ADDR(x) ((x) + 0x2U) - -#define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x)) -#define HW_UART_C1_RD(x) (HW_UART_C1(x).U) -#define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v)) -#define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v))) -#define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v))) -#define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C1 bitfields - */ - -/*! - * @name Register UART_C1, field PT[0] (RW) - * - * Determines whether the UART generates and checks for even parity or odd - * parity. With even parity, an even number of 1s clears the parity bit and an odd - * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the - * parity bit and an even number of 1s sets the parity bit. This field must be - * cleared when C7816[ISO_7816E] is set/enabled. - * - * Values: - * - 0 - Even parity. - * - 1 - Odd parity. - */ -/*@{*/ -#define BP_UART_C1_PT (0U) /*!< Bit position for UART_C1_PT. */ -#define BM_UART_C1_PT (0x01U) /*!< Bit mask for UART_C1_PT. */ -#define BS_UART_C1_PT (1U) /*!< Bit field size in bits for UART_C1_PT. */ - -/*! @brief Read current value of the UART_C1_PT field. */ -#define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT)) - -/*! @brief Format value for bitfield UART_C1_PT. */ -#define BF_UART_C1_PT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT) - -/*! @brief Set the PT field to a new value. */ -#define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field PE[1] (RW) - * - * Enables the parity function. When parity is enabled, parity function inserts - * a parity bit in the bit position immediately preceding the stop bit. This - * field must be set when C7816[ISO_7816E] is set/enabled. - * - * Values: - * - 0 - Parity function disabled. - * - 1 - Parity function enabled. - */ -/*@{*/ -#define BP_UART_C1_PE (1U) /*!< Bit position for UART_C1_PE. */ -#define BM_UART_C1_PE (0x02U) /*!< Bit mask for UART_C1_PE. */ -#define BS_UART_C1_PE (1U) /*!< Bit field size in bits for UART_C1_PE. */ - -/*! @brief Read current value of the UART_C1_PE field. */ -#define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE)) - -/*! @brief Format value for bitfield UART_C1_PE. */ -#define BF_UART_C1_PE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE) - -/*! @brief Set the PE field to a new value. */ -#define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field ILT[2] (RW) - * - * Determines when the receiver starts counting logic 1s as idle character bits. - * The count begins either after a valid start bit or after the stop bit. If the - * count begins after the start bit, then a string of logic 1s preceding the - * stop bit can cause false recognition of an idle character. Beginning the count - * after the stop bit avoids false idle character recognition, but requires - * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a - * logic of 1'b0 is automatically shifted after a received stop bit, therefore - * resetting the idle count. In case the UART is programmed for IDLE line wakeup - * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting - * logic 1s as idle character bits. In idle line wakeup, an idle character is - * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE, - * and C4[M10] fields. - * - * Values: - * - 0 - Idle character bit count starts after start bit. - * - 1 - Idle character bit count starts after stop bit. - */ -/*@{*/ -#define BP_UART_C1_ILT (2U) /*!< Bit position for UART_C1_ILT. */ -#define BM_UART_C1_ILT (0x04U) /*!< Bit mask for UART_C1_ILT. */ -#define BS_UART_C1_ILT (1U) /*!< Bit field size in bits for UART_C1_ILT. */ - -/*! @brief Read current value of the UART_C1_ILT field. */ -#define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT)) - -/*! @brief Format value for bitfield UART_C1_ILT. */ -#define BF_UART_C1_ILT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT) - -/*! @brief Set the ILT field to a new value. */ -#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field WAKE[3] (RW) - * - * Determines which condition wakes the UART: Address mark in the most - * significant bit position of a received data character, or An idle condition on the - * receive pin input signal. - * - * Values: - * - 0 - Idle line wakeup. - * - 1 - Address mark wakeup. - */ -/*@{*/ -#define BP_UART_C1_WAKE (3U) /*!< Bit position for UART_C1_WAKE. */ -#define BM_UART_C1_WAKE (0x08U) /*!< Bit mask for UART_C1_WAKE. */ -#define BS_UART_C1_WAKE (1U) /*!< Bit field size in bits for UART_C1_WAKE. */ - -/*! @brief Read current value of the UART_C1_WAKE field. */ -#define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE)) - -/*! @brief Format value for bitfield UART_C1_WAKE. */ -#define BF_UART_C1_WAKE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE) - -/*! @brief Set the WAKE field to a new value. */ -#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field M[4] (RW) - * - * This field must be set when C7816[ISO_7816E] is set/enabled. - * - * Values: - * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. - * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. - */ -/*@{*/ -#define BP_UART_C1_M (4U) /*!< Bit position for UART_C1_M. */ -#define BM_UART_C1_M (0x10U) /*!< Bit mask for UART_C1_M. */ -#define BS_UART_C1_M (1U) /*!< Bit field size in bits for UART_C1_M. */ - -/*! @brief Read current value of the UART_C1_M field. */ -#define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M)) - -/*! @brief Format value for bitfield UART_C1_M. */ -#define BF_UART_C1_M(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M) - -/*! @brief Set the M field to a new value. */ -#define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field RSRC[5] (RW) - * - * This field has no meaning or effect unless the LOOPS field is set. When LOOPS - * is set, the RSRC field determines the source for the receiver shift register - * input. - * - * Values: - * - 0 - Selects internal loop back mode. The receiver input is internally - * connected to transmitter output. - * - 1 - Single wire UART mode where the receiver input is connected to the - * transmit pin input signal. - */ -/*@{*/ -#define BP_UART_C1_RSRC (5U) /*!< Bit position for UART_C1_RSRC. */ -#define BM_UART_C1_RSRC (0x20U) /*!< Bit mask for UART_C1_RSRC. */ -#define BS_UART_C1_RSRC (1U) /*!< Bit field size in bits for UART_C1_RSRC. */ - -/*! @brief Read current value of the UART_C1_RSRC field. */ -#define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC)) - -/*! @brief Format value for bitfield UART_C1_RSRC. */ -#define BF_UART_C1_RSRC(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC) - -/*! @brief Set the RSRC field to a new value. */ -#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field UARTSWAI[6] (RW) - * - * Values: - * - 0 - UART clock continues to run in Wait mode. - * - 1 - UART clock freezes while CPU is in Wait mode. - */ -/*@{*/ -#define BP_UART_C1_UARTSWAI (6U) /*!< Bit position for UART_C1_UARTSWAI. */ -#define BM_UART_C1_UARTSWAI (0x40U) /*!< Bit mask for UART_C1_UARTSWAI. */ -#define BS_UART_C1_UARTSWAI (1U) /*!< Bit field size in bits for UART_C1_UARTSWAI. */ - -/*! @brief Read current value of the UART_C1_UARTSWAI field. */ -#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI)) - -/*! @brief Format value for bitfield UART_C1_UARTSWAI. */ -#define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI) - -/*! @brief Set the UARTSWAI field to a new value. */ -#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field LOOPS[7] (RW) - * - * When LOOPS is set, the RxD pin is disconnected from the UART and the - * transmitter output is internally connected to the receiver input. The transmitter and - * the receiver must be enabled to use the loop function. - * - * Values: - * - 0 - Normal operation. - * - 1 - Loop mode where transmitter output is internally connected to receiver - * input. The receiver input is determined by RSRC. - */ -/*@{*/ -#define BP_UART_C1_LOOPS (7U) /*!< Bit position for UART_C1_LOOPS. */ -#define BM_UART_C1_LOOPS (0x80U) /*!< Bit mask for UART_C1_LOOPS. */ -#define BS_UART_C1_LOOPS (1U) /*!< Bit field size in bits for UART_C1_LOOPS. */ - -/*! @brief Read current value of the UART_C1_LOOPS field. */ -#define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS)) - -/*! @brief Format value for bitfield UART_C1_LOOPS. */ -#define BF_UART_C1_LOOPS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS) - -/*! @brief Set the LOOPS field to a new value. */ -#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C2 - UART Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_UART_C2 - UART Control Register 2 (RW) - * - * Reset value: 0x00U - * - * This register can be read or written at any time. - */ -typedef union _hw_uart_c2 -{ - uint8_t U; - struct _hw_uart_c2_bitfields - { - uint8_t SBK : 1; /*!< [0] Send Break */ - uint8_t RWU : 1; /*!< [1] Receiver Wakeup Control */ - uint8_t RE : 1; /*!< [2] Receiver Enable */ - uint8_t TE : 1; /*!< [3] Transmitter Enable */ - uint8_t ILIE : 1; /*!< [4] Idle Line Interrupt Enable */ - uint8_t RIE : 1; /*!< [5] Receiver Full Interrupt or DMA Transfer - * Enable */ - uint8_t TCIE : 1; /*!< [6] Transmission Complete Interrupt Enable */ - uint8_t TIE : 1; /*!< [7] Transmitter Interrupt or DMA Transfer - * Enable. */ - } B; -} hw_uart_c2_t; - -/*! - * @name Constants and macros for entire UART_C2 register - */ -/*@{*/ -#define HW_UART_C2_ADDR(x) ((x) + 0x3U) - -#define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x)) -#define HW_UART_C2_RD(x) (HW_UART_C2(x).U) -#define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v)) -#define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v))) -#define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v))) -#define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C2 bitfields - */ - -/*! - * @name Register UART_C2, field SBK[0] (RW) - * - * Toggling SBK sends one break character from the following: See Transmitting - * break characters for the number of logic 0s for the different configurations. - * Toggling implies clearing the SBK field before the break character has finished - * transmitting. As long as SBK is set, the transmitter continues to send - * complete break characters (10, 11, or 12 bits, or 13 or 14 bits). Ensure that C2[TE] - * is asserted atleast 1 clock before assertion of this bit. 10, 11, or 12 logic - * 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13] is set. This field - * must be cleared when C7816[ISO_7816E] is set. - * - * Values: - * - 0 - Normal transmitter operation. - * - 1 - Queue break characters to be sent. - */ -/*@{*/ -#define BP_UART_C2_SBK (0U) /*!< Bit position for UART_C2_SBK. */ -#define BM_UART_C2_SBK (0x01U) /*!< Bit mask for UART_C2_SBK. */ -#define BS_UART_C2_SBK (1U) /*!< Bit field size in bits for UART_C2_SBK. */ - -/*! @brief Read current value of the UART_C2_SBK field. */ -#define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK)) - -/*! @brief Format value for bitfield UART_C2_SBK. */ -#define BF_UART_C2_SBK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK) - -/*! @brief Set the SBK field to a new value. */ -#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field RWU[1] (RW) - * - * This field can be set to place the UART receiver in a standby state. RWU - * automatically clears when an RWU event occurs, that is, an IDLE event when - * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be - * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup - * on idle) if the channel is currently not idle. This can be determined by - * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already - * idle, it is possible that the UART will discard data. This is because the data - * must be received or a LIN break detected after an IDLE is detected before IDLE - * is allowed to reasserted. - * - * Values: - * - 0 - Normal operation. - * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt - * requests. Normally, hardware wakes the receiver by automatically clearing - * RWU. - */ -/*@{*/ -#define BP_UART_C2_RWU (1U) /*!< Bit position for UART_C2_RWU. */ -#define BM_UART_C2_RWU (0x02U) /*!< Bit mask for UART_C2_RWU. */ -#define BS_UART_C2_RWU (1U) /*!< Bit field size in bits for UART_C2_RWU. */ - -/*! @brief Read current value of the UART_C2_RWU field. */ -#define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU)) - -/*! @brief Format value for bitfield UART_C2_RWU. */ -#define BF_UART_C2_RWU(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU) - -/*! @brief Set the RWU field to a new value. */ -#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field RE[2] (RW) - * - * Enables the UART receiver. - * - * Values: - * - 0 - Receiver off. - * - 1 - Receiver on. - */ -/*@{*/ -#define BP_UART_C2_RE (2U) /*!< Bit position for UART_C2_RE. */ -#define BM_UART_C2_RE (0x04U) /*!< Bit mask for UART_C2_RE. */ -#define BS_UART_C2_RE (1U) /*!< Bit field size in bits for UART_C2_RE. */ - -/*! @brief Read current value of the UART_C2_RE field. */ -#define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE)) - -/*! @brief Format value for bitfield UART_C2_RE. */ -#define BF_UART_C2_RE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE) - -/*! @brief Set the RE field to a new value. */ -#define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field TE[3] (RW) - * - * Enables the UART transmitter. TE can be used to queue an idle preamble by - * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and - * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been - * transmitted. This condition is detected when TL7816[TLEN] = 0 and four - * additional characters are transmitted. - * - * Values: - * - 0 - Transmitter off. - * - 1 - Transmitter on. - */ -/*@{*/ -#define BP_UART_C2_TE (3U) /*!< Bit position for UART_C2_TE. */ -#define BM_UART_C2_TE (0x08U) /*!< Bit mask for UART_C2_TE. */ -#define BS_UART_C2_TE (1U) /*!< Bit field size in bits for UART_C2_TE. */ - -/*! @brief Read current value of the UART_C2_TE field. */ -#define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE)) - -/*! @brief Format value for bitfield UART_C2_TE. */ -#define BF_UART_C2_TE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE) - -/*! @brief Set the TE field to a new value. */ -#define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field ILIE[4] (RW) - * - * Enables the idle line flag, S1[IDLE], to generate interrupt requests - * - * Values: - * - 0 - IDLE interrupt requests disabled. - * - 1 - IDLE interrupt requests enabled. - */ -/*@{*/ -#define BP_UART_C2_ILIE (4U) /*!< Bit position for UART_C2_ILIE. */ -#define BM_UART_C2_ILIE (0x10U) /*!< Bit mask for UART_C2_ILIE. */ -#define BS_UART_C2_ILIE (1U) /*!< Bit field size in bits for UART_C2_ILIE. */ - -/*! @brief Read current value of the UART_C2_ILIE field. */ -#define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE)) - -/*! @brief Format value for bitfield UART_C2_ILIE. */ -#define BF_UART_C2_ILIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE) - -/*! @brief Set the ILIE field to a new value. */ -#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field RIE[5] (RW) - * - * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, - * based on the state of C5[RDMAS]. - * - * Values: - * - 0 - RDRF interrupt and DMA transfer requests disabled. - * - 1 - RDRF interrupt or DMA transfer requests enabled. - */ -/*@{*/ -#define BP_UART_C2_RIE (5U) /*!< Bit position for UART_C2_RIE. */ -#define BM_UART_C2_RIE (0x20U) /*!< Bit mask for UART_C2_RIE. */ -#define BS_UART_C2_RIE (1U) /*!< Bit field size in bits for UART_C2_RIE. */ - -/*! @brief Read current value of the UART_C2_RIE field. */ -#define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE)) - -/*! @brief Format value for bitfield UART_C2_RIE. */ -#define BF_UART_C2_RIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE) - -/*! @brief Set the RIE field to a new value. */ -#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field TCIE[6] (RW) - * - * Enables the transmission complete flag, S1[TC], to generate interrupt - * requests . - * - * Values: - * - 0 - TC interrupt requests disabled. - * - 1 - TC interrupt requests enabled. - */ -/*@{*/ -#define BP_UART_C2_TCIE (6U) /*!< Bit position for UART_C2_TCIE. */ -#define BM_UART_C2_TCIE (0x40U) /*!< Bit mask for UART_C2_TCIE. */ -#define BS_UART_C2_TCIE (1U) /*!< Bit field size in bits for UART_C2_TCIE. */ - -/*! @brief Read current value of the UART_C2_TCIE field. */ -#define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE)) - -/*! @brief Format value for bitfield UART_C2_TCIE. */ -#define BF_UART_C2_TCIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE) - -/*! @brief Set the TCIE field to a new value. */ -#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field TIE[7] (RW) - * - * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, - * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE - * must be cleared, and D[D] must not be written unless servicing a DMA request. - * - * Values: - * - 0 - TDRE interrupt and DMA transfer requests disabled. - * - 1 - TDRE interrupt or DMA transfer requests enabled. - */ -/*@{*/ -#define BP_UART_C2_TIE (7U) /*!< Bit position for UART_C2_TIE. */ -#define BM_UART_C2_TIE (0x80U) /*!< Bit mask for UART_C2_TIE. */ -#define BS_UART_C2_TIE (1U) /*!< Bit field size in bits for UART_C2_TIE. */ - -/*! @brief Read current value of the UART_C2_TIE field. */ -#define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE)) - -/*! @brief Format value for bitfield UART_C2_TIE. */ -#define BF_UART_C2_TIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_S1 - UART Status Register 1 - ******************************************************************************/ - -/*! - * @brief HW_UART_S1 - UART Status Register 1 (RO) - * - * Reset value: 0xC0U - * - * The S1 register provides inputs to the MCU for generation of UART interrupts - * or DMA requests. This register can also be polled by the MCU to check the - * status of its fields. To clear a flag, the status register should be read followed - * by a read or write to D register, depending on the interrupt flag type. Other - * instructions can be executed between the two steps as long the handling of - * I/O is not compromised, but the order of operations is important for flag - * clearing. When a flag is configured to trigger a DMA request, assertion of the - * associated DMA done signal from the DMA controller clears the flag. If the - * condition that results in the assertion of the flag, interrupt, or DMA request is not - * resolved prior to clearing the flag, the flag, and interrupt/DMA request, - * reasserts. For example, if the DMA or interrupt service routine fails to write - * sufficient data to the transmit buffer to raise it above the watermark level, the - * flag reasserts and generates another interrupt or DMA request. Reading an - * empty data register to clear one of the flags of the S1 register causes the FIFO - * pointers to become misaligned. A receive FIFO flush reinitializes the - * pointers. A better way to prevent this situation is to always leave one byte in FIFO - * and this byte will be read eventually in clearing the flag bit. - */ -typedef union _hw_uart_s1 -{ - uint8_t U; - struct _hw_uart_s1_bitfields - { - uint8_t PF : 1; /*!< [0] Parity Error Flag */ - uint8_t FE : 1; /*!< [1] Framing Error Flag */ - uint8_t NF : 1; /*!< [2] Noise Flag */ - uint8_t OR : 1; /*!< [3] Receiver Overrun Flag */ - uint8_t IDLE : 1; /*!< [4] Idle Line Flag */ - uint8_t RDRF : 1; /*!< [5] Receive Data Register Full Flag */ - uint8_t TC : 1; /*!< [6] Transmit Complete Flag */ - uint8_t TDRE : 1; /*!< [7] Transmit Data Register Empty Flag */ - } B; -} hw_uart_s1_t; - -/*! - * @name Constants and macros for entire UART_S1 register - */ -/*@{*/ -#define HW_UART_S1_ADDR(x) ((x) + 0x4U) - -#define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x)) -#define HW_UART_S1_RD(x) (HW_UART_S1(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_S1 bitfields - */ - -/*! - * @name Register UART_S1, field PF[0] (RO) - * - * PF is set when PE is set and the parity of the received data does not match - * its parity bit. The PF is not set in the case of an overrun condition. When PF - * is set, it indicates only that a dataword was received with parity error since - * the last time it was cleared. There is no guarantee that the first dataword - * read from the receive buffer has a parity error or that there is only one - * dataword in the buffer that was received with a parity error, unless the receive - * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is - * disabled, Within the receive buffer structure the received dataword is tagged - * if it is received with a parity error. This information is available by reading - * the ED register prior to reading the D register. - * - * Values: - * - 0 - No parity error detected since the last time this flag was cleared. If - * the receive buffer has a depth greater than 1, then there may be data in - * the receive buffer what was received with a parity error. - * - 1 - At least one dataword was received with a parity error since the last - * time this flag was cleared. - */ -/*@{*/ -#define BP_UART_S1_PF (0U) /*!< Bit position for UART_S1_PF. */ -#define BM_UART_S1_PF (0x01U) /*!< Bit mask for UART_S1_PF. */ -#define BS_UART_S1_PF (1U) /*!< Bit field size in bits for UART_S1_PF. */ - -/*! @brief Read current value of the UART_S1_PF field. */ -#define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF)) -/*@}*/ - -/*! - * @name Register UART_S1, field FE[1] (RO) - * - * FE is set when a logic 0 is accepted as the stop bit. FE does not set in the - * case of an overrun or while the LIN break detect feature is enabled (S2[LBKDE] - * = 1). FE inhibits further data reception until it is cleared. To clear FE, - * read S1 with FE set and then read D. The last data in the receive buffer - * represents the data that was received with the frame error enabled. Framing errors - * are not supported when 7816E is set/enabled. However, if this flag is set, data - * is still not received in 7816 mode. - * - * Values: - * - 0 - No framing error detected. - * - 1 - Framing error. - */ -/*@{*/ -#define BP_UART_S1_FE (1U) /*!< Bit position for UART_S1_FE. */ -#define BM_UART_S1_FE (0x02U) /*!< Bit mask for UART_S1_FE. */ -#define BS_UART_S1_FE (1U) /*!< Bit field size in bits for UART_S1_FE. */ - -/*! @brief Read current value of the UART_S1_FE field. */ -#define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE)) -/*@}*/ - -/*! - * @name Register UART_S1, field NF[2] (RO) - * - * NF is set when the UART detects noise on the receiver input. NF does not - * become set in the case of an overrun or while the LIN break detect feature is - * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has - * been received with noise since the last time it was cleared. There is no - * guarantee that the first dataword read from the receive buffer has noise or that there - * is only one dataword in the buffer that was received with noise unless the - * receive buffer has a depth of one. To clear NF, read S1 and then read D. - * - * Values: - * - 0 - No noise detected since the last time this flag was cleared. If the - * receive buffer has a depth greater than 1 then there may be data in the - * receiver buffer that was received with noise. - * - 1 - At least one dataword was received with noise detected since the last - * time the flag was cleared. - */ -/*@{*/ -#define BP_UART_S1_NF (2U) /*!< Bit position for UART_S1_NF. */ -#define BM_UART_S1_NF (0x04U) /*!< Bit mask for UART_S1_NF. */ -#define BS_UART_S1_NF (1U) /*!< Bit field size in bits for UART_S1_NF. */ - -/*! @brief Read current value of the UART_S1_NF field. */ -#define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF)) -/*@}*/ - -/*! - * @name Register UART_S1, field OR[3] (RO) - * - * OR is set when software fails to prevent the receive data register from - * overflowing with data. The OR bit is set immediately after the stop bit has been - * completely received for the dataword that overflows the buffer and all the other - * error flags (FE, NF, and PF) are prevented from setting. The data in the - * shift register is lost, but the data already in the UART data registers is not - * affected. If the OR flag is set, no data is stored in the data buffer even if - * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE - * flags are blocked from asserting, that is, transition from an inactive to an - * active state. To clear OR, read S1 when OR is set and then read D. See - * functional description for more details regarding the operation of the OR bit.If - * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF] - * is not cleared before the next data character is received. In 7816 mode, it is - * possible to configure a NACK to be returned by programing C7816[ONACK]. - * - * Values: - * - 0 - No overrun has occurred since the last time the flag was cleared. - * - 1 - Overrun has occurred or the overrun flag has not been cleared since the - * last overrun occured. - */ -/*@{*/ -#define BP_UART_S1_OR (3U) /*!< Bit position for UART_S1_OR. */ -#define BM_UART_S1_OR (0x08U) /*!< Bit mask for UART_S1_OR. */ -#define BS_UART_S1_OR (1U) /*!< Bit field size in bits for UART_S1_OR. */ - -/*! @brief Read current value of the UART_S1_OR field. */ -#define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR)) -/*@}*/ - -/*! - * @name Register UART_S1, field IDLE[4] (RO) - * - * After the IDLE flag is cleared, a frame must be received (although not - * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN - * break character must set the S2[LBKDIF] flag before an idle condition can set the - * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D. - * IDLE is set when either of the following appear on the receiver input: 10 - * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10] - * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle - * detection is not supported when 7816E is set/enabled and hence this flag is - * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE - * flag if RWUID is set, else the IDLE flag does not become set. - * - * Values: - * - 0 - Receiver input is either active now or has never become active since - * the IDLE flag was last cleared. - * - 1 - Receiver input has become idle or the flag has not been cleared since - * it last asserted. - */ -/*@{*/ -#define BP_UART_S1_IDLE (4U) /*!< Bit position for UART_S1_IDLE. */ -#define BM_UART_S1_IDLE (0x10U) /*!< Bit mask for UART_S1_IDLE. */ -#define BS_UART_S1_IDLE (1U) /*!< Bit field size in bits for UART_S1_IDLE. */ - -/*! @brief Read current value of the UART_S1_IDLE field. */ -#define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE)) -/*@}*/ - -/*! - * @name Register UART_S1, field RDRF[5] (RO) - * - * RDRF is set when the number of datawords in the receive buffer is equal to or - * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the - * process of being received is not included in the count. To clear RDRF, read S1 - * when RDRF is set and then read D. For more efficient interrupt and DMA - * operation, read all data except the final value from the buffer, using D/C3[T8]/ED. - * Then read S1 and the final data value, resulting in the clearing of the RDRF - * flag. Even if RDRF is set, data will continue to be received until an overrun - * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set. - * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive - * buffer but over-write each other. - * - * Values: - * - 0 - The number of datawords in the receive buffer is less than the number - * indicated by RXWATER. - * - 1 - The number of datawords in the receive buffer is equal to or greater - * than the number indicated by RXWATER at some point in time since this flag - * was last cleared. - */ -/*@{*/ -#define BP_UART_S1_RDRF (5U) /*!< Bit position for UART_S1_RDRF. */ -#define BM_UART_S1_RDRF (0x20U) /*!< Bit mask for UART_S1_RDRF. */ -#define BS_UART_S1_RDRF (1U) /*!< Bit field size in bits for UART_S1_RDRF. */ - -/*! @brief Read current value of the UART_S1_RDRF field. */ -#define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF)) -/*@}*/ - -/*! - * @name Register UART_S1, field TC[6] (RO) - * - * TC is set when the transmit buffer is empty and no data, preamble, or break - * character is being transmitted. When TC is set, the transmit data output signal - * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then - * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is - * set after any NACK signal has been received, but prior to any corresponding - * guard times expiring. Writing to D to transmit new data. Queuing a preamble by - * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK - * in C2. - * - * Values: - * - 0 - Transmitter active (sending data, a preamble, or a break). - * - 1 - Transmitter idle (transmission activity complete). - */ -/*@{*/ -#define BP_UART_S1_TC (6U) /*!< Bit position for UART_S1_TC. */ -#define BM_UART_S1_TC (0x40U) /*!< Bit mask for UART_S1_TC. */ -#define BS_UART_S1_TC (1U) /*!< Bit field size in bits for UART_S1_TC. */ - -/*! @brief Read current value of the UART_S1_TC field. */ -#define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC)) -/*@}*/ - -/*! - * @name Register UART_S1, field TDRE[7] (RO) - * - * TDRE will set when the number of datawords in the transmit buffer (D and - * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A - * character that is in the process of being transmitted is not included in the count. - * To clear TDRE, read S1 when TDRE is set and then write to the UART data - * register (D). For more efficient interrupt servicing, all data except the final value - * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read - * before writing the final data value, resulting in the clearing of the TRDE - * flag. This is more efficient because the TDRE reasserts until the watermark has - * been exceeded. So, attempting to clear the TDRE with every write will be - * ineffective until sufficient data has been written. - * - * Values: - * - 0 - The amount of data in the transmit buffer is greater than the value - * indicated by TWFIFO[TXWATER]. - * - 1 - The amount of data in the transmit buffer is less than or equal to the - * value indicated by TWFIFO[TXWATER] at some point in time since the flag - * has been cleared. - */ -/*@{*/ -#define BP_UART_S1_TDRE (7U) /*!< Bit position for UART_S1_TDRE. */ -#define BM_UART_S1_TDRE (0x80U) /*!< Bit mask for UART_S1_TDRE. */ -#define BS_UART_S1_TDRE (1U) /*!< Bit field size in bits for UART_S1_TDRE. */ - -/*! @brief Read current value of the UART_S1_TDRE field. */ -#define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE)) -/*@}*/ - -/******************************************************************************* - * HW_UART_S2 - UART Status Register 2 - ******************************************************************************/ - -/*! - * @brief HW_UART_S2 - UART Status Register 2 (RW) - * - * Reset value: 0x00U - * - * The S2 register provides inputs to the MCU for generation of UART interrupts - * or DMA requests. Also, this register can be polled by the MCU to check the - * status of these bits. This register can be read or written at any time, with the - * exception of the MSBF and RXINV bits, which should be changed by the user only - * between transmit and receive packets. - */ -typedef union _hw_uart_s2 -{ - uint8_t U; - struct _hw_uart_s2_bitfields - { - uint8_t RAF : 1; /*!< [0] Receiver Active Flag */ - uint8_t LBKDE : 1; /*!< [1] LIN Break Detection Enable */ - uint8_t BRK13 : 1; /*!< [2] Break Transmit Character Length */ - uint8_t RWUID : 1; /*!< [3] Receive Wakeup Idle Detect */ - uint8_t RXINV : 1; /*!< [4] Receive Data Inversion */ - uint8_t MSBF : 1; /*!< [5] Most Significant Bit First */ - uint8_t RXEDGIF : 1; /*!< [6] RxD Pin Active Edge Interrupt Flag */ - uint8_t LBKDIF : 1; /*!< [7] LIN Break Detect Interrupt Flag */ - } B; -} hw_uart_s2_t; - -/*! - * @name Constants and macros for entire UART_S2 register - */ -/*@{*/ -#define HW_UART_S2_ADDR(x) ((x) + 0x5U) - -#define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x)) -#define HW_UART_S2_RD(x) (HW_UART_S2(x).U) -#define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v)) -#define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v))) -#define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v))) -#define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_S2 bitfields - */ - -/*! - * @name Register UART_S2, field RAF[0] (RO) - * - * RAF is set when the UART receiver detects a logic 0 during the RT1 time - * period of the start bit search. RAF is cleared when the receiver detects an idle - * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is - * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] = - * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible - * to configure the guard time to 12. However, if a NACK is required to be - * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a - * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU - * prior to actually being inactive. - * - * Values: - * - 0 - UART receiver idle/inactive waiting for a start bit. - * - 1 - UART receiver active, RxD input not idle. - */ -/*@{*/ -#define BP_UART_S2_RAF (0U) /*!< Bit position for UART_S2_RAF. */ -#define BM_UART_S2_RAF (0x01U) /*!< Bit mask for UART_S2_RAF. */ -#define BS_UART_S2_RAF (1U) /*!< Bit field size in bits for UART_S2_RAF. */ - -/*! @brief Read current value of the UART_S2_RAF field. */ -#define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF)) -/*@}*/ - -/*! - * @name Register UART_S2, field LBKDE[1] (RW) - * - * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF], - * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see . - * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set. - * - * Values: - * - 0 - Break character detection is disabled. - * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or - * 12 bits time if C1[M] = 1. - */ -/*@{*/ -#define BP_UART_S2_LBKDE (1U) /*!< Bit position for UART_S2_LBKDE. */ -#define BM_UART_S2_LBKDE (0x02U) /*!< Bit mask for UART_S2_LBKDE. */ -#define BS_UART_S2_LBKDE (1U) /*!< Bit field size in bits for UART_S2_LBKDE. */ - -/*! @brief Read current value of the UART_S2_LBKDE field. */ -#define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE)) - -/*! @brief Format value for bitfield UART_S2_LBKDE. */ -#define BF_UART_S2_LBKDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE) - -/*! @brief Set the LBKDE field to a new value. */ -#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field BRK13[2] (RW) - * - * Determines whether the transmit break character is 10, 11, or 12 bits long, - * or 13 or 14 bits long. See for the length of the break character for the - * different configurations. The detection of a framing error is not affected by this - * field. Transmitting break characters - * - * Values: - * - 0 - Break character is 10, 11, or 12 bits long. - * - 1 - Break character is 13 or 14 bits long. - */ -/*@{*/ -#define BP_UART_S2_BRK13 (2U) /*!< Bit position for UART_S2_BRK13. */ -#define BM_UART_S2_BRK13 (0x04U) /*!< Bit mask for UART_S2_BRK13. */ -#define BS_UART_S2_BRK13 (1U) /*!< Bit field size in bits for UART_S2_BRK13. */ - -/*! @brief Read current value of the UART_S2_BRK13 field. */ -#define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13)) - -/*! @brief Format value for bitfield UART_S2_BRK13. */ -#define BF_UART_S2_BRK13(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13) - -/*! @brief Set the BRK13 field to a new value. */ -#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field RWUID[3] (RW) - * - * When RWU is set and WAKE is cleared, this field controls whether the idle - * character that wakes the receiver sets S1[IDLE]. This field must be cleared when - * C7816[ISO7816E] is set/enabled. - * - * Values: - * - 0 - S1[IDLE] is not set upon detection of an idle character. - * - 1 - S1[IDLE] is set upon detection of an idle character. - */ -/*@{*/ -#define BP_UART_S2_RWUID (3U) /*!< Bit position for UART_S2_RWUID. */ -#define BM_UART_S2_RWUID (0x08U) /*!< Bit mask for UART_S2_RWUID. */ -#define BS_UART_S2_RWUID (1U) /*!< Bit field size in bits for UART_S2_RWUID. */ - -/*! @brief Read current value of the UART_S2_RWUID field. */ -#define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID)) - -/*! @brief Format value for bitfield UART_S2_RWUID. */ -#define BF_UART_S2_RWUID(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID) - -/*! @brief Set the RWUID field to a new value. */ -#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field RXINV[4] (RW) - * - * Setting this field reverses the polarity of the received data input. In NRZ - * format, a one is represented by a mark and a zero is represented by a space for - * normal polarity, and the opposite for inverted polarity. In IrDA format, a - * zero is represented by short high pulse in the middle of a bit time remaining - * idle low for a one for normal polarity. A zero is represented by a short low - * pulse in the middle of a bit time remaining idle high for a one for inverted - * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are - * enabled and an initial character is detected in T = 0 protocol mode. Setting - * RXINV inverts the RxD input for data bits, start and stop bits, break, and - * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit - * are inverted. - * - * Values: - * - 0 - Receive data is not inverted. - * - 1 - Receive data is inverted. - */ -/*@{*/ -#define BP_UART_S2_RXINV (4U) /*!< Bit position for UART_S2_RXINV. */ -#define BM_UART_S2_RXINV (0x10U) /*!< Bit mask for UART_S2_RXINV. */ -#define BS_UART_S2_RXINV (1U) /*!< Bit field size in bits for UART_S2_RXINV. */ - -/*! @brief Read current value of the UART_S2_RXINV field. */ -#define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV)) - -/*! @brief Format value for bitfield UART_S2_RXINV. */ -#define BF_UART_S2_RXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV) - -/*! @brief Set the RXINV field to a new value. */ -#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field MSBF[5] (RW) - * - * Setting this field reverses the order of the bits that are transmitted and - * received on the wire. This field does not affect the polarity of the bits, the - * location of the parity bit, or the location of the start or stop bits. This - * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and - * an initial character is detected in T = 0 protocol mode. - * - * Values: - * - 0 - LSB (bit0) is the first bit that is transmitted following the start - * bit. Further, the first bit received after the start bit is identified as - * bit0. - * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following - * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the - * first bit received after the start bit is identified as bit8, bit7, or - * bit6, depending on the setting of C1[M] and C1[PE]. - */ -/*@{*/ -#define BP_UART_S2_MSBF (5U) /*!< Bit position for UART_S2_MSBF. */ -#define BM_UART_S2_MSBF (0x20U) /*!< Bit mask for UART_S2_MSBF. */ -#define BS_UART_S2_MSBF (1U) /*!< Bit field size in bits for UART_S2_MSBF. */ - -/*! @brief Read current value of the UART_S2_MSBF field. */ -#define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF)) - -/*! @brief Format value for bitfield UART_S2_MSBF. */ -#define BF_UART_S2_MSBF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF) - -/*! @brief Set the MSBF field to a new value. */ -#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field RXEDGIF[6] (W1C) - * - * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is - * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1 - * to it. See for additional details. RXEDGIF description The active edge is - * detected only in two wire mode and on receiving data coming from the RxD pin. - * - * Values: - * - 0 - No active edge on the receive pin has occurred. - * - 1 - An active edge on the receive pin has occurred. - */ -/*@{*/ -#define BP_UART_S2_RXEDGIF (6U) /*!< Bit position for UART_S2_RXEDGIF. */ -#define BM_UART_S2_RXEDGIF (0x40U) /*!< Bit mask for UART_S2_RXEDGIF. */ -#define BS_UART_S2_RXEDGIF (1U) /*!< Bit field size in bits for UART_S2_RXEDGIF. */ - -/*! @brief Read current value of the UART_S2_RXEDGIF field. */ -#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF)) - -/*! @brief Format value for bitfield UART_S2_RXEDGIF. */ -#define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF) - -/*! @brief Set the RXEDGIF field to a new value. */ -#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field LBKDIF[7] (W1C) - * - * LBKDIF is set when LBKDE is set and a LIN break character is detected on the - * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M] - * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the - * last LIN break character. LBKDIF is cleared by writing a 1 to it. - * - * Values: - * - 0 - No LIN break character detected. - * - 1 - LIN break character detected. - */ -/*@{*/ -#define BP_UART_S2_LBKDIF (7U) /*!< Bit position for UART_S2_LBKDIF. */ -#define BM_UART_S2_LBKDIF (0x80U) /*!< Bit mask for UART_S2_LBKDIF. */ -#define BS_UART_S2_LBKDIF (1U) /*!< Bit field size in bits for UART_S2_LBKDIF. */ - -/*! @brief Read current value of the UART_S2_LBKDIF field. */ -#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF)) - -/*! @brief Format value for bitfield UART_S2_LBKDIF. */ -#define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF) - -/*! @brief Set the LBKDIF field to a new value. */ -#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C3 - UART Control Register 3 - ******************************************************************************/ - -/*! - * @brief HW_UART_C3 - UART Control Register 3 (RW) - * - * Reset value: 0x00U - * - * Writing R8 does not have any effect. TXDIR and TXINV can be changed only - * between transmit and receive packets. - */ -typedef union _hw_uart_c3 -{ - uint8_t U; - struct _hw_uart_c3_bitfields - { - uint8_t PEIE : 1; /*!< [0] Parity Error Interrupt Enable */ - uint8_t FEIE : 1; /*!< [1] Framing Error Interrupt Enable */ - uint8_t NEIE : 1; /*!< [2] Noise Error Interrupt Enable */ - uint8_t ORIE : 1; /*!< [3] Overrun Error Interrupt Enable */ - uint8_t TXINV : 1; /*!< [4] Transmit Data Inversion. */ - uint8_t TXDIR : 1; /*!< [5] Transmitter Pin Data Direction in - * Single-Wire mode */ - uint8_t T8 : 1; /*!< [6] Transmit Bit 8 */ - uint8_t R8 : 1; /*!< [7] Received Bit 8 */ - } B; -} hw_uart_c3_t; - -/*! - * @name Constants and macros for entire UART_C3 register - */ -/*@{*/ -#define HW_UART_C3_ADDR(x) ((x) + 0x6U) - -#define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x)) -#define HW_UART_C3_RD(x) (HW_UART_C3(x).U) -#define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v)) -#define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v))) -#define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v))) -#define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C3 bitfields - */ - -/*! - * @name Register UART_C3, field PEIE[0] (RW) - * - * Enables the parity error flag, S1[PF], to generate interrupt requests. - * - * Values: - * - 0 - PF interrupt requests are disabled. - * - 1 - PF interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_PEIE (0U) /*!< Bit position for UART_C3_PEIE. */ -#define BM_UART_C3_PEIE (0x01U) /*!< Bit mask for UART_C3_PEIE. */ -#define BS_UART_C3_PEIE (1U) /*!< Bit field size in bits for UART_C3_PEIE. */ - -/*! @brief Read current value of the UART_C3_PEIE field. */ -#define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE)) - -/*! @brief Format value for bitfield UART_C3_PEIE. */ -#define BF_UART_C3_PEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE) - -/*! @brief Set the PEIE field to a new value. */ -#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field FEIE[1] (RW) - * - * Enables the framing error flag, S1[FE], to generate interrupt requests. - * - * Values: - * - 0 - FE interrupt requests are disabled. - * - 1 - FE interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_FEIE (1U) /*!< Bit position for UART_C3_FEIE. */ -#define BM_UART_C3_FEIE (0x02U) /*!< Bit mask for UART_C3_FEIE. */ -#define BS_UART_C3_FEIE (1U) /*!< Bit field size in bits for UART_C3_FEIE. */ - -/*! @brief Read current value of the UART_C3_FEIE field. */ -#define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE)) - -/*! @brief Format value for bitfield UART_C3_FEIE. */ -#define BF_UART_C3_FEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field NEIE[2] (RW) - * - * Enables the noise flag, S1[NF], to generate interrupt requests. - * - * Values: - * - 0 - NF interrupt requests are disabled. - * - 1 - NF interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_NEIE (2U) /*!< Bit position for UART_C3_NEIE. */ -#define BM_UART_C3_NEIE (0x04U) /*!< Bit mask for UART_C3_NEIE. */ -#define BS_UART_C3_NEIE (1U) /*!< Bit field size in bits for UART_C3_NEIE. */ - -/*! @brief Read current value of the UART_C3_NEIE field. */ -#define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE)) - -/*! @brief Format value for bitfield UART_C3_NEIE. */ -#define BF_UART_C3_NEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE) - -/*! @brief Set the NEIE field to a new value. */ -#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field ORIE[3] (RW) - * - * Enables the overrun error flag, S1[OR], to generate interrupt requests. - * - * Values: - * - 0 - OR interrupts are disabled. - * - 1 - OR interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_ORIE (3U) /*!< Bit position for UART_C3_ORIE. */ -#define BM_UART_C3_ORIE (0x08U) /*!< Bit mask for UART_C3_ORIE. */ -#define BS_UART_C3_ORIE (1U) /*!< Bit field size in bits for UART_C3_ORIE. */ - -/*! @brief Read current value of the UART_C3_ORIE field. */ -#define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE)) - -/*! @brief Format value for bitfield UART_C3_ORIE. */ -#define BF_UART_C3_ORIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE) - -/*! @brief Set the ORIE field to a new value. */ -#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field TXINV[4] (RW) - * - * Setting this field reverses the polarity of the transmitted data output. In - * NRZ format, a one is represented by a mark and a zero is represented by a space - * for normal polarity, and the opposite for inverted polarity. In IrDA format, - * a zero is represented by short high pulse in the middle of a bit time - * remaining idle low for a one for normal polarity, and a zero is represented by short - * low pulse in the middle of a bit time remaining idle high for a one for - * inverted polarity. This field is automatically set when C7816[INIT] and - * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode. - * Setting TXINV inverts all transmitted values, including idle, break, start, and - * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit - * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only - * the transmitted data bits and parity bit are inverted. - * - * Values: - * - 0 - Transmit data is not inverted. - * - 1 - Transmit data is inverted. - */ -/*@{*/ -#define BP_UART_C3_TXINV (4U) /*!< Bit position for UART_C3_TXINV. */ -#define BM_UART_C3_TXINV (0x10U) /*!< Bit mask for UART_C3_TXINV. */ -#define BS_UART_C3_TXINV (1U) /*!< Bit field size in bits for UART_C3_TXINV. */ - -/*! @brief Read current value of the UART_C3_TXINV field. */ -#define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV)) - -/*! @brief Format value for bitfield UART_C3_TXINV. */ -#define BF_UART_C3_TXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV) - -/*! @brief Set the TXINV field to a new value. */ -#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field TXDIR[5] (RW) - * - * Determines whether the TXD pin is used as an input or output in the - * single-wire mode of operation. This field is relevant only to the single wire mode. - * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is - * automatically cleared after the requested block is transmitted. This condition is - * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted. - * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is - * being transmitted, the hardware automatically overrides this field as needed. In - * this situation, TXDIR does not reflect the temporary state associated with - * the NACK. - * - * Values: - * - 0 - TXD pin is an input in single wire mode. - * - 1 - TXD pin is an output in single wire mode. - */ -/*@{*/ -#define BP_UART_C3_TXDIR (5U) /*!< Bit position for UART_C3_TXDIR. */ -#define BM_UART_C3_TXDIR (0x20U) /*!< Bit mask for UART_C3_TXDIR. */ -#define BS_UART_C3_TXDIR (1U) /*!< Bit field size in bits for UART_C3_TXDIR. */ - -/*! @brief Read current value of the UART_C3_TXDIR field. */ -#define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR)) - -/*! @brief Format value for bitfield UART_C3_TXDIR. */ -#define BF_UART_C3_TXDIR(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR) - -/*! @brief Set the TXDIR field to a new value. */ -#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field T8[6] (RW) - * - * T8 is the ninth data bit transmitted when the UART is configured for 9-bit - * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the - * same as in the previous transmission, T8 does not have to be rewritten. The same - * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit, - * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with - * the remaining data. - */ -/*@{*/ -#define BP_UART_C3_T8 (6U) /*!< Bit position for UART_C3_T8. */ -#define BM_UART_C3_T8 (0x40U) /*!< Bit mask for UART_C3_T8. */ -#define BS_UART_C3_T8 (1U) /*!< Bit field size in bits for UART_C3_T8. */ - -/*! @brief Read current value of the UART_C3_T8 field. */ -#define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8)) - -/*! @brief Format value for bitfield UART_C3_T8. */ -#define BF_UART_C3_T8(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8) - -/*! @brief Set the T8 field to a new value. */ -#define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field R8[7] (RO) - * - * R8 is the ninth data bit received when the UART is configured for 9-bit data - * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the - * current data value in the UARTx_D register. To read the 9th bit, read the - * value of UARTx_C3[R8], then read the UARTx_D register. - */ -/*@{*/ -#define BP_UART_C3_R8 (7U) /*!< Bit position for UART_C3_R8. */ -#define BM_UART_C3_R8 (0x80U) /*!< Bit mask for UART_C3_R8. */ -#define BS_UART_C3_R8 (1U) /*!< Bit field size in bits for UART_C3_R8. */ - -/*! @brief Read current value of the UART_C3_R8 field. */ -#define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8)) -/*@}*/ - -/******************************************************************************* - * HW_UART_D - UART Data Register - ******************************************************************************/ - -/*! - * @brief HW_UART_D - UART Data Register (RW) - * - * Reset value: 0x00U - * - * This register is actually two separate registers. Reads return the contents - * of the read-only receive data register and writes go to the write-only transmit - * data register. In 8-bit or 9-bit data format, only UART data register (D) - * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is - * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D - * register, only if the ninth bit of data needs to be captured. Similarly, the - * ED register needs to be read, prior to the D register, only if the additional - * flag data for the dataword needs to be captured. In the normal 8-bit mode (M - * bit cleared) if the parity is enabled, you get seven data bits and one parity - * bit. That one parity bit is loaded into the D register. So, for the data bits, - * mask off the parity bit from the value you read out of this register. When - * transmitting in 9-bit data format and using 8-bit write instructions, write first - * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to - * C3[T8] stores the data in a temporary register. If D register is written first, - * and then the new data on data bus is stored in D, the temporary value written by - * the last write to C3[T8] gets stored in the C3[T8] register. - */ -typedef union _hw_uart_d -{ - uint8_t U; - struct _hw_uart_d_bitfields - { - uint8_t RT : 8; /*!< [7:0] */ - } B; -} hw_uart_d_t; - -/*! - * @name Constants and macros for entire UART_D register - */ -/*@{*/ -#define HW_UART_D_ADDR(x) ((x) + 0x7U) - -#define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x)) -#define HW_UART_D_RD(x) (HW_UART_D(x).U) -#define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v)) -#define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v))) -#define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v))) -#define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_D bitfields - */ - -/*! - * @name Register UART_D, field RT[7:0] (RW) - * - * Reads return the contents of the read-only receive data register and writes - * go to the write-only transmit data register. - */ -/*@{*/ -#define BP_UART_D_RT (0U) /*!< Bit position for UART_D_RT. */ -#define BM_UART_D_RT (0xFFU) /*!< Bit mask for UART_D_RT. */ -#define BS_UART_D_RT (8U) /*!< Bit field size in bits for UART_D_RT. */ - -/*! @brief Read current value of the UART_D_RT field. */ -#define BR_UART_D_RT(x) (HW_UART_D(x).U) - -/*! @brief Format value for bitfield UART_D_RT. */ -#define BF_UART_D_RT(v) ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT) - -/*! @brief Set the RT field to a new value. */ -#define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_MA1 - UART Match Address Registers 1 - ******************************************************************************/ - -/*! - * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW) - * - * Reset value: 0x00U - * - * The MA1 and MA2 registers are compared to input data addresses when the most - * significant bit is set and the associated C4[MAEN] field is set. If a match - * occurs, the following data is transferred to the data register. If a match - * fails, the following data is discarded. These registers can be read and written at - * anytime. - */ -typedef union _hw_uart_ma1 -{ - uint8_t U; - struct _hw_uart_ma1_bitfields - { - uint8_t MA : 8; /*!< [7:0] Match Address */ - } B; -} hw_uart_ma1_t; - -/*! - * @name Constants and macros for entire UART_MA1 register - */ -/*@{*/ -#define HW_UART_MA1_ADDR(x) ((x) + 0x8U) - -#define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x)) -#define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U) -#define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v)) -#define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v))) -#define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v))) -#define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_MA1 bitfields - */ - -/*! - * @name Register UART_MA1, field MA[7:0] (RW) - */ -/*@{*/ -#define BP_UART_MA1_MA (0U) /*!< Bit position for UART_MA1_MA. */ -#define BM_UART_MA1_MA (0xFFU) /*!< Bit mask for UART_MA1_MA. */ -#define BS_UART_MA1_MA (8U) /*!< Bit field size in bits for UART_MA1_MA. */ - -/*! @brief Read current value of the UART_MA1_MA field. */ -#define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U) - -/*! @brief Format value for bitfield UART_MA1_MA. */ -#define BF_UART_MA1_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA) - -/*! @brief Set the MA field to a new value. */ -#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_MA2 - UART Match Address Registers 2 - ******************************************************************************/ - -/*! - * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW) - * - * Reset value: 0x00U - * - * These registers can be read and written at anytime. The MA1 and MA2 registers - * are compared to input data addresses when the most significant bit is set and - * the associated C4[MAEN] field is set. If a match occurs, the following data - * is transferred to the data register. If a match fails, the following data is - * discarded. - */ -typedef union _hw_uart_ma2 -{ - uint8_t U; - struct _hw_uart_ma2_bitfields - { - uint8_t MA : 8; /*!< [7:0] Match Address */ - } B; -} hw_uart_ma2_t; - -/*! - * @name Constants and macros for entire UART_MA2 register - */ -/*@{*/ -#define HW_UART_MA2_ADDR(x) ((x) + 0x9U) - -#define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x)) -#define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U) -#define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v)) -#define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v))) -#define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v))) -#define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_MA2 bitfields - */ - -/*! - * @name Register UART_MA2, field MA[7:0] (RW) - */ -/*@{*/ -#define BP_UART_MA2_MA (0U) /*!< Bit position for UART_MA2_MA. */ -#define BM_UART_MA2_MA (0xFFU) /*!< Bit mask for UART_MA2_MA. */ -#define BS_UART_MA2_MA (8U) /*!< Bit field size in bits for UART_MA2_MA. */ - -/*! @brief Read current value of the UART_MA2_MA field. */ -#define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U) - -/*! @brief Format value for bitfield UART_MA2_MA. */ -#define BF_UART_MA2_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA) - -/*! @brief Set the MA field to a new value. */ -#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C4 - UART Control Register 4 - ******************************************************************************/ - -/*! - * @brief HW_UART_C4 - UART Control Register 4 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_uart_c4 -{ - uint8_t U; - struct _hw_uart_c4_bitfields - { - uint8_t BRFA : 5; /*!< [4:0] Baud Rate Fine Adjust */ - uint8_t M10 : 1; /*!< [5] 10-bit Mode select */ - uint8_t MAEN2 : 1; /*!< [6] Match Address Mode Enable 2 */ - uint8_t MAEN1 : 1; /*!< [7] Match Address Mode Enable 1 */ - } B; -} hw_uart_c4_t; - -/*! - * @name Constants and macros for entire UART_C4 register - */ -/*@{*/ -#define HW_UART_C4_ADDR(x) ((x) + 0xAU) - -#define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x)) -#define HW_UART_C4_RD(x) (HW_UART_C4(x).U) -#define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v)) -#define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v))) -#define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v))) -#define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C4 bitfields - */ - -/*! - * @name Register UART_C4, field BRFA[4:0] (RW) - * - * This bit field is used to add more timing resolution to the average baud - * frequency, in increments of 1/32. See Baud rate generation for more information. - */ -/*@{*/ -#define BP_UART_C4_BRFA (0U) /*!< Bit position for UART_C4_BRFA. */ -#define BM_UART_C4_BRFA (0x1FU) /*!< Bit mask for UART_C4_BRFA. */ -#define BS_UART_C4_BRFA (5U) /*!< Bit field size in bits for UART_C4_BRFA. */ - -/*! @brief Read current value of the UART_C4_BRFA field. */ -#define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA) - -/*! @brief Format value for bitfield UART_C4_BRFA. */ -#define BF_UART_C4_BRFA(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA) - -/*! @brief Set the BRFA field to a new value. */ -#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v))) -/*@}*/ - -/*! - * @name Register UART_C4, field M10[5] (RW) - * - * Causes a tenth, non-memory mapped bit to be part of the serial transmission. - * This tenth bit is generated and interpreted as a parity bit. The M10 field - * does not affect the LIN send or detect break behavior. If M10 is set, then both - * C1[M] and C1[PE] must also be set. This field must be cleared when - * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information. - * - * Values: - * - 0 - The parity bit is the ninth bit in the serial transmission. - * - 1 - The parity bit is the tenth bit in the serial transmission. - */ -/*@{*/ -#define BP_UART_C4_M10 (5U) /*!< Bit position for UART_C4_M10. */ -#define BM_UART_C4_M10 (0x20U) /*!< Bit mask for UART_C4_M10. */ -#define BS_UART_C4_M10 (1U) /*!< Bit field size in bits for UART_C4_M10. */ - -/*! @brief Read current value of the UART_C4_M10 field. */ -#define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10)) - -/*! @brief Format value for bitfield UART_C4_M10. */ -#define BF_UART_C4_M10(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10) - -/*! @brief Set the M10 field to a new value. */ -#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v)) -/*@}*/ - -/*! - * @name Register UART_C4, field MAEN2[6] (RW) - * - * See Match address operation for more information. - * - * Values: - * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared. - * - 1 - All data received with the most significant bit cleared, is discarded. - * All data received with the most significant bit set, is compared with - * contents of MA2 register. If no match occurs, the data is discarded. If a - * match occurs, data is transferred to the data buffer. This field must be - * cleared when C7816[ISO7816E] is set/enabled. - */ -/*@{*/ -#define BP_UART_C4_MAEN2 (6U) /*!< Bit position for UART_C4_MAEN2. */ -#define BM_UART_C4_MAEN2 (0x40U) /*!< Bit mask for UART_C4_MAEN2. */ -#define BS_UART_C4_MAEN2 (1U) /*!< Bit field size in bits for UART_C4_MAEN2. */ - -/*! @brief Read current value of the UART_C4_MAEN2 field. */ -#define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2)) - -/*! @brief Format value for bitfield UART_C4_MAEN2. */ -#define BF_UART_C4_MAEN2(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2) - -/*! @brief Set the MAEN2 field to a new value. */ -#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v)) -/*@}*/ - -/*! - * @name Register UART_C4, field MAEN1[7] (RW) - * - * See Match address operation for more information. - * - * Values: - * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared. - * - 1 - All data received with the most significant bit cleared, is discarded. - * All data received with the most significant bit set, is compared with - * contents of MA1 register. If no match occurs, the data is discarded. If match - * occurs, data is transferred to the data buffer. This field must be cleared - * when C7816[ISO7816E] is set/enabled. - */ -/*@{*/ -#define BP_UART_C4_MAEN1 (7U) /*!< Bit position for UART_C4_MAEN1. */ -#define BM_UART_C4_MAEN1 (0x80U) /*!< Bit mask for UART_C4_MAEN1. */ -#define BS_UART_C4_MAEN1 (1U) /*!< Bit field size in bits for UART_C4_MAEN1. */ - -/*! @brief Read current value of the UART_C4_MAEN1 field. */ -#define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1)) - -/*! @brief Format value for bitfield UART_C4_MAEN1. */ -#define BF_UART_C4_MAEN1(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1) - -/*! @brief Set the MAEN1 field to a new value. */ -#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C5 - UART Control Register 5 - ******************************************************************************/ - -/*! - * @brief HW_UART_C5 - UART Control Register 5 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_uart_c5 -{ - uint8_t U; - struct _hw_uart_c5_bitfields - { - uint8_t RESERVED0 : 5; /*!< [4:0] */ - uint8_t RDMAS : 1; /*!< [5] Receiver Full DMA Select */ - uint8_t RESERVED1 : 1; /*!< [6] */ - uint8_t TDMAS : 1; /*!< [7] Transmitter DMA Select */ - } B; -} hw_uart_c5_t; - -/*! - * @name Constants and macros for entire UART_C5 register - */ -/*@{*/ -#define HW_UART_C5_ADDR(x) ((x) + 0xBU) - -#define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x)) -#define HW_UART_C5_RD(x) (HW_UART_C5(x).U) -#define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v)) -#define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v))) -#define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v))) -#define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C5 bitfields - */ - -/*! - * @name Register UART_C5, field RDMAS[5] (RW) - * - * Configures the receiver data register full flag, S1[RDRF], to generate - * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is - * set, the RDRF DMA and RDFR interrupt request signals are not asserted, - * regardless of the state of RDMAS. - * - * Values: - * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is - * asserted to request an interrupt service. - * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is - * asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_RDMAS (5U) /*!< Bit position for UART_C5_RDMAS. */ -#define BM_UART_C5_RDMAS (0x20U) /*!< Bit mask for UART_C5_RDMAS. */ -#define BS_UART_C5_RDMAS (1U) /*!< Bit field size in bits for UART_C5_RDMAS. */ - -/*! @brief Read current value of the UART_C5_RDMAS field. */ -#define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS)) - -/*! @brief Format value for bitfield UART_C5_RDMAS. */ -#define BF_UART_C5_RDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS) - -/*! @brief Set the RDMAS field to a new value. */ -#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v)) -/*@}*/ - -/*! - * @name Register UART_C5, field TDMAS[7] (RW) - * - * Configures the transmit data register empty flag, S1[TDRE], to generate - * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and - * TDRE interrupt request signals are not asserted when the TDRE flag is set, - * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE] - * must be cleared, and D must not be written unless a DMA request is being - * serviced. - * - * Values: - * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt - * request signal is asserted to request interrupt service. - * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request - * signal is asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_TDMAS (7U) /*!< Bit position for UART_C5_TDMAS. */ -#define BM_UART_C5_TDMAS (0x80U) /*!< Bit mask for UART_C5_TDMAS. */ -#define BS_UART_C5_TDMAS (1U) /*!< Bit field size in bits for UART_C5_TDMAS. */ - -/*! @brief Read current value of the UART_C5_TDMAS field. */ -#define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS)) - -/*! @brief Format value for bitfield UART_C5_TDMAS. */ -#define BF_UART_C5_TDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS) - -/*! @brief Set the TDMAS field to a new value. */ -#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_ED - UART Extended Data Register - ******************************************************************************/ - -/*! - * @brief HW_UART_ED - UART Extended Data Register (RO) - * - * Reset value: 0x00U - * - * This register contains additional information flags that are stored with a - * received dataword. This register may be read at any time but contains valid data - * only if there is a dataword in the receive FIFO. The data contained in this - * register represents additional information regarding the conditions on which a - * dataword was received. The importance of this data varies with the - * application, and in some cases maybe completely optional. These fields automatically - * update to reflect the conditions of the next dataword whenever D is read. If - * S1[NF] and S1[PF] have not been set since the last time the receive buffer was - * empty, the NOISY and PARITYE fields will be zero. - */ -typedef union _hw_uart_ed -{ - uint8_t U; - struct _hw_uart_ed_bitfields - { - uint8_t RESERVED0 : 6; /*!< [5:0] */ - uint8_t PARITYE : 1; /*!< [6] */ - uint8_t NOISY : 1; /*!< [7] */ - } B; -} hw_uart_ed_t; - -/*! - * @name Constants and macros for entire UART_ED register - */ -/*@{*/ -#define HW_UART_ED_ADDR(x) ((x) + 0xCU) - -#define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x)) -#define HW_UART_ED_RD(x) (HW_UART_ED(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_ED bitfields - */ - -/*! - * @name Register UART_ED, field PARITYE[6] (RO) - * - * The current received dataword contained in D and C3[R8] was received with a - * parity error. - * - * Values: - * - 0 - The dataword was received without a parity error. - * - 1 - The dataword was received with a parity error. - */ -/*@{*/ -#define BP_UART_ED_PARITYE (6U) /*!< Bit position for UART_ED_PARITYE. */ -#define BM_UART_ED_PARITYE (0x40U) /*!< Bit mask for UART_ED_PARITYE. */ -#define BS_UART_ED_PARITYE (1U) /*!< Bit field size in bits for UART_ED_PARITYE. */ - -/*! @brief Read current value of the UART_ED_PARITYE field. */ -#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE)) -/*@}*/ - -/*! - * @name Register UART_ED, field NOISY[7] (RO) - * - * The current received dataword contained in D and C3[R8] was received with - * noise. - * - * Values: - * - 0 - The dataword was received without noise. - * - 1 - The data was received with noise. - */ -/*@{*/ -#define BP_UART_ED_NOISY (7U) /*!< Bit position for UART_ED_NOISY. */ -#define BM_UART_ED_NOISY (0x80U) /*!< Bit mask for UART_ED_NOISY. */ -#define BS_UART_ED_NOISY (1U) /*!< Bit field size in bits for UART_ED_NOISY. */ - -/*! @brief Read current value of the UART_ED_NOISY field. */ -#define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY)) -/*@}*/ - -/******************************************************************************* - * HW_UART_MODEM - UART Modem Register - ******************************************************************************/ - -/*! - * @brief HW_UART_MODEM - UART Modem Register (RW) - * - * Reset value: 0x00U - * - * The MODEM register controls options for setting the modem configuration. - * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is - * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The - * ISO-7816 protocol does not use the RTS and CTS signals. - */ -typedef union _hw_uart_modem -{ - uint8_t U; - struct _hw_uart_modem_bitfields - { - uint8_t TXCTSE : 1; /*!< [0] Transmitter clear-to-send enable */ - uint8_t TXRTSE : 1; /*!< [1] Transmitter request-to-send enable */ - uint8_t TXRTSPOL : 1; /*!< [2] Transmitter request-to-send polarity */ - uint8_t RXRTSE : 1; /*!< [3] Receiver request-to-send enable */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_uart_modem_t; - -/*! - * @name Constants and macros for entire UART_MODEM register - */ -/*@{*/ -#define HW_UART_MODEM_ADDR(x) ((x) + 0xDU) - -#define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x)) -#define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U) -#define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v)) -#define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v))) -#define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v))) -#define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_MODEM bitfields - */ - -/*! - * @name Register UART_MODEM, field TXCTSE[0] (RW) - * - * TXCTSE controls the operation of the transmitter. TXCTSE can be set - * independently from the state of TXRTSE and RXRTSE. - * - * Values: - * - 0 - CTS has no effect on the transmitter. - * - 1 - Enables clear-to-send operation. The transmitter checks the state of - * CTS each time it is ready to send a character. If CTS is asserted, the - * character is sent. If CTS is deasserted, the signal TXD remains in the mark - * state and transmission is delayed until CTS is asserted. Changes in CTS as a - * character is being sent do not affect its transmission. - */ -/*@{*/ -#define BP_UART_MODEM_TXCTSE (0U) /*!< Bit position for UART_MODEM_TXCTSE. */ -#define BM_UART_MODEM_TXCTSE (0x01U) /*!< Bit mask for UART_MODEM_TXCTSE. */ -#define BS_UART_MODEM_TXCTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXCTSE. */ - -/*! @brief Read current value of the UART_MODEM_TXCTSE field. */ -#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE)) - -/*! @brief Format value for bitfield UART_MODEM_TXCTSE. */ -#define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE) - -/*! @brief Set the TXCTSE field to a new value. */ -#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v)) -/*@}*/ - -/*! - * @name Register UART_MODEM, field TXRTSE[1] (RW) - * - * Controls RTS before and after a transmission. - * - * Values: - * - 0 - The transmitter has no effect on RTS. - * - 1 - When a character is placed into an empty transmitter data buffer , RTS - * asserts one bit time before the start bit is transmitted. RTS deasserts - * one bit time after all characters in the transmitter data buffer and shift - * register are completely sent, including the last stop bit. (FIFO) (FIFO) - */ -/*@{*/ -#define BP_UART_MODEM_TXRTSE (1U) /*!< Bit position for UART_MODEM_TXRTSE. */ -#define BM_UART_MODEM_TXRTSE (0x02U) /*!< Bit mask for UART_MODEM_TXRTSE. */ -#define BS_UART_MODEM_TXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSE. */ - -/*! @brief Read current value of the UART_MODEM_TXRTSE field. */ -#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE)) - -/*! @brief Format value for bitfield UART_MODEM_TXRTSE. */ -#define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE) - -/*! @brief Set the TXRTSE field to a new value. */ -#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v)) -/*@}*/ - -/*! - * @name Register UART_MODEM, field TXRTSPOL[2] (RW) - * - * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the - * polarity of the receiver RTS. RTS will remain negated in the active low state - * unless TXRTSE is set. - * - * Values: - * - 0 - Transmitter RTS is active low. - * - 1 - Transmitter RTS is active high. - */ -/*@{*/ -#define BP_UART_MODEM_TXRTSPOL (2U) /*!< Bit position for UART_MODEM_TXRTSPOL. */ -#define BM_UART_MODEM_TXRTSPOL (0x04U) /*!< Bit mask for UART_MODEM_TXRTSPOL. */ -#define BS_UART_MODEM_TXRTSPOL (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSPOL. */ - -/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */ -#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL)) - -/*! @brief Format value for bitfield UART_MODEM_TXRTSPOL. */ -#define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL) - -/*! @brief Set the TXRTSPOL field to a new value. */ -#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v)) -/*@}*/ - -/*! - * @name Register UART_MODEM, field RXRTSE[3] (RW) - * - * Allows the RTS output to control the CTS input of the transmitting device to - * prevent receiver overrun. Do not set both RXRTSE and TXRTSE. - * - * Values: - * - 0 - The receiver has no effect on RTS. - * - 1 - RTS is deasserted if the number of characters in the receiver data - * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted - * when the number of characters in the receiver data register (FIFO) is less - * than RWFIFO[RXWATER]. - */ -/*@{*/ -#define BP_UART_MODEM_RXRTSE (3U) /*!< Bit position for UART_MODEM_RXRTSE. */ -#define BM_UART_MODEM_RXRTSE (0x08U) /*!< Bit mask for UART_MODEM_RXRTSE. */ -#define BS_UART_MODEM_RXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_RXRTSE. */ - -/*! @brief Read current value of the UART_MODEM_RXRTSE field. */ -#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE)) - -/*! @brief Format value for bitfield UART_MODEM_RXRTSE. */ -#define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE) - -/*! @brief Set the RXRTSE field to a new value. */ -#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_IR - UART Infrared Register - ******************************************************************************/ - -/*! - * @brief HW_UART_IR - UART Infrared Register (RW) - * - * Reset value: 0x00U - * - * The IR register controls options for setting the infrared configuration. - */ -typedef union _hw_uart_ir -{ - uint8_t U; - struct _hw_uart_ir_bitfields - { - uint8_t TNP : 2; /*!< [1:0] Transmitter narrow pulse */ - uint8_t IREN : 1; /*!< [2] Infrared enable */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_uart_ir_t; - -/*! - * @name Constants and macros for entire UART_IR register - */ -/*@{*/ -#define HW_UART_IR_ADDR(x) ((x) + 0xEU) - -#define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x)) -#define HW_UART_IR_RD(x) (HW_UART_IR(x).U) -#define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v)) -#define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v))) -#define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v))) -#define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_IR bitfields - */ - -/*! - * @name Register UART_IR, field TNP[1:0] (RW) - * - * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse. - * - * Values: - * - 00 - 3/16. - * - 01 - 1/16. - * - 10 - 1/32. - * - 11 - 1/4. - */ -/*@{*/ -#define BP_UART_IR_TNP (0U) /*!< Bit position for UART_IR_TNP. */ -#define BM_UART_IR_TNP (0x03U) /*!< Bit mask for UART_IR_TNP. */ -#define BS_UART_IR_TNP (2U) /*!< Bit field size in bits for UART_IR_TNP. */ - -/*! @brief Read current value of the UART_IR_TNP field. */ -#define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP) - -/*! @brief Format value for bitfield UART_IR_TNP. */ -#define BF_UART_IR_TNP(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP) - -/*! @brief Set the TNP field to a new value. */ -#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v))) -/*@}*/ - -/*! - * @name Register UART_IR, field IREN[2] (RW) - * - * Enables/disables the infrared modulation/demodulation. - * - * Values: - * - 0 - IR disabled. - * - 1 - IR enabled. - */ -/*@{*/ -#define BP_UART_IR_IREN (2U) /*!< Bit position for UART_IR_IREN. */ -#define BM_UART_IR_IREN (0x04U) /*!< Bit mask for UART_IR_IREN. */ -#define BS_UART_IR_IREN (1U) /*!< Bit field size in bits for UART_IR_IREN. */ - -/*! @brief Read current value of the UART_IR_IREN field. */ -#define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN)) - -/*! @brief Format value for bitfield UART_IR_IREN. */ -#define BF_UART_IR_IREN(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN) - -/*! @brief Set the IREN field to a new value. */ -#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_PFIFO - UART FIFO Parameters - ******************************************************************************/ - -/*! - * @brief HW_UART_PFIFO - UART FIFO Parameters (RW) - * - * Reset value: 0x00U - * - * This register provides the ability for the programmer to turn on and off FIFO - * functionality. It also provides the size of the FIFO that has been - * implemented. This register may be read at any time. This register must be written only - * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is - * empty. - */ -typedef union _hw_uart_pfifo -{ - uint8_t U; - struct _hw_uart_pfifo_bitfields - { - uint8_t RXFIFOSIZE : 3; /*!< [2:0] Receive FIFO. Buffer Depth */ - uint8_t RXFE : 1; /*!< [3] Receive FIFO Enable */ - uint8_t TXFIFOSIZE : 3; /*!< [6:4] Transmit FIFO. Buffer Depth */ - uint8_t TXFE : 1; /*!< [7] Transmit FIFO Enable */ - } B; -} hw_uart_pfifo_t; - -/*! - * @name Constants and macros for entire UART_PFIFO register - */ -/*@{*/ -#define HW_UART_PFIFO_ADDR(x) ((x) + 0x10U) - -#define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x)) -#define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U) -#define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v)) -#define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v))) -#define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v))) -#define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_PFIFO bitfields - */ - -/*! - * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO) - * - * The maximum number of receive datawords that can be stored in the receive - * buffer before an overrun occurs. This field is read only. - * - * Values: - * - 000 - Receive FIFO/Buffer depth = 1 dataword. - * - 001 - Receive FIFO/Buffer depth = 4 datawords. - * - 010 - Receive FIFO/Buffer depth = 8 datawords. - * - 011 - Receive FIFO/Buffer depth = 16 datawords. - * - 100 - Receive FIFO/Buffer depth = 32 datawords. - * - 101 - Receive FIFO/Buffer depth = 64 datawords. - * - 110 - Receive FIFO/Buffer depth = 128 datawords. - * - 111 - Reserved. - */ -/*@{*/ -#define BP_UART_PFIFO_RXFIFOSIZE (0U) /*!< Bit position for UART_PFIFO_RXFIFOSIZE. */ -#define BM_UART_PFIFO_RXFIFOSIZE (0x07U) /*!< Bit mask for UART_PFIFO_RXFIFOSIZE. */ -#define BS_UART_PFIFO_RXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. */ - -/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */ -#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE) -/*@}*/ - -/*! - * @name Register UART_PFIFO, field RXFE[3] (RW) - * - * When this field is set, the built in FIFO structure for the receive buffer is - * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field. - * If this field is not set, the receive buffer operates as a FIFO of depth one - * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be - * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH - * commands must be issued immediately after changing this field. - * - * Values: - * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) - * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. - */ -/*@{*/ -#define BP_UART_PFIFO_RXFE (3U) /*!< Bit position for UART_PFIFO_RXFE. */ -#define BM_UART_PFIFO_RXFE (0x08U) /*!< Bit mask for UART_PFIFO_RXFE. */ -#define BS_UART_PFIFO_RXFE (1U) /*!< Bit field size in bits for UART_PFIFO_RXFE. */ - -/*! @brief Read current value of the UART_PFIFO_RXFE field. */ -#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE)) - -/*! @brief Format value for bitfield UART_PFIFO_RXFE. */ -#define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE) - -/*! @brief Set the RXFE field to a new value. */ -#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO) - * - * The maximum number of transmit datawords that can be stored in the transmit - * buffer. This field is read only. - * - * Values: - * - 000 - Transmit FIFO/Buffer depth = 1 dataword. - * - 001 - Transmit FIFO/Buffer depth = 4 datawords. - * - 010 - Transmit FIFO/Buffer depth = 8 datawords. - * - 011 - Transmit FIFO/Buffer depth = 16 datawords. - * - 100 - Transmit FIFO/Buffer depth = 32 datawords. - * - 101 - Transmit FIFO/Buffer depth = 64 datawords. - * - 110 - Transmit FIFO/Buffer depth = 128 datawords. - * - 111 - Reserved. - */ -/*@{*/ -#define BP_UART_PFIFO_TXFIFOSIZE (4U) /*!< Bit position for UART_PFIFO_TXFIFOSIZE. */ -#define BM_UART_PFIFO_TXFIFOSIZE (0x70U) /*!< Bit mask for UART_PFIFO_TXFIFOSIZE. */ -#define BS_UART_PFIFO_TXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. */ - -/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */ -#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE) -/*@}*/ - -/*! - * @name Register UART_PFIFO, field TXFE[7] (RW) - * - * When this field is set, the built in FIFO structure for the transmit buffer - * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this - * field is not set, the transmit buffer operates as a FIFO of depth one dataword - * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared - * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must - * be issued immediately after changing this field. - * - * Values: - * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). - * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. - */ -/*@{*/ -#define BP_UART_PFIFO_TXFE (7U) /*!< Bit position for UART_PFIFO_TXFE. */ -#define BM_UART_PFIFO_TXFE (0x80U) /*!< Bit mask for UART_PFIFO_TXFE. */ -#define BS_UART_PFIFO_TXFE (1U) /*!< Bit field size in bits for UART_PFIFO_TXFE. */ - -/*! @brief Read current value of the UART_PFIFO_TXFE field. */ -#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE)) - -/*! @brief Format value for bitfield UART_PFIFO_TXFE. */ -#define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE) - -/*! @brief Set the TXFE field to a new value. */ -#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_CFIFO - UART FIFO Control Register - ******************************************************************************/ - -/*! - * @brief HW_UART_CFIFO - UART FIFO Control Register (RW) - * - * Reset value: 0x00U - * - * This register provides the ability to program various control fields for FIFO - * operation. This register may be read or written at any time. Note that - * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action - * to prevent unintended/unpredictable behavior. Therefore, it is recommended that - * TE and RE be cleared prior to flushing the corresponding FIFO. - */ -typedef union _hw_uart_cfifo -{ - uint8_t U; - struct _hw_uart_cfifo_bitfields - { - uint8_t RXUFE : 1; /*!< [0] Receive FIFO Underflow Interrupt Enable */ - uint8_t TXOFE : 1; /*!< [1] Transmit FIFO Overflow Interrupt Enable */ - uint8_t RXOFE : 1; /*!< [2] Receive FIFO Overflow Interrupt Enable */ - uint8_t RESERVED0 : 3; /*!< [5:3] */ - uint8_t RXFLUSH : 1; /*!< [6] Receive FIFO/Buffer Flush */ - uint8_t TXFLUSH : 1; /*!< [7] Transmit FIFO/Buffer Flush */ - } B; -} hw_uart_cfifo_t; - -/*! - * @name Constants and macros for entire UART_CFIFO register - */ -/*@{*/ -#define HW_UART_CFIFO_ADDR(x) ((x) + 0x11U) - -#define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x)) -#define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U) -#define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v)) -#define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v))) -#define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v))) -#define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_CFIFO bitfields - */ - -/*! - * @name Register UART_CFIFO, field RXUFE[0] (RW) - * - * When this field is set, the RXUF flag generates an interrupt to the host. - * - * Values: - * - 0 - RXUF flag does not generate an interrupt to the host. - * - 1 - RXUF flag generates an interrupt to the host. - */ -/*@{*/ -#define BP_UART_CFIFO_RXUFE (0U) /*!< Bit position for UART_CFIFO_RXUFE. */ -#define BM_UART_CFIFO_RXUFE (0x01U) /*!< Bit mask for UART_CFIFO_RXUFE. */ -#define BS_UART_CFIFO_RXUFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXUFE. */ - -/*! @brief Read current value of the UART_CFIFO_RXUFE field. */ -#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE)) - -/*! @brief Format value for bitfield UART_CFIFO_RXUFE. */ -#define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE) - -/*! @brief Set the RXUFE field to a new value. */ -#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field TXOFE[1] (RW) - * - * When this field is set, the TXOF flag generates an interrupt to the host. - * - * Values: - * - 0 - TXOF flag does not generate an interrupt to the host. - * - 1 - TXOF flag generates an interrupt to the host. - */ -/*@{*/ -#define BP_UART_CFIFO_TXOFE (1U) /*!< Bit position for UART_CFIFO_TXOFE. */ -#define BM_UART_CFIFO_TXOFE (0x02U) /*!< Bit mask for UART_CFIFO_TXOFE. */ -#define BS_UART_CFIFO_TXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_TXOFE. */ - -/*! @brief Read current value of the UART_CFIFO_TXOFE field. */ -#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE)) - -/*! @brief Format value for bitfield UART_CFIFO_TXOFE. */ -#define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE) - -/*! @brief Set the TXOFE field to a new value. */ -#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field RXOFE[2] (RW) - * - * When this field is set, the RXOF flag generates an interrupt to the host. - * - * Values: - * - 0 - RXOF flag does not generate an interrupt to the host. - * - 1 - RXOF flag generates an interrupt to the host. - */ -/*@{*/ -#define BP_UART_CFIFO_RXOFE (2U) /*!< Bit position for UART_CFIFO_RXOFE. */ -#define BM_UART_CFIFO_RXOFE (0x04U) /*!< Bit mask for UART_CFIFO_RXOFE. */ -#define BS_UART_CFIFO_RXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXOFE. */ - -/*! @brief Read current value of the UART_CFIFO_RXOFE field. */ -#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE)) - -/*! @brief Format value for bitfield UART_CFIFO_RXOFE. */ -#define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE) - -/*! @brief Set the RXOFE field to a new value. */ -#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ) - * - * Writing to this field causes all data that is stored in the receive - * FIFO/buffer to be flushed. This does not affect data that is in the receive shift - * register. - * - * Values: - * - 0 - No flush operation occurs. - * - 1 - All data in the receive FIFO/buffer is cleared out. - */ -/*@{*/ -#define BP_UART_CFIFO_RXFLUSH (6U) /*!< Bit position for UART_CFIFO_RXFLUSH. */ -#define BM_UART_CFIFO_RXFLUSH (0x40U) /*!< Bit mask for UART_CFIFO_RXFLUSH. */ -#define BS_UART_CFIFO_RXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_RXFLUSH. */ - -/*! @brief Format value for bitfield UART_CFIFO_RXFLUSH. */ -#define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH) - -/*! @brief Set the RXFLUSH field to a new value. */ -#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ) - * - * Writing to this field causes all data that is stored in the transmit - * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift - * register. - * - * Values: - * - 0 - No flush operation occurs. - * - 1 - All data in the transmit FIFO/Buffer is cleared out. - */ -/*@{*/ -#define BP_UART_CFIFO_TXFLUSH (7U) /*!< Bit position for UART_CFIFO_TXFLUSH. */ -#define BM_UART_CFIFO_TXFLUSH (0x80U) /*!< Bit mask for UART_CFIFO_TXFLUSH. */ -#define BS_UART_CFIFO_TXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_TXFLUSH. */ - -/*! @brief Format value for bitfield UART_CFIFO_TXFLUSH. */ -#define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH) - -/*! @brief Set the TXFLUSH field to a new value. */ -#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_SFIFO - UART FIFO Status Register - ******************************************************************************/ - -/*! - * @brief HW_UART_SFIFO - UART FIFO Status Register (RW) - * - * Reset value: 0xC0U - * - * This register provides status information regarding the transmit and receiver - * buffers/FIFOs, including interrupt information. This register may be written - * to or read at any time. - */ -typedef union _hw_uart_sfifo -{ - uint8_t U; - struct _hw_uart_sfifo_bitfields - { - uint8_t RXUF : 1; /*!< [0] Receiver Buffer Underflow Flag */ - uint8_t TXOF : 1; /*!< [1] Transmitter Buffer Overflow Flag */ - uint8_t RXOF : 1; /*!< [2] Receiver Buffer Overflow Flag */ - uint8_t RESERVED0 : 3; /*!< [5:3] */ - uint8_t RXEMPT : 1; /*!< [6] Receive Buffer/FIFO Empty */ - uint8_t TXEMPT : 1; /*!< [7] Transmit Buffer/FIFO Empty */ - } B; -} hw_uart_sfifo_t; - -/*! - * @name Constants and macros for entire UART_SFIFO register - */ -/*@{*/ -#define HW_UART_SFIFO_ADDR(x) ((x) + 0x12U) - -#define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x)) -#define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U) -#define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v)) -#define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v))) -#define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v))) -#define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_SFIFO bitfields - */ - -/*! - * @name Register UART_SFIFO, field RXUF[0] (W1C) - * - * Indicates that more data has been read from the receive buffer than was - * present. This field will assert regardless of the value of CFIFO[RXUFE]. However, - * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag - * is cleared by writing a 1. - * - * Values: - * - 0 - No receive buffer underflow has occurred since the last time the flag - * was cleared. - * - 1 - At least one receive buffer underflow has occurred since the last time - * the flag was cleared. - */ -/*@{*/ -#define BP_UART_SFIFO_RXUF (0U) /*!< Bit position for UART_SFIFO_RXUF. */ -#define BM_UART_SFIFO_RXUF (0x01U) /*!< Bit mask for UART_SFIFO_RXUF. */ -#define BS_UART_SFIFO_RXUF (1U) /*!< Bit field size in bits for UART_SFIFO_RXUF. */ - -/*! @brief Read current value of the UART_SFIFO_RXUF field. */ -#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF)) - -/*! @brief Format value for bitfield UART_SFIFO_RXUF. */ -#define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF) - -/*! @brief Set the RXUF field to a new value. */ -#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field TXOF[1] (W1C) - * - * Indicates that more data has been written to the transmit buffer than it can - * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However, - * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This - * flag is cleared by writing a 1. - * - * Values: - * - 0 - No transmit buffer overflow has occurred since the last time the flag - * was cleared. - * - 1 - At least one transmit buffer overflow has occurred since the last time - * the flag was cleared. - */ -/*@{*/ -#define BP_UART_SFIFO_TXOF (1U) /*!< Bit position for UART_SFIFO_TXOF. */ -#define BM_UART_SFIFO_TXOF (0x02U) /*!< Bit mask for UART_SFIFO_TXOF. */ -#define BS_UART_SFIFO_TXOF (1U) /*!< Bit field size in bits for UART_SFIFO_TXOF. */ - -/*! @brief Read current value of the UART_SFIFO_TXOF field. */ -#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF)) - -/*! @brief Format value for bitfield UART_SFIFO_TXOF. */ -#define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF) - -/*! @brief Set the TXOF field to a new value. */ -#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field RXOF[2] (W1C) - * - * Indicates that more data has been written to the receive buffer than it can - * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However, - * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag - * is cleared by writing a 1. - * - * Values: - * - 0 - No receive buffer overflow has occurred since the last time the flag - * was cleared. - * - 1 - At least one receive buffer overflow has occurred since the last time - * the flag was cleared. - */ -/*@{*/ -#define BP_UART_SFIFO_RXOF (2U) /*!< Bit position for UART_SFIFO_RXOF. */ -#define BM_UART_SFIFO_RXOF (0x04U) /*!< Bit mask for UART_SFIFO_RXOF. */ -#define BS_UART_SFIFO_RXOF (1U) /*!< Bit field size in bits for UART_SFIFO_RXOF. */ - -/*! @brief Read current value of the UART_SFIFO_RXOF field. */ -#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF)) - -/*! @brief Format value for bitfield UART_SFIFO_RXOF. */ -#define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF) - -/*! @brief Set the RXOF field to a new value. */ -#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field RXEMPT[6] (RO) - * - * Asserts when there is no data in the receive FIFO/Buffer. This field does not - * take into account data that is in the receive shift register. - * - * Values: - * - 0 - Receive buffer is not empty. - * - 1 - Receive buffer is empty. - */ -/*@{*/ -#define BP_UART_SFIFO_RXEMPT (6U) /*!< Bit position for UART_SFIFO_RXEMPT. */ -#define BM_UART_SFIFO_RXEMPT (0x40U) /*!< Bit mask for UART_SFIFO_RXEMPT. */ -#define BS_UART_SFIFO_RXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_RXEMPT. */ - -/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */ -#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field TXEMPT[7] (RO) - * - * Asserts when there is no data in the Transmit FIFO/buffer. This field does - * not take into account data that is in the transmit shift register. - * - * Values: - * - 0 - Transmit buffer is not empty. - * - 1 - Transmit buffer is empty. - */ -/*@{*/ -#define BP_UART_SFIFO_TXEMPT (7U) /*!< Bit position for UART_SFIFO_TXEMPT. */ -#define BM_UART_SFIFO_TXEMPT (0x80U) /*!< Bit mask for UART_SFIFO_TXEMPT. */ -#define BS_UART_SFIFO_TXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_TXEMPT. */ - -/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */ -#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT)) -/*@}*/ - -/******************************************************************************* - * HW_UART_TWFIFO - UART FIFO Transmit Watermark - ******************************************************************************/ - -/*! - * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW) - * - * Reset value: 0x00U - * - * This register provides the ability to set a programmable threshold for - * notification of needing additional transmit data. This register may be read at any - * time but must be written only when C2[TE] is not set. Changing the value of the - * watermark will not clear the S1[TDRE] flag. - */ -typedef union _hw_uart_twfifo -{ - uint8_t U; - struct _hw_uart_twfifo_bitfields - { - uint8_t TXWATER : 8; /*!< [7:0] Transmit Watermark */ - } B; -} hw_uart_twfifo_t; - -/*! - * @name Constants and macros for entire UART_TWFIFO register - */ -/*@{*/ -#define HW_UART_TWFIFO_ADDR(x) ((x) + 0x13U) - -#define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x)) -#define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U) -#define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v)) -#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v))) -#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v))) -#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_TWFIFO bitfields - */ - -/*! - * @name Register UART_TWFIFO, field TXWATER[7:0] (RW) - * - * When the number of datawords in the transmit FIFO/buffer is equal to or less - * than the value in this register field, an interrupt via S1[TDRE] or a DMA - * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For - * proper operation, the value in TXWATER must be set to be less than the size of - * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE]. - */ -/*@{*/ -#define BP_UART_TWFIFO_TXWATER (0U) /*!< Bit position for UART_TWFIFO_TXWATER. */ -#define BM_UART_TWFIFO_TXWATER (0xFFU) /*!< Bit mask for UART_TWFIFO_TXWATER. */ -#define BS_UART_TWFIFO_TXWATER (8U) /*!< Bit field size in bits for UART_TWFIFO_TXWATER. */ - -/*! @brief Read current value of the UART_TWFIFO_TXWATER field. */ -#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U) - -/*! @brief Format value for bitfield UART_TWFIFO_TXWATER. */ -#define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER) - -/*! @brief Set the TXWATER field to a new value. */ -#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_TCFIFO - UART FIFO Transmit Count - ******************************************************************************/ - -/*! - * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO) - * - * Reset value: 0x00U - * - * This is a read only register that indicates how many datawords are currently - * in the transmit buffer/FIFO. It may be read at any time. - */ -typedef union _hw_uart_tcfifo -{ - uint8_t U; - struct _hw_uart_tcfifo_bitfields - { - uint8_t TXCOUNT : 8; /*!< [7:0] Transmit Counter */ - } B; -} hw_uart_tcfifo_t; - -/*! - * @name Constants and macros for entire UART_TCFIFO register - */ -/*@{*/ -#define HW_UART_TCFIFO_ADDR(x) ((x) + 0x14U) - -#define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x)) -#define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_TCFIFO bitfields - */ - -/*! - * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO) - * - * The value in this register indicates the number of datawords that are in the - * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the - * transmit shift register, it is not included in the count. This value may be used - * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the - * transmit FIFO/buffer. - */ -/*@{*/ -#define BP_UART_TCFIFO_TXCOUNT (0U) /*!< Bit position for UART_TCFIFO_TXCOUNT. */ -#define BM_UART_TCFIFO_TXCOUNT (0xFFU) /*!< Bit mask for UART_TCFIFO_TXCOUNT. */ -#define BS_UART_TCFIFO_TXCOUNT (8U) /*!< Bit field size in bits for UART_TCFIFO_TXCOUNT. */ - -/*! @brief Read current value of the UART_TCFIFO_TXCOUNT field. */ -#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U) -/*@}*/ - -/******************************************************************************* - * HW_UART_RWFIFO - UART FIFO Receive Watermark - ******************************************************************************/ - -/*! - * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW) - * - * Reset value: 0x01U - * - * This register provides the ability to set a programmable threshold for - * notification of the need to remove data from the receiver FIFO/buffer. This register - * may be read at any time but must be written only when C2[RE] is not asserted. - * Changing the value in this register will not clear S1[RDRF]. - */ -typedef union _hw_uart_rwfifo -{ - uint8_t U; - struct _hw_uart_rwfifo_bitfields - { - uint8_t RXWATER : 8; /*!< [7:0] Receive Watermark */ - } B; -} hw_uart_rwfifo_t; - -/*! - * @name Constants and macros for entire UART_RWFIFO register - */ -/*@{*/ -#define HW_UART_RWFIFO_ADDR(x) ((x) + 0x15U) - -#define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x)) -#define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U) -#define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v)) -#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v))) -#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v))) -#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_RWFIFO bitfields - */ - -/*! - * @name Register UART_RWFIFO, field RXWATER[7:0] (RW) - * - * When the number of datawords in the receive FIFO/buffer is equal to or - * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA - * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For - * proper operation, the value in RXWATER must be set to be less than the receive - * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be - * greater than 0. - */ -/*@{*/ -#define BP_UART_RWFIFO_RXWATER (0U) /*!< Bit position for UART_RWFIFO_RXWATER. */ -#define BM_UART_RWFIFO_RXWATER (0xFFU) /*!< Bit mask for UART_RWFIFO_RXWATER. */ -#define BS_UART_RWFIFO_RXWATER (8U) /*!< Bit field size in bits for UART_RWFIFO_RXWATER. */ - -/*! @brief Read current value of the UART_RWFIFO_RXWATER field. */ -#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U) - -/*! @brief Format value for bitfield UART_RWFIFO_RXWATER. */ -#define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER) - -/*! @brief Set the RXWATER field to a new value. */ -#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_RCFIFO - UART FIFO Receive Count - ******************************************************************************/ - -/*! - * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO) - * - * Reset value: 0x00U - * - * This is a read only register that indicates how many datawords are currently - * in the receive FIFO/buffer. It may be read at any time. - */ -typedef union _hw_uart_rcfifo -{ - uint8_t U; - struct _hw_uart_rcfifo_bitfields - { - uint8_t RXCOUNT : 8; /*!< [7:0] Receive Counter */ - } B; -} hw_uart_rcfifo_t; - -/*! - * @name Constants and macros for entire UART_RCFIFO register - */ -/*@{*/ -#define HW_UART_RCFIFO_ADDR(x) ((x) + 0x16U) - -#define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x)) -#define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_RCFIFO bitfields - */ - -/*! - * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO) - * - * The value in this register indicates the number of datawords that are in the - * receive FIFO/buffer. If a dataword is being received, that is, in the receive - * shift register, it is not included in the count. This value may be used in - * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the - * receive FIFO/buffer. - */ -/*@{*/ -#define BP_UART_RCFIFO_RXCOUNT (0U) /*!< Bit position for UART_RCFIFO_RXCOUNT. */ -#define BM_UART_RCFIFO_RXCOUNT (0xFFU) /*!< Bit mask for UART_RCFIFO_RXCOUNT. */ -#define BS_UART_RCFIFO_RXCOUNT (8U) /*!< Bit field size in bits for UART_RCFIFO_RXCOUNT. */ - -/*! @brief Read current value of the UART_RCFIFO_RXCOUNT field. */ -#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U) -/*@}*/ - -/******************************************************************************* - * HW_UART_C7816 - UART 7816 Control Register - ******************************************************************************/ - -/*! - * @brief HW_UART_C7816 - UART 7816 Control Register (RW) - * - * Reset value: 0x00U - * - * The C7816 register is the primary control register for ISO-7816 specific - * functionality. This register is specific to 7816 functionality and the values in - * this register have no effect on UART operation and should be ignored if - * ISO_7816E is not set/enabled. This register may be read at any time but values must - * be changed only when ISO_7816E is not set. - */ -typedef union _hw_uart_c7816 -{ - uint8_t U; - struct _hw_uart_c7816_bitfields - { - uint8_t ISO_7816E : 1; /*!< [0] ISO-7816 Functionality Enabled */ - uint8_t TTYPE : 1; /*!< [1] Transfer Type */ - uint8_t INIT : 1; /*!< [2] Detect Initial Character */ - uint8_t ANACK : 1; /*!< [3] Generate NACK on Error */ - uint8_t ONACK : 1; /*!< [4] Generate NACK on Overflow */ - uint8_t RESERVED0 : 3; /*!< [7:5] */ - } B; -} hw_uart_c7816_t; - -/*! - * @name Constants and macros for entire UART_C7816 register - */ -/*@{*/ -#define HW_UART_C7816_ADDR(x) ((x) + 0x18U) - -#define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x)) -#define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U) -#define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v)) -#define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v))) -#define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v))) -#define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C7816 bitfields - */ - -/*! - * @name Register UART_C7816, field ISO_7816E[0] (RW) - * - * Indicates that the UART is operating according to the ISO-7816 protocol. This - * field must be modified only when no transmit or receive is occurring. If this - * field is changed during a data transfer, the data being transmitted or - * received may be transferred incorrectly. - * - * Values: - * - 0 - ISO-7816 functionality is turned off/not enabled. - * - 1 - ISO-7816 functionality is turned on/enabled. - */ -/*@{*/ -#define BP_UART_C7816_ISO_7816E (0U) /*!< Bit position for UART_C7816_ISO_7816E. */ -#define BM_UART_C7816_ISO_7816E (0x01U) /*!< Bit mask for UART_C7816_ISO_7816E. */ -#define BS_UART_C7816_ISO_7816E (1U) /*!< Bit field size in bits for UART_C7816_ISO_7816E. */ - -/*! @brief Read current value of the UART_C7816_ISO_7816E field. */ -#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E)) - -/*! @brief Format value for bitfield UART_C7816_ISO_7816E. */ -#define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E) - -/*! @brief Set the ISO_7816E field to a new value. */ -#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field TTYPE[1] (RW) - * - * Indicates the transfer protocol being used. See ISO-7816 / smartcard support - * for more details. - * - * Values: - * - 0 - T = 0 per the ISO-7816 specification. - * - 1 - T = 1 per the ISO-7816 specification. - */ -/*@{*/ -#define BP_UART_C7816_TTYPE (1U) /*!< Bit position for UART_C7816_TTYPE. */ -#define BM_UART_C7816_TTYPE (0x02U) /*!< Bit mask for UART_C7816_TTYPE. */ -#define BS_UART_C7816_TTYPE (1U) /*!< Bit field size in bits for UART_C7816_TTYPE. */ - -/*! @brief Read current value of the UART_C7816_TTYPE field. */ -#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE)) - -/*! @brief Format value for bitfield UART_C7816_TTYPE. */ -#define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE) - -/*! @brief Set the TTYPE field to a new value. */ -#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field INIT[2] (RW) - * - * When this field is set, all received characters are searched for a valid - * initial character. If an invalid initial character is identified, and ANACK is - * set, a NACK is sent. All received data is discarded and error flags blocked - * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[ADT], - * IS7816[GTV]) until a valid initial character is detected. Upon detecting a - * valid initial character, the configuration values S2[MSBF], C3[TXINV], and - * S2[RXINV] are automatically updated to reflect the initial character that was - * received. The actual INIT data value is not stored in the receive buffer. - * Additionally, upon detection of a valid initial character, IS7816[INITD] is set and an - * interrupt issued as programmed by IE7816[INITDE]. When a valid initial - * character is detected, INIT is automatically cleared. This Initial Character Detect - * feature is supported only in T = 0 protocol mode. - * - * Values: - * - 0 - Normal operating mode. Receiver does not seek to identify initial - * character. - * - 1 - Receiver searches for initial character. - */ -/*@{*/ -#define BP_UART_C7816_INIT (2U) /*!< Bit position for UART_C7816_INIT. */ -#define BM_UART_C7816_INIT (0x04U) /*!< Bit mask for UART_C7816_INIT. */ -#define BS_UART_C7816_INIT (1U) /*!< Bit field size in bits for UART_C7816_INIT. */ - -/*! @brief Read current value of the UART_C7816_INIT field. */ -#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT)) - -/*! @brief Format value for bitfield UART_C7816_INIT. */ -#define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT) - -/*! @brief Set the INIT field to a new value. */ -#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field ANACK[3] (RW) - * - * When this field is set, the receiver automatically generates a NACK response - * if a parity error occurs or if INIT is set and an invalid initial character is - * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART - * attempts to retransmit the data indefinitely. To stop retransmission attempts, - * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again. - * - * Values: - * - 0 - No NACK is automatically generated. - * - 1 - A NACK is automatically generated if a parity error is detected or if - * an invalid initial character is detected. - */ -/*@{*/ -#define BP_UART_C7816_ANACK (3U) /*!< Bit position for UART_C7816_ANACK. */ -#define BM_UART_C7816_ANACK (0x08U) /*!< Bit mask for UART_C7816_ANACK. */ -#define BS_UART_C7816_ANACK (1U) /*!< Bit field size in bits for UART_C7816_ANACK. */ - -/*! @brief Read current value of the UART_C7816_ANACK field. */ -#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK)) - -/*! @brief Format value for bitfield UART_C7816_ANACK. */ -#define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK) - -/*! @brief Set the ANACK field to a new value. */ -#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field ONACK[4] (RW) - * - * When this field is set, the receiver automatically generates a NACK response - * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems, - * this results in the transmitter resending the packet that overflowed until the - * retransmit threshold for that transmitter is reached. A NACK is generated only - * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK - * considerations - * - * Values: - * - 0 - The received data does not generate a NACK when the receipt of the data - * results in an overflow event. - * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a - * received character. - */ -/*@{*/ -#define BP_UART_C7816_ONACK (4U) /*!< Bit position for UART_C7816_ONACK. */ -#define BM_UART_C7816_ONACK (0x10U) /*!< Bit mask for UART_C7816_ONACK. */ -#define BS_UART_C7816_ONACK (1U) /*!< Bit field size in bits for UART_C7816_ONACK. */ - -/*! @brief Read current value of the UART_C7816_ONACK field. */ -#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK)) - -/*! @brief Format value for bitfield UART_C7816_ONACK. */ -#define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK) - -/*! @brief Set the ONACK field to a new value. */ -#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_IE7816 - UART 7816 Interrupt Enable Register - ******************************************************************************/ - -/*! - * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW) - * - * Reset value: 0x00U - * - * The IE7816 register controls which flags result in an interrupt being issued. - * This register is specific to 7816 functionality, the corresponding flags that - * drive the interrupts are not asserted when 7816E is not set/enabled. However, - * these flags may remain set if they are asserted while 7816E was set and not - * subsequently cleared. This register may be read or written to at any time. - */ -typedef union _hw_uart_ie7816 -{ - uint8_t U; - struct _hw_uart_ie7816_bitfields - { - uint8_t RXTE : 1; /*!< [0] Receive Threshold Exceeded Interrupt - * Enable */ - uint8_t TXTE : 1; /*!< [1] Transmit Threshold Exceeded Interrupt - * Enable */ - uint8_t GTVE : 1; /*!< [2] Guard Timer Violated Interrupt Enable */ - uint8_t ADTE : 1; /*!< [3] ATR Duration Timer Interrupt Enable */ - uint8_t INITDE : 1; /*!< [4] Initial Character Detected Interrupt - * Enable */ - uint8_t BWTE : 1; /*!< [5] Block Wait Timer Interrupt Enable */ - uint8_t CWTE : 1; /*!< [6] Character Wait Timer Interrupt Enable */ - uint8_t WTE : 1; /*!< [7] Wait Timer Interrupt Enable */ - } B; -} hw_uart_ie7816_t; - -/*! - * @name Constants and macros for entire UART_IE7816 register - */ -/*@{*/ -#define HW_UART_IE7816_ADDR(x) ((x) + 0x19U) - -#define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x)) -#define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U) -#define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v)) -#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v))) -#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v))) -#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_IE7816 bitfields - */ - -/*! - * @name Register UART_IE7816, field RXTE[0] (RW) - * - * Values: - * - 0 - The assertion of IS7816[RXT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_RXTE (0U) /*!< Bit position for UART_IE7816_RXTE. */ -#define BM_UART_IE7816_RXTE (0x01U) /*!< Bit mask for UART_IE7816_RXTE. */ -#define BS_UART_IE7816_RXTE (1U) /*!< Bit field size in bits for UART_IE7816_RXTE. */ - -/*! @brief Read current value of the UART_IE7816_RXTE field. */ -#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE)) - -/*! @brief Format value for bitfield UART_IE7816_RXTE. */ -#define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE) - -/*! @brief Set the RXTE field to a new value. */ -#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field TXTE[1] (RW) - * - * Values: - * - 0 - The assertion of IS7816[TXT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_TXTE (1U) /*!< Bit position for UART_IE7816_TXTE. */ -#define BM_UART_IE7816_TXTE (0x02U) /*!< Bit mask for UART_IE7816_TXTE. */ -#define BS_UART_IE7816_TXTE (1U) /*!< Bit field size in bits for UART_IE7816_TXTE. */ - -/*! @brief Read current value of the UART_IE7816_TXTE field. */ -#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE)) - -/*! @brief Format value for bitfield UART_IE7816_TXTE. */ -#define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE) - -/*! @brief Set the TXTE field to a new value. */ -#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field GTVE[2] (RW) - * - * Values: - * - 0 - The assertion of IS7816[GTV] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_GTVE (2U) /*!< Bit position for UART_IE7816_GTVE. */ -#define BM_UART_IE7816_GTVE (0x04U) /*!< Bit mask for UART_IE7816_GTVE. */ -#define BS_UART_IE7816_GTVE (1U) /*!< Bit field size in bits for UART_IE7816_GTVE. */ - -/*! @brief Read current value of the UART_IE7816_GTVE field. */ -#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE)) - -/*! @brief Format value for bitfield UART_IE7816_GTVE. */ -#define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE) - -/*! @brief Set the GTVE field to a new value. */ -#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field ADTE[3] (RW) - * - * Values: - * - 0 - The assertion of IS7816[ADT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[ADT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_ADTE (3U) /*!< Bit position for UART_IE7816_ADTE. */ -#define BM_UART_IE7816_ADTE (0x08U) /*!< Bit mask for UART_IE7816_ADTE. */ -#define BS_UART_IE7816_ADTE (1U) /*!< Bit field size in bits for UART_IE7816_ADTE. */ - -/*! @brief Read current value of the UART_IE7816_ADTE field. */ -#define BR_UART_IE7816_ADTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_ADTE)) - -/*! @brief Format value for bitfield UART_IE7816_ADTE. */ -#define BF_UART_IE7816_ADTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_ADTE) & BM_UART_IE7816_ADTE) - -/*! @brief Set the ADTE field to a new value. */ -#define BW_UART_IE7816_ADTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_ADTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field INITDE[4] (RW) - * - * Values: - * - 0 - The assertion of IS7816[INITD] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[INITD] results in the generation of an - * interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_INITDE (4U) /*!< Bit position for UART_IE7816_INITDE. */ -#define BM_UART_IE7816_INITDE (0x10U) /*!< Bit mask for UART_IE7816_INITDE. */ -#define BS_UART_IE7816_INITDE (1U) /*!< Bit field size in bits for UART_IE7816_INITDE. */ - -/*! @brief Read current value of the UART_IE7816_INITDE field. */ -#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE)) - -/*! @brief Format value for bitfield UART_IE7816_INITDE. */ -#define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE) - -/*! @brief Set the INITDE field to a new value. */ -#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field BWTE[5] (RW) - * - * Values: - * - 0 - The assertion of IS7816[BWT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_BWTE (5U) /*!< Bit position for UART_IE7816_BWTE. */ -#define BM_UART_IE7816_BWTE (0x20U) /*!< Bit mask for UART_IE7816_BWTE. */ -#define BS_UART_IE7816_BWTE (1U) /*!< Bit field size in bits for UART_IE7816_BWTE. */ - -/*! @brief Read current value of the UART_IE7816_BWTE field. */ -#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE)) - -/*! @brief Format value for bitfield UART_IE7816_BWTE. */ -#define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE) - -/*! @brief Set the BWTE field to a new value. */ -#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field CWTE[6] (RW) - * - * Values: - * - 0 - The assertion of IS7816[CWT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_CWTE (6U) /*!< Bit position for UART_IE7816_CWTE. */ -#define BM_UART_IE7816_CWTE (0x40U) /*!< Bit mask for UART_IE7816_CWTE. */ -#define BS_UART_IE7816_CWTE (1U) /*!< Bit field size in bits for UART_IE7816_CWTE. */ - -/*! @brief Read current value of the UART_IE7816_CWTE field. */ -#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE)) - -/*! @brief Format value for bitfield UART_IE7816_CWTE. */ -#define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE) - -/*! @brief Set the CWTE field to a new value. */ -#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field WTE[7] (RW) - * - * Values: - * - 0 - The assertion of IS7816[WT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_WTE (7U) /*!< Bit position for UART_IE7816_WTE. */ -#define BM_UART_IE7816_WTE (0x80U) /*!< Bit mask for UART_IE7816_WTE. */ -#define BS_UART_IE7816_WTE (1U) /*!< Bit field size in bits for UART_IE7816_WTE. */ - -/*! @brief Read current value of the UART_IE7816_WTE field. */ -#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE)) - -/*! @brief Format value for bitfield UART_IE7816_WTE. */ -#define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE) - -/*! @brief Set the WTE field to a new value. */ -#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_IS7816 - UART 7816 Interrupt Status Register - ******************************************************************************/ - -/*! - * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (W1C) - * - * Reset value: 0x00U - * - * The IS7816 register provides a mechanism to read and clear the interrupt - * flags. All flags/interrupts are cleared by writing a 1 to the field location. - * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only - * the flag condition that occurred since the last time the bit was cleared, not - * that the condition currently exists. The status flags are set regardless of - * whether the corresponding field in the IE7816 is set or cleared. The IE7816 - * controls only if an interrupt is issued to the host processor. This register is - * specific to 7816 functionality and the values in this register have no affect on - * UART operation and should be ignored if 7816E is not set/enabled. This - * register may be read or written at anytime. - */ -typedef union _hw_uart_is7816 -{ - uint8_t U; - struct _hw_uart_is7816_bitfields - { - uint8_t RXT : 1; /*!< [0] Receive Threshold Exceeded Interrupt */ - uint8_t TXT : 1; /*!< [1] Transmit Threshold Exceeded Interrupt */ - uint8_t GTV : 1; /*!< [2] Guard Timer Violated Interrupt */ - uint8_t ADT : 1; /*!< [3] ATR Duration Time Interrupt */ - uint8_t INITD : 1; /*!< [4] Initial Character Detected Interrupt */ - uint8_t BWT : 1; /*!< [5] Block Wait Timer Interrupt */ - uint8_t CWT : 1; /*!< [6] Character Wait Timer Interrupt */ - uint8_t WT : 1; /*!< [7] Wait Timer Interrupt */ - } B; -} hw_uart_is7816_t; - -/*! - * @name Constants and macros for entire UART_IS7816 register - */ -/*@{*/ -#define HW_UART_IS7816_ADDR(x) ((x) + 0x1AU) - -#define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x)) -#define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U) -#define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v)) -#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v))) -#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v))) -#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_IS7816 bitfields - */ - -/*! - * @name Register UART_IS7816, field RXT[0] (W1C) - * - * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS - * generated in response to parity errors on received data. This flag requires ANACK - * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0. - * Clearing this field also resets the counter keeping track of consecutive NACKS. The - * UART will continue to attempt to receive data regardless of whether this flag - * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1, - * or packet is received without needing to issue a NACK, the internal NACK - * detection counter is cleared and the count restarts from zero on the next - * transmitted NACK. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - The number of consecutive NACKS generated as a result of parity errors - * and buffer overruns is less than or equal to the value in - * ET7816[RXTHRESHOLD]. - * - 1 - The number of consecutive NACKS generated as a result of parity errors - * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. - */ -/*@{*/ -#define BP_UART_IS7816_RXT (0U) /*!< Bit position for UART_IS7816_RXT. */ -#define BM_UART_IS7816_RXT (0x01U) /*!< Bit mask for UART_IS7816_RXT. */ -#define BS_UART_IS7816_RXT (1U) /*!< Bit field size in bits for UART_IS7816_RXT. */ - -/*! @brief Read current value of the UART_IS7816_RXT field. */ -#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT)) - -/*! @brief Format value for bitfield UART_IS7816_RXT. */ -#define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT) - -/*! @brief Set the RXT field to a new value. */ -#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field TXT[1] (W1C) - * - * Indicates that the transmit NACK threshold has been exceeded as indicated by - * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART - * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If - * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is - * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the - * internal NACK detection counter is cleared and the count restarts from zero on - * the next received NACK. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - The number of retries and corresponding NACKS does not exceed the value - * in ET7816[TXTHRESHOLD]. - * - 1 - The number of retries and corresponding NACKS exceeds the value in - * ET7816[TXTHRESHOLD]. - */ -/*@{*/ -#define BP_UART_IS7816_TXT (1U) /*!< Bit position for UART_IS7816_TXT. */ -#define BM_UART_IS7816_TXT (0x02U) /*!< Bit mask for UART_IS7816_TXT. */ -#define BS_UART_IS7816_TXT (1U) /*!< Bit field size in bits for UART_IS7816_TXT. */ - -/*! @brief Read current value of the UART_IS7816_TXT field. */ -#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT)) - -/*! @brief Format value for bitfield UART_IS7816_TXT. */ -#define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT) - -/*! @brief Set the TXT field to a new value. */ -#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field GTV[2] (W1C) - * - * Indicates that one or more of the character guard time, block guard time, or - * guard time are violated. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - A guard time (GT, CGT, or BGT) has not been violated. - * - 1 - A guard time (GT, CGT, or BGT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_GTV (2U) /*!< Bit position for UART_IS7816_GTV. */ -#define BM_UART_IS7816_GTV (0x04U) /*!< Bit mask for UART_IS7816_GTV. */ -#define BS_UART_IS7816_GTV (1U) /*!< Bit field size in bits for UART_IS7816_GTV. */ - -/*! @brief Read current value of the UART_IS7816_GTV field. */ -#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV)) - -/*! @brief Format value for bitfield UART_IS7816_GTV. */ -#define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV) - -/*! @brief Set the GTV field to a new value. */ -#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field ADT[3] (W1C) - * - * Indicates that the ATR duration time, the time between the leading edge of - * the TS character being received and the leading edge of the next response - * character, has exceeded the programmed value. This flag asserts only when - * C7816[TTYPE] = 0. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - ATR Duration time (ADT) has not been violated. - * - 1 - ATR Duration time (ADT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_ADT (3U) /*!< Bit position for UART_IS7816_ADT. */ -#define BM_UART_IS7816_ADT (0x08U) /*!< Bit mask for UART_IS7816_ADT. */ -#define BS_UART_IS7816_ADT (1U) /*!< Bit field size in bits for UART_IS7816_ADT. */ - -/*! @brief Read current value of the UART_IS7816_ADT field. */ -#define BR_UART_IS7816_ADT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_ADT)) - -/*! @brief Format value for bitfield UART_IS7816_ADT. */ -#define BF_UART_IS7816_ADT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_ADT) & BM_UART_IS7816_ADT) - -/*! @brief Set the ADT field to a new value. */ -#define BW_UART_IS7816_ADT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_ADT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field INITD[4] (W1C) - * - * Indicates that a valid initial character is received. This interrupt is - * cleared by writing 1. - * - * Values: - * - 0 - A valid initial character has not been received. - * - 1 - A valid initial character has been received. - */ -/*@{*/ -#define BP_UART_IS7816_INITD (4U) /*!< Bit position for UART_IS7816_INITD. */ -#define BM_UART_IS7816_INITD (0x10U) /*!< Bit mask for UART_IS7816_INITD. */ -#define BS_UART_IS7816_INITD (1U) /*!< Bit field size in bits for UART_IS7816_INITD. */ - -/*! @brief Read current value of the UART_IS7816_INITD field. */ -#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD)) - -/*! @brief Format value for bitfield UART_IS7816_INITD. */ -#define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD) - -/*! @brief Set the INITD field to a new value. */ -#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field BWT[5] (W1C) - * - * Indicates that the block wait time, the time between the leading edge of - * first received character of a block and the leading edge of the last character the - * previously transmitted block, has exceeded the programmed value. This flag - * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1. - * - * Values: - * - 0 - Block wait time (BWT) has not been violated. - * - 1 - Block wait time (BWT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_BWT (5U) /*!< Bit position for UART_IS7816_BWT. */ -#define BM_UART_IS7816_BWT (0x20U) /*!< Bit mask for UART_IS7816_BWT. */ -#define BS_UART_IS7816_BWT (1U) /*!< Bit field size in bits for UART_IS7816_BWT. */ - -/*! @brief Read current value of the UART_IS7816_BWT field. */ -#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT)) - -/*! @brief Format value for bitfield UART_IS7816_BWT. */ -#define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT) - -/*! @brief Set the BWT field to a new value. */ -#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field CWT[6] (W1C) - * - * Indicates that the character wait time, the time between the leading edges of - * two consecutive characters in a block, has exceeded the programmed value. - * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by - * writing 1. - * - * Values: - * - 0 - Character wait time (CWT) has not been violated. - * - 1 - Character wait time (CWT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_CWT (6U) /*!< Bit position for UART_IS7816_CWT. */ -#define BM_UART_IS7816_CWT (0x40U) /*!< Bit mask for UART_IS7816_CWT. */ -#define BS_UART_IS7816_CWT (1U) /*!< Bit field size in bits for UART_IS7816_CWT. */ - -/*! @brief Read current value of the UART_IS7816_CWT field. */ -#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT)) - -/*! @brief Format value for bitfield UART_IS7816_CWT. */ -#define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT) - -/*! @brief Set the CWT field to a new value. */ -#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field WT[7] (W1C) - * - * Indicates that the wait time, the time between the leading edge of a - * character being transmitted and the leading edge of the next response character, has - * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0. - * This interrupt is cleared by writing 1. - * - * Values: - * - 0 - Wait time (WT) has not been violated. - * - 1 - Wait time (WT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_WT (7U) /*!< Bit position for UART_IS7816_WT. */ -#define BM_UART_IS7816_WT (0x80U) /*!< Bit mask for UART_IS7816_WT. */ -#define BS_UART_IS7816_WT (1U) /*!< Bit field size in bits for UART_IS7816_WT. */ - -/*! @brief Read current value of the UART_IS7816_WT field. */ -#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT)) - -/*! @brief Format value for bitfield UART_IS7816_WT. */ -#define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT) - -/*! @brief Set the WT field to a new value. */ -#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WP7816 - UART 7816 Wait Parameter Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816 - UART 7816 Wait Parameter Register (RW) - * - * Reset value: 0x00U - * - * The WP7816 register contains the WTX variable used in the generation of the - * block wait timer. This register may be read at any time. This register must be - * written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816 -{ - uint8_t U; - struct _hw_uart_wp7816_bitfields - { - uint8_t WTX : 8; /*!< [7:0] Wait Time Multiplier (C7816[TTYPE] = 1) */ - } B; -} hw_uart_wp7816_t; - -/*! - * @name Constants and macros for entire UART_WP7816 register - */ -/*@{*/ -#define HW_UART_WP7816_ADDR(x) ((x) + 0x1BU) - -#define HW_UART_WP7816(x) (*(__IO hw_uart_wp7816_t *) HW_UART_WP7816_ADDR(x)) -#define HW_UART_WP7816_RD(x) (HW_UART_WP7816(x).U) -#define HW_UART_WP7816_WR(x, v) (HW_UART_WP7816(x).U = (v)) -#define HW_UART_WP7816_SET(x, v) (HW_UART_WP7816_WR(x, HW_UART_WP7816_RD(x) | (v))) -#define HW_UART_WP7816_CLR(x, v) (HW_UART_WP7816_WR(x, HW_UART_WP7816_RD(x) & ~(v))) -#define HW_UART_WP7816_TOG(x, v) (HW_UART_WP7816_WR(x, HW_UART_WP7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816 bitfields - */ - -/*! - * @name Register UART_WP7816, field WTX[7:0] (RW) - * - * Used to calculate the value used for the BWT counter. It represents a value - * between 0 and 255. This value is used only when C7816[TTYPE] = 1. See Wait time - * and guard time parameters. - */ -/*@{*/ -#define BP_UART_WP7816_WTX (0U) /*!< Bit position for UART_WP7816_WTX. */ -#define BM_UART_WP7816_WTX (0xFFU) /*!< Bit mask for UART_WP7816_WTX. */ -#define BS_UART_WP7816_WTX (8U) /*!< Bit field size in bits for UART_WP7816_WTX. */ - -/*! @brief Read current value of the UART_WP7816_WTX field. */ -#define BR_UART_WP7816_WTX(x) (HW_UART_WP7816(x).U) - -/*! @brief Format value for bitfield UART_WP7816_WTX. */ -#define BF_UART_WP7816_WTX(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816_WTX) & BM_UART_WP7816_WTX) - -/*! @brief Set the WTX field to a new value. */ -#define BW_UART_WP7816_WTX(x, v) (HW_UART_WP7816_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WN7816 - UART 7816 Wait N Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW) - * - * Reset value: 0x00U - * - * The WN7816 register contains a parameter that is used in the calculation of - * the guard time counter. This register may be read at any time. This register - * must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wn7816 -{ - uint8_t U; - struct _hw_uart_wn7816_bitfields - { - uint8_t GTN : 8; /*!< [7:0] Guard Band N */ - } B; -} hw_uart_wn7816_t; - -/*! - * @name Constants and macros for entire UART_WN7816 register - */ -/*@{*/ -#define HW_UART_WN7816_ADDR(x) ((x) + 0x1CU) - -#define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x)) -#define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U) -#define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v)) -#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v))) -#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v))) -#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WN7816 bitfields - */ - -/*! - * @name Register UART_WN7816, field GTN[7:0] (RW) - * - * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The - * value represents an integer number between 0 and 255. See Wait time and guard - * time parameters . - */ -/*@{*/ -#define BP_UART_WN7816_GTN (0U) /*!< Bit position for UART_WN7816_GTN. */ -#define BM_UART_WN7816_GTN (0xFFU) /*!< Bit mask for UART_WN7816_GTN. */ -#define BS_UART_WN7816_GTN (8U) /*!< Bit field size in bits for UART_WN7816_GTN. */ - -/*! @brief Read current value of the UART_WN7816_GTN field. */ -#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U) - -/*! @brief Format value for bitfield UART_WN7816_GTN. */ -#define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN) - -/*! @brief Set the GTN field to a new value. */ -#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WF7816 - UART 7816 Wait FD Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW) - * - * Reset value: 0x01U - * - * The WF7816 contains parameters that are used in the generation of various - * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wf7816 -{ - uint8_t U; - struct _hw_uart_wf7816_bitfields - { - uint8_t GTFD : 8; /*!< [7:0] FD Multiplier */ - } B; -} hw_uart_wf7816_t; - -/*! - * @name Constants and macros for entire UART_WF7816 register - */ -/*@{*/ -#define HW_UART_WF7816_ADDR(x) ((x) + 0x1DU) - -#define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x)) -#define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U) -#define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v)) -#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v))) -#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v))) -#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WF7816 bitfields - */ - -/*! - * @name Register UART_WF7816, field GTFD[7:0] (RW) - * - * Used as another multiplier in the calculation of BWT. This value represents a - * number between 1 and 255. The value of 0 is invalid. This value is not used - * in baud rate generation. See Wait time and guard time parameters and Baud rate - * generation . - */ -/*@{*/ -#define BP_UART_WF7816_GTFD (0U) /*!< Bit position for UART_WF7816_GTFD. */ -#define BM_UART_WF7816_GTFD (0xFFU) /*!< Bit mask for UART_WF7816_GTFD. */ -#define BS_UART_WF7816_GTFD (8U) /*!< Bit field size in bits for UART_WF7816_GTFD. */ - -/*! @brief Read current value of the UART_WF7816_GTFD field. */ -#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U) - -/*! @brief Format value for bitfield UART_WF7816_GTFD. */ -#define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD) - -/*! @brief Set the GTFD field to a new value. */ -#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_ET7816 - UART 7816 Error Threshold Register - ******************************************************************************/ - -/*! - * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW) - * - * Reset value: 0x00U - * - * The ET7816 register contains fields that determine the number of NACKs that - * must be received or transmitted before the host processor is notified. This - * register may be read at anytime. This register must be written to only when - * C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_et7816 -{ - uint8_t U; - struct _hw_uart_et7816_bitfields - { - uint8_t RXTHRESHOLD : 4; /*!< [3:0] Receive NACK Threshold */ - uint8_t TXTHRESHOLD : 4; /*!< [7:4] Transmit NACK Threshold */ - } B; -} hw_uart_et7816_t; - -/*! - * @name Constants and macros for entire UART_ET7816 register - */ -/*@{*/ -#define HW_UART_ET7816_ADDR(x) ((x) + 0x1EU) - -#define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x)) -#define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U) -#define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v)) -#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v))) -#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v))) -#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_ET7816 bitfields - */ - -/*! - * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW) - * - * The value written to this field indicates the maximum number of consecutive - * NACKs generated as a result of a parity error or receiver buffer overruns - * before the host processor is notified. After the counter exceeds that value in the - * field, the IS7816[RXT] is asserted. This field is meaningful only when - * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive - * NACKs that have been transmitted since the last successful reception. This - * counter saturates at 4'hF and does not wrap around. Regardless of the number of - * NACKs sent, the UART continues to receive valid packets indefinitely. For - * additional information, see IS7816[RXT] field description. - */ -/*@{*/ -#define BP_UART_ET7816_RXTHRESHOLD (0U) /*!< Bit position for UART_ET7816_RXTHRESHOLD. */ -#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /*!< Bit mask for UART_ET7816_RXTHRESHOLD. */ -#define BS_UART_ET7816_RXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. */ - -/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */ -#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD) - -/*! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. */ -#define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD) - -/*! @brief Set the RXTHRESHOLD field to a new value. */ -#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v))) -/*@}*/ - -/*! - * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW) - * - * The value written to this field indicates the maximum number of failed - * attempts (NACKs) a transmitted character can have before the host processor is - * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1. - * The value read from this field represents the number of consecutive NACKs - * that have been received since the last successful transmission. This counter - * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are - * received, the UART continues to retransmit indefinitely. This flag only - * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field - * description. - * - * Values: - * - 0 - TXT asserts on the first NACK that is received. - * - 1 - TXT asserts on the second NACK that is received. - */ -/*@{*/ -#define BP_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit position for UART_ET7816_TXTHRESHOLD. */ -#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /*!< Bit mask for UART_ET7816_TXTHRESHOLD. */ -#define BS_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. */ - -/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */ -#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD) - -/*! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. */ -#define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD) - -/*! @brief Set the TXTHRESHOLD field to a new value. */ -#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v))) -/*@}*/ - -/******************************************************************************* - * HW_UART_TL7816 - UART 7816 Transmit Length Register - ******************************************************************************/ - -/*! - * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW) - * - * Reset value: 0x00U - * - * The TL7816 register is used to indicate the number of characters contained in - * the block being transmitted. This register is used only when C7816[TTYPE] = - * 1. This register may be read at anytime. This register must be written only - * when C2[TE] is not enabled. - */ -typedef union _hw_uart_tl7816 -{ - uint8_t U; - struct _hw_uart_tl7816_bitfields - { - uint8_t TLEN : 8; /*!< [7:0] Transmit Length */ - } B; -} hw_uart_tl7816_t; - -/*! - * @name Constants and macros for entire UART_TL7816 register - */ -/*@{*/ -#define HW_UART_TL7816_ADDR(x) ((x) + 0x1FU) - -#define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x)) -#define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U) -#define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v)) -#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v))) -#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v))) -#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_TL7816 bitfields - */ - -/*! - * @name Register UART_TL7816, field TLEN[7:0] (RW) - * - * This value plus four indicates the number of characters contained in the - * block being transmitted. This register is automatically decremented by 1 for each - * character in the information field portion of the block. Additionally, this - * register is automatically decremented by 1 for the first character of a CRC in - * the epilogue field. Therefore, this register must be programmed with the number - * of bytes in the data packet if an LRC is being transmitted, and the number of - * bytes + 1 if a CRC is being transmitted. This register is not decremented for - * characters that are assumed to be part of the Prologue field, that is, the - * first three characters transmitted in a block, or the LRC or last CRC character - * in the Epilogue field, that is, the last character transmitted. This field - * must be programed or adjusted only when C2[TE] is cleared. - */ -/*@{*/ -#define BP_UART_TL7816_TLEN (0U) /*!< Bit position for UART_TL7816_TLEN. */ -#define BM_UART_TL7816_TLEN (0xFFU) /*!< Bit mask for UART_TL7816_TLEN. */ -#define BS_UART_TL7816_TLEN (8U) /*!< Bit field size in bits for UART_TL7816_TLEN. */ - -/*! @brief Read current value of the UART_TL7816_TLEN field. */ -#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U) - -/*! @brief Format value for bitfield UART_TL7816_TLEN. */ -#define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN) - -/*! @brief Set the TLEN field to a new value. */ -#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A - ******************************************************************************/ - -/*! - * @brief HW_UART_AP7816A_T0 - UART 7816 ATR Duration Timer Register A (RW) - * - * Reset value: 0x00U - * - * The AP7816A_T0 register contains variables used in the generation of the ATR - * Duration Timer. This register may be read at any time. This register must be - * written to only when C7816[ISO_7816E] is not set, except when writing 0 to - * clear the ADT Counter. The ADT Counter starts counting on detection of the - * complete TS Character. It must be noted that by this time, exactly 10 ETUs have - * elapsed since the start bit of the TS character. The user must take this into - * account while programming this register. - */ -typedef union _hw_uart_ap7816a_t0 -{ - uint8_t U; - struct _hw_uart_ap7816a_t0_bitfields - { - uint8_t ADTI_H : 8; /*!< [7:0] ATR Duration Time Integer High - * (C7816[TTYPE] = 0) */ - } B; -} hw_uart_ap7816a_t0_t; - -/*! - * @name Constants and macros for entire UART_AP7816A_T0 register - */ -/*@{*/ -#define HW_UART_AP7816A_T0_ADDR(x) ((x) + 0x3AU) - -#define HW_UART_AP7816A_T0(x) (*(__IO hw_uart_ap7816a_t0_t *) HW_UART_AP7816A_T0_ADDR(x)) -#define HW_UART_AP7816A_T0_RD(x) (HW_UART_AP7816A_T0(x).U) -#define HW_UART_AP7816A_T0_WR(x, v) (HW_UART_AP7816A_T0(x).U = (v)) -#define HW_UART_AP7816A_T0_SET(x, v) (HW_UART_AP7816A_T0_WR(x, HW_UART_AP7816A_T0_RD(x) | (v))) -#define HW_UART_AP7816A_T0_CLR(x, v) (HW_UART_AP7816A_T0_WR(x, HW_UART_AP7816A_T0_RD(x) & ~(v))) -#define HW_UART_AP7816A_T0_TOG(x, v) (HW_UART_AP7816A_T0_WR(x, HW_UART_AP7816A_T0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_AP7816A_T0 bitfields - */ - -/*! - * @name Register UART_AP7816A_T0, field ADTI_H[7:0] (RW) - * - * Used to calculate the value used for the ADT Counter. This register field - * provides the most significant byte of the 16 bit ATR Duration Time Integer field - * ADTI formed by {AP7816A_T0[ADTI_H], AP7816B_T0[ADTI_L]}. Programming a value - * of ADTI = 0 disables the ADT counter. This value is used only when C7816[TTYPE] - * = 0. See ATR Duration Time Counter. - */ -/*@{*/ -#define BP_UART_AP7816A_T0_ADTI_H (0U) /*!< Bit position for UART_AP7816A_T0_ADTI_H. */ -#define BM_UART_AP7816A_T0_ADTI_H (0xFFU) /*!< Bit mask for UART_AP7816A_T0_ADTI_H. */ -#define BS_UART_AP7816A_T0_ADTI_H (8U) /*!< Bit field size in bits for UART_AP7816A_T0_ADTI_H. */ - -/*! @brief Read current value of the UART_AP7816A_T0_ADTI_H field. */ -#define BR_UART_AP7816A_T0_ADTI_H(x) (HW_UART_AP7816A_T0(x).U) - -/*! @brief Format value for bitfield UART_AP7816A_T0_ADTI_H. */ -#define BF_UART_AP7816A_T0_ADTI_H(v) ((uint8_t)((uint8_t)(v) << BP_UART_AP7816A_T0_ADTI_H) & BM_UART_AP7816A_T0_ADTI_H) - -/*! @brief Set the ADTI_H field to a new value. */ -#define BW_UART_AP7816A_T0_ADTI_H(x, v) (HW_UART_AP7816A_T0_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B - ******************************************************************************/ - -/*! - * @brief HW_UART_AP7816B_T0 - UART 7816 ATR Duration Timer Register B (RW) - * - * Reset value: 0x00U - * - * The AP7816B_T0 register contains variables used in the generation of the ATR - * Duration Timer. This register may be read at any time. This register must be - * written to only when C7816[ISO_7816E] is not set, except when writing 0 to - * clear the ADT Counter. The ADT Counter starts counting on detection of the - * complete TS Character. It must be noted that by this time, exactly 10 ETUs have - * elapsed since the start bit of the TS character. The user must take this into - * account while programming this register. - */ -typedef union _hw_uart_ap7816b_t0 -{ - uint8_t U; - struct _hw_uart_ap7816b_t0_bitfields - { - uint8_t ADTI_L : 8; /*!< [7:0] ATR Duration Time Integer Low - * (C7816[TTYPE] = 0) */ - } B; -} hw_uart_ap7816b_t0_t; - -/*! - * @name Constants and macros for entire UART_AP7816B_T0 register - */ -/*@{*/ -#define HW_UART_AP7816B_T0_ADDR(x) ((x) + 0x3BU) - -#define HW_UART_AP7816B_T0(x) (*(__IO hw_uart_ap7816b_t0_t *) HW_UART_AP7816B_T0_ADDR(x)) -#define HW_UART_AP7816B_T0_RD(x) (HW_UART_AP7816B_T0(x).U) -#define HW_UART_AP7816B_T0_WR(x, v) (HW_UART_AP7816B_T0(x).U = (v)) -#define HW_UART_AP7816B_T0_SET(x, v) (HW_UART_AP7816B_T0_WR(x, HW_UART_AP7816B_T0_RD(x) | (v))) -#define HW_UART_AP7816B_T0_CLR(x, v) (HW_UART_AP7816B_T0_WR(x, HW_UART_AP7816B_T0_RD(x) & ~(v))) -#define HW_UART_AP7816B_T0_TOG(x, v) (HW_UART_AP7816B_T0_WR(x, HW_UART_AP7816B_T0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_AP7816B_T0 bitfields - */ - -/*! - * @name Register UART_AP7816B_T0, field ADTI_L[7:0] (RW) - * - * Used to calculate the value used for the ADT counter. This register field - * provides the least significant byte of the 16 bit ATR Duration Time Integer field - * ADTI formed by {AP7816A_T0[ADTI_H], AP7816B_T0[ADTI_L]}. Programming a value - * of ADTI = 0 disables the ADT counter. This value is used only when - * C7816[TTYPE] = 0. See ATR Duration Time Counter. - */ -/*@{*/ -#define BP_UART_AP7816B_T0_ADTI_L (0U) /*!< Bit position for UART_AP7816B_T0_ADTI_L. */ -#define BM_UART_AP7816B_T0_ADTI_L (0xFFU) /*!< Bit mask for UART_AP7816B_T0_ADTI_L. */ -#define BS_UART_AP7816B_T0_ADTI_L (8U) /*!< Bit field size in bits for UART_AP7816B_T0_ADTI_L. */ - -/*! @brief Read current value of the UART_AP7816B_T0_ADTI_L field. */ -#define BR_UART_AP7816B_T0_ADTI_L(x) (HW_UART_AP7816B_T0(x).U) - -/*! @brief Format value for bitfield UART_AP7816B_T0_ADTI_L. */ -#define BF_UART_AP7816B_T0_ADTI_L(v) ((uint8_t)((uint8_t)(v) << BP_UART_AP7816B_T0_ADTI_L) & BM_UART_AP7816B_T0_ADTI_L) - -/*! @brief Set the ADTI_L field to a new value. */ -#define BW_UART_AP7816B_T0_ADTI_L(x, v) (HW_UART_AP7816B_T0_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WP7816A_T0 - UART 7816 Wait Parameter Register A - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816A_T0 - UART 7816 Wait Parameter Register A (RW) - * - * Reset value: 0x00U - * - * The WP7816A_T0 register contains constants used in the generation of various - * wait time counters. To save register space, this register is used differently - * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816a_t0 -{ - uint8_t U; - struct _hw_uart_wp7816a_t0_bitfields - { - uint8_t WI_H : 8; /*!< [7:0] Wait Time Integer High (C7816[TTYPE] = - * 0) */ - } B; -} hw_uart_wp7816a_t0_t; - -/*! - * @name Constants and macros for entire UART_WP7816A_T0 register - */ -/*@{*/ -#define HW_UART_WP7816A_T0_ADDR(x) ((x) + 0x3CU) - -#define HW_UART_WP7816A_T0(x) (*(__IO hw_uart_wp7816a_t0_t *) HW_UART_WP7816A_T0_ADDR(x)) -#define HW_UART_WP7816A_T0_RD(x) (HW_UART_WP7816A_T0(x).U) -#define HW_UART_WP7816A_T0_WR(x, v) (HW_UART_WP7816A_T0(x).U = (v)) -#define HW_UART_WP7816A_T0_SET(x, v) (HW_UART_WP7816A_T0_WR(x, HW_UART_WP7816A_T0_RD(x) | (v))) -#define HW_UART_WP7816A_T0_CLR(x, v) (HW_UART_WP7816A_T0_WR(x, HW_UART_WP7816A_T0_RD(x) & ~(v))) -#define HW_UART_WP7816A_T0_TOG(x, v) (HW_UART_WP7816A_T0_WR(x, HW_UART_WP7816A_T0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816A_T0 bitfields - */ - -/*! - * @name Register UART_WP7816A_T0, field WI_H[7:0] (RW) - * - * Used to calculate the value used for the WT counter. This register field - * provides the most significant byte of the 16 bit Wait Time Integer field WI formed - * by {WP7816A_T0[WI_H], WP7816B_T0[WI_L]}. The value of WI = 0 is invalid and - * must not be programmed. This value is used only when C7816[TTYPE] = 0. See Wait - * time and guard time parameters. - */ -/*@{*/ -#define BP_UART_WP7816A_T0_WI_H (0U) /*!< Bit position for UART_WP7816A_T0_WI_H. */ -#define BM_UART_WP7816A_T0_WI_H (0xFFU) /*!< Bit mask for UART_WP7816A_T0_WI_H. */ -#define BS_UART_WP7816A_T0_WI_H (8U) /*!< Bit field size in bits for UART_WP7816A_T0_WI_H. */ - -/*! @brief Read current value of the UART_WP7816A_T0_WI_H field. */ -#define BR_UART_WP7816A_T0_WI_H(x) (HW_UART_WP7816A_T0(x).U) - -/*! @brief Format value for bitfield UART_WP7816A_T0_WI_H. */ -#define BF_UART_WP7816A_T0_WI_H(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816A_T0_WI_H) & BM_UART_WP7816A_T0_WI_H) - -/*! @brief Set the WI_H field to a new value. */ -#define BW_UART_WP7816A_T0_WI_H(x, v) (HW_UART_WP7816A_T0_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_UART_WP7816B_T0 - UART 7816 Wait Parameter Register B - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816B_T0 - UART 7816 Wait Parameter Register B (RW) - * - * Reset value: 0x14U - * - * The WP7816B_T0 register contains constants used in the generation of various - * wait time counters. To save register space, this register is used differently - * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816b_t0 -{ - uint8_t U; - struct _hw_uart_wp7816b_t0_bitfields - { - uint8_t WI_L : 8; /*!< [7:0] Wait Time Integer Low (C7816[TTYPE] = 0) - * */ - } B; -} hw_uart_wp7816b_t0_t; - -/*! - * @name Constants and macros for entire UART_WP7816B_T0 register - */ -/*@{*/ -#define HW_UART_WP7816B_T0_ADDR(x) ((x) + 0x3DU) - -#define HW_UART_WP7816B_T0(x) (*(__IO hw_uart_wp7816b_t0_t *) HW_UART_WP7816B_T0_ADDR(x)) -#define HW_UART_WP7816B_T0_RD(x) (HW_UART_WP7816B_T0(x).U) -#define HW_UART_WP7816B_T0_WR(x, v) (HW_UART_WP7816B_T0(x).U = (v)) -#define HW_UART_WP7816B_T0_SET(x, v) (HW_UART_WP7816B_T0_WR(x, HW_UART_WP7816B_T0_RD(x) | (v))) -#define HW_UART_WP7816B_T0_CLR(x, v) (HW_UART_WP7816B_T0_WR(x, HW_UART_WP7816B_T0_RD(x) & ~(v))) -#define HW_UART_WP7816B_T0_TOG(x, v) (HW_UART_WP7816B_T0_WR(x, HW_UART_WP7816B_T0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816B_T0 bitfields - */ - -/*! - * @name Register UART_WP7816B_T0, field WI_L[7:0] (RW) - * - * Used to calculate the value used for the WT counter. This register field - * provides the least significant byte of the 16 bit Wait Time Integer field WI - * formed by {WP7816A_T0[WI_H], WP7816B_T0[WI_L]} . The value of WI = 0 is invalid and - * must not be programmed. This value is used only when C7816[TTYPE] = 0. See - * Wait time and guard time parameters. - */ -/*@{*/ -#define BP_UART_WP7816B_T0_WI_L (0U) /*!< Bit position for UART_WP7816B_T0_WI_L. */ -#define BM_UART_WP7816B_T0_WI_L (0xFFU) /*!< Bit mask for UART_WP7816B_T0_WI_L. */ -#define BS_UART_WP7816B_T0_WI_L (8U) /*!< Bit field size in bits for UART_WP7816B_T0_WI_L. */ - -/*! @brief Read current value of the UART_WP7816B_T0_WI_L field. */ -#define BR_UART_WP7816B_T0_WI_L(x) (HW_UART_WP7816B_T0(x).U) - -/*! @brief Format value for bitfield UART_WP7816B_T0_WI_L. */ -#define BF_UART_WP7816B_T0_WI_L(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816B_T0_WI_L) & BM_UART_WP7816B_T0_WI_L) - -/*! @brief Set the WI_L field to a new value. */ -#define BW_UART_WP7816B_T0_WI_L(x, v) (HW_UART_WP7816B_T0_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_UART_WP7816A_T1 - UART 7816 Wait Parameter Register A - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816A_T1 - UART 7816 Wait Parameter Register A (RW) - * - * Reset value: 0x00U - * - * The WP7816A_T1 register contains constants used in the generation of various - * wait time counters. To save register space, this register is used differently - * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816a_t1 -{ - uint8_t U; - struct _hw_uart_wp7816a_t1_bitfields - { - uint8_t BWI_H : 8; /*!< [7:0] Block Wait Time Integer High - * (C7816[TTYPE] = 1) */ - } B; -} hw_uart_wp7816a_t1_t; - -/*! - * @name Constants and macros for entire UART_WP7816A_T1 register - */ -/*@{*/ -#define HW_UART_WP7816A_T1_ADDR(x) ((x) + 0x3CU) - -#define HW_UART_WP7816A_T1(x) (*(__IO hw_uart_wp7816a_t1_t *) HW_UART_WP7816A_T1_ADDR(x)) -#define HW_UART_WP7816A_T1_RD(x) (HW_UART_WP7816A_T1(x).U) -#define HW_UART_WP7816A_T1_WR(x, v) (HW_UART_WP7816A_T1(x).U = (v)) -#define HW_UART_WP7816A_T1_SET(x, v) (HW_UART_WP7816A_T1_WR(x, HW_UART_WP7816A_T1_RD(x) | (v))) -#define HW_UART_WP7816A_T1_CLR(x, v) (HW_UART_WP7816A_T1_WR(x, HW_UART_WP7816A_T1_RD(x) & ~(v))) -#define HW_UART_WP7816A_T1_TOG(x, v) (HW_UART_WP7816A_T1_WR(x, HW_UART_WP7816A_T1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816A_T1 bitfields - */ - -/*! - * @name Register UART_WP7816A_T1, field BWI_H[7:0] (RW) - * - * Used to calculate the value used for the BWT counter. This register field - * provides the most significant byte of the 16 bit Block Wait Time Integer field - * BWI formed by {WP7816A_T1[BWI_H], WP7816B_T1[BWI_L]}. The value of BWI = 0 is - * invalid and should not be programmed. This value is used only when C7816[TTYPE] - * = 1. See Wait time and guard time parameters. - */ -/*@{*/ -#define BP_UART_WP7816A_T1_BWI_H (0U) /*!< Bit position for UART_WP7816A_T1_BWI_H. */ -#define BM_UART_WP7816A_T1_BWI_H (0xFFU) /*!< Bit mask for UART_WP7816A_T1_BWI_H. */ -#define BS_UART_WP7816A_T1_BWI_H (8U) /*!< Bit field size in bits for UART_WP7816A_T1_BWI_H. */ - -/*! @brief Read current value of the UART_WP7816A_T1_BWI_H field. */ -#define BR_UART_WP7816A_T1_BWI_H(x) (HW_UART_WP7816A_T1(x).U) - -/*! @brief Format value for bitfield UART_WP7816A_T1_BWI_H. */ -#define BF_UART_WP7816A_T1_BWI_H(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816A_T1_BWI_H) & BM_UART_WP7816A_T1_BWI_H) - -/*! @brief Set the BWI_H field to a new value. */ -#define BW_UART_WP7816A_T1_BWI_H(x, v) (HW_UART_WP7816A_T1_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_UART_WP7816B_T1 - UART 7816 Wait Parameter Register B - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816B_T1 - UART 7816 Wait Parameter Register B (RW) - * - * Reset value: 0x14U - * - * The WP7816B_T1 register contains constants used in the generation of various - * wait time counters. To save register space, this register is used differently - * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816b_t1 -{ - uint8_t U; - struct _hw_uart_wp7816b_t1_bitfields - { - uint8_t BWI_L : 8; /*!< [7:0] Block Wait Time Integer Low - * (C7816[TTYPE] = 1) */ - } B; -} hw_uart_wp7816b_t1_t; - -/*! - * @name Constants and macros for entire UART_WP7816B_T1 register - */ -/*@{*/ -#define HW_UART_WP7816B_T1_ADDR(x) ((x) + 0x3DU) - -#define HW_UART_WP7816B_T1(x) (*(__IO hw_uart_wp7816b_t1_t *) HW_UART_WP7816B_T1_ADDR(x)) -#define HW_UART_WP7816B_T1_RD(x) (HW_UART_WP7816B_T1(x).U) -#define HW_UART_WP7816B_T1_WR(x, v) (HW_UART_WP7816B_T1(x).U = (v)) -#define HW_UART_WP7816B_T1_SET(x, v) (HW_UART_WP7816B_T1_WR(x, HW_UART_WP7816B_T1_RD(x) | (v))) -#define HW_UART_WP7816B_T1_CLR(x, v) (HW_UART_WP7816B_T1_WR(x, HW_UART_WP7816B_T1_RD(x) & ~(v))) -#define HW_UART_WP7816B_T1_TOG(x, v) (HW_UART_WP7816B_T1_WR(x, HW_UART_WP7816B_T1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816B_T1 bitfields - */ - -/*! - * @name Register UART_WP7816B_T1, field BWI_L[7:0] (RW) - * - * Used to calculate the value used for the BWT counter. This register field - * provides the least significant byte of the 16 bit Block Wait Time Integer field - * BWI formed by {WP7816A_T1[BWI_H], WP7816B_T1[BWI_L]}. The value of BWI = 0 is - * invalid and should not be programmed. This value is used only when C7816[TTYPE] - * = 1. See Wait time and guard time parameters. - */ -/*@{*/ -#define BP_UART_WP7816B_T1_BWI_L (0U) /*!< Bit position for UART_WP7816B_T1_BWI_L. */ -#define BM_UART_WP7816B_T1_BWI_L (0xFFU) /*!< Bit mask for UART_WP7816B_T1_BWI_L. */ -#define BS_UART_WP7816B_T1_BWI_L (8U) /*!< Bit field size in bits for UART_WP7816B_T1_BWI_L. */ - -/*! @brief Read current value of the UART_WP7816B_T1_BWI_L field. */ -#define BR_UART_WP7816B_T1_BWI_L(x) (HW_UART_WP7816B_T1(x).U) - -/*! @brief Format value for bitfield UART_WP7816B_T1_BWI_L. */ -#define BF_UART_WP7816B_T1_BWI_L(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816B_T1_BWI_L) & BM_UART_WP7816B_T1_BWI_L) - -/*! @brief Set the BWI_L field to a new value. */ -#define BW_UART_WP7816B_T1_BWI_L(x, v) (HW_UART_WP7816B_T1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WGP7816_T1 - UART 7816 Wait and Guard Parameter Register (RW) - * - * Reset value: 0x06U - * - * The WGP7816_T1 register contains constants used in the generation of various - * wait and guard timer counters. This register may be read at any time. This - * register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wgp7816_t1 -{ - uint8_t U; - struct _hw_uart_wgp7816_t1_bitfields - { - uint8_t BGI : 4; /*!< [3:0] Block Guard Time Integer (C7816[TTYPE] = - * 1) */ - uint8_t CWI1 : 4; /*!< [7:4] Character Wait Time Integer 1 - * (C7816[TTYPE] = 1) */ - } B; -} hw_uart_wgp7816_t1_t; - -/*! - * @name Constants and macros for entire UART_WGP7816_T1 register - */ -/*@{*/ -#define HW_UART_WGP7816_T1_ADDR(x) ((x) + 0x3EU) - -#define HW_UART_WGP7816_T1(x) (*(__IO hw_uart_wgp7816_t1_t *) HW_UART_WGP7816_T1_ADDR(x)) -#define HW_UART_WGP7816_T1_RD(x) (HW_UART_WGP7816_T1(x).U) -#define HW_UART_WGP7816_T1_WR(x, v) (HW_UART_WGP7816_T1(x).U = (v)) -#define HW_UART_WGP7816_T1_SET(x, v) (HW_UART_WGP7816_T1_WR(x, HW_UART_WGP7816_T1_RD(x) | (v))) -#define HW_UART_WGP7816_T1_CLR(x, v) (HW_UART_WGP7816_T1_WR(x, HW_UART_WGP7816_T1_RD(x) & ~(v))) -#define HW_UART_WGP7816_T1_TOG(x, v) (HW_UART_WGP7816_T1_WR(x, HW_UART_WGP7816_T1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WGP7816_T1 bitfields - */ - -/*! - * @name Register UART_WGP7816_T1, field BGI[3:0] (RW) - * - * Used to calculate the value used for the BGT counter. It represent a value - * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time - * and guard time parameters . - */ -/*@{*/ -#define BP_UART_WGP7816_T1_BGI (0U) /*!< Bit position for UART_WGP7816_T1_BGI. */ -#define BM_UART_WGP7816_T1_BGI (0x0FU) /*!< Bit mask for UART_WGP7816_T1_BGI. */ -#define BS_UART_WGP7816_T1_BGI (4U) /*!< Bit field size in bits for UART_WGP7816_T1_BGI. */ - -/*! @brief Read current value of the UART_WGP7816_T1_BGI field. */ -#define BR_UART_WGP7816_T1_BGI(x) (HW_UART_WGP7816_T1(x).B.BGI) - -/*! @brief Format value for bitfield UART_WGP7816_T1_BGI. */ -#define BF_UART_WGP7816_T1_BGI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WGP7816_T1_BGI) & BM_UART_WGP7816_T1_BGI) - -/*! @brief Set the BGI field to a new value. */ -#define BW_UART_WGP7816_T1_BGI(x, v) (HW_UART_WGP7816_T1_WR(x, (HW_UART_WGP7816_T1_RD(x) & ~BM_UART_WGP7816_T1_BGI) | BF_UART_WGP7816_T1_BGI(v))) -/*@}*/ - -/*! - * @name Register UART_WGP7816_T1, field CWI1[7:4] (RW) - * - * Used to calculate the value used for the CWT counter. It represents a value - * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time - * and guard time parameters . - */ -/*@{*/ -#define BP_UART_WGP7816_T1_CWI1 (4U) /*!< Bit position for UART_WGP7816_T1_CWI1. */ -#define BM_UART_WGP7816_T1_CWI1 (0xF0U) /*!< Bit mask for UART_WGP7816_T1_CWI1. */ -#define BS_UART_WGP7816_T1_CWI1 (4U) /*!< Bit field size in bits for UART_WGP7816_T1_CWI1. */ - -/*! @brief Read current value of the UART_WGP7816_T1_CWI1 field. */ -#define BR_UART_WGP7816_T1_CWI1(x) (HW_UART_WGP7816_T1(x).B.CWI1) - -/*! @brief Format value for bitfield UART_WGP7816_T1_CWI1. */ -#define BF_UART_WGP7816_T1_CWI1(v) ((uint8_t)((uint8_t)(v) << BP_UART_WGP7816_T1_CWI1) & BM_UART_WGP7816_T1_CWI1) - -/*! @brief Set the CWI1 field to a new value. */ -#define BW_UART_WGP7816_T1_CWI1(x, v) (HW_UART_WGP7816_T1_WR(x, (HW_UART_WGP7816_T1_RD(x) & ~BM_UART_WGP7816_T1_CWI1) | BF_UART_WGP7816_T1_CWI1(v))) -/*@}*/ - -/******************************************************************************* - * HW_UART_WP7816C_T1 - UART 7816 Wait Parameter Register C - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816C_T1 - UART 7816 Wait Parameter Register C (RW) - * - * Reset value: 0x0BU - * - * The WP7816C_T1 register contains constants used in the generation of various - * wait timer counters. This register may be read at any time. This register must - * be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816c_t1 -{ - uint8_t U; - struct _hw_uart_wp7816c_t1_bitfields - { - uint8_t CWI2 : 5; /*!< [4:0] Character Wait Time Integer 2 - * (C7816[TTYPE] = 1) */ - uint8_t RESERVED0 : 3; /*!< [7:5] */ - } B; -} hw_uart_wp7816c_t1_t; - -/*! - * @name Constants and macros for entire UART_WP7816C_T1 register - */ -/*@{*/ -#define HW_UART_WP7816C_T1_ADDR(x) ((x) + 0x3FU) - -#define HW_UART_WP7816C_T1(x) (*(__IO hw_uart_wp7816c_t1_t *) HW_UART_WP7816C_T1_ADDR(x)) -#define HW_UART_WP7816C_T1_RD(x) (HW_UART_WP7816C_T1(x).U) -#define HW_UART_WP7816C_T1_WR(x, v) (HW_UART_WP7816C_T1(x).U = (v)) -#define HW_UART_WP7816C_T1_SET(x, v) (HW_UART_WP7816C_T1_WR(x, HW_UART_WP7816C_T1_RD(x) | (v))) -#define HW_UART_WP7816C_T1_CLR(x, v) (HW_UART_WP7816C_T1_WR(x, HW_UART_WP7816C_T1_RD(x) & ~(v))) -#define HW_UART_WP7816C_T1_TOG(x, v) (HW_UART_WP7816C_T1_WR(x, HW_UART_WP7816C_T1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816C_T1 bitfields - */ - -/*! - * @name Register UART_WP7816C_T1, field CWI2[4:0] (RW) - * - * Used to calculate the value used for the CWT counter. It represents a value - * between 0 and 31. This value is used only when C7816[TTYPE] = 1. See Wait time - * and guard time parameters . - */ -/*@{*/ -#define BP_UART_WP7816C_T1_CWI2 (0U) /*!< Bit position for UART_WP7816C_T1_CWI2. */ -#define BM_UART_WP7816C_T1_CWI2 (0x1FU) /*!< Bit mask for UART_WP7816C_T1_CWI2. */ -#define BS_UART_WP7816C_T1_CWI2 (5U) /*!< Bit field size in bits for UART_WP7816C_T1_CWI2. */ - -/*! @brief Read current value of the UART_WP7816C_T1_CWI2 field. */ -#define BR_UART_WP7816C_T1_CWI2(x) (HW_UART_WP7816C_T1(x).B.CWI2) - -/*! @brief Format value for bitfield UART_WP7816C_T1_CWI2. */ -#define BF_UART_WP7816C_T1_CWI2(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816C_T1_CWI2) & BM_UART_WP7816C_T1_CWI2) - -/*! @brief Set the CWI2 field to a new value. */ -#define BW_UART_WP7816C_T1_CWI2(x, v) (HW_UART_WP7816C_T1_WR(x, (HW_UART_WP7816C_T1_RD(x) & ~BM_UART_WP7816C_T1_CWI2) | BF_UART_WP7816C_T1_CWI2(v))) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_uart_t - module struct - ******************************************************************************/ -/*! - * @brief All UART module registers. - */ -#pragma pack(1) -typedef struct _hw_uart -{ - __IO hw_uart_bdh_t BDH; /*!< [0x0] UART Baud Rate Registers: High */ - __IO hw_uart_bdl_t BDL; /*!< [0x1] UART Baud Rate Registers: Low */ - __IO hw_uart_c1_t C1; /*!< [0x2] UART Control Register 1 */ - __IO hw_uart_c2_t C2; /*!< [0x3] UART Control Register 2 */ - __I hw_uart_s1_t S1; /*!< [0x4] UART Status Register 1 */ - __IO hw_uart_s2_t S2; /*!< [0x5] UART Status Register 2 */ - __IO hw_uart_c3_t C3; /*!< [0x6] UART Control Register 3 */ - __IO hw_uart_d_t D; /*!< [0x7] UART Data Register */ - __IO hw_uart_ma1_t MA1; /*!< [0x8] UART Match Address Registers 1 */ - __IO hw_uart_ma2_t MA2; /*!< [0x9] UART Match Address Registers 2 */ - __IO hw_uart_c4_t C4; /*!< [0xA] UART Control Register 4 */ - __IO hw_uart_c5_t C5; /*!< [0xB] UART Control Register 5 */ - __I hw_uart_ed_t ED; /*!< [0xC] UART Extended Data Register */ - __IO hw_uart_modem_t MODEM; /*!< [0xD] UART Modem Register */ - __IO hw_uart_ir_t IR; /*!< [0xE] UART Infrared Register */ - uint8_t _reserved0[1]; - __IO hw_uart_pfifo_t PFIFO; /*!< [0x10] UART FIFO Parameters */ - __IO hw_uart_cfifo_t CFIFO; /*!< [0x11] UART FIFO Control Register */ - __IO hw_uart_sfifo_t SFIFO; /*!< [0x12] UART FIFO Status Register */ - __IO hw_uart_twfifo_t TWFIFO; /*!< [0x13] UART FIFO Transmit Watermark */ - __I hw_uart_tcfifo_t TCFIFO; /*!< [0x14] UART FIFO Transmit Count */ - __IO hw_uart_rwfifo_t RWFIFO; /*!< [0x15] UART FIFO Receive Watermark */ - __I hw_uart_rcfifo_t RCFIFO; /*!< [0x16] UART FIFO Receive Count */ - uint8_t _reserved1[1]; - __IO hw_uart_c7816_t C7816; /*!< [0x18] UART 7816 Control Register */ - __IO hw_uart_ie7816_t IE7816; /*!< [0x19] UART 7816 Interrupt Enable Register */ - __IO hw_uart_is7816_t IS7816; /*!< [0x1A] UART 7816 Interrupt Status Register */ - __IO hw_uart_wp7816_t WP7816; /*!< [0x1B] UART 7816 Wait Parameter Register */ - __IO hw_uart_wn7816_t WN7816; /*!< [0x1C] UART 7816 Wait N Register */ - __IO hw_uart_wf7816_t WF7816; /*!< [0x1D] UART 7816 Wait FD Register */ - __IO hw_uart_et7816_t ET7816; /*!< [0x1E] UART 7816 Error Threshold Register */ - __IO hw_uart_tl7816_t TL7816; /*!< [0x1F] UART 7816 Transmit Length Register */ - uint8_t _reserved2[26]; - __IO hw_uart_ap7816a_t0_t AP7816A_T0; /*!< [0x3A] UART 7816 ATR Duration Timer Register A */ - __IO hw_uart_ap7816b_t0_t AP7816B_T0; /*!< [0x3B] UART 7816 ATR Duration Timer Register B */ - union { - struct { - __IO hw_uart_wp7816a_t0_t WP7816A_T0; /*!< [0x3C] UART 7816 Wait Parameter Register A */ - __IO hw_uart_wp7816b_t0_t WP7816B_T0; /*!< [0x3D] UART 7816 Wait Parameter Register B */ - } TYPE0; - struct { - __IO hw_uart_wp7816a_t1_t WP7816A_T1; /*!< [0x3C] UART 7816 Wait Parameter Register A */ - __IO hw_uart_wp7816b_t1_t WP7816B_T1; /*!< [0x3D] UART 7816 Wait Parameter Register B */ - } TYPE1; - }; - __IO hw_uart_wgp7816_t1_t WGP7816_T1; /*!< [0x3E] UART 7816 Wait and Guard Parameter Register */ - __IO hw_uart_wp7816c_t1_t WP7816C_T1; /*!< [0x3F] UART 7816 Wait Parameter Register C */ -} hw_uart_t; -#pragma pack() - -/*! @brief Macro to access all UART registers. */ -/*! @param x UART module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_UART(UART0_BASE). */ -#define HW_UART(x) (*(hw_uart_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_UART_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h deleted file mode 100644 index c02b4a02a36..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h +++ /dev/null @@ -1,3804 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_USB_REGISTERS_H__ -#define __HW_USB_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 USB - * - * Universal Serial Bus, OTG Capable Controller - * - * Registers defined in this header file: - * - HW_USB_PERID - Peripheral ID register - * - HW_USB_IDCOMP - Peripheral ID Complement register - * - HW_USB_REV - Peripheral Revision register - * - HW_USB_ADDINFO - Peripheral Additional Info register - * - HW_USB_OTGISTAT - OTG Interrupt Status register - * - HW_USB_OTGICR - OTG Interrupt Control register - * - HW_USB_OTGSTAT - OTG Status register - * - HW_USB_OTGCTL - OTG Control register - * - HW_USB_ISTAT - Interrupt Status register - * - HW_USB_INTEN - Interrupt Enable register - * - HW_USB_ERRSTAT - Error Interrupt Status register - * - HW_USB_ERREN - Error Interrupt Enable register - * - HW_USB_STAT - Status register - * - HW_USB_CTL - Control register - * - HW_USB_ADDR - Address register - * - HW_USB_BDTPAGE1 - BDT Page register 1 - * - HW_USB_FRMNUML - Frame Number register Low - * - HW_USB_FRMNUMH - Frame Number register High - * - HW_USB_TOKEN - Token register - * - HW_USB_SOFTHLD - SOF Threshold register - * - HW_USB_BDTPAGE2 - BDT Page Register 2 - * - HW_USB_BDTPAGE3 - BDT Page Register 3 - * - HW_USB_ENDPTn - Endpoint Control register - * - HW_USB_USBCTRL - USB Control register - * - HW_USB_OBSERVE - USB OTG Observe register - * - HW_USB_CONTROL - USB OTG Control register - * - HW_USB_USBTRC0 - USB Transceiver Control register 0 - * - HW_USB_USBFRMADJUST - Frame Adjust Register - * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control - * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register - * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status - * - * - hw_usb_t - Struct containing all module registers. - */ - -#define HW_USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */ - -/******************************************************************************* - * HW_USB_PERID - Peripheral ID register - ******************************************************************************/ - -/*! - * @brief HW_USB_PERID - Peripheral ID register (RO) - * - * Reset value: 0x04U - * - * Reads back the value of 0x04. This value is defined for the USB peripheral. - */ -typedef union _hw_usb_perid -{ - uint8_t U; - struct _hw_usb_perid_bitfields - { - uint8_t ID : 6; /*!< [5:0] Peripheral Identification */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_usb_perid_t; - -/*! - * @name Constants and macros for entire USB_PERID register - */ -/*@{*/ -#define HW_USB_PERID_ADDR(x) ((x) + 0x0U) - -#define HW_USB_PERID(x) (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR(x)) -#define HW_USB_PERID_RD(x) (HW_USB_PERID(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_PERID bitfields - */ - -/*! - * @name Register USB_PERID, field ID[5:0] (RO) - * - * This field always reads 0x4h. - */ -/*@{*/ -#define BP_USB_PERID_ID (0U) /*!< Bit position for USB_PERID_ID. */ -#define BM_USB_PERID_ID (0x3FU) /*!< Bit mask for USB_PERID_ID. */ -#define BS_USB_PERID_ID (6U) /*!< Bit field size in bits for USB_PERID_ID. */ - -/*! @brief Read current value of the USB_PERID_ID field. */ -#define BR_USB_PERID_ID(x) (HW_USB_PERID(x).B.ID) -/*@}*/ - -/******************************************************************************* - * HW_USB_IDCOMP - Peripheral ID Complement register - ******************************************************************************/ - -/*! - * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO) - * - * Reset value: 0xFBU - * - * Reads back the complement of the Peripheral ID register. For the USB - * peripheral, the value is 0xFB. - */ -typedef union _hw_usb_idcomp -{ - uint8_t U; - struct _hw_usb_idcomp_bitfields - { - uint8_t NID : 6; /*!< [5:0] */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_usb_idcomp_t; - -/*! - * @name Constants and macros for entire USB_IDCOMP register - */ -/*@{*/ -#define HW_USB_IDCOMP_ADDR(x) ((x) + 0x4U) - -#define HW_USB_IDCOMP(x) (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR(x)) -#define HW_USB_IDCOMP_RD(x) (HW_USB_IDCOMP(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_IDCOMP bitfields - */ - -/*! - * @name Register USB_IDCOMP, field NID[5:0] (RO) - * - * Ones' complement of PERID[ID]. bits. - */ -/*@{*/ -#define BP_USB_IDCOMP_NID (0U) /*!< Bit position for USB_IDCOMP_NID. */ -#define BM_USB_IDCOMP_NID (0x3FU) /*!< Bit mask for USB_IDCOMP_NID. */ -#define BS_USB_IDCOMP_NID (6U) /*!< Bit field size in bits for USB_IDCOMP_NID. */ - -/*! @brief Read current value of the USB_IDCOMP_NID field. */ -#define BR_USB_IDCOMP_NID(x) (HW_USB_IDCOMP(x).B.NID) -/*@}*/ - -/******************************************************************************* - * HW_USB_REV - Peripheral Revision register - ******************************************************************************/ - -/*! - * @brief HW_USB_REV - Peripheral Revision register (RO) - * - * Reset value: 0x33U - * - * Contains the revision number of the USB module. - */ -typedef union _hw_usb_rev -{ - uint8_t U; - struct _hw_usb_rev_bitfields - { - uint8_t REV : 8; /*!< [7:0] Revision */ - } B; -} hw_usb_rev_t; - -/*! - * @name Constants and macros for entire USB_REV register - */ -/*@{*/ -#define HW_USB_REV_ADDR(x) ((x) + 0x8U) - -#define HW_USB_REV(x) (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR(x)) -#define HW_USB_REV_RD(x) (HW_USB_REV(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_REV bitfields - */ - -/*! - * @name Register USB_REV, field REV[7:0] (RO) - * - * Indicates the revision number of the USB Core. - */ -/*@{*/ -#define BP_USB_REV_REV (0U) /*!< Bit position for USB_REV_REV. */ -#define BM_USB_REV_REV (0xFFU) /*!< Bit mask for USB_REV_REV. */ -#define BS_USB_REV_REV (8U) /*!< Bit field size in bits for USB_REV_REV. */ - -/*! @brief Read current value of the USB_REV_REV field. */ -#define BR_USB_REV_REV(x) (HW_USB_REV(x).U) -/*@}*/ - -/******************************************************************************* - * HW_USB_ADDINFO - Peripheral Additional Info register - ******************************************************************************/ - -/*! - * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO) - * - * Reset value: 0x01U - * - * Reads back the value of the Host Enable bit. - */ -typedef union _hw_usb_addinfo -{ - uint8_t U; - struct _hw_usb_addinfo_bitfields - { - uint8_t IEHOST : 1; /*!< [0] */ - uint8_t RESERVED0 : 7; /*!< [7:1] */ - } B; -} hw_usb_addinfo_t; - -/*! - * @name Constants and macros for entire USB_ADDINFO register - */ -/*@{*/ -#define HW_USB_ADDINFO_ADDR(x) ((x) + 0xCU) - -#define HW_USB_ADDINFO(x) (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR(x)) -#define HW_USB_ADDINFO_RD(x) (HW_USB_ADDINFO(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_ADDINFO bitfields - */ - -/*! - * @name Register USB_ADDINFO, field IEHOST[0] (RO) - * - * This bit is set if host mode is enabled. - */ -/*@{*/ -#define BP_USB_ADDINFO_IEHOST (0U) /*!< Bit position for USB_ADDINFO_IEHOST. */ -#define BM_USB_ADDINFO_IEHOST (0x01U) /*!< Bit mask for USB_ADDINFO_IEHOST. */ -#define BS_USB_ADDINFO_IEHOST (1U) /*!< Bit field size in bits for USB_ADDINFO_IEHOST. */ - -/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */ -#define BR_USB_ADDINFO_IEHOST(x) (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR(x), BP_USB_ADDINFO_IEHOST)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGISTAT - OTG Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW) - * - * Reset value: 0x00U - * - * Records changes of the ID sense and VBUS signals. Software can read this - * register to determine the event that triggers interrupt. Only bits that have - * changed since the last software read are set. Writing a one to a bit clears the - * associated interrupt. - */ -typedef union _hw_usb_otgistat -{ - uint8_t U; - struct _hw_usb_otgistat_bitfields - { - uint8_t AVBUSCHG : 1; /*!< [0] */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t B_SESS_CHG : 1; /*!< [2] */ - uint8_t SESSVLDCHG : 1; /*!< [3] */ - uint8_t RESERVED1 : 1; /*!< [4] */ - uint8_t LINE_STATE_CHG : 1; /*!< [5] */ - uint8_t ONEMSEC : 1; /*!< [6] */ - uint8_t IDCHG : 1; /*!< [7] */ - } B; -} hw_usb_otgistat_t; - -/*! - * @name Constants and macros for entire USB_OTGISTAT register - */ -/*@{*/ -#define HW_USB_OTGISTAT_ADDR(x) ((x) + 0x10U) - -#define HW_USB_OTGISTAT(x) (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR(x)) -#define HW_USB_OTGISTAT_RD(x) (HW_USB_OTGISTAT(x).U) -#define HW_USB_OTGISTAT_WR(x, v) (HW_USB_OTGISTAT(x).U = (v)) -#define HW_USB_OTGISTAT_SET(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) | (v))) -#define HW_USB_OTGISTAT_CLR(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) & ~(v))) -#define HW_USB_OTGISTAT_TOG(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGISTAT bitfields - */ - -/*! - * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW) - * - * This bit is set when a change in VBUS is detected on an A device. - */ -/*@{*/ -#define BP_USB_OTGISTAT_AVBUSCHG (0U) /*!< Bit position for USB_OTGISTAT_AVBUSCHG. */ -#define BM_USB_OTGISTAT_AVBUSCHG (0x01U) /*!< Bit mask for USB_OTGISTAT_AVBUSCHG. */ -#define BS_USB_OTGISTAT_AVBUSCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */ -#define BR_USB_OTGISTAT_AVBUSCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG. */ -#define BF_USB_OTGISTAT_AVBUSCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_AVBUSCHG) & BM_USB_OTGISTAT_AVBUSCHG) - -/*! @brief Set the AVBUSCHG field to a new value. */ -#define BW_USB_OTGISTAT_AVBUSCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW) - * - * This bit is set when a change in VBUS is detected on a B device. - */ -/*@{*/ -#define BP_USB_OTGISTAT_B_SESS_CHG (2U) /*!< Bit position for USB_OTGISTAT_B_SESS_CHG. */ -#define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) /*!< Bit mask for USB_OTGISTAT_B_SESS_CHG. */ -#define BS_USB_OTGISTAT_B_SESS_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */ -#define BR_USB_OTGISTAT_B_SESS_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG. */ -#define BF_USB_OTGISTAT_B_SESS_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_B_SESS_CHG) & BM_USB_OTGISTAT_B_SESS_CHG) - -/*! @brief Set the B_SESS_CHG field to a new value. */ -#define BW_USB_OTGISTAT_B_SESS_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW) - * - * This bit is set when a change in VBUS is detected indicating a session valid - * or a session no longer valid. - */ -/*@{*/ -#define BP_USB_OTGISTAT_SESSVLDCHG (3U) /*!< Bit position for USB_OTGISTAT_SESSVLDCHG. */ -#define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) /*!< Bit mask for USB_OTGISTAT_SESSVLDCHG. */ -#define BS_USB_OTGISTAT_SESSVLDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */ -#define BR_USB_OTGISTAT_SESSVLDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG. */ -#define BF_USB_OTGISTAT_SESSVLDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_SESSVLDCHG) & BM_USB_OTGISTAT_SESSVLDCHG) - -/*! @brief Set the SESSVLDCHG field to a new value. */ -#define BW_USB_OTGISTAT_SESSVLDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW) - * - * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) - * are stable without change for 1 millisecond, and the value of the line state - * is different from the last time when the line state was stable. It is set on - * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state. - * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt - * can be used in detecting Reset, Resume, Connect, and Data Line Pulse - * signaling. - */ -/*@{*/ -#define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) /*!< Bit position for USB_OTGISTAT_LINE_STATE_CHG. */ -#define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) /*!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG. */ -#define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */ -#define BR_USB_OTGISTAT_LINE_STATE_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG. */ -#define BF_USB_OTGISTAT_LINE_STATE_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_LINE_STATE_CHG) & BM_USB_OTGISTAT_LINE_STATE_CHG) - -/*! @brief Set the LINE_STATE_CHG field to a new value. */ -#define BW_USB_OTGISTAT_LINE_STATE_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW) - * - * This bit is set when the 1 millisecond timer expires. This bit stays asserted - * until cleared by software. The interrupt must be serviced every millisecond - * to avoid losing 1msec counts. - */ -/*@{*/ -#define BP_USB_OTGISTAT_ONEMSEC (6U) /*!< Bit position for USB_OTGISTAT_ONEMSEC. */ -#define BM_USB_OTGISTAT_ONEMSEC (0x40U) /*!< Bit mask for USB_OTGISTAT_ONEMSEC. */ -#define BS_USB_OTGISTAT_ONEMSEC (1U) /*!< Bit field size in bits for USB_OTGISTAT_ONEMSEC. */ - -/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */ -#define BR_USB_OTGISTAT_ONEMSEC(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC)) - -/*! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC. */ -#define BF_USB_OTGISTAT_ONEMSEC(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_ONEMSEC) & BM_USB_OTGISTAT_ONEMSEC) - -/*! @brief Set the ONEMSEC field to a new value. */ -#define BW_USB_OTGISTAT_ONEMSEC(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field IDCHG[7] (RW) - * - * This bit is set when a change in the ID Signal from the USB connector is - * sensed. - */ -/*@{*/ -#define BP_USB_OTGISTAT_IDCHG (7U) /*!< Bit position for USB_OTGISTAT_IDCHG. */ -#define BM_USB_OTGISTAT_IDCHG (0x80U) /*!< Bit mask for USB_OTGISTAT_IDCHG. */ -#define BS_USB_OTGISTAT_IDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_IDCHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */ -#define BR_USB_OTGISTAT_IDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_IDCHG. */ -#define BF_USB_OTGISTAT_IDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_IDCHG) & BM_USB_OTGISTAT_IDCHG) - -/*! @brief Set the IDCHG field to a new value. */ -#define BW_USB_OTGISTAT_IDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGICR - OTG Interrupt Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW) - * - * Reset value: 0x00U - * - * Enables the corresponding interrupt status bits defined in the OTG Interrupt - * Status Register. - */ -typedef union _hw_usb_otgicr -{ - uint8_t U; - struct _hw_usb_otgicr_bitfields - { - uint8_t AVBUSEN : 1; /*!< [0] A VBUS Valid Interrupt Enable */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t BSESSEN : 1; /*!< [2] B Session END Interrupt Enable */ - uint8_t SESSVLDEN : 1; /*!< [3] Session Valid Interrupt Enable */ - uint8_t RESERVED1 : 1; /*!< [4] */ - uint8_t LINESTATEEN : 1; /*!< [5] Line State Change Interrupt Enable - * */ - uint8_t ONEMSECEN : 1; /*!< [6] One Millisecond Interrupt Enable */ - uint8_t IDEN : 1; /*!< [7] ID Interrupt Enable */ - } B; -} hw_usb_otgicr_t; - -/*! - * @name Constants and macros for entire USB_OTGICR register - */ -/*@{*/ -#define HW_USB_OTGICR_ADDR(x) ((x) + 0x14U) - -#define HW_USB_OTGICR(x) (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR(x)) -#define HW_USB_OTGICR_RD(x) (HW_USB_OTGICR(x).U) -#define HW_USB_OTGICR_WR(x, v) (HW_USB_OTGICR(x).U = (v)) -#define HW_USB_OTGICR_SET(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) | (v))) -#define HW_USB_OTGICR_CLR(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) & ~(v))) -#define HW_USB_OTGICR_TOG(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGICR bitfields - */ - -/*! - * @name Register USB_OTGICR, field AVBUSEN[0] (RW) - * - * Values: - * - 0 - Disables the AVBUSCHG interrupt. - * - 1 - Enables the AVBUSCHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_AVBUSEN (0U) /*!< Bit position for USB_OTGICR_AVBUSEN. */ -#define BM_USB_OTGICR_AVBUSEN (0x01U) /*!< Bit mask for USB_OTGICR_AVBUSEN. */ -#define BS_USB_OTGICR_AVBUSEN (1U) /*!< Bit field size in bits for USB_OTGICR_AVBUSEN. */ - -/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */ -#define BR_USB_OTGICR_AVBUSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN)) - -/*! @brief Format value for bitfield USB_OTGICR_AVBUSEN. */ -#define BF_USB_OTGICR_AVBUSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_AVBUSEN) & BM_USB_OTGICR_AVBUSEN) - -/*! @brief Set the AVBUSEN field to a new value. */ -#define BW_USB_OTGICR_AVBUSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field BSESSEN[2] (RW) - * - * Values: - * - 0 - Disables the B_SESS_CHG interrupt. - * - 1 - Enables the B_SESS_CHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_BSESSEN (2U) /*!< Bit position for USB_OTGICR_BSESSEN. */ -#define BM_USB_OTGICR_BSESSEN (0x04U) /*!< Bit mask for USB_OTGICR_BSESSEN. */ -#define BS_USB_OTGICR_BSESSEN (1U) /*!< Bit field size in bits for USB_OTGICR_BSESSEN. */ - -/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */ -#define BR_USB_OTGICR_BSESSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN)) - -/*! @brief Format value for bitfield USB_OTGICR_BSESSEN. */ -#define BF_USB_OTGICR_BSESSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_BSESSEN) & BM_USB_OTGICR_BSESSEN) - -/*! @brief Set the BSESSEN field to a new value. */ -#define BW_USB_OTGICR_BSESSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field SESSVLDEN[3] (RW) - * - * Values: - * - 0 - Disables the SESSVLDCHG interrupt. - * - 1 - Enables the SESSVLDCHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_SESSVLDEN (3U) /*!< Bit position for USB_OTGICR_SESSVLDEN. */ -#define BM_USB_OTGICR_SESSVLDEN (0x08U) /*!< Bit mask for USB_OTGICR_SESSVLDEN. */ -#define BS_USB_OTGICR_SESSVLDEN (1U) /*!< Bit field size in bits for USB_OTGICR_SESSVLDEN. */ - -/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */ -#define BR_USB_OTGICR_SESSVLDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN)) - -/*! @brief Format value for bitfield USB_OTGICR_SESSVLDEN. */ -#define BF_USB_OTGICR_SESSVLDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_SESSVLDEN) & BM_USB_OTGICR_SESSVLDEN) - -/*! @brief Set the SESSVLDEN field to a new value. */ -#define BW_USB_OTGICR_SESSVLDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field LINESTATEEN[5] (RW) - * - * Values: - * - 0 - Disables the LINE_STAT_CHG interrupt. - * - 1 - Enables the LINE_STAT_CHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_LINESTATEEN (5U) /*!< Bit position for USB_OTGICR_LINESTATEEN. */ -#define BM_USB_OTGICR_LINESTATEEN (0x20U) /*!< Bit mask for USB_OTGICR_LINESTATEEN. */ -#define BS_USB_OTGICR_LINESTATEEN (1U) /*!< Bit field size in bits for USB_OTGICR_LINESTATEEN. */ - -/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */ -#define BR_USB_OTGICR_LINESTATEEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN)) - -/*! @brief Format value for bitfield USB_OTGICR_LINESTATEEN. */ -#define BF_USB_OTGICR_LINESTATEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_LINESTATEEN) & BM_USB_OTGICR_LINESTATEEN) - -/*! @brief Set the LINESTATEEN field to a new value. */ -#define BW_USB_OTGICR_LINESTATEEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field ONEMSECEN[6] (RW) - * - * Values: - * - 0 - Diables the 1ms timer interrupt. - * - 1 - Enables the 1ms timer interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_ONEMSECEN (6U) /*!< Bit position for USB_OTGICR_ONEMSECEN. */ -#define BM_USB_OTGICR_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGICR_ONEMSECEN. */ -#define BS_USB_OTGICR_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGICR_ONEMSECEN. */ - -/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */ -#define BR_USB_OTGICR_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN)) - -/*! @brief Format value for bitfield USB_OTGICR_ONEMSECEN. */ -#define BF_USB_OTGICR_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_ONEMSECEN) & BM_USB_OTGICR_ONEMSECEN) - -/*! @brief Set the ONEMSECEN field to a new value. */ -#define BW_USB_OTGICR_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field IDEN[7] (RW) - * - * Values: - * - 0 - The ID interrupt is disabled - * - 1 - The ID interrupt is enabled - */ -/*@{*/ -#define BP_USB_OTGICR_IDEN (7U) /*!< Bit position for USB_OTGICR_IDEN. */ -#define BM_USB_OTGICR_IDEN (0x80U) /*!< Bit mask for USB_OTGICR_IDEN. */ -#define BS_USB_OTGICR_IDEN (1U) /*!< Bit field size in bits for USB_OTGICR_IDEN. */ - -/*! @brief Read current value of the USB_OTGICR_IDEN field. */ -#define BR_USB_OTGICR_IDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN)) - -/*! @brief Format value for bitfield USB_OTGICR_IDEN. */ -#define BF_USB_OTGICR_IDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_IDEN) & BM_USB_OTGICR_IDEN) - -/*! @brief Set the IDEN field to a new value. */ -#define BW_USB_OTGICR_IDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGSTAT - OTG Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGSTAT - OTG Status register (RW) - * - * Reset value: 0x00U - * - * Displays the actual value from the external comparator outputs of the ID pin - * and VBUS. - */ -typedef union _hw_usb_otgstat -{ - uint8_t U; - struct _hw_usb_otgstat_bitfields - { - uint8_t AVBUSVLD : 1; /*!< [0] A VBUS Valid */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t BSESSEND : 1; /*!< [2] B Session End */ - uint8_t SESS_VLD : 1; /*!< [3] Session Valid */ - uint8_t RESERVED1 : 1; /*!< [4] */ - uint8_t LINESTATESTABLE : 1; /*!< [5] */ - uint8_t ONEMSECEN : 1; /*!< [6] */ - uint8_t ID : 1; /*!< [7] */ - } B; -} hw_usb_otgstat_t; - -/*! - * @name Constants and macros for entire USB_OTGSTAT register - */ -/*@{*/ -#define HW_USB_OTGSTAT_ADDR(x) ((x) + 0x18U) - -#define HW_USB_OTGSTAT(x) (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR(x)) -#define HW_USB_OTGSTAT_RD(x) (HW_USB_OTGSTAT(x).U) -#define HW_USB_OTGSTAT_WR(x, v) (HW_USB_OTGSTAT(x).U = (v)) -#define HW_USB_OTGSTAT_SET(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) | (v))) -#define HW_USB_OTGSTAT_CLR(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) & ~(v))) -#define HW_USB_OTGSTAT_TOG(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGSTAT bitfields - */ - -/*! - * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW) - * - * Values: - * - 0 - The VBUS voltage is below the A VBUS Valid threshold. - * - 1 - The VBUS voltage is above the A VBUS Valid threshold. - */ -/*@{*/ -#define BP_USB_OTGSTAT_AVBUSVLD (0U) /*!< Bit position for USB_OTGSTAT_AVBUSVLD. */ -#define BM_USB_OTGSTAT_AVBUSVLD (0x01U) /*!< Bit mask for USB_OTGSTAT_AVBUSVLD. */ -#define BS_USB_OTGSTAT_AVBUSVLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD. */ - -/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */ -#define BR_USB_OTGSTAT_AVBUSVLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD)) - -/*! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD. */ -#define BF_USB_OTGSTAT_AVBUSVLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_AVBUSVLD) & BM_USB_OTGSTAT_AVBUSVLD) - -/*! @brief Set the AVBUSVLD field to a new value. */ -#define BW_USB_OTGSTAT_AVBUSVLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field BSESSEND[2] (RW) - * - * Values: - * - 0 - The VBUS voltage is above the B session end threshold. - * - 1 - The VBUS voltage is below the B session end threshold. - */ -/*@{*/ -#define BP_USB_OTGSTAT_BSESSEND (2U) /*!< Bit position for USB_OTGSTAT_BSESSEND. */ -#define BM_USB_OTGSTAT_BSESSEND (0x04U) /*!< Bit mask for USB_OTGSTAT_BSESSEND. */ -#define BS_USB_OTGSTAT_BSESSEND (1U) /*!< Bit field size in bits for USB_OTGSTAT_BSESSEND. */ - -/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */ -#define BR_USB_OTGSTAT_BSESSEND(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND)) - -/*! @brief Format value for bitfield USB_OTGSTAT_BSESSEND. */ -#define BF_USB_OTGSTAT_BSESSEND(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_BSESSEND) & BM_USB_OTGSTAT_BSESSEND) - -/*! @brief Set the BSESSEND field to a new value. */ -#define BW_USB_OTGSTAT_BSESSEND(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW) - * - * Values: - * - 0 - The VBUS voltage is below the B session valid threshold - * - 1 - The VBUS voltage is above the B session valid threshold. - */ -/*@{*/ -#define BP_USB_OTGSTAT_SESS_VLD (3U) /*!< Bit position for USB_OTGSTAT_SESS_VLD. */ -#define BM_USB_OTGSTAT_SESS_VLD (0x08U) /*!< Bit mask for USB_OTGSTAT_SESS_VLD. */ -#define BS_USB_OTGSTAT_SESS_VLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_SESS_VLD. */ - -/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */ -#define BR_USB_OTGSTAT_SESS_VLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD)) - -/*! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD. */ -#define BF_USB_OTGSTAT_SESS_VLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_SESS_VLD) & BM_USB_OTGSTAT_SESS_VLD) - -/*! @brief Set the SESS_VLD field to a new value. */ -#define BW_USB_OTGSTAT_SESS_VLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW) - * - * Indicates that the internal signals that control the LINE_STATE_CHG field of - * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG - * field and then read this field. If this field reads as 1, then the value of - * LINE_STATE_CHG can be considered stable. - * - * Values: - * - 0 - The LINE_STAT_CHG bit is not yet stable. - * - 1 - The LINE_STAT_CHG bit has been debounced and is stable. - */ -/*@{*/ -#define BP_USB_OTGSTAT_LINESTATESTABLE (5U) /*!< Bit position for USB_OTGSTAT_LINESTATESTABLE. */ -#define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) /*!< Bit mask for USB_OTGSTAT_LINESTATESTABLE. */ -#define BS_USB_OTGSTAT_LINESTATESTABLE (1U) /*!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE. */ - -/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */ -#define BR_USB_OTGSTAT_LINESTATESTABLE(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE)) - -/*! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE. */ -#define BF_USB_OTGSTAT_LINESTATESTABLE(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_LINESTATESTABLE) & BM_USB_OTGSTAT_LINESTATESTABLE) - -/*! @brief Set the LINESTATESTABLE field to a new value. */ -#define BW_USB_OTGSTAT_LINESTATESTABLE(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW) - * - * This bit is reserved for the 1ms count, but it is not useful to software. - */ -/*@{*/ -#define BP_USB_OTGSTAT_ONEMSECEN (6U) /*!< Bit position for USB_OTGSTAT_ONEMSECEN. */ -#define BM_USB_OTGSTAT_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGSTAT_ONEMSECEN. */ -#define BS_USB_OTGSTAT_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN. */ - -/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */ -#define BR_USB_OTGSTAT_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN)) - -/*! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN. */ -#define BF_USB_OTGSTAT_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ONEMSECEN) & BM_USB_OTGSTAT_ONEMSECEN) - -/*! @brief Set the ONEMSECEN field to a new value. */ -#define BW_USB_OTGSTAT_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field ID[7] (RW) - * - * Indicates the current state of the ID pin on the USB connector - * - * Values: - * - 0 - Indicates a Type A cable is plugged into the USB connector. - * - 1 - Indicates no cable is attached or a Type B cable is plugged into the - * USB connector. - */ -/*@{*/ -#define BP_USB_OTGSTAT_ID (7U) /*!< Bit position for USB_OTGSTAT_ID. */ -#define BM_USB_OTGSTAT_ID (0x80U) /*!< Bit mask for USB_OTGSTAT_ID. */ -#define BS_USB_OTGSTAT_ID (1U) /*!< Bit field size in bits for USB_OTGSTAT_ID. */ - -/*! @brief Read current value of the USB_OTGSTAT_ID field. */ -#define BR_USB_OTGSTAT_ID(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID)) - -/*! @brief Format value for bitfield USB_OTGSTAT_ID. */ -#define BF_USB_OTGSTAT_ID(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ID) & BM_USB_OTGSTAT_ID) - -/*! @brief Set the ID field to a new value. */ -#define BW_USB_OTGSTAT_ID(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGCTL - OTG Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGCTL - OTG Control register (RW) - * - * Reset value: 0x00U - * - * Controls the operation of VBUS and Data Line termination resistors. - */ -typedef union _hw_usb_otgctl -{ - uint8_t U; - struct _hw_usb_otgctl_bitfields - { - uint8_t RESERVED0 : 2; /*!< [1:0] */ - uint8_t OTGEN : 1; /*!< [2] On-The-Go pullup/pulldown resistor enable - * */ - uint8_t RESERVED1 : 1; /*!< [3] */ - uint8_t DMLOW : 1; /*!< [4] D- Data Line pull-down resistor enable */ - uint8_t DPLOW : 1; /*!< [5] D+ Data Line pull-down resistor enable */ - uint8_t RESERVED2 : 1; /*!< [6] */ - uint8_t DPHIGH : 1; /*!< [7] D+ Data Line pullup resistor enable */ - } B; -} hw_usb_otgctl_t; - -/*! - * @name Constants and macros for entire USB_OTGCTL register - */ -/*@{*/ -#define HW_USB_OTGCTL_ADDR(x) ((x) + 0x1CU) - -#define HW_USB_OTGCTL(x) (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR(x)) -#define HW_USB_OTGCTL_RD(x) (HW_USB_OTGCTL(x).U) -#define HW_USB_OTGCTL_WR(x, v) (HW_USB_OTGCTL(x).U = (v)) -#define HW_USB_OTGCTL_SET(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) | (v))) -#define HW_USB_OTGCTL_CLR(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) & ~(v))) -#define HW_USB_OTGCTL_TOG(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGCTL bitfields - */ - -/*! - * @name Register USB_OTGCTL, field OTGEN[2] (RW) - * - * Values: - * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then - * the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ - * and D- Data Line pull-down resistors are engaged. - * - 1 - The pull-up and pull-down controls in this register are used. - */ -/*@{*/ -#define BP_USB_OTGCTL_OTGEN (2U) /*!< Bit position for USB_OTGCTL_OTGEN. */ -#define BM_USB_OTGCTL_OTGEN (0x04U) /*!< Bit mask for USB_OTGCTL_OTGEN. */ -#define BS_USB_OTGCTL_OTGEN (1U) /*!< Bit field size in bits for USB_OTGCTL_OTGEN. */ - -/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */ -#define BR_USB_OTGCTL_OTGEN(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN)) - -/*! @brief Format value for bitfield USB_OTGCTL_OTGEN. */ -#define BF_USB_OTGCTL_OTGEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_OTGEN) & BM_USB_OTGCTL_OTGEN) - -/*! @brief Set the OTGEN field to a new value. */ -#define BW_USB_OTGCTL_OTGEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGCTL, field DMLOW[4] (RW) - * - * Values: - * - 0 - D- pulldown resistor is not enabled. - * - 1 - D- pulldown resistor is enabled. - */ -/*@{*/ -#define BP_USB_OTGCTL_DMLOW (4U) /*!< Bit position for USB_OTGCTL_DMLOW. */ -#define BM_USB_OTGCTL_DMLOW (0x10U) /*!< Bit mask for USB_OTGCTL_DMLOW. */ -#define BS_USB_OTGCTL_DMLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DMLOW. */ - -/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */ -#define BR_USB_OTGCTL_DMLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW)) - -/*! @brief Format value for bitfield USB_OTGCTL_DMLOW. */ -#define BF_USB_OTGCTL_DMLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DMLOW) & BM_USB_OTGCTL_DMLOW) - -/*! @brief Set the DMLOW field to a new value. */ -#define BW_USB_OTGCTL_DMLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGCTL, field DPLOW[5] (RW) - * - * This bit should always be enabled together with bit 4 (DMLOW) - * - * Values: - * - 0 - D+ pulldown resistor is not enabled. - * - 1 - D+ pulldown resistor is enabled. - */ -/*@{*/ -#define BP_USB_OTGCTL_DPLOW (5U) /*!< Bit position for USB_OTGCTL_DPLOW. */ -#define BM_USB_OTGCTL_DPLOW (0x20U) /*!< Bit mask for USB_OTGCTL_DPLOW. */ -#define BS_USB_OTGCTL_DPLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DPLOW. */ - -/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */ -#define BR_USB_OTGCTL_DPLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW)) - -/*! @brief Format value for bitfield USB_OTGCTL_DPLOW. */ -#define BF_USB_OTGCTL_DPLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPLOW) & BM_USB_OTGCTL_DPLOW) - -/*! @brief Set the DPLOW field to a new value. */ -#define BW_USB_OTGCTL_DPLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGCTL, field DPHIGH[7] (RW) - * - * Values: - * - 0 - D+ pullup resistor is not enabled - * - 1 - D+ pullup resistor is enabled - */ -/*@{*/ -#define BP_USB_OTGCTL_DPHIGH (7U) /*!< Bit position for USB_OTGCTL_DPHIGH. */ -#define BM_USB_OTGCTL_DPHIGH (0x80U) /*!< Bit mask for USB_OTGCTL_DPHIGH. */ -#define BS_USB_OTGCTL_DPHIGH (1U) /*!< Bit field size in bits for USB_OTGCTL_DPHIGH. */ - -/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */ -#define BR_USB_OTGCTL_DPHIGH(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH)) - -/*! @brief Format value for bitfield USB_OTGCTL_DPHIGH. */ -#define BF_USB_OTGCTL_DPHIGH(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPHIGH) & BM_USB_OTGCTL_DPHIGH) - -/*! @brief Set the DPHIGH field to a new value. */ -#define BW_USB_OTGCTL_DPHIGH(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ISTAT - Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_ISTAT - Interrupt Status register (W1C) - * - * Reset value: 0x00U - * - * Contains fields for each of the interrupt sources within the USB Module. Each - * of these fields are qualified with their respective interrupt enable bits. - * All fields of this register are logically OR'd together along with the OTG - * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the - * processor's interrupt controller. After an interrupt bit has been set it may only - * be cleared by writing a one to the respective interrupt bit. This register - * contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_istat -{ - uint8_t U; - struct _hw_usb_istat_bitfields - { - uint8_t USBRST : 1; /*!< [0] */ - uint8_t ERROR : 1; /*!< [1] */ - uint8_t SOFTOK : 1; /*!< [2] */ - uint8_t TOKDNE : 1; /*!< [3] */ - uint8_t SLEEP : 1; /*!< [4] */ - uint8_t RESUME : 1; /*!< [5] */ - uint8_t ATTACH : 1; /*!< [6] Attach Interrupt */ - uint8_t STALL : 1; /*!< [7] Stall Interrupt */ - } B; -} hw_usb_istat_t; - -/*! - * @name Constants and macros for entire USB_ISTAT register - */ -/*@{*/ -#define HW_USB_ISTAT_ADDR(x) ((x) + 0x80U) - -#define HW_USB_ISTAT(x) (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR(x)) -#define HW_USB_ISTAT_RD(x) (HW_USB_ISTAT(x).U) -#define HW_USB_ISTAT_WR(x, v) (HW_USB_ISTAT(x).U = (v)) -#define HW_USB_ISTAT_SET(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) | (v))) -#define HW_USB_ISTAT_CLR(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) & ~(v))) -#define HW_USB_ISTAT_TOG(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ISTAT bitfields - */ - -/*! - * @name Register USB_ISTAT, field USBRST[0] (W1C) - * - * This bit is set when the USB Module has decoded a valid USB reset. This - * informs the processor that it should write 0x00 into the address register and - * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5 - * microseconds. It is not asserted again until the USB reset condition has been - * removed and then reasserted. - */ -/*@{*/ -#define BP_USB_ISTAT_USBRST (0U) /*!< Bit position for USB_ISTAT_USBRST. */ -#define BM_USB_ISTAT_USBRST (0x01U) /*!< Bit mask for USB_ISTAT_USBRST. */ -#define BS_USB_ISTAT_USBRST (1U) /*!< Bit field size in bits for USB_ISTAT_USBRST. */ - -/*! @brief Read current value of the USB_ISTAT_USBRST field. */ -#define BR_USB_ISTAT_USBRST(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST)) - -/*! @brief Format value for bitfield USB_ISTAT_USBRST. */ -#define BF_USB_ISTAT_USBRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_USBRST) & BM_USB_ISTAT_USBRST) - -/*! @brief Set the USBRST field to a new value. */ -#define BW_USB_ISTAT_USBRST(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field ERROR[1] (W1C) - * - * This bit is set when any of the error conditions within Error Interrupt - * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register - * to determine the source of the error. - */ -/*@{*/ -#define BP_USB_ISTAT_ERROR (1U) /*!< Bit position for USB_ISTAT_ERROR. */ -#define BM_USB_ISTAT_ERROR (0x02U) /*!< Bit mask for USB_ISTAT_ERROR. */ -#define BS_USB_ISTAT_ERROR (1U) /*!< Bit field size in bits for USB_ISTAT_ERROR. */ - -/*! @brief Read current value of the USB_ISTAT_ERROR field. */ -#define BR_USB_ISTAT_ERROR(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR)) - -/*! @brief Format value for bitfield USB_ISTAT_ERROR. */ -#define BF_USB_ISTAT_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ERROR) & BM_USB_ISTAT_ERROR) - -/*! @brief Set the ERROR field to a new value. */ -#define BW_USB_ISTAT_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field SOFTOK[2] (W1C) - * - * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In - * Host mode this field is set when the SOF threshold is reached, so that - * software can prepare for the next SOF. - */ -/*@{*/ -#define BP_USB_ISTAT_SOFTOK (2U) /*!< Bit position for USB_ISTAT_SOFTOK. */ -#define BM_USB_ISTAT_SOFTOK (0x04U) /*!< Bit mask for USB_ISTAT_SOFTOK. */ -#define BS_USB_ISTAT_SOFTOK (1U) /*!< Bit field size in bits for USB_ISTAT_SOFTOK. */ - -/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */ -#define BR_USB_ISTAT_SOFTOK(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK)) - -/*! @brief Format value for bitfield USB_ISTAT_SOFTOK. */ -#define BF_USB_ISTAT_SOFTOK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SOFTOK) & BM_USB_ISTAT_SOFTOK) - -/*! @brief Set the SOFTOK field to a new value. */ -#define BW_USB_ISTAT_SOFTOK(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field TOKDNE[3] (W1C) - * - * This bit is set when the current token being processed has completed. The - * processor must immediately read the STATUS (STAT) register to determine the - * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes - * STAT to be cleared or the STAT holding register to be loaded into the STAT - * register. - */ -/*@{*/ -#define BP_USB_ISTAT_TOKDNE (3U) /*!< Bit position for USB_ISTAT_TOKDNE. */ -#define BM_USB_ISTAT_TOKDNE (0x08U) /*!< Bit mask for USB_ISTAT_TOKDNE. */ -#define BS_USB_ISTAT_TOKDNE (1U) /*!< Bit field size in bits for USB_ISTAT_TOKDNE. */ - -/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */ -#define BR_USB_ISTAT_TOKDNE(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE)) - -/*! @brief Format value for bitfield USB_ISTAT_TOKDNE. */ -#define BF_USB_ISTAT_TOKDNE(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_TOKDNE) & BM_USB_ISTAT_TOKDNE) - -/*! @brief Set the TOKDNE field to a new value. */ -#define BW_USB_ISTAT_TOKDNE(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field SLEEP[4] (W1C) - * - * This bit is set when the USB Module detects a constant idle on the USB bus - * for 3 ms. The sleep timer is reset by activity on the USB bus. - */ -/*@{*/ -#define BP_USB_ISTAT_SLEEP (4U) /*!< Bit position for USB_ISTAT_SLEEP. */ -#define BM_USB_ISTAT_SLEEP (0x10U) /*!< Bit mask for USB_ISTAT_SLEEP. */ -#define BS_USB_ISTAT_SLEEP (1U) /*!< Bit field size in bits for USB_ISTAT_SLEEP. */ - -/*! @brief Read current value of the USB_ISTAT_SLEEP field. */ -#define BR_USB_ISTAT_SLEEP(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP)) - -/*! @brief Format value for bitfield USB_ISTAT_SLEEP. */ -#define BF_USB_ISTAT_SLEEP(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SLEEP) & BM_USB_ISTAT_SLEEP) - -/*! @brief Set the SLEEP field to a new value. */ -#define BW_USB_ISTAT_SLEEP(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field RESUME[5] (W1C) - * - * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us. - * When not in suspend mode this interrupt must be disabled. - */ -/*@{*/ -#define BP_USB_ISTAT_RESUME (5U) /*!< Bit position for USB_ISTAT_RESUME. */ -#define BM_USB_ISTAT_RESUME (0x20U) /*!< Bit mask for USB_ISTAT_RESUME. */ -#define BS_USB_ISTAT_RESUME (1U) /*!< Bit field size in bits for USB_ISTAT_RESUME. */ - -/*! @brief Read current value of the USB_ISTAT_RESUME field. */ -#define BR_USB_ISTAT_RESUME(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME)) - -/*! @brief Format value for bitfield USB_ISTAT_RESUME. */ -#define BF_USB_ISTAT_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_RESUME) & BM_USB_ISTAT_RESUME) - -/*! @brief Set the RESUME field to a new value. */ -#define BW_USB_ISTAT_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field ATTACH[6] (W1C) - * - * This bit is set when the USB Module detects an attach of a USB device. This - * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a - * peripheral is now present and must be configured; it is asserted if there have - * been no transitions on the USB for 2.5 us and the current bus state is not SE0." - */ -/*@{*/ -#define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */ -#define BM_USB_ISTAT_ATTACH (0x40U) /*!< Bit mask for USB_ISTAT_ATTACH. */ -#define BS_USB_ISTAT_ATTACH (1U) /*!< Bit field size in bits for USB_ISTAT_ATTACH. */ - -/*! @brief Read current value of the USB_ISTAT_ATTACH field. */ -#define BR_USB_ISTAT_ATTACH(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH)) - -/*! @brief Format value for bitfield USB_ISTAT_ATTACH. */ -#define BF_USB_ISTAT_ATTACH(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ATTACH) & BM_USB_ISTAT_ATTACH) - -/*! @brief Set the ATTACH field to a new value. */ -#define BW_USB_ISTAT_ATTACH(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field STALL[7] (W1C) - * - * In Target mode this bit is asserted when a STALL handshake is sent by the - * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge - * during the handshake phase of a USB transaction.This interrupt can be used to - * determine whether the last USB transaction was completed successfully or - * stalled. - */ -/*@{*/ -#define BP_USB_ISTAT_STALL (7U) /*!< Bit position for USB_ISTAT_STALL. */ -#define BM_USB_ISTAT_STALL (0x80U) /*!< Bit mask for USB_ISTAT_STALL. */ -#define BS_USB_ISTAT_STALL (1U) /*!< Bit field size in bits for USB_ISTAT_STALL. */ - -/*! @brief Read current value of the USB_ISTAT_STALL field. */ -#define BR_USB_ISTAT_STALL(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL)) - -/*! @brief Format value for bitfield USB_ISTAT_STALL. */ -#define BF_USB_ISTAT_STALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_STALL) & BM_USB_ISTAT_STALL) - -/*! @brief Set the STALL field to a new value. */ -#define BW_USB_ISTAT_STALL(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_INTEN - Interrupt Enable register - ******************************************************************************/ - -/*! - * @brief HW_USB_INTEN - Interrupt Enable register (RW) - * - * Reset value: 0x00U - * - * Contains enable fields for each of the interrupt sources within the USB - * Module. Setting any of these bits enables the respective interrupt source in the - * ISTAT register. This register contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_inten -{ - uint8_t U; - struct _hw_usb_inten_bitfields - { - uint8_t USBRSTEN : 1; /*!< [0] USBRST Interrupt Enable */ - uint8_t ERROREN : 1; /*!< [1] ERROR Interrupt Enable */ - uint8_t SOFTOKEN : 1; /*!< [2] SOFTOK Interrupt Enable */ - uint8_t TOKDNEEN : 1; /*!< [3] TOKDNE Interrupt Enable */ - uint8_t SLEEPEN : 1; /*!< [4] SLEEP Interrupt Enable */ - uint8_t RESUMEEN : 1; /*!< [5] RESUME Interrupt Enable */ - uint8_t ATTACHEN : 1; /*!< [6] ATTACH Interrupt Enable */ - uint8_t STALLEN : 1; /*!< [7] STALL Interrupt Enable */ - } B; -} hw_usb_inten_t; - -/*! - * @name Constants and macros for entire USB_INTEN register - */ -/*@{*/ -#define HW_USB_INTEN_ADDR(x) ((x) + 0x84U) - -#define HW_USB_INTEN(x) (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR(x)) -#define HW_USB_INTEN_RD(x) (HW_USB_INTEN(x).U) -#define HW_USB_INTEN_WR(x, v) (HW_USB_INTEN(x).U = (v)) -#define HW_USB_INTEN_SET(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) | (v))) -#define HW_USB_INTEN_CLR(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) & ~(v))) -#define HW_USB_INTEN_TOG(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_INTEN bitfields - */ - -/*! - * @name Register USB_INTEN, field USBRSTEN[0] (RW) - * - * Values: - * - 0 - Disables the USBRST interrupt. - * - 1 - Enables the USBRST interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_USBRSTEN (0U) /*!< Bit position for USB_INTEN_USBRSTEN. */ -#define BM_USB_INTEN_USBRSTEN (0x01U) /*!< Bit mask for USB_INTEN_USBRSTEN. */ -#define BS_USB_INTEN_USBRSTEN (1U) /*!< Bit field size in bits for USB_INTEN_USBRSTEN. */ - -/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */ -#define BR_USB_INTEN_USBRSTEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN)) - -/*! @brief Format value for bitfield USB_INTEN_USBRSTEN. */ -#define BF_USB_INTEN_USBRSTEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_USBRSTEN) & BM_USB_INTEN_USBRSTEN) - -/*! @brief Set the USBRSTEN field to a new value. */ -#define BW_USB_INTEN_USBRSTEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field ERROREN[1] (RW) - * - * Values: - * - 0 - Disables the ERROR interrupt. - * - 1 - Enables the ERROR interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_ERROREN (1U) /*!< Bit position for USB_INTEN_ERROREN. */ -#define BM_USB_INTEN_ERROREN (0x02U) /*!< Bit mask for USB_INTEN_ERROREN. */ -#define BS_USB_INTEN_ERROREN (1U) /*!< Bit field size in bits for USB_INTEN_ERROREN. */ - -/*! @brief Read current value of the USB_INTEN_ERROREN field. */ -#define BR_USB_INTEN_ERROREN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN)) - -/*! @brief Format value for bitfield USB_INTEN_ERROREN. */ -#define BF_USB_INTEN_ERROREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ERROREN) & BM_USB_INTEN_ERROREN) - -/*! @brief Set the ERROREN field to a new value. */ -#define BW_USB_INTEN_ERROREN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field SOFTOKEN[2] (RW) - * - * Values: - * - 0 - Disbles the SOFTOK interrupt. - * - 1 - Enables the SOFTOK interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_SOFTOKEN (2U) /*!< Bit position for USB_INTEN_SOFTOKEN. */ -#define BM_USB_INTEN_SOFTOKEN (0x04U) /*!< Bit mask for USB_INTEN_SOFTOKEN. */ -#define BS_USB_INTEN_SOFTOKEN (1U) /*!< Bit field size in bits for USB_INTEN_SOFTOKEN. */ - -/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */ -#define BR_USB_INTEN_SOFTOKEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN)) - -/*! @brief Format value for bitfield USB_INTEN_SOFTOKEN. */ -#define BF_USB_INTEN_SOFTOKEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SOFTOKEN) & BM_USB_INTEN_SOFTOKEN) - -/*! @brief Set the SOFTOKEN field to a new value. */ -#define BW_USB_INTEN_SOFTOKEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field TOKDNEEN[3] (RW) - * - * Values: - * - 0 - Disables the TOKDNE interrupt. - * - 1 - Enables the TOKDNE interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_TOKDNEEN (3U) /*!< Bit position for USB_INTEN_TOKDNEEN. */ -#define BM_USB_INTEN_TOKDNEEN (0x08U) /*!< Bit mask for USB_INTEN_TOKDNEEN. */ -#define BS_USB_INTEN_TOKDNEEN (1U) /*!< Bit field size in bits for USB_INTEN_TOKDNEEN. */ - -/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */ -#define BR_USB_INTEN_TOKDNEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN)) - -/*! @brief Format value for bitfield USB_INTEN_TOKDNEEN. */ -#define BF_USB_INTEN_TOKDNEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_TOKDNEEN) & BM_USB_INTEN_TOKDNEEN) - -/*! @brief Set the TOKDNEEN field to a new value. */ -#define BW_USB_INTEN_TOKDNEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field SLEEPEN[4] (RW) - * - * Values: - * - 0 - Disables the SLEEP interrupt. - * - 1 - Enables the SLEEP interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_SLEEPEN (4U) /*!< Bit position for USB_INTEN_SLEEPEN. */ -#define BM_USB_INTEN_SLEEPEN (0x10U) /*!< Bit mask for USB_INTEN_SLEEPEN. */ -#define BS_USB_INTEN_SLEEPEN (1U) /*!< Bit field size in bits for USB_INTEN_SLEEPEN. */ - -/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */ -#define BR_USB_INTEN_SLEEPEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN)) - -/*! @brief Format value for bitfield USB_INTEN_SLEEPEN. */ -#define BF_USB_INTEN_SLEEPEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SLEEPEN) & BM_USB_INTEN_SLEEPEN) - -/*! @brief Set the SLEEPEN field to a new value. */ -#define BW_USB_INTEN_SLEEPEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field RESUMEEN[5] (RW) - * - * Values: - * - 0 - Disables the RESUME interrupt. - * - 1 - Enables the RESUME interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_RESUMEEN (5U) /*!< Bit position for USB_INTEN_RESUMEEN. */ -#define BM_USB_INTEN_RESUMEEN (0x20U) /*!< Bit mask for USB_INTEN_RESUMEEN. */ -#define BS_USB_INTEN_RESUMEEN (1U) /*!< Bit field size in bits for USB_INTEN_RESUMEEN. */ - -/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */ -#define BR_USB_INTEN_RESUMEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN)) - -/*! @brief Format value for bitfield USB_INTEN_RESUMEEN. */ -#define BF_USB_INTEN_RESUMEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_RESUMEEN) & BM_USB_INTEN_RESUMEEN) - -/*! @brief Set the RESUMEEN field to a new value. */ -#define BW_USB_INTEN_RESUMEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field ATTACHEN[6] (RW) - * - * Values: - * - 0 - Disables the ATTACH interrupt. - * - 1 - Enables the ATTACH interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_ATTACHEN (6U) /*!< Bit position for USB_INTEN_ATTACHEN. */ -#define BM_USB_INTEN_ATTACHEN (0x40U) /*!< Bit mask for USB_INTEN_ATTACHEN. */ -#define BS_USB_INTEN_ATTACHEN (1U) /*!< Bit field size in bits for USB_INTEN_ATTACHEN. */ - -/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */ -#define BR_USB_INTEN_ATTACHEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN)) - -/*! @brief Format value for bitfield USB_INTEN_ATTACHEN. */ -#define BF_USB_INTEN_ATTACHEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ATTACHEN) & BM_USB_INTEN_ATTACHEN) - -/*! @brief Set the ATTACHEN field to a new value. */ -#define BW_USB_INTEN_ATTACHEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field STALLEN[7] (RW) - * - * Values: - * - 0 - Diasbles the STALL interrupt. - * - 1 - Enables the STALL interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_STALLEN (7U) /*!< Bit position for USB_INTEN_STALLEN. */ -#define BM_USB_INTEN_STALLEN (0x80U) /*!< Bit mask for USB_INTEN_STALLEN. */ -#define BS_USB_INTEN_STALLEN (1U) /*!< Bit field size in bits for USB_INTEN_STALLEN. */ - -/*! @brief Read current value of the USB_INTEN_STALLEN field. */ -#define BR_USB_INTEN_STALLEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN)) - -/*! @brief Format value for bitfield USB_INTEN_STALLEN. */ -#define BF_USB_INTEN_STALLEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_STALLEN) & BM_USB_INTEN_STALLEN) - -/*! @brief Set the STALLEN field to a new value. */ -#define BW_USB_INTEN_STALLEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ERRSTAT - Error Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW) - * - * Reset value: 0x00U - * - * Contains enable bits for each of the error sources within the USB Module. - * Each of these bits are qualified with their respective error enable bits. All - * bits of this register are logically OR'd together and the result placed in the - * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only - * be cleared by writing a one to the respective interrupt bit. Each bit is set - * as soon as the error condition is detected. Therefore, the interrupt does not - * typically correspond with the end of a token being processed. This register - * contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_errstat -{ - uint8_t U; - struct _hw_usb_errstat_bitfields - { - uint8_t PIDERR : 1; /*!< [0] */ - uint8_t CRC5EOF : 1; /*!< [1] */ - uint8_t CRC16 : 1; /*!< [2] */ - uint8_t DFN8 : 1; /*!< [3] */ - uint8_t BTOERR : 1; /*!< [4] */ - uint8_t DMAERR : 1; /*!< [5] */ - uint8_t RESERVED0 : 1; /*!< [6] */ - uint8_t BTSERR : 1; /*!< [7] */ - } B; -} hw_usb_errstat_t; - -/*! - * @name Constants and macros for entire USB_ERRSTAT register - */ -/*@{*/ -#define HW_USB_ERRSTAT_ADDR(x) ((x) + 0x88U) - -#define HW_USB_ERRSTAT(x) (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR(x)) -#define HW_USB_ERRSTAT_RD(x) (HW_USB_ERRSTAT(x).U) -#define HW_USB_ERRSTAT_WR(x, v) (HW_USB_ERRSTAT(x).U = (v)) -#define HW_USB_ERRSTAT_SET(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) | (v))) -#define HW_USB_ERRSTAT_CLR(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) & ~(v))) -#define HW_USB_ERRSTAT_TOG(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ERRSTAT bitfields - */ - -/*! - * @name Register USB_ERRSTAT, field PIDERR[0] (W1C) - * - * This bit is set when the PID check field fails. - */ -/*@{*/ -#define BP_USB_ERRSTAT_PIDERR (0U) /*!< Bit position for USB_ERRSTAT_PIDERR. */ -#define BM_USB_ERRSTAT_PIDERR (0x01U) /*!< Bit mask for USB_ERRSTAT_PIDERR. */ -#define BS_USB_ERRSTAT_PIDERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_PIDERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */ -#define BR_USB_ERRSTAT_PIDERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_PIDERR. */ -#define BF_USB_ERRSTAT_PIDERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_PIDERR) & BM_USB_ERRSTAT_PIDERR) - -/*! @brief Set the PIDERR field to a new value. */ -#define BW_USB_ERRSTAT_PIDERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C) - * - * This error interrupt has two functions. When the USB Module is operating in - * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token - * packets generated by the host. If set the token packet was rejected due to a - * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this - * interrupt detects End Of Frame (EOF) error conditions. This occurs when the - * USB Module is transmitting or receiving data and the SOF counter reaches zero. - * This interrupt is useful when developing USB packet scheduling software to - * ensure that no USB transactions cross the start of the next frame. - */ -/*@{*/ -#define BP_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit position for USB_ERRSTAT_CRC5EOF. */ -#define BM_USB_ERRSTAT_CRC5EOF (0x02U) /*!< Bit mask for USB_ERRSTAT_CRC5EOF. */ -#define BS_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC5EOF. */ - -/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */ -#define BR_USB_ERRSTAT_CRC5EOF(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF)) - -/*! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF. */ -#define BF_USB_ERRSTAT_CRC5EOF(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC5EOF) & BM_USB_ERRSTAT_CRC5EOF) - -/*! @brief Set the CRC5EOF field to a new value. */ -#define BW_USB_ERRSTAT_CRC5EOF(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field CRC16[2] (W1C) - * - * This bit is set when a data packet is rejected due to a CRC16 error. - */ -/*@{*/ -#define BP_USB_ERRSTAT_CRC16 (2U) /*!< Bit position for USB_ERRSTAT_CRC16. */ -#define BM_USB_ERRSTAT_CRC16 (0x04U) /*!< Bit mask for USB_ERRSTAT_CRC16. */ -#define BS_USB_ERRSTAT_CRC16 (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC16. */ - -/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */ -#define BR_USB_ERRSTAT_CRC16(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16)) - -/*! @brief Format value for bitfield USB_ERRSTAT_CRC16. */ -#define BF_USB_ERRSTAT_CRC16(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC16) & BM_USB_ERRSTAT_CRC16) - -/*! @brief Set the CRC16 field to a new value. */ -#define BW_USB_ERRSTAT_CRC16(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field DFN8[3] (W1C) - * - * This bit is set if the data field received was not 8 bits in length. USB - * Specification 1.0 requires that data fields be an integral number of bytes. If the - * data field was not an integral number of bytes, this bit is set. - */ -/*@{*/ -#define BP_USB_ERRSTAT_DFN8 (3U) /*!< Bit position for USB_ERRSTAT_DFN8. */ -#define BM_USB_ERRSTAT_DFN8 (0x08U) /*!< Bit mask for USB_ERRSTAT_DFN8. */ -#define BS_USB_ERRSTAT_DFN8 (1U) /*!< Bit field size in bits for USB_ERRSTAT_DFN8. */ - -/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */ -#define BR_USB_ERRSTAT_DFN8(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8)) - -/*! @brief Format value for bitfield USB_ERRSTAT_DFN8. */ -#define BF_USB_ERRSTAT_DFN8(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DFN8) & BM_USB_ERRSTAT_DFN8) - -/*! @brief Set the DFN8 field to a new value. */ -#define BW_USB_ERRSTAT_DFN8(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field BTOERR[4] (W1C) - * - * This bit is set when a bus turnaround timeout error occurs. The USB module - * contains a bus turnaround timer that keeps track of the amount of time elapsed - * between the token and data phases of a SETUP or OUT TOKEN or the data and - * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the - * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs. - */ -/*@{*/ -#define BP_USB_ERRSTAT_BTOERR (4U) /*!< Bit position for USB_ERRSTAT_BTOERR. */ -#define BM_USB_ERRSTAT_BTOERR (0x10U) /*!< Bit mask for USB_ERRSTAT_BTOERR. */ -#define BS_USB_ERRSTAT_BTOERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTOERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */ -#define BR_USB_ERRSTAT_BTOERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_BTOERR. */ -#define BF_USB_ERRSTAT_BTOERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTOERR) & BM_USB_ERRSTAT_BTOERR) - -/*! @brief Set the BTOERR field to a new value. */ -#define BW_USB_ERRSTAT_BTOERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field DMAERR[5] (W1C) - * - * This bit is set if the USB Module has requested a DMA access to read a new - * BDT but has not been given the bus before it needs to receive or transmit data. - * If processing a TX transfer this would cause a transmit data underflow - * condition. If processing a RX transfer this would cause a receive data overflow - * condition. This interrupt is useful when developing device arbitration hardware for - * the microprocessor and the USB module to minimize bus request and bus grant - * latency. This bit is also set if a data packet to or from the host is larger - * than the buffer size allocated in the BDT. In this case the data packet is - * truncated as it is put in buffer memory. - */ -/*@{*/ -#define BP_USB_ERRSTAT_DMAERR (5U) /*!< Bit position for USB_ERRSTAT_DMAERR. */ -#define BM_USB_ERRSTAT_DMAERR (0x20U) /*!< Bit mask for USB_ERRSTAT_DMAERR. */ -#define BS_USB_ERRSTAT_DMAERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_DMAERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */ -#define BR_USB_ERRSTAT_DMAERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_DMAERR. */ -#define BF_USB_ERRSTAT_DMAERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DMAERR) & BM_USB_ERRSTAT_DMAERR) - -/*! @brief Set the DMAERR field to a new value. */ -#define BW_USB_ERRSTAT_DMAERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field BTSERR[7] (W1C) - * - * This bit is set when a bit stuff error is detected. If set, the corresponding - * packet is rejected due to the error. - */ -/*@{*/ -#define BP_USB_ERRSTAT_BTSERR (7U) /*!< Bit position for USB_ERRSTAT_BTSERR. */ -#define BM_USB_ERRSTAT_BTSERR (0x80U) /*!< Bit mask for USB_ERRSTAT_BTSERR. */ -#define BS_USB_ERRSTAT_BTSERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTSERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */ -#define BR_USB_ERRSTAT_BTSERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_BTSERR. */ -#define BF_USB_ERRSTAT_BTSERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTSERR) & BM_USB_ERRSTAT_BTSERR) - -/*! @brief Set the BTSERR field to a new value. */ -#define BW_USB_ERRSTAT_BTSERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ERREN - Error Interrupt Enable register - ******************************************************************************/ - -/*! - * @brief HW_USB_ERREN - Error Interrupt Enable register (RW) - * - * Reset value: 0x00U - * - * Contains enable bits for each of the error interrupt sources within the USB - * module. Setting any of these bits enables the respective interrupt source in - * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore, - * the interrupt does not typically correspond with the end of a token being - * processed. This register contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_erren -{ - uint8_t U; - struct _hw_usb_erren_bitfields - { - uint8_t PIDERREN : 1; /*!< [0] PIDERR Interrupt Enable */ - uint8_t CRC5EOFEN : 1; /*!< [1] CRC5/EOF Interrupt Enable */ - uint8_t CRC16EN : 1; /*!< [2] CRC16 Interrupt Enable */ - uint8_t DFN8EN : 1; /*!< [3] DFN8 Interrupt Enable */ - uint8_t BTOERREN : 1; /*!< [4] BTOERR Interrupt Enable */ - uint8_t DMAERREN : 1; /*!< [5] DMAERR Interrupt Enable */ - uint8_t RESERVED0 : 1; /*!< [6] */ - uint8_t BTSERREN : 1; /*!< [7] BTSERR Interrupt Enable */ - } B; -} hw_usb_erren_t; - -/*! - * @name Constants and macros for entire USB_ERREN register - */ -/*@{*/ -#define HW_USB_ERREN_ADDR(x) ((x) + 0x8CU) - -#define HW_USB_ERREN(x) (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR(x)) -#define HW_USB_ERREN_RD(x) (HW_USB_ERREN(x).U) -#define HW_USB_ERREN_WR(x, v) (HW_USB_ERREN(x).U = (v)) -#define HW_USB_ERREN_SET(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) | (v))) -#define HW_USB_ERREN_CLR(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) & ~(v))) -#define HW_USB_ERREN_TOG(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ERREN bitfields - */ - -/*! - * @name Register USB_ERREN, field PIDERREN[0] (RW) - * - * Values: - * - 0 - Disables the PIDERR interrupt. - * - 1 - Enters the PIDERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_PIDERREN (0U) /*!< Bit position for USB_ERREN_PIDERREN. */ -#define BM_USB_ERREN_PIDERREN (0x01U) /*!< Bit mask for USB_ERREN_PIDERREN. */ -#define BS_USB_ERREN_PIDERREN (1U) /*!< Bit field size in bits for USB_ERREN_PIDERREN. */ - -/*! @brief Read current value of the USB_ERREN_PIDERREN field. */ -#define BR_USB_ERREN_PIDERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN)) - -/*! @brief Format value for bitfield USB_ERREN_PIDERREN. */ -#define BF_USB_ERREN_PIDERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_PIDERREN) & BM_USB_ERREN_PIDERREN) - -/*! @brief Set the PIDERREN field to a new value. */ -#define BW_USB_ERREN_PIDERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field CRC5EOFEN[1] (RW) - * - * Values: - * - 0 - Disables the CRC5/EOF interrupt. - * - 1 - Enables the CRC5/EOF interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_CRC5EOFEN (1U) /*!< Bit position for USB_ERREN_CRC5EOFEN. */ -#define BM_USB_ERREN_CRC5EOFEN (0x02U) /*!< Bit mask for USB_ERREN_CRC5EOFEN. */ -#define BS_USB_ERREN_CRC5EOFEN (1U) /*!< Bit field size in bits for USB_ERREN_CRC5EOFEN. */ - -/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */ -#define BR_USB_ERREN_CRC5EOFEN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN)) - -/*! @brief Format value for bitfield USB_ERREN_CRC5EOFEN. */ -#define BF_USB_ERREN_CRC5EOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC5EOFEN) & BM_USB_ERREN_CRC5EOFEN) - -/*! @brief Set the CRC5EOFEN field to a new value. */ -#define BW_USB_ERREN_CRC5EOFEN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field CRC16EN[2] (RW) - * - * Values: - * - 0 - Disables the CRC16 interrupt. - * - 1 - Enables the CRC16 interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_CRC16EN (2U) /*!< Bit position for USB_ERREN_CRC16EN. */ -#define BM_USB_ERREN_CRC16EN (0x04U) /*!< Bit mask for USB_ERREN_CRC16EN. */ -#define BS_USB_ERREN_CRC16EN (1U) /*!< Bit field size in bits for USB_ERREN_CRC16EN. */ - -/*! @brief Read current value of the USB_ERREN_CRC16EN field. */ -#define BR_USB_ERREN_CRC16EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN)) - -/*! @brief Format value for bitfield USB_ERREN_CRC16EN. */ -#define BF_USB_ERREN_CRC16EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC16EN) & BM_USB_ERREN_CRC16EN) - -/*! @brief Set the CRC16EN field to a new value. */ -#define BW_USB_ERREN_CRC16EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field DFN8EN[3] (RW) - * - * Values: - * - 0 - Disables the DFN8 interrupt. - * - 1 - Enables the DFN8 interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_DFN8EN (3U) /*!< Bit position for USB_ERREN_DFN8EN. */ -#define BM_USB_ERREN_DFN8EN (0x08U) /*!< Bit mask for USB_ERREN_DFN8EN. */ -#define BS_USB_ERREN_DFN8EN (1U) /*!< Bit field size in bits for USB_ERREN_DFN8EN. */ - -/*! @brief Read current value of the USB_ERREN_DFN8EN field. */ -#define BR_USB_ERREN_DFN8EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN)) - -/*! @brief Format value for bitfield USB_ERREN_DFN8EN. */ -#define BF_USB_ERREN_DFN8EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DFN8EN) & BM_USB_ERREN_DFN8EN) - -/*! @brief Set the DFN8EN field to a new value. */ -#define BW_USB_ERREN_DFN8EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field BTOERREN[4] (RW) - * - * Values: - * - 0 - Disables the BTOERR interrupt. - * - 1 - Enables the BTOERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_BTOERREN (4U) /*!< Bit position for USB_ERREN_BTOERREN. */ -#define BM_USB_ERREN_BTOERREN (0x10U) /*!< Bit mask for USB_ERREN_BTOERREN. */ -#define BS_USB_ERREN_BTOERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTOERREN. */ - -/*! @brief Read current value of the USB_ERREN_BTOERREN field. */ -#define BR_USB_ERREN_BTOERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN)) - -/*! @brief Format value for bitfield USB_ERREN_BTOERREN. */ -#define BF_USB_ERREN_BTOERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTOERREN) & BM_USB_ERREN_BTOERREN) - -/*! @brief Set the BTOERREN field to a new value. */ -#define BW_USB_ERREN_BTOERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field DMAERREN[5] (RW) - * - * Values: - * - 0 - Disables the DMAERR interrupt. - * - 1 - Enables the DMAERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_DMAERREN (5U) /*!< Bit position for USB_ERREN_DMAERREN. */ -#define BM_USB_ERREN_DMAERREN (0x20U) /*!< Bit mask for USB_ERREN_DMAERREN. */ -#define BS_USB_ERREN_DMAERREN (1U) /*!< Bit field size in bits for USB_ERREN_DMAERREN. */ - -/*! @brief Read current value of the USB_ERREN_DMAERREN field. */ -#define BR_USB_ERREN_DMAERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN)) - -/*! @brief Format value for bitfield USB_ERREN_DMAERREN. */ -#define BF_USB_ERREN_DMAERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DMAERREN) & BM_USB_ERREN_DMAERREN) - -/*! @brief Set the DMAERREN field to a new value. */ -#define BW_USB_ERREN_DMAERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field BTSERREN[7] (RW) - * - * Values: - * - 0 - Disables the BTSERR interrupt. - * - 1 - Enables the BTSERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_BTSERREN (7U) /*!< Bit position for USB_ERREN_BTSERREN. */ -#define BM_USB_ERREN_BTSERREN (0x80U) /*!< Bit mask for USB_ERREN_BTSERREN. */ -#define BS_USB_ERREN_BTSERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTSERREN. */ - -/*! @brief Read current value of the USB_ERREN_BTSERREN field. */ -#define BR_USB_ERREN_BTSERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN)) - -/*! @brief Format value for bitfield USB_ERREN_BTSERREN. */ -#define BF_USB_ERREN_BTSERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTSERREN) & BM_USB_ERREN_BTSERREN) - -/*! @brief Set the BTSERREN field to a new value. */ -#define BW_USB_ERREN_BTSERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_STAT - Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_STAT - Status register (RO) - * - * Reset value: 0x00U - * - * Reports the transaction status within the USB module. When the processor's - * interrupt controller has received a TOKDNE, interrupt the Status Register must - * be read to determine the status of the previous endpoint communication. The - * data in the status register is valid when TOKDNE interrupt is asserted. The - * Status register is actually a read window into a status FIFO maintained by the USB - * module. When the USB module uses a BD, it updates the Status register. If - * another USB transaction is performed before the TOKDNE interrupt is serviced, the - * USB module stores the status of the next transaction in the STAT FIFO. Thus - * STAT is actually a four byte FIFO that allows the processor core to process one - * transaction while the SIE is processing the next transaction. Clearing the - * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents - * of the next STAT value. If the data in the STAT holding register is valid, the - * SIE immediately reasserts to TOKDNE interrupt. - */ -typedef union _hw_usb_stat -{ - uint8_t U; - struct _hw_usb_stat_bitfields - { - uint8_t RESERVED0 : 2; /*!< [1:0] */ - uint8_t ODD : 1; /*!< [2] */ - uint8_t TX : 1; /*!< [3] Transmit Indicator */ - uint8_t ENDP : 4; /*!< [7:4] */ - } B; -} hw_usb_stat_t; - -/*! - * @name Constants and macros for entire USB_STAT register - */ -/*@{*/ -#define HW_USB_STAT_ADDR(x) ((x) + 0x90U) - -#define HW_USB_STAT(x) (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR(x)) -#define HW_USB_STAT_RD(x) (HW_USB_STAT(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_STAT bitfields - */ - -/*! - * @name Register USB_STAT, field ODD[2] (RO) - * - * This bit is set if the last buffer descriptor updated was in the odd bank of - * the BDT. - */ -/*@{*/ -#define BP_USB_STAT_ODD (2U) /*!< Bit position for USB_STAT_ODD. */ -#define BM_USB_STAT_ODD (0x04U) /*!< Bit mask for USB_STAT_ODD. */ -#define BS_USB_STAT_ODD (1U) /*!< Bit field size in bits for USB_STAT_ODD. */ - -/*! @brief Read current value of the USB_STAT_ODD field. */ -#define BR_USB_STAT_ODD(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_ODD)) -/*@}*/ - -/*! - * @name Register USB_STAT, field TX[3] (RO) - * - * Values: - * - 0 - The most recent transaction was a receive operation. - * - 1 - The most recent transaction was a transmit operation. - */ -/*@{*/ -#define BP_USB_STAT_TX (3U) /*!< Bit position for USB_STAT_TX. */ -#define BM_USB_STAT_TX (0x08U) /*!< Bit mask for USB_STAT_TX. */ -#define BS_USB_STAT_TX (1U) /*!< Bit field size in bits for USB_STAT_TX. */ - -/*! @brief Read current value of the USB_STAT_TX field. */ -#define BR_USB_STAT_TX(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_TX)) -/*@}*/ - -/*! - * @name Register USB_STAT, field ENDP[7:4] (RO) - * - * This four-bit field encodes the endpoint address that received or transmitted - * the previous token. This allows the processor core to determine the BDT entry - * that was updated by the last USB transaction. - */ -/*@{*/ -#define BP_USB_STAT_ENDP (4U) /*!< Bit position for USB_STAT_ENDP. */ -#define BM_USB_STAT_ENDP (0xF0U) /*!< Bit mask for USB_STAT_ENDP. */ -#define BS_USB_STAT_ENDP (4U) /*!< Bit field size in bits for USB_STAT_ENDP. */ - -/*! @brief Read current value of the USB_STAT_ENDP field. */ -#define BR_USB_STAT_ENDP(x) (HW_USB_STAT(x).B.ENDP) -/*@}*/ - -/******************************************************************************* - * HW_USB_CTL - Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_CTL - Control register (RW) - * - * Reset value: 0x00U - * - * Provides various control and configuration information for the USB module. - */ -typedef union _hw_usb_ctl -{ - uint8_t U; - struct _hw_usb_ctl_bitfields - { - uint8_t USBENSOFEN : 1; /*!< [0] USB Enable */ - uint8_t ODDRST : 1; /*!< [1] */ - uint8_t RESUME : 1; /*!< [2] */ - uint8_t HOSTMODEEN : 1; /*!< [3] */ - uint8_t RESET : 1; /*!< [4] */ - uint8_t TXSUSPENDTOKENBUSY : 1; /*!< [5] */ - uint8_t SE0 : 1; /*!< [6] Live USB Single Ended Zero signal */ - uint8_t JSTATE : 1; /*!< [7] Live USB differential receiver JSTATE - * signal */ - } B; -} hw_usb_ctl_t; - -/*! - * @name Constants and macros for entire USB_CTL register - */ -/*@{*/ -#define HW_USB_CTL_ADDR(x) ((x) + 0x94U) - -#define HW_USB_CTL(x) (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR(x)) -#define HW_USB_CTL_RD(x) (HW_USB_CTL(x).U) -#define HW_USB_CTL_WR(x, v) (HW_USB_CTL(x).U = (v)) -#define HW_USB_CTL_SET(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) | (v))) -#define HW_USB_CTL_CLR(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) & ~(v))) -#define HW_USB_CTL_TOG(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CTL bitfields - */ - -/*! - * @name Register USB_CTL, field USBENSOFEN[0] (RW) - * - * Setting this bit enables the USB-FS to operate; clearing it disables the - * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs. - * Therefore, setting this bit resets much of the logic in the SIE. When host mode - * is enabled, clearing this bit causes the SIE to stop sending SOF tokens. - * - * Values: - * - 0 - Disables the USB Module. - * - 1 - Enables the USB Module. - */ -/*@{*/ -#define BP_USB_CTL_USBENSOFEN (0U) /*!< Bit position for USB_CTL_USBENSOFEN. */ -#define BM_USB_CTL_USBENSOFEN (0x01U) /*!< Bit mask for USB_CTL_USBENSOFEN. */ -#define BS_USB_CTL_USBENSOFEN (1U) /*!< Bit field size in bits for USB_CTL_USBENSOFEN. */ - -/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */ -#define BR_USB_CTL_USBENSOFEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN)) - -/*! @brief Format value for bitfield USB_CTL_USBENSOFEN. */ -#define BF_USB_CTL_USBENSOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_USBENSOFEN) & BM_USB_CTL_USBENSOFEN) - -/*! @brief Set the USBENSOFEN field to a new value. */ -#define BW_USB_CTL_USBENSOFEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field ODDRST[1] (RW) - * - * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which - * then specifies the EVEN BDT bank. - */ -/*@{*/ -#define BP_USB_CTL_ODDRST (1U) /*!< Bit position for USB_CTL_ODDRST. */ -#define BM_USB_CTL_ODDRST (0x02U) /*!< Bit mask for USB_CTL_ODDRST. */ -#define BS_USB_CTL_ODDRST (1U) /*!< Bit field size in bits for USB_CTL_ODDRST. */ - -/*! @brief Read current value of the USB_CTL_ODDRST field. */ -#define BR_USB_CTL_ODDRST(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST)) - -/*! @brief Format value for bitfield USB_CTL_ODDRST. */ -#define BF_USB_CTL_ODDRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_ODDRST) & BM_USB_CTL_ODDRST) - -/*! @brief Set the ODDRST field to a new value. */ -#define BW_USB_CTL_ODDRST(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field RESUME[2] (RW) - * - * When set to 1 this bit enables the USB Module to execute resume signaling. - * This allows the USB Module to perform remote wake-up. Software must set RESUME - * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN - * bit is set, the USB module appends a Low Speed End of Packet to the Resume - * signaling when the RESUME bit is cleared. For more information on RESUME - * signaling see Section 7.1.4.5 of the USB specification version 1.0. - */ -/*@{*/ -#define BP_USB_CTL_RESUME (2U) /*!< Bit position for USB_CTL_RESUME. */ -#define BM_USB_CTL_RESUME (0x04U) /*!< Bit mask for USB_CTL_RESUME. */ -#define BS_USB_CTL_RESUME (1U) /*!< Bit field size in bits for USB_CTL_RESUME. */ - -/*! @brief Read current value of the USB_CTL_RESUME field. */ -#define BR_USB_CTL_RESUME(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME)) - -/*! @brief Format value for bitfield USB_CTL_RESUME. */ -#define BF_USB_CTL_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESUME) & BM_USB_CTL_RESUME) - -/*! @brief Set the RESUME field to a new value. */ -#define BW_USB_CTL_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field HOSTMODEEN[3] (RW) - * - * When set to 1, this bit enables the USB Module to operate in Host mode. In - * host mode, the USB module performs USB transactions under the programmed control - * of the host processor. - */ -/*@{*/ -#define BP_USB_CTL_HOSTMODEEN (3U) /*!< Bit position for USB_CTL_HOSTMODEEN. */ -#define BM_USB_CTL_HOSTMODEEN (0x08U) /*!< Bit mask for USB_CTL_HOSTMODEEN. */ -#define BS_USB_CTL_HOSTMODEEN (1U) /*!< Bit field size in bits for USB_CTL_HOSTMODEEN. */ - -/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */ -#define BR_USB_CTL_HOSTMODEEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN)) - -/*! @brief Format value for bitfield USB_CTL_HOSTMODEEN. */ -#define BF_USB_CTL_HOSTMODEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_HOSTMODEEN) & BM_USB_CTL_HOSTMODEEN) - -/*! @brief Set the HOSTMODEEN field to a new value. */ -#define BW_USB_CTL_HOSTMODEEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field RESET[4] (RW) - * - * Setting this bit enables the USB Module to generate USB reset signaling. This - * allows the USB Module to reset USB peripherals. This control signal is only - * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the - * required amount of time and then clear it to 0 to end reset signaling. For more - * information on reset signaling see Section 7.1.4.3 of the USB specification version - * 1.0. - */ -/*@{*/ -#define BP_USB_CTL_RESET (4U) /*!< Bit position for USB_CTL_RESET. */ -#define BM_USB_CTL_RESET (0x10U) /*!< Bit mask for USB_CTL_RESET. */ -#define BS_USB_CTL_RESET (1U) /*!< Bit field size in bits for USB_CTL_RESET. */ - -/*! @brief Read current value of the USB_CTL_RESET field. */ -#define BR_USB_CTL_RESET(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET)) - -/*! @brief Format value for bitfield USB_CTL_RESET. */ -#define BF_USB_CTL_RESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESET) & BM_USB_CTL_RESET) - -/*! @brief Set the RESET field to a new value. */ -#define BW_USB_CTL_RESET(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW) - * - * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB - * token. Software must not write more token commands to the Token Register when - * TOKEN_BUSY is set. Software should check this field before writing any tokens - * to the Token Register to ensure that token commands are not lost. In Target - * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and - * reception. Clearing this bit allows the SIE to continue token processing. This bit - * is set by the SIE when a SETUP Token is received allowing software to dequeue - * any pending packet transactions in the BDT before resuming token processing. - */ -/*@{*/ -#define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) /*!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY. */ -#define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) /*!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY. */ -#define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) /*!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY. */ - -/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */ -#define BR_USB_CTL_TXSUSPENDTOKENBUSY(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY)) - -/*! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY. */ -#define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_TXSUSPENDTOKENBUSY) & BM_USB_CTL_TXSUSPENDTOKENBUSY) - -/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */ -#define BW_USB_CTL_TXSUSPENDTOKENBUSY(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field SE0[6] (RW) - */ -/*@{*/ -#define BP_USB_CTL_SE0 (6U) /*!< Bit position for USB_CTL_SE0. */ -#define BM_USB_CTL_SE0 (0x40U) /*!< Bit mask for USB_CTL_SE0. */ -#define BS_USB_CTL_SE0 (1U) /*!< Bit field size in bits for USB_CTL_SE0. */ - -/*! @brief Read current value of the USB_CTL_SE0 field. */ -#define BR_USB_CTL_SE0(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0)) - -/*! @brief Format value for bitfield USB_CTL_SE0. */ -#define BF_USB_CTL_SE0(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_SE0) & BM_USB_CTL_SE0) - -/*! @brief Set the SE0 field to a new value. */ -#define BW_USB_CTL_SE0(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field JSTATE[7] (RW) - * - * The polarity of this signal is affected by the current state of LSEN . - */ -/*@{*/ -#define BP_USB_CTL_JSTATE (7U) /*!< Bit position for USB_CTL_JSTATE. */ -#define BM_USB_CTL_JSTATE (0x80U) /*!< Bit mask for USB_CTL_JSTATE. */ -#define BS_USB_CTL_JSTATE (1U) /*!< Bit field size in bits for USB_CTL_JSTATE. */ - -/*! @brief Read current value of the USB_CTL_JSTATE field. */ -#define BR_USB_CTL_JSTATE(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE)) - -/*! @brief Format value for bitfield USB_CTL_JSTATE. */ -#define BF_USB_CTL_JSTATE(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_JSTATE) & BM_USB_CTL_JSTATE) - -/*! @brief Set the JSTATE field to a new value. */ -#define BW_USB_CTL_JSTATE(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ADDR - Address register - ******************************************************************************/ - -/*! - * @brief HW_USB_ADDR - Address register (RW) - * - * Reset value: 0x00U - * - * Holds the unique USB address that the USB module decodes when in Peripheral - * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module - * transmits this address with a TOKEN packet. This enables the USB module to - * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1. - * The Address register is reset to 0x00 after the reset input becomes active or - * the USB module decodes a USB reset signal. This action initializes the Address - * register to decode address 0x00 as required by the USB specification. - */ -typedef union _hw_usb_addr -{ - uint8_t U; - struct _hw_usb_addr_bitfields - { - uint8_t ADDR : 7; /*!< [6:0] USB Address */ - uint8_t LSEN : 1; /*!< [7] Low Speed Enable bit */ - } B; -} hw_usb_addr_t; - -/*! - * @name Constants and macros for entire USB_ADDR register - */ -/*@{*/ -#define HW_USB_ADDR_ADDR(x) ((x) + 0x98U) - -#define HW_USB_ADDR(x) (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR(x)) -#define HW_USB_ADDR_RD(x) (HW_USB_ADDR(x).U) -#define HW_USB_ADDR_WR(x, v) (HW_USB_ADDR(x).U = (v)) -#define HW_USB_ADDR_SET(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) | (v))) -#define HW_USB_ADDR_CLR(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) & ~(v))) -#define HW_USB_ADDR_TOG(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ADDR bitfields - */ - -/*! - * @name Register USB_ADDR, field ADDR[6:0] (RW) - * - * Defines the USB address that the USB module decodes in peripheral mode, or - * transmits when in host mode. - */ -/*@{*/ -#define BP_USB_ADDR_ADDR (0U) /*!< Bit position for USB_ADDR_ADDR. */ -#define BM_USB_ADDR_ADDR (0x7FU) /*!< Bit mask for USB_ADDR_ADDR. */ -#define BS_USB_ADDR_ADDR (7U) /*!< Bit field size in bits for USB_ADDR_ADDR. */ - -/*! @brief Read current value of the USB_ADDR_ADDR field. */ -#define BR_USB_ADDR_ADDR(x) (HW_USB_ADDR(x).B.ADDR) - -/*! @brief Format value for bitfield USB_ADDR_ADDR. */ -#define BF_USB_ADDR_ADDR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_ADDR) & BM_USB_ADDR_ADDR) - -/*! @brief Set the ADDR field to a new value. */ -#define BW_USB_ADDR_ADDR(x, v) (HW_USB_ADDR_WR(x, (HW_USB_ADDR_RD(x) & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v))) -/*@}*/ - -/*! - * @name Register USB_ADDR, field LSEN[7] (RW) - * - * Informs the USB module that the next token command written to the token - * register must be performed at low speed. This enables the USB module to perform the - * necessary preamble required for low-speed data transmissions. - */ -/*@{*/ -#define BP_USB_ADDR_LSEN (7U) /*!< Bit position for USB_ADDR_LSEN. */ -#define BM_USB_ADDR_LSEN (0x80U) /*!< Bit mask for USB_ADDR_LSEN. */ -#define BS_USB_ADDR_LSEN (1U) /*!< Bit field size in bits for USB_ADDR_LSEN. */ - -/*! @brief Read current value of the USB_ADDR_LSEN field. */ -#define BR_USB_ADDR_LSEN(x) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN)) - -/*! @brief Format value for bitfield USB_ADDR_LSEN. */ -#define BF_USB_ADDR_LSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_LSEN) & BM_USB_ADDR_LSEN) - -/*! @brief Set the LSEN field to a new value. */ -#define BW_USB_ADDR_LSEN(x, v) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_BDTPAGE1 - BDT Page register 1 - ******************************************************************************/ - -/*! - * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW) - * - * Reset value: 0x00U - * - * Provides address bits 15 through 9 of the base address where the current - * Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base - * Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base - * address are always zero. - */ -typedef union _hw_usb_bdtpage1 -{ - uint8_t U; - struct _hw_usb_bdtpage1_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t BDTBA : 7; /*!< [7:1] */ - } B; -} hw_usb_bdtpage1_t; - -/*! - * @name Constants and macros for entire USB_BDTPAGE1 register - */ -/*@{*/ -#define HW_USB_BDTPAGE1_ADDR(x) ((x) + 0x9CU) - -#define HW_USB_BDTPAGE1(x) (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR(x)) -#define HW_USB_BDTPAGE1_RD(x) (HW_USB_BDTPAGE1(x).U) -#define HW_USB_BDTPAGE1_WR(x, v) (HW_USB_BDTPAGE1(x).U = (v)) -#define HW_USB_BDTPAGE1_SET(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) | (v))) -#define HW_USB_BDTPAGE1_CLR(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) & ~(v))) -#define HW_USB_BDTPAGE1_TOG(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_BDTPAGE1 bitfields - */ - -/*! - * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW) - * - * Provides address bits 15 through 9 of the BDT base address. - */ -/*@{*/ -#define BP_USB_BDTPAGE1_BDTBA (1U) /*!< Bit position for USB_BDTPAGE1_BDTBA. */ -#define BM_USB_BDTPAGE1_BDTBA (0xFEU) /*!< Bit mask for USB_BDTPAGE1_BDTBA. */ -#define BS_USB_BDTPAGE1_BDTBA (7U) /*!< Bit field size in bits for USB_BDTPAGE1_BDTBA. */ - -/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */ -#define BR_USB_BDTPAGE1_BDTBA(x) (HW_USB_BDTPAGE1(x).B.BDTBA) - -/*! @brief Format value for bitfield USB_BDTPAGE1_BDTBA. */ -#define BF_USB_BDTPAGE1_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE1_BDTBA) & BM_USB_BDTPAGE1_BDTBA) - -/*! @brief Set the BDTBA field to a new value. */ -#define BW_USB_BDTPAGE1_BDTBA(x, v) (HW_USB_BDTPAGE1_WR(x, (HW_USB_BDTPAGE1_RD(x) & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v))) -/*@}*/ - -/******************************************************************************* - * HW_USB_FRMNUML - Frame Number register Low - ******************************************************************************/ - -/*! - * @brief HW_USB_FRMNUML - Frame Number register Low (RW) - * - * Reset value: 0x00U - * - * The Frame Number registers (low and high) contain the 11-bit frame number. - * These registers are updated with the current frame number whenever a SOF TOKEN - * is received. - */ -typedef union _hw_usb_frmnuml -{ - uint8_t U; - struct _hw_usb_frmnuml_bitfields - { - uint8_t FRM : 8; /*!< [7:0] */ - } B; -} hw_usb_frmnuml_t; - -/*! - * @name Constants and macros for entire USB_FRMNUML register - */ -/*@{*/ -#define HW_USB_FRMNUML_ADDR(x) ((x) + 0xA0U) - -#define HW_USB_FRMNUML(x) (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR(x)) -#define HW_USB_FRMNUML_RD(x) (HW_USB_FRMNUML(x).U) -#define HW_USB_FRMNUML_WR(x, v) (HW_USB_FRMNUML(x).U = (v)) -#define HW_USB_FRMNUML_SET(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) | (v))) -#define HW_USB_FRMNUML_CLR(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) & ~(v))) -#define HW_USB_FRMNUML_TOG(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_FRMNUML bitfields - */ - -/*! - * @name Register USB_FRMNUML, field FRM[7:0] (RW) - * - * This 8-bit field and the 3-bit field in the Frame Number Register High are - * used to compute the address where the current Buffer Descriptor Table (BDT) - * resides in system memory. - */ -/*@{*/ -#define BP_USB_FRMNUML_FRM (0U) /*!< Bit position for USB_FRMNUML_FRM. */ -#define BM_USB_FRMNUML_FRM (0xFFU) /*!< Bit mask for USB_FRMNUML_FRM. */ -#define BS_USB_FRMNUML_FRM (8U) /*!< Bit field size in bits for USB_FRMNUML_FRM. */ - -/*! @brief Read current value of the USB_FRMNUML_FRM field. */ -#define BR_USB_FRMNUML_FRM(x) (HW_USB_FRMNUML(x).U) - -/*! @brief Format value for bitfield USB_FRMNUML_FRM. */ -#define BF_USB_FRMNUML_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUML_FRM) & BM_USB_FRMNUML_FRM) - -/*! @brief Set the FRM field to a new value. */ -#define BW_USB_FRMNUML_FRM(x, v) (HW_USB_FRMNUML_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_FRMNUMH - Frame Number register High - ******************************************************************************/ - -/*! - * @brief HW_USB_FRMNUMH - Frame Number register High (RW) - * - * Reset value: 0x00U - * - * The Frame Number registers (low and high) contain the 11-bit frame number. - * These registers are updated with the current frame number whenever a SOF TOKEN - * is received. - */ -typedef union _hw_usb_frmnumh -{ - uint8_t U; - struct _hw_usb_frmnumh_bitfields - { - uint8_t FRM : 3; /*!< [2:0] */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_usb_frmnumh_t; - -/*! - * @name Constants and macros for entire USB_FRMNUMH register - */ -/*@{*/ -#define HW_USB_FRMNUMH_ADDR(x) ((x) + 0xA4U) - -#define HW_USB_FRMNUMH(x) (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR(x)) -#define HW_USB_FRMNUMH_RD(x) (HW_USB_FRMNUMH(x).U) -#define HW_USB_FRMNUMH_WR(x, v) (HW_USB_FRMNUMH(x).U = (v)) -#define HW_USB_FRMNUMH_SET(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) | (v))) -#define HW_USB_FRMNUMH_CLR(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) & ~(v))) -#define HW_USB_FRMNUMH_TOG(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_FRMNUMH bitfields - */ - -/*! - * @name Register USB_FRMNUMH, field FRM[2:0] (RW) - * - * This 3-bit field and the 8-bit field in the Frame Number Register Low are - * used to compute the address where the current Buffer Descriptor Table (BDT) - * resides in system memory. - */ -/*@{*/ -#define BP_USB_FRMNUMH_FRM (0U) /*!< Bit position for USB_FRMNUMH_FRM. */ -#define BM_USB_FRMNUMH_FRM (0x07U) /*!< Bit mask for USB_FRMNUMH_FRM. */ -#define BS_USB_FRMNUMH_FRM (3U) /*!< Bit field size in bits for USB_FRMNUMH_FRM. */ - -/*! @brief Read current value of the USB_FRMNUMH_FRM field. */ -#define BR_USB_FRMNUMH_FRM(x) (HW_USB_FRMNUMH(x).B.FRM) - -/*! @brief Format value for bitfield USB_FRMNUMH_FRM. */ -#define BF_USB_FRMNUMH_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUMH_FRM) & BM_USB_FRMNUMH_FRM) - -/*! @brief Set the FRM field to a new value. */ -#define BW_USB_FRMNUMH_FRM(x, v) (HW_USB_FRMNUMH_WR(x, (HW_USB_FRMNUMH_RD(x) & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v))) -/*@}*/ - -/******************************************************************************* - * HW_USB_TOKEN - Token register - ******************************************************************************/ - -/*! - * @brief HW_USB_TOKEN - Token register (RW) - * - * Reset value: 0x00U - * - * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the - * software needs to execute a USB transaction to a peripheral, it writes the - * TOKEN type and endpoint to this register. After this register has been written, - * the USB module begins the specified USB transaction to the address contained in - * the address register. The processor core must always check that the - * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register. - * This ensures that the token commands are not overwritten before they can be - * executed. The address register and endpoint control register 0 are also used when - * performing a token command and therefore must also be written before the - * Token Register. The address register is used to select the USB peripheral address - * transmitted by the token command. The endpoint control register determines the - * handshake and retry policies used during the transfer. - */ -typedef union _hw_usb_token -{ - uint8_t U; - struct _hw_usb_token_bitfields - { - uint8_t TOKENENDPT : 4; /*!< [3:0] */ - uint8_t TOKENPID : 4; /*!< [7:4] */ - } B; -} hw_usb_token_t; - -/*! - * @name Constants and macros for entire USB_TOKEN register - */ -/*@{*/ -#define HW_USB_TOKEN_ADDR(x) ((x) + 0xA8U) - -#define HW_USB_TOKEN(x) (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR(x)) -#define HW_USB_TOKEN_RD(x) (HW_USB_TOKEN(x).U) -#define HW_USB_TOKEN_WR(x, v) (HW_USB_TOKEN(x).U = (v)) -#define HW_USB_TOKEN_SET(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) | (v))) -#define HW_USB_TOKEN_CLR(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) & ~(v))) -#define HW_USB_TOKEN_TOG(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_TOKEN bitfields - */ - -/*! - * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW) - * - * Holds the Endpoint address for the token command. The four bit value written - * must be a valid endpoint. - */ -/*@{*/ -#define BP_USB_TOKEN_TOKENENDPT (0U) /*!< Bit position for USB_TOKEN_TOKENENDPT. */ -#define BM_USB_TOKEN_TOKENENDPT (0x0FU) /*!< Bit mask for USB_TOKEN_TOKENENDPT. */ -#define BS_USB_TOKEN_TOKENENDPT (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENENDPT. */ - -/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */ -#define BR_USB_TOKEN_TOKENENDPT(x) (HW_USB_TOKEN(x).B.TOKENENDPT) - -/*! @brief Format value for bitfield USB_TOKEN_TOKENENDPT. */ -#define BF_USB_TOKEN_TOKENENDPT(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENENDPT) & BM_USB_TOKEN_TOKENENDPT) - -/*! @brief Set the TOKENENDPT field to a new value. */ -#define BW_USB_TOKEN_TOKENENDPT(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v))) -/*@}*/ - -/*! - * @name Register USB_TOKEN, field TOKENPID[7:4] (RW) - * - * Contains the token type executed by the USB module. - * - * Values: - * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction. - * - 1001 - IN Token. USB Module performs an In (RX) transaction. - * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction - */ -/*@{*/ -#define BP_USB_TOKEN_TOKENPID (4U) /*!< Bit position for USB_TOKEN_TOKENPID. */ -#define BM_USB_TOKEN_TOKENPID (0xF0U) /*!< Bit mask for USB_TOKEN_TOKENPID. */ -#define BS_USB_TOKEN_TOKENPID (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENPID. */ - -/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */ -#define BR_USB_TOKEN_TOKENPID(x) (HW_USB_TOKEN(x).B.TOKENPID) - -/*! @brief Format value for bitfield USB_TOKEN_TOKENPID. */ -#define BF_USB_TOKEN_TOKENPID(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENPID) & BM_USB_TOKEN_TOKENPID) - -/*! @brief Set the TOKENPID field to a new value. */ -#define BW_USB_TOKEN_TOKENPID(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v))) -/*@}*/ - -/******************************************************************************* - * HW_USB_SOFTHLD - SOF Threshold register - ******************************************************************************/ - -/*! - * @brief HW_USB_SOFTHLD - SOF Threshold register (RW) - * - * Reset value: 0x00U - * - * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in - * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The - * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with - * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF) - * token is transmitted. The SOF threshold register is used to program the number - * of USB byte times before the SOF to stop initiating token packet transactions. - * This register must be set to a value that ensures that other packets are not - * actively being transmitted when the SOF time counts to zero. When the SOF - * counter reaches the threshold value, no more tokens are transmitted until after the - * SOF has been transmitted. The value programmed into the threshold register - * must reserve enough time to ensure the worst case transaction completes. In - * general the worst case transaction is an IN token followed by a data packet from - * the target followed by the response from the host. The actual time required is - * a function of the maximum packet size on the bus. Typical values for the SOF - * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26; - * 8-byte packets=18. - */ -typedef union _hw_usb_softhld -{ - uint8_t U; - struct _hw_usb_softhld_bitfields - { - uint8_t CNT : 8; /*!< [7:0] */ - } B; -} hw_usb_softhld_t; - -/*! - * @name Constants and macros for entire USB_SOFTHLD register - */ -/*@{*/ -#define HW_USB_SOFTHLD_ADDR(x) ((x) + 0xACU) - -#define HW_USB_SOFTHLD(x) (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR(x)) -#define HW_USB_SOFTHLD_RD(x) (HW_USB_SOFTHLD(x).U) -#define HW_USB_SOFTHLD_WR(x, v) (HW_USB_SOFTHLD(x).U = (v)) -#define HW_USB_SOFTHLD_SET(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) | (v))) -#define HW_USB_SOFTHLD_CLR(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) & ~(v))) -#define HW_USB_SOFTHLD_TOG(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_SOFTHLD bitfields - */ - -/*! - * @name Register USB_SOFTHLD, field CNT[7:0] (RW) - * - * Represents the SOF count threshold in byte times. - */ -/*@{*/ -#define BP_USB_SOFTHLD_CNT (0U) /*!< Bit position for USB_SOFTHLD_CNT. */ -#define BM_USB_SOFTHLD_CNT (0xFFU) /*!< Bit mask for USB_SOFTHLD_CNT. */ -#define BS_USB_SOFTHLD_CNT (8U) /*!< Bit field size in bits for USB_SOFTHLD_CNT. */ - -/*! @brief Read current value of the USB_SOFTHLD_CNT field. */ -#define BR_USB_SOFTHLD_CNT(x) (HW_USB_SOFTHLD(x).U) - -/*! @brief Format value for bitfield USB_SOFTHLD_CNT. */ -#define BF_USB_SOFTHLD_CNT(v) ((uint8_t)((uint8_t)(v) << BP_USB_SOFTHLD_CNT) & BM_USB_SOFTHLD_CNT) - -/*! @brief Set the CNT field to a new value. */ -#define BW_USB_SOFTHLD_CNT(x, v) (HW_USB_SOFTHLD_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_BDTPAGE2 - BDT Page Register 2 - ******************************************************************************/ - -/*! - * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW) - * - * Reset value: 0x00U - * - * Contains an 8-bit value used to compute the address where the current Buffer - * Descriptor Table (BDT) resides in system memory. - */ -typedef union _hw_usb_bdtpage2 -{ - uint8_t U; - struct _hw_usb_bdtpage2_bitfields - { - uint8_t BDTBA : 8; /*!< [7:0] */ - } B; -} hw_usb_bdtpage2_t; - -/*! - * @name Constants and macros for entire USB_BDTPAGE2 register - */ -/*@{*/ -#define HW_USB_BDTPAGE2_ADDR(x) ((x) + 0xB0U) - -#define HW_USB_BDTPAGE2(x) (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR(x)) -#define HW_USB_BDTPAGE2_RD(x) (HW_USB_BDTPAGE2(x).U) -#define HW_USB_BDTPAGE2_WR(x, v) (HW_USB_BDTPAGE2(x).U = (v)) -#define HW_USB_BDTPAGE2_SET(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) | (v))) -#define HW_USB_BDTPAGE2_CLR(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) & ~(v))) -#define HW_USB_BDTPAGE2_TOG(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_BDTPAGE2 bitfields - */ - -/*! - * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW) - * - * Provides address bits 23 through 16 of the BDT base address that defines the - * location of Buffer Descriptor Table resides in system memory. - */ -/*@{*/ -#define BP_USB_BDTPAGE2_BDTBA (0U) /*!< Bit position for USB_BDTPAGE2_BDTBA. */ -#define BM_USB_BDTPAGE2_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE2_BDTBA. */ -#define BS_USB_BDTPAGE2_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE2_BDTBA. */ - -/*! @brief Read current value of the USB_BDTPAGE2_BDTBA field. */ -#define BR_USB_BDTPAGE2_BDTBA(x) (HW_USB_BDTPAGE2(x).U) - -/*! @brief Format value for bitfield USB_BDTPAGE2_BDTBA. */ -#define BF_USB_BDTPAGE2_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE2_BDTBA) & BM_USB_BDTPAGE2_BDTBA) - -/*! @brief Set the BDTBA field to a new value. */ -#define BW_USB_BDTPAGE2_BDTBA(x, v) (HW_USB_BDTPAGE2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_BDTPAGE3 - BDT Page Register 3 - ******************************************************************************/ - -/*! - * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW) - * - * Reset value: 0x00U - * - * Contains an 8-bit value used to compute the address where the current Buffer - * Descriptor Table (BDT) resides in system memory. - */ -typedef union _hw_usb_bdtpage3 -{ - uint8_t U; - struct _hw_usb_bdtpage3_bitfields - { - uint8_t BDTBA : 8; /*!< [7:0] */ - } B; -} hw_usb_bdtpage3_t; - -/*! - * @name Constants and macros for entire USB_BDTPAGE3 register - */ -/*@{*/ -#define HW_USB_BDTPAGE3_ADDR(x) ((x) + 0xB4U) - -#define HW_USB_BDTPAGE3(x) (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR(x)) -#define HW_USB_BDTPAGE3_RD(x) (HW_USB_BDTPAGE3(x).U) -#define HW_USB_BDTPAGE3_WR(x, v) (HW_USB_BDTPAGE3(x).U = (v)) -#define HW_USB_BDTPAGE3_SET(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) | (v))) -#define HW_USB_BDTPAGE3_CLR(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) & ~(v))) -#define HW_USB_BDTPAGE3_TOG(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_BDTPAGE3 bitfields - */ - -/*! - * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW) - * - * Provides address bits 31 through 24 of the BDT base address that defines the - * location of Buffer Descriptor Table resides in system memory. - */ -/*@{*/ -#define BP_USB_BDTPAGE3_BDTBA (0U) /*!< Bit position for USB_BDTPAGE3_BDTBA. */ -#define BM_USB_BDTPAGE3_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE3_BDTBA. */ -#define BS_USB_BDTPAGE3_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE3_BDTBA. */ - -/*! @brief Read current value of the USB_BDTPAGE3_BDTBA field. */ -#define BR_USB_BDTPAGE3_BDTBA(x) (HW_USB_BDTPAGE3(x).U) - -/*! @brief Format value for bitfield USB_BDTPAGE3_BDTBA. */ -#define BF_USB_BDTPAGE3_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE3_BDTBA) & BM_USB_BDTPAGE3_BDTBA) - -/*! @brief Set the BDTBA field to a new value. */ -#define BW_USB_BDTPAGE3_BDTBA(x, v) (HW_USB_BDTPAGE3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ENDPTn - Endpoint Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_ENDPTn - Endpoint Control register (RW) - * - * Reset value: 0x00U - * - * Contains the endpoint control bits for each of the 16 endpoints available - * within the USB module for a decoded address. The format for these registers is - * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control - * pipe 0, which is required for all USB functions. Therefore, after a USBRST - * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode - * ENDPT0 is used to determine the handshake, retry and low speed - * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK - * bit should be 1. For Isochronous transfers it should be 0. Common values to - * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, - * and 0x4C for Isochronous transfers. - */ -typedef union _hw_usb_endptn -{ - uint8_t U; - struct _hw_usb_endptn_bitfields - { - uint8_t EPHSHK : 1; /*!< [0] */ - uint8_t EPSTALL : 1; /*!< [1] */ - uint8_t EPTXEN : 1; /*!< [2] */ - uint8_t EPRXEN : 1; /*!< [3] */ - uint8_t EPCTLDIS : 1; /*!< [4] */ - uint8_t RESERVED0 : 1; /*!< [5] */ - uint8_t RETRYDIS : 1; /*!< [6] */ - uint8_t HOSTWOHUB : 1; /*!< [7] */ - } B; -} hw_usb_endptn_t; - -/*! - * @name Constants and macros for entire USB_ENDPTn register - */ -/*@{*/ -#define HW_USB_ENDPTn_COUNT (16U) - -#define HW_USB_ENDPTn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n))) - -#define HW_USB_ENDPTn(x, n) (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(x, n)) -#define HW_USB_ENDPTn_RD(x, n) (HW_USB_ENDPTn(x, n).U) -#define HW_USB_ENDPTn_WR(x, n, v) (HW_USB_ENDPTn(x, n).U = (v)) -#define HW_USB_ENDPTn_SET(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) | (v))) -#define HW_USB_ENDPTn_CLR(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) & ~(v))) -#define HW_USB_ENDPTn_TOG(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ENDPTn bitfields - */ - -/*! - * @name Register USB_ENDPTn, field EPHSHK[0] (RW) - * - * When set this bit enables an endpoint to perform handshaking during a - * transaction to this endpoint. This bit is generally 1 unless the endpoint is - * Isochronous. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPHSHK (0U) /*!< Bit position for USB_ENDPTn_EPHSHK. */ -#define BM_USB_ENDPTn_EPHSHK (0x01U) /*!< Bit mask for USB_ENDPTn_EPHSHK. */ -#define BS_USB_ENDPTn_EPHSHK (1U) /*!< Bit field size in bits for USB_ENDPTn_EPHSHK. */ - -/*! @brief Read current value of the USB_ENDPTn_EPHSHK field. */ -#define BR_USB_ENDPTn_EPHSHK(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPHSHK. */ -#define BF_USB_ENDPTn_EPHSHK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPHSHK) & BM_USB_ENDPTn_EPHSHK) - -/*! @brief Set the EPHSHK field to a new value. */ -#define BW_USB_ENDPTn_EPHSHK(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPSTALL[1] (RW) - * - * When set this bit indicates that the endpoint is called. This bit has - * priority over all other control bits in the EndPoint Enable Register, but it is only - * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB - * Module to return a STALL handshake. After an endpoint is stalled it requires - * intervention from the Host Controller. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPSTALL (1U) /*!< Bit position for USB_ENDPTn_EPSTALL. */ -#define BM_USB_ENDPTn_EPSTALL (0x02U) /*!< Bit mask for USB_ENDPTn_EPSTALL. */ -#define BS_USB_ENDPTn_EPSTALL (1U) /*!< Bit field size in bits for USB_ENDPTn_EPSTALL. */ - -/*! @brief Read current value of the USB_ENDPTn_EPSTALL field. */ -#define BR_USB_ENDPTn_EPSTALL(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPSTALL. */ -#define BF_USB_ENDPTn_EPSTALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPSTALL) & BM_USB_ENDPTn_EPSTALL) - -/*! @brief Set the EPSTALL field to a new value. */ -#define BW_USB_ENDPTn_EPSTALL(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPTXEN[2] (RW) - * - * This bit, when set, enables the endpoint for TX transfers. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */ -#define BM_USB_ENDPTn_EPTXEN (0x04U) /*!< Bit mask for USB_ENDPTn_EPTXEN. */ -#define BS_USB_ENDPTn_EPTXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPTXEN. */ - -/*! @brief Read current value of the USB_ENDPTn_EPTXEN field. */ -#define BR_USB_ENDPTn_EPTXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPTXEN. */ -#define BF_USB_ENDPTn_EPTXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPTXEN) & BM_USB_ENDPTn_EPTXEN) - -/*! @brief Set the EPTXEN field to a new value. */ -#define BW_USB_ENDPTn_EPTXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPRXEN[3] (RW) - * - * This bit, when set, enables the endpoint for RX transfers. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */ -#define BM_USB_ENDPTn_EPRXEN (0x08U) /*!< Bit mask for USB_ENDPTn_EPRXEN. */ -#define BS_USB_ENDPTn_EPRXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPRXEN. */ - -/*! @brief Read current value of the USB_ENDPTn_EPRXEN field. */ -#define BR_USB_ENDPTn_EPRXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPRXEN. */ -#define BF_USB_ENDPTn_EPRXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPRXEN) & BM_USB_ENDPTn_EPRXEN) - -/*! @brief Set the EPRXEN field to a new value. */ -#define BW_USB_ENDPTn_EPRXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW) - * - * This bit, when set, disables control (SETUP) transfers. When cleared, control - * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits - * are also set. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */ -#define BM_USB_ENDPTn_EPCTLDIS (0x10U) /*!< Bit mask for USB_ENDPTn_EPCTLDIS. */ -#define BS_USB_ENDPTn_EPCTLDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_EPCTLDIS. */ - -/*! @brief Read current value of the USB_ENDPTn_EPCTLDIS field. */ -#define BR_USB_ENDPTn_EPCTLDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS. */ -#define BF_USB_ENDPTn_EPCTLDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPCTLDIS) & BM_USB_ENDPTn_EPCTLDIS) - -/*! @brief Set the EPCTLDIS field to a new value. */ -#define BW_USB_ENDPTn_EPCTLDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field RETRYDIS[6] (RW) - * - * This is a Host mode only bit and is present in the control register for - * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed - * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID - * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When - * this bit is cleared, NAKed transactions are retried in hardware. This bit must - * be set when the host is attempting to poll an interrupt endpoint. - */ -/*@{*/ -#define BP_USB_ENDPTn_RETRYDIS (6U) /*!< Bit position for USB_ENDPTn_RETRYDIS. */ -#define BM_USB_ENDPTn_RETRYDIS (0x40U) /*!< Bit mask for USB_ENDPTn_RETRYDIS. */ -#define BS_USB_ENDPTn_RETRYDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_RETRYDIS. */ - -/*! @brief Read current value of the USB_ENDPTn_RETRYDIS field. */ -#define BR_USB_ENDPTn_RETRYDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS)) - -/*! @brief Format value for bitfield USB_ENDPTn_RETRYDIS. */ -#define BF_USB_ENDPTn_RETRYDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_RETRYDIS) & BM_USB_ENDPTn_RETRYDIS) - -/*! @brief Set the RETRYDIS field to a new value. */ -#define BW_USB_ENDPTn_RETRYDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW) - * - * This is a Host mode only field and is present in the control register for - * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a - * directly connected low speed device. When cleared, the host produces the - * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed - * device as required to communicate with a low speed device through a hub. - */ -/*@{*/ -#define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */ -#define BM_USB_ENDPTn_HOSTWOHUB (0x80U) /*!< Bit mask for USB_ENDPTn_HOSTWOHUB. */ -#define BS_USB_ENDPTn_HOSTWOHUB (1U) /*!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB. */ - -/*! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field. */ -#define BR_USB_ENDPTn_HOSTWOHUB(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB)) - -/*! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB. */ -#define BF_USB_ENDPTn_HOSTWOHUB(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_HOSTWOHUB) & BM_USB_ENDPTn_HOSTWOHUB) - -/*! @brief Set the HOSTWOHUB field to a new value. */ -#define BW_USB_ENDPTn_HOSTWOHUB(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_USBCTRL - USB Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_USBCTRL - USB Control register (RW) - * - * Reset value: 0xC0U - */ -typedef union _hw_usb_usbctrl -{ - uint8_t U; - struct _hw_usb_usbctrl_bitfields - { - uint8_t RESERVED0 : 6; /*!< [5:0] */ - uint8_t PDE : 1; /*!< [6] */ - uint8_t SUSP : 1; /*!< [7] */ - } B; -} hw_usb_usbctrl_t; - -/*! - * @name Constants and macros for entire USB_USBCTRL register - */ -/*@{*/ -#define HW_USB_USBCTRL_ADDR(x) ((x) + 0x100U) - -#define HW_USB_USBCTRL(x) (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR(x)) -#define HW_USB_USBCTRL_RD(x) (HW_USB_USBCTRL(x).U) -#define HW_USB_USBCTRL_WR(x, v) (HW_USB_USBCTRL(x).U = (v)) -#define HW_USB_USBCTRL_SET(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) | (v))) -#define HW_USB_USBCTRL_CLR(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) & ~(v))) -#define HW_USB_USBCTRL_TOG(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_USBCTRL bitfields - */ - -/*! - * @name Register USB_USBCTRL, field PDE[6] (RW) - * - * Enables the weak pulldowns on the USB transceiver. - * - * Values: - * - 0 - Weak pulldowns are disabled on D+ and D-. - * - 1 - Weak pulldowns are enabled on D+ and D-. - */ -/*@{*/ -#define BP_USB_USBCTRL_PDE (6U) /*!< Bit position for USB_USBCTRL_PDE. */ -#define BM_USB_USBCTRL_PDE (0x40U) /*!< Bit mask for USB_USBCTRL_PDE. */ -#define BS_USB_USBCTRL_PDE (1U) /*!< Bit field size in bits for USB_USBCTRL_PDE. */ - -/*! @brief Read current value of the USB_USBCTRL_PDE field. */ -#define BR_USB_USBCTRL_PDE(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE)) - -/*! @brief Format value for bitfield USB_USBCTRL_PDE. */ -#define BF_USB_USBCTRL_PDE(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_PDE) & BM_USB_USBCTRL_PDE) - -/*! @brief Set the PDE field to a new value. */ -#define BW_USB_USBCTRL_PDE(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE) = (v)) -/*@}*/ - -/*! - * @name Register USB_USBCTRL, field SUSP[7] (RW) - * - * Places the USB transceiver into the suspend state. - * - * Values: - * - 0 - USB transceiver is not in suspend state. - * - 1 - USB transceiver is in suspend state. - */ -/*@{*/ -#define BP_USB_USBCTRL_SUSP (7U) /*!< Bit position for USB_USBCTRL_SUSP. */ -#define BM_USB_USBCTRL_SUSP (0x80U) /*!< Bit mask for USB_USBCTRL_SUSP. */ -#define BS_USB_USBCTRL_SUSP (1U) /*!< Bit field size in bits for USB_USBCTRL_SUSP. */ - -/*! @brief Read current value of the USB_USBCTRL_SUSP field. */ -#define BR_USB_USBCTRL_SUSP(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP)) - -/*! @brief Format value for bitfield USB_USBCTRL_SUSP. */ -#define BF_USB_USBCTRL_SUSP(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_SUSP) & BM_USB_USBCTRL_SUSP) - -/*! @brief Set the SUSP field to a new value. */ -#define BW_USB_USBCTRL_SUSP(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OBSERVE - USB OTG Observe register - ******************************************************************************/ - -/*! - * @brief HW_USB_OBSERVE - USB OTG Observe register (RO) - * - * Reset value: 0x50U - * - * Provides visibility on the state of the pull-ups and pull-downs at the - * transceiver. Useful when interfacing to an external OTG control module via a serial - * interface. - */ -typedef union _hw_usb_observe -{ - uint8_t U; - struct _hw_usb_observe_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t DMPD : 1; /*!< [4] */ - uint8_t RESERVED1 : 1; /*!< [5] */ - uint8_t DPPD : 1; /*!< [6] */ - uint8_t DPPU : 1; /*!< [7] */ - } B; -} hw_usb_observe_t; - -/*! - * @name Constants and macros for entire USB_OBSERVE register - */ -/*@{*/ -#define HW_USB_OBSERVE_ADDR(x) ((x) + 0x104U) - -#define HW_USB_OBSERVE(x) (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR(x)) -#define HW_USB_OBSERVE_RD(x) (HW_USB_OBSERVE(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_OBSERVE bitfields - */ - -/*! - * @name Register USB_OBSERVE, field DMPD[4] (RO) - * - * Provides observability of the D- Pulldown enable at the USB transceiver. - * - * Values: - * - 0 - D- pulldown disabled. - * - 1 - D- pulldown enabled. - */ -/*@{*/ -#define BP_USB_OBSERVE_DMPD (4U) /*!< Bit position for USB_OBSERVE_DMPD. */ -#define BM_USB_OBSERVE_DMPD (0x10U) /*!< Bit mask for USB_OBSERVE_DMPD. */ -#define BS_USB_OBSERVE_DMPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DMPD. */ - -/*! @brief Read current value of the USB_OBSERVE_DMPD field. */ -#define BR_USB_OBSERVE_DMPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DMPD)) -/*@}*/ - -/*! - * @name Register USB_OBSERVE, field DPPD[6] (RO) - * - * Provides observability of the D+ Pulldown enable at the USB transceiver. - * - * Values: - * - 0 - D+ pulldown disabled. - * - 1 - D+ pulldown enabled. - */ -/*@{*/ -#define BP_USB_OBSERVE_DPPD (6U) /*!< Bit position for USB_OBSERVE_DPPD. */ -#define BM_USB_OBSERVE_DPPD (0x40U) /*!< Bit mask for USB_OBSERVE_DPPD. */ -#define BS_USB_OBSERVE_DPPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPD. */ - -/*! @brief Read current value of the USB_OBSERVE_DPPD field. */ -#define BR_USB_OBSERVE_DPPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPD)) -/*@}*/ - -/*! - * @name Register USB_OBSERVE, field DPPU[7] (RO) - * - * Provides observability of the D+ Pullup enable at the USB transceiver. - * - * Values: - * - 0 - D+ pullup disabled. - * - 1 - D+ pullup enabled. - */ -/*@{*/ -#define BP_USB_OBSERVE_DPPU (7U) /*!< Bit position for USB_OBSERVE_DPPU. */ -#define BM_USB_OBSERVE_DPPU (0x80U) /*!< Bit mask for USB_OBSERVE_DPPU. */ -#define BS_USB_OBSERVE_DPPU (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPU. */ - -/*! @brief Read current value of the USB_OBSERVE_DPPU field. */ -#define BR_USB_OBSERVE_DPPU(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPU)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CONTROL - USB OTG Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_CONTROL - USB OTG Control register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_usb_control -{ - uint8_t U; - struct _hw_usb_control_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t DPPULLUPNONOTG : 1; /*!< [4] */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_usb_control_t; - -/*! - * @name Constants and macros for entire USB_CONTROL register - */ -/*@{*/ -#define HW_USB_CONTROL_ADDR(x) ((x) + 0x108U) - -#define HW_USB_CONTROL(x) (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR(x)) -#define HW_USB_CONTROL_RD(x) (HW_USB_CONTROL(x).U) -#define HW_USB_CONTROL_WR(x, v) (HW_USB_CONTROL(x).U = (v)) -#define HW_USB_CONTROL_SET(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) | (v))) -#define HW_USB_CONTROL_CLR(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) & ~(v))) -#define HW_USB_CONTROL_TOG(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CONTROL bitfields - */ - -/*! - * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW) - * - * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG - * device mode. - * - * Values: - * - 0 - DP Pullup in non-OTG device mode is not enabled. - * - 1 - DP Pullup in non-OTG device mode is enabled. - */ -/*@{*/ -#define BP_USB_CONTROL_DPPULLUPNONOTG (4U) /*!< Bit position for USB_CONTROL_DPPULLUPNONOTG. */ -#define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) /*!< Bit mask for USB_CONTROL_DPPULLUPNONOTG. */ -#define BS_USB_CONTROL_DPPULLUPNONOTG (1U) /*!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG. */ - -/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */ -#define BR_USB_CONTROL_DPPULLUPNONOTG(x) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG)) - -/*! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG. */ -#define BF_USB_CONTROL_DPPULLUPNONOTG(v) ((uint8_t)((uint8_t)(v) << BP_USB_CONTROL_DPPULLUPNONOTG) & BM_USB_CONTROL_DPPULLUPNONOTG) - -/*! @brief Set the DPPULLUPNONOTG field to a new value. */ -#define BW_USB_CONTROL_DPPULLUPNONOTG(x, v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_USBTRC0 - USB Transceiver Control register 0 - ******************************************************************************/ - -/*! - * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW) - * - * Reset value: 0x00U - * - * Includes signals for basic operation of the on-chip USB Full Speed - * transceiver and configuration of the USB data connection that are not otherwise included - * in the USB Full Speed controller registers. - */ -typedef union _hw_usb_usbtrc0 -{ - uint8_t U; - struct _hw_usb_usbtrc0_bitfields - { - uint8_t USB_RESUME_INT : 1; /*!< [0] USB Asynchronous Interrupt */ - uint8_t SYNC_DET : 1; /*!< [1] Synchronous USB Interrupt Detect */ - uint8_t USB_CLK_RECOVERY_INT : 1; /*!< [2] Combined USB Clock - * Recovery interrupt status */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t USBRESMEN : 1; /*!< [5] Asynchronous Resume Interrupt Enable - * */ - uint8_t RESERVED1 : 1; /*!< [6] */ - uint8_t USBRESET : 1; /*!< [7] USB Reset */ - } B; -} hw_usb_usbtrc0_t; - -/*! - * @name Constants and macros for entire USB_USBTRC0 register - */ -/*@{*/ -#define HW_USB_USBTRC0_ADDR(x) ((x) + 0x10CU) - -#define HW_USB_USBTRC0(x) (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR(x)) -#define HW_USB_USBTRC0_RD(x) (HW_USB_USBTRC0(x).U) -#define HW_USB_USBTRC0_WR(x, v) (HW_USB_USBTRC0(x).U = (v)) -#define HW_USB_USBTRC0_SET(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) | (v))) -#define HW_USB_USBTRC0_CLR(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) & ~(v))) -#define HW_USB_USBTRC0_TOG(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_USBTRC0 bitfields - */ - -/*! - * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO) - * - * Values: - * - 0 - No interrupt was generated. - * - 1 - Interrupt was generated because of the USB asynchronous interrupt. - */ -/*@{*/ -#define BP_USB_USBTRC0_USB_RESUME_INT (0U) /*!< Bit position for USB_USBTRC0_USB_RESUME_INT. */ -#define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) /*!< Bit mask for USB_USBTRC0_USB_RESUME_INT. */ -#define BS_USB_USBTRC0_USB_RESUME_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT. */ - -/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */ -#define BR_USB_USBTRC0_USB_RESUME_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_RESUME_INT)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field SYNC_DET[1] (RO) - * - * Values: - * - 0 - Synchronous interrupt has not been detected. - * - 1 - Synchronous interrupt has been detected. - */ -/*@{*/ -#define BP_USB_USBTRC0_SYNC_DET (1U) /*!< Bit position for USB_USBTRC0_SYNC_DET. */ -#define BM_USB_USBTRC0_SYNC_DET (0x02U) /*!< Bit mask for USB_USBTRC0_SYNC_DET. */ -#define BS_USB_USBTRC0_SYNC_DET (1U) /*!< Bit field size in bits for USB_USBTRC0_SYNC_DET. */ - -/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */ -#define BR_USB_USBTRC0_SYNC_DET(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_SYNC_DET)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO) - * - * This read-only field will be set to value high at 1'b1 when any of USB clock - * recovery interrupt conditions are detected and those interrupts are unmasked. - * For customer use the only unmasked USB clock recovery interrupt condition - * results from an overflow of the frequency trim setting values indicating that the - * frequency trim calculated is out of the adjustment range of the IRC48M output - * clock. To clear this bit after it has been set, Write 0xFF to register - * USB_CLK_RECOVER_INT_STATUS. - */ -/*@{*/ -#define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) /*!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ -#define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) /*!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ -#define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ - -/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */ -#define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_CLK_RECOVERY_INT)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field USBRESMEN[5] (RW) - * - * This bit, when set, allows the USB module to send an asynchronous wakeup - * event to the MCU upon detection of resume signaling on the USB bus. The MCU then - * re-enables clocks to the USB module. It is used for low-power suspend mode when - * USB module clocks are stopped or the USB transceiver is in Suspend mode. - * Async wakeup only works in device mode. - * - * Values: - * - 0 - USB asynchronous wakeup from suspend mode disabled. - * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous - * resume interrupt differs from the synchronous resume interrupt in that it - * asynchronously detects K-state using the unfiltered state of the D+ and D- - * pins. This interrupt should only be enabled when the Transceiver is - * suspended. - */ -/*@{*/ -#define BP_USB_USBTRC0_USBRESMEN (5U) /*!< Bit position for USB_USBTRC0_USBRESMEN. */ -#define BM_USB_USBTRC0_USBRESMEN (0x20U) /*!< Bit mask for USB_USBTRC0_USBRESMEN. */ -#define BS_USB_USBTRC0_USBRESMEN (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESMEN. */ - -/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */ -#define BR_USB_USBTRC0_USBRESMEN(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN)) - -/*! @brief Format value for bitfield USB_USBTRC0_USBRESMEN. */ -#define BF_USB_USBTRC0_USBRESMEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESMEN) & BM_USB_USBTRC0_USBRESMEN) - -/*! @brief Set the USBRESMEN field to a new value. */ -#define BW_USB_USBTRC0_USBRESMEN(x, v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field USBRESET[7] (WO) - * - * Generates a hard reset to USBOTG. After this bit is set and the reset occurs, - * this bit is automatically cleared. This bit is always read as zero. Wait two - * USB clock cycles after setting this bit. - * - * Values: - * - 0 - Normal USB module operation. - * - 1 - Returns the USB module to its reset state. - */ -/*@{*/ -#define BP_USB_USBTRC0_USBRESET (7U) /*!< Bit position for USB_USBTRC0_USBRESET. */ -#define BM_USB_USBTRC0_USBRESET (0x80U) /*!< Bit mask for USB_USBTRC0_USBRESET. */ -#define BS_USB_USBTRC0_USBRESET (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESET. */ - -/*! @brief Format value for bitfield USB_USBTRC0_USBRESET. */ -#define BF_USB_USBTRC0_USBRESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESET) & BM_USB_USBTRC0_USBRESET) -/*@}*/ - -/******************************************************************************* - * HW_USB_USBFRMADJUST - Frame Adjust Register - ******************************************************************************/ - -/*! - * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_usb_usbfrmadjust -{ - uint8_t U; - struct _hw_usb_usbfrmadjust_bitfields - { - uint8_t ADJ : 8; /*!< [7:0] Frame Adjustment */ - } B; -} hw_usb_usbfrmadjust_t; - -/*! - * @name Constants and macros for entire USB_USBFRMADJUST register - */ -/*@{*/ -#define HW_USB_USBFRMADJUST_ADDR(x) ((x) + 0x114U) - -#define HW_USB_USBFRMADJUST(x) (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR(x)) -#define HW_USB_USBFRMADJUST_RD(x) (HW_USB_USBFRMADJUST(x).U) -#define HW_USB_USBFRMADJUST_WR(x, v) (HW_USB_USBFRMADJUST(x).U = (v)) -#define HW_USB_USBFRMADJUST_SET(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) | (v))) -#define HW_USB_USBFRMADJUST_CLR(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) & ~(v))) -#define HW_USB_USBFRMADJUST_TOG(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_USBFRMADJUST bitfields - */ - -/*! - * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW) - * - * In Host mode, the frame adjustment is a twos complement number that adjusts - * the period of each USB frame in 12-MHz clock periods. A SOF is normally - * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this - * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock. - * Changes to the ADJ bit take effect at the next start of the next frame. - */ -/*@{*/ -#define BP_USB_USBFRMADJUST_ADJ (0U) /*!< Bit position for USB_USBFRMADJUST_ADJ. */ -#define BM_USB_USBFRMADJUST_ADJ (0xFFU) /*!< Bit mask for USB_USBFRMADJUST_ADJ. */ -#define BS_USB_USBFRMADJUST_ADJ (8U) /*!< Bit field size in bits for USB_USBFRMADJUST_ADJ. */ - -/*! @brief Read current value of the USB_USBFRMADJUST_ADJ field. */ -#define BR_USB_USBFRMADJUST_ADJ(x) (HW_USB_USBFRMADJUST(x).U) - -/*! @brief Format value for bitfield USB_USBFRMADJUST_ADJ. */ -#define BF_USB_USBFRMADJUST_ADJ(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBFRMADJUST_ADJ) & BM_USB_USBFRMADJUST_ADJ) - -/*! @brief Set the ADJ field to a new value. */ -#define BW_USB_USBFRMADJUST_ADJ(x, v) (HW_USB_USBFRMADJUST_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW) - * - * Reset value: 0x00U - * - * Signals in this register control the crystal-less USB clock mode in which the - * internal IRC48M oscillator is tuned to match the clock extracted from the - * incoming USB data stream. The IRC48M internal oscillator module must be enabled - * in register USB_CLK_RECOVER_IRC_EN for this mode. - */ -typedef union _hw_usb_clk_recover_ctrl -{ - uint8_t U; - struct _hw_usb_clk_recover_ctrl_bitfields - { - uint8_t RESERVED0 : 5; /*!< [4:0] */ - uint8_t RESTART_IFRTRIM_EN : 1; /*!< [5] Restart from IFR trim value - * */ - uint8_t RESET_RESUME_ROUGH_EN : 1; /*!< [6] Reset/resume to rough - * phase enable */ - uint8_t CLOCK_RECOVER_EN : 1; /*!< [7] Crystal-less USB enable */ - } B; -} hw_usb_clk_recover_ctrl_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_CTRL_ADDR(x) ((x) + 0x140U) - -#define HW_USB_CLK_RECOVER_CTRL(x) (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR(x)) -#define HW_USB_CLK_RECOVER_CTRL_RD(x) (HW_USB_CLK_RECOVER_CTRL(x).U) -#define HW_USB_CLK_RECOVER_CTRL_WR(x, v) (HW_USB_CLK_RECOVER_CTRL(x).U = (v)) -#define HW_USB_CLK_RECOVER_CTRL_SET(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_CTRL_CLR(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_CTRL_TOG(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW) - * - * IRC48 has a default trim fine value whose default value is factory trimmed - * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz - * and keeps updating the trim fine value accordingly - * - * Values: - * - 0 - Trim fine adjustment always works based on the previous updated trim - * fine value (default) - * - 1 - Trim fine restarts from the IFR trim value whenever - * bus_reset/bus_resume is detected or module enable is desasserted - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ -#define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ -#define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */ -#define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ -#define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) - -/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW) - * - * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock. - * It has two phases after user enables clock_recover_en bit, rough phase and - * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine - * value is different during these two phases. The step in rough phase is larger - * than that in tracking phase. Switch back to rough stage whenever USB bus reset - * or bus resume occurs. - * - * Values: - * - 0 - Always works in tracking phase after the 1st time rough to track - * transition (default) - * - 1 - Go back to rough stage whenever bus reset or bus resume occurs - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ -#define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ -#define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */ -#define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ -#define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) - -/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW) - * - * This bit must be enabled if user wants to use the crystal-less USB mode for - * the Full Speed USB controller and transceiver. This bit should not be set for - * USB host mode or OTG. - * - * Values: - * - 0 - Disable clock recovery block (default) - * - 1 - Enable clock recovery block - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) /*!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ -#define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ -#define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */ -#define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ -#define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) - -/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW) - * - * Reset value: 0x01U - * - * Controls basic operation of the on-chip IRC48M module used to produce nominal - * 48MHz clocks for USB crystal-less operation and other functions. See - * additional information about the IRC48M operation in the Clock Distribution chapter. - */ -typedef union _hw_usb_clk_recover_irc_en -{ - uint8_t U; - struct _hw_usb_clk_recover_irc_en_bitfields - { - uint8_t REG_EN : 1; /*!< [0] IRC48M regulator enable */ - uint8_t IRC_EN : 1; /*!< [1] IRC48M enable */ - uint8_t RESERVED0 : 6; /*!< [7:2] */ - } B; -} hw_usb_clk_recover_irc_en_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_IRC_EN_ADDR(x) ((x) + 0x144U) - -#define HW_USB_CLK_RECOVER_IRC_EN(x) (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR(x)) -#define HW_USB_CLK_RECOVER_IRC_EN_RD(x) (HW_USB_CLK_RECOVER_IRC_EN(x).U) -#define HW_USB_CLK_RECOVER_IRC_EN_WR(x, v) (HW_USB_CLK_RECOVER_IRC_EN(x).U = (v)) -#define HW_USB_CLK_RECOVER_IRC_EN_SET(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_IRC_EN_CLR(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_IRC_EN_TOG(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW) - * - * This bit is used to enable the local analog regulator for IRC48Mhz module. - * This bit must be set if user wants to use the crystal-less USB clock - * configuration. - * - * Values: - * - 0 - IRC48M local regulator is disabled - * - 1 - IRC48M local regulator is enabled (default) - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN. */ -#define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN. */ -#define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */ -#define BR_USB_CLK_RECOVER_IRC_EN_REG_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN. */ -#define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN) - -/*! @brief Set the REG_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW) - * - * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for - * crystal-less USB. It can only be used for FS USB device mode operation. This - * bit must be set before using the crystal-less USB clock configuration. - * - * Values: - * - 0 - Disable the IRC48M module (default) - * - 1 - Enable the IRC48M module - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ -#define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ -#define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */ -#define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN. */ -#define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN) - -/*! @brief Set the IRC_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C) - * - * Reset value: 0x00U - * - * A Write operation with value high at 1'b1 on any combination of individual - * bits will clear those bits. - */ -typedef union _hw_usb_clk_recover_int_status -{ - uint8_t U; - struct _hw_usb_clk_recover_int_status_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t OVF_ERROR : 1; /*!< [4] */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_usb_clk_recover_int_status_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x) ((x) + 0x15CU) - -#define HW_USB_CLK_RECOVER_INT_STATUS(x) (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x)) -#define HW_USB_CLK_RECOVER_INT_STATUS_RD(x) (HW_USB_CLK_RECOVER_INT_STATUS(x).U) -#define HW_USB_CLK_RECOVER_INT_STATUS_WR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS(x).U = (v)) -#define HW_USB_CLK_RECOVER_INT_STATUS_SET(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_INT_STATUS_CLR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_INT_STATUS_TOG(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C) - * - * Indicates that the USB clock recovery algorithm has detected that the - * frequency trim adjustment needed for the IRC48M output clock is outside the available - * TRIM_FINE adjustment range for the IRC48M module. - * - * Values: - * - 0 - No interrupt is reported - * - 1 - Unmasked interrupt has been generated - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) /*!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ -#define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ -#define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */ -#define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ -#define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) - -/*! @brief Set the OVF_ERROR field to a new value. */ -#define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_usb_t - module struct - ******************************************************************************/ -/*! - * @brief All USB module registers. - */ -#pragma pack(1) -typedef struct _hw_usb -{ - __I hw_usb_perid_t PERID; /*!< [0x0] Peripheral ID register */ - uint8_t _reserved0[3]; - __I hw_usb_idcomp_t IDCOMP; /*!< [0x4] Peripheral ID Complement register */ - uint8_t _reserved1[3]; - __I hw_usb_rev_t REV; /*!< [0x8] Peripheral Revision register */ - uint8_t _reserved2[3]; - __I hw_usb_addinfo_t ADDINFO; /*!< [0xC] Peripheral Additional Info register */ - uint8_t _reserved3[3]; - __IO hw_usb_otgistat_t OTGISTAT; /*!< [0x10] OTG Interrupt Status register */ - uint8_t _reserved4[3]; - __IO hw_usb_otgicr_t OTGICR; /*!< [0x14] OTG Interrupt Control register */ - uint8_t _reserved5[3]; - __IO hw_usb_otgstat_t OTGSTAT; /*!< [0x18] OTG Status register */ - uint8_t _reserved6[3]; - __IO hw_usb_otgctl_t OTGCTL; /*!< [0x1C] OTG Control register */ - uint8_t _reserved7[99]; - __IO hw_usb_istat_t ISTAT; /*!< [0x80] Interrupt Status register */ - uint8_t _reserved8[3]; - __IO hw_usb_inten_t INTEN; /*!< [0x84] Interrupt Enable register */ - uint8_t _reserved9[3]; - __IO hw_usb_errstat_t ERRSTAT; /*!< [0x88] Error Interrupt Status register */ - uint8_t _reserved10[3]; - __IO hw_usb_erren_t ERREN; /*!< [0x8C] Error Interrupt Enable register */ - uint8_t _reserved11[3]; - __I hw_usb_stat_t STAT; /*!< [0x90] Status register */ - uint8_t _reserved12[3]; - __IO hw_usb_ctl_t CTL; /*!< [0x94] Control register */ - uint8_t _reserved13[3]; - __IO hw_usb_addr_t ADDR; /*!< [0x98] Address register */ - uint8_t _reserved14[3]; - __IO hw_usb_bdtpage1_t BDTPAGE1; /*!< [0x9C] BDT Page register 1 */ - uint8_t _reserved15[3]; - __IO hw_usb_frmnuml_t FRMNUML; /*!< [0xA0] Frame Number register Low */ - uint8_t _reserved16[3]; - __IO hw_usb_frmnumh_t FRMNUMH; /*!< [0xA4] Frame Number register High */ - uint8_t _reserved17[3]; - __IO hw_usb_token_t TOKEN; /*!< [0xA8] Token register */ - uint8_t _reserved18[3]; - __IO hw_usb_softhld_t SOFTHLD; /*!< [0xAC] SOF Threshold register */ - uint8_t _reserved19[3]; - __IO hw_usb_bdtpage2_t BDTPAGE2; /*!< [0xB0] BDT Page Register 2 */ - uint8_t _reserved20[3]; - __IO hw_usb_bdtpage3_t BDTPAGE3; /*!< [0xB4] BDT Page Register 3 */ - uint8_t _reserved21[11]; - struct { - __IO hw_usb_endptn_t ENDPTn; /*!< [0xC0] Endpoint Control register */ - uint8_t _reserved0[3]; - } ENDPOINT[16]; - __IO hw_usb_usbctrl_t USBCTRL; /*!< [0x100] USB Control register */ - uint8_t _reserved22[3]; - __I hw_usb_observe_t OBSERVE; /*!< [0x104] USB OTG Observe register */ - uint8_t _reserved23[3]; - __IO hw_usb_control_t CONTROL; /*!< [0x108] USB OTG Control register */ - uint8_t _reserved24[3]; - __IO hw_usb_usbtrc0_t USBTRC0; /*!< [0x10C] USB Transceiver Control register 0 */ - uint8_t _reserved25[7]; - __IO hw_usb_usbfrmadjust_t USBFRMADJUST; /*!< [0x114] Frame Adjust Register */ - uint8_t _reserved26[43]; - __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; /*!< [0x140] USB Clock recovery control */ - uint8_t _reserved27[3]; - __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; /*!< [0x144] IRC48M oscillator enable register */ - uint8_t _reserved28[23]; - __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; /*!< [0x15C] Clock recovery separated interrupt status */ -} hw_usb_t; -#pragma pack() - -/*! @brief Macro to access all USB registers. */ -/*! @param x USB module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_USB(USB0_BASE). */ -#define HW_USB(x) (*(hw_usb_t *)(x)) - -#endif /* __HW_USB_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h deleted file mode 100644 index c9030e9d62e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h +++ /dev/null @@ -1,384 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_VREF_REGISTERS_H__ -#define __HW_VREF_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 VREF - * - * Voltage Reference - * - * Registers defined in this header file: - * - HW_VREF_TRM - VREF Trim Register - * - HW_VREF_SC - VREF Status and Control Register - * - * - hw_vref_t - Struct containing all module registers. - */ - -#define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */ - -/******************************************************************************* - * HW_VREF_TRM - VREF Trim Register - ******************************************************************************/ - -/*! - * @brief HW_VREF_TRM - VREF Trim Register (RW) - * - * Reset value: 0x00U - * - * This register contains bits that contain the trim data for the Voltage - * Reference. - */ -typedef union _hw_vref_trm -{ - uint8_t U; - struct _hw_vref_trm_bitfields - { - uint8_t TRIM : 6; /*!< [5:0] Trim bits */ - uint8_t CHOPEN : 1; /*!< [6] Chop oscillator enable. When set, - * internal chopping operation is enabled and the internal analog offset will be - * minimized. */ - uint8_t RESERVED0 : 1; /*!< [7] */ - } B; -} hw_vref_trm_t; - -/*! - * @name Constants and macros for entire VREF_TRM register - */ -/*@{*/ -#define HW_VREF_TRM_ADDR(x) ((x) + 0x0U) - -#define HW_VREF_TRM(x) (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x)) -#define HW_VREF_TRM_RD(x) (HW_VREF_TRM(x).U) -#define HW_VREF_TRM_WR(x, v) (HW_VREF_TRM(x).U = (v)) -#define HW_VREF_TRM_SET(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) | (v))) -#define HW_VREF_TRM_CLR(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v))) -#define HW_VREF_TRM_TOG(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual VREF_TRM bitfields - */ - -/*! - * @name Register VREF_TRM, field TRIM[5:0] (RW) - * - * These bits change the resulting VREF by approximately +/- 0.5 mV for each - * step. Min = minimum and max = maximum voltage reference output. For minimum and - * maximum voltage reference output values, refer to the Data Sheet for this chip. - * - * Values: - * - 000000 - Min - * - 111111 - Max - */ -/*@{*/ -#define BP_VREF_TRM_TRIM (0U) /*!< Bit position for VREF_TRM_TRIM. */ -#define BM_VREF_TRM_TRIM (0x3FU) /*!< Bit mask for VREF_TRM_TRIM. */ -#define BS_VREF_TRM_TRIM (6U) /*!< Bit field size in bits for VREF_TRM_TRIM. */ - -/*! @brief Read current value of the VREF_TRM_TRIM field. */ -#define BR_VREF_TRM_TRIM(x) (HW_VREF_TRM(x).B.TRIM) - -/*! @brief Format value for bitfield VREF_TRM_TRIM. */ -#define BF_VREF_TRM_TRIM(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM) - -/*! @brief Set the TRIM field to a new value. */ -#define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v))) -/*@}*/ - -/*! - * @name Register VREF_TRM, field CHOPEN[6] (RW) - * - * This bit is set during factory trimming of the VREF voltage. This bit should - * be written to 1 to achieve the performance stated in the data sheet. - * - * Values: - * - 0 - Chop oscillator is disabled. - * - 1 - Chop oscillator is enabled. - */ -/*@{*/ -#define BP_VREF_TRM_CHOPEN (6U) /*!< Bit position for VREF_TRM_CHOPEN. */ -#define BM_VREF_TRM_CHOPEN (0x40U) /*!< Bit mask for VREF_TRM_CHOPEN. */ -#define BS_VREF_TRM_CHOPEN (1U) /*!< Bit field size in bits for VREF_TRM_CHOPEN. */ - -/*! @brief Read current value of the VREF_TRM_CHOPEN field. */ -#define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN)) - -/*! @brief Format value for bitfield VREF_TRM_CHOPEN. */ -#define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN) - -/*! @brief Set the CHOPEN field to a new value. */ -#define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_VREF_SC - VREF Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_VREF_SC - VREF Status and Control Register (RW) - * - * Reset value: 0x00U - * - * This register contains the control bits used to enable the internal voltage - * reference and to select the buffer mode to be used. - */ -typedef union _hw_vref_sc -{ - uint8_t U; - struct _hw_vref_sc_bitfields - { - uint8_t MODE_LV : 2; /*!< [1:0] Buffer Mode selection */ - uint8_t VREFST : 1; /*!< [2] Internal Voltage Reference stable */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t ICOMPEN : 1; /*!< [5] Second order curvature compensation - * enable */ - uint8_t REGEN : 1; /*!< [6] Regulator enable */ - uint8_t VREFEN : 1; /*!< [7] Internal Voltage Reference enable */ - } B; -} hw_vref_sc_t; - -/*! - * @name Constants and macros for entire VREF_SC register - */ -/*@{*/ -#define HW_VREF_SC_ADDR(x) ((x) + 0x1U) - -#define HW_VREF_SC(x) (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x)) -#define HW_VREF_SC_RD(x) (HW_VREF_SC(x).U) -#define HW_VREF_SC_WR(x, v) (HW_VREF_SC(x).U = (v)) -#define HW_VREF_SC_SET(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) | (v))) -#define HW_VREF_SC_CLR(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v))) -#define HW_VREF_SC_TOG(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual VREF_SC bitfields - */ - -/*! - * @name Register VREF_SC, field MODE_LV[1:0] (RW) - * - * These bits select the buffer modes for the Voltage Reference module. - * - * Values: - * - 00 - Bandgap on only, for stabilization and startup - * - 01 - High power buffer mode enabled - * - 10 - Low-power buffer mode enabled - * - 11 - Reserved - */ -/*@{*/ -#define BP_VREF_SC_MODE_LV (0U) /*!< Bit position for VREF_SC_MODE_LV. */ -#define BM_VREF_SC_MODE_LV (0x03U) /*!< Bit mask for VREF_SC_MODE_LV. */ -#define BS_VREF_SC_MODE_LV (2U) /*!< Bit field size in bits for VREF_SC_MODE_LV. */ - -/*! @brief Read current value of the VREF_SC_MODE_LV field. */ -#define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV) - -/*! @brief Format value for bitfield VREF_SC_MODE_LV. */ -#define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV) - -/*! @brief Set the MODE_LV field to a new value. */ -#define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v))) -/*@}*/ - -/*! - * @name Register VREF_SC, field VREFST[2] (RO) - * - * This bit indicates that the bandgap reference within the Voltage Reference - * module has completed its startup and stabilization. - * - * Values: - * - 0 - The module is disabled or not stable. - * - 1 - The module is stable. - */ -/*@{*/ -#define BP_VREF_SC_VREFST (2U) /*!< Bit position for VREF_SC_VREFST. */ -#define BM_VREF_SC_VREFST (0x04U) /*!< Bit mask for VREF_SC_VREFST. */ -#define BS_VREF_SC_VREFST (1U) /*!< Bit field size in bits for VREF_SC_VREFST. */ - -/*! @brief Read current value of the VREF_SC_VREFST field. */ -#define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST)) -/*@}*/ - -/*! - * @name Register VREF_SC, field ICOMPEN[5] (RW) - * - * This bit is set during factory trimming of the VREF voltage. This bit should - * be written to 1 to achieve the performance stated in the data sheet. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_VREF_SC_ICOMPEN (5U) /*!< Bit position for VREF_SC_ICOMPEN. */ -#define BM_VREF_SC_ICOMPEN (0x20U) /*!< Bit mask for VREF_SC_ICOMPEN. */ -#define BS_VREF_SC_ICOMPEN (1U) /*!< Bit field size in bits for VREF_SC_ICOMPEN. */ - -/*! @brief Read current value of the VREF_SC_ICOMPEN field. */ -#define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN)) - -/*! @brief Format value for bitfield VREF_SC_ICOMPEN. */ -#define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN) - -/*! @brief Set the ICOMPEN field to a new value. */ -#define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v)) -/*@}*/ - -/*! - * @name Register VREF_SC, field REGEN[6] (RW) - * - * This bit is used to enable the internal 1.75 V regulator to produce a - * constant internal voltage supply in order to reduce the sensitivity to external - * supply noise and variation. If it is desired to keep the regulator enabled in very - * low power modes, refer to the Chip Configuration details for a description on - * how this can be achieved. This bit is set during factory trimming of the VREF - * voltage. This bit should be written to 1 to achieve the performance stated in - * the data sheet. - * - * Values: - * - 0 - Internal 1.75 V regulator is disabled. - * - 1 - Internal 1.75 V regulator is enabled. - */ -/*@{*/ -#define BP_VREF_SC_REGEN (6U) /*!< Bit position for VREF_SC_REGEN. */ -#define BM_VREF_SC_REGEN (0x40U) /*!< Bit mask for VREF_SC_REGEN. */ -#define BS_VREF_SC_REGEN (1U) /*!< Bit field size in bits for VREF_SC_REGEN. */ - -/*! @brief Read current value of the VREF_SC_REGEN field. */ -#define BR_VREF_SC_REGEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN)) - -/*! @brief Format value for bitfield VREF_SC_REGEN. */ -#define BF_VREF_SC_REGEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN) - -/*! @brief Set the REGEN field to a new value. */ -#define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v)) -/*@}*/ - -/*! - * @name Register VREF_SC, field VREFEN[7] (RW) - * - * This bit is used to enable the bandgap reference within the Voltage Reference - * module. After the VREF is enabled, turning off the clock to the VREF module - * via the corresponding clock gate register will not disable the VREF. VREF must - * be disabled via this VREFEN bit. - * - * Values: - * - 0 - The module is disabled. - * - 1 - The module is enabled. - */ -/*@{*/ -#define BP_VREF_SC_VREFEN (7U) /*!< Bit position for VREF_SC_VREFEN. */ -#define BM_VREF_SC_VREFEN (0x80U) /*!< Bit mask for VREF_SC_VREFEN. */ -#define BS_VREF_SC_VREFEN (1U) /*!< Bit field size in bits for VREF_SC_VREFEN. */ - -/*! @brief Read current value of the VREF_SC_VREFEN field. */ -#define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN)) - -/*! @brief Format value for bitfield VREF_SC_VREFEN. */ -#define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN) - -/*! @brief Set the VREFEN field to a new value. */ -#define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_vref_t - module struct - ******************************************************************************/ -/*! - * @brief All VREF module registers. - */ -#pragma pack(1) -typedef struct _hw_vref -{ - __IO hw_vref_trm_t TRM; /*!< [0x0] VREF Trim Register */ - __IO hw_vref_sc_t SC; /*!< [0x1] VREF Status and Control Register */ -} hw_vref_t; -#pragma pack() - -/*! @brief Macro to access all VREF registers. */ -/*! @param x VREF module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_VREF(VREF_BASE). */ -#define HW_VREF(x) (*(hw_vref_t *)(x)) - -#endif /* __HW_VREF_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h deleted file mode 100644 index b33990791db..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h +++ /dev/null @@ -1,1153 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_WDOG_REGISTERS_H__ -#define __HW_WDOG_REGISTERS_H__ - -#include "MK22F51212.h" -#include "fsl_bitaccess.h" - -/* - * MK22F51212 WDOG - * - * Generation 2008 Watchdog Timer - * - * Registers defined in this header file: - * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High - * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low - * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High - * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low - * - HW_WDOG_WINH - Watchdog Window Register High - * - HW_WDOG_WINL - Watchdog Window Register Low - * - HW_WDOG_REFRESH - Watchdog Refresh register - * - HW_WDOG_UNLOCK - Watchdog Unlock register - * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High - * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low - * - HW_WDOG_RSTCNT - Watchdog Reset Count register - * - HW_WDOG_PRESC - Watchdog Prescaler register - * - * - hw_wdog_t - Struct containing all module registers. - */ - -#define HW_WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */ - -/******************************************************************************* - * HW_WDOG_STCTRLH - Watchdog Status and Control Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW) - * - * Reset value: 0x01D3U - */ -typedef union _hw_wdog_stctrlh -{ - uint16_t U; - struct _hw_wdog_stctrlh_bitfields - { - uint16_t WDOGEN : 1; /*!< [0] */ - uint16_t CLKSRC : 1; /*!< [1] */ - uint16_t IRQRSTEN : 1; /*!< [2] */ - uint16_t WINEN : 1; /*!< [3] */ - uint16_t ALLOWUPDATE : 1; /*!< [4] */ - uint16_t DBGEN : 1; /*!< [5] */ - uint16_t STOPEN : 1; /*!< [6] */ - uint16_t WAITEN : 1; /*!< [7] */ - uint16_t RESERVED0 : 2; /*!< [9:8] */ - uint16_t TESTWDOG : 1; /*!< [10] */ - uint16_t TESTSEL : 1; /*!< [11] */ - uint16_t BYTESEL : 2; /*!< [13:12] */ - uint16_t DISTESTWDOG : 1; /*!< [14] */ - uint16_t RESERVED1 : 1; /*!< [15] */ - } B; -} hw_wdog_stctrlh_t; - -/*! - * @name Constants and macros for entire WDOG_STCTRLH register - */ -/*@{*/ -#define HW_WDOG_STCTRLH_ADDR(x) ((x) + 0x0U) - -#define HW_WDOG_STCTRLH(x) (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR(x)) -#define HW_WDOG_STCTRLH_RD(x) (HW_WDOG_STCTRLH(x).U) -#define HW_WDOG_STCTRLH_WR(x, v) (HW_WDOG_STCTRLH(x).U = (v)) -#define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) | (v))) -#define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v))) -#define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_STCTRLH bitfields - */ - -/*! - * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW) - * - * Enables or disables the WDOG's operation. In the disabled state, the watchdog - * timer is kept in the reset state, but the other exception conditions can - * still trigger a reset/interrupt. A change in the value of this bit must be held - * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. - * - * Values: - * - 0 - WDOG is disabled. - * - 1 - WDOG is enabled. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_WDOGEN (0U) /*!< Bit position for WDOG_STCTRLH_WDOGEN. */ -#define BM_WDOG_STCTRLH_WDOGEN (0x0001U) /*!< Bit mask for WDOG_STCTRLH_WDOGEN. */ -#define BS_WDOG_STCTRLH_WDOGEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */ -#define BR_WDOG_STCTRLH_WDOGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. */ -#define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN) - -/*! @brief Set the WDOGEN field to a new value. */ -#define BW_WDOG_STCTRLH_WDOGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW) - * - * Selects clock source for the WDOG timer and other internal timing operations. - * - * Values: - * - 0 - WDOG clock sourced from LPO . - * - 1 - WDOG clock sourced from alternate clock source. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_CLKSRC (1U) /*!< Bit position for WDOG_STCTRLH_CLKSRC. */ -#define BM_WDOG_STCTRLH_CLKSRC (0x0002U) /*!< Bit mask for WDOG_STCTRLH_CLKSRC. */ -#define BS_WDOG_STCTRLH_CLKSRC (1U) /*!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. */ - -/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */ -#define BR_WDOG_STCTRLH_CLKSRC(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. */ -#define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC) - -/*! @brief Set the CLKSRC field to a new value. */ -#define BW_WDOG_STCTRLH_CLKSRC(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW) - * - * Used to enable the debug breadcrumbs feature. A change in this bit is updated - * immediately, as opposed to updating after WCT. - * - * Values: - * - 0 - WDOG time-out generates reset only. - * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates - * a reset. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_IRQRSTEN (2U) /*!< Bit position for WDOG_STCTRLH_IRQRSTEN. */ -#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /*!< Bit mask for WDOG_STCTRLH_IRQRSTEN. */ -#define BS_WDOG_STCTRLH_IRQRSTEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */ -#define BR_WDOG_STCTRLH_IRQRSTEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. */ -#define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN) - -/*! @brief Set the IRQRSTEN field to a new value. */ -#define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field WINEN[3] (RW) - * - * Enables Windowing mode. - * - * Values: - * - 0 - Windowing mode is disabled. - * - 1 - Windowing mode is enabled. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_WINEN (3U) /*!< Bit position for WDOG_STCTRLH_WINEN. */ -#define BM_WDOG_STCTRLH_WINEN (0x0008U) /*!< Bit mask for WDOG_STCTRLH_WINEN. */ -#define BS_WDOG_STCTRLH_WINEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WINEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */ -#define BR_WDOG_STCTRLH_WINEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_WINEN. */ -#define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN) - -/*! @brief Set the WINEN field to a new value. */ -#define BW_WDOG_STCTRLH_WINEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW) - * - * Enables updates to watchdog write-once registers, after the reset-triggered - * initial configuration window (WCT) closes, through unlock sequence. - * - * Values: - * - 0 - No further updates allowed to WDOG write-once registers. - * - 1 - WDOG write-once registers can be unlocked for updating. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) /*!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. */ -#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /*!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. */ -#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) /*!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. */ - -/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */ -#define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. */ -#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE) - -/*! @brief Set the ALLOWUPDATE field to a new value. */ -#define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field DBGEN[5] (RW) - * - * Enables or disables WDOG in Debug mode. - * - * Values: - * - 0 - WDOG is disabled in CPU Debug mode. - * - 1 - WDOG is enabled in CPU Debug mode. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_DBGEN (5U) /*!< Bit position for WDOG_STCTRLH_DBGEN. */ -#define BM_WDOG_STCTRLH_DBGEN (0x0020U) /*!< Bit mask for WDOG_STCTRLH_DBGEN. */ -#define BS_WDOG_STCTRLH_DBGEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_DBGEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */ -#define BR_WDOG_STCTRLH_DBGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. */ -#define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN) - -/*! @brief Set the DBGEN field to a new value. */ -#define BW_WDOG_STCTRLH_DBGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field STOPEN[6] (RW) - * - * Enables or disables WDOG in Stop mode. - * - * Values: - * - 0 - WDOG is disabled in CPU Stop mode. - * - 1 - WDOG is enabled in CPU Stop mode. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_STOPEN (6U) /*!< Bit position for WDOG_STCTRLH_STOPEN. */ -#define BM_WDOG_STCTRLH_STOPEN (0x0040U) /*!< Bit mask for WDOG_STCTRLH_STOPEN. */ -#define BS_WDOG_STCTRLH_STOPEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_STOPEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */ -#define BR_WDOG_STCTRLH_STOPEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. */ -#define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN) - -/*! @brief Set the STOPEN field to a new value. */ -#define BW_WDOG_STCTRLH_STOPEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field WAITEN[7] (RW) - * - * Enables or disables WDOG in Wait mode. - * - * Values: - * - 0 - WDOG is disabled in CPU Wait mode. - * - 1 - WDOG is enabled in CPU Wait mode. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_WAITEN (7U) /*!< Bit position for WDOG_STCTRLH_WAITEN. */ -#define BM_WDOG_STCTRLH_WAITEN (0x0080U) /*!< Bit mask for WDOG_STCTRLH_WAITEN. */ -#define BS_WDOG_STCTRLH_WAITEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WAITEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */ -#define BR_WDOG_STCTRLH_WAITEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. */ -#define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN) - -/*! @brief Set the WAITEN field to a new value. */ -#define BW_WDOG_STCTRLH_WAITEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW) - * - * Puts the watchdog in the functional test mode. In this mode, the watchdog - * timer and the associated compare and reset generation logic is tested for correct - * operation. The clock for the timer is switched from the main watchdog clock - * to the fast clock input for watchdog functional test. The TESTSEL bit selects - * the test to be run. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_TESTWDOG (10U) /*!< Bit position for WDOG_STCTRLH_TESTWDOG. */ -#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /*!< Bit mask for WDOG_STCTRLH_TESTWDOG. */ -#define BS_WDOG_STCTRLH_TESTWDOG (1U) /*!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. */ - -/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */ -#define BR_WDOG_STCTRLH_TESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. */ -#define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG) - -/*! @brief Set the TESTWDOG field to a new value. */ -#define BW_WDOG_STCTRLH_TESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW) - * - * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog - * timer. - * - * Values: - * - 0 - Quick test. The timer runs in normal operation. You can load a small - * time-out value to do a quick test. - * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes - * of the timer are enabled for operation and are compared for time-out - * against the corresponding byte of the programmed time-out value. Select the - * byte through BYTESEL[1:0] for testing. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_TESTSEL (11U) /*!< Bit position for WDOG_STCTRLH_TESTSEL. */ -#define BM_WDOG_STCTRLH_TESTSEL (0x0800U) /*!< Bit mask for WDOG_STCTRLH_TESTSEL. */ -#define BS_WDOG_STCTRLH_TESTSEL (1U) /*!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. */ - -/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */ -#define BR_WDOG_STCTRLH_TESTSEL(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. */ -#define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL) - -/*! @brief Set the TESTSEL field to a new value. */ -#define BW_WDOG_STCTRLH_TESTSEL(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW) - * - * This 2-bit field selects the byte to be tested when the watchdog is in the - * byte test mode. - * - * Values: - * - 00 - Byte 0 selected - * - 01 - Byte 1 selected - * - 10 - Byte 2 selected - * - 11 - Byte 3 selected - */ -/*@{*/ -#define BP_WDOG_STCTRLH_BYTESEL (12U) /*!< Bit position for WDOG_STCTRLH_BYTESEL. */ -#define BM_WDOG_STCTRLH_BYTESEL (0x3000U) /*!< Bit mask for WDOG_STCTRLH_BYTESEL. */ -#define BS_WDOG_STCTRLH_BYTESEL (2U) /*!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. */ - -/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */ -#define BR_WDOG_STCTRLH_BYTESEL(x) (HW_WDOG_STCTRLH(x).B.BYTESEL) - -/*! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. */ -#define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL) - -/*! @brief Set the BYTESEL field to a new value. */ -#define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v))) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW) - * - * Allows the WDOG's functional test mode to be disabled permanently. After it - * is set, it can only be cleared by a reset. It cannot be unlocked for editing - * after it is set. - * - * Values: - * - 0 - WDOG functional test mode is not disabled. - * - 1 - WDOG functional test mode is disabled permanently until reset. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_DISTESTWDOG (14U) /*!< Bit position for WDOG_STCTRLH_DISTESTWDOG. */ -#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /*!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. */ -#define BS_WDOG_STCTRLH_DISTESTWDOG (1U) /*!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. */ - -/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */ -#define BR_WDOG_STCTRLH_DISTESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. */ -#define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG) - -/*! @brief Set the DISTESTWDOG field to a new value. */ -#define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_STCTRLL - Watchdog Status and Control Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW) - * - * Reset value: 0x0001U - */ -typedef union _hw_wdog_stctrll -{ - uint16_t U; - struct _hw_wdog_stctrll_bitfields - { - uint16_t RESERVED0 : 15; /*!< [14:0] */ - uint16_t INTFLG : 1; /*!< [15] */ - } B; -} hw_wdog_stctrll_t; - -/*! - * @name Constants and macros for entire WDOG_STCTRLL register - */ -/*@{*/ -#define HW_WDOG_STCTRLL_ADDR(x) ((x) + 0x2U) - -#define HW_WDOG_STCTRLL(x) (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR(x)) -#define HW_WDOG_STCTRLL_RD(x) (HW_WDOG_STCTRLL(x).U) -#define HW_WDOG_STCTRLL_WR(x, v) (HW_WDOG_STCTRLL(x).U = (v)) -#define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) | (v))) -#define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v))) -#define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_STCTRLL bitfields - */ - -/*! - * @name Register WDOG_STCTRLL, field INTFLG[15] (RW) - * - * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a - * precondition to set this flag. INTFLG = 1 results in an interrupt being issued - * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this - * bit. It also gets cleared on a system reset. - */ -/*@{*/ -#define BP_WDOG_STCTRLL_INTFLG (15U) /*!< Bit position for WDOG_STCTRLL_INTFLG. */ -#define BM_WDOG_STCTRLL_INTFLG (0x8000U) /*!< Bit mask for WDOG_STCTRLL_INTFLG. */ -#define BS_WDOG_STCTRLL_INTFLG (1U) /*!< Bit field size in bits for WDOG_STCTRLL_INTFLG. */ - -/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */ -#define BR_WDOG_STCTRLL_INTFLG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG)) - -/*! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. */ -#define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG) - -/*! @brief Set the INTFLG field to a new value. */ -#define BW_WDOG_STCTRLL_INTFLG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TOVALH - Watchdog Time-out Value Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW) - * - * Reset value: 0x004CU - */ -typedef union _hw_wdog_tovalh -{ - uint16_t U; - struct _hw_wdog_tovalh_bitfields - { - uint16_t TOVALHIGH : 16; /*!< [15:0] */ - } B; -} hw_wdog_tovalh_t; - -/*! - * @name Constants and macros for entire WDOG_TOVALH register - */ -/*@{*/ -#define HW_WDOG_TOVALH_ADDR(x) ((x) + 0x4U) - -#define HW_WDOG_TOVALH(x) (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR(x)) -#define HW_WDOG_TOVALH_RD(x) (HW_WDOG_TOVALH(x).U) -#define HW_WDOG_TOVALH_WR(x, v) (HW_WDOG_TOVALH(x).U = (v)) -#define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) | (v))) -#define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v))) -#define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TOVALH bitfields - */ - -/*! - * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW) - * - * Defines the upper 16 bits of the 32-bit time-out value for the watchdog - * timer. It is defined in terms of cycles of the watchdog clock. - */ -/*@{*/ -#define BP_WDOG_TOVALH_TOVALHIGH (0U) /*!< Bit position for WDOG_TOVALH_TOVALHIGH. */ -#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /*!< Bit mask for WDOG_TOVALH_TOVALHIGH. */ -#define BS_WDOG_TOVALH_TOVALHIGH (16U) /*!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. */ - -/*! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. */ -#define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U) - -/*! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. */ -#define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH) - -/*! @brief Set the TOVALHIGH field to a new value. */ -#define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TOVALL - Watchdog Time-out Value Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW) - * - * Reset value: 0x4B4CU - * - * The time-out value of the watchdog must be set to a minimum of four watchdog - * clock cycles. This is to take into account the delay in new settings taking - * effect in the watchdog clock domain. - */ -typedef union _hw_wdog_tovall -{ - uint16_t U; - struct _hw_wdog_tovall_bitfields - { - uint16_t TOVALLOW : 16; /*!< [15:0] */ - } B; -} hw_wdog_tovall_t; - -/*! - * @name Constants and macros for entire WDOG_TOVALL register - */ -/*@{*/ -#define HW_WDOG_TOVALL_ADDR(x) ((x) + 0x6U) - -#define HW_WDOG_TOVALL(x) (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR(x)) -#define HW_WDOG_TOVALL_RD(x) (HW_WDOG_TOVALL(x).U) -#define HW_WDOG_TOVALL_WR(x, v) (HW_WDOG_TOVALL(x).U = (v)) -#define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) | (v))) -#define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v))) -#define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TOVALL bitfields - */ - -/*! - * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW) - * - * Defines the lower 16 bits of the 32-bit time-out value for the watchdog - * timer. It is defined in terms of cycles of the watchdog clock. - */ -/*@{*/ -#define BP_WDOG_TOVALL_TOVALLOW (0U) /*!< Bit position for WDOG_TOVALL_TOVALLOW. */ -#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) /*!< Bit mask for WDOG_TOVALL_TOVALLOW. */ -#define BS_WDOG_TOVALL_TOVALLOW (16U) /*!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. */ - -/*! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. */ -#define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U) - -/*! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. */ -#define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW) - -/*! @brief Set the TOVALLOW field to a new value. */ -#define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_WINH - Watchdog Window Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_WINH - Watchdog Window Register High (RW) - * - * Reset value: 0x0000U - * - * You must set the Window Register value lower than the Time-out Value Register. - */ -typedef union _hw_wdog_winh -{ - uint16_t U; - struct _hw_wdog_winh_bitfields - { - uint16_t WINHIGH : 16; /*!< [15:0] */ - } B; -} hw_wdog_winh_t; - -/*! - * @name Constants and macros for entire WDOG_WINH register - */ -/*@{*/ -#define HW_WDOG_WINH_ADDR(x) ((x) + 0x8U) - -#define HW_WDOG_WINH(x) (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR(x)) -#define HW_WDOG_WINH_RD(x) (HW_WDOG_WINH(x).U) -#define HW_WDOG_WINH_WR(x, v) (HW_WDOG_WINH(x).U = (v)) -#define HW_WDOG_WINH_SET(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) | (v))) -#define HW_WDOG_WINH_CLR(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v))) -#define HW_WDOG_WINH_TOG(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_WINH bitfields - */ - -/*! - * @name Register WDOG_WINH, field WINHIGH[15:0] (RW) - * - * Defines the upper 16 bits of the 32-bit window for the windowed mode of - * operation of the watchdog. It is defined in terms of cycles of the watchdog clock. - * In this mode, the watchdog can be refreshed only when the timer has reached a - * value greater than or equal to this window length. A refresh outside this - * window resets the system or if IRQRSTEN is set, it interrupts and then resets the - * system. - */ -/*@{*/ -#define BP_WDOG_WINH_WINHIGH (0U) /*!< Bit position for WDOG_WINH_WINHIGH. */ -#define BM_WDOG_WINH_WINHIGH (0xFFFFU) /*!< Bit mask for WDOG_WINH_WINHIGH. */ -#define BS_WDOG_WINH_WINHIGH (16U) /*!< Bit field size in bits for WDOG_WINH_WINHIGH. */ - -/*! @brief Read current value of the WDOG_WINH_WINHIGH field. */ -#define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U) - -/*! @brief Format value for bitfield WDOG_WINH_WINHIGH. */ -#define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH) - -/*! @brief Set the WINHIGH field to a new value. */ -#define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_WINL - Watchdog Window Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW) - * - * Reset value: 0x0010U - * - * You must set the Window Register value lower than the Time-out Value Register. - */ -typedef union _hw_wdog_winl -{ - uint16_t U; - struct _hw_wdog_winl_bitfields - { - uint16_t WINLOW : 16; /*!< [15:0] */ - } B; -} hw_wdog_winl_t; - -/*! - * @name Constants and macros for entire WDOG_WINL register - */ -/*@{*/ -#define HW_WDOG_WINL_ADDR(x) ((x) + 0xAU) - -#define HW_WDOG_WINL(x) (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR(x)) -#define HW_WDOG_WINL_RD(x) (HW_WDOG_WINL(x).U) -#define HW_WDOG_WINL_WR(x, v) (HW_WDOG_WINL(x).U = (v)) -#define HW_WDOG_WINL_SET(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) | (v))) -#define HW_WDOG_WINL_CLR(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v))) -#define HW_WDOG_WINL_TOG(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_WINL bitfields - */ - -/*! - * @name Register WDOG_WINL, field WINLOW[15:0] (RW) - * - * Defines the lower 16 bits of the 32-bit window for the windowed mode of - * operation of the watchdog. It is defined in terms of cycles of the pre-scaled - * watchdog clock. In this mode, the watchdog can be refreshed only when the timer - * reaches a value greater than or equal to this window length value. A refresh - * outside of this window resets the system or if IRQRSTEN is set, it interrupts and - * then resets the system. - */ -/*@{*/ -#define BP_WDOG_WINL_WINLOW (0U) /*!< Bit position for WDOG_WINL_WINLOW. */ -#define BM_WDOG_WINL_WINLOW (0xFFFFU) /*!< Bit mask for WDOG_WINL_WINLOW. */ -#define BS_WDOG_WINL_WINLOW (16U) /*!< Bit field size in bits for WDOG_WINL_WINLOW. */ - -/*! @brief Read current value of the WDOG_WINL_WINLOW field. */ -#define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U) - -/*! @brief Format value for bitfield WDOG_WINL_WINLOW. */ -#define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW) - -/*! @brief Set the WINLOW field to a new value. */ -#define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_REFRESH - Watchdog Refresh register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW) - * - * Reset value: 0xB480U - */ -typedef union _hw_wdog_refresh -{ - uint16_t U; - struct _hw_wdog_refresh_bitfields - { - uint16_t WDOGREFRESH : 16; /*!< [15:0] */ - } B; -} hw_wdog_refresh_t; - -/*! - * @name Constants and macros for entire WDOG_REFRESH register - */ -/*@{*/ -#define HW_WDOG_REFRESH_ADDR(x) ((x) + 0xCU) - -#define HW_WDOG_REFRESH(x) (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR(x)) -#define HW_WDOG_REFRESH_RD(x) (HW_WDOG_REFRESH(x).U) -#define HW_WDOG_REFRESH_WR(x, v) (HW_WDOG_REFRESH(x).U = (v)) -#define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) | (v))) -#define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v))) -#define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_REFRESH bitfields - */ - -/*! - * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW) - * - * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 - * bus clock cycles written to this register refreshes the WDOG and prevents it - * from resetting the system. Writing a value other than the above mentioned - * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if - * IRQRSTEN is set, it interrupts and then resets the system. - */ -/*@{*/ -#define BP_WDOG_REFRESH_WDOGREFRESH (0U) /*!< Bit position for WDOG_REFRESH_WDOGREFRESH. */ -#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /*!< Bit mask for WDOG_REFRESH_WDOGREFRESH. */ -#define BS_WDOG_REFRESH_WDOGREFRESH (16U) /*!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. */ - -/*! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. */ -#define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U) - -/*! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. */ -#define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH) - -/*! @brief Set the WDOGREFRESH field to a new value. */ -#define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_UNLOCK - Watchdog Unlock register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW) - * - * Reset value: 0xD928U - */ -typedef union _hw_wdog_unlock -{ - uint16_t U; - struct _hw_wdog_unlock_bitfields - { - uint16_t WDOGUNLOCK : 16; /*!< [15:0] */ - } B; -} hw_wdog_unlock_t; - -/*! - * @name Constants and macros for entire WDOG_UNLOCK register - */ -/*@{*/ -#define HW_WDOG_UNLOCK_ADDR(x) ((x) + 0xEU) - -#define HW_WDOG_UNLOCK(x) (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR(x)) -#define HW_WDOG_UNLOCK_RD(x) (HW_WDOG_UNLOCK(x).U) -#define HW_WDOG_UNLOCK_WR(x, v) (HW_WDOG_UNLOCK(x).U = (v)) -#define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) | (v))) -#define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v))) -#define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_UNLOCK bitfields - */ - -/*! - * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW) - * - * Writing the unlock sequence values to this register to makes the watchdog - * write-once registers writable again. The required unlock sequence is 0xC520 - * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a - * window equal in length to the WCT within which you can update the registers. - * Writing a value other than the above mentioned sequence or if the sequence is - * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts - * and then resets the system. The unlock sequence is effective only if - * ALLOWUPDATE is set. - */ -/*@{*/ -#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) /*!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. */ -#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /*!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. */ -#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) /*!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. */ - -/*! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. */ -#define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U) - -/*! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. */ -#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK) - -/*! @brief Set the WDOGUNLOCK field to a new value. */ -#define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TMROUTH - Watchdog Timer Output Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_wdog_tmrouth -{ - uint16_t U; - struct _hw_wdog_tmrouth_bitfields - { - uint16_t TIMEROUTHIGH : 16; /*!< [15:0] */ - } B; -} hw_wdog_tmrouth_t; - -/*! - * @name Constants and macros for entire WDOG_TMROUTH register - */ -/*@{*/ -#define HW_WDOG_TMROUTH_ADDR(x) ((x) + 0x10U) - -#define HW_WDOG_TMROUTH(x) (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR(x)) -#define HW_WDOG_TMROUTH_RD(x) (HW_WDOG_TMROUTH(x).U) -#define HW_WDOG_TMROUTH_WR(x, v) (HW_WDOG_TMROUTH(x).U = (v)) -#define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) | (v))) -#define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v))) -#define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TMROUTH bitfields - */ - -/*! - * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW) - * - * Shows the value of the upper 16 bits of the watchdog timer. - */ -/*@{*/ -#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) /*!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. */ -#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /*!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. */ -#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /*!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. */ - -/*! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. */ -#define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U) - -/*! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. */ -#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH) - -/*! @brief Set the TIMEROUTHIGH field to a new value. */ -#define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TMROUTL - Watchdog Timer Output Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW) - * - * Reset value: 0x0000U - * - * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of - * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK - * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following - * the watchdog timer. - */ -typedef union _hw_wdog_tmroutl -{ - uint16_t U; - struct _hw_wdog_tmroutl_bitfields - { - uint16_t TIMEROUTLOW : 16; /*!< [15:0] */ - } B; -} hw_wdog_tmroutl_t; - -/*! - * @name Constants and macros for entire WDOG_TMROUTL register - */ -/*@{*/ -#define HW_WDOG_TMROUTL_ADDR(x) ((x) + 0x12U) - -#define HW_WDOG_TMROUTL(x) (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR(x)) -#define HW_WDOG_TMROUTL_RD(x) (HW_WDOG_TMROUTL(x).U) -#define HW_WDOG_TMROUTL_WR(x, v) (HW_WDOG_TMROUTL(x).U = (v)) -#define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) | (v))) -#define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v))) -#define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TMROUTL bitfields - */ - -/*! - * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW) - * - * Shows the value of the lower 16 bits of the watchdog timer. - */ -/*@{*/ -#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) /*!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. */ -#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /*!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. */ -#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) /*!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. */ - -/*! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. */ -#define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U) - -/*! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. */ -#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW) - -/*! @brief Set the TIMEROUTLOW field to a new value. */ -#define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_RSTCNT - Watchdog Reset Count register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_wdog_rstcnt -{ - uint16_t U; - struct _hw_wdog_rstcnt_bitfields - { - uint16_t RSTCNT : 16; /*!< [15:0] */ - } B; -} hw_wdog_rstcnt_t; - -/*! - * @name Constants and macros for entire WDOG_RSTCNT register - */ -/*@{*/ -#define HW_WDOG_RSTCNT_ADDR(x) ((x) + 0x14U) - -#define HW_WDOG_RSTCNT(x) (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR(x)) -#define HW_WDOG_RSTCNT_RD(x) (HW_WDOG_RSTCNT(x).U) -#define HW_WDOG_RSTCNT_WR(x, v) (HW_WDOG_RSTCNT(x).U = (v)) -#define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) | (v))) -#define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v))) -#define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_RSTCNT bitfields - */ - -/*! - * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW) - * - * Counts the number of times the watchdog resets the system. This register is - * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear - * the contents of this register. - */ -/*@{*/ -#define BP_WDOG_RSTCNT_RSTCNT (0U) /*!< Bit position for WDOG_RSTCNT_RSTCNT. */ -#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) /*!< Bit mask for WDOG_RSTCNT_RSTCNT. */ -#define BS_WDOG_RSTCNT_RSTCNT (16U) /*!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. */ - -/*! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. */ -#define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U) - -/*! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. */ -#define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT) - -/*! @brief Set the RSTCNT field to a new value. */ -#define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_PRESC - Watchdog Prescaler register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW) - * - * Reset value: 0x0400U - */ -typedef union _hw_wdog_presc -{ - uint16_t U; - struct _hw_wdog_presc_bitfields - { - uint16_t RESERVED0 : 8; /*!< [7:0] */ - uint16_t PRESCVAL : 3; /*!< [10:8] */ - uint16_t RESERVED1 : 5; /*!< [15:11] */ - } B; -} hw_wdog_presc_t; - -/*! - * @name Constants and macros for entire WDOG_PRESC register - */ -/*@{*/ -#define HW_WDOG_PRESC_ADDR(x) ((x) + 0x16U) - -#define HW_WDOG_PRESC(x) (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR(x)) -#define HW_WDOG_PRESC_RD(x) (HW_WDOG_PRESC(x).U) -#define HW_WDOG_PRESC_WR(x, v) (HW_WDOG_PRESC(x).U = (v)) -#define HW_WDOG_PRESC_SET(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) | (v))) -#define HW_WDOG_PRESC_CLR(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v))) -#define HW_WDOG_PRESC_TOG(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_PRESC bitfields - */ - -/*! - * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW) - * - * 3-bit prescaler for the watchdog clock source. A value of zero indicates no - * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + - * 1) to provide the prescaled WDOG_CLK. - */ -/*@{*/ -#define BP_WDOG_PRESC_PRESCVAL (8U) /*!< Bit position for WDOG_PRESC_PRESCVAL. */ -#define BM_WDOG_PRESC_PRESCVAL (0x0700U) /*!< Bit mask for WDOG_PRESC_PRESCVAL. */ -#define BS_WDOG_PRESC_PRESCVAL (3U) /*!< Bit field size in bits for WDOG_PRESC_PRESCVAL. */ - -/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */ -#define BR_WDOG_PRESC_PRESCVAL(x) (HW_WDOG_PRESC(x).B.PRESCVAL) - -/*! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. */ -#define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL) - -/*! @brief Set the PRESCVAL field to a new value. */ -#define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v))) -/*@}*/ - -/******************************************************************************* - * hw_wdog_t - module struct - ******************************************************************************/ -/*! - * @brief All WDOG module registers. - */ -#pragma pack(1) -typedef struct _hw_wdog -{ - __IO hw_wdog_stctrlh_t STCTRLH; /*!< [0x0] Watchdog Status and Control Register High */ - __IO hw_wdog_stctrll_t STCTRLL; /*!< [0x2] Watchdog Status and Control Register Low */ - __IO hw_wdog_tovalh_t TOVALH; /*!< [0x4] Watchdog Time-out Value Register High */ - __IO hw_wdog_tovall_t TOVALL; /*!< [0x6] Watchdog Time-out Value Register Low */ - __IO hw_wdog_winh_t WINH; /*!< [0x8] Watchdog Window Register High */ - __IO hw_wdog_winl_t WINL; /*!< [0xA] Watchdog Window Register Low */ - __IO hw_wdog_refresh_t REFRESH; /*!< [0xC] Watchdog Refresh register */ - __IO hw_wdog_unlock_t UNLOCK; /*!< [0xE] Watchdog Unlock register */ - __IO hw_wdog_tmrouth_t TMROUTH; /*!< [0x10] Watchdog Timer Output Register High */ - __IO hw_wdog_tmroutl_t TMROUTL; /*!< [0x12] Watchdog Timer Output Register Low */ - __IO hw_wdog_rstcnt_t RSTCNT; /*!< [0x14] Watchdog Reset Count register */ - __IO hw_wdog_presc_t PRESC; /*!< [0x16] Watchdog Prescaler register */ -} hw_wdog_t; -#pragma pack() - -/*! @brief Macro to access all WDOG registers. */ -/*! @param x WDOG module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_WDOG(WDOG_BASE). */ -#define HW_WDOG(x) (*(hw_wdog_t *)(x)) - -#endif /* __HW_WDOG_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h deleted file mode 100644 index 2efc27f1359..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h +++ /dev/null @@ -1,526 +0,0 @@ -/* -** ################################################################### -** Version: rev. 2.5, 2014-05-06 -** Build: b140604 -** -** Abstract: -** Register bit field access macros. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-07-23) -** Initial version. -** - rev. 1.1 (2013-09-17) -** RM rev. 0.4 update. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-20) -** Update according to reference manual rev. 0.6, -** - rev. 2.3 (2014-01-13) -** Update according to reference manual rev. 0.61, -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h -** - rev. 2.5 (2014-05-06) -** Update according to reference manual rev. 1.0, -** Update of system and startup files. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - - -#ifndef _FSL_BITACCESS_H -#define _FSL_BITACCESS_H 1 - -#include -#include - -/** - * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/** - * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/** - * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/* - * Macros for single instance registers - */ - -#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) -#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) -#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) - -#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) -#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) -#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) - -#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym - -#define BF_RD(reg, field) HW_##reg.B.field -#define BF_WR(reg, field, v) BW_##reg##_##field(v) - -#define BF_CS1(reg, f1, v1) \ - (HW_##reg##_CLR(BM_##reg##_##f1), \ - HW_##reg##_SET(BF_##reg##_##f1(v1))) - -#define BF_CS2(reg, f1, v1, f2, v2) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2))) - -#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3))) - -#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4))) - -#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5))) - -#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6))) - -#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7))) - -#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8))) - -/* - * Macros for multiple instance registers - */ - -#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) -#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) -#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) - -#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) -#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) -#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) - -#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym - -#define BF_RDn(reg, n, field) HW_##reg(n).B.field -#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) - -#define BF_CS1n(reg, n, f1, v1) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) - -#define BF_CS2n(reg, n, f1, v1, f2, v2) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2)))) - -#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3)))) - -#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4)))) - -#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5)))) - -#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6)))) - -#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7)))) - -#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8)))) - -/* - * Macros for single instance MULTI-BLOCK registers - */ - -#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) -#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) -#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) - -#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) -#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) -#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) - -#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym - -#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field -#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) - -#define BFn_CS1(reg, blk, f1, v1) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) - -#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2))) - -#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3))) - -#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4))) - -#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5))) - -#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6))) - -#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7))) - -#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8))) - -/* - * Macros for MULTI-BLOCK multiple instance registers - */ - -#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) -#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) -#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) - -#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) -#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) -#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) - -#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym - -#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field -#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) - -#define BFn_CS1n(reg, blk, n, f1, v1) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) - -#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2)))) - -#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3)))) - -#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4)))) - -#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5)))) - -#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6)))) - -#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7)))) - -#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8)))) - -#endif /* _FSL_BITACCESS_H */ - -/******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/fsl_device_registers.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/fsl_device_registers.h deleted file mode 100644 index 02dc670bfa9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/fsl_device_registers.h +++ /dev/null @@ -1,1526 +0,0 @@ -/* - * Copyright (c) 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \ - defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)) - - #define K02F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK02F12810/MK02F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK02F12810/MK02F12810_adc.h" - #include "device/MK02F12810/MK02F12810_cmp.h" - #include "device/MK02F12810/MK02F12810_crc.h" - #include "device/MK02F12810/MK02F12810_dac.h" - #include "device/MK02F12810/MK02F12810_dma.h" - #include "device/MK02F12810/MK02F12810_dmamux.h" - #include "device/MK02F12810/MK02F12810_ewm.h" - #include "device/MK02F12810/MK02F12810_fmc.h" - #include "device/MK02F12810/MK02F12810_ftfa.h" - #include "device/MK02F12810/MK02F12810_ftm.h" - #include "device/MK02F12810/MK02F12810_gpio.h" - #include "device/MK02F12810/MK02F12810_i2c.h" - #include "device/MK02F12810/MK02F12810_llwu.h" - #include "device/MK02F12810/MK02F12810_lptmr.h" - #include "device/MK02F12810/MK02F12810_mcg.h" - #include "device/MK02F12810/MK02F12810_mcm.h" - #include "device/MK02F12810/MK02F12810_nv.h" - #include "device/MK02F12810/MK02F12810_osc.h" - #include "device/MK02F12810/MK02F12810_pdb.h" - #include "device/MK02F12810/MK02F12810_pit.h" - #include "device/MK02F12810/MK02F12810_pmc.h" - #include "device/MK02F12810/MK02F12810_port.h" - #include "device/MK02F12810/MK02F12810_rcm.h" - #include "device/MK02F12810/MK02F12810_sim.h" - #include "device/MK02F12810/MK02F12810_smc.h" - #include "device/MK02F12810/MK02F12810_spi.h" - #include "device/MK02F12810/MK02F12810_uart.h" - #include "device/MK02F12810/MK02F12810_vref.h" - #include "device/MK02F12810/MK02F12810_wdog.h" - -#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \ - defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \ - defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \ - defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \ - defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \ - defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)) - - #define K20D5_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK20D5/MK20D5.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK20D5/MK20D5_adc.h" - #include "device/MK20D5/MK20D5_cmp.h" - #include "device/MK20D5/MK20D5_cmt.h" - #include "device/MK20D5/MK20D5_crc.h" - #include "device/MK20D5/MK20D5_dma.h" - #include "device/MK20D5/MK20D5_dmamux.h" - #include "device/MK20D5/MK20D5_ewm.h" - #include "device/MK20D5/MK20D5_fmc.h" - #include "device/MK20D5/MK20D5_ftfl.h" - #include "device/MK20D5/MK20D5_ftm.h" - #include "device/MK20D5/MK20D5_gpio.h" - #include "device/MK20D5/MK20D5_i2c.h" - #include "device/MK20D5/MK20D5_i2s.h" - #include "device/MK20D5/MK20D5_llwu.h" - #include "device/MK20D5/MK20D5_lptmr.h" - #include "device/MK20D5/MK20D5_mcg.h" - #include "device/MK20D5/MK20D5_nv.h" - #include "device/MK20D5/MK20D5_osc.h" - #include "device/MK20D5/MK20D5_pdb.h" - #include "device/MK20D5/MK20D5_pit.h" - #include "device/MK20D5/MK20D5_pmc.h" - #include "device/MK20D5/MK20D5_port.h" - #include "device/MK20D5/MK20D5_rcm.h" - #include "device/MK20D5/MK20D5_rfsys.h" - #include "device/MK20D5/MK20D5_rfvbat.h" - #include "device/MK20D5/MK20D5_rtc.h" - #include "device/MK20D5/MK20D5_sim.h" - #include "device/MK20D5/MK20D5_smc.h" - #include "device/MK20D5/MK20D5_spi.h" - #include "device/MK20D5/MK20D5_tsi.h" - #include "device/MK20D5/MK20D5_uart.h" - #include "device/MK20D5/MK20D5_usb.h" - #include "device/MK20D5/MK20D5_usbdcd.h" - #include "device/MK20D5/MK20D5_vref.h" - #include "device/MK20D5/MK20D5_wdog.h" - -#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \ - defined(CPU_MK22FN128VMP10)) - - #define K22F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK22F12810/MK22F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK22F12810/MK22F12810_adc.h" - #include "device/MK22F12810/MK22F12810_cmp.h" - #include "device/MK22F12810/MK22F12810_crc.h" - #include "device/MK22F12810/MK22F12810_dac.h" - #include "device/MK22F12810/MK22F12810_dma.h" - #include "device/MK22F12810/MK22F12810_dmamux.h" - #include "device/MK22F12810/MK22F12810_ewm.h" - #include "device/MK22F12810/MK22F12810_fmc.h" - #include "device/MK22F12810/MK22F12810_ftfa.h" - #include "device/MK22F12810/MK22F12810_ftm.h" - #include "device/MK22F12810/MK22F12810_gpio.h" - #include "device/MK22F12810/MK22F12810_i2c.h" - #include "device/MK22F12810/MK22F12810_i2s.h" - #include "device/MK22F12810/MK22F12810_llwu.h" - #include "device/MK22F12810/MK22F12810_lptmr.h" - #include "device/MK22F12810/MK22F12810_lpuart.h" - #include "device/MK22F12810/MK22F12810_mcg.h" - #include "device/MK22F12810/MK22F12810_mcm.h" - #include "device/MK22F12810/MK22F12810_nv.h" - #include "device/MK22F12810/MK22F12810_osc.h" - #include "device/MK22F12810/MK22F12810_pdb.h" - #include "device/MK22F12810/MK22F12810_pit.h" - #include "device/MK22F12810/MK22F12810_pmc.h" - #include "device/MK22F12810/MK22F12810_port.h" - #include "device/MK22F12810/MK22F12810_rcm.h" - #include "device/MK22F12810/MK22F12810_rfsys.h" - #include "device/MK22F12810/MK22F12810_rfvbat.h" - #include "device/MK22F12810/MK22F12810_rtc.h" - #include "device/MK22F12810/MK22F12810_sim.h" - #include "device/MK22F12810/MK22F12810_smc.h" - #include "device/MK22F12810/MK22F12810_spi.h" - #include "device/MK22F12810/MK22F12810_uart.h" - #include "device/MK22F12810/MK22F12810_usb.h" - #include "device/MK22F12810/MK22F12810_vref.h" - #include "device/MK22F12810/MK22F12810_wdog.h" - -#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \ - defined(CPU_MK22FN256VMP12)) - - #define K22F25612_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK22F25612/MK22F25612.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK22F25612/MK22F25612_adc.h" - #include "device/MK22F25612/MK22F25612_cmp.h" - #include "device/MK22F25612/MK22F25612_crc.h" - #include "device/MK22F25612/MK22F25612_dac.h" - #include "device/MK22F25612/MK22F25612_dma.h" - #include "device/MK22F25612/MK22F25612_dmamux.h" - #include "device/MK22F25612/MK22F25612_ewm.h" - #include "device/MK22F25612/MK22F25612_fmc.h" - #include "device/MK22F25612/MK22F25612_ftfa.h" - #include "device/MK22F25612/MK22F25612_ftm.h" - #include "device/MK22F25612/MK22F25612_gpio.h" - #include "device/MK22F25612/MK22F25612_i2c.h" - #include "device/MK22F25612/MK22F25612_i2s.h" - #include "device/MK22F25612/MK22F25612_llwu.h" - #include "device/MK22F25612/MK22F25612_lptmr.h" - #include "device/MK22F25612/MK22F25612_lpuart.h" - #include "device/MK22F25612/MK22F25612_mcg.h" - #include "device/MK22F25612/MK22F25612_mcm.h" - #include "device/MK22F25612/MK22F25612_nv.h" - #include "device/MK22F25612/MK22F25612_osc.h" - #include "device/MK22F25612/MK22F25612_pdb.h" - #include "device/MK22F25612/MK22F25612_pit.h" - #include "device/MK22F25612/MK22F25612_pmc.h" - #include "device/MK22F25612/MK22F25612_port.h" - #include "device/MK22F25612/MK22F25612_rcm.h" - #include "device/MK22F25612/MK22F25612_rfsys.h" - #include "device/MK22F25612/MK22F25612_rfvbat.h" - #include "device/MK22F25612/MK22F25612_rng.h" - #include "device/MK22F25612/MK22F25612_rtc.h" - #include "device/MK22F25612/MK22F25612_sim.h" - #include "device/MK22F25612/MK22F25612_smc.h" - #include "device/MK22F25612/MK22F25612_spi.h" - #include "device/MK22F25612/MK22F25612_uart.h" - #include "device/MK22F25612/MK22F25612_usb.h" - #include "device/MK22F25612/MK22F25612_vref.h" - #include "device/MK22F25612/MK22F25612_wdog.h" - -#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12)) - - #define K22F51212_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK22F51212/MK22F51212.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK22F51212/MK22F51212_adc.h" - #include "device/MK22F51212/MK22F51212_cmp.h" - #include "device/MK22F51212/MK22F51212_crc.h" - #include "device/MK22F51212/MK22F51212_dac.h" - #include "device/MK22F51212/MK22F51212_dma.h" - #include "device/MK22F51212/MK22F51212_dmamux.h" - #include "device/MK22F51212/MK22F51212_ewm.h" - #include "device/MK22F51212/MK22F51212_fb.h" - #include "device/MK22F51212/MK22F51212_fmc.h" - #include "device/MK22F51212/MK22F51212_ftfa.h" - #include "device/MK22F51212/MK22F51212_ftm.h" - #include "device/MK22F51212/MK22F51212_gpio.h" - #include "device/MK22F51212/MK22F51212_i2c.h" - #include "device/MK22F51212/MK22F51212_i2s.h" - #include "device/MK22F51212/MK22F51212_llwu.h" - #include "device/MK22F51212/MK22F51212_lptmr.h" - #include "device/MK22F51212/MK22F51212_lpuart.h" - #include "device/MK22F51212/MK22F51212_mcg.h" - #include "device/MK22F51212/MK22F51212_mcm.h" - #include "device/MK22F51212/MK22F51212_nv.h" - #include "device/MK22F51212/MK22F51212_osc.h" - #include "device/MK22F51212/MK22F51212_pdb.h" - #include "device/MK22F51212/MK22F51212_pit.h" - #include "device/MK22F51212/MK22F51212_pmc.h" - #include "device/MK22F51212/MK22F51212_port.h" - #include "device/MK22F51212/MK22F51212_rcm.h" - #include "device/MK22F51212/MK22F51212_rfsys.h" - #include "device/MK22F51212/MK22F51212_rfvbat.h" - #include "device/MK22F51212/MK22F51212_rng.h" - #include "device/MK22F51212/MK22F51212_rtc.h" - #include "device/MK22F51212/MK22F51212_sim.h" - #include "device/MK22F51212/MK22F51212_smc.h" - #include "device/MK22F51212/MK22F51212_spi.h" - #include "device/MK22F51212/MK22F51212_uart.h" - #include "device/MK22F51212/MK22F51212_usb.h" - #include "device/MK22F51212/MK22F51212_vref.h" - #include "device/MK22F51212/MK22F51212_wdog.h" - -#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12)) - - #define K24F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK24F12/MK24F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK24F12/MK24F12_adc.h" - #include "device/MK24F12/MK24F12_aips.h" - #include "device/MK24F12/MK24F12_axbs.h" - #include "device/MK24F12/MK24F12_can.h" - #include "device/MK24F12/MK24F12_cau.h" - #include "device/MK24F12/MK24F12_cmp.h" - #include "device/MK24F12/MK24F12_cmt.h" - #include "device/MK24F12/MK24F12_crc.h" - #include "device/MK24F12/MK24F12_dac.h" - #include "device/MK24F12/MK24F12_dma.h" - #include "device/MK24F12/MK24F12_dmamux.h" - #include "device/MK24F12/MK24F12_ewm.h" - #include "device/MK24F12/MK24F12_fb.h" - #include "device/MK24F12/MK24F12_fmc.h" - #include "device/MK24F12/MK24F12_ftfe.h" - #include "device/MK24F12/MK24F12_ftm.h" - #include "device/MK24F12/MK24F12_gpio.h" - #include "device/MK24F12/MK24F12_i2c.h" - #include "device/MK24F12/MK24F12_i2s.h" - #include "device/MK24F12/MK24F12_llwu.h" - #include "device/MK24F12/MK24F12_lptmr.h" - #include "device/MK24F12/MK24F12_mcg.h" - #include "device/MK24F12/MK24F12_mcm.h" - #include "device/MK24F12/MK24F12_mpu.h" - #include "device/MK24F12/MK24F12_nv.h" - #include "device/MK24F12/MK24F12_osc.h" - #include "device/MK24F12/MK24F12_pdb.h" - #include "device/MK24F12/MK24F12_pit.h" - #include "device/MK24F12/MK24F12_pmc.h" - #include "device/MK24F12/MK24F12_port.h" - #include "device/MK24F12/MK24F12_rcm.h" - #include "device/MK24F12/MK24F12_rfsys.h" - #include "device/MK24F12/MK24F12_rfvbat.h" - #include "device/MK24F12/MK24F12_rng.h" - #include "device/MK24F12/MK24F12_rtc.h" - #include "device/MK24F12/MK24F12_sdhc.h" - #include "device/MK24F12/MK24F12_sim.h" - #include "device/MK24F12/MK24F12_smc.h" - #include "device/MK24F12/MK24F12_spi.h" - #include "device/MK24F12/MK24F12_uart.h" - #include "device/MK24F12/MK24F12_usb.h" - #include "device/MK24F12/MK24F12_usbdcd.h" - #include "device/MK24F12/MK24F12_vref.h" - #include "device/MK24F12/MK24F12_wdog.h" - -#elif (defined(CPU_MK24FN256VDC12)) - - #define K24F25612_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK24F25612/MK24F25612.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK24F25612/MK24F25612_adc.h" - #include "device/MK24F25612/MK24F25612_aips.h" - #include "device/MK24F25612/MK24F25612_cmp.h" - #include "device/MK24F25612/MK24F25612_cmt.h" - #include "device/MK24F25612/MK24F25612_crc.h" - #include "device/MK24F25612/MK24F25612_dac.h" - #include "device/MK24F25612/MK24F25612_dma.h" - #include "device/MK24F25612/MK24F25612_dmamux.h" - #include "device/MK24F25612/MK24F25612_ewm.h" - #include "device/MK24F25612/MK24F25612_fmc.h" - #include "device/MK24F25612/MK24F25612_ftfa.h" - #include "device/MK24F25612/MK24F25612_ftm.h" - #include "device/MK24F25612/MK24F25612_gpio.h" - #include "device/MK24F25612/MK24F25612_i2c.h" - #include "device/MK24F25612/MK24F25612_i2s.h" - #include "device/MK24F25612/MK24F25612_llwu.h" - #include "device/MK24F25612/MK24F25612_lptmr.h" - #include "device/MK24F25612/MK24F25612_mcg.h" - #include "device/MK24F25612/MK24F25612_mcm.h" - #include "device/MK24F25612/MK24F25612_osc.h" - #include "device/MK24F25612/MK24F25612_pdb.h" - #include "device/MK24F25612/MK24F25612_pit.h" - #include "device/MK24F25612/MK24F25612_pmc.h" - #include "device/MK24F25612/MK24F25612_port.h" - #include "device/MK24F25612/MK24F25612_rcm.h" - #include "device/MK24F25612/MK24F25612_rfsys.h" - #include "device/MK24F25612/MK24F25612_rfvbat.h" - #include "device/MK24F25612/MK24F25612_rng.h" - #include "device/MK24F25612/MK24F25612_rtc.h" - #include "device/MK24F25612/MK24F25612_sim.h" - #include "device/MK24F25612/MK24F25612_smc.h" - #include "device/MK24F25612/MK24F25612_spi.h" - #include "device/MK24F25612/MK24F25612_uart.h" - #include "device/MK24F25612/MK24F25612_usb.h" - #include "device/MK24F25612/MK24F25612_usbdcd.h" - #include "device/MK24F25612/MK24F25612_vref.h" - #include "device/MK24F25612/MK24F25612_wdog.h" - -#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12)) - - #define K63F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK63F12/MK63F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK63F12/MK63F12_adc.h" - #include "device/MK63F12/MK63F12_aips.h" - #include "device/MK63F12/MK63F12_axbs.h" - #include "device/MK63F12/MK63F12_can.h" - #include "device/MK63F12/MK63F12_cau.h" - #include "device/MK63F12/MK63F12_cmp.h" - #include "device/MK63F12/MK63F12_cmt.h" - #include "device/MK63F12/MK63F12_crc.h" - #include "device/MK63F12/MK63F12_dac.h" - #include "device/MK63F12/MK63F12_dma.h" - #include "device/MK63F12/MK63F12_dmamux.h" - #include "device/MK63F12/MK63F12_enet.h" - #include "device/MK63F12/MK63F12_ewm.h" - #include "device/MK63F12/MK63F12_fb.h" - #include "device/MK63F12/MK63F12_fmc.h" - #include "device/MK63F12/MK63F12_ftfe.h" - #include "device/MK63F12/MK63F12_ftm.h" - #include "device/MK63F12/MK63F12_gpio.h" - #include "device/MK63F12/MK63F12_i2c.h" - #include "device/MK63F12/MK63F12_i2s.h" - #include "device/MK63F12/MK63F12_llwu.h" - #include "device/MK63F12/MK63F12_lptmr.h" - #include "device/MK63F12/MK63F12_mcg.h" - #include "device/MK63F12/MK63F12_mcm.h" - #include "device/MK63F12/MK63F12_mpu.h" - #include "device/MK63F12/MK63F12_nv.h" - #include "device/MK63F12/MK63F12_osc.h" - #include "device/MK63F12/MK63F12_pdb.h" - #include "device/MK63F12/MK63F12_pit.h" - #include "device/MK63F12/MK63F12_pmc.h" - #include "device/MK63F12/MK63F12_port.h" - #include "device/MK63F12/MK63F12_rcm.h" - #include "device/MK63F12/MK63F12_rfsys.h" - #include "device/MK63F12/MK63F12_rfvbat.h" - #include "device/MK63F12/MK63F12_rng.h" - #include "device/MK63F12/MK63F12_rtc.h" - #include "device/MK63F12/MK63F12_sdhc.h" - #include "device/MK63F12/MK63F12_sim.h" - #include "device/MK63F12/MK63F12_smc.h" - #include "device/MK63F12/MK63F12_spi.h" - #include "device/MK63F12/MK63F12_uart.h" - #include "device/MK63F12/MK63F12_usb.h" - #include "device/MK63F12/MK63F12_usbdcd.h" - #include "device/MK63F12/MK63F12_vref.h" - #include "device/MK63F12/MK63F12_wdog.h" - -#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)) - - #define K64F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK64F12/MK64F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK64F12/MK64F12_adc.h" - #include "device/MK64F12/MK64F12_aips.h" - #include "device/MK64F12/MK64F12_axbs.h" - #include "device/MK64F12/MK64F12_can.h" - #include "device/MK64F12/MK64F12_cau.h" - #include "device/MK64F12/MK64F12_cmp.h" - #include "device/MK64F12/MK64F12_cmt.h" - #include "device/MK64F12/MK64F12_crc.h" - #include "device/MK64F12/MK64F12_dac.h" - #include "device/MK64F12/MK64F12_dma.h" - #include "device/MK64F12/MK64F12_dmamux.h" - #include "device/MK64F12/MK64F12_enet.h" - #include "device/MK64F12/MK64F12_ewm.h" - #include "device/MK64F12/MK64F12_fb.h" - #include "device/MK64F12/MK64F12_fmc.h" - #include "device/MK64F12/MK64F12_ftfe.h" - #include "device/MK64F12/MK64F12_ftm.h" - #include "device/MK64F12/MK64F12_gpio.h" - #include "device/MK64F12/MK64F12_i2c.h" - #include "device/MK64F12/MK64F12_i2s.h" - #include "device/MK64F12/MK64F12_llwu.h" - #include "device/MK64F12/MK64F12_lptmr.h" - #include "device/MK64F12/MK64F12_mcg.h" - #include "device/MK64F12/MK64F12_mcm.h" - #include "device/MK64F12/MK64F12_mpu.h" - #include "device/MK64F12/MK64F12_nv.h" - #include "device/MK64F12/MK64F12_osc.h" - #include "device/MK64F12/MK64F12_pdb.h" - #include "device/MK64F12/MK64F12_pit.h" - #include "device/MK64F12/MK64F12_pmc.h" - #include "device/MK64F12/MK64F12_port.h" - #include "device/MK64F12/MK64F12_rcm.h" - #include "device/MK64F12/MK64F12_rfsys.h" - #include "device/MK64F12/MK64F12_rfvbat.h" - #include "device/MK64F12/MK64F12_rng.h" - #include "device/MK64F12/MK64F12_rtc.h" - #include "device/MK64F12/MK64F12_sdhc.h" - #include "device/MK64F12/MK64F12_sim.h" - #include "device/MK64F12/MK64F12_smc.h" - #include "device/MK64F12/MK64F12_spi.h" - #include "device/MK64F12/MK64F12_uart.h" - #include "device/MK64F12/MK64F12_usb.h" - #include "device/MK64F12/MK64F12_usbdcd.h" - #include "device/MK64F12/MK64F12_vref.h" - #include "device/MK64F12/MK64F12_wdog.h" - -#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18)) - - #define K65F18_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK65F18/MK65F18.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK65F18/MK65F18_adc.h" - #include "device/MK65F18/MK65F18_aips.h" - #include "device/MK65F18/MK65F18_axbs.h" - #include "device/MK65F18/MK65F18_can.h" - #include "device/MK65F18/MK65F18_cau.h" - #include "device/MK65F18/MK65F18_cmp.h" - #include "device/MK65F18/MK65F18_cmt.h" - #include "device/MK65F18/MK65F18_crc.h" - #include "device/MK65F18/MK65F18_dac.h" - #include "device/MK65F18/MK65F18_dma.h" - #include "device/MK65F18/MK65F18_dmamux.h" - #include "device/MK65F18/MK65F18_enet.h" - #include "device/MK65F18/MK65F18_ewm.h" - #include "device/MK65F18/MK65F18_fb.h" - #include "device/MK65F18/MK65F18_fmc.h" - #include "device/MK65F18/MK65F18_ftfe.h" - #include "device/MK65F18/MK65F18_ftm.h" - #include "device/MK65F18/MK65F18_gpio.h" - #include "device/MK65F18/MK65F18_i2c.h" - #include "device/MK65F18/MK65F18_i2s.h" - #include "device/MK65F18/MK65F18_llwu.h" - #include "device/MK65F18/MK65F18_lmem.h" - #include "device/MK65F18/MK65F18_lptmr.h" - #include "device/MK65F18/MK65F18_lpuart.h" - #include "device/MK65F18/MK65F18_mcg.h" - #include "device/MK65F18/MK65F18_mcm.h" - #include "device/MK65F18/MK65F18_mpu.h" - #include "device/MK65F18/MK65F18_nv.h" - #include "device/MK65F18/MK65F18_osc.h" - #include "device/MK65F18/MK65F18_pdb.h" - #include "device/MK65F18/MK65F18_pit.h" - #include "device/MK65F18/MK65F18_pmc.h" - #include "device/MK65F18/MK65F18_port.h" - #include "device/MK65F18/MK65F18_rcm.h" - #include "device/MK65F18/MK65F18_rfsys.h" - #include "device/MK65F18/MK65F18_rfvbat.h" - #include "device/MK65F18/MK65F18_rng.h" - #include "device/MK65F18/MK65F18_rtc.h" - #include "device/MK65F18/MK65F18_sdhc.h" - #include "device/MK65F18/MK65F18_sdram.h" - #include "device/MK65F18/MK65F18_sim.h" - #include "device/MK65F18/MK65F18_smc.h" - #include "device/MK65F18/MK65F18_spi.h" - #include "device/MK65F18/MK65F18_tpm.h" - #include "device/MK65F18/MK65F18_tsi.h" - #include "device/MK65F18/MK65F18_uart.h" - #include "device/MK65F18/MK65F18_usb.h" - #include "device/MK65F18/MK65F18_usbdcd.h" - #include "device/MK65F18/MK65F18_usbhs.h" - #include "device/MK65F18/MK65F18_usbhsdcd.h" - #include "device/MK65F18/MK65F18_usbphy.h" - #include "device/MK65F18/MK65F18_vref.h" - #include "device/MK65F18/MK65F18_wdog.h" - -#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18)) - - #define K66F18_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK66F18/MK66F18.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK66F18/MK66F18_adc.h" - #include "device/MK66F18/MK66F18_aips.h" - #include "device/MK66F18/MK66F18_axbs.h" - #include "device/MK66F18/MK66F18_can.h" - #include "device/MK66F18/MK66F18_cau.h" - #include "device/MK66F18/MK66F18_cmp.h" - #include "device/MK66F18/MK66F18_cmt.h" - #include "device/MK66F18/MK66F18_crc.h" - #include "device/MK66F18/MK66F18_dac.h" - #include "device/MK66F18/MK66F18_dma.h" - #include "device/MK66F18/MK66F18_dmamux.h" - #include "device/MK66F18/MK66F18_enet.h" - #include "device/MK66F18/MK66F18_ewm.h" - #include "device/MK66F18/MK66F18_fb.h" - #include "device/MK66F18/MK66F18_fmc.h" - #include "device/MK66F18/MK66F18_ftfe.h" - #include "device/MK66F18/MK66F18_ftm.h" - #include "device/MK66F18/MK66F18_gpio.h" - #include "device/MK66F18/MK66F18_i2c.h" - #include "device/MK66F18/MK66F18_i2s.h" - #include "device/MK66F18/MK66F18_llwu.h" - #include "device/MK66F18/MK66F18_lmem.h" - #include "device/MK66F18/MK66F18_lptmr.h" - #include "device/MK66F18/MK66F18_lpuart.h" - #include "device/MK66F18/MK66F18_mcg.h" - #include "device/MK66F18/MK66F18_mcm.h" - #include "device/MK66F18/MK66F18_mpu.h" - #include "device/MK66F18/MK66F18_nv.h" - #include "device/MK66F18/MK66F18_osc.h" - #include "device/MK66F18/MK66F18_pdb.h" - #include "device/MK66F18/MK66F18_pit.h" - #include "device/MK66F18/MK66F18_pmc.h" - #include "device/MK66F18/MK66F18_port.h" - #include "device/MK66F18/MK66F18_rcm.h" - #include "device/MK66F18/MK66F18_rfsys.h" - #include "device/MK66F18/MK66F18_rfvbat.h" - #include "device/MK66F18/MK66F18_rng.h" - #include "device/MK66F18/MK66F18_rtc.h" - #include "device/MK66F18/MK66F18_sdhc.h" - #include "device/MK66F18/MK66F18_sdram.h" - #include "device/MK66F18/MK66F18_sim.h" - #include "device/MK66F18/MK66F18_smc.h" - #include "device/MK66F18/MK66F18_spi.h" - #include "device/MK66F18/MK66F18_tpm.h" - #include "device/MK66F18/MK66F18_tsi.h" - #include "device/MK66F18/MK66F18_uart.h" - #include "device/MK66F18/MK66F18_usb.h" - #include "device/MK66F18/MK66F18_usbdcd.h" - #include "device/MK66F18/MK66F18_usbhs.h" - #include "device/MK66F18/MK66F18_usbhsdcd.h" - #include "device/MK66F18/MK66F18_usbphy.h" - #include "device/MK66F18/MK66F18_vref.h" - #include "device/MK66F18/MK66F18_wdog.h" - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK70F12/MK70F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK70F12/MK70F12_adc.h" - #include "device/MK70F12/MK70F12_aips.h" - #include "device/MK70F12/MK70F12_axbs.h" - #include "device/MK70F12/MK70F12_can.h" - #include "device/MK70F12/MK70F12_cau.h" - #include "device/MK70F12/MK70F12_cmp.h" - #include "device/MK70F12/MK70F12_cmt.h" - #include "device/MK70F12/MK70F12_crc.h" - #include "device/MK70F12/MK70F12_dac.h" - #include "device/MK70F12/MK70F12_ddr.h" - #include "device/MK70F12/MK70F12_dma.h" - #include "device/MK70F12/MK70F12_dmamux.h" - #include "device/MK70F12/MK70F12_enet.h" - #include "device/MK70F12/MK70F12_ewm.h" - #include "device/MK70F12/MK70F12_fb.h" - #include "device/MK70F12/MK70F12_fmc.h" - #include "device/MK70F12/MK70F12_ftfe.h" - #include "device/MK70F12/MK70F12_ftm.h" - #include "device/MK70F12/MK70F12_gpio.h" - #include "device/MK70F12/MK70F12_i2c.h" - #include "device/MK70F12/MK70F12_i2s.h" - #include "device/MK70F12/MK70F12_lcdc.h" - #include "device/MK70F12/MK70F12_llwu.h" - #include "device/MK70F12/MK70F12_lmem.h" - #include "device/MK70F12/MK70F12_lptmr.h" - #include "device/MK70F12/MK70F12_mcg.h" - #include "device/MK70F12/MK70F12_mcm.h" - #include "device/MK70F12/MK70F12_mpu.h" - #include "device/MK70F12/MK70F12_nfc.h" - #include "device/MK70F12/MK70F12_nv.h" - #include "device/MK70F12/MK70F12_osc.h" - #include "device/MK70F12/MK70F12_pdb.h" - #include "device/MK70F12/MK70F12_pit.h" - #include "device/MK70F12/MK70F12_pmc.h" - #include "device/MK70F12/MK70F12_port.h" - #include "device/MK70F12/MK70F12_rcm.h" - #include "device/MK70F12/MK70F12_rfsys.h" - #include "device/MK70F12/MK70F12_rfvbat.h" - #include "device/MK70F12/MK70F12_rng.h" - #include "device/MK70F12/MK70F12_rtc.h" - #include "device/MK70F12/MK70F12_sdhc.h" - #include "device/MK70F12/MK70F12_sim.h" - #include "device/MK70F12/MK70F12_smc.h" - #include "device/MK70F12/MK70F12_spi.h" - #include "device/MK70F12/MK70F12_tsi.h" - #include "device/MK70F12/MK70F12_uart.h" - #include "device/MK70F12/MK70F12_usb.h" - #include "device/MK70F12/MK70F12_usbdcd.h" - #include "device/MK70F12/MK70F12_usbhs.h" - #include "device/MK70F12/MK70F12_vref.h" - #include "device/MK70F12/MK70F12_wdog.h" - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK70F15/MK70F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK70F15/MK70F15_adc.h" - #include "device/MK70F15/MK70F15_aips.h" - #include "device/MK70F15/MK70F15_axbs.h" - #include "device/MK70F15/MK70F15_can.h" - #include "device/MK70F15/MK70F15_cau.h" - #include "device/MK70F15/MK70F15_cmp.h" - #include "device/MK70F15/MK70F15_cmt.h" - #include "device/MK70F15/MK70F15_crc.h" - #include "device/MK70F15/MK70F15_dac.h" - #include "device/MK70F15/MK70F15_ddr.h" - #include "device/MK70F15/MK70F15_dma.h" - #include "device/MK70F15/MK70F15_dmamux.h" - #include "device/MK70F15/MK70F15_enet.h" - #include "device/MK70F15/MK70F15_ewm.h" - #include "device/MK70F15/MK70F15_fb.h" - #include "device/MK70F15/MK70F15_fmc.h" - #include "device/MK70F15/MK70F15_ftfe.h" - #include "device/MK70F15/MK70F15_ftm.h" - #include "device/MK70F15/MK70F15_gpio.h" - #include "device/MK70F15/MK70F15_i2c.h" - #include "device/MK70F15/MK70F15_i2s.h" - #include "device/MK70F15/MK70F15_lcdc.h" - #include "device/MK70F15/MK70F15_llwu.h" - #include "device/MK70F15/MK70F15_lmem.h" - #include "device/MK70F15/MK70F15_lptmr.h" - #include "device/MK70F15/MK70F15_mcg.h" - #include "device/MK70F15/MK70F15_mcm.h" - #include "device/MK70F15/MK70F15_mpu.h" - #include "device/MK70F15/MK70F15_nfc.h" - #include "device/MK70F15/MK70F15_nv.h" - #include "device/MK70F15/MK70F15_osc.h" - #include "device/MK70F15/MK70F15_pdb.h" - #include "device/MK70F15/MK70F15_pit.h" - #include "device/MK70F15/MK70F15_pmc.h" - #include "device/MK70F15/MK70F15_port.h" - #include "device/MK70F15/MK70F15_rcm.h" - #include "device/MK70F15/MK70F15_rfsys.h" - #include "device/MK70F15/MK70F15_rfvbat.h" - #include "device/MK70F15/MK70F15_rng.h" - #include "device/MK70F15/MK70F15_rtc.h" - #include "device/MK70F15/MK70F15_sdhc.h" - #include "device/MK70F15/MK70F15_sim.h" - #include "device/MK70F15/MK70F15_smc.h" - #include "device/MK70F15/MK70F15_spi.h" - #include "device/MK70F15/MK70F15_tsi.h" - #include "device/MK70F15/MK70F15_uart.h" - #include "device/MK70F15/MK70F15_usb.h" - #include "device/MK70F15/MK70F15_usbdcd.h" - #include "device/MK70F15/MK70F15_usbhs.h" - #include "device/MK70F15/MK70F15_vref.h" - #include "device/MK70F15/MK70F15_wdog.h" - -#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \ - defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \ - defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4)) - - #define KL02Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL02Z4/MKL02Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL02Z4/MKL02Z4_adc.h" - #include "device/MKL02Z4/MKL02Z4_cmp.h" - #include "device/MKL02Z4/MKL02Z4_fgpio.h" - #include "device/MKL02Z4/MKL02Z4_ftfa.h" - #include "device/MKL02Z4/MKL02Z4_gpio.h" - #include "device/MKL02Z4/MKL02Z4_i2c.h" - #include "device/MKL02Z4/MKL02Z4_lptmr.h" - #include "device/MKL02Z4/MKL02Z4_mcg.h" - #include "device/MKL02Z4/MKL02Z4_mcm.h" - #include "device/MKL02Z4/MKL02Z4_mtb.h" - #include "device/MKL02Z4/MKL02Z4_mtbdwt.h" - #include "device/MKL02Z4/MKL02Z4_nv.h" - #include "device/MKL02Z4/MKL02Z4_osc.h" - #include "device/MKL02Z4/MKL02Z4_pmc.h" - #include "device/MKL02Z4/MKL02Z4_port.h" - #include "device/MKL02Z4/MKL02Z4_rcm.h" - #include "device/MKL02Z4/MKL02Z4_rom.h" - #include "device/MKL02Z4/MKL02Z4_sim.h" - #include "device/MKL02Z4/MKL02Z4_smc.h" - #include "device/MKL02Z4/MKL02Z4_spi.h" - #include "device/MKL02Z4/MKL02Z4_tpm.h" - #include "device/MKL02Z4/MKL02Z4_uart0.h" - -#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \ - defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \ - defined(CPU_MKL03Z32VFK4)) - - #define KL03Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL03Z4/MKL03Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL03Z4/MKL03Z4_adc.h" - #include "device/MKL03Z4/MKL03Z4_cmp.h" - #include "device/MKL03Z4/MKL03Z4_fgpio.h" - #include "device/MKL03Z4/MKL03Z4_ftfa.h" - #include "device/MKL03Z4/MKL03Z4_gpio.h" - #include "device/MKL03Z4/MKL03Z4_i2c.h" - #include "device/MKL03Z4/MKL03Z4_llwu.h" - #include "device/MKL03Z4/MKL03Z4_lptmr.h" - #include "device/MKL03Z4/MKL03Z4_lpuart.h" - #include "device/MKL03Z4/MKL03Z4_mcg.h" - #include "device/MKL03Z4/MKL03Z4_mcm.h" - #include "device/MKL03Z4/MKL03Z4_mtb.h" - #include "device/MKL03Z4/MKL03Z4_mtbdwt.h" - #include "device/MKL03Z4/MKL03Z4_nv.h" - #include "device/MKL03Z4/MKL03Z4_osc.h" - #include "device/MKL03Z4/MKL03Z4_pmc.h" - #include "device/MKL03Z4/MKL03Z4_port.h" - #include "device/MKL03Z4/MKL03Z4_rcm.h" - #include "device/MKL03Z4/MKL03Z4_rfsys.h" - #include "device/MKL03Z4/MKL03Z4_rom.h" - #include "device/MKL03Z4/MKL03Z4_rtc.h" - #include "device/MKL03Z4/MKL03Z4_sim.h" - #include "device/MKL03Z4/MKL03Z4_smc.h" - #include "device/MKL03Z4/MKL03Z4_spi.h" - #include "device/MKL03Z4/MKL03Z4_tpm.h" - #include "device/MKL03Z4/MKL03Z4_vref.h" - -#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \ - defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ - defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ - defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)) - - #define KL05Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL05Z4/MKL05Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL05Z4/MKL05Z4_adc.h" - #include "device/MKL05Z4/MKL05Z4_cmp.h" - #include "device/MKL05Z4/MKL05Z4_dac.h" - #include "device/MKL05Z4/MKL05Z4_dma.h" - #include "device/MKL05Z4/MKL05Z4_dmamux.h" - #include "device/MKL05Z4/MKL05Z4_fgpio.h" - #include "device/MKL05Z4/MKL05Z4_ftfa.h" - #include "device/MKL05Z4/MKL05Z4_gpio.h" - #include "device/MKL05Z4/MKL05Z4_i2c.h" - #include "device/MKL05Z4/MKL05Z4_llwu.h" - #include "device/MKL05Z4/MKL05Z4_lptmr.h" - #include "device/MKL05Z4/MKL05Z4_mcg.h" - #include "device/MKL05Z4/MKL05Z4_mcm.h" - #include "device/MKL05Z4/MKL05Z4_mtb.h" - #include "device/MKL05Z4/MKL05Z4_mtbdwt.h" - #include "device/MKL05Z4/MKL05Z4_nv.h" - #include "device/MKL05Z4/MKL05Z4_osc.h" - #include "device/MKL05Z4/MKL05Z4_pit.h" - #include "device/MKL05Z4/MKL05Z4_pmc.h" - #include "device/MKL05Z4/MKL05Z4_port.h" - #include "device/MKL05Z4/MKL05Z4_rcm.h" - #include "device/MKL05Z4/MKL05Z4_rom.h" - #include "device/MKL05Z4/MKL05Z4_rtc.h" - #include "device/MKL05Z4/MKL05Z4_sim.h" - #include "device/MKL05Z4/MKL05Z4_smc.h" - #include "device/MKL05Z4/MKL05Z4_spi.h" - #include "device/MKL05Z4/MKL05Z4_tpm.h" - #include "device/MKL05Z4/MKL05Z4_tsi.h" - #include "device/MKL05Z4/MKL05Z4_uart0.h" - -#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ - defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ - defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4)) - - #define KL13Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL13Z4/MKL13Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL13Z4/MKL13Z4_adc.h" - #include "device/MKL13Z4/MKL13Z4_cmp.h" - #include "device/MKL13Z4/MKL13Z4_dac.h" - #include "device/MKL13Z4/MKL13Z4_dma.h" - #include "device/MKL13Z4/MKL13Z4_dmamux.h" - #include "device/MKL13Z4/MKL13Z4_flexio.h" - #include "device/MKL13Z4/MKL13Z4_ftfa.h" - #include "device/MKL13Z4/MKL13Z4_gpio.h" - #include "device/MKL13Z4/MKL13Z4_i2c.h" - #include "device/MKL13Z4/MKL13Z4_i2s.h" - #include "device/MKL13Z4/MKL13Z4_llwu.h" - #include "device/MKL13Z4/MKL13Z4_lptmr.h" - #include "device/MKL13Z4/MKL13Z4_lpuart.h" - #include "device/MKL13Z4/MKL13Z4_mcg.h" - #include "device/MKL13Z4/MKL13Z4_mcm.h" - #include "device/MKL13Z4/MKL13Z4_mtb.h" - #include "device/MKL13Z4/MKL13Z4_mtbdwt.h" - #include "device/MKL13Z4/MKL13Z4_nv.h" - #include "device/MKL13Z4/MKL13Z4_osc.h" - #include "device/MKL13Z4/MKL13Z4_pit.h" - #include "device/MKL13Z4/MKL13Z4_pmc.h" - #include "device/MKL13Z4/MKL13Z4_port.h" - #include "device/MKL13Z4/MKL13Z4_rcm.h" - #include "device/MKL13Z4/MKL13Z4_rom.h" - #include "device/MKL13Z4/MKL13Z4_rtc.h" - #include "device/MKL13Z4/MKL13Z4_sim.h" - #include "device/MKL13Z4/MKL13Z4_smc.h" - #include "device/MKL13Z4/MKL13Z4_spi.h" - #include "device/MKL13Z4/MKL13Z4_tpm.h" - #include "device/MKL13Z4/MKL13Z4_uart.h" - #include "device/MKL13Z4/MKL13Z4_vref.h" - -#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ - defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ - defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4)) - - #define KL23Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL23Z4/MKL23Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL23Z4/MKL23Z4_adc.h" - #include "device/MKL23Z4/MKL23Z4_cmp.h" - #include "device/MKL23Z4/MKL23Z4_dac.h" - #include "device/MKL23Z4/MKL23Z4_dma.h" - #include "device/MKL23Z4/MKL23Z4_dmamux.h" - #include "device/MKL23Z4/MKL23Z4_flexio.h" - #include "device/MKL23Z4/MKL23Z4_ftfa.h" - #include "device/MKL23Z4/MKL23Z4_gpio.h" - #include "device/MKL23Z4/MKL23Z4_i2c.h" - #include "device/MKL23Z4/MKL23Z4_i2s.h" - #include "device/MKL23Z4/MKL23Z4_llwu.h" - #include "device/MKL23Z4/MKL23Z4_lptmr.h" - #include "device/MKL23Z4/MKL23Z4_lpuart.h" - #include "device/MKL23Z4/MKL23Z4_mcg.h" - #include "device/MKL23Z4/MKL23Z4_mcm.h" - #include "device/MKL23Z4/MKL23Z4_mtb.h" - #include "device/MKL23Z4/MKL23Z4_mtbdwt.h" - #include "device/MKL23Z4/MKL23Z4_nv.h" - #include "device/MKL23Z4/MKL23Z4_osc.h" - #include "device/MKL23Z4/MKL23Z4_pit.h" - #include "device/MKL23Z4/MKL23Z4_pmc.h" - #include "device/MKL23Z4/MKL23Z4_port.h" - #include "device/MKL23Z4/MKL23Z4_rcm.h" - #include "device/MKL23Z4/MKL23Z4_rom.h" - #include "device/MKL23Z4/MKL23Z4_rtc.h" - #include "device/MKL23Z4/MKL23Z4_sim.h" - #include "device/MKL23Z4/MKL23Z4_smc.h" - #include "device/MKL23Z4/MKL23Z4_spi.h" - #include "device/MKL23Z4/MKL23Z4_tpm.h" - #include "device/MKL23Z4/MKL23Z4_uart.h" - #include "device/MKL23Z4/MKL23Z4_usb.h" - #include "device/MKL23Z4/MKL23Z4_vref.h" - -#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ - defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)) - - #define KL25Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL25Z4/MKL25Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL25Z4/MKL25Z4_adc.h" - #include "device/MKL25Z4/MKL25Z4_cmp.h" - #include "device/MKL25Z4/MKL25Z4_dac.h" - #include "device/MKL25Z4/MKL25Z4_dma.h" - #include "device/MKL25Z4/MKL25Z4_dmamux.h" - #include "device/MKL25Z4/MKL25Z4_fgpio.h" - #include "device/MKL25Z4/MKL25Z4_ftfa.h" - #include "device/MKL25Z4/MKL25Z4_gpio.h" - #include "device/MKL25Z4/MKL25Z4_i2c.h" - #include "device/MKL25Z4/MKL25Z4_llwu.h" - #include "device/MKL25Z4/MKL25Z4_lptmr.h" - #include "device/MKL25Z4/MKL25Z4_mcg.h" - #include "device/MKL25Z4/MKL25Z4_mcm.h" - #include "device/MKL25Z4/MKL25Z4_mtb.h" - #include "device/MKL25Z4/MKL25Z4_mtbdwt.h" - #include "device/MKL25Z4/MKL25Z4_nv.h" - #include "device/MKL25Z4/MKL25Z4_osc.h" - #include "device/MKL25Z4/MKL25Z4_pit.h" - #include "device/MKL25Z4/MKL25Z4_pmc.h" - #include "device/MKL25Z4/MKL25Z4_port.h" - #include "device/MKL25Z4/MKL25Z4_rcm.h" - #include "device/MKL25Z4/MKL25Z4_rom.h" - #include "device/MKL25Z4/MKL25Z4_rtc.h" - #include "device/MKL25Z4/MKL25Z4_sim.h" - #include "device/MKL25Z4/MKL25Z4_smc.h" - #include "device/MKL25Z4/MKL25Z4_spi.h" - #include "device/MKL25Z4/MKL25Z4_tpm.h" - #include "device/MKL25Z4/MKL25Z4_tsi.h" - #include "device/MKL25Z4/MKL25Z4_uart.h" - #include "device/MKL25Z4/MKL25Z4_uart0.h" - #include "device/MKL25Z4/MKL25Z4_usb.h" - -#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \ - defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \ - defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \ - defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ - defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4)) - - #define KL26Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL26Z4/MKL26Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL26Z4/MKL26Z4_adc.h" - #include "device/MKL26Z4/MKL26Z4_cmp.h" - #include "device/MKL26Z4/MKL26Z4_dac.h" - #include "device/MKL26Z4/MKL26Z4_dma.h" - #include "device/MKL26Z4/MKL26Z4_dmamux.h" - #include "device/MKL26Z4/MKL26Z4_fgpio.h" - #include "device/MKL26Z4/MKL26Z4_ftfa.h" - #include "device/MKL26Z4/MKL26Z4_gpio.h" - #include "device/MKL26Z4/MKL26Z4_i2c.h" - #include "device/MKL26Z4/MKL26Z4_i2s.h" - #include "device/MKL26Z4/MKL26Z4_llwu.h" - #include "device/MKL26Z4/MKL26Z4_lptmr.h" - #include "device/MKL26Z4/MKL26Z4_mcg.h" - #include "device/MKL26Z4/MKL26Z4_mcm.h" - #include "device/MKL26Z4/MKL26Z4_mtb.h" - #include "device/MKL26Z4/MKL26Z4_mtbdwt.h" - #include "device/MKL26Z4/MKL26Z4_nv.h" - #include "device/MKL26Z4/MKL26Z4_osc.h" - #include "device/MKL26Z4/MKL26Z4_pit.h" - #include "device/MKL26Z4/MKL26Z4_pmc.h" - #include "device/MKL26Z4/MKL26Z4_port.h" - #include "device/MKL26Z4/MKL26Z4_rcm.h" - #include "device/MKL26Z4/MKL26Z4_rom.h" - #include "device/MKL26Z4/MKL26Z4_rtc.h" - #include "device/MKL26Z4/MKL26Z4_sim.h" - #include "device/MKL26Z4/MKL26Z4_smc.h" - #include "device/MKL26Z4/MKL26Z4_spi.h" - #include "device/MKL26Z4/MKL26Z4_tpm.h" - #include "device/MKL26Z4/MKL26Z4_tsi.h" - #include "device/MKL26Z4/MKL26Z4_uart.h" - #include "device/MKL26Z4/MKL26Z4_uart0.h" - #include "device/MKL26Z4/MKL26Z4_usb.h" - -#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \ - defined(CPU_MKL33Z256VMP4)) - - #define KL33Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL33Z4/MKL33Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL33Z4/MKL33Z4_adc.h" - #include "device/MKL33Z4/MKL33Z4_cmp.h" - #include "device/MKL33Z4/MKL33Z4_dac.h" - #include "device/MKL33Z4/MKL33Z4_dma.h" - #include "device/MKL33Z4/MKL33Z4_dmamux.h" - #include "device/MKL33Z4/MKL33Z4_flexio.h" - #include "device/MKL33Z4/MKL33Z4_ftfa.h" - #include "device/MKL33Z4/MKL33Z4_gpio.h" - #include "device/MKL33Z4/MKL33Z4_i2c.h" - #include "device/MKL33Z4/MKL33Z4_i2s.h" - #include "device/MKL33Z4/MKL33Z4_lcd.h" - #include "device/MKL33Z4/MKL33Z4_llwu.h" - #include "device/MKL33Z4/MKL33Z4_lptmr.h" - #include "device/MKL33Z4/MKL33Z4_lpuart.h" - #include "device/MKL33Z4/MKL33Z4_mcg.h" - #include "device/MKL33Z4/MKL33Z4_mcm.h" - #include "device/MKL33Z4/MKL33Z4_mtb.h" - #include "device/MKL33Z4/MKL33Z4_mtbdwt.h" - #include "device/MKL33Z4/MKL33Z4_nv.h" - #include "device/MKL33Z4/MKL33Z4_osc.h" - #include "device/MKL33Z4/MKL33Z4_pit.h" - #include "device/MKL33Z4/MKL33Z4_pmc.h" - #include "device/MKL33Z4/MKL33Z4_port.h" - #include "device/MKL33Z4/MKL33Z4_rcm.h" - #include "device/MKL33Z4/MKL33Z4_rom.h" - #include "device/MKL33Z4/MKL33Z4_rtc.h" - #include "device/MKL33Z4/MKL33Z4_sim.h" - #include "device/MKL33Z4/MKL33Z4_smc.h" - #include "device/MKL33Z4/MKL33Z4_spi.h" - #include "device/MKL33Z4/MKL33Z4_tpm.h" - #include "device/MKL33Z4/MKL33Z4_uart.h" - #include "device/MKL33Z4/MKL33Z4_vref.h" - -#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \ - defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)) - - #define KL43Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL43Z4/MKL43Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL43Z4/MKL43Z4_adc.h" - #include "device/MKL43Z4/MKL43Z4_cmp.h" - #include "device/MKL43Z4/MKL43Z4_dac.h" - #include "device/MKL43Z4/MKL43Z4_dma.h" - #include "device/MKL43Z4/MKL43Z4_dmamux.h" - #include "device/MKL43Z4/MKL43Z4_flexio.h" - #include "device/MKL43Z4/MKL43Z4_ftfa.h" - #include "device/MKL43Z4/MKL43Z4_gpio.h" - #include "device/MKL43Z4/MKL43Z4_i2c.h" - #include "device/MKL43Z4/MKL43Z4_i2s.h" - #include "device/MKL43Z4/MKL43Z4_lcd.h" - #include "device/MKL43Z4/MKL43Z4_llwu.h" - #include "device/MKL43Z4/MKL43Z4_lptmr.h" - #include "device/MKL43Z4/MKL43Z4_lpuart.h" - #include "device/MKL43Z4/MKL43Z4_mcg.h" - #include "device/MKL43Z4/MKL43Z4_mcm.h" - #include "device/MKL43Z4/MKL43Z4_mtb.h" - #include "device/MKL43Z4/MKL43Z4_mtbdwt.h" - #include "device/MKL43Z4/MKL43Z4_nv.h" - #include "device/MKL43Z4/MKL43Z4_osc.h" - #include "device/MKL43Z4/MKL43Z4_pit.h" - #include "device/MKL43Z4/MKL43Z4_pmc.h" - #include "device/MKL43Z4/MKL43Z4_port.h" - #include "device/MKL43Z4/MKL43Z4_rcm.h" - #include "device/MKL43Z4/MKL43Z4_rom.h" - #include "device/MKL43Z4/MKL43Z4_rtc.h" - #include "device/MKL43Z4/MKL43Z4_sim.h" - #include "device/MKL43Z4/MKL43Z4_smc.h" - #include "device/MKL43Z4/MKL43Z4_spi.h" - #include "device/MKL43Z4/MKL43Z4_tpm.h" - #include "device/MKL43Z4/MKL43Z4_uart.h" - #include "device/MKL43Z4/MKL43Z4_usb.h" - #include "device/MKL43Z4/MKL43Z4_vref.h" - -#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)) - - #define KL46Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL46Z4/MKL46Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL46Z4/MKL46Z4_adc.h" - #include "device/MKL46Z4/MKL46Z4_cmp.h" - #include "device/MKL46Z4/MKL46Z4_dac.h" - #include "device/MKL46Z4/MKL46Z4_dma.h" - #include "device/MKL46Z4/MKL46Z4_dmamux.h" - #include "device/MKL46Z4/MKL46Z4_fgpio.h" - #include "device/MKL46Z4/MKL46Z4_ftfa.h" - #include "device/MKL46Z4/MKL46Z4_gpio.h" - #include "device/MKL46Z4/MKL46Z4_i2c.h" - #include "device/MKL46Z4/MKL46Z4_i2s.h" - #include "device/MKL46Z4/MKL46Z4_lcd.h" - #include "device/MKL46Z4/MKL46Z4_llwu.h" - #include "device/MKL46Z4/MKL46Z4_lptmr.h" - #include "device/MKL46Z4/MKL46Z4_mcg.h" - #include "device/MKL46Z4/MKL46Z4_mcm.h" - #include "device/MKL46Z4/MKL46Z4_mtb.h" - #include "device/MKL46Z4/MKL46Z4_mtbdwt.h" - #include "device/MKL46Z4/MKL46Z4_nv.h" - #include "device/MKL46Z4/MKL46Z4_osc.h" - #include "device/MKL46Z4/MKL46Z4_pit.h" - #include "device/MKL46Z4/MKL46Z4_pmc.h" - #include "device/MKL46Z4/MKL46Z4_port.h" - #include "device/MKL46Z4/MKL46Z4_rcm.h" - #include "device/MKL46Z4/MKL46Z4_rom.h" - #include "device/MKL46Z4/MKL46Z4_rtc.h" - #include "device/MKL46Z4/MKL46Z4_sim.h" - #include "device/MKL46Z4/MKL46Z4_smc.h" - #include "device/MKL46Z4/MKL46Z4_spi.h" - #include "device/MKL46Z4/MKL46Z4_tpm.h" - #include "device/MKL46Z4/MKL46Z4_tsi.h" - #include "device/MKL46Z4/MKL46Z4_uart.h" - #include "device/MKL46Z4/MKL46Z4_uart0.h" - #include "device/MKL46Z4/MKL46Z4_usb.h" - -#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)) - - #define KV30F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV30F12810/MKV30F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV30F12810/MKV30F12810_adc.h" - #include "device/MKV30F12810/MKV30F12810_cmp.h" - #include "device/MKV30F12810/MKV30F12810_crc.h" - #include "device/MKV30F12810/MKV30F12810_dac.h" - #include "device/MKV30F12810/MKV30F12810_dma.h" - #include "device/MKV30F12810/MKV30F12810_dmamux.h" - #include "device/MKV30F12810/MKV30F12810_ewm.h" - #include "device/MKV30F12810/MKV30F12810_fmc.h" - #include "device/MKV30F12810/MKV30F12810_ftfa.h" - #include "device/MKV30F12810/MKV30F12810_ftm.h" - #include "device/MKV30F12810/MKV30F12810_gpio.h" - #include "device/MKV30F12810/MKV30F12810_i2c.h" - #include "device/MKV30F12810/MKV30F12810_llwu.h" - #include "device/MKV30F12810/MKV30F12810_lptmr.h" - #include "device/MKV30F12810/MKV30F12810_mcg.h" - #include "device/MKV30F12810/MKV30F12810_mcm.h" - #include "device/MKV30F12810/MKV30F12810_nv.h" - #include "device/MKV30F12810/MKV30F12810_osc.h" - #include "device/MKV30F12810/MKV30F12810_pdb.h" - #include "device/MKV30F12810/MKV30F12810_pit.h" - #include "device/MKV30F12810/MKV30F12810_pmc.h" - #include "device/MKV30F12810/MKV30F12810_port.h" - #include "device/MKV30F12810/MKV30F12810_rcm.h" - #include "device/MKV30F12810/MKV30F12810_sim.h" - #include "device/MKV30F12810/MKV30F12810_smc.h" - #include "device/MKV30F12810/MKV30F12810_spi.h" - #include "device/MKV30F12810/MKV30F12810_uart.h" - #include "device/MKV30F12810/MKV30F12810_vref.h" - #include "device/MKV30F12810/MKV30F12810_wdog.h" - -#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)) - - #define KV31F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV31F12810/MKV31F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV31F12810/MKV31F12810_adc.h" - #include "device/MKV31F12810/MKV31F12810_cmp.h" - #include "device/MKV31F12810/MKV31F12810_crc.h" - #include "device/MKV31F12810/MKV31F12810_dac.h" - #include "device/MKV31F12810/MKV31F12810_dma.h" - #include "device/MKV31F12810/MKV31F12810_dmamux.h" - #include "device/MKV31F12810/MKV31F12810_ewm.h" - #include "device/MKV31F12810/MKV31F12810_fmc.h" - #include "device/MKV31F12810/MKV31F12810_ftfa.h" - #include "device/MKV31F12810/MKV31F12810_ftm.h" - #include "device/MKV31F12810/MKV31F12810_gpio.h" - #include "device/MKV31F12810/MKV31F12810_i2c.h" - #include "device/MKV31F12810/MKV31F12810_llwu.h" - #include "device/MKV31F12810/MKV31F12810_lptmr.h" - #include "device/MKV31F12810/MKV31F12810_lpuart.h" - #include "device/MKV31F12810/MKV31F12810_mcg.h" - #include "device/MKV31F12810/MKV31F12810_mcm.h" - #include "device/MKV31F12810/MKV31F12810_nv.h" - #include "device/MKV31F12810/MKV31F12810_osc.h" - #include "device/MKV31F12810/MKV31F12810_pdb.h" - #include "device/MKV31F12810/MKV31F12810_pit.h" - #include "device/MKV31F12810/MKV31F12810_pmc.h" - #include "device/MKV31F12810/MKV31F12810_port.h" - #include "device/MKV31F12810/MKV31F12810_rcm.h" - #include "device/MKV31F12810/MKV31F12810_rfsys.h" - #include "device/MKV31F12810/MKV31F12810_sim.h" - #include "device/MKV31F12810/MKV31F12810_smc.h" - #include "device/MKV31F12810/MKV31F12810_spi.h" - #include "device/MKV31F12810/MKV31F12810_uart.h" - #include "device/MKV31F12810/MKV31F12810_vref.h" - #include "device/MKV31F12810/MKV31F12810_wdog.h" - -#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)) - - #define KV31F25612_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV31F25612/MKV31F25612.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV31F25612/MKV31F25612_adc.h" - #include "device/MKV31F25612/MKV31F25612_cmp.h" - #include "device/MKV31F25612/MKV31F25612_crc.h" - #include "device/MKV31F25612/MKV31F25612_dac.h" - #include "device/MKV31F25612/MKV31F25612_dma.h" - #include "device/MKV31F25612/MKV31F25612_dmamux.h" - #include "device/MKV31F25612/MKV31F25612_ewm.h" - #include "device/MKV31F25612/MKV31F25612_fmc.h" - #include "device/MKV31F25612/MKV31F25612_ftfa.h" - #include "device/MKV31F25612/MKV31F25612_ftm.h" - #include "device/MKV31F25612/MKV31F25612_gpio.h" - #include "device/MKV31F25612/MKV31F25612_i2c.h" - #include "device/MKV31F25612/MKV31F25612_llwu.h" - #include "device/MKV31F25612/MKV31F25612_lptmr.h" - #include "device/MKV31F25612/MKV31F25612_lpuart.h" - #include "device/MKV31F25612/MKV31F25612_mcg.h" - #include "device/MKV31F25612/MKV31F25612_mcm.h" - #include "device/MKV31F25612/MKV31F25612_nv.h" - #include "device/MKV31F25612/MKV31F25612_osc.h" - #include "device/MKV31F25612/MKV31F25612_pdb.h" - #include "device/MKV31F25612/MKV31F25612_pit.h" - #include "device/MKV31F25612/MKV31F25612_pmc.h" - #include "device/MKV31F25612/MKV31F25612_port.h" - #include "device/MKV31F25612/MKV31F25612_rcm.h" - #include "device/MKV31F25612/MKV31F25612_rfsys.h" - #include "device/MKV31F25612/MKV31F25612_rng.h" - #include "device/MKV31F25612/MKV31F25612_sim.h" - #include "device/MKV31F25612/MKV31F25612_smc.h" - #include "device/MKV31F25612/MKV31F25612_spi.h" - #include "device/MKV31F25612/MKV31F25612_uart.h" - #include "device/MKV31F25612/MKV31F25612_vref.h" - #include "device/MKV31F25612/MKV31F25612_wdog.h" - -#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)) - - #define KV31F51212_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV31F51212/MKV31F51212.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV31F51212/MKV31F51212_adc.h" - #include "device/MKV31F51212/MKV31F51212_cmp.h" - #include "device/MKV31F51212/MKV31F51212_crc.h" - #include "device/MKV31F51212/MKV31F51212_dac.h" - #include "device/MKV31F51212/MKV31F51212_dma.h" - #include "device/MKV31F51212/MKV31F51212_dmamux.h" - #include "device/MKV31F51212/MKV31F51212_ewm.h" - #include "device/MKV31F51212/MKV31F51212_fb.h" - #include "device/MKV31F51212/MKV31F51212_fmc.h" - #include "device/MKV31F51212/MKV31F51212_ftfa.h" - #include "device/MKV31F51212/MKV31F51212_ftm.h" - #include "device/MKV31F51212/MKV31F51212_gpio.h" - #include "device/MKV31F51212/MKV31F51212_i2c.h" - #include "device/MKV31F51212/MKV31F51212_llwu.h" - #include "device/MKV31F51212/MKV31F51212_lptmr.h" - #include "device/MKV31F51212/MKV31F51212_lpuart.h" - #include "device/MKV31F51212/MKV31F51212_mcg.h" - #include "device/MKV31F51212/MKV31F51212_mcm.h" - #include "device/MKV31F51212/MKV31F51212_nv.h" - #include "device/MKV31F51212/MKV31F51212_osc.h" - #include "device/MKV31F51212/MKV31F51212_pdb.h" - #include "device/MKV31F51212/MKV31F51212_pit.h" - #include "device/MKV31F51212/MKV31F51212_pmc.h" - #include "device/MKV31F51212/MKV31F51212_port.h" - #include "device/MKV31F51212/MKV31F51212_rcm.h" - #include "device/MKV31F51212/MKV31F51212_rfsys.h" - #include "device/MKV31F51212/MKV31F51212_rng.h" - #include "device/MKV31F51212/MKV31F51212_sim.h" - #include "device/MKV31F51212/MKV31F51212_smc.h" - #include "device/MKV31F51212/MKV31F51212_spi.h" - #include "device/MKV31F51212/MKV31F51212_uart.h" - #include "device/MKV31F51212/MKV31F51212_vref.h" - #include "device/MKV31F51212/MKV31F51212_wdog.h" - -#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15)) - - #define KV40F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV40F15/MKV40F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV40F15/MKV40F15_adc.h" - #include "device/MKV40F15/MKV40F15_aoi.h" - #include "device/MKV40F15/MKV40F15_can.h" - #include "device/MKV40F15/MKV40F15_cmp.h" - #include "device/MKV40F15/MKV40F15_crc.h" - #include "device/MKV40F15/MKV40F15_dma.h" - #include "device/MKV40F15/MKV40F15_dmamux.h" - #include "device/MKV40F15/MKV40F15_enc.h" - #include "device/MKV40F15/MKV40F15_ewm.h" - #include "device/MKV40F15/MKV40F15_fmc.h" - #include "device/MKV40F15/MKV40F15_ftfa.h" - #include "device/MKV40F15/MKV40F15_ftm.h" - #include "device/MKV40F15/MKV40F15_gpio.h" - #include "device/MKV40F15/MKV40F15_i2c.h" - #include "device/MKV40F15/MKV40F15_llwu.h" - #include "device/MKV40F15/MKV40F15_lptmr.h" - #include "device/MKV40F15/MKV40F15_mcg.h" - #include "device/MKV40F15/MKV40F15_mcm.h" - #include "device/MKV40F15/MKV40F15_nv.h" - #include "device/MKV40F15/MKV40F15_osc.h" - #include "device/MKV40F15/MKV40F15_pdb.h" - #include "device/MKV40F15/MKV40F15_pit.h" - #include "device/MKV40F15/MKV40F15_pmc.h" - #include "device/MKV40F15/MKV40F15_port.h" - #include "device/MKV40F15/MKV40F15_rcm.h" - #include "device/MKV40F15/MKV40F15_sim.h" - #include "device/MKV40F15/MKV40F15_smc.h" - #include "device/MKV40F15/MKV40F15_spi.h" - #include "device/MKV40F15/MKV40F15_uart.h" - #include "device/MKV40F15/MKV40F15_vref.h" - #include "device/MKV40F15/MKV40F15_wdog.h" - #include "device/MKV40F15/MKV40F15_xbara.h" - #include "device/MKV40F15/MKV40F15_xbarb.h" - -#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15)) - - #define KV43F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV43F15/MKV43F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV43F15/MKV43F15_adc.h" - #include "device/MKV43F15/MKV43F15_aoi.h" - #include "device/MKV43F15/MKV43F15_can.h" - #include "device/MKV43F15/MKV43F15_cmp.h" - #include "device/MKV43F15/MKV43F15_crc.h" - #include "device/MKV43F15/MKV43F15_dma.h" - #include "device/MKV43F15/MKV43F15_dmamux.h" - #include "device/MKV43F15/MKV43F15_enc.h" - #include "device/MKV43F15/MKV43F15_ewm.h" - #include "device/MKV43F15/MKV43F15_fmc.h" - #include "device/MKV43F15/MKV43F15_ftfa.h" - #include "device/MKV43F15/MKV43F15_gpio.h" - #include "device/MKV43F15/MKV43F15_i2c.h" - #include "device/MKV43F15/MKV43F15_llwu.h" - #include "device/MKV43F15/MKV43F15_lptmr.h" - #include "device/MKV43F15/MKV43F15_mcg.h" - #include "device/MKV43F15/MKV43F15_mcm.h" - #include "device/MKV43F15/MKV43F15_nv.h" - #include "device/MKV43F15/MKV43F15_osc.h" - #include "device/MKV43F15/MKV43F15_pdb.h" - #include "device/MKV43F15/MKV43F15_pit.h" - #include "device/MKV43F15/MKV43F15_pmc.h" - #include "device/MKV43F15/MKV43F15_port.h" - #include "device/MKV43F15/MKV43F15_pwm.h" - #include "device/MKV43F15/MKV43F15_rcm.h" - #include "device/MKV43F15/MKV43F15_sim.h" - #include "device/MKV43F15/MKV43F15_smc.h" - #include "device/MKV43F15/MKV43F15_spi.h" - #include "device/MKV43F15/MKV43F15_uart.h" - #include "device/MKV43F15/MKV43F15_vref.h" - #include "device/MKV43F15/MKV43F15_wdog.h" - #include "device/MKV43F15/MKV43F15_xbara.h" - #include "device/MKV43F15/MKV43F15_xbarb.h" - -#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)) - - #define KV44F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV44F15/MKV44F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV44F15/MKV44F15_adc.h" - #include "device/MKV44F15/MKV44F15_aoi.h" - #include "device/MKV44F15/MKV44F15_can.h" - #include "device/MKV44F15/MKV44F15_cmp.h" - #include "device/MKV44F15/MKV44F15_crc.h" - #include "device/MKV44F15/MKV44F15_dac.h" - #include "device/MKV44F15/MKV44F15_dma.h" - #include "device/MKV44F15/MKV44F15_dmamux.h" - #include "device/MKV44F15/MKV44F15_enc.h" - #include "device/MKV44F15/MKV44F15_ewm.h" - #include "device/MKV44F15/MKV44F15_fmc.h" - #include "device/MKV44F15/MKV44F15_ftfa.h" - #include "device/MKV44F15/MKV44F15_gpio.h" - #include "device/MKV44F15/MKV44F15_i2c.h" - #include "device/MKV44F15/MKV44F15_llwu.h" - #include "device/MKV44F15/MKV44F15_lptmr.h" - #include "device/MKV44F15/MKV44F15_mcg.h" - #include "device/MKV44F15/MKV44F15_mcm.h" - #include "device/MKV44F15/MKV44F15_nv.h" - #include "device/MKV44F15/MKV44F15_osc.h" - #include "device/MKV44F15/MKV44F15_pdb.h" - #include "device/MKV44F15/MKV44F15_pit.h" - #include "device/MKV44F15/MKV44F15_pmc.h" - #include "device/MKV44F15/MKV44F15_port.h" - #include "device/MKV44F15/MKV44F15_pwm.h" - #include "device/MKV44F15/MKV44F15_rcm.h" - #include "device/MKV44F15/MKV44F15_sim.h" - #include "device/MKV44F15/MKV44F15_smc.h" - #include "device/MKV44F15/MKV44F15_spi.h" - #include "device/MKV44F15/MKV44F15_uart.h" - #include "device/MKV44F15/MKV44F15_vref.h" - #include "device/MKV44F15/MKV44F15_wdog.h" - #include "device/MKV44F15/MKV44F15_xbara.h" - #include "device/MKV44F15/MKV44F15_xbarb.h" - -#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ - defined(CPU_MKV45F256VLL15)) - - #define KV45F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV45F15/MKV45F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV45F15/MKV45F15_adc.h" - #include "device/MKV45F15/MKV45F15_aoi.h" - #include "device/MKV45F15/MKV45F15_can.h" - #include "device/MKV45F15/MKV45F15_cmp.h" - #include "device/MKV45F15/MKV45F15_crc.h" - #include "device/MKV45F15/MKV45F15_dma.h" - #include "device/MKV45F15/MKV45F15_dmamux.h" - #include "device/MKV45F15/MKV45F15_enc.h" - #include "device/MKV45F15/MKV45F15_ewm.h" - #include "device/MKV45F15/MKV45F15_fmc.h" - #include "device/MKV45F15/MKV45F15_ftfa.h" - #include "device/MKV45F15/MKV45F15_ftm.h" - #include "device/MKV45F15/MKV45F15_gpio.h" - #include "device/MKV45F15/MKV45F15_i2c.h" - #include "device/MKV45F15/MKV45F15_llwu.h" - #include "device/MKV45F15/MKV45F15_lptmr.h" - #include "device/MKV45F15/MKV45F15_mcg.h" - #include "device/MKV45F15/MKV45F15_mcm.h" - #include "device/MKV45F15/MKV45F15_nv.h" - #include "device/MKV45F15/MKV45F15_osc.h" - #include "device/MKV45F15/MKV45F15_pdb.h" - #include "device/MKV45F15/MKV45F15_pit.h" - #include "device/MKV45F15/MKV45F15_pmc.h" - #include "device/MKV45F15/MKV45F15_port.h" - #include "device/MKV45F15/MKV45F15_pwm.h" - #include "device/MKV45F15/MKV45F15_rcm.h" - #include "device/MKV45F15/MKV45F15_sim.h" - #include "device/MKV45F15/MKV45F15_smc.h" - #include "device/MKV45F15/MKV45F15_spi.h" - #include "device/MKV45F15/MKV45F15_uart.h" - #include "device/MKV45F15/MKV45F15_vref.h" - #include "device/MKV45F15/MKV45F15_wdog.h" - #include "device/MKV45F15/MKV45F15_xbara.h" - #include "device/MKV45F15/MKV45F15_xbarb.h" - -#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15)) - - #define KV46F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV46F15/MKV46F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV46F15/MKV46F15_adc.h" - #include "device/MKV46F15/MKV46F15_aoi.h" - #include "device/MKV46F15/MKV46F15_can.h" - #include "device/MKV46F15/MKV46F15_cmp.h" - #include "device/MKV46F15/MKV46F15_crc.h" - #include "device/MKV46F15/MKV46F15_dac.h" - #include "device/MKV46F15/MKV46F15_dma.h" - #include "device/MKV46F15/MKV46F15_dmamux.h" - #include "device/MKV46F15/MKV46F15_enc.h" - #include "device/MKV46F15/MKV46F15_ewm.h" - #include "device/MKV46F15/MKV46F15_fmc.h" - #include "device/MKV46F15/MKV46F15_ftfa.h" - #include "device/MKV46F15/MKV46F15_ftm.h" - #include "device/MKV46F15/MKV46F15_gpio.h" - #include "device/MKV46F15/MKV46F15_i2c.h" - #include "device/MKV46F15/MKV46F15_llwu.h" - #include "device/MKV46F15/MKV46F15_lptmr.h" - #include "device/MKV46F15/MKV46F15_mcg.h" - #include "device/MKV46F15/MKV46F15_mcm.h" - #include "device/MKV46F15/MKV46F15_nv.h" - #include "device/MKV46F15/MKV46F15_osc.h" - #include "device/MKV46F15/MKV46F15_pdb.h" - #include "device/MKV46F15/MKV46F15_pit.h" - #include "device/MKV46F15/MKV46F15_pmc.h" - #include "device/MKV46F15/MKV46F15_port.h" - #include "device/MKV46F15/MKV46F15_pwm.h" - #include "device/MKV46F15/MKV46F15_rcm.h" - #include "device/MKV46F15/MKV46F15_sim.h" - #include "device/MKV46F15/MKV46F15_smc.h" - #include "device/MKV46F15/MKV46F15_spi.h" - #include "device/MKV46F15/MKV46F15_uart.h" - #include "device/MKV46F15/MKV46F15_vref.h" - #include "device/MKV46F15/MKV46F15_wdog.h" - #include "device/MKV46F15/MKV46F15_xbara.h" - #include "device/MKV46F15/MKV46F15_xbarb.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/mbed_overrides.c deleted file mode 100644 index 103049260ee..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/mbed_overrides.c +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" - -// called before main - implement here if board needs it otherwise, let -// the application override this if necessary -void mbed_sdk_init() -{ - pin_function(PTA2, 1); //By default the GREEN LED is enabled. This disables it -} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - gpio_t gpio; - gpio_init_in(&gpio, PTA4); -} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.c deleted file mode 100644 index 04ae3e77286..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.c +++ /dev/null @@ -1,267 +0,0 @@ -/* -* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_phy_driver.h" - -#ifndef MBED_NO_ENET - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Define Phy API structure for MAC application*/ -const enet_phy_api_t g_enetPhyApi = -{ - phy_auto_discover, - phy_init, - phy_get_link_speed, - phy_get_link_status, - phy_get_link_duplex, -}; -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION**************************************************************** - * - * Function Name: phy_init - * Return Value: The execution status. - * Description: Initialize Phy. - * This interface provides initialize functions for Phy, This is called by enet - * initialize function. Phy is usually deault auto-negotiation. so there is no - * need to do the intialize about this. we just need to check the loop mode. - *END*********************************************************************/ -uint32_t phy_init(enet_dev_if_t * enetIfPtr) -{ - uint32_t data; - uint32_t counter; - uint32_t result; - - /* Check input parameters*/ - if (!enetIfPtr) - { - return kStatus_PHY_InvaildInput; - } - - /* Reset Phy*/ - if ((result = (enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhySR,&data))) == kStatus_PHY_Success) - { - if ((data & kEnetPhyAutoNegAble) != 0) - { - /* Set Autonegotiation*/ - enetIfPtr->macApiPtr->enet_mii_write(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr, kEnetPhyCR, kEnetPhyAutoNeg); - for (counter = 0; counter < kPhyTimeout; counter++) - { - if (enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhySR,&data)== kStatus_PHY_Success) - { - if ((data & kEnetPhyAutoNegComplete) != 0) - { - break; - } - } - } - - if (counter == kPhyTimeout) - { - return kStatus_PHY_TimeOut; - } - } - } - - if (enetIfPtr->phyCfgPtr->isLoopEnabled) - { - /* First read the current status in control register*/ - if (enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCR,&data)) - { - result = enetIfPtr->macApiPtr->enet_mii_write(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCR,(data|kEnetPhyLoop)); - } - } - - return result; -} - -/*FUNCTION**************************************************************** - * - * Function Name: phy_auto_discover - * Return Value: The execution status. - * Description: Phy address auto discover. - * This function provides a interface to get phy address using phy address auto - * discovering, this interface is used when the phy address is unknown. - *END*********************************************************************/ -uint32_t phy_auto_discover(enet_dev_if_t * enetIfPtr) -{ - uint32_t addrIdx,data; - uint32_t result = kStatus_PHY_Fail; - - /* Check input parameters*/ - if (!enetIfPtr) - { - return kStatus_PHY_InvaildInput; - } - - for (addrIdx = 0; addrIdx < 32; addrIdx++) - { - enetIfPtr->phyCfgPtr->phyAddr = addrIdx; - result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyId1,&data); - if ((result == kStatus_PHY_Success) && (data != 0) && (data != 0xffff) ) - { - return kStatus_PHY_Success; - } - } - - return result; -} - -/*FUNCTION**************************************************************** - * - * Function Name: phy_get_link_speed - * Return Value: The execution status. - * Description: Get phy link speed. - * This function provides a interface to get link speed. - *END*********************************************************************/ -uint32_t phy_get_link_speed(enet_dev_if_t * enetIfPtr, enet_phy_speed_t *status) -{ - uint32_t result = kStatus_PHY_Success; - uint32_t data; - - /* Check input parameters*/ - if ((!enetIfPtr) || (!status)) - { - return kStatus_PHY_InvaildInput; - } - - result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr, kEnetPhyCt2,&data); - if (result == kStatus_PHY_Success) - { - data &= kEnetPhySpeedDulpexMask; - if ((kEnetPhy100HalfDuplex == data) || (kEnetPhy100FullDuplex == data)) - { - *status = kEnetSpeed100M; - } - else - { - *status = kEnetSpeed10M; - } - } - - return result; -} - -/*FUNCTION**************************************************************** - * - * Function Name: phy_get_link_status - * Return Value: The execution status. - * Description: Get phy link status. - * This function provides a interface to get link status to see if the link - * status is on or off. - *END*********************************************************************/ - uint32_t phy_get_link_status(enet_dev_if_t * enetIfPtr, bool *status) -{ - uint32_t result = kStatus_PHY_Success; - uint32_t data; - - /* Check input parameters*/ - if ((!enetIfPtr) || (!status)) - { - return kStatus_PHY_InvaildInput; - } - - result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCR,&data); - if ((result == kStatus_PHY_Success) && (!(data & kEnetPhyReset))) - { - data = 0; - result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhySR, &data); - if (result == kStatus_PHY_Success) - { - if (!(kEnetPhyLinkStatus & data)) - { - *status = false; - } - else - { - *status = true; - } - } - } - - return result; -} - -/*FUNCTION**************************************************************** - * - * Function Name: phy_get_link_duplex - * Return Value: The execution status. - * Description: Get phy link duplex. - * This function provides a interface to get link duplex to see if the link - * duplex is full or half. - *END*********************************************************************/ -uint32_t phy_get_link_duplex(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *status) -{ - uint32_t result = kStatus_PHY_Success; - uint32_t data; - - /* Check input parameters*/ - if ((!enetIfPtr) || (!status)) - { - return kStatus_PHY_InvaildInput; - } - - result = enetIfPtr->macApiPtr->enet_mii_read(enetIfPtr->deviceNumber, - enetIfPtr->phyCfgPtr->phyAddr,kEnetPhyCt2,&data); - if (result == kStatus_PHY_Success) - { - data &= kEnetPhySpeedDulpexMask; - if ((kEnetPhy10FullDuplex == data) || (kEnetPhy100FullDuplex == data)) - { - *status = kEnetFullDuplex; - } - else - { - *status = kEnetHalfDuplex; - } - } - - return result; -} - -#endif - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.h deleted file mode 100644 index e3a4f346e01..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_PHY_DRIVER_H__ -#define __FSL_PHY_DRIVER_H__ - -#include -#include -#include "fsl_enet_driver.h" - -#ifndef MBED_NO_ENET - -/*! - * @addtogroup phy_driver - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Defines the PHY return status. */ -typedef enum _phy_status -{ - kStatus_PHY_Success = 0, /*!< Success*/ - kStatus_PHY_InvaildInput = 1, /*!< Invalid PHY input parameter*/ - kStatus_PHY_TimeOut = 2, /*!< PHY timeout*/ - kStatus_PHY_Fail = 3 /*!< PHY fail*/ -} phy_status_t; - -/*! @brief Defines the ENET timeout.*/ -typedef enum _phy_timeout -{ - kPhyTimeout = 0x10000, /*!< ENET resets timeout.*/ -} phy_timeout_t; - -/*! @brief Defines the PHY register.*/ -typedef enum _enet_phy_register -{ - kEnetPhyCR = 0, /*!< PHY control register */ - kEnetPhySR = 1, /*!< PHY status register*/ - kEnetPhyId1 = 2, /*!< PHY identification register 1*/ - kEnetPhyId2 = 3, /*!< PHY identification register 2*/ - kEnetPhyCt2 = 0x1e /*!< PHY control2 register*/ -} enet_phy_register_t; - -/*! @brief Defines the control flag.*/ -typedef enum _enet_phy_control -{ - kEnetPhyAutoNeg = 0x1000,/*!< ENET PHY auto negotiation control*/ - kEnetPhySpeed = 0x2000, /*! ENET PHY speed control*/ - kEnetPhyLoop = 0x4000, /*!< ENET PHY loop control*/ - kEnetPhyReset = 0x8000, /*!< ENET PHY reset control*/ - kEnetPhy10HalfDuplex = 0x01, /*!< ENET PHY 10 M half duplex*/ - kEnetPhy100HalfDuplex = 0x02,/*!< ENET PHY 100 M half duplex*/ - kEnetPhy10FullDuplex = 0x05,/*!< ENET PHY 10 M full duplex*/ - kEnetPhy100FullDuplex = 0x06/*!< ENET PHY 100 M full duplex*/ -} enet_phy_control_t; - -/*! @brief Defines the PHY link speed. */ -typedef enum _enet_phy_speed -{ - kEnetSpeed10M = 0, /*!< ENET PHY 10 M speed*/ - kEnetSpeed100M = 1 /*!< ENET PHY 100 M speed*/ -} enet_phy_speed_t; - -/*! @brief Defines the PHY link duplex.*/ -typedef enum _enet_phy_duplex -{ - kEnetHalfDuplex = 0, /*!< ENET PHY half duplex*/ - kEnetFullDuplex = 1 /*!< ENET PHY full duplex*/ -} enet_phy_duplex_t; - -/*! @brief Defines the PHY status.*/ -typedef enum _enet_phy_status -{ - kEnetPhyLinkStatus = 0x4, /*!< ENET PHY link status bit*/ - kEnetPhyAutoNegAble = 0x08, /*!< ENET PHY auto negotiation ability*/ - kEnetPhyAutoNegComplete = 0x20, /*!< ENET PHY auto negotiation complete*/ - kEnetPhySpeedDulpexMask = 0x07 /*!< ENET PHY speed mask on status register 2*/ -} enet_phy_status_t; - -/*! @brief Defines the basic PHY application.*/ -typedef struct ENETPhyApi -{ - uint32_t (* phy_auto_discover)(enet_dev_if_t * enetIfPtr);/*!< PHY auto discover*/ - uint32_t (* phy_init)(enet_dev_if_t * enetIfPtr);/*!< PHY initialize*/ - uint32_t (* phy_get_link_speed)(enet_dev_if_t * enetIfPtr, enet_phy_speed_t *speed);/*!< Get PHY speed*/ - uint32_t (* phy_get_link_status)(enet_dev_if_t * enetIfPtr, bool *status);/*! Get PHY link status*/ - uint32_t (* phy_get_link_duplex)(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *duplex);/*!< Get PHY link duplex*/ -} enet_phy_api_t; - -/******************************************************************************* - * Global variables - ******************************************************************************/ -extern const enet_phy_api_t g_enetPhyApi; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name PHY Driver - * @{ - */ - -/*! - * @brief Initializes PHY. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t phy_init(enet_dev_if_t * enetIfPtr); - -/*! - * @brief PHY address auto discover. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t phy_auto_discover(enet_dev_if_t * enetIfPtr); - -/*! - * @brief Gets the PHY link speed. - * - * @param enetIfPtr The ENET context structure. - * @param status The link speed of PHY. - * @return The execution status. - */ -uint32_t phy_get_link_speed(enet_dev_if_t * enetIfPtr, enet_phy_speed_t *status); - -/*! - * @brief Gets the PHY link status. - * - * @param enetIfPtr The ENET context structure. - * @param status The link on or down status of the PHY. - * @return The execution status. - */ -uint32_t phy_get_link_status(enet_dev_if_t * enetIfPtr, bool *status); - -/*! - * @brief Gets the PHY link duplex. - * - * @param enetIfPtr The ENET context structure. - * @param status The link duplex status of PHY. - * @return The execution status. - */ -uint32_t phy_get_link_duplex(enet_dev_if_t * enetIfPtr, enet_phy_duplex_t *status); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif - -/*! @}*/ - -#endif /* __FSL_PHY_DRIVER_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.c deleted file mode 100644 index 9d15d22ff38..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_device_registers.h" -#include "fsl_clock_manager.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Table of base addresses for instances. */ -const uint32_t g_simBaseAddr[] = SIM_BASE_ADDRS; -const uint32_t g_mcgBaseAddr[] = MCG_BASE_ADDRS; - - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSysClkFreq - * Description : Internal function to get the system clock frequency - * This function will check the clock name configuration table for specific - * chip family and find out the supported clock name for that chip family - * then it will call the mcg hal function to get the basic system clock, - * calculate the clock frequency for specified clock name. - * - *END**************************************************************************/ -clock_manager_error_code_t CLOCK_SYS_GetSysClkFreq(clock_names_t clockName, - uint32_t *frequency) -{ - /* system clock out divider*/ - uint32_t divider; - - const clock_name_config_t *table = &kClockNameConfigTable[clockName]; - - /* check if we need to use a reference clock*/ - if (table->useOtherRefClock) - { - /* get other specified ref clock*/ - if ( kClockManagerSuccess != CLOCK_SYS_GetFreq(table->otherRefClockName, - frequency) ) - { - return kClockManagerNoSuchClockName; - } - } - else - { - /* get default ref clock */ - *frequency = CLOCK_HAL_GetOutClk(g_mcgBaseAddr[0]); - } - - /* get system clock divider*/ - if ( CLOCK_HAL_GetDivider(g_simBaseAddr[0], table->dividerName, ÷r) == kSimHalSuccess) - { - /* get the frequency for the specified clock*/ - *frequency = (*frequency) / (divider + 1); - return kClockManagerSuccess; - } - else - { - return kClockManagerNoSuchDivider; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFreq - * Description : Internal function to get the frequency by clock name - * This function will get/calculate the clock frequency based on clock name - * and current configuration of clock generator. - * - *END**************************************************************************/ -clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName, - uint32_t *frequency) -{ - clock_manager_error_code_t returnCode = kClockManagerSuccess; - - /* branch according to clock name */ - switch(clockName) - { - /* osc clock*/ - case kOsc32kClock: - *frequency = CPU_XTAL32k_CLK_HZ; - break; - case kOsc0ErClock: -#if FSL_FEATURE_MCG_HAS_OSC1 - /* System oscillator 0 drives MCG clock */ - *frequency = CPU_XTAL0_CLK_HZ; -#else - /* System oscillator 0 drives MCG clock */ - *frequency = CPU_XTAL_CLK_HZ; -#endif - break; - -#if FSL_FEATURE_MCG_HAS_OSC1 - case kOsc1ErClock: - *frequency = CPU_XTAL1_CLK_HZ; - break; -#endif - -#if FSL_FEATURE_MCG_HAS_IRC_48M - /* irc clock*/ - case kIrc48mClock: - *frequency = CPU_INT_IRC_CLK_HZ; - break; -#endif - - /* rtc clock*/ - case kRtc32kClock: - *frequency = CPU_XTAL32k_CLK_HZ; - break; - - case kRtc1hzClock: - *frequency = CPU_XTAL1hz_CLK_HZ; // defined in fsl_clock_manager.h for now - break; - - /* lpo clcok*/ - case kLpoClock: - *frequency = CPU_LPO_CLK_HZ; // defined in fsl_clock_manager.h for now - break; - - /* mcg clocks, calling mcg clock functions */ - case kMcgFfClock: - *frequency = CLOCK_HAL_GetFllRefClk(g_mcgBaseAddr[0]); - break; - case kMcgFllClock: - *frequency = CLOCK_HAL_GetFllClk(g_mcgBaseAddr[0]); - break; -#if FSL_FEATURE_MCG_HAS_PLL - case kMcgPll0Clock: - *frequency = CLOCK_HAL_GetPll0Clk(g_mcgBaseAddr[0]); - break; -#endif - case kMcgOutClock: - *frequency = CLOCK_HAL_GetOutClk(g_mcgBaseAddr[0]); - break; - case kMcgIrClock: - *frequency = CLOCK_HAL_GetInternalRefClk(g_mcgBaseAddr[0]); - break; - - case kSDHC0_CLKIN: - *frequency = SDHC0_CLKIN; // defined in fsl_clock_manager.h for now - break; - case kENET_1588_CLKIN: - *frequency = ENET_1588_CLKIN; // defined in fsl_clock_manager.h for now - break; - case kEXTAL_Clock: - *frequency = EXTAL_Clock; // defined in fsl_clock_manager.h for now - break; - case kEXTAL1_Clock: - *frequency = EXTAL1_Clock; // defined in fsl_clock_manager.h for now - break; - case kUSB_CLKIN: - *frequency = USB_CLKIN; // defined in fsl_clock_manager.h for now - break; - - /* system clocks */ - case kCoreClock: - case kSystemClock: - case kPlatformClock: - case kBusClock: - case kFlexBusClock: - case kFlashClock: - returnCode = CLOCK_SYS_GetSysClkFreq(clockName, frequency); - break; - /* reserved value*/ - case kReserved: - default: - *frequency = 55555; /* for testing use purpose*/ - returnCode = kClockManagerNoSuchClockName; - break; - } - - return returnCode; -} - - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_SetSource - * Description : Set clock source setting - * This function will set the settings for specified clock source. Each clock - * source has its clock selection settings. Refer to reference manual for - * details of settings for each clock source. Refer to clock_source_names_t - * for clock sources. - * - *END**************************************************************************/ -clock_manager_error_code_t CLOCK_SYS_SetSource(clock_source_names_t clockSource, - uint8_t setting) -{ - clock_manager_error_code_t returnCode = kClockManagerSuccess; - - if (CLOCK_HAL_SetSource(g_simBaseAddr[0], clockSource, setting) != kSimHalSuccess) - { - returnCode = kClockManagerNoSuchClockSource; - } - - return returnCode; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSource - * Description : Get clock source setting - * This function will get the settings for specified clock source. Each clock - * source has its clock selection settings. Refer to reference manual for - * details of settings for each clock source. Refer to clock_source_names_t - * for clock sources. - * - *END**************************************************************************/ -clock_manager_error_code_t CLOCK_SYS_GetSource(clock_source_names_t clockSource, - uint8_t *setting) -{ - clock_manager_error_code_t returnCode = kClockManagerSuccess; - - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], clockSource, setting) != kSimHalSuccess) - { - returnCode = kClockManagerNoSuchClockSource; - } - - return returnCode; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_SetDivider - * Description : Set clock divider setting - * This function will set the setting for specified clock divider. Refer to - * reference manual for supported clock divider and value range. Refer to - * clock_divider_names_t for dividers. - * - *END**************************************************************************/ -clock_manager_error_code_t CLOCK_SYS_SetDivider(clock_divider_names_t clockDivider, - uint32_t setting) -{ - clock_manager_error_code_t returnCode = kClockManagerSuccess; - - if (CLOCK_HAL_SetDivider(g_simBaseAddr[0], clockDivider, setting) != kSimHalSuccess) - { - returnCode = kClockManagerNoSuchDivider; - } - - return returnCode; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetDivider - * Description : Get clock divider setting - * This function will get the setting for specified clock divider. Refer to - * reference manual for supported clock divider and value range. Refer to - * clock_divider_names_t for dividers. - * - *END**************************************************************************/ -clock_manager_error_code_t CLOCK_SYS_GetDivider(clock_divider_names_t clockDivider, - uint32_t *setting) -{ - clock_manager_error_code_t returnCode = kClockManagerSuccess; - - if (CLOCK_HAL_GetDivider(g_simBaseAddr[0], clockDivider, setting) != kSimHalSuccess) - { - returnCode = kClockManagerNoSuchDivider; - } - - return returnCode; -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.h deleted file mode 100644 index 493ac9d5c76..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_CLOCK_MANAGER_H__) -#define __FSL_CLOCK_MANAGER_H__ - -#include -#include -#include -#include "fsl_mcg_hal.h" -#include "fsl_sim_hal.h" - -/*! @addtogroup clock_manager*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* system clocks definition (should be moved to other proper place) */ -#define CPU_XTAL1hz_CLK_HZ 1 -#define CPU_LPO_CLK_HZ 1000 - -/* external clock definition (should be moved to other proper place) */ - -#define SDHC0_CLKIN 0 /* kSimSDHC0_CLKIN */ -#define ENET_1588_CLKIN 0 /* kSimENET_1588_CLKIN */ -#define EXTAL_Clock 0 /* kSimEXTAL_Clock */ -#define EXTAL1_Clock 0 /* kSimEXTAL1_Clock */ -#define USB_CLKIN 0 /* kSimUSB_CLKIN */ - -/* Table of base addresses for instances. */ -extern const uint32_t g_simBaseAddr[]; -extern const uint32_t g_mcgBaseAddr[]; - -/*! - * @brief Error code definition for the clock manager APIs - */ -typedef enum _clock_manager_error_code { - kClockManagerSuccess, /*!< success */ - kClockManagerNoSuchClockName, /*!< cannot find the clock name */ - kClockManagerNoSuchClockModule, /*!< cannot find the clock module name */ - kClockManagerNoSuchClockSource, /*!< cannot find the clock source name */ - kClockManagerNoSuchDivider, /*!< cannot find the divider name */ - kClockManagerUnknown /*!< unknown error*/ -} clock_manager_error_code_t; - - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Clock Frequencies*/ -/*@{*/ - -/*! - * @brief Gets the clock frequency for a specific clock name. - * - * This function checks the current clock configurations and then calculates - * the clock frequency for a specific clock name defined in clock_names_t. - * The MCG must be properly configured before using this function. See - * the reference manual for supported clock names for different chip families. - * The returned value is in Hertz. If it cannot find the clock name - * or the name is not supported for a specific chip family, it returns an - * error. - * - * @param clockName Clock names defined in clock_names_t - * @param frequency Returned clock frequency value in Hertz - * @return status Error code defined in clock_manager_error_code_t - */ -clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName, - uint32_t *frequency); - -/*! - * @brief Sets the clock source setting. - * - * This function sets the settings for a specified clock source. Each clock - * source has its own clock selection settings. See the chip reference manual for - * clock source detailed settings and the sim_clock_source_names_t - * for clock sources. - * - * @param clockSource Clock source name defined in sim_clock_source_names_t - * @param setting Setting value - * @return status If the clock source doesn't exist, it returns an error. - */ -clock_manager_error_code_t CLOCK_SYS_SetSource(clock_source_names_t clockSource, - uint8_t setting); - -/*! - * @brief Gets the clock source setting. - * - * This function gets the settings for a specified clock source. Each clock - * source has its own clock selection settings. See the reference manual for - * clock source detailed settings and the sim_clock_source_names_t - * for clock sources. - * - * @param clockSource Clock source name - * @param setting Current setting for the clock source - * @return status If the clock source doesn't exist, it returns an error. - */ -clock_manager_error_code_t CLOCK_SYS_GetSource(clock_source_names_t clockSource, - uint8_t *setting); - -/*! - * @brief Sets the clock divider setting. - * - * This function sets the setting for a specified clock divider. See the - * reference manual for a supported clock divider and value range and the - * sim_clock_divider_names_t for dividers. - * - * @param clockDivider Clock divider name - * @param divider Divider setting - * @return status If the clock divider doesn't exist, it returns an error. - */ -clock_manager_error_code_t CLOCK_SYS_SetDivider(clock_divider_names_t clockDivider, - uint32_t setting); - -/*! - * @brief Gets the clock divider setting. - * - * This function gets the setting for a specified clock divider. See the - * reference manual for a supported clock divider and value range and the - * clock_divider_names_t for dividers. - * - * @param clockDivider Clock divider name - * @param divider Divider value pointer - * @return status If the clock divider doesn't exist, it returns an error. - */ -clock_manager_error_code_t CLOCK_SYS_GetDivider(clock_divider_names_t clockDivider, - uint32_t *setting); - -/*! - * @brief Sets the clock out dividers setting. - * - * This function sets the setting for all clock out dividers at the same time. - * See the reference manual for a supported clock divider and value range and the - * clock_divider_names_t for clock out dividers. - * - * @param outdiv1 Outdivider1 setting - * @param outdiv2 Outdivider2 setting - * @param outdiv3 Outdivider3 setting - * @param outdiv4 Outdivider4 setting - */ -static inline void CLOCK_SYS_SetOutDividers(uint32_t outdiv1, uint32_t outdiv2, - uint32_t outdiv3, uint32_t outdiv4) -{ - CLOCK_HAL_SetOutDividers(g_simBaseAddr[0], outdiv1, outdiv2, outdiv3, outdiv4); -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -/* - * Include the cpu specific clock API header files. - */ -#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \ - defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)) - - #define K02F12810_SERIES - -#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \ - defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \ - defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \ - defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \ - defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \ - defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)) - - #define K20D5_SERIES - - -#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \ - defined(CPU_MK22FN128VMP10)) - - #define K22F12810_SERIES - - /* Clock System Level API header file */ - #include "MK22F12810/fsl_clock_K22F12810.h" - -#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \ - defined(CPU_MK22FN256VMP12)) - - #define K22F25612_SERIES - - /* Clock System Level API header file */ - #include "MK22F25612/fsl_clock_K22F25612.h" - - - -#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12)) - - #define K22F51212_SERIES - - /* Clock System Level API header file */ - #include "MK22F51212/fsl_clock_K22F51212.h" - - -#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12)) - - #define K24F12_SERIES - - /* Clock System Level API header file */ - #include "MK24F12/fsl_clock_K24F12.h" - -#elif (defined(CPU_MK24FN256VDC12)) - - #define K24F25612_SERIES - - -#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12)) - - #define K63F12_SERIES - - /* Clock System Level API header file */ - #include "MK63F12/fsl_clock_K63F12.h" - -#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)) - - #define K64F12_SERIES - - /* Clock System Level API header file */ - #include "MK64F12/fsl_clock_K64F12.h" - -#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18)) - - #define K65F18_SERIES - - -#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18)) - - #define K66F18_SERIES - - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F12_SERIES - - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F15_SERIES - - -#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \ - defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \ - defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4)) - - #define KL02Z4_SERIES - - -#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \ - defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \ - defined(CPU_MKL03Z32VFK4)) - - #define KL03Z4_SERIES - - -#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \ - defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ - defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ - defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)) - - #define KL05Z4_SERIES - - -#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ - defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ - defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4)) - - #define KL13Z4_SERIES - - -#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ - defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ - defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4)) - - #define KL23Z4_SERIES - - -#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ - defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)) - - #define KL25Z4_SERIES - - /* Clock System Level API header file */ - #include "MKL25Z4/fsl_clock_KL25Z4.h" - -#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \ - defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \ - defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \ - defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ - defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4)) - - #define KL26Z4_SERIES - - -#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \ - defined(CPU_MKL33Z256VMP4)) - - #define KL33Z4_SERIES - - -#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \ - defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)) - - #define KL43Z4_SERIES - - -#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)) - - #define KL46Z4_SERIES - - -#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)) - - #define KV30F12810_SERIES - - -#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)) - - #define KV31F12810_SERIES - - /* Clock System Level API header file */ - #include "MKV31F12810/fsl_clock_KV31F12810.h" - -#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)) - - #define KV31F25612_SERIES - - /* Clock System Level API header file */ - #include "MKV31F25612/fsl_clock_KV31F25612.h" - - -#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)) - - #define KV31F51212_SERIES - - /* Clock System Level API header file */ - #include "MKV31F51212/fsl_clock_KV31F51212.h" - -#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15)) - - #define KV40F15_SERIES - - -#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15)) - - #define KV43F15_SERIES - - -#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)) - - #define KV44F15_SERIES - - -#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ - defined(CPU_MKV45F256VLL15)) - - #define KV45F15_SERIES - - -#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15)) - - #define KV46F15_SERIES - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_CLOCK_MANAGER_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_driver.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_driver.h deleted file mode 100644 index 75db5a4e477..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_driver.h +++ /dev/null @@ -1,952 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_ENET_DRIVER_H__ -#define __FSL_ENET_DRIVER_H__ - -#include -#include -#include "fsl_enet_hal.h" -#include "fsl_os_abstraction.h" - -#ifndef MBED_NO_ENET - -/*! - * @addtogroup enet_driver - * @{ - */ - -/******************************************************************************* - * Definitions - - ******************************************************************************/ -/*! @brief Defines the approach: ENET interrupt handler do receive */ -#define ENET_RECEIVE_ALL_INTERRUPT 0 - -/*! @brief Defines the statistic enable macro.*/ -#define ENET_ENABLE_DETAIL_STATS 0 - -/*! @brief Defines the alignment operation.*/ -#define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1))) - -#if FSL_FEATURE_ENET_SUPPORT_PTP -/*! @brief Defines the PTP IOCTL macro.*/ -typedef enum _enet_ptp_ioctl -{ - kEnetPtpGetRxTimestamp = 0, /*!< ENET PTP gets receive timestamp*/ - kEnetPtpGetTxTimestamp, /*!< ENET PTP gets transmit timestamp*/ - kEnetPtpGetCurrentTime, /*!< ENET PTP gets current time*/ - kEnetPtpSetCurrentTime, /*!< ENET PTP sets current time*/ - kEnetPtpFlushTimestamp, /*!< ENET PTP flushes timestamp*/ - kEnetPtpCorrectTime, /*!< ENET PTP time correction*/ - kEnetPtpSendEthernetPtpV2, /*!< ENET PTPv2 sends Ethernet frame*/ - kEnetPtpReceiveEthernetPtpV2 /*!< ENET PTPv2 receives with Ethernet frame*/ -} enet_ptp_ioctl_t; - -/*! @brief Defines the PTP message buffer number.*/ -typedef enum _enet_ptp_buffer_number -{ - kEnetPtpL2bufferNumber = 10, /*!< PTP layer2 frame buffer number*/ - kEnetPtpRingNumber = 25 /*!< PTP Ring buffer number*/ -} enet_ptp_buffer_number_t; - -/*! @brief Defines the ENET PTP message related constant.*/ -typedef enum _enet_ptp_event_type -{ - kEnetPtpSourcePortIdLen = 10, /*!< PTP message sequence id length*/ - kEnetPtpEventMsgType = 3, /*!< PTP event message type*/ - kEnetPtpEventPort = 319, /*!< PTP event port number*/ - kEnetPtpGnrlPort = 320 /*!< PTP general port number*/ -} enet_ptp_event_type_t; - -/*! @brief Defines all ENET PTP content offsets in the IPv4 PTP UDP/IP multicast message.*/ -typedef enum _enet_ipv4_ptp_content_offset -{ - kEnetPtpIpVersionOffset = 0xe, /*!< IPv4 PTP message IP version offset*/ - kEnetPtpUdpProtocolOffset = 0x17,/*!< IPv4 PTP message UDP protocol offset*/ - kEnetPtpUdpPortOffset = 0x24, /*!< IPv4 PTP message UDP port offset*/ - kEnetPtpUdpMsgTypeOffset = 0x2a, /*!< IPv4 PTP message UDP message type offset*/ - kEnetPtpUdpVersionoffset = 0x2b, /*!< IPv4 PTP message UDP version offset*/ - kEnetPtpUdpClockIdOffset = 0x3e, /*!< IPv4 PTP message UDP clock id offset*/ - kEnetPtpUdpSequenIdOffset = 0x48,/*!< IPv4 PTP message UDP sequence id offset*/ - kEnetPtpUdpCtlOffset = 0x4a /*!< IPv4 PTP message UDP control offset*/ -} enet_ipv4_ptp_content_offset_t; - -/*! @brief Defines all ENET PTP content offset in THE IPv6 PTP UDP/IP multicast message.*/ -typedef enum _enet_ipv6_ptp_content_offset -{ - kEnetPtpIpv6UdpProtocolOffset = 0x14, /*!< IPv6 PTP message UDP protocol offset*/ - kEnetPtpIpv6UdpPortOffset = 0x38, /*!< IPv6 PTP message UDP port offset*/ - kEnetPtpIpv6UdpMsgTypeOffset = 0x3e, /*!< IPv6 PTP message UDP message type offset*/ - kEnetPtpIpv6UdpVersionOffset = 0x3f, /*!< IPv6 PTP message UDP version offset*/ - kEnetPtpIpv6UdpClockIdOffset = 0x52, /*!< IPv6 PTP message UDP clock id offset*/ - kEnetPtpIpv6UdpSequenceIdOffset = 0x5c,/*!< IPv6 PTP message UDP sequence id offset*/ - kEnetPtpIpv6UdpCtlOffset = 0x5e /*!< IPv6 PTP message UDP control offset*/ -} enet_ipv6_ptp_content_offset_t; - -/*! @brief Defines all ENET PTP content offset in the PTP Layer2 Ethernet message.*/ -typedef enum _enet_ethernet_ptp_content_offset -{ - kEnetPtpEtherPktTypeOffset = 0x0c, /*!< PTPv2 message Ethernet packet type offset*/ - kEnetPtpEtherMsgTypeOffset = 0x0e, /*!< PTPv2 message Ethernet message type offset*/ - kEnetPtpEtherVersionOffset = 0x0f, /*!< PTPv2 message Ethernet version type offset*/ - kEnetPtpEtherClockIdOffset = 0x22, /*!< PTPv2 message Ethernet clock id offset*/ - kEnetPtpEtherSequenceIdOffset = 0x2c,/*!< PTPv2 message Ethernet sequence id offset*/ - kEnetPtpEtherCtlOffset = 0x2e /*!< PTPv2 message Ethernet control offset*/ -} enet_ethernet_ptp_content_offset_t; - -/*! @brief Defines the 1588 timer parameters.*/ -typedef enum _enet_ptp_timer_wrap_period -{ - kEnetPtpAtperVaule = 1000000000, /*!< PTP timer wrap around one second */ - kEnetBaseIncreaseUnit = 2 /*!< PTP timer adjusts clock and increases value to 2*/ -} enet_ptp_timer_wrap_period_t; -#endif - -/*! @brief Defines the interrupt source index for the interrupt vector change table.*/ -typedef enum _enet_interrupt_number -{ - kEnetTstimerInt = 0, /*!< Timestamp interrupt*/ - kEnetTsAvailInt, /*!< TS-avail interrupt*/ - kEnetWakeUpInt, /*!< Wakeup interrupt*/ - kEnetPlrInt, /*!< Plr interrupt*/ - kEnetUnInt, /*!< Un interrupt*/ - kEnetRlInt, /*!< RL interrupt*/ - kEnetLcInt, /*!< LC interrupt*/ - kEnetEberrInt, /*!< Eberr interrupt*/ - kEnetMiiInt, /*!< MII interrupt*/ - kEnetRxbInt , /*!< Receive byte interrupt*/ - kEnetRxfInt, /*!< Receive frame interrupt*/ - kEnetTxbInt, /*!< Transmit byte interrupt*/ - kEnetTxfInt, /*!< Transmit frame interrupt*/ - kEnetGraInt, /*!< Gra interrupt*/ - kEnetBabtInt, /*!< Babt interrupt*/ - kEnetBabrInt, /*!< Babr interrupt*/ - kEnetIntNum /*!< Interrupt number*/ -} enet_interrupt_number_t; - -/*! @brief Defines the ENET main constant.*/ -typedef enum _enet_frame_max -{ - kEnetMaxTimeout = 0x10000, /*!< Maximum timeout*/ - kEnetMaxFrameSize = 1518, /*!< Maximum frame size*/ - kEnetMaxFrameVlanSize = 1522, /*!< Maximum VLAN frame size*/ - kEnetMaxFrameDateSize = 1500, /*!< Maximum frame data size*/ - kEnetMaxFrameBdNumbers = 7, /*!< Maximum buffer descriptor numbers of a frame*/ - kEnetFrameFcsLen = 4, /*!< FCS length*/ - kEnetEthernetHeadLen = 14 /*!< Ethernet Frame header length*/ -} enet_frame_max_t; - -/*! @brief Defines the CRC data for a hash value calculation.*/ -typedef enum _enet_crc_parameter -{ - kEnetCrcData = 0xFFFFFFFFU, /*!< CRC-32 maximum data */ - kEnetCrcOffset = 8, /*!< CRC-32 offset2*/ - kEnetCrcMask1 = 0x3F /*!< CRC-32 mask*/ -} enet_crc_parameter_t; - -/*! @brief Defines the ENET protocol type and main parameters.*/ -typedef enum _enet_protocol_type -{ - kEnetProtocolIeee8023 = 0x88F7, /*!< Packet type Ethernet ieee802.3*/ - kEnetProtocolIpv4 = 0x0800, /*!< Packet type IPv4*/ - kEnetProtocolIpv6 = 0x86dd, /*!< Packet type IPv6*/ - kEnetProtocol8021QVlan = 0x8100, /*!< Packet type VLAN*/ - kEnetPacketUdpVersion = 0x11, /*!< UDP protocol type*/ - kEnetPacketIpv4Version = 0x4, /*!< Packet IP version IPv4*/ - kEnetPacketIpv6Version = 0x6 /*!< Packet IP version IPv6*/ -} enet_protocol_type_t; - -/*! @brief Defines the ENET MAC control Configure*/ -typedef enum _enet_mac_control_flag -{ - kEnetSleepModeEnable = 0x1, /*!< ENET control sleep mode Enable*/ - kEnetPayloadlenCheckEnable = 0x2, /*!< ENET receive payload length check Enable*/ - kEnetRxFlowControlEnable = 0x4, /*!< ENET flow control, receiver detects PAUSE frames and stops transmitting data when a PAUSE frame is detected*/ - kEnetRxCrcFwdEnable = 0x8, /*!< Received frame crc is stripped from the frame*/ - kEnetRxPauseFwdEnable = 0x10,/*!< Pause frames are forwarded to the user application*/ - kEnetRxPadRemoveEnable = 0x20, /*!< Padding is removed from received frames*/ - kEnetRxBcRejectEnable = 0x40, /*!< Broadcast frame reject*/ - kEnetRxPromiscuousEnable = 0x80, /*!< Promiscuous mode enabled*/ - kEnetRxMiiLoopback = 0x100, /*!< MAC MII loopback mode*/ -} enet_mac_control_flag_t; - -/*! @brief Defines the multicast group structure for the ENET device. */ -typedef struct ENETMulticastGroup -{ - enetMacAddr groupAdddr; /*!< Multicast group address*/ - uint32_t hash; /*!< Hash value of the multicast group address*/ - struct ENETMulticastGroup *next; /*!< Pointer of the next group structure*/ - struct ENETMulticastGroup *prv; /*!< Pointer of the previous structure*/ -} enet_multicast_group_t; - -/*! @brief Defines the receive buffer descriptor configure structure.*/ -typedef struct ENETRxBdConfig -{ - uint8_t *rxBdPtrAlign; /*!< Aligned receive buffer descriptor pointer */ - uint8_t *rxBufferAlign; /*!< Aligned receive data buffer pointer */ - uint8_t *rxLargeBufferAlign; /*!< Aligned receive large data buffer pointer*/ - uint8_t rxBdNum; /*!< Aligned receive buffer descriptor pointer*/ - uint8_t rxBufferNum; /*!< Receive buffer number*/ - uint8_t rxLargeBufferNum; /*!< Large receive buffer number*/ - uint32_t rxLargeBufferSizeAlign; /*!< Aligned large receive buffer size*/ -}enet_rxbd_config_t; - -/*! @brief Defines the transmit buffer descriptor configure structure.*/ -typedef struct ENETTxBdConfig -{ - uint8_t *txBdPtrAlign; /*!< Aligned transmit buffer descriptor pointer*/ - uint8_t *txBufferAlign; /*!< Aligned transmit buffer descriptor pointer*/ - uint8_t txBufferNum; /*!< Transmit buffer number*/ - uint32_t txBufferSizeAlign; /*!< Aligned transmit buffer size*/ -}enet_txbd_config_t; - -/*! @brief Defines the basic configuration structure for the ENET device.*/ -typedef struct ENETMacConfig -{ - uint16_t rxBufferSize; /*!< Receive buffer size*/ - uint16_t rxLargeBufferNumber; /*!< Receive large buffer number; Needed only when the BD size is smaller than the maximum frame length.*/ - uint16_t rxBdNumber; /*!< Receive buffer descriptor number*/ - uint16_t txBdNumber; /*!< Transmit buffer descriptor number*/ - enetMacAddr macAddr; /*!< MAC hardware address*/ - enet_config_rmii_t rmiiCfgMode;/*!< RMII configure mode*/ - enet_config_speed_t speed; /*!< Speed configuration*/ - enet_config_duplex_t duplex; /*!< Duplex configuration*/ - /*!< Mac control configure, it is recommended to use enet_mac_control_flag_t - it is special control set for loop mode, sleep mode, crc forward/terminate etc*/ - uint32_t macCtlConfigure; - bool isTxAccelEnabled;/*!< Switcher to enable transmit accelerator*/ - bool isRxAccelEnabled;/*!< Switcher to enable receive accelerator*/ - bool isStoreAndFwEnabled; /*!< Switcher to enable store and forward*/ - enet_config_rx_accelerator_t rxAcceler; /*!< Receive accelerator configure*/ - enet_config_tx_accelerator_t txAcceler; /*!< Transmit accelerator configure*/ - bool isVlanEnabled; /*!< Switcher to enable VLAN frame*/ - bool isPhyAutoDiscover;/*!< Switcher to use PHY auto discover*/ - uint32_t miiClock; /*!< MII speed*/ -#if FSL_FEATURE_ENET_SUPPORT_PTP - uint16_t ptpRingBufferNumber; /*!< PTP ring buffer number*/ - bool isSlaveModeEnabled; /*!< PTP timer configuration*/ -#endif -} enet_mac_config_t; - -/*! @brief Defines the basic configuration for PHY.*/ -typedef struct ENETPhyConfig -{ - uint8_t phyAddr; /*!< PHY address*/ - bool isLoopEnabled; /*!< Switcher to enable the HY loop mode*/ -} enet_phy_config_t; - -#if FSL_FEATURE_ENET_SUPPORT_PTP -/*! @brief Defines the ENET Mac PTP timestamp structure.*/ -typedef struct ENETMacPtpTime -{ - uint64_t second; /*!< Second*/ - uint32_t nanosecond; /*!< Nanosecond*/ -} enet_mac_ptp_time_t; - -/*! @brief Defines the ENET PTP timer drift structure.*/ -typedef struct ENETPtpDrift -{ - int32_t drift; /*!< Drift for the PTP timer to adjust*/ -} enet_ptp_drift_t; - -/*! @brief Defines the ENET MAC PTP time parameter.*/ -typedef struct ENETPtpMasterTimeData -{ - uint8_t masterPtpInstance;/*!< PTP master timer instance*/ - uint64_t second; /*!< PTP master timer second */ -} enet_ptp_master_time_data_t; - -/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ -typedef struct ENETMacPtpTsData -{ - uint8_t version; /*!< PTP version*/ - uint8_t sourcePortId[kEnetPtpSourcePortIdLen];/*!< PTP source port ID*/ - uint16_t sequenceId; /*!< PTP sequence ID*/ - uint8_t messageType; /*!< PTP message type*/ - enet_mac_ptp_time_t timeStamp;/*!< PTP timestamp*/ -} enet_mac_ptp_ts_data_t; - -/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ -typedef struct ENETMacPtpTsRing -{ - uint32_t front; /*!< The first index of the ring*/ - uint32_t end; /*!< The end index of the ring*/ - uint32_t size; /*!< The size of the ring*/ - enet_mac_ptp_ts_data_t *ptpTsDataPtr;/*!< PTP message data structure*/ -} enet_mac_ptp_ts_ring_t; - -/*! @brief Defines the ENET packet for the PTP version2 message using the layer2 Ethernet frame.*/ -typedef struct ENETPtpL2packet -{ - uint8_t packet[kEnetMaxFrameDateSize]; /*!< Buffer for ptpv2 message*/ - uint16_t length; /*!< PTP message length*/ -} enet_ptp_l2packet_t; - -/*! @brief Defines the ENET PTPv2 packet queue using the layer2 Ethernet frame.*/ -typedef struct ENETPtpL2queue -{ - enet_ptp_l2packet_t l2Packet[kEnetPtpL2bufferNumber]; /*!< PTP layer2 packet*/ - uint16_t writeIdex; /*!< Queue write index*/ - uint16_t readIdx; /*!< Queue read index*/ -} enet_ptp_l2queue_t; - -/*! @brief Defines the ENET PTP layer2 Ethernet frame structure.*/ -typedef struct ENETPtpL2Ethernet -{ - uint8_t *ptpMsg; /*!< PTP message*/ - uint16_t length; /*!< Length of the PTP message*/ - enetMacAddr hwAddr; /*!< Destination hardware address*/ -} enet_ptp_l2_ethernet_t; - -/*! @brief Defines the ENET PTP buffer structure for all 1588 data.*/ -typedef struct ENETPrivatePtpBuffer -{ - enet_mac_ptp_ts_ring_t rxTimeStamp;/*!< Data structure for receive message*/ - enet_mac_ptp_ts_ring_t txTimeStamp;/*!< Data structure for transmit timestamp*/ - enet_ptp_l2queue_t *l2QueuePtr; /*!< Data structure for layer2 Ethernet queue*/ - uint64_t masterSecond; /*!< PTP time second when it's master time*/ -} enet_private_ptp_buffer_t; -#endif - -/*! @brief Defines the ENET header structure. */ -typedef struct ENETEthernetHeader -{ - enetMacAddr destAddr; /*!< Destination address */ - enetMacAddr sourceAddr;/*!< Source address*/ - uint16_t type; /*!< Protocol type*/ -} enet_ethernet_header_t; - -/*! @brief Defines the ENET VLAN frame header structure. */ -typedef struct ENET8021vlanHeader -{ - enetMacAddr destAddr; /*!< Destination address */ - enetMacAddr sourceAddr;/*!< Source address*/ - uint16_t tpidtag; /*!< ENET 8021tag header tag region*/ - uint16_t othertag; /*!< ENET 8021tag header type region*/ - uint16_t type; /*!< Protocol type*/ -} enet_8021vlan_header_t; - -/*! @brief Defines the ENET MAC context structure for the buffer address, buffer descriptor address, etc.*/ -typedef struct ENETMacContext -{ - uint8_t *rxBufferPtr; /*!< Receive buffer pointer*/ - uint8_t *rxLargeBufferPtr; /*!< Receive large buffer descriptor*/ - uint8_t *txBufferPtr; /*!< Transmit buffer pointer*/ - uint8_t *rxBdBasePtr; /*!< Receive buffer descriptor base address pointer*/ - uint8_t *rxBdCurPtr; /*!< Current receive buffer descriptor pointer*/ - uint8_t *rxBdDirtyPtr; /*!< Receive dirty buffer descriptor*/ - uint8_t *txBdBasePtr; /*!< Transmit buffer descriptor base address pointer*/ - uint8_t *txBdCurPtr; /*!< Current transmit buffer descriptor pointer*/ - uint8_t *txBdDirtyPtr; /*!< Last cleaned transmit buffer descriptor pointer*/ - bool isTxFull; /*!< Transmit buffer descriptor full*/ - bool isRxFull; /*!< Receive buffer descriptor full*/ - uint32_t bufferdescSize; /*!< ENET buffer descriptor size*/ - uint16_t rxBufferSizeAligned; /*!< Receive buffer alignment size*/ -#if FSL_FEATURE_ENET_SUPPORT_PTP - enet_private_ptp_buffer_t privatePtp;/*!< PTP private buffer*/ -#endif -} enet_mac_context_t; - -/*! @brief Defines the ENET packets statistic structure.*/ -typedef struct ENETMacStats -{ - uint32_t statsRxTotal; /*!< Total number of receive packets*/ - uint32_t statsRxMissed; /*!< Total number of receive packets*/ - uint32_t statsRxDiscard; /*!< Receive discarded with error */ - uint32_t statsRxError; /*!< Receive discarded with error packets*/ - uint32_t statsTxTotal; /*!< Total number of transmit packets*/ - uint32_t statsTxMissed; /*!< Transmit missed*/ - uint32_t statsTxDiscard; /*!< Transmit discarded with error */ - uint32_t statsTxError; /*!< Transmit error*/ - uint32_t statsRxAlign; /*!< Receive non-octet alignment*/ - uint32_t statsRxFcs; /*!< Receive CRC error*/ - uint32_t statsRxTruncate;/*!< Receive truncate*/ - uint32_t statsRxLengthGreater; /*!< Receive length greater than RCR[MAX_FL] */ - uint32_t statsRxCollision; /*!< Receive collision*/ - uint32_t statsRxOverRun; /*!< Receive over run*/ - uint32_t statsTxOverFlow; /*!< Transmit overflow*/ - uint32_t statsTxLateCollision; /*!< Transmit late collision*/ - uint32_t statsTxExcessCollision;/*!< Transmit excess collision*/ - uint32_t statsTxUnderFlow; /*!< Transmit under flow*/ - uint32_t statsTxLarge; /*!< Transmit large packet*/ - uint32_t statsTxSmall; /*!< Transmit small packet*/ -} enet_stats_t; - -/*! @brief Defines the ENET MAC packet buffer structure.*/ -typedef struct ENETMacPacketBuffer -{ - uint8_t *data; - uint16_t length; -} enet_mac_packet_buffer_t; - -#if ENET_RECEIVE_ALL_INTERRUPT -typedef uint32_t (* enet_netif_callback_t)(void *enetPtr, enet_mac_packet_buffer_t *packetBuffer); -#endif - -/*! @brief Defines the ENET device data structure for the ENET.*/ -typedef struct ENETDevIf -{ - struct ENETDevIf *next; /*!< Next device structure address*/ - void *netIfPtr; /*!< Store the connected upper layer in the structure*/ -#if ENET_RECEIVE_ALL_INTERRUPT - void *enetNetifService; /*!< Service function*/ -#endif - enet_multicast_group_t *multiGroupPtr; /*!< Multicast group chain*/ - uint32_t deviceNumber; /*!< Device number*/ - bool isInitialized; /*!< Device initialized*/ - uint16_t maxFrameSize; /*!< MAC maximum frame size*/ - enet_mac_config_t *macCfgPtr;/*!< MAC configuration structure*/ - enet_phy_config_t *phyCfgPtr;/*!< PHY configuration structure*/ - const struct ENETMacApi *macApiPtr; /*!< MAC application interface structure*/ - void *phyApiPtr; /*!< PHY application interface structure*/ - enet_mac_context_t *macContextPtr; /*!< MAC context pointer*/ -#if ENET_ENABLE_DETAIL_STATS - enet_stats_t stats; /*!< Packets statistic*/ -#endif -#if ENET_RECEIVE_ALL_INTERRUPT - enet_netif_callback_t enetNetifcall; /*!< Receive callback function to the upper layer*/ -#else - event_object_t enetReceiveSync; /*!< Receive sync signal*/ -#endif - lock_object_t enetContextSync; /*!< Sync signal*/ -} enet_dev_if_t; - -/*! @brief Defines the basic application for the ENET device.*/ -typedef struct ENETMacApi -{ - uint32_t (* enet_mac_init)(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg, enet_txbd_config_t *txbdCfg);/*!< MAC initialize interface*/ - uint32_t (* enet_mac_deinit)(enet_dev_if_t * enetIfPtr);/*!< MAC close interface*/ - uint32_t (* enet_mac_send)(enet_dev_if_t * enetIfPtr, uint8_t *packet, uint32_t size);/*!< MAC send packets*/ -#if !ENET_RECEIVE_ALL_INTERRUPT - uint32_t (* enet_mac_receive)(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer);/*!< MAC receive interface*/ -#endif - uint32_t (* enet_mii_read)(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);/*!< MII reads PHY*/ - uint32_t (* enet_mii_write)(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t data);/*!< MII writes PHY*/ - uint32_t (* enet_add_multicast_group)(uint32_t instance, enet_multicast_group_t *multiGroupPtr, uint8_t *groupAddr);/*!< Add multicast group*/ - uint32_t (* enet_leave_multicast_group)(uint32_t instance, enet_multicast_group_t *multiGroupPtr, uint8_t *groupAddr);/*!< Leave multicast group*/ -} enet_mac_api_t; - -/******************************************************************* -* Global variables - -***********************************************************************/ -extern const enet_mac_api_t g_enetMacApi; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name ENET Driver - * @{ - */ - - -#if FSL_FEATURE_ENET_SUPPORT_PTP -/*! - * @brief Initializes the ENET PTP context structure with the basic configuration. - * - * @param macContextPtr The pointer to the ENET MAC macContext structure. - * @return The execution status. - */ -uint32_t enet_ptp_init(enet_private_ptp_buffer_t *privatePtpPtr, uint32_t ptpRxBufferNum, enet_mac_ptp_ts_data_t *ptpTsRxDataPtr, uint32_t ptpTxBufferNum, enet_mac_ptp_ts_data_t *ptpTsTxDataPtr); - -/*! - * @brief Initializes the ENET PTP timer with the basic configuration. - * - * After the PTP starts, the 1588 timer also starts running. If the user wants the 1588 timer - * as the slave, enable the isSlaveEnabled flag. - * - * @param instance The ENET instance number. - * @param ptpCfgPtr The pointer to the basic PTP timer configuration structure. - * @return The execution status. - */ -uint32_t enet_ptp_start(uint32_t instance, bool isSlaveEnabled); - -/*! - * @brief Parses the ENET packet. - * - * Parses the ENET message and checks if it is a PTP message. If it is a PTP message, - * the message is stored in the PTP information structure. Message parsing - * decides whether timestamp processing is done after that. - * - * @param packet The ENET packet. - * @param ptpTsPtr The pointer to the PTP data structure. - * @param isPtpMsg The PTP message flag. - * @param isFastEnabled The fast operation flag. If set, only check if it is a ptp message - * and doesn't store any ptp message. - * @return The execution status. - */ -uint32_t enet_ptp_parse(uint8_t *packet, enet_mac_ptp_ts_data_t *ptpTsPtr, bool *isPtpMsg, bool isFastEnabled); - -/*! - * @brief Gets the current value of the ENET PTP time. - * - * @param ptpTimerPtr The PTP timer structure. - * @return The execution status. - */ -uint32_t enet_ptp_get_time(enet_mac_ptp_time_t *ptpTimerPtr); - -/*! - * @brief Sets the current value of the ENET PTP time. - * - * @param ptpTimerPtr The PTP timer structure. - * @return The execution status. - */ -uint32_t enet_ptp_set_time(enet_mac_ptp_time_t *ptpTimerPtr); - -/*! - * @brief Adjusts the ENET PTP time. - * - * @param instance The ENET instance number. - * @param drift The PTP timer drift value. - * @return The execution status. - */ -uint32_t enet_ptp_correction_time(uint32_t instance, int32_t drift); - - -/*! - * @brief Stores the transmit timestamp. - * - * @param ptpBuffer The PTP buffer pointer. - * @param bdPtr The current transmit buffer descriptor. - * @return The execution status. - */ -uint32_t enet_ptp_store_tx_timestamp(enet_private_ptp_buffer_t *ptpBuffer,void *bdPtr); - -/*! - * @brief Stores receive timestamp. - * - * @param ptpBuffer The PTP buffer pointer. - * @param packet The current receive packet. - * @param bdPtr The current receive buffer descriptor. - * @return The execution status. - */ -uint32_t enet_ptp_store_rx_timestamp(enet_private_ptp_buffer_t *ptpBuffer, uint8_t *packet, void *bdPtr); - -/*! - * @brief Initializes the buffer queue for the PTP layer2 Ethernet packets. - * - * @param ptpBuffer The PTP buffer pointer. - * @return The execution status. - */ -uint32_t enet_ptp_l2queue_init(enet_private_ptp_buffer_t *ptpBuffer, enet_ptp_l2queue_t *ptpL2QuePtr); - -/*! - * @brief Adds the PTP layer2 Ethernet packet to the PTP Ethernet packet queue. - * - * @param ptpQuePtr The ENET private ptp layer2 buffer queue structure pointer. - * @param packet The packet buffer pointer. - * @param length The packet length. - * @return The execution status. - */ -uint32_t enet_ptp_service_l2packet(enet_ptp_l2queue_t * ptpQuePtr, uint8_t *packet, uint16_t length); - -/*! - * @brief Sends the PTP layer2 Ethernet packet to the Net. - * - * @param enetIfPtr The ENET context structure. - * @param paramPtr The buffer from upper layer. - * @return The execution status. - */ -uint32_t enet_ptp_send_l2packet(enet_dev_if_t * enetIfPtr, void *paramPtr); - -/*! - * @brief Receives the PTP layer2 Ethernet packet from the Net. - * - * @param enetIfPtr The ENET context structure. - * @param paramPtr The buffer receive from net and will send to upper layer. - * @return The execution status. - */ -uint32_t enet_ptp_receive_l2packet(enet_dev_if_t * enetIfPtr,void *paramPtr); - -/*! - * @brief Provides the handler for the 1588 stack to do PTP IOCTL. - * - * @param enetIfPtr The ENET context structure. - * @param commandId The command id. - * @param inOutPtr The data buffer. - * @return The execution status. - */ -uint32_t enet_ptp_ioctl(enet_dev_if_t * enetIfPtr, uint32_t commandId, void *inOutPtr); - -/*! - * @brief Stops the ENET PTP timer. - * - * @param instance The ENET instance number. - * @return The execution status. - */ -uint32_t enet_ptp_stop(uint32_t instance); - -/*! - * @brief Checks whether the PTP ring buffer is full. - * - * @param ptpTsRingPtr The ENET PTP timestamp ring. - * @return True if the PTP ring buffer is full. Otherwise, false. - */ -bool enet_ptp_ring_is_full(enet_mac_ptp_ts_ring_t *ptpTsRingPtr); - -/*! - * @brief Updates the latest ring buffers. - * - * Adds the PTP message data to the PTP ring buffers and increases the - * PTP ring buffer index. - * - * @param ptpTsRingPtr The ENET PTP timestamp ring. - * @param data The PTP data buffer. - * @return The execution status. - */ -uint32_t enet_ptp_ring_update(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data); - -/*! - * @brief Searches the element in ring buffers with the message ID and Clock ID. - * - * @param ptpTsRingPtr The ENET PTP timestamp ring. - * @param data The PTP data buffer. - * @return The execution status. - */ -uint32_t enet_ptp_ring_search(enet_mac_ptp_ts_ring_t *ptpTsRingPtr, enet_mac_ptp_ts_data_t *data); - -/*! - * @brief Calculates the ENET PTP ring buffer index. - * - * @param size The ring size. - * @param curIdx The current ring index. - * @param offset The offset index. - * @return The execution status. - */ -static inline uint32_t enet_ptp_ring_index(uint32_t size, uint32_t curIdx, uint32_t offset) -{ - return ((curIdx + offset) % size); -} - -/*! - * @brief Frees all ring buffers. - * - * @param enetContextPtr The ENET MAC context buffer. - * @return The execution status. - */ -uint32_t enet_ptp_deinit(enet_mac_context_t *enetContextPtr); - -/*! - * @brief The ENET PTP time interrupt handler. - * - * @param enetIfPtr The ENET context structure pointer. - */ -void enet_mac_ts_isr(void *enetIfPtr); -#endif -/*! - * @brief(R)MII Read function. - * - * @param instance The ENET instance number. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param dataPtr The data read from MII. - * @return The execution status. - */ -uint32_t enet_mii_read(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); - -/*! - * @brief(R)MII Read function. - * - * @param instance The ENET instance number. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param data The data write to MII. - * @return The execution status. - */ -uint32_t enet_mii_write(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t data); - -/*! - * @brief Initializes ENET buffer descriptors. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_bd_init(enet_dev_if_t * enetIfPtr); - -/*! - * @brief Initializes the ENET MAC MII(MDC/MDIO) interface. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_mii_init(enet_dev_if_t * enetIfPtr); - -/*! - * @brief Initialize the ENET receive buffer descriptors. - * - * If you open ENET_RECEIVE_ALL_INTERRUPT to do receive - * data buffer numbers can be the same as the receive descriptor numbers. - * But if you close ENET_RECEIVE_ALL_INTERRUPT and choose polling receive - * frames please make sure the receive data buffers are more than - * buffer descriptor numbers to guarantee a good performance. - * - * @param enetIfPtr The ENET context structure. - * @param rxbdCfg The receive buffer descriptor configuration. - * @return The execution status. - */ -uint32_t enet_mac_rxbd_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg); - -/*! - * @brief Deinitialize the ENET receive buffer descriptors. - * - * Deinitialize the ENET receive buffer descriptors. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ - -uint32_t enet_mac_rxbd_deinit(enet_dev_if_t * enetIfPtr); - -/*! - * @brief Initialize the ENET transmit buffer descriptors. - * - * @param enetIfPtr The ENET context structure. - * @param txbdCfg The transmit buffer descriptor configuration. - * @return The execution status. - */ -uint32_t enet_mac_txbd_init(enet_dev_if_t * enetIfPtr, enet_txbd_config_t *txbdCfg); - -/*! - * @brief Deinitialize the ENET transmit buffer descriptors. - * - * Deinitialize the ENET transmit buffer descriptors. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_txbd_deinit(enet_dev_if_t * enetIfPtr); - -/*! - * @brief Initializes ENET MAC FIFO and accelerator with the basic configuration. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_configure_fifo_accel(enet_dev_if_t * enetIfPtr); - -/*! - * @brief the ENET controller with the basic configuration. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_configure_controller(enet_dev_if_t * enetIfPtr); - -/*! - * @brief Deinit the ENET device. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_deinit(enet_dev_if_t * enetIfPtr); - -#if !ENET_RECEIVE_ALL_INTERRUPT -/*! - * @brief Updates the receive buffer descriptor. - * - * This updates the used receive buffer descriptor ring to - * ensure that the used BDS is correctly used again. It cleans - * the status region and sets the control region of the used receive buffer - * descriptor. If the isBufferUpdate flag is set, the data buffer in the - * buffer descriptor is updated. - * - * @param enetIfPtr The ENET context structure. - * @param isBufferUpdate The data buffer update flag. - * @return The execution status. - */ -uint32_t enet_mac_update_rxbd(enet_dev_if_t * enetIfPtr, bool isBufferUpdate); -#else -/*! - * @brief Updates the receive buffer descriptor. - * - * Clears the status region and sets the control region of the current receive buffer - * descriptor to ensure that it is used correctly again. It increases the buffer - * descriptor index to the next buffer descriptor. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_update_rxbd(enet_dev_if_t * enetIfPtr); -#endif -/*! - * @brief Processes the ENET receive frame error statistics. - * - * This interface gets the error statistics of the received frame. - * Because the error information is in the last BD of a frame, this interface - * should be called when processing the last BD of a frame. - * - * @param enetIfPtr The ENET context structure. - * @param data The current control and status data of the buffer descriptor. - * @return The frame error status. - * - True if the frame has an error. - * - False if the frame does not have an error. - */ -bool enet_mac_rx_error_stats(enet_dev_if_t * enetIfPtr, uint32_t data); - -/*! - * @brief Processes the ENET transmit frame statistics. - * - * This interface gets the error statistics of the transmit frame. - * Because the error information is in the last BD of a frame, this interface - * should be called when processing the last BD of a frame. - * - * @param enetIfPtr The ENET context structure. - * @param curBd The current buffer descriptor. - */ -void enet_mac_tx_error_stats(enet_dev_if_t * enetIfPtr,void *curBd); - -/*! - * @brief ENET transmit buffer descriptor cleanup. - * - * First, store the transmit frame error statistic and PTP timestamp of the transmitted packets. - * Second, clean up the used transmit buffer descriptors. - * If the PTP 1588 feature is open, this interface captures the 1588 timestamp. - * It is called by the transmit interrupt handler. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_tx_cleanup(enet_dev_if_t * enetIfPtr); -#if !ENET_RECEIVE_ALL_INTERRUPT -/*! - * @brief Receives ENET packets. - * - * @param enetIfPtr The ENET context structure. - * @param packBuffer The received data buffer. - * @return The execution status. - */ -uint32_t enet_mac_receive(enet_dev_if_t * enetIfPtr, enet_mac_packet_buffer_t *packBuffer); -#else -/*! - * @brief Receives ENET packets. - * - * @param enetIfPtr The ENET context structure. - * @return The execution status. - */ -uint32_t enet_mac_receive(enet_dev_if_t * enetIfPtr); -#endif -/*! - * @brief Transmits ENET packets. - * - * @param enetIfPtr The ENET context structure. - * @param packet The frame to be transmitted. - * @param size The frame size. - * @return The execution status. - */ -uint32_t enet_mac_send(enet_dev_if_t * enetIfPtr, uint8_t *packet, uint32_t size); - -/*! - * @brief The ENET receive interrupt handler. - * - * @param enetIfPtr The ENET context structure pointer. - */ -void enet_mac_rx_isr(void *enetIfPtr); - -/*! - * @brief The ENET transmit interrupt handler. - * - * @param enetIfPtr The ENET context structure pointer. - */ -void enet_mac_tx_isr(void *enetIfPtr); - -/*! - * @brief Calculates the CRC hash value. - * - * @param address The ENET MAC hardware address. - * @param crcVlaue The calculated CRC value of the Mac address. - */ -void enet_mac_calculate_crc32(enetMacAddr address, uint32_t *crcValue); - -/*! - * @brief Adds the ENET device to a multicast group. - * - * @param instance The ENET instance number. - * @param multiGroupPtr The ENET multicast group structure. - * @param address The ENET MAC hardware address. - * @return The execution status. - */ -uint32_t enet_mac_add_multicast_group(uint32_t instance, enet_multicast_group_t *multiGroupPtr, enetMacAddr address); - -/*! - * @brief Moves the ENET device from a multicast group. - * - * @param instance The ENET instance number. - * @param multiGroupPtr The ENET multicast group structure. - * @param address The ENET MAC hardware address. - * @return The execution status. - */ -uint32_t enet_mac_leave_multicast_group(uint32_t instance, enet_multicast_group_t *multiGroupPtr, enetMacAddr address); - -/*! - * @brief Initializes the ENET with the basic configuration. - * - * @param enetIfPtr The pointer to the basic configuration structure. - * @return The execution status. - */ -uint32_t enet_mac_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg, - enet_txbd_config_t *txbdCfg); - -/*! - * @brief Enqueues a data buffer to the buffer queue. - * - * @param queue The buffer queue. - * @param buffer The buffer to add to the buffer queue. - */ -void enet_mac_enqueue_buffer( void **queue, void *buffer); - -/*! - * @brief Dequeues a buffer from the buffer queue. - * - * @param queue The buffer queue. - * @return The dequeued data buffer. - */ -void *enet_mac_dequeue_buffer( void **queue); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif - -/*! @}*/ - -#endif /* __FSL_ENET_DRIVER_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_rtcs_adapter.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_rtcs_adapter.h deleted file mode 100644 index 49eeba71b5c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_rtcs_adapter.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_ENET_RTCS_ADAPTOR_H__ -#define __FSL_ENET_RTCS_ADAPTOR_H__ - -#include "fsl_enet_hal.h" - -#ifndef MBED_NO_ENET - -#ifdef FSL_RTOS_MQX - #include "rtcs.h" - #include "pcb.h" -#endif -/*! - * @addtogroup enet_rtcs_adaptor - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Definitions of the task parameter*/ -#ifndef FSL_RTOS_MQX - extern unsigned long _RTCSTASK_priority; -#endif -#define ENET_RECEIVE_TASK_PRIO (1) -#define ENET_TASK_STACK_SIZE (800) -#define ENET_PCB_NUM (16) - -/*! @brief Definitions of the configuration parameter*/ -#define ENET_RXBD_NUM (8) -#define ENET_TXBD_NUM (4) -#define ENET_EXTRXBD_NUM (4) -#define ENET_RXBuff_SIZE (kEnetMaxFrameSize) -#define ENET_TXBuff_SIZE (kEnetMaxFrameSize) -#define ENET_RXRTCSBUFF_NUM (8) -#define ENET_RX_BUFFER_ALIGNMENT (16) -#define ENET_TX_BUFFER_ALIGNMENT (16) -#define ENET_BD_ALIGNMENT (16) -#define ENET_RXBuffSizeAlign(n) ENET_ALIGN(n, ENET_RX_BUFFER_ALIGNMENT) -#define ENET_TXBuffSizeAlign(n) ENET_ALIGN(n, ENET_TX_BUFFER_ALIGNMENT) -#define ENET_MII_CLOCK (2500000L) -#if FSL_FEATURE_ENET_SUPPORT_PTP -#define ENET_PTP_TXTS_RING_LEN (25) -#define ENET_PTP_RXTS_RING_LEN (25) -#endif - -/*! @brief Definitions of the error codes */ -#define ENET_OK (0) -#define ENET_ERROR (0xff) /* General ENET error */ - -#define ENETERR_INVALID_DEVICE (kStatus_ENET_InvalidDevice) /* Device number out of range */ -#define ENETERR_INIT_DEVICE (kStatus_ENET_Initialized) /* Device already initialized */ - -/*! @brief Definitions of the ENET protocol parameter*/ -#define ENETPROT_IP 0x0800 -#define ENETPROT_ARP 0x0806 -#define ENETPROT_8021Q 0x8100 -#define ENETPROT_IP6 0x86DD -#define ENETPROT_ETHERNET 0x88F7 -#define ENET_OPT_8023 0x0001 -#define ENET_OPT_8021QTAG 0x0002 -#define ENET_SETOPT_8021QPRIO(p) (ENET_OPT_8021QTAG | (((uint_32)(p) & 0x7) << 2)) -#define ENET_GETOPT_8021QPRIO(f) ((((unsigned int)f) >> 2) & 0x7) - -/*! @brief Definitions of the ENET option macro*/ -#define ENET_OPTION_HW_TX_IP_CHECKSUM 0x00001000 -#define ENET_OPTION_HW_TX_PROTOCOL_CHECKSUM 0x00002000 -#define ENET_OPTION_HW_RX_IP_CHECKSUM 0x00004000 -#define ENET_OPTION_HW_RX_PROTOCOL_CHECKSUM 0x00008000 -#define ENET_OPTION_HW_RX_MAC_ERR 0x00010000 - -/*! @brief Definitions of the ENET default Mac*/ -#define ENET_DEFAULT_MAC_ADD { 0x00, 0x00, 0x5E, 0, 0, 0 } -#define PCB_MINIMUM_SIZE (sizeof(PCB2)) -#define PCB_free(pcb_ptr) ((pcb_ptr)->FREE(pcb_ptr)) - -/*! @brief Definitions of the macro for byte-swap*/ -#if SYSTEM_LITTLE_ENDIAN -#define RTCS_HTONS(n) BSWAP_16(n) -#define RTCS_HTONL(n) BSWAP_32(n) -#define RTCS_NTOHS(n) BSWAP_16(n) -#define RTCS_NTOHL(n) BSWAP_32(n) -#else -#define RTCS_HTONS(n) (n) -#define RTCS_HTONL(n) (n) -#define RTCS_NTOHS(n) (n) -#define RTCS_NTOHL(n) (n) -#endif - -#ifndef FSL_RTOS_MQX - #define htonl(p,x) (((uint_8_ptr)(p))[0] = ((x) >> 24) & 0xFF, \ - ((uint_8_ptr)(p))[1] = ((x) >> 16) & 0xFF, \ - ((uint_8_ptr)(p))[2] = ((x) >> 8) & 0xFF, \ - ((uint_8_ptr)(p))[3] = (x) & 0xFF, \ - (x)) - -#define htons(p,x) (((uint_8_ptr)(p))[0] = ((x) >> 8) & 0xFF, \ - ((uint_8_ptr)(p))[1] = (x) & 0xFF, \ - (x)) - -#define htonc(p,x) (((uint_8_ptr)(p))[0] = (x) & 0xFF, \ - (x)) - -#define ntohl(p) (\ - (((uint_32)(((uint_8_ptr)(p))[0])) << 24) | \ - (((uint_32)(((uint_8_ptr)(p))[1])) << 16) | \ - (((uint_32)(((uint_8_ptr)(p))[2])) << 8) | \ - ( (uint_32)(((uint_8_ptr)(p))[3])) \ - ) - -#define ntohs(p) (\ - (((uint_16)(((uint_8_ptr)(p))[0])) << 8) | \ - ( (uint_16)(((uint_8_ptr)(p))[1])) \ - ) - -#define ntohc(p) ((uint_8)(((uint_8_ptr)(p))[0])) -#endif -#define htone(p,x) ((p)[0] = (x)[0], \ - (p)[1] = (x)[1], \ - (p)[2] = (x)[2], \ - (p)[3] = (x)[3], \ - (p)[4] = (x)[4], \ - (p)[5] = (x)[5] \ - ) - -#define ntohe(p,x) ((x)[0] = (p)[0] & 0xFF, \ - (x)[1] = (p)[1] & 0xFF, \ - (x)[2] = (p)[2] & 0xFF, \ - (x)[3] = (p)[3] & 0xFF, \ - (x)[4] = (p)[4] & 0xFF, \ - (x)[5] = (p)[5] & 0xFF \ - ) - -/*! @brief Definitions of the add to queue*/ -#define QUEUEADD(head,tail,pcb) \ - if ((head) == NULL) { \ - (head) = (pcb); \ - } else { \ - (tail)->PRIVATE = (pcb); \ - } \ - (tail) = (pcb); \ - (pcb)->PRIVATE = NULL - -/*! @brief Definitions of the get from queue*/ -#define QUEUEGET(head,tail,pcb) \ - (pcb) = (head); \ - if (head) { \ - (head) = (head)->PRIVATE; \ - if ((head) == NULL) { \ - (tail) = NULL; \ - } \ - } - -/*! @brief Definition for ENET six-byte Mac type*/ -typedef unsigned char _enet_address[6]; - -/*! @brief Definition of the IPCFG structure*/ -typedef void * _enet_handle; - -#ifndef FSL_RTOS_MQX - struct pcb; - typedef void (* PCB_FREE_FPTR)(struct pcb *); -#endif - -/*! @brief Definition of the Ethernet packet header structure*/ -typedef struct enet_header -{ - _enet_address DEST; /*!< destination Mac address*/ - _enet_address SOURCE; /*!< source Mac address*/ - unsigned char TYPE[2]; /*!< protocol type*/ -} ENET_HEADER, * ENET_HEADER_PTR; - -#ifndef FSL_RTOS_MQX - -/*! @brief Definition of the fragment PCB structure*/ -typedef struct pcb_fragment -{ - uint32_t LENGTH; /*!< Packet fragment length*/ - unsigned char *FRAGMENT; /*!< brief Pointer to fragment*/ -} PCB_FRAGMENT, * PCB_FRAGMENT_PTR; - -/*! @brief Definition of the PCB structure for the RTCS adaptor*/ -typedef struct pcb -{ - PCB_FREE_FPTR FREE; /*!< Function that frees PCB*/ - void *PRIVATE; /*!< Private PCB information*/ - PCB_FRAGMENT FRAG[1]; /*!< Pointer to PCB fragment*/ -} PCB, * PCB_PTR; - -/*! @brief Definition of the two fragment PCB structure*/ -typedef struct pcb2 -{ - PCB_FREE_FPTR FREE; /*!< Function that frees PCB*/ - void *PRIVATE; /*!< Private PCB information*/ - PCB_FRAGMENT FRAG[2]; /*!< Pointers to two PCB fragments*/ -} PCB2, *PCB2_PTR; - -#endif - -/*! @brief Definition of the two fragment PCB structure*/ -typedef struct pcb_queue -{ - PCB *pcbHead; /*!< PCB buffer head*/ - PCB *pcbTail; /*!< PCB buffer tail*/ -}pcb_queue; - -/*! @brief Definition of the ECB structure, which contains the protocol type and it's related service function*/ -typedef struct ENETEcbStruct -{ - uint16_t TYPE; - void (* SERVICE)(PCB_PTR, void *); - void *PRIVATE; - struct ENETEcbStruct *NEXT; -} enet_ecb_struct_t; - -/*! @brief Definition of the 8022 header*/ -typedef struct enet_8022_header -{ - uint8_t dsap[1]; /*!< DSAP region*/ - uint8_t ssap[1]; /*!< SSAP region*/ - uint8_t command[1]; /*!< Command region*/ - uint8_t oui[3]; /*!< OUI region*/ - uint16_t type; /*!< type region*/ -}enet_8022_header_t, *enet_8022_header_ptr; - -/*! @brief Definition of the common status structure*/ -typedef struct enet_commom_stats_struct { - uint32_t ST_RX_TOTAL; /*!< Total number of received packets*/ - uint32_t ST_RX_MISSED; /*!< Number of missed packets*/ - uint32_t ST_RX_DISCARDED; /*!< Discarded a protocol that was not recognized*/ - uint32_t ST_RX_ERRORS; /*!< Discarded error during reception*/ - uint32_t ST_TX_TOTAL; /*!< Total number of transmitted packets*/ - uint32_t ST_TX_MISSED; /*!< Discarded transmit ring full*/ - uint32_t ST_TX_DISCARDED; /*!< Discarded bad packet*/ - uint32_t ST_TX_ERRORS; /*!< Error during transmission*/ -} ENET_COMMON_STATS_STRUCT, * ENET_COMMON_STATS_STRUCT_PTR; - -typedef struct enet_stats { - ENET_COMMON_STATS_STRUCT COMMON; /*!< Common status structure*/ - uint32_t ST_RX_ALIGN; /*!< Frame Alignment error*/ - uint32_t ST_RX_FCS; /*!< CRC error */ - uint32_t ST_RX_RUNT; /*!< Runt packet received */ - uint32_t ST_RX_GIANT; /*!< Giant packet received*/ - uint32_t ST_RX_LATECOLL; /*!< Late collision */ - uint32_t ST_RX_OVERRUN; /*!< DMA overrun*/ - uint32_t ST_TX_SQE; /*!< Heartbeat lost*/ - uint32_t ST_TX_DEFERRED; /*!< Transmission deferred*/ - uint32_t ST_TX_LATECOLL; /*!< Late collision*/ - uint32_t ST_TX_EXCESSCOLL; /*!< Excessive collisions*/ - uint32_t ST_TX_CARRIER; /*!< Carrier sense lost*/ - uint32_t ST_TX_UNDERRUN; /*!< DMA underrun*/ - /* Following stats are collected by the Ethernet driver */ - uint32_t ST_RX_COPY_SMALL; /*!< Driver had to copy packet */ - uint32_t ST_RX_COPY_LARGE; /*!< Driver had to copy packet */ - uint32_t ST_TX_COPY_SMALL; /*!< Driver had to copy packet */ - uint32_t ST_TX_COPY_LARGE; /*!< Driver had to copy packet */ - uint32_t RX_FRAGS_EXCEEDED; - uint32_t RX_PCBS_EXHAUSTED; - uint32_t RX_LARGE_BUFFERS_EXHAUSTED; - uint32_t TX_ALIGNED; - uint32_t TX_ALL_ALIGNED; -#if BSPCFG_ENABLE_ENET_HISTOGRAM - uint32_t RX_HISTOGRAM[ENET_HISTOGRAM_ENTRIES]; - uint32_t TX_HISTOGRAM[ENET_HISTOGRAM_ENTRIES]; -#endif - -} ENET_STATS, * ENET_STATS_PTR; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name ENET RTCS ADAPTOR - * @{ - */ - - /*! - * @brief Initializes the ENET device. - * - * @param device The ENET device number. - * @param address The hardware address. - * @param flag The flag for upper layer. - * @param handle The address pointer for ENET device structure. - * @return The execution status. - */ -uint32_t ENET_initialize(uint32_t device, _enet_address address,uint32_t flag, _enet_handle *handle); - -/*! - * @brief Opens the ENET device. - * - * @param handle The address pointer for ENET device structure. - * @param type The ENET protocol type. - * @param service The service function for type. - * @param private The private data for ENET device. - * @return The execution status. - */ -uint32_t ENET_open(_enet_handle handle, uint16_t type, void (* service)(PCB_PTR, void *), void *private); - -/*! - * @brief Shuts down the ENET device. - * - * @param handle The address pointer for ENET device structure. - * @return The execution status. - */ -uint32_t ENET_shutdown(_enet_handle handle); -#if !ENET_RECEIVE_ALL_INTERRUPT -/*! - * @brief ENET frame receive. - * - * @param enetIfPtr The address pointer for ENET device structure. - */ -static void ENET_receive(task_param_t param); -#endif -/*! - * @brief ENET frame transmit. - * - * @param handle The address pointer for ENET device structure. - * @param packet The ENET packet buffer. - * @param type The ENET protocol type. - * @param dest The destination hardware address. - * @param flag The flag for upper layer. - * @return The execution status. - */ -uint32_t ENET_send(_enet_handle handle, PCB_PTR packet, uint32_t type, _enet_address dest, uint32_t flags) ; - -/*! - * @brief The ENET gets the address with the initialized device. - * - * @param handle The address pointer for ENET device structure. - * @param address The destination hardware address. - * @return The execution status. - */ -uint32_t ENET_get_address(_enet_handle handle, _enet_address address); - -/*! - * @brief The ENET gets the address with an uninitialized device. - * - * @param handle The address pointer for ENET device structure. - * @param value The value to change the last three bytes of hardware. - * @param address The destination hardware address. - * @return True if the execution status is success else false. - */ -uint32_t ENET_get_mac_address(uint32_t device, uint32_t value, _enet_address address); -/*! - * @brief The ENET joins a multicast group address. - * - * @param handle The address pointer for ENET device structure. - * @param type The ENET protocol type. - * @param address The destination hardware address. - * @return The execution status. - */ -uint32_t ENET_join(_enet_handle handle, uint16_t type, _enet_address address); - -/*! - * @brief The ENET leaves a multicast group address. - * - * @param handle The address pointer for ENET device structure. - * @param type The ENET protocol type. - * @param address The destination hardware address. - * @return The execution status. - */ -uint32_t ENET_leave(_enet_handle handle, uint16_t type, _enet_address address); -#if BSPCFG_ENABLE_ENET_STATS -/*! - * @brief The ENET gets the packet statistic. - * - * @param handle The address pointer for ENET device structure. - * @return The statistic. - */ -ENET_STATS_PTR ENET_get_stats(_enet_handle handle); -#endif -/*! - * @brief The ENET gets the link status. - * - * @param handle The address pointer for ENET device structure. - * @return The link status. - */ -bool ENET_link_status(_enet_handle handle); - -/*! - * @brief The ENET gets the link speed. - * - * @param handle The address pointer for ENET device structure. - * @return The link speed. - */ -uint32_t ENET_get_speed(_enet_handle handle); - -/*! - * @brief The ENET gets the MTU. - * - * @param handle The address pointer for ENET device structure. - * @return The link MTU - */ -uint32_t ENET_get_MTU(_enet_handle handle); - -/*! - * @brief Gets the ENET PHY registers. - * - * @param handle The address pointer for ENET device structure. - * @param numRegs The number of registers. - * @param regPtr The buffer for data read from PHY registers. - * @return True if all numRegs registers are read succeed else false. - */ -bool ENET_phy_registers(_enet_handle handle, uint32_t numRegs, uint32_t *regPtr); - -/*! - * @brief Gets ENET options. - * - * @param handle The address pointer for ENET device structure. - * @return ENET options. - */ -uint32_t ENET_get_options(_enet_handle handle); - -/*! - * @brief Unregisters a protocol type on an Ethernet channel. - * - * @param handle The address pointer for ENET device structure. - * @return ENET options. - */ -uint32_t ENET_close(_enet_handle handle, uint16_t type); - -/*! - * @brief ENET mediactl. - * - * @param handle The address pointer for ENET device structure. - * @param The command ID. - * @param The buffer for input or output parameters. - * @return ENET options. - */ -uint32_t ENET_mediactl(_enet_handle handle, uint32_t commandId, void *inOutParam); - -/*! - * @brief Gets the next ENET device handle address. - * - * @param handle The address pointer for ENET device structure. - * @return The address of next ENET device handle. - */ -_enet_handle ENET_get_next_device_handle(_enet_handle handle); - -/*! - * @brief ENET free. - * - * @param packet The buffer address. - */ -void ENET_free(PCB_PTR packet); - -/*! - * @brief ENET error description. - * - * @param error The ENET error code. - * @return The error string. - */ -const char * ENET_strerror(uint32_t error); - - - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* MBED_NO_ENET */ - -#endif /* __FSL_ENET_RTCS_ADAPTOR_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - - - - - - - - - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/src/fsl_enet_irq.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/src/fsl_enet_irq.c deleted file mode 100644 index f2aba406377..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/src/fsl_enet_irq.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_enet_driver.h" -#include "fsl_clock_manager.h" -/******************************************************************************* - * Variables - ******************************************************************************/ - - -/* Internal irq number*/ -typedef enum _enet_irq_number -{ - kEnetTsTimerNumber = 0, /*!< ENET ts_timer irq number*/ - kEnetReceiveNumber = 1, /*!< ENET receive irq number*/ - kEnetTransmitNumber = 2, /*!< ENET transmit irq number*/ - kEnetMiiErrorNumber = 3 /*!< ENET mii error irq number*/ -}enet_irq_number_t; - -#if FSL_FEATURE_ENET_SUPPORT_PTP -extern enet_ptp_master_time_data_t g_ptpMasterTime; -#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT -#define ENET_TIMER_CHANNEL_NUM 2 -#endif -#endif - -#if defined (K64F12_SERIES) || defined (K70F12_SERIES) -IRQn_Type enet_irq_ids[HW_ENET_INSTANCE_COUNT][FSL_FEATURE_ENET_INTERRUPT_COUNT] = -{ - { ENET_1588_Timer_IRQn, ENET_Receive_IRQn, ENET_Transmit_IRQn, ENET_Error_IRQn} -}; - -uint8_t enetIntMap[kEnetIntNum] = -{ - kEnetTsTimerNumber, - kEnetTsTimerNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetReceiveNumber, - kEnetReceiveNumber, - kEnetTransmitNumber, - kEnetTransmitNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber, - kEnetMiiErrorNumber -}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -/* The code was moved to k64f mac file (eth) */ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/subdir.mk b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/subdir.mk deleted file mode 100644 index 533824b7cda..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/subdir.mk +++ /dev/null @@ -1,4 +0,0 @@ -ENET_DRIVER_DIR := $(SDK_ROOT)/platform/drivers/enet -SOURCES += $(ENET_DRIVER_DIR)/src/fsl_enet_driver.c \ - $(ENET_DRIVER_DIR)/src/fsl_enet_irq.c -INCLUDES += $(ENET_DRIVER_DIR) diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_features.h deleted file mode 100644 index d85555fd011..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_features.h +++ /dev/null @@ -1,126 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140526 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_INTERRUPT_FEATURES_H__) -#define __FSL_INTERRUPT_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) - /* @brief Lowest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) - /* @brief Highest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MAX (73) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ - defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Lowest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) - /* @brief Highest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ - defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \ - defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) - /* @brief Lowest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) - /* @brief Highest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || \ - defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV45F128VLL15) || \ - defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15) - /* @brief Lowest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) - /* @brief Highest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MAX (99) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \ - defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \ - defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ - defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || \ - defined(CPU_MKL17Z128VFT4) || defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4) || \ - defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ - defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ - defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \ - defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL33Z128VLH4) || \ - defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || \ - defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || \ - defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Lowest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) - /* @brief Highest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ - defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ - defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15) - /* @brief Lowest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) - /* @brief Highest interrupt request number. */ - #define FSL_FEATURE_INTERRUPT_IRQ_MAX (92) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_INTERRUPT_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h deleted file mode 100644 index 6e42e1c90e3..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_INTERRUPT_MANAGER_H__) -#define __FSL_INTERRUPT_MANAGER_H__ - -#include -#include -#include -#include "fsl_interrupt_features.h" -#include "device/fsl_device_registers.h" - -/*! @addtogroup interrupt_manager*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name interrupt_manager APIs*/ -/*@{*/ - -/*! - * @brief Installs an interrupt handler routine for a given IRQ number. - * - * This function lets the application register/replace the interrupt - * handler for a specified IRQ number. The IRQ number is different than the vector - * number. IRQ 0 starts from the vector 16 address. See a chip-specific reference - * manual for details and the startup_MKxxxx.s file for each chip - * family to find out the default interrupt handler for each device. This - * function converts the IRQ number to the vector number by adding 16 to - * it. - * - * @param irqNumber IRQ number - * @param handler Interrupt handler routine address pointer - */ -void INT_SYS_InstallHandler(IRQn_Type irqNumber, void (*handler)(void)); - -/*! - * @brief Enables an interrupt for a given IRQ number. - * - * This function enables the individual interrupt for a specified IRQ - * number. It calls the system NVIC API to access the interrupt control - * register. The input IRQ number does not include the core interrupt, only - * the peripheral interrupt, from 0 to a maximum supported IRQ. - * - * @param irqNumber IRQ number - */ -static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber) -{ - /* check IRQ number */ - assert(0 <= irqNumber); - assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX); - - /* call core API to enable the IRQ*/ - NVIC_EnableIRQ(irqNumber); -} - -/*! - * @brief Disables an interrupt for a given IRQ number. - * - * This function enables the individual interrupt for a specified IRQ - * number. It calls the system NVIC API to access the interrupt control - * register. - * - * @param irqNumber IRQ number - */ -static inline void INT_SYS_DisableIRQ(IRQn_Type irqNumber) -{ - /* check IRQ number */ - assert(0 <= irqNumber); - assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX); - - /* call core API to disable the IRQ*/ - NVIC_DisableIRQ(irqNumber); -} - -/*! - * @brief Enables system interrupt. - * - * This function enables the global interrupt by calling the core API. - * - */ -void INT_SYS_EnableIRQGlobal(void); - -/*! - * @brief Disable system interrupt. - * - * This function disables the global interrupt by calling the core API. - * - */ -void INT_SYS_DisableIRQGlobal(void); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_INTERRUPT_MANAGER_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.c deleted file mode 100644 index fb92a0bb2ce..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pit_features.h" -#include "fsl_device_registers.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Table of base addresses for pit instances. */ -const uint32_t g_pitBaseAddr[] = PIT_BASE_ADDRS; - -/* Table to save PIT IRQ enum numbers defined in CMSIS files. */ -const IRQn_Type g_pitIrqId[] = PIT_IRQS; - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.h deleted file mode 100644 index de9bddea83b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_PIT_COMMON_H__) -#define __FSL_PIT_COMMON_H__ - -#include -#include "fsl_device_registers.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Table of base addresses for pit instances. */ -extern const uint32_t g_pitBaseAddr[]; - -/*! @brief Table to save pit IRQ enum numbers defined in CMSIS header file. */ -extern const IRQn_Type g_pitIrqId[]; - -#endif /* __FSL_PIT_COMMON_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/fsl_pit_driver.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/fsl_pit_driver.h deleted file mode 100644 index c92a58975ab..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/fsl_pit_driver.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_PIT_DRIVER_H__ -#define __FSL_PIT_DRIVER_H__ - -#include -#include -#include "fsl_pit_hal.h" - -/*! - * @addtogroup pit_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief PIT timer configuration structure - * - * Define structure PitConfig and use the PIT_DRV_InitChannel() function to make necessary - * initializations. You may also use the remaining functions for PIT configuration. - * - * @note The timer chain feature is not valid in all devices. Check the - * fsl_pit_features.h for accurate settings. If it's not valid, the value set here - * will be bypassed inside the PIT_DRV_InitChannel() function. - */ -typedef struct PitUserConfig { - bool isInterruptEnabled; /*!< Timer interrupt 0-disable/1-enable*/ - bool isTimerChained; /*!< Chained with previous timer, 0-not/1-chained*/ - uint32_t periodUs; /*!< Timer period in unit of microseconds*/ -} pit_user_config_t; - -/*! @brief PIT ISR callback function typedef */ -typedef void (*pit_isr_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialize and Shutdown - * @{ - */ - -/*! - * @brief Initializes the PIT module. - * - * This function must be called before calling all the other PIT driver functions. - * This function un-gates the PIT clock and enables the PIT module. The isRunInDebug - * passed into function affects all timer channels. - * - * @param instance PIT module instance number. - * @param isRunInDebug Timers run or stop in debug mode. - * - true: Timers continue to run in debug mode. - * - false: Timers stop in debug mode. - */ -void PIT_DRV_Init(uint32_t instance, bool isRunInDebug); - -/*! - * @brief Disables the PIT module and gate control. - * - * This function disables all PIT interrupts and PIT clock. It then gates the - * PIT clock control. PIT_DRV_Init must be called if you want to use PIT again. - * - * @param instance PIT module instance number. - */ -void PIT_DRV_Deinit(uint32_t instance); - -/*! - * @brief Initializes the PIT channel. - * - * This function initializes the PIT timers by using a channel. Pass in the timer number and its - * configuration structure. Timers do not start counting by default after calling this - * function. The function PIT_DRV_StartTimer must be called to start the timer counting. - * Call the PIT_DRV_SetTimerPeriodByUs to re-set the period. - * - * This is an example demonstrating how to define a PIT channel configuration structure: - @code - pit_user_config_t pitTestInit = { - .isInterruptEnabled = true, - // Only takes effect when chain feature is available. - // Otherwise, pass in arbitrary value(true/false). - .isTimerChained = false, - // In unit of microseconds. - .periodUs = 1000, - }; - @endcode - * - * @param instance PIT module instance number. - * @param channel Timer channel number. - * @param config PIT channel configuration structure. - */ -void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config); - -/* @} */ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, count down to 0 and - * then load the respective start value again. Each time a timer reaches 0, - * it generates a trigger pulse and sets the timeout interrupt flag. - * - * @param instance PIT module instance number. - * @param channel Timer channel number. - */ -void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel); - -/*! - * @brief Stops the timer counting. - * - * This function stops every timer counting. Timers reload their periods - * respectively after the next time they call the PIT_DRV_StartTimer. - * - * @param instance PIT module instance number. - * @param channel Timer channel number. - */ -void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel); - -/* @} */ - -/*! - * @name Timer Period - * @{ - */ - -/*! - * @brief Sets the timer period in microseconds. - * - * The period range depends on the frequency of the PIT source clock. If the required period - * is out of range, use the lifetime timer. - * - * @param instance PIT module instance number. - * @param channel Timer channel number. - * @param us Timer period in microseconds. - */ -void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us); - -/*! - * @brief Reads the current timer value in microseconds. - * - * This function returns an absolute time stamp in microseconds. - * One common use of this function is to measure the running time of a part of - * code. Call this function at both the beginning and end of code. The time - * difference between these two time stamps is the running time. Make sure the - * running time does not exceed the timer period. The time stamp returned is - * up-counting. - * - * @param instance PIT module instance number. - * @param channel Timer channel number. - * @return Current timer value in microseconds. - */ -uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel); - -#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER -/*! - * @brief Sets the lifetime timer period. - * - * Timer 1 must be chained with timer 0 before using the lifetime timer. The period - * range is restricted by "period * pitSourceClock < max of an uint64_t integer", - * or it may cause an overflow and be unable to set the correct period. - * - * @param instance PIT module instance number. - * @param period Lifetime timer period in microseconds. - */ -void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us); - -/*! - * @brief Reads the current lifetime value in microseconds. - * - * This feature returns an absolute time stamp in microseconds. The time stamp - * value does not exceed the timer period. The timer is up-counting. - * - * @param instance PIT module instance number. - * @return Current lifetime timer value in microseconds. - */ -uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance); -#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/ - -/* @} */ - -/*! - * @name ISR Callback Function - * @{ - */ - -/*! - * @brief Registers the PIT ISR callback function. - * - * System default ISR interfaces are already defined in the fsl_pit_irq.c. Users - * can either edit these ISRs or use this function to register a callback - * function. The default ISR runs the callback function if there is one - * installed. - * - * @param instance PIT module instance number. - * @param channel Timer channel number. - * @param function Pointer to pit ISR callback function. - */ -void PIT_DRV_InstallCallback(uint32_t instance, uint32_t channel, pit_isr_callback_t function); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_PIT_DRIVER_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_driver.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_driver.c deleted file mode 100644 index 0068541186c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_driver.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pit_common.h" -#include "fsl_pit_driver.h" -#include "fsl_clock_manager.h" -#include "fsl_interrupt_manager.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* pit source clock variable which will be updated in PIT_DRV_Init. */ -uint64_t pitSourceClock; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_Init - * Description : Initialize PIT module. - * This function must be called before calling all the other PIT driver functions. - * This function un-gates the PIT clock and enables the PIT module. The isRunInDebug - * passed into function will affect all timer channels. - * - *END**************************************************************************/ -void PIT_DRV_Init(uint32_t instance, bool isRunInDebug) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - - /* Un-gate pit clock*/ - CLOCK_SYS_EnablePitClock( 0U); - - /* Enable PIT module clock*/ - PIT_HAL_Enable(baseAddr); - - /* Set timer run or stop in debug mode*/ - PIT_HAL_SetTimerRunInDebugCmd(baseAddr, isRunInDebug); - - /* Finally, update pit source clock frequency.*/ - pitSourceClock = CLOCK_SYS_GetPitFreq(0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_InitChannel - * Description : Initialize PIT channel. - * This function initialize PIT timers by channel. Pass in timer number and its - * config structure. Timers do not start counting by default after calling this - * function. Function PIT_DRV_StartTimer must be called to start timer counting. - * Call PIT_DRV_SetTimerPeriodByUs to re-set the period. - * - *END**************************************************************************/ -void PIT_DRV_InitChannel(uint32_t instance, uint32_t channel, const pit_user_config_t * config) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - /* Set timer period.*/ - PIT_DRV_SetTimerPeriodByUs(instance, channel, config->periodUs); - - #if FSL_FEATURE_PIT_HAS_CHAIN_MODE - /* Configure timer chained or not.*/ - PIT_HAL_SetTimerChainCmd(baseAddr, channel, config->isTimerChained); - #endif - - /* Enable or disable interrupt.*/ - PIT_HAL_SetIntCmd(baseAddr, channel, config->isInterruptEnabled); - - /* Configure NVIC*/ - if (config->isInterruptEnabled) - { - /* Enable PIT interrupt.*/ - INT_SYS_EnableIRQ(g_pitIrqId[channel]); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_Deinit - * Description : Disable PIT module and gate control - * This function will disable all PIT interrupts and PIT clock. Then gate the - * PIT clock control. pit_init must be called in order to use PIT again. - * - *END**************************************************************************/ -void PIT_DRV_Deinit(uint32_t instance) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - uint32_t i; - - /* Disable all PIT interrupts. */ - for (i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++) - { - PIT_HAL_SetIntCmd(baseAddr, i, false); - INT_SYS_DisableIRQ(g_pitIrqId[i]); - } - - /* Disable PIT module clock*/ - PIT_HAL_Disable(baseAddr); - - /* Gate PIT clock control*/ - CLOCK_SYS_DisablePitClock( 0U); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_StartTimer - * Description : Start timer counting. - * After calling this function, timers load period value, count down to 0 and - * then load the respective start value again. Each time a timer reaches 0, - * it will generate a trigger pulse and set the timeout interrupt flag. - * - *END**************************************************************************/ -void PIT_DRV_StartTimer(uint32_t instance, uint32_t channel) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - PIT_HAL_StartTimer(baseAddr, channel); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_StopTimer - * Description : Stop timer counting. - * This function will stop every timer counting. Timers will reload their periods - * respectively after calling PIT_DRV_StartTimer next time. - * - *END**************************************************************************/ -void PIT_DRV_StopTimer(uint32_t instance, uint32_t channel) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - PIT_HAL_StopTimer(baseAddr, channel); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_SetTimerPeriodByUs - * Description : Set timer period in microseconds unit. - * The period range depends on the frequency of PIT source clock. If required - * period is out the range, try to use lifetime timer if applicable. - * - *END**************************************************************************/ -void PIT_DRV_SetTimerPeriodByUs(uint32_t instance, uint32_t channel, uint32_t us) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - /* Calculate the count value, assign it to timer counter register.*/ - uint32_t count = (uint32_t)(us * pitSourceClock / 1000000U - 1U); - PIT_HAL_SetTimerPeriodByCount(baseAddr, channel, count); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_ReadTimerUs - * Description : Read current timer value in microseconds unit. - * This function will return an absolute time stamp in the unit of microseconds. - * One common use of this function is to measure the running time of part of - * code. Just call this function at both the beginning and end of code, the time - * difference between these two time stamp will be the running time (Need to - * make sure the running time will not exceed the timer period). Also, the time - * stamp returned is up-counting. - * - *END**************************************************************************/ -uint32_t PIT_DRV_ReadTimerUs(uint32_t instance, uint32_t channel) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - /* Get current timer count, and reverse it to up-counting.*/ - uint64_t currentTime = (~PIT_HAL_ReadTimerCount(baseAddr, channel)); - - /* Convert count numbers to microseconds unit.*/ - currentTime = (currentTime * 1000000U) / pitSourceClock; - return (uint32_t)currentTime; -} - -#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_SetLifetimeTimerPeriodByUs - * Description : Set lifetime timer period (Timers must be chained). - * Timer 1 must be chained with timer 0 before using lifetime timer. The period - * range is restricted by "period * pitSourceClock < max of an uint64_t integer", - * or it may cause a overflow and is not able to set correct period. - * - *END**************************************************************************/ -void PIT_DRV_SetLifetimeTimerPeriodByUs(uint32_t instance, uint64_t us) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - uint64_t lifeTimeCount; - - /* Calculate the counter value.*/ - lifeTimeCount = us * pitSourceClock / 1000000U - 1U; - - /* Assign to timers.*/ - PIT_HAL_SetTimerPeriodByCount(baseAddr, 0U, (uint32_t)lifeTimeCount); - PIT_HAL_SetTimerPeriodByCount(baseAddr, 1U, (uint32_t)(lifeTimeCount >> 32U)); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_ReadLifetimeTimerUs - * Description : Read current lifetime value in microseconds unit. - * Return an absolute time stamp in the unit of microseconds. The time stamp - * value will not exceed the timer period. Also, the timer is up-counting. - * - *END**************************************************************************/ -uint64_t PIT_DRV_ReadLifetimeTimerUs(uint32_t instance) -{ - assert(instance < HW_PIT_INSTANCE_COUNT); - - uint32_t baseAddr = g_pitBaseAddr[instance]; - /* Get current lifetime timer count, and reverse it to up-counting.*/ - uint64_t currentTime = (~PIT_HAL_ReadLifetimeTimerCount(baseAddr)); - - /* Convert count numbers to microseconds unit.*/ - /* Note: using currentTime * 1000 rather than 1000000 to avoid short time overflow. */ - return currentTime = (currentTime * 1000U) / (pitSourceClock / 1000U); -} -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_irq.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_irq.c deleted file mode 100644 index 411ee79e878..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_irq.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "fsl_pit_common.h" -#include "fsl_pit_driver.h" - -/*! - * @addtogroup pit_irq - * @{ - */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! - * @brief Function table to save PIT isr callback function pointers. - * - * Call PIT_DRV_InstallCallback to install isr callback functions. - */ -static pit_isr_callback_t pitIsrCallbackTable[HW_PIT_INSTANCE_COUNT][FSL_FEATURE_PIT_TIMER_COUNT] = {{NULL}}; - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined (KL25Z4_SERIES) -/*! - * @brief System default IRQ handler defined in startup code. - * - * Users can either edit this handler or define a callback function. Furthermore, - * interrupt manager could be used to re-map the IRQ handler to another function. - */ -void PIT_IRQHandler(void) -{ - uint32_t i; - for(i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++) - { - /* Clear interrupt flag.*/ - PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], i); - - /* Run callback function if it exists.*/ - if (pitIsrCallbackTable[0][i]) - { - (*pitIsrCallbackTable[0][i])(); - } - } -} - -#elif defined (K64F12_SERIES) || defined (K24F12_SERIES) || defined (K63F12_SERIES) || \ - defined (K22F12810_SERIES) || defined (K22F25612_SERIES) || defined (K22F51212_SERIES) || \ - defined (KV31F12810_SERIES) || defined (KV31F25612_SERIES) || defined (KV31F51212_SERIES) || \ - defined (K70F12_SERIES) -void PIT0_IRQHandler(void) -{ - /* Clear interrupt flag.*/ - PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 0U); - - /* Run callback function if it exists.*/ - if (pitIsrCallbackTable[0][0]) - { - (*pitIsrCallbackTable[0][0])(); - } -} - -void PIT1_IRQHandler(void) -{ - /* Clear interrupt flag.*/ - PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 1U); - - /* Run callback function if it exists.*/ - if (pitIsrCallbackTable[0][1]) - { - (*pitIsrCallbackTable[0][1])(); - } -} - -void PIT2_IRQHandler(void) -{ - /* Clear interrupt flag.*/ - PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 2U); - - /* Run callback function if it exists.*/ - if (pitIsrCallbackTable[0][2]) - { - (*pitIsrCallbackTable[0][2])(); - } -} - -void PIT3_IRQHandler(void) -{ - /* Clear interrupt flag.*/ - PIT_HAL_ClearIntFlag(g_pitBaseAddr[0], 3U); - - /* Run callback function if it exists.*/ - if (pitIsrCallbackTable[0][3]) - { - (*pitIsrCallbackTable[0][3])(); - } -} -#endif - -/*! @} */ - -/*FUNCTION********************************************************************** - * - * Function Name : PIT_DRV_InstallCallback - * Description : Register pit isr callback function. - * System default ISR interfaces are already defined in fsl_pit_irq.c. Users - * can either edit these ISRs or use this function to register a callback - * function. The default ISR will run the callback function it there is one - * installed here. - - *END**************************************************************************/ -void PIT_DRV_InstallCallback(uint32_t instance, uint32_t channel, pit_isr_callback_t function) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - assert(function != NULL); - - pitIsrCallbackTable[instance][channel] = function; -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h deleted file mode 100644 index ac41fc56705..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h +++ /dev/null @@ -1,220 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_ADC_FEATURES_H__) -#define __FSL_ADC_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ - defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ - defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ - defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \ - defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ - defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ - defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ - defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ - defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \ - defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ - defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || \ - defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) - /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ - #define FSL_FEATURE_ADC_HAS_PGA (0) - /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ - #define FSL_FEATURE_ADC_HAS_DMA (1) - /* @brief Has differential mode (bitfield SC1x[DIFF]). */ - #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1) - /* @brief Has FIFO (bit SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_HAS_FIFO (0) - /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_FIFO_SIZE (0) - /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ - #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) - /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ - #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) - /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ - #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) - /* @brief Has HW averaging (bit SC3[AVGE]). */ - #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) - /* @brief Has offset correction (register OFS). */ - #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) - /* @brief Maximum ADC resolution. */ - #define FSL_FEATURE_ADC_MAX_RESOLUTION (16) - /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ - #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) -#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) - /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ - #define FSL_FEATURE_ADC_HAS_PGA (0) - /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ - #define FSL_FEATURE_ADC_HAS_DMA (1) - /* @brief Has differential mode (bitfield SC1x[DIFF]). */ - #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0) - /* @brief Has FIFO (bit SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_HAS_FIFO (0) - /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_FIFO_SIZE (0) - /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ - #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) - /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ - #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) - /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ - #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) - /* @brief Has HW averaging (bit SC3[AVGE]). */ - #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) - /* @brief Has offset correction (register OFS). */ - #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) - /* @brief Maximum ADC resolution. */ - #define FSL_FEATURE_ADC_MAX_RESOLUTION (16) - /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ - #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ - #define FSL_FEATURE_ADC_HAS_PGA (1) - /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ - #define FSL_FEATURE_ADC_HAS_DMA (1) - /* @brief Has differential mode (bitfield SC1x[DIFF]). */ - #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1) - /* @brief Has FIFO (bit SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_HAS_FIFO (0) - /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_FIFO_SIZE (0) - /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ - #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) - /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ - #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) - /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ - #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) - /* @brief Has HW averaging (bit SC3[AVGE]). */ - #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) - /* @brief Has offset correction (register OFS). */ - #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) - /* @brief Maximum ADC resolution. */ - #define FSL_FEATURE_ADC_MAX_RESOLUTION (16) - /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ - #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ - #define FSL_FEATURE_ADC_HAS_PGA (0) - /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ - #define FSL_FEATURE_ADC_HAS_DMA (0) - /* @brief Has differential mode (bitfield SC1x[DIFF]). */ - #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0) - /* @brief Has FIFO (bit SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_HAS_FIFO (0) - /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_FIFO_SIZE (0) - /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ - #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) - /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ - #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) - /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ - #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) - /* @brief Has HW averaging (bit SC3[AVGE]). */ - #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) - /* @brief Has offset correction (register OFS). */ - #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) - /* @brief Maximum ADC resolution. */ - #define FSL_FEATURE_ADC_MAX_RESOLUTION (12) - /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ - #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) - /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ - #define FSL_FEATURE_ADC_HAS_PGA (0) - /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ - #define FSL_FEATURE_ADC_HAS_DMA (1) - /* @brief Has differential mode (bitfield SC1x[DIFF]). */ - #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0) - /* @brief Has FIFO (bit SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_HAS_FIFO (0) - /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ - #define FSL_FEATURE_ADC_FIFO_SIZE (0) - /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ - #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1) - /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ - #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0) - /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ - #define FSL_FEATURE_ADC_HAS_CALIBRATION (1) - /* @brief Has HW averaging (bit SC3[AVGE]). */ - #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1) - /* @brief Has offset correction (register OFS). */ - #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1) - /* @brief Maximum ADC resolution. */ - #define FSL_FEATURE_ADC_MAX_RESOLUTION (12) - /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ - #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_ADC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c deleted file mode 100644 index d41a71e7809..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc_hal.h" - -/*FUNCTION********************************************************************* - * - * Function Name : ADC_HAL_Init - * Description :Reset all the registers into a known state for ADC - * module. This known state is the default value indicated by the Reference - * manual. It is strongly recommended to call this API before any operations - * when initializing the ADC module. Note registers for calibration would not - * be cleared in this function. - * - *END*************************************************************************/ -void ADC_HAL_Init(uint32_t baseAddr) -{ - HW_ADC_CFG1_WR(baseAddr, 0U); - HW_ADC_CFG2_WR(baseAddr, 0U); - HW_ADC_CV1_WR(baseAddr, 0U); - HW_ADC_CV2_WR(baseAddr, 0U); - HW_ADC_SC2_WR(baseAddr, 0U); - HW_ADC_SC3_WR(baseAddr, 0U); -#if FSL_FEATURE_ADC_HAS_PGA - HW_ADC_PGA_WR(baseAddr, 0U); -#endif /* FSL_FEATURE_ADC_HAS_PGA */ -} - -/*FUNCTION********************************************************************* - * - * Function Name : ADC_HAL_SetHwCmpMode - * Description :Set the asserted compare range when enabling hardware - * compare function. About the selection of range mode, see to the description - * for "adc_hw_cmp_range_mode_t". - * - *END*************************************************************************/ -void ADC_HAL_SetHwCmpMode(uint32_t baseAddr, adc_hw_cmp_range_mode_t mode) -{ - switch (mode) - { - case kAdcHwCmpRangeModeOf1: - ADC_HAL_SetHwCmpGreaterCmd(baseAddr, false); - ADC_HAL_SetHwCmpRangeCmd(baseAddr, false); - break; - case kAdcHwCmpRangeModeOf2: - ADC_HAL_SetHwCmpGreaterCmd(baseAddr, true); - ADC_HAL_SetHwCmpRangeCmd(baseAddr, false); - break; - case kAdcHwCmpRangeModeOf3: - ADC_HAL_SetHwCmpGreaterCmd(baseAddr, false); - ADC_HAL_SetHwCmpRangeCmd(baseAddr, true); - break; - case kAdcHwCmpRangeModeOf4: - ADC_HAL_SetHwCmpGreaterCmd(baseAddr, true); - ADC_HAL_SetHwCmpRangeCmd(baseAddr, true); - break; - default: - break; - } -} - -#if FSL_FEATURE_ADC_HAS_CALIBRATION - -/*FUNCTION********************************************************************* - * - * Function Name : ADC_HAL_GetAutoPlusSideGainValue - * Description : Get the values of CLP0 - CLP4 and CLPS internally, - * accumulate them, and return the value that can be used to be set in PG - * register directly. Note that this API should be called after the process of - * auto calibration has been done. - * - *END*************************************************************************/ -uint16_t ADC_HAL_GetAutoPlusSideGainValue(uint32_t baseAddr) -{ - uint16_t cal_var; - - /* Calculate plus-side calibration */ - cal_var = 0U; - cal_var += BR_ADC_CLP0_CLP0(baseAddr); - cal_var += BR_ADC_CLP1_CLP1(baseAddr); - cal_var += BR_ADC_CLP2_CLP2(baseAddr); - cal_var += BR_ADC_CLP3_CLP3(baseAddr); - cal_var += BR_ADC_CLP4_CLP4(baseAddr); - cal_var += BR_ADC_CLPS_CLPS(baseAddr); - cal_var = 0x8000U | (cal_var>>1U); - - return cal_var; -} - -#if FSL_FEATURE_ADC_HAS_DIFF_MODE - -/*FUNCTION********************************************************************* - * - * Function Name : ADC_HAL_GetAutoMinusSideGainValue - * Description : Get the values of CLM0 - CLM4 and CLMS internally, - * accumulate them, and return the value that can be used to be set in MG - * register directly. Note that this API should be called after the process of - * auto calibration has been done. - * - *END*************************************************************************/ -uint16_t ADC_HAL_GetAutoMinusSideGainValue(uint32_t baseAddr) -{ - uint16_t cal_var; - - /* Calculate minus-side calibration */ - cal_var = 0U; - cal_var += BR_ADC_CLM0_CLM0(baseAddr); - cal_var += BR_ADC_CLM1_CLM1(baseAddr); - cal_var += BR_ADC_CLM2_CLM2(baseAddr); - cal_var += BR_ADC_CLM3_CLM3(baseAddr); - cal_var += BR_ADC_CLM4_CLM4(baseAddr); - cal_var += BR_ADC_CLMS_CLMS(baseAddr); - cal_var = 0x8000U | (cal_var>>1U); - - return cal_var; -} - -#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */ - -#endif /* FSL_FEATURE_ADC_HAS_CALIBRATION */ - -/****************************************************************************** - * EOF - *****************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h deleted file mode 100644 index 45b72df1f30..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h +++ /dev/null @@ -1,906 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_ADC_HAL_H__ -#define __FSL_ADC_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_adc_features.h" - -/*! - * @addtogroup adc_hal - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! - * @brief ADC status return codes. - */ -typedef enum _adc_status -{ - kStatus_ADC_Success = 0U, /*!< Success. */ - kStatus_ADC_InvalidArgument = 1U, /*!< Invalid argument existed. */ - kStatus_ADC_Failed = 2U /*!< Execution failed. */ -} adc_status_t; - -#if FSL_FEATURE_ADC_HAS_MUX_SELECT - -/*! - * @brief Defines the type of the enumerating channel multiplexer mode for each channel. - * - * For some ADC channels, there are two selections for the channel multiplexer. For - * example, ADC0_SE4a and ADC0_SE4b are the different channels but share the same - * channel number. - */ -typedef enum _adc_chn_mux_mode -{ - kAdcChnMuxOfA = 0U, /*!< For channel with channel mux a. */ - kAdcChnMuxOfB = 1U, /*!< For channel with channel mux b. */ - kAdcChnMuxOfDefault = kAdcChnMuxOfA /*!< For channel without any channel mux identifier. */ -} adc_chn_mux_mode_t; -#endif /* FSL_FEATURE_ADC_HAS_MUX_SELECT */ - -/*! - * @brief Defines the type of the enumerating divider for the converter. - */ -typedef enum _adc_clk_divider_mode -{ - kAdcClkDividerInputOf1 = 0U, /*!< For divider 1 from the input clock to ADC. */ - kAdcClkDividerInputOf2 = 1U, /*!< For divider 2 from the input clock to ADC. */ - kAdcClkDividerInputOf4 = 2U, /*!< For divider 4 from the input clock to ADC. */ - kAdcClkDividerInputOf8 = 3U /*!< For divider 8 from the input clock to ADC. */ -} adc_clk_divider_mode_t; - -/*! - *@brief Defines the type of the enumerating resolution for the converter. - */ -typedef enum _adc_resolution_mode -{ - kAdcResolutionBitOf8or9 = 0U, - /*!< 8-bit for single end sample, or 9-bit for differential sample. */ - kAdcResolutionBitOfSingleEndAs8 = kAdcResolutionBitOf8or9, /*!< 8-bit for single end sample. */ - kAdcResolutionBitOfDiffModeAs9 = kAdcResolutionBitOf8or9, /*!< 9-bit for differential sample. */ - - kAdcResolutionBitOf12or13 = 1U, - /*!< 12-bit for single end sample, or 13-bit for differential sample. */ - kAdcResolutionBitOfSingleEndAs12 = kAdcResolutionBitOf12or13, /*!< 12-bit for single end sample. */ - kAdcResolutionBitOfDiffModeAs13 = kAdcResolutionBitOf12or13, /*!< 13-bit for differential sample. */ - - kAdcResolutionBitOf10or11 = 2U, - /*!< 10-bit for single end sample, or 11-bit for differential sample. */ - kAdcResolutionBitOfSingleEndAs10 = kAdcResolutionBitOf10or11, /*!< 10-bit for single end sample. */ - kAdcResolutionBitOfDiffModeAs11 = kAdcResolutionBitOf10or11 /*!< 11-bit for differential sample. */ -#if (FSL_FEATURE_ADC_MAX_RESOLUTION>=16) - , kAdcResolutionBitOf16 = 3U, - /*!< 16-bit for both single end sample and differential sample. */ - kAdcResolutionBitOfSingleEndAs16 = kAdcResolutionBitOf16, /*!< 16-bit for single end sample. */ - kAdcResolutionBitOfDiffModeAs16 = kAdcResolutionBitOf16 /*!< 16-bit for differential sample. */ - -#endif /* FSL_FEATURE_ADC_MAX_RESOLUTION */ -} adc_resolution_mode_t; - -/*! - * @brief Defines the type of the enumerating source of the input clock. - */ -typedef enum _adc_clk_src_mode -{ - kAdcClkSrcOfBusClk = 0U, /*!< For input as bus clock. */ - kAdcClkSrcOfBusOrAltClk2 = 1U, /*!< For input as bus clock /2 or AltClk2. */ - kAdcClkSrcOfAltClk = 2U, /*!< For input as alternate clock (ALTCLK). */ - kAdcClkSrcOfAsynClk = 3U /*!< For input as asynchronous clock (ADACK). */ -} adc_clk_src_mode_t; - -/* - * @brief Defines the type of the enumerating long sample cycles. - */ -typedef enum _adc_long_sample_cycle_mode -{ - kAdcLongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ - kAdcLongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ - kAdcLongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ - kAdcLongSampleCycleOf4 = 3U /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ -} adc_long_sample_cycle_mode_t; - -/* - * @brief Defines the type of the enumerating reference voltage source. - */ -typedef enum _adc_ref_volt_src_mode -{ - kAdcRefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ - kAdcRefVoltSrcOfValt = 1U /*!< For alternate reference pair of ValtH and ValtL.*/ -} adc_ref_volt_src_mode_t; - -#if FSL_FEATURE_ADC_HAS_HW_AVERAGE - -/* - * @brief Defines the type of the enumerating hardware average mode. - */ -typedef enum _adc_hw_average_count_mode -{ - kAdcHwAverageCountOf4 = 0U, /*!< For hardware average with 4 samples. */ - kAdcHwAverageCountOf8 = 1U, /*!< For hardware average with 8 samples. */ - kAdcHwAverageCountOf16 = 2U, /*!< For hardware average with 16 samples. */ - kAdcHwAverageCountOf32 = 3U /*!< For hardware average with 32 samples. */ -} adc_hw_average_count_mode_t; - -#endif /* FSL_FEATURE_ADC_HAS_HW_AVERAGE */ - -/*! - * @brief Defines the type of the enumerating asserted range in the hardware compare. - * - * When the internal CMP is enabled, the COCO flag, which represents the complement - * of the conversion, is not asserted if the sample value is not in the indicated - * range. Eventually, the data of conversion result is not kept in the result - * data register. The two values, cmpValue1 and cmpValue2, mark - * the thresholds with the comparator feature. - * kAdcHwCmpRangeModeOf1: - * Both greater than and in range switchers are disabled. - * The available range is "< cmpValue1". - * kAdcHwCmpRangeModeOf2: - * Greater than switcher is enabled while the in range switcher is disabled. - * The available range is " > cmpValue1". - * kAdcHwCmpRangeModeOf3: - * Greater than switcher is disabled while in range switcher is enabled. - * The available range is "< cmpValue1" or "> cmpValue2" when - * cmpValue1 <= cmpValue2, or "< cmpValue1" and "> cmpValue2" when - * cmpValue1 >= cmpValue2. - * kAdcHwCmpRangeModeOf4: - * Both greater than and in range switchers are enabled. - * The available range is "> cmpValue1" and "< cmpValue2" when - * cmpValue1 <= cmpValue2, or "> cmpValue1" or "< cmpValue2" when - * cmpValue1 < cmpValue2. - */ -typedef enum _adc_hw_cmp_range_mode -{ - kAdcHwCmpRangeModeOf1 = 0U, /*!< For selection mode 1. */ - kAdcHwCmpRangeModeOf2 = 1U, /*!< For selection mode 2. */ - kAdcHwCmpRangeModeOf3 = 2U, /*!< For selection mode 3. */ - kAdcHwCmpRangeModeOf4 = 3U /*!< For selection mode 4. */ -} adc_hw_cmp_range_mode_t; - -#if FSL_FEATURE_ADC_HAS_PGA - -/*! - * @brief Defines the type of enumerating PGA's Gain mode. - */ -typedef enum _adc_pga_gain_mode -{ - kAdcPgaGainValueOf1 = 0U, /*!< For amplifier gain of 1.*/ - kAdcPgaGainValueOf2 = 1U, /*!< For amplifier gain of 2.*/ - kAdcPgaGainValueOf4 = 2U, /*!< For amplifier gain of 4.*/ - kAdcPgaGainValueOf8 = 3U, /*!< For amplifier gain of 8.*/ - kAdcPgaGainValueOf16 = 4U, /*!< For amplifier gain of 16.*/ - kAdcPgaGainValueOf32 = 5U, /*!< For amplifier gain of 32.*/ - kAdcPgaGainValueOf64 = 6U /*!< For amplifier gain of 64.*/ -} adc_pga_gain_mode_t; - -#endif /* FSL_FEATURE_ADC_HAS_PGA */ - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - - -/*! - * @brief Resets all registers into a known state for the ADC module. - * - * This function resets all registers into a known state for the ADC - * module. This known state is the reset value indicated by the Reference - * manual. It is strongly recommended to call this API before any other operation - * when initializing the ADC module. - * - * @param baseAddr Register base address for the module. - */ -void ADC_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Configures the conversion channel for the ADC module. - * - * This function configures the channel for the ADC module. At any point, - * only one of the configuration groups takes effect. The other channel mux of - * the first group (group A, 0) is only for the hardware trigger. Both software and - * hardware trigger can be used to the first group. When in software trigger - * mode, once the available channel is set, the conversion begins to execute. - * - * @param baseAddr Register base address for the module. - * @param chnGroup Channel configuration group ID. - * @param intEnable Switcher to enable interrupt when conversion is completed. - * @param diffEnable Switcher to enable differential channel mode. - * @param chnNum ADC channel for next conversion. - */ -static inline void ADC_HAL_ConfigChn(uint32_t baseAddr, uint32_t chnGroup, - bool intEnable, bool diffEnable, uint8_t chnNum) -{ - assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); - -#if FSL_FEATURE_ADC_HAS_DIFF_MODE - HW_ADC_SC1n_WR(baseAddr, chnGroup, \ - ( (intEnable ? BM_ADC_SC1n_AIEN : 0U) \ - | ( (diffEnable)? BM_ADC_SC1n_DIFF : 0U) \ - | BF_ADC_SC1n_ADCH(chnNum) \ - ) ); -#else - HW_ADC_SC1n_WR(baseAddr, chnGroup, \ - ( (intEnable ? BM_ADC_SC1n_AIEN : 0U) \ - | BF_ADC_SC1n_ADCH(chnNum) \ - ) ); - -#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */ - -} - -#if FSL_FEATURE_ADC_HAS_DIFF_MODE - -/*! - * @brief Checks whether the channel differential mode is enabled. - * - * This function checks whether the channel differential mode for - * is enabled. - * - * @param baseAddr Register base address for the module. - * @param chnGroup Channel configuration group ID. - * @return Assertion of enabling differential mode. - */ -static inline bool ADC_HAL_GetChnDiffCmd(uint32_t baseAddr, uint32_t chnGroup) -{ - assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); - return (1U == BR_ADC_SC1n_DIFF(baseAddr, chnGroup)); -} -#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */ - -/*! - * @brief Checks whether the channel conversion is completed. - * - * This function checks whether the channel conversion for the ADC - * module is completed. - * - * @param baseAddr Register base address for the module. - * @param chnGroup Channel configuration group ID. - * @return Assertion of completed conversion mode. - */ -static inline bool ADC_HAL_GetChnConvCompletedCmd(uint32_t baseAddr, uint32_t chnGroup) -{ - assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); - return (1U == BR_ADC_SC1n_COCO(baseAddr, chnGroup) ); -} - -/*! - * @brief Switches to enable the low power mode for ADC module. - * - * This function switches to enable the low power mode for ADC module. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetLowPowerCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_CFG1_ADLPC(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Selects the clock divider mode for the ADC module. - * - * This function selects the clock divider mode for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode enumeration. See to "adc_clk_divider_mode_t". - */ -static inline void ADC_HAL_SetClkDividerMode(uint32_t baseAddr, adc_clk_divider_mode_t mode) -{ - BW_ADC_CFG1_ADIV(baseAddr, (uint32_t)mode ); -} - -/*! - * @brief Switches to enable the long sample mode for the ADC module. - * - * This function switches to enable the long sample mode for the ADC module. - * This function adjusts the sample period to allow the higher impedance inputs to - * be accurately sampled or to maximize the conversion speed for the lower impedance - * inputs. Longer sample times can also be used to lower overall power - * consumption if the continuous conversions are enabled and the high conversion rates - * are not required. If the long sample mode is enabled, more configuration - * is set by calling the "ADC_HAL_SetLongSampleCycleMode()" function. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetLongSampleCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_CFG1_ADLSMP(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Selects the conversion resolution mode for ADC module. - * - * This function selects the conversion resolution mode for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode enumeration. See to "adc_resolution_mode_t". - */ -static inline void ADC_HAL_SetResolutionMode(uint32_t baseAddr, adc_resolution_mode_t mode) -{ - BW_ADC_CFG1_MODE(baseAddr, (uint32_t)mode ); -} - -/*! - * @brief Gets the conversion resolution mode for ADC module. - * - * This function gets the conversion resolution mode for the ADC module. - * It is specially used when processing the conversion result of RAW format. - * - * @param baseAddr Register base address for the module. - * @return Current conversion resolution mode. - */ -static inline adc_resolution_mode_t ADC_HAL_GetResolutionMode(uint32_t baseAddr) -{ - return (adc_resolution_mode_t)( BR_ADC_CFG1_MODE(baseAddr) ); -} - -/*! - * @brief Selects the input clock source for the ADC module. - * - * This function selects the input clock source for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode enumeration. See to "adc_clk_src_mode_t". - */ -static inline void ADC_HAL_SetClkSrcMode(uint32_t baseAddr, adc_clk_src_mode_t mode) -{ - BW_ADC_CFG1_ADICLK(baseAddr, (uint32_t)mode ); -} - -#if FSL_FEATURE_ADC_HAS_MUX_SELECT - -/*! - * @brief Selects the channel mux mode for the ADC module. - * - * This function selects the channel mux mode for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode enumeration. See to "adc_chn_mux_mode_t". - */ -static inline void ADC_HAL_SetChnMuxMode(uint32_t baseAddr, adc_chn_mux_mode_t mode) -{ - BW_ADC_CFG2_MUXSEL(baseAddr, ((kAdcChnMuxOfA == mode) ? 0U : 1U) ); -} - -/*! - * @brief Gets the current channel mux mode for the ADC module. - * - * This function selects the channel mux mode for the ADC module. - * - * @param baseAddr Register base address for the module. - * @return Selection of mode enumeration. See to "adc_chn_mux_mode_t". - */ -static inline adc_chn_mux_mode_t ADC_HAL_GetChnMuxMode(uint32_t baseAddr) -{ - return (adc_chn_mux_mode_t)(BR_ADC_CFG2_MUXSEL(baseAddr) ); -} - -#endif /* FSL_FEATURE_ADC_HAS_MUX_SELECT */ - -/*! - * @brief Switches to enable the asynchronous clock for the ADC module. - * - * This function switches to enable the asynchronous clock for the ADC module. - * It enables the ADC's asynchronous clock source and the clock source - * output regardless of the conversion and the input clock select status of the - * ADC. Asserting this function allows the clock to be used even while the ADC - * is idle or operating from a different clock source. Also, latency of - * initiating a single or first-continuous conversion with the asynchronous - * clock selected is reduced since the ADC internal clock has been already - * operational. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetAsyncClkCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_CFG2_ADACKEN(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Switches to enable the high speed mode for the ADC module. - * - * This function switches to enable the high speed mode for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetHighSpeedCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_CFG2_ADHSC(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Selects the long sample cycle mode for the ADC module. - * - * This function selects the long sample cycle mode for the ADC module. - * This function should be called along with "ADC_HAL_SetLongSampleCmd()". - * - * @param baseAddr Register base address for the module. - * @param mode Selection of long sample cycle mode. See the "adc_long_sample_cycle_mode_t". - */ -static inline void ADC_HAL_SetLongSampleCycleMode(uint32_t baseAddr, - adc_long_sample_cycle_mode_t mode) -{ - BW_ADC_CFG2_ADLSTS(baseAddr, (uint32_t)mode ); -} - -/*! - * @brief Gets the raw result data of channel conversion for the ADC module. - * - * This function gets the result data of conversion for the ADC module. - * The return value is raw data that is not processed. The unavailable bits would be - * filled with "0" in single-ended mode and sign bit in differential mode. - * - * @param baseAddr Register base address for the module. - * @param chnGroup Channel configuration group ID. - * @return Conversion value of RAW. - */ -static inline uint16_t ADC_HAL_GetChnConvValueRAW(uint32_t baseAddr, - uint32_t chnGroup ) -{ - assert(chnGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); - return (uint16_t)(BR_ADC_Rn_D(baseAddr, chnGroup) ); -} - -/*! - * @brief Sets the compare value of the lower limitation for the ADC module. - * - * This function sets the compare value of the lower limitation for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param value Setting value. - */ -static inline void ADC_HAL_SetHwCmpValue1(uint32_t baseAddr, uint16_t value) -{ - BW_ADC_CV1_CV(baseAddr,value); -} - -/*! - * @brief Sets the compare value of the higher limitation for the ADC module. - * - * This function sets the compare value of the higher limitation for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param value Setting value. - */ -static inline void ADC_HAL_SetHwCmpValue2(uint32_t baseAddr, uint16_t value) -{ - BW_ADC_CV2_CV(baseAddr,value); -} - -/*! - * @brief Checks whether the converter is active for the ADC module. - * - * This function checks whether the converter is active for the ADC - * module. If it is dis-asserted when the conversion is completed, one of the - * completed flag is asserted for the indicated group mux. See the - * "ADC_HAL_GetChnConvCompletedCmd()". - * - * @param baseAddr Register base address for the module. - * @return Assertion of that the converter is active. - */ -static inline bool ADC_HAL_GetConvActiveCmd(uint32_t baseAddr) -{ - return (1U == BR_ADC_SC2_ADACT(baseAddr) ); -} - -/*! - * @brief Switches to enable the hardware trigger mode for the ADC module. - * - * This function switches to enable the hardware trigger mode for the ADC - * module. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetHwTriggerCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC2_ADTRG(baseAddr,(enable ? 1U : 0U) ); -} - -/*! - * @brief Switches to enable the hardware comparator for the ADC module. - * - * This function switches to enable the hardware comparator for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetHwCmpCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC2_ACFE(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Switches to enable the setting that is greater than the hardware comparator. - * - * This function switches to enable the setting that is greater than the - * hardware comparator. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetHwCmpGreaterCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC2_ACFGT(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Switches to enable the setting of the range for hardware comparator. - * - * This function switches to enable the setting of range for the hardware - * comparator. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetHwCmpRangeCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC2_ACREN(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Configures the asserted range of the hardware comparator for the ADC module. - * - * This function configures the asserted range of the hardware comparator for the - * ADC module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of range mode, see to "adc_hw_cmp_range_mode_t". - */ -void ADC_HAL_SetHwCmpMode(uint32_t baseAddr, adc_hw_cmp_range_mode_t mode); - -#if FSL_FEATURE_ADC_HAS_DMA - -/*! - * @brief Switches to enable the DMA for the ADC module. - * - * This function switches to enable the DMA for the ADC module. When enabled, the - * DMA request is asserted during the ADC conversion complete event, which is noted - * by the assertion of any of the ADC channel completed flags. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetDmaCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC2_DMAEN(baseAddr, (enable ? 1U : 0U) ); -} - -#endif /* FSL_FEATURE_ADC_HAS_DMA */ - -/*! - * @brief Selects the reference voltage source for the ADC module. - * - * This function selects the reference voltage source for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of asserted the feature. - */ -static inline void ADC_HAL_SetRefVoltSrcMode(uint32_t baseAddr, adc_ref_volt_src_mode_t mode) -{ - BW_ADC_SC2_REFSEL(baseAddr, (uint32_t)mode ); -} - -#if FSL_FEATURE_ADC_HAS_CALIBRATION - -/*! - * @brief Switches to enable the hardware calibration for the ADC module. - * - * This function launches the hardware calibration for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetAutoCalibrationCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC3_CAL(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Gets the hardware calibration status for the ADC module. - * - * This function gets the status whether the hardware calibration is active - * for the ADC module. The return value holds on as asserted during the hardware - * calibration. Then, it is cleared and dis-asserted after the - * calibration. - * - * @param baseAddr Register base address for the module. - */ -static inline bool ADC_HAL_GetAutoCalibrationActiveCmd(uint32_t baseAddr) -{ - return (1U == BR_ADC_SC3_CAL(baseAddr) ); -} - -/*! - * @brief Gets the hardware calibration status for the ADC module. - * - * This function gets the status whether the hardware calibration has failed - * for the ADC module. The return value is asserted if there is anything wrong - * with the hardware calibration. - * - * @param baseAddr Register base address for the module. - */ -static inline bool ADC_HAL_GetAutoCalibrationFailedCmd(uint32_t baseAddr) -{ - return (1U == BR_ADC_SC3_CALF(baseAddr) ); -} - -/*! - * @brief Gets and calculates the plus side calibration parameter from the auto calibration. - * - * This function gets the values of CLP0 - CLP4 and CLPS internally, - * accumulates them, and returns the value that can be used to be set in the PG - * register directly. Note that this API should be called after the process of - * auto calibration is complete. - * - * @param baseAddr Register base address for the module. - * @return value that can be set into PG directly. - */ -uint16_t ADC_HAL_GetAutoPlusSideGainValue(uint32_t baseAddr); - -/*! - * @brief Sets the plus side gain calibration value for the ADC module. - * - * This function sets the plus side gain calibration value for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param value Setting value for plus side gain. - */ -static inline void ADC_HAL_SetPlusSideGainValue(uint32_t baseAddr, uint16_t value) -{ - BW_ADC_PG_PG(baseAddr, value); -} - -#if FSL_FEATURE_ADC_HAS_DIFF_MODE - -/*! - * @brief Gets and calculates the minus side calibration parameter from the auto calibration. - * - * This function gets the values of CLM0 - CLM4 and CLMS internally, - * accumulates them, and returns the value that can be used to be set in the MG - * register directly. Note that this API should be called after the process of - * auto calibration is complete. - * - * @param baseAddr Register base address for the module. - * @return value that can be set into MG directly. - */ -uint16_t ADC_HAL_GetAutoMinusSideGainValue(uint32_t baseAddr); - -/*! - * @brief Sets the minus side gain calibration value for the ADC module. - * - * This function sets the minus side gain calibration value for the ADC module. - * - * @param baseAddr Register base address for the module. - * @param value Setting value for minus side gain. - */ -static inline void ADC_HAL_SetMinusSideGainValue(uint32_t baseAddr, uint16_t value) -{ - BW_ADC_MG_MG(baseAddr, value); -} - -#endif /* FSL_FEATURE_ADC_HAS_DIFF_MODE */ - -#endif /* FSL_FEATURE_ADC_HAS_CALIBRATION */ - -#if FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION - -/*! - * @brief Gets the offset correction value for the ADC module. - * - * This function gets the offset correction value for the ADC module. - * When auto calibration is executed, the OFS register holds the new value - * generated by the calibration. It can be left as default or modified - * according to the use case. - * - * @param baseAddr Register base address for the module. - * @return current value for OFS. - */ -static inline uint16_t ADC_HAL_GetOffsetValue(uint32_t baseAddr) -{ - return (uint16_t)(BR_ADC_OFS_OFS(baseAddr) ); -} - -/*! - * @brief Sets the offset correction value for the ADC module. - * - * This function sets the offset correction value for the ADC module. The ADC - * offset correction register (OFS) contains the user-selected or calibration-generated - * offset error correction value. The value in the offset correction - * registers (OFS) is subtracted from the conversion and the result is - * transferred into the result registers (Rn). If the result is above the - * maximum or below the minimum result value, it is forced to the appropriate - * limit for the current mode of operation. - * - * @param baseAddr Register base address for the module. - * @param value Setting value for OFS. - */ -static inline void ADC_HAL_SetOffsetValue(uint32_t baseAddr, uint16_t value) -{ - BW_ADC_OFS_OFS(baseAddr, value); -} - -#endif /* FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION */ - -/*! - * @brief Switches to enable the continuous conversion mode for the ADC module. - * - * This function switches to enable the continuous conversion mode for the ADC - * module. Once enabled, continuous conversions, or sets of conversions if the - * hardware average function, is enabled after initiating a conversion. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetContinuousConvCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC3_ADCO(baseAddr, (enable ? 1U : 0U) ); -} - -#if FSL_FEATURE_ADC_HAS_HW_AVERAGE - -/*! - * @brief Switches to enable the hardware average for the ADC module. - * - * This function switches to enable the hardware average for the ADC module. - * Once enabled, the conversion does not stop before the average - * count has been reached. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted the feature. - */ -static inline void ADC_HAL_SetHwAverageCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_SC3_AVGE(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Selects the hardware average mode for the ADC module. - * - * This function switches to select the hardware average mode for the ADC - * module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of hardware average count mode, see to "adc_hw_average_count_mode_t". - */ -static inline void ADC_HAL_SetHwAverageMode(uint32_t baseAddr, adc_hw_average_count_mode_t mode) -{ - BW_ADC_SC3_AVGS(baseAddr, (uint32_t)mode ); -} - -#endif /* FSL_FEATURE_ADC_HAS_HW_AVERAGE */ - -#if FSL_FEATURE_ADC_HAS_PGA - -/*! - * @brief Switches to enable the Programmable Gain Amplifier for ADC module. - * - * This function enables the PGA for the ADC module. The Programmable Gain - * Amplifier (PGA) is designed to increase the dynamic range by amplifying the - * low-amplitude signals before they are fed to the 16 bit SAR ADC. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted feature. - */ -static inline void ADC_HAL_SetPgaCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_PGA_PGAEN(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Switches to enable the PGA chopping mode for the ADC module. - * - * This function switches to enable the PGA chopping mode for the ADC module. - * The PGA employs chopping to remove/reduce offset and 1/f noise and offers an - * offset measurement configuration that aids the offset calibration. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted feature. - */ -static inline void ADC_HAL_SetPgaChoppingCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_PGA_PGACHPb(baseAddr, (enable ? 0U : 1U) ); -} - -/*! - * @brief Switches to enable the PGA working in low power mode for the ADC module. - * - * This function switches to enable the PGA working in low power mode for - * ADC module. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted feature. - */ -static inline void ADC_HAL_SetPgaLowPowerCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_PGA_PGALPb(baseAddr, (enable ? 0U : 1U) ); -} - -/*! - * @brief Selects the amplifier mode for the PGA. - * - * This function selects the amplifier mode for the PGA. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of asserted feature. See to "adc_pga_gain_mode_t". - */ -static inline void ADC_HAL_SetPgaGainMode(uint32_t baseAddr, adc_pga_gain_mode_t mode) -{ - BW_ADC_PGA_PGAG(baseAddr, (uint32_t)mode ); -} - -/*! - * @brief Switches to enable the offset measurement mode for the ADC module. - * - * This function switches to enable the offset measurement mode for the ADC - * module. When asserted, the PGA disconnects from the external inputs and - * auto-configures into offset measurement mode. With this function asserted, - * run the ADC in recommended settings and enable maximum hardware averaging - * to get the PGA offset number. The output is the (PGA offset * (64+1)) - * for a given setting. - * - * @param baseAddr Register base address for the module. - * @param enable Switcher to asserted feature. - */ -static inline void ADC_HAL_SetPgaOffsetMeasurementCmd(uint32_t baseAddr, bool enable) -{ - BW_ADC_PGA_PGAOFSM(baseAddr, (enable ? 1U : 0U) ); -} - -#endif /* FSL_FEATURE_ADC_HAS_PGA */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_ADC_HAL_H__ */ - -/****************************************************************************** - * EOF - *****************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_features.h deleted file mode 100644 index 73bbba6ab98..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_features.h +++ /dev/null @@ -1,119 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140516 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_FLEXCAN_FEATURES_H__) -#define __FSL_FLEXCAN_FEATURES_H__ - -#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18) - /* @brief Message buffer size */ - #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) - /* @brief Has doze mode support (register bit field MCR[DOZE]). */ - #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) - /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ - #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) - /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ - #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) - /* @brief Has extended bit timing register (register CBT). */ - #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) - /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ - #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) - /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ - #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) - /* @brief Number of interrupt vectors. */ - #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Message buffer size */ - #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) - /* @brief Has doze mode support (register bit field MCR[DOZE]). */ - #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) - /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ - #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (0) - /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ - #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) - /* @brief Has extended bit timing register (register CBT). */ - #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) - /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ - #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) - /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ - #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (0) - /* @brief Number of interrupt vectors. */ - #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Message buffer size */ - #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) - /* @brief Has doze mode support (register bit field MCR[DOZE]). */ - #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) - /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ - #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) - /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ - #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) - /* @brief Has extended bit timing register (register CBT). */ - #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (1) - /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ - #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) - /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ - #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) - /* @brief Number of interrupt vectors. */ - #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) -#else - #define MBED_NO_FLEXCAN -#endif - -#endif /* __FSL_FLEXCAN_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.c deleted file mode 100644 index cf0e94d5fd0..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.c +++ /dev/null @@ -1,1845 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_flexcan_hal.h" - -#ifndef MBED_NO_FLEXCAN - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU) /*!< FlexCAN RX FIFO ID filter*/ - /*! format A extended mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format A extended shift.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format A standard mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format A standard shift.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x3FFFU) /*!< FlexCAN RX FIFO ID filter*/ - /*! format B extended mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format B extended mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format B extended mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x3FF8U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format B standard mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format B standard shift1.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format B standard shift2.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU) /*!< FlexCAN RX FIFO ID filter*/ - /*! format C mask.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format C shift1.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format C shift2.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format C shift3.*/ -#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U) /*!< FlexCAN RX FIFO ID filter*/ - /*! format C shift4.*/ -#define FLEXCAN_ALL_INT (0x0007U) /*!< Masks for wakeup, error, bus off*/ - /*! interrupts*/ -#define FLEXCAN_BYTE_DATA_FIELD_MASK (0xFFU) /*!< Masks for byte data field.*/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_Enable - * Description : Enable FlexCAN module. - * This function will enable FlexCAN module clock. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_Enable(uint32_t canBaseAddr) -{ - /* Check for low power mode*/ - if(BR_CAN_MCR_LPMACK(canBaseAddr)) - { - /* Enable clock*/ - HW_CAN_MCR_CLR(canBaseAddr, BM_CAN_MCR_MDIS); - /* Wait until enabled*/ - while (BR_CAN_MCR_LPMACK(canBaseAddr)){} - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_Disable - * Description : Disable FlexCAN module. - * This function will disable FlexCAN module clock. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_Disable(uint32_t canBaseAddr) -{ - /* To access the memory mapped registers*/ - /* Entre disable mode (hard reset).*/ - if(BR_CAN_MCR_MDIS(canBaseAddr) == 0x0) - { - /* Clock disable (module)*/ - BW_CAN_MCR_MDIS(canBaseAddr, 0x1); - - /* Wait until disable mode acknowledged*/ - while (!(BR_CAN_MCR_LPMACK(canBaseAddr))){} - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SelectClock - * Description : Select FlexCAN clock source. - * This function will select either internal bus clock or external clock as - * FlexCAN clock source. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SelectClock( - uint32_t canBaseAddr, - flexcan_clk_source_t clk) -{ - if (clk == kFlexCanClkSource_Ipbus) - { - /* Internal bus clock (fsys/2)*/ - BW_CAN_CTRL1_CLKSRC(canBaseAddr, 0x1); - } - else if (clk == kFlexCanClkSource_Osc) - { - /* External clock*/ - BW_CAN_CTRL1_CLKSRC(canBaseAddr, 0x0); - } - else - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_Init - * Description : Initialize FlexCAN module. - * This function will reset FlexCAN module, set maximum number of message - * buffers, initialize all message buffers as inactive, enable RX FIFO - * if needed, mask all mask bits, and disable all MB interrupts. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_Init(uint32_t canBaseAddr, const flexcan_user_config_t *data) -{ - uint32_t i; - volatile CAN_Type *flexcan_reg_ptr; - - assert(data); - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - /* Reset the FLEXCAN*/ - BW_CAN_MCR_SOFTRST(canBaseAddr, 0x1); - - /* Wait for reset cycle to complete*/ - while (BR_CAN_MCR_SOFTRST(canBaseAddr)){} - - /* Set Freeze, Halt*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* check for freeze Ack*/ - while ((!BR_CAN_MCR_FRZACK(canBaseAddr)) || - (!BR_CAN_MCR_NOTRDY(canBaseAddr))){} - - /* Set maximum number of message buffers*/ - BW_CAN_MCR_MAXMB(canBaseAddr, data->max_num_mb); - - /* Initialize all message buffers as inactive*/ - for (i = 0; i < data->max_num_mb; i++) - { - flexcan_reg_ptr->MB[i].CS = 0x0; - flexcan_reg_ptr->MB[i].ID = 0x0; - flexcan_reg_ptr->MB[i].WORD0 = 0x0; - flexcan_reg_ptr->MB[i].WORD1 = 0x0; - } - - /* Enable RX FIFO if need*/ - if (data->is_rx_fifo_needed) - { - /* Enable RX FIFO*/ - BW_CAN_MCR_RFEN(canBaseAddr, 0x1); - /* Set the number of the RX FIFO filters needed*/ - BW_CAN_CTRL2_RFFN(canBaseAddr, data->num_id_filters); - /* RX FIFO global mask*/ - HW_CAN_RXFGMASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RXFGMASK_FGM_MASK)); - for (i = 0; i < data->max_num_mb; i++) - { - /* RX individual mask*/ - HW_CAN_RXIMRn_WR(canBaseAddr, i, CAN_ID_EXT(CAN_RXIMR_MI_MASK)); - } - } - - /* Rx global mask*/ - HW_CAN_RXMGMASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RXMGMASK_MG_MASK)); - - /* Rx reg 14 mask*/ - HW_CAN_RX14MASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RX14MASK_RX14M_MASK)); - - /* Rx reg 15 mask*/ - HW_CAN_RX15MASK_WR(canBaseAddr, CAN_ID_EXT(CAN_RX15MASK_RX15M_MASK)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while(BR_CAN_MCR_FRZACK(canBaseAddr)){} - - /* Disable all MB interrupts*/ - HW_CAN_IMASK1_WR(canBaseAddr, 0x0); - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetTimeSegments - * Description : Set FlexCAN time segments. - * This function will set all FlexCAN time segments which define the length of - * Propagation Segment in the bit time, the length of Phase Buffer Segment 2 in - * the bit time, the length of Phase Buffer Segment 1 in the bit time, the ratio - * between the PE clock frequency and the Serial Clock (Sclock) frequency, and - * the maximum number of time quanta that a bit time can be changed by one - * resynchronization. (One time quantum is equal to the Sclock period.) - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetTimeSegments( - uint32_t canBaseAddr, - flexcan_time_segment_t *time_seg) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while(!(BR_CAN_MCR_FRZACK(canBaseAddr))) {} - - /* Set FlexCAN time segments*/ - HW_CAN_CTRL1_CLR(canBaseAddr, (CAN_CTRL1_PROPSEG_MASK | CAN_CTRL1_PSEG2_MASK | - CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PRESDIV_MASK) | - CAN_CTRL1_RJW_MASK); - HW_CAN_CTRL1_SET(canBaseAddr, (CAN_CTRL1_PROPSEG(time_seg->propseg) | - CAN_CTRL1_PSEG2(time_seg->pseg2) | - CAN_CTRL1_PSEG1(time_seg->pseg1) | - CAN_CTRL1_PRESDIV(time_seg->pre_divider) | - CAN_CTRL1_RJW(time_seg->rjw))); - - /* De-assert Freeze mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while(BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_GetTimeSegments - * Description : Get FlexCAN time segments. - * This function will get all FlexCAN time segments defined. - * - *END**************************************************************************/ -void FLEXCAN_HAL_GetTimeSegments( - uint32_t canBaseAddr, - flexcan_time_segment_t *time_seg) -{ - time_seg->pre_divider = BR_CAN_CTRL1_PRESDIV(canBaseAddr); - time_seg->propseg = BR_CAN_CTRL1_PROPSEG(canBaseAddr); - time_seg->pseg1 = BR_CAN_CTRL1_PSEG1(canBaseAddr); - time_seg->pseg2 = BR_CAN_CTRL1_PSEG2(canBaseAddr); - time_seg->rjw = BR_CAN_CTRL1_RJW(canBaseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetMbTx - * Description : Configure a message buffer for transmission. - * This function will first check if RX FIFO is enabled. If RX FIFO is enabled, - * the function will make sure if the MB requested is not occupied by RX FIFO - * and ID filter table. Then this function will copy user's buffer into the - * message buffer data area and configure the message buffer as required for - * transmission. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SetMbTx( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx, - flexcan_mb_code_status_t *cs, - uint32_t msg_id, - uint8_t *mb_data) -{ - uint32_t i; - uint32_t val1, val2 = 1, temp, temp1; - - assert(data); - - volatile CAN_Type *flexcan_reg_ptr; - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Check if RX FIFO is enabled*/ - if (BR_CAN_MCR_RFEN(canBaseAddr)) - { - /* Get the number of RX FIFO Filters*/ - val1 = (BR_CAN_CTRL2_RFFN(canBaseAddr)); - /* Get the number if MBs occupied by RX FIFO and ID filter table*/ - /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/ - /* Every number of RFFN means 8 number of RX FIFO filters*/ - /* and every 4 number of RX FIFO filters occupied one MB*/ - val2 = 6 + (val1 + 1) * 8 / 4; - - if (mb_idx <= (val2 - 1)) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - } - - /* Copy user's buffer into the message buffer data area*/ - if (mb_data != NULL) - { - flexcan_reg_ptr->MB[mb_idx].WORD0 = 0x0; - flexcan_reg_ptr->MB[mb_idx].WORD1 = 0x0; - - for (i = 0; i < cs->data_length; i++ ) - { - temp1 = (*(mb_data + i)); - if (i < 4) - { - temp = temp1 << ((3 - i) * 8); - flexcan_reg_ptr->MB[mb_idx].WORD0 |= temp; - } - else - { - temp = temp1 << ((7 - i) * 8); - flexcan_reg_ptr->MB[mb_idx].WORD1 |= temp; - } - } - } - - /* Set the ID according the format structure*/ - if (cs->msg_id_type == kFlexCanMbId_Ext) - { - /* ID [28-0]*/ - flexcan_reg_ptr->MB[mb_idx].ID &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK); - flexcan_reg_ptr->MB[mb_idx].ID |= (msg_id & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK)); - - /* Set IDE*/ - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_IDE_MASK; - - /* Clear SRR bit*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_SRR_MASK; - - /* Set the length of data in bytes*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK; - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_DLC(cs->data_length); - - /* Set MB CODE*/ - /* Reset the code*/ - if (cs->code != kFlexCanTX_NotUsed) - { - if (cs->code == kFlexCanTX_Remote) - { - /* Set RTR bit*/ - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_RTR_MASK; - cs->code = kFlexCanTX_Data; - } - - /* Reset the code*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~(CAN_CS_CODE_MASK); - - /* Activating message buffer*/ - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code); - } - } - else if(cs->msg_id_type == kFlexCanMbId_Std) - { - /* ID[28-18]*/ - flexcan_reg_ptr->MB[mb_idx].ID &= ~CAN_ID_STD_MASK; - flexcan_reg_ptr->MB[mb_idx].ID |= CAN_ID_STD(msg_id); - - /* make sure IDE and SRR are not set*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK); - - /* Set the length of data in bytes*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK; - flexcan_reg_ptr->MB[mb_idx].CS |= (cs->data_length) << CAN_CS_DLC_SHIFT; - - /* Set MB CODE*/ - if (cs->code != kFlexCanTX_NotUsed) - { - if (cs->code == kFlexCanTX_Remote) - { - /* Set RTR bit*/ - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_RTR_MASK; - cs->code = kFlexCanTX_Data; - } - - /* Reset the code*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_CODE_MASK; - - /* Set the code*/ - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code); - } - } - else - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetMbRx - * Description : Configure a message buffer for receiving. - * This function will first check if RX FIFO is enabled. If RX FIFO is enabled, - * the function will make sure if the MB requested is not occupied by RX FIFO - * and ID filter table. Then this function will configure the message buffer as - * required for receiving. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SetMbRx( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx, - flexcan_mb_code_status_t *cs, - uint32_t msg_id) -{ - uint32_t val1, val2 = 1; - - assert(data); - - volatile CAN_Type *flexcan_reg_ptr; - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Check if RX FIFO is enabled*/ - if (BR_CAN_MCR_RFEN(canBaseAddr)) - { - /* Get the number of RX FIFO Filters*/ - val1 = BR_CAN_CTRL2_RFFN(canBaseAddr); - /* Get the number if MBs occupied by RX FIFO and ID filter table*/ - /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/ - /* Every number of RFFN means 8 number of RX FIFO filters*/ - /* and every 4 number of RX FIFO filters occupied one MB*/ - val2 = 6 + (val1 + 1) * 8 / 4; - - if (mb_idx <= (val2 - 1)) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - } - - /* Set the ID according the format structure*/ - if (cs->msg_id_type == kFlexCanMbId_Ext) - { - /* Set IDE*/ - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_IDE_MASK; - - /* Clear SRR bit*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_SRR_MASK; - - /* Set the length of data in bytes*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK; - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_DLC(cs->data_length); - - /* ID [28-0]*/ - flexcan_reg_ptr->MB[mb_idx].ID &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK); - flexcan_reg_ptr->MB[mb_idx].ID |= (msg_id & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK)); - - /* Set MB CODE*/ - if (cs->code != kFlexCanRX_NotUsed) - { - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_CODE_MASK; - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code); - } - } - else if(cs->msg_id_type == kFlexCanMbId_Std) - { - /* Make sure IDE and SRR are not set*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK); - - /* Set the length of data in bytes*/ - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_DLC_MASK; - flexcan_reg_ptr->MB[mb_idx].CS |= (cs->data_length) << CAN_CS_DLC_SHIFT; - - /* ID[28-18]*/ - flexcan_reg_ptr->MB[mb_idx].ID &= ~CAN_ID_STD_MASK; - flexcan_reg_ptr->MB[mb_idx].ID |= CAN_ID_STD(msg_id); - - /* Set MB CODE*/ - if (cs->code != kFlexCanRX_NotUsed) - { - flexcan_reg_ptr->MB[mb_idx].CS &= ~CAN_CS_CODE_MASK; - flexcan_reg_ptr->MB[mb_idx].CS |= CAN_CS_CODE(cs->code); - } - } - else - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_GetMb - * Description : Get a message buffer field values. - * This function will first check if RX FIFO is enabled. If RX FIFO is enabled, - * the function will make sure if the MB requested is not occupied by RX FIFO - * and ID filter table. Then this function will get the message buffer field - * values and copy the MB data field into user's buffer. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_GetMb( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx, - flexcan_mb_t *mb) -{ - uint32_t i; - uint32_t val1, val2 = 1; - volatile CAN_Type *flexcan_reg_ptr; - - assert(data); - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Check if RX FIFO is enabled*/ - if (BR_CAN_MCR_RFEN(canBaseAddr)) - { - /* Get the number of RX FIFO Filters*/ - val1 = BR_CAN_CTRL2_RFFN(canBaseAddr); - /* Get the number if MBs occupied by RX FIFO and ID filter table*/ - /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/ - /* Every number of RFFN means 8 number of RX FIFO filters*/ - /* and every 4 number of RX FIFO filters occupied one MB*/ - val2 = 6 + (val1 + 1) * 8 / 4; - - if (mb_idx <= (val2 - 1)) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - } - - /* Get a MB field values*/ - mb->cs = flexcan_reg_ptr->MB[mb_idx].CS; - if ((mb->cs) & CAN_CS_IDE_MASK) - { - mb->msg_id = flexcan_reg_ptr->MB[mb_idx].ID; - } - else - { - mb->msg_id = (flexcan_reg_ptr->MB[mb_idx].ID) >> CAN_ID_STD_SHIFT; - } - - /* Copy MB data field into user's buffer*/ - for (i = 0 ; i < kFlexCanMessageSize ; i++) - { - if (i < 4) - { - mb->data[3 - i] = ((flexcan_reg_ptr->MB[mb_idx].WORD0) >> (i * 8)) & - FLEXCAN_BYTE_DATA_FIELD_MASK; - } - else - { - mb->data[11 - i] = ((flexcan_reg_ptr->MB[mb_idx].WORD1) >> ((i - 4) * 8)) & - FLEXCAN_BYTE_DATA_FIELD_MASK; - } - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_LockRxMb - * Description : Lock the RX message buffer. - * This function will the RX message buffer. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_LockRxMb( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx) -{ - assert(data); - - volatile CAN_Type *flexcan_reg_ptr; - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Lock the mailbox*/ - flexcan_reg_ptr->MB[mb_idx].CS; - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableRxFifo - * Description : Enable Rx FIFO feature. - * This function will enable the Rx FIFO feature. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnableRxFifo(uint32_t canBaseAddr) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* Enable RX FIFO*/ - BW_CAN_MCR_RFEN(canBaseAddr, 0x1); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableRxFifo - * Description : Disable Rx FIFO feature. - * This function will disable the Rx FIFO feature. - * - *END**************************************************************************/ -void FLEXCAN_HAL_DisableRxFifo(uint32_t canBaseAddr) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while(!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* Disable RX FIFO*/ - BW_CAN_MCR_RFEN(canBaseAddr, 0x0); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxFifoFiltersNumber - * Description : Set the number of Rx FIFO filters. - * This function will define the number of Rx FIFO filters. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxFifoFiltersNumber( - uint32_t canBaseAddr, - uint32_t number) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while(!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* Set the number of RX FIFO ID filters*/ - BW_CAN_CTRL2_RFFN(canBaseAddr, number); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetMaxMbNumber - * Description : Set the number of the last Message Buffers. - * This function will define the number of the last Message Buffers - * -*END**************************************************************************/ -void FLEXCAN_HAL_SetMaxMbNumber( - uint32_t canBaseAddr, - const flexcan_user_config_t *data) -{ - assert(data); - - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while(!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* Set the maximum number of MBs*/ - BW_CAN_MCR_MAXMB(canBaseAddr, data->max_num_mb); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetIdFilterTableElements - * Description : Set ID filter table elements. - * This function will set up ID filter table elements. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SetIdFilterTableElements( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - flexcan_rx_fifo_id_element_format_t id_format, - flexcan_id_table_t *id_filter_table) -{ - uint32_t i, j; - uint32_t val1, val2, val; - volatile CAN_Type *flexcan_reg_ptr; - - assert(data); - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - switch(id_format) - { - case (kFlexCanRxFifoIdElementFormat_A): - /* One full ID (standard and extended) per ID Filter Table element.*/ - BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_A); - if (id_filter_table->is_remote_mb) - { - val = 1U << 31U; - } - if (id_filter_table->is_extended_mb) - { - val |= 1 << 30; - j = 0; - for (i = 0; i < (data->num_id_filters + 1) * 8; i += 4) - { - flexcan_reg_ptr->MB[6 + i - j * 3].CS = val + - ((*(id_filter_table->id_filter + i)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK); - flexcan_reg_ptr->MB[6 + i - j * 3].ID = val + - ((*(id_filter_table->id_filter + i + 1)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val + - ((*(id_filter_table->id_filter + i + 2)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val + - ((*(id_filter_table->id_filter + i + 3)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK); - j++; - } - } - else - { - j = 0; - for (i = 0; i < (data->num_id_filters + 1) * 8; i += 4) - { - flexcan_reg_ptr->MB[6 + i - j * 3].CS = val + - ((*(id_filter_table->id_filter + i)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK); - flexcan_reg_ptr->MB[6 + i - j * 3].ID = val + - ((*(id_filter_table->id_filter + i + 1)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val + - ((*(id_filter_table->id_filter + i + 2)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val + - ((*(id_filter_table->id_filter + i + 3)) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK); - j++; - } - } - break; - case (kFlexCanRxFifoIdElementFormat_B): - /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/ - /* per ID Filter Table element.*/ - BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_B); - if (id_filter_table->is_remote_mb) - { - val1 = 1U << 31U; - val2 = 1 << 15; - } - if (id_filter_table->is_extended_mb) - { - val1 |= 1 << 30; - val2 |= 1 << 14; - j = 0; - for (i = 0; i < (data->num_id_filters + 1) * 8; i += 8) - { - flexcan_reg_ptr->MB[6 + i - j * 3].CS = val1 + - ((*(id_filter_table->id_filter + i)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].CS |= val2 + - ((*(id_filter_table->id_filter + i + 1)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2); - - flexcan_reg_ptr->MB[6 + i - j * 3].ID = val1 + - ((*(id_filter_table->id_filter + i + 2)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].ID |= val2 + - ((*(id_filter_table->id_filter + i + 3)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2); - - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val1 + - ((*(id_filter_table->id_filter + i + 4)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= val2 + - ((*(id_filter_table->id_filter + i + 5)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2); - - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val1 + - ((*(id_filter_table->id_filter + i + 6)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= val2 + - ((*(id_filter_table->id_filter + i + 7)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2); - j++; - } - } - else - { - j = 0; - for (i = 0; i < (data->num_id_filters + 1) * 8; i += 8) - { - flexcan_reg_ptr->MB[6 + i - j * 3].CS = val1 + - (((*(id_filter_table->id_filter + i)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].CS |= val2 + - (((*(id_filter_table->id_filter + i + 1)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2); - - flexcan_reg_ptr->MB[6 + i - j * 3].ID = val1 + - (((*(id_filter_table->id_filter + i + 2)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].ID |= val2 + - (((*(id_filter_table->id_filter + i + 3)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2); - - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = val1 + - (((*(id_filter_table->id_filter + i + 4)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= val2 + - (((*(id_filter_table->id_filter + i + 5)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2); - - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = val1 + - (((*(id_filter_table->id_filter + i + 6)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= val2 + - (((*(id_filter_table->id_filter + i + 7)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2); - j++; - } - } - break; - case (kFlexCanRxFifoIdElementFormat_C): - /* Four partial 8-bit Standard IDs per ID Filter Table element.*/ - BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_C); - j = 0; - for (i = 0; i < (data->num_id_filters + 1) * 8; i += 16) - { - flexcan_reg_ptr->MB[6 + i - j * 3].CS = ((*(id_filter_table->id_filter + i)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].CS |= ((*(id_filter_table->id_filter + i + 1)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2); - flexcan_reg_ptr->MB[6 + i - j * 3].CS |= ((*(id_filter_table->id_filter + i + 2)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3); - flexcan_reg_ptr->MB[6 + i - j * 3].CS |= ((*(id_filter_table->id_filter + i + 3)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4); - - flexcan_reg_ptr->MB[6 + i - j * 3].ID = ((*(id_filter_table->id_filter + i + 4)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].ID |= ((*(id_filter_table->id_filter + i + 5)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2); - flexcan_reg_ptr->MB[6 + i - j * 3].ID |= ((*(id_filter_table->id_filter + i + 6)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3); - flexcan_reg_ptr->MB[6 + i - j * 3].ID |= ((*(id_filter_table->id_filter + i + 7)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4); - - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 = ((*(id_filter_table->id_filter + i + 8)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= ((*(id_filter_table->id_filter + i + 9)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= ((*(id_filter_table->id_filter + i + 10)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD0 |= ((*(id_filter_table->id_filter + i + 11)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4); - - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 = ((*(id_filter_table->id_filter + i + 12)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= ((*(id_filter_table->id_filter + i + 13)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= ((*(id_filter_table->id_filter + i + 14)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3); - flexcan_reg_ptr->MB[6 + i - j * 3].WORD1 |= ((*(id_filter_table->id_filter + i + 15)) & - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK << - FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4); - - j++; - } - break; - case (kFlexCanRxFifoIdElementFormat_D): - /* All frames rejected.*/ - BW_CAN_MCR_IDAM(canBaseAddr, kFlexCanRxFifoIdElementFormat_D); - break; - default: - return kStatus_FLEXCAN_InvalidArgument; - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxFifo - * Description : Confgure RX FIFO ID filter table elements. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SetRxFifo( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - flexcan_rx_fifo_id_element_format_t id_format, - flexcan_id_table_t *id_filter_table) -{ - assert(data); - - if (!data->is_rx_fifo_needed) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - /* Set RX FIFO ID filter table elements*/ - return FLEXCAN_HAL_SetIdFilterTableElements(canBaseAddr, data, id_format, id_filter_table); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableMbInt - * Description : Enable the corresponding Message Buffer interrupt. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_EnableMbInt( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx) -{ - assert(data); - uint32_t temp; - - if ( mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Enable the corresponding message buffer Interrupt*/ - temp = 0x1 << mb_idx; - HW_CAN_IMASK1_SET(canBaseAddr, temp); - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableMbInt - * Description : Disable the corresponding Message Buffer interrupt. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_DisableMbInt( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx) -{ - assert(data); - uint32_t temp; - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Disable the corresponding message buffer Interrupt*/ - temp = 0x1 << mb_idx; - HW_CAN_IMASK1_CLR(canBaseAddr, temp); - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableErrInt - * Description : Enable the error interrupts. - * This function will enable Error interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnableErrInt(uint32_t canBaseAddr) -{ - /* Enable Error interrupt*/ - BW_CAN_CTRL1_ERRMSK(canBaseAddr, 0x1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableErrorInt - * Description : Disable the error interrupts. - * This function will disable Error interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_DisableErrInt(uint32_t canBaseAddr) -{ - /* Disable Error interrupt*/ - BW_CAN_CTRL1_ERRMSK(canBaseAddr, 0x0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableBusOffInt - * Description : Enable the Bus off interrupts. - * This function will enable Bus Off interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnableBusOffInt(uint32_t canBaseAddr) -{ - /* Enable Bus Off interrupt*/ - BW_CAN_CTRL1_BOFFMSK(canBaseAddr, 0x1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableBusOffInt - * Description : Disable the Bus off interrupts. - * This function will disable Bus Off interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_DisableBusOffInt(uint32_t canBaseAddr) -{ - /* Disable Bus Off interrupt*/ - BW_CAN_CTRL1_BOFFMSK(canBaseAddr, 0x0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableWakeupInt - * Description : Enable the wakeup interrupts. - * This function will enable Wake up interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnableWakeupInt(uint32_t canBaseAddr) -{ - /* Enable Wake Up interrupt*/ - BW_CAN_MCR_WAKMSK(canBaseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableWakeupInt - * Description : Disable the wakeup interrupts. - * This function will disable Wake up interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_DisableWakeupInt(uint32_t canBaseAddr) -{ - /* Disable Wake Up interrupt*/ - BW_CAN_MCR_WAKMSK(canBaseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableTxWarningInt - * Description : Enable the TX warning interrupts. - * This function will enable TX warning interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnableTxWarningInt(uint32_t canBaseAddr) -{ - /* Enable TX warning interrupt*/ - BW_CAN_CTRL1_TWRNMSK(canBaseAddr, 0x1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableTxWarningInt - * Description : Disable the TX warning interrupts. - * This function will disable TX warning interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_DisableTxWarningInt(uint32_t canBaseAddr) -{ - /* Disable TX warning interrupt*/ - BW_CAN_CTRL1_TWRNMSK(canBaseAddr, 0x0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableRxWarningInt - * Description : Enable the RX warning interrupts. - * This function will enable RX warning interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnableRxWarningInt(uint32_t canBaseAddr) -{ - /* Enable RX warning interrupt*/ - BW_CAN_CTRL1_RWRNMSK(canBaseAddr, 0x1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableRxWarningInt - * Description : Disable the RX warning interrupts. - * This function will disable RX warning interrupt. - * - *END**************************************************************************/ -void FLEXCAN_HAL_DisableRxWarningInt(uint32_t canBaseAddr) -{ - /* Disable RX warning interrupt*/ - BW_CAN_CTRL1_RWRNMSK(canBaseAddr, 0x0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_ExitFreezeMode - * Description : Exit of freeze mode. - * - *END**************************************************************************/ -void FLEXCAN_HAL_ExitFreezeMode(uint32_t canBaseAddr) -{ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnterFreezeMode - * Description : Enter the freeze mode. - * - *END**************************************************************************/ -void FLEXCAN_HAL_EnterFreezeMode(uint32_t canBaseAddr) -{ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_GetMbIntFlag - * Description : Get the corresponding message buffer interrupt flag. - * - *END**************************************************************************/ -uint8_t FLEXCAN_HAL_GetMbIntFlag( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx) -{ - assert(data); - assert(mb_idx < data->max_num_mb); - uint32_t temp; - - /* Get the corresponding message buffer interrupt flag*/ - temp = 0x1 << mb_idx; - if (HW_CAN_IFLAG1_RD(canBaseAddr) & temp) - { - return 1; - } - else - { - return 0; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_GetErrCounter - * Description : Get transmit error counter and receive error counter. - * - *END**************************************************************************/ -void FLEXCAN_HAL_GetErrCounter( - uint32_t canBaseAddr, - flexcan_berr_counter_t *err_cnt) -{ - /* Get transmit error counter and receive error counter*/ - err_cnt->rxerr = HW_CAN_ECR(canBaseAddr).B.RXERRCNT; - err_cnt->txerr = HW_CAN_ECR(canBaseAddr).B.TXERRCNT; -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_ClearErrIntStatus - * Description : Clear all error interrupt status. - * - *END**************************************************************************/ -void FLEXCAN_HAL_ClearErrIntStatus(uint32_t canBaseAddr) -{ - if(HW_CAN_ESR1_RD(canBaseAddr) & FLEXCAN_ALL_INT) - { - HW_CAN_ESR1_SET(canBaseAddr, FLEXCAN_ALL_INT); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_ReadFifo - * Description : Read Rx FIFO data. - * This function will copy MB[0] data field into user's buffer. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_ReadFifo( - uint32_t canBaseAddr, - flexcan_mb_t *rx_fifo) -{ - uint32_t i; - volatile CAN_Type *flexcan_reg_ptr; - - flexcan_reg_ptr = ((CAN_Type *)canBaseAddr); - if (NULL == flexcan_reg_ptr) - { - return (kStatus_FLEXCAN_InvalidArgument); - } - - rx_fifo->cs = flexcan_reg_ptr->MB[0].CS; - - if ((rx_fifo->cs) & CAN_CS_IDE_MASK) - { - rx_fifo->msg_id = flexcan_reg_ptr->MB[0].ID; - } - else - { - rx_fifo->msg_id = (flexcan_reg_ptr->MB[0].ID) >> CAN_ID_STD_SHIFT; - } - - /* Copy MB[0] data field into user's buffer*/ - for ( i=0 ; i < kFlexCanMessageSize ; i++ ) - { - if (i < 4) - { - rx_fifo->data[3 - i] = ((flexcan_reg_ptr->MB[0].WORD0) >> (i * 8)) & - FLEXCAN_BYTE_DATA_FIELD_MASK; - } - else - { - rx_fifo->data[11 - i] = ((flexcan_reg_ptr->MB[0].WORD1) >> ((i - 4) * 8)) & - FLEXCAN_BYTE_DATA_FIELD_MASK; - } - } - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetMaskType - * Description : Set RX masking type. - * This function will set RX masking type as RX global mask or RX individual - * mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetMaskType( - uint32_t canBaseAddr, - flexcan_rx_mask_type_t type) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* Set RX masking type (RX global mask or RX individual mask)*/ - if (type == kFlexCanRxMask_Global) - { - /* Enable Global RX masking*/ - BW_CAN_MCR_IRMQ(canBaseAddr, 0x0); - } - else - { - /* Enable Individual Rx Masking and Queue*/ - BW_CAN_MCR_IRMQ(canBaseAddr, 0x1); - } - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxFifoGlobalStdMask - * Description : Set Rx FIFO global mask as the 11-bit standard mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxFifoGlobalStdMask( - uint32_t canBaseAddr, - uint32_t std_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 11 bit standard mask*/ - HW_CAN_RXFGMASK_WR(canBaseAddr, CAN_ID_STD(std_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxFifoGlobalExtMask - * Description : Set Rx FIFO global mask as the 29-bit extended mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxFifoGlobalExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 29-bit extended mask*/ - HW_CAN_RXFGMASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxIndividualStdMask - * Description : Set Rx individual mask as the 11-bit standard mask. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask( - uint32_t canBaseAddr, - const flexcan_user_config_t * data, - uint32_t mb_idx, - uint32_t std_mask) -{ - assert(data); - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 11 bit standard mask*/ - HW_CAN_RXIMRn_WR(canBaseAddr, mb_idx, CAN_ID_STD(std_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxIndividualExtMask - * Description : Set Rx individual mask as the 29-bit extended mask. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask( - uint32_t canBaseAddr, - const flexcan_user_config_t * data, - uint32_t mb_idx, - uint32_t ext_mask) -{ - assert(data); - - if (mb_idx >= data->max_num_mb) - { - return (kStatus_FLEXCAN_OutOfRange); - } - - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 29-bit extended mask*/ - HW_CAN_RXIMRn_WR(canBaseAddr, mb_idx, CAN_ID_EXT(ext_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxMbGlobalStdMask - * Description : Set Rx Message Buffer global mask as the 11-bit standard mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxMbGlobalStdMask( - uint32_t canBaseAddr, - uint32_t std_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 11 bit standard mask*/ - HW_CAN_RXMGMASK_WR(canBaseAddr, CAN_ID_STD(std_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxMbBuf14StdMask - * Description : Set Rx Message Buffer 14 mask as the 11-bit standard mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxMbBuf14StdMask( - uint32_t canBaseAddr, - uint32_t std_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 11 bit standard mask*/ - HW_CAN_RX14MASK_WR(canBaseAddr, CAN_ID_STD(std_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxMbBuf15StdMask - * Description : Set Rx Message Buffer 15 mask as the 11-bit standard mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxMbBuf15StdMask( - uint32_t canBaseAddr, - uint32_t std_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 11 bit standard mask*/ - HW_CAN_RX15MASK_WR(canBaseAddr, CAN_ID_STD(std_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxMbGlobalExtMask - * Description : Set Rx Message Buffer global mask as the 29-bit extended mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxMbGlobalExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(HW_CAN_MCR_RD(canBaseAddr))){} - - /* 29-bit extended mask*/ - HW_CAN_RXMGMASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxMbBuf14ExtMask - * Description : Set Rx Message Buffer 14 mask as the 29-bit extended mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxMbBuf14ExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 29-bit extended mask*/ - HW_CAN_RX14MASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_SetRxMbBuf15ExtMask - * Description : Set Rx Message Buffer 15 mask as the 29-bit extended mask. - * - *END**************************************************************************/ -void FLEXCAN_HAL_SetRxMbBuf15ExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask) -{ - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - /* 29-bit extended mask*/ - HW_CAN_RX15MASK_WR(canBaseAddr, CAN_ID_EXT(ext_mask)); - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_EnableOperationMode - * Description : Enable a FlexCAN operation mode. - * This function will enable one of the modes listed in flexcan_operation_modes_t. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_EnableOperationMode( - uint32_t canBaseAddr, - flexcan_operation_modes_t mode) -{ - if (mode == kFlexCanFreezeMode) - { - /* Debug mode, Halt and Freeze*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - return (kStatus_FLEXCAN_Success); - } - else if (mode == kFlexCanDisableMode) - { - /* Debug mode, Halt and Freeze*/ - BW_CAN_MCR_MDIS(canBaseAddr, 0x1); - return (kStatus_FLEXCAN_Success); - } - - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - if (mode == kFlexCanNormalMode) - { - BW_CAN_MCR_SUPV(canBaseAddr, 0x0); - } - else if (mode == kFlexCanListenOnlyMode) - { - BW_CAN_CTRL1_LOM(canBaseAddr, 0x1); - } - else if (mode == kFlexCanLoopBackMode) - { - BW_CAN_CTRL1_LPB(canBaseAddr, 0x1); - } - else - { - return kStatus_FLEXCAN_InvalidArgument; - } - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} - - return (kStatus_FLEXCAN_Success); -} - -/*FUNCTION********************************************************************** - * - * Function Name : FLEXCAN_HAL_DisableOperationMode - * Description : Disable a FlexCAN operation mode. - * This function will disable one of the modes listed in flexcan_operation_modes_t. - * - *END**************************************************************************/ -flexcan_status_t FLEXCAN_HAL_DisableOperationMode( - uint32_t canBaseAddr, - flexcan_operation_modes_t mode) -{ - if (mode == kFlexCanFreezeMode) - { - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} - - return (kStatus_FLEXCAN_Success); - } - else if (mode == kFlexCanDisableMode) - { - /* Disable module mode*/ - BW_CAN_MCR_MDIS(canBaseAddr, 0x0); - return (kStatus_FLEXCAN_Success); - } - - /* Set Freeze mode*/ - BW_CAN_MCR_FRZ(canBaseAddr, 0x1); - BW_CAN_MCR_HALT(canBaseAddr, 0x1); - - /* Wait for entering the freeze mode*/ - while (!(BR_CAN_MCR_FRZACK(canBaseAddr))){} - - if (mode == kFlexCanNormalMode) - { - BW_CAN_MCR_SUPV(canBaseAddr, 0x1); - } - else if (mode == kFlexCanListenOnlyMode) - { - BW_CAN_CTRL1_LOM(canBaseAddr, 0x0); - } - else if (mode == kFlexCanLoopBackMode) - { - BW_CAN_CTRL1_LPB(canBaseAddr, 0x0); - } - else - { - return kStatus_FLEXCAN_InvalidArgument; - } - - /* De-assert Freeze Mode*/ - BW_CAN_MCR_HALT(canBaseAddr, 0x0); - BW_CAN_MCR_FRZ(canBaseAddr, 0x0); - - /* Wait till exit of freeze mode*/ - while (BR_CAN_MCR_FRZACK(canBaseAddr)){} - - return (kStatus_FLEXCAN_Success); -} - -#endif /* MBED_NO_FLEXCAN */ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.h deleted file mode 100644 index deed4a95897..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.h +++ /dev/null @@ -1,837 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_FLEXCAN_HAL_H__ -#define __FSL_FLEXCAN_HAL_H__ - -#include -#include -#include -#include "fsl_flexcan_features.h" -#include "fsl_device_registers.h" - -#ifndef MBED_NO_FLEXCAN - -/*! - * @addtogroup flexcan_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief FlexCAN constants*/ -enum _flexcan_constants -{ - kFlexCanMessageSize = 8, /*!< FlexCAN message buffer data size in bytes*/ -}; - -/*! @brief The Status enum is used to report current status of the FlexCAN interface.*/ -enum _flexcan_err_status -{ - kFlexCan_RxWrn = 0x0080, /*!< Reached warning level for RX errors*/ - kFlexCan_TxWrn = 0x0100, /*!< Reached warning level for TX errors*/ - kFlexCan_StfErr = 0x0200, /*!< Stuffing Error*/ - kFlexCan_FrmErr = 0x0400, /*!< Form Error*/ - kFlexCan_CrcErr = 0x0800, /*!< Cyclic Redundancy Check Error*/ - kFlexCan_AckErr = 0x1000, /*!< Received no ACK on transmission*/ - kFlexCan_Bit0Err = 0x2000, /*!< Unable to send dominant bit*/ - kFlexCan_Bit1Err = 0x4000, /*!< Unable to send recessive bit*/ -}; - -/*! @brief FlexCAN status return codes*/ -typedef enum _flexcan_status -{ - kStatus_FLEXCAN_Success = 0, - kStatus_FLEXCAN_OutOfRange, - kStatus_FLEXCAN_UnknownProperty, - kStatus_FLEXCAN_InvalidArgument, - kStatus_FLEXCAN_Fail, - kStatus_FLEXCAN_TimeOut, -} flexcan_status_t; - - -/*! @brief FlexCAN operation modes*/ -typedef enum _flexcan_operation_modes { - kFlexCanNormalMode, /*!< Normal mode or user mode*/ - kFlexCanListenOnlyMode, /*!< Listen-only mode*/ - kFlexCanLoopBackMode, /*!< Loop-back mode*/ - kFlexCanFreezeMode, /*!< Freeze mode*/ - kFlexCanDisableMode, /*!< Module disable mode*/ -} flexcan_operation_modes_t; - -/*! @brief FlexCAN message buffer CODE for Rx buffers*/ -typedef enum _flexcan_mb_code_rx { - kFlexCanRX_Inactive = 0x0, /*!< MB is not active.*/ - kFlexCanRX_Full = 0x2, /*!< MB is full.*/ - kFlexCanRX_Empty = 0x4, /*!< MB is active and empty.*/ - kFlexCanRX_Overrun = 0x6, /*!< MB is overwritten into a full buffer.*/ - kFlexCanRX_Busy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ - /*! The CPU must not access the MB.*/ - kFlexCanRX_Ranswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame*/ - /*! and transmit a Response Frame in return.*/ - kFlexCanRX_NotUsed = 0xF, /*!< Not used*/ -} flexcan_mb_code_rx_t; - -/*! @brief FlexCAN message buffer CODE FOR Tx buffers*/ -typedef enum _flexcan_mb_code_tx { - kFlexCanTX_Inactive = 0x08, /*!< MB is not active.*/ - kFlexCanTX_Abort = 0x09, /*!< MB is aborted.*/ - kFlexCanTX_Data = 0x0C, /*!< MB is a TX Data Frame(MB RTR must be 0).*/ - kFlexCanTX_Remote = 0x1C, /*!< MB is a TX Remote Request Frame (MB RTR must be 1).*/ - kFlexCanTX_Tanswer = 0x0E, /*!< MB is a TX Response Request Frame from.*/ - /*! an incoming Remote Request Frame.*/ - kFlexCanTX_NotUsed = 0xF, /*!< Not used*/ -} flexcan_mb_code_tx_t; - -/*! @brief FlexCAN message buffer transmission types*/ -typedef enum _flexcan_mb_transmission_type { - kFlexCanMBStatusType_TX, /*!< Transmit MB*/ - kFlexCanMBStatusType_TXRemote, /*!< Transmit remote request MB*/ - kFlexCanMBStatusType_RX, /*!< Receive MB*/ - kFlexCanMBStatusType_RXRemote, /*!< Receive remote request MB*/ - kFlexCanMBStatusType_RXTXRemote, /*!< FlexCAN remote frame receives remote request and*/ - /*! transmits MB.*/ -} flexcan_mb_transmission_type_t; - -typedef enum _flexcan_rx_fifo_id_element_format { - kFlexCanRxFifoIdElementFormat_A, /*!< One full ID (standard and extended) per ID Filter Table*/ - /*! element.*/ - kFlexCanRxFifoIdElementFormat_B, /*!< Two full standard IDs or two partial 14-bit (standard and*/ - /*! extended) IDs per ID Filter Table element.*/ - kFlexCanRxFifoIdElementFormat_C, /*!< Four partial 8-bit Standard IDs per ID Filter Table*/ - /*! element.*/ - kFlexCanRxFifoIdElementFormat_D, /*!< All frames rejected.*/ -} flexcan_rx_fifo_id_element_format_t; - -/*! @brief FlexCAN Rx FIFO filters number*/ -typedef enum _flexcan_rx_fifo_id_filter_number { - kFlexCanRxFifoIDFilters_8 = 0x0, /*!< 8 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_16 = 0x1, /*!< 16 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_24 = 0x2, /*!< 24 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_32 = 0x3, /*!< 32 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_40 = 0x4, /*!< 40 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_48 = 0x5, /*!< 48 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_56 = 0x6, /*!< 56 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_64 = 0x7, /*!< 64 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_72 = 0x8, /*!< 72 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_80 = 0x9, /*!< 80 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_88 = 0xA, /*!< 88 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_96 = 0xB, /*!< 96 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_104 = 0xC, /*!< 104 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_112 = 0xD, /*!< 112 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_120 = 0xE, /*!< 120 Rx FIFO Filters*/ - kFlexCanRxFifoIDFilters_128 = 0xF /*!< 128 Rx FIFO Filters*/ -} flexcan_rx_fifo_id_filter_num_t; - -/*! @brief FlexCAN RX FIFO ID filter table structure*/ -typedef struct FLEXCANIdTable { - bool is_remote_mb; /*!< Remote frame*/ - bool is_extended_mb; /*!< Extended frame*/ - uint32_t *id_filter; /*!< Rx FIFO ID filter elements*/ -} flexcan_id_table_t; - -/*! @brief FlexCAN RX mask type.*/ -typedef enum _flexcan_rx_mask_type { - kFlexCanRxMask_Global, /*!< Rx global mask*/ - kFlexCanRxMask_Individual, /*!< Rx individual mask*/ -} flexcan_rx_mask_type_t; - -/*! @brief FlexCAN MB ID type*/ -typedef enum _flexcan_mb_id_type { - kFlexCanMbId_Std, /*!< Standard ID*/ - kFlexCanMbId_Ext, /*!< Extended ID*/ -} flexcan_mb_id_type_t; - -/*! @brief FlexCAN clock source*/ -typedef enum _flexcan_clk_source { - kFlexCanClkSource_Osc, /*!< Oscillator clock*/ - kFlexCanClkSource_Ipbus, /*!< Peripheral clock*/ -} flexcan_clk_source_t; - -/*! @brief FlexCAN error interrupt types*/ -typedef enum _flexcan_int_type { - kFlexCanInt_Buf, /*!< OR'd message buffers interrupt*/ - kFlexCanInt_Err, /*!< Error interrupt*/ - kFlexCanInt_Boff, /*!< Bus off interrupt*/ - kFlexCanInt_Wakeup, /*!< Wakeup interrupt*/ - kFlexCanInt_Txwarning, /*!< TX warning interrupt*/ - kFlexCanInt_Rxwarning, /*!< RX warning interrupt*/ -} flexcan_int_type_t; - -/*! @brief FlexCAN bus error counters*/ -typedef struct FLEXCANBerrCounter { - uint16_t txerr; /*!< Transmit error counter*/ - uint16_t rxerr; /*!< Receive error counter*/ -} flexcan_berr_counter_t; - -/*! @brief FlexCAN MB code and status for transmit and receive */ -typedef struct FLEXCANMbCodeStatus { - uint32_t code; /*!< MB code for TX or RX buffers. - Defined by flexcan_mb_code_rx_t and flexcan_mb_code_tx_t */ - flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/ - uint32_t data_length; /*!< Length of Data in Bytes*/ -} flexcan_mb_code_status_t; - -/*! @brief FlexCAN message buffer structure*/ -typedef struct FLEXCANMb { - uint32_t cs; /*!< Code and Status*/ - uint32_t msg_id; /*!< Message Buffer ID*/ - uint8_t data[kFlexCanMessageSize]; /*!< Bytes of the FlexCAN message*/ -} flexcan_mb_t; - -/*! @brief FlexCAN configuration*/ -typedef struct FLEXCANUserConfig { - uint32_t max_num_mb; /*!< The maximum number of Message Buffers*/ - flexcan_rx_fifo_id_filter_num_t num_id_filters; /*!< The number of Rx FIFO ID filters needed*/ - bool is_rx_fifo_needed; /*!< 1 if needed; 0 if not*/ -} flexcan_user_config_t; - -/*! @brief FlexCAN timing related structures*/ -typedef struct FLEXCANTimeSegment { - uint32_t propseg; /*!< Propagation segment*/ - uint32_t pseg1; /*!< Phase segment 1*/ - uint32_t pseg2; /*!< Phase segment 2*/ - uint32_t pre_divider; /*!< Clock pre divider*/ - uint32_t rjw; /*!< Resync jump width*/ -} flexcan_time_segment_t; - - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Configuration - * @{ - */ - -/*! - * @brief Enables FlexCAN controller. - * - * @param canBaseAddr The FlexCAN base address - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_Enable(uint32_t canBaseAddr); - -/*! - * @brief Disables FlexCAN controller. - * - * @param canBaseAddr The FlexCAN base address - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_Disable(uint32_t canBaseAddr); - -/*! - * @brief Checks whether the FlexCAN is enabled or disabled. - * - * @param canBaseAddr The FlexCAN base address - * @return State of FlexCAN enable(0)/disable(1) - */ -static inline bool FLEXCAN_HAL_IsEnabled(uint32_t canBaseAddr) -{ - return BR_CAN_MCR_MDIS(canBaseAddr); -} - -/*! - * @brief Selects the clock source for FlexCAN. - * - * @param canBaseAddr The FlexCAN base address - * @param clk The FlexCAN clock source - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_SelectClock(uint32_t canBaseAddr, flexcan_clk_source_t clk); - -/*! - * @brief Initializes the FlexCAN controller. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data. - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_Init(uint32_t canBaseAddr, const flexcan_user_config_t *data); - -/*! - * @brief Sets the FlexCAN time segments for setting up bit rate. - * - * @param canBaseAddr The FlexCAN base address - * @param time_seg FlexCAN time segments, which need to be set for the bit rate. - * @return 0 if successful; non-zero failed - */ -void FLEXCAN_HAL_SetTimeSegments(uint32_t canBaseAddr, flexcan_time_segment_t *time_seg); - -/*! - * @brief Gets the FlexCAN time segments to calculate the bit rate. - * - * @param canBaseAddr The FlexCAN base address - * @param time_seg FlexCAN time segments read for bit rate - * @return 0 if successful; non-zero failed - */ -void FLEXCAN_HAL_GetTimeSegments(uint32_t canBaseAddr, flexcan_time_segment_t *time_seg); - -/*! - * @brief Un freezes the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - * @return 0 if successful; non-zero failed. - */ -void FLEXCAN_HAL_ExitFreezeMode(uint32_t canBaseAddr); - -/*! - * @brief Freezes the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnterFreezeMode(uint32_t canBaseAddr); - -/*! - * @brief Enables operation mode. - * - * @param canBaseAddr The FlexCAN base address - * @param mode An operation mode to be enabled - * @return 0 if successful; non-zero failed. - */ -flexcan_status_t FLEXCAN_HAL_EnableOperationMode( - uint32_t canBaseAddr, - flexcan_operation_modes_t mode); - -/*! - * @brief Disables operation mode. - * - * @param canBaseAddr The FlexCAN base address - * @param mode An operation mode to be disabled - * @return 0 if successful; non-zero failed. - */ -flexcan_status_t FLEXCAN_HAL_DisableOperationMode( - uint32_t canBaseAddr, - flexcan_operation_modes_t mode); - -/*@}*/ - -/*! - * @name Data transfer - * @{ - */ - -/*! - * @brief Sets the FlexCAN message buffer fields for transmitting. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @param cs CODE/status values (TX) - * @param msg_id ID of the message to transmit - * @param mb_data Bytes of the FlexCAN message - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_SetMbTx( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx, - flexcan_mb_code_status_t *cs, - uint32_t msg_id, - uint8_t *mb_data); - -/*! - * @brief Sets the FlexCAN message buffer fields for receiving. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @param cs CODE/status values (RX) - * @param msg_id ID of the message to receive - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_SetMbRx( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx, - flexcan_mb_code_status_t *cs, - uint32_t msg_id); - -/*! - * @brief Gets the FlexCAN message buffer fields. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @param mb The fields of the message buffer - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_GetMb( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx, - flexcan_mb_t *mb); - -/*! - * @brief Locks the FlexCAN Rx message buffer. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_LockRxMb( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx); - -/*! - * @brief Unlocks the FlexCAN Rx message buffer. - * - * @param canBaseAddr The FlexCAN base address - * @return 0 if successful; non-zero failed - */ -static inline void FLEXCAN_HAL_UnlockRxMb(uint32_t canBaseAddr) -{ - /* Unlock the mailbox */ - HW_CAN_TIMER_RD(canBaseAddr); -} - -/*! - * @brief Enables the Rx FIFO. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnableRxFifo(uint32_t canBaseAddr); - -/*! - * @brief Disables the Rx FIFO. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_DisableRxFifo(uint32_t canBaseAddr); - -/*! - * @brief Sets the number of the Rx FIFO filters. - * - * @param canBaseAddr The FlexCAN base address - * @param number The number of Rx FIFO filters - */ -void FLEXCAN_HAL_SetRxFifoFiltersNumber(uint32_t canBaseAddr, uint32_t number); - -/*! - * @brief Sets the maximum number of Message Buffers. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - */ -void FLEXCAN_HAL_SetMaxMbNumber( - uint32_t canBaseAddr, - const flexcan_user_config_t *data); - -/*! - * @brief Sets the Rx FIFO ID filter table elements. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param id_format The format of the Rx FIFO ID Filter Table Elements - * @param id_filter_table The ID filter table elements which contain if RTR bit, - * IDE bit and RX message ID need to be set. - * @return 0 if successful; non-zero failed. - */ -flexcan_status_t FLEXCAN_HAL_SetIdFilterTableElements( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - flexcan_rx_fifo_id_element_format_t id_format, - flexcan_id_table_t *id_filter_table); - -/*! - * @brief Sets the FlexCAN Rx FIFO fields. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param id_format The format of the Rx FIFO ID Filter Table Elements - * @param id_filter_table The ID filter table elements which contain RTR bit, IDE bit, - * and RX message ID. - * @return 0 if successful; non-zero failed. - */ -flexcan_status_t FLEXCAN_HAL_SetRxFifo( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - flexcan_rx_fifo_id_element_format_t id_format, - flexcan_id_table_t *id_filter_table); - -/*! - * @brief Gets the FlexCAN Rx FIFO data. - * - * @param canBaseAddr The FlexCAN base address - * @param rx_fifo The FlexCAN receive FIFO data - * @return 0 if successful; non-zero failed. - */ -flexcan_status_t FLEXCAN_HAL_ReadFifo( - uint32_t canBaseAddr, - flexcan_mb_t *rx_fifo); - -/*@}*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexCAN Message Buffer interrupt. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_EnableMbInt( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx); - -/*! - * @brief Disables the FlexCAN Message Buffer interrupt. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @return 0 if successful; non-zero failed - */ -flexcan_status_t FLEXCAN_HAL_DisableMbInt( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx); - -/*! - * @brief Enables error interrupt of the FlexCAN module. - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnableErrInt(uint32_t canBaseAddr); - -/*! - * @brief Disables error interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_DisableErrInt(uint32_t canBaseAddr); - -/*! - * @brief Enables Bus off interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnableBusOffInt(uint32_t canBaseAddr); - -/*! - * @brief Disables Bus off interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_DisableBusOffInt(uint32_t canBaseAddr); - -/*! - * @brief Enables Wakeup interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnableWakeupInt(uint32_t canBaseAddr); - -/*! - * @brief Disables Wakeup interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_DisableWakeupInt(uint32_t canBaseAddr); - -/*! - * @brief Enables TX warning interrupt of the FlexCAN module - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnableTxWarningInt(uint32_t canBaseAddr); - -/*! - * @brief Disables TX warning interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_DisableTxWarningInt(uint32_t canBaseAddr); - -/*! - * @brief Enables RX warning interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_EnableRxWarningInt(uint32_t canBaseAddr); - -/*! - * @brief Disables RX warning interrupt of the FlexCAN module. - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_DisableRxWarningInt(uint32_t canBaseAddr); - -/*@}*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the value of FlexCAN freeze ACK. - * - * @param canBaseAddr The FlexCAN base address - * @return freeze ACK state (1-freeze mode, 0-not in freeze mode). - */ -static inline uint32_t FLEXCAN_HAL_GetFreezeAck(uint32_t canBaseAddr) -{ - return HW_CAN_MCR(canBaseAddr).B.FRZACK; -} - -/*! - * @brief Gets the individual FlexCAN MB interrupt flag. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @return the individual MB interrupt flag (0 and 1 are the flag value) - */ -uint8_t FLEXCAN_HAL_GetMbIntFlag( - uint32_t canBaseAddr, - const flexcan_user_config_t *data, - uint32_t mb_idx); - -/*! - * @brief Gets all FlexCAN MB interrupt flags. - * - * @param canBaseAddr The FlexCAN base address - * @return all MB interrupt flags - */ -static inline uint32_t FLEXCAN_HAL_GetAllMbIntFlags(uint32_t canBaseAddr) -{ - return HW_CAN_IFLAG1_RD(canBaseAddr); -} - -/*! - * @brief Clears the interrupt flag of the message buffers. - * - * @param canBaseAddr The FlexCAN base address - * @param reg_val The value to be written to the interrupt flag1 register. - */ -/* See fsl_flexcan_hal.h for documentation of this function.*/ -static inline void FLEXCAN_HAL_ClearMbIntFlag( - uint32_t canBaseAddr, - uint32_t reg_val) -{ - /* Clear the corresponding message buffer interrupt flag*/ - HW_CAN_IFLAG1_SET(canBaseAddr, reg_val); -} - -/*! - * @brief Gets the transmit error counter and receives the error counter. - * - * @param canBaseAddr The FlexCAN base address - * @param err_cnt Transmit error counter and receive error counter - */ -void FLEXCAN_HAL_GetErrCounter( - uint32_t canBaseAddr, - flexcan_berr_counter_t *err_cnt); - -/*! - * @brief Gets error and status. - * - * @param canBaseAddr The FlexCAN base address - * @return The current error and status - */ -static inline uint32_t FLEXCAN_HAL_GetErrStatus(uint32_t canBaseAddr) -{ - return HW_CAN_ESR1_RD(canBaseAddr); -} - -/*! - * @brief Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup). - * - * @param canBaseAddr The FlexCAN base address - */ -void FLEXCAN_HAL_ClearErrIntStatus(uint32_t canBaseAddr); - -/*@}*/ - -/*! - * @name Mask - * @{ - */ - -/*! - * @brief Sets the Rx masking type. - * - * @param canBaseAddr The FlexCAN base address - * @param type The FlexCAN Rx mask type - */ -void FLEXCAN_HAL_SetMaskType(uint32_t canBaseAddr, flexcan_rx_mask_type_t type); - -/*! - * @brief Sets the FlexCAN RX FIFO global standard mask. - * - * @param canBaseAddr The FlexCAN base address - * @param std_mask Standard mask - */ -void FLEXCAN_HAL_SetRxFifoGlobalStdMask( - uint32_t canBaseAddr, - uint32_t std_mask); - -/*! - * @brief Sets the FlexCAN Rx FIFO global extended mask. - * - * @param canBaseAddr The FlexCAN base address - * @param ext_mask Extended mask - */ -void FLEXCAN_HAL_SetRxFifoGlobalExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask); - -/*! - * @brief Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @param std_mask Individual standard mask - * @return 0 if successful; non-zero failed -*/ -flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask( - uint32_t canBaseAddr, - const flexcan_user_config_t * data, - uint32_t mb_idx, - uint32_t std_mask); - -/*! - * @brief Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx MBs and the Rx FIFO. - * - * @param canBaseAddr The FlexCAN base address - * @param data The FlexCAN platform data - * @param mb_idx Index of the message buffer - * @param ext_mask Individual extended mask - * @return 0 if successful; non-zero failed -*/ -flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask( - uint32_t canBaseAddr, - const flexcan_user_config_t * data, - uint32_t mb_idx, - uint32_t ext_mask); - -/*! - * @brief Sets the FlexCAN Rx MB global standard mask. - * - * @param canBaseAddr The FlexCAN base address - * @param std_mask Standard mask - */ -void FLEXCAN_HAL_SetRxMbGlobalStdMask( - uint32_t canBaseAddr, - uint32_t std_mask); - -/*! - * @brief Sets the FlexCAN RX MB BUF14 standard mask. - * - * @param canBaseAddr The FlexCAN base address - * @param std_mask Standard mask - */ -void FLEXCAN_HAL_SetRxMbBuf14StdMask( - uint32_t canBaseAddr, - uint32_t std_mask); - -/*! - * @brief Sets the FlexCAN Rx MB BUF15 standard mask. - * - * @param canBaseAddr The FlexCAN base address - * @param std_mask Standard mask - * @return 0 if successful; non-zero failed - */ -void FLEXCAN_HAL_SetRxMbBuf15StdMask( - uint32_t canBaseAddr, - uint32_t std_mask); - -/*! - * @brief Sets the FlexCAN RX MB global extended mask. - * - * @param canBaseAddr The FlexCAN base address - * @param ext_mask Extended mask - */ -void FLEXCAN_HAL_SetRxMbGlobalExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask); - -/*! - * @brief Sets the FlexCAN RX MB BUF14 extended mask. - * - * @param canBaseAddr The FlexCAN base address - * @param ext_mask Extended mask - */ -void FLEXCAN_HAL_SetRxMbBuf14ExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask); - -/*! - * @brief Sets the FlexCAN RX MB BUF15 extended mask. - * - * @param canBaseAddr The FlexCAN base address - * @param ext_mask Extended mask - */ -void FLEXCAN_HAL_SetRxMbBuf15ExtMask( - uint32_t canBaseAddr, - uint32_t ext_mask); - -/*! - * @brief Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO. - * - * @param canBaseAddr The FlexCAN base address - * @return RX FIFO information - */ -static inline uint32_t FLEXCAN_HAL_GetIdAcceptanceFilterRxFifo(uint32_t canBaseAddr) -{ - return BR_CAN_RXFIR_IDHIT(canBaseAddr); -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* MBED_NO_FLEXCAN */ - -#endif /* __FSL_FLEXCAN_HAL_H__*/ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_features.h deleted file mode 100644 index c94fe0e777c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_features.h +++ /dev/null @@ -1,100 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_DAC_FEATURES_H__) -#define __FSL_DAC_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ - defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || \ - defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || \ - defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || \ - defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || \ - defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \ - defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV44F128VLH15) || \ - defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \ - defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Define the size of hardware buffer */ - #define FSL_FEATURE_DAC_BUFFER_SIZE (16) - /* @brief Define has watermark event detection or not. */ - #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ - defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ - defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ - defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ - defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ - defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Define the size of hardware buffer */ - #define FSL_FEATURE_DAC_BUFFER_SIZE (2) - /* @brief Define has watermark event detection or not. */ - #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DAC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c deleted file mode 100644 index 8d62e2039db..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dac_hal.h" - -/*FUNCTION********************************************************************* - * - * Function Name : DAC_HAL_Init - * Description : Reset all the configurable registers to be reset state for DAC. - * It should be called before configuring the DAC module. - * - *END*************************************************************************/ -void DAC_HAL_Init(uint32_t baseAddr) -{ - /* DACx_DATL and DACx_DATH */ - HW_DAC_DATnL_WR(baseAddr, 0U, 0U); HW_DAC_DATnH_WR(baseAddr, 0U, 0U); - HW_DAC_DATnL_WR(baseAddr, 1U, 0U); HW_DAC_DATnH_WR(baseAddr, 1U, 0U); -#if (HW_DAC_DATnL_COUNT > 2U) - HW_DAC_DATnL_WR(baseAddr, 2U, 0U); HW_DAC_DATnH_WR(baseAddr, 2U, 0U); - HW_DAC_DATnL_WR(baseAddr, 3U, 0U); HW_DAC_DATnH_WR(baseAddr, 3U, 0U); - HW_DAC_DATnL_WR(baseAddr, 4U, 0U); HW_DAC_DATnH_WR(baseAddr, 4U, 0U); - HW_DAC_DATnL_WR(baseAddr, 5U, 0U); HW_DAC_DATnH_WR(baseAddr, 5U, 0U); - HW_DAC_DATnL_WR(baseAddr, 6U, 0U); HW_DAC_DATnH_WR(baseAddr, 6U, 0U); - HW_DAC_DATnL_WR(baseAddr, 7U, 0U); HW_DAC_DATnH_WR(baseAddr, 7U, 0U); - HW_DAC_DATnL_WR(baseAddr, 8U, 0U); HW_DAC_DATnH_WR(baseAddr, 8U, 0U); - HW_DAC_DATnL_WR(baseAddr, 9U, 0U); HW_DAC_DATnH_WR(baseAddr, 9U, 0U); - HW_DAC_DATnL_WR(baseAddr, 10U, 0U); HW_DAC_DATnH_WR(baseAddr, 10U, 0U); - HW_DAC_DATnL_WR(baseAddr, 11U, 0U); HW_DAC_DATnH_WR(baseAddr, 11U, 0U); - HW_DAC_DATnL_WR(baseAddr, 12U, 0U); HW_DAC_DATnH_WR(baseAddr, 12U, 0U); - HW_DAC_DATnL_WR(baseAddr, 13U, 0U); HW_DAC_DATnH_WR(baseAddr, 13U, 0U); - HW_DAC_DATnL_WR(baseAddr, 14U, 0U); HW_DAC_DATnH_WR(baseAddr, 14U, 0U); - HW_DAC_DATnL_WR(baseAddr, 15U, 0U); HW_DAC_DATnH_WR(baseAddr, 15U, 0U); -#endif /* HW_DAC_DATnL_COUNT */ - /* DACx_SR. */ - HW_DAC_SR_WR(baseAddr, 0U); /* Clear all flags. */ - /* DACx_C0. */ - HW_DAC_C0_WR(baseAddr, 0U); - /* DACx_C1. */ - HW_DAC_C1_WR(baseAddr, 0U); - /* DACx_C2. */ - HW_DAC_C2_WR(baseAddr, 15U); -} - -/*FUNCTION********************************************************************* - * - * Function Name : DAC_HAL_SetBuffValue - * Description : Set the value assembled by the low 8 bits and high 4 - * bits of 12-bit DAC item in buffer. - * - *END*************************************************************************/ -void DAC_HAL_SetBuffValue(uint32_t baseAddr, uint8_t index, uint16_t value) -{ - assert(index < HW_DAC_DATnL_COUNT); - BW_DAC_DATnL_DATA0(baseAddr, index, (uint8_t)(0xFFU & value) ); - BW_DAC_DATnH_DATA1(baseAddr, index, (uint8_t)((0xF00U & value)>>8U) ); -} - -/*FUNCTION********************************************************************* - * - * Function Name : DAC_HAL_GetBuffValue - * Description : Get the value assembled by the low 8 bits and high 4 - * bits of 12-bit DAC item in buffer. - * - *END*************************************************************************/ -uint16_t DAC_HAL_GetBuffValue(uint32_t baseAddr, uint8_t index) -{ - assert(index < HW_DAC_DATnL_COUNT); - uint16_t ret16; - ret16 = BR_DAC_DATnH_DATA1(baseAddr, index); - ret16 <<= 8U; - ret16 |= BR_DAC_DATnL_DATA0(baseAddr, index); - return ret16; -} - -/****************************************************************************** - * EOF - *****************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h deleted file mode 100644 index 729b530c903..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_DAC_HAL_H__ -#define __FSL_DAC_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_dac_features.h" - -/*! - * @addtogroup dac_hal - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! - * @brief DAC status return codes. - */ -typedef enum _dac_status -{ - kStatus_DAC_Success = 0U, /*!< Success. */ - kStatus_DAC_InvalidArgument = 1U, /*!< Invalid argument existed. */ - kStatus_DAC_Failed = 2U /*!< Execution failed. */ -} dac_status_t; - -/*! - * @brief Defines the type of selection for DAC module's reference voltage source. - * - * See the appropriate SoC Reference Manual for actual connections. - */ -typedef enum _dac_ref_volt_src_mode -{ - kDacRefVoltSrcOfVref1 = 0U, /*!< Select DACREF_1 as the reference voltage. */ - kDacRefVoltSrcOfVref2 = 1U, /*!< Select DACREF_2 as the reference voltage. */ -} dac_ref_volt_src_mode_t; - -/*! - * @brief Defines the type of selection for DAC module trigger mode. - */ -typedef enum _dac_trigger_mode -{ - kDacTriggerByHardware = 0U, /*!< Select hardware trigger. */ - kDacTriggerBySoftware = 1U /*!< Select software trigger. */ -} dac_trigger_mode_t; - -/*! - * @brief Defines the type of selection for buffer watermark mode. - * - * If the buffer feature for DAC module is enabled, a watermark event will - * occur when the buffer index hits the watermark. - */ -typedef enum _dac_buff_watermark_mode -{ - kDacBuffWatermarkFromUpperAs1Word = 0U, /*!< Select 1 word away from the upper of buffer. */ - kDacBuffWatermarkFromUpperAs2Word = 1U, /*!< Select 2 word away from the upper of buffer. */ - kDacBuffWatermarkFromUpperAs3Word = 2U, /*!< Select 3 word away from the upper of buffer. */ - kDacBuffWatermarkFromUpperAs4Word = 3U, /*!< Select 4 word away from the upper of buffer. */ -} dac_buff_watermark_mode_t; - -/*! - * @brief Defines the type of selection for buffer work mode. - * - * There are three kinds of work modes when the DAC buffer is enabled. - * Normal mode - When the buffer index hits the upper level, it - * starts (0) on the next trigger. - * Swing mode - When the buffer index hits the upper level, it goes backward to - * the start and is reduced one-by-one on the next trigger. When the buffer index - * hits the start, it goes backward to the upper level and increases one-by-one - * on the next trigger. - * One-Time-Scan mode - The buffer index can only be increased on the next trigger. - * When the buffer index hits the upper level, it is not updated by the trigger. - * FIFO mode - */ -typedef enum _dac_buff_work_mode -{ - kDacBuffWorkAsNormalMode = 0U, /*!< Buffer works as Normal. */ - kDacBuffWorkAsSwingMode = 1U, /*!< Buffer works as swing. */ - kDacBuffWorkAsOneTimeScanMode = 2U, /*!< Buffer works as one time scan.*/ - kDacBuffWorkAsFIFOMode = 3U /*!< Buffer works as FIFO.*/ -} dac_buff_work_mode_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Resets all configurable registers to be in the reset state for DAC. - * - * This function resets all configurable registers to be in the reset state for DAC. - * It should be called before configuring the DAC module. - * - * @param baseAddr The DAC peripheral base address. - */ -void DAC_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Sets the 12-bit value for the DAC items in the buffer. - * - * This function sets the value assembled by the low 8 bits and high 4 - * bits of 12-bit DAC item in the buffer. - * - * @param baseAddr The DAC peripheral base address. - * @param index Buffer index. - * @param value Setting value. - */ -void DAC_HAL_SetBuffValue(uint32_t baseAddr, uint8_t index, uint16_t value); - -/*! - * @brief Gets the 12-bit value from the DAC item in the buffer. - * - * This function gets the value assembled by the low 8 bits and high 4 - * bits of 12-bit DAC item in the buffer. - * - * @param baseAddr The DAC peripheral base address. - * @param index Buffer index. - * @return Current setting value. - */ -uint16_t DAC_HAL_GetBuffValue(uint32_t baseAddr, uint8_t index); - -/*! - * @brief Clears the flag of the DAC buffer read pointer. - * - * This function clears the flag of the DAC buffer read pointer when it hits the - * bottom position. - * - * @param baseAddr The DAC peripheral base address. - */ -static inline void DAC_HAL_ClearBuffIndexUpperFlag(uint32_t baseAddr) -{ - BW_DAC_SR_DACBFRPBF(baseAddr, 0U); -} - -/*! - * @brief Gets the flag of DAC buffer read pointer when it hits the bottom position. - * - * This function gets the flag of DAC buffer read pointer when it hits the - * bottom position. - * - * @param baseAddr The DAC peripheral base address. - * @return Assertion of indicated event. - */ -static inline bool DAC_HAL_GetBuffIndexUpperFlag(uint32_t baseAddr) -{ - return ( 1U == BR_DAC_SR_DACBFRPBF(baseAddr) ); -} - -/*! - * @brief Clears the flag of the DAC buffer read pointer when it hits the top position. - * - * This function clears the flag of the DAC buffer read pointer when it hits the - * top position. - * - * @param baseAddr The DAC peripheral base address. - */ -static inline void DAC_HAL_ClearBuffIndexStartFlag(uint32_t baseAddr) -{ - BW_DAC_SR_DACBFRPTF(baseAddr, 0U); -} - -/*! - * @brief Gets the flag of the DAC buffer read pointer when it hits the top position. - * - * This function gets the flag of the DAC buffer read pointer when it hits the - * top position. - * - * @param baseAddr The DAC peripheral base address. - * @return Assertion of indicated event. - */ -static inline bool DAC_HAL_GetBuffIndexStartFlag(uint32_t baseAddr) -{ - return ( 1U == BR_DAC_SR_DACBFRPTF(baseAddr) ); -} - -#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - -/*! - * @brief Gets the flag of the DAC buffer read pointer when it hits the watermark position. - * - * This function gets the flag of the DAC buffer read pointer when it hits the - * watermark position. - * - * @param baseAddr The DAC peripheral base address. - * @return Assertion of indicated event. - */ -static inline bool DAC_HAL_GetBuffIndexWatermarkFlag(uint32_t baseAddr) -{ - return ( 1U == BR_DAC_SR_DACBFWMF(baseAddr) ); -} - -/*! - * @brief Clears the flag of the DAC buffer read pointer when it hits the watermark position. - * - * This function clears the flag of the DAC buffer read pointer when it hits the - * watermark position. - * - * @param baseAddr The DAC peripheral base address. - * @return Assertion of indicated event. - */ -static inline void DAC_HAL_ClearBuffIndexWatermarkFlag(uint32_t baseAddr) -{ - BW_DAC_SR_DACBFWMF(baseAddr, 0U); -} -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - -/*! - * @brief Enables the Programmable Reference Generator. - * - * This function enables the Programmable Reference Generator. Then the - * DAC system is enabled. - * - * @param baseAddr The DAC peripheral base address. - */ -static inline void DAC_HAL_Enable(uint32_t baseAddr) -{ - BW_DAC_C0_DACEN(baseAddr, 1U); -} - -/*! - * @brief Disables the Programmable Reference Generator. - * - * This function disables the Programmable Reference Generator. Then the - * DAC system is disabled. - * - * @param baseAddr The DAC peripheral base address. - */ -static inline void DAC_HAL_Disable(uint32_t baseAddr) -{ - BW_DAC_C0_DACEN(baseAddr, 0U); -} - -/*! - * @brief Sets the reference voltage source mode for the DAC module. - * - * This function sets the reference voltage source mode for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param mode Selection of enumeration mode. See to "dac_ref_volt_src_mode_t". - */ -static inline void DAC_HAL_SetRefVoltSrcMode(uint32_t baseAddr, dac_ref_volt_src_mode_t mode) -{ - BW_DAC_C0_DACRFS(baseAddr, ((kDacRefVoltSrcOfVref1==mode)?0U:1U) ); -} - -/*! - * @brief Sets the trigger mode for the DAC module. - * - * This function sets the trigger mode for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param mode Selection of enumeration mode. See to "dac_trigger_mode_t". - */ -static inline void DAC_HAL_SetTriggerMode(uint32_t baseAddr, dac_trigger_mode_t mode) -{ - BW_DAC_C0_DACTRGSEL(baseAddr, ((kDacTriggerByHardware==mode)?0U:1U) ); -} - -/*! - * @brief Triggers the converter with software. - * - * This function triggers the converter with software. If the DAC software - * trigger is selected and buffer enabled, calling this API advances the - * buffer read pointer once. - * - * @param baseAddr The DAC peripheral base address. - */ -static inline void DAC_HAL_SetSoftTriggerCmd(uint32_t baseAddr) -{ - BW_DAC_C0_DACSWTRG(baseAddr, 1U); -} - -/*! - * @brief Switches to enable working in low power mode for the DAC module. - * - * This function switches to enable working in low power mode for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param enable Switcher to assert the feature. - */ -static inline void DAC_HAL_SetLowPowerCmd(uint32_t baseAddr, bool enable) -{ - BW_DAC_C0_LPEN(baseAddr, (enable?1U:0U) ); -} - -#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION -/*! - * @brief Switches to enable the interrupt when buffer read pointer hits the watermark position. - * - * This function switches to enable the interrupt when the buffer read pointer hits - * the watermark position. - * - * @param baseAddr The DAC peripheral base address. - * @param enable Switcher to assert the feature. - */ -static inline void DAC_HAL_SetBuffIndexWatermarkIntCmd(uint32_t baseAddr, bool enable) -{ - BW_DAC_C0_DACBWIEN(baseAddr, (enable?1U:0U) ); -} -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - -/*! - * @brief Switches to enable the interrupt when the buffer read pointer hits the top position. - * - * This function switches to enable the interrupt when the buffer read pointer hits - * the top position. - * - * @param baseAddr The DAC peripheral base address. - * @param enable Switcher to assert the feature. - */ -static inline void DAC_HAL_SetBuffIndexStartIntCmd(uint32_t baseAddr, bool enable) -{ - BW_DAC_C0_DACBTIEN(baseAddr, (enable?1U:0U) ); -} - -/*! - * @brief Switches to enable the interrupt when the buffer read pointer hits the bottom position. - * - * This function switches to enable the interrupt when the buffer read pointer hits - * the bottom position. - * - * @param baseAddr The DAC peripheral base address. - * @param enable Switcher to assert the feature. - */ -static inline void DAC_HAL_SetBuffIndexUpperIntCmd(uint32_t baseAddr, bool enable) -{ - BW_DAC_C0_DACBBIEN(baseAddr, (enable?1U:0U) ); -} - -/*! - * @brief Switches to enable the DMA for DAC. - * - * This function switches to enable the DMA for the DAC module. When the DMA is enabled, - * DMA request is generated by the original interrupts, which are - * not presented on this module at the same time. - * - * @param baseAddr The DAC peripheral base address. - * @param enable Switcher to assert the feature. - */ -static inline void DAC_HAL_SetDmaCmd(uint32_t baseAddr, bool enable) -{ - BW_DAC_C1_DMAEN(baseAddr, (enable?1U:0U) ); -} - -#if FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION -/*! - * @brief Sets the watermark mode of the buffer for the DAC module. - * - * This function sets the watermark mode of the buffer for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param mode Selection of enumeration mode. See to "dac_buff_watermark_mode_t". - */ -static inline void DAC_HAL_SetBuffWatermarkMode(uint32_t baseAddr, dac_buff_watermark_mode_t mode) -{ - BW_DAC_C1_DACBFWM(baseAddr, (uint8_t)mode); -} -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - -/*! - * @brief Sets the work mode of the buffer for the DAC module. - * - * This function sets the work mode of the buffer for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param mode Selection of enumeration mode. See to "dac_buff_work_mode_t". - */ -static inline void DAC_HAL_SetBuffWorkMode(uint32_t baseAddr, dac_buff_work_mode_t mode) -{ - BW_DAC_C1_DACBFMD(baseAddr, (uint8_t)mode ); -} - -/*! - * @brief Switches to enable the buffer for the DAC module. - * - * This function switches to enable the buffer for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param enable Switcher to assert the feature. - */ -static inline void DAC_HAL_SetBuffCmd(uint32_t baseAddr, bool enable) -{ - BW_DAC_C1_DACBFEN(baseAddr, (enable?1U:0U) ); -} - -/*! - * @brief Gets the buffer index upper limitation for the DAC module. - * - * This function gets the upper buffer index upper limitation for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @return Value of buffer index upper limitation. - */ -static inline uint8_t DAC_HAL_GetBuffUpperIndex(uint32_t baseAddr) -{ - return BR_DAC_C2_DACBFUP(baseAddr); -} - -/*! - * @brief Sets the buffer index upper limitation for the DAC module. - * - * This function sets the upper buffer index upper limitation for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @param index Setting value of upper limitation for buffer index. - */ -static inline void DAC_HAL_SetBuffUpperIndex(uint32_t baseAddr, uint8_t index) -{ - assert(index < HW_DAC_DATnL_COUNT); - BW_DAC_C2_DACBFUP(baseAddr , index); -} - -/*! - * @brief Gets the current buffer index upper limitation for the DAC module. - * - * This function gets the current buffer index for the DAC module. - * - * @param baseAddr The DAC peripheral base address. - * @return Value of current buffer index. - */ -static inline uint8_t DAC_HAL_GetBuffCurrentIndex(uint32_t baseAddr) -{ - return BR_DAC_C2_DACBFRP(baseAddr); -} - -/*! - * @brief Sets the buffer index for the DAC module. - * - * This function sets the upper buffer index for the DAC module. - * - * @param baseAddr the DAC peripheral base address. - * @param index Setting value for buffer index. - */ -static inline void DAC_HAL_SetBuffCurrentIndex(uint32_t baseAddr, uint8_t index) -{ - assert(index < HW_DAC_DATnL_COUNT); - BW_DAC_C2_DACBFRP(baseAddr, index); -} - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_DAC_HAL_H__ */ - -/****************************************************************************** - * EOF - *****************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_features.h deleted file mode 100644 index e96d12ec2d6..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_features.h +++ /dev/null @@ -1,114 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_DMAMUX_FEATURES_H__) -#define __FSL_DMAMUX_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ - defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ - defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ - defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ - defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ - defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ - defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ - defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ - defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ - defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ - defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ - defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \ - defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ - defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) - /* @brief Number of DMA channels (related to number of register CHCFGn). */ - #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 4) -#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ - defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \ - defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ - defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ - defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ - defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Number of DMA channels (related to number of register CHCFGn). */ - #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 16) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Number of DMA channels (related to number of register CHCFGn). */ - #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 32) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DMAMUX_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.c deleted file mode 100644 index 13a6bc2273d..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.c +++ /dev/null @@ -1,56 +0,0 @@ -/* -* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#include "fsl_dmamux_hal.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : dmamux_hal_init - * Description : Initialize the dmamux module to the reset state. - * - *END**************************************************************************/ -void DMAMUX_HAL_Init(uint32_t baseAddr) -{ - int i; - - for (i = 0; i < FSL_FEATURE_DMAMUX_MODULE_CHANNEL; i++) - { - BW_DMAMUX_CHCFGn_ENBL(baseAddr, i, 0U); - BW_DMAMUX_CHCFGn_SOURCE(baseAddr, i, 0U); - } -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.h deleted file mode 100644 index 4aa7544c5f1..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_DMAMUX_HAL_H__ -#define __FSL_DMAMUX_HAL_H__ - -#include -#include -#include -#include "fsl_dmamux_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup dmamux_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @brief A constant for the length of the DMA hardware source. This structure is used inside - * the DMA driver. - */ -typedef enum _dmamux_source { - kDmamuxDmaRequestSource = 64U /*!< Maximum number of the DMA requests allowed for the DMA mux. */ -} dmamux_dma_request_source; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMAMUX HAL function - * @{ - */ - -/*! - * @brief Initializes the DMAMUX module to the reset state. - * - * Initializes the DMAMUX module to the reset state. - * - * @param baseAddr Register base address for DMAMUX module. - */ -void DMAMUX_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Enables/Disables the DMAMUX channel. - * - * Enables the hardware request. If enabled, the hardware request is sent to - * the corresponding DMA channel. - * - * @param baseAddr Register base address for DMAMUX module. - * @param channel DMAMUX channel number. - * @param enable Enables (true) or Disables (false) DMAMUX channel. - */ -static inline void DMAMUX_HAL_SetChannelCmd(uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - BW_DMAMUX_CHCFGn_ENBL(baseAddr, channel, enable); -} - - -/*! - * @brief Enables/Disables the period trigger. - * - * @param baseAddr Register base address for DMAMUX module. - * @param channel DMAMUX channel number. - * @param enable Enables (true) or Disables (false) period trigger. - */ -static inline void DMAMUX_HAL_SetPeriodTriggerCmd(uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - BW_DMAMUX_CHCFGn_TRIG(baseAddr, channel, enable); -} - - -/*! - * @brief Configures the DMA request for the DMAMUX channel. - * - * Sets the trigger source for the DMA channel. The trigger source is in the file - * fsl_dma_request.h. - * - * @param baseAddr Register base address for DMAMUX module. - * @param channel DMAMUX channel number. - * @param source DMA request source. - */ -static inline void DMAMUX_HAL_SetTriggerSource(uint32_t baseAddr, uint32_t channel, uint8_t source) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - BW_DMAMUX_CHCFGn_SOURCE(baseAddr, channel, source); -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* __FSL_DMAMUX_HAL_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h deleted file mode 100644 index cff53b7a7bd..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h +++ /dev/null @@ -1,247 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_DSPI_FEATURES_H__) -#define __FSL_DSPI_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ - defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : (-1)) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (4) : (-1)) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || \ - defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ - defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ - defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : (-1)) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (5) : (-1)) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLL12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLL12) || \ - defined(CPU_MKV31F512VLL12) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (6) : \ - ((x) == 1 ? (4) : (-1))) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VLH12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F512VLH12) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (5) : \ - ((x) == 1 ? (2) : (-1))) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (6) : \ - ((x) == 1 ? (4) : \ - ((x) == 2 ? (2) : (-1)))) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (6) : \ - ((x) == 1 ? (4) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : \ - ((x) == 1 ? (4) : \ - ((x) == 2 ? (4) : (-1)))) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (6) : \ - ((x) == 1 ? (4) : \ - ((x) == 2 ? (2) : (-1)))) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ - defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : (-1)) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (5) : (-1)) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV44F128VLL15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) - /* @brief Receive/transmit FIFO size in number of items. */ - #define FSL_FEATURE_DSPI_FIFO_SIZE (4) - #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ - ((x) == 0 ? (4) : (-1)) - /* @brief Maximum transfer data width in bits. */ - #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) - /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ - #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) - /* @brief Number of chip select pins. */ - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) - #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \ - ((x) == 0 ? (6) : (-1)) - /* @brief Has chip select strobe capability on the PCS5 pin. */ - #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) - /* @brief Has 16-bit data transfer support. */ - #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DSPI_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c deleted file mode 100644 index 54ed0594878..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c +++ /dev/null @@ -1,604 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dspi_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_Init - * Description : Restore DSPI to reset configuration. - * This function basically resets all of the DSPI registers to their default setting including - * disabling the module. - * - *END**************************************************************************/ -void DSPI_HAL_Init(uint32_t baseAddr) -{ - /* first, make sure the module is enabled to allow writes to certain registers*/ - DSPI_HAL_Enable(baseAddr); - - /* Halt all transfers*/ - DSPI_HAL_StopTransfer(baseAddr); - - /* set the registers to their default states*/ - /* clear the status bits (write-1-to-clear)*/ - HW_SPI_SR_WR(baseAddr, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF | - BM_SPI_SR_TFFF | BM_SPI_SR_RFOF | BM_SPI_SR_RFDF); - HW_SPI_TCR_WR(baseAddr, 0); - HW_SPI_CTARn_WR(baseAddr, 0, 0x78000000); /* CTAR0*/ - HW_SPI_CTARn_WR(baseAddr, 1, 0x78000000); /* CTAR1*/ - HW_SPI_RSER_WR(baseAddr, 0); - - /* Clear out PUSHR register. Since DSPI is halted, nothing should be transmitted. Be - * sure the flush the FIFOs afterwards - */ - HW_SPI_PUSHR_WR(baseAddr, 0); - - /* flush the fifos*/ - DSPI_HAL_SetFlushFifoCmd(baseAddr, true, true); - - /* Now set MCR to default value, which disables module: set MDIS and HALT, clear other bits */ - HW_SPI_MCR_WR(baseAddr, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT); -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetBaudRate - * Description : Set the DSPI baud rate in bits per second. - * This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest - * possible baud rate without exceeding the desired baud rate, and will return the calculated - * baud rate in bits-per-second. It requires that the caller also provide the frequency of the - * module source clock (in Hz). - * - *END**************************************************************************/ -uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, - uint32_t bitsPerSec, uint32_t sourceClockInHz) -{ - /* for master mode configuration, if slave mode detected, return 0*/ - if (!DSPI_HAL_IsMaster(baseAddr)) - { - return 0; - } - - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t dbr, bestDbr; - uint32_t realBaudrate, bestBaudrate; - uint32_t diff, min_diff; - uint32_t baudrate = bitsPerSec; - - /* find combination of prescaler and scaler resulting in baudrate closest to the */ - /* requested value */ - min_diff = 0xFFFFFFFFU; - bestPrescaler = 0; - bestScaler = 0; - bestDbr = 1; - bestBaudrate = 0; /* required to avoid compilation warning */ - - /* In all for loops, if min_diff = 0, the exit for loop*/ - for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) - { - for (scaler = 0; (scaler < 16) && min_diff; scaler++) - { - for (dbr = 1; (dbr < 3) && min_diff; dbr++) - { - realBaudrate = ((sourceClockInHz * dbr) / - (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler]))); - - /* calculate the baud rate difference based on the conditional statement*/ - /* that states that the calculated baud rate must not exceed the desired baud rate*/ - if (baudrate >= realBaudrate) - { - diff = baudrate-realBaudrate; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestBaudrate = realBaudrate; - bestDbr = dbr; - } - } - } - } - } - - /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/ - BW_SPI_CTARn_DBR(baseAddr, whichCtar, (bestDbr - 1)); - BW_SPI_CTARn_PBR(baseAddr, whichCtar, bestPrescaler); - BW_SPI_CTARn_BR(baseAddr, whichCtar, bestScaler); - - /* return the actual calculated baud rate*/ - return bestBaudrate; -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetBaudDivisors - * Description : Configure the baud rate divisors manually. - * This function allows the caller to manually set the baud rate divisors in the event that - * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function. - * - *END**************************************************************************/ -void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr, - dspi_ctar_selection_t whichCtar, - const dspi_baud_rate_divisors_t * divisors) -{ - /* these settings are only relevant in master mode*/ - if (DSPI_HAL_IsMaster(baseAddr)) - { - BW_SPI_CTARn_DBR(baseAddr, whichCtar, divisors->doubleBaudRate); - BW_SPI_CTARn_PBR(baseAddr, whichCtar, divisors->prescaleDivisor); - BW_SPI_CTARn_BR(baseAddr, whichCtar, divisors->baudRateDivisor); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetPcsPolarityMode - * Description : Configure DSPI peripheral chip select polarity. - * This function will take in the desired peripheral chip select (PCS) and it's - * corresponding desired polarity and will configure the PCS signal to operate with the - * desired characteristic. - * - *END**************************************************************************/ -void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs, - dspi_pcs_polarity_config_t activeLowOrHigh) -{ - uint32_t temp; - - temp = BR_SPI_MCR_PCSIS(baseAddr); - - if (activeLowOrHigh == kDspiPcs_ActiveLow) - { - temp |= pcs; - } - else /* kDspiPcsPolarity_ActiveHigh*/ - { - temp &= ~(unsigned)pcs; - } - - BW_SPI_MCR_PCSIS(baseAddr, temp); -} - - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetFifoCmd - * Description : Enables (or disables) the DSPI FIFOs. - * This function with allow the caller to disable/enable the TX and RX FIFOs (independently). - * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO - * configuration. To enable, the caller must pass in a logic 1 (true). - * - *END**************************************************************************/ -void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo) -{ - /* first see if MDIS is set or cleared */ - uint32_t isMdisSet = BR_SPI_MCR_MDIS(baseAddr); - - if (isMdisSet) - { - /* clear the MDIS bit (enable DSPI) to allow us to write to the fifo disables */ - DSPI_HAL_Enable(baseAddr); - } - - /* Note, the bit definition is "disable FIFO", so a "1" would disable. If user wants to enable - * the FIFOs, they pass in true, which we must logically negate (turn to false) to enable the - * FIFO - */ - BW_SPI_MCR_DIS_TXF(baseAddr, ~(enableTxFifo == true)); - BW_SPI_MCR_DIS_RXF(baseAddr, ~(enableRxFifo == true)); - - /* set MDIS (disable DSPI) if it was set to begin with */ - if (isMdisSet) - { - DSPI_HAL_Disable(baseAddr); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetFlushFifoCmd - * Description : Flush DSPI fifos. - * - *END**************************************************************************/ -void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo) -{ - BW_SPI_MCR_CLR_TXF(baseAddr, (enableFlushTxFifo == true)); - BW_SPI_MCR_CLR_RXF(baseAddr, (enableFlushRxFifo == true)); -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetDataFormat - * Description : Configure the data format for a particular CTAR. - * This function configures the bits-per-frame, polarity, phase, and shift direction for a - * particular CTAR. An example use case is as follows: - * dspi_data_format_config_t dataFormat; - * dataFormat.bitsPerFrame = 16; - * dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow; - * dataFormat.clkPhase = kDspiClockPhase_FirstEdge; - * dataFormat.direction = kDspiMsbFirst; - * DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &dataFormat); - * - *END**************************************************************************/ -dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr, - dspi_ctar_selection_t whichCtar, - const dspi_data_format_config_t * config) -{ - /* check bits-per-frame value to make sure it it within the proper range*/ - /* in either master or slave mode*/ - if ((config->bitsPerFrame < 4) || - ((config->bitsPerFrame > 16) && (HW_SPI_MCR(baseAddr).B.MSTR == 1)) || - ((config->bitsPerFrame > 32) && (HW_SPI_MCR(baseAddr).B.MSTR == 0))) - { - return kStatus_DSPI_InvalidBitCount; - } - - /* for master mode configuration*/ - if (DSPI_HAL_IsMaster(baseAddr)) - { - BW_SPI_CTARn_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1)); - BW_SPI_CTARn_CPOL(baseAddr, whichCtar, config->clkPolarity); - BW_SPI_CTARn_CPHA(baseAddr, whichCtar, config->clkPhase); - BW_SPI_CTARn_LSBFE(baseAddr, whichCtar, config->direction); - } - else /* for slave mode configuration*/ - { - BW_SPI_CTARn_SLAVE_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1)); - BW_SPI_CTARn_SLAVE_CPOL(baseAddr, whichCtar, config->clkPolarity); - BW_SPI_CTARn_SLAVE_CPHA(baseAddr, whichCtar, config->clkPhase); - } - return kStatus_DSPI_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetDelay - * Description : Manually configures the delay prescaler and scaler for a particular CTAR. - * This function configures the: - * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), - * After SCK delay pre-scalar (PASC) and scalar (ASC), - * Delay after transfer pre-scalar (PDT)and scalar (DT). - * - * These delay names are available in type dspi_delay_type_t. - * - * The user passes which delay they want to configure along with the prescaler and scaler value. - * This basically allows the user to directly set the prescaler/scaler values if they have - * pre-calculated them or if they simply wish to manually increment either value. - *END**************************************************************************/ -void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler, - uint32_t scaler, dspi_delay_type_t whichDelay) -{ - /* these settings are only relevant in master mode*/ - if (DSPI_HAL_IsMaster(baseAddr)) - { - if (whichDelay == kDspiPcsToSck) - { - BW_SPI_CTARn_PCSSCK(baseAddr, whichCtar, prescaler); - BW_SPI_CTARn_CSSCK(baseAddr, whichCtar, scaler); - } - - if (whichDelay == kDspiLastSckToPcs) - { - BW_SPI_CTARn_PASC(baseAddr, whichCtar, prescaler); - BW_SPI_CTARn_ASC(baseAddr, whichCtar, scaler); - } - - if (whichDelay == kDspiAfterTransfer) - { - BW_SPI_CTARn_PDT(baseAddr, whichCtar, prescaler); - BW_SPI_CTARn_DT(baseAddr, whichCtar, scaler); - } - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_CalculateDelay - * Description : Calculates the delay prescaler and scaler based on desired delay input in - * nano-seconds. - * - * This function calculates the values for: - * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or - * After SCK delay pre-scalar (PASC) and scalar (ASC), or - * Delay after transfer pre-scalar (PDT)and scalar (DT). - * - * These delay names are available in type dspi_delay_type_t. - * - * The user passes which delay they want to configure along with the desired delay value in - * nano-seconds. The function will calculate the values needed for the prescaler and scaler and - * will return the actual calculated delay as an exact delay match may not be acheivable. In this - * case, the closest match will be calculated without going below the desired delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in - * which case the maximum supported delay will be returned. It will be up to the higher level - * peripheral driver to alert the user of an out of range delay input. - *END**************************************************************************/ -uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, - dspi_delay_type_t whichDelay, uint32_t sourceClockInHz, - uint32_t delayInNanoSec) -{ - /* for master mode configuration, if slave mode detected, return 0*/ - if (!DSPI_HAL_IsMaster(baseAddr)) - { - return 0; - } - - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t realDelay, bestDelay; - uint32_t diff, min_diff; - uint32_t initialDelayNanoSec; - - /* find combination of prescaler and scaler resulting in the delay closest to the - * requested value - */ - min_diff = 0xFFFFFFFFU; - /* Initialize prescaler and scaler to their max values to generate the max delay */ - bestPrescaler = 0x3; - bestScaler = 0xF; - bestDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[bestPrescaler] * - s_delayScaler[bestScaler]; - - /* First calculate the initial, default delay */ - initialDelayNanoSec = 1000000000/sourceClockInHz * 2; - - /* If the initial, default delay is already greater than the desired delay, then - * set the delays to their initial value (0) and return the delay. In other words, - * there is no way to decrease the delay value further. - */ - if (initialDelayNanoSec >= delayInNanoSec) - { - DSPI_HAL_SetDelay(baseAddr, whichCtar, 0, 0, whichDelay); - return initialDelayNanoSec; - } - - - /* In all for loops, if min_diff = 0, the exit for loop*/ - for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) - { - for (scaler = 0; (scaler < 16) && min_diff; scaler++) - { - realDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[prescaler] * - s_delayScaler[scaler]; - - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the desired delay - */ - if (realDelay >= delayInNanoSec) - { - diff = realDelay-delayInNanoSec; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestDelay = realDelay; - } - } - } - } - - /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/ - DSPI_HAL_SetDelay(baseAddr, whichCtar, bestPrescaler, bestScaler, whichDelay); - - /* return the actual calculated baud rate*/ - return bestDelay; -} - - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetTxFifoFillDmaIntMode - * Description : Configures the DSPI Tx FIFO Fill request to generate DMA or interrupt requests. - * This function configures the DSPI Tx FIFO Fill flag to generate either - * an interrupt or DMA request. The user passes in which request they'd like to generate - * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request. - * Note, when disabling the request, the request type is don't care. - * - * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA - * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt - * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable - * - *END**************************************************************************/ -void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable) -{ - BW_SPI_RSER_TFFF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */ - BW_SPI_RSER_TFFF_RE(baseAddr, (enable == true)); /* Enable or disable the request */ -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetRxFifoDrainDmaIntMode - * Description : Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests. - * This function configures the DSPI Rx FIFO Drain flag to generate either - * an interrupt or DMA request. The user passes in which request they'd like to generate - * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request. - * Note, when disabling the request, the request type is don't care. - * - * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA - * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt - * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable - * - *END**************************************************************************/ -void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable) -{ - BW_SPI_RSER_RFDF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */ - BW_SPI_RSER_RFDF_RE(baseAddr, (enable == true)); /* Enable or disable the request */ -} - - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_SetIntMode - * Description : Configure DSPI interrupts. - * This function configures the various interrupt sources of the DSPI. The parameters are - * baseAddr, interrupt source, and enable/disable setting. - * The interrupt source is a typedef enum whose value is the bit position of the - * interrupt source setting within the RSER register. In the DSPI, all interrupt - * configuration settings are in one register. The typedef enum equates each - * interrupt source to the bit position defined in the device header file. - * The function uses these bit positions in its algorithm to enable/disable the - * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type. - * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions: - * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as - * these requests can generate either an interrupt or DMA request. - * - * DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case - * - *END**************************************************************************/ -void DSPI_HAL_SetIntMode(uint32_t baseAddr, - dspi_status_and_interrupt_request_t interruptSrc, - bool enable) -{ - uint32_t temp; - - temp = (HW_SPI_RSER_RD(baseAddr) & ~(0x1U << interruptSrc)) | - ((uint32_t)enable << interruptSrc); - HW_SPI_RSER_WR(baseAddr, temp); -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_GetFifoData - * Description : Read fifo registers for debug purposes. - * - *END**************************************************************************/ -uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry) -{ - if (whichFifo == kDspiTxFifo) - { - return HW_SPI_TXFRn_RD(baseAddr, whichFifoEntry); - } - else - { - return HW_SPI_RXFRn_RD(baseAddr, whichFifoEntry); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_WriteDataMastermode - * Description : Write data into the data buffer, master mode. - * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion - * provides characteristics of the data being sent such as: optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). An example use case is as follows: - * dspi_command_config_t commandConfig; - * commandConfig.isChipSelectContinuous = true; - * commandConfig.whichCtar = kDspiCtar0; - * commandConfig.whichPcs = kDspiPcs1; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord); - * - *END**************************************************************************/ -void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr, - dspi_command_config_t * command, - uint16_t data) -{ - uint32_t temp; - - /* First, build up the 32-bit word then write it to the PUSHR */ - temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) | - BF_SPI_PUSHR_CTAS(command->whichCtar) | - BF_SPI_PUSHR_PCS(command->whichPcs) | - BF_SPI_PUSHR_EOQ(command->isEndOfQueue) | - BF_SPI_PUSHR_CTCNT(command->clearTransferCount) | - BF_SPI_PUSHR_TXDATA(data); - - HW_SPI_PUSHR_WR(baseAddr, temp); -} - -/*FUNCTION********************************************************************** - * - * Function Name : DSPI_HAL_WriteDataMastermode - * Description : Write data into the data buffer, master mode and waits till complete to return. - * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion - * provides characteristics of the data being sent such as: optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). An example use case is as follows: - * dspi_command_config_t commandConfig; - * commandConfig.isChipSelectContinuous = true; - * commandConfig.whichCtar = kDspiCtar0; - * commandConfig.whichPcs = kDspiPcs1; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord); - * - * Note that this function will not return until after the transmit is complete. Also note that - * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0). - * Since the SPI is a synchronous protocol, receive data will be available when transmit completes. - * - *END**************************************************************************/ -void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr, - dspi_command_config_t * command, - uint16_t data) -{ - uint32_t temp; - - /* First, clear Transmit Complete Flag (TCF) */ - BW_SPI_SR_TCF(baseAddr, 1); - - /* First, build up the 32-bit word then write it to the PUSHR */ - temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) | - BF_SPI_PUSHR_CTAS(command->whichCtar) | - BF_SPI_PUSHR_PCS(command->whichPcs) | - BF_SPI_PUSHR_EOQ(command->isEndOfQueue) | - BF_SPI_PUSHR_CTCNT(command->clearTransferCount) | - BF_SPI_PUSHR_TXDATA(data); - - HW_SPI_PUSHR_WR(baseAddr, temp); - - /* Wait till TCF sets */ - while(BR_SPI_SR_TCF(baseAddr) == 0) { } -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h deleted file mode 100644 index 5fa1587e798..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h +++ /dev/null @@ -1,900 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_DSPI_HAL_H__) -#define __FSL_DSPI_HAL_H__ - -#include -#include -#include "fsl_dspi_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup dspi_hal - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ -static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 }; -static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, - 4096, 8192, 16384, 32768 }; - -static const uint32_t s_delayPrescaler[] = { 1, 3, 5, 7 }; -static const uint32_t s_delayScaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, - 4096, 8192, 16384, 32768, 65536 }; - - -/*! @brief Error codes for the DSPI driver.*/ -typedef enum _dspi_status -{ - kStatus_DSPI_Success = 0, - kStatus_DSPI_SlaveTxUnderrun, /*!< DSPI Slave Tx Under run error*/ - kStatus_DSPI_SlaveRxOverrun, /*!< DSPI Slave Rx Overrun error*/ - kStatus_DSPI_Timeout, /*!< DSPI transfer timed out*/ - kStatus_DSPI_Busy, /*!< DSPI instance is already busy performing a - transfer.*/ - kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer - was in progress*/ - kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/ - kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/ - kStatus_DSPI_OutOfRange /*!< DSPI out-of-range error used in slave callback */ -} dspi_status_t; - -/*! @brief DSPI master or slave configuration*/ -typedef enum _dspi_master_slave_mode { - kDspiMaster = 1, /*!< DSPI peripheral operates in master mode*/ - kDspiSlave = 0 /*!< DSPI peripheral operates in slave mode*/ -} dspi_master_slave_mode_t; - -/*! @brief DSPI clock polarity configuration for a given CTAR*/ -typedef enum _dspi_clock_polarity { - kDspiClockPolarity_ActiveHigh = 0, /*!< Active-high DSPI clock (idles low)*/ - kDspiClockPolarity_ActiveLow = 1 /*!< Active-low DSPI clock (idles high)*/ -} dspi_clock_polarity_t; - -/*! @brief DSPI clock phase configuration for a given CTAR*/ -typedef enum _dspi_clock_phase { - kDspiClockPhase_FirstEdge = 0, /*!< Data is captured on the leading edge of the SCK and - changed on the following edge.*/ - kDspiClockPhase_SecondEdge = 1 /*!< Data is changed on the leading edge of the SCK and - captured on the following edge.*/ -} dspi_clock_phase_t; - -/*! @brief DSPI data shifter direction options for a given CTAR*/ -typedef enum _dspi_shift_direction { - kDspiMsbFirst = 0, /*!< Data transfers start with most significant bit.*/ - kDspiLsbFirst = 1 /*!< Data transfers start with least significant bit.*/ -} dspi_shift_direction_t; - -/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/ -typedef enum _dspi_ctar_selection { - kDspiCtar0 = 0, /*!< CTAR0 selection option for master or slave mode*/ - kDspiCtar1 = 1 /*!< CTAR1 selection option for master mode only*/ -} dspi_ctar_selection_t; - -/*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/ -typedef enum _dspi_pcs_polarity_config { - kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low)*/ - kDspiPcs_ActiveLow = 1 /*!< PCS Active Low (idles high)*/ -} dspi_pcs_polarity_config_t; - -/*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/ -typedef enum _dspi_which_pcs_config { - kDspiPcs0 = 1 << 0, /*!< PCS[0] */ - kDspiPcs1 = 1 << 1, /*!< PCS[1] */ - kDspiPcs2 = 1 << 2, /*!< PCS[2] */ - kDspiPcs3 = 1 << 3, /*!< PCS[3] */ - kDspiPcs4 = 1 << 4, /*!< PCS[4] */ - kDspiPcs5 = 1 << 5 /*!< PCS[5] */ -} dspi_which_pcs_config_t; - -/*! - * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer - * Format. This field is valid only when CPHA bit in CTAR register is 0. - */ -typedef enum _dspi_master_sample_point { - kDspiSckToSin_0Clock = 0, /*!< 0 system clocks between SCK edge and SIN sample*/ - kDspiSckToSin_1Clock = 1, /*!< 1 system clock between SCK edge and SIN sample*/ - kDspiSckToSin_2Clock = 2 /*!< 2 system clocks between SCK edge and SIN sample*/ -} dspi_master_sample_point_t; - -/*! @brief DSPI FIFO selects*/ -typedef enum _dspi_fifo { - kDspiTxFifo = 0, /*!< DSPI Tx FIFO*/ - kDspiRxFifo = 1 /*!< DSPI Rx FIFO.*/ -} dspi_fifo_t; - -/*! @brief DSPI Tx FIFO Fill and Rx FIFO Drain DMA or Interrupt configuration */ -typedef enum _dspi_dma_or_int_mode { - kDspiGenerateIntReq = 0, /*!< Desired flag generates an Interrupt request */ - kDspiGenerateDmaReq = 1 /*!< Desired flag generates a DMA request */ -} dspi_dma_or_int_mode_t; - -/*! @brief DSPI status flags and interrupt request enable*/ -typedef enum _dspi_status_and_interrupt_request { - kDspiTxComplete = BP_SPI_RSER_TCF_RE, /*!< TCF status/interrupt enable */ - kDspiTxAndRxStatus = BP_SPI_SR_TXRXS, /*!< TXRXS status only, no interrupt*/ - kDspiEndOfQueue = BP_SPI_RSER_EOQF_RE, /*!< EOQF status/interrupt enable*/ - kDspiTxFifoUnderflow = BP_SPI_RSER_TFUF_RE, /*!< TFUF status/interrupt enable*/ - kDspiTxFifoFillRequest = BP_SPI_RSER_TFFF_RE, /*!< TFFF status/interrupt enable*/ - kDspiRxFifoOverflow = BP_SPI_RSER_RFOF_RE, /*!< RFOF status/interrupt enable*/ - kDspiRxFifoDrainRequest = BP_SPI_RSER_RFDF_RE /*!< RFDF status/interrupt enable*/ -} dspi_status_and_interrupt_request_t; - -/*! @brief DSPI FIFO counter or pointer defines based on bit positions*/ -typedef enum _dspi_fifo_counter_pointer { - kDspiRxFifoPointer = BP_SPI_SR_POPNXTPTR, /*!< Rx FIFO pointer*/ - kDspiRxFifoCounter = BP_SPI_SR_RXCTR, /*!< Rx FIFO counter*/ - kDspiTxFifoPointer = BP_SPI_SR_TXNXTPTR, /*!< Tx FIFO pointer*/ - kDspiTxFifoCounter = BP_SPI_SR_TXCTR /*!< Tx FIFO counter*/ -} dspi_fifo_counter_pointer_t; - -/*! @brief DSPI delay type selection*/ -typedef enum _dspi_delay_type { - kDspiPcsToSck = 1, /*!< PCS-to-SCK delay */ - kDspiLastSckToPcs = 2, /*!< Last SCK edge to PCS delay */ - kDspiAfterTransfer = 3, /*!< Delay between transfers */ -} dspi_delay_type_t; - -/*! - * @brief DSPI data format settings configuration structure - * - * This structure contains the data format settings. These settings apply to a specific - * CTARn register, which the user must provide in this structure. - */ -typedef struct DspiDataFormatConfig { - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16 (master), 32 (slave) */ - dspi_clock_polarity_t clkPolarity; /*!< Active high or low clock polarity*/ - dspi_clock_phase_t clkPhase; /*!< Clock phase setting to change and capture data*/ - dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction - This setting relevant only in master mode and - can be ignored in slave mode */ -} dspi_data_format_config_t; - -/*! - * @brief DSPI hardware configuration settings for slave mode. - * - * Use an instance of this structure with the DSPI_HAL_SlaveInit() to configure the - * most common settings of the DSPI peripheral in slave mode with a single function call. - */ -typedef struct DspiSlaveConfig { - bool isEnabled; /*!< Set to true to enable the DSPI peripheral. */ - dspi_data_format_config_t dataConfig; /*!< Data format configuration structure */ - bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */ - bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */ -} dspi_slave_config_t; - -/*! - * @brief DSPI baud rate divisors settings configuration structure. - * - * Note: These settings are relevant only in master mode. - * This structure contains the baud rate divisor settings, which provides the user with the option - * to explicitly set these baud rate divisors. In addition, the user must also set the - * CTARn register with the divisor settings. - */ -typedef struct DspiBaudRateDivisors { - bool doubleBaudRate; /*!< Double Baud rate parameter setting */ - uint32_t prescaleDivisor; /*!< Baud Rate Pre-scalar parameter setting*/ - uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */ -} dspi_baud_rate_divisors_t; - -/*! - * @brief DSPI command and data configuration structure - * - * Note: This structure is used with the PUSHR register, which - * provides the means to write to the Tx FIFO. Data written to this register is - * transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all - * 32 register bits to the Tx FIFO. The register structure is different in master and slave - * modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx - * FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI - * frame operation. - */ -typedef struct DspiCommandDataConfig { - bool isChipSelectContinuous; /*!< Option to enable the continuous assertion of chip select - between transfers*/ - dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes - Register (CTAR) to use for CTAS*/ - dspi_which_pcs_config_t whichPcs; /*!< The desired PCS signal to use for the data transfer*/ - bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue*/ - bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/ -} dspi_command_config_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -extern const uint32_t spi_base_addr[]; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Configuration - * @{ - */ - -/*! - * @brief Restores the DSPI to reset the configuration. - * - * This function basically resets all of the DSPI registers to their default setting including - * disabling the module. - * - * @param baseAddr Module base address - */ -void DSPI_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. - * - * @param baseAddr Module base address - */ -static inline void DSPI_HAL_Enable(uint32_t baseAddr) -{ - BW_SPI_MCR_MDIS(baseAddr, 0); -} - -/*! - * @brief Disables the DSPI peripheral, sets MCR MDIS to 1. - * - * @param baseAddr Module base address - */ -static inline void DSPI_HAL_Disable(uint32_t baseAddr) -{ - BW_SPI_MCR_MDIS(baseAddr, 1); -} - -/*! - * @brief Sets the DSPI baud rate in bits per second. - * - * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest - * possible baud rate without exceeding the desired baud rate, and returns the calculated - * baud rate in bits-per-second. It requires that the caller also provide the frequency of the - * module source clock (in Hertz). - * - * @param baseAddr Module base address - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type - * dspi_ctar_selection_t - * @param bitsPerSec The desired baud rate in bits per second - * @param sourceClockInHz Module source input clock in Hertz - * @return The actual calculated baud rate - */ -uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, - uint32_t bitsPerSec, uint32_t sourceClockInHz); - -/*! - * @brief Configures the baud rate divisors manually. - * - * This function allows the caller to manually set the baud rate divisors in the event that - * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function. - * - * @param baseAddr Module base address - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type - * dspi_ctar_selection_t - * @param divisors Pointer to a structure containing the user defined baud rate divisor settings - */ -void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr, - dspi_ctar_selection_t whichCtar, - const dspi_baud_rate_divisors_t * divisors); - -/*! - * @brief Configures the DSPI for master or slave. - * - * @param baseAddr Module base address - * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t - */ -static inline void DSPI_HAL_SetMasterSlaveMode(uint32_t baseAddr, dspi_master_slave_mode_t mode) -{ - BW_SPI_MCR_MSTR(baseAddr, (uint32_t)mode); -} - -/*! - * @brief Returns whether the DSPI module is in master mode. - * - * @param baseAddr Module base address - * @retval true The module is in master mode. - * @retval false The module is in slave mode. - */ -static inline bool DSPI_HAL_IsMaster(uint32_t baseAddr) -{ - return (bool)BR_SPI_MCR_MSTR(baseAddr); -} - -/*! - * @brief Configures the DSPI for the continuous SCK operation. - * - * @param baseAddr Module base address - * @param enable Enables (true) or disables(false) continuous SCK operation. - */ -static inline void DSPI_HAL_SetContinuousSckCmd(uint32_t baseAddr, bool enable) -{ - BW_SPI_MCR_CONT_SCKE(baseAddr, (enable == true)); -} - -/*! - * @brief Configures the DSPI to enable modified timing format. - * - * @param baseAddr Module base address - * @param enable Enables (true) or disables(false) modified timing format. - */ -static inline void DSPI_HAL_SetModifiedTimingFormatCmd(uint32_t baseAddr, bool enable) -{ - BW_SPI_MCR_MTFE(baseAddr, (enable == true)); -} - -/*! - * @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the - * active-low PCS Strobe output. - * - * PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral - * Chip Select in master mode. When configured as a strobe, it provides a signal to an external - * demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals. - * - * @param baseAddr Module base address - * @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe - * If disable (false), PCS[5] operates as a peripheral chip select - */ -static inline void DSPI_HAL_SetPcsStrobeCmd(uint32_t baseAddr, bool enable) -{ - BW_SPI_MCR_PCSSE(baseAddr, (enable == true)); -} - -/*! - * @brief Configures the DSPI received FIFO overflow overwrite enable. - * - * When enabled, this function allows incoming receive data to overwrite the existing data in the - * receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data - * is ignored when the RX FIFO is full. - * - * @param baseAddr Module base address. - * @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full, - * else incoming data is ignored. - */ -static inline void DSPI_HAL_SetRxFifoOverwriteCmd(uint32_t baseAddr, bool enable) -{ - BW_SPI_MCR_ROOE(baseAddr, (enable == true)); -} - -/*! - * @brief Configures the DSPI peripheral chip select polarity. - * - * This function takes in the desired peripheral chip select (PCS) and it's - * corresponding desired polarity and configures the PCS signal to operate with the - * desired characteristic. - * - * @param baseAddr Module base address - * @param pcs The particular peripheral chip select (parameter value is of type - * dspi_which_pcs_config_t) for which we wish to apply the active high or active - * low characteristic. - * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or - * "active low, inactive high(1)" of type dspi_pcs_polarity_config_t. - */ -void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs, - dspi_pcs_polarity_config_t activeLowOrHigh); - -/*! - * @brief Enables (or disables) the DSPI FIFOs. - * - * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently). - * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO - * configuration. To enable, the caller must pass in a logic 1 (true). - * - * @param baseAddr Module instance number - * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO - * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO - */ -void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo); - -/*! - * @brief Flushes the DSPI FIFOs. - * - * @param baseAddr Module base address - * @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO - * @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO - */ -void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo); - - -/*! - * @brief Configures the time when the DSPI master samples SIN in the Modified Transfer Format. - * - * This function controls when the DSPI master samples SIN (data in) in the Modified Transfer - * Format. Note that this is valid only when the CPHA bit in the CTAR register is 0. - * - * @param baseAddr Module base address - * @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t. - * This value selects either 0, 1, or 2 system clocks between the SCK edge - * and the SIN (data in) sample. - */ -static inline void DSPI_HAL_SetDatainSamplepointMode(uint32_t baseAddr, - dspi_master_sample_point_t samplePnt) -{ - BW_SPI_MCR_SMPL_PT(baseAddr, samplePnt); -} - - -/*! - * @brief Starts the DSPI transfers, clears HALT bit in MCR. - * - * This function call called whenever the module is ready to begin data transfers in either master - * or slave mode. - * - * @param baseAddr Module base address - */ -static inline void DSPI_HAL_StartTransfer(uint32_t baseAddr) -{ - BW_SPI_MCR_HALT(baseAddr, 0); -} - -/*! - * @brief Stops (halts) DSPI transfers, sets HALT bit in MCR. - * - * This function call stops data transfers in either master or slave mode. - * - * @param baseAddr Module base address - */ -static inline void DSPI_HAL_StopTransfer(uint32_t baseAddr) -{ - BW_SPI_MCR_HALT(baseAddr, 1); -} - -/*! - * @brief Configures the data format for a particular CTAR. - * - * This function configures the bits-per-frame, polarity, phase, and shift direction for a - * particular CTAR. An example use case is as follows: - @code - dspi_data_format_config_t dataFormat; - dataFormat.bitsPerFrame = 16; - dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow; - dataFormat.clkPhase = kDspiClockPhase_FirstEdge; - dataFormat.direction = kDspiMsbFirst; - DSPI_HAL_SetDataFormat(instance, kDspiCtar0, &dataFormat); - @endcode - * - * @param baseAddr Module base address - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type - * dspi_ctar_selection_t. - * @param config Pointer to structure containing user defined data format configuration settings. - * @return An error code or kStatus_DSPI_Success - */ -dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr, - dspi_ctar_selection_t whichCtar, - const dspi_data_format_config_t * config); - -/*! - * @brief Manually configures the delay prescaler and scaler for a particular CTAR. - * - * This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), - * after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay - * after transfer pre-scalar (PDT)and scalar (DT). - * - * These delay names are available in type dspi_delay_type_t. - * - * The user passes which delay they want to configure along with the prescaler and scaler value. - * This allows the user to directly set the prescaler/scaler values if they have - * pre-calculated them or if they simply wish to manually increment either value. - * - * @param baseAddr Module base address - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type - * dspi_ctar_selection_t. - * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). - * @param prescaler The scaler delay value (can be any integer between 0 to 15). - * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t - */ -void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler, - uint32_t scaler, dspi_delay_type_t whichDelay); - - -/*! - * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. - * - * This function calculates the values for: - * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or - * After SCK delay pre-scalar (PASC) and scalar (ASC), or - * Delay after transfer pre-scalar (PDT)and scalar (DT). - * - * These delay names are available in type dspi_delay_type_t. - * - * The user passes which delay they want to configure along with the desired delay value in - * nano-seconds. The function calculates the values needed for the prescaler and scaler and - * returning the actual calculated delay as an exact delay match may not be possible. In this - * case, the closest match is calculated without going below the desired delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in - * which case the maximum supported delay will be returned. It is to the higher level - * peripheral driver to alert the user of an out of range delay input. - * - * @param baseAddr Module base address - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type - * dspi_ctar_selection_t. - * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t - * @param sourceClockInHz Module source input clock in Hertz - * @param delayInNanoSec The desired delay value in nano-seconds. - * @return The actual calculated delay value. - */ -uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, - dspi_delay_type_t whichDelay, uint32_t sourceClockInHz, - uint32_t delayInNanoSec); - -/*@}*/ - -/*! - * @name Low power - * @{ - */ - -/*! - * @brief Configures the DSPI operation during doze mode. - * - * This function provides support for an externally controlled doze mode, power-saving, mechanism. - * When disabled, the doze mode has no effect on the DSPI, and when enabled, the Doze mode - * disables the DSPI. - * - * @param baseAddr Module base address - * @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true), - * the doze mode disables the DSPI. - */ -static inline void DSPI_HAL_SetDozemodeCmd(uint32_t baseAddr, bool enable) -{ - BW_SPI_MCR_DOZE(baseAddr, (enable == true)); -} - -/*@}*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Configures the DSPI Tx FIFO fill request to generate DMA or interrupt requests. - * - * This function configures the DSPI Tx FIFO Fill flag to generate either - * an interrupt or DMA request. The user passes in which request they'd like to generate - * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request. - * Note, when disabling the request, the request type is don't care. - @code - DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA - DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt - DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable - @endcode - * @param baseAddr Module base address - * @param mode Configures the DSPI Tx FIFO Fill to generate an interrupt or DMA request - * @param enable Enable (true) or disable (false) the DSPI Tx FIFO Fill flag to generate requests - */ -void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable); - -/*! - * @brief Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests. - * - * This function configures the DSPI Rx FIFO Drain flag to generate either - * an interrupt or a DMA request. The user passes in which request they'd like to generate - * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request. - * Note, when disabling the request, the request type is don't care. - @code - DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA - DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt - DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable - @endcode - * @param baseAddr Module base address - * @param mode Configures the Rx FIFO Drain to generate an interrupt or DMA request - * @param enable Enable (true) or disable (false) the Rx FIFO Drain flag to generate requests - */ -void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable); - - - -/*! - * @brief Configures the DSPI interrupts. - * - * This function configures the various interrupt sources of the DSPI. The parameters are - * baseAddr, interrupt source, and enable/disable setting. - * The interrupt source is a typedef enumeration whose value is the bit position of the - * interrupt source setting within the RSER register. In the DSPI, all interrupt - * configuration settings are in one register. The typedef enum equates each - * interrupt source to the bit position defined in the device header file. - * The function uses these bit positions in its algorithm to enable/disable the - * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type. - * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions: - * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as - * these requests can generate either an interrupt or DMA request. - @code - DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case - @endcode - * - * @param baseAddr Module base address - * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t - * @param enable Enable (true) or disable (false) the interrupt source to generate requests - */ -void DSPI_HAL_SetIntMode(uint32_t baseAddr, - dspi_status_and_interrupt_request_t interruptSrc, - bool enable); - - -/*! - * @brief Gets DSPI interrupt configuration, returns if interrupt request is enabled or disabled. - * - * This function returns the requested interrupt source setting (enabled or disabled, of - * type bool). The parameters to pass in are baseAddr and interrupt source. It utilizes the - * same enumeration definitions for the interrupt sources as described in the "interrupt configuration" - * function. The function uses these bit positions in its algorithm to obtain the desired - * interrupt source setting. - * Note, for Tx FIFO Fill and Rx FIFO Drain requests, this returns whether or not their - * requests are enabled. - @code - getInterruptSetting = DSPI_HAL_GetIntMode(baseAddr, kDspiTxComplete); - @endcode - * - * @param baseAddr Module base address - * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t - * @return Configuration of interrupt request: enable (true) or disable (false). - */ -static inline bool DSPI_HAL_GetIntMode(uint32_t baseAddr, - dspi_status_and_interrupt_request_t interruptSrc) -{ - return ((HW_SPI_RSER_RD(baseAddr) >> interruptSrc) & 0x1); -} - -/*@}*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the DSPI status flag state. - * - * The status flag is defined in the same enumeration as the interrupt source enable because the bit - * position of the interrupt source and corresponding status flag are the same in the RSER and - * SR registers. The function uses these bit positions in its algorithm to obtain the desired - * flag state, similar to the dspi_get_interrupt_config function. - @code - getStatus = DSPI_HAL_GetStatusFlag(baseAddr, kDspiTxComplete); - @endcode - * - * @param baseAddr Module base address - * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t - * @return State of the status flag: asserted (true) or not-asserted (false) - */ -static inline bool DSPI_HAL_GetStatusFlag(uint32_t baseAddr, - dspi_status_and_interrupt_request_t statusFlag) -{ - return ((HW_SPI_SR_RD(baseAddr) >> statusFlag) & 0x1); -} - -/*! - * @brief Clears the DSPI status flag. - * - * This function clears the desired status bit by using a write-1-to-clear. The user passes in - * the baseAddr and the desired status bit to clear. The list of status bits is defined in the - * dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm - * to clear the desired flag state. Example usage: - @code - DSPI_HAL_ClearStatusFlag(baseAddr, kDspiTxComplete); - @endcode - * - * @param baseAddr Module base address - * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t - */ -static inline void DSPI_HAL_ClearStatusFlag(uint32_t baseAddr, - dspi_status_and_interrupt_request_t statusFlag) -{ - HW_SPI_SR_SET(baseAddr, (0x1U << statusFlag)); -} - - -/*! - * @brief Gets the DSPI FIFO counter or pointer. - * - * This function returns the number of entries or the next pointer in the Tx or Rx FIFO. - * The parameters to pass in are the baseAddr and either the Tx or Rx FIFO counter or a - * pointer. The latter is an enumeration type defined as the bitmask of - * those particular bit fields found in the device header file. Example usage: - @code - DSPI_HAL_GetFifoCountOrPtr(baseAddr, kDspiRxFifoCounter); - @endcode - * - * @param baseAddr Module base address - * @param desiredParameter Desired parameter to obtain, of type dspi_fifo_counter_pointer_t - */ -static inline uint32_t DSPI_HAL_GetFifoCountOrPtr(uint32_t baseAddr, - dspi_fifo_counter_pointer_t desiredParameter) -{ - return ((HW_SPI_SR_RD(baseAddr) >> desiredParameter) & 0xFU); -} - - -/*@}*/ - -/*! - * @name Data transfer - * @{ - */ - -/*! - * @brief Reads data from the data buffer. - * - * @param baseAddr Module base address - */ -static inline uint32_t DSPI_HAL_ReadData(uint32_t baseAddr) -{ - return HW_SPI_POPR_RD(baseAddr); -} - -/*! - * @brief Writes data into the data buffer, slave mode. - * - * In slave mode, up to 32-bit words may be written. - * - * @param baseAddr Module base address - * @param data The data to send - */ -static inline void DSPI_HAL_WriteDataSlavemode(uint32_t baseAddr, uint32_t data) -{ - HW_SPI_PUSHR_SLAVE_WR(baseAddr, data); -} - -/*! - * @brief Writes data into the data buffer, master mode. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data such as: optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example: - @code - dspi_command_config_t commandConfig; - commandConfig.isChipSelectContinuous = true; - commandConfig.whichCtar = kDspiCtar0; - commandConfig.whichPcs = kDspiPcs1; - commandConfig.clearTransferCount = false; - commandConfig.isEndOfQueue = false; - DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord); - @endcode - * - * @param baseAddr Module base address - * @param command Pointer to command structure - * @param data The data word to be sent - */ -void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr, - dspi_command_config_t * command, - uint16_t data); - -/*! - * @brief Writes data into the data buffer, master mode and waits till complete to return. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data such as: optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example: - @code - dspi_command_config_t commandConfig; - commandConfig.isChipSelectContinuous = true; - commandConfig.whichCtar = kDspiCtar0; - commandConfig.whichPcs = kDspiPcs1; - commandConfig.clearTransferCount = false; - commandConfig.isEndOfQueue = false; - DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord); - @endcode - * - * Note that this function does not return until after the transmit is complete. Also note that - * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0). - * Since the SPI is a synchronous protocol, receive data is available when transmit completes. - * - * @param baseAddr Module base address - * @param command Pointer to command structure - * @param data The data word to be sent - */ -void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr, - dspi_command_config_t * command, - uint16_t data); - -/*! - * @brief Gets the transfer count. - * - * This function returns the current value of the DSPI Transfer Count Register. - * - * @param baseAddr Module base address - * @return The current transfer count - */ -static inline uint32_t DSPI_HAL_GetTransferCount(uint32_t baseAddr) -{ - return BR_SPI_TCR_SPI_TCNT(baseAddr); -} - -/*! - * @brief Pre-sets the transfer count. - * - * This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up - * to 65535; Incrementing past this resets the counter back to 0. - * - * @param baseAddr Module base address - * @param presetValue The desired pre-set value for the transfer counter - */ -static inline void DSPI_HAL_PresetTransferCount(uint32_t baseAddr, uint16_t presetValue) -{ - BW_SPI_TCR_SPI_TCNT(baseAddr, presetValue); -} - -/*@}*/ - -/*! - * @name Debug - * @{ - */ - -/*! - * @brief Reads FIFO registers for debug purposes. - * - * @param baseAddr Module base address - * @param whichFifo Selects Tx or Rx FIFO, of type dspi_fifo_t. - * @param whichFifoEntry Selects which FIFO entry to read: 0, 1, 2, or 3. - * @return The desired FIFO register contents - */ -uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry); - -/*! - * @brief Configures the DSPI to halt during debug mode. - * - * @param baseAddr Module base address - * @param enable Enables (true) debug mode to halt transfers, else disable to not halt transfer - * in debug mode. - */ -static inline void DSPI_HAL_SetHaltInDebugmodeCmd(uint32_t baseAddr, bool enable) -{ - BW_SPI_MCR_FRZ(baseAddr, (enable == true)); -} - -/* @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_DSPI_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h deleted file mode 100644 index 231d2a30b59..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h +++ /dev/null @@ -1,135 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_EDMA_FEATURES_H__) -#define __FSL_EDMA_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) - /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4) - /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) - /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) - /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4) - /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) - /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) -#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F256VLH12) || \ - defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || \ - defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || \ - defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ - defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || \ - defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \ - defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16) - /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) - /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ - defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16) - /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) - /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32) - /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) - /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) - /* @brief Total number of DMA channels on all modules. */ - #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32) - /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) - /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ - #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_EDMA_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c deleted file mode 100644 index b70eef7ccdc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c +++ /dev/null @@ -1,633 +0,0 @@ -/* -* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#include "fsl_edma_hal.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_Init - * Description : Initializes eDMA module to known state. - * - *END**************************************************************************/ -void EDMA_HAL_Init(uint32_t baseAddr) -{ - uint32_t i; - - /* Risk there, in SoCs with more than 1 group, we can't set the CR - * register to 0, or fault may happens. Stange that in K70 spec, - * the RM tell the reset value is 0. */ - HW_DMA_CR_WR(baseAddr, 0U); - - for (i = 0; i < FSL_FEATURE_EDMA_MODULE_CHANNEL; i++) - { - EDMA_HAL_HTCDClearReg(baseAddr, i); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_CancelTransfer - * Description : Cancels the remaining data transfer. - * - *END**************************************************************************/ -void EDMA_HAL_CancelTransfer(uint32_t baseAddr) -{ - BW_DMA_CR_CX(baseAddr, 1U); - while (BR_DMA_CR_CX(baseAddr)) - {} -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_ErrorCancelTransfer - * Description : Cancels the remaining data transfer and treat it as error. - * - *END**************************************************************************/ -void EDMA_HAL_ErrorCancelTransfer(uint32_t baseAddr) -{ - BW_DMA_CR_ECX(baseAddr, 1U); - while (BR_DMA_CR_ECX(baseAddr)) - {} -} - -#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U) -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_SetGroupPriority - * Description : - * - *END**************************************************************************/ -void EDMA_HAL_SetGroupPriority(uint32_t baseAddr, edma_group_priority_t groupPriority) -{ - - if (groupPriority == kEDMAGroup0PriorityLowGroup1PriorityHigh) - { - BW_DMA_CR_GRP0PRI(baseAddr, 0U); - BW_DMA_CR_GRP1PRI(baseAddr, 1U); - } - else - { - BW_DMA_CR_GRP0PRI(baseAddr, 1U); - BW_DMA_CR_GRP1PRI(baseAddr, 0U); - } - -} -#endif -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_SetErrorIntCmd - * Description : Enable/Disable error interrupt for channels. - * - *END**************************************************************************/ -void EDMA_HAL_SetErrorIntCmd(uint32_t baseAddr, bool enable, edma_channel_indicator_t channel) -{ - - if (enable) - { - HW_DMA_SEEI_WR(baseAddr, channel); - } - else - { - HW_DMA_CEEI_WR(baseAddr, channel); - } -} -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_SetDmaRequestCmd - * Description : Enable/Disable dma request for channel or all channels. - * - *END**************************************************************************/ -void EDMA_HAL_SetDmaRequestCmd(uint32_t baseAddr, edma_channel_indicator_t channel,bool enable) -{ - - if (enable) - { - HW_DMA_SERQ_WR(baseAddr, channel); - } - else - { - HW_DMA_CERQ_WR(baseAddr, channel); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_GetErrorIntCmd - * Description : Gets eDMA channel error interrupt enable status. - * - *END**************************************************************************/ -bool EDMA_HAL_GetErrorIntCmd(uint32_t baseAddr, uint32_t channel) -{ - return (bool)((HW_DMA_EEI_RD(baseAddr) >> channel) & 1U); -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCDClearReg - * Description : Set registers to 0 for hardware TCD of eDMA channel. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDClearReg(uint32_t baseAddr,uint32_t channel) -{ - HW_DMA_TCDn_SADDR_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_SOFF_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_ATTR_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_NBYTES_MLNO_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_SLAST_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_DADDR_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_DOFF_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_CITER_ELINKNO_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_DLASTSGA_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_CSR_WR(baseAddr, channel, 0U); - HW_DMA_TCDn_BITER_ELINKNO_WR(baseAddr, channel, 0U); -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCDSetAttribute - * Description : Configures the transfer attribute for eDMA channel. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDSetAttribute( - uint32_t baseAddr, uint32_t channel, - edma_modulo_t srcModulo, edma_modulo_t destModulo, - edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - HW_DMA_TCDn_ATTR_WR(baseAddr, channel, - BF_DMA_TCDn_ATTR_SMOD(srcModulo) | BF_DMA_TCDn_ATTR_DMOD(destModulo) | - BF_DMA_TCDn_ATTR_SSIZE(srcTransferSize) | BF_DMA_TCDn_ATTR_DSIZE(destTransferSize)); - -} -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_SetNbytes - * Description : Configures the nbytes for eDMA channel. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDSetNbytes(uint32_t baseAddr, uint32_t channel, uint32_t nbytes) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (BR_DMA_CR_EMLM(baseAddr)) - { - if (!(BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(baseAddr, channel) || - BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(baseAddr, channel))) - { - BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(baseAddr, channel, nbytes); - } - else - { - BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(baseAddr, channel, nbytes); - } - - } - else - { - BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(baseAddr, channel, nbytes); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_GetHTCDNbytes - * Description : Get nbytes configuration data. - * - *END**************************************************************************/ -uint32_t EDMA_HAL_HTCDGetNbytes(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (BR_DMA_CR_EMLM(baseAddr)) - { - if (BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(baseAddr, channel) || - BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(baseAddr, channel)) - { - return BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(baseAddr, channel); - } - else - { - return BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(baseAddr, channel); - } - } - else - { - return BR_DMA_TCDn_NBYTES_MLNO_NBYTES(baseAddr, channel); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCD_SetMinorLoopOffset - * Description : Configures the minorloop offset for the hardware TCD. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDSetMinorLoopOffset( - uint32_t baseAddr, uint32_t channel, edma_minorloop_offset_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - if ((config->enableSrcMinorloop == true) || (config->enableDestMinorloop == true)) - { - BW_DMA_CR_EMLM(baseAddr, true); - BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(baseAddr, channel, config->enableSrcMinorloop); - BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(baseAddr, channel, config->enableDestMinorloop); - BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(baseAddr, channel, config->offset); - } -} -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCDSetScatterGatherLink - * Description : Configures the memory address for the next transfer TCD for the hardware TCD. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDSetScatterGatherLink( - uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_ESG(baseAddr, channel, true); - BW_DMA_TCDn_DLASTSGA_DLASTSGA(baseAddr, channel, (uint32_t)stcd); -} -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCD_SetChannelMinorLink - * Description : Set Channel minor link for hardware TCD. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDSetChannelMinorLink( - uint32_t baseAddr, uint32_t channel, uint32_t linkChannel, bool enable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (enable) - { - BW_DMA_TCDn_BITER_ELINKYES_ELINK(baseAddr, channel, enable); - BW_DMA_TCDn_BITER_ELINKYES_LINKCH(baseAddr, channel, linkChannel); - BW_DMA_TCDn_CITER_ELINKYES_ELINK(baseAddr, channel, enable); - BW_DMA_TCDn_CITER_ELINKYES_LINKCH(baseAddr, channel, linkChannel); - } - else - { - BW_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel, enable); - BW_DMA_TCDn_CITER_ELINKNO_ELINK(baseAddr, channel, enable); - } -} -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCD_HTCDSetMajorCount - * Description : Sets the major iteration count according to minor loop channel link setting. - * - *END**************************************************************************/ -void EDMA_HAL_HTCDSetMajorCount(uint32_t baseAddr, uint32_t channel, uint32_t count) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel)) - { - BW_DMA_TCDn_BITER_ELINKYES_BITER(baseAddr, channel, count); - BW_DMA_TCDn_CITER_ELINKYES_CITER(baseAddr, channel, count); - } - else - { - BW_DMA_TCDn_BITER_ELINKNO_BITER(baseAddr, channel, count); - BW_DMA_TCDn_CITER_ELINKNO_CITER(baseAddr, channel, count); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCD_HTCDSetMajorCount - * Description : Gets the begin major iteration count according to minor loop channel link setting. - * - *END**************************************************************************/ -uint32_t EDMA_HAL_HTCDGetBeginMajorCount(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel)) - { - return BR_DMA_TCDn_BITER_ELINKYES_BITER(baseAddr, channel); - } - else - { - return BR_DMA_TCDn_BITER_ELINKNO_BITER(baseAddr, channel); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCD_HTCDGetCurrentMajorCount - * Description : Gets the current major iteration count according to minor loop channel link setting. - * - *END**************************************************************************/ -uint32_t EDMA_HAL_HTCDGetCurrentMajorCount(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel)) - { - return BR_DMA_TCDn_CITER_ELINKYES_CITER(baseAddr, channel); - } - else - { - return BR_DMA_TCDn_CITER_ELINKNO_CITER(baseAddr, channel); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCDGetUnfinishedBytes - * Description : Get the bytes number of bytes haven't been transferred for this hardware TCD. - * - *END**************************************************************************/ -uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t nbytes; - - nbytes = EDMA_HAL_HTCDGetNbytes(baseAddr, channel); - - if (BR_DMA_TCDn_BITER_ELINKNO_ELINK(baseAddr, channel)) - { - return (BR_DMA_TCDn_CITER_ELINKYES_CITER(baseAddr, channel) * nbytes); - - } - else - { - return (BR_DMA_TCDn_CITER_ELINKNO_CITER(baseAddr, channel) * nbytes); - - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_HTCDGetFinishedBytes - * Description : Get the bytes number of bytes already be transferred for this hardware TCD. - * - *END**************************************************************************/ -uint32_t EDMA_HAL_HTCDGetFinishedBytes(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t nbytes, begin_majorcount, current_majorcount; - - nbytes = EDMA_HAL_HTCDGetNbytes(baseAddr, channel); - begin_majorcount = EDMA_HAL_HTCDGetBeginMajorCount(baseAddr,channel); - current_majorcount = EDMA_HAL_HTCDGetCurrentMajorCount(baseAddr,channel); - - return ((begin_majorcount - current_majorcount) * nbytes); -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_STCDSetAttribute - * Description : Configures the transfer attribute for software TCD. - * - *END**************************************************************************/ -void EDMA_HAL_STCDSetAttribute( - edma_software_tcd_t *stcd, - edma_modulo_t srcModulo, edma_modulo_t destModulo, - edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize) -{ - assert(stcd); - - stcd->ATTR = DMA_ATTR_SMOD(srcModulo) | DMA_ATTR_DMOD(destModulo) | - DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize); -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_STCDSetNbytes - * Description : Configures the nbytes for software TCD - * - *END**************************************************************************/ -void EDMA_HAL_STCDSetNbytes(uint32_t baseAddr, edma_software_tcd_t *stcd, uint32_t nbytes) -{ - assert(stcd); - - if (BR_DMA_CR_EMLM(baseAddr)) - { - if (stcd->NBYTES.MLOFFNO | (DMA_NBYTES_MLOFFNO_SMLOE_MASK | DMA_NBYTES_MLOFFNO_DMLOE_MASK)) - { - stcd->NBYTES.MLOFFYES = (stcd->NBYTES.MLOFFYES & ~DMA_NBYTES_MLOFFYES_NBYTES_MASK) | - DMA_NBYTES_MLOFFYES_NBYTES(nbytes); - } - else - { - stcd->NBYTES.MLOFFNO = (stcd->NBYTES.MLOFFNO & ~DMA_NBYTES_MLOFFNO_NBYTES_MASK) | - DMA_NBYTES_MLOFFNO_NBYTES(nbytes); - } - } - else - { - stcd->NBYTES.MLNO = (stcd->NBYTES.MLNO & ~DMA_NBYTES_MLNO_NBYTES_MASK) | - DMA_NBYTES_MLNO_NBYTES(nbytes); - } - -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_STCDSetMinorLoopOffset - * Description : - * - *END**************************************************************************/ -void EDMA_HAL_STCDSetMinorLoopOffset( - uint32_t baseAddr, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config) -{ - assert(stcd); - stcd->NBYTES.MLOFFYES = (stcd->NBYTES.MLOFFYES & - ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK)) | - (((uint32_t)config->enableSrcMinorloop << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) | - ((uint32_t)config->enableDestMinorloop << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)); - - if ((config->enableSrcMinorloop == true) || (config->enableDestMinorloop == true)) - { - BW_DMA_CR_EMLM(baseAddr, true); - stcd->NBYTES.MLOFFYES = (stcd->NBYTES.MLOFFYES & ~DMA_NBYTES_MLOFFYES_MLOFF_MASK) | - DMA_NBYTES_MLOFFYES_MLOFF(config->offset); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : - * Description : - * - *END**************************************************************************/ -void EDMA_HAL_STCDSetScatterGatherLink( - edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd) -{ - assert(stcd); - assert(nextStcd); - EDMA_HAL_STCDSetScatterGatherCmd(stcd, true); - stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA((uint32_t)nextStcd); -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_STCDSetChannelMinorLink - * Description : - * - *END**************************************************************************/ -void EDMA_HAL_STCDSetChannelMinorLink( - edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable) -{ - assert(stcd); - - if (enable) - { - stcd->BITER.ELINKYES = (stcd->BITER.ELINKYES & ~DMA_BITER_ELINKYES_ELINK_MASK) | - ((uint32_t)enable << DMA_BITER_ELINKYES_ELINK_SHIFT); - stcd->BITER.ELINKYES = (stcd->BITER.ELINKYES & ~DMA_BITER_ELINKYES_LINKCH_MASK) | - DMA_BITER_ELINKYES_LINKCH(linkChannel); - stcd->CITER.ELINKYES = (stcd->CITER.ELINKYES & ~DMA_CITER_ELINKYES_ELINK_MASK) | - ((uint32_t)enable << DMA_CITER_ELINKYES_ELINK_SHIFT); - stcd->CITER.ELINKYES = (stcd->CITER.ELINKYES & ~DMA_CITER_ELINKYES_LINKCH_MASK) | - DMA_CITER_ELINKYES_LINKCH(linkChannel); - } - else - { - stcd->BITER.ELINKNO = (stcd->BITER.ELINKNO & ~DMA_BITER_ELINKNO_ELINK_MASK) | - ((uint32_t)enable << DMA_BITER_ELINKNO_ELINK_SHIFT); - stcd->CITER.ELINKNO = (stcd->CITER.ELINKNO & ~DMA_CITER_ELINKNO_ELINK_MASK) | - ((uint32_t)enable << DMA_CITER_ELINKNO_ELINK_SHIFT); - } -} -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_STCDSetMajorCount - * Description : Sets the major iteration count according to minor loop channel link setting. - * - *END**************************************************************************/ -void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count) -{ - assert(stcd); - - if (stcd->BITER.ELINKNO & DMA_BITER_ELINKNO_ELINK_MASK) - { - stcd->BITER.ELINKYES = (stcd->BITER.ELINKYES & ~DMA_BITER_ELINKYES_BITER_MASK) | - DMA_BITER_ELINKYES_BITER(count); - stcd->CITER.ELINKYES = (stcd->CITER.ELINKYES & ~DMA_CITER_ELINKYES_CITER_MASK) | - DMA_CITER_ELINKYES_CITER(count); - } - else - { - stcd->BITER.ELINKNO = (stcd->BITER.ELINKNO & ~DMA_BITER_ELINKNO_BITER_MASK) | - DMA_BITER_ELINKNO_BITER(count); - stcd->CITER.ELINKNO = (stcd->CITER.ELINKNO & ~DMA_CITER_ELINKNO_CITER_MASK) | - DMA_CITER_ELINKNO_CITER(count); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_PushSTCDToHTCD - * Description : Copy the configuration data from the software TCD to hardware TCD. - * - *END**************************************************************************/ -void EDMA_HAL_PushSTCDToHTCD(uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(stcd); - - HW_DMA_TCDn_SADDR_WR(baseAddr, channel, stcd->SADDR); - HW_DMA_TCDn_SOFF_WR(baseAddr, channel, stcd->SOFF); - HW_DMA_TCDn_ATTR_WR(baseAddr, channel, stcd->ATTR); - HW_DMA_TCDn_NBYTES_MLNO_WR(baseAddr, channel, stcd->NBYTES.MLNO); - HW_DMA_TCDn_SLAST_WR(baseAddr, channel, stcd->SLAST); - HW_DMA_TCDn_DADDR_WR(baseAddr, channel, stcd->DADDR); - HW_DMA_TCDn_DOFF_WR(baseAddr, channel, stcd->DOFF); - HW_DMA_TCDn_CITER_ELINKYES_WR(baseAddr, channel, stcd->CITER.ELINKYES); - HW_DMA_TCDn_DLASTSGA_WR(baseAddr, channel, stcd->DLAST_SGA); - HW_DMA_TCDn_CSR_WR(baseAddr, channel, stcd->CSR); - HW_DMA_TCDn_BITER_ELINKYES_WR(baseAddr, channel, stcd->BITER.ELINKYES); -} - -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_SetSTCDBasicTransfer - * Description : Set the basic transfer for software TCD. - * - *END**************************************************************************/ -edma_status_t EDMA_HAL_STCDSetBasicTransfer( - uint32_t baseAddr, edma_software_tcd_t *stcd, edma_transfer_config_t *config, - bool enableInt, bool disableDmaRequest) -{ - assert(stcd); - - EDMA_HAL_STCDSetSrcAddr(stcd, config->srcAddr); - EDMA_HAL_STCDSetDestAddr(stcd, config->destAddr); - - EDMA_HAL_STCDSetSrcOffset(stcd, config->srcOffset); - EDMA_HAL_STCDSetDestOffset(stcd, config->destOffset); - - EDMA_HAL_STCDSetAttribute(stcd, config->srcModulo, config->destModulo, - config->srcTransferSize, config->destTransferSize); - - EDMA_HAL_STCDSetSrcLastAdjust(stcd, config->srcLastAddrAdjust); - EDMA_HAL_STCDSetDestLastAdjust(stcd, config->destLastAddrAdjust); - EDMA_HAL_STCDSetNbytes(baseAddr, stcd, config->minorLoopCount); - EDMA_HAL_STCDSetMajorCount(stcd, config->majorLoopCount); - - EDMA_HAL_STCDSetIntCmd(stcd, enableInt); - EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd(stcd, disableDmaRequest); - return kStatus_EDMA_Success; -} - -#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U) -/*FUNCTION********************************************************************** - * - * Function Name : EDMA_HAL_SetAsyncRequestInStopModeCmd - * Description : Enables/Disables an asynchronous request in stop mode. - * - *END**************************************************************************/ -void EDMA_HAL_SetAsyncRequestInStopModeCmd(uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if(enable) - { - HW_DMA_EARS_SET(baseAddr, 1U << channel); - } - else - { - HW_DMA_EARS_CLR(baseAddr, 1U << channel); - } -} -#endif -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h deleted file mode 100644 index 901b6e62de1..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h +++ /dev/null @@ -1,1418 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __EDMA_HAL_H__ -#define __EDMA_HAL_H__ - -#include -#include -#include -#include "fsl_edma_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup edma_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Error code for the eDMA Driver. */ -typedef enum _edma_status { - kStatus_EDMA_Success = 0U, - kStatus_EDMA_InvalidArgument = 1U, /*!< Parameter is invalid. */ - kStatus_EDMA_Fail = 2U /*!< Failed operation. */ -} edma_status_t; - -/*! @brief eDMA channel arbitration algorithm used for selection among channels. */ -typedef enum _edma_channel_arbitration { - kEDMAChnArbitrationFixedPriority = 0U, /*!< Fixed Priority arbitration is used for selection - among channels. */ - kEDMAChnArbitrationRoundrobin /*!< Round-Robin arbitration is used for selection among - channels. */ -} edma_channel_arbitration_t; - -/*! @brief eDMA channel priority setting */ -typedef enum _edma_chn_priority { - kEDMAChnPriority0 = 0U, - kEDMAChnPriority1, - kEDMAChnPriority2, - kEDMAChnPriority3, - kEDMAChnPriority4, - kEDMAChnPriority5, - kEDMAChnPriority6, - kEDMAChnPriority7, - kEDMAChnPriority8, - kEDMAChnPriority9, - kEDMAChnPriority10, - kEDMAChnPriority11, - kEDMAChnPriority12, - kEDMAChnPriority13, - kEDMAChnPriority14, - kEDMAChnPriority15 -} edma_channel_priority_t; - -#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U) -/*! @brief eDMA group arbitration algorithm used for selection among channels. */ -typedef enum _edma_group_arbitration -{ - kEDMAGroupArbitrationFixedPriority = 0U, /*!< Fixed Priority arbitration is used for - selection among eDMA groups. */ - kEDMAGroupArbitrationRoundrobin /*!< Round-Robin arbitration is used for selection - among eDMA channels. */ -} edma_group_arbitration_t; - -/*! @brief eDMA group priority setting */ -typedef enum _edma_group_priority { - kEDMAGroup0PriorityLowGroup1PriorityHigh, /*!< eDMA group 0's priority is lower priority. - eDMA group 1's priority is higher priority. */ - kEDMAGroup0PriorityHighGroup1PriorityLow /*!< eDMA group 0's priority is higher priority. - eDMA group 1's priority is lower priority. */ -} edma_group_priority_t; -#endif - -/*! @brief eDMA modulo configuration */ -typedef enum _edma_modulo { - kEDMAModuloDisable = 0U, - kEDMAModulo2bytes, - kEDMAModulo4bytes, - kEDMAModulo8bytes, - kEDMAModulo16bytes, - kEDMAModulo32bytes, - kEDMAModulo64bytes, - kEDMAModulo128bytes, - kEDMAModulo256bytes, - kEDMAModulo512bytes, - kEDMAModulo1Kbytes, - kEDMAModulo2Kbytes, - kEDMAModulo4Kbytes, - kEDMAModulo8Kbytes, - kEDMAModulo16Kbytes, - kEDMAModulo32Kbytes, - kEDMAModulo64Kbytes, - kEDMAModulo128Kbytes, - kEDMAModulo256Kbytes, - kEDMAModulo512Kbytes, - kEDMAModulo1Mbytes, - kEDMAModulo2Mbytes, - kEDMAModulo4Mbytes, - kEDMAModulo8Mbytes, - kEDMAModulo16Mbytes, - kEDMAModulo32Mbytes, - kEDMAModulo64Mbytes, - kEDMAModulo128Mbytes, - kEDMAModulo256Mbytes, - kEDMAModulo512Mbytes, - kEDMAModulo1Gbytes, - kEDMAModulo2Gbytes -} edma_modulo_t; - -/*! @brief eDMA transfer configuration */ -typedef enum _edma_transfer_size { - kEDMATransferSize_1Bytes = 0x0U, - kEDMATransferSize_2Bytes = 0x1U, - kEDMATransferSize_4Bytes = 0x2U, - kEDMATransferSize_16Bytes = 0x4U, - kEDMATransferSize_32Bytes = 0x5U -} edma_transfer_size_t; - -/*! - * @brief eDMA transfer size configuration. - * - * This structure configures the basic source/destination transfer attribute. - * This figure shows the eDMA's transfer model: - * _________________________________________________ - * | Transfer Size | | - * Minor Loop |_______________| Major loop Count 1 | - * Count | Transfer Size | | - * ____________|_______________|____________________|--> Minor loop complete - * ____________________________________ - * | | | - * |_______________| Major Loop Count 2 | - * | | | - * |_______________|____________________|--> Minor loop Complete - * - * ---------------------------------------------------------> Major loop complete - * - */ -typedef struct EDMATransferConfig { - uint32_t srcAddr; /*!< Memory address pointing to the source data. */ - uint32_t destAddr; /*!< Memory address pointing to the destination data. */ - edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ - edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ - int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to - form the next-state value as each source read/write is - completed. */ - int16_t destOffset; - uint32_t srcLastAddrAdjust; /*!< Last source address adjustment. */ - uint32_t destLastAddrAdjust; /*!< Last destination address adjustment. Note here it is only - valid when scatter/gather feature is not enabled. */ - edma_modulo_t srcModulo; /*!< Source address modulo. */ - edma_modulo_t destModulo; /*!< Destination address modulo. */ - uint32_t minorLoopCount; /*!< Minor bytes transfer count. Number of bytes to be transferred - in each service request of the channel. */ - uint16_t majorLoopCount; /*!< Major iteration count. */ -} edma_transfer_config_t; - -/*! @brief eDMA channel configuration. */ -typedef enum _edma_channel_indicator { - kEDMAChannel0 = 0U, /*!< Channel 0. */ - kEDMAChannel1 = 1U, - kEDMAChannel2 = 2U, - kEDMAChannel3 = 3U, -#if (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U) - kEDMAChannel4 = 4U, - kEDMAChannel5 = 5U, - kEDMAChannel6 = 6U, - kEDMAChannel7 = 7U, - kEDMAChannel8 = 8U, - kEDMAChannel9 = 9U, - kEDMAChannel10 = 10U, - kEDMAChannel11 = 11U, - kEDMAChannel12 = 12U, - kEDMAChannel13 = 13U, - kEDMAChannel14 = 14U, - kEDMAChannel15 = 15U, -#endif -#if (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U) - kEDMAChannel16 = 16U, - kEDMAChannel17 = 17U, - kEDMAChannel18 = 18U, - kEDMAChannel19 = 19U, - kEDMAChannel20 = 20U, - kEDMAChannel21 = 21U, - kEDMAChannel22 = 22U, - kEDMAChannel23 = 23U, - kEDMAChannel24 = 24U, - kEDMAChannel25 = 25U, - kEDMAChannel26 = 26U, - kEDMAChannel27 = 27U, - kEDMAChannel28 = 28U, - kEDMAChannel29 = 29U, - kEDMAChannel30 = 30U, - kEDMAChannel31 = 31U, -#endif - kEDMAAllChannel = 64U -} edma_channel_indicator_t; - -/*! @brief eDMA TCD Minor loop mapping configuration */ -typedef struct EDMAMinorLoopOffsetConfig { - bool enableSrcMinorloop; /*!< Enable(true) or Disable(false) source minor loop offset. */ - bool enableDestMinorloop; /*!< Enable(true) or Disable(false) destination minor loop offset. */ - uint32_t offset; /*!< Offset for minor loop mapping. */ -} edma_minorloop_offset_config_t; - -/*! @brief Error status of the eDMA module */ -typedef union EDMAErrorStatusAll { - struct { - uint32_t destinationBusError : 1; /*!< Bus error on destination address */ - uint32_t sourceBusError : 1; /*!< Bus error on the SRC address */ - uint32_t scatterOrGatherConfigurationError : 1; /*!< Error on the Scatter/Gather address */ - uint32_t nbyteOrCiterConfigurationError : 1; /*!< NBYTES/CITER configuration error */ - uint32_t destinationOffsetError : 1; /*!< Destination offset error */ - uint32_t destinationAddressError : 1; /*!< Destination address error */ - uint32_t sourceOffsetError : 1; /*!< Source offset error */ - uint32_t sourceAddressError : 1; /*!< Source address error */ - uint32_t errorChannel : 5; /*!< Error channel number of the cancelled - channel number */ - uint32_t _reserved1 : 1; - uint32_t channelPriorityError : 1; /*!< Channel priority error */ - uint32_t groupPriorityError : 1; /*!< Group priority error */ - uint32_t transferCancelledError : 1; /*!< Transfer cancelled */ - uint32_t _reserved0 : 14; - uint32_t orOfAllError : 1; /*!< Logical OR all ERR status bits */ - } U; - uint32_t B; -} edma_error_status_all_t; - -/*! @brief Bandwidth control configuration */ -typedef enum _edma_bandwidth_config { - kEDMABandwidthStallNone = 0U, /*!< No eDMA engine stalls. */ - kEDMABandwidthStall4Cycle = 2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ - kEDMABandwidthStall8Cycle = 3U /*!< eDMA engine stalls for 8 cycles after each read/write. */ -} edma_bandwidth_config_t; - -/*! @brief eDMA TCD */ -typedef struct EDMASoftwareTcd { - uint32_t SADDR; - uint16_t SOFF; - uint16_t ATTR; - union { - uint32_t MLNO; - uint32_t MLOFFNO; - uint32_t MLOFFYES; - } NBYTES; - uint32_t SLAST; - uint32_t DADDR; - uint16_t DOFF; - union { - uint16_t ELINKNO; - uint16_t ELINKYES; - } CITER; - uint32_t DLAST_SGA; - uint16_t CSR; - union { - uint16_t ELINKNO; - uint16_t ELINKYES; - } BITER; -} edma_software_tcd_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA HAL driver module level operation - * @{ - */ - -/*! - * @brief Initializes eDMA module to known state. - * - * @param baseAddr Register base address for eDMA module. - */ -void EDMA_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Cancels the remaining data transfer. - * - * This function stops the executing channel and forces the minor loop - * to finish. The cancellation takes effect after the last write of the - * current read/write sequence. The CX clears itself after the cancel has - * been honored. This cancel retires the channel normally as if the minor - * loop had completed. - * - * @param baseAddr Register base address for eDMA module. - */ -void EDMA_HAL_CancelTransfer(uint32_t baseAddr); - -/*! - * @brief Cancels the remaining data transfer and treats it as an error condition. - * - * This function stops the executing channel and forces the minor loop - * to finish. The cancellation takes effect after the last write of the - * current read/write sequence. The CX clears itself after the cancel has - * been honored. This cancel retires the channel normally as if the minor - * loop had completed. Additional thing is to treat this operation as an error - * condition. - * - * @param baseAddr Register base address for eDMA module. - */ -void EDMA_HAL_ErrorCancelTransfer(uint32_t baseAddr); - -/*! - * @brief Halts/Un-halts the DMA Operations. - * - * This function stalls/un-stalls the start of any new channels. Executing channels are allowed - * to be completed. - * - * @param baseAddr Register base address for eDMA module. - * @param halt Halts (true) or un-halts (false) eDMA transfer. - */ -static inline void EDMA_HAL_SetHaltCmd(uint32_t baseAddr, bool halt) -{ - BW_DMA_CR_HALT(baseAddr, halt); -} - -/*! - * @brief Halts or does not halt the eDMA module when an error occurs. - * - * An error causes the HALT bit to be set. Subsequently, all service requests are ignored until the - * HALT bit is cleared. - * - * @param baseAddr Register base address for eDMA module. - * @param haltOnError Halts (true) or not halt (false) eDMA module when an error occurs. - */ -static inline void EDMA_HAL_SetHaltOnErrorCmd(uint32_t baseAddr, bool haltOnError) -{ - BW_DMA_CR_HOE(baseAddr, haltOnError); -} - -/*! - * @brief Enables/Disables the eDMA DEBUG mode. - * - * This function enables/disables the eDMA Debug mode. - * When in debug mode, the DMA stalls the start of a new - * channel. Executing channels are allowed to complete. Channel execution resumes - * either when the system exits debug mode or when the EDBG bit is cleared. - * - * @param baseAddr Register base address for eDMA module. - * @param enable Enables (true) or Disable (false) eDMA module debug mode. - */ -static inline void EDMA_HAL_SetDebugCmd(uint32_t baseAddr, bool enable) -{ - BW_DMA_CR_EDBG(baseAddr, enable); -} -/* @} */ - -/*! - * @name eDMA HAL driver channel priority and arbitration configuration. - * @{ - */ -/*! - * @brief Sets the preempt and preemption feature for the eDMA channel. - * - * This function sets the preempt and preemption features. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param preempt eDMA channel can't suspend a lower priority channel (true). eDMA channel can - * suspend a lower priority channel (false). - * @param preemption eDMA channel can be temporarily suspended by the service request of a higher - * priority channel (true). eDMA channel can't be suspended by a higher priority channel (false). - */ -static inline void EDMA_HAL_SetChannelPreemptMode( - uint32_t baseAddr, uint32_t channel, bool preempt, bool preemption) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_DCHPRIn_DPA(baseAddr, HW_DMA_DCHPRIn_CHANNEL(channel), preempt); - BW_DMA_DCHPRIn_ECP(baseAddr, HW_DMA_DCHPRIn_CHANNEL(channel), preemption); -} - -/*! - * @brief Sets the eDMA channel priority. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param priority Priority of the DMA channel. Different channels should have different priority - * setting inside a group. - */ -static inline void EDMA_HAL_SetChannelPriority( - uint32_t baseAddr, uint32_t channel, edma_channel_priority_t priority) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_DCHPRIn_CHPRI(baseAddr, HW_DMA_DCHPRIn_CHANNEL(channel), priority); -} -/*! - * @brief Sets the channel arbitration algorithm. - * - * @param baseAddr Register base address for eDMA module. - * @param channelArbitration Round-Robin way for fixed priority way. - */ -static inline void EDMA_HAL_SetChannelArbitrationMode( - uint32_t baseAddr, edma_channel_arbitration_t channelArbitration) -{ - BW_DMA_CR_ERCA(baseAddr, channelArbitration); -} - -#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U) -/*! - * @brief Configures the group priority. - * - * This function configures the priority for group 0 and group 1. - * - * @param baseAddr Register base address for eDMA module. - * @param groupPriority Group priority configuration. Note that each group get its own - * group priority. - */ -void EDMA_HAL_SetGroupPriority(uint32_t baseAddr, edma_group_priority_t groupPriority); - -/*! - * @brief Sets the eDMA group arbitration algorithm. - * - * @param baseAddr Register base address for eDMA module. - * @param groupArbitration Group arbitration way. Fixed-Priority way or Round-Robin way. - */ -static inline void EDMA_HAL_SetGroupArbitrationMode( - uint32_t baseAddr, edma_group_arbitration_t groupArbitration) -{ - BW_DMA_CR_ERGA(baseAddr, groupArbitration); -} -#endif -/* @} */ - -/*! - * @name eDMA HAL driver configuration and operation. - * @{ - */ -/*! - * @brief Enables/Disables the minor loop mapping. - * - * This function enables/disables the minor loop mapping feature. - * If enabled, the NBYTES is redefined to include the individual enable fields and the NBYTES field. The - * individual enable fields allow the minor loop offset to be applied to the source address, the - * destination address, or both. The NBYTES field is reduced when either offset is enabled. - * - * @param baseAddr Register base address for eDMA module. - * @param enable Enables (true) or Disable (false) minor loop mapping. - */ -static inline void EDMA_HAL_SetMinorLoopMappingCmd(uint32_t baseAddr, bool enable) -{ - BW_DMA_CR_EMLM(baseAddr, enable); -} - -/*! - * @brief Enables or disables the continuous transfer mode. - * - * This function enables or disables the continuous transfer. If set, a minor loop channel link - * does not go through the channel arbitration before being activated again. Upon minor loop - * completion, the channel activates again if that channel has a minor loop channel link enabled and - * the link channel is itself. - * - * @param baseAddr Register base address for eDMA module. - * @param continuous Enables (true) or Disable (false) continuous transfer mode. - */ -static inline void EDMA_HAL_SetContinuousLinkCmd(uint32_t baseAddr, bool continuous) -{ - BW_DMA_CR_CLM(baseAddr, continuous); -} - -/*! - * @brief Gets the error status of the eDMA module. - * - * @param baseAddr Register base address for eDMA module. - * @return Detailed information of the error type in the eDMA module. - */ -static inline uint32_t EDMA_HAL_GetErrorStatus(uint32_t baseAddr) -{ - return HW_DMA_ES_RD(baseAddr); -} - -/*! - * @brief Enables/Disables the error interrupt for channels. - * - * @param baseAddr Register base address for eDMA module. - * @param enable Enable(true) or Disable (false) error interrupt. - * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt - * will be enabled/disabled. - */ -void EDMA_HAL_SetErrorIntCmd(uint32_t baseAddr, bool enable, edma_channel_indicator_t channel); - -/*! - * @brief Checks whether the eDMA channel error interrupt is enabled or disabled. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return Error interrupt is enabled (true) or disabled (false). - */ -bool EDMA_HAL_GetErrorIntCmd(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Gets the eDMA error interrupt status. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return 32 bit variable indicating error channels. If error happens on eDMA channel n, the bit n - * of this variable is '1'. If not, the bit n of this variable is '0'. - */ -static inline uint32_t EDMA_HAL_GetErrorIntStatusFlag(uint32_t baseAddr) -{ - return HW_DMA_ERR_RD(baseAddr); -} - -/*! - * @brief Clears the error interrupt status for the eDMA channel or channels. - * - * @param baseAddr Register base address for eDMA module. - * @param enable Enable(true) or Disable (false) error interrupt. - * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt - * status will be cleared. - */ -static inline void EDMA_HAL_ClearErrorIntStatusFlag( - uint32_t baseAddr, edma_channel_indicator_t channel) -{ - HW_DMA_CERR_WR(baseAddr, channel); -} - -/*! - * @brief Enables/Disables the DMA request for the channel or all channels. - * - * @param baseAddr Register base address for eDMA module. - * @param enable Enable(true) or Disable (false) DMA request. - * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels DMA request - * are enabled/disabled. - */ -void EDMA_HAL_SetDmaRequestCmd(uint32_t baseAddr, edma_channel_indicator_t channel,bool enable); - -/*! - * @brief Checks whether the eDMA channel DMA request is enabled or disabled. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return DMA request is enabled (true) or disabled (false). - */ -static inline bool EDMA_HAL_GetDmaRequestCmd(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - return ((HW_DMA_ERQ_RD(baseAddr) >> channel) & 1U); -} - -/*! - * @brief Gets the eDMA channel DMA request status. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return Hardware request is triggered in this eDMA channel (true) or not be triggered in this - * channel (false). - */ -static inline bool EDMA_HAL_GetDmaRequestStatusFlag(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - return (((uint32_t)HW_DMA_HRS_RD(baseAddr) >> channel) & 1U); -} - -/*! - * @brief Clears the done status for a channel or all channels. - * - * @param baseAddr Register base address for eDMA module. - * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' done status will - * be cleared. - */ -static inline void EDMA_HAL_ClearDoneStatusFlag(uint32_t baseAddr, edma_channel_indicator_t channel) -{ - HW_DMA_CDNE_WR(baseAddr, channel); -} - -/*! - * @brief Triggers the eDMA channel. - * - * @param baseAddr Register base address for eDMA module. - * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels are tirggere. - */ -static inline void EDMA_HAL_TriggerChannelStart(uint32_t baseAddr, edma_channel_indicator_t channel) -{ - HW_DMA_SSRT_WR(baseAddr, channel); -} - -/*! - * @brief Gets the eDMA channel interrupt request status. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return Interrupt request happens in this eDMA channel (true) or not happen in this - * channel (false). - */ -static inline bool EDMA_HAL_GetIntStatusFlag(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - return (((uint32_t)HW_DMA_INT_RD(baseAddr) >> channel) & 1U); -} - -/*! - * @brief Gets the eDMA all channel's interrupt request status. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return Interrupt status flag of all channels. - */ -static inline uint32_t EDMA_HAL_GetAllIntStatusFlag(uint32_t baseAddr) -{ - return (uint32_t)HW_DMA_INT_RD(baseAddr); -} - -/*! - * @brief Clears the interrupt status for the eDMA channel or all channels. - * - * @param baseAddr Register base address for eDMA module. - * @param enable Enable(true) or Disable (false) error interrupt. - * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' interrupt - * status will be cleared. - */ -static inline void EDMA_HAL_ClearIntStatusFlag( - uint32_t baseAddr, edma_channel_indicator_t channel) -{ - HW_DMA_CINT_WR(baseAddr, channel); -} - -#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U) -/*! - * @brief Enables/Disables an asynchronous request in stop mode. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param enable Enable (true) or Disable (false) async DMA request. - */ -void EDMA_HAL_SetAsyncRequestInStopModeCmd(uint32_t baseAddr, uint32_t channel, bool enable); -#endif - -/* @} */ - -/*! - * @name eDMA HAL driver hardware TCD configuration functions. - * @{ - */ - -/*! - * @brief Clears all registers to 0 for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - */ -void EDMA_HAL_HTCDClearReg(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Configures the source address for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param address The pointer to the source memory address. - */ -static inline void EDMA_HAL_HTCDSetSrcAddr(uint32_t baseAddr, uint32_t channel, uint32_t address) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_SADDR_SADDR(baseAddr, channel, address); -} - -/*! - * @brief Configures the source address signed offset for the hardware TCD. - * - * Sign-extended offset applied to the current source address to form the next-state value as each - * source read is complete. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param offset signed-offset for source address. - */ -static inline void EDMA_HAL_HTCDSetSrcOffset(uint32_t baseAddr, uint32_t channel, int16_t offset) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_SOFF_SOFF(baseAddr, channel, offset); -} - -/*! - * @brief Configures the transfer attribute for the eDMA channel. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param srcModulo enumeration type for an allowed source modulo. The value defines a specific address range - * specified as the value after the SADDR + SOFF calculation is performed on the original register - * value. Setting this field provides the ability to implement a circular data. For data queues - * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD - * field should be set to the appropriate value for the queue, freezing the desired number of upper - * address bits. The value programmed into this field specifies the number of the lower address bits - * allowed to change. For a circular queue application, the SOFF is typically set to the transfer - * size to implement post-increment addressing with SMOD function restricting the addresses to a - * 0-modulo-size range. - * @param destModulo Enum type for an allowed destination modulo. - * @param srcTransferSize Enum type for source transfer size. - * @param destTransferSize Enum type for destination transfer size. - */ -void EDMA_HAL_HTCDSetAttribute( - uint32_t baseAddr, uint32_t channel, - edma_modulo_t srcModulo, edma_modulo_t destModulo, - edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize); - -/*! - * @brief Configures the nbytes for the eDMA channel. - * - * Note here that user need firstly configure the minor loop mapping feature and then call this - * function. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param nbytes Number of bytes to be transferred in each service request of the channel - */ -void EDMA_HAL_HTCDSetNbytes(uint32_t baseAddr, uint32_t channel, uint32_t nbytes); - -/*! - * @brief Gets the nbytes configuration data for the hardware TCD. - * - * This function decides whether the minor loop mapping is enabled or whether the source/dest - * minor loop mapping is enabled. Then, the nbytes are returned accordingly. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return nbytes configuration according to minor loop setting. - */ -uint32_t EDMA_HAL_HTCDGetNbytes(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Configures the minor loop offset for the hardware TCD. - * - * Configures both the enable bits and the offset value. If neither source nor destination offset is enabled, - * offset is not configured. Note here if source or destination offset is required, the eDMA module - * EMLM bit will be set in this function. User need to know this side effect. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param config Configuration data structure for the minor loop offset - */ -void EDMA_HAL_HTCDSetMinorLoopOffset( - uint32_t baseAddr, uint32_t channel, edma_minorloop_offset_config_t *config); - -/*! - * @brief Configures the last source address adjustment for the hardware TCD. - * - * Adjustment value added to the source address at the completion of the major iteration count. This - * value can be applied to restore the source address to the initial value, or adjust the address to - * reference the next data structure. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param size adjustment value - */ -static inline void EDMA_HAL_HTCDSetSrcLastAdjust(uint32_t baseAddr, uint32_t channel, int32_t size) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_SLAST_SLAST(baseAddr, channel, size); -} - -/*! - * @brief Configures the destination address for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param address The pointer to the destination address. - */ -static inline void EDMA_HAL_HTCDSetDestAddr(uint32_t baseAddr, uint32_t channel, uint32_t address) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_DADDR_DADDR(baseAddr, channel, address); -} - -/*! - * @brief Configures the destination address signed offset for the hardware TCD. - * - * Sign-extended offset applied to the current source address to form the next-state value as each - * destination write is complete. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param offset signed-offset - */ -static inline void EDMA_HAL_HTCDSetDestOffset(uint32_t baseAddr, uint32_t channel, int16_t offset) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_DOFF_DOFF(baseAddr, channel, offset); -} - -/*! - * @brief Configures the last source address adjustment. - * - * This function adds an adjustment value added to the source address at the completion of the major - * iteration count. This value can be applied to restore the source address to the initial value, or - * adjust the address to reference the next data structure. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param adjust adjustment value - */ -static inline void EDMA_HAL_HTCDSetDestLastAdjust( - uint32_t baseAddr, uint32_t channel, uint32_t adjust) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_DLASTSGA_DLASTSGA(baseAddr, channel, adjust); -} - -/*! - * @brief Configures the memory address for the next transfer TCD for the hardware TCD. - * - * - * This function enables the scatter/gather feature for the hardware TCD and configures the next - * TCD's address. This address points to the beginning of a 0-modulo-32 byte region containing - * the next transfer TCD to be loaded into this channel. The channel reload is performed as the - * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise, - * a configuration error is reported. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param stcd The pointer to the TCD to be linked to this hardware TCD. - */ -void EDMA_HAL_HTCDSetScatterGatherLink( - uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd); - -/*! - * @brief Configures the bandwidth for the hardware TCD. - * - * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the - * minor loop, it continuously generates read/write sequences until the minor count is exhausted. - * This field forces the eDMA to stall after the completion of each read/write access to control the - * bus request bandwidth seen by the crossbar switch. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param bandwidth enum type for bandwidth control - */ -static inline void EDMA_HAL_HTCDSetBandwidth( - uint32_t baseAddr, uint32_t channel, edma_bandwidth_config_t bandwidth) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_BWC(baseAddr, channel, bandwidth); -} - -/*! - * @brief Configures the major channel link the hardware TCD. - * - * If the major link is enabled, after the major loop counter is exhausted, the eDMA engine initiates a - * channel service request at the channel defined by these six bits by setting that channel start - * bits. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param majorChannel channel number for major link - * @param enable Enables (true) or Disables (false) channel major link. - */ -static inline void EDMA_HAL_HTCDSetChannelMajorLink( - uint32_t baseAddr, uint32_t channel, uint32_t majorChannel, bool enable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_MAJORLINKCH(baseAddr, channel, majorChannel); - BW_DMA_TCDn_CSR_MAJORELINK(baseAddr, channel, enable); -} - -/*! - * @brief Gets the major link channel for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return major link channel number - */ -static inline uint32_t EDMA_HAL_HTCDGetMajorLinkChannel(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - return BR_DMA_TCDn_CSR_MAJORLINKCH(baseAddr, channel); -} - -/*! - * @brief Enables/Disables the scatter/gather feature for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param enable Enables (true) /Disables (false) scatter/gather feature. - */ -static inline void EDMA_HAL_HTCDSetScatterGatherCmd( - uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_ESG(baseAddr, channel, enable); -} - -/*! - * @brief Checks whether the scatter/gather feature is enabled for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return True stand for enabled. False stands for disabled. - */ -static inline bool EDMA_HAL_HTCDGetScatterGatherCmd(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - return BR_DMA_TCDn_CSR_ESG(baseAddr, channel); - -} - -/*! - * @brief Disables/Enables the DMA request after the major loop completes for the hardware TCD. - * - * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the - * current major iteration count reaches zero. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param disable Disable (true)/Enable (true) DMA request after TCD complete. - */ -static inline void EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd( - uint32_t baseAddr, uint32_t channel, bool disable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_DREQ(baseAddr, channel, disable); -} - -/*! - * @brief Enables/Disables the half complete interrupt for the hardware TCD. - * - * If set, the channel generates an interrupt request by setting the appropriate bit in the - * interrupt register when the current major iteration count reaches the halfway point. Specifically, - * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point - * interrupt request is provided to support the double-buffered schemes or other types of data movement - * where the processor needs an early indication of the transfer's process. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param enable Enable (true) /Disable (false) half complete interrupt. - */ -static inline void EDMA_HAL_HTCDSetHalfCompleteIntCmd( - uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_INTHALF(baseAddr, channel, enable); -} - -/*! - * @brief Enables/Disables the interrupt after the major loop completes for the hardware TCD. - * - * If enabled, the channel generates an interrupt request by setting the appropriate bit in the - * interrupt register when the current major iteration count reaches zero. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param enable Enable (true) /Disable (false) interrupt after TCD done. - */ -static inline void EDMA_HAL_HTCDSetIntCmd( - uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_INTMAJOR(baseAddr, channel, enable); -} - -/*! - * @brief Triggers the start bits for the hardware TCD. - * - * The eDMA hardware automatically clears this flag after the channel begins execution. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - */ -static inline void EDMA_HAL_HTCDTriggerChannelStart(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - BW_DMA_TCDn_CSR_START(baseAddr, channel, true); -} - -/*! - * @brief Checks whether the channel is running for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return True stands for running. False stands for not. - */ -static inline bool EDMA_HAL_HTCDGetChannelActiveStatus(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - return BR_DMA_TCDn_CSR_ACTIVE(baseAddr, channel); -} - -/*! - * @brief Sets the channel minor link for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param linkChannel Channel to be linked on minor loop complete. - * @param enable Enable (true)/Disable (false) channel minor link. - */ -void EDMA_HAL_HTCDSetChannelMinorLink( - uint32_t baseAddr, uint32_t channel, uint32_t linkChannel, bool enable); - -/*! - * @brief Sets the major iteration count according to minor loop channel link setting. - * - * Note here that user need to first set the minor loop channel link and then call this function. - * The execute flow inside this function is dependent on the minor loop channel link setting. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param count major loop count - */ -void EDMA_HAL_HTCDSetMajorCount(uint32_t baseAddr, uint32_t channel, uint32_t count); - -/*! - * @brief Gets the number of beginning major counts for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return Begin major counts. - */ -uint32_t EDMA_HAL_HTCDGetBeginMajorCount(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Gets the number of current major counts for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return Current major counts. - */ -uint32_t EDMA_HAL_HTCDGetCurrentMajorCount(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Gets the number of bytes already transferred for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return data bytes already transferred - */ -uint32_t EDMA_HAL_HTCDGetFinishedBytes(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Gets the number of bytes haven't transferred for the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return data bytes already transferred - */ -uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(uint32_t baseAddr, uint32_t channel); - -/*! - * @brief Gets the channel done status. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @return If channel done. - */ -static inline bool EDMA_HAL_HTCDGetDoneStatusFlag(uint32_t baseAddr, uint32_t channel) -{ - return BR_DMA_TCDn_CSR_DONE(baseAddr,channel); -} - -/* @} */ - -/*! - * @name EDMA HAL driver software TCD configuration functions. - * @{ - */ -/*! - * @brief Configures the source address for the software TCD. - * - * @param stcd The pointer to the software TCD. - * @param channel eDMA channel number. - * @param address The pointer to the source memory address. - */ -static inline void EDMA_HAL_STCDSetSrcAddr(edma_software_tcd_t *stcd, uint32_t address) -{ - assert(stcd); - stcd->SADDR = DMA_SADDR_SADDR(address); -} - -/*! - * @brief Configures the source address signed offset for the software TCD. - * - * Sign-extended offset applied to the current source address to form the next-state value as each - * source read is complete. - * - * @param stcd The pointer to the software TCD. - * @param offset signed-offset for source address. - */ -static inline void EDMA_HAL_STCDSetSrcOffset(edma_software_tcd_t *stcd, int16_t offset) -{ - assert(stcd); - stcd->SOFF = DMA_SOFF_SOFF(offset); -} - -/*! - * @brief Configures the transfer attribute for software TCD. - * - * @param stcd The pointer to the software TCD. - * @param srcModulo enum type for an allowed source modulo. The value defines a specific address range - * specified as the value after the SADDR + SOFF calculation is performed on the original register - * value. Setting this field provides the ability to implement a circular data. For data queues - * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD - * field should be set to the appropriate value for the queue, freezing the desired number of upper - * address bits. The value programmed into this field specifies the number of the lower address bits - * allowed to change. For a circular queue application, the SOFF is typically set to the transfer - * size to implement post-increment addressing with SMOD function restricting the addresses to a - * 0-modulo-size range. - * @param destModulo Enum type for an allowed destination modulo. - * @param srcTransferSize Enum type for source transfer size. - * @param destTransferSize Enum type for destinatio transfer size. - */ -void EDMA_HAL_STCDSetAttribute( - edma_software_tcd_t *stcd, - edma_modulo_t srcModulo, edma_modulo_t destModulo, - edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize); - -/*! - * @brief Configures the nbytes for software TCD. - * - * Note here that user need firstly configure the minor loop mapping feature and then call this - * function. - * - * @param baseAddr Register base address for eDMA module. - * @param stcd The pointer to the software TCD. - * @param nbytes Number of bytes to be transferred in each service request of the channel - */ -void EDMA_HAL_STCDSetNbytes(uint32_t baseAddr, edma_software_tcd_t *stcd, uint32_t nbytes); - -/*! - * @brief Configures the minorloop offset for the software TCD. - * - * Configures both the enable bits and the offset value. If neither source nor dest offset is enabled, - * offset is not configured. Note here if source or destination offset is requred, the eDMA module - * EMLM bit will be set in this function. User need to know this side effect. - * - * @param baseAddr Register base address for eDMA module. - * @param stcd The pointer to the software TCD. - * @param config Configuration data structure for the minorloop offset - */ -void EDMA_HAL_STCDSetMinorLoopOffset( - uint32_t baseAddr, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config); - -/*! - * @brief Configures the last source address adjustment for the software TCD. - * - * Adjustment value added to the source address at the completion of the major iteration count. This - * value can be applied to restore the source address to the initial value, or adjust the address to - * reference the next data structure. - * - * @param stcd The pointer to the software TCD. - * @param size adjustment value - */ -static inline void EDMA_HAL_STCDSetSrcLastAdjust(edma_software_tcd_t *stcd, int32_t size) -{ - assert(stcd); - stcd->SLAST = (stcd->SLAST & ~DMA_SLAST_SLAST_MASK) | DMA_SLAST_SLAST(size); -} - -/*! - * @brief Configures the destination address for the software TCD. - * - * @param stcd The pointer to the software TCD. - * @param address The pointer to the destination addresss. - */ -static inline void EDMA_HAL_STCDSetDestAddr(edma_software_tcd_t *stcd, uint32_t address) -{ - assert(stcd); - stcd->DADDR = DMA_DADDR_DADDR(address); -} - -/*! - * @brief Configures the destination address signed offset for the software TCD. - * - * Sign-extended offset applied to the current source address to form the next-state value as each - * destination write is complete. - * - * @param stcd The pointer to the software TCD. - * @param offset signed-offset - */ -static inline void EDMA_HAL_STCDSetDestOffset(edma_software_tcd_t *stcd, int16_t offset) -{ - assert(stcd); - stcd->DOFF = DMA_DOFF_DOFF(offset); -} - -/*! - * @brief Configures the last source address adjustment. - * - * This function add an adjustment value added to the source address at the completion of the major - * iteration count. This value can be applied to restore the source address to the initial value, or - * adjust the address to reference the next data structure. - * - * @param stcd The pointer to the software TCD. - * @param adjust adjustment value - */ -static inline void EDMA_HAL_STCDSetDestLastAdjust( - edma_software_tcd_t *stcd, uint32_t adjust) -{ - assert(stcd); - stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA(adjust); -} - -/*! - * @brief Configures the memory address for the next transfer TCD for the software TCD. - * - * - * This function enable the scatter/gather feature for the software TCD and configure the next - * TCD's address.This address points to the beginning of a 0-modulo-32 byte region containing - * the next transfer TCD to be loaded into this channel. The channel reload is performed as the - * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise, - * a configuration error is reported. - * - * @param stcd The pointer to the software TCD. - * @param nextStcd The pointer to the TCD to be linked to this software TCD. - */ -void EDMA_HAL_STCDSetScatterGatherLink( - edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd); - -/*! - * @brief Configures the bandwidth for the software TCD. - * - * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the - * minor loop, it continuously generates read/write sequences until the minor count is exhausted. - * This field forces the eDMA to stall after the completion of each read/write access to control the - * bus request bandwidth seen by the crossbar switch. - * - * @param stcd The pointer to the software TCD. - * @param bandwidth enum type for bandwidth control - */ -static inline void EDMA_HAL_STCDSetBandwidth( - edma_software_tcd_t *stcd, edma_bandwidth_config_t bandwidth) -{ - assert(stcd); - stcd->CSR = (stcd->CSR & ~DMA_CSR_BWC_MASK) | DMA_CSR_BWC(bandwidth); -} - -/*! - * @brief Configures the major channel link the software TCD. - * - * If the majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a - * channel service request at the channel defined by these six bits by setting that channel start - * bits. - * - * @param stcd The pointer to the software TCD. - * @param majorChannel channel number for major link - * @param enable Enables (true) or Disables (false) channel major link. - */ -static inline void EDMA_HAL_STCDSetChannelMajorLink( - edma_software_tcd_t *stcd, uint32_t majorChannel, bool enable) -{ - assert(stcd); - stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORLINKCH_MASK) | DMA_CSR_MAJORLINKCH(majorChannel); - stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORELINK_MASK) | - ((uint32_t)enable << DMA_CSR_MAJORELINK_SHIFT); -} - - -/*! - * @brief Enables/Disables the scatter/gather feature for the software TCD. - * - * @param stcd The pointer to the software TCD. - * @param enable Enables (true) /Disables (false) scatter/gather feature. - */ -static inline void EDMA_HAL_STCDSetScatterGatherCmd( - edma_software_tcd_t *stcd, bool enable) -{ - assert(stcd); - stcd->CSR = (stcd->CSR & ~DMA_CSR_ESG_MASK) | ((uint32_t)enable << DMA_CSR_ESG_SHIFT); -} - - -/*! - * @brief Disables/Enables the DMA request after the major loop completes for the software TCD. - * - * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the - * current major iteration count reaches zero. - * - * @param stcd The pointer to the software TCD. - * @param disable Disable (true)/Enable (true) dma request after TCD complete. - */ -static inline void EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd( - edma_software_tcd_t *stcd, bool disable) -{ - assert(stcd); - stcd->CSR = (stcd->CSR & ~DMA_CSR_DREQ_MASK) | ((uint32_t)disable << DMA_CSR_DREQ_SHIFT); -} - -/*! - * @brief Enables/Disables the half complete interrupt for the software TCD. - * - * If set, the channel generates an interrupt request by setting the appropriate bit in the - * interrupt register when the current major iteration count reaches the halfway point. Specifically, - * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point - * interrupt request is provided to support the double-buffered schemes or other types of data movement - * where the processor needs an early indication of the transfer's process. - * - * @param stcd The pointer to the software TCD. - * @param enable Enable (true) /Disable (false) half complete interrupt. - */ -static inline void EDMA_HAL_STCDSetHalfCompleteIntCmd( - edma_software_tcd_t *stcd, bool enable) -{ - assert(stcd); - stcd->CSR = (stcd->CSR & ~DMA_CSR_INTHALF_MASK) | ((uint32_t)enable << DMA_CSR_INTHALF_SHIFT); -} - -/*! - * @brief Enables/Disables the interrupt after the major loop completes for the software TCD. - * - * If enabled, the channel generates an interrupt request by setting the appropriate bit in the - * interrupt register when the current major iteration count reaches zero. - * - * @param stcd The pointer to the software TCD. - * @param enable Enable (true) /Disable (false) interrupt after TCD done. - */ -static inline void EDMA_HAL_STCDSetIntCmd(edma_software_tcd_t *stcd, bool enable) -{ - assert(stcd); - stcd->CSR = (stcd->CSR & ~DMA_CSR_INTMAJOR_MASK) | ((uint32_t)enable << DMA_CSR_INTMAJOR_SHIFT); -} - -/*! - * @brief Triggers the start bits for the software TCD. - * - * The eDMA hardware automatically clears this flag after the channel begins execution. - * - * @param stcd The pointer to the software TCD. - */ -static inline void EDMA_HAL_STCDTriggerChannelStart(edma_software_tcd_t *stcd) -{ - assert(stcd); - stcd->CSR |= DMA_CSR_START_MASK; -} - -/*! - * @brief Set Channel minor link for software TCD. - * - * @param stcd The pointer to the software TCD. - * @param linkChannel Channel to be linked on minor loop complete. - * @param enable Enable (true)/Disable (false) channel minor link. - */ -void EDMA_HAL_STCDSetChannelMinorLink( - edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable); - -/*! - * @brief Sets the major iteration count according to minor loop channel link setting. - * - * Note here that user need to first set the minor loop channel link and then call this function. - * The execute flow inside this function is dependent on the minor loop channel link setting. - * - * @param stcd The pointer to the software TCD. - * @param count major loop count - */ -void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count); - -/*! - * @brief Copy the software TCD configuration to the hardware TCD. - * - * @param baseAddr Register base address for eDMA module. - * @param channel eDMA channel number. - * @param stcd The pointer to the software TCD. - */ -void EDMA_HAL_PushSTCDToHTCD(uint32_t baseAddr, uint32_t channel, edma_software_tcd_t *stcd); - -/*! - * @brief Set the basic transfer for software TCD. - * - * This function is used to setup the basic transfer for software TCD. The minor loop setting is not - * involved here cause minor loop's configuration will lay a impact on the global eDMA setting. And - * the source minor loop offset is relevant to the dest minor loop offset. For these reasons, minor - * loop offset configuration is treated as an advanced configuration. User can call the - * EDMA_HAL_STCDSetMinorLoopOffset() to configure the minor loop offset feature. - * - * @param baseAddr Register base address for eDMA module. - * @param stcd The pointer to the software TCD. - * @param config The pointer to the transfer configuration structure. - * @param enableInt Enables (true) or Disables (false) interrupt on TCD complete. - * @param disableDmaRequest Disables (true) or Enable (false) dma request on TCD complete. - */ -edma_status_t EDMA_HAL_STCDSetBasicTransfer( - uint32_t baseAddr, edma_software_tcd_t *stcd, edma_transfer_config_t *config, - bool enableInt, bool disableDmaRequest); - - -/* @} */ - - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* __EDMA_HAL_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ - - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_features.h deleted file mode 100644 index 2fc74a032f0..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_features.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_ENET_FEATURES_H__) -#define __FSL_ENET_FEATURES_H__ - - -#if defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) - #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (1) - #define FSL_FEATURE_ENET_SUPPORT_PTP (0) - #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) - #define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT (0) -#elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) - #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0) - #define FSL_FEATURE_ENET_SUPPORT_PTP (0) - #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) - #define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT (0) -#elif defined(CPU_MK70FN1M0VMJ12) - #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (1) - #define FSL_FEATURE_ENET_SUPPORT_PTP (0) - #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) -#else - #define MBED_NO_ENET -#endif - - -#endif /* __FSL_ENET_FEATURES_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c deleted file mode 100644 index 77c911949a2..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_enet_hal.h" - -#ifndef MBED_NO_ENET - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_set_mac_address - * Description: Set ENET mac physical address. - * - *END*********************************************************************/ -void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - uint32_t address, data; - - address = (uint32_t)(((uint32_t)hwAddr[0] << 24U)|((uint32_t)hwAddr[1] << 16U)|((uint32_t)hwAddr[2] << 8U)| (uint32_t)hwAddr[3]) ; - HW_ENET_PALR_WR(instance,address); /* Set low physical address */ - address = (uint32_t)(((uint32_t)hwAddr[4] << 24U)|((uint32_t)hwAddr[5] << 16U)) ; - data = HW_ENET_PAUR_RD(instance) & BM_ENET_PAUR_TYPE; - HW_ENET_PAUR_WR(instance, (data | address)); /* Set high physical address */ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_set_group_hashtable - * Description: Set multicast group address hash value to the mac register - * To join the multicast group address. - *END*********************************************************************/ -void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - switch (mode) - { - case kEnetSpecialAddressInit: /* Clear group address register on ENET initialize */ - HW_ENET_GALR_WR(instance,0); - HW_ENET_GAUR_WR(instance,0); - break; - case kEnetSpecialAddressEnable: /* Enable a multicast group address*/ - if (!((crcValue >> 31) & 1U)) - { - HW_ENET_GALR_SET(instance,(1U << ((crcValue >> 26) & kEnetHashValMask))); - } - else - { - HW_ENET_GAUR_SET(instance,(1U << ((crcValue >> 26) & kEnetHashValMask))); - } - break; - case kEnetSpecialAddressDisable: /* Disable a multicast group address*/ - if (!((crcValue >> 31) & 1U)) - { - HW_ENET_GALR_CLR(instance,(1U << ((crcValue >> 26) & kEnetHashValMask))); - } - else - { - HW_ENET_GAUR_CLR(instance,(1U << ((crcValue>>26) & kEnetHashValMask))); - } - break; - default: - break; - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_set_individual_hashtable - * Description: Set a specific unicast address hash value to the mac register - * To receive frames with the individual destination address. - *END*********************************************************************/ -void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - switch (mode) - { - case kEnetSpecialAddressInit: /* Clear individual address register on ENET initialize */ - HW_ENET_IALR_WR(instance,0); - HW_ENET_IAUR_WR(instance,0); - break; - case kEnetSpecialAddressEnable: /* Enable a special address*/ - if (((crcValue >>31) & 1U) == 0) - { - HW_ENET_IALR_SET(instance,(1U << ((crcValue>>26)& kEnetHashValMask))); - } - else - { - HW_ENET_IAUR_SET(instance,(1U << ((crcValue>>26)& kEnetHashValMask))); - } - break; - case kEnetSpecialAddressDisable: /* Disable a special address*/ - if (((crcValue >>31) & 1U) == 0) - { - HW_ENET_IALR_CLR(instance,(1U << ((crcValue>>26)& kEnetHashValMask))); - } - else - { - HW_ENET_IAUR_CLR(instance,(1U << ((crcValue>>26)& kEnetHashValMask))); - } - break; - default: - break; - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_tx_fifo - * Description: Configure ENET transmit FIFO. - *END*********************************************************************/ -void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(thresholdCfg); - - BW_ENET_TFWR_STRFWD(instance, thresholdCfg->isStoreForwardEnabled); /* Set store and forward mode*/ - if(!thresholdCfg->isStoreForwardEnabled) - { - assert(thresholdCfg->txFifoWrite <= BM_ENET_TFWR_TFWR); - BW_ENET_TFWR_TFWR(instance, thresholdCfg->txFifoWrite); /* Set transmit FIFO write bytes*/ - } - BW_ENET_TSEM_TX_SECTION_EMPTY(instance,thresholdCfg->txEmpty); /* Set transmit FIFO empty threshold*/ - BW_ENET_TAEM_TX_ALMOST_EMPTY(instance,thresholdCfg->txAlmostEmpty); /* Set transmit FIFO almost empty threshold*/ - BW_ENET_TAFL_TX_ALMOST_FULL(instance,thresholdCfg->txAlmostFull); /* Set transmit FIFO almost full threshold*/ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_rx_fifo - * Description: Configure ENET receive FIFO. - *END*********************************************************************/ -void enet_hal_config_rx_fifo(uint32_t instance,enet_config_rx_fifo_t *thresholdCfg ) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(thresholdCfg); - if(thresholdCfg->rxFull > 0) - { - assert(thresholdCfg->rxFull > thresholdCfg->rxAlmostEmpty); - } - - BW_ENET_RSFL_RX_SECTION_FULL(instance,thresholdCfg->rxFull); /* Set receive FIFO full threshold*/ - BW_ENET_RSEM_RX_SECTION_EMPTY(instance,thresholdCfg->rxEmpty); /* Set receive FIFO empty threshold*/ - BW_ENET_RAEM_RX_ALMOST_EMPTY(instance,thresholdCfg->rxAlmostEmpty); /* Set receive FIFO almost empty threshold*/ - BW_ENET_RAFL_RX_ALMOST_FULL(instance,thresholdCfg->rxAlmostFull); /* Set receive FIFO almost full threshold*/ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_init_rxbds - * Description: Initialize ENET receive buffer descriptors. - *END*********************************************************************/ -void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd) -{ - assert(rxBds); - assert(buffer); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)rxBds; - - bdPtr->buffer = (uint8_t *)NTOHL((uint32_t)buffer); /* Set data buffer address */ - bdPtr->length = 0; /* Initialize data length*/ - - /*The last buffer descriptor should be set with the wrap flag*/ - if (isLastBd) - { - bdPtr->control |= kEnetRxBdWrap; - } - bdPtr->control |= kEnetRxBdEmpty; /* Initialize bd with empty bit*/ - bdPtr->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable receive interrupt*/ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_init_txbds - * Description: Initialize ENET transmit buffer descriptors. - *END*********************************************************************/ -void enet_hal_init_txbds(void *txBds, bool isLastBd) -{ - assert(txBds); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)txBds; - - bdPtr->length = 0; /* Initialize data length*/ - - /*The last buffer descriptor should be set with the wrap flag*/ - if (isLastBd) - { - bdPtr->control |= kEnetTxBdWrap; - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_update_rxbds - * Description: Update ENET receive buffer descriptors. - *END*********************************************************************/ -void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate) -{ - assert(rxBds); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)rxBds; - - if (isbufferUpdate) - { - bdPtr->buffer = (uint8_t *)HTONL((uint32_t)data); - } - bdPtr->control &= kEnetRxBdWrap; /* Clear status*/ - bdPtr->control |= kEnetRxBdEmpty; /* Set rx bd empty*/ - bdPtr->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable interrupt*/ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_update_txbds - * Description: Update ENET transmit buffer descriptors. - *END*********************************************************************/ -void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged) -{ - assert(txBds); - assert(buffer); - - volatile enet_bd_struct_t * bdPtr = (enet_bd_struct_t *)txBds; - - bdPtr->length = HTONS(length); /* Set data length*/ - bdPtr->buffer = (uint8_t *)HTONL((uint32_t)buffer); /* Set data buffer*/ - bdPtr->control |= kEnetTxBdLast | kEnetTxBdTransmitCrc | kEnetTxBdReady;/* set control */ - if (isTxtsCfged) - { - /* Set receive and timestamp interrupt*/ - bdPtr->controlExtend1 |= (kEnetTxBdTxInterrupt | kEnetTxBdTimeStamp); - } - else - { - /* Set receive interrupt*/ - bdPtr->controlExtend1 |= kEnetTxBdTxInterrupt; - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_rxbd_control - * Description: Get receive buffer descriptor control and status region. - *END*********************************************************************/ -uint16_t enet_hal_get_rxbd_control(void *curBd) -{ - assert(curBd); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - return bdPtr->control; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_txbd_control - * Description: Get ENET transmit buffer descriptor control and status data. - *END*********************************************************************/ -uint16_t enet_hal_get_txbd_control(void *curBd) -{ - assert(curBd); - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - return bdPtr->control; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_bd_length - * Description: Get ENET data length of buffer descriptors. - *END*********************************************************************/ -uint16_t enet_hal_get_bd_length(void *curBd) -{ - assert(curBd); - uint16_t length; - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - length = bdPtr->length; - return NTOHS(length); -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_bd_buffer - * Description: Get the buffer address of buffer descriptors. - *END*********************************************************************/ -uint8_t* enet_hal_get_bd_buffer(void *curBd) -{ - assert(curBd); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - uint32_t buffer = (uint32_t)(bdPtr->buffer); - return (uint8_t *)NTOHL(buffer); -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_bd_timestamp - * Description: Get the timestamp of buffer descriptors. - *END*********************************************************************/ -uint32_t enet_hal_get_bd_timestamp(void *curBd) -{ - assert(curBd); - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - uint32_t timestamp = bdPtr->timestamp; - return NTOHL(timestamp); -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_rxbd_control_extend - * Description: Get ENET receive buffer descriptor extended control region. - *END*********************************************************************/ -bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion) -{ - assert(curBd); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - -#if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY - if (((uint16_t)controlRegion > kEnetRxBdCtlJudge1) && ((uint16_t)controlRegion < kEnetRxBdCtlJudge2)) - { - return ((bdPtr->controlExtend0 & controlRegion) != 0); /* Control extended0 region*/ - } - else - { - return ((bdPtr->controlExtend1 & controlRegion) != 0); /* Control extended1 region*/ - } -#else - if( (uint16_t)controlRegion < kEnetRxBdCtlJudge1) - { - return ((bdPtr->controlExtend0 & controlRegion) != 0); /* Control extended0 region*/ - } - else - { - return ((bdPtr->controlExtend1 & controlRegion) != 0);/* Control extended1 region*/ - } -#endif -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_txbd_control_extend - * Description: Get ENET transmit buffer descriptor extended control region. - *END*********************************************************************/ -uint16_t enet_hal_get_txbd_control_extend(void *curBd) -{ - assert(curBd); - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - - return bdPtr->controlExtend0; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_get_txbd_timestamp_flag - * Description: Get ENET transmit buffer descriptor timestamp region. - *END*********************************************************************/ -bool enet_hal_get_txbd_timestamp_flag(void *curBd) -{ - assert(curBd); - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - return ((bdPtr->controlExtend1 & kEnetTxBdTimeStamp) != 0); -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_rmii - * Description: Configure (R)MII mode. - *END*********************************************************************/ -void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_RCR_MII_MODE(instance,1); /* Set mii mode */ - BW_ENET_RCR_RMII_MODE(instance,mode); - BW_ENET_RCR_RMII_10T(instance,speed); /* Set speed mode */ - BW_ENET_TCR_FDEN(instance,duplex); /* Set duplex mode*/ - if ((!duplex) && isRxOnTxDisabled) - { - BW_ENET_RCR_DRT(instance,1); /* Disable receive on transmit*/ - } - - if (mode == kEnetCfgMii) /* Set internal loop only for mii mode*/ - { - BW_ENET_RCR_LOOP(instance,isLoopEnabled); - } - else - { - BW_ENET_RCR_LOOP(instance, 0); /* Clear internal loop for rmii mode*/ - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_set_mii_command - * Description: Set MII command. - *END*********************************************************************/ -void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - uint32_t mmfrValue = 0 ; - - mmfrValue = BF_ENET_MMFR_ST(1)| BF_ENET_MMFR_OP(operation)| BF_ENET_MMFR_PA(phyAddr) | BF_ENET_MMFR_RA(phyReg)| BF_ENET_MMFR_TA(2) | (data&0xFFFF); /* mii command*/ - HW_ENET_MMFR_WR(instance,mmfrValue); -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_ethernet - * Description: Enable or disable normal Ethernet mode and enhanced mode. - *END*********************************************************************/ -void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_ECR_ETHEREN(instance,isEnabled); /* Enable/Disable Ethernet module*/ - if (isEnhanced) - { - BW_ENET_ECR_EN1588(instance,isEnabled); /* Enable/Disable enhanced frame feature*/ - } -#if SYSTEM_LITTLE_ENDIAN && !FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY - BW_ENET_ECR_DBSWP(instance,1); /* buffer descriptor byte swapping for little-endian system and endianness configurable IP*/ -#endif -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_interrupt - * Description: Enable or disable different Ethernet interrupts. - * the parameter source is the interrupt source and enet_interrupt_request_t - * enum types is recommended to be used as the interrupt sources. - *END*********************************************************************/ -void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - if (isEnabled) - { - HW_ENET_EIMR_SET(instance,source); /* Enable interrupt */ - } - else - { - HW_ENET_EIMR_CLR(instance,source); /* Disable interrupt*/ - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_tx_accelerator - * Description: Configure Ethernet transmit accelerator features. - *END*********************************************************************/ -void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(txCfgPtr); - - HW_ENET_TACC_WR(instance,0); /* Clear all*/ - BW_ENET_TACC_IPCHK(instance,txCfgPtr->isIpCheckEnabled); /* Insert ipheader checksum */ - BW_ENET_TACC_PROCHK(instance,txCfgPtr->isProtocolCheckEnabled); /* Insert protocol checksum*/ - BW_ENET_TACC_SHIFT16(instance,txCfgPtr->isShift16Enabled); /* Set tx fifo shift-16*/ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_config_rx_accelerator - * Description: Configure Ethernet receive accelerator features. - *END*********************************************************************/ -void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(rxCfgPtr); - - HW_ENET_RACC_WR(instance,0); /* Clear all*/ - BW_ENET_RACC_IPDIS(instance,rxCfgPtr->isIpcheckEnabled); /* Set ipchecksum field*/ - BW_ENET_RACC_PRODIS(instance,rxCfgPtr->isProtocolCheckEnabled); /* Set protocol field*/ - BW_ENET_RACC_LINEDIS(instance,rxCfgPtr->isMacCheckEnabled); /* Set maccheck field*/ - BW_ENET_RACC_SHIFT16(instance,rxCfgPtr->isShift16Enabled); /* Set rx fifo shift field*/ - BW_ENET_RACC_PADREM(instance,rxCfgPtr->isPadRemoveEnabled); /* Set rx padding remove field*/ -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_set_txpause - * Return Value: The execution status. - * Description: Set the ENET transmit controller with pause duration and - * Set enet transmit PAUSE frame transmission. - * This should be called when a PAUSE frame is dynamically wanted. - *END*********************************************************************/ -void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR); - BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration); - BW_ENET_TCR_TFC_PAUSE(instance, 1); -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_init_ptp_timer - * Description: Initialize Ethernet ptp timer. - *END*********************************************************************/ -void enet_hal_init_ptp_timer(uint32_t instance,enet_config_ptp_timer_t *ptpCfgPtr) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(ptpCfgPtr); - - BW_ENET_ATINC_INC(instance, ptpCfgPtr->clockIncease); /* Set increase value for ptp timer*/ - HW_ENET_ATPER_WR(instance, ptpCfgPtr->period); /* Set wrap time for ptp timer*/ - /* set periodical event and the event signal output assertion*/ - BW_ENET_ATCR_PEREN(instance, 1); - BW_ENET_ATCR_PINPER(instance, 1); - /* Set ptp timer slave/master mode*/ - BW_ENET_ATCR_SLAVE(instance, ptpCfgPtr->isSlaveEnabled); -} - -#endif /* MBED_NO_ENET */ - - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h deleted file mode 100644 index 2ceebc8d10d..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h +++ /dev/null @@ -1,1420 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_ENET_HAL_H__ -#define __FSL_ENET_HAL_H__ - -#include -#include -#include "fsl_device_registers.h" -#include "fsl_enet_features.h" -#include - -#ifndef MBED_NO_ENET - -/*! - * @addtogroup enet_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Defines the system endian type.*/ -#define SYSTEM_LITTLE_ENDIAN (1) - -/*! @brief Define macro to do the endianness swap*/ -#define BSWAP_16(x) (uint16_t)((uint16_t)(((uint16_t)(x) & (uint16_t)0xFF00) >> 0x8) | (uint16_t)(((uint16_t)(x) & (uint16_t)0xFF) << 0x8)) -#define BSWAP_32(x) (uint32_t)((((uint32_t)(x) & 0x00FFU) << 24) | (((uint32_t)(x) & 0x00FF00U) << 8) | (((uint32_t)(x) & 0xFF0000U) >> 8) | (((uint32_t)(x) & 0xFF000000U) >> 24)) -#if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY -#define HTONS(n) BSWAP_16(n) -#define HTONL(n) BSWAP_32(n) -#define NTOHS(n) BSWAP_16(n) -#define NTOHL(n) BSWAP_32(n) -#else -#define HTONS(n) (n) -#define HTONL(n) (n) -#define NTOHS(n) (n) -#define NTOHL(n) (n) -#endif - -/*! @brief Defines the Status return codes.*/ -typedef enum _enet_status -{ - kStatus_ENET_Success = 0, - kStatus_ENET_InvalidInput, /*!< Invalid ENET input parameter */ - kStatus_ENET_MemoryAllocateFail, /*!< Memory allocate failure*/ - kStatus_ENET_GetClockFreqFail, /*!< Get clock frequency failure*/ - kStatus_ENET_Initialized, /*!< ENET device already initialized*/ - kStatus_ENET_Layer2QueueNull, /*!< NULL L2 PTP buffer queue pointer*/ - kStatus_ENET_Layer2OverLarge, /*!< Layer2 packet length over large*/ - kStatus_ENET_Layer2BufferFull, /*!< Layer2 packet buffer full*/ - kStatus_ENET_PtpringBufferFull, /*!< PTP ring buffer full*/ - kStatus_ENET_PtpringBufferEmpty, /*!< PTP ring buffer empty*/ - kStatus_ENET_Miiuninitialized, /*!< MII uninitialized*/ - kStatus_ENET_RxbdInvalid, /*!< Receive buffer descriptor invalid*/ - kStatus_ENET_RxbdEmpty, /*!< Receive buffer descriptor empty*/ - kStatus_ENET_RxbdTrunc, /*!< Receive buffer descriptor truncate*/ - kStatus_ENET_RxbdError, /*!< Receive buffer descriptor error*/ - kStatus_ENET_RxBdFull, /*!< Receive buffer descriptor full*/ - kStatus_ENET_SmallBdSize, /*!< Small receive buffer size*/ - kStatus_ENET_LargeBufferFull, /*!< Receive large buffer full*/ - kStatus_ENET_TxbdFull, /*!< Transmit buffer descriptor full*/ - kStatus_ENET_TxbdNull, /*!< Transmit buffer descriptor Null*/ - kStatus_ENET_TxBufferNull, /*!< Transmit data buffer Null*/ - kStatus_ENET_NoRxBufferLeft, /*!< No more receive buffer left*/ - kStatus_ENET_UnknownCommand, /*!< Invalid ENET PTP IOCTL command*/ - kStatus_ENET_TimeOut, /*!< ENET Timeout*/ - kStatus_ENET_MulticastPointerNull, /*!< Null multicast group pointer*/ - kStatus_ENET_AlreadyAddedMulticast /*!< Have Already added to multicast group*/ -} enet_status_t; - - -#if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY && SYSTEM_LITTLE_ENDIAN -/*! @brief Defines the control and status regions of the receive buffer descriptor.*/ -typedef enum _enet_rx_bd_control_status -{ - kEnetRxBdBroadCast = 0x8000, /*!< Broadcast */ - kEnetRxBdMultiCast = 0x4000, /*!< Multicast*/ - kEnetRxBdLengthViolation = 0x2000, /*!< Receive length violation*/ - kEnetRxBdNoOctet = 0x1000, /*!< Receive non-octet aligned frame*/ - kEnetRxBdCrc = 0x0400, /*!< Receive CRC error*/ - kEnetRxBdOverRun = 0x0200, /*!< Receive FIFO overrun*/ - kEnetRxBdTrunc = 0x0100, /*!< Frame is truncated */ - kEnetRxBdEmpty = 0x0080, /*!< Empty bit*/ - kEnetRxBdRxSoftOwner1 = 0x0040, /*!< Receive software owner*/ - kEnetRxBdWrap = 0x0020, /*!< Update buffer descriptor*/ - kEnetRxBdRxSoftOwner2 = 0x0010, /*!< Receive software owner*/ - kEnetRxBdLast = 0x0008, /*!< Last BD in the frame*/ - kEnetRxBdMiss = 0x0001 /*!< Receive for promiscuous mode*/ -} enet_rx_bd_control_status_t; - -/*! @brief Defines the control extended regions of the receive buffer descriptor.*/ -typedef enum _enet_rx_bd_control_extend -{ - kEnetRxBdUnicast = 0x0001, /*!< Unicast frame*/ - kEnetRxBdCollision = 0x0002, /*!< BD collision*/ - kEnetRxBdPhyErr = 0x0004, /*!< PHY error*/ - kEnetRxBdMacErr = 0x0080, /*!< Mac error*/ - kEnetRxBdIpv4 = 0x0100, /*!< Ipv4 frame*/ - kEnetRxBdIpv6 = 0x0200, /*!< Ipv6 frame*/ - kEnetRxBdVlan = 0x0400, /*!< VLAN*/ - kEnetRxBdProtocolChecksumErr = 0x1000, /*!< Protocol checksum error*/ - kEnetRxBdIpHeaderChecksumErr = 0x2000, /*!< IP header checksum error*/ - kEnetRxBdIntrrupt = 0x8000 /*!< BD interrupt*/ -} enet_rx_bd_control_extend_t; - -/*! @brief Defines the control status region of the transmit buffer descriptor.*/ -typedef enum _enet_tx_bd_control_status -{ - kEnetTxBdReady = 0x0080, /*!< Ready bit*/ - kEnetTxBdTxSoftOwner1 = 0x0040, /*!< Transmit software owner*/ - kEnetTxBdWrap = 0x0020, /*!< Wrap buffer descriptor*/ - kEnetTxBdTxSoftOwner2 = 0x0010, /*!< Transmit software owner*/ - kEnetTxBdLast = 0x0008, /*!< Last BD in the frame*/ - kEnetTxBdTransmitCrc = 0x0004 /*!< Receive for transmit CRC*/ -} enet_tx_bd_control_status_t; - -/*! @brief Defines the control extended region of the transmit buffer descriptor.*/ -typedef enum _enet_tx_bd_control_extend -{ - kEnetTxBdTxErr = 0x0080, /*!< Transmit error*/ - kEnetTxBdTxUnderFlowErr = 0x0020, /*!< Underflow error*/ - kEnetTxBdExcessCollisionErr = 0x0010, /*!< Excess collision error*/ - kEnetTxBdTxFrameErr = 0x0008, /*!< Frame error*/ - kEnetTxBdLatecollisionErr = 0x0004, /*!< Late collision error*/ - kEnetTxBdOverFlowErr = 0x0002, /*!< Overflow error*/ - kEnetTxTimestampErr = 0x0001 /*!< Timestamp error*/ -} enet_tx_bd_control_extend_t; - -/*! @brief Defines the control extended2 region of the transmit buffer descriptor.*/ -typedef enum _enet_tx_bd_control_extend2 -{ - kEnetTxBdTxInterrupt = 0x0040, /*!< Transmit interrupt*/ - kEnetTxBdTimeStamp = 0x0020 /*!< Transmit timestamp flag */ -} enet_tx_bd_control_extend2_t; -#else -/*! @brief Defines the control and status region of the receive buffer descriptor.*/ -typedef enum _enet_rx_bd_control_status -{ - kEnetRxBdEmpty = 0x8000, /*!< Empty bit*/ - kEnetRxBdRxSoftOwner1 = 0x4000, /*!< Receive software owner*/ - kEnetRxBdWrap = 0x2000, /*!< Update buffer descriptor*/ - kEnetRxBdRxSoftOwner2 = 0x1000, /*!< Receive software owner*/ - kEnetRxBdLast = 0x0800, /*!< Last BD in the frame*/ - kEnetRxBdMiss = 0x0100, /*!< Receive for promiscuous mode*/ - kEnetRxBdBroadCast = 0x0080, /*!< Broadcast */ - kEnetRxBdMultiCast = 0x0040, /*!< Multicast*/ - kEnetRxBdLengthViolation = 0x0020, /*!< Receive length violation*/ - kEnetRxBdNoOctet = 0x0010, /*!< Receive non-octet aligned frame*/ - kEnetRxBdCrc = 0x0004, /*!< Receive CRC error*/ - kEnetRxBdOverRun = 0x0002, /*!< Receive FIFO overrun*/ - kEnetRxBdTrunc = 0x0001 /*!< Frame is truncated */ -} enet_rx_bd_control_status_t; - -/*! @brief Defines the control extended region of the receive buffer descriptor.*/ -typedef enum _enet_rx_bd_control_extend -{ - kEnetRxBdIpv4 = 0x0001, /*!< Ipv4 frame*/ - kEnetRxBdIpv6 = 0x0002, /*!< Ipv6 frame*/ - kEnetRxBdVlan = 0x0004, /*!< VLAN*/ - kEnetRxBdProtocolChecksumErr = 0x0010, /*!< Protocol checksum error*/ - kEnetRxBdIpHeaderChecksumErr = 0x0020, /*!< IP header checksum error*/ - kEnetRxBdIntrrupt = 0x0080, /*!< BD interrupt*/ - kEnetRxBdUnicast = 0x0100, /*!< Unicast frame*/ - kEnetRxBdCollision = 0x0200, /*!< BD collision*/ - kEnetRxBdPhyErr = 0x0400, /*!< PHY error*/ - kEnetRxBdMacErr = 0x8000 /*!< Mac error */ -} enet_rx_bd_control_extend_t; - -/*! @brief Defines the control status of the transmit buffer descriptor.*/ -typedef enum _enet_tx_bd_control_status -{ - kEnetTxBdReady = 0x8000, /*!< Ready bit*/ - kEnetTxBdTxSoftOwner1 = 0x4000, /*!< Transmit software owner*/ - kEnetTxBdWrap = 0x2000, /*!< Wrap buffer descriptor*/ - kEnetTxBdTxSoftOwner2 = 0x1000, /*!< Transmit software owner*/ - kEnetTxBdLast = 0x0800, /*!< Last BD in the frame*/ - kEnetTxBdTransmitCrc = 0x0400 /*!< Receive for transmit CRC */ -} enet_tx_bd_control_status_t; - -/*! @brief Defines the control extended of the transmit buffer descriptor.*/ -typedef enum _enet_tx_bd_control_extend -{ - kEnetTxBdTxErr = 0x8000, /*!< Transmit error*/ - kEnetTxBdTxUnderFlowErr = 0x2000, /*!< Underflow error*/ - kEnetTxBdExcessCollisionErr = 0x1000, /*!< Excess collision error*/ - kEnetTxBdTxFrameErr = 0x0800, /*!< Frame error*/ - kEnetTxBdLatecollisionErr = 0x0400, /*!< Late collision error*/ - kEnetTxBdOverFlowErr = 0x0200, /*!< Overflow error*/ - kEnetTxTimestampErr = 0x0100 /*!< Timestamp error*/ -} enet_tx_bd_control_extend_t; - -/*! @brief Defines the control extended2 of the transmit buffer descriptor.*/ -typedef enum _enet_tx_bd_control_extend2 -{ - kEnetTxBdTxInterrupt = 0x4000, /*!< Transmit interrupt*/ - kEnetTxBdTimeStamp = 0x2000 /*!< Transmit timestamp flag */ -} enet_tx_bd_control_extend2_t; -#endif - -/*! @brief Defines the macro to the different ENET constant value.*/ -typedef enum _enet_constant_parameter -{ - kEnetMacAddrLen = 6, /*!< ENET mac address length*/ - kEnetHashValMask = 0x1f, /*!< ENET hash value mask*/ - kEnetRxBdCtlJudge1 = 0x0080,/*!< ENET receive buffer descriptor control judge value1*/ - kEnetRxBdCtlJudge2 = 0x8000 /*!< ENET receive buffer descriptor control judge value2*/ -} enet_constant_parameter_t; - -/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY.*/ -typedef enum _enet_config_rmii -{ - kEnetCfgMii = 0, /*!< MII mode for data interface*/ - kEnetCfgRmii = 1 /*!< RMII mode for data interface*/ -} enet_config_rmii_t; - -/*! @brief Defines the 10 Mbps or 100 Mbps speed mode for the data transfer.*/ -typedef enum _enet_config_speed -{ - kEnetCfgSpeed100M = 0, /*!< Speed 100 M mode*/ - kEnetCfgSpeed10M = 1 /*!< Speed 10 M mode*/ -} enet_config_speed_t; - -/*! @brief Defines the half or full duplex mode for the data transfer.*/ -typedef enum _enet_config_duplex -{ - kEnetCfgHalfDuplex = 0, /*!< Half duplex mode*/ - kEnetCfgFullDuplex = 1 /*!< Full duplex mode*/ -} enet_config_duplex_t; - -/*! @brief Defines the write/read operation for the MII.*/ -typedef enum _enet_mii_operation -{ - kEnetWriteNoCompliant = 0, /*!< Write frame operation, but not MII compliant.*/ - kEnetWriteValidFrame = 1, /*!< Write frame operation for a valid MII management frame*/ - kEnetReadValidFrame = 2, /*!< Read frame operation for a valid MII management frame.*/ - kEnetReadNoCompliant = 3 /*!< Read frame operation, but not MII compliant*/ -}enet_mii_operation_t; - -/*! @brief Define holdon time on MDIO output*/ -typedef enum _enet_mdio_holdon_clkcycle -{ - kEnetMdioHoldOneClkCycle = 0, /*!< MDIO output hold on one clock cycle*/ - kEnetMdioHoldTwoClkCycle = 1, /*!< MDIO output hold on two clock cycles*/ - kEnetMdioHoldThreeClkCycle = 2, /*!< MDIO output hold on three clock cycles*/ - kEnetMdioHoldFourClkCycle = 3, /*!< MDIO output hold on four clock cycles*/ - kEnetMdioHoldFiveClkCycle = 4, /*!< MDIO output hold on five clock cycles*/ - kEnetMdioHoldSixClkCycle = 5, /*!< MDIO output hold on six clock cycles*/ - kEnetMdioHoldSevenClkCycle = 6, /*!< MDIO output hold seven two clock cycles*/ - kEnetMdioHoldEightClkCycle = 7, /*!< MDIO output hold on eight clock cycles*/ -}enet_mdio_holdon_clkcycle_t; - -/*! @brief Defines the initialization, enables or disables the operation for a special address filter */ -typedef enum _enet_special_address_filter -{ - kEnetSpecialAddressInit= 0, /*!< Initializes the special address filter.*/ - kEnetSpecialAddressEnable = 1, /*!< Enables the special address filter.*/ - kEnetSpecialAddressDisable = 2 /*!< Disables the special address filter.*/ -} enet_special_address_filter_t; - -/*! @brief Defines the capture or compare mode for 1588 timer channels.*/ -typedef enum _enet_timer_channel_mode -{ - kEnetChannelDisable = 0, /*!< Disable timer channel*/ - kEnetChannelRisingCapture = 1, /*!< Input capture on rising edge*/ - kEnetChannelFallingCapture = 2, /*!< Input capture on falling edge*/ - kEnetChannelBothCapture = 3, /*!< Input capture on both edges*/ - kEnetChannelSoftCompare = 4, /*!< Output compare software only*/ - kEnetChannelToggleCompare = 5, /*!< Toggle output on compare*/ - kEnetChannelClearCompare = 6, /*!< Clear output on compare*/ - kEnetChannelSetCompare = 7, /*!< Set output on compare*/ - kEnetChannelClearCompareSetOverflow = 10, /*!< Clear output on compare, set output on overflow*/ - kEnetChannelSetCompareClearOverflow = 11, /*!< Set output on compare, clear output on overflow*/ - kEnetChannelPulseLowonCompare = 14, /*!< Pulse output low on compare for one 1588 clock cycle*/ - kEnetChannelPulseHighonCompare = 15 /*!< Pulse output high on compare for one 1588 clock cycle*/ -} enet_timer_channel_mode_t; - -/*! @brief Defines the RXFRAME/RXBYTE/TXFRAME/TXBYTE/MII/TSTIMER/TSAVAIL interrupt source for ENET.*/ -typedef enum _enet_interrupt_request -{ - kEnetBabrInterrupt = 0x40000000, /*!< BABR interrupt source*/ - kEnetBabtInterrupt = 0x20000000, /*!< BABT interrupt source*/ - kEnetGraInterrupt = 0x10000000, /*!< GRA interrupt source*/ - kEnetTxFrameInterrupt = 0x8000000, /*!< TXFRAME interrupt source */ - kEnetTxByteInterrupt = 0x4000000, /*!< TXBYTE interrupt source*/ - kEnetRxFrameInterrupt = 0x2000000, /*!< RXFRAME interrupt source */ - kEnetRxByteInterrupt = 0x1000000, /*!< RXBYTE interrupt source */ - kEnetMiiInterrupt = 0x0800000, /*!< MII interrupt source*/ - kEnetEBERInterrupt = 0x0400000, /*!< EBERR interrupt source*/ - kEnetLcInterrupt = 0x0200000, /*!< LC interrupt source*/ - kEnetRlInterrupt = 0x0100000, /*!< RL interrupt source*/ - kEnetUnInterrupt = 0x0080000, /*!< UN interrupt source*/ - kEnetPlrInterrupt = 0x0040000, /*!< PLR interrupt source*/ - kEnetWakeupInterrupt = 0x0020000, /*!< WAKEUP interrupt source*/ - kEnetTsAvailInterrupt = 0x0010000, /*!< TS AVAIL interrupt source*/ - kEnetTsTimerInterrupt = 0x0008000, /*!< TS WRAP interrupt source*/ - kEnetAllInterrupt = 0x7FFFFFFF /*!< All interrupt*/ -} enet_interrupt_request_t; - -/*! @brief Defines the six-byte Mac address type.*/ -typedef uint8_t enetMacAddr[kEnetMacAddrLen]; - -#if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) && SYSTEM_LITTLE_ENDIAN -/*! @brief Defines the buffer descriptor structure for the little-Endian system and endianness configurable IP.*/ -typedef struct ENETBdStruct -{ - uint16_t length; /*!< Buffer descriptor data length*/ - uint16_t control; /*!< Buffer descriptor control*/ - uint8_t *buffer; /*!< Data buffer pointer*/ - uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/ - uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/ - uint16_t payloadCheckSum; /*!< Internal payload checksum*/ - uint8_t headerLength; /*!< Header length*/ - uint8_t protocalTyte; /*!< Protocol type*/ - uint16_t reserved0; - uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/ - uint32_t timestamp; /*!< Timestamp */ - uint16_t reserved1; - uint16_t reserved2; - uint16_t reserved3; - uint16_t reserved4; -} enet_bd_struct_t; -#define TX_DESC_UPDATED_MASK (0x8000) -#else -/*! @brief Defines the buffer descriptors structure for the Big-Endian system.*/ -typedef struct ENETBdStruct -{ - uint16_t control; /*!< Buffer descriptor control */ - uint16_t length; /*!< Buffer descriptor data length*/ - uint8_t *buffer; /*!< Data buffer pointer*/ - uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/ - uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/ - uint8_t headerLength; /*!< Header length*/ - uint8_t protocalTyte; /*!< Protocol type*/ - uint16_t payloadCheckSum; /*!< Internal payload checksum*/ - uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/ - uint16_t reserved0; - uint32_t timestamp; /*!< Timestamp pointer*/ - uint16_t reserved1; - uint16_t reserved2; - uint16_t reserved3; - uint16_t reserved4; -} enet_bd_struct_t; -#define TX_DESC_UPDATED_MASK (0x0080) -#endif - -/*! @brief Defines the configuration structure for the 1588 PTP timer.*/ -typedef struct ENETConfigPtpTimer -{ - bool isSlaveEnabled; /*!< Master or slave PTP timer*/ - uint32_t clockIncease; /*!< Timer increase value each clock period*/ - uint32_t period; /*!< Timer period for generate interrupt event */ -} enet_config_ptp_timer_t; - -/*! @brief Defines the transmit accelerator configuration.*/ -typedef struct ENETConfigTxAccelerator -{ - bool isIpCheckEnabled; /*!< Insert IP header checksum */ - bool isProtocolCheckEnabled; /*!< Insert protocol checksum*/ - bool isShift16Enabled; /*!< Tx FIFO shift-16*/ -} enet_config_tx_accelerator_t; - -/*! @brief Defines the receive accelerator configuration.*/ -typedef struct ENETConfigRxAccelerator -{ - bool isIpcheckEnabled; /*!< Discard with wrong IP header checksum */ - bool isProtocolCheckEnabled; /*!< Discard with wrong protocol checksum*/ - bool isMacCheckEnabled; /*!< Discard with Mac layer errors*/ - bool isPadRemoveEnabled; /*!< Padding removal for short IP frames*/ - bool isShift16Enabled; /*!< Rx FIFO shift-16*/ -} enet_config_rx_accelerator_t; - -/*! @brief Defines the transmit FIFO configuration.*/ -typedef struct ENETConfigTxFifo -{ - bool isStoreForwardEnabled; /*!< Transmit FIFO store and forward */ - uint8_t txFifoWrite; /*!< Transmit FIFO write */ - uint8_t txEmpty; /*!< Transmit FIFO section empty threshold*/ - uint8_t txAlmostEmpty; /*!< Transmit FIFO section almost empty threshold*/ - uint8_t txAlmostFull; /*!< Transmit FIFO section almost full threshold*/ -} enet_config_tx_fifo_t; - -/*! @brief Defines the receive FIFO configuration.*/ -typedef struct ENETConfigRxFifo -{ - uint8_t rxFull; /*!< Receive FIFO section full threshold*/ - uint8_t rxAlmostFull; /*!< Receive FIFO section almost full threshold*/ - uint8_t rxEmpty; /*!< Receive FIFO section empty threshold*/ - uint8_t rxAlmostEmpty; /*!< Receive FIFO section almost empty threshold*/ -} enet_config_rx_fifo_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Resets the ENET module. - * - * @param instance The ENET instance number - */ -static inline void enet_hal_reset_ethernet(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_ECR_SET(instance, BM_ENET_ECR_RESET); -} - -/*! - * @brief Gets the ENET status to check whether the reset has completed. - * - * @param instance The ENET instance number - * @return Current status of the reset operation - * - true if ENET reset completed. - * - false if ENET reset has not completed. - */ -static inline bool enet_hal_is_reset_completed(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return (BR_ENET_ECR_RESET(instance) == 0); -} - -/*! - * @brief Enable or disable stop mode. - * - * Enable stop mode will control device behavior in doze mode. - * In doze mode, if this filed is set then all clock of the enet assemably are - * disabled, except the RMII/MII clock. - * - * @param instance The ENET instance number. - * @param isEnabled The switch to enable/disable stop mode. - * - true to enabale the stop mode. - * - false to disable the stop mode. - */ -static inline void enet_hal_enable_stop(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_ECR_STOPEN(instance, isEnabled); -} -/*! - * @brief Enable or disable sleep mode. - * - * Enable sleep mode will disable normal operating mode. When enable the sleep - * mode, the magic packet detection is also enabled so that a remote agent can - * wakeup the node. - * - * @param instance The ENET instance number. - * @param isEnabled The switch to enable/disable the sleep mode. - * - true to enabale the sleep mode. - * - false to disable the sleep mode. - */ - static inline void enet_hal_enable_sleep(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_ECR_SLEEP(instance, isEnabled); - BW_ENET_ECR_MAGICEN(instance, isEnabled); -} - -/*! - * @brief Sets the Mac address. - * - * This interface sets the six-byte Mac address of the ENET interface. - * - * @param instance The ENET instance number - * @param hwAddr The mac address pointer store for six bytes Mac address - */ -void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr); - -/*! - * @brief Sets the hardware addressing filtering to a multicast group address. - * - * This interface is used to add the ENET device to a multicast group address. - * After joining the group, Mac receives all frames with the group Mac address. - * - * @param instance The ENET instance number - * @param crcValue The CRC value of the special address - * @param mode The operation for init/enable/disable the specified hardware address - */ -void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode); - -/*! - * @brief Sets the hardware addressing filtering to an individual address. - * - * This interface is used to add an individual address to the hardware address - * filter. Mac receives all frames with the individual address as a destination address. - * - * @param instance The ENET instance number - * @param crcValue The CRC value of the special address - * @param mode The operation for init/enable/disable the specified hardware address - */ -void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode); - -/*! - * @brief Enable/disable payload length check. - * - * If the length/type is less than 0x600,When enable payload length check - * the core checks the fame's payload length. If the length/type is greater - * than or equal to 0x600. The MAC interprets the field as a type and no - * payload length check is performanced. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable payload length check - * - True to enabale payload length check. - * - False to disable payload legnth check. - */ -static inline void enet_hal_enable_payloadcheck(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_RCR_NLC(instance, isEnabled); -} - -/*! - * @brief Enable/disable append CRC to transmitted frames. - * - * If transmit CRC forward is enabled, the transmit buffer descriptor controls - * whether the frame has a CRC from the application. If transmit CRC forward is disabled, - * transmitter does not append any CRC to transmitted frames. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable transmit the receive CRC - * - True the transmitter control CRC through transmit buffer descriptor. - * - False the transmitter does not append any CRC to transmitted frames. - */ -static inline void enet_hal_enable_txcrcforward(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_TCR_CRCFWD(instance, !isEnabled); -} - -/*! - * @brief Enable/disable forward the CRC filed of the received frame. - * - * This is used to deceide whether the CRC field of received frame is transmitted - * or stripped. Enable this feature to strip CRC field from the frame. - * If padding remove is enabled, this feature will be ignored and - * the CRC field is checked and always terminated and removed. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable transmit the receive CRC - * - True to transmit the received CRC. - * - False to strip the received CRC. - */ -static inline void enet_hal_enable_rxcrcforward(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_RCR_CRCFWD(instance, !isEnabled); -} -/*! - * @brief Enable/disable forward PAUSE frames. - * - * This is used to deceide whether PAUSE frames is forwarded or discarded. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable forward PAUSE frames - * - True to forward PAUSE frames. - * - False to terminate and discard PAUSE frames. - */ -static inline void enet_hal_enable_pauseforward(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_RCR_PAUFWD(instance, isEnabled); -} - -/*! - * @brief Enable/disable frame padding remove on receive. - * - * Enable frame padding remove will remove the padding from the received frames. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable remove padding - * - True to remove padding from frames. - * - False to disable padding remove. - */ -static inline void enet_hal_enable_padremove(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_RCR_PADEN(instance, isEnabled); -} - -/*! - * @brief Enable/disable flow control. - * - * If flow control is enabled, the receive detects PAUSE frames. - * Upon PAUSE frame detection, the transmitter stops transmitting - * data frames for a given duration. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable flow control - * - True to enable the flow control. - * - False to disable the flow control. - */ -static inline void enet_hal_enable_flowcontrol(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_RCR_CFEN(instance, isEnabled); - BW_ENET_RCR_FCE(instance, isEnabled); -} - -/*! - * @brief Enable/disable broadcast frame reject. - * - * If broadcast frame reject is enabled, frames with destination address - * equal to 0xffff_ffff_ffff are rejected unless the promiscuous mode is open. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable reject broadcast frames - * - True to reject broadcast frames. - * - False to accept broadcast frames. - */ -static inline void enet_hal_enable_broadcastreject(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_RCR_BC_REJ(instance, isEnabled); -} - -/*! - * @brief Sets PAUSE duration for a PAUSE frame. - * - * This function is used to set the pause duraion used in transmission - * of a PAUSE frame. When another node detects a PAUSE frame, that node - * pauses transmission for the pause duration. - * - * @param instance The ENET instance number - * @param pauseDuration The PAUSE duration for the transmitted PAUSE frame - * the maximum pause duration is 0xFFFF. - */ -static inline void enet_hal_set_pauseduration(uint32_t instance, uint32_t pauseDuration) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR); - BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration); -} - -/*! - * @brief Gets receive PAUSE frame status. - * - * This function is used to get the received PAUSE frame status. - * - * @param instance The ENET instance number - * @return The status of the received flow control frames - * true if the flow control pause frame is received. - * false if there is no flow control frame received or the pause duration is complete. - */ -static inline bool enet_hal_get_rxpause_status(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - return BR_ENET_TCR_RFC_PAUSE(instance); -} -/*! - * @brief Enables transmit frame control PAUSE. - * - * This function enables pauses frame transmission. - * When this is set, with transmission of data frames stopped, the MAC - * transmits a MAC control PAUSE frame. NEXT, the MAC clear the - * and resumes transmitting data frames. - * - * @param instance The ENET instance number - * @param isEnabled The switch to enable/disable PAUSE control frame transmission - * - True enable PAUSE control frame transmission. - * - Flase disable PAUSE control frame transmission. - */ -static inline void enet_hal_enable_txpause(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - BW_ENET_TCR_TFC_PAUSE(instance, isEnabled); -} - -/*! - * @brief Sets transmit PAUSE frame. - * - * This function Sets ENET transmit controller with pause duration. - * And set the transmit control to do PAUSE frame transmission - * This should be called when a PAUSE frame is dynamically wanted. - * - * @param instance The ENET instance number - */ -void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration); - -/*! - * @brief Sets the transmit inter-packet gap. - * - * This function indicates the IPG, in bytes, between transmitted frames. - * Valid values range from 8 to 27. If value is less than 8, the IPG is 8. - * If value is greater than 27, the IPG is 27. - * - * @param instance The ENET instance number - * @param ipgValue The IPG for transmitted frames - * The default value is 12, the maximum value set to ipg is 0x1F. - * - */ -static inline void enet_hal_set_txipg(uint32_t instance, uint32_t ipgValue) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(ipgValue <= BM_ENET_TIPG_IPG); - BW_ENET_TIPG_IPG(instance, ipgValue); -} - -/*! - * @brief Sets the receive frame truncation length. - * - * This function indicates the value a receive frame is truncated, - * if it is greater than this value. The frame truncation length must be greater - * than or equal to the receive maximum frame length. - * - * @param instance The ENET instance number - * @param length The truncation length. The maximum value is 0x3FFF - * The default truncation length is 2047(0x7FF). - * - */ -static inline void enet_hal_set_truncationlen(uint32_t instance, uint32_t length) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(length <= BM_ENET_FTRL_TRUNC_FL); - BW_ENET_FTRL_TRUNC_FL(instance, length); -} - -/*! - * @brief Sets the maximum receive buffer size and the maximum frame size. - * - * @param instance The ENET instance number - * @param maxBufferSize The maximum receive buffer size, which should not be smaller than 256 - * It should be evenly divisible by 16 and the maximum receive size should not be larger than 0x3ff0. - * @param maxFrameSize The maximum receive frame size, the reset value is 1518 or 1522 if the VLAN tags are - * supported. The length is measured starting at DA and including the CRC. - */ -static inline void enet_hal_set_rx_max_size(uint32_t instance, uint32_t maxBufferSize, uint32_t maxFrameSize) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - /* max buffer size must larger than 256 to minimize bus usage*/ - assert(maxBufferSize >= 256); - assert(maxFrameSize <= (BM_ENET_RCR_MAX_FL >> BP_ENET_RCR_MAX_FL)); - - BW_ENET_RCR_MAX_FL(instance, maxFrameSize); - HW_ENET_MRBR_WR(instance, (maxBufferSize & BM_ENET_MRBR_R_BUF_SIZE)); -} - -/*! - * @brief Configures the ENET transmit FIFO. - * - * @param instance The ENET instance number - * @param thresholdCfg The FIFO threshold configuration - */ -void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg); - -/*! - * @brief Configures the ENET receive FIFO. - * - * @param instance The ENET instance number - * @param thresholdCfg The FIFO threshold configuration - */ -void enet_hal_config_rx_fifo(uint32_t instance, enet_config_rx_fifo_t *thresholdCfg); - -/*! - * @brief Sets the start address for ENET receive buffer descriptors. - * - * This interface provides the beginning of the receive - * and receive buffer descriptor queue in the external memory. The - * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16. - * - * @param instance The ENET instance number - * @param rxBdAddr The start address of receive buffer descriptors - */ -static inline void enet_hal_set_rxbd_address(uint32_t instance, uint32_t rxBdAddr) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_RDSR_WR(instance,rxBdAddr); /* Initialize receive buffer descriptor start address*/ -} -/*! - * @brief Sets the start address for ENET transmit buffer descriptors. - * - * This interface provides the beginning of the receive - * and transmit buffer descriptor queue in the external memory. The - * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16. - * - * @param instance The ENET instance number - * @param txBdAddr The start address of transmit buffer descriptors - */ -static inline void enet_hal_set_txbd_address(uint32_t instance, uint32_t txBdAddr) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_TDSR_WR(instance,txBdAddr); /* Initialize transmit buffer descriptor start address*/ -} - -/*! - * @brief Initializes the receive buffer descriptors. - * - * To make sure the uDMA will do the right data transfer after you activate - * with wrap flag and all the buffer descriptors should be initialized with an empty bit. - * - * @param rxBds The current receive buffer descriptor - * @param buffer The data buffer on buffer descriptor - * @param isLastBd The flag to indicate the last receive buffer descriptor - */ -void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd); - -/*! - * @brief Initializes the transmit buffer descriptors. - * - * To make sure the uDMA will do the right data transfer after you active - * with wrap flag. - * - * @param txBds The current transmit buffer descriptor. - * @param isLastBd The last transmit buffer descriptor flag. - */ -void enet_hal_init_txbds(void *txBds, bool isLastBd); - -/*! - * @brief Updates the receive buffer descriptors. - * - * This interface mainly clears the status region and updates the received - * buffer descriptor to ensure that the BD is correctly used. - * - * @param rxBds The current receive buffer descriptor - * @param data The data buffer address - * @param isbufferUpdate The data buffer update flag. When you want to update - * the data buffer of the buffer descriptor ensure that this flag - * is set. - */ -void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate); - -/*! - * @brief Initializes the transmit buffer descriptors. - * - * Ensures that the uDMA transfer data correctly after the user activates - * with the wrap flag. - * - * @param txBds The current transmit buffer descriptor - * @param isLastBd The last transmit buffer descriptor flag - */ -void enet_hal_init_txbds(void *txBds, bool isLastBd); - -/*! - * @brief Updates the transmit buffer descriptors. - * - * This interface mainly clears the status region and updates the transmit - * buffer descriptor to ensure tat this BD is correctly used again. - * You should set the isTxtsCfged when the transmit timestamp feature is required. - * - * @param txBds The current transmit buffer descriptor - * @param buffer The data buffer on buffer descriptor - * @param length The data length on buffer descriptor - * @param isTxtsCfged The timestamp configure flag. The timestamp is - * added to the transmit buffer descriptor when this flag is set. - */ -void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged); - -/*! - * @brief Clears the context in the transmit buffer descriptors. - * - * Clears the data, length, control, and status region of the transmit buffer descriptor. - * - * @param curBd The current buffer descriptor - */ -static inline void enet_hal_clear_txbds(void *curBd) -{ - assert(curBd); - - volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd; - bdPtr->length = 0; /* Set data length*/ - bdPtr->buffer = (uint8_t *)(NULL);/* Set data buffer*/ - bdPtr->control &= (kEnetTxBdWrap);/* Set control */ -} - -/*! - * @brief Gets the control and the status region of the receive buffer descriptors. - * - * This interface can get the whole control and status region of the - * receive buffer descriptor. The enet_rx_bd_control_status_t enum type - * definition should be used if you want to get each status bit of - * the control and status region. - * - * @param curBd The current receive buffer descriptor - * @return The control and status data on buffer descriptors - */ -uint16_t enet_hal_get_rxbd_control(void *curBd); - -/*! - * @brief Gets the control and the status region of the transmit buffer descriptors. - * - * This interface can get the whole control and status region of the - * transmit buffer descriptor. The enet_tx_bd_control_status_t enum type - * definition should be used if you want to get each status bit of - * the control and status region. - * - * @param curBd The current transmit buffer descriptor - * @return The extended control region of transmit buffer descriptor - */ -uint16_t enet_hal_get_txbd_control(void *curBd); - -/*! - * @brief Gets the extended control region of the receive buffer descriptors. - * - * This interface can get the whole control and status region of the - * receive buffer descriptor. The enet_rx_bd_control_extend_t enum type - * definition should be used if you want to get each status bit of - * the control and status region. - * - * @param curBd The current receive buffer descriptor - * @param controlRegion The different control region - * @return The extended control region data of receive buffer descriptor - * - true when the control region is set - * - false when the control region is not set - */ -bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion); -/*! - * @brief Gets the extended control region of the transmit buffer descriptors. - * - * This interface can get the whole control and status region of the - * transmit buffer descriptor. The enet_tx_bd_control_extend_t enum type - * definition should be used if you want to get each status bit of - * the control and status region. - * - * @param curBd The current transmit buffer descriptor - * @return The extended control data - */ -uint16_t enet_hal_get_txbd_control_extend(void *curBd); - -/*! - * @brief Gets the data length of the buffer descriptors. - * - * @param curBd The current buffer descriptor - * @return The data length of the buffer descriptor - */ -uint16_t enet_hal_get_bd_length(void *curBd); - -/*! - * @brief Gets the buffer address of the buffer descriptors. - * - * @param curBd The current buffer descriptor - * @return The buffer address of the buffer descriptor - */ -uint8_t* enet_hal_get_bd_buffer(void *curBd); - -/*! - * @brief Gets the timestamp of the buffer descriptors. - * - * @param curBd The current buffer descriptor - * @return The time stamp of the frame in the buffer descriptor. - * Notice that the frame timestamp is only set in the last - * buffer descriptor of the frame. - */ -uint32_t enet_hal_get_bd_timestamp(void *curBd); - -/*! - * @brief Activates the receive buffer descriptor. - * - * The buffer descriptor activation - * should be done after the ENET module is enabled. Otherwise, the activation fails. - * - * @param instance The ENET instance number - */ - static inline void enet_hal_active_rxbd(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_RDAR_SET(instance, BM_ENET_RDAR_RDAR); -} - -/*! - * @brief Activates the transmit buffer descriptor. - * - * The buffer descriptor activation should be done after the ENET module is - * enabled. Otherwise, the activation fails. - * - * @param instance The ENET instance number - */ -static inline void enet_hal_active_txbd(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_TDAR_SET(instance, BM_ENET_TDAR_TDAR); -} - -/*! - * @brief Configures the (R)MII of ENET. - * - * @param instance The ENET instance number - * @param mode The RMII or MII mode - * @param speed The speed of RMII - * @param duplex The full or half duplex mode - * @param isRxOnTxDisabled The Receive on transmit disable flag - * @param isLoopEnabled The loop enable flag - */ -void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled); - -/*! - * @brief Configures the MII of ENET. - * - * Sets the MII interface between Mac and PHY. The miiSpeed is - * a value that controls the frequency of the MDC, relative to the internal module clock(InterClockSrc). - * A value of zero in this parameter turns the MDC off and leaves it in the low voltage state. - * Any non-zero value results in the MDC frequency MDC = InterClockSrc/((miiSpeed + 1)*2). - * So miiSpeed = InterClockSrc/(2*MDC) - 1. - * The Maximum MDC clock is 2.5MHZ(maximum). We should round up and plus one to simlplify: - * miiSpeed = InterClockSrc/(2*2.5MHZ). - * - * @param instance The ENET instance number - * @param miiSpeed The MII speed and it is ranged from 0~0x3F - * @param time The holdon clock cycles for MDIO output - * @param isPreambleDisabled The preamble disabled flag - */ -static inline void enet_hal_config_mii(uint32_t instance, uint32_t miiSpeed, - enet_mdio_holdon_clkcycle_t clkCycle, bool isPreambleDisabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_MSCR_MII_SPEED(instance, miiSpeed); /* MII speed set*/ - BW_ENET_MSCR_DIS_PRE(instance, isPreambleDisabled); /* Preamble is disabled*/ - BW_ENET_MSCR_HOLDTIME(instance, clkCycle); /* hold on clock cycles for MDIO output*/ - -} - -/*! - * @brief Gets the MII configuration status. - * - * This interface is usually called to check the MII interface before - * the Mac writes or reads the PHY registers. - * - * @param instance The ENET instance number - * @return The MII configuration status - * - true if the MII has been configured. - * - false if the MII has not been configured. - */ -static inline bool enet_hal_is_mii_enabled(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return (HW_ENET_MSCR_RD(instance) & 0x7E)!= 0; -} - -/*! - * @brief Reads data from PHY. - * - * @param instance The ENET instance number - * @return The data read from PHY - */ -static inline uint32_t enet_hal_get_mii_data(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return (uint32_t)BR_ENET_MMFR_DATA(instance); -} - -/*! - * @brief Sets the MII command. - * - * @param instance The ENET instance number - * @param phyAddr The PHY address - * @param phyReg The PHY register - * @param operation The read or write operation - * @param data The data written to PHY - */ -void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data); - -/*! - * @brief Enables/Disables the ENET module. - * - * @param instance The ENET instance number - * @param isEnhanced The enhanced 1588 feature switch - * @param isEnabled The ENET module enable switch - */ -void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled); - -/*! - * @brief Enables/Disables the ENET interrupt. - * - * @param instance The ENET instance number - * @param source The interrupt sources. enet_interrupt_request_t enum types - * is recommended as the interrupt source. - * @param isEnabled The interrupt enable switch - */ -void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled); - -/*! - * @brief Clears ENET interrupt events. - * - * @param instance The ENET instance number - * @param source The interrupt source to be cleared. enet_interrupt_request_t - * enum types is recommended as the interrupt source. - */ -static inline void enet_hal_clear_interrupt(uint32_t instance, uint32_t source) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_EIR_WR(instance,source); -} - -/*! - * @brief Gets the ENET interrupt status. - * - * @param instance The ENET instance number - * @param source The interrupt sources. enet_interrupt_request_t - * enum types is recommended as the interrupt source. - * @return The event status of the interrupt source - * - true if the interrupt event happened. - * - false if the interrupt event has not happened. - */ -static inline bool enet_hal_get_interrupt_status(uint32_t instance, uint32_t source) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return ((HW_ENET_EIR_RD(instance) & source) != 0); -} - -/* - * @brief Enables/disables the ENET promiscuous mode. - * - * @param instance The ENET instance number - * @param isEnabled The enable switch - */ -static inline void enet_hal_config_promiscuous(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_RCR_PROM(instance,isEnabled); -} - -/*! - * @brief Enables/disables the clear MIB counter. - * - * @param instance The ENET instance number - * @param isEnabled The enable switch - */ -static inline void enet_hal_clear_mib(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_MIBC_MIB_CLEAR(instance, isEnabled); - -} - -/*! - * @brief Sets the enable/disable of the MIB block. - * - * @param instance The ENET instance number - * @param isEnabled The enable flag - * - True to enabale MIB block. - * - False to disable MIB block. - */ -static inline void enet_hal_enable_mib(uint32_t instance, bool isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_MIBC_MIB_DIS(instance,!isEnabled); - -} - -/*! - * @brief Gets the MIB idle status. - * - * @param instance The ENET instance number - * @return true if in MIB idle and MIB is not updating else false. - */ -static inline bool enet_hal_get_mib_status(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return BR_ENET_MIBC_MIB_IDLE(instance); -} - -/*! - * @brief Sets the transmit accelerator. - * - * @param instance The ENET instance number - * @param txCfgPtr The transmit accelerator configuration - */ -void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr); - -/*! - * @brief Sets the receive accelerator. - * - * @param instance The ENET instance number - * @param rxCfgPtr The receive accelerator configuration - */ -void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr); - -/*! - * @brief Initializes the 1588 timer. - * - * This interface initializes the 1588 context structure. - * Initialize 1588 parameters according to the user configuration structure. - * - * @param instance The ENET instance number - * @param ptpCfg The 1588 timer configuration - */ -void enet_hal_init_ptp_timer(uint32_t instance, enet_config_ptp_timer_t *ptpCfgPtr); - -/*! - * @brief Enables or disables the 1588 timer. - * - * Enable the PTP timer will starts the timer. Disable the timer will stop timer - * at the current value. - * - * @param instance The ENET instance number. - * @param isEnabled The 1588 timer Enable switch - * - True enbaled the 1588 PTP timer. - * - False disable or stop the 1588 PTP timer. - */ -static inline void enet_hal_enable_ptp_timer(uint32_t instance, uint32_t isEnabled) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_ATCR_EN(instance,isEnabled); -} - -/*! - * @brief Restarts the 1588 timer. - * - * Restarting the PTP timer clears all PTP-timer counters to zero. - * - * @param instance The ENET instance number - */ -static inline void enet_hal_restart_ptp_timer(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - BW_ENET_ATCR_RESTART(instance,1); -} - -/*! - * @brief Adjusts the 1588 timer. - * - * Adjust the 1588 timer according to the increase and correction period of the configured correction. - * - * @param instance The ENET instance number - * @param inceaseCorrection The increase correction for 1588 timer - * @param periodCorrection The period correction for 1588 timer - */ -static inline void enet_hal_adjust_ptp_timer(uint32_t instance, uint32_t increaseCorrection, uint32_t periodCorrection) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_ATINC_SET(instance,((increaseCorrection << ENET_ATINC_INC_CORR_SHIFT) & ENET_ATINC_INC_CORR_MASK)); /* set correction for ptp timer increase*/ - /* set correction for ptp timer period*/ - HW_ENET_ATCOR_SET(instance, (BM_ENET_ATCOR_COR & periodCorrection)); -} - -/*! - * @brief Initializes the 1588 timer channel. - * - * @param instance The ENET instance number - * @Param channel The 1588 timer channel number - * @param mode Compare or capture mode for the 1588 timer channel - */ -static inline void enet_hal_init_timer_channel(uint32_t instance, uint32_t channel, enet_timer_channel_mode_t mode) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(channel < HW_ENET_TCSRn_COUNT); - HW_ENET_TCSRn_SET(instance, channel, - (BM_ENET_TCSRn_TMODE &(mode << BP_ENET_TCSRn_TMODE))); - HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TIE); -} - -/*! - * @brief Sets the compare value for the 1588 timer channel. - * - * @param instance The ENET instance number - * @Param channel The 1588 timer channel number - * @param compareValue Compare value for 1588 timer channel - */ -static inline void enet_hal_set_timer_channel_compare(uint32_t instance, uint32_t channel, uint32_t compareValue) -{ - assert(instance < HW_ENET_INSTANCE_COUNT); - assert(channel < HW_ENET_TCSRn_COUNT); - HW_ENET_TCCRn_WR(instance,channel, compareValue); -} - -/*! - * @brief Gets the 1588 timer channel status. - * - * @param instance The ENET instance number - * @param channel The 1588 timer channel number - * @return Compare or capture operation status - * - True if the compare or capture has occurred. - * - False if the compare or capture has not occurred. - */ -static inline bool enet_hal_get_timer_channel_status(uint32_t instance, uint32_t channel) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(channel < HW_ENET_TCSRn_COUNT); - - return BR_ENET_TCSRn_TF(instance,channel); -} - -/*! - * @brief Clears the 1588 timer channel flag. - * - * @param instance The ENET instance number - * @param channel The 1588 timer channel number - */ -static inline void enet_hal_clear_timer_channel_flag(uint32_t instance, uint32_t channel) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - assert(channel < HW_ENET_TCSRn_COUNT); - HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TF);/* clear interrupt flag*/ - HW_ENET_TGSR_WR(instance,(1U << channel)); /* clear channel flag*/ -} - -/*! - * @brief Sets the capture command to the 1588 timer. - * - * This is used before reading the current time register. - * After set timer capture, please wait for about 1us before read - * the captured timer. - * - * @param instance The ENET instance number - */ -static inline void enet_hal_set_timer_capture(uint32_t instance) -{ - assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_ATCR_SET(instance, BM_ENET_ATCR_CAPTURE); -} - -/*! - * @brief Sets the 1588 timer. - * - * @param instance The ENET instance number - * @param nanSecond The nanosecond set to 1588 timer - */ -static inline void enet_hal_set_current_time(uint32_t instance, uint32_t nanSecond) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - HW_ENET_ATVR_WR(instance,nanSecond); -} - -/*! - * @brief Gets the time from the 1588 timer. - * - * @param instance The ENET instance number - * @return the current time from 1588 timer - */ -static inline uint32_t enet_hal_get_current_time(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return HW_ENET_ATVR_RD(instance); -} - -/*! - * @brief Gets the transmit timestamp. - * - * @param instance The ENET instance number - * @return The timestamp of the last transmitted frame - */ -static inline uint32_t enet_hal_get_tx_timestamp(uint32_t instance) -{ - // assert(instance < HW_ENET_INSTANCE_COUNT); - - return HW_ENET_ATSTMP_RD(instance); -} - -/*! - * @brief Gets the transmit buffer descriptor timestamp flag. - * - * @param curBd The ENET transmit buffer descriptor - * @return true if timestamp region is set else false. - */ -bool enet_hal_get_txbd_timestamp_flag(void *curBd); - -/*! - * @brief Gets the buffer descriptor timestamp. - * - * @param null - * @return The the size of the buffer descriptor - */ -static inline uint32_t enet_hal_get_bd_size(void) -{ - return sizeof(enet_bd_struct_t); -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif - -/*! @}*/ -#endif /*!< __FSL_ENET_HAL_H__*/ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_features.h deleted file mode 100644 index 48c31906a8e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_features.h +++ /dev/null @@ -1,156 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_FTM_FEATURES_H__) -#define __FSL_FTM_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (6) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (6) : \ - ((x) == 1 ? (2) : \ - ((x) == 2 ? (2) : (-1)))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (2) : (-1))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (2) : \ - ((x) == 2 ? (2) : (-1)))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) -#elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (2) : \ - ((x) == 2 ? (2) : \ - ((x) == 3 ? (8) : (-1))))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ - defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \ - defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \ - defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ - defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (2) : \ - ((x) == 2 ? (2) : \ - ((x) == 3 ? (8) : (-1))))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (2) : (-1))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) -#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) - /* @brief Bus clock is the source clock for the module. */ - #define FSL_FEATURE_FTM_BUS_CLOCK (1) - /* @brief Number of channels. */ - #define FSL_FEATURE_FTM_CHANNEL_COUNT (8) - #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (2) : \ - ((x) == 2 ? (8) : (-1)))) - /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ - #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_FTM_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c deleted file mode 100644 index 190870c759e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_ftm_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -void FTM_HAL_Init(uint32_t ftmBaseAddr) -{ - -} - -void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel) -{ - FTM_HAL_SetDualEdgeCaptureCmd(ftmBaseAddr, channel, false); - FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, config->edgeMode ? 1 : 2); - switch(config->mode) - { - case kFtmEdgeAlignedPWM: - FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false); - FTM_HAL_SetCpwms(ftmBaseAddr, 0); - FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 2); - break; - case kFtmCenterAlignedPWM: - FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false); - FTM_HAL_SetCpwms(ftmBaseAddr, 1); - break; - case kFtmCombinedPWM: - FTM_HAL_SetCpwms(ftmBaseAddr, 0); - FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, true); - break; - default: - assert(0); - break; - } -} - -void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel) -{ - - FTM_HAL_SetChnCountVal(ftmBaseAddr, channel, 0); - FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, 0); - FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 0); - FTM_HAL_SetCpwms(ftmBaseAddr, 0); - FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false); -} - -void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance) -{ - uint8_t chan = FSL_FEATURE_FTM_CHANNEL_COUNTn(instance); - - HW_FTM_SC_WR(ftmBaseAddr, 0); - HW_FTM_CNT_WR(ftmBaseAddr, 0); - HW_FTM_MOD_WR(ftmBaseAddr, 0); - - for(int i = 0; i < chan; i++) - { - HW_FTM_CnSC_WR(ftmBaseAddr, i, 0); - HW_FTM_CnV_WR(ftmBaseAddr, i, 0); - } - HW_FTM_CNTIN_WR(ftmBaseAddr, 0); - HW_FTM_STATUS_WR(ftmBaseAddr, 0); - HW_FTM_MODE_WR(ftmBaseAddr, 0x00000004); - HW_FTM_SYNC_WR(ftmBaseAddr, 0); - HW_FTM_OUTINIT_WR(ftmBaseAddr, 0); - HW_FTM_OUTMASK_WR(ftmBaseAddr, 0); - HW_FTM_COMBINE_WR(ftmBaseAddr, 0); - HW_FTM_DEADTIME_WR(ftmBaseAddr, 0); - HW_FTM_EXTTRIG_WR(ftmBaseAddr, 0); - HW_FTM_POL_WR(ftmBaseAddr, 0); - HW_FTM_FMS_WR(ftmBaseAddr, 0); - HW_FTM_FILTER_WR(ftmBaseAddr, 0); - HW_FTM_FLTCTRL_WR(ftmBaseAddr, 0); - /*HW_FTM_QDCTRL_WR(instance, 0);*/ - HW_FTM_CONF_WR(ftmBaseAddr, 0); - HW_FTM_FLTPOL_WR(ftmBaseAddr, 0); - HW_FTM_SYNCONF_WR(ftmBaseAddr, 0); - HW_FTM_INVCTRL_WR(ftmBaseAddr, 0); - HW_FTM_SWOCTRL_WR(ftmBaseAddr, 0); - HW_FTM_PWMLOAD_WR(ftmBaseAddr, 0); -} - -void FTM_HAL_SetHardwareTriggerCmd(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable) -{ - switch(trigger_num) - { - case 0: - BW_FTM_SYNC_TRIG0(ftmBaseAddr, enable ? 1 : 0); - break; - case 1: - BW_FTM_SYNC_TRIG1(ftmBaseAddr, enable ? 1 : 0); - break; - case 2: - BW_FTM_SYNC_TRIG2(ftmBaseAddr, enable ? 1 : 0); - break; - default: - assert(0); - break; - } -} - -void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val) -{ - assert(channel < HW_CHAN6); - - uint8_t bit = val ? 1 : 0; - uint32_t value = (channel > 1U) ? (uint8_t)(bit << (channel - 2U)) : (uint8_t)(bit << (channel + 4U)); - - val ? HW_FTM_EXTTRIG_SET(ftmBaseAddr, value) : HW_FTM_EXTTRIG_CLR(ftmBaseAddr, value); -} - -void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val) -{ - assert(channel < HW_CHAN4); - - switch(channel) - { - case HW_CHAN0: - BW_FTM_FILTER_CH0FVAL(ftmBaseAddr, val); - break; - case HW_CHAN1: - BW_FTM_FILTER_CH1FVAL(ftmBaseAddr, val); - break; - case HW_CHAN2: - BW_FTM_FILTER_CH2FVAL(ftmBaseAddr, val); - break; - case HW_CHAN3: - BW_FTM_FILTER_CH3FVAL(ftmBaseAddr, val); - break; - default: - assert(0); - break; - } -} - -uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel) -{ - if((channel == HW_CHAN0) || (channel == HW_CHAN1)) - { - return 0; - } - else if((channel == HW_CHAN2) || (channel == HW_CHAN3)) - { - return 1; - } - else if((channel == HW_CHAN4) || (channel == HW_CHAN5)) - { - return 2; - } - else - { - return 3; - } -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h deleted file mode 100644 index d4f8a1e54c4..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h +++ /dev/null @@ -1,1433 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_FTM_HAL_H__) -#define __FSL_FTM_HAL_H__ - -#include "fsl_device_registers.h" -#include "fsl_ftm_features.h" -#include -#include - -/*! - * @addtogroup ftm_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define HW_CHAN0 (0U) /*!< Channel number for CHAN0.*/ -#define HW_CHAN1 (1U) /*!< Channel number for CHAN1.*/ -#define HW_CHAN2 (2U) /*!< Channel number for CHAN2.*/ -#define HW_CHAN3 (3U) /*!< Channel number for CHAN3.*/ -#define HW_CHAN4 (4U) /*!< Channel number for CHAN4.*/ -#define HW_CHAN5 (5U) /*!< Channel number for CHAN5.*/ -#define HW_CHAN6 (6U) /*!< Channel number for CHAN6.*/ -#define HW_CHAN7 (7U) /*!< Channel number for CHAN7.*/ - -#define FTM_COMBINE_CHAN_CTRL_WIDTH (8U) - -/*! @brief FlexTimer clock source selection*/ -typedef enum _ftm_clock_source -{ - kClock_source_FTM_None = 0, - kClock_source_FTM_SystemClk, - kClock_source_FTM_FixedClk, - kClock_source_FTM_ExternalClk -}ftm_clock_source_t; - -/*! @brief FlexTimer counting mode selection */ -typedef enum _ftm_counting_mode -{ - kCounting_FTM_UP = 0, - kCounting_FTM_UpDown -}ftm_counting_mode_t; - -/*! @brief FlexTimer pre-scaler factor selection for the clock source*/ -typedef enum _ftm_clock_ps -{ - kFtmDividedBy1 = 0, - kFtmDividedBy2 , - kFtmDividedBy4 , - kFtmDividedBy8, - kFtmDividedBy16, - kFtmDividedBy32, - kFtmDividedBy64, - kFtmDividedBy128 -}ftm_clock_ps_t; - -/*! @brief FlexTimer pre-scaler factor for the deadtime insertion*/ -typedef enum _ftm_deadtime_ps -{ - kFtmDivided1 = 1, - kFtmDivided4 = 2, - kFtmDivided16 = 3, -}ftm_deadtime_ps_t; - -/*! @brief FlexTimer operation mode, capture, output, dual */ -typedef enum _ftm_config_mode_t -{ - kFtmInputCapture, - kFtmOutputCompare, - kFtmEdgeAlignedPWM, - kFtmCenterAlignedPWM, - kFtmCombinedPWM, - kFtmDualEdgeCapture -}ftm_config_mode_t; - -/*! @brief FlexTimer input capture edge mode, rising edge, or falling edge */ -typedef enum _ftm_input_capture_edge_mode_t -{ - kFtmRisingEdge = 0, - kFtmFallingEdge, - kFtmRisingAndFalling -}ftm_input_capture_edge_mode_t; - -/*! @brief FlexTimer output compare edge mode. Toggle, clear or set.*/ -typedef enum _ftm_output_compare_edge_mode_t -{ - kFtmToggleOnMatch = 0, - kFtmClearOnMatch, - kFtmSetOnMatch -}ftm_output_compare_edge_mode_t; - -/*! @brief FlexTimer PWM output pulse mode, high-true or low-true on match up */ -typedef enum _ftm_pwm_edge_mode_t -{ - kFtmHighTrue = 0, - kFtmLowTrue -}ftm_pwm_edge_mode_t; - -/*! @brief FlexTimer dual capture edge mode, one shot or continuous */ -typedef enum _ftm_dual_capture_edge_mode_t -{ - kFtmOneShout = 0, - kFtmContinuous -}ftm_dual_capture_edge_mode_t; - -/*! @brief FlexTimer quadrature decode modes, phase encode or count and direction mode */ -typedef enum _ftm_quad_decode_mode_t -{ - kFtmQuadPhaseEncode = 0, - kFtmQuadCountAndDir -}ftm_quad_decode_mode_t; - -/*! @brief FlexTimer quadrature phase polarities, normal or inverted polarity */ -typedef enum _ftm_quad_phase_polarity_t -{ - kFtmQuadPhaseNormal = 0, - kFtmQuadPhaseInvert -}ftm_quad_phase_polarity_t; - -/*! @brief FlexTimer edge mode*/ -typedef union _ftm_edge_mode_t -{ - ftm_input_capture_edge_mode_t input_capture_edge_mode; - ftm_output_compare_edge_mode_t output_compare_edge_mode; - ftm_pwm_edge_mode_t ftm_pwm_edge_mode; - ftm_dual_capture_edge_mode_t ftm_dual_capture_edge_mode; -}ftm_edge_mode_t; - -/*! - * @brief FlexTimer driver PWM parameter - * - */ -typedef struct FtmPwmParam -{ - ftm_config_mode_t mode; /*!< FlexTimer PWM operation mode */ - ftm_pwm_edge_mode_t edgeMode; /*!< PWM output mode */ - uint32_t uFrequencyHZ; /*!< PWM period in Hz */ - uint32_t uDutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0=inactive signal(0% duty cycle)... - 100=active signal (100% duty cycle). */ - uint16_t uFirstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM. - Specifies the delay to the first edge in a PWM period. - If unsure please leave as 0, should be specified as - percentage of the PWM period*/ -}ftm_pwm_param_t; - -/*! @brief FlexTimer quadrature decode phase parameters */ -typedef struct FtmPhaseParam -{ - bool kFtmPhaseInputFilter; /*!< false: disable phase filter, true: enable phase filter */ - uint32_t kFtmPhaseFilterVal; /*!< Filter value, used only if phase input filter is enabled */ - ftm_quad_phase_polarity_t kFtmPhasePolarity; /*!< kFtmQuadPhaseNormal or kFtmQuadPhaseInvert */ -}ftm_phase_params_t; - -/*FTM timer control*/ -/*! - * @brief Sets the FTM clock source. - * - * @param ftmBaseAddr The FTM base address - * @param clock The FTM peripheral clock selection\n - * bits - 00: No clock 01: system clock 10: fixed clock 11: External clock - */ -static inline void FTM_HAL_SetClockSource(uint32_t ftmBaseAddr, ftm_clock_source_t clock) -{ - BW_FTM_SC_CLKS(ftmBaseAddr, clock); -} - -/*! - * @brief Reads the FTM clock source. - * - * @param ftmBaseAddr The FTM base address - * - * @return The FTM clock source selection\n - * bits - 00: No clock 01: system clock 10: fixed clock 11:External clock - */ -static inline uint8_t FTM_HAL_GetClockSource(uint32_t ftmBaseAddr) -{ - return BR_FTM_SC_CLKS(ftmBaseAddr); -} - -/*! - * @brief Sets the FTM clock divider. - * - * @param ftmBaseAddr The FTM base address - * @param ps The FTM peripheral clock pre-scale divider - */ -static inline void FTM_HAL_SetClockPs(uint32_t ftmBaseAddr, ftm_clock_ps_t ps) -{ - BW_FTM_SC_PS(ftmBaseAddr, ps); -} - -/*! - * @brief Reads the FTM clock divider. - * - * @param ftmBaseAddr The FTM base address - * - * @return The FTM clock pre-scale divider - */ -static inline uint8_t FTM_HAL_GetClockPs(uint32_t ftmBaseAddr) -{ - return BR_FTM_SC_PS(ftmBaseAddr); -} - -/*! - * @brief Enables the FTM peripheral timer overflow interrupt. - * - * @param ftmBaseAddr The FTM base address - */ -static inline void FTM_HAL_EnableTimerOverflowInt(uint32_t ftmBaseAddr) -{ - HW_FTM_SC_SET(ftmBaseAddr, BM_FTM_SC_TOIE); -} - -/*! - * @brief Disables the FTM peripheral timer overflow interrupt. - * - * @param ftmBaseAddr The FTM base address - */ -static inline void FTM_HAL_DisableTimerOverflowInt(uint32_t ftmBaseAddr) -{ - HW_FTM_SC_CLR(ftmBaseAddr, BM_FTM_SC_TOIE); -} - -/*! - * @brief Reads the bit that controls enabling the FTM timer overflow interrupt. - * - * @param baseAddr FTM module base address. - * @retval true if overflow interrupt is enabled, false if not - */ -static inline bool FTM_HAL_IsOverflowIntEnabled(uint32_t baseAddr) -{ - return (bool)(BR_FTM_SC_TOIE(baseAddr)); -} - -/*! - * @brief Clears the timer overflow interrupt flag. - * - * @param ftmBaseAddr The FTM base address - */ -static inline void FTM_HAL_ClearTimerOverflow(uint32_t ftmBaseAddr) -{ - BW_FTM_SC_TOF(ftmBaseAddr, 0); -} - -/*! - * @brief Returns the FTM peripheral timer overflow interrupt flag. - * - * @param ftmBaseAddr The FTM base address - * @retval true if overflow, false if not - */ -static inline bool FTM_HAL_HasTimerOverflowed(uint32_t ftmBaseAddr) -{ - return BR_FTM_SC_TOF(ftmBaseAddr); -} - -/*! - * @brief Sets the FTM center-aligned PWM select. - * - * @param ftmBaseAddr The FTM base address - * @param mode 1:upcounting mode 0:up_down counting mode - */ -static inline void FTM_HAL_SetCpwms(uint32_t ftmBaseAddr, uint8_t mode) -{ - assert(mode < 2); - BW_FTM_SC_CPWMS(ftmBaseAddr, mode); -} - -/*! - * @brief Sets the FTM peripheral current counter value. - * - * @param ftmBaseAddr The FTM base address - * @param val FTM timer counter value to be set - */ -static inline void FTM_HAL_SetCounter(uint32_t ftmBaseAddr,uint16_t val) -{ - BW_FTM_CNT_COUNT(ftmBaseAddr, val); -} - -/*! - * @brief Returns the FTM peripheral current counter value. - * - * @param ftmBaseAddr The FTM base address - * @retval current FTM timer counter value - */ -static inline uint16_t FTM_HAL_GetCounter(uint32_t ftmBaseAddr) -{ - return BR_FTM_CNT_COUNT(ftmBaseAddr); -} - -/*! - * @brief Sets the FTM peripheral timer modulo value. - * - * @param ftmBaseAddr The FTM base address - * @param val The value to be set to the timer modulo - */ -static inline void FTM_HAL_SetMod(uint32_t ftmBaseAddr, uint16_t val) -{ - BW_FTM_MOD_MOD(ftmBaseAddr, val); -} - -/*! - * @brief Returns the FTM peripheral counter modulo value. - * - * @param ftmBaseAddr The FTM base address - * @retval FTM timer modulo value - */ -static inline uint16_t FTM_HAL_GetMod(uint32_t ftmBaseAddr) -{ - return BR_FTM_MOD_MOD(ftmBaseAddr); -} - -/*! - * @brief Sets the FTM peripheral timer counter initial value. - * - * @param ftmBaseAddr The FTM base address - * @param val initial value to be set - */ -static inline void FTM_HAL_SetCounterInitVal(uint32_t ftmBaseAddr, uint16_t val) -{ - BW_FTM_CNTIN_INIT(ftmBaseAddr, val & BM_FTM_CNTIN_INIT); -} - -/*! - * @brief Returns the FTM peripheral counter initial value. - * - * @param ftmBaseAddr The FTM base address - * @retval FTM timer counter initial value - */ -static inline uint16_t FTM_HAL_GetCounterInitVal(uint32_t ftmBaseAddr) -{ - return BR_FTM_CNTIN_INIT(ftmBaseAddr); -} - -/*FTM channel operating mode (Mode, edge and level selection) for capture, output, PWM, combine, dual */ -/*! - * @brief Sets the FTM peripheral timer channel mode. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param selection The mode to be set valid value MSnB:MSnA :00,01, 10, 11 - */ -static inline void FTM_HAL_SetChnMSnBAMode(uint32_t ftmBaseAddr, uint8_t channel, uint8_t selection) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - BW_FTM_CnSC_MSA(ftmBaseAddr, channel, selection & 1); - BW_FTM_CnSC_MSB(ftmBaseAddr, channel, selection & 2 ? 1 : 0); -} - -/*! - * @brief Sets the FTM peripheral timer channel edge level. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param level The rising or falling edge to be set, valid value ELSnB:ELSnA :00,01, 10, 11 - */ -static inline void FTM_HAL_SetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel, uint8_t level) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - BW_FTM_CnSC_ELSA(ftmBaseAddr, channel, level & 1 ? 1 : 0); - BW_FTM_CnSC_ELSB(ftmBaseAddr, channel, level & 2 ? 1 : 0); -} - -/*! - * @brief Gets the FTM peripheral timer channel mode. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval The MSnB:MSnA mode value, will be 00,01, 10, 11 - */ -static inline uint8_t FTM_HAL_GetChnMode(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - return (BR_FTM_CnSC_MSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_MSB(ftmBaseAddr, channel) << 1)); -} - -/*! - * @brief Gets the FTM peripheral timer channel edge level. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval The ELSnB:ELSnA mode value, will be 00,01, 10, 11 - */ -static inline uint8_t FTM_HAL_GetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - return (BR_FTM_CnSC_ELSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_ELSB(ftmBaseAddr, channel) << 1)); -} - -/*! - * @brief Enables or disables the FTM peripheral timer channel DMA. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param val enable or disable - */ -static inline void FTM_HAL_SetChnDmaCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - BW_FTM_CnSC_DMA(ftmBaseAddr, channel,(val? 1 : 0)); -} - -/*! - * @brief Returns whether the FTM peripheral timer channel DMA is enabled. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval true if enabled, false if disabled - */ -static inline bool FTM_HAL_IsChnDma(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - return (BR_FTM_CnSC_DMA(ftmBaseAddr, channel) ? true : false); -} - -/*! - * @brief Enables the FTM peripheral timer channel(n) interrupt. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - */ -static inline void FTM_HAL_EnableChnInt(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 1); -} -/*! - * @brief Disables the FTM peripheral timer channel(n) interrupt. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - */ -static inline void FTM_HAL_DisableChnInt(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 0); -} - -/*! - * @brief Returns whether any event for the FTM peripheral timer channel has occurred. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval true if event occurred, false otherwise. - */ -static inline bool FTM_HAL_HasChnEventOccurred(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - return (BR_FTM_CnSC_CHF(ftmBaseAddr, channel)) ? true : false; -} - -/*FTM channel control*/ -/*! - * @brief Sets the FTM peripheral timer channel counter value. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param val counter value to be set - */ -static inline void FTM_HAL_SetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - HW_FTM_CnV_WR(ftmBaseAddr, channel, val); -} - -/*! - * @brief Gets the FTM peripheral timer channel counter value. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval val return current channel counter value - */ -static inline uint16_t FTM_HAL_GetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - return BR_FTM_CnV_VAL(ftmBaseAddr, channel); -} - -/*! - * @brief Gets the FTM peripheral timer channel event status. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval val return current channel event status value - */ -static inline uint32_t FTM_HAL_GetChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - return (HW_FTM_STATUS_RD(ftmBaseAddr)&(1U << channel)) ? true : false; - /*return BR_FTM_STATUS(ftmBaseAddr, channel);*/ -} - -/*! - * @brief Clears the FTM peripheral timer all channel event status. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @retval val return current channel counter value - */ -static inline void FTM_HAL_ClearChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - HW_FTM_STATUS_CLR(ftmBaseAddr, 1U << channel); -} - -/*! - * @brief Sets the FTM peripheral timer channel output mask. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param mask mask to be set 0 or 1, unmasked or masked - */ -static inline void FTM_HAL_SetChnOutputMask(uint32_t ftmBaseAddr, uint8_t channel, bool mask) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - mask? HW_FTM_OUTMASK_SET(ftmBaseAddr, 1U << channel) : HW_FTM_OUTMASK_CLR(ftmBaseAddr, 1U << channel); - /* BW_FTM_OUTMASK_CHnOM(ftmBaseAddr, channel,mask); */ -} - -/*! - * @brief Sets the FTM peripheral timer channel output initial state 0 or 1. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param state counter value to be set 0 or 1 - */ -static inline void FTM_HAL_SetChnOutputInitState(uint32_t ftmBaseAddr, uint8_t channel, uint8_t state) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - HW_FTM_OUTINIT_CLR(ftmBaseAddr, 1U << channel); - HW_FTM_OUTINIT_SET(ftmBaseAddr, (uint8_t)(state << channel)); -} - -/*! - * @brief Sets the FTM peripheral timer channel output polarity. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param pol polarity to be set 0 or 1 - */ -static inline void FTM_HAL_SetChnOutputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - HW_FTM_POL_CLR(ftmBaseAddr, 1U << channel); - HW_FTM_POL_SET(ftmBaseAddr, (uint8_t)(pol << channel)); -} -/*! - * @brief Sets the FTM peripheral timer channel input polarity. - * - * @param ftmBaseAddr The FTM base address - * @param channel The FTM peripheral channel number - * @param pol polarity to be set, 0: active high, 1:active low - */ -static inline void FTM_HAL_SetChnFaultInputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol) -{ - assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); - HW_FTM_FLTPOL_CLR(ftmBaseAddr, 1U << channel); - HW_FTM_FLTPOL_SET(ftmBaseAddr, (uint8_t)(pol< -#include -#include -#include "fsl_gpio_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup gpio_hal - * @{ - */ - -/*! - * @file fsl_gpio_hal.h - * - * @brief GPIO hardware driver configuration. Use these functions to set the GPIO input/output, - * set output logic or get input logic. Check the GPIO header file for base address. Each - * GPIO instance has 32 pins with numbers from 0 to 31. - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief GPIO direction definition*/ -typedef enum _gpio_pin_direction { - kGpioDigitalInput = 0, /*!< Set current pin as digital input*/ - kGpioDigitalOutput = 1 /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Configuration - * @{ - */ - -/*! - * @brief Sets the individual GPIO pin to general input or output. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - * @param direction GPIO directions - * - kGpioDigitalInput: set to input - * - kGpioDigitalOutput: set to output - */ -void GPIO_HAL_SetPinDir(uint32_t baseAddr, uint32_t pin, - gpio_pin_direction_t direction); - -/*! - * @brief Sets the GPIO port pins to general input or output. - * - * This function operates all 32 port pins. - * - * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param direction GPIO directions - * - 0: set to input - * - 1: set to output - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline void GPIO_HAL_SetPortDir(uint32_t baseAddr, uint32_t direction) -{ - HW_GPIO_PDDR_WR(baseAddr, direction); -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the current direction of the individual GPIO pin. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - * @return GPIO directions - * - kGpioDigitalInput: corresponding pin is set to input. - * - kGpioDigitalOutput: corresponding pin is set to output. - */ -static inline gpio_pin_direction_t GPIO_HAL_GetPinDir(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - return (gpio_pin_direction_t)((HW_GPIO_PDDR_RD(baseAddr) >> pin) & 1U); -} - -/*! - * @brief Gets the GPIO port pins direction. - * - * This function gets all 32-pin directions as a 32-bit integer. - * - * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @return GPIO directions. Each bit represents one pin. For each bit: - * - 0: corresponding pin is set to input - * - 1: corresponding pin is set to output - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline uint32_t GPIO_HAL_GetPortDir(uint32_t baseAddr) -{ - return HW_GPIO_PDDR_RD(baseAddr); -} - -/* @} */ - -/*! - * @name Output Operation - * @{ - */ - -/*! - * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - * @param output pin output logic level - */ -void GPIO_HAL_WritePinOutput(uint32_t baseAddr, uint32_t pin, uint32_t output); - -/*! - * @brief Reads the current pin output. - * - * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - * @return current pin output status. 0 - Low logic, 1 - High logic - */ -static inline uint32_t GPIO_HAL_ReadPinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - return ((HW_GPIO_PDOR_RD(baseAddr) >> pin) & 0x1U); -} - -/*! - * @brief Sets the output level of the individual GPIO pin to logic 1. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - */ -static inline void GPIO_HAL_SetPinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - HW_GPIO_PSOR_WR(baseAddr, 1U << pin); -} - -/*! - * @brief Clears the output level of the individual GPIO pin to logic 0. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - */ -static inline void GPIO_HAL_ClearPinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - HW_GPIO_PCOR_WR(baseAddr, 1U << pin); -} - -/*! - * @brief Reverses the current output logic of the individual GPIO pin. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - */ -static inline void GPIO_HAL_TogglePinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - HW_GPIO_PTOR_WR(baseAddr, 1U << pin); -} - -/*! - * @brief Sets the output of the GPIO port to a specific logic value. - * - * This function operates all 32 port pins. - * - * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param portOutput data to configure the GPIO output. Each bit represents one pin. For each bit: - * - 0: set logic level 0 to pin - * - 1: set logic level 1 to pin - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline void GPIO_HAL_WritePortOutput(uint32_t baseAddr, uint32_t portOutput) -{ - HW_GPIO_PDOR_WR(baseAddr, portOutput); -} - -/*! - * @brief Reads out all pin output status of the current port. - * - * This function operates all 32 port pins. - * - * @param baseAddr GPIO base address (HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @return current port output status. Each bit represents one pin. For each bit: - * - 0: corresponding pin is outputting logic level 0 - * - 1: corresponding pin is outputting logic level 1 - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline uint32_t GPIO_HAL_ReadPortOutput(uint32_t baseAddr) -{ - return HW_GPIO_PDOR_RD(baseAddr); -} - -/* @} */ - -/*! - * @name Input Operation - * @{ - */ - -/*! - * @brief Reads the current input value of the individual GPIO pin. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @param pin GPIO port pin number - * @return GPIO port input value - * - 0: Pin logic level is 0, or is not configured for use by digital function. - * - 1: Pin logic level is 1 - */ -static inline uint32_t GPIO_HAL_ReadPinInput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - return (HW_GPIO_PDIR_RD(baseAddr) >> pin) & 1U; -} - -/*! - * @brief Reads the current input value of a specific GPIO port. - * - * This function gets all 32-pin input as a 32-bit integer. - * - * @param baseAddr GPIO base address(HW_GPIOA, HW_GPIOB, HW_GPIOC, etc.) - * @return GPIO port input data. Each bit represents one pin. For each bit: - * - 0: Pin logic level is 0, or is not configured for use by digital function. - * - 1: Pin logic level is 1. - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline uint32_t GPIO_HAL_ReadPortInput(uint32_t baseAddr) -{ - return HW_GPIO_PDIR_RD(baseAddr); -} - -/* @} */ - -/*! - * @name FGPIO Operation - * - * @note FGPIO (Fast GPIO) is only available in a few MCUs. FGPIO and GPIO share the same - * peripheral but use different registers. FGPIO is closer to the core than the regular GPIO - * and it's faster to read and write. - * @{ - */ - -#if FSL_FEATURE_GPIO_HAS_FAST_GPIO - -/*! - * @name Output Operation - * @{ - */ - -/*! - * @brief Sets the output level of an individual FGPIO pin to logic 1. - * - * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.) - * @param pin FGPIO port pin number - */ -static inline void FGPIO_HAL_SetPinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - HW_FGPIO_PSOR_WR(baseAddr, 1U << pin); -} - -/*! - * @brief Clears the output level of an individual FGPIO pin to logic 0. - * - * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.) - * @param pin FGPIO port pin number - */ -static inline void FGPIO_HAL_ClearPinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - HW_FGPIO_PCOR_WR(baseAddr, 1U << pin); -} - -/*! - * @brief Reverses the current output logic of an individual FGPIO pin. - * - * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.) - * @param pin FGPIO port pin number - */ -static inline void FGPIO_HAL_TogglePinOutput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - HW_FGPIO_PTOR_WR(baseAddr, 1U << pin); -} - -/*! - * @brief Sets the output of the FGPIO port to a specific logic value. - * - * This function affects all 32 port pins. - * - * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.) - * @param portOutput data to configure the GPIO output. Each bit represents one pin. For each bit: - * - 0: set logic level 0 to pin. - * - 1: set logic level 1 to pin. - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline void FGPIO_HAL_WritePortOutput(uint32_t baseAddr, uint32_t portOutput) -{ - HW_FGPIO_PDOR_WR(baseAddr, portOutput); -} - -/* @} */ - -/*! - * @name Input Operation - * @{ - */ - -/*! - * @brief Gets the current input value of an individual FGPIO pin. - * - * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.) - * @param pin FGPIO port pin number - * @return FGPIO port input data - * - 0: Pin logic level is 0, or is not configured for use by digital function. - * - 1: Pin logic level is 1. - */ -static inline uint32_t FGPIO_HAL_ReadPinInput(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32); - return (HW_FGPIO_PDIR_RD(baseAddr) >> pin) & 1U; -} - -/*! - * @brief Gets the current input value of a specific FGPIO port. - * - * This function gets all 32-pin input as a 32-bit integer. - * - * @param baseAddr GPIO base address(HW_FPTA, HW_FPTB, HW_FPTC, etc.). - * @return FGPIO port input data. Each bit represents one pin. For each bit: - * - 0: Pin logic level is 0, or is not configured for use by digital function. - * - 1: Pin logic level is 1. - * - LSB: pin 0 - * - MSB: pin 31 - */ -static inline uint32_t FGPIO_HAL_ReadPortInput(uint32_t baseAddr) -{ - return HW_FGPIO_PDIR_RD(baseAddr); -} - -/* @} */ - -#endif /* FSL_FEATURE_GPIO_HAS_FAST_GPIO*/ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* __FSL_GPIO_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h deleted file mode 100644 index d897349c128..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h +++ /dev/null @@ -1,283 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_I2C_FEATURES_H__) -#define __FSL_I2C_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \ - defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \ - defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ - defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (1) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ - defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (0) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -#elif defined(CPU_MK24FN256VDC12) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (1) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (0) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (1) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (0) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (0) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (1) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) -#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (0) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) - /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ - #define FSL_FEATURE_I2C_HAS_SMBUS (1) - /* @brief Maximum supported baud rate in kilobit per second. */ - #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) - /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ - #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) - /* @brief Has DMA support (register bit C1[DMAEN]). */ - #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) - /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */ - #define FSL_FEATURE_I2C_HAS_START_DETECT (0) - /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */ - #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1) - /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ - #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) - /* @brief Maximum width of the glitch filter in number of bus clocks. */ - #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) - /* @brief Has control of the drive capability of the I2C pins. */ - #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) - /* @brief Has double buffering support (register S2). */ - #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_I2C_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c deleted file mode 100644 index 238cd1679a9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_hal.h" -#include "fsl_misc_utilities.h" /* For ARRAY_SIZE*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief An entry in the I2C divider table. - * - * This struct pairs the value of the I2C_F.ICR bitfield with the resulting - * clock divider value. - */ -typedef struct I2CDividerTableEntry { - uint8_t icr; /*!< F register ICR value.*/ - uint16_t sclDivider; /*!< SCL clock divider.*/ -} i2c_divider_table_entry_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! - * @brief I2C divider values. - * - * This table is taken from the I2C Divider and Hold values section of the - * reference manual. In the original table there are, in some cases, multiple - * entries with the same divider but different hold values. This table - * includes only one entry for every divider, selecting the lowest hold value. - */ -const i2c_divider_table_entry_t kI2CDividerTable[] = { - /* ICR Divider*/ - { 0x00, 20 }, - { 0x01, 22 }, - { 0x02, 24 }, - { 0x03, 26 }, - { 0x04, 28 }, - { 0x05, 30 }, - { 0x09, 32 }, - { 0x06, 34 }, - { 0x0a, 36 }, - { 0x07, 40 }, - { 0x0c, 44 }, - { 0x0d, 48 }, - { 0x0e, 56 }, - { 0x12, 64 }, - { 0x0f, 68 }, - { 0x13, 72 }, - { 0x14, 80 }, - { 0x15, 88 }, - { 0x19, 96 }, - { 0x16, 104 }, - { 0x1a, 112 }, - { 0x17, 128 }, - { 0x1c, 144 }, - { 0x1d, 160 }, - { 0x1e, 192 }, - { 0x22, 224 }, - { 0x1f, 240 }, - { 0x23, 256 }, - { 0x24, 288 }, - { 0x25, 320 }, - { 0x26, 384 }, - { 0x2a, 448 }, - { 0x27, 480 }, - { 0x2b, 512 }, - { 0x2c, 576 }, - { 0x2d, 640 }, - { 0x2e, 768 }, - { 0x32, 896 }, - { 0x2f, 960 }, - { 0x33, 1024 }, - { 0x34, 1152 }, - { 0x35, 1280 }, - { 0x36, 1536 }, - { 0x3a, 1792 }, - { 0x37, 1920 }, - { 0x3b, 2048 }, - { 0x3c, 2304 }, - { 0x3d, 2560 }, - { 0x3e, 3072 }, - { 0x3f, 3840 } - }; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : I2C_HAL_Init - * Description : Initialize I2C peripheral to reset state. - * - *END**************************************************************************/ -void I2C_HAL_Init(uint32_t baseAddr) -{ - - HW_I2C_A1_WR(baseAddr, 0u); - HW_I2C_F_WR(baseAddr, 0u); - HW_I2C_C1_WR(baseAddr, 0u); - HW_I2C_S_WR(baseAddr, 0u); - HW_I2C_D_WR(baseAddr, 0u); - HW_I2C_C2_WR(baseAddr, 0u); - HW_I2C_FLT_WR(baseAddr, 0u); - HW_I2C_RA_WR(baseAddr, 0u); - -#if FSL_FEATURE_I2C_HAS_SMBUS - HW_I2C_SMB_WR(baseAddr, 0u); - HW_I2C_A2_WR(baseAddr, 0xc2u); - HW_I2C_SLTH_WR(baseAddr, 0u); - HW_I2C_SLTL_WR(baseAddr, 0u); -#endif /* FSL_FEATURE_I2C_HAS_SMBUS*/ -} - -/*FUNCTION********************************************************************** - * - * Function Name : I2C_HAL_SetBaudRate - * Description : Sets the I2C bus frequency for master transactions. - * - *END**************************************************************************/ -i2c_status_t I2C_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t kbps, - uint32_t * absoluteError_Hz) -{ - uint32_t mult, i, multiplier; - uint32_t hz = kbps * 1000u; - uint32_t bestError = 0xffffffffu; - uint32_t bestMult = 0u; - uint32_t bestIcr = 0u; - - /* Check if the requested frequency is greater than the max supported baud.*/ - if ((kbps * 1000U) > (sourceClockInHz / (1U * 20U))) - { - return kStatus_I2C_OutOfRange; - } - - /* Search for the settings with the lowest error. - * mult is the MULT field of the I2C_F register, and ranges from 0-2. It selects the - * multiplier factor for the divider. */ - for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) - { - multiplier = 1u << mult; - - /* Scan table to find best match.*/ - for (i = 0u; i < ARRAY_SIZE(kI2CDividerTable); ++i) - { - uint32_t computedRate = sourceClockInHz / (multiplier * kI2CDividerTable[i].sclDivider); - uint32_t absError = hz > computedRate ? hz - computedRate : computedRate - hz; - - if (absError < bestError) - { - bestMult = mult; - bestIcr = kI2CDividerTable[i].icr; - bestError = absError; - - /* If the error is 0, then we can stop searching - * because we won't find a better match.*/ - if (absError == 0) - { - break; - } - } - } - } - - /* Set the resulting error.*/ - if (absoluteError_Hz) - { - *absoluteError_Hz = bestError; - } - - /* Set frequency register based on best settings.*/ - HW_I2C_F_WR(baseAddr, BF_I2C_F_MULT(bestMult) | BF_I2C_F_ICR(bestIcr)); - - return kStatus_I2C_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : I2C_HAL_SendStart - * Description : Send a START or Repeated START signal on the I2C bus. - * This function is used to initiate a new master mode transfer by sending the - * START signal. It is also used to send a Repeated START signal when a transfer - * is already in progress. - * - *END**************************************************************************/ -void I2C_HAL_SendStart(uint32_t baseAddr) -{ - /* Check if we're in a master mode transfer.*/ - if (BR_I2C_C1_MST(baseAddr)) - { -#if FSL_FEATURE_I2C_HAS_ERRATA_6070 - /* Errata 6070: Repeat start cannot be generated if the I2Cx_F[MULT] field is set to a - * non- zero value. - * The workaround is to either always keep MULT set to 0, or to temporarily set it to - * 0 while performing the repeated start and then restore it.*/ - uint32_t savedMult = 0; - if (BR_I2C_F_MULT(baseAddr) != 0) - { - savedMult = BR_I2C_F_MULT(baseAddr); - BW_I2C_F_MULT(baseAddr, 0U); - } -#endif /* FSL_FEATURE_I2C_HAS_ERRATA_6070*/ - - /* We are already in a transfer, so send a repeated start.*/ - BW_I2C_C1_RSTA(baseAddr, 1U); - -#if FSL_FEATURE_I2C_HAS_ERRATA_6070 - if (savedMult) - { - BW_I2C_F_MULT(baseAddr, savedMult); - } -#endif /* FSL_FEATURE_I2C_HAS_ERRATA_6070*/ - } - else - { - /* Initiate a transfer by sending the start signal.*/ - HW_I2C_C1_SET(baseAddr, BM_I2C_C1_MST | BM_I2C_C1_TX); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : I2C_HAL_SetAddress7bit - * Description : Sets the primary 7-bit slave address. - * - *END**************************************************************************/ -void I2C_HAL_SetAddress7bit(uint32_t baseAddr, uint8_t address) -{ - /* Set 7-bit slave address.*/ - HW_I2C_A1_WR(baseAddr, address << 1U); - - /* Disable the address extension option, selecting 7-bit mode.*/ - BW_I2C_C2_ADEXT(baseAddr, 0U); -} - -/*FUNCTION********************************************************************** - * - * Function Name : I2C_HAL_SetAddress10bit - * Description : Sets the primary slave address and enables 10-bit address mode. - * - *END**************************************************************************/ -void I2C_HAL_SetAddress10bit(uint32_t baseAddr, uint16_t address) -{ - - uint8_t temp; - - /* Set bottom 7 bits of slave address.*/ - temp = address & 0x7FU; - HW_I2C_A1_WR(baseAddr, temp << 1U); - - /* Enable 10-bit address extension.*/ - BW_I2C_C2_ADEXT(baseAddr, 1U); - - /* Set top 3 bits of slave address.*/ - BW_I2C_C2_AD(baseAddr, (address & 0x0380U) >> 7U); -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h deleted file mode 100644 index c233aec1315..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h +++ /dev/null @@ -1,702 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_I2C_HAL_H__) -#define __FSL_I2C_HAL_H__ - -#include -#include -#include "fsl_i2c_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup i2c_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief I2C status return codes.*/ -typedef enum _i2c_status { - kStatus_I2C_Success = 0x0U, - kStatus_I2C_OutOfRange = 0x1U, - kStatus_I2C_Fail = 0x2U, - kStatus_I2C_Busy = 0x3U, /*!< The master is already performing a transfer.*/ - kStatus_I2C_Timeout = 0x4U, /*!< The transfer timed out.*/ - kStatus_I2C_ReceivedNak = 0x5U, /*!< The slave device sent a NAK in response to a byte.*/ - kStatus_I2C_SlaveTxUnderrun = 0x6U, /*!< I2C Slave TX Underrun error.*/ - kStatus_I2C_SlaveRxOverrun = 0x7U, /*!< I2C Slave RX Overrun error.*/ - kStatus_I2C_AribtrationLost = 0x8U, /*!< I2C Arbitration Lost error.*/ -} i2c_status_t; - -/*! @brief I2C status flags. */ -typedef enum _i2c_status_flag { - kI2CTransferComplete = BP_I2C_S_TCF, - kI2CAddressAsSlave = BP_I2C_S_IAAS, - kI2CBusBusy = BP_I2C_S_BUSY, - kI2CArbitrationLost = BP_I2C_S_ARBL, - kI2CAddressMatch = BP_I2C_S_RAM, - kI2CSlaveTransmit = BP_I2C_S_SRW, - kI2CInterruptPending = BP_I2C_S_IICIF, - kI2CReceivedNak = BP_I2C_S_RXAK -} i2c_status_flag_t; - -/*! @brief Direction of master and slave transfers.*/ -typedef enum _i2c_direction { - kI2CReceive = 0U, /*!< Master and slave receive.*/ - kI2CSend = 1U /*!< Master and slave transmit.*/ -} i2c_direction_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Module controls - * @{ - */ - -/*! - * @brief Restores the I2C peripheral to reset state. - * - * @param baseAddr The I2C peripheral base address - */ -void I2C_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Enables the I2C module operation. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_Enable(uint32_t baseAddr) -{ - BW_I2C_C1_IICEN(baseAddr, 0x1U); -} - -/*! - * @brief Disables the I2C module operation. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_Disable(uint32_t baseAddr) -{ - BW_I2C_C1_IICEN(baseAddr, 0x0U); -} - -/*@}*/ - -/*! - * @name DMA - * @{ - */ - -/*! - * @brief Enables or disables the DMA support. - * - * @param baseAddr The I2C peripheral base address - * @param enable Pass true to enable DMA transfer signalling - */ -static inline void I2C_HAL_SetDmaCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C1_DMAEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Returns whether I2C DMA support is enabled. - * - * @param baseAddr The I2C peripheral base address. - * @retval true I2C DMA is enabled. - * @retval false I2C DMA is disabled. - */ -static inline bool I2C_HAL_GetDmaCmd(uint32_t baseAddr) -{ - return BR_I2C_C1_DMAEN(baseAddr); -} - -/*@}*/ - -/*! - * @name Pin functions - * @{ - */ - -/*! - * @brief Controls the drive capability of the I2C pads. - * - * @param baseAddr The I2C peripheral base address - * @param enable Passing true will enable high drive mode of the I2C pads. False sets normal - * drive mode. - */ -static inline void I2C_HAL_SetHighDriveCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C2_HDRS(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Controls the width of the programmable glitch filter. - * - * Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. - * The filter does not allow any glitch whose size is less than or equal to this width setting, - * to pass. - * - * @param baseAddr The I2C peripheral base address - * @param glitchWidth Maximum width in bus clock cycles of the glitches that is filtered. - * Pass zero to disable the glitch filter. - */ -static inline void I2C_HAL_SetGlitchWidth(uint32_t baseAddr, uint8_t glitchWidth) -{ - BW_I2C_FLT_FLT(baseAddr, glitchWidth); -} - -/*@}*/ - -/*! - * @name Low power - * @{ - */ - -/*! - * @brief Controls the I2C wakeup enable. - * - * The I2C module can wake the MCU from low power mode with no peripheral bus running when - * slave address matching occurs. - * - * @param baseAddr The I2C peripheral base address. - * @param enable true - Enables the wakeup function in low power mode.
- * false - Normal operation. No interrupt is generated when address matching in - * low power mode. - */ -static inline void I2C_HAL_SetWakeupCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C1_WUEN(baseAddr, (uint8_t)enable); -} - -#if FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF -/*! - * @brief Controls the stop mode hold off. - * - * This function lets you enable the hold off entry to low power stop mode when any data transmission - * or reception is occurring. - * - * @param baseAddr The I2C peripheral base address - * @param enable false - Stop hold off is disabled. The MCU's entry to stop mode is not gated.
- * true - Stop hold off is enabled. - */ - -static inline void I2C_HAL_SetStopHoldoffCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_FLT_SHEN(baseAddr, (uint8_t)enable); -} -#endif /* FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF*/ - -/*@}*/ - -/*! - * @name Baud rate - * @{ - */ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * @param baseAddr The I2C peripheral base address - * @param sourceClockInHz I2C source input clock in Hertz - * @param kbps Requested bus frequency in kilohertz. Common values are either 100 or 400. - * @param absoluteError_Hz If this parameter is not NULL, it is filled in with the - * difference in Hertz between the requested bus frequency and the closest frequency - * possible given available divider values. - * - * @retval kStatus_Success The baud rate was changed successfully. However, there is no - * guarantee on the minimum error. If you want to ensure that the baud was set to within - * a certain error, then use the @a absoluteError_Hz parameter. - * @retval kStatus_OutOfRange The requested baud rate was not within the range of rates - * supported by the peripheral. - */ -i2c_status_t I2C_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t kbps, - uint32_t * absoluteError_Hz); - -/*! - * @brief Sets the I2C baud rate multiplier and table entry. - * - * Use this function to set the I2C bus frequency register values directly, if they are - * known in advance. - * - * @param baseAddr The I2C peripheral base address - * @param mult Value of the MULT bitfield, ranging from 0-2. - * @param icr The ICR bitfield value, which is the index into an internal table in the I2C - * hardware that selects the baud rate divisor and SCL hold time. - */ -static inline void I2C_HAL_SetFreqDiv(uint32_t baseAddr, uint8_t mult, uint8_t icr) -{ - HW_I2C_F_WR(baseAddr, BF_I2C_F_MULT(mult) | BF_I2C_F_ICR(icr)); -} - -/*! - * @brief Slave baud rate control - * - * Enables an independent slave mode baud rate at the maximum frequency. This forces clock stretching - * on the SCL in very fast I2C modes. - * - * @param baseAddr The I2C peripheral base address - * @param enable true - Slave baud rate is independent of the master baud rate;
- * false - The slave baud rate follows the master baud rate and clock stretching may occur. - */ -static inline void I2C_HAL_SetSlaveBaudCtrlCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C2_SBRC(baseAddr, (uint8_t)enable); -} - -/*@}*/ - -/*! - * @name Bus operations - * @{ - */ - -/*! - * @brief Sends a START or a Repeated START signal on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. It - * is also used to send a Repeated START signal when a transfer is already in progress. - * - * @param baseAddr The I2C peripheral base address - */ -void I2C_HAL_SendStart(uint32_t baseAddr); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * This function changes the direction to receive. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_SendStop(uint32_t baseAddr) -{ - assert(BR_I2C_C1_MST(baseAddr) == 1); - HW_I2C_C1_CLR(baseAddr, BM_I2C_C1_MST | BM_I2C_C1_TX); -} - -/*! - * @brief Causes an ACK to be sent on the bus. - * - * This function specifies that an ACK signal is sent in response to the next received byte. - * - * Note that the behavior of this function is changed when the I2C peripheral is placed in - * Fast ACK mode. In this case, this function causes an ACK signal to be sent in - * response to the current byte, rather than the next received byte. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_SendAck(uint32_t baseAddr) -{ - BW_I2C_C1_TXAK(baseAddr, 0x0U); -} - -/*! - * @brief Causes a NAK to be sent on the bus. - * - * This function specifies that a NAK signal is sent in response to the next received byte. - * - * Note that the behavior of this function is changed when the I2C peripheral is placed in the - * Fast ACK mode. In this case, this function causes an NAK signal to be sent in - * response to the current byte, rather than the next received byte. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_SendNak(uint32_t baseAddr) -{ - BW_I2C_C1_TXAK(baseAddr, 0x1U); -} - -/*! - * @brief Selects either transmit or receive mode. - * - * @param baseAddr The I2C peripheral base address. - * @param direction Specifies either transmit mode or receive mode. The valid values are: - * - #kI2CTransmit - * - #kI2CReceive - */ -static inline void I2C_HAL_SetDirMode(uint32_t baseAddr, i2c_direction_t direction) -{ - BW_I2C_C1_TX(baseAddr, (uint8_t)direction); -} - -/*! - * @brief Returns the currently selected transmit or receive mode. - * - * @param baseAddr The I2C peripheral base address. - * @retval #kI2CTransmit I2C is configured for master or slave transmit mode. - * @retval #kI2CReceive I2C is configured for master or slave receive mode. - */ -static inline i2c_direction_t I2C_HAL_GetDirMode(uint32_t baseAddr) -{ - return (i2c_direction_t)BR_I2C_C1_TX(baseAddr); -} - -/*@}*/ - -/*! - * @name Data transfer - * @{ - */ - -/*! - * @brief Returns the last byte of data read from the bus and initiate another read. - * - * In a master receive mode, calling this function initiates receiving the next byte of data. - * - * @param baseAddr The I2C peripheral base address - * @return This function returns the last byte received while the I2C module is configured in master - * receive or slave receive mode. - */ -static inline uint8_t I2C_HAL_ReadByte(uint32_t baseAddr) -{ - return HW_I2C_D_RD(baseAddr); -} - -/*! - * @brief Writes one byte of data to the I2C bus. - * - * When this function is called in the master transmit mode, a data transfer is initiated. In slave - * mode, the same function is available after an address match occurs. - * - * In a master transmit mode, the first byte of data written following the start bit or repeated - * start bit is used for the address transfer and must consist of the slave address (in bits 7-1) - * concatenated with the required R/\#W bit (in position bit 0). - * - * @param baseAddr The I2C peripheral base address. - * @param byte The byte of data to transmit. - */ -static inline void I2C_HAL_WriteByte(uint32_t baseAddr, uint8_t byte) -{ - HW_I2C_D_WR(baseAddr, byte); -} - -/*@}*/ - -/*! - * @name Slave address - * @{ - */ - -/*! - * @brief Sets the primary 7-bit slave address. - * - * @param baseAddr The I2C peripheral base address - * @param address The slave address in the upper 7 bits. Bit 0 of this value must be 0. - */ -void I2C_HAL_SetAddress7bit(uint32_t baseAddr, uint8_t address); - -/*! - * @brief Sets the primary slave address and enables 10-bit address mode. - * - * @param baseAddr The I2C peripheral base address - * @param address The 10-bit slave address, in bits [10:1] of the value. Bit 0 must be 0. - */ -void I2C_HAL_SetAddress10bit(uint32_t baseAddr, uint16_t address); - -/*! - * @brief Enables or disables the extension address (10-bit). - * - * @param baseAddr The I2C peripheral base address - * @param enable true: 10-bit address is enabled. - * false: 10-bit address is not enabled. - */ -static inline void I2C_HAL_SetExtensionAddrCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C2_ADEXT(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Returns whether the extension address is enabled or not. - * - * @param baseAddr The I2C peripheral base address - * @return true: 10-bit address is enabled. - * false: 10-bit address is not enabled. - */ -static inline bool I2C_HAL_GetExtensionAddrCmd(uint32_t baseAddr) -{ - return BR_I2C_C2_ADEXT(baseAddr); -} - -/*! - * @brief Controls whether the general call address is recognized. - * - * @param baseAddr The I2C peripheral base address - * @param enable Whether to enable the general call address. - */ -static inline void I2C_HAL_SetGeneralCallCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C2_GCAEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Enables or disables the slave address range matching. - * - * @param baseAddr The I2C peripheral base address. - * @param enable Pass true to enable range address matching. You must also call - * I2C_HAL_SetUpperAddress7bit() to set the upper address. - */ -static inline void I2C_HAL_SetRangeMatchCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C2_RMEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Sets the upper slave address. - * - * This slave address is used as a secondary slave address. If range address - * matching is enabled, this slave address acts as the upper bound on the slave address - * range. - * - * This function sets only a 7-bit slave address. If 10-bit addressing was enabled by calling - * I2C_HAL_SetAddress10bit(), then the top 3 bits set with that function are also used - * with the address set with this function to form a 10-bit address. - * - * Passing 0 for the @a address parameter disables matching the upper slave address. - * - * @param baseAddr The I2C peripheral base address - * @param address The upper slave address in the upper 7 bits. Bit 0 of this value must be 0. - * In addition, this address must be greater than the primary slave address that is set by - * calling I2C_HAL_SetAddress7bit(). - */ -static inline void I2C_HAL_SetUpperAddress7bit(uint32_t baseAddr, uint8_t address) -{ - assert((address & 1) == 0); - assert((address == 0) || (address > HW_I2C_A1_RD(baseAddr))); - HW_I2C_RA_WR(baseAddr, address); -} - -/*@}*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the I2C status flag state. - * - * @param baseAddr The I2C peripheral base address. - * @param statusFlag The status flag, defined in type i2c_status_flag_t. - * @return State of the status flag: asserted (true) or not-asserted (false). - * - true: related status flag is being set. - * - false: related status flag is not set. - */ -static inline bool I2C_HAL_GetStatusFlag(uint32_t baseAddr, i2c_status_flag_t statusFlag) -{ - return (bool)((HW_I2C_S_RD(baseAddr) >> statusFlag) & 0x1U); -} - -/*! - * @brief Returns whether the I2C module is in master mode. - * - * @param baseAddr The I2C peripheral base address. - * @retval true The module is in master mode, which implies it is also performing a transfer. - * @retval false The module is in slave mode. - */ -static inline bool I2C_HAL_IsMaster(uint32_t baseAddr) -{ - return (bool)BR_I2C_C1_MST(baseAddr); -} - -/*! - * @brief Clears the arbitration lost flag. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_ClearArbitrationLost(uint32_t baseAddr) -{ - BW_I2C_S_ARBL(baseAddr, 0x1U); -} - -/*@}*/ - -/*! - * @name Interrupt - * @{ - */ - -/*! - * @brief Enables or disables I2C interrupt requests. - * - * @param baseAddr The I2C peripheral base address - * @param enable Pass true to enable interrupt, flase to disable. - */ -static inline void I2C_HAL_SetIntCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_C1_IICIE(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Returns whether the I2C interrupts are enabled. - * - * @param baseAddr The I2C peripheral base address - * @retval true I2C interrupts are enabled. - * @retval false I2C interrupts are disabled. - */ -static inline bool I2C_HAL_GetIntCmd(uint32_t baseAddr) -{ - return (bool)BR_I2C_C1_IICIE(baseAddr); -} - -/*! - * @brief Returns the current I2C interrupt flag. - * - * @param baseAddr The I2C peripheral base address - * @retval true An interrupt is pending. - * @retval false No interrupt is pending. - */ -static inline bool I2C_HAL_IsIntPending(uint32_t baseAddr) -{ - return (bool)BR_I2C_S_IICIF(baseAddr); -} - -/*! - * @brief Clears the I2C interrupt if set. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_ClearInt(uint32_t baseAddr) -{ - BW_I2C_S_IICIF(baseAddr, 0x1U); -} - -/*@}*/ - -#if FSL_FEATURE_I2C_HAS_STOP_DETECT - -/*! - * @name Bus stop detection status - * @{ - */ - -/*! - * @brief Gets the flag indicating a STOP signal was detected on the I2C bus. - * - * @param baseAddr The I2C peripheral base address - * @retval true STOP signal detected on bus. - * @retval false No STOP signal was detected on the bus. - */ -static inline bool I2C_HAL_GetStopFlag(uint32_t baseAddr) -{ - return (bool)BR_I2C_FLT_STOPF(baseAddr); -} - -/*! - * @brief Clears the bus STOP signal detected flag. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_ClearStopFlag(uint32_t baseAddr) -{ - BW_I2C_FLT_STOPF(baseAddr, 0x1U); -} - -/*@}*/ - -#if FSL_FEATURE_I2C_HAS_START_DETECT - -/*! - * @name Bus stop detection interrupt - * @{ - */ - -/*! - * @brief Enables the I2C bus stop detection interrupt. - * - * @param baseAddr The I2C peripheral base address - * @param enable Pass true to enable interrupt, flase to disable. - */ -static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_FLT_SSIE(baseAddr, enable); -} - -/*! - * @brief Returns whether the I2C bus stop detection interrupts are enabled. - * - * @param baseAddr The I2C peripheral base address - * @retval true Stop detect interrupts are enabled. - * @retval false Stop detect interrupts are disabled. - */ -static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr) -{ - return (bool)BR_I2C_FLT_SSIE(baseAddr); -} - -#else - -/*! @name Bus stop detection interrupt*/ -/*@{*/ - -/*! - * @brief Enables the I2C bus stop detection interrupt. - * - * @param baseAddr The I2C peripheral base address - */ -static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable) -{ - BW_I2C_FLT_STOPIE(baseAddr, enable); -} - -/*! - * @brief Returns whether the I2C bus stop detection interrupts are enabled. - * - * @param baseAddr The I2C peripheral base address - * @retval true Stop detect interrupts are enabled. - * @retval false Stop detect interrupts are disabled. - */ -static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr) -{ - return (bool)BR_I2C_FLT_STOPIE(baseAddr); -} - -#endif /* FSL_FEATURE_I2C_HAS_START_DETECT*/ - -/*@}*/ -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT*/ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* __FSL_I2C_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_features.h deleted file mode 100644 index a92b5a38eda..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_features.h +++ /dev/null @@ -1,153 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_LLWU_FEATURES_H__) -#define __FSL_LLWU_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ - defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) - /* @brief Maximum number of pins connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ - defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ - defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ - defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || \ - defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Maximum number of pins connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \ - defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ - defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ - defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ - defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ - defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Maximum number of pins connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Maximum number of pins connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (8) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (0) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (1) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) - /* @brief Maximum number of pins connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (8) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Maximum number of pins connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_LLWU_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c deleted file mode 100644 index 31d611c1f79..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_llwu_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_SetExternalInputPinMode - * Description : Set external input pin source mode - * This function will set the external input pin source mode that will be used - * as wake up source. - * - *END**************************************************************************/ -void LLWU_HAL_SetExternalInputPinMode(uint32_t baseAddr, - llwu_external_pin_modes_t pinMode, - uint32_t pinNumber) -{ - /* check pin number */ - assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN); - - switch (pinNumber) - { - case 0: - BW_LLWU_PE1_WUPE0(baseAddr, pinMode); - break; - case 1: - BW_LLWU_PE1_WUPE1(baseAddr, pinMode); - break; - case 2: - BW_LLWU_PE1_WUPE2(baseAddr, pinMode); - break; - case 3: - BW_LLWU_PE1_WUPE3(baseAddr, pinMode); - break; - case 4: - BW_LLWU_PE2_WUPE4(baseAddr, pinMode); - break; - case 5: - BW_LLWU_PE2_WUPE5(baseAddr, pinMode); - break; - case 6: - BW_LLWU_PE2_WUPE6(baseAddr, pinMode); - break; - case 7: - BW_LLWU_PE2_WUPE7(baseAddr, pinMode); - break; - case 8: - BW_LLWU_PE3_WUPE8(baseAddr, pinMode); - break; - case 9: - BW_LLWU_PE3_WUPE9(baseAddr, pinMode); - break; - case 10: - BW_LLWU_PE3_WUPE10(baseAddr, pinMode); - break; - case 11: - BW_LLWU_PE3_WUPE11(baseAddr, pinMode); - break; - case 12: - BW_LLWU_PE4_WUPE12(baseAddr, pinMode); - break; - case 13: - BW_LLWU_PE4_WUPE13(baseAddr, pinMode); - break; - case 14: - BW_LLWU_PE4_WUPE14(baseAddr, pinMode); - break; - case 15: - BW_LLWU_PE4_WUPE15(baseAddr, pinMode); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetExternalInputPinMode - * Description : Get external input pin source mode - * This function will get the external input pin source mode that will be used - * as wake up source. - * - *END**************************************************************************/ -llwu_external_pin_modes_t LLWU_HAL_GetExternalInputPinMode(uint32_t baseAddr, - uint32_t pinNumber) -{ - llwu_external_pin_modes_t retValue = (llwu_external_pin_modes_t)0; - - /* check pin number */ - assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN); - - switch (pinNumber) - { - case 0: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE0(baseAddr); - break; - case 1: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE1(baseAddr); - break; - case 2: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE2(baseAddr); - break; - case 3: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE1_WUPE3(baseAddr); - break; - case 4: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE4(baseAddr); - break; - case 5: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE5(baseAddr); - break; - case 6: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE6(baseAddr); - break; - case 7: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE2_WUPE7(baseAddr); - break; - case 8: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE8(baseAddr); - break; - case 9: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE9(baseAddr); - break; - case 10: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE10(baseAddr); - break; - case 11: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE3_WUPE11(baseAddr); - break; - case 12: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE12(baseAddr); - break; - case 13: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE13(baseAddr); - break; - case 14: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE14(baseAddr); - break; - case 15: - retValue = (llwu_external_pin_modes_t)BR_LLWU_PE4_WUPE15(baseAddr); - break; - default: - retValue = (llwu_external_pin_modes_t)0; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_SetInternalModuleCmd - * Description : Enable/disable internal module source - * This function will enable/disable the internal module source mode that will - * be used as wake up source. - * - *END**************************************************************************/ -void LLWU_HAL_SetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber, bool enable) -{ - /* check module number */ - assert(moduleNumber < FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE); - - switch (moduleNumber) - { - case 0: - BW_LLWU_ME_WUME0(baseAddr, enable); - break; - case 1: - BW_LLWU_ME_WUME1(baseAddr, enable); - break; - case 2: - BW_LLWU_ME_WUME2(baseAddr, enable); - break; - case 3: - BW_LLWU_ME_WUME3(baseAddr, enable); - break; - case 4: - BW_LLWU_ME_WUME4(baseAddr, enable); - break; - case 5: - BW_LLWU_ME_WUME5(baseAddr, enable); - break; - case 6: - BW_LLWU_ME_WUME6(baseAddr, enable); - break; - case 7: - BW_LLWU_ME_WUME7(baseAddr, enable); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetInternalModuleCmd - * Description : Get internal module source enable setting - * This function will enable/disable the internal module source mode that will - * be used as wake up source. - * - *END**************************************************************************/ -bool LLWU_HAL_GetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber) -{ - bool retValue = false; - - /* check module number */ - assert(moduleNumber < FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE); - - switch (moduleNumber) - { - case 0: - retValue = (bool)BR_LLWU_ME_WUME0(baseAddr); - break; - case 1: - retValue = (bool)BR_LLWU_ME_WUME1(baseAddr); - break; - case 2: - retValue = (bool)BR_LLWU_ME_WUME2(baseAddr); - break; - case 3: - retValue = (bool)BR_LLWU_ME_WUME3(baseAddr); - break; - case 4: - retValue = (bool)BR_LLWU_ME_WUME4(baseAddr); - break; - case 5: - retValue = (bool)BR_LLWU_ME_WUME5(baseAddr); - break; - case 6: - retValue = (bool)BR_LLWU_ME_WUME6(baseAddr); - break; - case 7: - retValue = (bool)BR_LLWU_ME_WUME7(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetExternalPinWakeupFlag - * Description : Get external wakeup source flag - * This function will get the external wakeup source flag for specific pin. - * - *END**************************************************************************/ -bool LLWU_HAL_GetExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber) -{ - bool retValue = false; - - /* check pin number */ - assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN); - - switch (pinNumber) - { - case 0: - retValue = (bool)BR_LLWU_F1_WUF0(baseAddr); - break; - case 1: - retValue = (bool)BR_LLWU_F1_WUF1(baseAddr); - break; - case 2: - retValue = (bool)BR_LLWU_F1_WUF2(baseAddr); - break; - case 3: - retValue = (bool)BR_LLWU_F1_WUF3(baseAddr); - break; - case 4: - retValue = (bool)BR_LLWU_F1_WUF4(baseAddr); - break; - case 5: - retValue = (bool)BR_LLWU_F1_WUF5(baseAddr); - break; - case 6: - retValue = (bool)BR_LLWU_F1_WUF6(baseAddr); - break; - case 7: - retValue = (bool)BR_LLWU_F1_WUF7(baseAddr); - break; - case 8: - retValue = (bool)BR_LLWU_F2_WUF8(baseAddr); - break; - case 9: - retValue = (bool)BR_LLWU_F2_WUF9(baseAddr); - break; - case 10: - retValue = (bool)BR_LLWU_F2_WUF10(baseAddr); - break; - case 11: - retValue = (bool)BR_LLWU_F2_WUF11(baseAddr); - break; - case 12: - retValue = (bool)BR_LLWU_F2_WUF12(baseAddr); - break; - case 13: - retValue = (bool)BR_LLWU_F2_WUF13(baseAddr); - break; - case 14: - retValue = (bool)BR_LLWU_F2_WUF14(baseAddr); - break; - case 15: - retValue = (bool)BR_LLWU_F2_WUF15(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_ClearExternalPinWakeupFlag - * Description : Clear external wakeup source flag - * This function will clear the external wakeup source flag for specific pin. - * - *END**************************************************************************/ -void LLWU_HAL_ClearExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber) -{ - /* check pin number */ - assert(pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN); - - switch (pinNumber) - { - case 0: - BW_LLWU_F1_WUF0(baseAddr, 1); - break; - case 1: - BW_LLWU_F1_WUF1(baseAddr, 1); - break; - case 2: - BW_LLWU_F1_WUF2(baseAddr, 1); - break; - case 3: - BW_LLWU_F1_WUF3(baseAddr, 1); - break; - case 4: - BW_LLWU_F1_WUF4(baseAddr, 1); - break; - case 5: - BW_LLWU_F1_WUF5(baseAddr, 1); - break; - case 6: - BW_LLWU_F1_WUF6(baseAddr, 1); - break; - case 7: - BW_LLWU_F1_WUF7(baseAddr, 1); - break; - case 8: - BW_LLWU_F2_WUF8(baseAddr, 1); - break; - case 9: - BW_LLWU_F2_WUF9(baseAddr, 1); - break; - case 10: - BW_LLWU_F2_WUF10(baseAddr, 1); - break; - case 11: - BW_LLWU_F2_WUF11(baseAddr, 1); - break; - case 12: - BW_LLWU_F2_WUF12(baseAddr, 1); - break; - case 13: - BW_LLWU_F2_WUF13(baseAddr, 1); - break; - case 14: - BW_LLWU_F2_WUF14(baseAddr, 1); - break; - case 15: - BW_LLWU_F2_WUF15(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetInternalModuleWakeupFlag - * Description : Get internal module wakeup source flag - * This function will get the internal module wakeup source flag for specific - * module - * - *END**************************************************************************/ -bool LLWU_HAL_GetInternalModuleWakeupFlag(uint32_t baseAddr, uint32_t moduleNumber) -{ - bool retValue = false; - - /* check module number */ - assert(moduleNumber < FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE); - - switch (moduleNumber) - { - case 0: - retValue = (bool)BR_LLWU_F3_MWUF0(baseAddr); - break; - case 1: - retValue = (bool)BR_LLWU_F3_MWUF1(baseAddr); - break; - case 2: - retValue = (bool)BR_LLWU_F3_MWUF2(baseAddr); - break; - case 3: - retValue = (bool)BR_LLWU_F3_MWUF3(baseAddr); - break; - case 4: - retValue = (bool)BR_LLWU_F3_MWUF4(baseAddr); - break; - case 5: - retValue = (bool)BR_LLWU_F3_MWUF5(baseAddr); - break; - case 6: - retValue = (bool)BR_LLWU_F3_MWUF6(baseAddr); - break; - case 7: - retValue = (bool)BR_LLWU_F3_MWUF7(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_SetPinFilterMode - * Description : Set pin filter configuration - * This function will set the pin filter configuration. - * - *END**************************************************************************/ -void LLWU_HAL_SetPinFilterMode(uint32_t baseAddr, - uint32_t filterNumber, - llwu_external_pin_filter_mode_t pinFilterMode) -{ - /* check filter and pin number */ - assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER); - assert(pinFilterMode.pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN); - - /* branch to filter number */ - switch(filterNumber) - { - case 0: - BW_LLWU_FILT1_FILTSEL(baseAddr, pinFilterMode.pinNumber); - BW_LLWU_FILT1_FILTE(baseAddr, pinFilterMode.filterMode); - break; - case 1: - BW_LLWU_FILT2_FILTSEL(baseAddr, pinFilterMode.pinNumber); - BW_LLWU_FILT2_FILTE(baseAddr, pinFilterMode.filterMode); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetPinFilterMode - * Description : Get pin filter configuration. - * This function will get the pin filter configuration. - * - *END**************************************************************************/ -void LLWU_HAL_GetPinFilterMode(uint32_t baseAddr, - uint32_t filterNumber, - llwu_external_pin_filter_mode_t *pinFilterMode) -{ - /* check filter and pin number */ - assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER); - assert(pinFilterMode->pinNumber < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN); - - /* branch to filter number */ - switch(filterNumber) - { - case 0: - pinFilterMode->pinNumber = BR_LLWU_FILT1_FILTSEL(baseAddr); - pinFilterMode->filterMode = (llwu_filter_modes_t)BR_LLWU_FILT1_FILTE(baseAddr); - break; - case 1: - pinFilterMode->pinNumber = BR_LLWU_FILT2_FILTSEL(baseAddr); - pinFilterMode->filterMode = (llwu_filter_modes_t)BR_LLWU_FILT2_FILTE(baseAddr); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetFilterDetectFlag - * Description : Get filter detect flag - * This function will get the filter detect flag. - * - *END**************************************************************************/ -bool LLWU_HAL_GetFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber) -{ - bool retValue = false; - - /* check filter and pin number */ - assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER); - - /* branch to filter number */ - switch(filterNumber) - { - case 0: - retValue = (bool)BR_LLWU_FILT1_FILTF(baseAddr); - break; - case 1: - retValue = (bool)BR_LLWU_FILT2_FILTF(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_ClearFilterDetectFlag - * Description : Clear filter detect flag - * This function will clear the filter detect flag. - * - *END**************************************************************************/ -void LLWU_HAL_ClearFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber) -{ - /* check filter and pin number */ - assert(filterNumber < FSL_FEATURE_LLWU_HAS_PIN_FILTER); - - /* branch to filter number */ - switch(filterNumber) - { - case 0: - BW_LLWU_FILT1_FILTF(baseAddr, 1); - break; - case 1: - BW_LLWU_FILT2_FILTF(baseAddr, 1); - break; - default: - break; - } -} - -#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_SetResetEnableMode - * Description : Set reset enable mode - * This function will set the reset enable mode. - * - *END**************************************************************************/ -void LLWU_HAL_SetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t resetEnableMode) -{ - BW_LLWU_RST_RSTFILT(baseAddr, resetEnableMode.digitalFilterMode); - BW_LLWU_RST_LLRSTE(baseAddr, resetEnableMode.lowLeakageMode); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LLWU_HAL_GetResetEnableMode - * Description : Get reset enable mode - * This function will get the reset enable mode. - * - *END**************************************************************************/ -void LLWU_HAL_GetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t *resetEnableMode) -{ - resetEnableMode->digitalFilterMode = (bool)BR_LLWU_RST_RSTFILT(baseAddr); - resetEnableMode->lowLeakageMode = (bool)BR_LLWU_RST_LLRSTE(baseAddr); -} -#endif - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h deleted file mode 100644 index 0ef39a805d9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_LLWU_HAL_H__) -#define __FSL_LLWU_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_llwu_features.h" - -/*! @addtogroup llwu_hal*/ -/*! @{*/ - -/*! @file fsl_llwu_hal.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief External input pin control modes */ -typedef enum _llwu_external_pin_modes { - kLlwuExternalPinDisabled, /* pin disabled as wakeup input */ - kLlwuExternalPinRisingEdge, /* pin enabled with rising edge detection */ - kLlwuExternalPinFallingEdge, /* pin enabled with falling edge detection */ - kLlwuExternalPinChangeDetect /* pin enabled with any change detection */ -} llwu_external_pin_modes_t; - -/*! @brief Digital filter control modes */ -typedef enum _llwu_filter_modes { - kLlwuFilterDisabled, /* filter disabled */ - kLlwuFilterPosEdgeDetect, /* filter positive edge detection */ - kLlwuFilterNegEdgeDetect, /* filter negative edge detection */ - kLlwuFilterAnyEdgeDetect /* filter any edge detection */ -} llwu_filter_modes_t; - -/*! @brief External input pin filter control structure */ -typedef struct _llwu_external_pin_filter_mode { - llwu_filter_modes_t filterMode; /* filter mode */ - uint32_t pinNumber; /* pin number */ -} llwu_external_pin_filter_mode_t; - -/*! @brief Reset enable control structure */ -typedef struct _llwu_reset_enable_mode { - bool lowLeakageMode; /* reset for Low-leakage mode */ - bool digitalFilterMode; /* reset for digital filter mode */ -} llwu_reset_enable_mode_t; - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @brief Sets the external input pin source mode. - * - * This function sets the external input pin source mode that is used - * as a wake up source. - * - * @param baseAddr Register base address of LLWU - * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t - * @param pinNumber pin number specified - */ -void LLWU_HAL_SetExternalInputPinMode(uint32_t baseAddr, - llwu_external_pin_modes_t pinMode, - uint32_t pinNumber); - -/*! - * @brief Gets the external input pin source mode. - * - * This function gets the external input pin source mode that is used - * as wake up source. - * - * @param baseAddr Register base address of LLWU - * @param pinNumber pin number specified - * @return pinMode pin mode defined in llwu_external_pin_modes_t - */ -llwu_external_pin_modes_t LLWU_HAL_GetExternalInputPinMode(uint32_t baseAddr, - uint32_t pinNumber); - -/*! - * @brief Enables/disables the internal module source. - * - * This function enables/disables the internal module source mode that is used - * as a wake up source. - * - * @param baseAddr Register base address of LLWU - * @param moduleNumber module number specified - * @param enable enable or disable setting - */ -void LLWU_HAL_SetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber, bool enable); - -/*! - * @brief Gets the internal module source enable setting. - * - * This function gets the internal module source enable setting that is used - * as a wake up source. - * - * @param baseAddr Register base address of LLWU - * @param moduleNumber module number specified - * @return enable enable or disable setting - */ -bool LLWU_HAL_GetInternalModuleCmd(uint32_t baseAddr, uint32_t moduleNumber); - -/*! - * @brief Gets the external wakeup source flag. - * - * This function gets the external wakeup source flag for a specific pin. - * - * @param baseAddr Register base address of LLWU - * @param pinNumber pin number specified - * @return flag true if wakeup source flag set - */ -bool LLWU_HAL_GetExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber); - -/*! - * @brief Clears the external wakeup source flag. - * - * This function clears the external wakeup source flag for a specific pin. - * - * @param baseAddr Register base address of LLWU - * @param pinNumber pin number specified - */ -void LLWU_HAL_ClearExternalPinWakeupFlag(uint32_t baseAddr, uint32_t pinNumber); - -/*! - * @brief Gets the internal module wakeup source flag. - * - * This function gets the internal module wakeup source flag for a specific module. - * - * @param baseAddr Register base address of LLWU - * @param moduleNumber module number specified - * @return flag true if wakeup flag set - */ -bool LLWU_HAL_GetInternalModuleWakeupFlag(uint32_t baseAddr, uint32_t moduleNumber); - -/*! - * @brief Sets the pin filter configuration. - * - * This function sets the pin filter configuration. - * - * @param baseAddr Register base address of LLWU - * @param filterNumber filter number specified - * @param pinFilterMode filter mode configuration - */ -void LLWU_HAL_SetPinFilterMode(uint32_t baseAddr, uint32_t filterNumber, - llwu_external_pin_filter_mode_t pinFilterMode); -/*! - * @brief Gets the pin filter configuration. - * - * This function gets the pin filter configuration. - * - * @param baseAddr Register base address of LLWU - * @param filterNumber filter number specified - * @param pinFilterMode filter mode configuration - */ -void LLWU_HAL_GetPinFilterMode(uint32_t baseAddr, uint32_t filterNumber, - llwu_external_pin_filter_mode_t *pinFilterMode); - -/*! - * @brief Gets the filter detect flag. - * - * This function will get the filter detect flag. - * - * @param baseAddr Register base address of LLWU - * @param filterNumber filter number specified - * @return flag true if the filter was a wakeup source - */ -bool LLWU_HAL_GetFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber); - -/*! - * @brief Clears the filter detect flag. - * - * This function will clear the filter detect flag. - * - * @param baseAddr Register base address of LLWU - * @param filterNumber filter number specified - */ -void LLWU_HAL_ClearFilterDetectFlag(uint32_t baseAddr, uint32_t filterNumber); - -#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE -/*! - * @brief Sets the reset enable mode. - * - * This function will set the reset enable mode. - * - * @param baseAddr Register base address of LLWU - * @param resetEnableMode reset enable mode defined in llwu_reset_enable_mode_t - */ -void LLWU_HAL_SetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t resetEnableMode); - -/*! - * @brief Gets the reset enable mode. - * - * This function gets the reset enable mode. - * - * @param baseAddr Register base address of LLWU - * @param resetEnableMode reset enable mode defined in llwu_reset_enable_mode_t - */ -void LLWU_HAL_GetResetEnableMode(uint32_t baseAddr, llwu_reset_enable_mode_t *resetEnableMode); -#endif - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Low-Leakage Wakeup Unit Control APIs*/ -/*@{*/ - - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_LLWU_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_features.h deleted file mode 100644 index 05dc795fef7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_features.h +++ /dev/null @@ -1,86 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_LPTMR_FEATURES_H__) -#define __FSL_LPTMR_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ - defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL03Z32CAF4) || \ - defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || \ - defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || \ - defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ - defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || \ - defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || \ - defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ - defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || \ - defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \ - defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \ - defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \ - defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ - defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || \ - defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || \ - defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) || defined(CPU_MKL25Z128VLK4) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_LPTMR_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.c deleted file mode 100644 index 79a9a9036ce..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lptmr_hal.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Variables - *******************************************************************************/ - -/******************************************************************************* - * Code - *******************************************************************************/ - -/******************************************************************************* - * EOF - *******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : LPTMR_HAL_Init - * Description : Initialize LPTMR module to reset state. - * - *END**************************************************************************/ -void LPTMR_HAL_Init(uint32_t baseAddr) -{ - LPTMR_HAL_Disable(baseAddr); - LPTMR_HAL_ClearIntFlag(baseAddr); - LPTMR_HAL_SetIntCmd(baseAddr, false); - LPTMR_HAL_SetPinSelectMode(baseAddr, kLptmrPinSelectCmpOut); - LPTMR_HAL_SetPinPolarityMode(baseAddr, kLptmrPinPolarityActiveHigh); - LPTMR_HAL_SetFreeRunningCmd(baseAddr, false); - LPTMR_HAL_SetTimerModeMode(baseAddr, kLptmrTimerModeTimeCounter); - LPTMR_HAL_SetPrescalerCmd(baseAddr, false); - LPTMR_HAL_SetPrescalerValueMode(baseAddr, kLptmrPrescalerDivide2); - LPTMR_HAL_SetPrescalerClockSourceMode(baseAddr, kLptmrPrescalerClockSourceMcgIrcClk); - LPTMR_HAL_SetCompareValue(baseAddr, 0x0); -} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.h deleted file mode 100644 index 451b25bf15e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_LPTMR_HAL_H__ -#define __FSL_LPTMR_HAL_H__ - -#include -#include -#include -#include "fsl_lptmr_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup lptmr_hal - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief LPTMR pin selection.*/ -typedef enum _lptmr_pin_select{ - kLptmrPinSelectCmpOut = 0x0U, /*!< Lptmr Pin is CMP0 output pin.*/ - kLptmrPinSelectLptmrAlt1 = 0x1U, /*!< Lptmr Pin is LPTMR_ALT1 pin.*/ - kLptmrPinSelectLptmrAlt2 = 0x2U, /*!< Lptmr Pin is LPTMR_ALT2 pin.*/ - kLptmrPinSelectLptmrAlt3 = 0x3U /*!< Lptmr Pin is LPTMR_ALT3 pin.*/ -} lptmr_pin_select_t; - -/*! @brief LPTMR pin polarity, used while in pluse counter mode.*/ -typedef enum _lptmr_pin_polarity{ - kLptmrPinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high.*/ - kLptmrPinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low.*/ -} lptmr_pin_polarity_t; - -/*! @brief LPTMR timer mode selection.*/ -typedef enum _lptmr_timer_mode{ - kLptmrTimerModeTimeCounter = 0x0U, /*!< Time Counter mode.*/ - kLptmrTimerModePluseCounter = 0x1U /*!< Pulse Counter mode.*/ -} lptmr_timer_mode_t; - -/*! @brief LPTMR proscaler value.*/ -typedef enum _lptmr_prescaler_value{ - kLptmrPrescalerDivide2 = 0x0U, /*!< Prescaler divide 2, glitch filter invalid.*/ - kLptmrPrescalerDivide4GlichFiltch2 = 0x1U, /*!< Prescaler divide 4, glitch filter 2.*/ - kLptmrPrescalerDivide8GlichFiltch4 = 0x2U, /*!< Prescaler divide 8, glitch filter 4.*/ - kLptmrPrescalerDivide16GlichFiltch8 = 0x3U, /*!< Prescaler divide 16, glitch filter 8.*/ - kLptmrPrescalerDivide32GlichFiltch16 = 0x4U, /*!< Prescaler divide 32, glitch filter 16.*/ - kLptmrPrescalerDivide64GlichFiltch32 = 0x5U, /*!< Prescaler divide 64, glitch filter 32.*/ - kLptmrPrescalerDivide128GlichFiltch64 = 0x6U, /*!< Prescaler divide 128, glitch filter 64.*/ - kLptmrPrescalerDivide256GlichFiltch128 = 0x7U, /*!< Prescaler divide 256, glitch filter 128.*/ - kLptmrPrescalerDivide512GlichFiltch256 = 0x8U, /*!< Prescaler divide 512, glitch filter 256.*/ - kLptmrPrescalerDivide1024GlichFiltch512 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512.*/ - kLptmrPrescalerDivide2048lichFiltch1024 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024.*/ - kLptmrPrescalerDivide4096GlichFiltch2048 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048.*/ - kLptmrPrescalerDivide8192GlichFiltch4096 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096.*/ - kLptmrPrescalerDivide16384GlichFiltch8192 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192.*/ - kLptmrPrescalerDivide32768GlichFiltch16384 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384.*/ - kLptmrPrescalerDivide65535GlichFiltch32768 = 0xFU /*!< Prescaler divide 65535, glitch filter 32768.*/ -} lptmr_prescaler_value_t; - -/*! @brief LPTMR clock source selection.*/ -typedef enum _lptmr_prescaler_clock_source{ - kLptmrPrescalerClockSourceMcgIrcClk = 0x0U, /*!< Clock source is MCGIRCLK.*/ - kLptmrPrescalerClockSourceLpo = 0x1U, /*!< Clock source is LPO.*/ - kLptmrPrescalerClockSourceErClk32K = 0x2U, /*!< Clock source is ERCLK32K.*/ - kLptmrPrescalerClockSourceOscErClk = 0x3U /*!< Clock source is OSCERCLK.*/ -} lptmr_prescaler_clock_source_t; - -/*! @brief LPTMR status return codes.*/ -typedef enum _lptmr_status { - kStatus_LPTMR_Success = 0x0U, /*!< Succeed. */ - kStatus_LPTMR_NotInitlialized = 0x1U, /*!< LPTMR is not initialized yet. */ - kStatus_LPTMR_NullArgument = 0x2U, /*!< Argument is NULL.*/ - kStatus_LPTMR_InvalidPrescalerValue = 0x3U, /*!< Value 0 is not valid in pulse counter mode. */ - kStatus_LPTMR_InvalidInTimeCounterMode = 0x4U, /*!< Function can not called in time counter mode. */ - kStatus_LPTMR_InvalidInPluseCounterMode = 0x5U, /*!< Function can not called in pulse counter mode. */ - kStatus_LPTMR_InvalidPlusePeriodCount = 0x6U, /*!< Pulse period count must be integer multiples of the glitch filter divider. */ - kStatus_LPTMR_TcfNotSet = 0x7U, /*!< If LPTMR is enabled, compare register can only altered when TCF is set. */ - kStatus_LPTMR_TimerPeriodUsTooSmall = 0x8U, /*!< Timer period time is too small for current clock source. */ - kStatus_LPTMR_TimerPeriodUsTooLarge = 0x9U /*!< Timer period time is too large for current clock source. */ - } lptmr_status_t; - -/******************************************************************************* - ** Variables - *******************************************************************************/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name LPTMR HAL. - * @{ - */ - -/*! - * @brief Enables the LPTMR module operation. - * - * @param baseAddr The LPTMR peripheral base address. - */ -static inline void LPTMR_HAL_Enable(uint32_t baseAddr) -{ - BW_LPTMR_CSR_TEN(baseAddr, (uint8_t)true); -} - -/*! - * @brief Disables the LPTMR module operation. - * - * @param baseAddr The LPTMR peripheral base address. - */ -static inline void LPTMR_HAL_Disable(uint32_t baseAddr) -{ - BW_LPTMR_CSR_TEN(baseAddr, (uint8_t)false); -} - -/*! - * @brief Checks whether the LPTMR module is enabled. - * - * @param baseAddr The LPTMR peripheral base address. - * @retval true LPTMR module is enabled. - * @retval false LPTMR module is disabled. - */ -static inline bool LPTMR_HAL_IsEnabled(uint32_t baseAddr) -{ - return (bool)BR_LPTMR_CSR_TEN(baseAddr); -} - -/*! - * @brief Clears the LPTMR interrupt flag if set. - * - * @param baseAddr The LPTMR peripheral base address. - */ -static inline void LPTMR_HAL_ClearIntFlag(uint32_t baseAddr) -{ - BW_LPTMR_CSR_TCF(baseAddr, 1); -} - -/*! - * @brief Returns the current LPTMR interrupt flag. - * - * @param baseAddr The LPTMR peripheral base address - * @retval true An interrupt is pending. - * @retval false No interrupt is pending. - */ -static inline bool LPTMR_HAL_IsIntPending(uint32_t baseAddr) -{ - return ((bool)BR_LPTMR_CSR_TCF(baseAddr)); -} - -/*! - * @brief Enables or disables the LPTMR interrupt. - * - * @param baseAddr The LPTMR peripheral base address - * @param enable Pass true to enable LPTMR interrupt - */ -static inline void LPTMR_HAL_SetIntCmd(uint32_t baseAddr, bool enable) -{ - BW_LPTMR_CSR_TIE(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Returns whether the LPTMR interrupt is enabled. - * - * @param baseAddr The LPTMR peripheral base address. - * @retval true LPTMR interrupt is enabled. - * @retval false LPTMR interrupt is disabled. - */ -static inline bool LPTMR_HAL_GetIntCmd(uint32_t baseAddr) -{ - return ((bool)BR_LPTMR_CSR_TIE(baseAddr)); -} - -/*! - * @brief Selects the LPTMR pulse input pin select. - * - * @param baseAddr The LPTMR peripheral base address. - * @param pinSelect Specifies LPTMR pulse input pin select, see #lptmr_pin_select_t - */ -static inline void LPTMR_HAL_SetPinSelectMode(uint32_t baseAddr, lptmr_pin_select_t pinSelect) -{ - BW_LPTMR_CSR_TPS(baseAddr, (uint8_t)pinSelect); -} - -/*! - * @brief Returns the LPTMR pulse input pin select. - * - * @param baseAddr The LPTMR peripheral base address. - * @return LPTMR pulse input pin select, see #lptmr_pin_select_t - */ -static inline lptmr_pin_select_t LPTMR_HAL_GetPinSelectMode(uint32_t baseAddr) -{ - return (lptmr_pin_select_t)BR_LPTMR_CSR_TPS(baseAddr); -} - -/*! - * @brief Selects the LPTMR pulse input pin polarity. - * - * @param baseAddr The LPTMR peripheral base address. - * @param pinPolarity Specifies LPTMR pulse input pin polarity, see #lptmr_pin_polarity_t - */ -static inline void LPTMR_HAL_SetPinPolarityMode(uint32_t baseAddr, lptmr_pin_polarity_t pinPolarity) -{ - BW_LPTMR_CSR_TPP(baseAddr, (uint8_t)pinPolarity); -} - -/*! - * @brief Returns the LPTMR pulse input pin polarity. - * - * @param baseAddr The LPTMR peripheral base address. - * @return LPTMR pulse input pin polarity, see #lptmr_pin_polarity_t - */ -static inline lptmr_pin_polarity_t LPTMR_HAL_GetPinPolarityMode(uint32_t baseAddr) -{ - return (lptmr_pin_polarity_t)BR_LPTMR_CSR_TPP(baseAddr); -} - -/*! - * @brief Enables or disables the LPTMR free running. - * - * @param baseAddr The LPTMR peripheral base address - * @param enable Pass true to enable LPTMR free running - */ -static inline void LPTMR_HAL_SetFreeRunningCmd(uint32_t baseAddr, bool enable) -{ - BW_LPTMR_CSR_TFC(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Returns whether the LPTMR free running is enabled. - * - * @param baseAddr The LPTMR peripheral base address. - * @retval true LPTMR free running is enabled. - * @retval false LPTMR free running is disabled. - */ -static inline bool LPTMR_HAL_GetFreeRunningCmd(uint32_t baseAddr) -{ - return ((bool)BR_LPTMR_CSR_TFC(baseAddr)); -} - -/*! - * @brief Selects the LPTMR working mode. - * - * @param baseAddr The LPTMR peripheral base address. - * @param timerMode Specifies LPTMR working mode, see #lptmr_timer_mode_t - */ -static inline void LPTMR_HAL_SetTimerModeMode(uint32_t baseAddr, lptmr_timer_mode_t timerMode) -{ - BW_LPTMR_CSR_TMS(baseAddr, (uint8_t)timerMode); -} - -/*! - * @brief Returns the LPTMR working mode. - * - * @param baseAddr The LPTMR peripheral base address. - * @return LPTMR working mode, see #lptmr_timer_mode_t - */ -static inline lptmr_timer_mode_t LPTMR_HAL_GetTimerModeMode(uint32_t baseAddr) -{ - return (lptmr_timer_mode_t)BR_LPTMR_CSR_TMS(baseAddr); -} - -/*! - * @brief Selects the LPTMR prescaler value. - * - * @param baseAddr The LPTMR peripheral base address. - * @param prescaleValue Specifies LPTMR prescaler value, see #lptmr_prescaler_value_t - */ -static inline void LPTMR_HAL_SetPrescalerValueMode(uint32_t baseAddr, lptmr_prescaler_value_t prescaleValue) -{ - BW_LPTMR_PSR_PRESCALE(baseAddr, (uint8_t)prescaleValue); -} - -/*! - * @brief Returns the LPTMR prescaler value. - * - * @param baseAddr The LPTMR peripheral base address. - * @return LPTMR prescaler value, see #lptmr_prescaler_value_t - */ -static inline lptmr_prescaler_value_t LPTMR_HAL_GetPrescalerValueMode(uint32_t baseAddr) -{ - return (lptmr_prescaler_value_t)BR_LPTMR_PSR_PRESCALE(baseAddr); -} - -/*! - * @brief Enables or disables the LPTMR prescaler. - * - * @param baseAddr The LPTMR peripheral base address - * @param enable Pass true to enable LPTMR free running - */ -static inline void LPTMR_HAL_SetPrescalerCmd(uint32_t baseAddr, bool enable) -{ - BW_LPTMR_PSR_PBYP(baseAddr, (uint8_t)(enable == false)); /* 1 means disable prelsaler , 0 means enalbe prescaler */ -} - -/*! - * @brief Returns whether the LPTMR prescaler is enabled. - * - * @param baseAddr The LPTMR peripheral base address. - * @retval true LPTMR prescaler is enabled. - * @retval false LPTMR prescaler is disabled. - */ -static inline bool LPTMR_HAL_GetPrescalerCmd(uint32_t baseAddr) -{ - return (bool)(0 == BR_LPTMR_PSR_PBYP(baseAddr)); /* 1 means prelsaler is disabled, 0 means prescaler is enalbed*/ -} - -/*! - * @brief Selects the LPTMR clock source. - * - * @param baseAddr The LPTMR peripheral base address. - * @param prescalerClockSource Specifies LPTMR clock source, see #lptmr_prescaler_clock_source_t - */ -static inline void LPTMR_HAL_SetPrescalerClockSourceMode(uint32_t baseAddr, lptmr_prescaler_clock_source_t prescalerClockSource) -{ - BW_LPTMR_PSR_PCS(baseAddr, (uint8_t)prescalerClockSource); -} - -/*! - * @brief Gets the LPTMR clock source. - * - * @param baseAddr The LPTMR peripheral base address. - * @return LPTMR clock source, see #lptmr_prescaler_clock_source_t - */ -static inline lptmr_prescaler_clock_source_t LPTMR_HAL_GetPrescalerClockSourceMode(uint32_t baseAddr) -{ - return (lptmr_prescaler_clock_source_t)BR_LPTMR_PSR_PCS(baseAddr); -} - -/*! - * @brief Sets the LPTMR compare value. - * - * @param baseAddr The LPTMR peripheral base address. - * @param compareValue Specifies LPTMR compare value, less than 0xFFFFU - */ -static inline void LPTMR_HAL_SetCompareValue(uint32_t baseAddr, uint32_t compareValue) -{ - BW_LPTMR_CMR_COMPARE(baseAddr, compareValue & 0xFFFFU); -} - -/*! - * @brief Gets the LPTMR compare value. - * - * @param baseAddr The LPTMR peripheral base address. - * @return Current LPTMR compare value - */ -static inline uint32_t LPTMR_HAL_GetCompareValue(uint32_t baseAddr) -{ - return (uint32_t)(BR_LPTMR_CMR_COMPARE(baseAddr) & 0xFFFFU); -} - -/*! - * @brief Gets the LPTMR counter value. - * - * @param baseAddr The LPTMR peripheral base address. - * @return Current LPTMR counter value - */ -static inline uint32_t LPTMR_HAL_GetCounterValue(uint32_t baseAddr) -{ - BW_LPTMR_CNR_COUNTER(baseAddr, 0); /* Must first write to the CNR with any value */ - return (uint32_t)(BR_LPTMR_CNR_COUNTER(baseAddr) & 0xFFFFU); -} - -/*! - * @brief Restores the LPTMR module to reset state. - * - * @param baseAddr The LPTMR peripheral base address - */ -void LPTMR_HAL_Init(uint32_t baseAddr); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_LPTMR_HAL_H__*/ -/******************************************************************************* - * EOF - *******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h deleted file mode 100644 index c50f05f8aed..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h +++ /dev/null @@ -1,220 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_LPUART_FEATURES_H__) -#define __FSL_LPUART_FEATURES_H__ - -#if defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_LPUART_HAS_FIFO (0) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) - /* @brief Peripheral type. */ - #define FSL_FEATURE_LPUART_IS_SCI (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_LPUART_FIFO_SIZE (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_LPUART_HAS_FIFO (0) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) - /* @brief Peripheral type. */ - #define FSL_FEATURE_LPUART_IS_SCI (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_LPUART_FIFO_SIZE (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_LPUART_HAS_FIFO (0) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) - /* @brief Peripheral type. */ - #define FSL_FEATURE_LPUART_IS_SCI (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_LPUART_FIFO_SIZE (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -#else - #define MBED_NO_LPUART -#endif - -#endif /* __FSL_LPUART_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.c deleted file mode 100644 index 075407dbee8..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.c +++ /dev/null @@ -1,782 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_lpuart_hal.h" - -#ifndef MBED_NO_LPUART - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_Init - * Description : Initializes the LPUART controller to known state. - * - *END**************************************************************************/ -void LPUART_HAL_Init(uint32_t baseAddr) -{ - HW_LPUART_BAUD_WR(baseAddr, 0x0F000004); - HW_LPUART_STAT_WR(baseAddr, 0xC01FC000); - HW_LPUART_CTRL_WR(baseAddr, 0x00000000); - HW_LPUART_MATCH_WR(baseAddr, 0x00000000); - HW_LPUART_MODIR_WR(baseAddr, 0x00000000); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetBaudRate - * Description : Configures the LPUART baud rate. - * In some LPUART instances the user must disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - *END**************************************************************************/ -lpuart_status_t LPUART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, - uint32_t desiredBaudRate) -{ - uint16_t sbr, sbrTemp, i; - uint32_t osr, tempDiff, calculatedBaud, baudDiff; - - /* This lpuart instantiation uses a slightly different baud rate calculation */ - /* The idea is to use the best OSR (over-sampling rate) possible */ - /* Note, osr is typically hard-set to 16 in other lpuart instantiations */ - /* First calculate the baud rate using the minimum OSR possible (4) */ - osr = 4; - sbr = (sourceClockInHz/(desiredBaudRate * osr)); - calculatedBaud = (sourceClockInHz / (osr * sbr)); - - if (calculatedBaud > desiredBaudRate) - { - baudDiff = calculatedBaud - desiredBaudRate; - } - else - { - baudDiff = desiredBaudRate - calculatedBaud; - } - - /* loop to find the best osr value possible, one that generates minimum baudDiff */ - /* iterate through the rest of the supported values of osr */ - for (i = 5; i <= 32; i++) - { - /* calculate the temporary sbr value */ - sbrTemp = (sourceClockInHz/(desiredBaudRate * i)); - /* calculate the baud rate based on the temporary osr and sbr values */ - calculatedBaud = (sourceClockInHz / (i * sbrTemp)); - - if (calculatedBaud > desiredBaudRate) - { - tempDiff = calculatedBaud - desiredBaudRate; - } - else - { - tempDiff = desiredBaudRate - calculatedBaud; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = i; /* update and store the best osr value calculated */ - sbr = sbrTemp; /* update store the best sbr value calculated */ - } - } - - /* next, check to see if actual baud rate is within 3% of desired baud rate */ - /* based on the best calculate osr value */ - if (baudDiff < ((desiredBaudRate / 100) * 3)) - { - /* Acceptable baud rate */ - /* Check if osr is between 4x and 7x oversampling */ - /* If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - BW_LPUART_BAUD_BOTHEDGE(baseAddr, 1); - } - - /* program the osr value (bit value is one less than actual value) */ - BW_LPUART_BAUD_OSR(baseAddr, (osr-1)); - - /* write the sbr value to the BAUD registers */ - BW_LPUART_BAUD_SBR(baseAddr, sbr); - } - else - { - /* Unacceptable baud rate difference of more than 3% */ - return kStatus_LPUART_BaudRatePercentDiffExceeded; - } - - return kStatus_LPUART_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetBitCountPerChar - * Description : Configures the number of bits per character in the LPUART controller. - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - *END**************************************************************************/ -void LPUART_HAL_SetBitCountPerChar(uint32_t baseAddr, lpuart_bit_count_per_char_t bitCountPerChar) -{ - if(bitCountPerChar == kLpuart10BitsPerChar) - { - BW_LPUART_BAUD_M10(baseAddr, 1); /* set M10 for 10-bit mode, M bit in C1 is don't care */ - } - else - { - BW_LPUART_CTRL_M(baseAddr, bitCountPerChar); /* config 8- (M=0) or 9-bits (M=1) */ - BW_LPUART_BAUD_M10(baseAddr, 0); /* clear M10 to make sure not 10-bit mode */ - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetParityMode - * Description : Configures parity mode in the LPUART controller. - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - *END**************************************************************************/ -void LPUART_HAL_SetParityMode(uint32_t baseAddr, lpuart_parity_mode_t parityModeType) -{ - /* configure the parity enable/type */ - - if ((parityModeType) == kLpuartParityDisabled) - { - /* parity disabled, hence parity type is don't care */ - BW_LPUART_CTRL_PE(baseAddr, 0); - } - else - { - /* parity enabled */ - BW_LPUART_CTRL_PE(baseAddr, 1); - /* parity odd/even depending on parity mode setting */ - BW_LPUART_CTRL_PT(baseAddr, (parityModeType) & 0x1); - } - -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetTxRxInversionCmd - * Description : Configures the transmit and receive inversion control in the LPUART controller. - * This function should only be called when the LPUART is between transmit and receive packets. - * - *END**************************************************************************/ -void LPUART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, uint32_t rxInvert, uint32_t txInvert) -{ - /* 0 - receive data not inverted, 1 - receive data inverted */ - BW_LPUART_STAT_RXINV(baseAddr, rxInvert); - /* 0 - transmit data not inverted, 1 - transmit data inverted */ - BW_LPUART_CTRL_TXINV(baseAddr, txInvert); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_EnableTransmitter - * Description : Enables the LPUART transmitter. - * - *END**************************************************************************/ -void LPUART_HAL_EnableTransmitter(uint32_t baseAddr) -{ - /* enable the transmitter based on the lpuart baseAddr */ - - /* for this lpuart baseAddr, there is a two step process to clear the transmit complete */ - /* status flag: */ - /* 1. Read the status register with the status bit set */ - /* 2. enable the transmitter (change TE from 0 to 1) */ - /* first read the status register */ - - /* no need to store the read value, it's assumed the status bit is set */ - HW_LPUART_STAT_RD(baseAddr); - /* second, enable the transmitter */ - BW_LPUART_CTRL_TE(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetIntMode - * Description : Configures the LPUART module interrupts to enable/disable various interrupt sources. - * - *END**************************************************************************/ -void LPUART_HAL_SetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt, bool enable) -{ - uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT; - uint32_t temp = 1U << (uint32_t)interrupt; - - switch ( reg ) - { - case LPUART_BAUD_REG_ID: - enable ? HW_LPUART_BAUD_SET(baseAddr, temp) : HW_LPUART_BAUD_CLR(baseAddr, temp); - break; - case LPUART_STAT_REG_ID: - enable ? HW_LPUART_STAT_SET(baseAddr, temp) : HW_LPUART_STAT_CLR(baseAddr, temp); - break; - case LPUART_CTRL_REG_ID: - enable ? HW_LPUART_CTRL_SET(baseAddr, temp) : HW_LPUART_CTRL_CLR(baseAddr, temp); - break; - case LPUART_DATA_REG_ID: - enable ? HW_LPUART_DATA_SET(baseAddr, temp) : HW_LPUART_DATA_CLR(baseAddr, temp); - break; - case LPUART_MATCH_REG_ID: - enable ? HW_LPUART_MATCH_SET(baseAddr, temp) : HW_LPUART_MATCH_CLR(baseAddr, temp); - break; - case LPUART_MODIR_REG_ID: - enable ? HW_LPUART_MODIR_SET(baseAddr, temp) : HW_LPUART_MODIR_CLR(baseAddr, temp); - break; - default : - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_GetIntMode - * Description : Returns whether the LPUART module interrupts is enabled/disabled. - * - *END**************************************************************************/ -bool LPUART_HAL_GetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt) -{ - uint32_t reg = (uint32_t)(interrupt) >> LPUART_SHIFT; - bool retVal = false; - - switch ( reg ) - { - case LPUART_BAUD_REG_ID: - retVal = HW_LPUART_BAUD_RD(baseAddr) >> (uint32_t)(interrupt) & 1U; - break; - case LPUART_STAT_REG_ID: - retVal = HW_LPUART_STAT_RD(baseAddr) >> (uint32_t)(interrupt) & 1U; - break; - case LPUART_CTRL_REG_ID: - retVal = HW_LPUART_CTRL_RD(baseAddr) >> (uint32_t)(interrupt) & 1U; - break; - case LPUART_DATA_REG_ID: - retVal = HW_LPUART_DATA_RD(baseAddr) >> (uint32_t)(interrupt) & 1U; - break; - case LPUART_MATCH_REG_ID: - retVal = HW_LPUART_MATCH_RD(baseAddr) >> (uint32_t)(interrupt) & 1U; - break; - case LPUART_MODIR_REG_ID: - retVal = HW_LPUART_MODIR_RD(baseAddr) >> (uint32_t)(interrupt) & 1U; - break; - default : - break; - } - - return retVal; -} - -#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_ConfigureDma - * Description : LPUART configures DMA requests for Transmitter and Receiver. - * - *END**************************************************************************/ -void LPUART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig) -{ - /* TDMAE configures the transmit data register empty flag, S1[TDRE], */ - /* to generate a DMA request. */ - BW_LPUART_BAUD_TDMAE(baseAddr, txDmaConfig) ;/* set TDMAE to enable, clear to disable */ - /* RDMAE configures the receive data register fell flag, S1[RDRF], */ - /* to generate a DMA request. */ - BW_LPUART_BAUD_RDMAE(baseAddr, rxDmaConfig); /* set RDMAE to enable, clear to disable */ -} -#endif - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_GetWaitModeOperationConfig - * Description : LPUART configures DMA requests for Transmitter and Receiver. - * - *END**************************************************************************/ -lpuart_operation_config_t LPUART_HAL_GetWaitModeOperationConfig(uint32_t baseAddr) -{ - /* get configuration lpuart operation in wait mode */ - /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */ - if (BR_LPUART_CTRL_DOZEEN(baseAddr) == 0) - { - return kLpuartOperates; - } - else - { - return kLpuartStops; - } - -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SedLoopbackCmd - * Description : Configures the LPUART loopback operation (enable/disable loopback operation) - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - *END**************************************************************************/ -void LPUART_HAL_SedLoopbackCmd(uint32_t baseAddr, bool enable) -{ - /* configure lpuart to enable/disable operation in loopback mode */ - - /* configure LOOPS bit to enable(1)/disable(0) loopback mode, but also need to clear RSRC */ - BW_LPUART_CTRL_LOOPS(baseAddr, enable); - - /* clear RSRC for loopback mode, and if loopback disabled, */ - /* this bit has no meaning but clear anyway */ - /* to set it back to default value */ - BW_LPUART_CTRL_RSRC(baseAddr, 0); - -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetSingleWireCmd - * Description : Configures the LPUART single-wire operation (enable/disable single-wire mode) - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - *END**************************************************************************/ -void LPUART_HAL_SetSingleWireCmd(uint32_t baseAddr, bool enable) -{ - /* configure lpuart to enable/disable operation in single mode */ - - /* to enable single-wire mode, need both LOOPS and RSRC set, to disable, clear both */ - BW_LPUART_CTRL_LOOPS(baseAddr, enable); - BW_LPUART_CTRL_RSRC(baseAddr, enable); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_PutReceiverInStandbyMode - * Description : Places the LPUART receiver in standby mode. - * In some LPUART instances, - * before placing LPUART in standby mode, first determine whether the receiver is set to - * wake on idle or whether it is already in idle state. - * NOTE that the RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently - * not idle. - * This can be determined by the S2[RAF] flag. If it is set to wake up an IDLE event and the channel is - * already idle, it is possible that the LPUART will discard data since data must be received - * (or a LIN break detect) after an IDLE is detected and before IDLE is allowed to reasserted. - * - *END**************************************************************************/ -lpuart_status_t LPUART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr) -{ - /* In some lpuart instances, there is a condition that must be met before placing */ - /* rx in standby mode. */ - /* Before placing lpuart in standby, need to first determine if receiver is set to */ - /* wake on idle and if receiver is already in idle state. Per ref manual: */ - /* NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is */ - /* currently not idle. */ - /* This can be determined by the STAT[RAF] flag. If set to wake up an IDLE event and */ - /* the channel is already idle, it is possible that the LPUART will discard data since data */ - /* must be received (or a LIN break detect) after an IDLE is detected before IDLE is */ - /* allowed to reasserted. */ - lpuart_wakeup_method_t rxWakeMethod; - bool lpuart_current_rx_state; - - /* see if wake is set for idle or */ - rxWakeMethod = LPUART_HAL_GetReceiverWakeupMethod(baseAddr); - lpuart_current_rx_state = LPUART_HAL_GetStatusFlag(baseAddr, kLpuartRxActive); - - /* if both rxWakeMethod is set for idle and current rx state is idle, don't put in standy */ - if ((rxWakeMethod == kLpuartIdleLineWake) && (lpuart_current_rx_state == 0)) - { - return kStatus_LPUART_RxStandbyModeError; - } - else - { - /* set the RWU bit to place receiver into standby mode */ - BW_LPUART_CTRL_RWU(baseAddr, 1); - return kStatus_LPUART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_GetReceiverWakeupMethod - * Description : Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode. - * - *END**************************************************************************/ -lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr) -{ - /* get configuration of the WAKE bit for idle line wake or address mark wake */ - if(HW_LPUART_CTRL(baseAddr).B.WAKE == 1) - { - return kLpuartAddrMarkWake; - } - else - { - return kLpuartIdleLineWake; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_ConfigureIdleLineDetect - * Description : LPUART idle-line detect operation configuration (idle line bit-count start and wake - * up affect on IDLE status bit). - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - *END**************************************************************************/ -void LPUART_HAL_ConfigureIdleLineDetect(uint32_t baseAddr, - const lpuart_idle_line_config_t *config) -{ - /* Configure the idle line detection configuration as follows: */ - /* configure the ILT to bit count after start bit or stop bit */ - /* configure RWUID to set or not set IDLE status bit upon detection of */ - /* an idle character when recevier in standby */ - BW_LPUART_CTRL_ILT(baseAddr, config->idleLineType); - BW_LPUART_STAT_RWUID(baseAddr, config->rxWakeIdleDetect); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetMatchAddressOperation - * Description : LPUART configures match address mode control (Note: Feature available on - * select LPUART instances) - * - *END**************************************************************************/ -lpuart_status_t LPUART_HAL_SetMatchAddressOperation( uint32_t baseAddr, - bool matchAddrMode1, bool matchAddrMode2, - uint8_t matchAddrValue1, uint8_t matchAddrValue2, lpuart_match_config_t config) -{ - BW_LPUART_BAUD_MAEN1(baseAddr, matchAddrMode1); /* Match Address Mode Enable 1 */ - BW_LPUART_BAUD_MAEN2(baseAddr, matchAddrMode2); /* Match Address Mode Enable 2 */ - BW_LPUART_MATCH_MA1(baseAddr, matchAddrValue1); /* match address register 1 */ - BW_LPUART_MATCH_MA2(baseAddr, matchAddrValue2); /* match address register 2 */ - BW_LPUART_BAUD_MATCFG(baseAddr, config); /* Match Configuration */ - - return kStatus_LPUART_Success; -} - -#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_SetInfraredOperation - * Description : Configures the LPUART infrared operation. - * - *END**************************************************************************/ -void LPUART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable, - lpuart_ir_tx_pulsewidth_t pulseWidth) -{ - /* enable or disable infrared */ - BW_LPUART_MODIR_IREN(baseAddr, enable); - - /* configure the narrow pulse width of the IR pulse */ - BW_LPUART_MODIR_TNP(baseAddr, pulseWidth); -} -#endif /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */ - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_GetStatusFlag - * Description : LPUART get status flag by passing flag enum. - * - *END**************************************************************************/ -bool LPUART_HAL_GetStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag) -{ - uint32_t reg = (uint32_t)(statusFlag) >> LPUART_SHIFT; - bool retVal = false; - - switch ( reg ) - { - case LPUART_BAUD_REG_ID: - retVal = HW_LPUART_BAUD_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U; - break; - case LPUART_STAT_REG_ID: - retVal = HW_LPUART_STAT_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U; - break; - case LPUART_CTRL_REG_ID: - retVal = HW_LPUART_CTRL_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U; - break; - case LPUART_DATA_REG_ID: - retVal = HW_LPUART_DATA_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U; - break; - case LPUART_MATCH_REG_ID: - retVal = HW_LPUART_MATCH_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U; - break; - case LPUART_MODIR_REG_ID: - retVal = HW_LPUART_MODIR_RD(baseAddr) >> (uint32_t)(statusFlag) & 1U; - break; - default: - break; - } - - return retVal; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_ClearStatusFlag - * Description : LPUART clears an individual status flag - * (see lpuart_status_flag_t for list of status bits). - * - *END**************************************************************************/ -lpuart_status_t LPUART_HAL_ClearStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag) -{ - lpuart_status_t returnCode = kStatus_LPUART_Success; - - /* clear the desired, individual status flag as passed in through statusFlag */ - switch(statusFlag) - { - case kLpuartTxDataRegEmpty: - /* This flag is cleared automatically by other lpuart operations */ - /* and cannot be manually cleared, return error code */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; - - case kLpuartTxComplete: - /* This flag is cleared automatically by other lpuart operations */ - /* and cannot be manually cleared, return error code */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; - - case kLpuartRxDataRegFull: - /* This flag is cleared automatically by other lpuart operations and */ - /* cannot be manually cleared, return error code */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; - - case kLpuartIdleLineDetect: - /* write one to clear status flag */ - BW_LPUART_STAT_IDLE(baseAddr, 1); - break; - - case kLpuartRxOverrun: - /* write one to clear status flag */ - BW_LPUART_STAT_OR(baseAddr, 1); - break; - - case kLpuartNoiseDetect: - /* write one to clear status flag */ - BW_LPUART_STAT_NF(baseAddr, 1); - break; - - case kLpuartFrameErr: - /* write one to clear status flag */ - BW_LPUART_STAT_FE(baseAddr, 1); - break; - - case kLpuartParityErr: - /* write one to clear status flag */ - BW_LPUART_STAT_PF(baseAddr, 1); - break; - - case kLpuartLineBreakDetect: - /* write one to clear status flag */ - BW_LPUART_STAT_LBKDIF(baseAddr, 1); - break; - - case kLpuartRxActiveEdgeDetect: - /* write one to clear status flag */ - BW_LPUART_STAT_RXEDGIF(baseAddr, (1U)); - break; - - case kLpuartRxActive: - /* This flag is cleared automatically by other lpuart operations and */ - /* cannot be manually cleared, return error code */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; - -#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS - case kLpuartNoiseInCurrentWord: - /* This flag is not clearable, it simply reflects the status in the */ - /* current data word and changes with each new data word */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; - - case kLpuartParityErrInCurrentWord: - /* This flag is not clearable, it simply reflects the status in the */ - /* current data word and changes with each new data word */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; -#endif - -#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - case kLpuartMatchAddrOne: - /* write one to clear status flag */ - BW_LPUART_STAT_MA1F(baseAddr, 1); - break; - case kLpuartMatchAddrTwo: - /* write one to clear status flag */ - BW_LPUART_STAT_MA2F(baseAddr, 1); - break; -#endif - - default: /* catch inputs that are not recognized */ - returnCode = kStatus_LPUART_ClearStatusFlagError; - break; - } - - return (returnCode); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_ClearAllNonAutoclearStatusFlags - * Description : LPUART clears ALL status flags. - * - *END**************************************************************************/ -void LPUART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr) -{ - /* clear the status flags that can be manually cleared */ - /* note, some flags are automatically cleared and cannot be cleared automatically */ - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartIdleLineDetect); - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartRxOverrun); - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartNoiseDetect); - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartFrameErr); - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartParityErr); - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartLineBreakDetect); - LPUART_HAL_ClearStatusFlag(baseAddr, kLpuartRxActiveEdgeDetect); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_Putchar9 - * Description : Sends the LPUART 9-bit character. - * - *END**************************************************************************/ -void LPUART_HAL_Putchar9(uint32_t baseAddr, uint16_t data) -{ - uint8_t ninthDataBit; - - ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit */ - - /* put 9-bit data to transmit */ - - /* first, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, T8=9th bit) */ - BW_LPUART_CTRL_R9T8(baseAddr, ninthDataBit); - - /* write to the data register last since this will trigger transmit complete status flag */ - /* also typecast to uint8_t to match register type */ - HW_LPUART_DATA_WR(baseAddr, (uint8_t)data); -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_Putchar10 - * Description : Sends the LPUART 10-bit character. - * - *END**************************************************************************/ -lpuart_status_t LPUART_HAL_Putchar10(uint32_t baseAddr, uint16_t data) -{ - uint8_t ninthDataBit; - uint8_t tenthDataBit; - - /* put 10-bit data to transmit */ - ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit */ - tenthDataBit = (data >> 9U) & 0x1U; /* isolate the tenth data bit */ - - /* first, write to the tenth data bit (bit position T9, where T[0:7]=8-bits, */ - /* T9=10th bit, T8=9th bit) */ - BW_LPUART_CTRL_R8T9(baseAddr, tenthDataBit); - - /* next, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, */ - /* T9=10th bit, T8=9th bit) */ - BW_LPUART_CTRL_R9T8(baseAddr, ninthDataBit); - - /* write to the data register last since this will trigger transmit complete status flag */ - /* also typecast to uint8_t to match register type */ - HW_LPUART_DATA_WR(baseAddr, (uint8_t)data); - - return kStatus_LPUART_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_Getchar - * Description : Gets the LPUART 8-bit character. - * - *END**************************************************************************/ -void LPUART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData) -{ - /* get 8-bit data from the lpuart data register */ - *readData = (uint8_t)HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */ -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_Getchar9 - * Description : Gets the LPUART 9-bit character. - * - *END**************************************************************************/ -void LPUART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData) -{ - uint16_t temp; - - /* get 9-bit data from the lpuart data register */ - /* read ninth data bit and left shift to bit position R8 before reading */ - /* the 8 other data bits R[7:0] */ - temp = HW_LPUART_CTRL(baseAddr).B.R8T9; /* need this two step process to work around mishra rule */ - *readData = temp << 8; - - /* do last: get 8-bit data from the lpuart data register, will clear certain */ - /* receive status bits once completed */ - /* need to OR these 8-bits with the ninth bit value above */ - *readData |= (uint8_t)HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */ -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_HAL_Getchar10 - * Description : Gets the LPUART 10-bit character. - * - *END**************************************************************************/ -lpuart_status_t LPUART_HAL_Getchar10(uint32_t baseAddr, uint16_t *readData) -{ - /* get 10-bit data from the lpuart data register, available only on supported lpuarts */ - - /* read tenth data bit and left shift to bit position R9 before reading the 9 other */ - /* data bits: R8 and R[7:0] */ - *readData = (uint16_t)((uint32_t)(HW_LPUART_CTRL(baseAddr).B.R9T8) << 9U); - - /* read ninth data bit and left shift to bit position R8 before reading the 8 other */ - /* data bits R[7:0] */ - *readData |= (uint16_t)((uint32_t)(HW_LPUART_CTRL(baseAddr).B.R8T9) << 8U); - - /* do last: get 8-bit data from the lpuart data register, will clear certain receive */ - /* status bits once completed */ - /* need to OR these 8-bits with the ninth bit value above */ - *readData |= HW_LPUART_DATA_RD(baseAddr); /* read 8-bit data from data register */ - - return kStatus_LPUART_Success; -} - -#endif /* MBED_NO_LPUART */ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.h deleted file mode 100644 index 02bf3548c5f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.h +++ /dev/null @@ -1,1134 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_LPUART_HAL_H__ -#define __FSL_LPUART_HAL_H__ - -#include -#include -#include -#include "fsl_lpuart_features.h" -#include "fsl_device_registers.h" - -#ifndef MBED_NO_LPUART - -/*! - * @addtogroup lpuart_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define LPUART_SHIFT (16U) -#define LPUART_BAUD_REG_ID (0U) -#define LPUART_STAT_REG_ID (1U) -#define LPUART_CTRL_REG_ID (2U) -#define LPUART_DATA_REG_ID (3U) -#define LPUART_MATCH_REG_ID (4U) -#define LPUART_MODIR_REG_ID (5U) - -/*! @brief Error codes for the LPUART driver.*/ -typedef enum _lpuart_status -{ - kStatus_LPUART_Success, - kStatus_LPUART_BaudRateCalculationError , /*!< LPUART Baud Rate calculation error out of range. */ - kStatus_LPUART_BaudRatePercentDiffExceeded, /*!< LPUART Baud Rate exceeds percentage difference*/ - kStatus_LPUART_BitCountNotSupported, /*!< LPUART bit count configuration not supported.*/ - kStatus_LPUART_StopBitCountNotSupported, /*!< LPUART stop bit count configuration not supported.*/ - kStatus_LPUART_RxStandbyModeError, /*!< LPUART unable to place receiver in standby mode.*/ - kStatus_LPUART_ClearStatusFlagError, /*!< LPUART clear status flag error.*/ - kStatus_LPUART_MSBFirstNotSupported, /*!< LPUART MSB first feature not supported.*/ - kStatus_LPUART_Resync_NotSupported, /*!< LPUART resync disable operation not supported.*/ - kStatus_LPUART_TxNotDisabled, /*!< LPUART Transmitter not disabled before enabling feature*/ - kStatus_LPUART_RxNotDisabled, /*!< LPUART Receiver not disabled before enabling feature*/ - kStatus_LPUART_TxOrRxNotDisabled, /*!< LPUART Transmitter or Receiver not disabled*/ - kStatus_LPUART_TxBusy, /*!< LPUART transmit still in progress.*/ - kStatus_LPUART_RxBusy, /*!< LPUART receive still in progress.*/ - kStatus_LPUART_NoTransmitInProgress, /*!< LPUART no transmit in progress.*/ - kStatus_LPUART_NoReceiveInProgress, /*!< LPUART no receive in progress.*/ - kStatus_LPUART_InvalidInstanceNumber, /*!< Invalid LPUART base address */ - kStatus_LPUART_InvalidBitSetting, /*!< Invalid setting for desired LPUART register bit field */ - kStatus_LPUART_OverSamplingNotSupported, /*!< LPUART oversampling not supported.*/ - kStatus_LPUART_BothEdgeNotSupported, /*!< LPUART both edge sampling not supported. */ - kStatus_LPUART_Timeout, /*!< LPUART transfer timed out.*/ - kStatus_LPUART_Initialized, -} lpuart_status_t; - -/*! @brief LPUART number of stop bits*/ -typedef enum _lpuart_stop_bit_count { - kLpuartOneStopBit = 0, /*!< one stop bit*/ - kLpuartTwoStopBit = 1, /*!< two stop bits*/ -} lpuart_stop_bit_count_t; - -/*! @brief LPUART parity mode*/ -typedef enum _lpuart_parity_mode { - kLpuartParityDisabled = 0x0, /*!< parity disabled*/ - kLpuartParityEven = 0x2, /*!< parity enabled, type even, bit setting: PE|PT = 10*/ - kLpuartParityOdd = 0x3, /*!< parity enabled, type odd, bit setting: PE|PT = 11*/ -} lpuart_parity_mode_t; - -/*! @brief LPUART number of bits in a character*/ -typedef enum _lpuart_bit_count_per_char { - kLpuart8BitsPerChar = 0, /*!< 8-bit data characters*/ - kLpuart9BitsPerChar = 1, /*!< 9-bit data characters*/ - kLpuart10BitsPerChar = 2, /*!< 10-bit data characters*/ -} lpuart_bit_count_per_char_t; - -/*! @brief LPUART operation configuration constants*/ -typedef enum _lpuart_operation_config { - kLpuartOperates = 0,/*!< LPUART continues to operate normally.*/ - kLpuartStops = 1, /*!< LPUART stops operation. */ -} lpuart_operation_config_t; - -/*! @brief LPUART wakeup from standby method constants*/ -typedef enum _lpuart_wakeup_method { - kLpuartIdleLineWake = 0, /*!< Idle-line wakes the LPUART receiver from standby. */ - kLpuartAddrMarkWake = 1, /*!< Addr-mark wakes LPUART receiver from standby.*/ -} lpuart_wakeup_method_t; - -/*! @brief LPUART idle line detect selection types*/ -typedef enum _lpuart_idle_line_select { - kLpuartIdleLineAfterStartBit = 0, /*!< LPUART idle character bit count start after start bit */ - kLpuartIdleLineAfterStopBit = 1, /*!< LPUART idle character bit count start after stop bit */ -} lpuart_idle_line_select_t; - -/*! - * @brief LPUART break character length settings for transmit/detect. - * - * The actual maximum bit times may vary depending on the LPUART instance. - */ -typedef enum _lpuart_break_char_length { - kLpuartBreakChar10BitMinimum = 0, /*!< LPUART break char length 10 bit times (if M = 0, SBNS = 0) - or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, - SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1 .*/ - kLpuartBreakChar13BitMinimum = 1, /*!< LPUART break char length 13 bit times (if M = 0, SBNS = 0) - or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, - SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1)*/ -} lpuart_break_char_length_t; - -/*! @brief LPUART single-wire mode TX direction*/ -typedef enum _lpuart_singlewire_txdir { - kLpuartSinglewireTxdirIn = 0, /*!< LPUART Single Wire mode TXDIR input*/ - kLpuartSinglewireTxdirOut = 1, /*!< LPUART Single Wire mode TXDIR output*/ -} lpuart_singlewire_txdir_t; - -/*! @brief LPUART Configures the match addressing mode used.*/ -typedef enum _lpuart_match_config { - kLpuartAddressMatchWakeup = 0, /*!< LPUART Address Match Wakeup*/ - kLpuartIdleMatchWakeup = 1, /*!< LPUART Idle Match Wakeup*/ - kLpuartMatchOnAndMatchOff = 2, /*!< LPUART Match On and Match Off*/ - kLpuartEnablesRwuOnDataMatch = 3, /*!< LPUART Enables RWU on Data Match and Match On/Off for transmitter CTS input*/ -} lpuart_match_config_t; - -/*! @brief LPUART infra-red transmitter pulse width options*/ -typedef enum _lpuart_ir_tx_pulsewidth { - kLpuartIrThreeSixteenthsWidth = 0, /*!< 3/16 pulse*/ - kLpuartIrOneSixteenthWidth = 1, /*!< 1/16 pulse*/ - kLpuartIrOneThirtysecondsWidth = 2, /*!< 1/32 pulse*/ - kLpuartIrOneFourthWidth = 3, /*!< 1/4 pulse*/ -} lpuart_ir_tx_pulsewidth_t; - -/*! @brief LPUART Configures the number of idle characters that must be received before the IDLE flag is set. */ -typedef enum _lpuart_idle_config { - kLpuart_1_IdleChar = 0, /*!< 1 idle character*/ - kLpuart_2_IdleChar = 1, /*!< 2 idle character*/ - kLpuart_4_IdleChar = 2, /*!< 4 idle character*/ - kLpuart_8_IdleChar = 3, /*!< 8 idle character*/ - kLpuart_16_IdleChar = 4, /*!< 16 idle character*/ - kLpuart_32_IdleChar = 5, /*!< 32 idle character*/ - kLpuart_64_IdleChar = 6, /*!< 64 idle character*/ - kLpuart_128_IdleChar = 7, /*!< 128 idle character*/ -} lpuart_idle_config_t; - -/*! @brief LPUART Transmits the CTS Configuration. Configures the source of the CTS input.*/ -typedef enum _lpuart_cts_source { - kLpuartCtsSourcePin = 0, /*!< LPUART CTS input is the LPUART_CTS pin.*/ - kLpuartCtsSourceInvertedReceiverMatch = 1, /*!< LPUART CTS input is the inverted Receiver Match result.*/ -} lpuart_cts_source_t; - -/*! @brief LPUART Transmits CTS Source.Configures if the CTS state is checked at the start of each character or only when the transmitter is idle.*/ -typedef enum _lpuart_cts_config { - kLpuartCtsSampledOnEachCharacter = 0, /*!< LPUART CTS input is sampled at the start of each character.*/ - kLpuartCtsSampledOnIdle = 1, /*!< LPUART CTS input is sampled when the transmitter is idle.*/ -} lpuart_cts_config_t; - -/*! @brief Structure for idle line configuration settings*/ -typedef struct LpuartIdleLineConfig { - unsigned idleLineType : 1; /*!< ILT, Idle bit count start: 0 - after start bit (default),*/ - /*! 1 - after stop bit */ - unsigned rxWakeIdleDetect : 1; /*!< RWUID, Receiver Wake Up Idle Detect. IDLE status bit */ - /*! operation during receive standbyControls whether idle */ - /*! character that wakes up receiver will also set */ - /*! IDLE status bit 0 - IDLE status bit doesn't */ - /*! get set (default), 1 - IDLE status bit gets set*/ -} lpuart_idle_line_config_t; - -/*! - * @brief LPUART status flags. - * - * This provides constants for the LPUART status flags for use in the UART functions. - */ -typedef enum _lpuart_status_flag { - kLpuartTxDataRegEmpty = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_TDRE, /*!< Tx data register empty flag, sets when Tx buffer is empty */ - kLpuartTxComplete = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_TC, /*!< Transmission complete flag, sets when transmission activity complete */ - kLpuartRxDataRegFull = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_RDRF, /*!< Rx data register full flag, sets when the receive data buffer is full */ - kLpuartIdleLineDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_IDLE, /*!< Idle line detect flag, sets when idle line detected */ - kLpuartRxOverrun = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_OR, /*!< Rxr Overrun, sets when new data is received before data is read from receive register */ - kLpuartNoiseDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_NF, /*!< Rxr takes 3 samples of each received bit. If any of these samples differ, noise flag sets */ - kLpuartFrameErr = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_FE, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ - kLpuartParityErr = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_PF, /*!< If parity enabled, sets upon parity error detection */ - kLpuartLineBreakDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_LBKDE, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ - kLpuartRxActiveEdgeDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_RXEDGIF, /*!< Rx pin active edge interrupt flag, sets when active edge detected */ - kLpuartRxActive = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_RAF, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ -#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS - kLpuartNoiseInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | BP_LPUART_DATA_NOISY, /*!< NOISY bit, sets if noise detected in current data word */ - kLpuartParityErrInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | BP_LPUART_DATA_PARITYE, /*!< PARITYE bit, sets if noise detected in current data word */ -#endif -#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - kLpuartMatchAddrOne = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_MA1F, /*!< Address one match flag */ - kLpuartMatchAddrTwo = LPUART_STAT_REG_ID << LPUART_SHIFT | BP_LPUART_STAT_MA2F, /*!< Address two match flag */ -#endif -} lpuart_status_flag_t; - -/*! @brief LPUART interrupt configuration structure, default settings are 0 (disabled)*/ -typedef enum _lpuart_interrupt { - kLpuartIntLinBreakDetect = LPUART_BAUD_REG_ID << LPUART_SHIFT | BP_LPUART_BAUD_LBKDIE, /*!< LIN break detect. */ - kLpuartIntRxActiveEdge = LPUART_BAUD_REG_ID << LPUART_SHIFT | BP_LPUART_BAUD_RXEDGIE, /*!< RX Active Edge. */ - kLpuartIntTxDataRegEmpty = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_TIE, /*!< Transmit data register empty. */ - kLpuartIntTxComplete = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_TCIE, /*!< Transmission complete. */ - kLpuartIntRxDataRegFull = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_RIE, /*!< Receiver data register full. */ - kLpuartIntIdleLine = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_ILIE, /*!< Idle line. */ - kLpuartIntRxOverrun = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_ORIE, /*!< Receiver Overrun. */ - kLpuartIntNoiseErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_NEIE, /*!< Noise error flag. */ - kLpuartIntFrameErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_FEIE, /*!< Framing error flag. */ - kLpuartIntParityErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_PEIE, /*!< Parity error flag. */ -#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - kLpuartIntMatchAddrOne = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_MA1IE, /*!< Match address one flag. */ - kLpuartIntMatchAddrTwo = LPUART_CTRL_REG_ID << LPUART_SHIFT | BP_LPUART_CTRL_MA2IE, /*!< Match address two flag. */ -#endif -} lpuart_interrupt_t; - - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name LPUART Common Configurations - * @{ - */ - -/*! - * @brief Initializes the LPUART controller to known state. - * - * @param baseAddr LPUART base address. - */ -void LPUART_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Enables the LPUART transmitter. - * - * @param baseAddr LPUART base address. - */ -void LPUART_HAL_EnableTransmitter(uint32_t baseAddr); - -/*! - * @brief Disables the LPUART transmitter. - * - * @param baseAddr LPUART base address - */ -static inline void LPUART_HAL_DisableTransmitter(uint32_t baseAddr) -{ - BW_LPUART_CTRL_TE(baseAddr, 0); -} - -/*! - * @brief Gets the LPUART transmitter enabled/disabled configuration. - * - * @param baseAddr LPUART base address - * @return State of LPUART transmitter enable(1)/disable(0) - */ -static inline bool LPUART_HAL_IsTransmitterEnabled(uint32_t baseAddr) -{ - return BR_LPUART_CTRL_TE(baseAddr); -} - -/*! - * @brief Enables the LPUART receiver. - * - * @param baseAddr LPUART base address - */ -static inline void LPUART_HAL_EnableReceiver(uint32_t baseAddr) -{ - BW_LPUART_CTRL_RE(baseAddr, 1); -} - -/*! - * @brief Disables the LPUART receiver. - * - * @param baseAddr LPUART base address - */ -static inline void LPUART_HAL_DisableReceiver(uint32_t baseAddr) -{ - BW_LPUART_CTRL_RE(baseAddr, 0); -} - -/*! - * @brief Gets the LPUART receiver enabled/disabled configuration. - * - * @param baseAddr LPUART base address - * @return State of LPUART receiver enable(1)/disable(0) - */ -static inline bool LPUART_HAL_IsReceiverEnabled(uint32_t baseAddr) -{ - return BR_LPUART_CTRL_RE(baseAddr); -} - -/*! - * @brief Configures the LPUART baud rate. - * - * In some LPUART instances the user must disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address. - * @param sourceClockInHz LPUART source input clock in Hz. - * @param desiredBaudRate LPUART desired baud rate. - * @return An error code or kStatus_Success - */ -lpuart_status_t LPUART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, - uint32_t desiredBaudRate); - -/*! - * @brief Sets the LPUART baud rate modulo divisor. - * - * @param baseAddr LPUART base address. - * @param baudRateDivisor The baud rate modulo division "SBR" - */ -static inline void LPUART_HAL_SetBaudRateDivisor(uint32_t baseAddr, uint32_t baudRateDivisor) -{ - assert ((baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1)); - BW_LPUART_BAUD_SBR(baseAddr, baudRateDivisor); -} - -#if FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT -/*! - * @brief Sets the LPUART baud rate oversampling ratio (Note: Feature available on select - * LPUART instances used together with baud rate programming) - * The oversampling ratio should be set between 4x (00011) and 32x (11111). Writing - * an invalid oversampling ratio results in an error and is set to a default - * 16x (01111) oversampling ratio. - * IDisable the transmitter/receiver before calling - * this function. - * - * @param baseAddr LPUART base address. - * @param overSamplingRatio The oversampling ratio "OSR" - */ -static inline void LPUART_HAL_SetOversamplingRatio(uint32_t baseAddr, uint32_t overSamplingRatio) -{ - assert(overSamplingRatio < 0x1F); - BW_LPUART_BAUD_OSR(baseAddr, overSamplingRatio); -} -#endif - -#if FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT -/*! - * @brief Configures the LPUART baud rate both edge sampling (Note: Feature available on select - * LPUART instances used with baud rate programming) - * When enabled, the received data is sampled on both edges of the baud rate clock. - * This must be set when the oversampling ratio is between 4x and 7x. - * This function should only be called when the receiver is disabled. - * - * @param baseAddr LPUART base address. - * @param enableBothEdgeSampling Enable (1) or Disable (0) Both Edge Sampling - * @return An error code or kStatus_Success - */ -static inline void LPUART_HAL_SetBothEdgeSamplingCmd(uint32_t baseAddr, bool enableBothEdgeSampling) -{ - BW_LPUART_BAUD_BOTHEDGE(baseAddr, enableBothEdgeSampling); -} -#endif - -/*! - * @brief Configures the number of bits per character in the LPUART controller. - * - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address. - * @param bitCountPerChar Number of bits per char (8, 9, or - * 10, depending on the LPUART instance) - */ -void LPUART_HAL_SetBitCountPerChar(uint32_t baseAddr, lpuart_bit_count_per_char_t bitCountPerChar); - - -/*! - * @brief Configures parity mode in the LPUART controller. - * - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address. - * @param parityModeType Parity mode (enabled, disable, odd, even - see parity_mode_t struct) - */ -void LPUART_HAL_SetParityMode(uint32_t baseAddr, lpuart_parity_mode_t parityModeType); - -/*! - * @brief Configures the number of stop bits in the LPUART controller. - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address. - * @param stopBitCount Number of stop bits (1 or 2 - see lpuart_stop_bit_count_t struct) - * @return An error code (an unsupported setting in some LPUARTs) or kStatus_Success - */ -static inline void LPUART_HAL_SetStopBitCount(uint32_t baseAddr, lpuart_stop_bit_count_t stopBitCount) -{ - /* configure the number of stop bits */ - BW_LPUART_BAUD_SBNS(baseAddr, stopBitCount); -} - -/*! - * @brief Configures the transmit and receive inversion control in the LPUART controller. - * - * This function should only be called when the LPUART is between transmit and receive packets. - * - * @param baseAddr LPUART base address. - * @param rxInvert Enable (1) or disable (0) receive inversion - * @param txInvert Enable (1) or disable (0) transmit inversion - */ -void LPUART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, uint32_t rxInvert, uint32_t txInvert); - -/*@}*/ - -/*! - * @name LPUART Interrupts and DMA - * @{ - */ - -/*! - * @brief Configures the LPUART module interrupts to enable/disable various interrupt sources. - * - * @param baseAddr LPUART module base address. - * @param interrupt LPUART interrupt configuration data. - * @param enable true: enable, false: disable. - */ -void LPUART_HAL_SetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt, bool enable); - -/*! - * @brief Returns whether the LPUART module interrupts is enabled/disabled. - * - * @param baseAddr LPUART module base address. - * @param interrupt LPUART interrupt configuration data. - * @return true: enable, false: disable. - */ -bool LPUART_HAL_GetIntMode(uint32_t baseAddr, lpuart_interrupt_t interrupt); - -/*! - * @brief Enable/Disable the transmission_complete_interrupt. - * - * @param baseAddr LPUART base address - * @param enable true: enable, false: disable. - */ -static inline void LPUART_HAL_SetTxDataRegEmptyIntCmd(uint32_t baseAddr, bool enable) -{ - BW_LPUART_CTRL_TIE(baseAddr, enable); -} - -/*! - * @brief Gets the configuration of the transmission_data_register_empty_interrupt enable setting. - * - * @param baseAddr LPUART base address - * @return Bit setting of the interrupt enable bit - */ -static inline bool LPUART_HAL_GetTxDataRegEmptyIntCmd(uint32_t baseAddr) -{ - return BR_LPUART_CTRL_TIE(baseAddr); -} - -/*! - * @brief Enables the rx_data_register_full_interrupt. - * - * @param baseAddr LPUART base address - * @param enable true: enable, false: disable. - */ -static inline void LPUART_HAL_SetRxDataRegFullIntCmd(uint32_t baseAddr, bool enable) -{ - BW_LPUART_CTRL_RIE(baseAddr, enable); -} - -/*! - * @brief Gets the configuration of the rx_data_register_full_interrupt enable. - * - * @param baseAddr LPUART base address - * @return Bit setting of the interrupt enable bit - */ -static inline bool LPUART_HAL_GetRxDataRegFullIntCmd(uint32_t baseAddr) -{ - return BR_LPUART_CTRL_RIE(baseAddr); -} - -#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE -/*! - * @brief LPUART configures DMA requests for Transmitter and Receiver. - * - * @param baseAddr LPUART base address - * @param txDmaConfig Transmit DMA request configuration (enable:1 /disable: 0) - * @param rxDmaConfig Receive DMA request configuration (enable: 1/disable: 0) - */ -void LPUART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig); - -/*! - * @brief Gets the LPUART Transmit DMA request configuration. - * - * @param baseAddr LPUART base address - * @return Transmit DMA request configuration (enable: 1/disable: 0) - */ -static inline bool LPUART_HAL_IsTxDmaEnabled(uint32_t baseAddr) -{ - /* TDMAE configures the transmit data register empty flag, S1[TDRE], to */ - /* generate a DMA request. */ - return BR_LPUART_BAUD_TDMAE(baseAddr); -} - -/*! - * @brief Gets the LPUART receive DMA request configuration. - * - * @param baseAddr LPUART base address - * @return Receives the DMA request configuration (enable: 1/disable: 0). - */ -static inline bool LPUART_HAL_IsRxDmaEnabled(uint32_t baseAddr) -{ - /* RDMAE configures the receive data register fell flag, S1[RDRF], to */ - /* generate a DMA request. */ - return BR_LPUART_BAUD_RDMAE(baseAddr); -} - -#endif - -/*@}*/ - -/*! - * @name LPUART Transfer Functions - * @{ - */ - -/*! - * @brief Sends the LPUART 8-bit character. - * - * @param baseAddr LPUART Instance - * @param data data to send (8-bit) - */ -static inline void LPUART_HAL_Putchar(uint32_t baseAddr, uint8_t data) -{ - /* put 8-bit data into the lpuart data register */ - HW_LPUART_DATA_WR(baseAddr, data); -} - -/*! - * @brief Sends the LPUART 9-bit character. - * - * @param baseAddr LPUART Instance - * @param data data to send (9-bit) - */ -void LPUART_HAL_Putchar9(uint32_t baseAddr, uint16_t data); - -/*! - * @brief Sends the LPUART 10-bit character (Note: Feature available on select LPUART instances). - * - * @param baseAddr LPUART Instance - * @param data data to send (10-bit) - * @return An error code or kStatus_Success - */ -lpuart_status_t LPUART_HAL_Putchar10(uint32_t baseAddr, uint16_t data); - -/*! - * @brief Gets the LPUART 8-bit character. - * - * @param baseAddr LPUART base address - * @param readData data read from receive (8-bit) - */ -void LPUART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData); - -/*! - * @brief Gets the LPUART 9-bit character. - * - * @param baseAddr LPUART base address - * @param readData data read from receive (9-bit) - */ -void LPUART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData); - -/*! - * @brief Gets the LPUART 10-bit character. - * - * @param baseAddr LPUART base address - * @param readData data read from receive (10-bit) - * @return An error code or kStatus_Success - */ -lpuart_status_t LPUART_HAL_Getchar10(uint32_t baseAddr, uint16_t *readData); - -/*! - * @brief Configures the number of idle characters that must be received before the IDLE flag is set. - * - * @param baseAddr LPUART base address - * @param idle_config idle characters configuration - */ -static inline void LPUART_HAL_IdleConfig(uint32_t baseAddr, lpuart_idle_config_t idleConfig) -{ - BW_LPUART_CTRL_IDLECFG(baseAddr, idleConfig); -} - -/*! - * @brief Gets the configuration of the number of idle characters that must be received before the IDLE flag is set. - * - * @param baseAddr LPUART base address - * @return idle characters configuration - */ -static inline lpuart_idle_config_t LPUART_HAL_GetIdleconfig(uint32_t baseAddr) -{ - /* get the receiver idle character config based on the LPUART baseAddr */ - return (lpuart_idle_config_t)BR_LPUART_CTRL_IDLECFG(baseAddr); -} - -#if FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS -/*! - * @brief Configures bit10 (if enabled) or bit9 (if disabled) as the parity bit in the serial - * transmission. - * This sets LPUARTx_C4[M10] - it is also required to set LPUARTx_C1[M] and LPUARTx_C1[PE] - * - * @param baseAddr LPUART base address - * @param enable Enable (1) to configure bit10 as the parity bit, disable (0) to - * configure bit 9 as the parity bit in the serial transmission - */ -static inline void LPUART_HAL_ConfigureBit10AsParityBitOperation(uint32_t baseAddr, bool enable) -{ - /* to enable the parity bit as the tenth data bit, along with enabling LPUARTx_C4[M10] */ - /* need to also enable parity and set LPUARTx_CTRL[M] bit */ - /* assumed that the user has already set the appropriate bits */ - BW_LPUART_BAUD_M10(baseAddr, enable); -} - -/*! - * @brief Gets the configuration of bit10 (if enabled) or bit9 (if disabled) as the - * parity bit in the serial transmission. - * - * @param baseAddr LPUART base address - * @return Configuration of bit10 (enabled (1)), or bit 9 (disabled (0)) as the - * parity bit in the serial transmission - */ -static inline bool LPUART_HAL_IsBit10SetAsParityBit(uint32_t baseAddr) -{ - /* to see if the parity bit is set as the tenth data bit, */ - /* return value of LPUARTx_BAUD[M10] */ - return BR_LPUART_BAUD_M10(baseAddr); -} - -/*! - * @brief Checks whether the current data word was received with noise. - * - * @param baseAddr LPUART base address. - * @return The status of the NOISY bit in the LPUART extended data register - */ -static inline bool LPUART_HAL_IsCurrentDatawordReceivedWithNoise(uint32_t baseAddr) -{ - /* to see if the current dataword was received with noise, */ - /* return value of LPUARTx_DATA[NOISY] */ - return BR_LPUART_DATA_NOISY(baseAddr); -} - -/*! - * @brief Checks whether the receive buffer is empty. - * - * @param baseAddr LPUART base address - * @return TRUE if the receive-buffer is empty. - */ -static inline bool LPUART_HAL_IsReceiveBufferEmpty(uint32_t baseAddr) -{ - /* to see if the current state of data buffer is empty, */ - /* return value of LPUARTx_DATA[RXEMPT] */ - return BR_LPUART_DATA_RXEMPT(baseAddr); -} - -/*! - * @brief Checks whether the previous BUS state was idle before this byte is received. - * - * @param baseAddr LPUART base address - * @return TRUE if the previous BUS state was IDLE. - */ -static inline bool LPUART_HAL_ItWasPreviousBusStateIdle(uint32_t baseAddr) -{ - /* to see if the current dataword was received with parity error, */ - /* return value of LPUARTx_DATA[PARITYE] */ - return BR_LPUART_DATA_IDLINE(baseAddr); -} - -/*! - * @brief Checks whether the current data word was received with parity error. - * - * @param baseAddr LPUART base address - * @return The status of the PARITYE bit in the LPUART extended data register - */ -static inline bool LPUART_HAL_IsCurrentDatawordReceivedWithParityError(uint32_t baseAddr) -{ - /* to see if the current dataword was received with parity error, */ - /* return value of LPUARTx_DATA[PARITYE] */ - return BR_LPUART_DATA_PARITYE(baseAddr); -} -#endif /* FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS */ - -/*@}*/ - -/*! - * @name LPUART Special Feature Configurations - * @{ - */ - -/*! - * @brief Configures the LPUART operation in wait mode (operates or stops operations in wait mode). - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address - * @param mode LPUART wait mode operation - operates or stops to operate in wait mode. - */ -static inline void LPUART_HAL_SetWaitModeOperation(uint32_t baseAddr, lpuart_operation_config_t mode) -{ - /* configure lpuart operation in wait mode */ - /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */ - BW_LPUART_CTRL_DOZEEN(baseAddr, mode); -} - -/*! - * @brief Gets the LPUART operation in wait mode (operates or stops operations in wait mode). - * - * @param baseAddr LPUART base address - * @return LPUART wait mode operation configuration - kLpuartOperates or KLpuartStops in wait mode - */ -lpuart_operation_config_t LPUART_HAL_GetWaitModeOperationConfig(uint32_t baseAddr); - -/*! - * @brief Configures the LPUART loopback operation (enable/disable loopback operation) - * - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address - * @param enable LPUART loopback mode - disabled (0) or enabled (1) - */ -void LPUART_HAL_SedLoopbackCmd(uint32_t baseAddr, bool enable); - -/*! - * @brief Configures the LPUART single-wire operation (enable/disable single-wire mode) - * - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address - * @param enable LPUART loopback mode - disabled (0) or enabled (1) - */ -void LPUART_HAL_SetSingleWireCmd(uint32_t baseAddr, bool enable); - -/*! - * @brief Configures the LPUART transmit direction while in single-wire mode. - * - * @param baseAddr LPUART base address - * @param direction LPUART single-wire transmit direction - input or output - */ -static inline void LPUART_HAL_ConfigureTxdirInSinglewireMode(uint32_t baseAddr, - lpuart_singlewire_txdir_t direction) -{ - /* configure LPUART transmit direction (input or output) when in single-wire mode */ - /* it is assumed LPUART is in single-wire mode */ - BW_LPUART_CTRL_TXDIR(baseAddr, direction); -} - -/*! - * @brief Places the LPUART receiver in standby mode. - * - * In some LPUART instances, - * before placing LPUART in standby mode, first determine whether the receiver is set to - * wake on idle or whether it is already in idle state. - * NOTE that the RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently - * not idle. - * This can be determined by the S2[RAF] flag. If it is set to wake up an IDLE event and the channel is - * already idle, it is possible that the LPUART will discard data since data must be received - * (or a LIN break detect) after an IDLE is detected and before IDLE is allowed to reasserted. - * - * @param baseAddr LPUART base address - * @return Error code or kStatus_Success - */ -lpuart_status_t LPUART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr); - -/*! - * @brief Places the LPUART receiver in a normal mode (disable standby mode operation). - * - * @param baseAddr LPUART base address - */ -static inline void LPUART_HAL_PutReceiverInNormalMode(uint32_t baseAddr) -{ - /* clear the RWU bit to place receiver into normal mode (disable standby mode) */ - BW_LPUART_CTRL_RWU(baseAddr, 0); -} - -/*! - * @brief Checks whether the LPUART receiver is in a standby mode. - * - * @param baseAddr LPUART base address - * @return LPUART in normal more (0) or standby (1) - */ -static inline bool LPUART_HAL_IsReceiverInStandby(uint32_t baseAddr) -{ - /* return the RWU bit setting (0 - normal more, 1 - standby) */ - return BR_LPUART_CTRL_RWU(baseAddr); -} - -/*! - * @brief LPUART receiver wakeup method (idle line or addr-mark) from standby mode - * - * @param baseAddr LPUART base address - * @param method LPUART wakeup method: 0 - Idle-line wake (default), 1 - addr-mark wake - */ -static inline void LPUART_HAL_SelectReceiverWakeupMethod(uint32_t baseAddr, lpuart_wakeup_method_t method) -{ - /* configure the WAKE bit for idle line wake or address mark wake */ - BW_LPUART_CTRL_WAKE(baseAddr, method); -} - -/*! - * @brief Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode. - * - * @param baseAddr LPUART base address - * @return LPUART wakeup method: kLpuartIdleLineWake: 0 - Idle-line wake (default), - * kLpuartAddrMarkWake: 1 - addr-mark wake - */ -lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr); - -/*! - * @brief LPUART idle-line detect operation configuration (idle line bit-count start and wake - * up affect on IDLE status bit). - * - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address - * @param config LPUART configuration data for idle line detect operation - */ -void LPUART_HAL_ConfigureIdleLineDetect(uint32_t baseAddr, - const lpuart_idle_line_config_t *config); - -/*! - * @brief LPUART break character transmit length configuration - * In some LPUART instances, the user should disable the transmitter before calling - * this function. Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address - * @param length LPUART break character length setting: 0 - minimum 10-bit times (default), - * 1 - minimum 13-bit times - */ -static inline void LPUART_HAL_SetBreakCharTransmitLength(uint32_t baseAddr, - lpuart_break_char_length_t length) -{ - /* Configure BRK13 - Break Character transmit length configuration */ - /* LPUART break character length setting: */ - /* 0 - minimum 10-bit times (default), */ - /* 1 - minimum 13-bit times */ - BW_LPUART_STAT_BRK13(baseAddr, length); -} - -/*! - * @brief LPUART break character detect length configuration - * - * @param baseAddr LPUART base address - * @param length LPUART break character length setting: 0 - minimum 10-bit times (default), - * 1 - minimum 13-bit times - */ -static inline void LPUART_HAL_SetBreakCharDetectLength(uint32_t baseAddr, - lpuart_break_char_length_t length) -{ - /* Configure LBKDE - Break Character detect length configuration */ - /* LPUART break character length setting: */ - /* 0 - minimum 10-bit times (default), */ - /* 1 - minimum 13-bit times */ - BW_LPUART_STAT_LBKDE(baseAddr, length); -} - -/*! - * @brief LPUART transmit sends break character configuration. - * - * @param baseAddr LPUART base address - * @param enable LPUART normal/queue break char - disabled (normal mode, default: 0) or - * enabled (queue break char: 1) - */ -static inline void LPUART_HAL_QueueBreakCharToSend(uint32_t baseAddr, bool enable) -{ - /* Configure SBK - Send Break */ - /* LPUART send break character setting: */ - /* 0 - normal transmitter operation, */ - /* 1 - Queue break character(s) to be sent */ - - BW_LPUART_CTRL_SBK(baseAddr, enable); -} - -/*! - * @brief LPUART configures match address mode control (Note: Feature available on - * select LPUART instances) - * - * @param baseAddr LPUART base address - * @param matchAddrMode1 MAEN1: match address mode1 enable (1)/disable (0) - * @param matchAddrMode2 MAEN2: match address mode2 enable (1)/disable (0) - * @param matchAddrValue1 MA: match address value to program into match address register 1 - * @param matchAddrValue2 MA: match address value to program into match address register 2 - * @param config MATCFG: Configures the match addressing mode used. - * @return An error code or kStatus_Success - */ -lpuart_status_t LPUART_HAL_SetMatchAddressOperation(uint32_t baseAddr, - bool matchAddrMode1, bool matchAddrMode2, - uint8_t matchAddrValue1, uint8_t matchAddrValue2, - lpuart_match_config_t config); - -/*! - * @brief LPUART sends the MSB first configuration (Note: Feature available on select LPUART instances) - * In some LPUART instances, the user should disable the transmitter/receiver - * before calling this function. - * Generally, this may be applied to all LPUARTs to ensure safe operation. - * - * @param baseAddr LPUART base address - * @param enable MSB first mode configuration, MSBF: 0 - LSB (default, feature disabled), - * 1 - MSB (feature enabled) - */ -static inline void LPUART_HAL_ConfigureSendMsbFirstOperation(uint32_t baseAddr, bool enable) -{ - BW_LPUART_STAT_MSBF(baseAddr, enable); -} - -/*! - * @brief LPUART disables re-sync of received data configuration (Note: Feature available on - * select LPUART instances). - * - * @param baseAddr LPUART base address - * @param enable disable re-sync of received data word configuration, RESYNCDIS: - * 0 - re-sync of received data word (default, feature disabled), - * 1 - disable the re-sync (feature enabled) - */ -static inline void LPUART_HAL_ConfigureReceiveResyncDisableOperation(uint32_t baseAddr, bool enable) -{ - /* When set, disables the resynchronization of the received data word when a data */ - /* one followed by data zero transition is detected. This bit should only be changed */ - /* when the receiver is disabled. */ - BW_LPUART_BAUD_RESYNCDIS(baseAddr, enable); -} - -#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT -/*! - * @brief Transmits the CTS source configuration. - * - * @param baseAddr LPUART base address - * @param source LPUART CTS source - */ -static inline void LPUART_HAL_SelectSourceCts(uint32_t baseAddr, lpuart_cts_source_t source) -{ - /* Set TXCTSSRC */ - BW_LPUART_MODIR_TXCTSSRC(baseAddr, source); -} - -/*! - * @brief Transmits the CTS configuration. - * Note: configures if the CTS state is checked at the start of each character or only when the transmitter is idle. - * - * @param baseAddr LPUART base address - * @param config LPUART CTS configuration - */ -static inline void LPUART_HAL_ConfigureCts(uint32_t baseAddr, lpuart_cts_config_t config) -{ - /* Set TXCTSC */ - BW_LPUART_MODIR_TXCTSC(baseAddr, config); -} - -/*! - * @brief Enables the receiver request-to-send. - * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE). - * - * @param baseAddr LPUART base address - * @param enable disable(0)/enable(1) receiver RTS. - */ - -static inline void LPUART_HAL_SetReceiverRts(uint32_t baseAddr, bool enable) -{ - BW_LPUART_MODIR_RXRTSE(baseAddr, enable); -} - -/*! - * @brief Enables the transmitter request-to-send. - * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE). - * - * @param baseAddr LPUART base address - * @param enable disable(0)/enable(1) transmitter RTS. - */ -static inline void LPUART_HAL_SetTransmitterRtsCmd(uint32_t baseAddr, bool enable) -{ - BW_LPUART_MODIR_TXRTSE(baseAddr, enable); -} - -/*! - * @brief Configures the transmitter RTS polarity: 0=active low, 1=active high. - * - * @param baseAddr LPUART base address - * @param polarity Settings to choose RTS polarity. - */ -static inline void LPUART_HAL_SetTransmitterRtsPolarityMode(uint32_t baseAddr, bool polarity) -{ - /* Configure the transmitter rts polarity: 0=active low, 1=active high */ - BW_LPUART_MODIR_TXRTSPOL(baseAddr, polarity); -} - -/*! - * @brief Enables the transmitter clear-to-send. - * - * @param baseAddr LPUART base address - * @param enable disable(0)/enable(1) transmitter CTS. - */ -static inline void LPUART_HAL_SetTransmitterCtsCmd(uint32_t baseAddr, bool enable) -{ - BW_LPUART_MODIR_TXCTSE(baseAddr, enable); -} - -#endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */ - -#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT -/*! - * @brief Configures the LPUART infrared operation. - * - * @param baseAddr LPUART base address - * @param enable Enable (1) or disable (0) the infrared operation - * @param pulseWidth The transmit narrow pulse width of type lpuart_ir_tx_pulsewidth_t - */ -void LPUART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable, - lpuart_ir_tx_pulsewidth_t pulseWidth); -#endif /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */ - -/*@}*/ - -/*! - * @name LPUART Status Flags - * @{ - */ - -/*! - * @brief LPUART get status flag - * - * @param baseAddr LPUART base address - * @param statusFlag The status flag to query - */ -bool LPUART_HAL_GetStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag); - -/*! - * @brief Gets the LPUART Transmit data register empty flag. - * - * This function returns the state of the LPUART Transmit data register empty flag. - * - * @param baseAddr LPUART module base address. - * @return The status of Transmit data register empty flag, which is set when transmit buffer - * is empty. - */ -static inline bool LPUART_HAL_IsTxDataRegEmpty(uint32_t baseAddr) -{ - /* return status condition of TDRE flag */ - return BR_LPUART_STAT_TDRE(baseAddr); -} - -/*! - * @brief Gets the LPUART receive data register full flag. - * - * @param baseAddr LPUART base address - * @return Status of the receive data register full flag, sets when the receive data buffer is full. - */ -static inline bool LPUART_HAL_IsRxDataRegFull(uint32_t baseAddr) -{ - /* return status condition of RDRF flag */ - return BR_LPUART_STAT_RDRF(baseAddr); -} - -/*! - * @brief Gets the LPUART transmission complete flag. - * - * @param baseAddr LPUART base address - * @return Status of Transmission complete flag, sets when transmitter is idle - * (transmission activity complete) - */ -static inline bool LPUART_HAL_IsTxComplete(uint32_t baseAddr) -{ - /* return status condition of TC flag */ - return BR_LPUART_STAT_TC(baseAddr); -} - -/*! - * @brief LPUART clears an individual status flag (see lpuart_status_flag_t for list of status bits). - * - * @param baseAddr LPUART base address - * @param statusFlag Desired LPUART status flag to clear - * @return An error code or kStatus_Success - */ -lpuart_status_t LPUART_HAL_ClearStatusFlag(uint32_t baseAddr, lpuart_status_flag_t statusFlag); - -/*! - * @brief LPUART clears ALL status flags. - * - * @param baseAddr LPUART base address - */ -void LPUART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* MBED_NO_LPUART */ - -#endif /* __FSL_LPUART_HAL_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h deleted file mode 100644 index d3c591148d7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h +++ /dev/null @@ -1,705 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_MCG_FEATURES_H__) -#define __FSL_MCG_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (1) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (0) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (0) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (1) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (1) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (1) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (0) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (0) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ - defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (1) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (1) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (1) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (1) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (1) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (1) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (1) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (0) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (1) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (0) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (0) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (0) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (0) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (0) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (0) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (0) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (0) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (0) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (0) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (0) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (0) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1) -#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ - defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ - defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (0) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (0) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (1) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (1) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ - #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) - /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ - #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ - #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) - /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ - #define FSL_FEATURE_MCG_HAS_RTC_32K (0) - /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_PLL1 (0) - /* @brief Has 48MHz internal oscillator. */ - #define FSL_FEATURE_MCG_HAS_IRC_48M (0) - /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ - #define FSL_FEATURE_MCG_HAS_OSC1 (0) - /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ - #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) - /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ - #define FSL_FEATURE_MCG_HAS_LOLRE (1) - /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ - #define FSL_FEATURE_MCG_USE_OSCSEL (0) - /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ - #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) - /* @brief TBD */ - #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) - /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL (1) - /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ - #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) - /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ - #define FSL_FEATURE_MCG_HAS_FLL (1) - /* @brief Has PLL external to MCG (register C9). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) - /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ - #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) - /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) - /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ - #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) - /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ - #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) - /* @brief Has external clock monitor (register bit C6[CME]). */ - #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) - /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ - #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) - /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ - #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_MCG_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c deleted file mode 100644 index 36c08c3246f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_mcg_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetFllRefclk - * Description : Internal function to find the fll reference clock - * This is an internal function to get the fll reference clock. The returned - * value will be used for other APIs to calculate teh fll and other clock value. - * - *END**************************************************************************/ -uint32_t CLOCK_HAL_GetFllRefClk(uint32_t baseAddr) -{ - uint32_t mcgffclk; - uint8_t divider; - - if (CLOCK_HAL_GetInternalRefSelMode(baseAddr) == kMcgInternalRefClkSrcExternal) - { - /* External reference clock is selected */ -#if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for ffclk */ - - int32_t oscsel = CLOCK_HAL_GetOscselMode(baseAddr); - if (oscsel == kMcgOscselOsc) - { -#if FSL_FEATURE_MCG_HAS_OSC1 - /* System oscillator 0 drives MCG clock */ - mcgffclk = CPU_XTAL0_CLK_HZ; -#else - /* System oscillator 0 drives MCG clock */ - mcgffclk = CPU_XTAL_CLK_HZ; -#endif - } - else if (oscsel == kMcgOscselRtc) - { - /* RTC 32 kHz oscillator drives MCG clock */ - mcgffclk = CPU_XTAL32k_CLK_HZ; - } -#if FSL_FEATURE_MCG_HAS_IRC_48M /* case 1.1: if IRC 48M exists*/ - else if (oscsel == kMcgOscselIrc) - { - /* IRC 48Mhz oscillator drives MCG clock */ - mcgffclk = CPU_INT_IRC_CLK_HZ; - } -#endif - else - { - mcgffclk = 0; - } - -#else /* case 2: use default osc0*/ - - /* System oscillator 0 drives MCG clock */ - mcgffclk = CPU_XTAL_CLK_HZ; - -#endif - - divider = (uint8_t)(1u << CLOCK_HAL_GetFllExternalRefDivider(baseAddr)); - - /* Calculate the divided FLL reference clock*/ - mcgffclk = (mcgffclk / divider); - - if ((CLOCK_HAL_GetRange0Mode(baseAddr) != kMcgFreqRangeSelLow) -#if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for ffclk */ - && (CLOCK_HAL_GetOscselMode(baseAddr) != kMcgOscselRtc)) -#else - ) -#endif - { - /* If high range is enabled, additional 32 divider is active*/ - mcgffclk = (mcgffclk >> kMcgConstant5); - } - } - else - { - /* The slow internal reference clock is selected */ - mcgffclk = CPU_INT_SLOW_CLK_HZ; - } - return mcgffclk; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetFllclk - * Description : Get the current mcg fll clock - * This function will return the mcgfllclk value in frequency(hz) based on - * current mcg configurations and settings. Fll should be properly configured - * in order to get the valid value. - * - *END**************************************************************************/ -uint32_t CLOCK_HAL_GetFllClk(uint32_t baseAddr) -{ - uint32_t mcgfllclk; - mcg_dmx32_select_t dmx32; - mcg_digital_controlled_osc_range_select_t drstDrs; - - mcgfllclk = CLOCK_HAL_GetFllRefClk(baseAddr); - - /* Select correct multiplier to calculate the MCG output clock */ - dmx32 = CLOCK_HAL_GetDmx32(baseAddr); - drstDrs = CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr); - - switch (drstDrs) - { - case kMcgDigitalControlledOscRangeSelLow: /* Low frequency range */ - switch (dmx32) - { - case kMcgDmx32Default: /* DCO has a default range of 25% */ - mcgfllclk *= kMcgConstant640; - break; - case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */ - mcgfllclk *= kMcgConstant732; - break; - default: - break; - } - break; - case kMcgDigitalControlledOscRangeSelMid: /* Mid frequency range*/ - switch (dmx32) - { - case kMcgDmx32Default: /* DCO has a default range of 25% */ - mcgfllclk *= kMcgConstant1280; - break; - case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */ - mcgfllclk *= kMcgConstant1464; - break; - default: - break; - } - break; - case kMcgDigitalControlledOscRangeSelMidHigh: /* Mid-High frequency range */ - switch (dmx32) - { - case kMcgDmx32Default: /* DCO has a default range of 25% */ - mcgfllclk *= kMcgConstant1920; - break; - case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */ - mcgfllclk *= kMcgConstant2197; - break; - default: - break; - } - break; - case kMcgDigitalControlledOscRangeSelHigh: /* High frequency range */ - switch (dmx32) - { - case kMcgDmx32Default: /* DCO has a default range of 25% */ - mcgfllclk *= kMcgConstant2560; - break; - case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */ - mcgfllclk *= kMcgConstant2929; - break; - default: - break; - } - break; - default: - break; - } - - return mcgfllclk; -} -#if FSL_FEATURE_MCG_HAS_PLL -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetPll0clk - * Description : Get the current mcg pll/pll0 clock - * This function will return the mcgpllclk/mcgpll0 value in frequency(hz) based - * on current mcg configurations and settings. PLL/PLL0 should be properly - * configured in order to get the valid value. - * - *END**************************************************************************/ -uint32_t CLOCK_HAL_GetPll0Clk(uint32_t baseAddr) -{ - uint32_t mcgpll0clk; - uint8_t divider; - - /* PLL(0) output is selected*/ -#if FSL_FEATURE_MCG_USE_PLLREFSEL /* case 1 use pllrefsel to select pll*/ - - if (CLOCK_HAL_GetPllRefSel0Mode(baseAddr) != kMcgPllExternalRefClkSelOsc0) - { - /* OSC1 clock source used as an external reference clock */ - mcgpll0clk = CPU_XTAL1_CLK_HZ; - } - else - { - /* OSC0 clock source used as an external reference clock*/ - mcgpll0clk = CPU_XTAL0_CLK_HZ; - } -#else -#if FSL_FEATURE_MCG_USE_OSCSEL /* case 2: use oscsel for pll */ - mcg_oscsel_select_t oscsel = CLOCK_HAL_GetOscselMode(baseAddr); - if (oscsel == kMcgOscselOsc) /* case 2.1: OSC0 */ - { - /* System oscillator drives MCG clock*/ - mcgpll0clk = CPU_XTAL_CLK_HZ; - } - else if (oscsel == kMcgOscselRtc) /* case 2.2: RTC */ - { - /* RTC 32 kHz oscillator drives MCG clock*/ - mcgpll0clk = CPU_XTAL32k_CLK_HZ; - } -#if FSL_FEATURE_MCG_HAS_IRC_48M - else if (oscsel == kMcgOscselIrc) /* case 2.3: IRC 48M */ - { - /* IRC 48Mhz oscillator drives MCG clock*/ - mcgpll0clk = CPU_INT_IRC_CLK_HZ; - } - else - { - mcgpll0clk = 0; - } -#endif -#else /* case 3: use default osc0*/ - /* System oscillator drives MCG clock*/ - mcgpll0clk = CPU_XTAL_CLK_HZ; -#endif -#endif - - divider = (kMcgConstant1 + CLOCK_HAL_GetPllExternalRefDivider0(baseAddr)); - - /* Calculate the PLL reference clock*/ - mcgpll0clk /= divider; - divider = (CLOCK_HAL_GetVoltCtrlOscDivider0(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE); - - /* Calculate the MCG output clock*/ - mcgpll0clk = (mcgpll0clk * divider); - - return mcgpll0clk; -} -#endif - -#if FSL_FEATURE_MCG_HAS_PLL1 -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetPll1Clk - * Description : Get the current mcg pll1 clock - * This function will return the mcgpll1clk value in frequency(hz) based - * on current mcg configurations and settings. PLL1 should be properly configured - * in order to get the valid value. - * - *END**************************************************************************/ -uint32_t CLOCK_HAL_GetPll1Clk(uint32_t baseAddr) -{ - uint32_t mcgpll1clk; - uint8_t divider; - - if (CLOCK_HAL_GetPllRefSel1Mode(baseAddr) != kMcgPllExternalRefClkSelOsc0) - { - /* OSC1 clock source used as an external reference clock*/ - mcgpll1clk = CPU_XTAL1_CLK_HZ; - } - else - { - /* OSC0 clock source used as an external reference clock*/ - mcgpll1clk = CPU_XTAL0_CLK_HZ; - } - - divider = (kMcgConstant1 + CLOCK_HAL_GetPllExternalRefDivider1(baseAddr)); - - /* Calculate the PLL reference clock*/ - mcgpll1clk /= divider; - divider = (CLOCK_HAL_GetVoltCtrlOscDivider1(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE); - - /* Calculate the MCG output clock*/ - mcgpll1clk = ((mcgpll1clk * divider) >> kMcgConstant1); /* divided by 2*/ - return mcgpll1clk; -} -#endif - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetIrclk - * Description : Get the current mcg ir clock - * This function will return the mcgirclk value in frequency(hz) based - * on current mcg configurations and settings. It will not check if the - * mcgirclk is enabled or not, just calculate and return the value. - * - *END**************************************************************************/ -uint32_t CLOCK_HAL_GetInternalRefClk(uint32_t baseAddr) -{ - int32_t mcgirclk; - if (CLOCK_HAL_GetInternalRefClkSelMode(baseAddr) == kMcgInternalRefClkSelSlow) - { - /* Slow internal reference clock selected*/ - mcgirclk = CPU_INT_SLOW_CLK_HZ; - } - else - { - mcgirclk = CPU_INT_FAST_CLK_HZ / (1 << CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr)); - } - return mcgirclk; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetOutclk - * Description : Get the current mcg out clock - * This function will return the mcgoutclk value in frequency(hz) based on - * current mcg configurations and settings. The configuration should be - * properly done in order to get the valid value. - * - *END**************************************************************************/ -uint32_t CLOCK_HAL_GetOutClk(uint32_t baseAddr) -{ - /* Variable to store output clock frequency of the MCG module*/ - uint32_t mcgoutclk = 0; - - if (CLOCK_HAL_GetClkSrcMode(baseAddr) == kMcgClkSelOut) - { -#if FSL_FEATURE_MCG_HAS_PLL - /* Output of FLL or PLL is selected*/ - if (CLOCK_HAL_GetPllSelMode(baseAddr) == kMcgPllSelFll) - { - /* FLL is selected*/ - mcgoutclk = CLOCK_HAL_GetFllClk(baseAddr); - } - else - { - /* PLL is selected*/ -#if FSL_FEATURE_MCG_HAS_PLL1 - if (CLOCK_HAL_GetPllClkSelMode(baseAddr) != kMcgPllClkSelPll0) - { - /* PLL1 output is selected*/ - mcgoutclk = CLOCK_HAL_GetPll1Clk(baseAddr); - } - else - { - mcgoutclk = CLOCK_HAL_GetPll0Clk(baseAddr); - } -#else - mcgoutclk = CLOCK_HAL_GetPll0Clk(baseAddr); -#endif // FSL_FEATURE_MCG_HAS_PLL1 - } -#else - mcgoutclk = CLOCK_HAL_GetFllClk(baseAddr); -#endif // FSL_FEATURE_MCG_HAS_PLL - } - else if (CLOCK_HAL_GetClkSrcMode(baseAddr) == kMcgClkSelInternal) - { - /* Internal reference clock is selected*/ - mcgoutclk = CLOCK_HAL_GetInternalRefClk(baseAddr); - } - else if (CLOCK_HAL_GetClkSrcMode(baseAddr) == kMcgClkSelExternal) - { - /* External reference clock is selected*/ - -#if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for outclock */ - - uint32_t oscsel = CLOCK_HAL_GetOscselMode(baseAddr); - if (oscsel == kMcgOscselOsc) - { -#if FSL_FEATURE_MCG_HAS_OSC1 - /* System oscillator drives MCG clock*/ - mcgoutclk = CPU_XTAL0_CLK_HZ; -#else - /* System oscillator drives MCG clock*/ - mcgoutclk = CPU_XTAL_CLK_HZ; -#endif - } - else if (oscsel == kMcgOscselRtc) - { - /* RTC 32 kHz oscillator drives MCG clock*/ - mcgoutclk = CPU_XTAL32k_CLK_HZ; - } -#if FSL_FEATURE_MCG_HAS_IRC_48M /* case 1.1: IRC 48M exists*/ - else if (oscsel == kMcgOscselIrc) - { - /* IRC 48Mhz oscillator drives MCG clock*/ - mcgoutclk = CPU_INT_IRC_CLK_HZ; - } - else - { - mcgoutclk = 0; - } -#endif - -#else /* case 2: use default osc0*/ - /* System oscillator drives MCG clock*/ - mcgoutclk = CPU_XTAL_CLK_HZ; -#endif - } - else - { - /* Reserved value*/ - return mcgoutclk; - } - return mcgoutclk; -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h deleted file mode 100644 index 2fd76fd200a..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h +++ /dev/null @@ -1,2184 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_MCG_HAL_H__) -#define __FSL_MCG_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_mcg_features.h" - -/*! @addtogroup mcg_hal*/ -/*! @{*/ - -/*! @file fsl_mcg_hal.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief MCG constant definitions*/ -enum _mcg_constant -{ - kMcgConstant0 = (0u), - kMcgConstant1 = (1u), - kMcgConstant2 = (2u), - kMcgConstant3 = (3u), - kMcgConstant4 = (4u), - kMcgConstant5 = (5u), - kMcgConstant32 = (32u), - - kMcgConstant640 = (640u), - kMcgConstant1280 = (1280u), - kMcgConstant1920 = (1920u), - kMcgConstant2560 = (2560u), - kMcgConstant732 = (732u), - kMcgConstant1464 = (1464u), - kMcgConstant2197 = (2197u), - kMcgConstant2929 = (2929u), - - kMcgConstantHex20 = (0x20u), - kMcgConstantHex40 = (0x40u), - kMcgConstantHex60 = (0x60u), - kMcgConstantHex80 = (0x80u), - kMcgConstantHexA0 = (0xA0u), - kMcgConstantHexC0 = (0xC0u), - kMcgConstantHexE0 = (0xE0u), - - kMcgConstant2000 = (2000u), - kMcgConstant3000 = (3000u), - kMcgConstant4000 = (4000u), - - kMcgConstant10000 = (10000u), - kMcgConstant30000 = (30000u), - kMcgConstant31250 = (31250u), - kMcgConstant39063 = (39063u), - kMcgConstant40000 = (40000u), - - kMcgConstant1250000 = (1250000u), - kMcgConstant2500000 = (2500000u), - kMcgConstant3000000 = (3000000u), - kMcgConstant5000000 = (5000000u), - kMcgConstant8000000 = (8000000u), - - kMcgConstant10000000 = (10000000u), - kMcgConstant20000000 = (20000000u), - kMcgConstant25000000 = (25000000u), - kMcgConstant32000000 = (32000000u), - kMcgConstant40000000 = (40000000u), - kMcgConstant50000000 = (50000000u), - kMcgConstant60000000 = (60000000u), - kMcgConstant75000000 = (75000000u), - kMcgConstant80000000 = (80000000u), - - kMcgConstant100000000 = (100000000u), - kMcgConstant180000000 = (180000000u), - kMcgConstant360000000 = (360000000u) -}; - -/*! @brief MCG clock source select */ -typedef enum _mcg_clock_select -{ - kMcgClkSelOut, /* Output of FLL or PLLCS is selected(depends on PLLS bit) */ - kMcgClkSelInternal, /* Internal reference clock is selected */ - kMcgClkSelExternal, /* External reference clock is selected */ - kMcgClkSelReserved -} mcg_clock_select_t; - -/*! @brief MCG internal reference clock source select */ -typedef enum _mcg_internal_ref_clock_source -{ - kMcgInternalRefClkSrcExternal, /* External reference clock is selected */ - kMcgInternalRefClkSrcSlow /* The slow internal reference clock is selected */ -} mcg_internal_ref_clock_source_t; - -/*! @brief MCG frequency range select */ -typedef enum _mcg_freq_range_select -{ - kMcgFreqRangeSelLow, /* Low frequency range selected for the crystal OSC */ - kMcgFreqRangeSelHigh, /* High frequency range selected for the crystal OSC */ - kMcgFreqRangeSelVeryHigh, /* Very High frequency range selected for the crystal OSC */ - kMcgFreqRangeSelVeryHigh1 /* Very High frequency range selected for the crystal OSC */ -} mcg_freq_range_select_t; - -/*! @brief MCG high gain oscillator select */ -typedef enum _mcg_high_gain_osc_select -{ - kMcgHighGainOscSelLow, /* Configure crystal oscillator for low-power operation */ - kMcgHighGainOscSelHigh /* Configure crystal oscillator for high-gain operation */ -} mcg_high_gain_osc_select_t; - -/*! @brief MCG high gain oscillator select */ -typedef enum _mcg_external_ref_clock_select -{ - kMcgExternalRefClkSelExternal, /* External reference clock requested */ - kMcgExternalRefClkSelOsc /* Oscillator requested */ -} mcg_external_ref_clock_select_t; - -/*! @brief MCG low power select */ -typedef enum _mcg_low_power_select -{ - kMcgLowPowerSelNormal, /* FLL (or PLL) is not disabled in bypass modes */ - kMcgLowPowerSelLowPower /* FLL (or PLL) is disabled in bypass modes (lower power) */ -} mcg_low_power_select_t; - -/*! @brief MCG internal reference clock select */ -typedef enum _mcg_internal_ref_clock_select -{ - kMcgInternalRefClkSelSlow, /* Slow internal reference clock selected */ - kMcgInternalRefClkSelFast /* Fast internal reference clock selected */ -} mcg_internal_ref_clock_select_t; - -/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ -typedef enum _mcg_dmx32_select -{ - kMcgDmx32Default, /* DCO has a default range of 25% */ - kMcgDmx32Fine /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ -} mcg_dmx32_select_t; - -/*! @brief MCG DCO range select */ -typedef enum _mcg_digital_controlled_osc_range_select -{ - kMcgDigitalControlledOscRangeSelLow, /* Low frequency range */ - kMcgDigitalControlledOscRangeSelMid, /* Mid frequency range*/ - kMcgDigitalControlledOscRangeSelMidHigh, /* Mid-High frequency range */ - kMcgDigitalControlledOscRangeSelHigh /* High frequency range */ -} mcg_digital_controlled_osc_range_select_t; - -/*! @brief MCG PLL external reference clock select */ -typedef enum _mcg_pll_external_ref_clk_select -{ - kMcgPllExternalRefClkSelOsc0, /* Selects OSC0 clock source as its external reference clock */ - kMcgPllExternalRefClkSelOsc1 /* Selects OSC1 clock source as its external reference clock */ -} mcg_pll_external_ref_clk_select_t; - -/*! @brief MCG PLL select */ -typedef enum _mcg_pll_select -{ - kMcgPllSelFll, /* FLL is selected */ - kMcgPllSelPllClkSel /* PLLCS output clock is selected */ -} mcg_pll_select_t; - -/*! @brief MCG loss of lock status */ -typedef enum _mcg_loss_of_lock_status -{ - kMcgLossOfLockNotLost, /* PLL has not lost lock since LOLS 0 was last cleared */ - kMcgLossOfLockLost /* PLL has lost lock since LOLS 0 was last cleared */ -} mcg_loss_of_lock_status_t; - -/*! @brief MCG lock status */ -typedef enum _mcg_lock_status -{ - kMcgLockUnlocked, /* PLL is currently unlocked */ - kMcgLockLocked /* PLL is currently locked */ -} mcg_lock_status_t; - -/*! @brief MCG clock status */ -typedef enum _mcg_pll_stat_status -{ - kMcgPllStatFll, /* Source of PLLS clock is FLL clock */ - kMcgPllStatPllClkSel /* Source of PLLS clock is PLLCS output clock */ -} mcg_pll_stat_status_t; - -/*! @brief MCG iref status */ -typedef enum _mcg_internal_ref_status -{ - kMcgInternalRefStatExternal, /* FLL reference clock is the external reference clock */ - kMcgInternalRefStatInternal /* FLL reference clock is the internal reference clock */ -} mcg_internal_ref_status_t; - -/*! @brief MCG clock mode status */ -typedef enum _mcg_clk_stat_status -{ - kMcgClkStatFll, /* Output of the FLL is selected (reset default) */ - kMcgClkStatInternalRef, /* Internal reference clock is selected */ - kMcgClkStatExternalRef, /* External reference clock is selected */ - kMcgClkStatPll /* Output of the PLL is selected */ -} mcg_clk_stat_status_t; - -/*! @brief MCG ircst status */ -typedef enum _mcg_internal_ref_clk_status -{ - kMcgInternalRefClkStatSlow, /* internal reference clock is the slow clock (32 kHz IRC) */ - kMcgInternalRefClkStatFast /* internal reference clock is the fast clock (2 MHz IRC) */ -} mcg_internal_ref_clk_status_t; - -/*! @brief MCG auto trim fail status */ -typedef enum _mcg_auto_trim_machine_fail_status -{ - kMcgAutoTrimMachineNormal, /* Automatic Trim Machine completed normally */ - kMcgAutoTrimMachineFail /* Automatic Trim Machine failed */ -} mcg_auto_trim_machine_fail_status_t; - -/*! @brief MCG loss of clock status */ -typedef enum _mcg_locs0_status -{ - kMcgLocs0NotOccured, /* Loss of OSC0 has not occurred */ - kMcgLocs0Occured /* Loss of OSC0 has occurred */ -} mcg_locs0_status_t; - -/*! @brief MCG Automatic Trim Machine Select */ -typedef enum _mcg_auto_trim_machine_select -{ - kMcgAutoTrimMachineSel32k, /* 32 kHz Internal Reference Clock selected */ - kMcgAutoTrimMachineSel4m /* 4 MHz Internal Reference Clock selected */ -} mcg_auto_trim_machine_select_t; - -/*! @brief MCG OSC Clock Select */ -typedef enum _mcg_oscsel_select -{ - kMcgOscselOsc, /* Selects System Oscillator (OSCCLK) */ - kMcgOscselRtc, /* Selects 32 kHz RTC Oscillator */ -#if FSL_FEATURE_MCG_HAS_IRC_48M - kMcgOscselIrc /* Selects 48 MHz IRC Oscillator */ -#endif -} mcg_oscsel_select_t; - -/*! @brief MCG loss of clock status */ -typedef enum _mcg_loss_of_clk1_status -{ - kMcgLossOfClk1NotOccured, /* Loss of RTC has not occurred */ - kMcgLossOfClk1Occured /* Loss of RTC has occurred */ -} mcg_loss_of_clk1_status_t; - -/*! @brief MCG PLLCS select */ -typedef enum _mcg_pll_clk_select -{ - kMcgPllClkSelPll0, /* PLL0 output clock is selected */ - kMcgPllClkSelPll1, /* PLL1 output clock is selected */ -} mcg_pll_clk_select_t; - -/*! @brief MCG loss of clock status */ -typedef enum _mcg_locs2_status -{ - kMcgLocs2NotOccured, /* Loss of OSC1 has not occurred */ - kMcgLocs2Occured /* Loss of OSC1 has occurred */ -} mcg_locs2_status_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name MCG out clock access API*/ -/*@{*/ - -/*! - * @brief Gets the current MCG FLL clock. - * - * This function returns the mcgfllclk value in frequency(Hertz) based on the - * current MCG configurations and settings. FLL should be properly configured - * in order to get the valid value. - * - * @param baseAddr Base address for current MCG instance. - * @return value Frequency value in Hertz of the mcgpllclk. - */ -uint32_t CLOCK_HAL_GetFllRefClk(uint32_t baseAddr); - -/*! - * @brief Gets the current MCG FLL clock. - * - * This function returns the mcgfllclk value in frequency(Hertz) based on the - * current MCG configurations and settings. FLL should be properly configured - * in order to get the valid value. - * - * @param baseAddr Base address for current MCG instance. - * @return value Frequency value in Hertz of the mcgpllclk. - */ -uint32_t CLOCK_HAL_GetFllClk(uint32_t baseAddr); - -/*! - * @brief Gets the current MCG PLL/PLL0 clock. - * - * This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based - * on the current MCG configurations and settings. PLL/PLL0 should be properly - * configured in order to get the valid value. - * - * @param baseAddr Base address for current MCG instance. - * @return value Frequency value in Hertz of the mcgpllclk or the mcgpll0clk. - */ -uint32_t CLOCK_HAL_GetPll0Clk(uint32_t baseAddr); - -#if FSL_FEATURE_MCG_HAS_PLL1 -/*! - * @brief Gets the current MCG PLL1 clock. - * - * This function returns the mcgpll1clk value in frequency (Hertz) based - * on the current MCG configurations and settings. PLL1 should be properly configured - * in order to get the valid value. - * - * @param baseAddr Base address for current MCG instance. - * @return value Frequency value in Hertz of mcgpll1clk. - */ -uint32_t CLOCK_HAL_GetPll1Clk(uint32_t baseAddr); -#endif - -/*! - * @brief Gets the current MCG IR clock. - * - * This function returns the mcgirclk value in frequency (Hertz) based - * on the current MCG configurations and settings. It does not check if the - * mcgirclk is enabled or not, just calculate and return the value. - * - * @param baseAddr Base address for current MCG instance. - * @return value Frequency value in Hertz of the mcgirclk. - */ -uint32_t CLOCK_HAL_GetInternalRefClk(uint32_t baseAddr); - -/*! - * @brief Gets the current MCG out clock. - * - * This function returns the mcgoutclk value in frequency (Hertz) based on the - * current MCG configurations and settings. The configuration should be - * properly done in order to get the valid value. - * - * @param baseAddr Base address for current MCG instance. - * @return value Frequency value in Hertz of mcgoutclk. - */ -uint32_t CLOCK_HAL_GetOutClk(uint32_t baseAddr); - -/*@}*/ - -/*! @name MCG control register access API*/ -/*@{*/ - -/*! - * @brief Sets the Clock Source Select - * - * This function selects the clock source for the MCGOUTCLK. - * - * @param baseAddr Base address for current MCG instance. - * @param select Clock source selection - * - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit) - * - 01: Internal reference clock is selected. - * - 10: External reference clock is selected. - * - 11: Reserved. - */ -static inline void CLOCK_HAL_SetClkSrcMode(uint32_t baseAddr, mcg_clock_select_t select) -{ - BW_MCG_C1_CLKS(baseAddr, select); -} - -/*! - * @brief Gets the Clock Source Select. - * - * This function gets the select of the clock source for the MCGOUTCLK. - * - * @param baseAddr Base address for current MCG instance. - * @return select Clock source selection - */ -static inline mcg_clock_select_t CLOCK_HAL_GetClkSrcMode(uint32_t baseAddr) -{ - return (mcg_clock_select_t)BR_MCG_C1_CLKS(baseAddr); -} - -/*! - * @brief Sets the FLL External Reference Divider. - * - * This function sets the FLL External Reference Divider. - * - * @param baseAddr Base address for current MCG instance. - * @param setting Divider setting - */ -static inline void CLOCK_HAL_SetFllExternalRefDivider(uint32_t baseAddr, - uint8_t setting) -{ - BW_MCG_C1_FRDIV(baseAddr, setting); -} - -/*! - * @brief Gets the FLL External Reference Divider. - * - * This function gets the FLL External Reference Divider. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Divider setting - */ -static inline uint8_t CLOCK_HAL_GetFllExternalRefDivider(uint32_t baseAddr) -{ - return BR_MCG_C1_FRDIV(baseAddr); -} - -/*! - * @brief Sets the Internal Reference Select. - * - * This function selects the reference clock source for the FLL. - * - * @param baseAddr Base address for current MCG instance. - * @param select Clock source select - * - 0: External reference clock is selected - * - 1: The slow internal reference clock is selected - */ -static inline void CLOCK_HAL_SetInternalRefSelMode(uint32_t baseAddr, - mcg_internal_ref_clock_source_t select) -{ - BW_MCG_C1_IREFS(baseAddr, select); -} - -/*! - * @brief Gets the Internal Reference Select - * - * This function gets the reference clock source for the FLL. - * - * @param baseAddr Base address for current MCG instance. - * @return select Clock source select - */ -static inline mcg_internal_ref_clock_source_t CLOCK_HAL_GetInternalRefSelMode(uint32_t baseAddr) -{ - return (mcg_internal_ref_clock_source_t)BR_MCG_C1_IREFS(baseAddr); -} - -/*! - * @brief Sets the CLKS, FRDIV and IREFS at the same time. - * - * This function sets the CLKS, FRDIV, and IREFS settings at the same time - * in order keep the integrity of the clock switching. - * - * @param baseAddr Base address for current MCG instance. - * @param clks Clock source select - * @param frdiv FLL external reference divider select - * @param irefs Internal reference select - */ -static inline void CLOCK_HAL_SetClksFrdivInternalRefSelect(uint32_t baseAddr, - mcg_clock_select_t clks, - uint8_t frdiv, - mcg_internal_ref_clock_source_t irefs) -{ - /* Set the required CLKS , FRDIV and IREFS values */ - HW_MCG_C1_WR(baseAddr, (HW_MCG_C1_RD(baseAddr) & ~(BM_MCG_C1_CLKS | BM_MCG_C1_FRDIV | BM_MCG_C1_IREFS)) - | (BF_MCG_C1_CLKS(clks) | BF_MCG_C1_FRDIV(frdiv) | BF_MCG_C1_IREFS(irefs))); -} - -/*! - * @brief Sets the Enable Internal Reference Clock setting. - * - * This function enables/disables the internal reference clock to use as the MCGIRCLK. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Enable or disable internal reference clock. - * - true: MCGIRCLK active - * - false: MCGIRCLK inactive - */ -static inline void CLOCK_HAL_SetInternalClkCmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C1_IRCLKEN(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the enable Internal Reference Clock setting. - * - * This function gets the reference clock enable setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if the internal reference clock is enabled. - */ -static inline bool CLOCK_HAL_GetInternalClkCmd(uint32_t baseAddr) -{ - return BR_MCG_C1_IRCLKEN(baseAddr); -} - -/*! - * @brief Sets the Internal Reference Clock Stop Enable setting. - * - * This function controls whether or not the internal reference clock remains - * enabled when the MCG enters Stop mode. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Enable or disable the internal reference clock stop setting. - * - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set - * or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. - * - false: Internal reference clock is disabled in Stop mode - */ -static inline void CLOCK_HAL_SetInternalRefStopCmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C1_IREFSTEN(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Enable Internal Reference Clock setting. - * - * This function gets the Internal Reference Clock Stop Enable setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if internal reference clock stop is enabled. - */ -static inline bool CLOCK_HAL_GetInternalRefStopCmd(uint32_t baseAddr) -{ - return BR_MCG_C1_IREFSTEN(baseAddr); -} - -/*! - * @brief Sets the Loss of Clock Reset Enable setting. - * - * This function determines whether an interrupt or a reset request is made following a loss - * of the OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Loss of Clock Reset Enable setting - * - true: Generate a reset request on a loss of OSC0 external reference clock - * - false: Interrupt request is generated on a loss of OSC0 external reference clock - */ -static inline void CLOCK_HAL_SetLossOfClkReset0Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C2_LOCRE0(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Loss of Clock Reset Enable setting. - * - * This function gets the Loss of Clock Reset Enable setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if Loss of Clock Reset is enabled. - */ -static inline bool CLOCK_HAL_GetLossOfClkReset0Cmd(uint32_t baseAddr) -{ - return BR_MCG_C2_LOCRE0(baseAddr); -} - -#if FSL_FEATURE_MCG_HAS_FCFTRIM -/*! - * @brief Sets the Fast Internal Reference Clock Fine Trim setting. - * - * This function sets the Fast Internal Reference Clock Fine Trim setting. FCFTRIM - * controls the smallest adjustment of the fast internal reference clock frequency. - * Setting the FCFTRIM increases the period and clearing FCFTRIM decreases the period - * by the smallest amount possible. If an FCFTRIM value is stored and non-volatile - * memory is to be used, it is the user's responsibility to copy that value from the - * non-volatile memory location to this bit. - * - * @param baseAddr Base address for current MCG instance. - * @params setting Fast Internal Reference Clock Fine Trim setting - */ -static inline void CLOCK_HAL_SetFastInternalRefClkFineTrim(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C2_FCFTRIM(baseAddr, setting); -} - -/*! - * @brief Gets the Fast Internal Reference Clock Fine Trim setting. - * - * This function gets the Fast Internal Reference Clock Fine Trim setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Fast Internal Reference Clock Fine Trim setting - */ -static inline uint8_t CLOCK_HAL_GetFastInternalRefClkFineTrim(uint32_t baseAddr) -{ - return BR_MCG_C2_FCFTRIM(baseAddr); -} -#endif /* FSL_FEATURE_MCG_HAS_FCFTRIM */ - -/*! - * @brief Sets the Frequency Range Select. - * - * This function selects the frequency range for the crystal oscillator or an external - * clock source. See the Oscillator (OSC) chapter for more details and the device - * data sheet for the frequency ranges used. - * - * @param baseAddr Base address for current MCG instance. - * @params select Frequency Range Select - * - 00: Low frequency range selected for the crystal oscillator - * - 01: High frequency range selected for the crystal oscillator - * - 1X: Very high frequency range selected for the crystal oscillator - */ -static inline void CLOCK_HAL_SetRange0Mode(uint32_t baseAddr, mcg_freq_range_select_t select) -{ - BW_MCG_C2_RANGE(baseAddr, select); -} - -/*! - * @brief Gets the Frequency Range Select. - * - * This function gets the Frequency Range Select. - * - * @param baseAddr Base address for current MCG instance. - * @return select Frequency Range Select - */ -static inline mcg_freq_range_select_t CLOCK_HAL_GetRange0Mode(uint32_t baseAddr) -{ - return (mcg_freq_range_select_t)BR_MCG_C2_RANGE(baseAddr); -} - -/*! - * @brief Sets the High Gain Oscillator Select. - * - * This function controls the crystal oscillator mode of operation. See the - * Oscillator (OSC) chapter for more details. - * - * @param baseAddr Base address for current MCG instance. - * @params select High Gain Oscillator Select. - * - 0: Configure crystal oscillator for low-power operation - * - 1: Configure crystal oscillator for high-gain operation - */ -static inline void CLOCK_HAL_SetHighGainOsc0Mode(uint32_t baseAddr, mcg_high_gain_osc_select_t select) -{ - BW_MCG_C2_HGO(baseAddr, select); -} - -/*! - * @brief Gets the High Gain Oscillator Select. - * - * This function gets the High Gain Oscillator Select. - * - * @param baseAddr Base address for current MCG instance. - * @return select High Gain Oscillator Select - */ -static inline mcg_high_gain_osc_select_t CLOCK_HAL_GetHighGainOsc0Mode(uint32_t baseAddr) -{ - return (mcg_high_gain_osc_select_t)BR_MCG_C2_HGO(baseAddr); -} - -/*! - * @brief Sets the External Reference Select. - * - * This function selects the source for the external reference clock. - * See the Oscillator (OSC) chapter for more details. - * - * @param baseAddr Base address for current MCG instance. - * @params select External Reference Select - * - 0: External reference clock requested - * - 1: Oscillator requested - */ -static inline void CLOCK_HAL_SetExternalRefSel0Mode(uint32_t baseAddr, mcg_external_ref_clock_select_t select) -{ - BW_MCG_C2_EREFS(baseAddr, select); -} - -/*! - * @brief Gets the External Reference Select. - * - * This function gets the External Reference Select. - * - * @param baseAddr Base address for current MCG instance. - * @return select External Reference Select - */ -static inline mcg_external_ref_clock_select_t CLOCK_HAL_GetExternalRefSel0Mode(uint32_t baseAddr) -{ - return (mcg_external_ref_clock_select_t)BR_MCG_C2_EREFS(baseAddr); -} - -/*! - * @brief Sets the Low Power Select. - * - * This function controls whether the FLL (or PLL) is disabled in the BLPI and the - * BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG - * into the BLPE mode; in the FBI mode, setting this bit to 1 transitions the MCG into - * the BLPI mode. In any other MCG mode, the LP bit has no affect.. - * - * @param baseAddr Base address for current MCG instance. - * @params select Low Power Select - * - 0: FLL (or PLL) is not disabled in bypass modes - * - 1: FLL (or PLL) is disabled in bypass modes (lower power) - */ -static inline void CLOCK_HAL_SetLowPowerMode(uint32_t baseAddr, mcg_low_power_select_t select) -{ - BW_MCG_C2_LP(baseAddr, select); -} - -/*! - * @brief Gets the Low Power Select. - * - * This function gets the Low Power Select. - * - * @param baseAddr Base address for current MCG instance. - * @return select Low Power Select - */ -static inline mcg_low_power_select_t CLOCK_HAL_GetLowPowerMode(uint32_t baseAddr) -{ - return (mcg_low_power_select_t)BR_MCG_C2_LP(baseAddr); -} - -/*! - * @brief Sets the Internal Reference Clock Select. - * - * This function selects between the fast or slow internal reference clock source. - * - * @param baseAddr Base address for current MCG instance. - * @params select Low Power Select - * - 0: Slow internal reference clock selected. - * - 1: Fast internal reference clock selected. - */ -static inline void CLOCK_HAL_SetInternalRefClkSelMode(uint32_t baseAddr, - mcg_internal_ref_clock_select_t select) -{ - BW_MCG_C2_IRCS(baseAddr, select); -} - -/*! - * @brief Gets the Internal Reference Clock Select. - * - * This function gets the Internal Reference Clock Select. - * - * @param baseAddr Base address for current MCG instance. - * @return select Internal Reference Clock Select - */ -static inline mcg_internal_ref_clock_select_t CLOCK_HAL_GetInternalRefClkSelMode(uint32_t baseAddr) -{ - return (mcg_internal_ref_clock_select_t)BR_MCG_C2_IRCS(baseAddr); -} - -/*! - * @brief Sets the Slow Internal Reference Clock Trim Setting. - * - * This function controls the slow internal reference clock frequency by - * controlling the slow internal reference clock period. The SCTRIM bits are - * binary weighted (that is, bit 1 adjusts twice as much as bit 0). - * Increasing the binary value increases the period, and decreasing the value - * decreases the period. - * An additional fine trim bit is available in the C4 register as the SCFTRIM bit. - * Upon reset, this value is loaded with a factory trim value. - * If an SCTRIM value stored in non-volatile memory is to be used, it is the user's - * responsibility to copy that value from the non-volatile memory location to - * this register. - * - * @param baseAddr Base address for current MCG instance. - * @params setting Slow Internal Reference Clock Trim Setting - */ -static inline void CLOCK_HAL_SetSlowInternalRefClkTrim(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C3_SCTRIM(baseAddr, setting); -} - -/*! - * @brief Gets the Slow Internal Reference Clock Trim Setting. - * - * This function gets the Slow Internal Reference Clock Trim Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Slow Internal Reference Clock Trim Setting - */ -static inline uint8_t CLOCK_HAL_GetSlowInternalRefClkTrim(uint32_t baseAddr) -{ - return BR_MCG_C3_SCTRIM(baseAddr); -} - -/*! - * @brief Sets the DCO Maximum Frequency with 32.768 kHz Reference. - * - * This function controls whether or not the DCO frequency range - * is narrowed to its maximum frequency with a 32.768 kHz reference. - * - * @param baseAddr Base address for current MCG instance. - * @params setting DCO Maximum Frequency with 32.768 kHz Reference Setting - * - 0: DCO has a default range of 25%. - * - 1: DCO is fine-tuned for maximum frequency with 32.768 kHz reference. - */ -static inline void CLOCK_HAL_SetDmx32(uint32_t baseAddr, mcg_dmx32_select_t setting) -{ - BW_MCG_C4_DMX32(baseAddr, setting); -} - -/*! - * @brief Gets the DCO Maximum Frequency with the 32.768 kHz Reference Setting. - * - * This function gets the DCO Maximum Frequency with 32.768 kHz Reference Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting DCO Maximum Frequency with 32.768 kHz Reference Setting - */ -static inline mcg_dmx32_select_t CLOCK_HAL_GetDmx32(uint32_t baseAddr) -{ - return (mcg_dmx32_select_t)BR_MCG_C4_DMX32(baseAddr); -} - -/*! - * @brief Sets the DCO Range Select. - * - * This function selects the frequency range for the FLL output, DCOOUT. - * When the LP bit is set, the writes to the DRS bits are ignored. The DRST read - * field indicates the current frequency range for the DCOOUT. The DRST field does - * not update immediately after a write to the DRS field due to internal - * synchronization between the clock domains. See the DCO Frequency Range table - * for more details. - * - * @param baseAddr Base address for current MCG instance. - * @params setting DCO Range Select Setting - * - 00: Low range (reset default). - * - 01: Mid range. - * - 10: Mid-high range. - * - 11: High range. - */ -static inline void CLOCK_HAL_SetDigitalControlledOscRangeMode(uint32_t baseAddr, - mcg_digital_controlled_osc_range_select_t setting) -{ - BW_MCG_C4_DRST_DRS(baseAddr, setting); -} - -/*! - * @brief Gets the DCO Range Select Setting. - * - * This function gets the DCO Range Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting DCO Range Select Setting - */ -static inline mcg_digital_controlled_osc_range_select_t CLOCK_HAL_GetDigitalControlledOscRangeMode(uint32_t baseAddr) -{ - return (mcg_digital_controlled_osc_range_select_t)BR_MCG_C4_DRST_DRS(baseAddr); -} - -/*! - * @brief Sets the Fast Internal Reference Clock Trim Setting. - * - * This function controls the fast internal reference clock frequency - * by controlling the fast internal reference clock period. The FCTRIM - * bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). - * Increasing the binary value increases the period, and decreasing the - * value decreases the period. - * If an FCTRIM[3:0] value stored in non-volatile memory is to be used, it is - * the user's responsibility to copy that value from the non-volatile memory location - * to this register. - * - * @param baseAddr Base address for current MCG instance. - * @params setting Fast Internal Reference Clock Trim Setting. - */ -static inline void CLOCK_HAL_SetFastInternalRefClkTrim(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C4_FCTRIM(baseAddr, setting); -} - -/*! - * @brief Gets the Fast Internal Reference Clock Trim Setting. - * - * This function gets the Fast Internal Reference Clock Trim Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Fast Internal Reference Clock Trim Setting - */ -static inline uint8_t CLOCK_HAL_GetFastInternalRefClkTrim(uint32_t baseAddr) -{ - return BR_MCG_C4_FCTRIM(baseAddr); -} - -/*! - * @brief Sets the Slow Internal Reference Clock Fine Trim Setting. - * - * This function controls the smallest adjustment of the slow internal - * reference clock frequency. Setting the SCFTRIM increases the period and - * clearing the SCFTRIM decreases the period by the smallest amount possible. - * If an SCFTRIM value, stored in non-volatile memory, is to be used, it is - * the user's responsibility to copy that value from the non-volatile memory - * location to this bit. - * - * @param baseAddr Base address for current MCG instance. - * @params setting Slow Internal Reference Clock Fine Trim Setting - */ -static inline void CLOCK_HAL_SetSlowInternalRefClkFineTrim(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C4_SCFTRIM(baseAddr, setting); -} - -/*! - * @brief Gets the Slow Internal Reference Clock Fine Trim Setting. - * - * This function gets the Slow Internal Reference Clock Fine Trim Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Slow Internal Reference Clock Fine Trim Setting - */ -static inline uint8_t CLOCK_HAL_GetSlowInternalRefClkFineTrim(uint32_t baseAddr) -{ - return BR_MCG_C4_SCFTRIM(baseAddr); -} - -#if FSL_FEATURE_MCG_USE_PLLREFSEL -/*! - * @brief Sets the PLL0 External Reference Select Setting. - * - * This function selects the PLL0 external reference clock source. - * - * @param baseAddr Base address for current MCG instance. - * @params setting PLL0 External Reference Select Setting - * - 0: Selects OSC0 clock source as its external reference clock - * - 1: Selects OSC1 clock source as its external reference clock - */ -static inline void CLOCK_HAL_SetPllRefSel0Mode(uint32_t baseAddr, - mcg_pll_external_ref_clk_select_t setting) -{ - BW_MCG_C5_PLLREFSEL0(baseAddr, setting); -} - -/*! - * @brief Gets the PLL0 External Reference Select Setting. - * - * This function gets the PLL0 External Reference Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting PLL0 External Reference Select Setting - */ -static inline mcg_pll_external_ref_clk_select_t CLOCK_HAL_GetPllRefSel0Mode(uint32_t baseAddr) -{ - return (mcg_pll_external_ref_clk_select_t)BR_MCG_C5_PLLREFSEL0(baseAddr); -} -#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */ - -#if FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR - -/*! - * @brief Sets the Clock Monitor Enable Setting. - * - * This function enables/disables the loss of clock monitoring circuit for - * the OSC0 external reference mux select. The LOCRE0 bit determines whether an - * interrupt or a reset request is generated following a loss of the OSC0 indication. - * The CME0 bit should only be set to a logic 1 when the MCG is in an operational - * mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the - * CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register - * should not be changed. CME0 bit should be set to a logic 0 before the MCG - * enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. - * CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes - * if the MCG is in BLPE mode. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Clock Monitor Enable Setting - * - true: External clock monitor is enabled for OSC0. - * - false: External clock monitor is disabled for OSC0. - */ -static inline void CLOCK_HAL_SetClkMonitor0Cmd(uint32_t baseAddr, bool enable) -{ -#if FSL_FEATURE_MCG_HAS_PLL - BW_MCG_C6_CME0(baseAddr, enable ? 1 : 0); -#else - BW_MCG_C6_CME(baseAddr, enable ? 1 : 0); -#endif -} - -/*! - * @brief Gets the Clock Monitor Enable Setting. - * - * This function gets the Clock Monitor Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if Clock Monitor is enabled - */ -static inline bool CLOCK_HAL_GetClkMonitor0Cmd(uint32_t baseAddr) -{ -#if FSL_FEATURE_MCG_HAS_PLL - return BR_MCG_C6_CME0(baseAddr); -#else - return BR_MCG_C6_CME(baseAddr); -#endif -} - -#endif - -#if FSL_FEATURE_MCG_HAS_PLL -/*! - * @brief Sets the PLL Clock Enable Setting. - * - * This function enables/disables the PLL0 independent of the PLLS and enables the PLL0 - * clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to - * the correct divider to generate a PLL1 reference clock in a valid reference range - * prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external - * oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being - * enabled with the PLLCLKEN0 bit, and the external oscillator is being used - * as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable PLL Clock Enable Setting - * - true: MCGPLL0CLK and MCGPLL0CLK2X are active - * - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive - */ -static inline void CLOCK_HAL_SetPllClk0Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C5_PLLCLKEN0(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the PLL Clock Enable Setting. - * - * This function gets the PLL Clock Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if PLL0 PLL Clock is enabled. - */ -static inline bool CLOCK_HAL_GetPllClk0Cmd(uint32_t baseAddr) -{ - return BR_MCG_C5_PLLCLKEN0(baseAddr); -} - -/*! - * @brief Sets the PLL0 Stop Enable Setting. - * - * This function enables/disables the PLL0 Clock during a Normal Stop (In Low - * Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other - * power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock - * to run if it is written to 1. - * - * @param baseAddr Base address for current MCG instance. - * @params enable PLL0 Stop Enable Setting - * - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in - * Normal Stop mode. - * - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the - * Stop modes. - */ -static inline void CLOCK_HAL_SetPllStat0Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C5_PLLSTEN0(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the PLL0 Stop Enable Setting. - * - * This function gets the PLL0 Stop Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if the PLL0 Stop is enabled. - */ -static inline bool CLOCK_HAL_GetPllStat0Cmd(uint32_t baseAddr) -{ - return BR_MCG_C5_PLLSTEN0(baseAddr); -} - -/*! - * @brief Sets the PLL0 External Reference Divider Setting. - * - * This function selects the amount to divide down the external reference - * clock for the PLL0. The resulting frequency must be in a valid reference - * range. After the PLL0 is enabled, (by setting either PLLCLKEN0 or PLLS), the - * PRDIV0 value must not be changed when LOCK0 is zero. - * - * @param baseAddr Base address for current MCG instance. - * @params setting PLL0 External Reference Divider Setting - */ -static inline void CLOCK_HAL_SetPllExternalRefDivider0(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C5_PRDIV0(baseAddr, setting); -} - -/*! - * @brief Gets the PLL0 External Reference Divider Setting. - * - * This function gets the PLL0 External Reference Divider Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting PLL0 External Reference Divider Setting - */ -static inline uint8_t CLOCK_HAL_GetPllExternalRefDivider0(uint32_t baseAddr) -{ - return BR_MCG_C5_PRDIV0(baseAddr); -} - -/*! - * @brief Sets the Loss of Lock Interrupt Enable Setting. - * - * This function determine whether an interrupt request is made following a loss - * of lock indication. This bit only has an effect when LOLS 0 is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Loss of Lock Interrupt Enable Setting - * - true: Generate an interrupt request on loss of lock. - * - false: No interrupt request is generated on loss of lock. - */ -static inline void CLOCK_HAL_SetLossOfClkInt0Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C6_LOLIE0(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Loss of the Lock Interrupt Enable Setting. - * - * This function gets the Loss of the Lock Interrupt Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if the Loss of Lock Interrupt is enabled. - */ -static inline bool CLOCK_HAL_GetLossOfClkInt0Cmd(uint32_t baseAddr) -{ - return BR_MCG_C6_LOLIE0(baseAddr); -} - -/*! - * @brief Sets the PLL Select Setting. - * - * This function controls whether the PLLCS or FLL output is selected as the - * MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN0 and - * PLLCLKEN1 is not set, the PLLCS output clock is disabled in all modes. If the - * PLLS is set, the FLL is disabled in all modes. - * - * @param baseAddr Base address for current MCG instance. - * @params setting PLL Select Setting - * - 0: FLL is selected. - * - 1: PLLCS output clock is selected (PRDIV0 bits of PLL in - * control need to be programmed to the correct divider to - * generate a PLL reference clock in the range of 1 - 32 MHz - * prior to setting the PLLS bit). - */ -static inline void CLOCK_HAL_SetPllSelMode(uint32_t baseAddr, mcg_pll_select_t setting) -{ - BW_MCG_C6_PLLS(baseAddr, setting); -} - -/*! - * @brief Gets the PLL Select Setting. - * - * This function gets the PLL Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting PLL Select Setting - */ -static inline mcg_pll_select_t CLOCK_HAL_GetPllSelMode(uint32_t baseAddr) -{ - return (mcg_pll_select_t)BR_MCG_C6_PLLS(baseAddr); -} - -/*! - * @brief Sets the VCO0 Divider Setting. - * - * This function selects the amount to divide the VCO output of the PLL0. - * The VDIV0 bits establish the multiplication factor (M) applied to the - * reference clock frequency. After the PLL0 is enabled (by setting either - * PLLCLKEN0 or PLLS), the VDIV0 value must not be changed when LOCK0 is zero. - * - * @param baseAddr Base address for current MCG instance. - * @params setting VCO0 Divider Setting - */ -static inline void CLOCK_HAL_SetVoltCtrlOscDivider0(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C6_VDIV0(baseAddr, setting); -} - -/*! - * @brief Gets the VCO0 Divider Setting. - * - * This function gets the VCO0 Divider Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting VCO0 Divider Setting - */ -static inline uint8_t CLOCK_HAL_GetVoltCtrlOscDivider0(uint32_t baseAddr) -{ - return BR_MCG_C6_VDIV0(baseAddr); -} - -/*! - * @brief Gets the Loss of the Lock Status. - * - * This function gets the Loss of Lock Status. This bit is a sticky bit indicating - * the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL - * output frequency has fallen outside the lock exit frequency tolerance, D unl . - * LOLIE 0 determines whether an interrupt request is made when LOLS 0 is set. - * This bit is cleared by reset or by writing a logic 1 to it when set. Writing a - * logic 0 to this bit has no effect. - * - * @param baseAddr Base address for current MCG instance. - * @return status Loss of Lock Status - * - 0: PLL has not lost lock since LOLS 0 was last cleared - * - 1: PLL has lost lock since LOLS 0 was last cleared - */ -static inline mcg_loss_of_lock_status_t CLOCK_HAL_GetLossOfLock0Mode(uint32_t baseAddr) -{ - return (mcg_loss_of_lock_status_t)BR_MCG_S_LOLS0(baseAddr); -} - -/*! - * @brief Gets the Lock Status. - * - * This function gets the Lock Status. This bit indicates whether the PLL0 has - * acquired the lock. Lock detection is disabled when not operating in either the PBE or the - * PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode. - * While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and - * MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock - * status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register - * or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear - * and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference - * clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS, - * VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear - * and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock. - * Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and - * MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted. - * - * @param baseAddr Base address for current MCG instance. - * @return status Lock Status - * - 0: PLL is currently unlocked - * - 1: PLL is currently locked - */ -static inline mcg_lock_status_t CLOCK_HAL_GetLock0Mode(uint32_t baseAddr) -{ - return (mcg_lock_status_t)BR_MCG_S_LOCK0(baseAddr); -} - -/*! - * @brief Gets the PLL Select Status. - * - * This function gets the PLL Select Status. This bit indicates the clock source - * selected by PLLS . The PLLST bit does not update immediately after a write to - * the PLLS bit due to the internal synchronization between the clock domains. - * - * @param baseAddr Base address for current MCG instance. - * @return status PLL Select Status - * - 0: Source of PLLS clock is FLL clock. - * - 1: Source of PLLS clock is PLLCS output clock. - */ -static inline mcg_pll_stat_status_t CLOCK_HAL_GetPllStatMode(uint32_t baseAddr) -{ - return (mcg_pll_stat_status_t)BR_MCG_S_PLLST(baseAddr); -} -#endif - -/*! - * @brief Gets the Internal Reference Status. - * - * This function gets the Internal Reference Status. This bit indicates the current - * source for the FLL reference clock. The IREFST bit does not update immediately - * after a write to the IREFS bit due to internal synchronization between the clock - * domains. - * - * @param baseAddr Base address for current MCG instance. - * @return status Internal Reference Status - * - 0: Source of FLL reference clock is the external reference clock. - * - 1: Source of FLL reference clock is the internal reference clock. - */ -static inline mcg_internal_ref_status_t CLOCK_HAL_GetInternalRefStatMode(uint32_t baseAddr) -{ - return (mcg_internal_ref_status_t)BR_MCG_S_IREFST(baseAddr); -} - -/*! - * @brief Gets the Clock Mode Status. - * - * This function gets the Clock Mode Status. These bits indicate the current clock mode. - * The CLKST bits do not update immediately after a write to the CLKS bits due to - * internal synchronization between clock domains. - * - * @param baseAddr Base address for current MCG instance. - * @return status Clock Mode Status - * - 00: Output of the FLL is selected (reset default). - * - 01: Internal reference clock is selected. - * - 10: External reference clock is selected. - * - 11: Output of the PLL is selected. - */ -static inline mcg_clk_stat_status_t CLOCK_HAL_GetClkStatMode(uint32_t baseAddr) -{ - return (mcg_clk_stat_status_t)BR_MCG_S_CLKST(baseAddr); -} - -/*! - * @brief Gets the OSC Initialization Status. - * - * This function gets the OSC Initialization Status. This bit, which resets to 0, is set - * to 1 after the initialization cycles of the crystal oscillator clock have completed. - * After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the - * OSC module's detailed description for more information. - * - * @param baseAddr Base address for current MCG instance. - * @return status OSC Initialization Status - */ -static inline uint8_t CLOCK_HAL_GetOscInit0(uint32_t baseAddr) -{ - return BR_MCG_S_OSCINIT0(baseAddr); -} - -/*! - * @brief Gets the Internal Reference Clock Status. - * - * This function gets the Internal Reference Clock Status. The IRCST bit indicates the - * current source for the internal reference clock select clock (IRCSCLK). The IRCST bit - * does not update immediately after a write to the IRCS bit due to the internal - * synchronization between clock domains. The IRCST bit is only updated if the - * internal reference clock is enabled, either by the MCG being in a mode that uses the - * IRC or by setting the C1[IRCLKEN] bit. - * - * @param baseAddr Base address for current MCG instance. - * @return status Internal Reference Clock Status - * - 0: Source of internal reference clock is the slow clock (32 kHz IRC). - * - 1: Source of internal reference clock is the fast clock (2 MHz IRC). - */ -static inline mcg_internal_ref_clk_status_t CLOCK_HAL_GetInternalRefClkStatMode(uint32_t baseAddr) -{ - return (mcg_internal_ref_clk_status_t)BR_MCG_S_IRCST(baseAddr); -} - -/*! - * @brief Gets the Automatic Trim machine Fail Flag. - * - * This function gets the Automatic Trim machine Fail Flag. This Fail flag for the - * Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is - * enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG - * enters into any Stop mode. A write to ATMF clears the flag. - * - * @param baseAddr Base address for current MCG instance. - * @return flag Automatic Trim machine Fail Flag - * - 0: Automatic Trim Machine completed normally. - * - 1: Automatic Trim Machine failed. - */ -static inline mcg_auto_trim_machine_fail_status_t CLOCK_HAL_GetAutoTrimMachineFailMode(uint32_t baseAddr) -{ - return (mcg_auto_trim_machine_fail_status_t)BR_MCG_SC_ATMF(baseAddr); -} - -/*! - * @brief Sets the Automatic Trim machine Fail Flag. - * - * This function clears the ATMF flag. - * - * @param baseAddr Base address for current MCG instance. - */ -static inline void CLOCK_HAL_SetAutoTrimMachineFail(uint32_t baseAddr) -{ - BW_MCG_SC_ATMF(baseAddr, 1); -} - -/*! - * @brief Gets the OSC0 Loss of Clock Status. - * - * This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of - * OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. - * This bit is cleared by writing a logic 1 to it when set. - * - * @param baseAddr Base address for current MCG instance. - * @return status OSC0 Loss of Clock Status - * - 0: Loss of OSC0 has not occurred. - * - 1: Loss of OSC0 has occurred. - */ -static inline mcg_locs0_status_t CLOCK_HAL_GetLocs0Mode(uint32_t baseAddr) -{ - return (mcg_locs0_status_t)BR_MCG_SC_LOCS0(baseAddr); -} - -/*! - * @brief Sets the Automatic Trim Machine Enable Setting. - * - * This function enables/disables the Auto Trim Machine to start automatically - * trimming the selected Internal Reference Clock. - * ATME de-asserts after the Auto Trim Machine has completed trimming all trim bits - * of the IRCS clock selected by the ATMS bit. - * Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto - * trim operation and clears this bit. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Automatic Trim Machine Enable Setting - * - true: Auto Trim Machine enabled - * - false: Auto Trim Machine disabled - */ -static inline void CLOCK_HAL_SetAutoTrimMachineCmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_SC_ATME(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Automatic Trim Machine Enable Setting. - * - * This function gets the Automatic Trim Machine Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if Automatic Trim Machine is enabled - */ -static inline bool CLOCK_HAL_GetAutoTrimMachineCmd(uint32_t baseAddr) -{ - return BR_MCG_SC_ATME(baseAddr); -} - -/*! - * @brief Sets the Automatic Trim Machine Select Setting. - * - * This function selects the IRCS clock for Auto Trim Test. - * - * @param baseAddr Base address for current MCG instance. - * @params setting Automatic Trim Machine Select Setting - * - 0: 32 kHz Internal Reference Clock selected - * - 1: 4 MHz Internal Reference Clock selected - */ -static inline void CLOCK_HAL_SetAutoTrimMachineSelMode(uint32_t baseAddr, - mcg_auto_trim_machine_select_t setting) -{ - BW_MCG_SC_ATMS(baseAddr, setting); -} - -/*! - * @brief Gets the Automatic Trim Machine Select Setting. - * - * This function gets the Automatic Trim Machine Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Automatic Trim Machine Select Setting - */ -static inline mcg_auto_trim_machine_select_t CLOCK_HAL_GetAutoTrimMachineSelMode(uint32_t baseAddr) -{ - return (mcg_auto_trim_machine_select_t)BR_MCG_SC_ATMS(baseAddr); -} - -/*! - * @brief Sets the FLL Filter Preserve Enable Setting. - * - * This function sets the FLL Filter Preserve Enable. This bit prevents the - * FLL filter values from resetting allowing the FLL output frequency to remain the - * same during the clock mode changes where the FLL/DCO output is still valid. - * (Note: This requires that the FLL reference frequency remain the same as - * the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency - * values change.) - * - * @param baseAddr Base address for current MCG instance. - * @params enable FLL Filter Preserve Enable Setting - * - true: FLL filter and FLL frequency retain their previous values - * during new clock mode change - * - false: FLL filter and FLL frequency will reset on changes to correct - * clock mode - */ -static inline void CLOCK_HAL_SetFllFilterPreserveCmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_SC_FLTPRSRV(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the FLL Filter Preserve Enable Setting. - * - * This function gets the FLL Filter Preserve Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if FLL Filter Preserve is enabled. - */ -static inline bool CLOCK_HAL_GetFllFilterPreserveCmd(uint32_t baseAddr) -{ - return BR_MCG_SC_FLTPRSRV(baseAddr); -} - -/*! - * @brief Sets the Fast Clock Internal Reference Divider Setting. - * - * This function selects the amount to divide down the fast internal reference - * clock. The resulting frequency is in the range 31.25 kHz to 4 MHz. - * (Note: Changing the divider when the Fast IRC is enabled is not supported). - * - * @param baseAddr Base address for current MCG instance. - * @params setting Fast Clock Internal Reference Divider Setting - */ -static inline void CLOCK_HAL_SetFastClkInternalRefDivider(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_SC_FCRDIV(baseAddr, setting); -} - -/*! - * @brief Gets the Fast Clock Internal Reference Divider Setting. - * - * This function gets the Fast Clock Internal Reference Divider Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Fast Clock Internal Reference Divider Setting - */ -static inline uint8_t CLOCK_HAL_GetFastClkInternalRefDivider(uint32_t baseAddr) -{ - return BR_MCG_SC_FCRDIV(baseAddr); -} - -/*! - * @brief Sets the ATM Compare Value High Setting. - * - * This function sets the ATM compare value high setting. The values are used by the - * Auto Trim Machine to compare and adjust the Internal Reference trim values during the ATM - * SAR conversion. - * - * @param baseAddr Base address for current MCG instance. - * @params setting ATM Compare Value High Setting - */ -static inline void CLOCK_HAL_SetAutoTrimMachineCompValHigh(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_ATCVH_ATCVH(baseAddr, setting); -} - -/*! - * @brief Gets the ATM Compare Value High Setting. - * - * This function gets the ATM Compare Value High Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting ATM Compare Value High Setting - */ -static inline uint8_t CLOCK_HAL_GetAutoTrimMachineCompValHigh(uint32_t baseAddr) -{ - return BR_MCG_ATCVH_ATCVH(baseAddr); -} - -/*! - * @brief Sets the ATM Compare Value Low Setting. - * - * This function sets the ATM compare value low setting. The values are used by the - * Auto Trim Machine to compare and adjust Internal Reference trim values during the ATM - * SAR conversion. - * - * @param baseAddr Base address for current MCG instance. - * @params setting ATM Compare Value Low Setting - */ -static inline void CLOCK_HAL_SetAutoTrimMachineCompValLow(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_ATCVL_ATCVL(baseAddr, setting); -} - -/*! - * @brief Gets the ATM Compare Value Low Setting. - * - * This function gets the ATM Compare Value Low Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting ATM Compare Value Low Setting - */ -static inline uint8_t CLOCK_HAL_GetAutoTrimMachineCompValLow(uint32_t baseAddr) -{ - return BR_MCG_ATCVL_ATCVL(baseAddr); -} - -#if FSL_FEATURE_MCG_USE_OSCSEL -/*! - * @brief Sets the MCG OSC Clock Select Setting. - * - * This function selects the MCG FLL external reference clock. - * - * @param baseAddr Base address for current MCG instance. - * @params setting MCG OSC Clock Select Setting - * - 0: Selects System Oscillator (OSCCLK). - * - 1: Selects 32 kHz RTC Oscillator. - */ -static inline void CLOCK_HAL_SetOscselMode(uint32_t baseAddr, mcg_oscsel_select_t setting) -{ - BW_MCG_C7_OSCSEL(baseAddr, setting); -} - -/*! - * @brief Gets the MCG OSC Clock Select Setting. - * - * This function gets the MCG OSC Clock Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting MCG OSC Clock Select Setting - */ -static inline mcg_oscsel_select_t CLOCK_HAL_GetOscselMode(uint32_t baseAddr) -{ - return (mcg_oscsel_select_t)BR_MCG_C7_OSCSEL(baseAddr); -} -#endif /* FSL_FEATURE_MCG_USE_OSCSEL */ - -#if FSL_FEATURE_MCG_HAS_LOLRE -/*! - * @brief Sets the PLL Loss of Lock Reset Enable Setting. - * - * This function determines whether an interrupt or a reset request is made - * following a PLL loss of lock. - * - * @param baseAddr Base address for current MCG instance. - * @params enable PLL Loss of Lock Reset Enable Setting - * - true: Generate a reset request on a PLL loss of lock indication. - * - false: Interrupt request is generated on a PLL loss of lock - * indication. The PLL loss of lock interrupt enable bit - * must also be set to generate the interrupt request. - */ -static inline void CLOCK_HAL_SetLossOfClkResetCmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C8_LOLRE(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the PLL Loss of Lock Reset Enable Setting. - * - * This function gets the PLL Loss of Lock Reset Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if the PLL Loss of Lock Reset is enabled. - */ -static inline bool CLOCK_HAL_GetLossOfClkResetCmd(uint32_t baseAddr) -{ - return BR_MCG_C8_LOLRE(baseAddr); -} -#endif /* FSL_FEATURE_MCG_HAS_LOLRE */ - - -#if FSL_FEATURE_MCG_HAS_RTC_32K -/*! - * @brief Sets the Loss of Clock Reset Enable Setting. - * - * This function determines whether an interrupt or a reset request is made following - * a loss of the RTC external reference clock. The LOCRE1 only has an affect when CME1 - * is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Loss of Clock Reset Enable Setting - * - true: Generate a reset request on a loss of RTC external reference clock. - * - false: Interrupt request is generated on a loss of RTC external - * reference clock. - */ -static inline void CLOCK_HAL_SetLossClkReset1Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C8_LOCRE1(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Loss of Clock Reset Enable Setting. - * - * This function gets the Loss of Clock Reset Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if Loss of Clock Reset is enabled. - */ -static inline bool CLOCK_HAL_GetLossClkReset1Cmd(uint32_t baseAddr) -{ - return BR_MCG_C8_LOCRE1(baseAddr); -} - -/*! - * @brief Sets the Clock Monitor Enable1 Setting. - * - * This function enables/disables the loss of the clock monitoring circuit for the - * output of the RTC external reference clock. The LOCRE1 bit determines whether an - * interrupt or a reset request is generated following a loss of the RTC clock indication. - * The CME1 bit should only be set to a logic 1 when the MCG is in an operational mode - * that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). CME1 bit must be set to - * a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur - * while in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or - * VLPW power modes if the MCG is in BLPE mode. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Clock Monitor Enable1 Setting - * - true: External clock monitor is enabled for RTC clock. - * - false: External clock monitor is disabled for RTC clock. - */ -static inline void CLOCK_HAL_SetClkMonitor1Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C8_CME1(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Clock Monitor Enable1 Setting. - * - * This function gets the Clock Monitor Enable1 Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if Clock Monitor Enable1 is enabled - */ -static inline bool CLOCK_HAL_GetClkMonitor1Cmd(uint32_t baseAddr) -{ - return BR_MCG_C8_CME1(baseAddr); -} - -/*! - * @brief Gets the RTC Loss of Clock Status. - * - * This function gets the RTC Loss of Clock Status. This bit indicates when a loss - * of clock has occurred. This bit is cleared by writing a logic 1 to it when set. - * - * @param baseAddr Base address for current MCG instance. - * @return status RTC Loss of Clock Status - * - 0: Loss of RTC has not occurred - * - 1: Loss of RTC has occurred - */ -static inline mcg_loss_of_clk1_status_t CLOCK_HAL_GetLossOfClk1Mode(uint32_t baseAddr) -{ - return (mcg_loss_of_clk1_status_t)BR_MCG_C8_LOCS1(baseAddr); -} -#endif /* FSL_FEATURE_MCG_HAS_RTC_32K */ - -#if FSL_FEATURE_MCG_USE_PLLREFSEL -/*! - * @brief Sets the OSC1 Loss of Clock Reset Enable Setting. - * - * This function determines whether an interrupt or reset request is made following - * a loss of OSC1 external reference clock. The LOCRE2 only has an affect when - * LOCS2 is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable OSC1 Loss of Clock Reset Enable Setting - * - true: Reset request is generated on a loss of OSC1 external - * reference clock.. - * - false: Interrupt request is generated on a loss of OSC1 external - * reference clock. - */ -static inline void CLOCK_HAL_SetLossClkReset2Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C10_LOCRE2(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the OSC1 Loss of the Clock Reset Enable Setting. - * - * This function gets the OSC1 Loss of Clock Reset Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if OSC1 Loss of Clock Reset is enabled. - */ -static inline bool CLOCK_HAL_GetLossClkReset2Cmd(uint32_t baseAddr) -{ - return BR_MCG_C10_LOCRE2(baseAddr); -} - -/*! - * @brief Sets the Frequency Range1 Select Setting. - * - * This function selects the frequency range for the OSC1 crystal oscillator - * or an external clock source. See the Oscillator chapter for more details and - * the device data sheet for the frequency ranges used. - * - * @param baseAddr Base address for current MCG instance. - * @params setting Frequency Range1 Select Setting - * - 00: Low frequency range selected for the crystal oscillator. - * - 01: High frequency range selected for the crystal oscillator. - * - 1X: Very high frequency range selected for the crystal oscillator. - */ -static inline void CLOCK_HAL_SetRange1Mode(uint32_t baseAddr, mcg_freq_range_select_t setting) -{ - BW_MCG_C10_RANGE1(baseAddr, setting); -} - -/*! - * @brief Gets the Frequency Range1 Select Setting. - * - * This function gets the Frequency Range1 Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting Frequency Range1 Select Setting - */ -static inline mcg_freq_range_select_t CLOCK_HAL_GetRange1Mode(uint32_t baseAddr) -{ - return (mcg_freq_range_select_t)BR_MCG_C10_RANGE1(baseAddr); -} - -/*! - * @brief Sets the High Gain Oscillator1 Select Setting. - * - * This function controls the OSC1 crystal oscillator mode of operation. - * See the Oscillator chapter for more details. - * - * @param baseAddr Base address for current MCG instance. - * @params setting High Gain Oscillator1 Select Setting - * - 0: Configure crystal oscillator for low-power operation. - * - 1: Configure crystal oscillator for high-gain operation. - */ -static inline void CLOCK_HAL_SetHighGainOsc1Mode(uint32_t baseAddr, - mcg_high_gain_osc_select_t setting) -{ - BW_MCG_C10_HGO1(baseAddr, setting); -} - -/*! - * @brief Gets the High Gain Oscillator1 Select Setting. - * - * This function gets the High Gain Oscillator1 Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting High Gain Oscillator1 Select Setting - */ -static inline mcg_high_gain_osc_select_t CLOCK_HAL_GetHighGainOsc1Mode(uint32_t baseAddr) -{ - return (mcg_high_gain_osc_select_t)BR_MCG_C10_HGO1(baseAddr); -} - -/*! - * @brief Sets the External Reference Select Setting. - * - * This function selects the source for the OSC1 external reference clock. - * See the Oscillator chapter for more details. - * - * @param baseAddr Base address for current MCG instance. - * @params setting External Reference Select Setting - * - 0: External reference clock requested. - * - 1: Oscillator requested. - */ -static inline void CLOCK_HAL_SetExternalRefSel1Mode(uint32_t baseAddr, - mcg_external_ref_clock_select_t setting) -{ - BW_MCG_C10_EREFS1(baseAddr, setting); -} - -/*! - * @brief Gets the External Reference Select Setting. - * - * This function gets the External Reference Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting External Reference Select Setting - */ -static inline mcg_external_ref_clock_select_t CLOCK_HAL_GetExternalRefSel1Mode(uint32_t baseAddr) -{ - return (mcg_external_ref_clock_select_t)BR_MCG_C10_EREFS1(baseAddr); -} - -/*! - * @brief Sets the PLL1 External Reference Select Setting. - * - * This function selects the PLL1 external reference clock source. - * - * @param baseAddr Base address for current MCG instance. - * @params setting PLL1 External Reference Select Setting - * - 0: Selects OSC0 clock source as its external reference clock. - * - 1: Selects OSC1 clock source as its external reference clock. - */ -static inline void CLOCK_HAL_SetPllRefSel1Mode(uint32_t baseAddr, - mcg_pll_external_ref_clk_select_t setting) -{ - BW_MCG_C11_PLLREFSEL1(baseAddr, setting); -} - -/*! - * @brief Gets the PLL1 External Reference Select Setting. - * - * This function gets the PLL1 External Reference Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting PLL1 External Reference Select Setting - */ -static inline mcg_pll_external_ref_clk_select_t CLOCK_HAL_GetPllRefSel1Mode(uint32_t baseAddr) -{ - return (mcg_pll_external_ref_clk_select_t)BR_MCG_C11_PLLREFSEL1(baseAddr); -} - -/*! - * @brief Sets the PLL1 Clock Enable Setting. - * - * This function enables/disables the PLL1 independent of PLLS and enables the - * PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs - * to be programmed to the correct divider to generate a PLL1 reference clock in a - * valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1 - * enables the PLL1 selected external oscillator if not already enabled. - * Whenever the PLL1 is enabled with the PLLCLKEN1 bit, and the - * external oscillator is used as the reference clock, the OSCINIT1 bit should - * be checked to make sure it is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable PLL1 Clock Enable Setting - * - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless - * MCG is in a bypass mode with LP=1 (BLPI or BLPE). - * - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive. - */ -static inline void CLOCK_HAL_SetPllClk1Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C11_PLLCLKEN1(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the PLL1 Clock Enable Setting. - * - * This function gets the PLL1 Clock Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if the PLL1 Clock is enabled. - */ -static inline bool CLOCK_HAL_GetPllClk1Cmd(uint32_t baseAddr) -{ - return BR_MCG_C11_PLLCLKEN1(baseAddr); -} - -/*! - * @brief Sets the PLL1 Stop Enable Setting. - * - * This function enables/disables the PLL1 Clock during the Normal Stop (In Low - * Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other - * power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to - * run if it is written to 1. - * - * @param baseAddr Base address for current MCG instance. - * @params enable PLL1 Stop Enable Setting - * - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and - * MCGDDRCLK2X) are enabled if system is in Normal Stop mode. - * - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) - * are disabled in any of the Stop modes. - */ -static inline void CLOCK_HAL_SetPllStop1Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C11_PLLSTEN1(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the PLL1 Stop Enable Setting. - * - * This function gets the PLL1 Stop Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if PLL1 Stop is enabled. - */ -static inline bool CLOCK_HAL_GetPllStop1Cmd(uint32_t baseAddr) -{ - return BR_MCG_C11_PLLSTEN1(baseAddr); -} - -/*! - * @brief Sets the PLL Clock Select Setting. - * - * This function controls whether the PLL0 or PLL1 output is selected as the - * MCG source when CLKS are programmed in PLL Engaged External (PEE) mode - * (CLKS[1:0]=00 and IREFS=0 and PLLS=1). - * - * @param baseAddr Base address for current MCG instance. - * @params setting PLL Clock Select Setting - * - 0: PLL0 output clock is selected. - * - 1: PLL1 output clock is selected. - */ -static inline void CLOCK_HAL_SetPllClkSelMode(uint32_t baseAddr, mcg_pll_clk_select_t setting) -{ - BW_MCG_C11_PLLCS(baseAddr, setting); -} - -/*! - * @brief Gets the PLL Clock Select Setting. - * - * This function gets the PLL Clock Select Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting PLL Clock Select Setting - */ -static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelMode(uint32_t baseAddr) -{ - return (mcg_pll_clk_select_t)BR_MCG_C11_PLLCS(baseAddr); -} - -/*! - * @brief Sets the PLL1 External Reference Divider Setting. - * - * This function selects the amount to divide down the external reference - * clock selected by REFSEL2 for PLL1. The resulting frequency must be in a valid - * reference range. After the PLL1 is enabled (by setting either PLLCLKEN1 or PLLS), - * the PRDIV1 value must not be changed when LOCK1 is zero. - * - * @param baseAddr Base address for current MCG instance. - * @params setting PLL1 External Reference Divider Setting - */ -static inline void CLOCK_HAL_SetPllExternalRefDivider1(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C11_PRDIV1(baseAddr, setting); -} - -/*! - * @brief Gets the PLL1 External Reference Divider Setting. - * - * This function gets the PLL1 External Reference Divider Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting PLL1 External Reference Divider Setting - */ -static inline uint8_t CLOCK_HAL_GetPllExternalRefDivider1(uint32_t baseAddr) -{ - return BR_MCG_C11_PRDIV1(baseAddr); -} - -/*! - * @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting. - * - * This function determines whether an interrupt request is made following a - * loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set. - * - * @param baseAddr Base address for current MCG instance. - * @params enable PLL1 Loss of Lock Interrupt Enable Setting - * - true: Generate an interrupt request on loss of lock on PLL1. - * - false: No interrupt request is generated on loss of lock on PLL1. - */ -static inline void CLOCK_HAL_SetLossOfLock1Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C12_LOLIE1(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the PLL1 Loss of Lock Interrupt Enable Setting. - * - * This function gets the PLL1 Loss of Lock Interrupt Enable Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled true if PLL1 Loss of Lock Interrupt is enabled. - */ -static inline bool CLOCK_HAL_GetLossOfLock1Cmd(uint32_t baseAddr) -{ - return BR_MCG_C12_LOLIE1(baseAddr); -} - -/*! - * @brief Sets the Clock Monitor Enable2 Setting - * - * This function enables/disables the loss of the clock monitor for the OSC1 external - * reference clock. LOCRE2 determines whether a reset or interrupt request is generated - * following a loss of OSC1 external reference clock. The CME2 bit should only be set - * to a logic 1 when the MCG is in an operational mode that uses the external clock - * (PEE or PBE) . Whenever the CME2 bit is set to a logic 1, the value of the RANGE1 - * bits in the C10 register should not be changed. CME2 bit should be set to a logic 0 - * before the MCG enters any Stop mode. Otherwise, a reset request may occur while in - * Stop mode. - * - * @param baseAddr Base address for current MCG instance. - * @params enable Clock Monitor Enable2 Setting - * - true: Generate a reset request on loss of external clock on OSC1. - * - false: External clock monitor for OSC1 is disabled. - */ -static inline void CLOCK_HAL_SetClkMonitor2Cmd(uint32_t baseAddr, bool enable) -{ - BW_MCG_C12_CME2(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the Clock Monitor Enable2 Setting. - * - * This function gets the Clock Monitor Enable2 Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return enabled True if Clock Monitor Enable2 is enabled. - */ -static inline bool CLOCK_HAL_GetClkMonitor2Cmd(uint32_t baseAddr) -{ - return BR_MCG_C12_CME2(baseAddr); -} - -/*! - * @brief Sets the VCO1 Divider Setting. - * - * This function selects the amount to divide the VCO output of the PLL1. - * The VDIV1 bits establishes the multiplication factor (M) applied to the reference - * clock frequency. After the PLL1 is enabled (by setting either PLLCLKEN1 or - * PLLS), the VDIV1 value must not be changed when LOCK1 is zero. - * - * @param baseAddr Base address for current MCG instance. - * @params setting VCO1 Divider Setting - */ -static inline void CLOCK_HAL_SetVoltCtrlOscDivider1(uint32_t baseAddr, uint8_t setting) -{ - BW_MCG_C12_VDIV1(baseAddr, setting); -} - -/*! - * @brief Gets the VCO1 Divider Setting. - * - * This function gets the VCO1 Divider Setting. - * - * @param baseAddr Base address for current MCG instance. - * @return setting VCO1 Divider Setting - */ -static inline uint8_t CLOCK_HAL_GetVoltCtrlOscDivider1(uint32_t baseAddr) -{ - return BR_MCG_C12_VDIV1(baseAddr); -} - -/*! - * @brief Gets the Loss of the Lock2 Status. - * - * This function gets the Loss of the Lock2 Status. This bit is a sticky bit indicating - * the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1 - * output frequency has fallen outside the lock exit frequency tolerance, D unl. - * LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This - * bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 - * to this bit has no effect. - * - * @param baseAddr Base address for current MCG instance. - * @return status Loss of Lock2 Status - * - 0: PLL1 has not lost lock since LOLS1 was last cleared. - * - 1: PLL1 has lost lock since LOLS1 was last cleared. - */ -static inline mcg_loss_of_lock_status_t CLOCK_HAL_GetLossOfLock1Mode(uint32_t baseAddr) -{ - return (mcg_loss_of_lock_status_t)BR_MCG_S2_LOLS1(baseAddr); -} - -/*! - * @brief Gets the Lock1 Status. - * - * This function gets the Lock1 Status. This bit indicates whether PLL1 has - * acquired the lock. PLL1 Lock detection is disabled when not operating in either - * PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the - * BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK, - * MCGPLL1CLK2X, and MCGDDRCLK2X are gated off until the LOCK1 bit gets - * asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0] - * bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the - * lock status bit to clear and stay cleared until the PLL1 has reacquired lock. - * Loss of PLL1 reference clock will also causes the LOCK1 bit to clear until the PLL1 - * has reacquired lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also - * causes the lock status bit to clear and stay cleared until the Stop mode is exited - * and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit - * is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are gated off - * until the LOCK1 bit is asserted again. - * - * @param baseAddr Base address for current MCG instance. - * @return status Lock1 Status - * - 0: PLL1 is currently unlocked. - * - 1: PLL1 is currently locked. - */ -static inline mcg_lock_status_t CLOCK_HAL_GetLock1Mode(uint32_t baseAddr) -{ - return (mcg_lock_status_t)BR_MCG_S2_LOCK1(baseAddr); -} - -/*! - * @brief Gets the PLL Clock Select Status. - * - * This function gets the PLL Clock Select Status. The PLLCST indicates the PLL - * clock selected by PLLCS. The PLLCST bit is not updated immediately after a - * write to the PLLCS bit due internal synchronization between clock domains. - * - * @param baseAddr Base address for current MCG instance. - * @return status PLL Clock Select Status - * - 0: Source of PLLCS is PLL0 clock. - * - 1: Source of PLLCS is PLL1 clock. - */ -static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelStatMode(uint32_t baseAddr) -{ - return (mcg_pll_clk_select_t)BR_MCG_S2_PLLCST(baseAddr); -} - -/*! - * @brief Gets the OSC1 Initialization Status. - * - * This function gets the OSC1 Initialization Status. This bit is set after the - * initialization cycles of the 2nd crystal oscillator clock have completed. See - * the Oscillator block guide for more details. - * - * @param baseAddr Base address for current MCG instance. - * @return status OSC1 Initialization Status - */ -static inline uint8_t CLOCK_HAL_GetOscInit1(uint32_t baseAddr) -{ - return BR_MCG_S2_OSCINIT1(baseAddr); -} - -/*! - * @brief Gets the OSC1 Loss of Clock Status. - * - * This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss - * of the OSC1 external reference clock has occurred. LOCRE2 determines if a reset or - * interrupt is generated when LOCS2 is set. This bit is cleared by writing a - * logic 1 to it when set. - * - * @param baseAddr Base address for current MCG instance. - * @return status OSC1 Loss of Clock Status - * - 0: No loss of OSC1 external reference clock has occurred. - * - 1: Loss of OSC1 external reference clock has occurred. - */ -static inline mcg_locs2_status_t CLOCK_HAL_GetLocs2Mode(uint32_t baseAddr) -{ - return (mcg_locs2_status_t)BR_MCG_S2_LOCS2(baseAddr); -} -#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_MCG_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.c deleted file mode 100644 index 3933af9adca..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.c +++ /dev/null @@ -1,2501 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_mcg_hal_modes.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/***************************************************************** - * MCG clock mode transition functions - * - * FEI -> FEE - * FEI -> FBI - * FEI -> FBE - * - * FEE -> FEI - * FEE -> FBI - * FEE -> FBE - * - * FBI -> FEI - * FBI -> FEE - * FBI -> FBE - * FBI -> BLPI - * - * BLPI -> FBI - * - * FBE -> FEE - * FBE -> FEI - * FBE -> FBI - * FBE -> PBE - * FBE -> BLPE - * - * PBE -> FBE - * PBE -> PEE - * PBE -> BLPE - * - * BLPE -> FBE - * BLPE -> PBE - * - * PEE -> PBE - * - *****************************************************************/ -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_GetMcgMode - * Description : internal function will check the mcg registers and determine - * the current mcg mode - * - * Return value : mcgMode or error code mcg_modes_t defined in fsl_mcg_hal_modes.h - *END***********************************************************************************/ -mcg_modes_t CLOCK_HAL_GetMcgMode(uint32_t baseAddr) -{ - /* Check MSG is in FEI mode */ - if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) && /* CLKS mux is FLL output (CLKST=0) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) /* FLL ref is internal ref clk (IREFST=1) */ -#if FSL_FEATURE_MCG_HAS_PLL - && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)) /* PLLS mux is FLL (PLLST=0) */ -#else - ) -#endif - { - return kMcgModeFEI; /* return FEI code */ - } - /* Check MCG is in PEE mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatPll) && /* CLKS mux is PLL output (CLKST=3) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) /* FLL ref is external ref clk (IREFST=0) */ -#if FSL_FEATURE_MCG_HAS_PLL - && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)) /* PLLS mux is PLL or PLLCS (PLLST=1) */ -#else - ) -#endif - { - return kMcgModePEE; /* return PEE code */ - } - /* Check MCG is in PBE mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */ -#if FSL_FEATURE_MCG_HAS_PLL - (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) && /* PLLS mux is PLL or PLLCS (PLLST=1) */ -#endif - (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */ - { - return kMcgModePBE; /* return PBE code */ - } - /* Check MCG is in FBE mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */ -#if FSL_FEATURE_MCG_HAS_PLL - (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */ -#endif - (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */ - { - return kMcgModeFBE; /* return FBE code */ - } - /* Check MCG is in BLPE mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */ - (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelLowPower))/* MCG_C2[LP] bit is set (LP=1) */ - { - return kMcgModeBLPE; /* return BLPE code */ - } - /* Check if in BLPI mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) && /* CLKS mux in internal ref clk (CLKST=1) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) && /* FLL ref is internal ref clk (IREFST=1) */ -#if FSL_FEATURE_MCG_HAS_PLL - (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */ -#endif - (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelLowPower))/* MCG_C2[LP] bit is set (LP=1) */ - { - return kMcgModeBLPI; /* return BLPI code */ - } - /* Check if in FBI mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) && /* CLKS mux in internal ref clk (CLKST=1) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) && /* FLL ref is internal ref clk (IREFST=1) */ -#if FSL_FEATURE_MCG_HAS_PLL - (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */ -#endif - (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */ - { - return kMcgModeFBI; /* return FBI code */ - } - /* Check MCG is in FEE mode */ - else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) && /* CLKS mux is FLL output (CLKST=0) */ - (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) /* FLL ref is external ref clk (IREFST=0) */ -#if FSL_FEATURE_MCG_HAS_PLL - && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)) /* PLLS mux is FLL (PLLST=0) */ -#else - ) -#endif - { - return kMcgModeFEE; /* return FEE code */ - } - else - { - return kMcgModeError; /* error unknown mode */ - } -} /* CLOCK_HAL_GetMcgMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_GetFllFrequency - * Description : internal function to check the fll frequency - * This function will calculate and check the fll frequency value based on input value. - * - * Parameters: fllRef - fll reference clock in Hz. - * - * Return value : fll output frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_GetFllFrequency(uint32_t baseAddr, int32_t fllRef) -{ - int32_t fllFreqHz = 0; - - /* Check that only allowed ranges have been selected */ - if (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr) > kMcgDigitalControlledOscRangeSelMid) - { - return kMcgErrFllDrstDrsRange; /* return error code if DRS range 2 or 3 selected */ - } - - /* if DMX32 set */ - if (CLOCK_HAL_GetDmx32(baseAddr)) - { - /* determine multiplier based on DRS */ - switch (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr)) - { - case 0: - fllFreqHz = (fllRef * kMcgConstant732); - if (fllFreqHz < kMcgConstant20000000) - { - return kMcgErrFllRange0Min; - } - else if (fllFreqHz > kMcgConstant25000000) - { - return kMcgErrFllRange0Max; - } - break; - case 1: - fllFreqHz = (fllRef * kMcgConstant1464); - if (fllFreqHz < kMcgConstant40000000) - { - return kMcgErrFllRange1Min; - } - else if (fllFreqHz > kMcgConstant50000000) - { - return kMcgErrFllRange1Max; - } - break; - case 2: - fllFreqHz = (fllRef * kMcgConstant2197); - if (fllFreqHz < kMcgConstant60000000) - { - return kMcgErrFllRange2Min; - } - else if (fllFreqHz > kMcgConstant75000000) - { - return kMcgErrFllRange2Max; - } - break; - case 3: - fllFreqHz = (fllRef * kMcgConstant2929); - if (fllFreqHz < kMcgConstant80000000) - { - return kMcgErrFllRange3Min; - } - else if (fllFreqHz > kMcgConstant100000000) - { - return kMcgErrFllRange3Max; - } - break; - default: - break; - } - } - /* if DMX32 = 0 */ - else - { - /* determine multiplier based on DRS */ - switch (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr)) - { - case 0: - fllFreqHz = (fllRef * kMcgConstant640); - if (fllFreqHz < kMcgConstant20000000) - { - return kMcgErrFllRange0Min; - } - else if (fllFreqHz > kMcgConstant25000000) - { - return kMcgErrFllRange0Max; - } - break; - case 1: - fllFreqHz = (fllRef * kMcgConstant1280); - if (fllFreqHz < kMcgConstant40000000) - { - return kMcgErrFllRange1Min; - } - else if (fllFreqHz > kMcgConstant50000000) - { - return kMcgErrFllRange1Max; - } - break; - case 2: - fllFreqHz = (fllRef * kMcgConstant1920); - if (fllFreqHz < kMcgConstant60000000) - { - return kMcgErrFllRange2Min; - } - else if (fllFreqHz > kMcgConstant75000000) - { - return kMcgErrFllRange2Max; - } - break; - case 3: - fllFreqHz = (fllRef * kMcgConstant2560); - if (fllFreqHz < kMcgConstant80000000) - { - return kMcgErrFllRange3Min; - } - else if (fllFreqHz > kMcgConstant100000000) - { - return kMcgErrFllRange3Max; - } - break; - default: - break; - } - } - return fllFreqHz; -} /* CLOCK_HAL_GetFllFrequency */ - - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFeiToFeeMode - * Description : Mode transition FEI to FEE mode - * This function transitions the MCG from FEI mode to FEE mode. - * - * Parameters: oscselVal - oscillator selection value - * (eunm defined in mcg_oscsel_select_t) - * 0: kMcgOscselOsc, Selects System Oscillator (OSCCLK) - * 1: kMcgOscselRtc, Selects 32 kHz RTC Oscillator - * 2: kMcgOscselIrc, Selects 48 MHz IRC Oscillator (K70) - * crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * (enum defined in mcg_high_gain_osc_select_t) - * 0: kMcgHgoSelectLow, Configure for low-power operation - * 1: kMcgHgoSelectHigh, Configure for high-gain operation - * erefsVal - selects external clock or crystal osc - * (enum defined in mcg_external_ref_clock_select_t) - * 0: kMcgErefClockSelectExt, External reference clock requested - * 1: kMcgErefClockSelectOsc, Oscillator requested - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFeiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) -{ - uint8_t frDivVal; - uint32_t mcgOut, fllRefFreq, i; - - /* check if in FEI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI) - { - return kMcgErrNotInFeiMode; /* return error code */ - } - - /* check external frequency is less than the maximum frequency */ - if (crystalVal > kMcgConstant50000000) - { - return kMcgErrOscEtalRange; /* - external frequency is bigger than max frequency */ - } - - /* check crystal frequency is within spec. if crystal osc is being used */ - if (oscselVal == kMcgOscselOsc) - { - if (erefsVal) - { - /* return error if one of the available crystal options is not available */ - if ((crystalVal < kMcgConstant30000) || - ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || - (crystalVal > kMcgConstant32000000)) - { - return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */ - } - - /* config the hgo settings */ - CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); - } - - /* config the erefs0 settings */ - CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); - } - - /* - * the RANGE value is determined by the external frequency. Since the RANGE parameter - * affects the FRDIV divide value it still needs to be set correctly even if the - * oscillator is not being used - */ - if (crystalVal <= kMcgConstant40000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); - } - else if (crystalVal <= kMcgConstant8000000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); - } - else - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); - } - - /* determine FRDIV based on reference clock frequency */ - /* since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here. */ - if (crystalVal <= kMcgConstant1250000) - { - frDivVal = kMcgConstant0; - } - else if (crystalVal <= kMcgConstant2500000) - { - frDivVal = kMcgConstant1; - } - else if (crystalVal <= kMcgConstant5000000) - { - frDivVal = kMcgConstant2; - } - else if (crystalVal <= kMcgConstant10000000) - { - frDivVal = kMcgConstant3; - } - else if (crystalVal <= kMcgConstant20000000) - { - frDivVal = kMcgConstant4; - } - else - { - frDivVal = kMcgConstant5; - } - - /* The FLL ref clk divide value depends on FRDIV and the RANGE value */ - if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow) - { - fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal)); - } - else - { - fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal)); - } - - /* Check resulting FLL frequency */ - /* FLL reference frequency calculated from ext ref freq and FRDIV */ - mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq); - if (mcgOut < kMcgErrMax) - { - return mcgOut; /* If error code returned, return the code to calling function */ - } - - /* - * Select external oscilator and Reference Divider and clear IREFS to start ext osc - * If IRCLK is required it must be enabled outside of this driver, existing state will - * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0 - */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, frDivVal, kMcgInternalRefClkSrcExternal); - - /* if the external oscillator is used need to wait for OSCINIT to set */ - if ((oscselVal == kMcgOscselOsc) && (erefsVal)) - { - for (i = 0 ; i < kMcgConstant20000000 ; i++) - { - if (CLOCK_HAL_GetOscInit0(baseAddr)) - { - break; /* jump out early if OSCINIT sets before loop finishes */ - } - } - - if (!CLOCK_HAL_GetOscInit0(baseAddr)) - { - /* check bit is really set and return with error if not set */ - return kMcgErrOscSetTimeout; - } - } - - /* Wait for clock status bits to show clock source is FLL */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) - { - break; // jump out early if CLKST shows FLL selected before loop finishes - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) - { - return kMcgErrClkst0; // check FLL is really selected and return with error if not - } - - /* - * Now in FEE - * It is recommended that the clock monitor is enabled when using an external clock as the - * clock source/reference. - * It is enabled here but can be removed if this is not required. - */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); - - return mcgOut; /* MCGOUT frequency equals FLL frequency */ -} /* CLOCK_HAL_SetFeiToFeeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFeiToFbiMode - * Description : Mode transition FEI to FBI mode - * This function transitions the MCG from FEI mode to FBI mode. - * - * Parameters: ircFreq - internal reference clock frequency value - * ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFeiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) -{ - uint8_t fcrDivVal; - uint16_t i; - - /* Check MCG is in FEI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI) - { - return kMcgErrNotInFeiMode; /* return error code */ - } - - - /* Check that the irc frequency matches the selected IRC */ - if (!(ircSelect)) - { - if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) - { - return kMcgErrIrcSlowRange; - } - } - else - { - if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000)) - { - return kMcgErrIrcFastRange; - } /* Fast IRC freq */ - } - - /* Select the desired IRC */ - CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect); - - /* Change the CLKS mux to select the IRC as the MCGOUT */ - CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelInternal); - - /* Set LP bit to enable the FLL */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); - - /* wait until internal reference switches to requested irc. */ - if (ircSelect == kMcgInternalRefClkSelSlow) - { - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (!(MCG_S & MCG_S_IRCST_MASK)) - { - break; /* jump out early if IRCST clears before loop finishes */ - } - } - if (MCG_S & MCG_S_IRCST_MASK) - { - /* check bit is really clear and return with error if set */ - return kMcgErrIrcstClearTimeout; - } - } - else - { - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (MCG_S & MCG_S_IRCST_MASK) - { - break; /* jump out early if IRCST sets before loop finishes */ - } - } - if (!(MCG_S & MCG_S_IRCST_MASK)) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout1; - } - } - - /* Wait for clock status bits to update */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) - { - break; /* jump out early if CLKST shows IRC slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef) - { - /* check IRC is really selected and return with error if not */ - return kMcgErrClkst1; - } - - /* Now in FBI mode */ - if (ircSelect == kMcgInternalRefClkSelFast) - { - fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); - - /* MCGOUT frequency equals fast IRC frequency divided by 2 */ - return (ircFreq / fcrDivVal); - } - else - { - return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ - } -} /* CLOCK_HAL_SetFeiToFbiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFeiToFbeMode - * Description : Mode transition FEI to FBE mode - * This function transitions the MCG from FEI mode to FBE mode. - * - * Parameters: oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * erefsVal - selects external clock (=0) or crystal osc (=1) - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFeiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) -{ - uint8_t frDivVal; - int16_t i; - - /* check if in FEI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI) - { - return kMcgErrNotInFeiMode; /* return error code */ - } - - /* check external frequency is less than the maximum frequency */ - if (crystalVal > kMcgConstant50000000) - { - /* - external frequency is bigger than max frequency */ - return kMcgErrOscEtalRange; - } - - /* check crystal frequency is within spec. if crystal osc is being used */ - if (oscselVal == kMcgOscselOsc) - { - if (erefsVal) - { - /* return error if one of the available crystal options is not available */ - if ((crystalVal < kMcgConstant30000) || - ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || - (crystalVal > kMcgConstant32000000)) - { - /* - crystal frequency outside allowed range */ - return kMcgErrOscXtalRange; - } - - /* config the hgo settings */ - CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); - } - - /* config the erefs0 settings */ - CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); - } - - /* - * the RANGE value is determined by the external frequency. Since the RANGE parameter - * affects the FRDIV divide value it still needs to be set correctly even if the - * oscillator is not being used - */ - if (crystalVal <= kMcgConstant40000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); - } - else if (crystalVal <= kMcgConstant8000000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); - } - else - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); - } - - /* determine FRDIV based on reference clock frequency */ - /* since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here. */ - if (crystalVal <= kMcgConstant1250000) - { - frDivVal = kMcgConstant0; - } - else if (crystalVal <= kMcgConstant2500000) - { - frDivVal = kMcgConstant1; - } - else if (crystalVal <= kMcgConstant5000000) - { - frDivVal = kMcgConstant2; - } - else if (crystalVal <= kMcgConstant10000000) - { - frDivVal = kMcgConstant3; - } - else if (crystalVal <= kMcgConstant20000000) - { - frDivVal = kMcgConstant4; - } - else - { - frDivVal = kMcgConstant5; - } - - /* Set LP bit to enable the FLL */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); - - /* - * Select external oscilator and Reference Divider and clear IREFS to start ext osc - * If IRCLK is required it must be enabled outside of this driver, existing state will - * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0 - */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelExternal, frDivVal, kMcgInternalRefClkSrcExternal); - - /* if the external oscillator is used need to wait for OSCINIT to set */ - if ((oscselVal == kMcgOscselOsc) && (erefsVal)) - { - for (i = 0 ; i < kMcgConstant10000 ; i++) - { - if (CLOCK_HAL_GetOscInit0(baseAddr)) - { - break; /* jump out early if OSCINIT sets before loop finishes */ - } - } - - if (!CLOCK_HAL_GetOscInit0(baseAddr)) - { - /* check bit is really set and return with error if not set */ - return kMcgErrOscSetTimeout; - } - } - - /* wait for Reference clock Status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr)) - { - break; /* jump out early if IREFST clears before loop finishes */ - } - } - - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr)) - { - /* check bit is really clear and return with error if not set */ - return kMcgErrIrefstClearTimeOut; - } - - /* Wait for clock status bits to show clock source is ext ref clk */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) - { - break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) - { - return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ - } - - /* - * Now in FBE - * It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference. - * It is enabled here but can be removed if this is not required. - */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); - - return crystalVal; /* MCGOUT frequency equals external clock frequency */ -} /* CLOCK_HAL_SetFeiToFbeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFeeToFeiMode - * Description : Mode transition FEE to FEI mode - * This function transitions the MCG from FEE mode to FEI mode. - * - * Parameters: ircFreq - internal reference clock frequency value (slow) - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFeeToFeiMode(uint32_t baseAddr, uint32_t ircFreq) -{ - int16_t i; - uint32_t mcgOut; - - /* Check MCG is in FEE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE) - { - return kMcgErrNotInFeeMode; /* return error code */ - } - - /* Check IRC frequency is within spec. */ - if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) - { - return kMcgErrIrcSlowRange; - } - - /* Check resulting FLL frequency */ - mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq); - if (mcgOut < kMcgErrMax) - { - /* If error code returned, return the code to calling function */ - return mcgOut; - } - - /* Ensure clock monitor is disabled before switching to FEI otherwise - * a loss of clock will trigger - */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); - - /* Change FLL reference clock from external to internal by setting IREFS bit */ - CLOCK_HAL_SetInternalRefSelMode(baseAddr, kMcgInternalRefClkSrcSlow); - - /* wait for Reference clock to switch to internal reference */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) - { - break; /* jump out early if IREFST sets before loop finishes */ - } - } - - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout; - } - - /* Now in FEI mode */ - return mcgOut; -} /* CLOCK_HAL_SetFeeToFeiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFeeToFbiMode - * Description : Mode transition FEE to FBI mode - * This function transitions the MCG from FEE mode to FBI mode. - * - * Parameters: ircFreq - internal reference clock frequency value - * ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFeeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) -{ - uint8_t fcrDivVal; - int16_t i; - - /* Check MCG is in FEE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE) - { - return kMcgErrNotInFeeMode; /* return error code */ - } - - /* Check that the irc frequency matches the selected IRC */ - if (!(ircSelect)) - { - if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) - { - return kMcgErrIrcSlowRange; - } - } - else - { - if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000)) - { - return kMcgErrIrcFastRange; - } /* Fast IRC freq */ - } - - /* Select the required IRC */ - CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect); - - /* Make sure the clock monitor is disabled before switching modes otherwise it will trigger */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); - - /* Select the IRC as the CLKS mux selection */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelInternal, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); - - /* wait until internal reference switches to requested irc. */ - if (ircSelect == kMcgInternalRefClkSelSlow) - { - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatSlow) - { - break; /* jump out early if IRCST clears before loop finishes */ - } - } - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatSlow) - { - /* check bit is really clear and return with error if set */ - return kMcgErrIrcstClearTimeout; - } - } - else - { - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatFast) - { - break; /* jump out early if IRCST sets before loop finishes */ - } - } - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatFast) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout1; - } - } - - /* Wait for clock status bits to update */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) - { - break; /* jump out early if CLKST shows IRC slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef) - { - return kMcgErrClkst1; /* check IRC is really selected and return with error if not */ - } - - /* wait for Reference clock Status bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) - { - break; /* jump out early if IREFST sets before loop finishes */ - } - } - - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout; - } - - /* Now in FBI mode */ - if (ircSelect == kMcgInternalRefClkSelFast) - { - fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); - - return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ - } - else - { - return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ - } -} /* CLOCK_HAL_SetFeeToFbiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFeeToFbeMode - * Description : Mode transition FEE to FBE mode - * This function transitions the MCG from FEE mode to FBE mode. - * - * Parameters: crystalVal - external reference clock frequency value - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFeeToFbeMode(uint32_t baseAddr, uint32_t crystalVal) -{ - uint16_t i; - - /* Check MCG is in FEE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE) - { - return kMcgErrNotInFeeMode; /* return error code */ - } - - /* Set CLKS field to 2 to switch CLKS mux to select ext ref clock */ - CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelExternal); - - /* Wait for clock status bits to show clock source is ext ref clk */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) - { - break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) - { - return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ - } - - /* Now in FBE mode */ - return crystalVal; -} /* CLOCK_HAL_SetFeeToFbeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbiToFeiMode - * Description : Mode transition FBI to FEI mode - * This function transitions the MCG from FBI mode to FEI mode. - * - * Parameters: ircFreq - internal reference clock frequency value (slow) - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbiToFeiMode(uint32_t baseAddr, uint32_t ircFreq) -{ - int16_t i; - int32_t mcgOut; - - /* check if in FBI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) - { - return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ - } - - /* Check IRC frequency is within spec. */ - if ((ircFreq < 31250) || (ircFreq > 39063)) - { - return kMcgErrIrcSlowRange; - } - - /* Check resulting FLL frequency */ - mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq); - if (mcgOut < kMcgErrMax) - { - /* If error code returned, return the code to calling function */ - return mcgOut; - } - - /* Change the CLKS mux to select the FLL output as MCGOUT */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); - - /* wait for Reference clock Status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr)) - { - break; /* jump out early if IREFST clears before loop finishes */ - } - } - - if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr)) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout; - } - - /* Wait for clock status bits to show clock source is ext ref clk */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) - { - break; /* jump out early if CLKST shows FLL slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) - { - return kMcgErrClkst0; /* check FLL is really selected and return with error if not */ - } - - /* Now in FEI mode */ - return mcgOut; -} /* CLOCK_HAL_SetFbiToFeiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbiToFeeMode - * Description : Mode transition FBI to FEE mode - * This function transitions the MCG from FBI mode to FEE mode. - * - * Parameters: oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * erefsVal - selects external clock (=0) or crystal osc (=1) - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) -{ - uint8_t frDivVal; - uint32_t i; - uint32_t mcgOut, fllRefFreq; - - /* check if in FBI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) - { - return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ - } - - /* check external frequency is less than the maximum frequency */ - if (crystalVal > kMcgConstant50000000) - { - return kMcgErrOscEtalRange; - } - - /* check crystal frequency is within spec. if crystal osc is being used */ - if (oscselVal == kMcgOscselOsc) - { - if (erefsVal) - { - /* return error if one of the available crystal options is not available */ - if ((crystalVal < kMcgConstant30000) || - ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || - (crystalVal > kMcgConstant32000000)) - { - return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */ - } - - /* config the hgo settings */ - CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); - } - - /* config the erefs0 settings */ - CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); - } - - /* - * the RANGE value is determined by the external frequency. Since the RANGE parameter - * affects the FRDIV divide value it still needs to be set correctly even if the - * oscillator is not being used - */ - if (crystalVal <= kMcgConstant40000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); - } - else if (crystalVal <= kMcgConstant8000000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); - } - else - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); - } - - /* determine FRDIV based on reference clock frequency */ - /* since the external frequency has already been checked only the maximum frequency for each FRDIV - * value needs to be compared here. - */ - if (crystalVal <= kMcgConstant1250000) - { - frDivVal = kMcgConstant0; - } - else if (crystalVal <= kMcgConstant2500000) - { - frDivVal = kMcgConstant1; - } - else if (crystalVal <= kMcgConstant5000000) - { - frDivVal = kMcgConstant2; - } - else if (crystalVal <= kMcgConstant10000000) - { - frDivVal = kMcgConstant3; - } - else if (crystalVal <= kMcgConstant20000000) - { - frDivVal = kMcgConstant4; - } - else - { - frDivVal = kMcgConstant5; - } - - /* The FLL ref clk divide value depends on FRDIV and the RANGE value */ - if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow) - { - fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal)); - } - else - { - fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal)); - } - - /* Check resulting FLL frequency */ - /* FLL reference frequency calculated from ext ref freq and FRDIV */ - mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq); - if (mcgOut < kMcgErrMax) - { - return mcgOut; /* If error code returned, return the code to calling function */ - } - - /* - * Select external oscilator and Reference Divider and clear IREFS to start ext osc - * If IRCLK is required it must be enabled outside of this driver, existing state will - * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0 - */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, frDivVal, kMcgInternalRefClkSrcExternal); - - /* if the external oscillator is used need to wait for OSCINIT to set */ - if ((oscselVal == kMcgOscselOsc) && (erefsVal)) - { - for (i = 0 ; i < kMcgConstant20000000 ; i++) - { - if (CLOCK_HAL_GetOscInit0(baseAddr)) - { - break; /* jump out early if OSCINIT sets before loop finishes */ - } - } - - if (!CLOCK_HAL_GetOscInit0(baseAddr)) - { - /* check bit is really set and return with error if not set */ - return kMcgErrOscSetTimeout; - } - } - - /* Wait for clock status bits to show clock source is FLL */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) - { - break; // jump out early if CLKST shows FLL selected before loop finishes - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) - { - return kMcgErrClkst0; // check FLL is really selected and return with error if not - } - - /* - * Now in FEE - * It is recommended that the clock monitor is enabled when using an external clock as the - * clock source/reference. - * It is enabled here but can be removed if this is not required. - */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); - - return mcgOut; /* MCGOUT frequency equals FLL frequency */ -} /* CLOCK_HAL_SetFbiToFeeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbiToFbeMode - * Description : Mode transition FBI to FBE mode - * This function transitions the MCG from FBI mode to FBE mode. - * - * Parameters: oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * erefsVal - selects external clock (=0) or crystal osc (=1) - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) -{ - uint8_t frDivVal; - uint16_t i; - - /* check if in FBI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) - { - return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ - } - - /* check external frequency is less than the maximum frequency */ - if (crystalVal > kMcgConstant50000000) - { - return kMcgErrOscEtalRange; - } - - /* check crystal frequency is within spec. if crystal osc is being used */ - if (oscselVal == kMcgOscselOsc) - { - if (erefsVal) - { - /* return error if one of the available crystal options is not available */ - if ((crystalVal < kMcgConstant30000) || - ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || - (crystalVal > kMcgConstant32000000)) - { - return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */ - } - - /* config the hgo settings */ - CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); - } - - /* config the erefs0 settings */ - CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); - } - - /* - * the RANGE value is determined by the external frequency. Since the RANGE parameter - * affects the FRDIV divide value it still needs to be set correctly even if the - * oscillator is not being used - */ - if (crystalVal <= kMcgConstant40000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); - } - else if (crystalVal <= kMcgConstant8000000) - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); - } - else - { - CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); - } - - /* determine FRDIV based on reference clock frequency */ - /* since the external frequency has already been checked only the maximum frequency for each FRDIV - * value needs to be compared here. - */ - if (crystalVal <= kMcgConstant1250000) - { - frDivVal = kMcgConstant0; - } - else if (crystalVal <= kMcgConstant2500000) - { - frDivVal = kMcgConstant1; - } - else if (crystalVal <= kMcgConstant5000000) - { - frDivVal = kMcgConstant2; - } - else if (crystalVal <= kMcgConstant10000000) - { - frDivVal = kMcgConstant3; - } - else if (crystalVal <= kMcgConstant20000000) - { - frDivVal = kMcgConstant4; - } - else - { - frDivVal = kMcgConstant5; - } - - /* Set LP bit to enable the FLL */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); - - /* - * Select external oscilator and Reference Divider and clear IREFS to start ext osc - * If IRCLK is required it must be enabled outside of this driver, existing state will be maintained - * CLKS=2, FRDIV=frdiv_val, IREFS=0 - */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelExternal, frDivVal, kMcgInternalRefClkSrcExternal); - - /* if the external oscillator is used need to wait for OSCINIT to set */ - if ((oscselVal == kMcgOscselOsc) && (erefsVal)) - { - for (i = 0 ; i < kMcgConstant10000 ; i++) - { - if (CLOCK_HAL_GetOscInit0(baseAddr)) - { - break; /* jump out early if OSCINIT sets before loop finishes */ - } - } - - if (!CLOCK_HAL_GetOscInit0(baseAddr)) - { - /* check bit is really set and return with error if not set */ - return kMcgErrOscSetTimeout; - } - } - - /* wait for Reference clock Status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr)) - { - break; /* jump out early if IREFST clears before loop finishes */ - } - } - - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr)) - { - /* check bit is really clear and return with error if not set */ - return kMcgErrIrefstClearTimeOut; - } - - /* Wait for clock status bits to show clock source is ext ref clk */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) - { - break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) - { - return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ - } - - /* - * Now in FBE - * It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference. - * It is enabled here but can be removed if this is not required. - */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); - - return crystalVal; /* MCGOUT frequency equals external clock frequency */ -} /* CLOCK_HAL_SetFbiToFbeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbiToBlpiMode - * Description : Mode transition FBI to BLPI mode - * This function transitions the MCG from FBI mode to BLPI mode.This is - * achieved by setting the MCG_C2[LP] bit. - * - * Parameters: ircFreq - internal reference clock frequency value - * ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbiToBlpiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) -{ - uint8_t fcrDivVal; - - /* check if in FBI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) - { - return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ - } - - /* Set LP bit to disable the FLL and enter BLPI */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower); - - /* Now in BLPI */ - if (ircSelect == kMcgInternalRefClkSelFast) - { - fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); - return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ - } - else - { - return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ - } -} /* CLOCK_HAL_SetFbiToBlpiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetBlpiToFbiMode - * Description : Mode transition BLPI to FBI mode - * This function transitions the MCG from BLPI mode to FBI mode.This is - * achieved by clearing the MCG_C2[LP] bit. - * - * Parameters: ircFreq - internal reference clock frequency value - * ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetBlpiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, uint8_t ircSelect) -{ - uint8_t fcrDivVal; - - /* check if in BLPI mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPI) - { - return kMcgErrNotInBlpiMode; /* MCG not in correct mode return fail code */ - } - - /* Clear LP bit to enable the FLL and enter FBI mode */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); - - /* Now in FBI mode */ - if (ircSelect) - { - fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); - return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ - } - else - { - return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ - } -} /* CLOCK_HAL_SetBlpiToFbiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbeToFeeMode - * Description : Mode transition FBE to FEE mode - * This function transitions the MCG from FBE mode to FEE mode. - * - * Parameters: crystalVal - external reference clock frequency value - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToFeeMode(uint32_t baseAddr, uint32_t crystalVal) -{ - uint16_t i, fllRefFreq, frDivVal; - uint32_t mcgOut; - - /* Check MCG is in FBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) - { - return kMcgErrNotInFbeMode; /* return error code */ - } - - /* get curretn frdiv value */ - frDivVal = CLOCK_HAL_GetFllExternalRefDivider(baseAddr); - - /* The FLL ref clk divide value depends on FRDIV and the RANGE value */ - if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow) - { - fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal)); - } - else - { - fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal)); - } - - /* Check resulting FLL frequency */ - /* FLL reference frequency calculated from ext ref freq and FRDIV */ - mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq); - if (mcgOut < kMcgErrMax) - { - return mcgOut; /* If error code returned, return the code to calling function */ - } - - /* Clear CLKS field to switch CLKS mux to select FLL output */ - CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelOut); - - /* Wait for clock status bits to show clock source is FLL */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) - { - break; // jump out early if CLKST shows FLL selected before loop finishes - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) - { - return kMcgErrClkst0; // check FLL is really selected and return with error if not - } - - /* Now in FEE mode */ - return mcgOut; -} /* CLOCK_HAL_SetFbeToFeeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbeToFeiMode - * Description : Mode transition FBE to FEI mode - * This function transitions the MCG from FBE mode to FEI mode. - * - * Parameters: ircFreq - internal reference clock frequency value (slow) - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToFeiMode(uint32_t baseAddr, uint32_t ircFreq) -{ - uint16_t i; - uint32_t mcgOut; - - /* Check MCG is in FBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) - { - return kMcgErrNotInFbeMode; /* return error code */ - } - - /* Check IRC frequency is within spec. */ - if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) - { - return kMcgErrIrcSlowRange; - } - - /* Check resulting FLL frequency */ - mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq); - if (mcgOut < kMcgErrMax) - { - /* If error code returned, return the code to calling function */ - return mcgOut; - } - - /* - * Ensure clock monitor is disabled before switching to FEI otherwise - * a loss of clock will trigger. This assumes OSC0 is used as the external clock source. - */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); - - // Move to FEI by setting CLKS to 0 and enabling the slow IRC as the FLL reference clock - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); - - /* wait for Reference clock to switch to internal reference */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) - { - break; /* jump out early if IREFST sets before loop finishes */ - } - } - - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout; - } - - /* Wait for clock status bits to show clock source is FLL output */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) - { - /* jump out early if CLKST shows FLL output slected before loop finishes */ - break; - } - } - - /* check FLL output is really selected */ - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) - { - /* return with error if not */ - return kMcgErrClkst0; - } - - /* Now in FEI mode */ - return mcgOut; -} /* CLOCK_HAL_SetFbeToFeiMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbeToFbiMode - * Description : Mode transition FBE to FBI mode - * This function transitions the MCG from FBE mode to FBI mode. - * - * Parameters: ircFreq - internal reference clock frequency value - * ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) -{ - uint8_t fcrDivVal; - uint16_t i; - - /* Check MCG is in FBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) - { - return kMcgErrNotInFbeMode; /* return error code */ - } - - /* Check that the irc frequency matches the selected IRC */ - if (!(ircSelect)) - { - if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) - { - return kMcgErrIrcSlowRange; - } - } - else - { - if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000)) - { - return kMcgErrIrcFastRange; - } /* Fast IRC freq */ - } - - /* Select the required IRC */ - CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect); - - /* Make sure the clock monitor is disabled before switching modes otherwise it will trigger */ - CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); - - /* Select the IRC as the CLKS mux selection */ - CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelInternal, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); - - /* wait until internal reference switches to requested irc. */ - if (ircSelect == kMcgInternalRefClkSelSlow) - { - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatSlow) - { - break; /* jump out early if IRCST clears before loop finishes */ - } - } - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatSlow) - { - /* check bit is really clear and return with error if set */ - return kMcgErrIrcstClearTimeout; - } - } - else - { - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatFast) - { - break; /* jump out early if IRCST sets before loop finishes */ - } - } - if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatFast) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout1; - } - } - - /* Wait for clock status bits to update */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) - { - break; /* jump out early if CLKST shows IRC slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef) - { - return kMcgErrClkst1; /* check IRC is really selected and return with error if not */ - } - - /* wait for Reference clock Status bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) - { - break; /* jump out early if IREFST sets before loop finishes */ - } - } - - if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) - { - /* check bit is really set and return with error if not set */ - return kMcgErrIrefstSetTimeout; - } - - /* Now in FBI mode */ - if (ircSelect == kMcgInternalRefClkSelFast) - { - fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); - - return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ - } - else - { - return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ - } -} /* CLOCK_HAL_SetFbeToFbiMode */ - -#if FSL_FEATURE_MCG_HAS_PLL - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbeToPbeMode - * Description : Mode transition FBE to PBE mode - * This function transitions the MCG from FBE mode to PBE mode. - * The function requires the desired OSC and PLL be passed in to it for compatibility - * with the future support of OSC/PLL selection - * (This function presently only supports OSC0 as PLL source) - * Parameters: crystalVal - external clock frequency in Hz - * pllcsSelect - 0 to select PLL0, non-zero to select PLL1. - * prdivVal - value to divide the external clock source by to create - * the desired PLL reference clock frequency - * vdivVal - value to multiply the PLL reference clock frequency by - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect, - uint8_t prdivVal, uint8_t vdivVal) -{ - uint16_t i; - uint32_t pllFreq; - - /* Check MCG is in FBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) - { - return kMcgErrNotInFbeMode; /* return error code */ - } - - /* - * As the external frequency (osc0) has already been checked when FBE mode was enterred - * it is not checked here. - */ - - /* Check PLL divider settings are within spec.*/ - if ((prdivVal < 1) || (prdivVal > FSL_FEATURE_MCG_PLL_PRDIV_MAX)) - { - return kMcgErrPllPrdidRange; - } - - if ((vdivVal < FSL_FEATURE_MCG_PLL_VDIV_BASE) || (vdivVal > (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31))) - { - return kMcgErrPllVdivRange; - } - - /* Check PLL reference clock frequency is within spec. */ - if (((crystalVal / prdivVal) < kMcgConstant8000000) || ((crystalVal / prdivVal) > kMcgConstant32000000)) - { - return kMcgErrPllRefClkRange; - } - - /* Check PLL output frequency is within spec. */ - pllFreq = (crystalVal / prdivVal) * vdivVal; - if ((pllFreq < kMcgConstant180000000) || (pllFreq > kMcgConstant360000000)) - { - return kMcgErrPllOutClkRange; - } - -#if FSL_FEATURE_MCG_HAS_PLL1 - /* set pllcsSelect */ - CLOCK_HAL_SetPllcs(pllcsSelect); - - if (pllcsSelect == kMcgPllcsSelectPll0) -#endif - { - /* - * Configure MCG_C5 - * If the PLL is to run in STOP mode then the PLLSTEN bit needs - * to be OR'ed in here or in user code. - */ - - CLOCK_HAL_SetPllExternalRefDivider0(baseAddr, prdivVal - 1); - - /* - * Configure MCG_C6 - * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk - * The clock monitor is not enabled here as it has likely been enabled previously and - * so the value of CME is not altered here. - * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit in MCG_C6 - */ - - CLOCK_HAL_SetVoltCtrlOscDivider0(baseAddr, vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); - CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelPllClkSel); - - // wait for PLLST status bit to set - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) - { - /* return with error if not set */ - return kMcgErrPllstSetTimeout; - } - - /* Wait for LOCK bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked) - { - /* jump out early if LOCK sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked)) - { - /* return with error if not set */ - return kMcgErrPllLockBit; - } - -#if FSL_FEATURE_MCG_USE_PLLREFSEL - /* wait for PLLCST status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll0) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll0) - { - /* return with error if not set */ - return kMcgErrPllcst; - } -#endif - } -#if FSL_FEATURE_MCG_HAS_PLL1 - else - { - /* - * Configure MCG_C11 - * If the PLL is to run in STOP mode - * then the PLLSTEN bit needs to be OR'ed in here or in user code. - */ - CLOCK_HAL_SetPrdiv1(prdivVal - 1); - - /* - * Configure MCG_C12 - * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk - * The clock monitor is not enabled here as it has likely been enabled previously - * and so the value of CME is not altered here. - * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit - * in MCG_C12 - */ - - CLOCK_HAL_SetVdiv1(vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); - CLOCK_HAL_SetPllSelMode(kMcgPllSelPllClkSel); - - // wait for PLLST status bit to set - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) - { - /* return with error if not set */ - return kMcgErrPllstSetTimeout; - } - - /* Wait for LOCK bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked) - { - /* jump out early if LOCK sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked)) - { - /* return with error if not set */ - return kMcgErrPllLockBit; - } - - /* wait for PLLCST status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll1) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll1) - { - /* return with error if not set */ - return kMcgErrPllcst; - } - } -#endif /* PLL1 is selected */ - - /* now in PBE */ - - /* MCGOUT frequency equals external clock frequency */ - return crystalVal; -} /* CLOCK_HAL_SetFbeToPbeMode */ -#endif - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetFbeToBlpeMode - * Description : Mode transition FBE to BLPE mode - * This function transitions the MCG from FBE mode to BLPE mode. - * - * Parameters: crystalVal - external clock frequency in Hz - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal) -{ - /* Check MCG is in FBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) - { - return kMcgErrNotInFbeMode; /* return error code */ - } - - /* To move from FBE to BLPE the LP bit must be set */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower); - - /* now in FBE mode */ - - /* MCGOUT frequency equals external clock frequency */ - return crystalVal; -} /* CLOCK_HAL_SetFbeToBlpeMode */ - -#if FSL_FEATURE_MCG_HAS_PLL - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetPbeToFbeMode - * Description : Mode transition PBE to FBE mode - * This function transitions the MCG from PBE mode to FBE mode. - * - * Parameters: crystalVal - external clock frequency in Hz - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetPbeToFbeMode(uint32_t baseAddr, uint32_t crystalVal) -{ - int16_t i; - - /* Check MCG is in PBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE) - { - return kMcgErrNotInPbeMode; /* return error code */ - } - - /* - * As we are running from the ext clock, by default the external clock settings are valid - * To move to FBE from PBE simply requires the switching of the PLLS mux to disable the PLL - */ - - CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelFll); - - /* wait for PLLST status bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) - { - /* jump out early if PLLST clears before loop finishes */ - break; - } - } - - /* check bit is really clear */ - if (CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatFll) - { - /* return with error if not clear */ - return kMcgErrPllstClearTimeout; - } - - /* Now in FBE mode */ - - /* MCGOUT frequency equals external clock frequency */ - return crystalVal; -} /* CLOCK_HAL_SetPbeToFbeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetPbeToPeeMode - * Description : Mode transition PBE to PEE mode - * This function transitions the MCG from PBE mode to PEE mode. - * - * Parameters: crystalVal - external clock frequency in Hz - * pllcsSelect - PLLCS select setting - * mcg_pll_clk_select_t is defined in fsl_mcg_hal.h - * 0: kMcgPllcsSelectPll0 PLL0 output clock is selected - * 1: kMcgPllcsSelectPll1 PLL1 output clock is selected - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetPbeToPeeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect) -{ - uint8_t prDiv, vDiv; - uint16_t i; - uint32_t mcgOut; - - /* Check MCG is in PBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE) - { - return kMcgErrNotInPbeMode; /* return error code */ - } - - /* As the PLL settings have already been checked when PBE mode was enterred they are not checked here */ - - /* Check the PLL state before transitioning to PEE mode */ - -#if FSL_FEATURE_MCG_HAS_PLL1 - /* Check the selected PLL state before transitioning to PEE mode */ - if (pllcsSelect == kMcgPllcsSelectPll1) - { - /* Check LOCK bit is set before transitioning MCG to PLL output */ - /* already checked in fbe_pbe but good practice to re-check before switch to use PLL */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked) - { - /* jump out early if LOCK sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked)) - { - /* return with error if not set */ - return kMcgErrPllLockBit; - } - - /* Use actual PLL settings to calculate PLL frequency */ - prDiv = (CLOCK_HAL_GetPrdiv1(baseAddr) + 1); - vDiv = (CLOCK_HAL_GetVdiv1(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE); - } - else -#endif - { - /* Check LOCK bit is set before transitioning MCG to PLL output */ - /* already checked in fbe_pbe but good practice to re-check before switch to use PLL */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked) - { - /* jump out early if LOCK sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked)) - { - /* return with error if not set */ - return kMcgErrPllLockBit; - } - - /* Use actual PLL settings to calculate PLL frequency */ - prDiv = (CLOCK_HAL_GetPllExternalRefDivider0(baseAddr) + 1); - vDiv = (CLOCK_HAL_GetVoltCtrlOscDivider0(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE); - } - - /* clear CLKS to switch CLKS mux to select PLL as MCG_OUT */ - CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelOut); - - /* Wait for clock status bits to update */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatPll) - { - break; /* jump out early if CLKST = 3 before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatPll) - { - return kMcgErrClkst3; /* check CLKST is set correctly and return with error if not */ - } - - /* Now in PEE */ - - /* MCGOUT equals PLL output frequency with any special divider */ - mcgOut = (crystalVal / prDiv) * vDiv; - - return mcgOut; -} /* CLOCK_HAL_SetPbeToPeeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetPbeToBlpeMode - * Description : Mode transition PBE to BLPE mode - * This function transitions the MCG from PBE mode to BLPE mode. - * - * Parameters: crystalVal - external clock frequency in Hz - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetPbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal) -{ - /* Check MCG is in PBE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE) - { - return kMcgErrNotInPbeMode; /* return error code */ - } - - /* To enter BLPE mode the LP bit must be set, disabling the PLL */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower); - - /* Now in BLPE mode */ - return crystalVal; -} /* CLOCK_HAL_SetPbeToBlpeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetPeeToPbeMode - * Description : Mode transition PEE to PBE mode - * This function transitions the MCG from PEE mode to PBE mode. - * - * Parameters: crystalVal - external clock frequency in Hz - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetPeeToPbeMode(uint32_t baseAddr, uint32_t crystalVal) -{ - uint16_t i; - - /* Check MCG is in PEE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePEE) - { - return kMcgErrNotInPeeMode; /* return error code */ - } - - /* - * As we are running from the PLL by default the PLL and external clock settings are valid - * To move to PBE from PEE simply requires the switching of the CLKS mux to select the ext clock - */ - /* As CLKS is already 0 the CLKS value can simply be OR'ed into the register */ - CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelExternal); - - /* Wait for clock status bits to update */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) - { - break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ - } - } - - if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) - { - return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ - } - - /* Now in PBE mode */ - return crystalVal; /* MCGOUT frequency equals external clock frequency */ -} /* CLOCK_HAL_SetPeeToPbeMode */ - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetBlpeToPbeMode - * Description : Mode transition BLPE to PBE mode - * This function transitions the MCG from BLPE mode to PBE mode. - * The function requires the desired OSC and PLL be passed in to it for compatibility - * with the future support of OSC/PLL selection - * (This function presently only supports OSC0 as PLL source) - * Parameters: crystalVal - external clock frequency in Hz - * pllcsSelect - 0 to select PLL0, non-zero to select PLL1. - * prdivVal - value to divide the external clock source by to create - * the desired PLL reference clock frequency - * vdivVal - value to multiply the PLL reference clock frequency by - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetBlpeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect, uint8_t prdivVal, uint8_t vdivVal) -{ - uint16_t i; - uint32_t pllFreq; - - /* Check MCG is in BLPE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPE) - { - return kMcgErrNotInBlpeMode; /* return error code */ - } - - /* - * As the external frequency (osc0) has already been checked when FBE mode was enterred - * it is not checked here. - */ - - /* Check PLL divider settings are within spec.*/ - if ((prdivVal < 1) || (prdivVal > FSL_FEATURE_MCG_PLL_PRDIV_MAX)) - { - return kMcgErrPllPrdidRange; - } - - if ((vdivVal < FSL_FEATURE_MCG_PLL_VDIV_BASE) || (vdivVal > (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31))) - { - return kMcgErrPllVdivRange; - } - - /* Check PLL reference clock frequency is within spec. */ - if (((crystalVal / prdivVal) < kMcgConstant8000000) || ((crystalVal / prdivVal) > kMcgConstant32000000)) - { - return kMcgErrPllRefClkRange; - } - - /* Check PLL output frequency is within spec. */ - pllFreq = (crystalVal / prdivVal) * vdivVal; - if ((pllFreq < kMcgConstant180000000) || (pllFreq > kMcgConstant360000000)) - { - return kMcgErrPllOutClkRange; - } - -#if FSL_FEATURE_MCG_HAS_PLL1 - /* set pllcsSelect */ - CLOCK_HAL_SetPllcs(pllcsSelect); - - if (pllcsSelect == kMcgPllcsSelectPll0) -#endif - { - /* - * Configure MCG_C5 - * If the PLL is to run in STOP mode then the PLLSTEN bit needs - * to be OR'ed in here or in user code. - */ - - CLOCK_HAL_SetPllExternalRefDivider0(baseAddr, prdivVal - 1); - - /* - * Configure MCG_C6 - * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk - * The clock monitor is not enabled here as it has likely been enabled previously and - * so the value of CME is not altered here. - * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit in MCG_C6 - */ - - CLOCK_HAL_SetVoltCtrlOscDivider0(baseAddr, vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); - CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelPllClkSel); - - /* Set LP bit to enable the PLL */ - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); - - // wait for PLLST status bit to set - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) - { - /* return with error if not set */ - return kMcgErrPllstSetTimeout; - } - - /* Wait for LOCK bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked) - { - /* jump out early if LOCK sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked)) - { - /* return with error if not set */ - return kMcgErrPllLockBit; - } - -#if FSL_FEATURE_MCG_USE_PLLREFSEL - /* wait for PLLCST status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll0) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll0) - { - /* return with error if not set */ - return kMcgErrPllcst; - } -#endif - } -#if FSL_FEATURE_MCG_HAS_PLL1 - else - { - /* - * Configure MCG_C11 - * If the PLL is to run in STOP mode - * then the PLLSTEN bit needs to be OR'ed in here or in user code. - */ - CLOCK_HAL_SetPrdiv1(prdivVal - 1); - - /* - * Configure MCG_C12 - * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk - * The clock monitor is not enabled here as it has likely been enabled previously - * and so the value of CME is not altered here. - * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit - * in MCG_C12 - */ - - CLOCK_HAL_SetVdiv1(vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); - CLOCK_HAL_SetPllSelMode(kMcgPllSelPllClkSel); - - /* Set LP bit to enable the PLL */ - CLOCK_HAL_SetLowPowerMode(kMcgLowPowerSelNormal); - - // wait for PLLST status bit to set - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) - { - /* return with error if not set */ - return kMcgErrPllstSetTimeout; - } - - /* Wait for LOCK bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked) - { - /* jump out early if LOCK sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked)) - { - /* return with error if not set */ - return kMcgErrPllLockBit; - } - - /* wait for PLLCST status bit to clear */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll1) - { - /* jump out early if PLLST sets before loop finishes */ - break; - } - } - - /* check bit is really set */ - if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll1) - { - /* return with error if not set */ - return kMcgErrPllcst; - } - } -#endif /* PLL1 is selected */ - - /* now in PBE */ - - /* MCGOUT frequency equals external clock frequency */ - return crystalVal; -} /* CLOCK_HAL_SetBlpeToPbeMode */ -#endif - -/*FUNCTION****************************************************************************** - * - * Functon name : CLOCK_HAL_SetBlpeToFbeMode - * Description : Mode transition BLPE to FBE mode - * This function transitions the MCG from BLPE mode to FBE mode. - * - * Parameters: crystalVal - external reference clock frequency value - * - * Return value : MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetBlpeToFbeMode(uint32_t baseAddr, uint32_t crystalVal) -{ -#if FSL_FEATURE_MCG_HAS_PLL - uint16_t i; -#endif - - /* Check MCG is in BLPE mode */ - if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPE) - { - return kMcgErrNotInBlpeMode; /* return error code */ - } - - /* To move from BLPE to FBE the PLLS mux be set to select the FLL output*/ - /* and the LP bit must be cleared */ -#if FSL_FEATURE_MCG_HAS_PLL - CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelFll); -#endif - CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); - -#if FSL_FEATURE_MCG_HAS_PLL - /* wait for PLLST status bit to set */ - for (i = 0 ; i < kMcgConstant2000 ; i++) - { - if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) - { - /* jump out early if PLLST clears before loop finishes */ - break; - } - } - - /* check bit is really clear */ - if (CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatFll) - { - /* return with error if not clear */ - return kMcgErrPllstClearTimeout; - } -#endif - /* now in FBE mode */ - - /* MCGOUT frequency equals external clock frequency */ - return crystalVal; -} /* CLOCK_HAL_SetBlpeToFbeMode */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.h deleted file mode 100644 index bf322982f42..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.h +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (c) 2013, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_MCG_HAL_MODES_H__) -#define __FSL_MCG_HAL_MODES_H__ - -#include -#include -#include -#include "fsl_mcg_features.h" -#include "fsl_mcg_hal.h" - -//! @addtogroup mcg_hal -//! @{ - -//////////////////////////////////////////////////////////////////////////////// -// Definitions -//////////////////////////////////////////////////////////////////////////////// - -/*! @brief MCG mode definitions */ -typedef enum _mcg_modes { - kMcgModeFEI, /* FEI - FLL Engaged Internal */ - kMcgModeFEE, /* FEE - FLL Engaged External */ - kMcgModeFBI, /* FBI - FLL Bypassed Internal */ - kMcgModeFBE, /* FBE - FLL Bypassed External */ - kMcgModePEE, /* PEE - PLL Engaged External */ - kMcgModePBE, /* PBE - PLL Bypassed Enternal */ - kMcgModeBLPI, /* BLPI - Bypassed Low Power Internal */ - kMcgModeBLPE, /* BLPE - Bypassed Low Power External */ - kMcgModeSTOP, /* STOP - Stop */ - kMcgModeError /* Unknown mode */ -} mcg_modes_t; - -/*! @brief MCG mode transition API error code definitions */ -typedef enum McgModeErrorCode { - - /* MCG mode error codes */ - - kMcgErrNotInFeiMode = 0x01, /* - Not in FEI mode */ - kMcgErrNotInFeeMode = 0x02, /* - Not in FEE mode */ - kMcgErrNotInFbiMode = 0x03, /* - Not in FBI mode */ - kMcgErrNotInFbeMode = 0x04, /* - Not in FBE mode */ - kMcgErrNotInBlpiMode = 0x05, /* - Not in BLPI mode */ - kMcgErrNotInBlpeMode = 0x06, /* - Not in BLPE mode */ - kMcgErrNotInPbeMode = 0x07, /* - Not in PBE mode */ - kMcgErrNotInPeeMode = 0x08, /* - Not in PEE mode */ - - /* CLock MUX switching error codes */ - - kMcgErrIrefstClearTimeOut = 0x11, /* - IREFST did not clear within allowed time, FLL - reference did not switch over from internal to - external clock */ - kMcgErrIrefstSetTimeout = 0x12, /* - IREFST did not set within allowed time, the FLL - reference did not switch over from external to - internal clock(NEED TO CHECK IN MOVES TO FBI MODE) */ - kMcgErrIrcstClearTimeout = 0x13, /* - IRCST did not clear within allowed time, - slow IRC is not selected */ - kMcgErrIrefstSetTimeout1 = 0x14, /* - IREFST did not set within allowed time, - fast IRC is not selected */ - kMcgErrPllstClearTimeout = 0x15, /* - PLLST did not clear, PLLST did not switch to - FLL output, FLL is not running */ - kMcgErrPllstSetTimeout = 0x16, /* - PLLST did not set, PLLST did not switch to PLL - ouptut, PLL is not running */ - kMcgErrPllcst = 0x17, /* - PLLCST did not switch to the correct state, - the correct PLL is not selected as PLLS clock source */ - kMcgErrClkst0 = 0x18, /* - CLKST != 0, MCG did not switch to FLL output */ - kMcgErrClkst1 = 0x19, /* - CLKST != 1, MCG did not switch to internal reference - clock source */ - kMcgErrClkst2 = 0x1A, /* - CLKST != 2, MCG did not switch to external clock */ - kMcgErrClkst3 = 0x1B, /* - CLKST != 3, MCG did not switch to PLL */ - - /* Oscillator error codes */ - - kMcgErrOscEtalRange = 0x21, /* - external frequency is bigger than max frequency */ - kMcgErrOscXtalRange = 0x22, /* - crystal frequency outside allowed range */ - kMcgErrOscSetTimeout = 0x23, /* - OSCINIT/OSCINIT2 did not set within allowed time */ - - /* IRC and FLL error codes */ - - kMcgErrIrcSlowRange = 0x31, /* - slow IRC is outside allowed range */ - kMcgErrIrcFastRange = 0x32, /* - fast IRC is outside allowed range */ - kMcgErrFllRange0Min = 0x33, /* - FLL frequency is below minimum value for range 0 */ - kMcgErrFllRange0Max = 0x34, /* - FLL frequency is above maximum value for range 0 */ - kMcgErrFllRange1Min = 0x35, /* - FLL frequency is below minimum value for range 1 */ - kMcgErrFllRange1Max = 0x36, /* - FLL frequency is above maximum value for range 1 */ - kMcgErrFllRange2Min = 0x37, /* - FLL frequency is below minimum value for range 2 */ - kMcgErrFllRange2Max = 0x38, /* - FLL frequency is above maximum value for range 2 */ - kMcgErrFllRange3Min = 0x39, /* - FLL frequency is below minimum value for range 3 */ - kMcgErrFllRange3Max = 0x3A, /* - FLL frequency is above maximum value for range 3 */ - kMcgErrFllDrstDrsRange = 0x3B, /* - DRS is out of range */ - - kMcgErrFllFreqency = 0x3C, - - /* PLL error codes */ - - kMcgErrPllPrdidRange = 0x41, /* - PRDIV outside allowed range */ - kMcgErrPllVdivRange = 0x42, /* - VDIV outside allowed range */ - kMcgErrPllRefClkRange = 0x43, /* - PLL reference clock frequency, out of allowed range */ - kMcgErrPllLockBit = 0x44, /* - LOCK or LOCK2 bit did not set */ - kMcgErrPllOutClkRange = 0x45, /* - PLL output frequency is outside allowed range (NEED - TO ADD THIS CHECK TO fbe_pbe and blpe_pbe) only in - fei-pee at this time */ - kMcgErrMax = 0x1000 -} mcg_mode_error_code_t; - -//////////////////////////////////////////////////////////////////////////////// -// API -//////////////////////////////////////////////////////////////////////////////// - -#if defined(__cplusplus) -extern "C" { -#endif // __cplusplus - -/*! - * @brief Gets the current MCG mode. - * - * This is an internal function that checks the MCG registers and determine - * the current MCG mode - * - * @param baseAddr Base address for current MCG instance. - * @return mcgMode Current MCG mode or error code mcg_modes_t - */ -mcg_modes_t CLOCK_HAL_GetMcgMode(uint32_t baseAddr); - -/*! - * @brief Checks the FLL frequency integrity. - * - * This function calculates and checks the FLL frequency value based on input value. - * - * @param baseAddr Base address for current MCG instance. - * @param fllRef - FLL reference clock in Hz. - * - * @return value FLL output frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_GetFllFrequency(uint32_t baseAddr, int32_t fllRef); - -/*! - * @brief Mode transition FEI to FEE mode - * - * This function transitions the MCG from FEI mode to FEE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * @param crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * @param hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * @param erefsVal - selects external clock (=0) or crystal OSC (=1) - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFeiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, - uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, - mcg_external_ref_clock_select_t erefsVal); - -/*! - * @brief Mode transition FEI to FBI mode - * - * This function transitions the MCG from FEI mode to FBI mode. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value - * @param ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFeiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, - mcg_internal_ref_clock_select_t ircSelect); - -/*! - * @brief Mode transition FEI to FBE mode - * - * This function transitions the MCG from FEI mode to FBE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * @param crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * @param hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * @param erefsVal - selects external clock (=0) or crystal OSC (=1) - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFeiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, - uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, - mcg_external_ref_clock_select_t erefsVal); - -/*! - * @brief Mode transition FEE to FEI mode - * - * This function transitions the MCG from FEE mode to FEI mode. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value (slow) - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFeeToFeiMode(uint32_t baseAddr, uint32_t ircFreq); - -/*! - * @brief Mode transition FEE to FBI mode - * - * This function transitions the MCG from FEE mode to FBI mode. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value - * @param ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFeeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, - mcg_internal_ref_clock_select_t ircSelect); - -/*! - * @brief Mode transition FEE to FBE mode - * - * This function transitions the MCG from FEE mode to FBE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external reference clock frequency value - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFeeToFbeMode(uint32_t baseAddr, uint32_t crystalVal); - -/*! - * @brief Mode transition FBI to FEI mode - * - * This function transitions the MCG from FBI mode to FEI mode. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value (slow) - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbiToFeiMode(uint32_t baseAddr, uint32_t ircFreq); - -/*! - * @brief Mode transition FBI to FEE mode - * - * This function transitions the MCG from FBI mode to FEE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * @param crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * @param hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * @param erefsVal - selects external clock (=0) or crystal OSC (=1) - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, - uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, - mcg_external_ref_clock_select_t erefsVal); - -/*! - * @brief Mode transition FBI to FBE mode - * - * This function transitions the MCG from FBI mode to FBE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param oscselVal - oscillator selection value - * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M - * @param crystalVal - external clock frequency in Hz - * oscselVal - 0 - * erefsVal - 0: osc0 external clock frequency - * erefsVal - 1: osc0 crystal clock frequency - * oscselVal - 1: RTC 32Khz clock source frequency - * oscselVal - 2: IRC 48Mhz clock source frequency - * @param hgoVal - selects whether low power or high gain mode is selected - * for the crystal oscillator. This value is only valid when - * oscselVal is 0 and erefsVal is 1. - * @param erefsVal - selects external clock (=0) or crystal OSC (=1) - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, - uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, - mcg_external_ref_clock_select_t erefsVal); - -/*! - * @brief Mode transition FBI to BLPI mode - * - * This function transitions the MCG from FBI mode to BLPI mode.This is - * achieved by setting the MCG_C2[LP] bit. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value - * @param ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbiToBlpiMode(uint32_t baseAddr, uint32_t ircFreq, - mcg_internal_ref_clock_select_t ircSelect); - -/*! - * @brief Mode transition BLPI to FBI mode - * - * This function transitions the MCG from BLPI mode to FBI mode.This is - * achieved by clearing the MCG_C2[LP] bit. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value - * @param ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetBlpiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, uint8_t ircSelect); - -/*! - * @brief Mode transition FBE to FEE mode - * - * This function transitions the MCG from FBE mode to FEE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external reference clock frequency value - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbeToFeeMode(uint32_t baseAddr, uint32_t crystalVal); - -/*! - * @brief Mode transition FBE to FEI mode - * - * This function transitions the MCG from FBE mode to FEI mode. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value (slow) - * - * @return value MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToFeiMode(uint32_t baseAddr, uint32_t ircFreq); - -/*! - * @brief Mode transition FBE to FBI mode - * - * This function transitions the MCG from FBE mode to FBI mode. - * - * @param baseAddr Base address for current MCG instance. - * @param ircFreq - internal reference clock frequency value - * @param ircSelect - slow or fast clock selection - * 0: slow, 1: fast - * - * @return value MCGCLKOUT frequency (Hz) or error code - *END***********************************************************************************/ -uint32_t CLOCK_HAL_SetFbeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, - mcg_internal_ref_clock_select_t ircSelect); - -/*! - * @brief Mode transition FBE to PBE mode - * - * This function transitions the MCG from FBE mode to PBE mode. - * The function requires the desired OSC and PLL be passed in to it for compatibility - * with the future support of OSC/PLL selection - * (This function presently only supports OSC0 as PLL source) - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * @param pllcsSelect - 0 to select PLL0, non-zero to select PLL1. - * @param prdivVal - value to divide the external clock source by to create - * the desired PLL reference clock frequency - * @param vdivVal - value to multiply the PLL reference clock frequency by - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, - mcg_pll_clk_select_t pllcsSelect, - uint8_t prdivVal, uint8_t vdivVal); - -/*! - * @brief Mode transition FBE to BLPE mode - * - * This function transitions the MCG from FBE mode to BLPE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetFbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal); - -/*! - * @brief Mode transition PBE to FBE mode - * - * This function transitions the MCG from PBE mode to FBE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetPbeToFbeMode(uint32_t baseAddr, uint32_t crystalVal); - -/*! - * @brief Mode transition PBE to PEE mode - * - * This function transitions the MCG from PBE mode to PEE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * @param pllcsSelect - PLLCS select setting - * mcg_pll_clk_select_t is defined in fsl_mcg_hal.h - * 0: kMcgPllcsSelectPll0 PLL0 output clock is selected - * 1: kMcgPllcsSelectPll1 PLL1 output clock is selected - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetPbeToPeeMode(uint32_t baseAddr, uint32_t crystalVal, - mcg_pll_clk_select_t pllcsSelect); - -/*! - * @brief Mode transition PBE to BLPE mode - * - * This function transitions the MCG from PBE mode to BLPE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetPbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal); - -/*! - * @brief Mode transition PEE to PBE mode - * - * This function transitions the MCG from PEE mode to PBE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetPeeToPbeMode(uint32_t baseAddr, uint32_t crystalVal); - -/*! - * @brief Mode transition BLPE to PBE mode - * - * This function transitions the MCG from BLPE mode to PBE mode. - * The function requires the desired OSC and PLL be passed in to it for compatibility - * with the future support of OSC/PLL selection - * (This function presently only supports OSC0 as PLL source) - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external clock frequency in Hz - * @param pllcsSelect - 0 to select PLL0, non-zero to select PLL1. - * @param prdivVal - value to divide the external clock source by to create - * the desired PLL reference clock frequency - * @param vdivVal - value to multiply the PLL reference clock frequency by - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetBlpeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, - mcg_pll_clk_select_t pllcsSelect, - uint8_t prdivVal, uint8_t vdivVal); - -/*! - * @brief Mode transition BLPE to FBE mode - * - * This function transitions the MCG from BLPE mode to FBE mode. - * - * @param baseAddr Base address for current MCG instance. - * @param crystalVal - external reference clock frequency value - * - * @return value MCGCLKOUT frequency (Hz) or error code - */ -uint32_t CLOCK_HAL_SetBlpeToFbeMode(uint32_t baseAddr, uint32_t crystalVal); - -#if defined(__cplusplus) -} -#endif // __cplusplus - -//! @} - -#endif // __FSL_MCG_HAL_MODES_H__ -//////////////////////////////////////////////////////////////////////////////// -// EOF -//////////////////////////////////////////////////////////////////////////////// diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_features.h deleted file mode 100644 index df0b9eda0ad..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_features.h +++ /dev/null @@ -1,146 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_MPU_FEATURES_H__) -#define __FSL_MPU_FEATURES_H__ - -#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) - /* @brief Specifies number of descriptors available. */ - #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) - /* @brief Has process identifier support. */ - #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) - /* @brief Has master 0. */ - #define FSL_FEATURE_MPU_HAS_MASTER0 (1) - /* @brief Has master 1. */ - #define FSL_FEATURE_MPU_HAS_MASTER1 (1) - /* @brief Has master 2. */ - #define FSL_FEATURE_MPU_HAS_MASTER2 (1) - /* @brief Has master 3. */ - #define FSL_FEATURE_MPU_HAS_MASTER3 (0) - /* @brief Has master 4. */ - #define FSL_FEATURE_MPU_HAS_MASTER4 (1) - /* @brief Has master 5. */ - #define FSL_FEATURE_MPU_HAS_MASTER5 (1) - /* @brief Has master 6. */ - #define FSL_FEATURE_MPU_HAS_MASTER6 (0) - /* @brief Has master 7. */ - #define FSL_FEATURE_MPU_HAS_MASTER7 (0) -#elif defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Specifies number of descriptors available. */ - #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) - /* @brief Has process identifier support. */ - #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) - /* @brief Has master 0. */ - #define FSL_FEATURE_MPU_HAS_MASTER0 (1) - /* @brief Has master 1. */ - #define FSL_FEATURE_MPU_HAS_MASTER1 (1) - /* @brief Has master 2. */ - #define FSL_FEATURE_MPU_HAS_MASTER2 (1) - /* @brief Has master 3. */ - #define FSL_FEATURE_MPU_HAS_MASTER3 (1) - /* @brief Has master 4. */ - #define FSL_FEATURE_MPU_HAS_MASTER4 (1) - /* @brief Has master 5. */ - #define FSL_FEATURE_MPU_HAS_MASTER5 (1) - /* @brief Has master 6. */ - #define FSL_FEATURE_MPU_HAS_MASTER6 (0) - /* @brief Has master 7. */ - #define FSL_FEATURE_MPU_HAS_MASTER7 (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Specifies number of descriptors available. */ - #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) - /* @brief Has process identifier support. */ - #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) - /* @brief Has master 0. */ - #define FSL_FEATURE_MPU_HAS_MASTER0 (1) - /* @brief Has master 1. */ - #define FSL_FEATURE_MPU_HAS_MASTER1 (1) - /* @brief Has master 2. */ - #define FSL_FEATURE_MPU_HAS_MASTER2 (1) - /* @brief Has master 3. */ - #define FSL_FEATURE_MPU_HAS_MASTER3 (1) - /* @brief Has master 4. */ - #define FSL_FEATURE_MPU_HAS_MASTER4 (1) - /* @brief Has master 5. */ - #define FSL_FEATURE_MPU_HAS_MASTER5 (1) - /* @brief Has master 6. */ - #define FSL_FEATURE_MPU_HAS_MASTER6 (1) - /* @brief Has master 7. */ - #define FSL_FEATURE_MPU_HAS_MASTER7 (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Specifies number of descriptors available. */ - #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (16) - /* @brief Has process identifier support. */ - #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) - /* @brief Has master 0. */ - #define FSL_FEATURE_MPU_HAS_MASTER0 (1) - /* @brief Has master 1. */ - #define FSL_FEATURE_MPU_HAS_MASTER1 (1) - /* @brief Has master 2. */ - #define FSL_FEATURE_MPU_HAS_MASTER2 (1) - /* @brief Has master 3. */ - #define FSL_FEATURE_MPU_HAS_MASTER3 (1) - /* @brief Has master 4. */ - #define FSL_FEATURE_MPU_HAS_MASTER4 (1) - /* @brief Has master 5. */ - #define FSL_FEATURE_MPU_HAS_MASTER5 (1) - /* @brief Has master 6. */ - #define FSL_FEATURE_MPU_HAS_MASTER6 (0) - /* @brief Has master 7. */ - #define FSL_FEATURE_MPU_HAS_MASTER7 (0) -#else - #define MBED_NO_MPU -#endif - -#endif /* __FSL_MPU_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c deleted file mode 100644 index 7b3bc7f1e05..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_mpu_hal.h" - -#ifndef MBED_NO_MPU - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Variables - *******************************************************************************/ - -/******************************************************************************* - * Code - *******************************************************************************/ - -/******************************************************************************* - * EOF - *******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : MPU_HAL_Init - * Description : Initialize MPU module and all regoins will be invalid after cleared access permission. - * - *END**************************************************************************/ -void MPU_HAL_Init(uint32_t baseAddr) -{ - uint32_t i; - - MPU_HAL_Disable(baseAddr); - - for(i = 1; i < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; i++) - { - MPU_HAL_SetRegionStartAddr(baseAddr, (mpu_region_num)i, (uint32_t)0); - - MPU_HAL_SetRegionEndAddr(baseAddr, (mpu_region_num)i, (uint32_t)0); - } -} - -#endif /* MBED_NO_MPU */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h deleted file mode 100644 index c26fdcea8ff..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h +++ /dev/null @@ -1,1545 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_MPU_HAL_H__ -#define __FSL_MPU_HAL_H__ - -#include -#include -#include -#include "fsl_mpu_features.h" -#include "fsl_device_registers.h" - -#ifndef MBED_NO_MPU - -#define MPU_REGION_NUMBER 12 - -/*! - * @addtogroup mpu_hal - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @brief MPU region number region0~region11. */ -typedef enum _mpu_region_num{ - kMPURegionNum00 = 0U, /*!< MPU region number 0*/ - kMPURegionNum01 = 1U, /*!< MPU region number 1*/ - kMPURegionNum02 = 2U, /*!< MPU region number 2*/ - kMPURegionNum03 = 3U, /*!< MPU region number 3*/ - kMPURegionNum04 = 4U, /*!< MPU region number 4*/ - kMPURegionNum05 = 5U, /*!< MPU region number 5*/ - kMPURegionNum06 = 6U, /*!< MPU region number 6*/ - kMPURegionNum07 = 7U, /*!< MPU region number 7*/ - kMPURegionNum08 = 8U, /*!< MPU region number 8*/ - kMPURegionNum09 = 9U, /*!< MPU region number 9*/ - kMPURegionNum10 = 10U, /*!< MPU region number 10*/ - kMPURegionNum11 = 11U, /*!< MPU region number 11*/ -#if defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - kMPURegionNum11 = 12U, /*!< MPU region number 12*/ - kMPURegionNum11 = 13U, /*!< MPU region number 13*/ - kMPURegionNum11 = 14U, /*!< MPU region number 14*/ - kMPURegionNum11 = 15U, /*!< MPU region number 15*/ -#endif -}mpu_region_num; - -/*! @brief MPU error address register0~4. */ -typedef enum _mpu_error_addr_reg{ - kMPUErrorAddrReg00 = 0U, /*!< MPU error address register 0*/ - kMPUErrorAddrReg01 = 1U, /*!< MPU error address register 1*/ - kMPUErrorAddrReg02 = 2U, /*!< MPU error address register 2*/ - kMPUErrorAddrReg03 = 3U, /*!< MPU error address register 3*/ - kMPUErrorAddrReg04 = 4U /*!< MPU error address register 4*/ -}mpu_error_addr_reg; - -/*! @brief MPU error detail register0~4. */ -typedef enum _mpu_error_detail_reg{ - kMPUErrorDetailReg00 = 0U, /*!< MPU error detail register 0*/ - kMPUErrorDetailReg01 = 1U, /*!< MPU error detail register 1*/ - kMPUErrorDetailReg02 = 2U, /*!< MPU error detail register 2*/ - kMPUErrorDetailReg03 = 3U, /*!< MPU error detail register 3*/ - kMPUErrorDetailReg04 = 4U /*!< MPU error detail register 4*/ -}mpu_error_detail_reg; - -/*! @brief MPU access error. */ -typedef enum _mpu_error_access_type{ - kMPUReadErrorType = 0U, /*!< MPU error type---read*/ - kMPUWriteErrorType = 1U /*!< MPU error type---write*/ -}mpu_error_access_type; - -/*! @brief MPU access error attributes.*/ -typedef enum _mpu_error_attributes{ - kMPUUserModeInstructionAccess = 0U, /*!< access instruction error in user mode*/ - kMPUUserModeDataAccess = 1U, /*!< access data error in user mode*/ - kMPUSupervisorModeInstructionAccess = 2U, /*!< access instruction error in supervisor mode*/ - kMPUSupervisorModeDataAccess = 3U /*!< access data error in supervisor mode*/ -}mpu_error_attributes; - -/*! @brief access MPU in which mode. */ -typedef enum _mpu_access_mode{ - kMPUAccessInUserMode = 0U, /*!< access data or instruction in user mode*/ - kMPUAccessInSupervisorMode = 1U /*!< access data or instruction in supervisor mode*/ -}mpu_access_mode; - -/*! @brief MPU master number. */ -typedef enum _mpu_master_num{ - kMPUMaster00 = 0U, /*!< Core.*/ - kMPUMaster01 = 1U, /*!< Debugger.*/ - kMPUMaster02 = 2U, /*!< DMA.*/ - kMPUMaster03 = 3U, /*!< ENET.*/ - kMPUMaster04 = 4U, /*!< USB.*/ - kMPUMaster05 = 5U, /*!< SDHC.*/ - kMPUMaster06 = 6U, /*!< undefined.*/ - kMPUMaster07 = 7U /*!< undefined.*/ -}mpu_master_num; - -/*! @brief MPU error access control detail. */ -typedef enum _mpu_error_access_control{ - kMPUNoRegionHitError = 0U, /*!< no region hit error*/ - kMPUNoneOverlappRegionError = 1U, /*!< access single region error*/ - kMPUOverlappRegionError = 2U /*!< access overlapping region error*/ -}mpu_error_access_control; - -/*! @brief MPU access rights in supervisor mode for master0~master3. */ -typedef enum _mpu_supervisor_access_rights{ - kMPUSupervisorReadWriteExecute = 0U, /*!< R W E allowed in supervisor mode*/ - kMPUSupervisorReadExecute = 1U, /*!< R E allowed in supervisor mode*/ - kMPUSupervisorReadWrite = 2U, /*!< R W allowed in supervisor mode*/ - kMPUSupervisorEqualToUsermode = 3U /*!< access permission equal to user mode*/ -}mpu_supervisor_access_rights; - -/*! @brief MPU access rights in user mode for master0~master3. */ -typedef enum _mpu_user_access_rights{ - kMPUUserNoAccessRights = 0U, /*!< no access allowed in user mode*/ - kMPUUserExecute = 1U, /*!< E allowed in user mode*/ - kMPUUserWrite = 2U, /*!< W allowed in user mode*/ - kMPUUserWriteExecute = 3U, /*!< W E allowed in user mode*/ - kMPUUserRead = 4U, /*!< R allowed in user mode*/ - kMPUUserReadExecute = 5U, /*!< R E allowed in user mode*/ - kMPUUserReadWrite = 6U, /*!< R W allowed in user mode*/ - kMPUUserReadWriteExecute = 7U /*!< R W E allowed in user mode*/ -}mpu_user_access_rights; - -/*! @brief MPU process identifier. */ -typedef enum _mpu_process_identifier_value{ - kMPUIdentifierDisable = 0U, /*!< processor identifier disable*/ - kMPUIdentifierEnable = 1U /*!< processor identifier enable*/ -}mpu_process_identifier_value; - -/*! @brief MPU access control for master4~master7. */ -typedef enum _mpu_access_control{ - kMPUAccessDisable = 0U, /*!< Read or Write not allowed*/ - kMPUAccessEnable = 1U /*!< Read or Write allowed*/ -}mpu_access_control; - -/*! @brief MPU access type for master4~master7. */ -typedef enum _mpu_access_type{ - kMPUAccessRead = 0U, /*!< Access type is read*/ - kMPUAccessWrite = 1U /*!< Access type is write*/ -}mpu_access_type; - -/*! @brief MPU access region valid. */ -typedef enum _mpu_region_valid{ - kMPURegionInvalid = 0U, /*!< region invalid*/ - kMPURegionValid = 1U /*!< region valid*/ -}mpu_region_valid; - -/*! @brief MPU status return codes.*/ -typedef enum _MPU_status { - kStatus_MPU_Success = 0x0U, /*!< Succeed. */ - kStatus_MPU_NotInitlialized = 0x1U, /*!< MPU is not initialized yet. */ - kStatus_MPU_NullArgument = 0x2U, /*!< Argument is NULL.*/ - } mpu_status_t; - -/******************************************************************************* - ** Variables - *******************************************************************************/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name MPU HAL. - * @{ - */ - -/*! - * @brief Enables the MPU module operation - * - * @param baseAddr The MPU peripheral base address - */ -static inline void MPU_HAL_Enable(uint32_t baseAddr) -{ - BW_MPU_CESR_VLD(baseAddr, (uint8_t)true); -} - -/*! - * @brief Disables the MPU module operation - * - * @param baseAddr The MPU peripheral base address - */ -static inline void MPU_HAL_Disable(uint32_t baseAddr) -{ - BW_MPU_CESR_VLD(baseAddr, (uint8_t)false); -} - -/*! - * @brief Checks whether the MPU module is enabled - * - * @param baseAddr The MPU peripheral base address - * @retval true MPU module is enabled - * @retval false MPU module is disabled - */ -static inline bool MPU_HAL_IsEnabled(uint32_t baseAddr) -{ - return BR_MPU_CESR_VLD(baseAddr); -} - -/*! - * @brief Returns the total region number - * - * @param baseAddr The MPU peripheral base address - * @retval the number of regions - */ -static inline uint32_t MPU_HAL_GetNumberOfRegions(uint32_t baseAddr) -{ - return (BR_MPU_CESR_NRGD(baseAddr)); -} - -/*! - * @brief Returns MPU slave sports - * - * @param baseAddr The MPU peripheral base address - * @retval the number of slaves - */ -static inline uint32_t MPU_HAL_GetNumberOfSlaves(uint32_t baseAddr) -{ - return (BR_MPU_CESR_NSP(baseAddr)); -} - -/*! - * @brief Returns hardware level info - * - * @param baseAddr The MPU peripheral base address - * @retval hardware revision level - */ -static inline uint32_t MPU_HAL_GetHardwareRevisionLevel(uint32_t baseAddr) -{ - return (BR_MPU_CESR_HRL(baseAddr)); -} - -/*! - * @brief Returns hardware level info - * - * @param baseAddr The MPU peripheral base address - * @param regNum Error address register number - * @retval error access address - */ -static inline uint32_t MPU_HAL_GetErrorAccessAddr(uint32_t baseAddr, mpu_error_addr_reg regNum) -{ - assert(regNum < HW_MPU_EARn_COUNT); - return (BR_MPU_EARn_EADDR(baseAddr, regNum)); -} - -/*! - * @brief Returns error access slaves sports - * - * @param baseAddr The MPU peripheral base address - * @retval error slave sports -*/ -static inline uint8_t MPU_HAL_GetErrorSlaveSports(uint32_t baseAddr) -{ - return (BR_MPU_CESR_SPERR(baseAddr)); -} - -/*! - * @brief Returns error access address - * - * @param baseAddr The MPU peripheral base address - * @param errorDetailRegNum Error detail register number - * @retval error access type -*/ -static inline mpu_error_access_type MPU_HAL_GetErrorAccessType(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum) -{ - assert(errorDetailRegNum < HW_MPU_EDRn_COUNT); - return (mpu_error_access_type)(BR_MPU_EDRn_ERW(baseAddr, errorDetailRegNum)); -} - -/*! - * @brief Returns error access attributes - * - * @param baseAddr The MPU peripheral base address - * @param errorDetailRegNum Detail error register number - * @retval error access attributes - */ -static inline mpu_error_attributes MPU_HAL_GetErrorAttributes(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum) -{ - assert(errorDetailRegNum < HW_MPU_EDRn_COUNT); - return (mpu_error_attributes)(BR_MPU_EDRn_EATTR(baseAddr, errorDetailRegNum)); -} - -/*! - * @brief Returns error access master number - * - * @param baseAddr The MPU peripheral base address - * @param errorDetailRegNum Error register number - * @retval error master number - */ -static inline mpu_master_num MPU_HAL_GetErrorMasterNum(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum) -{ - assert(errorDetailRegNum < HW_MPU_EDRn_COUNT); - return (mpu_master_num)(BR_MPU_EDRn_EMN(baseAddr, errorDetailRegNum)); -} - -/*! - * @brief Returns error process identifier - * - * @param baseAddr The MPU peripheral base address - * @param errorDetailRegNum Error register number - * @retval error process identifier - */ -static inline uint32_t MPU_HAL_GetErrorProcessIdentifier(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum) -{ - assert(errorDetailRegNum < HW_MPU_EDRn_COUNT); - return(BR_MPU_EDRn_EPID(baseAddr, errorDetailRegNum)); -} - -/*! - * @brief Returns error access control - * - * @param baseAddr The MPU peripheral base address - * @param errorDetailRegNum Error register number - * @retval error access control - */ -static inline mpu_error_access_control MPU_HAL_GetErrorAccessControl(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum) -{ - assert(errorDetailRegNum < HW_MPU_EDRn_COUNT); - - uint32_t i = BR_MPU_EDRn_EACD(baseAddr, errorDetailRegNum); - - if(0 == i) - { - return (kMPUNoRegionHitError); - } - else if(!(i&(i-1))) - { - return (kMPUNoneOverlappRegionError); - } - else - { - return (kMPUOverlappRegionError); - } -} - -/*! - * @brief Returns the region start address - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval region start address - */ -static inline uint32_t MPU_HAL_GetRegionStartAddr(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD0_COUNT); - return (BR_MPU_RGDn_WORD0_SRTADDR(baseAddr, regionNum)<>= BP_MPU_RGDn_WORD0_SRTADDR; - BW_MPU_RGDn_WORD0_SRTADDR(baseAddr, regionNum, startAddr); -} - -/*! - * @brief Returns region end address - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval region end address - */ -static inline uint32_t MPU_HAL_GetRegionEndAddr(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD1_COUNT); - return (BR_MPU_RGDn_WORD1_ENDADDR(baseAddr, regionNum)<>= BP_MPU_RGDn_WORD0_SRTADDR; - BW_MPU_RGDn_WORD1_ENDADDR(baseAddr, regionNum, endAddr); -} - -/*! - * @brief Returns all masters access permission for a specific region - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval all masters access permission - */ -static inline uint32_t MPU_HAL_GetAllMastersAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (HW_MPU_RGDn_WORD2_RD(baseAddr, regionNum)); -} - -/*! - * @brief Sets all masters access permission for a specific region - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights All masters access rights - */ -static inline void MPU_HAL_SetAllMastersAccessRights(uint32_t baseAddr, mpu_region_num regionNum, uint32_t accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - HW_MPU_RGDn_WORD2_WR(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Gets M0 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master0 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM0SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M0SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets M0 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master0 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM0UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M0UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M0 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master0 access permission - */ -static inline void MPU_HAL_SetM0SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M0SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M0 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master0 access permission - */ -static inline void MPU_HAL_SetM0UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M0UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M0 process identifier is enabled in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m0 process identifier is enabled - * @retval false m0 process identifier is disabled - */ - -static inline bool MPU_HAL_IsM0ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDn_WORD2_M0PE(baseAddr, regionNum)); -} - -/*! - * @brief Sets the M0 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param identifierValue Process identifier value - */ -static inline void MPU_HAL_SetM0ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M0PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M1 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master1 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM1SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M1SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets M1 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master1 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM1UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M1UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M1 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master1 access permission - */ -static inline void MPU_HAL_SetM1SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M1SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M1 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master1 access permission - */ -static inline void MPU_HAL_SetM1UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M1UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether M1 process identifier enabled in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m1 process identifier is enabled - * @retval false m1 process identifier is disabled - */ -static inline bool MPU_HAL_IsM1ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDn_WORD2_M1PE(baseAddr, regionNum)); -} - -/*! - * @brief Sets the M1 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param identifierValue Process identifier value - */ -static inline void MPU_HAL_SetM1ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M1PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M2 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master2 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM2SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M2SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets M2 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master2 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM2UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M2UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M2 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master2 access permission - */ -static inline void MPU_HAL_SetM2SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M2SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M2 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master2 access permission - */ -static inline void MPU_HAL_SetM2UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M2UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M2 process identifier enabled in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m2 process identifier is enabled - * @retval false m2 process identifier is disabled - */ - -static inline bool MPU_HAL_IsM2ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDn_WORD2_M2PE(baseAddr, regionNum)); -} - -/*! - * @brief Sets the M2 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param identifierValue Process identifier value. - */ -static inline void MPU_HAL_SetM2ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M2PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M3 access permission in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master3 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM3SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M3SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets M3 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master3 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM3UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M3UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M3 access permission in supervisor mode. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessRights Master3 access permission. - */ -static inline void MPU_HAL_SetM3SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M3SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M3 access permission in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master3 access permission - */ -static inline void MPU_HAL_SetM3UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M3UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M3 process identifier enabled in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m3 process identifier is enabled - * @retval false m3 process identifier is disabled - */ - -static inline bool MPU_HAL_IsM3ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDn_WORD2_M3PE(baseAddr, regionNum)); -} - -/*! - * @brief Sets M3 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param identifierValue Process identifier value - */ -static inline void MPU_HAL_SetM3ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDn_WORD2_M3PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets the M4 access permission. - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @retval read or write permission - */ -static inline mpu_access_control MPU_HAL_GetM4AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M4RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M4WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets the M4 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @param accessControl Access permission - */ -static inline void MPU_HAL_SetM4AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDn_WORD2_M4RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDn_WORD2_M4WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Gets the M5 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @retval read or write permission - */ -static inline mpu_access_control MPU_HAL_GetM5AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M5RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M5WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets the M5 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @param accessControl Access permission - */ -static inline void MPU_HAL_SetM5AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDn_WORD2_M5RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDn_WORD2_M5WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Gets the M6 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType access type Read/Write - * @retval read or write permission - */ -static inline mpu_access_control MPU_HAL_GetM6AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M6RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M6WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets the M6 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @param accessControl Access permission - */ -static inline void MPU_HAL_SetM6AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDn_WORD2_M6RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDn_WORD2_M6WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Gets the M7 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @retval read or write permission - */ -static inline mpu_access_control MPU_HAL_GetM7AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M7RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDn_WORD2_M7WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets the M7 access permission - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessType Access type Read/Write - * @param accessControl Access permission - */ -static inline void MPU_HAL_SetM7AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDn_WORD2_M7RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDn_WORD2_M7WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Checks whether region is valid - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true region is valid - * @retval false region is invalid - */ -static inline bool MPU_HAL_IsRegionValid(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD3_COUNT); - return (1 == BR_MPU_RGDn_WORD3_VLD(baseAddr, regionNum)); -} - -/*! - * @brief Sets the region valid value - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param validValue Region valid value - */ -static inline void MPU_HAL_SetRegionValidValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_region_valid validValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD3_COUNT); - BW_MPU_RGDn_WORD3_VLD(baseAddr, regionNum, validValue); -} - -/*! - * @brief Gets the process identifier mask - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval region process identifier mask - */ -static inline uint8_t MPU_HAL_GetProcessIdentifierMask(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD3_COUNT); - return (BR_MPU_RGDn_WORD3_PIDMASK(baseAddr, regionNum)); -} - -/*! - * @brief Sets the process identifier mask - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param processIdentifierMask Process identifier mask value - */ -static inline void MPU_HAL_SetPIDMASK(uint32_t baseAddr, mpu_region_num regionNum, uint8_t processIdentifierMask) -{ - assert(regionNum < HW_MPU_RGDn_WORD3_COUNT); - BW_MPU_RGDn_WORD3_PIDMASK(baseAddr, regionNum, processIdentifierMask); -} - -/*! - * @brief Gets the process identifier - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval process identifier - */ -static inline uint8_t MPU_HAL_GetProcessIdentifier(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD3_COUNT); - return (BR_MPU_RGDn_WORD3_PID(baseAddr, regionNum)); -} - -/*! - * @brief Sets the process identifier - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param processIdentifier Process identifier - */ -static inline void MPU_HAL_SetProcessIdentifier(uint32_t baseAddr, mpu_region_num regionNum, uint8_t processIdentifier) -{ - assert(regionNum < HW_MPU_RGDn_WORD3_COUNT); - BW_MPU_RGDn_WORD3_PID(baseAddr, regionNum, processIdentifier); -} - -/*! - * @brief Gets all masters access permission from alternative register - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval all masters access permission - */ -static inline uint32_t MPU_HAL_GetAllMastersAlternateAcessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (HW_MPU_RGDAACn_RD(baseAddr, regionNum)); -} - -/*! - * @brief Sets all masters access permission through alternative register - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights All masters access permission - */ -static inline void MPU_HAL_SetAllMastersAlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, uint32_t accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - HW_MPU_RGDAACn_WR(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Gets the M0 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master0 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM0AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M0SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets the M0 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master0 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM0AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDAACn_M0UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets the M0 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master0 access permission - */ -static inline void MPU_HAL_SetM0AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M0SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets the M0 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master0 access permission - */ -static inline void MPU_HAL_SetM0AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M0UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M0 process identifier works in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m0 process identifier is enabled - * @retval false m0 process identifier is disabled - */ -static inline bool MPU_HAL_IsM0AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDAACn_M0PE(baseAddr, regionNum)); -} - -/*! - * @brief @brief Sets the M0 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param identifierValue Process identifier value - */ -static inline void MPU_HAL_SetM0AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDAACn_M0PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M1 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master1 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM1AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M1SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets M1 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval Master1 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM1AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDAACn_M1UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M1 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master1 access permission - */ -static inline void MPU_HAL_SetM1AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M1SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M1 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master1 access permission - */ -static inline void MPU_HAL_SetM1AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M1UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M1 process identifier works in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m1 process identifier is enabled - * @retval false m1 process identifier is disabled - */ -static inline bool MPU_HAL_IsM1AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDAACn_M1PE(baseAddr, regionNum)); -} - -/*! - * @brief @brief Sets M1 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param identifierValue process identifier value - */ -static inline void MPU_HAL_SetM1AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDAACn_M1PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M2 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval M2 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM2AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M2SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets the M2 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval M2 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM2AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDAACn_M2UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M2 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights M2 access permission - */ -static inline void MPU_HAL_SetM2AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M2SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M2 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights M2 access permission - */ -static inline void MPU_HAL_SetM2AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M2UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M2 process identifier works in region hit evaluation - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval true m2 process identifier is enabled - * @retval false m2 process identifier is disabled - */ -static inline bool MPU_HAL_IsM2AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDAACn_M2PE(baseAddr, regionNum)); -} - -/*! - * @brief Sets M2 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param identifierValue process identifier value - */ -static inline void MPU_HAL_SetM2AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDAACn_M2PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M3 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval M3 access permission - */ -static inline mpu_supervisor_access_rights MPU_HAL_GetM3AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M3SM(baseAddr, regionNum)); -} - -/*! - * @brief Gets M3 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @retval M3 access permission - */ -static inline mpu_user_access_rights MPU_HAL_GetM3AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - return (mpu_user_access_rights)(BR_MPU_RGDAACn_M3UM(baseAddr, regionNum)); -} - -/*! - * @brief Sets M3 access rights in supervisor mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master3 access permission - */ -static inline void MPU_HAL_SetM3AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M3SM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Sets M3 access rights in user mode - * - * @param baseAddr The MPU peripheral base address - * @param regionNum MPU region number - * @param accessRights Master3 access permission - */ -static inline void MPU_HAL_SetM3AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - BW_MPU_RGDAACn_M3UM(baseAddr, regionNum, accessRights); -} - -/*! - * @brief Checks whether the M3 process identifier works in region hit evaluation. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @retval true m3 process identifier is enabled. - * @retval false m3 process identifier is disabled. - */ -static inline bool MPU_HAL_IsM3AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - return (1 == BR_MPU_RGDAACn_M3PE(baseAddr, regionNum)); -} - -/*! - * @brief Sets M3 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param identifierValue process identifier value. - */ -static inline void MPU_HAL_SetM3AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue) -{ - assert(regionNum < HW_MPU_RGDn_WORD2_COUNT); - BW_MPU_RGDAACn_M3PE(baseAddr, regionNum, identifierValue); -} - -/*! - * @brief Gets M4 access permission from alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @retval read or write permission. - */ -static inline mpu_access_control MPU_HAL_GetM4AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDAACn_M4RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDAACn_M4WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets M4 access permission through alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @param accessControl Access permission. - */ -static inline void MPU_HAL_SetM4AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDAACn_M4RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDAACn_M4WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Gets M5 access permission from alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @retval read or write permission. - */ -static inline mpu_access_control MPU_HAL_GetM5AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDAACn_M5RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDAACn_M5WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets M5 access permission through alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @param accessControl Master5 Access permission. - */ -static inline void MPU_HAL_SetM5AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDAACn_M5RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDAACn_M5WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Gets M6 access permission from alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @retval read or write permission. - */ -static inline mpu_access_control MPU_HAL_GetM6AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDAACn_M6RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDAACn_M6WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets M6 access permission through alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @param accessControl Master6 access permission. - */ -static inline void MPU_HAL_SetM6AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDAACn_M6RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDAACn_M6WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Gets M7 access permission from alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @retval read or write permission. - */ -static inline mpu_access_control MPU_HAL_GetM7AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - return (mpu_access_control)(BR_MPU_RGDAACn_M7RE(baseAddr, regionNum)); - } - else - { - return (mpu_access_control)(BR_MPU_RGDAACn_M7WE(baseAddr, regionNum)); - } -} - -/*! - * @brief Sets M7 access permission through alternate register. - * - * @param baseAddr The MPU peripheral base address. - * @param regionNum MPU region number. - * @param accessType Access type Read/Write. - * @param accessControl Master7 access permission. - */ -static inline void MPU_HAL_SetM7AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl) -{ - assert(regionNum < HW_MPU_RGDAACn_COUNT); - if(kMPUAccessRead == accessType) - { - BW_MPU_RGDAACn_M7RE(baseAddr, regionNum, accessControl); - } - else - { - BW_MPU_RGDAACn_M7WE(baseAddr, regionNum, accessControl); - } -} - -/*! - * @brief Initializes the MPU module. - * - * @param baseAddr The MPU peripheral base address. - */ -void MPU_HAL_Init(uint32_t baseAddr); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* MBED_NO_MPU */ - -#endif /* __FSL_MPU_HAL_H__*/ -/******************************************************************************* - * EOF - *******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_features.h deleted file mode 100644 index 84fab5fde77..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_features.h +++ /dev/null @@ -1,166 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_OSC_FEATURES_H__) -#define __FSL_OSC_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) - /* @brief Has OSC1 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC1 (0) - /* @brief Has OSC0 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC0 (0) - /* @brief Has OSC external oscillator (without index). */ - #define FSL_FEATURE_OSC_HAS_OSC (1) - /* @brief Number of OSC external oscillators. */ - #define FSL_FEATURE_OSC_OSC_COUNT (1) - /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ - #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \ - defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ - defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \ - defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ - defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || \ - defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || \ - defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ - defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || \ - defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || \ - defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \ - defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \ - defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \ - defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \ - defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \ - defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \ - defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ - defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has OSC1 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC1 (0) - /* @brief Has OSC0 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC0 (1) - /* @brief Has OSC external oscillator (without index). */ - #define FSL_FEATURE_OSC_HAS_OSC (0) - /* @brief Number of OSC external oscillators. */ - #define FSL_FEATURE_OSC_OSC_COUNT (1) - /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ - #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ - defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Has OSC1 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC1 (0) - /* @brief Has OSC0 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC0 (0) - /* @brief Has OSC external oscillator (without index). */ - #define FSL_FEATURE_OSC_HAS_OSC (1) - /* @brief Number of OSC external oscillators. */ - #define FSL_FEATURE_OSC_OSC_COUNT (1) - /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ - #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has OSC1 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC1 (1) - /* @brief Has OSC0 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC0 (1) - /* @brief Has OSC external oscillator (without index). */ - #define FSL_FEATURE_OSC_HAS_OSC (0) - /* @brief Number of OSC external oscillators. */ - #define FSL_FEATURE_OSC_OSC_COUNT (2) - /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ - #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has OSC1 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC1 (0) - /* @brief Has OSC0 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC0 (0) - /* @brief Has OSC external oscillator (without index). */ - #define FSL_FEATURE_OSC_HAS_OSC (0) - /* @brief Number of OSC external oscillators. */ - #define FSL_FEATURE_OSC_OSC_COUNT (0) - /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ - #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Has OSC1 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC1 (0) - /* @brief Has OSC0 external oscillator. */ - #define FSL_FEATURE_OSC_HAS_OSC0 (0) - /* @brief Has OSC external oscillator (without index). */ - #define FSL_FEATURE_OSC_HAS_OSC (0) - /* @brief Number of OSC external oscillators. */ - #define FSL_FEATURE_OSC_OSC_COUNT (0) - /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ - #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_OSC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c deleted file mode 100644 index 428f8e041ea..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_osc_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_SetExternalRefClkCmd - * Description : Enable/disable the external reference clock - * This function will enable/disable the external reference clock output - * for oscillator - that is the OSCERCLK. This clock will be used by many - * peripherals. It should be enabled at early system init stage to ensure the - * peripherals could select it and use it. - * - *END**************************************************************************/ -void OSC_HAL_SetExternalRefClkCmd(uint32_t baseAddr, bool enable) -{ - BW_OSC_CR_ERCLKEN(baseAddr, enable); -} - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_GetExternalRefClkCmd - * Description : Get the external reference clock enable setting for osc - * This function will get the external reference clock output enable setting - * for oscillator - that is the OSCERCLK. This clock will be used by many - * peripherals. It should be enabled at early system init stage to ensure the - * peripherals could select it and use it. - * - *END**************************************************************************/ -bool OSC_HAL_GetExternalRefClkCmd(uint32_t baseAddr) -{ - return (bool)BR_OSC_CR_ERCLKEN(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_SetExternalRefClkInStopModeCmd - * Description : Enable/disable the external ref clock in stop mode - * This function will enable/disable the external reference clock (OSCERCLK) - * when MCU enters Stop mode. - * - *END**************************************************************************/ -void OSC_HAL_SetExternalRefClkInStopModeCmd(uint32_t baseAddr, bool enable) -{ - BW_OSC_CR_EREFSTEN(baseAddr, enable); -} - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_GetExternalRefClkInStopModeCmd - * Description : Get the external ref clock enable setting for osc in stop mode - * This function will get the external reference clock (OSCERCLK) setting when - * MCU enters Stop mode. - * - *END**************************************************************************/ -bool OSC_HAL_GetExternalRefClkInStopModeCmd(uint32_t baseAddr) -{ - return (bool)BR_OSC_CR_EREFSTEN(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_SetCapacitorCmd - * Description : Enable/disable the capacitor configuration for oscillator - * This function will enable/disable the specified capacitors configuration for - * oscillator. This should be done in early system level init function call - * based on system configuration. - * - *END**************************************************************************/ -void OSC_HAL_SetCapacitorCmd(uint32_t baseAddr, - osc_capacitor_config_t capacitorConfig, - bool enable) -{ - if (capacitorConfig == kOscCapacitor2p) - { - BW_OSC_CR_SC2P(baseAddr, enable); - } - else if (capacitorConfig == kOscCapacitor4p) - { - BW_OSC_CR_SC4P(baseAddr, enable); - } - else if (capacitorConfig == kOscCapacitor8p) - { - BW_OSC_CR_SC8P(baseAddr, enable); - } - else if (capacitorConfig == kOscCapacitor16p) - { - BW_OSC_CR_SC16P(baseAddr, enable); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_GetCapacitorCmd - * Description : Get the capacitor configuration for specific oscillator - * This function will get the specified capacitors configuration for the - * oscillator. - * - *END**************************************************************************/ -bool OSC_HAL_GetCapacitorCmd(uint32_t baseAddr, - osc_capacitor_config_t capacitorConfig) -{ - if (capacitorConfig == kOscCapacitor2p) - { - return (bool)BR_OSC_CR_SC2P(baseAddr); - } - else if (capacitorConfig == kOscCapacitor4p) - { - return (bool)BR_OSC_CR_SC4P(baseAddr); - } - else if (capacitorConfig == kOscCapacitor8p) - { - return (bool)BR_OSC_CR_SC8P(baseAddr); - } - else if (capacitorConfig == kOscCapacitor16p) - { - return (bool)BR_OSC_CR_SC16P(baseAddr); - } - - return 0; -} - -#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_SetExternalRefClkDivCmd - * Description : Set the external reference clock divider setting for osc - * This function will get the external reference clock divider setting - * for oscillator - that is the OSCERCLK. This clock will be used by many - * peripherals. - * - *END**************************************************************************/ -void OSC_HAL_SetExternalRefClkDivCmd(uint32_t baseAddr, uint32_t divider) -{ - BW_OSC_DIV_ERPS(baseAddr, divider); -} - -/*FUNCTION********************************************************************** - * - * Function Name : OSC_HAL_GetExternalRefClkDivCmd - * Description : Get the external reference clock divider setting for osc - * This function will get the external reference clock divider setting - * for oscillator - that is the OSCERCLK. This clock will be used by many - * peripherals. - * - *END**************************************************************************/ -uint32_t OSC_HAL_GetExternalRefClkDivCmd(uint32_t baseAddr) -{ - return BR_OSC_DIV_ERPS(baseAddr); -} -#endif - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h deleted file mode 100644 index cab94a167c4..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_OSC_HAL_H__) -#define __FSL_OSC_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_osc_features.h" - -/*! @addtogroup osc_hal*/ -/*! @{*/ - -/*! @file fsl_osc_hal.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Oscillator capacitor load configurations.*/ -typedef enum _osc_capacitor_config { - kOscCapacitor2p = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ - kOscCapacitor4p = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ - kOscCapacitor8p = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ - kOscCapacitor16p = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ -} osc_capacitor_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name oscillator control APIs*/ -/*@{*/ - - -/*! - * @brief Enables the external reference clock for the oscillator. - * - * This function enables the external reference clock output - * for the oscillator, OSCERCLK. This clock is used - * by many peripherals. It should be enabled at an early system initialization - * stage to ensure the peripherals can select and use it. - * - * @param baseAddr Oscillator register base address - * @param enable enable/disable the clock - */ -void OSC_HAL_SetExternalRefClkCmd(uint32_t baseAddr, bool enable); - -/*! - * @brief Gets the external reference clock enable setting for the oscillator. - * - * This function gets the external reference clock output enable setting - * for the oscillator , OSCERCLK. This clock is used - * by many peripherals. It should be enabled at an early system initialization - * stage to ensure the peripherals could select and use it. - * - * @param baseAddr Oscillator register base address - * @return enable clock enable/disable setting - */ -bool OSC_HAL_GetExternalRefClkCmd(uint32_t baseAddr); - -/*! - * @brief Enables/disables the external reference clock in stop mode. - * - * This function enables/disables the external reference clock (OSCERCLK) when an - * MCU enters the stop mode. - * - * @param baseAddr Oscillator register base address - * @param enable enable/disable setting - */ -void OSC_HAL_SetExternalRefClkInStopModeCmd(uint32_t baseAddr, bool enable); - -/*! - * @brief Gets the external reference clock enable setting in stop mode. - * - * This function gets the external reference clock (OSCERCLK) enable setting when an - * MCU enters stop mode. - * - * @param baseAddr Oscillator register base address - */ -bool OSC_HAL_GetExternalRefClkInStopModeCmd(uint32_t baseAddr); - -/*! - * @brief Enables the capacitor configuration for the oscillator. - * - * This function enables the specified capacitors configuration for the - * oscillator. This should be done in the early system level initialization function call - * based on the system configuration. - * - * @param baseAddr Oscillator register base address - * @param capacitorConfig Capacitor configuration. (2p, 4p, 8p, 16p) - * @param enable enable/disable the Capacitor configuration - */ -void OSC_HAL_SetCapacitorCmd(uint32_t baseAddr, - osc_capacitor_config_t capacitorConfig, - bool enable); - -/*! - * @brief Gets the capacitor configuration for a specific oscillator. - * - * This function gets the specified capacitors configuration for an - * oscillator. - * - * @param baseAddr Oscillator register base address - * @param capacitorConfig Capacitor configuration. - * @return enable enable/disable setting - */ -bool OSC_HAL_GetCapacitorCmd(uint32_t baseAddr, - osc_capacitor_config_t capacitorConfig); - -#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER -/*! - * @brief Sets the external reference clock divider. - * - * This function sets the divider for the external reference clock. - * - * @param baseAddr Oscillator register base address - * @param divider divider settings - */ -void OSC_HAL_SetExternalRefClkDivCmd(uint32_t baseAddr, uint32_t divider); - -/*! - * @brief Gets the external reference clock divider. - * - * This function gets the divider for the external reference clock. - * - * @param baseAddr Oscillator register base address - * @return divider divider settings - */ -uint32_t OSC_HAL_GetExternalRefClkDivCmd(uint32_t baseAddr); -#endif - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_OSC_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_features.h deleted file mode 100644 index c2f8e419c3b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_features.h +++ /dev/null @@ -1,87 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_PDB_FEATURES_H__) -#define __FSL_PDB_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ - defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ - defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ - defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ - defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ - defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ - defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ - defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \ - defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ - defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ - defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ - defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Define the count of supporting ADC pre-trigger for each channel. */ - #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_PDB_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c deleted file mode 100644 index 3019e1e7b2e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pdb_hal.h" - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_Init - * Description : Reset PDB's registers to a known state. This state is - * defined in Reference Manual, which is power on reset value. - * - *END*************************************************************************/ -void PDB_HAL_Init(uint32_t baseAddr) -{ - uint32_t chn, preChn; - HW_PDB_SC_WR(baseAddr, 0U); - HW_PDB_MOD_WR(baseAddr, 0xFFFFU); - HW_PDB_IDLY_WR(baseAddr, 0xFFFFU); - /* For ADC trigger. */ - for (chn = 0U; chn < HW_PDB_CHnC1_COUNT; chn++) - { - HW_PDB_CHnC1_WR(baseAddr, chn, 0U); - HW_PDB_CHnS_WR(baseAddr, chn,0xFU); - for (preChn = 0U; preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT; preChn++) - { - PDB_HAL_SetPreTriggerDelayCount(baseAddr, chn, preChn, 0U); - } - } - /* For DAC trigger. */ - for (chn = 0U; chn < HW_PDB_DACINTCn_COUNT; chn++) - { - HW_PDB_DACINTCn_WR(baseAddr, chn, 0U); - HW_PDB_DACINTn_WR(baseAddr ,chn, 0U); - } - /* For Pulse out trigger. */ - HW_PDB_POEN_WR(baseAddr, 0U); - for (chn = 0U; chn < HW_PDB_POnDLY_COUNT; chn++) - { - HW_PDB_POnDLY_WR(baseAddr, chn, 0U); - } - /* Load the setting value. */ - PDB_HAL_Enable(baseAddr); - PDB_HAL_SetLoadRegsCmd(baseAddr); - PDB_HAL_Disable(baseAddr); -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_SetPreTriggerBackToBackCmd - * Description : Switch to enable pre-trigger's back to back mode. - * - *END*************************************************************************/ -void PDB_HAL_SetPreTriggerBackToBackCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable) -{ - assert(chn < HW_PDB_CHnC1_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - - uint32_t tmp32 = HW_PDB_CHnC1_RD(baseAddr, chn); - if (enable) - { - tmp32 |= (1U << (preChn + BP_PDB_CHnC1_BB)); - } - else - { - tmp32 &= ~(1U << (preChn + BP_PDB_CHnC1_BB)); - } - HW_PDB_CHnC1_WR(baseAddr, chn, tmp32); -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_SetPreTriggerOutputCmd - * Description : Switch to enable pre-trigger's output. - * - *END*************************************************************************/ -void PDB_HAL_SetPreTriggerOutputCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable) -{ - assert(chn < HW_PDB_CHnC1_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - - uint32_t tmp32 = HW_PDB_CHnC1_RD(baseAddr, chn); - if (enable) - { - tmp32 |= (1U << (preChn + BP_PDB_CHnC1_TOS)); - } - else - { - tmp32 &= ~(1U << (preChn + BP_PDB_CHnC1_TOS)); - } - HW_PDB_CHnC1_WR(baseAddr, chn, tmp32); -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_SetPreTriggerCmd - * Description : Switch to enable pre-trigger's. - * - *END*************************************************************************/ -void PDB_HAL_SetPreTriggerCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable) -{ - assert(chn < HW_PDB_CHnC1_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - uint32_t tmp32 = HW_PDB_CHnC1_RD(baseAddr, chn); - - if (enable) - { - tmp32 |= (1U << (preChn + BP_PDB_CHnC1_EN)); - } - else - { - tmp32 &= ~(1U << (preChn + BP_PDB_CHnC1_EN)); - } - HW_PDB_CHnC1_WR(baseAddr, chn, tmp32); -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_ClearPreTriggerFlag - * Description : Clear the flag that the PDB counter reaches to the - * pre-trigger's delay value. - * - *END*************************************************************************/ -void PDB_HAL_ClearPreTriggerFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn) -{ - assert(chn < HW_PDB_CHnS_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - - /* Write 0 to clear. */ - uint32_t tmp32 = HW_PDB_CHnS_RD(baseAddr, chn); /* Get current value. */ - tmp32 &= ~(1U << (preChn + BP_PDB_CHnS_CF)); /* Update the change. */ - tmp32 &= BM_PDB_CHnS_CF; /* Limit the change range. */ - - HW_PDB_CHnS_WR(baseAddr, chn, tmp32); -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_ClearPreTriggerSeqErrFlag - * Description : Clear the flag that sequence error is detected. - * - *END*************************************************************************/ -void PDB_HAL_ClearPreTriggerSeqErrFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn) -{ - assert(chn < HW_PDB_CHnS_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - - /* Write 1 to clear. */ - uint32_t tmp32 = HW_PDB_CHnS_RD(baseAddr, chn); /* Get current value. */ - tmp32 &= ~BM_PDB_CHnS_ERR;/* Clear the operate controller. */ - tmp32 |= ( 1U << (preChn + BP_PDB_CHnS_ERR) );/* Add indicated clear operator. */ - - HW_PDB_CHnS_WR(baseAddr, chn, tmp32); -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_SetPreTriggerDelayCount - * Description : Set the delay value for pre-trigger. - * - *END*************************************************************************/ -void PDB_HAL_SetPreTriggerDelayCount(uint32_t baseAddr, uint32_t chn, uint32_t preChn, uint32_t value) -{ - assert(chn < HW_PDB_CHnDLY0_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - switch (preChn) - { - case 0U: - BW_PDB_CHnDLY0_DLY(baseAddr, chn, value); - break; -#if (FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT > 1U) - case 1U: - BW_PDB_CHnDLY1_DLY(baseAddr, chn, value); - break; -#endif /* FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT */ - default: - break; - } -} - -/*FUNCTION********************************************************************* - * - * Function Name : PDB_HAL_SetPulseOutCmd - * Description : Switch to enable the pulse-out trigger. - * - *END*************************************************************************/ -void PDB_HAL_SetPulseOutCmd(uint32_t baseAddr, uint32_t pulseChn, bool enable) -{ - assert(pulseChn < HW_PDB_POnDLY_COUNT); - - uint32_t tmp32 = HW_PDB_POEN_RD(baseAddr); - - if (enable) - { - tmp32 |= (1U << (pulseChn+BP_PDB_POEN_POEN)); - } - else - { - tmp32 &= ~(1U << (pulseChn+BP_PDB_POEN_POEN)); - } - HW_PDB_POEN_WR(baseAddr, tmp32); -} - -/****************************************************************************** - * EOF - *****************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h deleted file mode 100644 index eeec82b7cde..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h +++ /dev/null @@ -1,631 +0,0 @@ -/* - * Copyright (c) 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_PDB_HAL_H__ -#define __FSL_PDB_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_pdb_features.h" - -/*! - * @addtogroup pdb_hal - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! - * @brief PDB status return codes. - */ -typedef enum _pdb_status -{ - kStatus_PDB_Success = 0U, /*!< Success. */ - kStatus_PDB_InvalidArgument = 1U, /*!< Invalid argument existed. */ - kStatus_PDB_Failed = 2U /*!< Execution failed. */ -} pdb_status_t; - -/*! - * @brief Defines the type of value load mode for the PDB module. - * - * Some timing related registers, such as the MOD, IDLY, CHnDLYm, INTx and POyDLY, - * buffer the setting values. Only the load operation is triggered. - * The setting value is loaded from a buffer and takes effect. There are - * four loading modes to fit different applications. - */ -typedef enum _pdb_load_mode -{ - kPdbLoadImmediately = 0U, - /*!< Loaded immediately after load operation. */ - kPdbLoadAtModuloCounter = 1U, - /*!< Loaded when counter hits the modulo after load operation. */ - kPdbLoadAtNextTrigger = 2U, - /*!< Loaded when detecting an input trigger after load operation. */ - kPdbLoadAtModuloCounterOrNextTrigger = 3U - /*!< Loaded when counter hits the modulo or detecting an input trigger after load operation. */ -} pdb_load_mode_t; - -/*! - * @brief Defines the type of prescaler divider for the PDB counter clock. - */ -typedef enum _pdb_clk_prescaler_div_mode -{ - kPdbClkPreDivBy1 = 0U, /*!< Counting divided by multiplication factor selected by MULT. */ - kPdbClkPreDivBy2 = 1U, /*!< Counting divided by multiplication factor selected by 2 times ofMULT. */ - kPdbClkPreDivBy4 = 2U, /*!< Counting divided by multiplication factor selected by 4 times ofMULT. */ - kPdbClkPreDivBy8 = 3U, /*!< Counting divided by multiplication factor selected by 8 times ofMULT. */ - kPdbClkPreDivBy16 = 4U, /*!< Counting divided by multiplication factor selected by 16 times ofMULT. */ - kPdbClkPreDivBy32 = 5U, /*!< Counting divided by multiplication factor selected by 32 times ofMULT. */ - kPdbClkPreDivBy64 = 6U, /*!< Counting divided by multiplication factor selected by 64 times ofMULT. */ - kPdbClkPreDivBy128 = 7U, /*!< Counting divided by multiplication factor selected by 128 times ofMULT. */ -} pdb_clk_prescaler_div_mode_t; - -/*! - * @brief Defines the type of trigger source mode for the PDB. - * - * Selects the trigger input source for the PDB. The trigger input source can - * be internal or external (EXTRG pin), or the software trigger. - */ -typedef enum _pdb_trigger_src_mode -{ - kPdbTrigger0 = 0U, /*!< Select trigger-In 0. */ - kPdbTrigger1 = 1U, /*!< Select trigger-In 1. */ - kPdbTrigger2 = 2U, /*!< Select trigger-In 2. */ - kPdbTrigger3 = 3U, /*!< Select trigger-In 3. */ - kPdbTrigger4 = 4U, /*!< Select trigger-In 4. */ - kPdbTrigger5 = 5U, /*!< Select trigger-In 5. */ - kPdbTrigger6 = 6U, /*!< Select trigger-In 6. */ - kPdbTrigger7 = 7U, /*!< Select trigger-In 7. */ - kPdbTrigger8 = 8U, /*!< Select trigger-In 8. */ - kPdbTrigger9 = 9U, /*!< Select trigger-In 8. */ - kPdbTrigger10 = 10U, /*!< Select trigger-In 10. */ - kPdbTrigger11 = 11U, /*!< Select trigger-In 11. */ - kPdbTrigger12 = 12U, /*!< Select trigger-In 12. */ - kPdbTrigger13 = 13U, /*!< Select trigger-In 13. */ - kPdbTrigger14 = 14U, /*!< Select trigger-In 14. */ - kPdbSoftTrigger = 15U, /*!< Select software trigger. */ -} pdb_trigger_src_mode_t; - -/*! - * @brief Defines the type of the multiplication source mode for PDB. - * - * Selects the multiplication factor of the prescaler divider for the PDB counter clock. - */ -typedef enum _pdb_mult_factor_mode -{ - kPdbMultFactorAs1 = 0U, /*!< Multiplication factor is 1. */ - kPdbMultFactorAs10 = 1U, /*!< Multiplication factor is 10. */ - kPdbMultFactorAs20 = 2U, /*!< Multiplication factor is 20. */ - kPdbMultFactorAs40 = 3U /*!< Multiplication factor is 40. */ -} pdb_mult_factor_mode_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Resets the PDB registers to a known state. - * - * This function resets the PDB registers to a known state. This state is - * defined in a reference manual and is power on reset value. - * - * @param baseAddr Register base address for the module. - */ -void PDB_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Sets the load mode for timing registers. - * - * This function sets the load mode for some timing registers including - * MOD, IDLY, CHnDLYm, INTx and POyDLY. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode, see to "pdb_load_mode_t". - */ -static inline void PDB_HAL_SetLoadMode(uint32_t baseAddr, pdb_load_mode_t mode) -{ - BW_PDB_SC_LDMOD(baseAddr, (uint32_t)mode); -} - -/*! - * @brief Switches to enable the PDB sequence error interrupt. - * - * This function switches to enable the PDB sequence error interrupt. - * - * @param baseAddr Register base address for the module. - * @param enable The switcher to assert the feature. - */ -static inline void PDB_HAL_SetSeqErrIntCmd(uint32_t baseAddr, bool enabled) -{ - BW_PDB_SC_PDBEIE(baseAddr, (enabled ? 1U : 0U) ); -} - -/*! - * @brief Triggers the DAC by software if enabled. - * - * If enabled, this function triggers the DAC by using software. - * - * @param baseAddr Register base address for the module. - */ -static inline void PDB_HAL_SetSoftTriggerCmd(uint32_t baseAddr) -{ - BW_PDB_SC_SWTRIG(baseAddr, 1U); -} - -/*! - * @brief Switches to enable the PDB DMA support. - * - * This function switches to enable the PDB DMA support. - * - * @param baseAddr Register base address for the module. - * @param enable The switcher to assert the feature. - */ -static inline void PDB_HAL_SetDmaCmd(uint32_t baseAddr, bool enable) -{ - BW_PDB_SC_DMAEN(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Sets the prescaler divider from the peripheral bus clock for the PDB. - * - * This function sets the prescaler divider from the peripheral bus clock for the PDB. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode, see to "pdb_clk_prescaler_div_mode_t". - */ -static inline void PDB_HAL_SetPreDivMode(uint32_t baseAddr, pdb_clk_prescaler_div_mode_t mode) -{ - BW_PDB_SC_PRESCALER(baseAddr, (uint32_t)mode); -} - -/*! - * @brief Sets the trigger source mode for the PDB module. - * - * This function sets the trigger source mode for the PDB module. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode, see to "pdb_trigger_src_mode_t". - */ -static inline void PDB_HAL_SetTriggerSrcMode(uint32_t baseAddr, pdb_trigger_src_mode_t mode) -{ - BW_PDB_SC_TRGSEL(baseAddr, (uint32_t)mode); -} - -/*! - * @brief Switches on to enable the PDB module. - * - * This function switches on to enable the PDB module. - * - * @param baseAddr Register base address for the module. - */ -static inline void PDB_HAL_Enable(uint32_t baseAddr) -{ - BW_PDB_SC_PDBEN(baseAddr, 1U); -} - -/*! - * @brief Switches off to enable the PDB module. - * - * This function switches off to enable the PDB module. - * - * @param baseAddr Register base address for the module. - */ -static inline void PDB_HAL_Disable(uint32_t baseAddr) -{ - BW_PDB_SC_PDBEN(baseAddr, 0U); -} - -/*! - * @brief Gets the PDB delay interrupt flag. - * - * This function gets the PDB delay interrupt flag. - * - * @param baseAddr Register base address for the module. - * @return Flat status, true if the flag is set. - */ -static inline bool PDB_HAL_GetIntFlag(uint32_t baseAddr) -{ - return (1U == BR_PDB_SC_PDBIF(baseAddr)); -} - -/*! - * @brief Clears the PDB delay interrupt flag. - * - * This function clears PDB delay interrupt flag. - * - * @param baseAddr Register base address for the module. - * @return Flat status, true if the flag is set. - */ -static inline void PDB_HAL_ClearIntFlag(uint32_t baseAddr) -{ - BW_PDB_SC_PDBIF(baseAddr, 0U); -} - -/*! - * @brief Switches to enable the PDB interrupt. - * - * This function switches to enable the PDB interrupt. - * - * @param baseAddr Register base address for the module. - * @param enable The switcher to assert the feature. - */ -static inline void PDB_HAL_SetIntCmd(uint32_t baseAddr, bool enable) -{ - BW_PDB_SC_PDBIE(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Sets the PDB prescaler multiplication factor. - * - * This function sets the PDB prescaler multiplication factor. - * - * @param baseAddr Register base address for the module. - * @param mode Selection of mode, see to "pdb_mult_factor_mode_t". - */ -static inline void PDB_HAL_SetPreMultFactorMode(uint32_t baseAddr, - pdb_mult_factor_mode_t mode) -{ - BW_PDB_SC_MULT(baseAddr, (uint32_t)mode); -} - -/*! - * @brief Switches to enable the PDB continuous mode. - * - * This function switches to enable the PDB continuous mode. - * - * @param baseAddr Register base address for the module. - * @param enable The switcher to assert the feature. - */ -static inline void PDB_HAL_SetContinuousModeCmd(uint32_t baseAddr, bool enable) -{ - BW_PDB_SC_CONT(baseAddr, (enable ? 1U : 0U) ); -} - -/*! - * @brief Loads the delay registers value for the PDB module. - * - * This function sets the LDOK bit and loads the delay registers value. - * Writing one to this bit updates the internal registers MOD, IDLY, CHnDLYm, - * DACINTx, and POyDLY with the values written to their buffers. The MOD, IDLY, - * CHnDLYm, DACINTx, and POyDLY take effect according to the load mode settings. - * - * After one is written to the LDOK bit, the values in the buffers of above mentioned registers - * are not effective and cannot be written until the values in the - * buffers are loaded into their internal registers. - * The LDOK can be written only when the the PDB is enabled or as alone with it. It is - * automatically cleared either when the values in the buffers are loaded into the - * internal registers or when the PDB is disabled. - * - * @param baseAddr Register base address for the module. - */ -static inline void PDB_HAL_SetLoadRegsCmd(uint32_t baseAddr) -{ - BW_PDB_SC_LDOK(baseAddr, 1U); -} - -/*! - * @brief Sets the modulus value for the PDB module. - * - * This function sets the modulus value for the PDB module. - * When the counter reaches the setting value, it is automatically reset to zero. - * When in continuous mode, the counter begins to increase - * again. - * - * @param baseAddr Register base address for the module. - * @param value The setting value of upper limit for PDB counter. - */ -static inline void PDB_HAL_SetModulusValue(uint32_t baseAddr, uint32_t value) -{ - BW_PDB_MOD_MOD(baseAddr, value); -} - -/*! - * @brief Gets the modulus value for the PDB module. - * - * This function gets the modulus value for the PDB module. - * - * @param baseAddr Register base address for the module. - * @return The current value of upper limit for counter. - */ -static inline uint32_t PDB_HAL_GetModulusValue(uint32_t baseAddr) -{ - return BR_PDB_MOD_MOD(baseAddr); -} - -/*! - * @brief Gets the PDB counter value. - * - * This function gets the PDB counter value. - * - * @param baseAddr Register base address for the module. - * @return The current counter value. - */ -static inline uint32_t PDB_HAL_GetCounterValue(uint32_t baseAddr) -{ - return BR_PDB_CNT_CNT(baseAddr); -} - -/*! - * @brief Sets the interrupt delay milestone of the PDB counter. - * - * This function sets the interrupt delay milestone of the PDB counter. - * If enabled, a PDB interrupt is generated when the counter is equal to the - * setting value. - * - * @param baseAddr Register base address for the module. - * @param value The setting value for interrupt delay milestone of PDB counter. - */ -static inline void PDB_HAL_SetIntDelayValue(uint32_t baseAddr, uint32_t value) -{ - BW_PDB_IDLY_IDLY(baseAddr, value); -} - -/*! - * @brief Gets the current interrupt delay milestone of the PDB counter. - * - * This function gets the current interrupt delay milestone of the PDB counter. - * - * @param baseAddr Register base address for the module. - * @return The current setting value for interrupt delay milestone of PDB counter. - */ -static inline uint32_t PDB_HAL_GetIntDelayValue(uint32_t baseAddr) -{ - return BR_PDB_IDLY_IDLY(baseAddr); -} - -/*! - * @brief Switches to enable the pre-trigger back-to-back mode. - * - * This function switches to enable the pre-trigger back-to-back mode. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - * @param enable Switcher to assert the feature. - */ -void PDB_HAL_SetPreTriggerBackToBackCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable); - -/*! - * @brief Switches to enable the pre-trigger output. - * - * This function switches to enable pre-trigger output. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - * @param enable Switcher to assert the feature. - */ -void PDB_HAL_SetPreTriggerOutputCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable); - -/*! - * @brief Switches to enable the pre-trigger. - * - * This function switches to enable the pre-trigger. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - * @param enable Switcher to assert the feature. - */ -void PDB_HAL_SetPreTriggerCmd(uint32_t baseAddr, uint32_t chn, uint32_t preChn, bool enable); - -/*! - * @brief Gets the flag which indicates whether the PDB counter has reached the pre-trigger delay value. - * - * This function gets the flag which indicates the PDB counter has reached the - * pre-trigger delay value. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - * @return Flag status. True if the event is asserted. - */ -static inline bool PDB_HAL_GetPreTriggerFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn) -{ - assert(chn < HW_PDB_CHnC1_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - return ( ((1U<< preChn) & BR_PDB_CHnS_CF(baseAddr, chn))? true: false); -} - -/*! - * @brief Clears the flag which indicates that the PDB counter has reached the pre-trigger delay value. - * - * This function clears the flag which indicates that the PDB counter has reached the - * pre-trigger delay value. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - */ -void PDB_HAL_ClearPreTriggerFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn); - -/*! - * @brief Gets the flag which indicates whether a sequence error is detected. - * - * This function gets the flag which indicates whether a sequence error is detected. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - * @return Flag status. True if the event is asserted. - */ -static inline bool PDB_HAL_GetPreTriggerSeqErrFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn) -{ - assert(chn < HW_PDB_CHnC1_COUNT); - assert(preChn < FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT); - return ( ((1U<< preChn) & BR_PDB_CHnS_ERR(baseAddr, chn))? true: false); -} - -/*! - * @brief Clears the flag which indicates that a sequence error has been detected. - * - * This function clears the flag which indicates that the sequence error has been detected. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - */ -void PDB_HAL_ClearPreTriggerSeqErrFlag(uint32_t baseAddr, uint32_t chn, uint32_t preChn); - -/*! - * @brief Sets the pre-trigger delay value. - * - * This function sets the pre-trigger delay value. - * - * @param baseAddr Register base address for the module. - * @param chn ADC instance index for trigger. - * @param preChn ADC channel group index for trigger. - * @param value Setting value for pre-trigger's delay value. - */ -void PDB_HAL_SetPreTriggerDelayCount(uint32_t baseAddr, uint32_t chn, uint32_t preChn, uint32_t value); - -/*! - * @brief Switches to enable the DAC external trigger input. - * - * This function switches to enable the DAC external trigger input. - * - * @param baseAddr Register base address for the module. - * @param dacChn DAC instance index for trigger. - * @param value Setting value for pre-trigger's delay value. - */ -static inline void PDB_HAL_SetDacExtTriggerInputCmd(uint32_t baseAddr, uint32_t dacChn, bool enable) -{ - assert(dacChn < HW_PDB_DACINTCn_COUNT); - BW_PDB_DACINTCn_EXT(baseAddr, dacChn, (enable ? 1U: 0U) ); -} - -/*! - * @brief Switches to enable the DAC external trigger input. - * - * This function switches to enable the DAC external trigger input. - * - * @param baseAddr Register base address for the module. - * @param dacChn DAC instance index for trigger. - * @param enable Switcher to assert the feature. - */ -static inline void PDB_HAL_SetDacIntervalTriggerCmd(uint32_t baseAddr, uint32_t dacChn, bool enable) -{ - assert(dacChn < HW_PDB_DACINTCn_COUNT); - BW_PDB_DACINTCn_TOE(baseAddr, dacChn, (enable ? 1U: 0U) ); -} - -/*! - * @brief Sets the interval value for the DAC trigger. - * - * This function sets the interval value for the DAC trigger. - * - * @param baseAddr Register base address for the module. - * @param dacChn DAC instance index for trigger. - * @param value Setting value for DAC trigger interval. - */ -static inline void PDB_HAL_SetDacIntervalValue(uint32_t baseAddr, uint32_t dacChn, uint32_t value) -{ - assert(dacChn < HW_PDB_DACINTn_COUNT); - BW_PDB_DACINTn_INT(baseAddr, dacChn, value); -} - -/*! - * @brief Gets the interval value for the DAC trigger. - * - * This function gets the interval value for the DAC trigger. - * - * @param baseAddr Register base address for the module. - * @param dacChn DAC instance index for trigger. - * @return The current setting value for DAC trigger interval. - */ -static inline uint32_t PDB_HAL_GetDacIntervalValue(uint32_t baseAddr, uint32_t dacChn) -{ - assert(dacChn < HW_PDB_DACINTn_COUNT); - return BR_PDB_DACINTn_INT(baseAddr, dacChn); -} - -/*! - * @brief Switches to enable the pulse-out trigger. - * - * This function switches to enable the pulse-out trigger. - * - * @param baseAddr Register base address for the module. - * @param pulseChn Pulse-out channle index for trigger. - * @param enable Switcher to assert the feature. - */ -void PDB_HAL_SetPulseOutCmd(uint32_t baseAddr, uint32_t pulseChn, bool enable); - -/*! - * @brief Sets the counter delay value for the pulse-out goes high. - * - * This function sets the counter delay value for the pulse-out goes high. - * - * @param baseAddr Register base address for the module. - * @param pulseChn Pulse-out channel index for trigger. - * @param value Setting value for PDB delay . - */ -static inline void PDB_HAL_SetPulseOutDelayForHigh(uint32_t baseAddr, uint32_t pulseChn, uint32_t value) -{ - assert(pulseChn < HW_PDB_POnDLY_COUNT); - BW_PDB_POnDLY_DLY1(baseAddr, pulseChn, value); -} - -/*! - * @brief Sets the counter delay value for the pulse-out goes low. - * - * This function sets the counter delay value for the pulse-out goes low. - * - * @param baseAddr Register base address for the module. - * @param pulseChn Pulse-out channel index for trigger. - * @param value Setting value for PDB delay . - */ -static inline void PDB_HAL_SetPulseOutDelayForLow(uint32_t baseAddr, uint32_t pulseChn, uint32_t value) -{ - assert(pulseChn < HW_PDB_POnDLY_COUNT); - BW_PDB_POnDLY_DLY2(baseAddr, pulseChn, value); -} - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_PDB_HAL_H__ */ - -/****************************************************************************** - * EOF - *****************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_features.h deleted file mode 100644 index e965077e152..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_features.h +++ /dev/null @@ -1,127 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_PIT_FEATURES_H__) -#define __FSL_PIT_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ - defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MKV30F128VFM10) || \ - defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || \ - defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || \ - defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || \ - defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || \ - defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ - defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || \ - defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || \ - defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ - #define FSL_FEATURE_PIT_TIMER_COUNT (4) - /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ - #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) - /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ - #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ - defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ - #define FSL_FEATURE_PIT_TIMER_COUNT (4) - /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ - #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) - /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ - #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ - #define FSL_FEATURE_PIT_TIMER_COUNT (4) - /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ - #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) - /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ - #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ - defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ - defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ - defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ - defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ - defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ - #define FSL_FEATURE_PIT_TIMER_COUNT (2) - /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ - #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) - /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ - #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_PIT_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c deleted file mode 100644 index 378d10622e9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pit_hal.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER -/*FUNCTION********************************************************************** - * - * Function Name : PIT_HAL_ReadLifetimeTimerCount - * Description : Read current lifefime counter value. - * Lifetime timer is 64-bit timer which chains timer 0 and timer 1 together. - * So, timer 0 and 1 should by chained by calling PIT_HAL_SetTimerChainCmd - * before using this timer. The period of lifetime timer equals to "period of - * timer 0 * period of timer 1". For the 64-bit value, higher 32-bit will have - * the value of timer 1, and lower 32-bit have the value of timer 0. -* - *END**************************************************************************/ -uint64_t PIT_HAL_ReadLifetimeTimerCount(uint32_t baseAddr) -{ - uint32_t valueH = 0U, valueL = 0U; - - /* LTMR64H should be read before LTMR64L */ - valueH = HW_PIT_LTMR64H_RD(baseAddr); - valueL = HW_PIT_LTMR64L_RD(baseAddr); - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h deleted file mode 100644 index 050c555cdd5..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h +++ /dev/null @@ -1,336 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_PIT_HAL_H__ -#define __FSL_PIT_HAL_H__ - -#include -#include -#include -#include "fsl_pit_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup pit_hal - * @{ - */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Enables the PIT module. - * - * This function enables the PIT timer clock (Note: this function does not un-gate - * the system clock gating control). It should be called before any other timer - * related setup. - * - * @param baseAddr Base address for current PIT instance. - */ -static inline void PIT_HAL_Enable(uint32_t baseAddr) -{ - BW_PIT_MCR_MDIS(baseAddr, 0U); -} - -/*! - * @brief Disables the PIT module. - * - * This function disables all PIT timer clocks(Note: it does not affect the - * SIM clock gating control). - * - * @param baseAddr Base address for current PIT instance. - */ -static inline void PIT_HAL_Disable(uint32_t baseAddr) -{ - BW_PIT_MCR_MDIS(baseAddr, 1U); -} - -/*! - * @brief Configures the timers to continue running or to stop in debug mode. - * - * In debug mode, the timers may or may not be frozen, based on the configuration of - * this function. This is intended to aid software development, allowing the developer - * to halt the processor, investigate the current state of the system (for example, - * the timer values), and continue the operation. - * - * @param baseAddr Base address for current PIT instance. - * @param timerRun Timers run or stop in debug mode. - * - true: Timers continue to run in debug mode. - * - false: Timers stop in debug mode. - */ -static inline void PIT_HAL_SetTimerRunInDebugCmd(uint32_t baseAddr, bool timerRun) -{ - BW_PIT_MCR_FRZ(baseAddr, !timerRun); -} - -#if FSL_FEATURE_PIT_HAS_CHAIN_MODE -/*! - * @brief Enables or disables the timer chain with the previous timer. - * - * When a timer has a chain mode enabled, it only counts after the previous - * timer has expired. If the timer n-1 has counted down to 0, counter n - * decrements the value by one. This allows the developers to chain timers together - * and form a longer timer. The first timer (timer 0) cannot be chained to any - * other timer. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number which is chained with the previous timer. - * @param enable Enable or disable chain. - * - true: Current timer is chained with the previous timer. - * - false: Timer doesn't chain with other timers. - */ -static inline void PIT_HAL_SetTimerChainCmd(uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - BW_PIT_TCTRLn_CHN(baseAddr, channel, enable); -} - -#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE*/ - -/* @} */ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load the start value as specified by the function - * PIT_HAL_SetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel, uint32_t count), count down to - * 0, and load the respective start value again. Each time a timer reaches 0, - * it generates a trigger pulse and sets the time-out interrupt flag. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - */ -static inline void PIT_HAL_StartTimer(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - BW_PIT_TCTRLn_TEN(baseAddr, channel, 1U); -} - -/*! - * @brief Stops the timer from counting. - * - * This function stops every timer from counting. Timers reload their periods - * respectively after they call the PIT_HAL_StartTimer the next time. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - */ -static inline void PIT_HAL_StopTimer(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - BW_PIT_TCTRLn_TEN(baseAddr, channel, 0U); -} - -/*! - * @brief Checks to see whether the current timer is started or not. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @return Current timer running status - * -true: Current timer is running. - * -false: Current timer has stopped. - */ -static inline bool PIT_HAL_IsTimerRunning(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - return BR_PIT_TCTRLn_TEN(baseAddr, channel); -} - -/* @} */ - -/*! - * @name Timer Period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers begin counting from the value set by this function. - * The counter period of a running timer can be modified by first stopping - * the timer, setting a new load value, and starting the timer again. If - * timers are not restarted, the new value is loaded after the next trigger - * event. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @param count Timer period in units of count - */ -static inline void PIT_HAL_SetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel, uint32_t count) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - HW_PIT_LDVALn_WR(baseAddr, channel, count); -} - -/*! - * @brief Returns the current timer period in units of count. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @return Timer period in units of count - */ -static inline uint32_t PIT_HAL_GetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - return HW_PIT_LDVALn_RD(baseAddr, channel); -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @return Current timer counting value - */ -static inline uint32_t PIT_HAL_ReadTimerCount(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - return HW_PIT_CVALn_RD(baseAddr, channel); -} - -#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER -/*! - * @brief Reads the current lifetime counter value. - * - * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. - * Timer 0 and 1 are chained by calling the PIT_HAL_SetTimerChainCmd - * before using this timer. The period of lifetime timer is equal to the "period of - * timer 0 * period of timer 1". For the 64-bit value, the higher 32-bit has - * the value of timer 1, and the lower 32-bit has the value of timer 0. - * - * @param baseAddr Base address for current PIT instance. - * @return Current lifetime timer value - */ -uint64_t PIT_HAL_ReadLifetimeTimerCount(uint32_t baseAddr); -#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/ - -/* @} */ - -/*! - * @name Interrupt - * @{ - */ - -/*! - * @brief Enables or disables the timer interrupt. - * - * If enabled, an interrupt happens when a timeout event occurs - * (Note: NVIC should be called to enable pit interrupt in system level). - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @param enable Enable or disable interrupt. - * - true: Generate interrupt when timer counts to 0. - * - false: No interrupt is generated. - */ -static inline void PIT_HAL_SetIntCmd(uint32_t baseAddr, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - BW_PIT_TCTRLn_TIE(baseAddr, channel, enable); -} - -/*! - * @brief Checks whether the timer interrupt is enabled or not. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @return Status of enabled or disabled interrupt - * - true: Interrupt is enabled. - * - false: Interrupt is disabled. - */ -static inline bool PIT_HAL_GetIntCmd(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - return BR_PIT_TCTRLn_TIE(baseAddr, channel); -} - -/*! - * @brief Clears the timer interrupt flag. - * - * This function clears the timer interrupt flag after a timeout event - * occurs. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - */ -static inline void PIT_HAL_ClearIntFlag(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - /* Write 1 will clear the flag. */ - HW_PIT_TFLGn_WR(baseAddr, channel, 1U); -} - -/*! - * @brief Reads the current timer timeout flag. - * - * Every time the timer counts to 0, this flag is set. - * - * @param baseAddr Base address for current PIT instance. - * @param channel Timer channel number - * @return Current status of the timeout flag - * - true: Timeout has occurred. - * - false: Timeout has not yet occurred. - */ -static inline bool PIT_HAL_IsIntPending(uint32_t baseAddr, uint32_t channel) -{ - assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); - return HW_PIT_TFLGn_RD(baseAddr, channel); -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_PIT_HAL_H__*/ -/******************************************************************************* -* EOF -*******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_features.h deleted file mode 100644 index b6a73ae31ba..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_features.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_PMC_FEATURES_H__) -#define __FSL_PMC_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ - defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL03Z32CAF4) || \ - defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || \ - defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \ - defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ - defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \ - defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ - defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || \ - defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || \ - defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ - defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || \ - defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || \ - defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \ - defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \ - defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \ - defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \ - defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \ - defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \ - defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ - defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ - defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || \ - defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ - defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || \ - defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ - defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15) - /* @brief Has Bandgap Enable In VLPx Operation support. */ - #define FSL_FEATURE_PMC_HAS_BGEN (1) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ - defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has Bandgap Enable In VLPx Operation support. */ - #define FSL_FEATURE_PMC_HAS_BGEN (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_PMC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c deleted file mode 100644 index 6d5accaf658..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pmc_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : PMC_HAL_SetLowVoltIntCmd - * Description : Enable/Disable low voltage related interrupts - * This function enables the interrupt for the low voltage detection, warning, - * etc. When enabled, if the LVDF (Low Voltage Detect Flag) is set, a hardware - * interrupt occurs. - * - *END**************************************************************************/ -void PMC_HAL_SetLowVoltIntCmd(uint32_t baseAddr, pmc_int_select_t intSelect, bool enable) -{ - switch (intSelect) - { - case kPmcIntLowVoltDetect: /* Low Voltage Detect */ - BW_PMC_LVDSC1_LVDIE(baseAddr, enable); - break; - case kPmcIntLowVoltWarn: /* Low Voltage Warning */ - BW_PMC_LVDSC2_LVWIE(baseAddr, enable); - break; - default: - break; - } -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h deleted file mode 100644 index 10db1b4b3f9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_PMC_HAL_H__) -#define __FSL_PMC_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_pmc_features.h" - -/*! @addtogroup pmc_hal*/ -/*! @{*/ - -/*! @file fsl_pmc_hal.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Low-Voltage Warning Voltage Select*/ -typedef enum _pmc_low_volt_warn_volt_select { - kPmcLowVoltWarnVoltLowTrip, /*!< Low trip point selected (VLVW = VLVW1)*/ - kPmcLowVoltWarnVoltMid1Trip, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ - kPmcLowVoltWarnVoltMid2Trip, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ - kPmcLowVoltWarnVoltHighTrip /*!< High trip point selected (VLVW = VLVW4)*/ -} pmc_low_volt_warn_volt_select_t; - -/*! @brief Low-Voltage Detect Voltage Select*/ -typedef enum _pmc_low_volt_detect_volt_select { - kPmcLowVoltDetectVoltLowTrip, /*!< Low trip point selected (V LVD = V LVDL )*/ - kPmcLowVoltDetectVoltHighTrip, /*!< High trip point selected (V LVD = V LVDH )*/ -} pmc_low_volt_detect_volt_select_t; - -/*! @brief interrupt control*/ -typedef enum _pmc_int_select { - kPmcIntLowVoltDetect, /*!< Low Voltage Detect Interrupt */ - kPmcIntLowVoltWarn, /*!< Low Voltage Warning Interrupt */ -} pmc_int_select_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Power Management Controller Control APIs*/ -/*@{*/ - - -/*! - * @brief Enables/Disables low voltage-related interrupts. - * - * This function enables the interrupt for the low voltage detection, warning, - * etc. When enabled, if the LVDF (Low Voltage Detect Flag) is set, a hardware - * interrupt occurs. - * - * @param baseAddr Base address for current PMC instance. - * @param intSelect interrut select - * @param enable enable/disable the interrupt - */ -void PMC_HAL_SetLowVoltIntCmd(uint32_t baseAddr, pmc_int_select_t intSelect, bool enable); - -/*! - * @brief Low-Voltage Detect Hardware Reset Enable/Disable (write once) - * - * This function enables/disables the hardware reset for the low voltage - * detection. When enabled, if the LVDF (Low Voltage Detect Flag) is set, a - * hardware reset occurs. This setting is a write-once-only. Any additional writes - * are ignored. - * - * @param baseAddr Base address for current PMC instance. - * @param enable enable/disable the LVD hardware reset - */ -static inline void PMC_HAL_SetLowVoltDetectResetCmd(uint32_t baseAddr, bool enable) -{ - BW_PMC_LVDSC1_LVDRE(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Low-Voltage Detect Acknowledge - * - * This function acknowledges the low voltage detection errors (write 1 to - * clear LVDF). - * - * @param baseAddr Base address for current PMC instance. - */ -static inline void PMC_HAL_SetLowVoltDetectAck(uint32_t baseAddr) -{ - BW_PMC_LVDSC1_LVDACK(baseAddr, 1); -} - -/*! - * @brief Low-Voltage Detect Flag Read - * - * This function reads the current LVDF status. If it returns 1, a low - * voltage event is detected. - * - * @param baseAddr Base address for current PMC instance. - * @return status Current low voltage detect flag - * - true: Low-Voltage detected - * - false: Low-Voltage not detected - */ -static inline bool PMC_HAL_GetLowVoltDetectFlag(uint32_t baseAddr) -{ - return BR_PMC_LVDSC1_LVDF(baseAddr); -} - -/*! - * @brief Sets the Low-Voltage Detect Voltage Mode - * - * This function sets the low voltage detect voltage select. It sets - * the low voltage detect trip point voltage (Vlvd). An application can select - * either a low-trip or a high-trip point. See a chip reference manual for details. - * - * @param baseAddr Base address for current PMC instance. - * @param select Voltage select setting defined in pmc_lvdv_select_t - */ -static inline void PMC_HAL_SetLowVoltDetectVoltMode(uint32_t baseAddr, pmc_low_volt_detect_volt_select_t select) -{ - BW_PMC_LVDSC1_LVDV(baseAddr, select); -} - -/*! - * @brief Gets the Low-Voltage Detect Voltage Mode - * - * This function gets the low voltage detect voltage select. It gets - * the low voltage detect trip point voltage (Vlvd). An application can select - * either a low-trip or a high-trip point. See a chip reference manual for details. - * - * @param baseAddr Base address for current PMC instance. - * @return select Current voltage select setting - */ -static inline pmc_low_volt_detect_volt_select_t PMC_HAL_GetLowVoltDetectVoltMode(uint32_t baseAddr) -{ - return (pmc_low_volt_detect_volt_select_t)BR_PMC_LVDSC1_LVDV(baseAddr); -} - -/*! - * @brief Low-Voltage Warning Acknowledge - * - * This function acknowledges the low voltage warning errors (write 1 to - * clear LVWF). - * - * @param baseAddr Base address for current PMC instance. - */ -static inline void PMC_HAL_SetLowVoltWarnAck(uint32_t baseAddr) -{ - BW_PMC_LVDSC2_LVWACK(baseAddr, 1); -} - -/*! - * @brief Low-Voltage Warning Flag Read - * - * This function polls the current LVWF status. When 1 is returned, it - * indicates a low-voltage warning event. LVWF is set when V Supply transitions - * below the trip point or after reset and V Supply is already below the V LVW. - * - * @param baseAddr Base address for current PMC instance. - * @return status Current LVWF status - * - true: Low-Voltage Warning Flag is set. - * - false: the Low-Voltage Warning does not happen. - */ -static inline bool PMC_HAL_GetLowVoltWarnFlag(uint32_t baseAddr) -{ - return BR_PMC_LVDSC2_LVWF(baseAddr); -} - -/*! - * @brief Sets the Low-Voltage Warning Voltage Mode. - * - * This function sets the low voltage warning voltage select. It sets - * the low voltage warning trip point voltage (Vlvw). An application can select - * either a low, mid1, mid2 and a high-trip point. See a chip reference manual for - * details and the pmc_lvwv_select_t for supported settings. - * - * @param baseAddr Base address for current PMC instance. - * @param select Low voltage warning select setting - */ -static inline void PMC_HAL_SetLowVoltWarnVoltMode(uint32_t baseAddr, pmc_low_volt_warn_volt_select_t select) -{ - BW_PMC_LVDSC2_LVWV(baseAddr, select); -} - -/*! - * @brief Gets the Low-Voltage Warning Voltage Mode. - * - * This function gets the low voltage warning voltage select. It gets - * the low voltage warning trip point voltage (Vlvw). See the pmc_lvwv_select_t - * for supported settings. - * - * @param baseAddr Base address for current PMC instance. - * @return select Current low voltage warning select setting - */ -static inline pmc_low_volt_warn_volt_select_t PMC_HAL_GetLowVoltWarnVoltMode(uint32_t baseAddr) -{ - return (pmc_low_volt_warn_volt_select_t)BR_PMC_LVDSC2_LVWV(baseAddr); -} - -#if FSL_FEATURE_PMC_HAS_BGEN -/*! - * @brief Enables the Bandgap in the VLPx Operation. - * - * This function enables/disables the bandgap in lower power modes - * (VLPx, * LLS, and VLLSx). When on-chip peripherals require the bandgap voltage - * reference in low power modes, set the BGEN to continue to enable - * the bandgap operation. - * - * @param baseAddr Base address for current PMC instance. - * @param enable enable/disable the Bangap. - */ -static inline void PMC_HAL_SetBandgapInLowPowerModeCmd(uint32_t baseAddr, bool enable) -{ - BW_PMC_REGSC_BGEN(baseAddr, enable); -} -#endif - -/*! - * @brief Enables/Disables the Bandgap Buffer. - * - * This function enables/disables the Bandgap buffer. - * - * @param baseAddr Base address for current PMC instance. - * @param enable enable/disable the Bangap Buffer. - */ -static inline void PMC_HAL_SetBandgapBufferCmd(uint32_t baseAddr, bool enable) -{ - BW_PMC_REGSC_BGBE(baseAddr, enable); -} - -/*! - * @brief Gets the acknowledge isolation value. - * - * This function reads the Acknowledge Isolation setting that indicates - * whether certain peripherals and the I/O pads are in a latched state as - * a result of having been in the VLLS mode. - * - * @param baseAddr Base address for current PMC instance. - * @return value ACK isolation - * 0 - Peripherals and I/O pads are in a normal run state. - * 1 - Certain peripherals and I/O pads are in an isolated and - * latched state. - */ -static inline uint8_t PMC_HAL_GetAckIsolation(uint32_t baseAddr) -{ - return BR_PMC_REGSC_ACKISO(baseAddr); -} - -/*! - * @brief Clears an acknowledge isolation. - * - * This function clears the ACK Isolation flag. Writing one to this setting - * when it is set releases the I/O pads and certain peripherals to their normal - * run mode state. - * - * @param baseAddr Base address for current PMC instance. - */ -static inline void PMC_HAL_SetClearAckIsolation(uint32_t baseAddr) -{ - BW_PMC_REGSC_ACKISO(baseAddr, 1); -} - -/*! - * @brief Gets the Regulator regulation status. - * - * This function returns the regulator to a run regulation status. It provides - * the current status of the internal voltage regulator. - * - * @param baseAddr Base address for current PMC instance. - * @return value Regulation status - * 0 - Regulator is in a stop regulation or in transition to/from it. - * 1 - Regulator is in a run regulation. - * - */ -static inline uint8_t PMC_HAL_GetRegulatorStatus(uint32_t baseAddr) -{ - return BR_PMC_REGSC_REGONS(baseAddr); -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_PMC_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h deleted file mode 100644 index e9f802553b6..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h +++ /dev/null @@ -1,333 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_PORT_FEATURES_H__) -#define __FSL_PORT_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ - defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ - defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ - defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ - defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ - defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ - defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ - defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ - defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ - defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ - defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : (-1)))))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : (-1)))))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ - defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ - defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has control lock (register bit PCR[LK]). */ - #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) - /* @brief Has open drain control (register bit PCR[ODE]). */ - #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) - /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) - #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has DMA request (register bit field PCR[IRQC] values). */ - #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) - /* @brief Has pull resistor selection (register bit PCR[PS]). */ - #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) - /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */ - #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0) - /* @brief Has slew rate control (register bit PCR[SRE]). */ - #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) - /* @brief Has passive filter (register bit field PCR[PFE]). */ - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) - #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has drive strength control (register bit PCR[DSE]). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) - /* @brief Has separate drive strength register (HDRVE). */ - #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) - /* @brief Has glitch filter (register IOFLT). */ - #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_PORT_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c deleted file mode 100644 index 47157037cda..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_port_hal.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : PORT_HAL_SetLowGlobalPinCtrl - * Description : Configure low half of pin control register for the same settings, - * this function operates pin 0 -15 of one specific port. - * - *END**************************************************************************/ -void PORT_HAL_SetLowGlobalPinCtrl(uint32_t baseAddr, uint16_t lowPinSelect, uint16_t config) -{ - uint32_t combine = lowPinSelect; - combine = (combine << 16) + config; - HW_PORT_GPCLR_WR(baseAddr, combine); -} - -/*FUNCTION********************************************************************** - * - * Function Name : PORT_HAL_SetHighGlobalPinCtrl - * Description : Configure high half of pin control register for the same - * settings, this function operates pin 16 -31 of one specific port. - * - *END**************************************************************************/ -void PORT_HAL_SetHighGlobalPinCtrl(uint32_t baseAddr, uint16_t highPinSelect, uint16_t config) -{ - uint32_t combine = highPinSelect; - combine = (combine << 16) + config; - HW_PORT_GPCHR_WR(baseAddr, combine); -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h deleted file mode 100644 index fae08f8502b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_PORT_HAL_H__ -#define __FSL_PORT_HAL_H__ - -#include -#include -#include -#include "fsl_port_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup port_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Internal resistor pull feature selection*/ -typedef enum _port_pull { - kPortPullDown = 0U, /*!< internal pull-down resistor is enabled.*/ - kPortPullUp = 1U /*!< internal pull-up resistor is enabled.*/ -} port_pull_t; - -/*! @brief Slew rate selection*/ -typedef enum _port_slew_rate { - kPortFastSlewRate = 0U, /*!< fast slew rate is configured.*/ - kPortSlowSlewRate = 1U /*!< slow slew rate is configured.*/ -} port_slew_rate_t; - -/*! @brief Configures the drive strength.*/ -typedef enum _port_drive_strength { - kPortLowDriveStrength = 0U, /*!< low drive strength is configured.*/ - kPortHighDriveStrength = 1U /*!< high drive strength is configured.*/ -} port_drive_strength_t; - -/*! @brief Pin mux selection*/ -typedef enum _port_mux { - kPortPinDisabled = 0U, /*!< corresponding pin is disabled as analog.*/ - kPortMuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO.*/ - kPortMuxAlt2 = 2U, /*!< chip-specific*/ - kPortMuxAlt3 = 3U, /*!< chip-specific*/ - kPortMuxAlt4 = 4U, /*!< chip-specific*/ - kPortMuxAlt5 = 5U, /*!< chip-specific*/ - kPortMuxAlt6 = 6U, /*!< chip-specific*/ - kPortMuxAlt7 = 7U /*!< chip-specific*/ -} port_mux_t; - -/*! @brief Digital filter clock source selection*/ -#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER -typedef enum _port_digital_filter_clock_source { - kPortBusClock = 0U, /*!< Digital filters are clocked by the bus clock.*/ - kPortLPOClock = 1U /*!< Digital filters are clocked by the 1 kHz LPO clock.*/ -} port_digital_filter_clock_source_t; -#endif - -/*! @brief Configures the interrupt generation condition.*/ -typedef enum _port_interrupt_config { - kPortIntDisabled = 0x0U, /*!< Interrupt/DMA request is disabled.*/ - kPortDmaRisingEdge = 0x1U, /*!< DMA request on rising edge.*/ - kPortDmaFallingEdge = 0x2U, /*!< DMA request on falling edge.*/ - kPortDmaEitherEdge = 0x3U, /*!< DMA request on either edge.*/ - kPortIntLogicZero = 0x8U, /*!< Interrupt when logic zero. */ - kPortIntRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ - kPortIntFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ - kPortIntEitherEdge = 0xBU, /*!< Interrupt on either edge. */ - kPortIntLogicOne = 0xCU /*!< Interrupt when logic one. */ -} port_interrupt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Configuration - * @{ - */ - -/*! - * @brief Selects the internal resistor as pull-down or pull-up. - * - * Pull configuration is valid in all digital pin muxing modes. - * - * @param baseAddr port base address. - * @param pin port pin number - * @param pullSelect internal resistor pull feature selection - * - kPortPullDown: internal pull-down resistor is enabled. - * - kPortPullUp : internal pull-up resistor is enabled. - */ -static inline void PORT_HAL_SetPullMode(uint32_t baseAddr, - uint32_t pin, - port_pull_t pullSelect) -{ - assert(pin < 32U); - BW_PORT_PCRn_PS(baseAddr, pin, pullSelect); -} - -/*! - * @brief Enables or disables the internal pull resistor. - * - * @param baseAddr port base address - * @param pin port pin number - * @param isPullEnabled internal pull resistor enable or disable - * - true : internal pull resistor is enabled. - * - false: internal pull resistor is disabled. - */ -static inline void PORT_HAL_SetPullCmd(uint32_t baseAddr, uint32_t pin, bool isPullEnabled) -{ - assert(pin < 32U); - BW_PORT_PCRn_PE(baseAddr, pin, isPullEnabled); -} - -/*! - * @brief Configures the fast/slow slew rate if the pin is used as a digital output. - * - * @param baseAddr port base address - * @param pin port pin number - * @param rateSelect slew rate selection - * - kPortFastSlewRate: fast slew rate is configured. - * - kPortSlowSlewRate: slow slew rate is configured. - */ -static inline void PORT_HAL_SetSlewRateMode(uint32_t baseAddr, - uint32_t pin, - port_slew_rate_t rateSelect) -{ - assert(pin < 32U); - BW_PORT_PCRn_SRE(baseAddr, pin, rateSelect); -} - -/*! - * @brief Configures the passive filter if the pin is used as a digital input. - * - * If enabled, a low pass filter (10 MHz to 30 MHz bandwidth) is enabled - * on the digital input path. Disable the Passive Input Filter when supporting - * high speed interfaces (> 2 MHz) on the pin. - * - * @param baseAddr port base address - * @param pin port pin number - * @param isPassiveFilterEnabled passive filter configuration - * - false: passive filter is disabled. - * - true : passive filter is enabled. - */ -static inline void PORT_HAL_SetPassiveFilterCmd(uint32_t baseAddr, - uint32_t pin, - bool isPassiveFilterEnabled) -{ - assert(pin < 32U); - BW_PORT_PCRn_PFE(baseAddr, pin, isPassiveFilterEnabled); -} - -#if FSL_FEATURE_PORT_HAS_OPEN_DRAIN -/*! - * @brief Enables or disables the open drain. - * - * @param baseAddr port base address - * @param pin port pin number - * @param isOpenDrainEnabled enable open drain or not - * - false: Open Drain output is disabled on the corresponding pin. - * - true : Open Drain output is disabled on the corresponding pin. - */ -static inline void PORT_HAL_SetOpenDrainCmd(uint32_t baseAddr, - uint32_t pin, - bool isOpenDrainEnabled) -{ - assert(pin < 32U); - BW_PORT_PCRn_ODE(baseAddr, pin, isOpenDrainEnabled); -} -#endif /*FSL_FEATURE_PORT_HAS_OPEN_DRAIN*/ - -/*! - * @brief Configures the drive strength if the pin is used as a digital output. - * - * @param baseAddr port base address - * @param pin port pin number - * @param driveSelect drive strength selection - * - kLowDriveStrength : low drive strength is configured. - * - kHighDriveStrength: high drive strength is configured. - */ -static inline void PORT_HAL_SetDriveStrengthMode(uint32_t baseAddr, - uint32_t pin, - port_drive_strength_t driveSelect) -{ - assert(pin < 32U); - BW_PORT_PCRn_DSE(baseAddr, pin, driveSelect); -} - -/*! - * @brief Configures the pin muxing. - * - * @param baseAddr port base address - * @param pin port pin number - * @param mux pin muxing slot selection - * - kPinDisabled: Pin disabled. - * - kMuxAsGpio : Set as GPIO. - * - others : chip-specific. - */ -static inline void PORT_HAL_SetMuxMode(uint32_t baseAddr, uint32_t pin, port_mux_t mux) -{ - assert(pin < 32U); - BW_PORT_PCRn_MUX(baseAddr, pin, mux); -} - -#if FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK -/*! - * @brief Locks or unlocks the pin control register bits[15:0]. - * - * @param baseAddr port base address - * @param pin port pin number - * @param isPinLockEnabled lock pin control register or not - * - false: pin control register bit[15:0] are not locked. - * - true : pin control register bit[15:0] are locked, cannot be updated till system reset. - */ -static inline void PORT_HAL_SetPinCtrlLockCmd(uint32_t baseAddr, - uint32_t pin, - bool isPinLockEnabled) -{ - assert(pin < 32U); - BW_PORT_PCRn_LK(baseAddr, pin, isPinLockEnabled); -} -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK*/ - -#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER -/*! - * @brief Enables or disables the digital filter in one single port. - * Each bit of the 32-bit register represents one pin. - * - * @param baseAddr port base address - * @param pin port pin number - * @param isDigitalFilterEnabled digital filter enable/disable - * - false: digital filter is disabled on the corresponding pin. - * - true : digital filter is enabled on the corresponding pin. - */ -static inline void PORT_HAL_SetDigitalFilterCmd(uint32_t baseAddr, - uint32_t pin, - bool isDigitalFilterEnabled) -{ - assert(pin < 32U); - HW_PORT_DFER_SET(baseAddr, (uint32_t)isDigitalFilterEnabled << pin); -} - -/*! - * @brief Configures the clock source for the digital input filters. Changing the filter clock source should - * only be done after disabling all enabled filters. Every pin in one port uses the same - * clock source. - * - * @param baseAddr port base address - * @param clockSource chose which clock source to use for current port - * - kBusClock: digital filters are clocked by the bus clock. - * - kLPOClock: digital filters are clocked by the 1 kHz LPO clock. - */ -static inline void PORT_HAL_SetDigitalFilterClock(uint32_t baseAddr, - port_digital_filter_clock_source_t clockSource) -{ - HW_PORT_DFCR_WR(baseAddr, clockSource); -} - -/*! - * @brief Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs - * for enabled digital filters. Glitches that are longer than this register setting - * (in clock cycles) pass through the digital filter, while glitches that are equal - * to or less than this register setting (in clock cycles) are filtered. Changing the - * filter length should only be done after disabling all enabled filters. - * - * @param baseAddr port base address - * @param width configure digital filter width (should be less than 5 bits). - */ -static inline void PORT_HAL_SetDigitalFilterWidth(uint32_t baseAddr, uint8_t width) -{ - HW_PORT_DFWR_WR(baseAddr, width); -} -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER*/ - -/*! - * @brief Configures the low half of the pin control register for the same settings. - * This function operates pin 0 -15 of one specific port. - * - * @param baseAddr port base address - * @param lowPinSelect update corresponding pin control register or not. For a specific bit: - * - 0: corresponding low half of pin control register won't be updated according to configuration. - * - 1: corresponding low half of pin control register will be updated according to configuration. - * @param config value is written to a low half port control register bits[15:0]. - */ -void PORT_HAL_SetLowGlobalPinCtrl(uint32_t baseAddr, uint16_t lowPinSelect, uint16_t config); - -/*! - * @brief Configures the high half of pin control register for the same settings. - * This function operates pin 16 -31 of one specific port. - * - * @param baseAddr port base address - * @param highPinSelect update corresponding pin control register or not. For a specific bit: - * - 0: corresponding high half of pin control register won't be updated according to configuration. - * - 1: corresponding high half of pin control register will be updated according to configuration. - * @param config value is written to a high half port control register bits[15:0]. - */ -void PORT_HAL_SetHighGlobalPinCtrl(uint32_t baseAddr, uint16_t highPinSelect, uint16_t config); - -/*@}*/ - -/*! - * @name Interrupt - * @{ - */ - -/*! - * @brief Configures the port pin interrupt/DMA request. - * - * @param baseAddr port base address. - * @param pin port pin number - * @param intConfig interrupt configuration - * - kIntDisabled : Interrupt/DMA request disabled. - * - kDmaRisingEdge : DMA request on rising edge. - * - kDmaFallingEdge: DMA request on falling edge. - * - kDmaEitherEdge : DMA request on either edge. - * - KIntLogicZero : Interrupt when logic zero. - * - KIntRisingEdge : Interrupt on rising edge. - * - KIntFallingEdge: Interrupt on falling edge. - * - KIntEitherEdge : Interrupt on either edge. - * - KIntLogicOne : Interrupt when logic one. - */ -static inline void PORT_HAL_SetPinIntMode(uint32_t baseAddr, - uint32_t pin, - port_interrupt_config_t intConfig) -{ - assert(pin < 32U); - BW_PORT_PCRn_IRQC(baseAddr, pin, intConfig); -} - -/*! - * @brief Gets the current port pin interrupt/DMA request configuration. - * - * @param baseAddr port base address - * @param pin port pin number - * @return interrupt configuration - * - kIntDisabled : Interrupt/DMA request disabled. - * - kDmaRisingEdge : DMA request on rising edge. - * - kDmaFallingEdge: DMA request on falling edge. - * - kDmaEitherEdge : DMA request on either edge. - * - KIntLogicZero : Interrupt when logic zero. - * - KIntRisingEdge : Interrupt on rising edge. - * - KIntFallingEdge: Interrupt on falling edge. - * - KIntEitherEdge : Interrupt on either edge. - * - KIntLogicOne : Interrupt when logic one. - */ -static inline port_interrupt_config_t PORT_HAL_GetPinIntMode(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32U); - return (port_interrupt_config_t)BR_PORT_PCRn_IRQC(baseAddr, pin); -} - -/*! - * @brief Reads the individual pin-interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param baseAddr port base address - * @param pin port pin number - * @return current pin interrupt status flag - * - 0: interrupt is not detected. - * - 1: interrupt is detected. - */ -static inline bool PORT_HAL_IsPinIntPending(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32U); - return BR_PORT_PCRn_ISF(baseAddr, pin); -} - -/*! - * @brief Clears the individual pin-interrupt status flag. - * - * @param baseAddr port base address - * @param pin port pin number - */ -static inline void PORT_HAL_ClearPinIntFlag(uint32_t baseAddr, uint32_t pin) -{ - assert(pin < 32U); - BW_PORT_PCRn_ISF(baseAddr, pin, 1U); -} - -/*! - * @brief Reads the entire port interrupt status flag. - * - * @param baseAddr port base address - * @return all 32 pin interrupt status flags. For specific bit: - * - 0: interrupt is not detected. - * - 1: interrupt is detected. - */ -static inline uint32_t PORT_HAL_GetPortIntFlag(uint32_t baseAddr) -{ - return HW_PORT_ISFR_RD(baseAddr); -} - -/*! - * @brief Clears the entire port interrupt status flag. - * - * @param baseAddr port base address - */ -static inline void PORT_HAL_ClearPortIntFlag(uint32_t baseAddr) -{ - HW_PORT_ISFR_WR(baseAddr, ~0U); -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_PORT_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_features.h deleted file mode 100644 index 3fef669ab45..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_features.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140516 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_RCM_FEATURES_H__) -#define __FSL_RCM_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ - defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || \ - defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \ - defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \ - defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || \ - defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || \ - defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ - defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) - /* @brief Has Loss-of-Lock Reset support. */ - #define FSL_FEATURE_RCM_HAS_LOL (0) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \ - defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ - defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \ - defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \ - defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ - defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ - defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \ - defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || \ - defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \ - defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || \ - defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ - defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15) - /* @brief Has Loss-of-Lock Reset support. */ - #define FSL_FEATURE_RCM_HAS_LOL (1) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_RCM_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c deleted file mode 100644 index 5e4298eb3df..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rcm_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : RCM_HAL_GetSrcStatusCmd - * Description : Get the reset source status - * - * This function will get the current reset source status for specified source - * - *END**************************************************************************/ -bool RCM_HAL_GetSrcStatusCmd(uint32_t baseAddr, rcm_source_names_t srcName) -{ - bool retValue = false; - - assert(srcName < kRcmSrcNameMax); - - switch (srcName) - { - case kRcmWakeup: /* low-leakage wakeup reset */ - retValue = (bool)BR_RCM_SRS0_WAKEUP(baseAddr); - break; - case kRcmLowVoltDetect: /* low voltage detect reset */ - retValue = (bool)BR_RCM_SRS0_LVD(baseAddr); - break; - case kRcmLossOfClk: /* loss of clock reset */ - retValue = (bool)BR_RCM_SRS0_LOC(baseAddr); - break; -#if FSL_FEATURE_RCM_HAS_LOL - case kRcmLossOfLock: /* loss of lock reset */ - retValue = (bool)BR_RCM_SRS0_LOL(baseAddr); - break; -#endif - case kRcmWatchDog: /* watch dog reset */ - retValue = (bool)BR_RCM_SRS0_WDOG(baseAddr); - break; - case kRcmExternalPin: /* external pin reset */ - retValue = (bool)BR_RCM_SRS0_PIN(baseAddr); - break; - case kRcmPowerOn: /* power on reset */ - retValue = (bool)BR_RCM_SRS0_POR(baseAddr); - break; - case kRcmJtag: /* JTAG generated reset */ - retValue = (bool)BR_RCM_SRS1_JTAG(baseAddr); - break; - case kRcmCoreLockup: /* core lockup reset */ - retValue = (bool)BR_RCM_SRS1_LOCKUP(baseAddr); - break; - case kRcmSoftware: /* software reset */ - retValue = (bool)BR_RCM_SRS1_SW(baseAddr); - break; - case kRcmSystem: /* system reset request bit set reset */ - retValue = (bool)BR_RCM_SRS1_MDM_AP(baseAddr); - break; - case kRcmEzport: /* EzPort reset */ - retValue = (bool)BR_RCM_SRS1_EZPT(baseAddr); - break; - case kRcmStopModeAckErr: /* stop mode ack error reset */ - retValue = (bool)BR_RCM_SRS1_SACKERR(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h deleted file mode 100644 index 08021fbc580..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_RCM_HAL_H__) -#define __FSL_RCM_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_rcm_features.h" - -/*! @addtogroup rcm_hal*/ -/*! @{*/ - -/*! @file fsl_rcm_hal.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief System Reset Source Name definitions */ -typedef enum _rcm_source_names { - kRcmWakeup, /* low-leakage wakeup reset */ - kRcmLowVoltDetect, /* low voltage detect reset */ - kRcmLossOfClk, /* loss of clock reset */ - kRcmLossOfLock, /* loss of lock reset */ - kRcmWatchDog, /* watch dog reset */ - kRcmExternalPin, /* external pin reset */ - kRcmPowerOn, /* power on reset */ - kRcmJtag, /* JTAG generated reset */ - kRcmCoreLockup, /* core lockup reset */ - kRcmSoftware, /* software reset */ - kRcmSystem, /* system reset request bit set reset */ - kRcmEzport, /* EzPort reset */ - kRcmStopModeAckErr, /* stop mode ack error reset */ - kRcmSrcNameMax -} rcm_source_names_t; - -/*! @brief Reset pin filter select in Run and Wait modes */ -typedef enum _rcm_filter_run_wait_modes { - kRcmFilterDisabled, /* all filtering disabled */ - kRcmFilterBusClk, /* Bus clock filter enabled */ - kRcmFilterLpoClk, /* LPO clock filter enabled */ - kRcmFilterReserverd /* reserved setting */ -} rcm_filter_run_wait_modes_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Gets the reset source status. - * - * This function gets the current reset source status for a specified source. - * - * @param baseAddr Register base address of RCM - * @param srcName reset source name - * @return status true or false for specified reset source - */ -bool RCM_HAL_GetSrcStatusCmd(uint32_t baseAddr, rcm_source_names_t srcName); - -/*! - * @brief Sets the reset pin filter in stop mode. - * - * This function sets the reset pin filter enable setting in stop mode. - * - * @param baseAddr Register base address of RCM - * @param enable enable or disable the filter in stop mode - */ -static inline void RCM_HAL_SetFilterStopModeCmd(uint32_t baseAddr, bool enable) -{ - BW_RCM_RPFC_RSTFLTSS(baseAddr, enable); -} - -/*! - * @brief Gets the reset pin filter in stop mode. - * - * This function gets the reset pin filter enable setting in stop mode. - * - * @param baseAddr Register base address of RCM - * @return enable true/false to enable or disable the filter in stop mode - */ -static inline bool RCM_HAL_GetFilterStopModeCmd(uint32_t baseAddr) -{ - return (bool)BR_RCM_RPFC_RSTFLTSS(baseAddr); -} - -/*! - * @brief Sets the reset pin filter in run and wait mode. - * - * This function sets the reset pin filter enable setting in run/wait mode. - * - * @param baseAddr Register base address of RCM - * @param mode to be set for reset filter in run/wait mode - */ -static inline void RCM_HAL_SetFilterRunWaitMode(uint32_t baseAddr, rcm_filter_run_wait_modes_t mode) -{ - BW_RCM_RPFC_RSTFLTSRW(baseAddr, mode); -} - -/*! - * @brief Gets the reset pin filter for stop mode. - * - * This function gets the reset pin filter enable setting for stop mode. - * - * @param baseAddr Register base address of RCM - * @return mode for reset filter in run/wait mode - */ -static inline rcm_filter_run_wait_modes_t RCM_HAL_GetFilterRunWaitMode(uint32_t baseAddr) -{ - return (rcm_filter_run_wait_modes_t)BR_RCM_RPFC_RSTFLTSRW(baseAddr); -} - -/*! - * @brief Sets the reset pin filter width. - * - * This function sets the reset pin filter width. - * - * @param baseAddr Register base address of RCM - * @param width to be set for reset filter width - */ -static inline void RCM_HAL_SetFilterWidth(uint32_t baseAddr, uint32_t width) -{ - BW_RCM_RPFW_RSTFLTSEL(baseAddr, width); -} - -/*! - * @brief Gets the reset pin filter for stop mode. - * - * This function gets the reset pin filter width. - * - * @param baseAddr Register base address of RCM - * @return width reset filter width - */ -static inline uint32_t RCM_HAL_GetFilterWidth(uint32_t baseAddr) -{ - return (uint32_t)BR_RCM_RPFW_RSTFLTSEL(baseAddr); -} - -/*! - * @brief Gets the EZP_MS_B pin assert status. - * - * This function gets the easy port mode status (EZP_MS_B) pin assert status. - * - * @param baseAddr Register base address of RCM - * @return status true - asserted, false - reasserted - */ -static inline bool RCM_HAL_GetEasyPortModeStatusCmd(uint32_t baseAddr) -{ - return (bool)BR_RCM_MR_EZP_MS(baseAddr); -} - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Reset Control Module APIs*/ -/*@{*/ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_RCM_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_features.h deleted file mode 100644 index c04bcc93ab0..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_features.h +++ /dev/null @@ -1,144 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_RTC_FEATURES_H__) -#define __FSL_RTC_FEATURES_H__ - -#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) - /* @brief Has wakeup pin (bit field CR[WPS]). */ - #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) - /* @brief Has low power features (registers MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) - /* @brief Has read/write access control (registers WAR and RAR). */ - #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) - /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_SECURITY (0) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) - /* @brief Has wakeup pin (bit field CR[WPS]). */ - #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) - /* @brief Has low power features (registers MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) - /* @brief Has read/write access control (registers WAR and RAR). */ - #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) - /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_SECURITY (1) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Has wakeup pin (bit field CR[WPS]). */ - #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) - /* @brief Has low power features (registers MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) - /* @brief Has read/write access control (registers WAR and RAR). */ - #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) - /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_SECURITY (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Has wakeup pin (bit field CR[WPS]). */ - #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) - /* @brief Has low power features (registers MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) - /* @brief Has read/write access control (registers WAR and RAR). */ - #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) - /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_SECURITY (1) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has wakeup pin (bit field CR[WPS]). */ - #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) - /* @brief Has low power features (registers MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) - /* @brief Has read/write access control (registers WAR and RAR). */ - #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) - /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_SECURITY (1) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \ - defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \ - defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ - defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || \ - defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ - defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || \ - defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || \ - defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ - defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || \ - defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || \ - defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ - defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || \ - defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ - defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || \ - defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || \ - defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || \ - defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has wakeup pin (bit field CR[WPS]). */ - #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) - /* @brief Has low power features (registers MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) - /* @brief Has read/write access control (registers WAR and RAR). */ - #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) - /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ - #define FSL_FEATURE_RTC_HAS_SECURITY (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_RTC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c deleted file mode 100644 index 9dd420eb4e0..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rtc_hal.h" -#include "fsl_device_registers.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MIN (60U) -#define MINS_IN_A_HOUR (60U) -#define HOURS_IN_A_DAY (24U) -#define DAYS_IN_A_YEAR (365U) -#define DAYS_IN_A_LEAP_YEAR (366U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Table of month length (in days) for the Un-leap-year*/ -static const uint8_t ULY[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, - 31U,30U,31U}; - -/* Table of month length (in days) for the Leap-year*/ -static const uint8_t LY[] = {0U, 31U, 29U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, - 31U,30U,31U}; - -/* Number of days from begin of the non Leap-year*/ -static const uint16_t MONTH_DAYS[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, - 212U, 243U, 273U, 304U, 334U}; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : RTC_HAL_ConvertSecsToDatetime - * Description : converts time data from seconds to a datetime structure. - * This function will convert time data from seconds to a datetime structure. - * - *END**************************************************************************/ -void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime) -{ - uint32_t x; - uint32_t Seconds, Days, Days_in_year; - const uint8_t *Days_in_month; - - /* Start from 1970-01-01*/ - Seconds = *seconds; - /* days*/ - Days = Seconds / SECONDS_IN_A_DAY; - /* seconds left*/ - Seconds = Seconds % SECONDS_IN_A_DAY; - /* hours*/ - datetime->hour = Seconds / SECONDS_IN_A_HOUR; - /* seconds left*/ - Seconds = Seconds % SECONDS_IN_A_HOUR; - /* minutes*/ - datetime->minute = Seconds / SECONDS_IN_A_MIN; - /* seconds*/ - datetime->second = Seconds % SECONDS_IN_A_MIN; - /* year*/ - datetime->year = YEAR_RANGE_START; - Days_in_year = DAYS_IN_A_YEAR; - - while (Days > Days_in_year) - { - Days -= Days_in_year; - datetime->year++; - if (datetime->year & 3U) - { - Days_in_year = DAYS_IN_A_YEAR; - } - else - { - Days_in_year = DAYS_IN_A_LEAP_YEAR; - } - } - - if (datetime->year & 3U) - { - Days_in_month = ULY; - } - else - { - Days_in_month = LY; - } - - for (x=1U; x <= 12U; x++) - { - if (Days <= (*(Days_in_month + x))) - { - datetime->month = x; - break; - } - else - { - Days -= (*(Days_in_month + x)); - } - } - - datetime->day = Days; -} - -/*FUNCTION********************************************************************** - * - * Function Name : RTC_HAL_IsDatetimeCorrectFormat - * Description : checks if the datetime is in correct format. - * This function will check if the given datetime is in the correct format. - * - *END**************************************************************************/ -bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime) -{ - bool result = false; - - /* Test correctness of given parameters*/ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || - (datetime->month > 12U) || (datetime->month < 1U) || - (datetime->day > 31U) || (datetime->day < 1U) || - (datetime->hour >= HOURS_IN_A_DAY) || (datetime->minute >= MINS_IN_A_HOUR) || - (datetime->second >= SECONDS_IN_A_MIN)) - { - /* If not correct then error*/ - result = false; - } - else - { - result = true; - } - - /* Is given year un-leap-one?*/ - /* Leap year calculation only looks for years divisible by 4 as acceptable years is limited */ - if ( result && (datetime->year & 3U)) - { - /* Does the obtained number of days exceed number of days in the appropriate month & year?*/ - if (ULY[datetime->month] < datetime->day) - { - /* If yes (incorrect datetime inserted) then error*/ - result = false; - } - } - else /* Is given year leap-one?*/ - { - /* Does the obtained number of days exceed number of days in the appropriate month & year?*/ - if (result && (LY[datetime->month] < datetime->day)) - { - /* if yes (incorrect date inserted) then error*/ - result = false; - } - } - - return result; -} - -/*FUNCTION********************************************************************** - * - * Function Name : RTC_HAL_ConvertDatetimeToSecs - * Description : converts time data from datetime to seconds. - * This function will convert time data from datetime to seconds. - * - *END**************************************************************************/ -void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds) -{ - /* Compute number of days from 1970 till given year*/ - *seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - *seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - *seconds += MONTH_DAYS[datetime->month]; - /* Add days in given month*/ - *seconds += datetime->day; - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - (*seconds)--; - } - - *seconds = ((*seconds) * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MIN) + datetime->second; -} - -/*FUNCTION********************************************************************** - * - * Function Name : RTC_HAL_Enable - * Description : initializes the RTC module. - * This function will initiate a soft-reset of the RTC module to reset - * all the RTC registers. It also enables the RTC oscillator. - * - *END**************************************************************************/ -void RTC_HAL_Enable(uint32_t rtcBaseAddr) -{ - /* Enable RTC oscillator since it is required to start the counter*/ - RTC_HAL_SetOscillatorCmd(rtcBaseAddr, true); -} - -void RTC_HAL_Disable(uint32_t rtcBaseAddr) -{ - /* Disable counter*/ - RTC_HAL_EnableCounter(rtcBaseAddr, false); - - /* Disable RTC oscillator */ - RTC_HAL_SetOscillatorCmd(rtcBaseAddr, false); -} - -void RTC_HAL_Init(uint32_t rtcBaseAddr) -{ - uint32_t seconds = 0x1; - - /* Resets the RTC registers except for the SWR bit */ - RTC_HAL_SoftwareReset(rtcBaseAddr); - RTC_HAL_SoftwareResetFlagClear(rtcBaseAddr); - - /* Set TSR register to 0x1 to avoid the TIF bit being set in the SR register */ - RTC_HAL_SetSecsReg(rtcBaseAddr, seconds); - - /* Clear the interrupt enable register */ - RTC_HAL_SetSecsIntCmd(rtcBaseAddr, false); - RTC_HAL_SetAlarmIntCmd(rtcBaseAddr, false); - RTC_HAL_SetTimeOverflowIntCmd(rtcBaseAddr, false); - RTC_HAL_SetTimeInvalidIntCmd(rtcBaseAddr, false); -} - -void RTC_HAL_SetDatetime(uint32_t rtcBaseAddr, const rtc_datetime_t * datetime) -{ - uint32_t seconds; - - /* Protect against null pointers*/ - assert(datetime); - - RTC_HAL_ConvertDatetimeToSecs(datetime, &seconds); - /* Set time in seconds */ - RTC_HAL_SetDatetimeInsecs(rtcBaseAddr, seconds); -} - -void RTC_HAL_SetDatetimeInsecs(uint32_t rtcBaseAddr, const uint32_t seconds) -{ - /* Disable counter*/ - RTC_HAL_EnableCounter(rtcBaseAddr, false); - /* Set seconds counter*/ - RTC_HAL_SetSecsReg(rtcBaseAddr, seconds); - /* Enable the counter*/ - RTC_HAL_EnableCounter(rtcBaseAddr, true); -} - -void RTC_HAL_GetDatetime(uint32_t rtcBaseAddr, rtc_datetime_t * datetime) -{ - uint32_t seconds = 0; - - /* Protect against null pointers*/ - assert(datetime); - - RTC_HAL_GetDatetimeInSecs(rtcBaseAddr, &seconds); - - RTC_HAL_ConvertSecsToDatetime(&seconds, datetime); -} - -void RTC_HAL_GetDatetimeInSecs(uint32_t rtcBaseAddr, uint32_t * seconds) -{ - /* Protect against null pointers*/ - assert(seconds); - *seconds = RTC_HAL_GetSecsReg(rtcBaseAddr); -} - -bool RTC_HAL_SetAlarm(uint32_t rtcBaseAddr, const rtc_datetime_t * date) -{ - uint32_t alrm_seconds, curr_seconds; - - /* Protect against null pointers*/ - assert(date); - - RTC_HAL_ConvertDatetimeToSecs(date, &alrm_seconds); - - /* Get the current time */ - curr_seconds = RTC_HAL_GetSecsReg(rtcBaseAddr); - - /* Make sure the alarm is for a future time */ - if (alrm_seconds <= curr_seconds) - { - return false; - } - - /* set alarm in seconds*/ - RTC_HAL_SetAlarmReg(rtcBaseAddr, alrm_seconds); - - return true; -} - -void RTC_HAL_GetAlarm(uint32_t rtcBaseAddr, rtc_datetime_t * date) -{ - uint32_t seconds = 0; - - /* Protect against null pointers*/ - assert(date); - - /* Get alarm in seconds */ - seconds = RTC_HAL_GetAlarmReg(rtcBaseAddr); - - RTC_HAL_ConvertSecsToDatetime(&seconds, date); -} - -#if FSL_FEATURE_RTC_HAS_MONOTONIC - -void RTC_HAL_GetMonotonicCounter(uint32_t rtcBaseAddr, uint64_t * counter) -{ - uint32_t tmpCountHigh = 0; - uint32_t tmpCountLow = 0; - - tmpCountHigh = RTC_HAL_GetMonotonicCounterHigh(rtcBaseAddr); - tmpCountLow = RTC_HAL_GetMonotonicCounterLow(rtcBaseAddr); - - *counter = (((uint64_t)(tmpCountHigh) << 32) | ((uint64_t)tmpCountLow)); -} - -void RTC_HAL_SetMonotonicCounter(uint32_t rtcBaseAddr, const uint64_t * counter) -{ - uint32_t tmpCountHigh = 0; - uint32_t tmpCountLow = 0; - - tmpCountHigh = (uint32_t)((*counter) >> 32); - RTC_HAL_SetMonotonicCounterHigh(rtcBaseAddr, tmpCountHigh); - tmpCountLow = (uint32_t)(*counter); - RTC_HAL_SetMonotonicCounterLow(rtcBaseAddr, tmpCountLow); -} - -bool RTC_HAL_IncrementMonotonicCounter(uint32_t rtcBaseAddr) -{ - bool result = false; - - if((!(RTC_HAL_IsMonotonicCounterOverflow(rtcBaseAddr))) && (!(RTC_HAL_IsTimeInvalid(rtcBaseAddr)))) - { - /* prepare for incrementing after write*/ - RTC_HAL_SetMonotonicEnableCmd(rtcBaseAddr, true); - - /* write anything so the counter increments*/ - BW_RTC_MCLR_MCL(rtcBaseAddr, 1U); - - result = true; - } - - return result; -} - -#endif - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h deleted file mode 100644 index 3269c554019..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h +++ /dev/null @@ -1,1976 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_RTC_HAL_H__) -#define __FSL_RTC_HAL_H__ - -#include -#include -#include -#include "fsl_rtc_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup rtc_hal - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure is used to hold the time in a simple "date" format. - */ -typedef struct RtcDatetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint16_t month; /*!< Range from 1 to 12.*/ - uint16_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint16_t hour; /*!< Range from 0 to 23.*/ - uint16_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name RTC HAL API Functions - * @{ - */ - -/*! - * @brief Initializes the RTC module. - * - * This function enables the RTC oscillator. - * - * @param rtcBaseAddr The RTC base address. - */ -void RTC_HAL_Enable(uint32_t rtcBaseAddr); - -/*! - * @brief Disables the RTC module. - * - * This function disablesS the RTC counter and oscillator. - * - * @param rtcBaseAddr The RTC base address. - */ -void RTC_HAL_Disable(uint32_t rtcBaseAddr); - -/*! - * @brief Resets the RTC module. - * - * This function initiates a soft-reset of the RTC module to reset - * the RTC registers. - * - * @param rtcBaseAddr The RTC base address.. - */ -void RTC_HAL_Init(uint32_t rtcBaseAddr); - -/*! - * @brief Converts seconds to date time format data structure. - * - * @param seconds holds the date and time information in seconds - * @param datetime holds the converted information from seconds in date and time format - */ -void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime); - -/*! - * @brief Checks whether the date time structure elements have the information that is within the range. - * - * @param datetime holds the date and time information that needs to be converted to seconds - */ -bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime); - -/*! - * @brief Converts the date time format data structure to seconds. - * - * @param datetime holds the date and time information that needs to be converted to seconds - * @param seconds holds the converted date and time in seconds - */ -void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds); - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The function converts the data from the time structure to seconds and writes the seconds - * value to the RTC register. The RTC counter is started after setting the time. - * - * @param rtcBaseAddr The RTC base address - * @param datetime [in] Pointer to structure where the date and time - * details to set are stored. - */ -void RTC_HAL_SetDatetime(uint32_t rtcBaseAddr, const rtc_datetime_t * datetime); - -/*! - * @brief Sets the RTC date and time according to the given time provided in seconds. - * - * The RTC counter is started after setting the time. - * - * @param rtcBaseAddr The RTC base address - * @param seconds [in] Time in seconds - */ -void RTC_HAL_SetDatetimeInsecs(uint32_t rtcBaseAddr, const uint32_t seconds); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * The function reads the value in seconds from the RTC register. It then converts to the - * time structure which provides the time in date, hour, minutes and seconds. - * - * @param rtcBaseAddr The RTC base address - * @param datetime [out] pointer to a structure where the date and time details are - * stored. - */ -void RTC_HAL_GetDatetime(uint32_t rtcBaseAddr, rtc_datetime_t * datetime); - -/*! - * @brief Gets the RTC time and returns it in seconds. - * - * @param rtcBaseAddr The RTC base address - * @param datetime [out] pointer to variable where the RTC time is stored in seconds - */ -void RTC_HAL_GetDatetimeInSecs(uint32_t rtcBaseAddr, uint32_t * seconds); - -/*! - * @brief Reads the value of the time alarm. - * - * @param rtcBaseAddr The RTC base address - * @param date [out] pointer to a variable where the alarm date and time - * details are stored. - */ -void RTC_HAL_GetAlarm(uint32_t rtcBaseAddr, rtc_datetime_t * date); - -/*! - * @brief Sets the RTC alarm time and enables the alarm interrupt. - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param rtcBaseAddr The RTC base address.. - * @param date [in] pointer to structure where the alarm date and time - * details will be stored at. - * @return true: success in setting the RTC alarm\n - * false: error in setting the RTC alarm. - */ -bool RTC_HAL_SetAlarm(uint32_t rtcBaseAddr, const rtc_datetime_t * date); - -#if FSL_FEATURE_RTC_HAS_MONOTONIC -/*-------------------------------------------------------------------------------------------*/ -/* RTC Monotonic Counter*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns - * them as a single value. - * - * @param rtcBaseAddr The RTC base address - * @param counter [out] pointer to variable where the value is stored. - */ -void RTC_HAL_GetMonotonicCounter(uint32_t rtcBaseAddr, uint64_t * counter); - -/*! - * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing - * the given single value. - * - * @param rtcBaseAddr The RTC base address - * @param counter [in] pointer to variable where the value is stored. - */ -void RTC_HAL_SetMonotonicCounter(uint32_t rtcBaseAddr, const uint64_t * counter); - -/*! - * @brief Increments the Monotonic Counter by one. - * - * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting - * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the - * monotonic counter low that causes it to overflow also increments the monotonic counter high. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: success\n - * false: error occurred, either time invalid or monotonic overflow flag was found - */ -bool RTC_HAL_IncrementMonotonicCounter(uint32_t rtcBaseAddr); -#endif -/*! @}*/ - -/*! - * @name RTC register access functions - * @{ - */ - -/*! - * @brief Reads the value of the time seconds counter. - * - * The time counter reads as zero if either the SR[TOF] or the SR[TIF] is set. - * - * @param rtcBaseAddr The RTC base address.. - * - * @return contents of the seconds register. - */ -static inline uint32_t RTC_HAL_GetSecsReg(uint32_t rtcBaseAddr) -{ - return BR_RTC_TSR_TSR(rtcBaseAddr); -} - -/*! - * @brief Writes to the time seconds counter. - * - * When the time counter is enabled, the TSR is read only and increments - * once every second provided the SR[TOF] or SR[TIF] is not set. When the time counter - * is disabled, the TSR can be read or written. Writing to the TSR when the - * time counter is disabled clears the SR[TOF] and/or the SR[TIF]. Writing - * to the TSR register with zero is supported, but not recommended, since the TSR - * reads as zero when either the SR[TIF] or the SR[TOF] is set (indicating the time is - * invalid). - * - * @param rtcBaseAddr The RTC base address.. - * @param seconds [in] seconds value. - * - */ -static inline void RTC_HAL_SetSecsReg(uint32_t rtcBaseAddr, const uint32_t seconds) -{ - HW_RTC_TPR_WR(rtcBaseAddr, (uint32_t)0x00000000U); - BW_RTC_TSR_TSR(rtcBaseAddr, seconds); -} - -/*! - * @brief Sets the time alarm and clears the time alarm flag. - * - * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] - * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR - * clears the SR[TAF]. - * - * @param rtcBaseAddr The RTC base address.. - * @param seconds [in] alarm value in seconds. - */ -static inline void RTC_HAL_SetAlarmReg(uint32_t rtcBaseAddr, const uint32_t seconds) -{ - BW_RTC_TAR_TAR(rtcBaseAddr, seconds); -} - -/*! - * @brief Gets the time alarm register contents. - * - * @param rtcBaseAddr The RTC base address - * - * @return contents of the alarm register. - */ -static inline uint32_t RTC_HAL_GetAlarmReg(uint32_t rtcBaseAddr) -{ - return BR_RTC_TAR_TAR(rtcBaseAddr); -} - - -/*! - * @brief Reads the value of the time prescaler. - * - * The time counter reads as zero when either the SR[TOF] or the SR[TIF] is set. - * - * @param rtcBaseAddr The RTC base address - * - * @return contents of the time prescaler register. - */ -static inline uint16_t RTC_HAL_GetPrescaler(uint32_t rtcBaseAddr) -{ - return BR_RTC_TPR_TPR(rtcBaseAddr); -} - -/*! - * @brief Sets the time prescaler. - * - * When the time counter is enabled, the TPR is read only and increments - * every 32.768 kHz clock cycle. When the time counter is disabled, the TPR - * can be read or written. The TSR[TSR] increments when bit 14 of the TPR - * transitions from a logic one to a logic zero. - * - * @param rtcBaseAddr The RTC base address - * @param prescale Prescaler value - */ -static inline void RTC_HAL_SetPrescaler(uint32_t rtcBaseAddr, const uint16_t prescale) -{ - BW_RTC_TPR_TPR(rtcBaseAddr, prescale); -} - -/*-------------------------------------------------------------------------------------------*/ -/* RTC Time Compensation*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Reads the time compensation register contents. - * - * @param rtcBaseAddr The RTC base address - * - * @return time compensation register contents. - */ -static inline uint32_t RTC_HAL_GetCompensationReg(uint32_t rtcBaseAddr) -{ - return HW_RTC_TCR_RD(rtcBaseAddr); -} - -/*! - * @brief Writes the value to the RTC TCR register. - * - * @param rtcBaseAddr The RTC base address - * @param compValue value to be written to the compensation register. - */ -static inline void RTC_HAL_SetCompensationReg(uint32_t rtcBaseAddr, const uint32_t compValue) -{ - HW_RTC_TCR_WR(rtcBaseAddr, compValue); -} - -/*! - * @brief Reads the current value of the compensation interval counter, which is the field CIC in the RTC TCR register. - * - * @param rtcBaseAddr The RTC base address.. - * - * @return compensation interval value. - */ -static inline uint8_t RTC_HAL_GetCompensationIntervalCounter(uint32_t rtcBaseAddr) -{ - return BR_RTC_TCR_CIC(rtcBaseAddr); -} - -/*! - * @brief Reads the current value used by the compensation logic for the present second interval. - * - * @param rtcBaseAddr The RTC base address - * - * @return time compensation value - */ -static inline uint8_t RTC_HAL_GetTimeCompensationValue(uint32_t rtcBaseAddr) -{ - return BR_RTC_TCR_TCV(rtcBaseAddr); -} - -/*! - * @brief Reads the compensation interval register. - - * The value is the configured compensation interval in seconds from 1 to 256 to control - * how frequently the time compensation register should adjust the - * number of 32.768 kHz cycles in each second. The value is one - * less than the number of seconds (for example, zero means a - * configuration for a compensation interval of one second). - * - * @param rtcBaseAddr The RTC base address.. - * - * @return compensation interval in seconds. - */ -static inline uint8_t RTC_HAL_GetCompensationIntervalRegister(uint32_t rtcBaseAddr) -{ - return BR_RTC_TCR_CIR(rtcBaseAddr); -} - -/*! - * @brief Writes the compensation interval. - * - * This configures the compensation interval in seconds from 1 to 256 to control - * how frequently the TCR should adjust the number of 32.768 kHz - * cycles in each second. The value written should be one less than - * the number of seconds (for example, write zero to configure for - * a compensation interval of one second). This register is double - * buffered and writes do not take affect until the end of the - * current compensation interval. - * - * @param rtcBaseAddr The RTC base address.. - * @param value the compensation interval value. - */ -static inline void RTC_HAL_SetCompensationIntervalRegister(uint32_t rtcBaseAddr, const uint8_t value) -{ - BW_RTC_TCR_CIR(rtcBaseAddr, value); -} - -/*! - * @brief Reads the time compensation value which is the configured number - * of 32.768 kHz clock cycles in each second. - * - * @param rtcBaseAddr The RTC base address - * - * @return time compensation value. - */ -static inline uint8_t RTC_HAL_GetTimeCompensationRegister(uint32_t rtcBaseAddr) -{ - return BR_RTC_TCR_TCR(rtcBaseAddr); -} - -/*! - * @brief Writes to the field Time Compensation Register (TCR) of the RTC Time Compensation Register (RTC_TCR). - * - * Configures the number of 32.768 kHz clock cycles in each second. This register is double - * buffered and writes do not take affect until the end of the - * current compensation interval. - * 80h Time prescaler register overflows every 32896 clock cycles. - * .. ...\n - * FFh Time prescaler register overflows every 32769 clock cycles.\n - * 00h Time prescaler register overflows every 32768 clock cycles.\n - * 01h Time prescaler register overflows every 32767 clock cycles.\n - * ... ...\n - * 7Fh Time prescaler register overflows every 32641 clock cycles.\n - * - * @param rtcBaseAddr The RTC base address - * @param comp_value value of the time compensation. - */ -static inline void RTC_HAL_SetTimeCompensationRegister(uint32_t rtcBaseAddr, const uint8_t compValue) -{ - BW_RTC_TCR_TCR(rtcBaseAddr, compValue); -} - -/*-------------------------------------------------------------------------------------------*/ -/* RTC Control*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Enables/disables the oscillator configuration for the 2pF load. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables load\n - * false: disables load. - */ -static inline void RTC_HAL_SetOsc2pfLoadCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_CR_SC2P(rtcBaseAddr, enable); -} - -/*! - * @brief Reads the oscillator 2pF load configure bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: 2pF additional load enabled.\n - * false: 2pF additional load disabled. - */ -static inline bool RTC_HAL_GetOsc2pfLoad(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_SC2P(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the oscillator configuration for the 4pF load. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables load.\n - * false: disables load - */ -static inline void RTC_HAL_SetOsc4pfLoadCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_CR_SC4P(rtcBaseAddr, enable); -} - -/*! - * @brief Reads the oscillator 4pF load configure bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: 4pF additional load enabled.\n - * false: 4pF additional load disabled. - */ -static inline bool RTC_HAL_GetOsc4pfLoad(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_SC4P(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the oscillator configuration for the 8pF load. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables load.\n - * false: disables load. - */ -static inline void RTC_HAL_SetOsc8pfLoadCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_CR_SC8P(rtcBaseAddr, enable); -} - -/*! - * @brief Reads the oscillator 8pF load configure bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: 8pF additional load enabled.\n - * false: 8pF additional load disabled. - */ -static inline bool RTC_HAL_GetOsc8pfLoad(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_SC8P(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the oscillator configuration for the 16pF load. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables load.\n - * false: disables load. - */ -static inline void RTC_HAL_SetOsc16pfLoadCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_CR_SC16P(rtcBaseAddr, enable); -} - -/*! - * @brief Reads the oscillator 16pF load configure bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: 16pF additional load enabled.\n - * false: 16pF additional load disabled. - */ -static inline bool RTC_HAL_GetOsc16pfLoad(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_SC16P(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the 32 kHz clock output to other peripherals. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables clock out.\n - * false: disables clock out. - */ -static inline void RTC_HAL_SetClockOutCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_CR_CLKO(rtcBaseAddr, !enable); -} - -/*! - * @brief Reads the RTC_CR CLKO bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: 32 kHz clock is not output to other peripherals.\n - * false: 32 kHz clock is output to other peripherals. - */ -static inline bool RTC_HAL_GetClockOutCmd(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_CLKO(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the oscillator. - * - * After enabling, waits for the oscillator startup time before enabling the - * time counter to allow the 32.768 kHz clock time to stabilize. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables oscillator.\n - * false: disables oscillator. - */ -static inline void RTC_HAL_SetOscillatorCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_CR_OSCE(rtcBaseAddr, enable); -/* TODO: Wait for oscillator startup period if enabling the oscillator - if (enable) -*/ - -} - -/*! - * @brief Reads the RTC_CR OSCE bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: 32.768 kHz oscillator is enabled - * false: 32.768 kHz oscillator is disabled. - */ -static inline bool RTC_HAL_IsOscillatorEnabled(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_OSCE(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the update mode. - * - * This mode allows the time counter enable bit in the SR to be written - * even when the status register is locked. - * When set, the time counter enable, can always be written if the - * TIF (Time Invalid Flag) or TOF (Time Overflow Flag) are set or - * if the time counter enable is clear. For devices with the - * monotonic counter it allows the monotonic enable to be written - * when it is locked. When set, the monotonic enable can always be - * written if the TIF (Time Invalid Flag) or TOF (Time Overflow Flag) - * are set or if the montonic counter enable is clear. - * For devices with tamper detect it allows the it to be written - * when it is locked. When set, the tamper detect can always be - * written if the TIF (Time Invalid Flag) is clear. - * Note: Tamper and Monotonic features are not available in all MCUs. - * - * @param rtcBaseAddr The RTC base address - * @param lock can be true or false\n - * true: registers can be written when locked under limited conditions\n - * false: registers cannot be written when locked - */ -static inline void RTC_HAL_SetUpdateModeCmd(uint32_t rtcBaseAddr, bool lock) -{ - BW_RTC_CR_UM(rtcBaseAddr, lock); -} - -/*! - * @brief Reads the RTC_CR update mode bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Registers can be written when locked under limited conditions. - * false: Registers cannot be written when locked. - */ -static inline bool RTC_HAL_GetUpdateMode(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_UM(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the supervisor access. - * - * This configures non-supervisor mode write access to all RTC registers and - * non-supervisor mode read access to RTC tamper/monotonic registers. - * Note: Tamper and Monotonic features are NOT available in all MCUs. - * - * @param rtcBaseAddr The RTC base address.. - * @param enableRegWrite can be true or false\n - * true: non-supervisor mode write accesses are supported.\n - * false: non-supervisor mode write accesses are not supported and generate a bus error. - */ -static inline void RTC_HAL_SetSupervisorAccessCmd(uint32_t rtcBaseAddr, bool enableRegWrite) -{ - BW_RTC_CR_SUP(rtcBaseAddr, enableRegWrite); -} - -/*! - * @brief Reads the RTC_CR SUP bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Non-supervisor mode write accesses are supported - * false: Non-supervisor mode write accesses are not supported. - */ -static inline bool RTC_HAL_GetSupervisorAccess(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_SUP(rtcBaseAddr); -} - -#if FSL_FEATURE_RTC_HAS_WAKEUP_PIN -/*! - * @brief Enables/disables the wakeup pin. - * - * Note: The wakeup pin is optional and not available on all devices. - * - * @param rtcBaseAddr The RTC base address - * @param enable_wp can be true or false\n - * true: enables wakeup-pin, wakeup pin asserts if the - * RTC interrupt asserts and the chip is powered down.\n - * false: disables wakeup-pin. - */ -static inline void RTC_HAL_SetWakeupPinCmd(uint32_t rtcBaseAddr, bool enableWp) -{ - BW_RTC_CR_WPE(rtcBaseAddr, enableWp); -} - -/*! - * @brief Reads the RTC_CR WPE bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Wakeup pin is enabled. - * false: Wakeup pin is disabled. - */ -static inline bool RTC_HAL_GetWakeupPin(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_WPE(rtcBaseAddr); -} -#endif - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR - * registers. The SWR bit is cleared after VBAT POR and by software - * explicitly clearing it. - * Note: access control features (RTC_WAR and RTC_RAR registers) - * are not available in all MCUs. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_SoftwareReset(uint32_t rtcBaseAddr) -{ - BW_RTC_CR_SWR(rtcBaseAddr, 1u); -} - -/*! - * @brief Clears the software reset flag. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_SoftwareResetFlagClear(uint32_t rtcBaseAddr) -{ - BW_RTC_CR_SWR(rtcBaseAddr, 0u); -} - -/*! - * @brief Reads the RTC_CR SWR bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: SWR is set. - * false: SWR is cleared. - */ -static inline bool RTC_HAL_ReadSoftwareResetStatus(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_CR_SWR(rtcBaseAddr); -} - -/*-------------------------------------------------------------------------------------------*/ -/* RTC Status*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Reads the time counter status (enabled/disabled). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: time counter is enabled, time seconds register and time - * prescaler register are not writeable, but increment.\n - * false: time counter is disabled, time seconds register and - * time prescaler register are writeable, but do not increment. - */ -static inline bool RTC_HAL_IsCounterEnabled(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_SR_TCE(rtcBaseAddr); -} - -/*! - * @brief Changes the time counter status. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: enables the time counter\n - * false: disables the time counter. - */ -static inline void RTC_HAL_EnableCounter(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_SR_TCE(rtcBaseAddr, enable); -} - -#if FSL_FEATURE_RTC_HAS_MONOTONIC -/*! - * @brief Reads the value of the Monotonic Overflow Flag (MOF). - * - * This flag is set when the monotonic counter is enabled and the monotonic - * counter high overflows. The monotonic counter does not increment and - * reads as zero when this bit is set. This bit is cleared by writing the monotonic - * counter high register when the monotonic counter is disabled. - * - * @param rtcBaseAddr The RTC base address.. - * - * @return true: monotonic counter overflow has occurred and monotonic - * counter is read as zero.\n - * false: No monotonic counter overflow has occurred. - */ -static inline bool RTC_HAL_IsMonotonicCounterOverflow(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_SR_MOF(rtcBaseAddr); -} -#endif - -/*! - * @brief Checks whether the configured time alarm has occurred. - * - * Reads time alarm flag (TAF). This flag is set when the time - * alarm register (TAR) equals the time seconds register (TSR) and - * the TSR increments. This flag is cleared by writing the TAR register. - * - * @param rtcBaseAddr The RTC base address.. - * - * @return true: time alarm has occurred.\n - * false: no time alarm occurred. - */ -static inline bool RTC_HAL_HasAlarmOccured(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_SR_TAF(rtcBaseAddr); -} - -/*! - * @brief Checks whether a counter overflow has occurred. - * - * Reads the value of RTC Status Register (RTC_SR), field Time - * Overflow Flag (TOF). This flag is set when the time counter is - * enabled and overflows. The TSR and TPR do not increment and read - * as zero when this bit is set. This flag is cleared by writing the - * TSR register when the time counter is disabled. - * - * @param rtcBaseAddr The RTC base address.. - * - * @return true: time overflow occurred and time counter is zero.\n - * false: no time overflow occurred. - */ -static inline bool RTC_HAL_HasCounterOverflowed(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_SR_TOF(rtcBaseAddr); -} - -/*! - * @brief Checks whether the time has been marked as invalid. - * - * Reads the value of RTC Status Register (RTC_SR), field Time - * Invalid Flag (TIF). This flag is set on VBAT POR or software - * reset. The TSR and TPR do not increment and read as zero when - * this bit is set. This flag is cleared by writing the TSR - * register when the time counter is disabled. - * - * @param rtcBaseAddr The RTC base address.. - * - * @return true: time is INVALID and time counter is zero.\n - * false: time is valid. - */ -static inline bool RTC_HAL_IsTimeInvalid(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_SR_TIF(rtcBaseAddr); -} - -/*-------------------------------------------------------------------------------------------*/ -/* RTC Lock*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Configures the register lock to other module fields. - * - * @param rtcBaseAddr The RTC base address.. - * @param bitfields [in] configuration flags:\n - * Valid bitfields:\n - * LRL: Lock Register Lock \n - * SRL: Status Register Lock \n - * CRL: Control Register Lock \n - * TCL: Time Compensation Lock \n - * - * For MCUs that have the Tamper Detect only: \n - * TIL: Tamper Interrupt Lock \n - * TTL: Tamper Trim Lock \n - * TDL: Tamper Detect Lock \n - * TEL: Tamper Enable Lock \n - * TTSL: Tamper Time Seconds Lock \n - * - * For MCUs that have the Monotonic Counter only: \n - * MCHL: Monotonic Counter High Lock \n - * MCLL: Monotonic Counter Low Lock \n - * MEL: Monotonic Enable Lock \n - */ -static inline void RTC_HAL_SetLockRegistersCmd(uint32_t rtcBaseAddr, hw_rtc_lr_t bitfields) -{ - uint32_t valid_flags = 0; - - valid_flags |= (BM_RTC_LR_LRL | BM_RTC_LR_SRL | BM_RTC_LR_CRL | - BM_RTC_LR_TCL); - -#if FSL_FEATURE_RTC_HAS_MONOTONIC - valid_flags |= (BM_RTC_LR_MCHL | BM_RTC_LR_MCLL | BM_RTC_LR_MEL); -#endif - HW_RTC_LR_WR(rtcBaseAddr, (bitfields.U) & valid_flags); -} - -/*! - * @brief Obtains the lock status of the lock register. - * - * Reads the value of the field Lock Register Lock (LRL) of the RTC Lock Register (RTC_LR). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: lock register is not locked and writes complete as normal.\n - * false: lock register is locked and writes are ignored. - */ -static inline bool RTC_HAL_GetLockRegLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_LRL(rtcBaseAddr); -} - -/*! - * @brief Changes the lock status of the lock register. - * - * Writes to the field Lock Register Lock (LRL) of the RTC Lock Register (RTC_LR). - * Once cleared, this can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - * @param lock can be true or false\n - * true: Lock register is not locked and writes complete as normal.\n - * false: Lock register is locked and writes are ignored. - */ -static inline void RTC_HAL_SetLockRegLock(uint32_t rtcBaseAddr, bool lock) -{ - BW_RTC_LR_LRL(rtcBaseAddr, (uint32_t) lock); -} - -/*! - * @brief Obtains the state of the status register lock. - * - * Reads the value of field Status Register Lock (SRL) of the RTC Lock Register (RTC_LR), which is the field Status Register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Status register is not locked and writes complete as - * normal.\n - * false: Status register is locked and writes are ignored. - */ -static inline bool RTC_HAL_GetStatusRegLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_SRL(rtcBaseAddr); -} - -/*! - * @brief Changes the state of the status register lock. - * - * Writes to the field Status Register Lock (SRL) of the RTC Lock Register (RTC_LR). - * Once cleared, this can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - * @param lock can be true or false\n - * true: Status register is not locked and writes complete as - * normal.\n - * false: Status register is locked and writes are ignored. - */ -static inline void RTC_HAL_SetStatusRegLock(uint32_t rtcBaseAddr, bool lock) -{ - BW_RTC_LR_SRL(rtcBaseAddr, (uint32_t) lock); -} - -/*! - * @brief Obtains the state of the control register lock. - * - * Reads the field Control Register Lock (CRL)value of the RTC Lock Register (RTC_LR). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Control register is not locked and writes complete as - * normal.\n - * false: Control register is locked and writes are ignored. - */ -static inline bool RTC_HAL_GetControlRegLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_CRL(rtcBaseAddr); -} - -/*! - * @brief Changes the state of the control register lock. - * - * Writes to the field Control Register Lock (CRL) of the RTC Lock Register (RTC_LR). - * Once cleared, this can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - * @param lock can be true or false\n - * true: Control register is not locked and writes complete - * as normal.\n - * false: Control register is locked and writes are ignored. - */ -static inline void RTC_HAL_SetControlRegLock(uint32_t rtcBaseAddr, bool lock) -{ - BW_RTC_LR_CRL(rtcBaseAddr, (uint32_t) lock); -} - -/*! - * @brief Obtains the state of the time compensation lock. - * - * Reads the field Time Compensation Lock (TCL) value of the RTC Lock Register (RTC_LR). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Time compensation register is not locked and writes - * complete as normal.\n - * false: Time compensation register is locked and writes are - * ignored. - */ -static inline bool RTC_HAL_GetTimeCompLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_TCL(rtcBaseAddr); -} - -/*! - * @brief Changes the state of the time compensation lock. - * - * Writes to the field Time Compensation Lock (TCL) of the RTC Lock Register (RTC_LR). - * Once cleared, this can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - * @param lock can be true or false\n - * true: Time compensation register is not locked and writes - * complete as normal.\n - * false: Time compensation register is locked and writes are - * ignored. - */ -static inline void RTC_HAL_SetTimeCompLock(uint32_t rtcBaseAddr, bool lock) -{ - BW_RTC_LR_TCL(rtcBaseAddr, (uint32_t) lock); -} - -#if FSL_FEATURE_RTC_HAS_MONOTONIC -/*! - * @brief Reads the value of the Monotonic Counter High Lock. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Monotonic counter high register is not locked and writes - * complete as normal.\n - * false: Monotonic counter high register is locked and writes are - * ignored. - */ -static inline bool RTC_HAL_ReadMonotonicHcounterLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_MCHL(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter High Lock (MCHL) of the RTC Lock Register (RTC_LR). - * - * Once done, this flag can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicHcounterLock(uint32_t rtcBaseAddr) -{ - BW_RTC_LR_MCHL(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the value of the Monotonic Counter Low Lock. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Monotonic counter low register is not locked and writes - * complete as normal.\n - * false: Monotonic counter low register is locked and writes are - * ignored. - */ -static inline bool RTC_HAL_ReadMonotonicLcounterLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_MCLL(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter Low Lock (MCLL) of the RTC Lock Register (RTC_LR). - * - * Once done, this flag can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicLcounterLock(uint32_t rtcBaseAddr) -{ - BW_RTC_LR_MCLL(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the value of the Monotonic Enable Lock. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Monotonic enable register is not locked and writes - * complete as normal.\n - * false: Monotonic enable register is locked and writes are - * ignored. - */ -static inline bool RTC_HAL_ReadMonotonicEnableLock(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_LR_MEL(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the Monotonic Enable Lock field of the RTC Lock Register (RTC_LR). - * - * Once done, this flag can only be set by VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicEnableLock(uint32_t rtcBaseAddr) -{ - BW_RTC_LR_MEL(rtcBaseAddr, 0U); -} -#endif - -/*-------------------------------------------------------------------------------------------*/ -/* RTC Interrupt Enable*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Checks whether the Time Seconds Interrupt is enabled/disabled. - * - * Reads the value of field Time Seconds Interrupt Enable (TSIE)of the RTC Interrupt Enable Register (RTC_IER). - * The seconds interrupt is an edge-sensitive - * interrupt with a dedicated interrupt vector. It is generated once a second - * and requires no software overhead (there is no corresponding status flag to - * clear). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Seconds interrupt is enabled.\n - * false: Seconds interrupt is disabled. - */ -static inline bool RTC_HAL_IsSecsIntEnabled(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_IER_TSIE(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the Time Seconds Interrupt. - * - * Writes to the field Time Seconds - * Interrupt Enable (TSIE) of the RTC Interrupt Enable Register (RTC_IER). - * Note: The seconds interrupt is an edge-sensitive interrupt with a - * dedicated interrupt vector. It is generated once a second and - * requires no software overhead (there is no corresponding status - * flag to clear). - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: Seconds interrupt is enabled.\n - * false: Seconds interrupt is disabled. - */ -static inline void RTC_HAL_SetSecsIntCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_IER_TSIE(rtcBaseAddr, (uint32_t) enable); -} - -#if FSL_FEATURE_RTC_HAS_MONOTONIC - -/*! - * @brief Checks whether the Monotonic Overflow Interrupt is enabled/disabled. - * - * Reads the value of the RTC Interrupt Enable Register (RTC_IER), field - * Monotonic Overflow Interrupt Enable (MOIE). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Monotonic overflow flag does generate an interrupt.\n - * false: Monotonic overflow flag does not generate an interrupt. - */ -static inline bool RTC_HAL_ReadMonotonicOverflowInt(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_IER_MOIE(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the Monotonic Overflow Interrupt Enable. - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: Monotonic overflow flag does generate an interrupt.\n - * false: Monotonic overflow flag does not generate an interrupt. - */ -static inline void RTC_HAL_SetMonotonicOverflowIntCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_IER_MOIE(rtcBaseAddr, (uint32_t)enable); -} - -#endif - -/*! - * @brief Checks whether the Time Alarm Interrupt is enabled/disabled. - * - * Reads the field Time Alarm Interrupt Enable (TAIE) value of the RTC Interrupt Enable Register (RTC_IER). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Time alarm flag does generate an interrupt.\n - * false: Time alarm flag does not generate an interrupt. - */ -static inline bool RTC_HAL_ReadAlarmInt(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_IER_TAIE(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the Time Alarm Interrupt. - * - * Writes to the field Time Alarm - * Interrupt Enable (TAIE) of the RTC Interrupt Enable Register (RTC_IER). - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: Time alarm flag does generate an interrupt.\n - * false: Time alarm flag does not generate an interrupt. - */ -static inline void RTC_HAL_SetAlarmIntCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_IER_TAIE(rtcBaseAddr, (uint32_t) enable); -} - -/*! - * @brief Checks whether the Time Overflow Interrupt is enabled/disabled. - * - * Reads the field - * Time Overflow Interrupt Enable (TOIE) of the value of the RTC Interrupt Enable Register (RTC_IER). - * - * @param rtcBaseAddr The RTC base address.. - * - * @return true: Time overflow flag does generate an interrupt.\n - * false: Time overflow flag does not generate an interrupt. - */ -static inline bool RTC_HAL_ReadTimeOverflowInt(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_IER_TOIE(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the Time Overflow Interrupt. - * - * Writes to the field Time Overflow Interrupt Enable (TOIE) of the RTC Interrupt Enable Register (RTC_IER). - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: Time overflow flag does generate an interrupt.\n - * false: Time overflow flag does not generate an interrupt. - */ -static inline void RTC_HAL_SetTimeOverflowIntCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_IER_TOIE(rtcBaseAddr, (uint32_t) enable); -} - -/*! - * @brief Checks whether the Time Invalid Interrupt is enabled/disabled. - * - * Reads the value of the field Time - * Invalid Interrupt Enable (TIIE)of the RTC Interrupt Enable Register (RTC_IER). - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Time invalid flag does generate an interrupt.\n - * false: Time invalid flag does not generate an interrupt. - */ -static inline bool RTC_HAL_ReadTimeInvalidInt(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_IER_TIIE(rtcBaseAddr); -} - -/*! - * @brief Enables/disables the Time Invalid Interrupt. - * - * Writes to the field Time Invalid - * Interrupt Enable (TIIE) of the RTC Interrupt Enable Register (RTC_IER). - * - * @param rtcBaseAddr The RTC base address - * @param enable can be true or false\n - * true: Time invalid flag does generate an interrupt.\n - * false: Time invalid flag does not generate an interrupt. - */ -static inline void RTC_HAL_SetTimeInvalidIntCmd(uint32_t rtcBaseAddr, bool enable) -{ - BW_RTC_IER_TIIE(rtcBaseAddr, (uint32_t) enable); -} - -#if FSL_FEATURE_RTC_HAS_MONOTONIC - -/*-------------------------------------------------------------------------------------------*/ -/* RTC Monotonic Enable*/ -/*-------------------------------------------------------------------------------------------*/ - -/*! - * @brief Reads the Monotonic Counter Enable bit. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: This means writing to the monotonic counter increments the counter by one and - * the value written is ignored.\n - * false: This means writing to the monotonic counter loads the counter with the - * value written. - */ -static inline bool RTC_HAL_ReadMonotonicEnable(uint32_t rtcBaseAddr) -{ - /* Reads value of the RTC_MER register, field Monotonic Counter Enable (MCE). */ - return (bool)BR_RTC_MER_MCE(rtcBaseAddr); -} - -/*! - * @brief Changes the state of Monotonic Counter Enable bit. - * - * @param rtcBaseAddr The RTC base address - * @param enable value to be written to the MER[MCE] bit\n - * true: Set the bit to 1 which means writing to the monotonic counter will increment - * the counter by one and the value written will be ignored.\n - * false: Set the bit to 0 which means writing to the monotonic counter loads the counter - * with the value written. - */ -static inline void RTC_HAL_SetMonotonicEnableCmd(uint32_t rtcBaseAddr, bool enable) -{ - /* Writes to the RTC_MER registers Monotonic Counter Enable (MCE) bit.*/ - BW_RTC_MER_MCE(rtcBaseAddr, (uint32_t) enable); -} - -/*! - * @brief Reads the values of the Monotonic Counter Low register. - * - * @param rtcBaseAddr The RTC base address - * - * @return Monotonic Counter Low value. - */ -static inline uint32_t RTC_HAL_GetMonotonicCounterLow(uint32_t rtcBaseAddr) -{ - return BR_RTC_MCLR_MCL(rtcBaseAddr); -} - -/*! - * @brief Reads the values of the Monotonic Counter High register. - * - * @param rtcBaseAddr The RTC base address - * - * @return Monotonic Counter High value. - */ -static inline uint32_t RTC_HAL_GetMonotonicCounterHigh(uint32_t rtcBaseAddr) -{ - return BR_RTC_MCHR_MCH(rtcBaseAddr); -} - -/*! - * @brief Writes values of the Monotonic Counter Low register. - * - * @param rtcBaseAddr The RTC base address - * @param counter [in] Monotonic Counter Low value to be stored. - */ -static inline void RTC_HAL_SetMonotonicCounterLow(uint32_t rtcBaseAddr, const uint32_t counter) -{ - /* enable writing to the counter*/ - BW_RTC_MER_MCE(rtcBaseAddr, 0U); - BW_RTC_MCLR_MCL(rtcBaseAddr, counter); -} - -/*! - * @brief Writes values of the Monotonic Counter High register. - * - * @param rtcBaseAddr The RTC base address - * @param counter [in] Monotonic Counter High value to be stored. - */ -static inline void RTC_HAL_SetMonotonicCounterHigh(uint32_t rtcBaseAddr, const uint32_t counter) -{ - /* enable writing to the counter*/ - BW_RTC_MER_MCE(rtcBaseAddr, 0U); - BW_RTC_MCHR_MCH(rtcBaseAddr, counter); -} - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - -#if FSL_FEATURE_RTC_HAS_ACCESS_CONTROL - -#if FSL_FEATURE_RTC_HAS_MONOTONIC -/*! - * @brief Reads the field Monotonic Counter High Write (MCHW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the monotonic counter high register will complete as normal.\n - * false: Writes to the monotonic counter high register are ignored. - */ -static inline bool RTC_HAL_GetMonotonicHcountWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_MCHW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter High Write (MCHW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicHcountWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_MCHW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Monotonic Counter Low Write (MCLW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the monotonic counter low register will complete as normal.\n - * false: Writes to the monotonic counter low register are ignored. - */ -static inline bool RTC_HAL_GetMonotonicLcountWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_MCLW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter High Write (MCLW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by the system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address.. - */ -static inline void RTC_HAL_ClearMonotonicLcountWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_MCLW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Monotonic Enable Register Write (MERW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the monotonic enable register will complete as normal.\n - * false: Writes to the monotonic enable register are ignored. - */ -static inline bool RTC_HAL_GetMonotonicEnableWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_MERW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter High Write (MERW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicEnableWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_MERW(rtcBaseAddr, 0U); -} -#endif - -/*! - * @brief Reads the field Interrupt Enable Register Write (IERW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the interrupt enable register will complete as normal.\n - * false: Writes to the interrupt enable register are ignored. - */ -static inline bool RTC_HAL_GetIntEnableWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_IERW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Interrupt Enable Register Write (IERW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearIntEnableWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_IERW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Lock Register Write (LRW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the lock register will complete as normal.\n - * false: Writes to the lock register are ignored. - */ -static inline bool RTC_HAL_GetLockWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_LRW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Lock Register Write (LRW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearLockWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_LRW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Status Register Write (SRW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the status register completes as normal.\n - * false: Writes to the status register are ignored. - */ -static inline bool RTC_HAL_GetStatusWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_SRW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Status Register Write (SRW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearStatusWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_SRW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Control Register Write (CRW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the control register will complete as normal.\n - * false: Writes to the control register are ignored. - */ -static inline bool RTC_HAL_GetControlWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_CRW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Control Register Write (CRW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearControlWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_CRW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Compensation Register Write (TCRW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the time compensation register will complete as normal.\n - * false: Writes to the time compensation register are ignored. - */ -static inline bool RTC_HAL_GetCompensationWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_TCRW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Compensation Register Write (TCRW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearCompensationWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_TCRW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Alarm Register Write (TARW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the time alarm register will complete as normal.\n - * false: Writes to the time alarm register are ignored. - */ -static inline bool RTC_HAL_GetAlarmWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_TARW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Alarm Register Write (TARW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearAlarmWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_TARW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Prescaler Register Write (TPRW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the time prescaler register will complete as normal.\n - * false: Writes to the time prescaler register are ignored. - */ -static inline bool RTC_HAL_GetPrescalerWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_TPRW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Prescaler Register Write (TPRW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearPrescalerWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_TPRW(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Seconds Register Write (TSRW) value of the register RTC_WAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Writes to the time seconds register will complete as normal.\n - * false: Writes to the time seconds register are ignored. - */ -static inline bool RTC_HAL_GetSecsWreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_WAR_TSRW(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Seconds Register Write (TSRW) of the RTC_WAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearSecsWreg(uint32_t rtcBaseAddr) -{ - BW_RTC_WAR_TSRW(rtcBaseAddr, 0U); -} - -#if FSL_FEATURE_RTC_HAS_MONOTONIC - -/*! - * @brief Reads the field Monotonic Counter High Read (MCHR) value of the register RTC_RAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the monotonic counter high register completes as normal.\n - * false: Reads to the monotonic counter high register are ignored. - */ -static inline bool RTC_HAL_GetMonotonicHcountRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_MCHR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter High Read (MCHR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicHcountRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_MCHR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Monotonic Counter Low Read (MCLR) value of the register RTC_RAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the monotonic counter low register will complete as normal.\n - * false: Reads to the monotonic counter low register are ignored. - */ -static inline bool RTC_HAL_GetMonotonicLcountRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_MCLR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Counter Low Read (MCLR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicLcountRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_MCLR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Monotonic Enable Register Read (MERR) value of the register RTC_RAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the monotonic enable register completes as normal.\n - * false: Reads to the monotonic enable register are ignored. - */ -static inline bool RTC_HAL_GetMonotonicEnableRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_MERR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Monotonic Enable Register Read (MERR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearMonotonicEnableRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_MERR(rtcBaseAddr, 0U); -} - -#endif - -/*! - * @brief Reads the field Interrupt Enable Register Read (IERR) value of the register RTC_RAR. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the interrupt enable register completes as normal.\n - * false: Reads to the interrupt enable register are ignored. - */ -static inline bool RTC_HAL_GetIntEnableRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_IERR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Interrupt Enable Register Read (IERR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearIntEnableRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_IERR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Lock Register Read (LRR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the lock register will complete as normal.\n - * false: Reads to the lock register are ignored. - */ -static inline bool RTC_HAL_GetLockRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_LRR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Lock Register Read (LRR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearLockRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_LRR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Status Register Read (SRR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the status register completes as normal.\n - * false: Reads to the status register are ignored. - */ -static inline bool RTC_HAL_GetStatusRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_SRR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Status Register Read (SRR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearStatusRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_SRR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Control Register Read (CRR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the control register completes as normal.\n - * false: Reads to the control register are ignored. - */ -static inline bool RTC_HAL_GetControlRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_CRR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Control Register Read (CRR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearControlRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_CRR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Compensation Register Read (TCRR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the time compensation register completes as normal.\n - * false: Reads to the time compensation register are ignored. - */ -static inline bool RTC_HAL_GetCompensationRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_TCRR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Compensation Register Read (TCRR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearCompensationRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_TCRR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Alarm Register Read (TARR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the time alarm register completes as normal.\n - * false: Reads to the time alarm register are ignored. - */ -static inline bool RTC_HAL_GetAlarmRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_TARR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Alarm Register Read (TARR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearAlarmRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_TARR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Prescaler Register Read (TPRR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the time prescaler register completes as normal.\n - * false: Reads to the time prescaler register are ignored. - */ -static inline bool RTC_HAL_GetPrescalerRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_TPRR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Prescaler Register Read (TPRR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearPrescalerRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_TPRR(rtcBaseAddr, 0U); -} - -/*! - * @brief Reads the field Time Seconds Register Read (TSRR) value of the RTC_RAR register. - * - * @param rtcBaseAddr The RTC base address - * - * @return true: Reads to the time seconds register completes as normal.\n - * false: Reads to the time seconds register are ignored. - */ -static inline bool RTC_HAL_GetSecsRreg(uint32_t rtcBaseAddr) -{ - return (bool)BR_RTC_RAR_TSRR(rtcBaseAddr); -} - -/*! - * @brief Writes 0 to the field Time Seconds Register Read (TSRR) of the RTC_RAR register. - * - * Once cleared, this bit is only set by system reset. It is not affected by - * VBAT POR or software reset. - * - * @param rtcBaseAddr The RTC base address - */ -static inline void RTC_HAL_ClearSecsRreg(uint32_t rtcBaseAddr) -{ - BW_RTC_RAR_TSRR(rtcBaseAddr, 0U); -} - -#endif /* FSL_FEATURE_RTC_HAS_ACCESS_CONTROL */ - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - - -/*! @}*/ - -#endif /* __FSL_RTC_HAL_H__*/ - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_features.h deleted file mode 100644 index 4559eb7dc91..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_features.h +++ /dev/null @@ -1,168 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_SAI_FEATURES_H__) -#define __FSL_SAI_FEATURES_H__ - -#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ - defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ - defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ - defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || \ - defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ - #define FSL_FEATURE_SAI_FIFO_COUNT (8) - /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ - #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) - /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ - #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) - /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) - /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) - /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) - /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ - #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) - /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ - #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) - /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ - #define FSL_FEATURE_SAI_FIFO_COUNT (8) - /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ - #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) - /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ - #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16) - /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) - /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) - /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) - /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ - #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) - /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ - #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ - #define FSL_FEATURE_SAI_FIFO_COUNT (8) - /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ - #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) - /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ - #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) - /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) - /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) - /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) - /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ - #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) - /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ - #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ - #define FSL_FEATURE_SAI_FIFO_COUNT (4) - /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ - #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) - /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ - #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) - /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) - /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) - /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) - /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ - #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) - /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ - #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (1) -#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ - #define FSL_FEATURE_SAI_FIFO_COUNT (1) - /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ - #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) - /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ - #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) - /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) - /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) - /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ - #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) - /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ - #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) - /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ - #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_SAI_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c deleted file mode 100644 index e3ddd665001..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c +++ /dev/null @@ -1,835 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sai_hal.h" - -/****************************************************************************** -*Code -******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxInit - * Description : Initialize the sai Tx register, just set the register vaule to zero. - *This function just clear the register value of sai. - *END**************************************************************************/ -void SAI_HAL_TxInit(uint32_t saiBaseAddr) -{ - /* Software reset and FIFO reset */ - BW_I2S_TCSR_SR(saiBaseAddr, 1); - BW_I2S_TCSR_FR(saiBaseAddr, 1); - /* Clear all registers */ - HW_I2S_TCSR_WR(saiBaseAddr, 0); - HW_I2S_TCR1_WR(saiBaseAddr, 0); - HW_I2S_TCR2_WR(saiBaseAddr, 0); - HW_I2S_TCR3_WR(saiBaseAddr, 0); - HW_I2S_TCR4_WR(saiBaseAddr, 0); - HW_I2S_TCR5_WR(saiBaseAddr, 0); - HW_I2S_TMR_WR(saiBaseAddr,0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxInit - * Description : Initialize the sai Rx register, just set the register vaule to zero. - *This function just clear the register value of sai. - *END**************************************************************************/ -void SAI_HAL_RxInit(uint32_t saiBaseAddr) -{ - /* Software reset and FIFO reset */ - BW_I2S_RCSR_SR(saiBaseAddr, 1); - BW_I2S_RCSR_FR(saiBaseAddr, 1); - /* Clear all registers */ - HW_I2S_RCSR_WR(saiBaseAddr, 0); - HW_I2S_RCR1_WR(saiBaseAddr, 0); - HW_I2S_RCR2_WR(saiBaseAddr, 0); - HW_I2S_RCR3_WR(saiBaseAddr, 0); - HW_I2S_RCR4_WR(saiBaseAddr, 0); - HW_I2S_RCR5_WR(saiBaseAddr, 0); - HW_I2S_RMR_WR(saiBaseAddr,0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetProtocol - * Description : According to the protocol type to set the registers for tx. - *The protocol can be I2S left, I2S right, I2S and so on. - *END**************************************************************************/ -void SAI_HAL_TxSetProtocol(uint32_t saiBaseAddr,sai_protocol_t protocol) -{ - switch (protocol) - { - case kSaiBusI2SLeft: - BW_I2S_TCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */ - BW_I2S_TCR4_MF(saiBaseAddr,1);/* MSB transmitted fisrt */ - BW_I2S_TCR4_FSE(saiBaseAddr,0);/*Frame sync not early */ - BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left channel is high */ - BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusI2SRight: - BW_I2S_TCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */ - BW_I2S_TCR4_MF(saiBaseAddr,1);/* MSB transmitted firsrt */ - BW_I2S_TCR4_FSE(saiBaseAddr,0);/*Frame sync not early */ - BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */ - BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusI2SType: - BW_I2S_TCR2_BCP(saiBaseAddr,1);/*Bit clock polarity */ - BW_I2S_TCR4_MF(saiBaseAddr,1);/*MSB transmitted firsrt */ - BW_I2S_TCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */ - BW_I2S_TCR4_FSP(saiBaseAddr,1);/* Frame sync polarity, left channel is low */ - BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusPCMA: - BW_I2S_TCR2_BCP(saiBaseAddr,0); /* Bit clock active low */ - BW_I2S_TCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */ - BW_I2S_TCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */ - BW_I2S_TCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */ - BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */ - BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusPCMB: - BW_I2S_TCR2_BCP(saiBaseAddr,0); /* Bit clock active high */ - BW_I2S_TCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */ - BW_I2S_TCR4_FSE(saiBaseAddr,0);/* Frame sync not early */ - BW_I2S_TCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */ - BW_I2S_TCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */ - BW_I2S_TCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusAC97: - BW_I2S_TCR2_BCP(saiBaseAddr,1); /* Bit clock active high */ - BW_I2S_TCR4_MF(saiBaseAddr,1); /* MSB transmitted first */ - BW_I2S_TCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */ - BW_I2S_TCR4_FRSZ(saiBaseAddr,12); /* There are 13 words in a frame in AC'97 */ - BW_I2S_TCR4_SYWD(saiBaseAddr,15); /* Length of frame sync, 16 bit transmitted in first word */ - BW_I2S_TCR5_W0W(saiBaseAddr,15); /* The first word have 16 bits */ - BW_I2S_TCR5_WNW(saiBaseAddr,19); /* Other word is 20 bits */ - break; - - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetProtocol - * Description : According to the protocol type to set the registers for rx. - *The protocol can be I2S left, I2S right, I2S and so on. - *END**************************************************************************/ -void SAI_HAL_RxSetProtocol(uint32_t saiBaseAddr,sai_protocol_t protocol) -{ - switch (protocol) - { - case kSaiBusI2SLeft: - BW_I2S_RCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */ - BW_I2S_RCR4_MF(saiBaseAddr,1);/* MSB transmitted fisrt */ - BW_I2S_RCR4_FSE(saiBaseAddr,0);/*Frame sync one bit early */ - BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left channel is high */ - BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusI2SRight: - BW_I2S_RCR2_BCP(saiBaseAddr,1);/* Bit clock polarity */ - BW_I2S_RCR4_MF(saiBaseAddr,1);/* MSB transmitted fisrt */ - BW_I2S_RCR4_FSE(saiBaseAddr,0);/*Frame sync one bit early */ - BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */ - BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusI2SType: - BW_I2S_RCR2_BCP(saiBaseAddr,1);/*Bit clock polarity */ - BW_I2S_RCR4_MF(saiBaseAddr,1);/*MSB transmitted fisrt */ - BW_I2S_RCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */ - BW_I2S_RCR4_FSP(saiBaseAddr,1);/* Frame sync polarity, left channel is low */ - BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusPCMA: - BW_I2S_RCR2_BCP(saiBaseAddr,0); /* Bit clock active high */ - BW_I2S_RCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */ - BW_I2S_RCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */ - BW_I2S_RCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */ - BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */ - BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusPCMB: - BW_I2S_RCR2_BCP(saiBaseAddr,0); /* Bit clock active high */ - BW_I2S_RCR4_MF(saiBaseAddr, 1); /* MSB transmitted first */ - BW_I2S_RCR4_FSE(saiBaseAddr,0);/* Frame sync not early */ - BW_I2S_RCR4_SYWD(saiBaseAddr, 0); /* Only one bit clock in a frame sync */ - BW_I2S_RCR4_FSP(saiBaseAddr,0);/* Frame sync polarity, left chennel is high */ - BW_I2S_RCR4_FRSZ(saiBaseAddr,1);/* I2S uses 2 word in a frame */ - break; - - case kSaiBusAC97: - BW_I2S_RCR2_BCP(saiBaseAddr,1); /* Bit clock active high */ - BW_I2S_RCR4_MF(saiBaseAddr,1); /* MSB transmitted first */ - BW_I2S_RCR4_FSE(saiBaseAddr,1);/* Frame sync one bit early */ - BW_I2S_RCR4_FRSZ(saiBaseAddr,12); /* There are 13 words in a frame in AC'97 */ - BW_I2S_RCR4_SYWD(saiBaseAddr,15); /* Length of frame sync, 16 bit transmitted in first word */ - BW_I2S_RCR5_W0W(saiBaseAddr,15); /* The first word have 16 bits */ - BW_I2S_RCR5_WNW(saiBaseAddr,19); /* Other word is 20 bits */ - break; - - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_SetMclkDiv - * Description : Set the divider from the clock source to get the master clock. - *The function would compute the divider number and set the number to the registers. - *END**************************************************************************/ -void SAI_HAL_SetMclkDiv(uint32_t saiBaseAddr, uint32_t mclk, uint32_t src_clk) -{ - uint32_t freq = src_clk; - uint16_t fract, divide; - uint32_t remaind = 0; - uint32_t current_remainder = 0xffffffff; - uint16_t current_fract = 0; - uint16_t current_divide = 0; - uint32_t mul_freq = 0; - uint32_t max_fract = SAI_FRACT_MAX; - /*In order to prevent overflow */ - freq /= 10; - mclk/= 10; - max_fract = mclk * SAI_DIV_MAX/freq; - if(max_fract > SAI_FRACT_MAX) - { - max_fract = SAI_FRACT_MAX; - } - /* Looking for the closet frequency */ - for (fract = 1; fract < max_fract; fract ++) - { - mul_freq = freq * fract; - remaind = mul_freq % mclk; - divide = mul_freq/mclk; - /* Find the exactly frequency */ - if (remaind == 0) - { - current_fract = fract; - current_divide = mul_freq/mclk; - break; - } - /* closer to next one */ - if (remaind > mclk/2) - { - remaind = mclk - remaind; - divide += 1; - } - /* Update the closest div and fract */ - if (remaind < current_remainder) - { - current_fract = fract; - current_divide = divide; - current_remainder = remaind; - } - } - BW_I2S_MDR_DIVIDE(saiBaseAddr, current_divide -1); - /* Waiting for the divider updated */ - while(BR_I2S_MCR_DUF(saiBaseAddr)) - {} - BW_I2S_MDR_FRACT(saiBaseAddr, current_fract - 1); - /* Waiting for the divider updated */ - while(BR_I2S_MCR_DUF(saiBaseAddr)) - {} -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetMasterSlave - * Description : Set the tx master or slave mode. - *The slave or master mode only would affect the clock direction relevant registers. - *END**************************************************************************/ -void SAI_HAL_TxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode) -{ - if (master_slave_mode == kSaiMaster) - { - BW_I2S_TCR2_BCD(saiBaseAddr,1);/* Bit clock generated internal */ - BW_I2S_TCR4_FSD(saiBaseAddr,1);/* Frame sync generated internal */ - BW_I2S_MCR_MOE(saiBaseAddr,1);/* Master clock generated internal */ - } - else - { - BW_I2S_TCR2_BCD(saiBaseAddr,0);/* Bit clock generated external */ - BW_I2S_TCR4_FSD(saiBaseAddr,0);/* Frame sync generated external */ - BW_I2S_MCR_MOE(saiBaseAddr,0);/* Master clock generated external */ - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetMasterSlave - * Description : Set the rx master or slave mode. - *The slave or master mode only would affect the clock direction relevant registers. - *END**************************************************************************/ -void SAI_HAL_RxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode) -{ - if (master_slave_mode == kSaiMaster) - { - BW_I2S_RCR2_BCD(saiBaseAddr,1);/* Bit clock generated internal */ - BW_I2S_RCR4_FSD(saiBaseAddr,1);/* Frame sync generated internal */ - BW_I2S_MCR_MOE(saiBaseAddr,1);/* Master clock generated internal */ - } - else - { - BW_I2S_RCR2_BCD(saiBaseAddr,0);/* Bit clock generated external */ - BW_I2S_RCR4_FSD(saiBaseAddr,0);/* Frame sync generated external */ - BW_I2S_MCR_MOE(saiBaseAddr,0);/* Master clock generated external */ - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetSyncMode - * Description : Set the tx sync mode. - *Theer are four kinds of sync mode, async, sync, sync with other sai tx, sync with other sai rx. - *END**************************************************************************/ -void SAI_HAL_TxSetSyncMode(uint32_t saiBaseAddr, sai_sync_mode_t sync_mode) -{ - switch (sync_mode) - { - case kSaiModeAsync: - BW_I2S_TCR2_SYNC(saiBaseAddr,0); - break; - case kSaiModeSync: - BW_I2S_TCR2_SYNC(saiBaseAddr,1); - BW_I2S_RCR2_SYNC(saiBaseAddr,0);/* Receiver must be async mode */ - break; - case kSaiModeSyncWithOtherTx: - BW_I2S_TCR2_SYNC(saiBaseAddr,2); - break; - case kSaiModeSyncWithOtherRx: - BW_I2S_TCR2_SYNC(saiBaseAddr,3); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetSyncMode - * Description : Set the rx sync mode. - *Theer are four kinds of sync mode, async, sync, sync with other sai tx, sync with other sai rx. - *END**************************************************************************/ -void SAI_HAL_RxSetSyncMode(uint32_t saiBaseAddr,sai_sync_mode_t sync_mode) -{ - switch (sync_mode) - { - case kSaiModeAsync: - BW_I2S_RCR2_SYNC(saiBaseAddr,0); - break; - case kSaiModeSync: - BW_I2S_RCR2_SYNC(saiBaseAddr,1); - BW_I2S_TCR2_SYNC(saiBaseAddr,0);/* Receiver must be async mode */ - break; - case kSaiModeSyncWithOtherTx: - BW_I2S_RCR2_SYNC(saiBaseAddr,3); - break; - case kSaiModeSyncWithOtherRx: - BW_I2S_RCR2_SYNC(saiBaseAddr,2); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetIntCmd - * Description : Enable the interrupt request source for tx. - *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request. - *END**************************************************************************/ -void SAI_HAL_TxSetIntCmd(uint32_t saiBaseAddr, sai_interrupt_request_t source, bool enable) -{ - switch (source) - { - case kSaiIntrequestWordStart: - BW_I2S_TCSR_WSIE(saiBaseAddr, enable); - break; - case kSaiIntrequestSyncError: - BW_I2S_TCSR_SEIE(saiBaseAddr, enable); - break; - case kSaiIntrequestFIFOWarning: - BW_I2S_TCSR_FWIE(saiBaseAddr, enable); - break; - case kSaiIntrequestFIFOError: - BW_I2S_TCSR_FEIE(saiBaseAddr, enable); - break; - case kSaiIntrequestFIFORequest: - BW_I2S_TCSR_FRIE(saiBaseAddr, enable); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetIntCmd - * Description : Enable the interrupt request source for rx. - *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request. - *END**************************************************************************/ -void SAI_HAL_RxSetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source,bool enable) -{ - switch(source) - { - case kSaiIntrequestWordStart: - BW_I2S_RCSR_WSIE(saiBaseAddr, enable); - break; - case kSaiIntrequestSyncError: - BW_I2S_RCSR_SEIE(saiBaseAddr, enable); - break; - case kSaiIntrequestFIFOWarning: - BW_I2S_RCSR_FWIE(saiBaseAddr, enable); - break; - case kSaiIntrequestFIFOError: - BW_I2S_RCSR_FEIE(saiBaseAddr, enable); - break; - case kSaiIntrequestFIFORequest: - BW_I2S_RCSR_FRIE(saiBaseAddr, enable); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxGetIntCmd - * Description : Gets state of tx interrupt source. - *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request. - *END**************************************************************************/ -bool SAI_HAL_TxGetIntCmd(uint32_t saiBaseAddr, sai_interrupt_request_t source) -{ - bool ret = false; - switch (source) - { - case kSaiIntrequestWordStart: - ret = BR_I2S_TCSR_WSIE(saiBaseAddr); - break; - case kSaiIntrequestSyncError: - ret = BR_I2S_TCSR_SEIE(saiBaseAddr); - break; - case kSaiIntrequestFIFOWarning: - ret = BR_I2S_TCSR_FWIE(saiBaseAddr); - break; - case kSaiIntrequestFIFOError: - ret = BR_I2S_TCSR_FEIE(saiBaseAddr); - break; - case kSaiIntrequestFIFORequest: - ret = BR_I2S_TCSR_FRIE(saiBaseAddr); - break; - default: - break; - } - return ret; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxGetIntCmd - * Description : Gets state of rx interrupt source. - *The source can be word start, sync error, FIFO empty, FIFO error and FIFO request. - *END**************************************************************************/ -bool SAI_HAL_RxGetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source) -{ - bool ret = false; - switch(source) - { - case kSaiIntrequestWordStart: - ret = BR_I2S_RCSR_WSIE(saiBaseAddr); - break; - case kSaiIntrequestSyncError: - ret = BR_I2S_RCSR_SEIE(saiBaseAddr); - break; - case kSaiIntrequestFIFOWarning: - ret = BR_I2S_RCSR_FWIE(saiBaseAddr); - break; - case kSaiIntrequestFIFOError: - ret = BR_I2S_RCSR_FEIE(saiBaseAddr); - break; - case kSaiIntrequestFIFORequest: - ret= BR_I2S_RCSR_FRIE(saiBaseAddr); - break; - default: - break; - } - return ret; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetDmaCmd - * Description : Enable the dma request source for tx. - *The source can be FIFO empty or FIFO request. - *END**************************************************************************/ -void SAI_HAL_TxSetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source, bool enable) -{ - switch (source) - { - case kSaiDmaReqFIFOWarning: - BW_I2S_TCSR_FWDE(saiBaseAddr, enable); - break; - case kSaiDmaReqFIFORequest: - BW_I2S_TCSR_FRDE(saiBaseAddr, enable); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetDmaCmd - * Description : Enable the dma request source for rx. - *The source can be FIFO empty or FIFO request. - *END**************************************************************************/ -void SAI_HAL_RxSetDmaCmd(uint32_t saiBaseAddr,sai_dma_request_t source,bool enable) -{ - switch (source) - { - case kSaiDmaReqFIFOWarning: - BW_I2S_RCSR_FWDE(saiBaseAddr,enable); - break; - case kSaiDmaReqFIFORequest: - BW_I2S_RCSR_FRDE(saiBaseAddr,enable); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxGetDmaCmd - * Description : Gets state of tx dma request source. - *The source can be FIFO empty or FIFO request. - *END**************************************************************************/ -bool SAI_HAL_TxGetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source) -{ - bool ret = false; - switch (source) - { - case kSaiDmaReqFIFOWarning: - ret = BR_I2S_TCSR_FWDE(saiBaseAddr); - break; - case kSaiDmaReqFIFORequest: - ret = BR_I2S_TCSR_FRDE(saiBaseAddr); - break; - default: - break; - } - return ret; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxGetDmaCmd - * Description : Gets state of rx dma request source. - *The source can be FIFO empty or FIFO request. - *END**************************************************************************/ -bool SAI_HAL_RxGetDmaCmd(uint32_t saiBaseAddr,sai_dma_request_t source) -{ - bool ret = false; - switch (source) - { - case kSaiDmaReqFIFOWarning: - ret = BR_I2S_RCSR_FWDE(saiBaseAddr); - break; - case kSaiDmaReqFIFORequest: - ret = BR_I2S_RCSR_FRDE(saiBaseAddr); - break; - default: - break; - } - return ret; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxClearStateFlag - * Description : Clear the state flag of tx registers. - *The state flag incudes word start flag, sync error flag and fifo error flag. - *END**************************************************************************/ -void SAI_HAL_TxClearStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag) -{ - switch (flag) - { - case kSaiStateFlagWordStart: - BW_I2S_TCSR_WSF(saiBaseAddr,1);/* Write logic 1 to clear this bit */ - break; - case kSaiStateFlagSyncError: - BW_I2S_TCSR_SEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */ - break; - case kSaiStateFlagFIFOError: - BW_I2S_TCSR_FEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */ - break; - case kSaiStateFlagSoftReset: - BW_I2S_TCSR_SR(saiBaseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxClearStateFlag - * Description : Clear the state flag of rx registers. - *The state flag incudes word start flag, sync error flag and fifo error flag. - *END**************************************************************************/ -void SAI_HAL_RxClearStateFlag(uint32_t saiBaseAddr,sai_state_flag_t flag) -{ - switch (flag) - { - case kSaiStateFlagWordStart: - BW_I2S_RCSR_WSF(saiBaseAddr,1);/* Write logic 1 to clear this bit */ - break; - case kSaiStateFlagSyncError: - BW_I2S_RCSR_SEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */ - break; - case kSaiStateFlagFIFOError: - BW_I2S_RCSR_FEF(saiBaseAddr,1);/* Write logic 1 to clear this bit */ - break; - case kSaiStateFlagSoftReset: - BW_I2S_RCSR_SR(saiBaseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetReset - * Description : Reset tx according to reset mode. - *The reset mode can be software reset and FIFO reset. - *END**************************************************************************/ -void SAI_HAL_TxSetReset(uint32_t saiBaseAddr, sai_reset_type_t type) -{ - switch (type) - { - case kSaiResetTypeSoftware: - BW_I2S_TCSR_SR(saiBaseAddr,1); - break; - case kSaiResetTypeFIFO: - BW_I2S_TCSR_FR(saiBaseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetReset - * Description : Reset rx according to reset mode. - *The reset mode can be software reset and FIFO reset. - *END**************************************************************************/ -void SAI_HAL_RxSetReset(uint32_t saiBaseAddr,sai_reset_type_t type) -{ - switch (type) - { - case kSaiResetTypeSoftware: - BW_I2S_RCSR_SR(saiBaseAddr,1); - break; - case kSaiResetTypeFIFO: - BW_I2S_RCSR_FR(saiBaseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxSetRunModeCmd - * Description : Set the work mode for tx. - *The work mode have stop mode, debug mode and normal mode. - *END**************************************************************************/ -void SAI_HAL_TxSetRunModeCmd(uint32_t saiBaseAddr, sai_run_mode_t run_mode, bool enable) -{ - switch (run_mode) - { - case kSaiRunModeStop: - BW_I2S_TCSR_STOPE(saiBaseAddr, enable);/* Stop mode */ - break; - case kSaiRunModeDebug: - BW_I2S_TCSR_DBGE(saiBaseAddr, enable);/* Debug mode */ - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxSetRunModeCmd - * Description : Set the work mode for rx. - *The work mode have stop mode, debug mode and normal mode. - *END**************************************************************************/ -void SAI_HAL_RxSetRunModeCmd(uint32_t saiBaseAddr,sai_run_mode_t run_mode,bool enable) -{ - switch (run_mode) - { - case kSaiRunModeStop: - BW_I2S_RCSR_STOPE(saiBaseAddr, enable);/* Stop mode */ - break; - case kSaiRunModeDebug: - BW_I2S_RCSR_DBGE(saiBaseAddr, enable);/* Debug mode */ - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_TxGetFlagState - * Description : Get the state flag value of tx. - *The state flag includes fifo error, fifo warning, fifo request, software reset, - * sync error and word start. - *END**************************************************************************/ -bool SAI_HAL_TxGetStateFlag(uint32_t saiBaseAddr,sai_state_flag_t flag) -{ - bool ret = false; - switch(flag) - { - case kSaiStateFlagFIFOError: - ret = BR_I2S_TCSR_FEF(saiBaseAddr); - break; - case kSaiStateFlagFIFORequest: - ret = BR_I2S_TCSR_FRF(saiBaseAddr); - break; - case kSaiStateFlagFIFOWarning: - ret = BR_I2S_TCSR_FWF(saiBaseAddr); - break; - case kSaiStateFlagSoftReset: - ret = BR_I2S_TCSR_SR(saiBaseAddr); - break; - case kSaiStateFlagSyncError: - ret = BR_I2S_TCSR_SEF(saiBaseAddr); - break; - case kSaiStateFlagWordStart: - ret = BR_I2S_TCSR_WSF(saiBaseAddr); - break; - default: - break; - } - return ret; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_RxGetFlagState - * Description : Get the state flag value of rx. - *The state flag includes fifo error, fifo warning, fifo request, software reset, - * sync error and word start. - *END**************************************************************************/ -bool SAI_HAL_RxGetStateFlag(uint32_t saiBaseAddr,sai_state_flag_t flag) -{ - bool ret = false; - switch(flag) - { - case kSaiStateFlagFIFOError: - ret = BR_I2S_RCSR_FEF(saiBaseAddr); - break; - case kSaiStateFlagFIFORequest: - ret = BR_I2S_RCSR_FRF(saiBaseAddr); - break; - case kSaiStateFlagFIFOWarning: - ret = BR_I2S_RCSR_FWF(saiBaseAddr); - break; - case kSaiStateFlagSoftReset: - ret = BR_I2S_RCSR_SR(saiBaseAddr); - break; - case kSaiStateFlagSyncError: - ret = BR_I2S_RCSR_SEF(saiBaseAddr); - break; - case kSaiStateFlagWordStart: - ret = BR_I2S_RCSR_WSF(saiBaseAddr); - break; - default: - break; - } - return ret; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_ReceiveDataBlocking - * Description : Receive data in blocking way. - *The sending would wait until there is vaild data in FIFO for reading. - *END**************************************************************************/ -uint32_t SAI_HAL_ReceiveDataBlocking(uint32_t saiBaseAddr,uint32_t rx_channel) -{ - assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT); - /* Wait while fifo is empty */ - uint8_t w_ptr = BR_I2S_RFRn_WFP(saiBaseAddr,rx_channel); - uint8_t r_ptr = BR_I2S_RFRn_RFP(saiBaseAddr,rx_channel); - while(w_ptr == r_ptr) - { - w_ptr = BR_I2S_RFRn_WFP(saiBaseAddr,rx_channel); - r_ptr = BR_I2S_RFRn_RFP(saiBaseAddr,rx_channel); - } - return BR_I2S_RDRn_RDR(saiBaseAddr,rx_channel); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SAI_HAL_SendDataBlocking - * Description : Send data in blocking way. - *The sending would wait until there is space for writing. - *END**************************************************************************/ -void SAI_HAL_SendDataBlocking(uint32_t saiBaseAddr,uint32_t tx_channel,uint32_t data) -{ - assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT); - /* Wait while fifo is full */ - uint8_t w_ptr = BR_I2S_TFRn_WFP(saiBaseAddr,tx_channel); - uint8_t r_ptr = BR_I2S_TFRn_RFP(saiBaseAddr,tx_channel); - while((w_ptr ^ r_ptr) == 0x8) - { - w_ptr = BR_I2S_TFRn_WFP(saiBaseAddr,tx_channel); - r_ptr = BR_I2S_TFRn_RFP(saiBaseAddr,tx_channel); - } - BW_I2S_TDRn_TDR(saiBaseAddr, tx_channel, data); -} - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h deleted file mode 100644 index c163c322920..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h +++ /dev/null @@ -1,1423 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_SAI_HAL_H__ -#define __FSL_SAI_HAL_H__ - - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sai_features.h" - - -/*! - * @addtogroup sai_hal - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Define the bit limits of in a word*/ -#define SAI_BIT_MIN 8 -#define SAI_BIT_MAX 32 - -/* Define the max div and fract value for master clock divider. */ -#define SAI_FRACT_MAX 256 -#define SAI_DIV_MAX 4096 - -/*! @brief Define the bus type of sai */ -typedef enum _sai_protocol -{ - kSaiBusI2SLeft = 0x0, - kSaiBusI2SRight = 0x1, - kSaiBusI2SType = 0x2, - kSaiBusPCMA = 0x3, - kSaiBusPCMB = 0x4, - kSaiBusAC97 = 0x5 - } sai_protocol_t; - -/*! @brief Master or slave mode */ -typedef enum _sai_master_slave -{ - kSaiMaster = 0x0,/*!< Master mode */ - kSaiSlave = 0x1/*!< Slave mode */ -} sai_master_slave_t; - -/*! @brief Polarity of SAI clock. */ -typedef enum _sai_clk_polarity -{ - kSaiClkPolarityHigh = 0x0, /*!< Clock active high */ - kSaiClkPolarityLow = 0x1 /*!< Clock active low */ -} sai_clk_polarity_t; - -/*! @brief Clock generate direction. */ -typedef enum _sai_clk_direction -{ - kSaiClkInternal = 0x0, /*!< Clock generated internal. */ - kSaiClkExternal = 0x1 /*!< Clock generated external. */ -} sai_clk_direction_t; - -/*! @brief Data transfer polarity, means MSB first of LSB first.*/ -typedef enum _sai_data_order -{ - kSaiLSBFirst = 0x0, /*!< Least significant bit transferred first. */ - kSaiMSBFirst = 0x1 /*!< Most significant bit transferred first. */ -} sai_data_order_t; - -/*! @brief Synchronous or asynchronous mode */ -typedef enum _sai_sync_mode -{ - kSaiModeAsync = 0x0,/*!< Asynchronous mode */ - kSaiModeSync = 0x1,/*!< Synchronous mode (with receiver or transmit) */ - kSaiModeSyncWithOtherTx = 0x2,/*!< Synchronous with another SAI transmit */ - kSaiModeSyncWithOtherRx = 0x3/*!< Synchronous with another SAI receiver */ -} sai_sync_mode_t; - -/*! @brief Mater clock source */ -typedef enum _sai_mclk_source -{ - kSaiMclkSourceSysclk = 0x0,/*!< Master clock from the system clock */ - kSaiMclkSourceSelect1 = 0x1,/*!< Master clock from source 1 */ - kSaiMclkSourceSelect2 = 0x2,/*!< Master clock from source 2 */ - kSaiMclkSourceSelect3 = 0x3/*!< Master clock from source 3 */ -} sai_mclk_source_t; - -/*! @brief Bit clock source */ -typedef enum _sai_bclk_source -{ - kSaiBclkSourceBusclk = 0x0,/*!< Bit clock using bus clock */ - kSaiBclkSourceMclkDiv = 0x1,/*!< Bit clock using master clock divider */ - kSaiBclkSourceOtherSai0 = 0x2,/*!< Bit clock from other SAI device */ - kSaiBclkSourceOtherSai1 = 0x3/*!< Bit clock from other SAI device */ -} sai_bclk_source_t; - -/*! @brief The SAI state flag. */ -typedef enum _sai_interrupt_request -{ - kSaiIntrequestWordStart = 0x0,/*!< Word start flag, means the first word in a frame detected */ - kSaiIntrequestSyncError = 0x1,/*!< Sync error flag, means the sync error is detected */ - kSaiIntrequestFIFOWarning = 0x2,/*!< FIFO warning flag, means the FIFO is empty */ - kSaiIntrequestFIFOError = 0x3,/*!< FIFO error flag */ - kSaiIntrequestFIFORequest = 0x4/*!< FIFO request, means reached watermark */ -} sai_interrupt_request_t; - - -/*! @brief The DMA request sources */ -typedef enum _sai_dma_request -{ - kSaiDmaReqFIFOWarning = 0x0,/*!< FIFO warning caused by the DMA request */ - kSaiDmaReqFIFORequest = 0x1/*!< FIFO request caused by the DMA request */ -} sai_dma_request_t; - -/*! @brief The SAI state flag */ -typedef enum _sai_state_flag -{ - kSaiStateFlagWordStart = 0x0,/*!< Word start flag, means the first word in a frame detected. */ - kSaiStateFlagSyncError = 0x1,/*!< Sync error flag, means the sync error is detected */ - kSaiStateFlagFIFOError = 0x2,/*!< FIFO error flag */ - kSaiStateFlagFIFORequest = 0x3, - kSaiStateFlagFIFOWarning = 0x4, - kSaiStateFlagSoftReset = 0x5 /*!< Software reset flag */ -} sai_state_flag_t; - -/*! @brief The reset type */ -typedef enum _sai_reset_type -{ - kSaiResetTypeSoftware = 0x0,/*!< Software reset, reset the logic state */ - kSaiResetTypeFIFO = 0x1/*!< FIFO reset, reset the FIFO read and write pointer */ -} sai_reset_type_t; - -/* - * @brief The SAI running mode - * The mode includes normal mode, debug mode, and stop mode. - */ -typedef enum _sai_running_mode -{ - kSaiRunModeDebug = 0x0,/*!< In debug mode */ - kSaiRunModeStop = 0x1/*!< In stop mode */ -} sai_run_mode_t; - -#if FSL_FEATURE_SAI_HAS_FIFO_PACKING - -/* - * @brief The SAI packing mode - * The mode includes 8 bit and 16 bit packing. - */ -typedef enum _sai_fifo_packing -{ - kSaiFifoPackingDisabled = 0x0, /*!< Packing disabled. */ - kSaiFifoPacking8bit = 0x2,/*!< 8 bit packing enabled. */ - kSaiFifoPacking16bit = 0x3 /*!< 16bit packing enabled. */ -} sai_fifo_packing_t; - -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! -* @name Module control -* @{ -*/ - -/*! - * @brief Initializes the SAI Tx. - * - * The initialization resets the SAI module by setting the SR bit of TCSR register. - * Note that the function writes 0 to every control registers. - * @param saiBaseAddr Register base address of SAI module. - */ -void SAI_HAL_TxInit(uint32_t saiBaseAddr); - -/*! - * @brief Initializes the SAI Rx. - * - * The initialization resets the SAI module by setting the SR bit of RCSR register. - * Note that the function writes 0 to every control registers. - * @param saiBaseAddr Register base address of SAI module. - */ -void SAI_HAL_RxInit(uint32_t saiBaseAddr); - -/*! - * @brief Sets Tx protocol relevant settings. - * - * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol - * has a different configuration on bit clock and frame sync. - * @param saiBaseAddr Register base address of SAI module. - * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc. - */ -void SAI_HAL_TxSetProtocol(uint32_t saiBaseAddr, sai_protocol_t protocol); - -/*! - * @brief Sets Rx protocol relevant settings. - * - * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol - * has a different configuration on bit clock and frame sync. - * @param saiBaseAddr Register base address of SAI module. - * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc. - */ -void SAI_HAL_RxSetProtocol(uint32_t saiBaseAddr, sai_protocol_t protocol); - -/*! - * @brief Sets master or slave mode. - * - * The function determines master or slave mode. Master mode provides its - * own clock and slave mode uses an external clock. - * @param saiBaseAddr Register base address of SAI module. - * @param master_slave_mode Mater or slave mode. - */ -void SAI_HAL_TxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode); - -/*! - * @brief Sets master or slave mode. - * - * The function determines master or slave mode. Master mode provides its - * own clock and slave mode uses external clock. - * @param saiBaseAddr Register base address of SAI module. - * @param master_slave_mode Mater or slave mode. - */ -void SAI_HAL_RxSetMasterSlave(uint32_t saiBaseAddr, sai_master_slave_t master_slave_mode); - -/*! @}*/ - -/*! -* @name Master clock configuration -* @{ -*/ - -/*! - * @brief Sets the master clock source. - * - * The source of the clock is different from socs. - * This function sets the clock source for SAI master clock source. - * Master clock is used to produce the bit clock for the data transfer. - * @param saiBaseAddr Register base address of SAI module. - * @param source Mater clock source - */ -static inline void SAI_HAL_SetMclkSrc(uint32_t saiBaseAddr, sai_mclk_source_t source) -{ - BW_I2S_MCR_MICS(saiBaseAddr,source); -} - -/*! - * @brief Gets the master clock source. - * - * The source of the clock is different from socs. - * This function gets the clock source for SAI master clock source. - * Master clock is used to produce the bit clock for the data transfer. - * @param saiBaseAddr Register base address of SAI module. - * @return Mater clock source - */ -static inline uint32_t SAI_HAL_GetMclkSrc(uint32_t saiBaseAddr) -{ - return BR_I2S_MCR_MICS(saiBaseAddr); -} - -/*! - * @brief Sets the direction of the SAI master clock. - * - * This function would decides the direction of bit clock generated. - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means enable, false means disable. - */ -static inline void SAI_HAL_SetMclkDividerCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_MCR_MOE(saiBaseAddr,enable); -} - -/*! - * @brief Sets the divider of the master clock. - * - * Using the divider to get the master clock frequency wanted from the source. - * mclk = clk_source * fract/divide. The input is the master clock frequency needed and the source clock frequency. - * The master clock is decided by the sample rate and the multi-clock number. - * Notice that mclk should less than src_clk, or it would do hang as the HW refuses to write in this situation. - * @param saiBaseAddr Register base address of SAI module. - * @param mclk Master clock frequency needed. - * @param src_clk The source clock frequency. - */ -void SAI_HAL_SetMclkDiv(uint32_t saiBaseAddr, uint32_t mclk, uint32_t src_clk); - -/*! - * @brief Flag to see if the master clock divider is re-divided. - * @param saiBaseAddr Register base address of SAI module. - * @return True if the divider updated otherwise false. - */ -static inline bool SAI_HAL_GetMclkDivUpdatingCmd(uint32_t saiBaseAddr) -{ - return BR_I2S_MCR_DUF(saiBaseAddr); -} - -/*! @}*/ - -/*! -* @name Bit clock configuration -* @{ -*/ - -/*! - * @brief Sets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices. - * - * The function sets the source of the bit clock. The bit clock can be produced by the master - * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit - * clock either from Tx or Rx. - * @param saiBaseAddr Register base address of SAI module. - * @param source Bit clock source. - */ -static inline void SAI_HAL_TxSetBclkSrc(uint32_t saiBaseAddr, sai_bclk_source_t source) -{ - BW_I2S_TCR2_MSEL(saiBaseAddr,source); -} - -/*! - * @brief Sets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices. - * - * The function sets the source of the bit clock. The bit clock can be produced by the master - * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit - * clock either from Tx or Rx. - * @param saiBaseAddr Register base address of SAI module. - * @param source Bit clock source. - */ -static inline void SAI_HAL_RxSetBclkSrc(uint32_t saiBaseAddr, sai_bclk_source_t source) -{ - BW_I2S_RCR2_MSEL(saiBaseAddr,source); -} - -/*! - * @brief Gets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices. - * - * The function gets the source of the bit clock. The bit clock can be produced by the master - * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit - * clock either from Tx or Rx. - * @param saiBaseAddr Register base address of SAI module. - * @return Bit clock source. - */ -static inline uint32_t SAI_HAL_TxGetBclkSrc(uint32_t saiBaseAddr) -{ - return BR_I2S_TCR2_MSEL(saiBaseAddr); -} - -/*! - * @brief Gets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices. - * - * The function gets the source of the bit clock. The bit clock can be produced by the master - * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit - * clock either from Tx or Rx. - * @param saiBaseAddr Register base address of SAI module. - * @return Bit clock source. - */ -static inline uint32_t SAI_HAL_RxGetBclkSrc(uint32_t saiBaseAddr) -{ - return BR_I2S_RCR2_MSEL(saiBaseAddr); -} - -/*! - * @brief Sets the Tx bit clock divider value. - * - * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means - * how much time is needed to transfer one bit. - * Notice: The function is called while the bit clock source is the master clock. - * @param saiBaseAddr Register base address of SAI module. - * @param divider The divide number of bit clock. - */ -static inline void SAI_HAL_TxSetBclkDiv(uint32_t saiBaseAddr, uint32_t divider) -{ - BW_I2S_TCR2_DIV(saiBaseAddr,divider/2 -1); -} - -/*! - * @brief Sets the Rx bit clock divider value. - * - * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means - * how much time is needed to transfer one bit. - * Notice: The function is called while the bit clock source is the master clock. - * @param saiBaseAddr Register base address of SAI module. - * @param divider The divide number of bit clock. - */ -static inline void SAI_HAL_RxSetBclkDiv(uint32_t saiBaseAddr, uint32_t divider) -{ - BW_I2S_RCR2_DIV(saiBaseAddr,divider/2 -1); -} - -/*! - * @brief Enables or disables the Tx bit clock. - * - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means enable, false means disable. - */ -static inline void SAI_HAL_TxSetBclkCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_TCSR_BCE(saiBaseAddr,enable); -} - -/*! - * @brief Enables or disables the Rx bit clock. - * - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means enable, false means disable. - */ -static inline void SAI_HAL_RxSetBclkCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_RCSR_BCE(saiBaseAddr, enable); -} - -/*! - * @brief Enables or disables the Tx bit clock input bit. - * - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means enable, false means disable. - */ -static inline void SAI_HAL_TxSetBclkInputCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_TCR2_BCI(saiBaseAddr,enable); -} - -/*! - * @brief Enables or disables the Rx bit clock input bit. - * - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means enable, false means disable. - */ -static inline void SAI_HAL_RxSetBclkInputCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_RCR2_BCI(saiBaseAddr,enable); -} - -/*! - * @brief Sets the Tx bit clock swap. - * - * This field swaps the bit clock used by the transmitter. When the transmitter is configured in - * asynchronous mode and this bit is set, the transmitter is clocked by the receiver bit clock. - * This allows the transmitter and receiver to share the same bit clock, but the transmitter - * continues to use the transmit frame sync (SAI_TX_SYNC). - * When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver - * BCS field must be set to the same value. When both are set, the transmitter and receiver are both - * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC). - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means swap bit closk, false means no swap. - */ -static inline void SAI_HAL_TxSetSwapBclkCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_TCR2_BCS(saiBaseAddr,enable); -} - -/*! - * @brief Sets the Rx bit clock swap. - * - * This field swaps the bit clock used by the receiver. When the receiver is configured in - * asynchronous mode and this bit is set, the receiver is clocked by the transmitter bit clock - * (SAI_TX_BCLK). This allows the transmitter and receiver to share the same bit clock, but the - * receiver continues to use the receiver frame sync (SAI_RX_SYNC). - * When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS - * field must be set to the same value. When both are set, the transmitter and receiver are both - * clocked by the receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC). - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means swap bit closk, false means no swap. - */ -static inline void SAI_HAL_RxSetSwapBclkCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_RCR2_BCS(saiBaseAddr, enable); -} - -/*! - * @brief Sets the direction of the Tx SAI bit clock. - * - * This function sets the direction of the bit clock generated. - * @param saiBaseAddr Register base address of SAI module. - * @param direction Bit clock generated internal or external. - */ -static inline void SAI_HAL_TxSetBclkDir(uint32_t saiBaseAddr, sai_clk_direction_t direction) -{ - BW_I2S_TCR2_BCD(saiBaseAddr,direction); -} - -/*! - * @brief Sets the direction of the Rx SAI bit clock. - * - * This function sets the direction of the bit clock generated. - * @param saiBaseAddr Register base address of SAI module. - * @param direction Bit clock generated internal or external. - */ -static inline void SAI_HAL_RxSetBclkDir(uint32_t saiBaseAddr, sai_clk_direction_t direction) -{ - BW_I2S_RCR2_BCD(saiBaseAddr,direction); -} - -/*! - * @brief Sets the polarity of the Tx SAI bit clock. - * - * @param saiBaseAddr Register base address of SAI module. - * @param pol Polarity of the SAI bit clock, which can be configured to active high or low. - */ -static inline void SAI_HAL_TxSetBclkPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol) -{ - BW_I2S_TCR2_BCP(saiBaseAddr, pol); -} - -/*! - * @brief Sets the polarity of the Rx SAI bit clock. - * - * @param saiBaseAddr Register base address of SAI module. - * @param pol Polarity of SAI bit clock, which can be configured to active high or low. - */ -static inline void SAI_HAL_RxSetBclkPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol) -{ - BW_I2S_RCR2_BCP(saiBaseAddr, pol); -} -/*! @} */ - -/*! -* @name Frame sync configuration -* @{ -*/ - -/*! - * @brief Sets the Tx frame size. - * - * The frame size means how many words are in a frame. For example 2-channel - * audio data, the frame size is 2, which means 2 words in a frame. - * @param saiBaseAddr Register base address of SAI module. - * @param size Words number in a frame. - */ -static inline void SAI_HAL_TxSetFrameSize(uint32_t saiBaseAddr, uint32_t size) -{ - BW_I2S_TCR4_FRSZ(saiBaseAddr,size -1); -} - -/*! - * @brief Sets the Rx frame size. - * - * The frame size means how many words are in a frame. For example 2-channel - * audio data, the frame size is 2, which means 2 words in a frame. - * @param saiBaseAddr Register base address of SAI module. - * @param size Words number in a frame. - */ -static inline void SAI_HAL_RxSetFrameSize(uint32_t saiBaseAddr, uint32_t size) -{ - BW_I2S_RCR4_FRSZ(saiBaseAddr,size - 1); -} - -/*! - * @brief Gets the Tx frame size. - * - * @param saiBaseAddr Register base address of SAI module. - */ -static inline uint32_t SAI_HAL_TxGetFrameSize(uint32_t saiBaseAddr) -{ - return BR_I2S_TCR4_FRSZ(saiBaseAddr); -} - -/*! - * @brief Gets the Tx frame size. - * - * @param saiBaseAddr Register base address of SAI module. - */ -static inline uint32_t SAI_HAL_RxGetFrameSize(uint32_t saiBaseAddr) -{ - return BR_I2S_RCR4_FRSZ(saiBaseAddr); -} - -/*! - * @brief Sets the Tx sync width. - * - * A sync is the number of bit clocks of a frame. The sync width cannot be longer than the - * length of the first word of the frame. - * @param saiBaseAddr Register base address of SAI module. - * @param width How many bit clock in a sync. - */ -static inline void SAI_HAL_TxSetFrameSyncWidth(uint32_t saiBaseAddr, uint32_t width) -{ - BW_I2S_TCR4_SYWD(saiBaseAddr, width -1); -} - -/*! - * @brief Sets the Rx sync width. - * - * A sync is the number of bit clocks of a frame. The sync width cannot be longer than the - * length of the first word of the frame. - * @param saiBaseAddr Register base address of SAI module. - * @param width How many bit clock in a sync. - */ -static inline void SAI_HAL_RxSetFrameSyncWidth(uint32_t saiBaseAddr, uint32_t width) -{ - BW_I2S_RCR4_SYWD(saiBaseAddr, width -1); -} - -/*! - * @brief Sets the polarity of the Tx frame sync. - * - * @param saiBaseAddr Register base address of SAI module. - * @param pol Polarity of sai frame sync, can be configured to active high or low. - */ -static inline void SAI_HAL_TxSetFrameSyncPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol) -{ - BW_I2S_TCR4_FSP(saiBaseAddr,pol); -} - -/*! - * @brief Sets the polarity of the Rx frame sync. - * - * @param saiBaseAddr Register base address of SAI module.. - * @param pol Polarity of SAI frame sync, can be configured to active high or low. - */ -static inline void SAI_HAL_RxSetFrameSyncPolarity(uint32_t saiBaseAddr, sai_clk_polarity_t pol) -{ - BW_I2S_RCR4_FSP(saiBaseAddr,pol); -} - -/*! - * @brief Sets the direction of the SAI Tx frame sync. - * - * This function sets the direction of frame sync. - * @param saiBaseAddr Register base address of SAI module. - * @param direction Frame sync generated internal or external. - */ -static inline void SAI_HAL_TxSetFrameSyncDir(uint32_t saiBaseAddr,sai_clk_direction_t direction) -{ - BW_I2S_TCR4_FSD(saiBaseAddr,direction); -} - -/*! - * @brief Sets the direction of the SAI Rx frame sync. - * - * This function sets the direction of frame sync. - * @param saiBaseAddr Register base address of SAI module. - * @param direction Frame sync generated internal or external. - */ -static inline void SAI_HAL_RxSetFrameSyncDir(uint32_t saiBaseAddr,sai_clk_direction_t direction) -{ - BW_I2S_RCR4_FSD(saiBaseAddr,direction); -} - -/*! - * @brief Sets the Tx data transfer order. - * - * This function sets the data transfer order. It can be set to MSB first or LSB first. - * @param saiBaseAddr Register base address of SAI module. - * @param order MSB transmit first or LSB transmit first. - */ -static inline void SAI_HAL_TxSetBitOrder(uint32_t saiBaseAddr, sai_data_order_t order) -{ - BW_I2S_TCR4_MF(saiBaseAddr,order); -} - -/*! - * @brief Sets the Rx data transfer order. - * - * This function sets the data transfer order. It can be set to MSB first or LSB first. - * @param saiBaseAddr Register base address of SAI module. - * @param order MSB transmit first or LSB transmit first. - */ -static inline void SAI_HAL_RxSetBitOrder(uint32_t saiBaseAddr, sai_data_order_t order) -{ - BW_I2S_RCR4_MF(saiBaseAddr,order); -} - -/*! - * @brief Tx Frame sync one bit early. - * - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means the frame sync one bit early and false means no early. - */ -static inline void SAI_HAL_TxSetFrameSyncEarlyCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_TCR4_FSE(saiBaseAddr,enable); -} - -/*! - * @brief Rx Frame sync one bit early. - * - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means the frame sync one bit early and false means no early. - */ -static inline void SAI_HAL_RxSetFrameSyncEarlyCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_RCR4_FSE(saiBaseAddr,enable); -} - -/*! @} */ - -/*! -* @name Word configurations -* @{ -*/ - -/*! - * @brief Sets the word size for Tx. - * - * The word size means the quantization level of audio file. - * SAI supports the 8 bit, 16 bit, 24 bit, and 32 bit formats. - * @param saiBaseAddr Register base address of SAI module. - * @param bits How many bits in a word. -*/ -static inline void SAI_HAL_TxSetWordSize(uint32_t saiBaseAddr,uint32_t bits) -{ - BW_I2S_TCR5_WNW(saiBaseAddr,bits-1); -} - -/*! - * @brief Sets the word size for Rx. - * - * The word size means the quantization level of audio file. - * SAI supports 8 bit, 16 bit, 24 bit, and 32 bit formats. - * @param saiBaseAddr Register base address of SAI module. - * @param bits How many bits in a word. -*/ -static inline void SAI_HAL_RxSetWordSize(uint32_t saiBaseAddr,uint32_t bits) -{ - BW_I2S_RCR5_WNW(saiBaseAddr,bits-1); -} - -/*! - * @brief Gets the Tx word size. - * @param saiBaseAddr Register base address of SAI module. -*/ -static inline uint32_t SAI_HAL_TxGetWordSize(uint32_t saiBaseAddr) -{ - return BR_I2S_TCR5_WNW(saiBaseAddr); -} - -/*! - * @brief Gets the Rx word size. - * @param saiBaseAddr Register base address of SAI module. -*/ -static inline uint32_t SAI_HAL_RxGetWordSize(uint32_t saiBaseAddr) -{ - return BR_I2S_RCR5_WNW(saiBaseAddr); -} - -/*! - * @brief Sets the size of the first word of the Tx frame . - * - * In I2S protocol, the size of the first word is the same as the size of other words. In some protocols, - * for example, AC'97, the first word is not the same size as others. This function - * sets the length of the first word which is, in most situations, the same as others. - * @param saiBaseAddr Register base address of SAI module. - * @param size The length of frame head word. - */ -static inline void SAI_HAL_TxSetFirstWordSize(uint32_t saiBaseAddr, uint8_t size) -{ - BW_I2S_TCR5_W0W(saiBaseAddr, size-1); -} - -/*! - * @brief Sets the size of the first word of Rx frame . - * - * In I2S protocol, the size of the first word is the same as the size of other words. In some protocols, - * for example, AC'97, the first word is not the same size as others. This function - * sets the length of the first word which is, in most situations, the same as others. - * @param saiBaseAddr Register base address of SAI module. - * @param size The length of frame head word. - */ -static inline void SAI_HAL_RxSetFirstWordSize(uint32_t saiBaseAddr, uint8_t size) -{ - BW_I2S_RCR5_W0W(saiBaseAddr, size-1); -} - -/*! - * @brief Sets the FIFO index for the first bit data. - * - * The FIFO is 32-bit in SAI. However, not all audio data is 32-bit, but is mostly 16-bit. - * In this situation, the codec needs to know which bit of the FIFO marks the valid audio data. - * @param saiBaseAddr Register base address of SAI module. - * @param index First bit shifted in FIFO. - */ -static inline void SAI_HAL_TxSetFirstBitShifted(uint32_t saiBaseAddr, uint32_t index) -{ - BW_I2S_TCR5_FBT(saiBaseAddr, index-1); -} - -/*! - * @brief Sets the index in FIFO for the first bit data. - * - * The FIFO is 32-bit in SAI. However, not all audio data is 32-bit, but is mostly 16-bit. - * In this situation, the codec needs to know which bit of the FIFO marks the valid audio data. - * @param saiBaseAddr Register base address of SAI module. - * @param index First bit shifted in FIFO. - */ -static inline void SAI_HAL_RxSetFirstBitShifted(uint32_t saiBaseAddr, uint32_t index) -{ - BW_I2S_RCR5_FBT(saiBaseAddr, index-1); -} - -/*!@}*/ - -/*! -* @name watermark settings -* @{ -*/ - -/*! - * @brief Sets the Tx watermark value. - * - * While the value in the FIFO is less or equal to the watermark , it generates an interrupt - * request or a DMA request. The watermark value cannot be greater than the depth of FIFO. - * @param saiBaseAddr Register base address of SAI module. - * @param watermark Watermark value of a FIFO. - */ -static inline void SAI_HAL_TxSetWatermark(uint32_t saiBaseAddr, uint32_t watermark) -{ - BW_I2S_TCR1_TFW(saiBaseAddr, watermark); -} - -/*! - * @brief Sets the Tx watermark value. - * - * While the value in the FIFO is more or equal to the watermark , it generates an interrupt - * request or a DMA request. The watermark value cannot be greater than the depth of FIFO. - * @param saiBaseAddr Register base address of SAI module. - * @param watermark Watermark value of a FIFO. - */ -static inline void SAI_HAL_RxSetWatermark(uint32_t saiBaseAddr, uint32_t watermark) -{ - BW_I2S_RCR1_RFW(saiBaseAddr, watermark); -} - -/*! - * @brief Gets the Tx watermark value. - * - * @param saiBaseAddr Register base address of SAI module. - */ -static inline uint32_t SAI_HAL_TxGetWatermark(uint32_t saiBaseAddr) -{ - return BR_I2S_TCR1_TFW(saiBaseAddr); -} - -/*! - * @brief Gets the Rx watermark value. - * - * @param saiBaseAddr Register base address of SAI module. - */ -static inline uint32_t SAI_HAL_RxGetWatermark(uint32_t saiBaseAddr) -{ - return BR_I2S_RCR1_RFW(saiBaseAddr); -} - -/*! @}*/ - -/*! - * @brief SAI Tx sync mode setting. - * - * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device. - * When configured for a synchronous mode of operation, the receiver must be configured for the - * asynchronous operation. - * @param saiBaseAddr Register base address of SAI module. - * @param sync_mode Synchronous mode or Asynchronous mode. - */ -void SAI_HAL_TxSetSyncMode(uint32_t saiBaseAddr, sai_sync_mode_t sync_mode); - -/*! - * @brief SAI Rx sync mode setting. - * - * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device. - * When configured for a synchronous mode of operation, the receiver must be configured for the - * asynchronous operation. - * @param saiBaseAddr Register base address of SAI module. - * @param sync_mode Synchronous mode or Asynchronous mode. - */ -void SAI_HAL_RxSetSyncMode(uint32_t saiBaseAddr, sai_sync_mode_t sync_mode); - -/*! - * @brief Gets the Tx FIFO read pointer. - * - * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO. - * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are - * equal except for the MSB, the FIFO is full. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel selected. - * @return FIFO read pointer value. - */ -static inline uint8_t SAI_HAL_TxGetFifoReadPointer(uint32_t saiBaseAddr, uint32_t fifo_channel) -{ - return BR_I2S_TFRn_RFP(saiBaseAddr,fifo_channel); -} - -/*! - * @brief Gets the Rx FIFO read pointer. - * - * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO. - * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are - * equal except for the MSB, the FIFO is full. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel selected. - * @return FIFO read pointer value. - */ -static inline uint8_t SAI_HAL_RxGetFifoReadPointer(uint32_t saiBaseAddr, uint32_t fifo_channel) -{ - return BR_I2S_RFRn_RFP(saiBaseAddr,fifo_channel); -} - -/*! - * @brief Gets the Tx FIFO write pointer. - * - * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO. - * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and write_ptr are - * equal except for the MSB, the FIFO is full. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel selected. - * @return FIFO read pointer value. - */ -static inline uint8_t SAI_HAL_TxGetFifoWritePointer(uint32_t saiBaseAddr,uint32_t fifo_channel) -{ - return BR_I2S_TFRn_WFP(saiBaseAddr,fifo_channel); -} - -/*! - * @brief Gets the Rx FIFO write pointer. - * - * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO. - * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and write_ptr are - * equal except for the MSB, the FIFO is full. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel selected. - * @return FIFO read pointer value. - */ -static inline uint8_t SAI_HAL_RxGetFifoWritePointer(uint32_t saiBaseAddr,uint32_t fifo_channel) -{ - return BR_I2S_RFRn_WFP(saiBaseAddr,fifo_channel); -} - -/*! - * @brief Gets the TDR register address. - * - * This function determines the dest/src address of the DMA transfer. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel selected. - * @return TDR register or RDR register address - */ -static inline uint32_t* SAI_HAL_TxGetFifoAddr(uint32_t saiBaseAddr, uint32_t fifo_channel) -{ - return (uint32_t *)HW_I2S_TDRn_ADDR(saiBaseAddr, fifo_channel); -} - -/*! - * @brief Gets the RDR register address. - * - * This function determines the dest/src address of the DMA transfer. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel selected. - * @return TDR register or RDR register address - */ -static inline uint32_t* SAI_HAL_RxGetFifoAddr(uint32_t saiBaseAddr, uint32_t fifo_channel) -{ - return (uint32_t *)HW_I2S_RDRn_ADDR(saiBaseAddr, fifo_channel); -} - -/*! - * @brief Enables the SAI Tx module. - * - * Enables the Tx. This function enables both the bit clock and the transfer channel. - * @param saiBaseAddr Register base address of SAI module. - */ -static inline void SAI_HAL_TxEnable(uint32_t saiBaseAddr) -{ - BW_I2S_TCSR_BCE(saiBaseAddr,true); - BW_I2S_TCSR_TE(saiBaseAddr,true); -} - -/*! - * @brief Enables the SAI Rx module. - * - * Enables the Rx. This function enables both the bit clock and the receive channel. - * @param saiBaseAddr Register base address of SAI module. - */ -static inline void SAI_HAL_RxEnable(uint32_t saiBaseAddr) -{ - BW_I2S_RCSR_BCE(saiBaseAddr,true); - BW_I2S_RCSR_RE(saiBaseAddr,true); -} - -/*! - * @brief Disables the Tx module. - * - * Disables the Tx. This function disables both the bit clock and the transfer channel. - * @param saiBaseAddr Register base address of SAI module. - */ -static inline void SAI_HAL_TxDisable(uint32_t saiBaseAddr) -{ - BW_I2S_TCSR_TE(saiBaseAddr,false); - BW_I2S_TCSR_BCE(saiBaseAddr,false); -} - -/*! - * @brief Disables the Rx module. - * - * Disables the Rx. This function disables both the bit clock and the receive channel. - * @param saiBaseAddr Register base address of SAI module. - */ -static inline void SAI_HAL_RxDisable(uint32_t saiBaseAddr) -{ - BW_I2S_RCSR_RE(saiBaseAddr,false); - BW_I2S_RCSR_BCE(saiBaseAddr,false); -} - -/*! - * @brief Enables the Tx interrupt from different interrupt sources. - * - * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag. - * This function sets which flag causes an interrupt request. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI interrupt request source. - * @param enable Enable or disable. - */ -void SAI_HAL_TxSetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source, bool enable); - -/*! - * @brief Enables the Rx interrupt from different interrupt sources. - * - * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag. - * This function sets which flag causes an interrupt request. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI interrupt request source. - * @param enable Enable or disable. - */ -void SAI_HAL_RxSetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source, bool enable); - -/*! - * @brief Gets the status as to whether the Tx interrupt source is enabled. - * - * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag. - * This function sets which flag causes an interrupt request. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI interrupt request source. - * @return Enabled or disabled. - */ -bool SAI_HAL_TxGetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source); - -/*! - * @brief Gets the status as to whether the Rx interrupt source is enabled. - * - * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag. - * This function sets which flag causes an interrupt request. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI interrupt request source. - * @return Enabled or disabled. - */ -bool SAI_HAL_RxGetIntCmd(uint32_t saiBaseAddr,sai_interrupt_request_t source); - -/*! - * @brief Enables the Tx DMA request from different sources. - * - * The DMA sources can be: FIFO warning and FIFO request. - * This function enables the DMA request from different DMA request sources. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI DMA request source. - * @param enable Enable or disable. - */ -void SAI_HAL_TxSetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source, bool enable); - -/*! - * @brief Enables the Rx DMA request from different sources. - * - * The DMA sources can be: FIFO warning and FIFO request. - * This function enables the DMA request from different DMA request sources. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI DMA request source. - * @param enable Enable or disable. - */ -void SAI_HAL_RxSetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source, bool enable); - -/*! - * @brief Gets the status whether the Tx DMA source is enabled. - * - * The DMA sources can be: FIFO warning and FIFO request. - * This function enables the DMA request from different DMA request sources. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI DMA request source. - * @param Enable or disable. - */ -bool SAI_HAL_TxGetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source); - -/*! - * @brief Gets the status whether the Rx DMA source is enabled. - * - * The DMA sources can be: FIFO warning and FIFO request. - * This function enables the DMA request from different DMA request sources. - * @param saiBaseAddr Register base address of SAI module. - * @param source SAI DMA request source. - * @return Enable or disable. - */ -bool SAI_HAL_RxGetDmaCmd(uint32_t saiBaseAddr, sai_dma_request_t source); - -/*! - * @brief Clears the Tx state flags. - * - * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error, - * FIFO request flag. - * @param saiBaseAddr Register base address of SAI module. - * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning. - */ -void SAI_HAL_TxClearStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag); - -/*! - * @brief Clears the Rx state flags. - * - * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error, - * FIFO request flag. - * @param saiBaseAddr Register base address of SAI module. - * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning. - */ -void SAI_HAL_RxClearStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag); - -/*! - * @brief Resets the Tx module. - * - * There are two kinds of resets: Software reset and FIFO reset. - * Software reset: resets all transmitter internal logic, including the bit clock generation, - * status flags and FIFO pointers. It does not reset the configuration registers. - * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer. - * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set, - * and before the FIFO is re-initialized and the Error Flag is cleared. - * @param saiBaseAddr Register base address of SAI module. - * @param type SAI reset type. - */ -void SAI_HAL_TxSetReset(uint32_t saiBaseAddr, sai_reset_type_t type); - -/*! - * @brief Resets the Rx module. - * - * There are two kinds of resets: Software reset and FIFO reset. - * Software reset: resets all transmitter internal logic, including the bit clock generation, - * status flags and FIFO pointers. It does not reset the configuration registers. - * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer. - * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set, - * and before the FIFO is re-initialized and the Error Flag is cleared. - * @param saiBaseAddr Register base address of SAI module. - * @param type SAI reset type. - */ -void SAI_HAL_RxSetReset(uint32_t saiBaseAddr, sai_reset_type_t type); - -/*! - * @brief Sets the Tx mask word of the frame. - * - * Each bit number represent the mask word index. For example, 0 represents mask the 0th word, 3 - * represents mask 0th and 1st word. The TMR register can be different from frame to frame. If the - * user wants a mono audio, set the mask to 0/1. - * @param saiBaseAddr Register base address of SAI module. - * @param mask Which bits need to be masked in a frame. - */ -static inline void SAI_HAL_TxSetWordMask(uint32_t saiBaseAddr, uint32_t mask) -{ - BW_I2S_TMR_TWM(saiBaseAddr, mask); -} - -/*! - * @brief Sets the Rx mask word of the frame. - * - * Each bit number represent the mask word index. For example, 0 represents mask the 0th word, 3 - * represents mask 0th and 1st word. The TMR register can be different from frame to frame. If the - * user wants a mono audio, set the mask to 0/1. - * @param saiBaseAddr Register base address of SAI module. - * @param mask Which bits need to be masked in a frame. - */ -static inline void SAI_HAL_RxSetWordMask(uint32_t saiBaseAddr, uint32_t mask) -{ - BW_I2S_RMR_RWM(saiBaseAddr, mask); -} - -/*! - * @brief Sets the Tx FIFO channel. - * - * A SAI saiBaseAddr includes a Tx and an Rx. Each has several channels according to - * different platforms. A channel means a path for the audio data input/output. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel number. - */ -static inline void SAI_HAL_TxSetDataChn(uint32_t saiBaseAddr, uint8_t fifo_channel) -{ - BW_I2S_TCR3_TCE(saiBaseAddr, 1u << fifo_channel); -} - -/*! - * @brief Sets the Rx FIFO channel. - * - * A SAI saiBaseAddr includes a Tx and a Rx. Each has several channels according to - * different platforms. A channel means a path for the audio data input/output. - * @param saiBaseAddr Register base address of SAI module. - * @param fifo_channel FIFO channel number. - */ -static inline void SAI_HAL_RxSetDataChn(uint32_t saiBaseAddr, uint8_t fifo_channel) -{ - BW_I2S_RCR3_RCE(saiBaseAddr, 1u << fifo_channel); -} - -/*! - * @brief Sets the running mode of the Tx. There is a debug mode, stop mode, and a normal mode. - * - * This function can set the working mode of the SAI saiBaseAddr. Stop mode is always - * used in low power cases, and the debug mode disables the SAI after the current - * transmit/receive is completed. - * @param saiBaseAddr Register base address of SAI module. - * @param run_mode SAI running mode. - * @param enable Enable or disable a mode. - */ -void SAI_HAL_TxSetRunModeCmd(uint32_t saiBaseAddr, sai_run_mode_t run_mode, bool enable); - -/*! - * @brief Sets the running mode of the Rx. There is a debug mode, stop mode, and a normal mode. - * - * This function can set the working mode of the SAI saiBaseAddr. Stop mode is always - * used in low power cases, and the debug mode disables the SAI after the current - * transmit/receive is completed. - * @param saiBaseAddr Register base address of SAI module. - * @param run_mode SAI running mode. - * @param enable Enable or disable a mode. - */ -void SAI_HAL_RxSetRunModeCmd(uint32_t saiBaseAddr, sai_run_mode_t run_mode, bool enable); - -/*! - * @brief Configures at which word the start of word flag is set in the Tx. - * - * @param saiBaseAddr Register base address of SAI module. - * @param index Which word triggers word start flag. - */ -static inline void SAI_HAL_TxSetWordStartIndex(uint32_t saiBaseAddr,uint32_t index) -{ - assert(index <= FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME); - BW_I2S_TCR3_WDFL(saiBaseAddr, index -1); -} - -/*! - * @brief Configures at which word the start of word flag is set in the Tx. - * - * @param saiBaseAddr Register base address of SAI module. - * @param index Which word triggers word start flag. - */ -static inline void SAI_HAL_RxSetWordStartIndex(uint32_t saiBaseAddr,uint32_t index) -{ - assert(index <= FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME); - BW_I2S_RCR3_WDFL(saiBaseAddr, index -1); -} - -/*! - * @brief Gets the state of the flags in the TCSR. - * @param saiBaseAddr Register base address of SAI module. - * @param flag State flag type, it can be FIFO error, FIFO warning and so on. - * @return True if detect word start otherwise false. - */ -bool SAI_HAL_TxGetStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag); - -/*! - * @brief Gets the state of the flags in the RCSR. - * @param saiBaseAddr Register base address of SAI module. - * @param flag State flag type, it can be FIFO error, FIFO warning and so on. - * @return True if detect word start otherwise false. - */ -bool SAI_HAL_RxGetStateFlag(uint32_t saiBaseAddr, sai_state_flag_t flag); - -/*! - * @brief Receives the data from the FIFO. - * @param saiBaseAddr Register base address of SAI module. - * @param rx_channel Rx FIFO channel. - * @param data Pointer to the address to be written in. - */ -static inline uint32_t SAI_HAL_ReceiveData(uint32_t saiBaseAddr, uint32_t rx_channel) -{ - assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT); - return HW_I2S_RDRn_RD(saiBaseAddr, rx_channel); -} - -/*! - * @brief Transmits data to the FIFO. - * @param saiBaseAddr Register base address of SAI module. - * @param tx_channel Tx FIFO channel. - * @param data Data value which needs to be written into FIFO. - */ -static inline void SAI_HAL_SendData(uint32_t saiBaseAddr, uint32_t tx_channel, uint32_t data) -{ - assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT); - HW_I2S_TDRn_WR(saiBaseAddr,tx_channel,data); -} - -/*! -* @brief Uses blocking to receive data. -* @param saiBaseAddr The SAI saiBaseAddr. -* @param rx_channel Rx FIFO channel. -* @return Received data. -*/ -uint32_t SAI_HAL_ReceiveDataBlocking(uint32_t saiBaseAddr, uint32_t rx_channel); - -/*! -* @brief Uses blocking to send data. -* @param saiBaseAddr The SAI saiBaseAddr. -* @param tx_channel Tx FIFO channel. -* @param data Data value which needs to be written into FIFO. -*/ -void SAI_HAL_SendDataBlocking(uint32_t saiBaseAddr, uint32_t tx_channel, uint32_t data); - -#if FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE -/*! - * @brief Tx on-demand mode setting. - * - * When set, the frame sync is generated internally. A frame sync is only generated when the - * FIFO warning flag is clear. - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means on demand mode enable, false means disable. - */ -static inline void SAI_HAL_TxSetOndemandCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_TCR4_ONDEM(saiBaseAddr, enable); -} - -/*! - * @brief Rx on-demand mode setting. - * - * When set, the frame sync is generated internally. A frame sync is only generated when the - * FIFO warning flag is clear. - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means on demand mode enable, false means disable. - */ -static inline void SAI_HAL_RxSetOndemandCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_RCR4_ONDEM(saiBaseAddr, enable); -} -#endif - -#if FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR -/*! - * @brief Tx FIFO continues on error. - * - * Configures when the SAI continues transmitting after a FIFO error has been detected. - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means on demand mode enable, false means disable. - */ -static inline void SAI_HAL_TxSetFIFOErrorContinueCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_TCR4_FCONT(saiBaseAddr, enable); -} - -/*! - * @brief Rx FIFO continues on error. - * - * Configures when the SAI continues transmitting after a FIFO error has been detected. - * @param saiBaseAddr Register base address of SAI module. - * @param enable True means on demand mode enable, false means disable. - */ -static inline void SAI_HAL_RxSetFIFOErrorContinueCmd(uint32_t saiBaseAddr, bool enable) -{ - BW_I2S_RCR4_FCONT(saiBaseAddr, enable); -} -#endif - -#if FSL_FEATURE_SAI_HAS_FIFO_PACKING -/*! - * @brief Tx FIFO packing mode setting. - * - * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is - * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO. - * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted - * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write - * pointer only increments when the full 32-bit FIFO word has been written by software. - * @param saiBaseAddr Register base address of SAI module. - * @param mode FIFO packing mode. - */ -static inline void SAI_HAL_TxSetFIFOPackingMode(uint32_t saiBaseAddr, sai_fifo_packing_t mode) -{ - BW_I2S_TCR4_FPACK(saiBaseAddr,mode); -} - -/*! - * @brief Rx FIFO packing mode setting. - * - * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is - * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO. - * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted - * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write - * pointer only increments when the full 32-bit FIFO word has been written by software. - * @param saiBaseAddr Register base address of SAI module. - * @param mode FIFO packing mode. - */ -static inline void SAI_HAL_RxSetFIFOPackingMode(uint32_t saiBaseAddr, sai_fifo_packing_t mode) -{ - BW_I2S_RCR4_FPACK(saiBaseAddr,mode); -} -#endif - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* __FSL_SAI_HAL_H__ */ -/******************************************************************************* -* EOF -*******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_features.h deleted file mode 100644 index 76488a0a76f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_features.h +++ /dev/null @@ -1,84 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140519 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_SDHC_FEATURES_H__) -#define __FSL_SDHC_FEATURES_H__ - -#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) - /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ - #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) - /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ - #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) - /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ - #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ - #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0) - /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ - #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) - /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ - #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ - #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) - /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ - #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (1) - /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ - #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (1) -#else - #define MBED_NO_SDHC -#endif - -#endif /* __FSL_SDHC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c deleted file mode 100644 index 309c9ff0ccb..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_sdhc_hal.h" - -#ifndef MBED_NO_SDHC - -/*FUNCTION**************************************************************** - * - * Function Name: SDHC_HAL_Init - * Description: Initialize sdhc hal - * - *END*********************************************************************/ -void SDHC_HAL_Init(uint32_t baseAddr) -{ - SDHC_HAL_SetSdClock(baseAddr, false); - SDHC_HAL_SetExternalDmaRequest(baseAddr, false); - SDHC_HAL_SetIntState(baseAddr, false, (uint32_t)-1); - SDHC_HAL_SetIntSignal(baseAddr, false, (uint32_t)-1); -} - -/*FUNCTION**************************************************************** - * - * Function Name: SDHC_HAL_SetIntSignal - * Description: Enable specified interrupts - * - *END*********************************************************************/ -void SDHC_HAL_SetIntSignal(uint32_t baseAddr, bool enable, uint32_t mask) -{ - if (enable) - { - HW_SDHC_IRQSIGEN_SET(baseAddr, mask); - } - else - { - HW_SDHC_IRQSIGEN_CLR(baseAddr, mask); - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: SDHC_HAL_SetIntState - * Description: Enable specified interrupts' state - * - *END*********************************************************************/ -void SDHC_HAL_SetIntState(uint32_t baseAddr, bool enable, uint32_t mask) -{ - if (enable) - { - HW_SDHC_IRQSTATEN_SET(baseAddr, mask); - } - else - { - HW_SDHC_IRQSTATEN_CLR(baseAddr, mask); - } -} - -/*FUNCTION**************************************************************** - * - * Function Name: SDHC_HAL_GetResponse - * Description: get command response - * - *END*********************************************************************/ -uint32_t SDHC_HAL_GetResponse(uint32_t baseAddr, uint32_t index) -{ - uint32_t ret = 0; - - assert(index < 4); - - switch(index) - { - case 0: - ret = BR_SDHC_CMDRSP0_CMDRSP0(baseAddr); - break; - case 1: - ret = BR_SDHC_CMDRSP1_CMDRSP1(baseAddr); - break; - case 2: - ret = BR_SDHC_CMDRSP2_CMDRSP2(baseAddr); - break; - case 3: - ret = BR_SDHC_CMDRSP3_CMDRSP3(baseAddr); - break; - default: - break; - } - - return ret; -} - -/*FUNCTION**************************************************************** - * - * Function Name: SDHC_HAL_InitCard - * Description: Initialize card by sending 80 clocks to card - * - *END*********************************************************************/ -uint32_t SDHC_HAL_InitCard(uint32_t baseAddr, uint32_t timeout) -{ - assert(timeout); - BW_SDHC_SYSCTL_INITA(baseAddr, 1); - while((!BR_SDHC_SYSCTL_INITA(baseAddr))) - { - if (!timeout) - { - break; - } - timeout--; - } - return (!timeout); -} - -/*FUNCTION**************************************************************** - * - * Function Name: SDHC_HAL_Reset - * Description: Perform different kinds of reset - * - *END*********************************************************************/ -uint32_t SDHC_HAL_Reset(uint32_t baseAddr, uint32_t type, uint32_t timeout) -{ - uint32_t mask; - assert(timeout); - mask = type & (BM_SDHC_SYSCTL_RSTA - | BM_SDHC_SYSCTL_RSTC - | BM_SDHC_SYSCTL_RSTD); - HW_SDHC_SYSCTL_SET(baseAddr, mask); - while (!(HW_SDHC_SYSCTL_RD(baseAddr) & mask)) - { - if (!timeout) - { - break; - } - timeout--; - } - return (!timeout); -} - -#endif /* MBED_NO_SDHC */ - -/************************************************************************************************* - * EOF - ************************************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h deleted file mode 100644 index 7d86b197892..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h +++ /dev/null @@ -1,1236 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_SDHC_HAL_H__ -#define __FSL_SDHC_HAL_H__ - -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sdhc_features.h" - -#ifndef MBED_NO_SDHC - -/*! @addtogroup sdhc_hal */ -/*! @{ */ - -/* PRSSTA */ -#define SDHC_HAL_DAT0_LEVEL (BM_SDHC_PRSSTAT_DLSL & (1 << 24)) - -/* XFERTYP */ -#define SDHC_HAL_MAX_BLOCK_COUNT ((1 << BS_SDHC_BLKATTR_BLKCNT) - 1) -#define SDHC_HAL_ENABLE_DMA BM_SDHC_XFERTYP_DMAEN - -#define SDHC_HAL_CMD_TYPE_SUSPEND (BF_SDHC_XFERTYP_CMDTYP(1)) -#define SDHC_HAL_CMD_TYPE_RESUME (BF_SDHC_XFERTYP_CMDTYP(2)) -#define SDHC_HAL_CMD_TYPE_ABORT (BF_SDHC_XFERTYP_CMDTYP(3)) - -#define SDHC_HAL_ENABLE_BLOCK_COUNT BM_SDHC_XFERTYP_BCEN -#define SDHC_HAL_ENABLE_AUTO_CMD12 BM_SDHC_XFERTYP_AC12EN -#define SDHC_HAL_ENABLE_DATA_READ BM_SDHC_XFERTYP_DTDSEL -#define SDHC_HAL_MULTIPLE_BLOCK BM_SDHC_XFERTYP_MSBSEL - -#define SDHC_HAL_RESP_LEN_136 ((0x1 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP) -#define SDHC_HAL_RESP_LEN_48 ((0x2 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP) -#define SDHC_HAL_RESP_LEN_48_BC ((0x3 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP) - -#define SDHC_HAL_ENABLE_CRC_CHECK BM_SDHC_XFERTYP_CCCEN -#define SDHC_HAL_ENABLE_INDEX_CHECK BM_SDHC_XFERTYP_CICEN -#define SDHC_HAL_DATA_PRESENT BM_SDHC_XFERTYP_DPSEL - -/* SYSCTL */ -#define SDHC_HAL_MAX_DVS (16U) -#define SDHC_HAL_INITIAL_DVS (1U) /* initial value of divisor to calculate clock rate */ -#define SDHC_HAL_INITIAL_CLKFS (2U) /* initial value of clock selector to calculate clock rate */ -#define SDHC_HAL_NEXT_DVS(x) do { ((x) += 1); } while(0) -#define SDHC_HAL_PREV_DVS(x) do { ((x) -= 1); } while(0) -#define SDHC_HAL_MAX_CLKFS (256U) -#define SDHC_HAL_NEXT_CLKFS(x) do { ((x) <<= 1); } while(0) -#define SDHC_HAL_PREV_CLKFS(x) do { ((x) >>= 1); } while(0) - -/* IRQSTAT */ -#define SDHC_HAL_CMD_COMPLETE_INT BM_SDHC_IRQSTAT_CC -#define SDHC_HAL_DATA_COMPLETE_INT BM_SDHC_IRQSTAT_TC -#define SDHC_HAL_BLOCK_GAP_EVENT_INT BM_SDHC_IRQSTAT_BGE -#define SDHC_HAL_DMA_INT BM_SDHC_IRQSTAT_DINT -#define SDHC_HAL_DMA_ERR_INT BM_SDHC_IRQSTAT_DMAE -#define SDHC_HAL_BUF_WRITE_READY_INT BM_SDHC_IRQSTAT_BWR -#define SDHC_HAL_BUF_READ_READY_INT BM_SDHC_IRQSTAT_BRR -#define SDHC_HAL_CARD_INSERTION_INT BM_SDHC_IRQSTAT_CINS -#define SDHC_HAL_CARD_REMOVAL_INT BM_SDHC_IRQSTAT_CRM -#define SDHC_HAL_CARD_INT BM_SDHC_IRQSTAT_CINT -#define SDHC_HAL_CMD_TIMEOUT_ERR_INT BM_SDHC_IRQSTAT_CTOE -#define SDHC_HAL_CMD_CRC_ERR_INT BM_SDHC_IRQSTAT_CCE -#define SDHC_HAL_CMD_END_BIT_ERR_INT BM_SDHC_IRQSTAT_CEBE -#define SDHC_HAL_CMD_INDEX_ERR_INT BM_SDHC_IRQSTAT_CIE -#define SDHC_HAL_DATA_TIMEOUT_ERR_INT BM_SDHC_IRQSTAT_DTOE -#define SDHC_HAL_DATA_CRC_ERR_INT BM_SDHC_IRQSTAT_DCE -#define SDHC_HAL_DATA_END_BIT_ERR_INT BM_SDHC_IRQSTAT_DEBE -#define SDHC_HAL_AUTO_CMD12_ERR_INT BM_SDHC_IRQSTAT_AC12E - -#define SDHC_HAL_CMD_ERR_INT ((uint32_t)(SDHC_HAL_CMD_TIMEOUT_ERR_INT | \ - SDHC_HAL_CMD_CRC_ERR_INT | \ - SDHC_HAL_CMD_END_BIT_ERR_INT | \ - SDHC_HAL_CMD_INDEX_ERR_INT)) -#define SDHC_HAL_DATA_ERR_INT ((uint32_t)(SDHC_HAL_DATA_TIMEOUT_ERR_INT | \ - SDHC_HAL_DATA_CRC_ERR_INT | \ - SDHC_HAL_DATA_END_BIT_ERR_INT)) -#define SDHC_HAL_DATA_ALL_INT ((uint32_t)(SDHC_HAL_DATA_ERR_INT | \ - SDHC_HAL_DATA_COMPLETE_INT | \ - SDHC_HAL_BUF_READ_READY_INT | \ - SDHC_HAL_BUF_WRITE_READY_INT | \ - SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT)) -#define SDHC_HAL_CMD_ALL_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \ - SDHC_HAL_CMD_COMPLETE_INT | \ - SDHC_HAL_AUTO_CMD12_ERR_INT)) -#define SDHC_HAL_CD_ALL_INT ((uint32_t)(SDHC_HAL_CARD_INSERTION_INT | \ - SDHC_HAL_CARD_REMOVAL_INT)) -#define SDHC_HAL_ALL_ERR_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \ - SDHC_HAL_DATA_ERR_INT | \ - SDHC_HAL_AUTO_CMD12_ERR_INT | \ - SDHC_HAL_DMA_ERR_INT)) - -/* AC12ERR */ -#define SDHC_HAL_ACMD12_NOT_EXEC_ERR BM_SDHC_AC12ERR_AC12NE -#define SDHC_HAL_ACMD12_TIMEOUT_ERR BM_SDHC_AC12ERR_AC12TOE -#define SDHC_HAL_ACMD12_END_BIT_ERR BM_SDHC_AC12ERR_AC12EBE -#define SDHC_HAL_ACMD12_CRC_ERR BM_SDHC_AC12ERR_AC12CE -#define SDHC_HAL_ACMD12_INDEX_ERR BM_SDHC_AC12ERR_AC12IE -#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR BM_SDHC_AC12ERR_CNIBAC12E - -/* HTCAPBLT */ -#define SDHC_HAL_SUPPORT_ADMA BM_SDHC_HTCAPBLT_ADMAS -#define SDHC_HAL_SUPPORT_HIGHSPEED BM_SDHC_HTCAPBLT_HSS -#define SDHC_HAL_SUPPORT_DMA BM_SDHC_HTCAPBLT_DMAS -#define SDHC_HAL_SUPPORT_SUSPEND_RESUME BM_SDHC_HTCAPBLT_SRS -#define SDHC_HAL_SUPPORT_3_3_V BM_SDHC_HTCAPBLT_VS33 -#define SDHC_HAL_SUPPORT_3_0_V BM_SDHC_HTCAPBLT_VS30 -#define SDHC_HAL_SUPPORT_1_8_V BM_SDHC_HTCAPBLT_VS18 - -/* FEVT */ -#define SDHC_HAL_ACMD12_NOT_EXEC_ERR_EVENT BM_SDHC_FEVT_AC12NE -#define SDHC_HAL_ACMD12_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_AC12TOE -#define SDHC_HAL_ACMD12_CRC_ERR_EVENT BM_SDHC_FEVT_AC12CE -#define SDHC_HAL_ACMD12_END_BIT_ERR_EVENT BM_SDHC_FEVT_AC12EBE -#define SDHC_HAL_ACMD12_INDEX_ERR_EVENT BM_SDHC_FEVT_AC12IE -#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR_EVENT BM_SDHC_FEVT_CNIBAC12E -#define SDHC_HAL_CMD_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_CTOE -#define SDHC_HAL_CMD_CRC_ERR_EVENT BM_SDHC_FEVT_CCE -#define SDHC_HAL_CMD_END_BIT_ERR_EVENT BM_SDHC_FEVT_CEBE -#define SDHC_HAL_CMD_INDEX_ERR_EVENT BM_SDHC_FEVT_CIE -#define SDHC_HAL_DATA_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_DTOE -#define SDHC_HAL_DATA_CRC_ERR_EVENT BM_SDHC_FEVT_DCE -#define SDHC_HAL_DATA_END_BIT_ERR_EVENT BM_SDHC_FEVT_DEBE -#define SDHC_HAL_ACMD12_ERR_EVENT BM_SDHC_FEVT_AC12E -#define SDHC_HAL_CARD_INT_EVENT BM_SDHC_FEVT_CINT -#define SDHC_HAL_DMA_ERROR_EVENT BM_SDHC_FEVT_DMAE - -/* MMCBOOT */ -typedef enum _sdhc_hal_mmcboot { - kSdhcHalMmcbootNormal = 0, - kSdhcHalMmcbootAlter = 1, -} sdhc_hal_mmcboot_t; - -/* PROCTL */ -typedef enum _sdhc_hal_led { - kSdhcHalLedOff = 0, - kSdhcHalLedOn = 1, -} sdhc_hal_led_t; - -typedef enum _sdhc_hal_dtw { - kSdhcHalDtw1Bit = 0, - kSdhcHalDtw4Bit = 1, - kSdhcHalDtw8Bit = 2, -} sdhc_hal_dtw_t; - -typedef enum _sdhc_hal_endian { - kSdhcHalEndianBig = 0, - kSdhcHalEndianHalfWordBig = 1, - kSdhcHalEndianLittle = 2, -} sdhc_hal_endian_t; - -typedef enum _sdhc_hal_dma_mode { - kSdhcHalDmaSimple = 0, - kSdhcHalDmaAdma1 = 1, - kSdhcHalDmaAdma2 = 2, -} sdhc_hal_dma_mode_t; - -#define SDHC_HAL_ADMA1_ADDR_ALIGN (4096) -#define SDHC_HAL_ADMA1_LEN_ALIGN (4096) -#define SDHC_HAL_ADMA2_ADDR_ALIGN (4) -#define SDHC_HAL_ADMA2_LEN_ALIGN (4) - -/* - * ADMA1 descriptor table - * |------------------------|---------|--------------------------| - * | Address/page Field |reserved | Attribute | - * |------------------------|---------|--------------------------| - * |31 12|11 6|05 |04 |03|02 |01 |00 | - * |------------------------|---------|----|----|--|---|---|-----| - * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| - * |------------------------|---------|----|----|--|---|---|-----| - * - * - * |------|------|-----------------|-------|-------------| - * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | - * |------|------|-----------------|---------------------| - * | 0 | 0 | No op | Don't care | - * |------|------|-----------------|-------|-------------| - * | 0 | 1 | Set data length | 0000 | Data Length | - * |------|------|-----------------|-------|-------------| - * | 1 | 0 | Transfer data | Data address | - * |------|------|-----------------|---------------------| - * | 1 | 1 | Link descriptor | Descriptor address | - * |------|------|-----------------|---------------------| - * - */ -typedef uint32_t sdhc_hal_adma1_descriptor_t; -#define SDHC_HAL_ADMA1_DESC_VALID_MASK (1 << 0) -#define SDHC_HAL_ADMA1_DESC_END_MASK (1 << 1) -#define SDHC_HAL_ADMA1_DESC_INT_MASK (1 << 2) -#define SDHC_HAL_ADMA1_DESC_ACT1_MASK (1 << 4) -#define SDHC_HAL_ADMA1_DESC_ACT2_MASK (1 << 5) -#define SDHC_HAL_ADMA1_DESC_TYPE_NOP (SDHC_HAL_ADMA1_DESC_VALID_MASK) -#define SDHC_HAL_ADMA1_DESC_TYPE_TRAN (SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) -#define SDHC_HAL_ADMA1_DESC_TYPE_LINK (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) -#define SDHC_HAL_ADMA1_DESC_TYPE_SET (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) -#define SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT (12) -#define SDHC_HAL_ADMA1_DESC_ADDRESS_MASK (0xFFFFFU) -#define SDHC_HAL_ADMA1_DESC_LEN_SHIFT (12) -#define SDHC_HAL_ADMA1_DESC_LEN_MASK (0xFFFFU) -#define SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA1_DESC_LEN_MASK + 1) - -/* - * ADMA2 descriptor table - * |----------------|---------------|-------------|--------------------------| - * | Address Field | length | reserved | Attribute | - * |----------------|---------------|-------------|--------------------------| - * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | - * |----------------|---------------|-------------|----|----|--|---|---|-----| - * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| - * |----------------|---------------|-------------|----|----|--|---|---|-----| - * - * - * | Act2 | Act1 | Comment | Operation | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 0 | 0 | No op | Don't care | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 0 | 1 | Reserved | Read this line and go to next one | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 1 | 1 | Link descriptor | Link to another descriptor | - * |------|------|-----------------|-------------------------------------------------------------------| - * - */ -typedef struct SdhcHalAdma2Descriptor { - uint32_t attribute; - uint32_t *address; -} sdhc_hal_adma2_descriptor_t; - -#define SDHC_HAL_ADMA2_DESC_VALID_MASK (1 << 0) -#define SDHC_HAL_ADMA2_DESC_END_MASK (1 << 1) -#define SDHC_HAL_ADMA2_DESC_INT_MASK (1 << 2) -#define SDHC_HAL_ADMA2_DESC_ACT1_MASK (1 << 4) -#define SDHC_HAL_ADMA2_DESC_ACT2_MASK (1 << 5) -#define SDHC_HAL_ADMA2_DESC_TYPE_NOP (SDHC_HAL_ADMA2_DESC_VALID_MASK) -#define SDHC_HAL_ADMA2_DESC_TYPE_RCV (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) -#define SDHC_HAL_ADMA2_DESC_TYPE_TRAN (SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) -#define SDHC_HAL_ADMA2_DESC_TYPE_LINK (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) -#define SDHC_HAL_ADMA2_DESC_LEN_SHIFT (16) -#define SDHC_HAL_ADMA2_DESC_LEN_MASK (0xFFFFU) -#define SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA2_DESC_LEN_MASK + 1) - -#define SDHC_HAL_RST_TYPE_ALL BM_SDHC_SYSCTL_RSTA -#define SDHC_HAL_RST_TYPE_CMD BM_SDHC_SYSCTL_RSTC -#define SDHC_HAL_RST_TYPE_DATA BM_SDHC_SYSCTL_RSTD - -#define SDHC_HAL_MAX_BLKLEN_512B (0U) -#define SDHC_HAL_MAX_BLKLEN_1024B (1U) -#define SDHC_HAL_MAX_BLKLEN_2048B (2U) -#define SDHC_HAL_MAX_BLKLEN_4096B (3U) - -/************************************************************************************************* - * API - ************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name SDHC HAL FUNCTION */ -/*@{ */ - -/*! - * @brief Configures the DMA address. - * - * @param baseAddr SDHC base address - * @param address the DMA address - */ -static inline void SDHC_HAL_SetDmaAddress(uint32_t baseAddr, uint32_t address) -{ - HW_SDHC_DSADDR_WR(baseAddr, BF_SDHC_DSADDR_DSADDR(address)); -} - -/*! - * @brief Gets the DMA address. - * - * @param baseAddr SDHC base address - * @return the DMA address - */ -static inline uint32_t SDHC_HAL_GetDmaAddress(uint32_t baseAddr) -{ - return HW_SDHC_DSADDR_RD(baseAddr); -} - -/*! - * @brief Gets the block size configured. - * - * @param baseAddr SDHC base address - * @return the block size already configured - */ -static inline uint32_t SDHC_HAL_GetBlockSize(uint32_t baseAddr) -{ - return BR_SDHC_BLKATTR_BLKSIZE(baseAddr); -} - -/*! - * @brief Sets the block size. - * - * @param baseAddr SDHC base address - * @param blockSize the block size - */ -static inline void SDHC_HAL_SetBlockSize(uint32_t baseAddr, uint32_t blockSize) -{ - BW_SDHC_BLKATTR_BLKSIZE(baseAddr, blockSize); -} - -/*! - * @brief Sets the block count. - * - * @param baseAddr SDHC base address - * @param blockCount the block count - */ -static inline void SDHC_HAL_SetBlockCount(uint32_t baseAddr, uint32_t blockCount) -{ - BW_SDHC_BLKATTR_BLKCNT(baseAddr, blockCount); -} - -/*! - * @brief Gets the block count configured. - * - * @param baseAddr SDHC base address - * @return the block count already configured - */ -static inline uint32_t SDHC_HAL_GetBlockCount(uint32_t baseAddr) -{ - return BR_SDHC_BLKATTR_BLKCNT(baseAddr); -} - -/*! - * @brief Configures the command argument. - * - * @param baseAddr SDHC base address - * @param arg the command argument - */ -static inline void SDHC_HAL_SetCmdArgument(uint32_t baseAddr, uint32_t arg) -{ - BW_SDHC_CMDARG_CMDARG(baseAddr, arg); -} - -/*! - * @brief Sends a command. - * - * @param baseAddr SDHC base address - * @param index command index - * @param flags transfer type flags - */ -static inline void SDHC_HAL_SendCmd(uint32_t baseAddr, uint32_t index, uint32_t flags) -{ - HW_SDHC_XFERTYP_WR(baseAddr, ((index << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX) - | (flags & ( BM_SDHC_XFERTYP_DMAEN | BM_SDHC_XFERTYP_MSBSEL | BM_SDHC_XFERTYP_DPSEL - | BM_SDHC_XFERTYP_CMDTYP | BM_SDHC_XFERTYP_BCEN | BM_SDHC_XFERTYP_CICEN - | BM_SDHC_XFERTYP_CCCEN | BM_SDHC_XFERTYP_RSPTYP | BM_SDHC_XFERTYP_DTDSEL - | BM_SDHC_XFERTYP_AC12EN))); -} - -/*! - * @brief Fills the the data port. - * - * @param baseAddr SDHC base address - * @param data the data about to be sent - */ -static inline void SDHC_HAL_SetData(uint32_t baseAddr, uint32_t data) -{ - HW_SDHC_DATPORT_WR(baseAddr, data); -} - -/*! - * @brief Retrieves the data from the data port. - * - * @param baseAddr SDHC base address - * @return data the data read - */ -static inline uint32_t SDHC_HAL_GetData(uint32_t baseAddr) -{ - return BR_SDHC_DATPORT_DATCONT(baseAddr); -} - -/*! - * @brief Checks whether the command inhibit bit is set or not. - * - * @param baseAddr SDHC base address - * @return 1 if command inhibit, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsCmdInhibit(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_CIHB(baseAddr); -} - -/*! - * @brief Checks whether data inhibit bit is set or not. - * - * @param baseAddr SDHC base address - * @return 1 if data inhibit, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsDataInhibit(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_CDIHB(baseAddr); -} - -/*! - * @brief Checks whether data line is active. - * - * @param baseAddr SDHC base address - * @return 1 if it's active, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsDataLineActive(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_DLA(baseAddr); -} - -/*! - * @brief Checks whether the SD clock is stable or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's stable, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsSdClockStable(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_SDSTB(baseAddr); -} - -/*! - * @brief Checks whether the IPG clock is off or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's off, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsIpgClockOff(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_IPGOFF(baseAddr); -} - -/*! - * @brief Checks whether the system clock is off or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's off, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsSysClockOff(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_HCKOFF(baseAddr); -} - -/*! - * @brief Checks whether the peripheral clock is off or not. - * - * @param baseAddr SDHC base address. - * @return 1 if it's off, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsPeripheralClockOff(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_PEROFF(baseAddr); -} - -/*! - * @brief Checks whether the SD clock is off or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's off, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsSdClkOff(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_SDOFF(baseAddr); -} - -/*! - * @brief Checks whether the write transfer is active or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's active, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsWriteTransferActive(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_WTA(baseAddr); -} - -/*! - * @brief Checks whether the read transfer is active or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's off, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsReadTransferActive(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_RTA(baseAddr); -} - -/*! - * @brief Check whether the buffer write is enabled or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's isEnabledd, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsBuffWriteEnabled(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_BWEN(baseAddr); -} - -/*! - * @brief Checks whether the buffer read is enabled or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's isEnabledd, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsBuffReadEnabled(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_BREN(baseAddr); -} - -/*! - * @brief Checks whether the card is inserted or not. - * - * @param baseAddr SDHC base address. - * @return 1 if it's inserted, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsCardInserted(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_CINS(baseAddr); -} - -/*! - * @brief Checks whether the command line signal is high or not. - * - * @param baseAddr SDHC base address - * @return 1 if it's high, 0 if not. - */ -static inline uint32_t SDHC_HAL_IsCmdLineLevelHigh(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_CLSL(baseAddr); -} - -/*! - * @brief Gets the data line signal level or not. - * - * @param baseAddr SDHC base address - * @return [7:0] data line signal level - */ -static inline uint32_t SDHC_HAL_GetDataLineLevel(uint32_t baseAddr) -{ - return BR_SDHC_PRSSTAT_DLSL(baseAddr); -} - -/*! - * @brief Sets the LED state. - * - * @param baseAddr SDHC base address - * @param state the LED state - */ -static inline void SDHC_HAL_SetLedState(uint32_t baseAddr, sdhc_hal_led_t state) -{ - BW_SDHC_PROCTL_LCTL(baseAddr, state); -} - -/*! - * @brief Sets the data transfer width. - * - * @param baseAddr SDHC base address - * @param dtw data transfer width - */ -static inline void SDHC_HAL_SetDataTransferWidth(uint32_t baseAddr, sdhc_hal_dtw_t dtw) -{ - BW_SDHC_PROCTL_DTW(baseAddr, dtw); -} - -/*! - * @brief Checks whether the DAT3 is taken as card detect pin. - * - * @param baseAddr SDHC base address - * @return if DAT3 as card detect pin is enabled - */ -static inline bool SDHC_HAL_IsD3cdEnabled(uint32_t baseAddr) -{ - return BR_SDHC_PROCTL_D3CD(baseAddr); -} - -/*! - * @brief Enables the DAT3 as a card detect pin. - * - * @param baseAddr SDHC base address - * @param enable to enable DAT3 as card detect pin - */ -static inline void SDHC_HAL_SetD3cd(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_D3CD(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Configures the endian mode. - * - * @param baseAddr SDHC base address - * @param endianMode endian mode - */ -static inline void SDHC_HAL_SetEndian(uint32_t baseAddr, sdhc_hal_endian_t endianMode) -{ - BW_SDHC_PROCTL_EMODE(baseAddr, endianMode); -} - -/*! -* @brief Gets the card detect test level. -* -* @param baseAddr SDHC base address -* @return card detect test level -*/ -static inline uint32_t SDHC_HAL_GetCdTestLevel(uint32_t baseAddr) -{ - return BR_SDHC_PROCTL_CDTL(baseAddr); -} - -/*! -* @brief Enables the card detect test. -* -* @param baseAddr SDHC base address -* @param enable to enable card detect signal for test purpose -*/ -static inline void SDHC_HAL_SetCdTest(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_CDSS(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Sets the DMA mode. -* -* @param baseAddr SDHC base address -* @param dmaMode the DMA mode -*/ -static inline void SDHC_HAL_SetDmaMode(uint32_t baseAddr, sdhc_hal_dma_mode_t dmaMode) -{ - BW_SDHC_PROCTL_DMAS(baseAddr, dmaMode); -} - -/*! -* @brief Enables stop at the block gap. -* -* @param baseAddr SDHC base address -* @param enable to stop at block gap request -*/ -static inline void SDHC_HAL_SetStopAtBlockGap(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_SABGREQ(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Restarts a transaction which has stopped at the block gap. -* -* @param baseAddr SDHC base address -*/ -static inline void SDHC_HAL_SetContinueRequest(uint32_t baseAddr) -{ - BW_SDHC_PROCTL_CREQ(baseAddr, 1); -} - -/*! -* @brief Enables the read wait control for the SDIO cards. -* -* @param baseAddr SDHC base address -* @param enable to enable read wait control -*/ -static inline void SDHC_HAL_SetReadWaitCtrl(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_RWCTL(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables stop at the block gap requests. -* -* @param baseAddr SDHC base address -* @param enable to enable interrupt at block gap -*/ -static inline void SDHC_HAL_SetIntStopAtBlockGap(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_IABG(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables wakeup event on the card interrupt. -* -* @param baseAddr SDHC base address -* @param enable to enable wakeup event on card interrupt -*/ -static inline void SDHC_HAL_SetWakeupOnCardInt(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_WECINT(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables wakeup event on the card insertion. -* -* @param baseAddr SDHC base address -* @param enable to enable wakeup event on card insertion -*/ -static inline void SDHC_HAL_SetWakeupOnCardInsertion(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_WECINS(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables wakeup event on card removal. -* -* @param baseAddr SDHC base address -* @param enable to enable wakeup event on card removal -*/ -static inline void SDHC_HAL_SetWakeupOnCardRemoval(uint32_t baseAddr, bool enable) -{ - BW_SDHC_PROCTL_WECRM(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables the IPG clock and no automatic clock gating off. -* -* @param baseAddr SDHC base address -* @param enable to enable IPG clock -*/ -static inline void SDHC_HAL_SetIpgClock(uint32_t baseAddr, bool enable) -{ - BW_SDHC_SYSCTL_IPGEN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables the system clock and no automatic clock gating off. -* -* @param baseAddr SDHC base address -* @param enable to enable SYS clock -*/ -static inline void SDHC_HAL_SetSysClock(uint32_t baseAddr, bool enable) -{ - BW_SDHC_SYSCTL_HCKEN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables the peripheral clock and no automatic clock gating off. -* -* @param baseAddr SDHC base address -* @param enable to enable Peripheral clock -*/ -static inline void SDHC_HAL_SetPeripheralClock(uint32_t baseAddr, bool enable) -{ - BW_SDHC_SYSCTL_PEREN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables the SD clock. It should be disabled before changing the SD clock -* frequency. -* -* @param baseAddr SDHC base address -* @param enable to enable SD clock or not -*/ -static inline void SDHC_HAL_SetSdClock(uint32_t baseAddr, bool enable) -{ - BW_SDHC_SYSCTL_SDCLKEN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Sets the SD clock frequency divisor. -* -* @param baseAddr SDHC base address -* @param divisor the divisor -*/ -static inline void SDHC_HAL_SetClockDivisor(uint32_t baseAddr, uint32_t divisor) -{ - BW_SDHC_SYSCTL_DVS(baseAddr, divisor); -} - -/*! -* @brief Sets the SD clock frequency select. -* -* @param baseAddr SDHC base address -* @param frequency the frequency selector -*/ -static inline void SDHC_HAL_SetClockFrequency(uint32_t baseAddr, uint32_t frequency) -{ - BW_SDHC_SYSCTL_SDCLKFS(baseAddr, frequency); -} - -/*! -* @brief Sets the data timeout counter value. -* -* @param baseAddr SDHC base address -* @param timeout Data timeout counter value -*/ -static inline void SDHC_HAL_SetDataTimeout(uint32_t baseAddr, uint32_t timeout) -{ - BW_SDHC_SYSCTL_DTOCV(baseAddr, timeout); -} - -/*! -* @brief Gets the current interrupt status. -* -* @param baseAddr SDHC base address -* @return current interrupt flags -*/ -static inline uint32_t SDHC_HAL_GetIntFlags(uint32_t baseAddr) -{ - return HW_SDHC_IRQSTAT_RD(baseAddr); -} - -/*! -* @brief Clears a specified interrupt status. -* -* @param baseAddr SDHC base address -* @param mask to specify interrupts' flags to be cleared -*/ -static inline void SDHC_HAL_ClearIntFlags(uint32_t baseAddr, uint32_t mask) -{ - HW_SDHC_IRQSTAT_WR(baseAddr, mask); -} - -/*! -* @brief Gets the currently enabled interrupt signal. -* -* @param baseAddr SDHC base address -* @return currently enabled interrupt signal -*/ -static inline uint32_t SDHC_HAL_GetIntSignal(uint32_t baseAddr) -{ - return HW_SDHC_IRQSIGEN_RD(baseAddr); -} - -/*! -* @brief Gets the currently enabled interrupt state. -* -* @param baseAddr SDHC base address -* @return currently enabled interrupts' state -*/ -static inline uint32_t SDHC_HAL_GetIntState(uint32_t baseAddr) -{ - return HW_SDHC_IRQSTATEN_RD(baseAddr); -} - -/*! -* @brief Gets the auto cmd12 error. -* -* @param baseAddr SDHC base address -* @return auto cmd12 error status -*/ -static inline uint32_t SDHC_HAL_GetAc12Error(uint32_t baseAddr) -{ - return HW_SDHC_AC12ERR_RD(baseAddr); -} - -/*! -* @brief Gets the maximum block length supported. -* -* @param baseAddr SDHC base address -* @return the maximum block length support -*/ -static inline uint32_t SDHC_HAL_GetMaxBlockLength(uint32_t baseAddr) -{ - return BR_SDHC_HTCAPBLT_MBL(baseAddr); -} - -/*! -* @brief Checks whether the ADMA is supported. -* -* @param baseAddr SDHC base address -* @return if ADMA is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportAdma(uint32_t baseAddr) -{ - return BR_SDHC_HTCAPBLT_ADMAS(baseAddr); -} - -/*! -* @brief Checks whether the high speed is supported. -* -* @param baseAddr SDHC base address -* @return if high speed is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportHighspeed(uint32_t baseAddr) -{ - return BR_SDHC_HTCAPBLT_HSS(baseAddr); -} - -/*! -* @brief Checks whether the DMA is supported. -* -* @param baseAddr SDHC base address -* @return if high speed is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportDma(uint32_t baseAddr) -{ - return BR_SDHC_HTCAPBLT_DMAS(baseAddr); -} - -/*! -* @brief Checks whether the suspend/resume is supported. -* -* @param baseAddr SDHC base address -* @return if suspend and resume is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportSuspendResume(uint32_t baseAddr) -{ - return BR_SDHC_HTCAPBLT_SRS(baseAddr); -} - -/*! -* @brief Checks whether the voltage 3.3 is supported. -* -* @param baseAddr SDHC base address -* @return if voltage 3.3 is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportV330(uint32_t baseAddr) -{ - return BR_SDHC_HTCAPBLT_VS33(baseAddr); -} - -/*! -* @brief Checks whether the voltage 3.0 is supported. -* -* @param baseAddr SDHC base address -* @return if voltage 3.0 is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportV300(uint32_t baseAddr) -{ -#if defined(FSL_FEATURE_SDHC_HAS_V300_SUPPORT) && FSL_FEATURE_SDHC_HAS_V300_SUPPORT - return BR_SDHC_HTCAPBLT_VS30(baseAddr); -#else - return 0; -#endif -} - -/*! -* @brief Checks whether the voltage 1.8 is supported. -* -* @param baseAddr SDHC base address -* @return if voltage 1.8 is supported -*/ -static inline uint32_t SDHC_HAL_DoesHostSupportV180(uint32_t baseAddr) -{ -#if defined(FSL_FEATURE_SDHC_HAS_V180_SUPPORT) && FSL_FEATURE_SDHC_HAS_V180_SUPPORT - return BR_SDHC_HTCAPBLT_VS18(baseAddr); -#else - return 0; -#endif -} - -/*! -* @brief Sets the watermark for writing. -* -* @param baseAddr SDHC base address -* @param watermark for writing -*/ -static inline void SDHC_HAL_SetWriteWatermarkLevel(uint32_t baseAddr, uint32_t watermark) -{ - BW_SDHC_WML_WRWML(baseAddr, watermark); -} - -/*! -* @brief Sets the watermark for reading. -* -* @param baseAddr SDHC base address -* @param watermark for reading -*/ -static inline void SDHC_HAL_SetReadWatermarkLevel(uint32_t baseAddr, uint32_t watermark) -{ - BW_SDHC_WML_RDWML(baseAddr, watermark); -} - -/*! -* @brief Sets the force events according to the given mask. -* -* @param baseAddr SDHC base address -* @param mask to specify the force events' flags to be set -*/ -static inline void SDHC_HAL_SetForceEventFlags(uint32_t baseAddr, uint32_t mask) -{ - HW_SDHC_FEVT_WR(baseAddr, mask); -} - -/*! -* @brief Checks whether the ADMA error is length mismatch. -* -* @param baseAddr SDHC base address -* @return if ADMA error is length mismatch -*/ -static inline uint32_t SDHC_HAL_IsAdmaLengthMismatchError(uint32_t baseAddr) -{ - return BR_SDHC_ADMAES_ADMALME(baseAddr); -} - -/*! -* @brief Checks the SD clock. -* -* Checks whether the clock to the SD is enabled. -* -* @param baseAddr SDHC base address -* @return true if enabled -*/ -static inline bool SDHC_HAL_IsSdClockOff(uint32_t baseAddr) -{ - return BR_SDHC_SYSCTL_SDCLKEN(baseAddr); -} - -/*! -* @brief Returns the state of the ADMA error. -* -* @param baseAddr SDHC base address -* @return error state -*/ -static inline uint32_t SDHC_HAL_GetAdmaErrorState(uint32_t baseAddr) -{ - return BR_SDHC_ADMAES_ADMAES(baseAddr); -} - -/*! -* @brief Checks whether the ADMA error is a descriptor error. -* -* @param baseAddr SDHC base address -* @return if ADMA error is descriptor error -*/ -static inline uint32_t SDHC_HAL_IsAdmaDescriptionError(uint32_t baseAddr) -{ - return BR_SDHC_ADMAES_ADMADCE(baseAddr); -} - -/*! -* @brief Sets the ADMA address. -* -* @param baseAddr SDHC base address -* @param address for ADMA transfer -*/ -static inline void SDHC_HAL_SetAdmaAddress(uint32_t baseAddr, uint32_t address) -{ - HW_SDHC_ADSADDR_WR(baseAddr, address); -} - -/*! -* @brief Enables the external DMA request. -* -* @param baseAddr SDHC base address -* @param enable to external DMA -*/ -static inline void SDHC_HAL_SetExternalDmaRequest(uint32_t baseAddr, bool enable) -{ - BW_SDHC_VENDOR_EXTDMAEN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables the exact block number for the SDIO CMD53. -* -* @param baseAddr SDHC base address -* @param enable to enable exact block number block read for SDIO CMD53 -*/ -static inline void SDHC_HAL_SetExactBlockNumber(uint32_t baseAddr, bool enable) -{ - BW_SDHC_VENDOR_EXBLKNU(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Sets the timeout value for the boot ACK. -* -* @param baseAddr SDHC base address -* @param timeout boot ack time out counter value -*/ -static inline void SDHC_HAL_SetBootAckTimeout(uint32_t baseAddr, uint32_t timeout) -{ - BW_SDHC_MMCBOOT_DTOCVACK(baseAddr, timeout); -} - -/*! -* @brief Enables the boot ACK. -* -* @param baseAddr SDHC base address -* @param enable to enable boot ack mode -*/ -static inline void SDHC_HAL_SetBootAck(uint32_t baseAddr, bool enable) -{ - BW_SDHC_MMCBOOT_BOOTACK(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Configures the boot mode. -* -* @param baseAddr SDHC base address -* @param mode the boot mode -*/ -static inline void SDHC_HAL_SetBootMode(uint32_t baseAddr, sdhc_hal_mmcboot_t mode) -{ - BW_SDHC_MMCBOOT_BOOTMODE(baseAddr, mode); -} - -/*! -* @brief Enables the fast boot. -* -* @param baseAddr SDHC base address -* @param enable to enable fast boot -*/ -static inline void SDHC_HAL_SetFastboot(uint32_t baseAddr, bool enable) -{ - BW_SDHC_MMCBOOT_BOOTEN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Enables the automatic stop at the block gap. -* -* @param baseAddr SDHC base address -* @param enable to enable auto stop at block gap function, when boot. -*/ -static inline void SDHC_HAL_SetAutoStopAtBlockGap(uint32_t baseAddr, bool enable) -{ - BW_SDHC_MMCBOOT_AUTOSABGEN(baseAddr, enable ? 1 : 0); -} - -/*! -* @brief Configures the the block count for the boot. -* -* @param baseAddr SDHC base address -* @param blockCount the block count for boot -*/ -static inline void SDHC_HAL_SetBootBlockCount(uint32_t baseAddr, uint32_t blockCount) -{ - BW_SDHC_MMCBOOT_BOOTBLKCNT(baseAddr, blockCount); -} - -/*! -* @brief Gets a specification version. -* -* @param baseAddr SDHC base address -* @return specification version -*/ -static inline uint32_t SDHC_HAL_GetSpecificationVersion(uint32_t baseAddr) -{ - return BR_SDHC_HOSTVER_SVN(baseAddr); -} - -/*! -* @brief Gets the vendor version. -* -* @param baseAddr SDHC base address -* @return vendor version -*/ -static inline uint32_t SDHC_HAL_GetVendorVersion(uint32_t baseAddr) -{ - return BR_SDHC_HOSTVER_VVN(baseAddr); -} - -/*! - * @brief Gets the command response. - * - * @param baseAddr SDHC base address - * @param index of response register, range from 0 to 3 - */ -uint32_t SDHC_HAL_GetResponse(uint32_t baseAddr, uint32_t index); - -/*! -* @brief Enables the specified interrupts. -* -* @param baseAddr SDHC base address -* @param enable enable or disable -* @param mask to specify interrupts to be isEnabledd -*/ -void SDHC_HAL_SetIntSignal(uint32_t baseAddr, bool enable, uint32_t mask); - -/*! -* @brief Enables the specified interrupt state. -* -* @param baseAddr SDHC base address -* @param enable enable or disable -* @param mask to specify interrupts' state to be enabled -*/ -void SDHC_HAL_SetIntState(uint32_t baseAddr, bool enable, uint32_t mask); - -/*! -* @brief Performs an SDHC reset. -* -* @param baseAddr SDHC base address -* @param type the type of reset -* @param timeout timeout for reset -* @return 0 on success, else on error -*/ -uint32_t SDHC_HAL_Reset(uint32_t baseAddr, uint32_t type, uint32_t timeout); - -/*! -* @brief Sends 80 clocks to the card to initialize the card. -* -* @param baseAddr SDHC base address -* @param timeout timeout for initialize card -* @return 0 on success, else on error -*/ -uint32_t SDHC_HAL_InitCard(uint32_t baseAddr, uint32_t timeout); - -/*! -* @brief Gets the IRQ ID for a given host controller. -* -* @param baseAddr SDHC base address -* @return IRQ number for specific SDHC instance -*/ -IRQn_Type SDHC_HAL_GetIrqId(uint32_t baseAddr); - -/*! - * @brief Initializes the SDHC HAL. - * - * @param baseAddr SDHC base address - */ -void SDHC_HAL_Init(uint32_t baseAddr); - -/*@} */ -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* MBED_NO_SDHC */ - -#endif - -/************************************************************************************************* - * EOF - ************************************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h deleted file mode 100644 index b8fa86a9e0b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h +++ /dev/null @@ -1,4222 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_SIM_FEATURES_H__) -#define __FSL_SIM_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK24FN256VDC12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (1) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (1) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (1) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (1) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (1) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (1) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (1) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (1) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (1) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (4) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (1) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (1) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (1) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (1) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (1) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (1) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (1) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (1) -#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ - defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ - defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ - defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (2) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ - defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) - /* @brief Has USB FS divider. */ - #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) - /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ - #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) - /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) - /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) - /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) - /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ - #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) - /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) - /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) - /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) - /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) - /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) - /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) - /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) - /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ - #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) - /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ - #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) - /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) - /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) - /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ - #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) - /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) - /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) - /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) - /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) - /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) - /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) - /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) - /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) - /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) - /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) - /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ - #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) - /* @brief Has FTM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) - /* @brief Number of FTM modules. */ - #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) - /* @brief Number of FTM triggers with selectable source. */ - #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) - /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) - /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) - /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) - /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) - /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) - /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) - /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) - /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) - /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) - /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ - #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) - /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) - /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ - #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) - /* @brief Has TPM module(s) configuration. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) - /* @brief The highest TPM module index. */ - #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) - /* @brief Has TPM module with index 0. */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) - /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) - /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) - /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) - /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) - /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) - /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) - /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ - #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) - /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) - /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) - /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) - /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) - /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) - /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) - /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) - /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) - /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) - /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) - /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) - /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) - /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) - /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) - /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) - /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ - #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) - /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ - #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) - /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) - /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) - /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) - /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ - #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) - /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) - /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) - /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) - /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) - /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) - /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) - /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ - #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) - /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) - /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) - /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) - /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) - /* @brief Has device die ID (register bit field SDID[DIEID]). */ - #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) - /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ - #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) - /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) - /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) - /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) - /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) - /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) - /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) - /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) - /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) - /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) - /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) - /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) - /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ - #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) - /* @brief Has miscellanious control register (register MCR). */ - #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) - /* @brief Has COP watchdog (registers COPC and SRVCOP). */ - #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) - /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ - #define FSL_FEATURE_SIM_HAS_COP_STOP (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_SIM_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c deleted file mode 100644 index 8d62949cb08..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c +++ /dev/null @@ -1,1468 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sim_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_SetSource - * Description : Set clock source setting - * This function will set the settings for specified clock source. Each clock - * source has its clock selection settings. Refer to reference manual for - * details of settings for each clock source. Refer to clock_source_names_t - * for clock sources. - * - *END**************************************************************************/ -sim_hal_status_t CLOCK_HAL_SetSource(uint32_t baseAddr, - clock_source_names_t clockSource, - uint8_t setting) -{ - sim_hal_status_t status = kSimHalSuccess; - assert(clockSource < kClockSourceMax); - - switch (clockSource) - { -#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC - case kClockNfcSrc: /* NFCSRC*/ - BW_SIM_SOPT2_NFCSRC(baseAddr, setting); - break; - case kClockNfcSel: /* NFC_CLKSEL*/ - BW_SIM_SOPT2_NFC_CLKSEL(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC - case kClockEsdhcSrc: /* ESDHCSRC*/ - BW_SIM_SOPT2_ESDHCSRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_SDHCSRC - case kClockSdhcSrc: /* SDHCSRC*/ - BW_SIM_SOPT2_SDHCSRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC - case kClockLcdcSrc: /* LCDCSRC*/ - BW_SIM_SOPT2_LCDCSRC(baseAddr, setting); - break; - case kClockLcdcSel: /* LCDC_CLKSEL*/ - BW_SIM_SOPT2_LCDC_CLKSEL(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_TIMESRC - case kClockTimeSrc: /* TIMESRC*/ - BW_SIM_SOPT2_TIMESRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_RMIISRC - case kClockRmiiSrc: /* RMIISRC*/ - BW_SIM_SOPT2_RMIISRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_USBSRC - case kClockUsbSrc: /* USBSRC*/ - BW_SIM_SOPT2_USBSRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_USBFSRC - case kClockUsbfSrc: /* USBFSRC*/ - BW_SIM_SOPT2_USBFSRC(baseAddr, setting); - break; - case kClockUsbfSel: /* USBF_CLKSEL*/ - BW_SIM_SOPT2_USBF_CLKSEL(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_USBHSRC - case kClockUsbhSrc: /* USBHSRC*/ - BW_SIM_SOPT2_USBHSRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_UART0SRC - case kClockUart0Src: /* UART0SRC*/ - BW_SIM_SOPT2_UART0SRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_TPMSRC - case kClockTpmSrc: /* TPMSRC*/ - BW_SIM_SOPT2_TPMSRC(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC - case kClockLpuartSrc: /* LPUARTSRC*/ - BW_SIM_SOPT2_LPUARTSRC(baseAddr, setting); - break; -#endif - - case kClockOsc32kSel: /* OSC32KSEL*/ - BW_SIM_SOPT1_OSC32KSEL(baseAddr, setting); - break; - - case kClockPllfllSel: /* PLLFLLSEL*/ - BW_SIM_SOPT2_PLLFLLSEL(baseAddr, setting); - break; - -#if FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL - case kClockTraceSel: /* TRACE_CLKSEL*/ - BW_SIM_SOPT2_TRACECLKSEL(baseAddr, setting); - break; -#endif - - case kClockClkoutSel: /* CLKOUTSEL*/ - BW_SIM_SOPT2_CLKOUTSEL(baseAddr, setting); - break; - -#if FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION - case kClockRtcClkoutSel: /* RTCCLKOUTSEL*/ - BW_SIM_SOPT2_RTCCLKOUTSEL(baseAddr, setting); - break; -#endif - - default: - status = kSimHalNoSuchClockSrc; - break; - } - - return status; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetSource - * Description : Get clock source setting - * This function will get the settings for specified clock source. Each clock - * source has its clock selection settings. Refer to reference manual for - * details of settings for each clock source. Refer to clock_source_names_t - * for clock sources. - * - *END**************************************************************************/ -sim_hal_status_t CLOCK_HAL_GetSource(uint32_t baseAddr, - clock_source_names_t clockSource, - uint8_t *setting) -{ - sim_hal_status_t status = kSimHalSuccess; - assert(clockSource < kClockSourceMax); - - switch (clockSource) - { -#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC - case kClockNfcSrc: /* NFCSRC*/ - *setting = BR_SIM_SOPT2_NFCSRC(baseAddr); - break; - case kClockNfcSel: /* NFC_CLKSEL*/ - *setting = BR_SIM_SOPT2_NFC_CLKSEL(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC - case kClockEsdhcSrc: /* ESDHCSRC*/ - *setting = BR_SIM_SOPT2_ESDHCSRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_SDHCSRC - case kClockSdhcSrc: /* SDHCSRC*/ - *setting = BR_SIM_SOPT2_SDHCSRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC - case kClockLcdcSrc: /* LCDCSRC*/ - *setting = BR_SIM_SOPT2_LCDCSRC(baseAddr); - break; - case kClockLcdcSel: /* LCDC_CLKSEL*/ - *setting = BR_SIM_SOPT2_LCDC_CLKSEL(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_TIMESRC - case kClockTimeSrc: /* TIMESRC*/ - *setting = BR_SIM_SOPT2_TIMESRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_RMIISRC - case kClockRmiiSrc: /* RMIISRC*/ - *setting = BR_SIM_SOPT2_RMIISRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_USBSRC - case kClockUsbSrc: /* USBSRC*/ - *setting = BR_SIM_SOPT2_USBSRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_USBFSRC - case kClockUsbfSrc: /* USBFSRC*/ - *setting = BR_SIM_SOPT2_USBFSRC(baseAddr); - break; - case kClockUsbfSel: /* USBF_CLKSEL*/ - *setting = BR_SIM_SOPT2_USBF_CLKSEL(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_USBHSRC - case kClockUsbhSrc: /* USBHSRC*/ - *setting = BR_SIM_SOPT2_USBHSRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_UART0SRC - case kClockUart0Src: /* UART0SRC*/ - *setting = BR_SIM_SOPT2_UART0SRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_TPMSRC - case kClockTpmSrc: /* TPMSRC*/ - *setting = BR_SIM_SOPT2_TPMSRC(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC - case kClockLpuartSrc: /* LPUARTSRC*/ - *setting = BR_SIM_SOPT2_LPUARTSRC(baseAddr); - break; -#endif - - case kClockOsc32kSel: /* OSC32KSEL*/ - *setting = BR_SIM_SOPT1_OSC32KSEL(baseAddr); - break; - - case kClockPllfllSel: /* PLLFLLSEL*/ - *setting = BR_SIM_SOPT2_PLLFLLSEL(baseAddr); - break; - -#if FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL - case kClockTraceSel: /* TRACE_CLKSEL*/ - *setting = BR_SIM_SOPT2_TRACECLKSEL(baseAddr); - break; -#endif - - case kClockClkoutSel: /* CLKOUTSEL */ - *setting = BR_SIM_SOPT2_CLKOUTSEL(baseAddr); - break; - -#if FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION - case kClockRtcClkoutSel: /* RTCCLKOUTSEL */ - *setting = BR_SIM_SOPT2_RTCCLKOUTSEL(baseAddr); - break; -#endif - - default: - status = kSimHalNoSuchClockSrc; - break; - } - - return status; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_SetDivider - * Description : Set clock divider setting - * This function will set the setting for specified clock divider. Refer to - * reference manual for supported clock divider and value range. Refer to - * clock_divider_names_t for dividers. - * - *END**************************************************************************/ -sim_hal_status_t CLOCK_HAL_SetDivider(uint32_t baseAddr, - clock_divider_names_t clockDivider, - uint32_t setting) -{ - sim_hal_status_t status = kSimHalSuccess; - assert(clockDivider < kClockDividerMax); - - switch (clockDivider) - { - case kClockDividerOutdiv1: /* OUTDIV1*/ - BW_SIM_CLKDIV1_OUTDIV1(baseAddr, setting); - break; - -#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 - case kClockDividerOutdiv2: /* OUTDIV2*/ - BW_SIM_CLKDIV1_OUTDIV2(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 - case kClockDividerOutdiv3: /* OUTDIV3*/ - BW_SIM_CLKDIV1_OUTDIV3(baseAddr, setting); - break; -#endif - - case kClockDividerOutdiv4: /* OUTDIV4*/ - BW_SIM_CLKDIV1_OUTDIV4(baseAddr, setting); - break; - -#if FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV - case kClockDividerUsbFrac: /* USBFRAC*/ - BW_SIM_CLKDIV2_USBFRAC(baseAddr, setting); - break; - case kClockDividerUsbDiv: /* USBDIV*/ - BW_SIM_CLKDIV2_USBDIV(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV - case kClockDividerUsbfsFrac: /* USBFSFRAC*/ - BW_SIM_CLKDIV2_USBFSFRAC(baseAddr, setting); - break; - case kClockDividerUsbfsDiv: /* USBFSDIV*/ - BW_SIM_CLKDIV2_USBFSDIV(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV - case kClockDividerUsbhsFrac: /* USBHSFRAC*/ - BW_SIM_CLKDIV2_USBHSFRAC(baseAddr, setting); - break; - case kClockDividerUsbhsDiv: /* USBHSDIV*/ - BW_SIM_CLKDIV2_USBHSDIV(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC - case kClockDividerLcdcFrac: /* LCDCFRAC*/ - BW_SIM_CLKDIV3_LCDCFRAC(baseAddr, setting); - break; - case kClockDividerLcdcDiv: /* LCDCDIV*/ - BW_SIM_CLKDIV3_LCDCDIV(baseAddr, setting); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC - case kClockDividerNfcFrac: /* NFCFRAC*/ - BW_SIM_CLKDIV4_NFCFRAC(baseAddr, setting); - break; - case kClockDividerNfcDiv: /* NFCDIV*/ - BW_SIM_CLKDIV4_NFCDIV(baseAddr, setting); - break; -#endif - - case kClockDividerSpecial1: /* special divider 1 */ - break; - - default: - status = kSimHalNoSuchDivider; - break; - } - - return status; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_SetOutDividers - * Description : Set all clock out dividers setting at the same time - * This function will set the setting for all clock out dividers. Refer to - * reference manual for supported clock divider and value range. Refer to - * clock_divider_names_t for dividers. - * - *END**************************************************************************/ -void CLOCK_HAL_SetOutDividers(uint32_t baseAddr, uint32_t outdiv1, uint32_t outdiv2, - uint32_t outdiv3, uint32_t outdiv4) -{ - uint32_t clkdiv1 = 0; - - clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV1(outdiv1); -#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 - clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV2(outdiv2); -#endif -#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 - clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV3(outdiv3); -#endif - clkdiv1 |= BF_SIM_CLKDIV1_OUTDIV4(outdiv4); - - HW_SIM_CLKDIV1_WR(baseAddr, clkdiv1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_HAL_GetDivider - * Description : Get clock divider setting - * This function will get the setting for specified clock divider. Refer to - * reference manual for supported clock divider and value range. Refer to - * clock_divider_names_t for dividers. - * - *END**************************************************************************/ -sim_hal_status_t CLOCK_HAL_GetDivider(uint32_t baseAddr, - clock_divider_names_t clockDivider, - uint32_t *setting) -{ - sim_hal_status_t status = kSimHalSuccess; - assert(clockDivider < kClockDividerMax); - - *setting = 0; - - switch (clockDivider) - { - case kClockDividerOutdiv1: /* OUTDIV1*/ - *setting = BR_SIM_CLKDIV1_OUTDIV1(baseAddr); - break; - -#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 - case kClockDividerOutdiv2: /* OUTDIV2*/ - *setting = BR_SIM_CLKDIV1_OUTDIV2(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 - case kClockDividerOutdiv3: /* OUTDIV3*/ - *setting = BR_SIM_CLKDIV1_OUTDIV3(baseAddr); - break; -#endif - - case kClockDividerOutdiv4: /* OUTDIV4*/ - *setting = BR_SIM_CLKDIV1_OUTDIV4(baseAddr); - break; - -#if FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV - case kClockDividerUsbFrac: /* USBFRAC*/ - *setting = BR_SIM_CLKDIV2_USBFRAC(baseAddr); - break; - case kClockDividerUsbDiv: /* USBDIV*/ - *setting = BR_SIM_CLKDIV2_USBDIV(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV - case kClockDividerUsbfsFrac: /* USBFSFRAC*/ - *setting = BR_SIM_CLKDIV2_USBFSFRAC(baseAddr); - break; - case kClockDividerUsbfsDiv: /* USBFSDIV*/ - *setting = BR_SIM_CLKDIV2_USBFSDIV(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV - case kClockDividerUsbhsFrac: /* USBHSFRAC*/ - *setting = BR_SIM_CLKDIV2_USBHSFRAC(baseAddr); - break; - case kClockDividerUsbhsDiv: /* USBHSDIV*/ - *setting = BR_SIM_CLKDIV2_USBHSDIV(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_LCDCSRC - case kClockDividerLcdcFrac: /* LCDCFRAC*/ - *setting = BR_SIM_CLKDIV3_LCDCFRAC(baseAddr); - break; - case kClockDividerLcdcDiv: /* LCDCDIV*/ - *setting = BR_SIM_CLKDIV3_LCDCDIV(baseAddr); - break; -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_NFCSRC - case kClockDividerNfcFrac: /* NFCFRAC*/ - *setting = BR_SIM_CLKDIV4_NFCFRAC(baseAddr); - break; - case kClockDividerNfcDiv: /* NFCDIV*/ - *setting = BR_SIM_CLKDIV4_NFCDIV(baseAddr); - break; -#endif - - case kClockDividerSpecial1: /* special divider 1 */ - *setting = 1; - break; - - default: - status = kSimHalNoSuchDivider; - break; - } - - return status; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetAdcAlternativeTriggerCmd - * Description : Set ADCx alternate trigger enable setting - * This function will enable/disable alternative conversion triggers for ADCx. - * - *END**************************************************************************/ -void SIM_HAL_SetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance, bool enable) -{ - assert(instance < HW_ADC_INSTANCE_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT7_ADC0ALTTRGEN(baseAddr, enable ? 1 : 0); - break; -#if (HW_ADC_INSTANCE_COUNT > 1) - case 1: - BW_SIM_SOPT7_ADC1ALTTRGEN(baseAddr, enable ? 1 : 0); - break; -#if (HW_ADC_INSTANCE_COUNT > 2) - case 2: - BW_SIM_SOPT7_ADC2ALTTRGEN(baseAddr, enable ? 1 : 0); - break; - case 3: - BW_SIM_SOPT7_ADC3ALTTRGEN(baseAddr, enable ? 1 : 0); - break; -#endif -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetAdcAlternativeTriggerCmd - * Description : Get ADCx alternate trigger enable settingg - * This function will get ADCx alternate trigger enable setting. - * - *END**************************************************************************/ -bool SIM_HAL_GetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance) -{ - bool retValue = false; - - assert(instance < HW_ADC_INSTANCE_COUNT); - - switch (instance) - { - case 0: - retValue = BR_SIM_SOPT7_ADC0ALTTRGEN(baseAddr); - break; -#if (HW_ADC_INSTANCE_COUNT > 1) - case 1: - retValue = BR_SIM_SOPT7_ADC1ALTTRGEN(baseAddr); - break; -#if (HW_ADC_INSTANCE_COUNT > 2) - case 2: - retValue = BR_SIM_SOPT7_ADC2ALTTRGEN(baseAddr); - break; - case 3: - retValue = BR_SIM_SOPT7_ADC3ALTTRGEN(baseAddr); - break; -#endif -#endif - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetAdcPreTriggerMode - * Description : Set ADCx pre-trigger select setting - * This function will select the ADCx pre-trigger source when alternative - * triggers are enabled through ADCxALTTRGEN - * - *END**************************************************************************/ -void SIM_HAL_SetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance, sim_pretrgsel_t select) -{ - assert(instance < HW_ADC_INSTANCE_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT7_ADC0PRETRGSEL(baseAddr, select); - break; -#if (HW_ADC_INSTANCE_COUNT > 1) - case 1: - BW_SIM_SOPT7_ADC1PRETRGSEL(baseAddr, select); - break; -#if (HW_ADC_INSTANCE_COUNT > 2) - case 2: - BW_SIM_SOPT7_ADC2PRETRGSEL(baseAddr, select); - break; - case 3: - BW_SIM_SOPT7_ADC3PRETRGSEL(baseAddr, select); - break; -#endif -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetAdcPreTriggerMode - * Description : Get ADCx pre-trigger select setting - * This function will get ADCx pre-trigger select setting. - * - *END**************************************************************************/ -sim_pretrgsel_t SIM_HAL_GetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance) -{ - sim_pretrgsel_t retValue = (sim_pretrgsel_t)0; - - assert(instance < HW_ADC_INSTANCE_COUNT); - - switch (instance) - { - case 0: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC0PRETRGSEL(baseAddr); - break; -#if (HW_ADC_INSTANCE_COUNT > 1) - case 1: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC1PRETRGSEL(baseAddr); - break; -#if (HW_ADC_INSTANCE_COUNT > 2) - case 2: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC2PRETRGSEL(baseAddr); - break; - case 3: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC3PRETRGSEL(baseAddr); - break; -#endif -#endif - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetAdcTriggerMode - * Description : Set ADCx trigger select setting - * This function will select the ADCx trigger source when alternative triggers - * are enabled through ADCxALTTRGEN - * - *END**************************************************************************/ -void SIM_HAL_SetAdcTriggerMode(uint32_t baseAddr, uint8_t instance, sim_trgsel_t select) -{ - assert(instance < HW_ADC_INSTANCE_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT7_ADC0TRGSEL(baseAddr, select); - break; -#if (HW_ADC_INSTANCE_COUNT > 1) - case 1: - BW_SIM_SOPT7_ADC1TRGSEL(baseAddr, select); - break; -#if (HW_ADC_INSTANCE_COUNT > 2) - case 2: - BW_SIM_SOPT7_ADC2TRGSEL(baseAddr, select); - break; - case 3: - BW_SIM_SOPT7_ADC3TRGSEL(baseAddr, select); - break; -#endif -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetAdcTriggerMode - * Description : Get ADCx trigger select setting - * This function will get ADCx trigger select setting. - * - *END**************************************************************************/ -sim_pretrgsel_t SIM_HAL_GetAdcTriggerMode(uint32_t baseAddr, uint8_t instance) -{ - sim_pretrgsel_t retValue =(sim_pretrgsel_t)0; - - assert(instance < HW_ADC_INSTANCE_COUNT); - - switch (instance) - { - case 0: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC0TRGSEL(baseAddr); - break; -#if (HW_ADC_INSTANCE_COUNT > 1) - case 1: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC1TRGSEL(baseAddr); - break; -#if (HW_ADC_INSTANCE_COUNT > 2) - case 2: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC2TRGSEL(baseAddr); - break; - case 3: - retValue = (sim_pretrgsel_t)BR_SIM_SOPT7_ADC3TRGSEL(baseAddr); - break; -#endif -#endif - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetUartRxSrcMode - * Description : Set UARTx receive data source select setting - * This function will select the source for the UART1 receive data. - * - *END**************************************************************************/ -void SIM_HAL_SetUartRxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_rxsrc_t select) -{ - assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT5_UART0RXSRC(baseAddr, select); - break; - case 1: - BW_SIM_SOPT5_UART1RXSRC(baseAddr, select); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetAdcPreTriggerMode - * Description : Get UARTx receive data source select setting - * This function will get UARTx receive data source select setting. - * - *END**************************************************************************/ -sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(uint32_t baseAddr, uint8_t instance) -{ - sim_uart_rxsrc_t retValue = (sim_uart_rxsrc_t)0; - - assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT); - - switch (instance) - { - case 0: - retValue = (sim_uart_rxsrc_t)BR_SIM_SOPT5_UART0RXSRC(baseAddr); - break; - case 1: - retValue = (sim_uart_rxsrc_t)BR_SIM_SOPT5_UART1RXSRC(baseAddr); - break; - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetUartTxSrcMode - * Description : Set UARTx transmit data source select setting - * This function will select the source for the UARTx transmit data. - * - *END**************************************************************************/ -void SIM_HAL_SetUartTxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_txsrc_t select) -{ - assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT5_UART0TXSRC(baseAddr, select); - break; - case 1: - BW_SIM_SOPT5_UART1TXSRC(baseAddr, select); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUartTxSrcMode - * Description : Get UARTx transmit data source select setting - * This function will get UARTx transmit data source select setting. - * - *END**************************************************************************/ -sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(uint32_t baseAddr, uint8_t instance) -{ - sim_uart_txsrc_t retValue =(sim_uart_txsrc_t)0; - - assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT); - - switch (instance) - { - case 0: - retValue = (sim_uart_txsrc_t)BR_SIM_SOPT5_UART0TXSRC(baseAddr); - break; - case 1: - retValue = (sim_uart_txsrc_t)BR_SIM_SOPT5_UART1TXSRC(baseAddr); - break; - default: - break; - } - - return retValue; -} - -#if FSL_FEATURE_SIM_OPT_HAS_ODE -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetUartOpenDrainCmd - * Description : Set UARTx Open Drain Enable setting - * This function will enable/disable the UARTx Open Drain. - * - *END**************************************************************************/ -void SIM_HAL_SetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance, bool enable) -{ - assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT5_UART0ODE(baseAddr, enable ? 1 : 0); - break; - case 1: - BW_SIM_SOPT5_UART1ODE(baseAddr, enable ? 1 : 0); - break; - case 2: - BW_SIM_SOPT5_UART2ODE(baseAddr, enable ? 1 : 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUartOpenDrainCmd - * Description : Get UARTx Open Drain Enable setting - * This function will get UARTx Open Drain Enable setting. - * - *END**************************************************************************/ -bool SIM_HAL_GetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance) -{ - bool retValue = false; - - assert(instance < FSL_FEATURE_SIM_OPT_UART_COUNT); - - switch (instance) - { - case 0: - retValue = BR_SIM_SOPT5_UART0ODE(baseAddr); - break; - case 1: - retValue = BR_SIM_SOPT5_UART1ODE(baseAddr); - break; - case 2: - retValue = BR_SIM_SOPT5_UART2ODE(baseAddr); - break; - default: - break; - } - - return retValue; -} -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_FTM -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetFtmTriggerSrcMode - * Description : Set FlexTimer x hardware trigger y source select setting - * This function will select the source of FTMx hardware trigger y. - * - *END**************************************************************************/ -void SIM_HAL_SetFtmTriggerSrcMode(uint32_t baseAddr, - uint8_t instance, - uint8_t trigger, - sim_ftm_trg_src_t select) -{ - assert (instance < HW_FTM_INSTANCE_COUNT); - assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT); - - switch (instance) - { -#if FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER - case 0: - switch (trigger) - { - case 0: - BW_SIM_SOPT4_FTM0TRG0SRC(baseAddr, select); - break; - case 1: - BW_SIM_SOPT4_FTM0TRG1SRC(baseAddr, select); - break; - default: - break; - } - break; -#endif -#if FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER - case 3: - switch (trigger) - { - case 0: - BW_SIM_SOPT4_FTM3TRG0SRC(baseAddr, select); - break; - case 1: - BW_SIM_SOPT4_FTM3TRG1SRC(baseAddr, select); - break; - default: - break; - } - break; -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtmTriggerSrcMode - * Description : Get FlexTimer x hardware trigger y source select setting - * This function will get FlexTimer x hardware trigger y source select setting. - * - *END**************************************************************************/ -sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t trigger) -{ - sim_ftm_trg_src_t retValue = (sim_ftm_trg_src_t)0; - - assert (instance < HW_FTM_INSTANCE_COUNT); - assert (trigger < FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT); - - switch (instance) - { -#if FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER - case 0: - switch (trigger) - { - case 0: - retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM0TRG0SRC(baseAddr); - break; - case 1: - retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM0TRG1SRC(baseAddr); - break; - default: - break; - } - break; -#endif -#if FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER - case 3: - switch (trigger) - { - case 0: - retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM3TRG0SRC(baseAddr); - break; - case 1: - retValue = (sim_ftm_trg_src_t)BR_SIM_SOPT4_FTM3TRG1SRC(baseAddr); - break; - default: - break; - } - break; -#endif - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetFtmExternalClkPinMode - * Description : Set FlexTimer x external clock pin select setting - * This function will select the source of FTMx external clock pin select - * - *END**************************************************************************/ -void SIM_HAL_SetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance, sim_ftm_clk_sel_t select) -{ - assert (instance < HW_FTM_INSTANCE_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT4_FTM0CLKSEL(baseAddr, select); - break; - case 1: - BW_SIM_SOPT4_FTM1CLKSEL(baseAddr, select); - break; - case 2: - BW_SIM_SOPT4_FTM2CLKSEL(baseAddr, select); - break; -#if (HW_FTM_INSTANCE_COUNT > 3) - case 3: - BW_SIM_SOPT4_FTM3CLKSEL(baseAddr, select); - break; -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtmExternalClkPinMode - * Description : Get FlexTimer x external clock pin select setting - * This function will get FlexTimer x external clock pin select setting. - * - *END**************************************************************************/ -sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance) -{ - sim_ftm_clk_sel_t retValue = (sim_ftm_clk_sel_t)0; - - assert (instance < HW_FTM_INSTANCE_COUNT); - - switch (instance) - { - case 0: - retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM0CLKSEL(baseAddr); - break; - case 1: - retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM1CLKSEL(baseAddr); - break; - case 2: - retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM2CLKSEL(baseAddr); - break; -#if (HW_FTM_INSTANCE_COUNT > 3) - case 3: - retValue = (sim_ftm_clk_sel_t)BR_SIM_SOPT4_FTM3CLKSEL(baseAddr); - break; -#endif - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetFtmChSrcMode - * Description : FlexTimer x channel y input capture source select setting - * This function will select FlexTimer x channel y input capture source - * - *END**************************************************************************/ -void SIM_HAL_SetFtmChSrcMode(uint32_t baseAddr, - uint8_t instance, - uint8_t channel, - sim_ftm_ch_src_t select) -{ - assert (instance < HW_FTM_INSTANCE_COUNT); - - switch (instance) - { -#if FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS - case 1: - switch (channel) - { - case 0: - BW_SIM_SOPT4_FTM1CH0SRC(baseAddr, select); - break; - default: - break; - } - break; -#endif -#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS - case 2: - switch (channel) - { - case 0: - BW_SIM_SOPT4_FTM2CH0SRC(baseAddr, select); - break; -#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 - case 1: - BW_SIM_SOPT4_FTM2CH1SRC(baseAddr, select); - break; -#endif - default: - break; - } - break; -#endif -#if FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS - case 3: - switch (channel) - { - case 0: - BW_SIM_SOPT4_FTM3CH0SRC(baseAddr, select); - break; - default: - break; - } - break; -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtmChSrcMode - * Description : Get FlexTimer x channel y input capture source select setting - * This function will get FlexTimer x channel y input capture source select - * setting. - * - *END**************************************************************************/ -sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel) -{ - sim_ftm_ch_src_t retValue = (sim_ftm_ch_src_t)0; - - assert (instance < HW_FTM_INSTANCE_COUNT); - - switch (instance) - { -#if FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS - case 1: - switch (channel) - { - case 0: - retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM1CH0SRC(baseAddr); - break; - default: - break; - } - break; -#endif -#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS - case 2: - switch (channel) - { - case 0: - retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM2CH0SRC(baseAddr); - break; -#if FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 - case 1: - retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM2CH1SRC(baseAddr); - break; -#endif - default: - break; - } - break; -#endif -#if FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS - case 3: - switch (channel) - { - case 0: - retValue = (sim_ftm_ch_src_t)BR_SIM_SOPT4_FTM3CH0SRC(baseAddr); - break; - default: - break; - } - break; -#endif - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetFtmFaultSelMode - * Description : Set FlexTimer x fault y select setting - * This function will set the FlexTimer x fault y select setting. - * - *END**************************************************************************/ -void SIM_HAL_SetFtmFaultSelMode(uint32_t baseAddr, - uint8_t instance, - uint8_t fault, - sim_ftm_flt_sel_t select) -{ - assert (instance < HW_FTM_INSTANCE_COUNT); - - switch (instance) - { - case 0: - switch (fault) - { - case 0: - BW_SIM_SOPT4_FTM0FLT0(baseAddr, select); - break; - case 1: - BW_SIM_SOPT4_FTM0FLT1(baseAddr, select); - break; -#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 2) - case 2: - BW_SIM_SOPT4_FTM0FLT2(baseAddr, select); - break; -#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 3) - case 3: - BW_SIM_SOPT4_FTM0FLT3(baseAddr, select); - break; -#endif -#endif - default: - break; - } - break; - case 1: - BW_SIM_SOPT4_FTM1FLT0(baseAddr, select); - break; - case 2: - BW_SIM_SOPT4_FTM2FLT0(baseAddr, select); - break; -#if (HW_FTM_INSTANCE_COUNT > 3) - case 3: - BW_SIM_SOPT4_FTM3FLT0(baseAddr, select); - break; -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtmFaultSelMode - * Description : Get FlexTimer x fault y select setting - * This function will get FlexTimer x fault y select setting. - * - *END**************************************************************************/ -sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault) -{ - sim_ftm_flt_sel_t retValue = (sim_ftm_flt_sel_t)0; - - assert (instance < HW_FTM_INSTANCE_COUNT); - - switch (instance) - { - case 0: - switch (fault) - { - case 0: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT0(baseAddr); - break; - case 1: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT1(baseAddr); - break; -#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 2) - case 2: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT2(baseAddr); - break; -#if (FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT > 3) - case 3: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM0FLT3(baseAddr); - break; -#endif -#endif - default: - break; - } - break; - case 1: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM1FLT0(baseAddr); - break; - case 2: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM2FLT0(baseAddr); - break; -#if (HW_FTM_INSTANCE_COUNT > 3) - case 3: - retValue = (sim_ftm_flt_sel_t)BR_SIM_SOPT4_FTM3FLT0(baseAddr); - break; -#endif - default: - break; - } - - return retValue; -} -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_TPM -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetTpmExternalClkPinSelMode - * Description : Set Timer/PWM x external clock pin select setting - * This function will select the source of Timer/PWM x external clock pin select - * - *END**************************************************************************/ -void SIM_HAL_SetTpmExternalClkPinSelMode(uint32_t baseAddr, - uint8_t instance, - sim_tpm_clk_sel_t select) -{ - assert (instance < HW_TPM_INSTANCE_COUNT); - - switch (instance) - { - case 0: - BW_SIM_SOPT4_TPM0CLKSEL(baseAddr, select); - break; - case 1: - BW_SIM_SOPT4_TPM1CLKSEL(baseAddr, select); - break; - case 2: - BW_SIM_SOPT4_TPM2CLKSEL(baseAddr, select); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetTpmExternalClkPinSelMode - * Description : Get Timer/PWM x external clock pin select setting - * This function will get Timer/PWM x external clock pin select setting. - * - *END**************************************************************************/ -sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance) -{ - sim_tpm_clk_sel_t retValue = (sim_tpm_clk_sel_t)0; - - assert (instance < HW_TPM_INSTANCE_COUNT); - - switch (instance) - { - case 0: - retValue = (sim_tpm_clk_sel_t)BR_SIM_SOPT4_TPM0CLKSEL(baseAddr); - break; - case 1: - retValue = (sim_tpm_clk_sel_t)BR_SIM_SOPT4_TPM1CLKSEL(baseAddr); - break; - case 2: - retValue = (sim_tpm_clk_sel_t)BR_SIM_SOPT4_TPM2CLKSEL(baseAddr); - break; - default: - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_SetTpmChSrcMode - * Description : Timer/PWM x channel y input capture source select setting - * This function will select Timer/PWM x channel y input capture source - * - *END**************************************************************************/ -void SIM_HAL_SetTpmChSrcMode(uint32_t baseAddr, - uint8_t instance, - uint8_t channel, - sim_tpm_ch_src_t select) -{ - assert (instance < HW_TPM_INSTANCE_COUNT); - - switch (instance) - { - case 1: - switch (channel) - { - case 0: - BW_SIM_SOPT4_TPM1CH0SRC(baseAddr, select); - break; - default: - break; - } - break; - case 2: - switch (channel) - { - case 0: - BW_SIM_SOPT4_TPM2CH0SRC(baseAddr, select); - break; - default: - break; - } - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetTpmChSrcMode - * Description : Get Timer/PWM x channel y input capture source select setting - * This function will get Timer/PWM x channel y input capture source select - * setting. - * - *END**************************************************************************/ -sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(uint32_t baseAddr, - uint8_t instance, - uint8_t channel) -{ - sim_tpm_ch_src_t retValue = (sim_tpm_ch_src_t)0; - - assert (instance < HW_TPM_INSTANCE_COUNT); - - switch (instance) - { - case 1: - switch (channel) - { - case 0: - retValue = (sim_tpm_ch_src_t)BR_SIM_SOPT4_TPM1CH0SRC(baseAddr); - break; - default: - break; - } - break; - case 2: - switch (channel) - { - case 0: - retValue = (sim_tpm_ch_src_t)BR_SIM_SOPT4_TPM2CH0SRC(baseAddr); - break; - default: - break; - } - break; - default: - break; - } - - return retValue; -} -#endif - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h deleted file mode 100644 index e2b6d708d70..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h +++ /dev/null @@ -1,1620 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_SIM_HAL_H__) -#define __FSL_SIM_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sim_features.h" - -/*! @addtogroup sim_hal*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -typedef enum _clock_names { - - /* default clocks*/ - kCoreClock, /**/ - kSystemClock, /**/ - kPlatformClock, /**/ - kBusClock, /**/ - kFlexBusClock, /**/ - kFlashClock, /**/ - - /* other internal clocks used by peripherals*/ - /* osc clock*/ - kOsc32kClock, - kOsc0ErClock, - kOsc1ErClock, - - /* irc 48Mhz clock */ - kIrc48mClock, - - /* rtc clock*/ - kRtc32kClock, - kRtc1hzClock, - - /* lpo clcok*/ - kLpoClock, - - /* mcg clocks*/ - kMcgFfClock, - kMcgFllClock, - kMcgPll0Clock, - kMcgPll1Clock, - kMcgOutClock, - kMcgIrClock, - - /* constant clocks (provided in other header files?)*/ - kSDHC0_CLKIN, - kENET_1588_CLKIN, - kEXTAL_Clock, - kEXTAL1_Clock, - kUSB_CLKIN, - - /* reserved value*/ - kReserved, - - kClockNameCount -} clock_names_t; - -/*! @brief Clock source and sel names */ -typedef enum _clock_source_names { - kClockNfcSrc, /* NFCSRC*/ - kClockEsdhcSrc, /* ESDHCSRC K70*/ - kClockSdhcSrc, /* SDHCSRC K64*/ - kClockLcdcSrc, /* LCDCSRC*/ - kClockTimeSrc, /* TIMESRC*/ - kClockRmiiSrc, /* RMIISRC*/ - kClockUsbfSrc, /* USBFSRC K70*/ - kClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/ - kClockUsbhSrc, /* USBHSRC*/ - kClockUart0Src, /* UART0SRC*/ - kClockLpuartSrc, /* LPUARTSRC K22, KV31 */ - kClockTpmSrc, /* TPMSRC*/ - kClockOsc32kSel, /* OSC32KSEL*/ - kClockUsbfSel, /* USBF_CLKSEL*/ - kClockPllfllSel, /* PLLFLLSEL*/ - kClockNfcSel, /* NFC_CLKSEL*/ - kClockLcdcSel, /* LCDC_CLKSEL*/ - kClockTraceSel, /* TRACE_CLKSEL*/ - kClockClkoutSel, /* CLKOUTSEL*/ - kClockRtcClkoutSel, /* RTCCLKOUTSEL */ - kClockSourceMax -} clock_source_names_t; - -/*! @brief Clock Divider names*/ -typedef enum _clock_divider_names { - kClockDividerOutdiv1, /* OUTDIV1*/ - kClockDividerOutdiv2, /* OUTDIV2*/ - kClockDividerOutdiv3, /* OUTDIV3*/ - kClockDividerOutdiv4, /* OUTDIV4*/ - kClockDividerUsbFrac, /* (USBFRAC + 1) / (USBDIV + 1)*/ - kClockDividerUsbDiv, - kClockDividerUsbfsFrac, /* (USBFSFRAC + 1) / (USBFSDIV) + 1)*/ - kClockDividerUsbfsDiv, - kClockDividerUsbhsFrac, /* (USBHSFRAC + 1) / (USBHSDIV + 1)*/ - kClockDividerUsbhsDiv, - kClockDividerLcdcFrac, /* (LCDCFRAC + 1) / (LCDCDIV + 1)*/ - kClockDividerLcdcDiv, - kClockDividerNfcFrac, /* (NFCFRAC + 1) / (NFCDIV + 1)*/ - kClockDividerNfcDiv, - kClockDividerSpecial1, /* special divider 1*/ - kClockDividerMax -} clock_divider_names_t; - -/*! @brief SIM USB voltage regulator in standby mode setting during stop modes */ -typedef enum _sim_usbsstby_stop -{ - kSimUsbsstbyNoRegulator, /* regulator not in standby during Stop modes */ - kSimUsbsstbyWithRegulator /* regulator in standby during Stop modes */ -} sim_usbsstby_stop_t; - -/*! @brief SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes */ -typedef enum _sim_usbvstby_stop -{ - kSimUsbvstbyNoRegulator, /* regulator not in standby during VLPR and VLPW modes */ - kSimUsbvstbyWithRegulator /* regulator in standby during VLPR and VLPW modes */ -} sim_usbvstby_stop_t; - -/*! @brief SIM CMT/UART pad drive strength */ -typedef enum _sim_cmtuartpad_strengh -{ - kSimCmtuartSinglePad, /* Single-pad drive strength for CMT IRO or UART0_TXD */ - kSimCmtuartDualPad /* Dual-pad drive strength for CMT IRO or UART0_TXD */ -} sim_cmtuartpad_strengh_t; - -/*! @brief SIM PTD7 pad drive strength */ -typedef enum _sim_ptd7pad_strengh -{ - kSimPtd7padSinglePad, /* Single-pad drive strength for PTD7 */ - kSimPtd7padDualPad /* Dual-pad drive strength for PTD7 */ -} sim_ptd7pad_strengh_t; - -/*! @brief SIM FlexBus security level */ -typedef enum _sim_flexbus_security_level -{ - kSimFbslLevel0, /* All off-chip accesses (op code and data) via the FlexBus */ - /* and DDR controller are disallowed */ - kSimFbslLevel1, /* Undefined */ - kSimFbslLevel2, /* Off-chip op code accesses are disallowed. Data accesses */ - /* are allowed */ - kSimFbslLevel3 /* Off-chip op code accesses and data accesses are allowed */ -} sim_flexbus_security_level_t; - -/*! @brief SIM ADCx pre-trigger select */ -typedef enum _sim_pretrgsel -{ - kSimAdcPretrgselA, /* Pre-trigger A selected for ADCx */ - kSimAdcPretrgselB /* Pre-trigger B selected for ADCx */ -} sim_pretrgsel_t; - -/*! @brief SIM ADCx trigger select */ -typedef enum _sim_trgsel -{ - kSimAdcTrgselExt, /* External trigger */ - kSimAdcTrgSelHighSpeedComp0, /* High speed comparator 0 asynchronous interrupt */ - kSimAdcTrgSelHighSpeedComp1, /* High speed comparator 1 asynchronous interrupt */ - kSimAdcTrgSelHighSpeedComp2, /* High speed comparator 2 asynchronous interrupt */ - kSimAdcTrgSelPit0, /* PIT trigger 0 */ - kSimAdcTrgSelPit1, /* PIT trigger 1 */ - kSimAdcTrgSelPit2, /* PIT trigger 2 */ - kSimAdcTrgSelPit3, /* PIT trigger 3 */ - kSimAdcTrgSelFtm0, /* FTM0 trigger */ - kSimAdcTrgSelFtm1, /* FTM1 trigger */ - kSimAdcTrgSelFtm2, /* FTM2 trigger */ - kSimAdcTrgSelFtm3, /* FTM3 trigger */ - kSimAdcTrgSelRtcAlarm, /* RTC alarm */ - kSimAdcTrgSelRtcSec, /* RTC seconds */ - kSimAdcTrgSelLptimer, /* Low-power timer trigger */ - kSimAdcTrgSelHigSpeedComp3 /* High speed comparator 3 asynchronous interrupt */ -} sim_trgsel_t; - -/*! @brief SIM receive data source select */ -typedef enum _sim_uart_rxsrc -{ - kSimUartRxsrcPin, /* UARTx_RX Pin */ - kSimUartRxsrcCmp0, /* CMP0 */ - kSimUartRxsrcCmp1, /* CMP1 */ - kSimUartRxsrcReserved /* Reserved */ -} sim_uart_rxsrc_t; - -/*! @brief SIM transmit data source select */ -typedef enum _sim_uart_txsrc -{ - kSimUartTxsrcPin, /* UARTx_TX Pin */ - kSimUartTxsrcCmp0, /* UARTx_TX pin modulated with FTM1 channel 0 output */ - kSimUartTxsrcCmp1, /* UARTx_TX pin modulated with FTM2 channel 0 output */ - kSimUartTxsrcReserved /* Reserved */ -} sim_uart_txsrc_t; - -/*! @brief SIM FlexTimer x trigger y select */ -typedef enum _sim_ftm_trg_src -{ - kSimFtmTrgSrc0, /* FlexTimer x trigger y select 0 */ - kSimFtmTrgSrc1 /* FlexTimer x trigger y select 1 */ -} sim_ftm_trg_src_t; - -/*! @brief SIM FlexTimer external clock select */ -typedef enum _sim_ftm_clk_sel -{ - kSimFtmClkSel0, /* FTM CLKIN0 pin. */ - kSimFtmClkSel1 /* FTM CLKIN1 pin. */ -} sim_ftm_clk_sel_t; - -/*! @brief SIM FlexTimer x channel y input capture source select */ -typedef enum _sim_ftm_ch_src -{ - kSimFtmChSrc0, /* See RM for details of each selection for each channel */ - kSimFtmChSrc1, /* See RM for details of each selection for each channel */ - kSimFtmChSrc2, /* See RM for details of each selection for each channel */ - kSimFtmChSrc3 /* See RM for details of each selection for each channel */ -} sim_ftm_ch_src_t; - -/*! @brief SIM FlexTimer x Fault y select */ -typedef enum _sim_ftm_flt_sel -{ - kSimFtmFltSel0, /* FlexTimer x fault y select 0 */ - kSimFtmFltSel1 /* FlexTimer x fault y select 1 */ -} sim_ftm_flt_sel_t; - -/*! @brief SIM Timer/PWM external clock select */ -typedef enum _sim_tpm_clk_sel -{ - kSimTpmClkSel0, /* Timer/PWM TPM_CLKIN0 pin. */ - kSimTpmClkSel1 /* Timer/PWM TPM_CLKIN1 pin. */ -} sim_tpm_clk_sel_t; - -/*! @brief SIM Timer/PWM x channel y input capture source select */ -typedef enum _sim_tpm_ch_src -{ - kSimTpmChSrc0, /* TPMx_CH0 signal */ - kSimTpmChSrc1 /* CMP0 output */ -} sim_tpm_ch_src_t; - -/*! @brief SIM HAL API return status*/ -typedef enum _sim_hal_status { - kSimHalSuccess, - kSimHalFail, - kSimHalNoSuchModule, - kSimHalNoSuchClockSrc, - kSimHalNoSuchDivider -} sim_hal_status_t; - -/*! @brief Clock name configuration table structure*/ -typedef struct ClockNameConfig { - bool useOtherRefClock; /*!< if it uses the other ref clock*/ - clock_names_t otherRefClockName; /*!< other ref clock name*/ - clock_divider_names_t dividerName; /*!< clock divider name*/ -} clock_name_config_t; - -/*! @brief clock name configuration table for specified CPU defined in fsl_clock_module_names_Kxxx.h*/ -extern const clock_name_config_t kClockNameConfigTable[]; - - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name clock-related feature APIs*/ -/*@{*/ - -/*! - * @brief Sets the clock source setting. - * - * This function sets the settings for a specified clock source. Each clock - * source has its own clock selection settings. See the chip reference manual for - * clock source detailed settings and the clock_source_names_t - * for clock sources. - * - * @param baseAddr Base address for current SIM instance. - * @param clockSource Clock source name defined in sim_clock_source_names_t - * @param setting Setting value - * @return status If the clock source doesn't exist, it returns an error. - */ -sim_hal_status_t CLOCK_HAL_SetSource(uint32_t baseAddr, clock_source_names_t clockSource, uint8_t setting); - -/*! - * @brief Gets the clock source setting. - * - * This function gets the settings for a specified clock source. Each clock - * source has its own clock selection settings. See the reference manual for - * clock source detailed settings and the clock_source_names_t - * for clock sources. - * - * @param baseAddr Base address for current SIM instance. - * @param clockSource Clock source name - * @param setting Current setting pointer for the clock source - * @return status If the clock source doesn't exist, it returns an error. - */ -sim_hal_status_t CLOCK_HAL_GetSource(uint32_t baseAddr, clock_source_names_t clockSource, - uint8_t *setting); - -/*! - * @brief Sets the clock divider setting. - * - * This function sets the setting for a specified clock divider. See the - * reference manual for a supported clock divider and value range and the - * clock_divider_names_t for dividers. - * - * @param baseAddr Base address for current SIM instance. - * @param clockDivider Clock divider name - * @param setting Divider setting - * @return status If the clock divider doesn't exist, it returns an error. - */ -sim_hal_status_t CLOCK_HAL_SetDivider(uint32_t baseAddr, clock_divider_names_t clockDivider, - uint32_t setting); - -/*! - * @brief Sets the clock out dividers setting. - * - * This function sets the setting for all clock out dividers at the same time. - * See the reference manual for a supported clock divider and value range and the - * clock_divider_names_t for clock out dividers. - * - * @param baseAddr Base address for current SIM instance. - * @param outdiv1 Outdivider1 setting - * @param outdiv2 Outdivider2 setting - * @param outdiv3 Outdivider3 setting - * @param outdiv4 Outdivider4 setting - */ -void CLOCK_HAL_SetOutDividers(uint32_t baseAddr, uint32_t outdiv1, uint32_t outdiv2, - uint32_t outdiv3, uint32_t outdiv4); - -/*! - * @brief Gets the clock divider setting. - * - * This function gets the setting for a specified clock divider. See the - * reference manual for a supported clock divider and value range and the - * clock_divider_names_t for dividers. - * - * @param baseAddr Base address for current SIM instance. - * @param clockDivider Clock divider name - * @param setting Divider value pointer - * @return status If the clock divider doesn't exist, it returns an error. - */ -sim_hal_status_t CLOCK_HAL_GetDivider(uint32_t baseAddr, clock_divider_names_t clockDivider, - uint32_t *setting); - -/*@}*/ - -/*! @name individual field access APIs*/ -/*@{*/ - -#if FSL_FEATURE_SIM_OPT_HAS_RAMSIZE -/*! - * @brief Gets RAM size. - * - * This function gets the RAM size. The field specifies the amount of system RAM - * available on the device. - * - * @param baseAddr Base address for current SIM instance. - * @return size RAM size on the device - */ -static inline uint32_t SIM_HAL_GetRamSize(uint32_t baseAddr) -{ - return BR_SIM_SOPT1_RAMSIZE(baseAddr); -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_RAMSIZE */ - -#if FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR -/*! - * @brief Sets the USB voltage regulator enabled setting. - * - * This function controls whether the USB voltage regulator is enabled. This bit - * can only be written when the SOPT1CFG[URWE] bit is set. - * - * @param baseAddr Base address for current SIM instance. - * @param enable USB voltage regulator enable setting - * - true: USB voltage regulator is enabled. - * - false: USB voltage regulator is disabled. - */ -static inline void SIM_HAL_SetUsbVoltRegulatorCmd(uint32_t baseAddr, bool enable) -{ - BW_SIM_SOPT1_USBREGEN(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the USB voltage regulator enabled setting. - * - * This function gets the USB voltage regulator enabled setting. - * - * @param baseAddr Base address for current SIM instance. - * @return enabled True if the USB voltage regulator is enabled. - */ -static inline bool SIM_HAL_GetUsbVoltRegulatorCmd(uint32_t baseAddr) -{ - return BR_SIM_SOPT1_USBREGEN(baseAddr); -} - -/*! - * @brief Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS. - * - * This function controls whether the USB voltage regulator is placed in a standby - * mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the - * SOPT1CFG[USSWE] bit is set. - * - * @param baseAddr Base address for current SIM instance. - * @param setting USB voltage regulator in standby mode setting - * - 0: USB voltage regulator not in standby during Stop, VLPS, LLS and - * VLLS modes. - * - 1: USB voltage regulator in standby during Stop, VLPS, LLS and VLLS - * modes. - */ -static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode(uint32_t baseAddr, - sim_usbsstby_stop_t setting) -{ - BW_SIM_SOPT1_USBSSTBY(baseAddr, setting); -} - -/*! - * @brief Gets the USB voltage regulator in a standby mode setting. - * - * This function gets the USB voltage regulator in a standby mode setting. - * - * @param baseAddr Base address for current SIM instance. - * @return setting USB voltage regulator in a standby mode setting - */ -static inline sim_usbsstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode(uint32_t baseAddr) -{ - return (sim_usbsstby_stop_t)BR_SIM_SOPT1_USBSSTBY(baseAddr); -} - -/*! - * @brief Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW. - * - * This function controls whether the USB voltage regulator is placed in a standby - * mode during the VLPR and the VLPW modes. This bit can only be written when the - * SOPT1CFG[UVSWE] bit is set. - * - * @param baseAddr Base address for current SIM instance. - * @param setting USB voltage regulator in standby mode setting - * - 0: USB voltage regulator not in standby during VLPR and VLPW modes. - * - 1: USB voltage regulator in standby during VLPR and VLPW modes. - */ -static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode(uint32_t baseAddr, - sim_usbvstby_stop_t setting) -{ - BW_SIM_SOPT1_USBVSTBY(baseAddr, setting); -} - -/*! - * @brief Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW. - * - * This function gets the USB voltage regulator in a standby mode during the VLPR or the VLPW. - * - * @param baseAddr Base address for current SIM instance. - * @return setting USB voltage regulator in a standby mode during the VLPR or the VLPW - */ -static inline sim_usbvstby_stop_t SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode(uint32_t baseAddr) -{ - return (sim_usbvstby_stop_t)BR_SIM_SOPT1_USBVSTBY(baseAddr); -} - -/*! - * @brief Sets the USB voltage regulator stop standby write enable setting. - * - * This function controls whether the USB voltage regulator stop standby write - * feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This - * register bit clears after a write to SOPT1[USBSSTBY]. - * - * @param baseAddr Base address for current SIM instance. - * @param enable USB voltage regulator stop standby write enable setting - * - true: SOPT1[USBSSTBY] can be written. - * - false: SOPT1[USBSSTBY] cannot be written. - */ -static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd(uint32_t baseAddr, bool enable) -{ - BW_SIM_SOPT1CFG_USSWE(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the USB voltage regulator stop standby write enable setting. - * - * This function gets the USB voltage regulator stop standby write enable setting. - * - * @param baseAddr Base address for current SIM instance. - * @return enabled True if the USB voltage regulator stop standby write is enabled. - */ -static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd(uint32_t baseAddr) -{ - return BR_SIM_SOPT1CFG_USSWE(baseAddr); -} - -/*! - * @brief Sets the USB voltage regulator VLP standby write enable setting. - * - * This function controls whether USB voltage regulator VLP standby write - * feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This - * register bit clears after a write to SOPT1[USBVSTBY]. - * - * @param baseAddr Base address for current SIM instance. - * @param enable USB voltage regulator VLP standby write enable setting - * - true: SOPT1[USBSSTBY] can be written. - * - false: SOPT1[USBSSTBY] cannot be written. - */ -static inline void SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd(uint32_t baseAddr, bool enable) -{ - BW_SIM_SOPT1CFG_UVSWE(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the USB voltage regulator VLP standby write enable setting. - * - * This function gets the USB voltage regulator VLP standby write enable setting. - * - * @param baseAddr Base address for current SIM instance. - * @return enabled True if the USB voltage regulator VLP standby write is enabled. - */ -static inline bool SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd(uint32_t baseAddr) -{ - return BR_SIM_SOPT1CFG_UVSWE(baseAddr); -} - -/*! - * @brief Sets the USB voltage regulator enable write enable setting. - * - * This function controls whether the USB voltage regulator write enable - * feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written. - * This register bit clears after a write to SOPT1[USBREGEN]. - * - * @param baseAddr Base address for current SIM instance. - * @param enable USB voltage regulator enable write enable setting - * - true: SOPT1[USBSSTBY] can be written. - * - false: SOPT1[USBSSTBY] cannot be written. - */ -static inline void SIM_HAL_SetUsbVoltRegulatorWriteCmd(uint32_t baseAddr, bool enable) -{ - BW_SIM_SOPT1CFG_URWE(baseAddr, enable ? 1 : 0); -} - -/*! - * @brief Gets the USB voltage regulator enable write enable setting. - * - * This function gets the USB voltage regulator enable write enable setting. - * - * @param baseAddr Base address for current SIM instance. - * @return enabled True if USB voltage regulator enable write is enabled. - */ -static inline bool SIM_HAL_GetUsbVoltRegulatorWriteCmd(uint32_t baseAddr) -{ - return BR_SIM_SOPT1CFG_URWE(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD -/*! - * @brief Sets the CMT/UART pad drive strength setting. - * - * This function controls the output drive strength of the CMT IRO signal or - * UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it. - * - * @param baseAddr Base address for current SIM instance. - * @param setting CMT/UART pad drive strength setting - * - 0: Single-pad drive strength for CMT IRO or UART0_TXD. - * - 1: Dual-pad drive strength for CMT IRO or UART0_TXD. - */ -static inline void SIM_HAL_SetCmtUartPadDriveStrengthMode(uint32_t baseAddr, - sim_cmtuartpad_strengh_t setting) -{ - BW_SIM_SOPT2_CMTUARTPAD(baseAddr, setting); -} - -/*! - * @brief Gets the CMT/UART pad drive strength setting. - * - * This function gets the CMT/UART pad drive strength setting. - * - * @param baseAddr Base address for current SIM instance. - * @return setting CMT/UART pad drive strength setting - */ -static inline sim_cmtuartpad_strengh_t SIM_HAL_GetCmtUartPadDriveStrengthMode(uint32_t baseAddr) -{ - return (sim_cmtuartpad_strengh_t)BR_SIM_SOPT2_CMTUARTPAD(baseAddr); -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD */ - -#if FSL_FEATURE_SIM_OPT_HAS_PTD7PAD -/*! - * @brief Sets the PTD7 pad drive strength setting. - * - * This function controls the output drive strength of the PTD7 pin by selecting - * either one or two pads to drive it. - * - * @param baseAddr Base address for current SIM instance. - * @param setting PTD7 pad drive strength setting - * - 0: Single-pad drive strength for PTD7. - * - 1: Double pad drive strength for PTD7. - */ -static inline void SIM_HAL_SetPtd7PadDriveStrengthMode(uint32_t baseAddr, - sim_ptd7pad_strengh_t setting) -{ - BW_SIM_SOPT2_PTD7PAD(baseAddr, setting); -} - -/*! - * @brief Gets the PTD7 pad drive strength setting. - * - * This function gets the PTD7 pad drive strength setting. - * - * @param baseAddr Base address for current SIM instance. - * @return setting PTD7 pad drive strength setting - */ -static inline sim_ptd7pad_strengh_t SIM_HAL_GetPtd7PadDriveStrengthMode(uint32_t baseAddr) -{ - return (sim_ptd7pad_strengh_t)BR_SIM_SOPT2_PTD7PAD(baseAddr); -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_PTD7PAD */ - -#if FSL_FEATURE_SIM_OPT_HAS_FBSL -/*! - * @brief Sets the FlexBus security level setting. - * - * This function sets the FlexBus security level setting. If the security is enabled, - * this field affects which CPU operations can access the off-chip via the FlexBus - * and DDR controller interfaces. This field has no effect if the security is not enabled. - * - * @param baseAddr Base address for current SIM instance. - * @param setting FlexBus security level setting - * - 00: All off-chip accesses (op code and data) via the FlexBus and - * DDR controller are disallowed. - * - 10: Off-chip op code accesses are disallowed. Data accesses are - * allowed. - * - 11: Off-chip op code accesses and data accesses are allowed. - */ -static inline void SIM_HAL_SetFlexbusSecurityLevelMode(uint32_t baseAddr, - sim_flexbus_security_level_t setting) -{ - BW_SIM_SOPT2_FBSL(baseAddr, setting); -} - -/*! - * @brief Gets the FlexBus security level setting. - * - * This function gets the FlexBus security level setting. - * - * @param baseAddr Base address for current SIM instance. - * @return setting FlexBus security level setting - */ -static inline sim_flexbus_security_level_t SIM_HAL_GetFlexbusSecurityLevelMode(uint32_t baseAddr) -{ - return (sim_flexbus_security_level_t)BR_SIM_SOPT2_FBSL(baseAddr); -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_FBSL */ - -#if FSL_FEATURE_SIM_OPT_HAS_PCR -/*! - * @brief Sets the PCR setting. - * - * This function sets the PCR setting. This is the FlexBus hold cycles before - * FlexBus can release bus to NFC or to IDLE. - * - * @param baseAddr Base address for current SIM instance. - * @param setting PCR setting - */ -static inline void SIM_HAL_SetFlexbusHoldCycles(uint32_t baseAddr, uint32_t setting) -{ - BW_SIM_SOPT6_PCR(baseAddr, setting); -} - -/*! - * @brief Gets the PCR setting. - * - * This function gets the PCR setting. - * - * @param baseAddr Base address for current SIM instance. - * @return setting PCR setting - */ -static inline uint32_t SIM_HAL_GetFlexbusHoldCycles(uint32_t baseAddr) -{ - return BR_SIM_SOPT6_PCR(baseAddr); -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_PCR */ - -#if FSL_FEATURE_SIM_OPT_HAS_MCC -/*! - * @brief Sets the MCC setting. - * - * This function sets the MCC setting. This is the NFC hold cycle in case the - * FlexBus request during NFC is granted. - * - * @param baseAddr Base address for current SIM instance. - * @param setting MCC setting - */ -static inline void SIM_HAL_SetNandFlashControllerHoldCycles(uint32_t baseAddr, uint32_t setting) -{ - BW_SIM_SOPT6_MCC(baseAddr, setting); -} - -/*! - * @brief Gets the MCC setting. - * - * This function gets the MCC setting. - * - * @param baseAddr Base address for current SIM instance. - * @return setting MCC setting - */ -static inline uint32_t SIM_HAL_GetNandFlashControllerHoldCycles(uint32_t baseAddr) -{ - return BR_SIM_SOPT6_MCC(baseAddr); -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_MCC */ - -/*! - * @brief Sets the ADCx alternate trigger enable setting. - * - * This function enables/disables the alternative conversion triggers for ADCx. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param enable Enable alternative conversion triggers for ADCx - * - true: Select alternative conversion trigger. - * - false: Select PDB trigger. - */ -void SIM_HAL_SetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance, bool enable); - -/*! - * @brief Gets the ADCx alternate trigger enable setting. - * - * This function gets the ADCx alternate trigger enable setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return enabled True if ADCx alternate trigger is enabled - */ -bool SIM_HAL_GetAdcAlternativeTriggerCmd(uint32_t baseAddr, uint8_t instance); - -/*! - * @brief Sets the ADCx pre-trigger select setting. - * - * This function selects the ADCx pre-trigger source when the alternative triggers - * are enabled through ADCxALTTRGEN. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param select pre-trigger select setting for ADCx - * - 0: Pre-trigger A selected for ADCx. - * - 1: Pre-trigger B selected for ADCx. - */ -void SIM_HAL_SetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance, sim_pretrgsel_t select); - -/*! - * @brief Gets the ADCx pre-trigger select setting. - * - * This function gets the ADCx pre-trigger select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return select ADCx pre-trigger select setting - */ -sim_pretrgsel_t SIM_HAL_GetAdcPreTriggerMode(uint32_t baseAddr, uint8_t instance); - -/*! - * @brief Sets the ADCx trigger select setting. - * - * This function selects the ADCx trigger source when alternative triggers - * are enabled through ADCxALTTRGEN. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param select trigger select setting for ADCx - * - 0000: External trigger - * - 0001: High speed comparator 0 asynchronous interrupt - * - 0010: High speed comparator 1 asynchronous interrupt - * - 0011: High speed comparator 2 asynchronous interrupt - * - 0100: PIT trigger 0 - * - 0101: PIT trigger 1 - * - 0110: PIT trigger 2 - * - 0111: PIT trigger 3 - * - 1000: FTM0 trigger - * - 1001: FTM1 trigger - * - 1010: FTM2 trigger - * - 1011: FTM3 trigger - * - 1100: RTC alarm - * - 1101: RTC seconds - * - 1110: Low-power timer trigger - * - 1111: High speed comparator 3 asynchronous interrupt -*/ -void SIM_HAL_SetAdcTriggerMode(uint32_t baseAddr, uint8_t instance, sim_trgsel_t select); - -/*! - * @brief Gets the ADCx trigger select setting. - * - * This function gets the ADCx trigger select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return select ADCx trigger select setting - */ -sim_pretrgsel_t SIM_HAL_GetAdcTriggerMode(uint32_t baseAddr, uint8_t instance); - -/*! - * @brief Sets the UARTx receive data source select setting. - * - * This function selects the source for the UARTx receive data. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param select the source for the UARTx receive data - * - 00: UARTx_RX pin. - * - 01: CMP0. - * - 10: CMP1. - * - 11: Reserved. - */ -void SIM_HAL_SetUartRxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_rxsrc_t select); - -/*! - * @brief Gets the UARTx receive data source select setting. - * - * This function gets the UARTx receive data source select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return select UARTx receive data source select setting - */ -sim_uart_rxsrc_t SIM_HAL_GetUartRxSrcMode(uint32_t baseAddr, uint8_t instance); - -/*! - * @brief Sets the UARTx transmit data source select setting. - * - * This function selects the source for the UARTx transmit data. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param select the source for the UARTx transmit data - * - 00: UARTx_TX pin. - * - 01: UARTx_TX pin modulated with FTM1 channel 0 output. - * - 10: UARTx_TX pin modulated with FTM2 channel 0 output. - * - 11: Reserved. - */ -void SIM_HAL_SetUartTxSrcMode(uint32_t baseAddr, uint8_t instance, sim_uart_txsrc_t select); - -/*! - * @brief Gets the UARTx transmit data source select setting. - * - * This function gets the UARTx transmit data source select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return select UARTx transmit data source select setting - */ -sim_uart_txsrc_t SIM_HAL_GetUartTxSrcMode(uint32_t baseAddr, uint8_t instance); - -#if FSL_FEATURE_SIM_OPT_HAS_ODE -/*! - * @brief Sets the UARTx Open Drain Enable setting. - * - * This function enables/disables the UARTx Open Drain. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param enable Enable/disable UARTx Open Drain - * - True: Enable UARTx Open Drain - * - False: Disable UARTx Open Drain - */ -void SIM_HAL_SetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance, bool enable); - -/*! - * @brief Gets the UARTx Open Drain Enable setting. - * - * This function gets the UARTx Open Drain Enable setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return enabled True if UARTx Open Drain is enabled. - */ -bool SIM_HAL_GetUartOpenDrainCmd(uint32_t baseAddr, uint8_t instance); -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_FTM -/*! - * @brief Sets the FlexTimer x hardware trigger y source select setting. - * - * This function selects the source of FTMx hardware trigger y. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param trigger hardware trigger y - * @param select FlexTimer x hardware trigger y - * - 0: Pre-trigger A selected for ADCx. - * - 1: Pre-trigger B selected for ADCx. - */ -void SIM_HAL_SetFtmTriggerSrcMode(uint32_t baseAddr, - uint8_t instance, - uint8_t trigger, - sim_ftm_trg_src_t select); - -/*! - * @brief Gets the FlexTimer x hardware trigger y source select setting. - * - * This function gets the FlexTimer x hardware trigger y source select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param trigger hardware trigger y - * @return select FlexTimer x hardware trigger y source select setting - */ -sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t trigger); - -/*! - * @brief Sets the FlexTimer x external clock pin select setting. - * - * This function selects the source of FTMx external clock pin select. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param select FTMx external clock pin select - * - 0: FTMx external clock driven by FTM CLKIN0 pin. - * - 1: FTMx external clock driven by FTM CLKIN1 pin. - */ -void SIM_HAL_SetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance, sim_ftm_clk_sel_t select); - -/*! - * @brief Gets the FlexTimer x external clock pin select setting. - * - * This function gets the FlexTimer x external clock pin select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return select FlexTimer x external clock pin select setting - */ -sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(uint32_t baseAddr, uint8_t instance); - -/*! - * @brief Sets the FlexTimer x channel y input capture source select setting. - * - * This function selects the FlexTimer x channel y input capture source. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param channel FlexTimer channel y - * @param select FlexTimer x channel y input capture source - * See the reference manual for detailed definition for each channel and selection. - */ -void SIM_HAL_SetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel, sim_ftm_ch_src_t select); - -/*! - * @brief Gets the FlexTimer x channel y input capture source select setting. - * - * This function gets the FlexTimer x channel y input capture source select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param channel FlexTimer channel y - * @return select FlexTimer x channel y input capture source select setting - */ -sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel); - -/*! - * @brief Sets the FlexTimer x fault y select setting. - * - * This function sets the FlexTimer x fault y select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param fault fault y - * @param select FlexTimer x fault y select setting - * - 0: FlexTimer x fault y select 0. - * - 1: FlexTimer x fault y select 1. - */ -void SIM_HAL_SetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault, sim_ftm_flt_sel_t select); - -/*! - * @brief Gets the FlexTimer x fault y select setting. - * - * This function gets the FlexTimer x fault y select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param fault fault y - * @return select FlexTimer x fault y select setting - */ -sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode(uint32_t baseAddr, uint8_t instance, uint8_t fault); -#endif - -#if FSL_FEATURE_SIM_OPT_HAS_TPM -/*! - * @brief Sets the Timer/PWM x external clock pin select setting. - * - * This function selects the source of the Timer/PWM x external clock pin select. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param select Timer/PWM x external clock pin select - * - 0: Timer/PWM x external clock driven by the TPM_CLKIN0 pin. - * - 1: Timer/PWM x external clock driven by the TPM_CLKIN1 pin. - */ -void SIM_HAL_SetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance, sim_tpm_clk_sel_t select); - -/*! - * @brief Gets the Timer/PWM x external clock pin select setting. - * - * This function gets the Timer/PWM x external clock pin select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @return select Timer/PWM x external clock pin select setting - */ -sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode(uint32_t baseAddr, uint8_t instance); - -/*! - * @brief Sets the Timer/PWM x channel y input capture source select setting. - * - * This function selects the Timer/PWM x channel y input capture source. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param channel TPM channel y - * @param select Timer/PWM x channel y input capture source - * - 0: TPMx_CH0 signal - * - 1: CMP0 output - */ -void SIM_HAL_SetTpmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel, sim_tpm_ch_src_t select); - -/*! - * @brief Gets the Timer/PWM x channel y input capture source select setting. - * - * This function gets the Timer/PWM x channel y input capture source select setting. - * - * @param baseAddr Base address for current SIM instance. - * @param instance device instance. - * @param channel Tpm channel y - * @return select Timer/PWM x channel y input capture source select setting - */ -sim_tpm_ch_src_t SIM_HAL_GetTpmChSrcMode(uint32_t baseAddr, uint8_t instance, uint8_t channel); -#endif - -#if FSL_FEATURE_SIM_SDID_HAS_FAMILYID -/*! - * @brief Gets the Kinetis Family ID in the System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Family ID in the System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Family ID - */ -static inline uint32_t SIM_HAL_GetFamilyId(uint32_t baseAddr) -{ - return BR_SIM_SDID_FAMILYID(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_SDID_HAS_SUBFAMID -/*! - * @brief Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Sub-Family ID in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Sub-Family ID - */ -static inline uint32_t SIM_HAL_GetSubFamilyId(uint32_t baseAddr) -{ - return BR_SIM_SDID_SUBFAMID(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_SDID_HAS_SERIESID -/*! - * @brief Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Series ID in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Series ID - */ -static inline uint32_t SIM_HAL_GetSeriesId(uint32_t baseAddr) -{ - return BR_SIM_SDID_SERIESID(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_SDID_HAS_FAMID -/*! - * @brief Gets the Kinetis Fam ID in System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Fam ID in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Fam ID - */ -static inline uint32_t SIM_HAL_GetFamId(uint32_t baseAddr) -{ - return BR_SIM_SDID_FAMID(baseAddr); -} -#endif - -/*! - * @brief Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Pincount ID in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Pincount ID - */ -static inline uint32_t SIM_HAL_GetPinCntId(uint32_t baseAddr) -{ - return BR_SIM_SDID_PINID(baseAddr); -} - -/*! - * @brief Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Revision ID in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Revision ID - */ -static inline uint32_t SIM_HAL_GetRevId(uint32_t baseAddr) -{ - return BR_SIM_SDID_REVID(baseAddr); -} - -#if FSL_FEATURE_SIM_SDID_HAS_DIEID -/*! - * @brief Gets the Kinetis Die ID in the System Device ID register (SIM_SDID). - * - * This function gets the Kinetis Die ID in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis Die ID - */ -static inline uint32_t SIM_HAL_GetDieId(uint32_t baseAddr) -{ - return BR_SIM_SDID_DIEID(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE -/*! - * @brief Gets the Kinetis SRAM size in the System Device ID register (SIM_SDID). - * - * This function gets the Kinetis SRAM Size in System Device ID register. - * - * @param baseAddr Base address for current SIM instance. - * @return id Kinetis SRAM Size - */ -static inline uint32_t SIM_HAL_GetSramSize(uint32_t baseAddr) -{ - return BR_SIM_SDID_SRAMSIZE(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE -/*! - * @brief Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the FlexNVM size in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return size FlexNVM Size - */ -static inline uint32_t SIM_HAL_GetFlexnvmSize(uint32_t baseAddr) -{ - return BR_SIM_FCFG1_NVMSIZE(baseAddr); -} -#endif - -/*! - * @brief Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the program flash size in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return size Program flash Size - */ -static inline uint32_t SIM_HAL_GetProgramFlashSize(uint32_t baseAddr) -{ - return BR_SIM_FCFG1_PFSIZE(baseAddr); -} - -#if FSL_FEATURE_SIM_FCFG_HAS_EESIZE -/*! - * @brief Gets the EEProm size in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the EEProm size in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return size EEProm Size - */ -static inline uint32_t SIM_HAL_GetEepromSize(uint32_t baseAddr) -{ - return BR_SIM_FCFG1_EESIZE(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_DEPART -/*! - * @brief Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the FlexNVM partition in the Flash Configuration Register 1 - * - * @param baseAddr Base address for current SIM instance. - * @return setting FlexNVM partition setting - */ -static inline uint32_t SIM_HAL_GetFlexnvmPartition(uint32_t baseAddr) -{ - return BR_SIM_FCFG1_DEPART(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE -/*! - * @brief Sets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function sets the Flash Doze in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @param setting Flash Doze setting - */ -static inline void SIM_HAL_SetFlashDoze(uint32_t baseAddr, uint32_t setting) -{ - BW_SIM_FCFG1_FLASHDOZE(baseAddr, setting); -} - -/*! - * @brief Gets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the Flash Doze in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return setting Flash Doze setting - */ -static inline uint32_t SIM_HAL_GetFlashDoze(uint32_t baseAddr) -{ - return BR_SIM_FCFG1_FLASHDOZE(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS -/*! - * @brief Sets the Flash disable setting in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function sets the Flash disable setting in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @param disable Flash disable setting - */ -static inline void SIM_HAL_SetFlashDisableCmd(uint32_t baseAddr, bool disable) -{ - BW_SIM_FCFG1_FLASHDIS(baseAddr, disable); -} - -/*! - * @brief Gets the Flash disable setting in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the Flash disable setting in the Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return setting Flash disable setting - */ -static inline bool SIM_HAL_GetFlashDisableCmd(uint32_t baseAddr) -{ - return (bool)BR_SIM_FCFG1_FLASHDIS(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 -/*! - * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the Flash maximum block 0 in Flash Configuration Register 2. - * - * @param baseAddr Base address for current SIM instance. - * @return address Flash maximum block 0 address - */ -static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock0(uint32_t baseAddr) -{ - return BR_SIM_FCFG2_MAXADDR0(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 -/*! - * @brief Gets the Flash maximum address block 1 in Flash Configuration Register 2. - * - * This function gets the Flash maximum block 1 in Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return address Flash maximum block 0 address - */ -static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock1(uint32_t baseAddr) -{ - return BR_SIM_FCFG2_MAXADDR1(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 -/*! - * @brief Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG). - * - * This function gets the Flash maximum block 0 in Flash Configuration Register 2. - * - * @param baseAddr Base address for current SIM instance. - * @return address Flash maximum block 0 address - */ -static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock01(uint32_t baseAddr) -{ - return BR_SIM_FCFG2_MAXADDR01(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 -/*! - * @brief Gets the Flash maximum address block 1 in the Flash Configuration Register 2. - * - * This function gets the Flash maximum block 1 in Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return address Flash maximum block 0 address - */ -static inline uint32_t SIM_HAL_GetFlashMaxAddrBlock23(uint32_t baseAddr) -{ - return BR_SIM_FCFG2_MAXADDR23(baseAddr); -} -#endif - -#if FSL_FEATURE_SIM_FCFG_HAS_PFLSH -/*! - * @brief Gets the program flash in the Flash Configuration Register 2. - * - * This function gets the program flash maximum block 0 in Flash Configuration Register 1. - * - * @param baseAddr Base address for current SIM instance. - * @return status program flash status - */ -static inline uint32_t SIM_HAL_GetProgramFlashCmd(uint32_t baseAddr) -{ - return BR_SIM_FCFG2_PFLSH(baseAddr); -} -#endif - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - - -/* - * Include the CPU-specific clock API header files. - */ -#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \ - defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)) - - #define K02F12810_SERIES - -#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \ - defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \ - defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \ - defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \ - defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \ - defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)) - - #define K20D5_SERIES - - -#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \ - defined(CPU_MK22FN128VMP10)) - - #define K22F12810_SERIES - - /* Clock System Level API header file */ - #include "MK22F12810/fsl_sim_hal_K22F12810.h" - -#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \ - defined(CPU_MK22FN256VMP12)) - - #define K22F25612_SERIES - - /* Clock System Level API header file */ - #include "MK22F25612/fsl_sim_hal_K22F25612.h" - - - -#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12)) - - #define K22F51212_SERIES - - /* Clock System Level API header file */ - #include "MK22F51212/fsl_sim_hal_K22F51212.h" - - -#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12)) - - #define K24F12_SERIES - - /* Clock System Level API header file */ - #include "MK24F12/fsl_sim_hal_K24F12.h" - -#elif (defined(CPU_MK24FN256VDC12)) - - #define K24F25612_SERIES - - -#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12)) - - #define K63F12_SERIES - - /* Clock System Level API header file */ - #include "MK63F12/fsl_sim_hal_K63F12.h" - -#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)) - - #define K64F12_SERIES - - /* Clock System Level API header file */ - #include "MK64F12/fsl_sim_hal_K64F12.h" - -#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18)) - - #define K65F18_SERIES - - -#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18)) - - #define K66F18_SERIES - - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F12_SERIES - - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F15_SERIES - - -#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \ - defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \ - defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4)) - - #define KL02Z4_SERIES - - -#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \ - defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \ - defined(CPU_MKL03Z32VFK4)) - - #define KL03Z4_SERIES - - -#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \ - defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ - defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ - defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)) - - #define KL05Z4_SERIES - - -#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ - defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ - defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4)) - - #define KL13Z4_SERIES - - -#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ - defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ - defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4)) - - #define KL23Z4_SERIES - - -#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ - defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)) - - #define KL25Z4_SERIES - - /* Clock System Level API header file */ - #include "MKL25Z4/fsl_sim_hal_KL25Z4.h" - -#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \ - defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \ - defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \ - defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ - defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4)) - - #define KL26Z4_SERIES - - -#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \ - defined(CPU_MKL33Z256VMP4)) - - #define KL33Z4_SERIES - - -#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \ - defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)) - - #define KL43Z4_SERIES - - -#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)) - - #define KL46Z4_SERIES - - -#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)) - - #define KV30F12810_SERIES - - -#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)) - - #define KV31F12810_SERIES - - /* Clock System Level API header file */ - #include "MKV31F12810/fsl_sim_hal_KV31F12810.h" - -#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)) - - #define KV31F25612_SERIES - - /* Clock System Level API header file */ - #include "MKV31F25612/fsl_sim_hal_KV31F25612.h" - - -#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)) - - #define KV31F51212_SERIES - - /* Clock System Level API header file */ - #include "MKV31F51212/fsl_sim_hal_KV31F51212.h" - -#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15)) - - #define KV40F15_SERIES - - -#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15)) - - #define KV43F15_SERIES - - -#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)) - - #define KV44F15_SERIES - - -#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ - defined(CPU_MKV45F256VLL15)) - - #define KV45F15_SERIES - - -#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15)) - - #define KV46F15_SERIES - - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_SIM_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h deleted file mode 100644 index 03170b3d120..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h +++ /dev/null @@ -1,245 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_SMC_FEATURES_H__) -#define __FSL_SMC_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ - defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ - defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ - defined(CPU_MK22FN512VLL12) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (1) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (0) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (1) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (0) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ - defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ - defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ - defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ - defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ - defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (0) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (0) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (1) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (1) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (1) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (0) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (1) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (0) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (0) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (0) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (0) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (1) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -#elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ - defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (1) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (1) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (1) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (0) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ - defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ - defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ - defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ - defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ - defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ - defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ - defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ - defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (1) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (0) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (1) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (0) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ - #define FSL_FEATURE_SMC_HAS_PSTOPO (1) - /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ - #define FSL_FEATURE_SMC_HAS_LPOPO (1) - /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ - #define FSL_FEATURE_SMC_HAS_PORPO (1) - /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ - #define FSL_FEATURE_SMC_HAS_LPWUI (0) - /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ - #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) - /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) - /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ - #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) - /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ - #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) - /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ - #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) - /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ - #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_SMC_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c deleted file mode 100644 index ebacb1737ca..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_smc_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetMode - * Description : Config the power mode - * This function will configure the power mode control for any run, stop and - * stop submode if needed. It will also configure the power options for specific - * power mode. Application should follow the proper procedure to configure and - * switch power mode between the different run and stop mode. Refer to reference - * manual for the proper procedure and supported power mode that can be configured - * and switch between each other. Refert to smc_power_mode_config_t for required - * parameters to configure the power mode and the supported options. Other options - * may need to configure through the hal driver individaully. Refer to hal driver - * header for details. - * - *END**************************************************************************/ -smc_hal_error_code_t SMC_HAL_SetMode(uint32_t baseAddr, const smc_power_mode_config_t *powerModeConfig) -{ - smc_hal_error_code_t retCode = kSmcHalSuccess; - uint8_t currentStat; - volatile unsigned int dummyread; - smc_stop_mode_t stopMode; - smc_run_mode_t runMode; - power_mode_stat_t modeStat; - power_modes_t powerModeName = powerModeConfig->powerModeName; - - /* verify the power mode name*/ - assert(powerModeName < kPowerModeMax); - -#if FSL_FEATURE_SMC_HAS_LPWUI - /* check lpwui option*/ - if (powerModeConfig->lpwuiOption) - { - /* check current stat*/ - currentStat = SMC_HAL_GetStat(baseAddr); - - /* if not in VLPR stat, could not set to RUN*/ - if (currentStat == kStatRun) - { - SMC_HAL_SetLpwuiMode(baseAddr, powerModeConfig->lpwuiOptionValue); - } - } -#endif - - /* branch based on power mode name*/ - switch (powerModeName) - { - case kPowerModeRun: - case kPowerModeVlpr: - if (powerModeName == kPowerModeRun) - { - /* mode setting for normal RUN*/ - runMode = kSmcRun; - modeStat = kStatVlpr; - } - else - { - /* mode setting for VLPR*/ - runMode = kSmcVlpr; - modeStat = kStatRun; - } - - /* check current stat*/ - currentStat = SMC_HAL_GetStat(baseAddr); - - /* if not in VLPR stat, could not set to RUN*/ - if (currentStat != modeStat) - { - retCode = kSmcHalFailed; - } - else - { - /* set power mode to normal RUN or VLPR*/ - SMC_HAL_SetRunMode(baseAddr, runMode); - } - break; - -#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE - case kPowerModeHsrun: - /* mode setting for HSRUN (high speed run) */ - runMode = kSmcHsrun; - modeStat = kStatRun; - - /* check current stat*/ - currentStat = SMC_HAL_GetStat(baseAddr); - - if (currentStat != modeStat) - { - /* if not in the mode, return error*/ - retCode = kSmcHalFailed; - } - else - { - /* set power mode to normal RUN or VLPR mode first*/ - SMC_HAL_SetRunMode(baseAddr, runMode); - } - - break; -#endif - - case kPowerModeWait: - case kPowerModeVlpw: - if (powerModeName == kPowerModeWait) - { - /* mode setting for normal RUN*/ - runMode = kSmcRun; - modeStat = kStatRun; - } - else - { - /* mode setting for VLPR*/ - runMode = kSmcVlpr; - modeStat = kStatVlpr; - } - - /* check current stat*/ - currentStat = SMC_HAL_GetStat(baseAddr); - - if (currentStat != modeStat) - { - /* if not in the mode, return error*/ - retCode = kSmcHalFailed; - } - else - { - /* set power mode to normal RUN or VLPR mode first*/ - SMC_HAL_SetRunMode(baseAddr, runMode); - } - - if (retCode == kSmcHalSuccess) - { - /* Clear the SLEEPDEEP bit to disable deep sleep mode - enter wait mode*/ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - } - break; - - case kPowerModeStop: - case kPowerModeVlps: - case kPowerModeLls: - if (powerModeName == kPowerModeStop) - { -#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE - /* check current stat*/ - currentStat = SMC_HAL_GetStat(baseAddr); - - if ((currentStat == kStatHsrun) || (SMC_HAL_GetRunMode(baseAddr) == kSmcHsrun)) - { - retCode = kSmcHalFailed; - break; - } -#endif - stopMode = kSmcStop; -#if FSL_FEATURE_SMC_HAS_PSTOPO - if (powerModeConfig->pstopOption) - { - SMC_HAL_SetPstopMode(baseAddr, powerModeConfig->pstopOptionValue); - } -#endif - } - else if (powerModeName == kPowerModeVlps) - { - stopMode = kSmcVlps; - } - else - { - stopMode = kSmcLls; - } - - /* set power mode to specified STOP mode*/ - SMC_HAL_SetStopMode(baseAddr, stopMode); - -#if FSL_FEATURE_SMC_HAS_LLS_SUBMODE - if (powerModeName == kPowerModeLls) - { - /* further set the stop sub mode configuration*/ - SMC_HAL_SetStopSubMode(baseAddr, powerModeConfig->stopSubMode); - } -#endif - - /* wait for write to complete to SMC before stopping core */ - dummyread = SMC_HAL_GetStat(baseAddr); - dummyread = dummyread + 1; - - /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP)*/ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - - break; - - case kPowerModeVlls: - /* set power mode to specified STOP mode*/ - SMC_HAL_SetStopMode(baseAddr, kSmcVlls); - - /* further set the stop sub mode configuration*/ - SMC_HAL_SetStopSubMode(baseAddr, powerModeConfig->stopSubMode); - - /* check if Vlls0 option needs configuration*/ - if (powerModeConfig->stopSubMode == kSmcStopSub0) - { -#if FSL_FEATURE_SMC_HAS_PORPO - if (powerModeConfig->porOption) - { - SMC_HAL_SetPorMode(baseAddr, powerModeConfig->porOptionValue); - } -#endif - } - - /* wait for write to complete to SMC before stopping core */ - dummyread = SMC_HAL_GetStat(baseAddr); - dummyread = dummyread + 1; - - /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP)*/ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - - break; - default: - retCode = kSmcHalNoSuchModeName; - break; - } - - return retCode; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetProtection - * Description : Config all power mode protection settings - * This function will configure the power mode protection settings for - * supported power mode on the specified chip family. The availabe power modes - * are defined in smc_power_mode_protection_config_t. Application should provide - * the protect settings for all supported power mode on the chip and aslo this - * should be done at early system level init stage. Refer to reference manual - * for details. This register can only write once after power reset. So either - * use this function or use the individual set function if you only have single - * option to set. - * - *END**************************************************************************/ -void SMC_HAL_SetProtection(uint32_t baseAddr, smc_power_mode_protection_config_t *protectConfig) -{ - /* initialize the setting */ - uint8_t regValue = 0; - - /* check configurations for each mode and combine the seting together */ - if (protectConfig->vlpProt) - { - regValue |= BF_SMC_PMPROT_AVLP(1); - } - - if (protectConfig->llsProt) - { - regValue |= BF_SMC_PMPROT_ALLS(1); - } - - if (protectConfig->vllsProt) - { - regValue |= BF_SMC_PMPROT_AVLLS(1); - } - -#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE - if (protectConfig->hsrunProt) - { - regValue |= BF_SMC_PMPROT_AHSRUN(1); - } -#endif - - /* write once into pmprot register*/ - HW_SMC_PMPROT_SET(baseAddr, regValue); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetProtectionMode - * Description : Config the individual power mode protection setting - * This function will only configure the power mode protection settings for - * a specified power mode on the specified chip family. The availabe power modes - * are defined in smc_power_mode_protection_config_t. Refer to reference manual - * for details. This register can only write once after power reset. - * - *END**************************************************************************/ -void SMC_HAL_SetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect, bool allow) -{ - /* check the setting range */ - assert(protect < kAllowMax); - - /* branch according to mode and write the setting */ - switch (protect) - { - case kAllowVlp: - if (allow) - { - BW_SMC_PMPROT_AVLP(baseAddr, 1); - } - else - { - BW_SMC_PMPROT_AVLP(baseAddr, 0); - } - break; - case kAllowLls: - if (allow) - { - BW_SMC_PMPROT_ALLS(baseAddr, 1); - } - else - { - BW_SMC_PMPROT_ALLS(baseAddr, 0); - } - break; - case kAllowVlls: - if (allow) - { - BW_SMC_PMPROT_AVLLS(baseAddr, 1); - } - else - { - BW_SMC_PMPROT_AVLLS(baseAddr, 0); - } - break; -#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE - case kAllowHsrun: - if (allow) - { - BW_SMC_PMPROT_AHSRUN(baseAddr, 1); - } - else - { - BW_SMC_PMPROT_AHSRUN(baseAddr, 0); - } - break; -#endif - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetProtectionMode - * Description : Get the current power mode protection setting - * This function will get the current power mode protection settings for - * a specified power mode. - * - *END**************************************************************************/ -bool SMC_HAL_GetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect) -{ - bool retValue = false; - - /* check the mode range */ - assert(protect < kAllowMax); - - /* branch according to the mode and read the setting */ - switch (protect) - { - case kAllowVlp: - retValue = BR_SMC_PMPROT_AVLP(baseAddr); - break; - case kAllowLls: - retValue = BR_SMC_PMPROT_ALLS(baseAddr); - break; - case kAllowVlls: - retValue = BR_SMC_PMPROT_AVLLS(baseAddr); - break; -#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE - case kAllowHsrun: - retValue = BR_SMC_PMPROT_AHSRUN(baseAddr); - break; -#endif - default: - break; - } - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetRunMode - * Description : Config the RUN mode control setting - * This function will set the run mode settings. For example, normal run mode, - * very lower power run mode, etc. Refer to smc_run_mode_t for supported run - * mode on the chip family. Refer to reference manual for details about the - * run mode. - * - *END**************************************************************************/ -void SMC_HAL_SetRunMode(uint32_t baseAddr, smc_run_mode_t runMode) -{ - BW_SMC_PMCTRL_RUNM(baseAddr, runMode); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetRunMode - * Description : Get the current RUN mode config - * This function will get the run mode settings. Refer to smc_run_mode_t - * for supported run mode on the chip family. Refer to reference manual for - * details about the run mode. - * - *END**************************************************************************/ -smc_run_mode_t SMC_HAL_GetRunMode(uint32_t baseAddr) -{ - return (smc_run_mode_t)BR_SMC_PMCTRL_RUNM(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetStopMode - * Description : Config the STOP mode control setting - * This function will set the stop mode settings. For example, normal stop mode, - * very lower power stop mode, etc. Refer to smc_stop_mode_t for supported stop - * mode on the chip family. Refer to reference manual for details about the - * stop mode. - * - *END**************************************************************************/ -void SMC_HAL_SetStopMode(uint32_t baseAddr, smc_stop_mode_t stopMode) -{ - BW_SMC_PMCTRL_STOPM(baseAddr, stopMode); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetStopMode - * Description : Get the current STOP mode control setting - * This function will get the stop mode settings. For example, normal stop mode, - * very lower power stop mode, etc. Refer to smc_stop_mode_t for supported stop - * mode on the chip family. Refer to reference manual for details about the - * stop mode. - * - *END**************************************************************************/ -smc_stop_mode_t SMC_HAL_GetStopMode(uint32_t baseAddr) -{ - return (smc_stop_mode_t)BR_SMC_PMCTRL_STOPM(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetStopSubMode - * Description : Config the stop sub mode control setting - * This function will set the stop submode settings. Some of the stop mode will - * further have submode supported. Refer to smc_stop_submode_t for supported - * stop submode and Refer to reference manual for details about the submode - * for specific stop mode. - * - *END**************************************************************************/ -void SMC_HAL_SetStopSubMode(uint32_t baseAddr, smc_stop_submode_t stopSubMode) -{ -#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG - BW_SMC_VLLSCTRL_VLLSM(baseAddr, stopSubMode); -#else -#if FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM - BW_SMC_STOPCTRL_VLLSM(baseAddr, stopSubMode); -#else - BW_SMC_STOPCTRL_LLSM(baseAddr, stopSubMode); -#endif -#endif -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetStopSubMode - * Description : Get the current stop submode config - * This function will get the stop submode settings. Some of the stop mode will - * further have submode supported. Refer to smc_stop_submode_t for supported - * stop submode and Refer to reference manual for details about the submode - * for specific stop mode. - * - *END**************************************************************************/ -smc_stop_submode_t SMC_HAL_GetStopSubMode(uint32_t baseAddr) -{ -#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG - return (smc_stop_submode_t)BR_SMC_VLLSCTRL_VLLSM(baseAddr); -#else -#if FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM - return (smc_stop_submode_t)BR_SMC_STOPCTRL_VLLSM(baseAddr); -#else - return (smc_stop_submode_t)BR_SMC_STOPCTRL_LLSM(baseAddr); -#endif -#endif -} - -#if FSL_FEATURE_SMC_HAS_PORPO -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetPorMode - * Description : Config the POR (power-on-reset) option - * This function will set the POR power option setting. It controls whether the - * POR detect circuit (for brown-out detection) is enabled in certain stop mode. - * The setting will be either enable or disable the above feature when POR - * happened. Refer to reference manual for details. - * - *END**************************************************************************/ -void SMC_HAL_SetPorMode(uint32_t baseAddr, smc_por_option_t option) -{ -#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG - BW_SMC_VLLSCTRL_PORPO(baseAddr, option); -#else - BW_SMC_STOPCTRL_PORPO(baseAddr, option); -#endif -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetPorMode - * Description : Get the config of POR option - * This function will set the POR power option setting. See config function - * header for details. - * - *END**************************************************************************/ -smc_por_option_t SMC_HAL_GetPorMode(uint32_t baseAddr) -{ -#if FSL_FEATURE_SMC_USE_VLLSCTRL_REG - return (smc_por_option_t)BR_SMC_VLLSCTRL_PORPO(baseAddr); -#else - return (smc_por_option_t)BR_SMC_STOPCTRL_PORPO(baseAddr); -#endif -} -#endif - -#if FSL_FEATURE_SMC_HAS_PSTOPO -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetPorMode - * Description : Config the PSTOPO (Partial Stop Option) - * This function will set the PSTOPO option. It controls whether a Partial - * Stop mode is entered when STOPM=STOP. When entering a Partial Stop mode from - * RUN mode, the PMC, MCG and flash remain fully powered, allowing the device - * to wakeup almost instantaneously at the expense of higher power consumption. - * In PSTOP2, only system clocks are gated allowing peripherals running on bus - * clock to remain fully functional. In PSTOP1, both system and bus clocks are - * gated. Refer to smc_pstop_option_t for supported options. Refer to reference - * manual for details. - * - *END**************************************************************************/ -void SMC_HAL_SetPstopMode(uint32_t baseAddr, smc_pstop_option_t option) -{ - BW_SMC_STOPCTRL_PSTOPO(baseAddr, option); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetPorMode - * Description : Get the config of PSTOPO option - * This function will get the current PSTOPO option setting. Refer to config - * function for more details. - * - *END**************************************************************************/ -smc_pstop_option_t SMC_HAL_GetPstopMode(uint32_t baseAddr) -{ - return (smc_pstop_option_t)BR_SMC_STOPCTRL_PSTOPO(baseAddr); -} -#endif - -#if FSL_FEATURE_SMC_HAS_LPOPO -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetPorMode - * Description : Config the LPO option setting - * This function will set the LPO option setting. It controls whether the 1kHZ - * LPO clock is enabled in certain lower power stop modes. Refer to - * smc_lpo_option_t for supported options and refer to reference manual for - * details about this option. - * - *END**************************************************************************/ -void SMC_HAL_SetLpoMode(uint32_t baseAddr, smc_lpo_option_t option) -{ - BW_SMC_STOPCTRL_LPOPO(baseAddr, option); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetPorMode - * Description : Get the config of LPO option - * This function will get the current LPO option setting. Refer to config - * function for details. - * - *END**************************************************************************/ -smc_por_option_t SMC_HAL_GetLpoMode(uint32_t baseAddr) -{ - return (smc_por_option_t)BR_SMC_STOPCTRL_LPOPO(baseAddr); -} -#endif - -#if FSL_FEATURE_SMC_HAS_LPWUI -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetLpwuiMode - * Description : Config the LPWUI (Low Power Wake Up on interrup) option - * This function will set the LPWUI option. It will cause the system to exit - * to normal RUN mode when any active interrupt occurs while in a certain lower - * power mode. Refer to smc_lpwui_option_t for supported options and refer to - * reference manual for more details about this option. - * - *END**************************************************************************/ -void SMC_HAL_SetLpwuiMode(uint32_t baseAddr, smc_lpwui_option_t option) -{ - BW_SMC_PMCTRL_LPWUI(baseAddr, option); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_SetLpwuiMode - * Description : Get the current LPWUI option - * This function will get the LPWUI option. Refer to config function for more - * details. - * - *END**************************************************************************/ -smc_lpwui_option_t SMC_HAL_GetLpwuiMode(uint32_t baseAddr) -{ - return (smc_lpwui_option_t)BR_SMC_PMCTRL_LPWUI(baseAddr); -} -#endif - -/*FUNCTION********************************************************************** - * - * Function Name : SMC_HAL_GetStat - * Description : Get the current power mode stat - * This function will return the current power mode stat. Once application is - * switching the power mode, it should always check the stat to make sure it - * runs into the specified mode or not. Also application will need to check - * this mode before switching to certain mode. The system will require that - * only certain mode could switch to other specific mode. Refer to the - * reference manual for details. Refer to _power_mode_stat for the meaning - * of the power stat - * - *END**************************************************************************/ -uint8_t SMC_HAL_GetStat(uint32_t baseAddr) -{ - return BR_SMC_PMSTAT_PMSTAT(baseAddr); -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h deleted file mode 100644 index 822faaae589..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_SMC_HAL_H__) -#define __FSL_SMC_HAL_H__ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_smc_features.h" - -/*! @addtogroup smc_hal*/ -/*! @{*/ - -/*! @file fsl_smc_hal.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Power Modes */ -typedef enum _power_modes { - kPowerModeRun, - kPowerModeWait, - kPowerModeStop, - kPowerModeVlpr, - kPowerModeVlpw, - kPowerModeVlps, - kPowerModeLls, - kPowerModeVlls, - kPowerModeHsrun, - kPowerModeMax -} power_modes_t; - -/*! - * @brief Error code definition for the system mode controller manager APIs. - */ -typedef enum _smc_hal_error_code { - kSmcHalSuccess, /*!< Success */ - kSmcHalNoSuchModeName, /*!< Cannot find the mode name specified*/ - kSmcHalAlreadyInTheState, /*!< Already in the required state*/ - kSmcHalFailed /*!< Unknown error, operation failed*/ -} smc_hal_error_code_t; - -/*! @brief Power Modes in PMSTAT*/ -typedef enum _power_mode_stat { - kStatRun = 0x01, /*!< 0000_0001 - Current power mode is RUN*/ - kStatStop = 0x02, /*!< 0000_0010 - Current power mode is STOP*/ - kStatVlpr = 0x04, /*!< 0000_0100 - Current power mode is VLPR*/ - kStatVlpw = 0x08, /*!< 0000_1000 - Current power mode is VLPW*/ - kStatVlps = 0x10, /*!< 0001_0000 - Current power mode is VLPS*/ - kStatLls = 0x20, /*!< 0010_0000 - Current power mode is LLS*/ - kStatVlls = 0x40, /*!< 0100_0000 - Current power mode is VLLS*/ - kStatHsrun = 0x80 /*!< 1000_0000 - Current power mode is HSRUN*/ -} power_mode_stat_t; - -/*! @brief Power Modes Protection*/ -typedef enum _power_modes_protect { - kAllowHsrun, /*!< Allow High Speed Run mode*/ - kAllowVlp, /*!< Allow Very-Low-Power Modes*/ - kAllowLls, /*!< Allow Low-Leakage Stop Mode*/ - kAllowVlls, /*!< Allow Very-Low-Leakage Stop Mode*/ - kAllowMax -} power_modes_protect_t; - -/*! - * @brief Run mode definition - */ -typedef enum _smc_run_mode { - kSmcRun, /*!< normal RUN mode*/ - kSmcReservedRun, - kSmcVlpr, /*!< Very-Low-Power RUN mode*/ - kSmcHsrun /*!< High Speed Run mode (HSRUN)*/ -} smc_run_mode_t; - -/*! - * @brief Stop mode definition - */ -typedef enum _smc_stop_mode { - kSmcStop, /*!< Normal STOP mode*/ - kSmcReservedStop1, /*!< Reserved*/ - kSmcVlps, /*!< Very-Low-Power STOP mode*/ - kSmcLls, /*!< Low-Leakage Stop mode*/ - kSmcVlls /*!< Very-Low-Leakage Stop mode*/ -} smc_stop_mode_t; - -/*! - * @brief VLLS/LLS stop sub mode definition - */ -typedef enum _smc_stop_submode { - kSmcStopSub0, - kSmcStopSub1, - kSmcStopSub2, - kSmcStopSub3 -} smc_stop_submode_t; - -/*! @brief Low Power Wake Up on Interrupt option*/ -typedef enum _smc_lpwui_option { - kSmcLpwuiEnabled, /*!< Low Power Wake Up on Interrupt enabled*/ - kSmcLpwuiDisabled /*!< Low Power Wake Up on Interrupt disabled*/ -} smc_lpwui_option_t; - -/*! @brief Partial STOP option*/ -typedef enum _smc_pstop_option { - kSmcPstopStop, /*!< STOP - Normal Stop mode*/ - kSmcPstopStop1, /*!< Partial Stop with both system and bus clocks disabled*/ - kSmcPstopStop2, /*!< Partial Stop with system clock disabled and bus clock enabled*/ - kSmcPstopReserved, -} smc_pstop_option_t; - -/*! @brief POR option*/ -typedef enum _smc_por_option { - kSmcPorEnabled, /*!< POR detect circuit is enabled in VLLS0*/ - kSmcPorDisabled /*!< POR detect circuit is disabled in VLLS0*/ -} smc_por_option_t; - -/*! @brief LPO power option*/ -typedef enum _smc_lpo_option { - kSmcLpoEnabled, /*!< LPO clock is enabled in LLS/VLLSx*/ - kSmcLpoDisabled /*!< LPO clock is disabled in LLS/VLLSx*/ -} smc_lpo_option_t; - -/*! @brief Power mode control options*/ -typedef enum _smc_power_options { - kSmcOptionLpwui, /*!< Low Power Wake Up on Interrupt*/ - kSmcOptionPropo /*!< POR option*/ -} smc_power_options_t; - -/*! @brief Power mode protection configuration*/ -typedef struct _smc_power_mode_protection_config { - bool vlpProt; /*!< VLP protect*/ - bool llsProt; /*!< LLS protect */ - bool vllsProt; /*!< VLLS protect*/ -#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE - bool hsrunProt; /*!< HSRUN protect */ -#endif -} smc_power_mode_protection_config_t; - -/*! @brief Power mode control configuration used for calling the SMC_SYS_SetPowerMode API. */ -typedef struct _smc_power_mode_config { - power_modes_t powerModeName; /*!< Power mode(enum), see power_modes_t */ - smc_stop_submode_t stopSubMode; /*!< Stop submode(enum), see smc_stop_submode_t */ -#if FSL_FEATURE_SMC_HAS_LPWUI - bool lpwuiOption; /*!< If LPWUI option is needed */ - smc_lpwui_option_t lpwuiOptionValue; /*!< LPWUI option(enum), see smc_lpwui_option_t */ -#endif -#if FSL_FEATURE_SMC_HAS_PORPO - bool porOption; /*!< If POR option is needed */ - smc_por_option_t porOptionValue; /*!< POR option(enum), see smc_por_option_t */ -#endif -#if FSL_FEATURE_SMC_HAS_PSTOPO - bool pstopOption; /*!< If PSTOPO option is needed */ - smc_pstop_option_t pstopOptionValue; /*!< PSTOPO option(enum), see smc_por_option_t */ -#endif -} smc_power_mode_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name System mode controller APIs*/ -/*@{*/ - -/*! - * @brief Configures the power mode. - * - * This function configures the power mode control for both run, stop, and - * stop sub mode if needed. Also it configures the power options for a specific - * power mode. An application should follow the proper procedure to configure and - * switch power modes between different run and stop modes. For proper procedures - * and supported power modes, see an appropriate chip reference - * manual. See the smc_power_mode_config_t for required - * parameters to configure the power mode and the supported options. Other options - * may need to be individually configured through the HAL driver. See the HAL driver - * header file for details. - * - * @param baseAddr Base address for current SMC instance. - * @param powerModeConfig Power mode configuration structure smc_power_mode_config_t - * @return errorCode SMC error code - */ -smc_hal_error_code_t SMC_HAL_SetMode(uint32_t baseAddr, - const smc_power_mode_config_t *powerModeConfig); - -/*! - * @brief Configures all power mode protection settings. - * - * This function configures the power mode protection settings for - * supported power modes in the specified chip family. The available power modes - * are defined in the smc_power_mode_protection_config_t. An application should provide - * the protect settings for all supported power modes on the chip. This - * should be done at an early system level initialization stage. See the reference manual - * for details. This register can only write once after the power reset. If the user has - * only a single option to set, - * either use this function or use the individual set function. - * - * - * @param baseAddr Base address for current SMC instance. - * @param protectConfig Configurations for the supported power mode protect settings - * - See smc_power_mode_protection_config_t for details. - */ -void SMC_HAL_SetProtection(uint32_t baseAddr, smc_power_mode_protection_config_t *protectConfig); - -/*! - * @brief Configures the individual power mode protection settings. - * - * This function only configures the power mode protection settings for - * a specified power mode on the specified chip family. The available power modes - * are defined in the smc_power_mode_protection_config_t. See the reference manual - * for details. This register can only write once after the power reset. - * - * @param baseAddr Base address for current SMC instance. - * @param protect Power mode to set for protection - * @param allow Allow or not allow the power mode protection - */ -void SMC_HAL_SetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect, bool allow); - -/*! - * @brief Gets the the current power mode protection setting. - * - * This function gets the current power mode protection settings for - * a specified power mode. - * - * @param baseAddr Base address for current SMC instance. - * @param protect Power mode to set for protection - * @return state Status of the protection setting - * - true: Allowed - * - false: Not allowed -*/ -bool SMC_HAL_GetProtectionMode(uint32_t baseAddr, power_modes_protect_t protect); - -/*! - * @brief Configures the the RUN mode control setting. - * - * This function sets the run mode settings, for example, normal run mode, - * very lower power run mode, etc. See the smc_run_mode_t for supported run - * mode on the chip family and the reference manual for details about the - * run mode. - * - * @param baseAddr Base address for current SMC instance. - * @param runMode Run mode setting defined in smc_run_mode_t - */ -void SMC_HAL_SetRunMode(uint32_t baseAddr, smc_run_mode_t runMode); - -/*! - * @brief Gets the current RUN mode configuration setting. - * - * This function gets the run mode settings. See the smc_run_mode_t - * for a supported run mode on the chip family and the reference manual for - * details about the run mode. - * - * @param baseAddr Base address for current SMC instance. - * @return setting Run mode configuration setting - */ -smc_run_mode_t SMC_HAL_GetRunMode(uint32_t baseAddr); - -/*! - * @brief Configures the STOP mode control setting. - * - * This function sets the stop mode settings, for example, normal stop mode, - * very lower power stop mode, etc. See the smc_stop_mode_t for supported stop - * mode on the chip family and the reference manual for details about the - * stop mode. - * - * @param baseAddr Base address for current SMC instance. - * @param stopMode Stop mode defined in smc_stop_mode_t - */ -void SMC_HAL_SetStopMode(uint32_t baseAddr, smc_stop_mode_t stopMode); - -/*! - * @brief Gets the current STOP mode control settings. - * - * This function gets the stop mode settings, for example, normal stop mode, - * very lower power stop mode, etc. See the smc_stop_mode_t for supported stop - * mode on the chip family and the reference manual for details about the - * stop mode. - * - * @param baseAddr Base address for current SMC instance. - * @return setting Current stop mode configuration setting - */ -smc_stop_mode_t SMC_HAL_GetStopMode(uint32_t baseAddr); - -/*! - * @brief Configures the stop sub mode control setting. - * - * This function sets the stop submode settings. Some of the stop mode - * further supports submodes. See the smc_stop_submode_t for supported - * stop submodes and the reference manual for details about the submodes - * for a specific stop mode. - * - * @param baseAddr Base address for current SMC instance. - * @param stopSubMode Stop submode setting defined in smc_stop_submode_t - */ -void SMC_HAL_SetStopSubMode(uint32_t baseAddr, smc_stop_submode_t stopSubMode); - -/*! - * @brief Gets the current stop submode configuration settings. - * - * This function gets the stop submode settings. Some of the stop mode - * further support submodes. See the smc_stop_submode_t for supported - * stop submodes and the reference manual for details about the submode - * for a specific stop mode. - * - * @param baseAddr Base address for current SMC instance. - * @return setting Current stop submode setting -*/ -smc_stop_submode_t SMC_HAL_GetStopSubMode(uint32_t baseAddr); - -#if FSL_FEATURE_SMC_HAS_PORPO -/*! - * @brief Configures the POR (power-on-reset) option. - * - * This function sets the POR power option setting. It controls whether the - * POR detect circuit (for brown-out detection) is enabled in a certain stop mode. - * The setting either enables or disables the above feature when the POR - * occurs. See the reference manual for details. - * - * @param baseAddr Base address for current SMC instance. - * @param option POR option setting refer to smc_por_option_t - */ -void SMC_HAL_SetPorMode(uint32_t baseAddr, smc_por_option_t option); - -/*! - * @brief Gets the configuration settings for the POR option. - * - * This function sets the POR power option setting. See the configuration function - * header for details. - * - * @param baseAddr Base address for current SMC instance. - * @return option Current POR option setting -*/ -smc_por_option_t SMC_HAL_GetPorMode(uint32_t baseAddr); -#endif - -#if FSL_FEATURE_SMC_HAS_PSTOPO -/*! - * @brief Configures the PSTOPO (Partial Stop Option). - * - * This function sets the PSTOPO option. It controls whether a Partial - * Stop mode is entered when the STOPM=STOP. When entering a Partial Stop mode from the - * RUN mode, the PMC, MCG and Flash remain fully powered allowing the device - * to wakeup almost instantaneously at the expense of a higher power consumption. - * In PSTOP2, only the system clocks are gated, which allows the peripherals running on bus - * clock to remain fully functional. In PSTOP1, both system and bus clocks are - * gated. Refer to the smc_pstop_option_t for supported options. See the reference - * manual for details. - * - * @param baseAddr Base address for current SMC instance. - * @param option PSTOPO option setting defined in smc_pstop_option_t - */ -void SMC_HAL_SetPstopMode(uint32_t baseAddr, smc_pstop_option_t option); - -/*! - * @brief Gets the configuration of the PSTOPO option. - * - * This function gets the current PSTOPO option setting. See the configuration - * function for more details. - * - * @param baseAddr Base address for current SMC instance. - * @return option Current PSTOPO option setting - */ -smc_pstop_option_t SMC_HAL_GetPstopMode(uint32_t baseAddr); -#endif - -#if FSL_FEATURE_SMC_HAS_LPOPO -/*! - * @brief Configures the LPO option setting. - * - * This function sets the LPO option setting. It controls whether the 1 kHZ - * LPO clock is enabled in a certain lower power stop modes. See the - * smc_lpo_option_t for supported options and the reference manual for - * details about this option. - * - * @param baseAddr Base address for current SMC instance. - * @param option LPO option setting defined in smc_lpo_option_t - */ -void SMC_HAL_SetLpoMode(uint32_t baseAddr, smc_lpo_option_t option); - -/*! - * @brief Gets the settings of the LPO option. - * - * This function gets the current LPO option setting. See the configuration - * function for details. - * - * @param baseAddr Base address for current SMC instance. - * @return option Current LPO option setting - */ -smc_por_option_t SMC_HAL_GetLpoMode(uint32_t baseAddr); -#endif - -#if FSL_FEATURE_SMC_HAS_LPWUI -/*! - * @brief Configures the LPWUI (Low Power Wake Up on interrupt) option. - * - * This function sets the LPWUI option and cause the system to exit - * to normal RUN mode when any active interrupt occurs while in a specific lower - * power mode. See the smc_lpwui_option_t for supported options and the - * reference manual for more details about this option. - * - * @param baseAddr Base address for current SMC instance. - * @param option LPWUI option setting defined in smc_lpwui_option_t - */ -void SMC_HAL_SetLpwuiMode(uint32_t baseAddr, smc_lpwui_option_t option); - -/*! - * @brief Gets the current LPWUI option. - * - * This function gets the LPWUI option. See the configuration function for more - * details. - * - * @param baseAddr Base address for current SMC instance. - * @return setting Current LPWAUI option setting - */ -smc_lpwui_option_t SMC_HAL_GetLpwuiMode(uint32_t baseAddr); -#endif - -/*! - * @brief Gets the current power mode stat. - * - * This function returns the current power mode stat. Once application - * switches the power mode, it should always check the stat to check whether it - * runs into the specified mode or not. An application should check - * this mode before switching to a different mode. The system requires that - * only certain modes can switch to other specific modes. See the - * reference manual for details and the _power_mode_stat for information about - * the power stat. - * - * @param baseAddr Base address for current SMC instance. - * @return stat Current power mode stat - */ -uint8_t SMC_HAL_GetStat(uint32_t baseAddr); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_SMC_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h deleted file mode 100644 index 629d1f5ca6e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h +++ /dev/null @@ -1,1218 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_UART_FEATURES_H__) -#define __FSL_UART_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ - defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : (-1))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : (-1))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ - defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ - defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ - defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ - defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : \ - ((x) == 2 ? (9) : (-1)))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : \ - ((x) == 2 ? (10) : (-1)))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ - defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : (-1))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : (-1))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : \ - ((x) == 2 ? (9) : (-1)))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : \ - ((x) == 2 ? (10) : (-1)))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \ - defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ - defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (8) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : \ - ((x) == 2 ? (9) : \ - ((x) == 3 ? (9) : \ - ((x) == 4 ? (9) : \ - ((x) == 5 ? (9) : (-1))))))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : \ - ((x) == 2 ? (10) : \ - ((x) == 3 ? (10) : \ - ((x) == 4 ? (10) : \ - ((x) == 5 ? (10) : (-1))))))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ - defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (8) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : (-1)))))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : \ - ((x) == 2 ? (9) : \ - ((x) == 3 ? (9) : \ - ((x) == 4 ? (9) : (-1)))))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : \ - ((x) == 2 ? (10) : \ - ((x) == 3 ? (10) : \ - ((x) == 4 ? (10) : (-1)))))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : (-1)))))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : (-1)))))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : (-1)))))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : (-1)))))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ - defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (8) : \ - ((x) == 2 ? (8) : \ - ((x) == 3 ? (8) : \ - ((x) == 4 ? (8) : \ - ((x) == 5 ? (8) : (-1))))))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : \ - ((x) == 2 ? (9) : \ - ((x) == 3 ? (9) : \ - ((x) == 4 ? (9) : \ - ((x) == 5 ? (9) : (-1))))))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : \ - ((x) == 2 ? (10) : \ - ((x) == 3 ? (10) : \ - ((x) == 4 ? (10) : \ - ((x) == 5 ? (10) : (-1))))))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : \ - ((x) == 3 ? (1) : \ - ((x) == 4 ? (1) : \ - ((x) == 5 ? (1) : (-1))))))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : \ - ((x) == 3 ? (0) : \ - ((x) == 4 ? (0) : \ - ((x) == 5 ? (0) : (-1))))))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ - defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ - defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (0) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (0) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (10) : (-1)) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (9) : (-1)) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (1) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (0) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ - defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ - defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ - defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ - defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ - defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ - defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ - defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ - defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : (-1)) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : (-1)) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : (-1)) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (1) : (-1)) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : (-1)) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ - defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ - defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \ - defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ - defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (0) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (0) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (9) : \ - ((x) == 2 ? (9) : (-1)))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (8) : \ - ((x) == 2 ? (8) : (-1)))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (1) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (1) : \ - ((x) == 2 ? (1) : (-1)))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : \ - ((x) == 2 ? (0) : (-1)))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ - defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ - defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ - defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ - defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ - #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) - /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_HAS_FIFO (1) - /* @brief Hardware flow control (RTS, CTS) is supported. */ - #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) - /* @brief Infrared (modulation) is supported. */ - #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) - /* @brief 2 bits long stop bit is available. */ - #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Baud rate fine adjustment is available. */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) - /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) - /* @brief Baud rate oversampling is available. */ - #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) - /* @brief Peripheral type. */ - #define FSL_FEATURE_UART_IS_SCI (0) - /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ - #define FSL_FEATURE_UART_FIFO_SIZE (8) - #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ - ((x) == 0 ? (8) : \ - ((x) == 1 ? (8) : (-1))) - /* @brief Maximal data width without parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \ - ((x) == 0 ? (9) : \ - ((x) == 1 ? (9) : (-1))) - /* @brief Maximal data width with parity bit. */ - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) - #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \ - ((x) == 0 ? (10) : \ - ((x) == 1 ? (10) : (-1))) - /* @brief Supports two match addresses to filter incoming frames. */ - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) - #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) - #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ - #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) - #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) - #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \ - ((x) == 0 ? (1) : \ - ((x) == 1 ? (1) : (-1))) - /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has improved smart card (ISO7816 protocol) support. */ - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has local operation network (CEA709.1-B protocol) support. */ - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) - #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ - ((x) == 0 ? (0) : \ - ((x) == 1 ? (0) : (-1))) - /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ - #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_UART_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c deleted file mode 100644 index 4e7701aaab6..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c +++ /dev/null @@ -1,961 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_uart_hal.h" - -/******************************************************************************* - * Code - ******************************************************************************/ -/******************************************************************************* - * UART Common Configurations - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_Init - * Description : This function initializes the module to a known state. - * - *END**************************************************************************/ -void UART_HAL_Init(uint32_t baseAddr) -{ - HW_UART_BDH_WR(baseAddr, 0U); - HW_UART_BDL_WR(baseAddr, 4U); - HW_UART_C1_WR(baseAddr, 0U); - HW_UART_C2_WR(baseAddr, 0U); - HW_UART_S2_WR(baseAddr, 0U); - HW_UART_C3_WR(baseAddr, 0U); - HW_UART_D_WR(baseAddr, 0U); -#if FSL_FEATURE_UART_HAS_ADDRESS_MATCHING - HW_UART_MA1_WR(baseAddr, 0U); - HW_UART_MA2_WR(baseAddr, 0U); -#endif - HW_UART_C4_WR(baseAddr, 0U); -#if FSL_FEATURE_UART_HAS_DMA_ENABLE - HW_UART_C5_WR(baseAddr, 0U); -#endif -#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT - HW_UART_MODEM_WR(baseAddr, 0U); -#endif -#if FSL_FEATURE_UART_HAS_IR_SUPPORT - HW_UART_IR_WR(baseAddr, 0U); -#endif -#if FSL_FEATURE_UART_HAS_FIFO - HW_UART_PFIFO_WR(baseAddr, 0U); - HW_UART_CFIFO_WR(baseAddr, 0U); - HW_UART_SFIFO_WR(baseAddr, 0xC0U); - HW_UART_TWFIFO_WR(baseAddr, 0U); - HW_UART_RWFIFO_WR(baseAddr, 1U); -#endif -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetBaudRate - * Description : Configure the UART baud rate. - * This function programs the UART baud rate to the desired value passed in by the - * user. The user must also pass in the module source clock so that the function can - * calculate the baud rate divisors to their appropriate values. - * - *END**************************************************************************/ -uart_status_t UART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t baudRate) -{ - /* BaudRate = (SourceClkInHz)/[16 * (SBR + BRFA)] - * First, calculate SBR (integer part) then calculate the BRFA (fine adjust fractional field). */ - uint16_t brfa, sbr; - - /* calculate the baud rate modulo divisor, sbr*/ - sbr = sourceClockInHz / (baudRate * 16); - - /* check to see if sbr is out of range of register bits */ - if ( (sbr > 0x1FFF) || (sbr < 1) ) - { - /* unsupported baud rate for given source clock input*/ - return kStatus_UART_BaudRateCalculationError; - } - - /* write the sbr value to the BDH and BDL registers*/ - BW_UART_BDH_SBR(baseAddr, (uint8_t)(sbr >> 8)); - BW_UART_BDL_SBR(baseAddr, (uint8_t)sbr); - -#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT - /* determine if a fractional divider is needed to fine tune closer to the desired baud - * each value of brfa is in 1/32 increments, hence the multiply-by-32. */ - brfa = (32*sourceClockInHz/(baudRate*16)) - 32*sbr; - - /* write the brfa value to the register*/ - BW_UART_C4_BRFA(baseAddr, brfa); -#endif - - return kStatus_UART_Success; -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetBaudRateDivisor - * Description : Set the UART baud rate modulo divisor value. - * This function allows the user to program the baud rate divisor directly in - * situations where the divisor value is known. In this case, the user may not want to - * call the UART_HAL_SetBaudRate() function as the divisor is already known to them. - * - *END**************************************************************************/ -void UART_HAL_SetBaudRateDivisor(uint32_t baseAddr, uint16_t baudRateDivisor) -{ - /* check to see if baudRateDivisor is out of range of register bits */ - assert( (baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1) ); - - /* program the sbr (baudRateDivisor) value to the BDH and BDL registers*/ - BW_UART_BDH_SBR(baseAddr, (uint8_t)(baudRateDivisor >> 8)); - BW_UART_BDL_SBR(baseAddr, (uint8_t)baudRateDivisor); -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetTxRxInversionCmd - * Description : Configure the transmit and receive inversion control in UART - * controller. This function allows the user to invert the transmit and receive - * signals, independently. This function should only be called when the UART is - * between transmit and receive packets. - * - *END**************************************************************************/ -void UART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, bool rxInvertEnable, bool txInvertEnable) -{ - /* 0 - receive data not inverted, 1 - receive data inverted */ - BW_UART_S2_RXINV(baseAddr, (uint8_t)rxInvertEnable); - /* 0 - transmit data not inverted, 1 - transmit data inverted*/ - BW_UART_C3_TXINV(baseAddr, (uint8_t)txInvertEnable); -} - -/******************************************************************************* - * UART Transfer Functions - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_Putchar - * Description : This function allows the user to send an 8-bit character from the UART - * data register. - * - *END**************************************************************************/ -void UART_HAL_Putchar(uint32_t baseAddr, uint8_t data) -{ - /* put 8-bit data into the uart data register*/ - /* in addition to sending a char, this function also clears the transmit status flags - * for this uart baseAddr, there is a two step process to clear the - * transmit status flags: - * 1. Read the status register with the status bit set - * 2. write to the data register */ - HW_UART_S1_RD(baseAddr); - HW_UART_D_WR(baseAddr, data); -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_Putchar9 - * Description : This function allows the user to send a 9-bit character from the UART - * data register. - * - *END**************************************************************************/ -void UART_HAL_Putchar9(uint32_t baseAddr, uint16_t data) -{ - uint8_t ninthDataBit; - - ninthDataBit = (data >> 8U) & 0x1U; /* isolate the ninth data bit*/ - - /* put 9-bit data to transmit*/ - /* first, write to the ninth data bit (bit position T8, where T[0:7]=8-bits, T8=9th bit)*/ - BW_UART_C3_T8(baseAddr, ninthDataBit); - - /* in addition to sending a char, this function also clears the transmit status flags - * for this uart baseAddr, there is a two step process to clear the - * transmit status flags: - * 1. Read the status register with the status bit set - * 2. write to the data register */ - HW_UART_S1_RD(baseAddr); - /* write to the data register last since this will trigger transmit complete status flags - * also typecast to uint8_t to match register type */ - HW_UART_D_WR(baseAddr, (uint8_t)data); -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_Getchar - * Description : This function gets a received 8-bit character from the UART data register. - * - *END**************************************************************************/ -void UART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData) -{ - /* get 8-bit data from the uart data register*/ - /* in addition to getting a char, this function also clears the receive status flag RDRF - * along with IDLE, OR, NF, FE, and PF (these can also be cleared in separate functions) - * for this uart baseAddr, there is a two step process to clear the receive - * status flag: - * 1. Read the status register with the status bit set - * 2. read from the data register */ - HW_UART_S1_RD(baseAddr); - /* second, perform a read from the data register */ - *readData = HW_UART_D_RD(baseAddr); /* read 8-bit data from data register*/ -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_Getchar9 - * Description : This function gets a received 9-bit character from the UART data register. - * - *END**************************************************************************/ -void UART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData) -{ - uint16_t temp; - - /* get 9-bit data from the uart data register*/ - /* read ninth data bit and left shift to bit position R8 before reading - * the 8 other data bits R[7:0] - * *readData = (HW_UART_C3(baseAddr).B.R8) << 8; */ - temp = (HW_UART_C3(baseAddr).B.R8); - *readData = temp << 8; - - /* in addition to getting a char, this function also clears the receive status flag RDRF - * along with IDLE, OR, NF, FE, and PF (these can also be cleared in separate functions) - * for this uart baseAddr, there is a two step process to clear the receive - * status flag: - * 1. Read the status register with the status bit set - * 2. read from the data register */ - HW_UART_S1_RD(baseAddr); - /* do last: get 8-bit data from the uart data register, - * will clear certain receive status bits once completed - * need to OR these 8-bits with the ninth bit value above. */ - *readData |= HW_UART_D_RD(baseAddr); /* read 8-bit data from data register*/ -} - -/******************************************************************************* - * UART Interrupts and DMA - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_ConfigureInterrupts - * Description : Configure the UART module interrupts to enable/disable various - * interrupt sources. - * - *END**************************************************************************/ -void UART_HAL_SetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt, bool enable) -{ - uint8_t reg = (uint32_t)interrupt >> UART_SHIFT; - uint32_t temp = 1U << (uint8_t)interrupt; - - switch ( reg ) - { - case 0 : - enable ? HW_UART_BDH_SET(baseAddr, temp) : HW_UART_BDH_CLR(baseAddr, temp); - break; - case 1 : - enable ? HW_UART_C2_SET(baseAddr, temp) : HW_UART_C2_CLR(baseAddr, temp); - break; - case 2 : - enable ? HW_UART_C3_SET(baseAddr, temp) : HW_UART_C3_CLR(baseAddr, temp); - break; -#if FSL_FEATURE_UART_HAS_FIFO - case 3 : - enable ? HW_UART_CFIFO_SET(baseAddr, temp) : HW_UART_CFIFO_CLR(baseAddr, temp); - break; -#endif - default : - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_GetIntMode - * Description : Return whether the UART module interrupts is enabled/disabled. - * - *END**************************************************************************/ -bool UART_HAL_GetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt) -{ - uint8_t reg = (uint32_t)interrupt >> UART_SHIFT; - uint8_t temp = 0; - - switch ( reg ) - { - case 0 : - temp = HW_UART_BDH_RD(baseAddr) >> (uint8_t)(interrupt) & 1U; - break; - case 1 : - temp = HW_UART_C2_RD(baseAddr) >> (uint8_t)(interrupt) & 1U; - break; - case 2 : - temp = HW_UART_C3_RD(baseAddr) >> (uint8_t)(interrupt) & 1U; - break; -#if FSL_FEATURE_UART_HAS_FIFO - case 3 : - temp = HW_UART_CFIFO_RD(baseAddr) >> (uint8_t)(interrupt) & 1U; - break; -#endif - default : - break; - } - return (bool)temp; -} -#if FSL_FEATURE_UART_HAS_DMA_SELECT -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_ConfigureDma - * Description : Configure the UART DMA requests for the Transmitter and Receiver. - * This function allows the user to configure the transmit data register empty flag to - * generate an interrupt request (default) or a DMA request. Similarly, this function - * allows the user to conigure the receive data register full flag to generate an interrupt - * request (default) or a DMA request. - * - *END**************************************************************************/ -void UART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig) -{ - - /* TDMAS configures the transmit data register empty flag, TDRE, to generate interrupt - * or DMA requests if TIE is set. - * NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are - * not asserted when the TDRE flag is set, regardless of the state of TDMAS. - * If UART_C2[TIE] and TDMAS are both set, then UART_C2[TCIE] must be cleared, and UART_D - * must not be written outside of servicing of a DMA request. - * 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted - * to request interrupt service. - * 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted - * to request a DMA transfer. - */ - if (txDmaConfig == 1) - { - /* enable uart to generate transmit DMA request*/ - BW_UART_C5_TDMAS(baseAddr, 1U); /* set TDMAS */ - BW_UART_C2_TCIE(baseAddr, 0U); /* clear TCIE */ - BW_UART_C2_TIE(baseAddr, 1U); /* set TIE */ - } - else - { - /* disable uart transmit DMA request*/ - BW_UART_C2_TIE(baseAddr, 0U); /* clear TIE to disable */ - BW_UART_C5_TDMAS(baseAddr, 0U); /* clear TDMAS to disable */ - } - - /* RDMAS configures the receiver data register full flag, RDRF, to generate interrupt or - * DMA requests if RIEis set. - * NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals are not - * asserted when the RDRF flag is set, regardless of the state of RDMAS. - * 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is - * asserted to request interrupt service. - * 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted - * to request a DMA transfer. - */ - if (rxDmaConfig == 1) - { - /* enable uart to generate receive DMA request*/ - BW_UART_C5_RDMAS(baseAddr, 1U); /* set RDMAS */ - BW_UART_C2_RIE(baseAddr, 1U); /* set RIE */ - } - else - { - /* disable uart receive DMA request*/ - BW_UART_C2_RIE(baseAddr, 0U); /* clear RIE to disable */ - BW_UART_C5_RDMAS(baseAddr, 0U); /* clear RDMAS to disable */ - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_IsTxdmaEnabled - * Description : Get the UART Transmit DMA request configuration setting. - * This function returns to the user the configuration setting of the Transmit DMA request. - * - *END**************************************************************************/ -bool UART_HAL_IsTxdmaEnabled(uint32_t baseAddr) -{ - /* create variable for this to work around MISRA rule 12.4 since this is a volatile value*/ - uint32_t tcieBitStatus; - tcieBitStatus = HW_UART_C2(baseAddr).B.TCIE; - - /* TDMAS configures the transmit data register empty flag, TDRE, to generate interrupt or - * DMA requests if TIE is set. - * NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are - * not asserted when the TDRE flag is set, regardless of the state of TDMAS. - * If UART_C2[TIE] and TDMAS are both set, then UART_C2[TCIE] must be cleared, and UART_D - * must not be written outside of servicing of a DMA request. - * 0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted - * to request interrupt service. - * 1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to - * request a DMA transfer. - */ - if (BR_UART_C5_TDMAS(baseAddr) == 1) - { - /* in order to enable transmit DMA request, TIE must be set and TCIE must be cleared*/ - if ((BR_UART_C2_TIE(baseAddr) == 1) && (tcieBitStatus == 0)) - { - /* UART module is configured to generate TxDMA request*/ - return 1; - } - else - { - /* UART module is NOT configured to generate TxDMA request*/ - return 0; - } - } - else - { - /* UART module is NOT configured to generate TxDMA request*/ - return 0; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_IsRxdmaEnabled - * Description : Get the UART Receive DMA request configuration setting. - * This function returns to the user the configuration setting of the Receive DMA request. - * - *END**************************************************************************/ -bool UART_HAL_IsRxdmaEnabled(uint32_t baseAddr) -{ - /* RDMAS configures the receiver data register full flag, RDRF, to generate interrupt or - * DMA requests if RIE is set. - * NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals are not - * asserted when the RDRF flag is set, regardless of the state of RDMAS. - * 0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted - * to requestinterrupt service. - * 1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to - * request a DMA transfer. - */ - if (BR_UART_C5_RDMAS(baseAddr) == 1) - { - /* enable uart to generate receive DMA request*/ - if (BR_UART_C2_RIE(baseAddr) == 1) - { - /* UART module is configured to generate RxDMA request*/ - return 1; - } - else - { - /* UART module is NOT configured to generate RxDMA request*/ - return 0; - } - } - else - { - /* UART module is NOT configured to generate RxDMA request*/ - return 0; - } -} -#endif -/******************************************************************************* - * UART UART Status Flags - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_GetStatusFlag - * Description : Get UART status flag states. - * - *END**************************************************************************/ -bool UART_HAL_GetStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag) -{ - uint8_t reg = (uint32_t)statusFlag >> UART_SHIFT; - uint8_t temp = 0; - - switch ( reg ) - { - case 0 : - temp = HW_UART_S1_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U; - break; - case 1 : - temp = HW_UART_S2_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U; - break; -#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS - case 2 : - temp = HW_UART_ED_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U; - break; -#endif -#if FSL_FEATURE_UART_HAS_FIFO - case 3 : - temp = HW_UART_SFIFO_RD(baseAddr) >> (uint8_t)(statusFlag) & 1U; - break; -#endif - default : - break; - } - return (bool)temp; -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_ClearStatusFlag - * Description : Clear an individual and specific UART status flag. - * This function allows the user to clear an individual and specific UART status flag. Refer to - * structure definition uart_status_flag_t for list of status bits. - * - *END**************************************************************************/ -uart_status_t UART_HAL_ClearStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag) -{ - uart_status_t returnCode; /* return code variable */ - returnCode = kStatus_UART_Success; /* default return code, unless changed by error condition*/ - - /* clear the desired, individual status flag as passed in through statusFlag */ - switch(statusFlag) - { - case kUartTxDataRegEmpty: - /* This flag is cleared automatically by other uart operations and - * cannot be manually cleared, return error code - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - - case kUartTxComplete: - /* This flag is cleared automatically by other uart operations and - * cannot be manually cleared, return error code - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - - case kUartRxDataRegFull: - /* This flag is cleared automatically by other uart operations and - * cannot be manually cleared, return error code - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - - case kUartIdleLineDetect: - /* to clear the status is a two-step process: - * first, read S1 register with the status flag set - */ - HW_UART_S1_RD(baseAddr); - /* second, read the data register*/ - HW_UART_D_RD(baseAddr); - break; - - case kUartRxOverrun: - /* to clear the status is a two-step process: - * first, read S1 register with the status flag set - */ - HW_UART_S1_RD(baseAddr); - /* second, read the data register*/ - HW_UART_D_RD(baseAddr); - break; - - case kUartNoiseDetect: - /* to clear the status is a two-step process: - * first, read S1 register with the status flag set - */ - HW_UART_S1_RD(baseAddr); - /* second, read the data register*/ - HW_UART_D_RD(baseAddr); - break; - - case kUartFrameErr: - /* to clear the status is a two-step process: - * first, read S1 register with the status flag set - */ - HW_UART_S1_RD(baseAddr); - /* second, read the data register*/ - HW_UART_D_RD(baseAddr); - break; - - case kUartParityErr: - /* to clear the status is a two-step process: - * first, read S1 register with the status flag set - */ - HW_UART_S1_RD(baseAddr); - /* second, read the data register*/ - HW_UART_D_RD(baseAddr); - break; - - case kUartLineBreakDetect: - /* write one to clear status flag */ - HW_UART_S2_SET(baseAddr, BM_UART_S2_LBKDIF); - break; - - case kUartRxActiveEdgeDetect: - /* write one to clear status flag */ - HW_UART_S2_SET(baseAddr, BM_UART_S2_RXEDGIF); - break; - - case kUartRxActive: - /* This flag is cleared automatically by other uart operations and - * cannot be manually cleared, return error code - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - -#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS - case kUartNoiseInCurrentWord: - /* This flag is not clearable, it simply reflects the status in the - * current data word and changes with each new data word - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - - case kUartParityErrInCurrentWord: - /* This flag is not clearable, it simply reflects the status in the - * current data word and changes with each new data word - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; -#endif -#if FSL_FEATURE_UART_HAS_FIFO - case kUartTxBuffEmpty: - /* This flag is not clearable, it simply reflects the current - * status of the buffer/FIFO - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - - case kUartRxBuffEmpty: - /* This flag is not clearable, it simply reflects the current - * status of the buffer/FIFO - */ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - - case kUartTxBuffOverflow: - /* write one to clear status flag */ - HW_UART_SFIFO_SET(baseAddr, BM_UART_SFIFO_TXOF); - break; - - case kUartRxBuffUnderflow: - /* write one to clear status flag */ - HW_UART_SFIFO_SET(baseAddr, BM_UART_SFIFO_RXUF); - break; -#endif - default: /* catch inputs that are not recognized*/ - returnCode = kStatus_UART_ClearStatusFlagError; - break; - } - - return (returnCode); -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_ClearAllNonAutoclearStatusFlags - * Description : Clear ALL of the UART status flags. - * This function tries to clear all of the UART status flags. In some cases, some of the status - * flags may not get cleared because of the condition that set the flag may still exist. - * - *END**************************************************************************/ -void UART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr) -{ - /* clear the status flags that can be manually cleared - * note, some flags are automatically cleared and cannot be cleared automatically - */ - UART_HAL_ClearStatusFlag(baseAddr, kUartIdleLineDetect); - UART_HAL_ClearStatusFlag(baseAddr, kUartRxOverrun); - UART_HAL_ClearStatusFlag(baseAddr, kUartNoiseDetect); - UART_HAL_ClearStatusFlag(baseAddr, kUartFrameErr); - UART_HAL_ClearStatusFlag(baseAddr, kUartParityErr); - UART_HAL_ClearStatusFlag(baseAddr, kUartLineBreakDetect); - UART_HAL_ClearStatusFlag(baseAddr, kUartRxActiveEdgeDetect); -#if FSL_FEATURE_UART_HAS_FIFO - UART_HAL_ClearStatusFlag(baseAddr, kUartTxBuffOverflow); - UART_HAL_ClearStatusFlag(baseAddr, kUartRxBuffUnderflow); -#endif -} - -/******************************************************************************* - * UART FIFO Configurations - ******************************************************************************/ -#if FSL_FEATURE_UART_HAS_FIFO -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetTxFifo - * Description : Enable or disable the UART transmit FIFO. - * This function allows the user to enable or disable the UART transmit FIFO. - * It is required that the transmitter/receiver should be disabled before calling this - * function and when the FIFO is empty. Additionally, TXFLUSH and RXFLUSH commands - * should be issued after calling this function. - * - *END**************************************************************************/ -uart_status_t UART_HAL_SetTxFifoCmd(uint32_t baseAddr, bool enable) -{ - /* before enabling the tx fifo, UARTx_C2[TE] (transmitter) and - * UARTx_C2[RE] (receiver) must be disabled - * if not, return an error code */ - uint8_t txEnable = BR_UART_C2_TE(baseAddr); - uint8_t rxEnable = BR_UART_C2_RE(baseAddr); - - if (txEnable || rxEnable) - { - return kStatus_UART_TxOrRxNotDisabled; - } - else - { - BW_UART_PFIFO_TXFE(baseAddr, enable); - return kStatus_UART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetRxFifoCmd - * Description : Enable or disable the UART receive FIFO. - * This function allows the user to enable or disable the UART receive FIFO. - * It is required that the transmitter/receiver should be disabled before calling - * this function and when the FIFO is empty. Additionally, TXFLUSH and RXFLUSH - * commands should be issued after calling this function. - * - *END**************************************************************************/ -uart_status_t UART_HAL_SetRxFifoCmd(uint32_t baseAddr, bool enable) -{ - /* before enabling the rx fifo, UARTx_C2[TE] (transmitter) and - * UARTx_C2[RE] (receiver) must be disabled - * if not, return an error code */ - uint8_t txEnable = BR_UART_C2_TE(baseAddr); - uint8_t rxEnable = BR_UART_C2_RE(baseAddr); - - if (txEnable || rxEnable) - { - return kStatus_UART_TxOrRxNotDisabled; - } - else - { - BW_UART_PFIFO_RXFE(baseAddr, enable); - return kStatus_UART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_FlushTxFifo - * Description : Flush the UART transmit FIFO. - * This function allows you to flush the UART transmit FIFO for a particular modulei - * baseAddr. Flushing the FIFO may result in data loss. It is recommended that the - * transmitter should be disabled before calling this function. - * - *END**************************************************************************/ -uart_status_t UART_HAL_FlushTxFifo(uint32_t baseAddr) -{ - /* in order to flush the tx fifo, UARTx_C2[TE] (transmitter) must be disabled - * if not, return an error code */ - if (BR_UART_C2_TE(baseAddr) != 0) - { - return kStatus_UART_TxNotDisabled; - } - else - { - /* Set the bit to flush fifo*/ - BW_UART_CFIFO_TXFLUSH(baseAddr, 1U); - return kStatus_UART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_FlushRxFifo - * Description : Flush the UART receive FIFO. - * This function allows you to flush the UART receive FIFO for a particular module - * baseAddr. Flushing the FIFO may result in data loss. It is recommended that the - * receiver should be disabled before calling this function. - * - *END**************************************************************************/ -uart_status_t UART_HAL_FlushRxFifo(uint32_t baseAddr) -{ - /* in order to flush the rx fifo, UARTx_C2[RE] (receiver) must be disabled - * if not, return an error code. */ - if (BR_UART_C2_RE(baseAddr) != 0) - { - return kStatus_UART_RxNotDisabled; - } - else - { - /* Set the bit to flush fifo*/ - BW_UART_CFIFO_RXFLUSH(baseAddr, 1U); - return kStatus_UART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetTxFifoWatermark - * Description : Set the UART transmit FIFO watermark value. - * Programming the transmit watermark should be done when UART the transmitter is - * disabled and the value must be set less than the size obtained from - * UART_HAL_GetTxFifoSize. - * - *END**************************************************************************/ -uart_status_t UART_HAL_SetTxFifoWatermark(uint32_t baseAddr, uint8_t watermark) -{ - /* in order to set the tx watermark, UARTx_C2[TE] (transmitter) must be disabled - * if not, return an error code - */ - if (BR_UART_C2_TE(baseAddr) != 0) - { - return kStatus_UART_TxNotDisabled; - } - else - { - /* Programming the transmit watermark should be done when the transmitter is - * disabled and the value must be set less than the size given in - * PFIFO[TXFIFOSIZE] */ - HW_UART_TWFIFO_WR(baseAddr, watermark); - return kStatus_UART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetRxFifoWatermark - * Description : Set the UART receive FIFO watermark value. - * Programming the receive watermark should be done when the receiver is disabled - * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize - * and greater than zero. - * - *END**************************************************************************/ -uart_status_t UART_HAL_SetRxFifoWatermark(uint32_t baseAddr, uint8_t watermark) -{ - /* in order to set the rx watermark, UARTx_C2[RE] (receiver) must be disabled - * if not, return an error code. */ - if (BR_UART_C2_RE(baseAddr) != 0) - { - return kStatus_UART_RxNotDisabled; - } - else - { - /* Programming the receive watermark should be done when the receiver is - * disabled and the value must be set less than the size given in - * PFIFO[RXFIFOSIZE] and greater than zero. */ - HW_UART_RWFIFO_WR(baseAddr, watermark); - return kStatus_UART_Success; - } -} -#endif /* FSL_FEATURE_UART_HAS_FIFO*/ - -/******************************************************************************* - * UART Special Feature Configurations - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_PutReceiverInStandbyMode - * Description : Place the UART receiver in standby mode. - * This function, when called, will place the UART receiver into standby mode. - * In some UART baseAddrs, there is a condition that must be met before placing rx in standby mode. - * Before placing UART in standby, you need to first determine if receiver is set to - * wake on idle and if receiver is already in idle state. Per ref manual: - * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently - * not idle. - * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel - * is already idle, it is possible that the UART will discard data since data must be received - * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to reasserted. - * - *END**************************************************************************/ -uart_status_t UART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr) -{ - /* In some uart baseAddrs, there is a condition that must be met before placing - * rx in standby mode. - * Before placing uart in standby, need to first determine if receiver is set to - * wake on idle and if receiver is already in idle state. Per ref manual: - * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is - * currently not idle. - * This can be determined by the S2[RAF] flag. If set to wake up an IDLE event and - * the channel is already idle, it is possible that the UART will discard data since data - * must be received (or a LIN break detect) after an IDLE is detected before IDLE is - * allowed to reasserted. - */ - uart_wakeup_method_t rxWakeMethod; - bool uart_current_rx_state; - - /* see if wake is set for idle or */ - rxWakeMethod = UART_HAL_GetReceiverWakeupMethod(baseAddr); - uart_current_rx_state = UART_HAL_GetStatusFlag(baseAddr, kUartRxActive); - - /* if both rxWakeMethod is set for idle and current rx state is idle, don't put in standy*/ - if ((rxWakeMethod == kUartIdleLineWake) && (uart_current_rx_state == 0)) - { - return kStatus_UART_RxStandbyModeError; - } - else - { - /* set the RWU bit to place receiver into standby mode*/ - HW_UART_C2_SET(baseAddr, BM_UART_C2_RWU); - return kStatus_UART_Success; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_ConfigIdleLineDetect - * Description : Configure the operation options of the UART idle line detect. - * This function allows the user to configure the UART idle-line detect operation. There are two - * separate operations for the user to configure, the idle line bit-count start and the receive - * wake up affect on IDLE status bit. The user will pass in a stucture of type - * uart_idle_line_config_t. - * - *END**************************************************************************/ -void UART_HAL_ConfigIdleLineDetect(uint32_t baseAddr, uint8_t idleLine, uint8_t rxWakeIdleDetect) -{ - /* Configure the idle line detection configuration as follows: - * configure the ILT to bit count after start bit or stop bit - * configure RWUID to set or not set IDLE status bit upon detection of - * an idle character when recevier in standby */ - BW_UART_C1_ILT(baseAddr, idleLine); - BW_UART_S2_RWUID(baseAddr, rxWakeIdleDetect); -} -#if FSL_FEATURE_UART_HAS_ADDRESS_MATCHING -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetMatchAddress - * Description : Configure the UART match address mode control operation. (Note: Feature - * available on select UART baseAddrs) - * The function allows the user to configure the UART match address control operation. The user - * has the option to enable the match address mode and to program the match address value. There - * are two match address modes, each with it's own enable and programmable match address value. - * - *END**************************************************************************/ -void UART_HAL_SetMatchAddress( uint32_t baseAddr, bool matchAddrMode1, bool matchAddrMode2, - uint8_t matchAddrValue1, uint8_t matchAddrValue2) -{ - BW_UART_C4_MAEN1(baseAddr, matchAddrMode1); /* Match Address Mode Enable 1 */ - BW_UART_C4_MAEN2(baseAddr, matchAddrMode2); /* Match Address Mode Enable 2 */ - HW_UART_MA1_WR(baseAddr, matchAddrValue1); /* match address register 1 */ - HW_UART_MA2_WR(baseAddr, matchAddrValue2); /* match address register 2 */ -} -#endif - -#if FSL_FEATURE_UART_HAS_IR_SUPPORT -/*FUNCTION********************************************************************** - * - * Function Name : UART_HAL_SetInfraredOperation - * Description : Configure the UART infrared operation. - * The function allows the user to enable or disable the UART infrared (IR) operation - * and to configure the IR pulse width. - * - *END**************************************************************************/ -void UART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable, - uart_ir_tx_pulsewidth_t pulseWidth) -{ - /* enable or disable infrared */ - BW_UART_IR_IREN(baseAddr, enable); - /* configure the narrow pulse width of the IR pulse */ - BW_UART_IR_TNP(baseAddr, pulseWidth); -} -#endif /* FSL_FEATURE_UART_HAS_IR_SUPPORT */ - - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h deleted file mode 100644 index 6f1b50063e6..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h +++ /dev/null @@ -1,1333 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_UART_HAL_H__ -#define __FSL_UART_HAL_H__ - -#include -#include -#include -#include "fsl_uart_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup uart_hal - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define UART_SHIFT (8U) - -/*! @brief Error codes for the UART driver. */ -typedef enum _uart_status -{ - kStatus_UART_Success = 0x0U, - kStatus_UART_BaudRateCalculationError = 0x1U, - kStatus_UART_RxStandbyModeError = 0x2U, - kStatus_UART_ClearStatusFlagError = 0x3U, - kStatus_UART_TxNotDisabled = 0x4U, - kStatus_UART_RxNotDisabled = 0x5U, - kStatus_UART_TxOrRxNotDisabled = 0x6U, - kStatus_UART_TxBusy = 0x7U, - kStatus_UART_RxBusy = 0x8U, - kStatus_UART_NoTransmitInProgress = 0x9U, - kStatus_UART_NoReceiveInProgress = 0xAU, - kStatus_UART_Timeout = 0xBU, - kStatus_UART_Initialized = 0xCU, - kStatus_UART_RxCallBackEnd = 0xDU -} uart_status_t; - -/*! - * @brief UART number of stop bits. - * - * These constants define the number of allowable stop bits to configure in a UART baseAddr. - */ -typedef enum _uart_stop_bit_count { - kUartOneStopBit = 0U, /*!< one stop bit */ - kUartTwoStopBit = 1U, /*!< two stop bits */ -} uart_stop_bit_count_t; - -/*! - * @brief UART parity mode. - * - * These constants define the UART parity mode options: disabled or enabled of type even or odd. - */ -typedef enum _uart_parity_mode { - kUartParityDisabled = 0x0U, /*!< parity disabled */ - kUartParityEven = 0x2U, /*!< parity enabled, type even, bit setting: PE|PT = 10 */ - kUartParityOdd = 0x3U, /*!< parity enabled, type odd, bit setting: PE|PT = 11 */ -} uart_parity_mode_t; - -/*! - * @brief UART number of bits in a character. - * - * These constants define the number of allowable data bits per UART character. Note, check the - * UART documentation to determine if the desired UART baseAddr supports the desired number - * of data bits per UART character. - */ -typedef enum _uart_bit_count_per_char { - kUart8BitsPerChar = 0U, /*!< 8-bit data characters */ - kUart9BitsPerChar = 1U, /*!< 9-bit data characters */ -} uart_bit_count_per_char_t; - -/*! - * @brief UART operation configuration constants. - * - * This provides constants for UART operational states: "operates normally" - * or "stops/ceases operation" - */ -typedef enum _uart_operation_config { - kUartOperates = 0U, /*!< UART continues to operate normally */ - kUartStops = 1U, /*!< UART ceases operation */ -} uart_operation_config_t; - -/*! @brief UART receiver source select mode. */ -typedef enum _uart_receiver_source { - kUartLoopBack = 0U, /*!< Internal loop back mode. */ - kUartSingleWire = 1U,/*!< Single wire mode. */ -} uart_receiver_source_t ; - -/*! - * @brief UART wakeup from standby method constants. - * - * This provides constants for the two UART wakeup methods: idle-line or address-mark. - */ -typedef enum _uart_wakeup_method { - kUartIdleLineWake = 0U, /*!< The idle-line wakes UART receiver from standby */ - kUartAddrMarkWake = 1U, /*!< The address-mark wakes UART receiver from standby */ -} uart_wakeup_method_t; - -/*! - * @brief UART idle-line detect selection types. - * - * This provides constants for the UART idle character bit-count start: either after start or - * stop bit. - */ -typedef enum _uart_idle_line_select { - kUartIdleLineAfterStartBit = 0U, /*!< UART idle character bit count start after start bit */ - kUartIdleLineAfterStopBit = 1U, /*!< UART idle character bit count start after stop bit */ -} uart_idle_line_select_t; - -/*! - * @brief UART break character length settings for transmit/detect. - * - * This provides constants for the UART break character length for both transmission and detection - * purposes. Note that the actual maximum bit times may vary depending on the UART baseAddr. - */ -typedef enum _uart_break_char_length { - kUartBreakChar10BitMinimum = 0U, /*!< UART break char length 10 bit times (if M = 0, SBNS = 0) or - 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, - SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */ - kUartBreakChar13BitMinimum = 1U, /*!< UART break char length 13 bit times (if M = 0, SBNS = 0) or - 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, - SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1) */ -} uart_break_char_length_t; - -/*! - * @brief UART single-wire mode transmit direction. - * - * This provides constants for the UART transmit direction when configured for single-wire mode. - * The transmit line TXDIR is either an input or output. - */ -typedef enum _uart_singlewire_txdir { - kUartSinglewireTxdirIn = 0U, /*!< UART Single-Wire mode TXDIR input */ - kUartSinglewireTxdirOut = 1U, /*!< UART Single-Wire mode TXDIR output */ -} uart_singlewire_txdir_t; - -/*! - * @brief UART infrared transmitter pulse width options. - * - * This provides constants for the UART infrared (IR) pulse widths. Options include 3/16, 1/16 - * 1/32, and 1/4 pulse widths. - */ -typedef enum _uart_ir_tx_pulsewidth { - kUartIrThreeSixteenthsWidth = 0U, /*!< 3/16 pulse */ - kUartIrOneSixteenthWidth = 1U, /*!< 1/16 pulse */ - kUartIrOneThirtysecondsWidth = 2U, /*!< 1/32 pulse */ - kUartIrOneFourthWidth = 3U, /*!< 1/4 pulse */ -} uart_ir_tx_pulsewidth_t; - -/*! - * @brief UART status flags. - * - * This provides constants for the UART status flags for use in the UART functions. - */ -typedef enum _uart_status_flag { - kUartTxDataRegEmpty = 0U << UART_SHIFT | BP_UART_S1_TDRE, /*!< Tx data register empty flag, sets when Tx buffer is empty */ - kUartTxComplete = 0U << UART_SHIFT | BP_UART_S1_TC, /*!< Transmission complete flag, sets when transmission activity complete */ - kUartRxDataRegFull = 0U << UART_SHIFT | BP_UART_S1_RDRF, /*!< Rx data register full flag, sets when the receive data buffer is full */ - kUartIdleLineDetect = 0U << UART_SHIFT | BP_UART_S1_IDLE, /*!< Idle line detect flag, sets when idle line detected */ - kUartRxOverrun = 0U << UART_SHIFT | BP_UART_S1_OR, /*!< Rxr Overrun, sets when new data is received before data is read from receive register */ - kUartNoiseDetect = 0U << UART_SHIFT | BP_UART_S1_NF, /*!< Rxr takes 3 samples of each received bit. If any of these samples differ, noise flag sets */ - kUartFrameErr = 0U << UART_SHIFT | BP_UART_S1_FE, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ - kUartParityErr = 0U << UART_SHIFT | BP_UART_S1_PF, /*!< If parity enabled, sets upon parity error detection */ - kUartLineBreakDetect = 1U << UART_SHIFT | BP_UART_S2_LBKDIF, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ - kUartRxActiveEdgeDetect = 1U << UART_SHIFT | BP_UART_S2_RXEDGIF, /*!< Rx pin active edge interrupt flag, sets when active edge detected */ - kUartRxActive = 1U << UART_SHIFT | BP_UART_S2_RAF, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ -#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS - kUartNoiseInCurrentWord = 2U << UART_SHIFT | BP_UART_ED_NOISY, /*!< NOISY bit, sets if noise detected in current data word */ - kUartParityErrInCurrentWord = 2U << UART_SHIFT | BP_UART_ED_PARITYE, /*!< PARITYE bit, sets if noise detected in current data word */ -#endif -#if FSL_FEATURE_UART_HAS_FIFO - kUartTxBuffEmpty = 3U << UART_SHIFT | BP_UART_SFIFO_TXEMPT, /*!< TXEMPT bit, sets if Tx buffer is empty */ - kUartRxBuffEmpty = 3U << UART_SHIFT | BP_UART_SFIFO_RXEMPT, /*!< RXEMPT bit, sets if Rx buffer is empty */ - kUartTxBuffOverflow = 3U << UART_SHIFT | BP_UART_SFIFO_TXOF, /*!< TXOF bit, sets if Tx buffer overflow occurred */ - kUartRxBuffUnderflow = 3U << UART_SHIFT | BP_UART_SFIFO_RXUF, /*!< RXUF bit, sets if receive buffer underflow occurred */ -#endif -} uart_status_flag_t; - -/*! - * @brief UART interrupt configuration structure, default settings are 0 (disabled). - * - * This structure contains the settings for all of the UART interrupt configurations. - */ -typedef enum _uart_interrupt { - kUartIntLinBreakDetect = 0U << UART_SHIFT | BP_UART_BDH_LBKDIE, /*!< LIN break detect. */ - kUartIntRxActiveEdge = 0U << UART_SHIFT | BP_UART_BDH_RXEDGIE, /*!< RX Active Edge. */ - kUartIntTxDataRegEmpty = 1U << UART_SHIFT | BP_UART_C2_TIE, /*!< Transmit data register empty. */ - kUartIntTxComplete = 1U << UART_SHIFT | BP_UART_C2_TCIE, /*!< Transmission complete. */ - kUartIntRxDataRegFull = 1U << UART_SHIFT | BP_UART_C2_RIE, /*!< Receiver data register full. */ - kUartIntIdleLine = 1U << UART_SHIFT | BP_UART_C2_ILIE, /*!< Idle line. */ - kUartIntRxOverrun = 2U << UART_SHIFT | BP_UART_C3_ORIE, /*!< Receiver Overrun. */ - kUartIntNoiseErrFlag = 2U << UART_SHIFT | BP_UART_C3_NEIE, /*!< Noise error flag. */ - kUartIntFrameErrFlag = 2U << UART_SHIFT | BP_UART_C3_FEIE, /*!< Framing error flag. */ - kUartIntParityErrFlag = 2U << UART_SHIFT | BP_UART_C3_PEIE, /*!< Parity error flag. */ -#if FSL_FEATURE_UART_HAS_FIFO - kUartIntTxFifoOverflow = 3U << UART_SHIFT | BP_UART_CFIFO_TXOFE, /*!< TX FIFO Overflow. */ - kUartIntRxFifoUnderflow = 3U << UART_SHIFT | BP_UART_CFIFO_RXUFE, /*!< RX FIFO Underflow. */ -#endif -} uart_interrupt_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name UART Common Configurations - * @{ - */ - -/*! - * @brief Initializes the UART controller. - * - * This function initializes the module to a known state. - * - * @param baseAddr UART module base address. - */ -void UART_HAL_Init(uint32_t baseAddr); - -/*! - * @brief Enables the UART transmitter. - * - * This function allows the user to enable the UART transmitter. - * - * @param baseAddr UART module base address. - */ -static inline void UART_HAL_EnableTransmitter(uint32_t baseAddr) -{ - BW_UART_C2_TE(baseAddr, 1U); -} - -/*! - * @brief Disables the UART transmitter. - * - * This function allows the user to disable the UART transmitter. - * - * @param baseAddr UART module base address. - */ -static inline void UART_HAL_DisableTransmitter(uint32_t baseAddr) -{ - BW_UART_C2_TE(baseAddr, 0U); -} - -/*! - * @brief Gets the UART transmitter enabled/disabled configuration setting. - * - * This function allows the user to get the setting of the UART transmitter. - * - * @param baseAddr UART module base address. - * @return The state of UART transmitter enable(true)/disable(false) setting. - */ -static inline bool UART_HAL_IsTransmitterEnabled(uint32_t baseAddr) -{ - return (bool)BR_UART_C2_TE(baseAddr); -} - -/*! - * @brief Enables the UART receiver. - * - * This function allows the user to enable the UART receiver. - * - * @param baseAddr UART module base address. - */ -static inline void UART_HAL_EnableReceiver(uint32_t baseAddr) -{ - BW_UART_C2_RE(baseAddr, 1U); -} - -/*! - * @brief Disables the UART receiver. - * - * This function allows the user to disable the UART receiver. - * - * @param baseAddr UART module base address. - */ -static inline void UART_HAL_DisableReceiver(uint32_t baseAddr) -{ - BW_UART_C2_RE(baseAddr, 0U); -} - -/*! - * @brief Gets the UART receiver enabled/disabled configuration setting. - * - * This function allows the user to get the setting of the UART receiver. - * - * @param baseAddr UART module base address. - * @return The state of UART receiver enable(true)/disable(false) setting. - */ -static inline bool UART_HAL_IsReceiverEnabled(uint32_t baseAddr) -{ - return (bool)BR_UART_C2_RE(baseAddr); -} - -/*! - * @brief Configures the UART baud rate. - * - * This function programs the UART baud rate to the desired value passed in by the user. The user - * must also pass in the module source clock so that the function can calculate the baud - * rate divisors to their appropriate values. - * In some UART baseAddrs it is required that the transmitter/receiver be disabled - * before calling this function. - * Generally this is applied to all UARTs to ensure safe operation. - * - * @param baseAddr UART module base address. - * @param sourceClockInHz UART source input clock in Hz. - * @param baudRate UART desired baud rate. - * @return An error code or kStatus_UART_Success - */ -uart_status_t UART_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t baudRate); - -/*! - * @brief Sets the UART baud rate modulo divisor value. - * - * This function allows the user to program the baud rate divisor directly in situations - * where the divisor value is known. In this case, the user may not want to call the - * UART_HAL_SetBaudRate() function, as the divisor is already known. - * - * @param baseAddr UART module base address. - * @param baudRateDivisor The baud rate modulo division "SBR" value. - */ -void UART_HAL_SetBaudRateDivisor(uint32_t baseAddr, uint16_t baudRateDivisor); - -#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT -/*! - * @brief Sets the UART baud rate fine adjust. (Note: Feature available on select - * UART baseAddrs used in conjunction with baud rate programming) - * - * This function, which programs the baud rate fine adjust, is used together with - * programming the baud rate modulo divisor in situations where these divisors value are known. - * In this case, the user may not want to call the UART_HAL_SetBaudRate() function, as the - * divisors are already known. - * - * @param baseAddr UART module base address. - * @param baudFineAdjust Value of 5-bit field used to add more timing resolution to average - * baud rate frequency is 1/32 increments. - */ -static inline void UART_HAL_SetBaudRateFineAdjust(uint32_t baseAddr, uint8_t baudFineAdjust) -{ - assert(baudFineAdjust < 0x1F); - BW_UART_C4_BRFA(baseAddr, baudFineAdjust); -} -#endif - -/*! - * @brief Configures the number of bits per character in the UART controller. - * - * This function allows the user to configure the number of bits per character according to the - * typedef uart_bit_count_per_char_t. - * - * @param baseAddr UART module base address. - * @param bitCountPerChar Number of bits per char (8, 9, or 10, depending on the UART baseAddr). - */ -static inline void UART_HAL_SetBitCountPerChar(uint32_t baseAddr, - uart_bit_count_per_char_t bitCountPerChar) -{ - /* config 8- (M=0) or 9-bits (M=1) */ - BW_UART_C1_M(baseAddr, bitCountPerChar); -} - -/*! - * @brief Configures the parity mode in the UART controller. - * - * This function allows the user to configure the parity mode of the UART controller to disable - * it or enable it for even parity or for odd parity. - * - * @param baseAddr UART module base address. - * @param parityMode Parity mode setting (enabled, disable, odd, even - see - * parity_mode_t struct). - */ -static inline void UART_HAL_SetParityMode(uint32_t baseAddr, uart_parity_mode_t parityMode) -{ - HW_UART_C1_SET(baseAddr, parityMode); -} - -#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT -/*! - * @brief Configures the number of stop bits in the UART controller. - * - * This function allows the user to configure the number of stop bits in the UART controller - * to be one or two stop bits. - * - * @param baseAddr UART module base address. - * @param stopBitCount Number of stop bits setting (1 or 2 - see uart_stop_bit_count_t struct). - * @return An error code (an unsupported setting in some UARTs) or kStatus_UART_Success. - */ -static inline void UART_HAL_SetStopBitCount(uint32_t baseAddr, uart_stop_bit_count_t stopBitCount) -{ - BW_UART_BDH_SBNS(baseAddr, stopBitCount); -} -#endif - -/*! - * @brief Configures the transmit and receive inversion control in UART controller. - * - * This function allows the user to invert the transmit and receive signals, independently. - * This function should only be called when the UART is between transmit and receive packets. - * - * @param baseAddr UART module base address. - * @param rxInvert Enable (true) or disable (false) receive inversion. - * @param txInvert Enable (true) or disable (false) transmit inversion. - */ -void UART_HAL_SetTxRxInversionCmd(uint32_t baseAddr, bool rxInvertEnable, bool txInvertEnable); - -/*@}*/ - -/*! - * @name UART Interrupts and DMA - * @{ - */ - -/*! - * @brief Configures the UART module interrupts to enable/disable various interrupt sources. - * - * @param baseAddr UART module base address. - * @param interrupt UART interrupt configuration data. - * @param enable true: enable, false: disable. - */ -void UART_HAL_SetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt, bool enable); - -/*! - * @brief Returns whether the UART module interrupts is enabled/disabled. - * - * @param baseAddr UART module base address. - * @param interrupt UART interrupt configuration data. - * @return true: enable, false: disable. - */ -bool UART_HAL_GetIntMode(uint32_t baseAddr, uart_interrupt_t interrupt); - -/*! - * @brief Enables or disables the tx_data_register_empty_interrupt. - * - * @param baseAddr UART module base address. - * @param enable true: enable, false: disable. - */ -static inline void UART_HAL_SetTxDataRegEmptyIntCmd(uint32_t baseAddr, bool enable) -{ - /* transmit interrupt enable for TDRE (transmit data register empty)*/ - BW_UART_C2_TIE(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Gets the configuration of the tx_data_register_empty_interrupt enable setting. - * - * @param baseAddr UART module base address. - * @return setting of the interrupt enable bit. - */ -static inline bool UART_HAL_GetTxDataRegEmptyIntCmd(uint32_t baseAddr) -{ - /* return interrupt enable condition of TIE */ - return (bool)BR_UART_C2_TIE(baseAddr); -} - -/*! - * @brief Disables the rx_data_register_full_interrupt. - * - * @param baseAddr UART module base address. - * @param enable true: enable, false: disable. - */ -static inline void UART_HAL_SetRxDataRegFullIntCmd(uint32_t baseAddr, bool enable) -{ - /* receiver interrupt enable for receiver data register full (RDRF)*/ - BW_UART_C2_RIE(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Gets the configuration of the rx_data_register_full_interrupt enable setting. - * - * @param baseAddr UART module base address. - * @return Bit setting of the interrupt enable bit. - */ -static inline bool UART_HAL_GetRxDataRegFullIntCmd(uint32_t baseAddr) -{ - /* return interrupt enable condition of RIE */ - return (bool)BR_UART_C2_RIE(baseAddr); -} - -/*! - * @brief Configures the UART DMA requests for the Transmitter and Receiver. - * - * This function allows the user to configure the transmit data register empty flag to - * generate an interrupt request (default) or a DMA request. Similarly, this function - * allows the user to configure the receive data register full flag to generate an interrupt - * request (default) or a DMA request. - * - * @param baseAddr UART module base address. - * @param txDmaConfig Transmit DMA request configuration setting (enable: true /disable: false). - * @param rxDmaConfig Receive DMA request configuration setting (enable: true/disable: false). - */ -void UART_HAL_ConfigureDma(uint32_t baseAddr, bool txDmaConfig, bool rxDmaConfig); - -/*! - * @brief Gets the UART Transmit DMA request configuration setting. - * - * This function returns the configuration setting of the Transmit DMA request. - * - * @param baseAddr UART module base address. - * @return Transmit DMA request configuration setting (enable: true /disable: false). - */ -bool UART_HAL_IsTxdmaEnabled(uint32_t baseAddr); - -/*! - * @brief Gets the UART Receive DMA request configuration setting. - * - * This function returns the configuration setting of the Receive DMA request. - * - * @param baseAddr UART module base address. - * @return Receive DMA request configuration setting (enable: true /disable: false). - */ -bool UART_HAL_IsRxdmaEnabled(uint32_t baseAddr); - -/*! - * @brief Get UART tx/rx data register address. - * - * This function is used for DMA transfer. - * - * @return UART tx/rx data register address. - */ -static inline uint32_t UART_HAL_GetDataRegAddr(uint32_t baseAddr) -{ - return (uint32_t)HW_UART_D_ADDR(baseAddr); -} - -/*@}*/ - -/*! - * @name UART Transfer Functions - * @{ - */ - -/*! - * @brief This function allows the user to send an 8-bit character from the UART data register. - * - * @param baseAddr UART module base address. - * @param data The data to send of size 8-bit. - */ -void UART_HAL_Putchar(uint32_t baseAddr, uint8_t data); - -/*! - * @brief This function allows the user to send a 9-bit character from the UART data register. - * - * @param baseAddr UART module base address. - * @param data The data to send of size 9-bit. - */ -void UART_HAL_Putchar9(uint32_t baseAddr, uint16_t data); - -/*! - * @brief This function gets a received 8-bit character from the UART data register. - * - * @param baseAddr UART module base address. - * @param readData The received data read from data register of size 8-bit. - */ -void UART_HAL_Getchar(uint32_t baseAddr, uint8_t *readData); - -/*! - * @brief This function gets a received 9-bit character from the UART data register. - * - * @param baseAddr UART module base address. - * @param readData The received data read from data register of size 9-bit. - */ -void UART_HAL_Getchar9(uint32_t baseAddr, uint16_t *readData); - -#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS -/*! - * @brief Configures the UART bit 10 (if enabled) or bit 9 (if disabled) as the parity bit in the - * serial transmission. - * - * This function configures bit 10 or bit 9 to be the parity bit. To configure bit 10 as the parity - * bit, the function sets UARTx_C4[M10]; it also sets UARTx_C1[M] and UARTx_C1[PE] as required. - * - * @param baseAddr UART module base address. - * @param enable The setting to enable (true), which configures bit 10 as the parity bit or to - * disable (false), which configures bit 9 as the parity bit in the serial - * transmission. - */ -static inline void UART_HAL_SetBit10AsParitybit(uint32_t baseAddr, bool enable) -{ - /* to enable the parity bit as the tenth data bit, along with enabling UARTx_C4[M10] - * need to also enable parity and set UARTx_C1[M] bit - * assumed that the user has already set the appropriate bits */ - BW_UART_C4_M10(baseAddr, enable); -} - -/*! - * @brief Gets the configuration of the UART bit 10 (if enabled) or bit 9 (if disabled) as the - * parity bit in the serial transmission. - * - * This function returns true if bit 10 is configured as the parity bit, otherwise it returns - * false if bit 9 is configured as the parity bit. - * - * @param baseAddr UART module base address. - * @return The configuration setting of bit 10 (true), or bit 9 (false) as the - * parity bit in the serial transmission. - */ -static inline bool UART_HAL_IsBit10SetAsParitybit(uint32_t baseAddr) -{ - /* to see if the parity bit is set as the tenth data bit, - * return value of UARTx_C4[M10] */ - return BR_UART_C4_M10(baseAddr); -} - -/*! - * @brief Determines whether the UART received data word was received with noise. - * - * This function returns true if the received data word was received with noise. Otherwise, - * it returns false indicating no noise was detected. - * - * @param baseAddr UART module base address. - * @return The status of the NOISY bit in the UART extended data register. - */ -static inline bool UART_HAL_IsCurrentDatawordReceivedWithNoise(uint32_t baseAddr) -{ - /* to see if the current dataword was received with noise, - * return value of UARTx_ED[NOISY] */ - return BR_UART_ED_NOISY(baseAddr); -} - -/*! - * @brief Determines whether the UART received data word was received with a parity error. - * - * This function returns true if the received data word was received with a parity error. - * Otherwise, it returns false indicating no parity error was detected. - * - * @param baseAddr UART module base address. - * @return The status of the PARITYE (parity error) bit in the UART extended data register. - */ -static inline bool UART_HAL_IsCurrentDatawordReceivedWithParityerror(uint32_t baseAddr) -{ - /* to see if the current dataword was received with parity error, - * return value of UARTx_ED[PARITYE] */ - return BR_UART_ED_PARITYE(baseAddr); -} - -#endif /* FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS*/ - -/*@}*/ - -/*! - * @name UART Special Feature Configurations - * @{ - */ - -/*! - * @brief Configures the UART to either operate or cease to operate in WAIT mode. - * - * The function configures the UART to either operate or cease to operate when WAIT mode is - * entered. - * - * @param baseAddr UART module base address. - * @param mode The UART WAIT mode operation - operates or ceases to operate in WAIT mode. - */ -static inline void UART_HAL_SetWaitModeOperation(uint32_t baseAddr, uart_operation_config_t mode) -{ - /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */ - BW_UART_C1_UARTSWAI(baseAddr, mode); -} - -/*! - * @brief Determines if the UART operates or ceases to operate in WAIT mode. - * - * This function returns kUartOperates if the UART has been configured to operate in WAIT mode. - * Else it returns KUartStops if the UART has been configured to cease-to-operate in WAIT mode. - * - * @param baseAddr UART module base address. - * @return The UART WAIT mode operation configuration, returns either kUartOperates or KUartStops. - */ -static inline uart_operation_config_t UART_HAL_GetWaitModeOperation(uint32_t baseAddr) -{ - /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */ - return (uart_operation_config_t)BR_UART_C1_UARTSWAI(baseAddr); -} - -/*! - * @brief Configures the UART loopback operation. - * - * This function enables or disables the UART loopback operation. - * - * @param baseAddr UART module base address. - * @param enable The UART loopback mode configuration, either disabled (false) or enabled (true). - */ -static inline void UART_HAL_SetLoopCmd(uint32_t baseAddr, bool enable) -{ - BW_UART_C1_LOOPS(baseAddr, enable); -} - -/*! - * @brief Configures the UART single-wire operation. - * - * This function enables or disables the UART single-wire operation. - * In some UART baseAddrs it is required that the transmitter/receiver be disabled - * before calling this function. - * This may be applied to all UARTs to ensure safe operation. - * - * @param baseAddr UART module base address. - * @param enable The UART single-wire mode configuration, either disabled (false) or enabled (true). - */ -static inline void UART_HAL_SetReceiverSource(uint32_t baseAddr, uart_receiver_source_t source) -{ - BW_UART_C1_RSRC(baseAddr, source); -} -/*! - * @brief Configures the UART transmit direction while in single-wire mode. - * - * This function configures the transmitter direction when the UART is configured for single-wire - * operation. - * - * @param baseAddr UART module base address. - * @param direction The UART single-wire mode transmit direction configuration of type - * uart_singlewire_txdir_t (either kUartSinglewireTxdirIn or - * kUartSinglewireTxdirOut. - */ -static inline void UART_HAL_SetTransmitterDir(uint32_t baseAddr, uart_singlewire_txdir_t direction) -{ - /* configure UART transmit direction (input or output) when in single-wire mode - * it is assumed UART is in single-wire mode - */ - BW_UART_C3_TXDIR(baseAddr, direction); -} - -/*! - * @brief Places the UART receiver in standby mode. - * - * This function, when called, places the UART receiver into standby mode. - * In some UART baseAddrs, there are conditions that must be met before placing Rx in standby mode. - * Before placing UART in standby, determine if receiver is set to - * wake on idle, and if receiver is already in idle state. - * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently - * not idle. - * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel - * is already idle, it is possible that the UART will discard data because data must be received - * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to be reasserted. - * - * @param baseAddr UART module base address. - * @return Error code or kStatus_UART_Success. - */ -uart_status_t UART_HAL_PutReceiverInStandbyMode(uint32_t baseAddr); - -/*! - * @brief Places the UART receiver in normal mode (disable standby mode operation). - * - * This function, when called, places the UART receiver into normal mode and out of - * standby mode. - * - * @param baseAddr UART module base address. - */ -static inline void UART_HAL_PutReceiverInNormalMode(uint32_t baseAddr) -{ - /* clear the RWU bit to place receiver into normal mode (disable standby mode)*/ - HW_UART_C2_CLR(baseAddr, BM_UART_C2_RWU); -} - -/*! - * @brief Determines if the UART receiver is currently in standby mode. - * - * This function determines the state of the UART receiver. If it returns true, this means - * that the UART receiver is in standby mode; if it returns false, the UART receiver - * is in normal mode. - * - * @param baseAddr UART module base address. - * @return The UART receiver is in normal mode (false) or standby mode (true). - */ -static inline bool UART_HAL_IsReceiverInStandby(uint32_t baseAddr) -{ - /* return the RWU bit setting (0 - normal more, 1 - standby)*/ - return BR_UART_C2_RWU(baseAddr); -} - -/*! - * @brief Selects the UART receiver wakeup method (idle-line or address-mark) from standby mode. - * - * This function configures the wakeup method of the UART receiver from standby mode. The options - * are idle-line wake or address-mark wake. - * - * @param baseAddr UART module base address. - * @param method The UART receiver wakeup method options: kUartIdleLineWake - Idle-line wake or - * kUartAddrMarkWake - address-mark wake. - */ -static inline void UART_HAL_SetReceiverWakeupMethod(uint32_t baseAddr, uart_wakeup_method_t method) -{ - /* configure the WAKE bit for idle line wake or address mark wake */ - BW_UART_C1_WAKE(baseAddr, method); -} - -/*! - * @brief Gets the UART receiver wakeup method (idle-line or address-mark) from standby mode. - * - * This function returns how the UART receiver is configured to wake from standby mode. The - * wake method options that can be returned are kUartIdleLineWake or kUartAddrMarkWake. - * - * @param baseAddr UART module base address. - * @return The UART receiver wakeup from standby method, false: kUartIdleLineWake (idle-line wake) - * or true: kUartAddrMarkWake (address-mark wake). - */ -static inline uart_wakeup_method_t UART_HAL_GetReceiverWakeupMethod(uint32_t baseAddr) -{ - /* get configuration of the WAKE bit for idle line wake or address mark wake */ - return (uart_wakeup_method_t)BR_UART_C1_WAKE(baseAddr); -} - -/*! - * @brief Configures the operation options of the UART idle line detect. - * - * This function allows the user to configure the UART idle-line detect operation. There are two - * separate operations for the user to configure, the idle line bit-count start and the receive - * wake up affect on IDLE status bit. The user will pass in a structure of type - * uart_idle_line_config_t. - * - * @param baseAddr UART module base address. - * @param idleLine Idle bit count start: 0 - after start bit (default), 1 - after stop bit - * @param rxWakeIdleDetect Receiver Wake Up Idle Detect. IDLE status bit operation during receive - * standby. Controls whether idle character that wakes up receiver will also set IDLE status - * bit. 0 - IDLE status bit doesn't get set (default), 1 - IDLE status bit gets set - */ -void UART_HAL_ConfigIdleLineDetect(uint32_t baseAddr, uint8_t idleLine, uint8_t rxWakeIdleDetect); - -/*! - * @brief Configures the UART break character transmit length. - * - * This function allows the user to configure the UART break character transmit length. Refer to - * the typedef uart_break_char_length_t for setting options. - * In some UART baseAddrs it is required that the transmitter be disabled before calling - * this function. This may be applied to all UARTs to ensure safe operation. - * - * @param baseAddr UART module base address. - * @param length The UART break character length setting of type uart_break_char_length_t, either a - * minimum 10-bit times or a minimum 13-bit times. - */ -static inline void UART_HAL_SetBreakCharTransmitLength(uint32_t baseAddr, - uart_break_char_length_t length) -{ - /* Configure BRK13 - Break Character transmit length configuration - * UART break character length setting: - * 0 - minimum 10-bit times (default), - * 1 - minimum 13-bit times */ - BW_UART_S2_BRK13(baseAddr, length); -} - -/*! - * @brief Configures the UART break character detect length. - * - * This function allows the user to configure the UART break character detect length. Refer to - * the typedef uart_break_char_length_t for setting options. - * - * @param baseAddr UART module base address. - * @param length The UART break character length setting of type uart_break_char_length_t, either a - * minimum 10-bit times or a minimum 13-bit times. - */ -static inline void UART_HAL_SetBreakCharDetectLength(uint32_t baseAddr, uart_break_char_length_t length) -{ - /* Configure LBKDE - Break Character detect length configuration - * UART break character length setting: - * 0 - minimum 10-bit times (default), - * 1 - minimum 13-bit times */ - BW_UART_S2_LBKDE(baseAddr, length); -} - -/*! - * @brief Configures the UART transmit send break character operation. - * - * This function allows the user to queue a UART break character to send. If true is passed into - * the function, then a break character is queued for transmission. A break character will - * continuously be queued until this function is called again when a false is passed into this - * function. - * - * @param baseAddr UART module base address. - * @param enable If false, the UART normal/queue break character setting is disabled, which - * configures the UART for normal transmitter operation. If true, a break - * character is queued for transmission. - */ -static inline void UART_HAL_SetBreakCharCmd(uint32_t baseAddr, bool enable) -{ - BW_UART_C2_SBK(baseAddr, enable); -} - -/*! - * @brief Configures the UART match address mode control operation. (Note: Feature available on - * select UART baseAddrs) - * - * The function allows the user to configure the UART match address control operation. The user - * has the option to enable the match address mode and to program the match address value. There - * are two match address modes, each with its own enable and programmable match address value. - * - * @param baseAddr UART module base address. - * @param matchAddrMode1 If true, this enables match address mode 1 (MAEN1), where false disables. - * @param matchAddrMode2 If true, this enables match address mode 2 (MAEN2), where false disables. - * @param matchAddrValue1 The match address value to program for match address mode 1. - * @param matchAddrValue2 The match address value to program for match address mode 2. - */ -void UART_HAL_SetMatchAddress(uint32_t baseAddr, bool matchAddrMode1, bool matchAddrMode2, - uint8_t matchAddrValue1, uint8_t matchAddrValue2); - -#if FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT -/*! - * @brief Configures the UART to send data MSB first - * (Note: Feature available on select UART baseAddrs) - * - * The function allows the user to configure the UART to send data MSB first or LSB first. - * In some UART baseAddrs it is required that the transmitter/receiver be disabled - * before calling this function. - * This may be applied to all UARTs to ensure safe operation. - * - * @param baseAddr UART module base address. - * @param enable This configures send MSB first mode configuration. If true, the data is sent MSB - * first; if false, it is sent LSB first. - */ -static inline void UART_HAL_SetSendMsbFirstCmd(uint32_t baseAddr, bool enable) -{ - BW_UART_S2_MSBF(baseAddr, enable); -} -#endif - -#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT -/*! - * @brief Enables the UART receiver request-to-send functionality. - * - * This function allows the user to enable the UART receiver request-to-send (RTS) functionality. - * By enabling, it allows the RTS output to control the CTS input of the transmitting device to - * prevent receiver overrun. RTS is deasserted if the number of characters in the receiver data - * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the - * number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. - * Do not set both RXRTSE and TXRTSE. - * - * @param baseAddr UART module base address. - * @param enable Enable or disable receiver rts. - */ -static inline void UART_HAL_SetReceiverRtsCmd(uint32_t baseAddr, bool enable) -{ - /* Set RXRTSE */ - BW_UART_MODEM_RXRTSE(baseAddr, enable); -} - -/*! - * @brief Enables the UART transmitter request-to-send functionality. - * - * This function allows the user to enable the UART transmitter request-to-send (RTS) functionality. - * When enabled, it allows the UART to control the RTS assertion before and after a transmission - * such that when a character is placed into an empty transmitter data buffer, RTS - * asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all - * characters in the transmitter data buffer and shift register are completely sent, including - * the last stop bit. - * - * @param baseAddr UART module base address. - * @param enable Enable or disable transmitter RTS. - */ -static inline void UART_HAL_SetTransmitterRtsCmd(uint32_t baseAddr, bool enable) -{ - /* Set TXRTSE */ - BW_UART_MODEM_TXRTSE(baseAddr, enable); -} - -/*! - * @brief Configures the UART transmitter RTS polarity. - * - * This function allows the user configure the transmitter RTS polarity to be either active low - * or active high. - * - * @param baseAddr UART module base address. - * @param polarity The UART transmitter RTS polarity setting (false - active low, - * true - active high). - */ -static inline void UART_HAL_SetTransmitterRtsPolarityMode(uint32_t baseAddr, bool polarity) -{ - /* Configure the transmitter rts polarity: 0=active low, 1=active high */ - BW_UART_MODEM_TXRTSPOL(baseAddr, polarity); -} - -/*! - * @brief Enables the UART transmitter clear-to-send functionality. - * - * This function allows the user to enable the UART transmitter clear-to-send (CTS) functionality. - * When enabled, the transmitter checks the state of CTS each time it is ready to send a character. - * If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in - * the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a - * character is being sent do not affect its transmission. - * - * @param baseAddr UART module base address. - * @param enable Enable or disable transmitter CTS. - */ -static inline void UART_HAL_SetTransmitterCtsCmd(uint32_t baseAddr, bool enable) -{ - /* Set TXCTSE */ - BW_UART_MODEM_TXCTSE(baseAddr, enable); -} - -#endif /* FSL_FEATURE_UART_HAS_MODEM_SUPPORT*/ - -#if FSL_FEATURE_UART_HAS_IR_SUPPORT -/*! - * @brief Configures the UART infrared operation. - * - * The function allows the user to enable or disable the UART infrared (IR) operation - * and to configure the IR pulse width. - * - * @param baseAddr UART module base address. - * @param enable Enable (true) or disable (false) the infrared operation. - * @param pulseWidth The UART transmit narrow pulse width setting of type uart_ir_tx_pulsewidth_t. - */ -void UART_HAL_SetInfraredOperation(uint32_t baseAddr, bool enable, - uart_ir_tx_pulsewidth_t pulseWidth); -#endif /* FSL_FEATURE_UART_HAS_IR_SUPPORT*/ - -/*@}*/ - -/*! - * @name UART Status Flags - * @{ - */ - -/*! - * @brief Gets all UART status flag states. - * - * @param baseAddr UART module base address. - * @param statusFlag Status flag name. - */ -bool UART_HAL_GetStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag); - -/*! - * @brief Gets the UART Transmit data register empty flag. - * - * This function returns the state of the UART Transmit data register empty flag. - * - * @param baseAddr UART module base address. - * @return The status of Transmit data register empty flag, which is set when transmit buffer - * is empty. - */ -static inline bool UART_HAL_IsTxDataRegEmpty(uint32_t baseAddr) -{ - /* return status condition of TDRE flag */ - return BR_UART_S1_TDRE(baseAddr); -} - -/*! - * @brief Gets the UART Transmission complete flag. - * - * This function returns the state of the UART Transmission complete flag. - * - * @param baseAddr UART module base address. - * @return The status of Transmission complete flag, which is set when the transmitter is idle - * (transmission activity complete). - */ -static inline bool UART_HAL_IsTxComplete(uint32_t baseAddr) -{ - /* return status condition of TC flag */ - return BR_UART_S1_TC(baseAddr); -} - -/*! - * @brief Gets the UART Receive data register full flag. - * - * This function returns the state of the UART Receive data register full flag. - * - * @param baseAddr UART module base address. - * @return The status of Receive data register full flag, which is set when the receive data buffer - * is full. - */ -static inline bool UART_HAL_IsRxDataRegFull(uint32_t baseAddr) -{ - /* return status condition of RDRF flag */ - return BR_UART_S1_RDRF(baseAddr); -} - -/*! - * @brief Clears an individual and specific UART status flag. - * - * This function allows the user to clear an individual and specific UART status flag. Refer to - * structure definition uart_status_flag_t for list of status bits. - * - * @param baseAddr UART module base address. - * @param statusFlag The desired UART status flag to clear. - * @return An error code or kStatus_UART_Success. - */ -uart_status_t UART_HAL_ClearStatusFlag(uint32_t baseAddr, uart_status_flag_t statusFlag); - -/*! - * @brief Clears all UART status flags. - * - * This function tries to clear all of the UART status flags. In some cases, some of the status - * flags may not get cleared because the condition that set the flag may still exist. - * - * @param baseAddr UART module base address. - */ -void UART_HAL_ClearAllNonAutoclearStatusFlags(uint32_t baseAddr); - -/*@}*/ - -/*! - * @name UART FIFO Configurations - * @{ - */ - -#if FSL_FEATURE_UART_HAS_FIFO -/*! - * @brief Enables or disable the UART transmit FIFO. - * - * This function allows the user to enable or disable the UART transmit FIFO. - * It is required that the transmitter/receiver be disabled before calling this function - * when the FIFO is empty. - * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function. - * - * @param baseAddr UART module base address. - * @param enable Enable or disable Tx FIFO. - * @return Error code if it is detected that the transmitter or receiver is enabled or - * kStatus_UART_Success. - */ -uart_status_t UART_HAL_SetTxFifoCmd(uint32_t baseAddr, bool enable); - -/*! - * @brief Enables or disable the UART receive FIFO. - * - * This function allows the user to enable or disable the UART receive FIFO. - * It is required that the transmitter/receiver be disabled before calling this function - * when the FIFO is empty. - * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function. - * - * @param baseAddr UART module base address. - * @param enable Enable or disable Rx FIFO. - * @return Error code if it is detected that the transmitter or receiver is enabled or - * kStatus_UART_Success. - */ -uart_status_t UART_HAL_SetRxFifoCmd(uint32_t baseAddr, bool enable); - -/*! - * @brief Gets the size of the UART transmit FIFO. - * - * This function returns the size (number of entries) supported in the UART transmit FIFO for - * a particular module baseAddr. - * - * @param baseAddr UART module base address. - * @return The UART transmit FIFO size as follows: - * 0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words - * 0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved - */ -static inline uint8_t UART_HAL_GetTxFifoSize(uint32_t baseAddr) -{ - return BR_UART_PFIFO_TXFIFOSIZE(baseAddr); -} - -/*! - * @brief Gets the size of the UART receive FIFO. - * - * This function returns the size (number of entries) supported in the UART receive FIFO for - * a particular module baseAddr. - * - * @param baseAddr UART module base address. - * @return The receive FIFO size as follows: - * 0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words - * 0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved - */ -static inline uint8_t UART_HAL_GetRxFifoSize(uint32_t baseAddr) -{ - return BR_UART_PFIFO_RXFIFOSIZE(baseAddr); -} - -/*! - * @brief Flushes the UART transmit FIFO. - * - * This function allows the user to flush the UART transmit FIFO for a particular module baseAddr. - * Flushing the FIFO may result in data loss. - * It is recommended that the transmitter be disabled before calling this function. - * - * @param baseAddr UART module base address. - * @return Error code if it is detected that the transmitter or receiver is enabled or - * kStatus_UART_Success. - */ -uart_status_t UART_HAL_FlushTxFifo(uint32_t baseAddr); - -/*! - * @brief Flushes the UART receive FIFO. - * - * This function allows the user to flush the UART receive FIFO for a particular module baseAddr. - * Flushing the FIFO may result in data loss. - * It is recommended that the receiver be disabled before calling this function. - * - * @param baseAddr UART module base address. - * @return Error code if it is detected that the transmitter or receiver is enabled or - * kStatus_UART_Success. - */ -uart_status_t UART_HAL_FlushRxFifo(uint32_t baseAddr); - -/*! - * @brief Gets the UART transmit FIFO empty status state. - * - * The function returns the state of the transmit FIFO empty status state, but does not take into - * account data in the shift register. - * - * @param baseAddr UART module base address. - * @return The UART transmit FIFO empty status: true=empty; false=not-empty. - */ -static inline bool UART_HAL_IsTxFifoEmpty(uint32_t baseAddr) -{ - return BR_UART_SFIFO_TXEMPT(baseAddr); -} - -/*! - * @brief Gets the UART receive FIFO empty status state. - * - * The function returns the state of the receive FIFO empty status state, but does not take into - * account data in the shift register. - * - * @param baseAddr UART module base address. - * @return The UART receive FIFO empty status: true=empty; false=not-empty. - */ -static inline bool UART_HAL_IsRxFifoEmpty(uint32_t baseAddr) -{ - return BR_UART_SFIFO_RXEMPT(baseAddr); -} - -/*! - * @brief Sets the UART transmit FIFO watermark value. - * - * Programming the transmit watermark should be done when UART the transmitter is disabled - * and the value must be set less than the size obtained from UART_HAL_GetTxFifoSize. - * - * @param baseAddr UART module base address. - * @param watermark The UART transmit watermark value to be programmed. - * @return Error code if transmitter is enabled or kStatus_UART_Success. - */ -uart_status_t UART_HAL_SetTxFifoWatermark(uint32_t baseAddr, uint8_t watermark); - -/*! - * @brief Gets the UART transmit FIFO watermark value. - * - * @param baseAddr UART module base address. - * @return The value currently programmed for the UART transmit watermark. - */ -static inline uint8_t UART_HAL_GetTxFifoWatermark(uint32_t baseAddr) -{ - /* get watermark*/ - return HW_UART_TWFIFO_RD(baseAddr); -} - -/*! - * @brief Gets the UART transmit FIFO data word count (number of words in the transmit FIFO). - * - * The function UART_HAL_GetTxDatawordCountInFifo excludes any data that may - * be in the UART transmit shift register - * - * @param baseAddr UART module base address. - * @return The number of data words currently in the UART transmit FIFO. - */ -static inline uint8_t UART_HAL_GetTxDatawordCountInFifo(uint32_t baseAddr) -{ - /* get the current number of datawords in the FIFO*/ - return HW_UART_TCFIFO_RD(baseAddr); -} - -/*! - * @brief Sets the UART receive FIFO watermark value. - * - * Programming the receive watermark should be done when the receiver is disabled - * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize and - * greater than zero. - * - * @param baseAddr UART module base address. - * @param watermark The UART receive watermark value to be programmed. - * @return Error code if receiver is enabled or kStatus_UART_Success. - */ -uart_status_t UART_HAL_SetRxFifoWatermark(uint32_t baseAddr, uint8_t watermark); - -/*! - * @brief Gets the UART receive FIFO data word count (number of words in the receive FIFO). - * - * The function UART_HAL_GetRxDatawordCountInFifo excludes any data that may be - * in the receive shift register. - * - * @param baseAddr UART module base address. - * @return The number of data words currently in the UART receive FIFO. - */ -static inline uint8_t UART_HAL_GetRxDatawordCountInFifo(uint32_t baseAddr) -{ - /* get the current number of datawords in the FIFO*/ - return HW_UART_RCFIFO_RD(baseAddr); -} - -/*! - * @brief Gets the UART receive FIFO watermark value. - * - * @param baseAddr UART module base address. - * @return The value currently programmed for the UART receive watermark. - */ -static inline uint8_t UART_HAL_GetRxFifoWatermark(uint32_t baseAddr) -{ - /* get watermark*/ - return HW_UART_RWFIFO_RD(baseAddr); -} - -#endif /* FSL_FEATURE_UART_HAS_FIFO*/ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_UART_HAL_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_features.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_features.h deleted file mode 100644 index cad5b73387e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_features.h +++ /dev/null @@ -1,87 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2014-05-14 -** Build: b140515 -** -** Abstract: -** Chip specific module features. -** -** Copyright: 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-05-14) -** Customer release. -** -** ################################################################### -*/ - -#if !defined(__FSL_WDOG_FEATURES_H__) -#define __FSL_WDOG_FEATURES_H__ - -#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ - defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ - defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ - defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ - defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ - defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ - defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \ - defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ - defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ - defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ - defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ - defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ - defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \ - defined(CPU_MK70FX512VMJ15) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ - defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ - defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \ - defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \ - defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \ - defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) - /* @brief Watchdog is available. */ - #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_WDOG_FEATURES_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c deleted file mode 100644 index d29bf4c661b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_wdog_hal.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Variables - *******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : WDOG_HAL_Init - * Description : Initialize WDOG peripheral to reset state. - * - *END**************************************************************************/ -void WDOG_HAL_Init(uint32_t baseAddr) -{ - wdog_common_config wdogCommonConfig; - wdogCommonConfig.commonConfig.workInWaitModeEnable = (uint8_t)true; - wdogCommonConfig.commonConfig.workInDebugModeEnable = (uint8_t)false; - wdogCommonConfig.commonConfig.workInStopModeEnable = (uint8_t)true; - wdogCommonConfig.commonConfig.clockSource = (uint8_t)kWdogClockSourceBusClock; - wdogCommonConfig.commonConfig.interruptEnable = (uint8_t)false; - wdogCommonConfig.commonConfig.windowModeEnable = (uint8_t)false; - wdogCommonConfig.commonConfig.updateRegisterEnable = (uint8_t)true; - wdogCommonConfig.commonConfig.wdogEnable = (uint8_t)(true); - - WDOG_HAL_Unlock(baseAddr); - WDOG_HAL_SetTimeoutValue(baseAddr, 0x004C4B4CU); - WDOG_HAL_SetWindowValue(baseAddr, 0); - WDOG_HAL_SetClockPrescalerValueMode(baseAddr, kWdogClockPrescalerValueDevide5); - WDOG_HAL_ClearIntFlag(baseAddr); - WDOG_HAL_SetCommonConfig(baseAddr, wdogCommonConfig); - -} - -/******************************************************************************* - * EOF - *******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h deleted file mode 100644 index 55cb384c189..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_WDOG_HAL_H__ -#define __FSL_WDOG_HAL_H__ - -#include -#include -#include -#include "fsl_wdog_features.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup wdog_hal - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -#define WDOG_UNLOCK_VALUE_HIGH (0xC520U) -#define WDOG_UNLOCK_VALUE_LOW (0xD928U) - -#define WDOG_REFRESH_VALUE_HIGH (0xA602U) -#define WDOG_REFRESH_VALUE_LOW (0xB480U) - -/*! @brief Watchdog clock source selection.*/ -typedef enum _wdog_clock_source { - kWdogClockSourceLpoClock = 0x0U, /*!< Clock source is LPO clock */ - kWdogClockSourceBusClock = 0x1U /*!< Clock source is Bus clock */ -} wdog_clock_source_t; - -/*! @brief Define the selection of the clock prescaler*/ -typedef enum _wdog_clock_prescaler_value { - kWdogClockPrescalerValueDevide1 = 0x0U, /*!< Divided by 1 */ - kWdogClockPrescalerValueDevide2 = 0x1U, /*!< Divided by 2 */ - kWdogClockPrescalerValueDevide3 = 0x2U, /*!< Divided by 3 */ - kWdogClockPrescalerValueDevide4 = 0x3U, /*!< Divided by 4 */ - kWdogClockPrescalerValueDevide5 = 0x4U, /*!< Divided by 5 */ - kWdogClockPrescalerValueDevide6 = 0x5U, /*!< Divided by 6 */ - kWdogClockPrescalerValueDevide7 = 0x6U, /*!< Divided by 7 */ - kWdogClockPrescalerValueDevide8 = 0x7U /*!< Divided by 8 */ -} wdog_clock_prescaler_value_t; - -/*! @brief Define the common configure */ -typedef union _wdog_common_config { - uint32_t U; - struct CommonConfig { - uint32_t wdogEnable:1; /*!< Enable configure, 1 means enable WDOG */ - uint32_t clockSource:1; /*!< Clock source */ - uint32_t interruptEnable:1; /*!< WDOG interrupt configure, 1 means enable interrupt */ - uint32_t windowModeEnable:1; /*!< Window mode configure, 1 means enable window mode */ - uint32_t updateRegisterEnable:1; /*!< 1 means WDOG register can reconfigure by unlock */ - uint32_t workInDebugModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */ - uint32_t workInStopModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */ - uint32_t workInWaitModeEnable:1; /*!< 1 means WDOG works while CPU in Debug mode */ - uint32_t reserved0:1; /*!< Reserved */ - uint32_t reserved1:1; /*!< Reserved */ - uint32_t testWdog:1; /*!< WDOG enable configure */ - uint32_t testSelect:1; /*!< 0 means quick test, 1 means byte test */ - uint32_t byteSelect:2; /*!< Test byte select */ - uint32_t disableTestWdog:1; /*!< 1 means WDOG test mode is disabled */ - uint32_t reserved2:1; /*!< Reserved */ - uint32_t reserved3:16; /*!< Reserved */ - } commonConfig; -} wdog_common_config; - - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Watchdog HAL. - * @{ - */ - -/*! - * @brief Sets the WDOG common configure. - * - * This function is used to set the WDOG common configure. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, the WCT window is still open and - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. - * The common configuration is controlled by the WDOG_STCTRLH. This is a write-once register and this interface - * is used to set all field of the WDOG_STCTRLH registers at the same time. - * If only one field needs to be set, the API can be used. These API write to the WDOG_STCTRLH register: - * #WDOG_HAL_Enable,#WDOG_HAL_Disable,#WDOG_HAL_SetIntCmd,#WDOG_HAL_SetClockSourceMode,#WDOG_HAL_SetWindowModeCmd, - * #WDOG_HAL_SetRegisterUpdateCmd,#WDOG_HAL_SetWorkInDebugModeCmd,#WDOG_HAL_SetWorkInStopModeCmd, - * #WDOG_HAL_SetWorkInWaitModeCmd - * - * @param baseAddr The WDOG peripheral base address - * @param commonConfig The common configure of the WDOG - */ -static inline void WDOG_HAL_SetCommonConfig(uint32_t baseAddr, wdog_common_config commonConfig) -{ - HW_WDOG_STCTRLH_WR(baseAddr,(uint16_t)commonConfig.U); -} - -/*! - * @brief Enables the Watchdog module. - * - * This function enables the WDOG. - * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_Enable(uint32_t baseAddr) -{ - BW_WDOG_STCTRLH_WDOGEN(baseAddr, (uint8_t)true); -} - -/*! - * @brief Disables the Watchdog module. - * - * This function disables the WDOG. - * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_Disable(uint32_t baseAddr) -{ - BW_WDOG_STCTRLH_WDOGEN(baseAddr, (uint8_t)false); -} - -/*! - * @brief Checks whether the WDOG is enabled. - * - * This function checks whether the WDOG is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @return false means WDOG is disabled, true means WODG is enabled. - * - */ -static inline bool WDOG_HAL_IsEnabled(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_WDOGEN(baseAddr); -} - -/*! - * @brief Enables and disables the Watchdog interrupt. - * - * This function enables or disables the WDOG interrupt. - * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param enable false means disable watchdog interrupt and true means enable watchdog interrupt. - */ -static inline void WDOG_HAL_SetIntCmd(uint32_t baseAddr, bool enable) -{ - BW_WDOG_STCTRLH_IRQRSTEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Checks whether the WDOG interrupt is enabled. - * - * This function checks whether the WDOG interrupt is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @return false means interrupt is disabled, true means interrupt is enabled. - */ -static inline bool WDOG_HAL_GetIntCmd(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_IRQRSTEN(baseAddr); -} - -/*! - * @brief Sets the Watchdog clock Source. - * - * This function sets the WDOG clock source. There are two clock sources that can be used: - * the LPO clock and the bus clock. - * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param clockSource watchdog clock source, see #wdog_clock_source_t. - */ -static inline void WDOG_HAL_SetClockSourceMode(uint32_t baseAddr, wdog_clock_source_t clockSource) -{ - BW_WDOG_STCTRLH_CLKSRC(baseAddr, (uint8_t)clockSource); -} - -/*! - * @brief Gets the Watchdog clock Source. - * - * This function gets the WDOG clock source. There are two clock sources that can be used: - * the LPO clock and the bus clock. - * A Clock Switching Delay time is about 2 clock A cycles plus 2 - * clock B, where clock A and B are the two input clocks to the clock mux. - * - * @param baseAddr The WDOG peripheral base address - * @return watchdog clock source, see #wdog_clock_source_t. - */ -static inline wdog_clock_source_t WDOG_HAL_GetClockSourceMode(uint32_t baseAddr) -{ - return (wdog_clock_source_t)BR_WDOG_STCTRLH_CLKSRC(baseAddr); -} - -/*! - * @brief Enables and disables the Watchdog window mode. - * - * This function configures the WDOG window mode. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param enable false means disable watchdog window mode. true means enable watchdog window mode. - */ -static inline void WDOG_HAL_SetWindowModeCmd(uint32_t baseAddr, bool enable) -{ - BW_WDOG_STCTRLH_WINEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Checks whether the window mode is enabled. - * - * This function checks whether the WDOG window mode is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @return false means window mode is disabled, true means window mode is enabled. - */ -static inline bool WDOG_HAL_GetWindowModeCmd(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_WINEN(baseAddr); -} - -/*! - * @brief Enables and disables the Watchdog write-once-only register update. - * - * This function configures the WDOG register update feature. If disabled, it means that - * all WDOG registers is never written again unless Power On Reset. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param enable false means disable watchdog write-once-only register update. - * true means enable watchdog write-once-only register update. - */ -static inline void WDOG_HAL_SetRegisterUpdateCmd(uint32_t baseAddr, bool enable) -{ - BW_WDOG_STCTRLH_ALLOWUPDATE(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Checks whether the register update is enabled. - * - * This function checks whether the WDOG register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @return false means register update is disabled, true means register update is enabled. - */ -static inline bool WDOG_HAL_GetRegisterUpdateCmd(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_ALLOWUPDATE(baseAddr); -} - -/*! - * @brief Sets whether Watchdog is working while the CPU is in debug mode. - * - * This function configures whether the WDOG is enabled in the CPU debug mode. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param enable false means watchdog is disabled in CPU debug mode. - * true means watchdog is enabled in CPU debug mode. - */ -static inline void WDOG_HAL_SetWorkInDebugModeCmd(uint32_t baseAddr, bool enable) -{ - BW_WDOG_STCTRLH_DBGEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Checks whether the WDOG works while in the CPU debug mode. - * - * This function checks whether the WDOG works in the CPU debug mode. - * - * @param baseAddr The WDOG peripheral base address - * @return false means not work while in CPU debug mode, true means works while in CPU debug mode. - */ -static inline bool WDOG_HAL_GetWorkInDebugModeCmd(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_DBGEN(baseAddr); -} - -/*! - * @brief Sets whether the Watchdog is working while the CPU is in stop mode. - * - * This function configures whether the WDOG is enabled in the CPU stop mode. - * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param enable false means watchdog is disabled in CPU stop mode. - * true means watchdog is enabled in CPU stop mode. - */ -static inline void WDOG_HAL_SetWorkInStopModeCmd(uint32_t baseAddr, bool enable) -{ - BW_WDOG_STCTRLH_STOPEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Checks whether the WDOG works while in CPU stop mode. - * - * This function checks whether the WDOG works in the CPU stop mode. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @return false means not work while in CPU stop mode, true means works while in CPU stop mode. - */ -static inline bool WDOG_HAL_GetWorkInStopModeCmd(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_STOPEN(baseAddr); -} - -/*! - * @brief Sets whether the Watchdog is working while the CPU is in wait mode. - * - * This function configures whether the WDOG is enabled in the CPU wait mode. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that - * the WDOG_STCTRLH register has not been written in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param enable false means watchdog is disabled in CPU wait mode. - * true means watchdog is enabled in CPU wait mode. - */ -static inline void WDOG_HAL_SetWorkInWaitModeCmd(uint32_t baseAddr, bool enable) -{ - BW_WDOG_STCTRLH_WAITEN(baseAddr, (uint8_t)enable); -} - -/*! - * @brief Checks whether the WDOG works while in the CPU wait mode. - * - * This function checks whether the WDOG works in the CPU wait mode. - * - * @param baseAddr The WDOG peripheral base address - * @return false means not work while in CPU wait mode, true means works while in CPU wait mode. - */ - -static inline bool WDOG_HAL_GetWorkInWaitModeCmd(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLH_WAITEN(baseAddr); -} - -/*! - * @brief Gets the Watchdog interrupt status. - * - * This function gets the WDOG interrupt flag. - * - * @param baseAddr The WDOG peripheral base address - * @return Watchdog interrupt status, false means interrupt not asserted, true means interrupt asserted. - */ -static inline bool WDOG_HAL_IsIntPending(uint32_t baseAddr) -{ - return (bool)BR_WDOG_STCTRLL_INTFLG(baseAddr); -} - -/*! - * @brief Clears the Watchdog interrupt flag. - * - * This function clears the WDOG interrupt flag. - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_ClearIntFlag(uint32_t baseAddr) -{ - BW_WDOG_STCTRLL_INTFLG(baseAddr, true); -} - -/*! - * @brief Set the Watchdog timeout value. - * - * This function sets the WDOG_TOVAL value. - * It should be ensured that the time-out value for the Watchdog is always greater than - * 2xWCT time + 20 bus clock cycles. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that - * this API has not been called in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param timeoutCount watchdog timeout value, count of watchdog clock tick. - */ -static inline void WDOG_HAL_SetTimeoutValue(uint32_t baseAddr, uint32_t timeoutCount) -{ - HW_WDOG_TOVALH_WR(baseAddr, (uint16_t)((timeoutCount >> 16U) & 0xFFFFU)); - HW_WDOG_TOVALL_WR(baseAddr, (uint16_t)((timeoutCount) & 0xFFFFU)); -} - -/*! - * @brief Gets the Watchdog timeout value. - * - * This function gets the WDOG_TOVAL value. - * - * @param baseAddr The WDOG peripheral base address - * @return value of register WDOG_TOVAL. - */ -static inline uint32_t WDOG_HAL_GetTimeoutValue(uint32_t baseAddr) -{ - return (uint32_t)((((uint32_t)(HW_WDOG_TOVALH_RD(baseAddr))) << 16U) | (HW_WDOG_TOVALL_RD(baseAddr))); -} - -/*! - * @brief Gets the Watchdog timer output. - * - * This function gets the WDOG_TMROUT value. - * - * @param baseAddr The WDOG peripheral base address - * @return Current value of watchdog timer counter. - */ -static inline uint32_t WDOG_HAL_GetTimerOutputValue(uint32_t baseAddr) -{ - return (uint32_t)((((uint32_t)(HW_WDOG_TMROUTH_RD(baseAddr))) << 16U) | (HW_WDOG_TMROUTL_RD(baseAddr))); -} - -/*! - * @brief Sets the Watchdog clock prescaler. - * - * This function sets the WDOG clock prescaler. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that - * this API has not been called in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param clockPrescaler watchdog clock prescaler, see #wdog_clock_prescaler_value_t. - */ -static inline void WDOG_HAL_SetClockPrescalerValueMode(uint32_t baseAddr, wdog_clock_prescaler_value_t clockPrescaler) -{ - BW_WDOG_PRESC_PRESCVAL(baseAddr, (uint8_t)clockPrescaler); -} - -/*! - * @brief Gets the Watchdog clock prescaler. - * - * This function gets the WDOG clock prescaler. - * - * @param baseAddr The WDOG peripheral base address - * @return WDOG clock prescaler, see #wdog_clock_prescaler_value_t. - */ -static inline wdog_clock_prescaler_value_t WDOG_HAL_GetClockPrescalerValueMode(uint32_t baseAddr) -{ - return (wdog_clock_prescaler_value_t)BR_WDOG_PRESC_PRESCVAL(baseAddr); -} - -/*! - * @brief Sets the Watchdog window value. - * - * This function sets the WDOG_WIN value. - * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that - * this API has not been called in this WCT while this function is called. - * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. - * - * @param baseAddr The WDOG peripheral base address - * @param windowValue watchdog window value. - */ -static inline void WDOG_HAL_SetWindowValue(uint32_t baseAddr, uint32_t windowValue) -{ - HW_WDOG_WINH_WR(baseAddr, (uint16_t)((windowValue>>16U) & 0xFFFFU)); - HW_WDOG_WINL_WR(baseAddr, (uint16_t)((windowValue) & 0xFFFFU)); -} - -/*! - * @brief Gets the Watchdog window value. - * - * This function gets the WDOG_WIN value. - * - * @param baseAddr The WDOG peripheral base address - * @return watchdog window value. - */ -static inline uint32_t WDOG_HAL_GetWindowValue(uint32_t baseAddr) -{ - return (uint32_t)((((uint32_t)(HW_WDOG_WINH_RD(baseAddr))) << 16U) | (HW_WDOG_WINL_RD(baseAddr))); -} - -/*! - * @brief Unlocks the Watchdog register written. - * - * This function unlocks the WDOG register written. - * This function must be called before any configuration is set because watchdog register - * will be locked automatically after a WCT(256 bus cycles). - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_Unlock(uint32_t baseAddr) -{ - HW_WDOG_UNLOCK_WR(baseAddr, WDOG_UNLOCK_VALUE_HIGH); - HW_WDOG_UNLOCK_WR(baseAddr, WDOG_UNLOCK_VALUE_LOW); -} - -/*! - * @brief Refreshes the Watchdog timer. - * - * This function feeds the WDOG. - * This function should be called before watchdog timer is in timeout. Otherwise, a reset is asserted. - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_Refresh(uint32_t baseAddr) -{ - HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_HIGH); - HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_LOW); -} - -/*! - * @brief Resets the chip using the Watchdog. - * - * This function resets the chip using WDOG. - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_ResetSystem(uint32_t baseAddr) -{ - HW_WDOG_REFRESH_WR(baseAddr, WDOG_REFRESH_VALUE_HIGH); - HW_WDOG_REFRESH_WR(baseAddr, 0); - while(1) - { - } -} - -/*! - * @brief Gets the chip reset count that was reset by Watchdog. - * - * This function gets the value of the WDOG_RSTCNT. - * - * @param baseAddr The WDOG peripheral base address - * @return Chip reset count that was reset by Watchdog. - */ -static inline uint32_t WDOG_HAL_GetResetCount(uint32_t baseAddr) -{ - return HW_WDOG_RSTCNT_RD(baseAddr); -} - -/*! - * @brief Clears the chip reset count that was reset by Watchdog. - * - * This function clears the WDOG_RSTCNT. - * - * @param baseAddr The WDOG peripheral base address - */ -static inline void WDOG_HAL_ClearResetCount(uint32_t baseAddr) -{ - HW_WDOG_RSTCNT_WR(baseAddr, 0xFFFFU); -} - -/*! - * @brief Restores the WDOG module to reset value. - * - * This function restores the WDOG module to reset value. - * - * @param baseAddr The WDOG peripheral base address - */ -void WDOG_HAL_Init(uint32_t baseAddr); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_WDOG_HAL_H__*/ -/******************************************************************************* - * EOF - *******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/mbed KSDK readme.txt b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/mbed KSDK readme.txt deleted file mode 100644 index 556c6ced96a..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/mbed KSDK readme.txt +++ /dev/null @@ -1,15 +0,0 @@ -This document is not complete, please try to add more to it to keep it as much up-to-date as possible. - -*************ADDING NEW TARGET************* -TODO (partially) - -UNAVAILABLE PERIPHERALS: -The original build system of the KSDK simply does not compile files which are not available on a target, mbed tries to compile everything. If your target tries to compile a peripheral which is not available, compilation will fail with a "No valid CPU defined!" error message. In the file which throws the error, replace the error code with: #define MBED_NO_[PERIPHERAL-NAME]. Then in the other .h and .c file in the same folder add #ifndef guards. See for an example: \mbed\targets\hal\TARGET_Freescale\TARGET_KPSDK_MCUS\TARGET_KPSDK_CODE\hal\lpuart. - -SYSTEM_MKXXXXX.C: -The file included in the top cannot be found by the compiler, replace it by cmsis.h - - - -************UPDATING KSDK FILES************ -TODO (Also good luck with it). \ No newline at end of file diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_misc_utilities.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_misc_utilities.h deleted file mode 100644 index b1f90a7a3b8..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_misc_utilities.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_MISC_UTILITIES_H__ -#define __FSL_MISC_UTILITIES_H__ - -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Min/max macros */ -#if !defined(MIN) - #define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) - #define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif - -/*! @brief Computes the number of elements in an array.*/ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/*! @brief Byte swap macros */ -#define BSWAP_16(x) (uint16_t)((((x) & 0xFF00) >> 0x8) | (((x) & 0xFF) << 0x8)) -#define BSWAP_32(val) (uint32_t)((BSWAP_16((uint32_t)(val) & (uint32_t)0xFFFF) << 0x10) | \ - (BSWAP_16((uint32_t)((val) >> 0x10)))) - -#endif /* __FSL_MISC_UTILITIES_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction.h deleted file mode 100644 index 03971063765..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction.h +++ /dev/null @@ -1,572 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#if !defined(__FSL_OS_ABSTRACTION_H__) -#define __FSL_OS_ABSTRACTION_H__ - -#include -#include -#include - -#if defined __CC_ARM -#define inline __inline -#endif - -/*! - * @addtogroup os_abstraction - * @{ - */ - -/*! @brief Status values to be returned by functions. */ -typedef enum -{ - kSuccess = 0, /*!< Functions work correctly. */ - kError, /*!< Functions work failed. */ - kTimeout, /*!< Timeout occurs while waiting for an object. */ - kIdle /*!< Can not get the object in non-blocking mode.*/ -}fsl_rtos_status; - -/*! @brief The event flags are set or not.*/ -typedef enum -{ - kFlagNotSet = 0, /*!< The flags checked are set. */ - kFlagSet /*!< The flags checked are not set. */ -}event_status; - -/*! @brief The event flags are cleared automatically or manually.*/ -typedef enum -{ - kEventAutoClr = 0, /*!< The flags of the event will be cleared automatically. */ - kEventManualClr /*!< The flags of the event will be cleared manually. */ -}event_clear_type; - -// Temporary "fix", until the proper macros are integrated in the on-line build system -#define FSL_RTOS_MBED - -/* Include required header file based on RTOS selection */ -#if defined (FSL_RTOS_MQX) - /*! @brief Macro to set message queue copy messages to internal memory or not. */ - #define __FSL_RTOS_MSGQ_COPY_MSG__ 1 - #include "fsl_os_abstraction_mqx.h" - -#elif defined (FSL_RTOS_FREE_RTOS) - #define __FSL_RTOS_MSGQ_COPY_MSG__ 1 - #include "fsl_os_abstraction_free_rtos.h" - -#elif defined (FSL_RTOS_UCOSII) - #define __FSL_RTOS_MSGQ_COPY_MSG__ 1 - #include "fsl_os_abstraction_ucosii.h" - -#elif defined (FSL_RTOS_UCOSIII) - #define __FSL_RTOS_MSGQ_COPY_MSG__ 1 - #include "fsl_os_abstraction_ucosiii.h" - -#elif defined (FSL_RTOS_CMSIS) - #define __FSL_RTOS_MSGQ_COPY_MSG__ 0 - #include "fsl_os_abstraction_cmsis.h" - -#elif defined (FSL_RTOS_MBED) - #define __FSL_RTOS_MSGQ_COPY_MSG__ 1 - #include "fsl_os_abstraction_mbed.h" - -#else - #define __FSL_RTOS_MSGQ_COPY_MSG__ 1 - #include "fsl_os_abstraction_bm.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Synchronization - * @{ - */ - -/*! - * @brief Initialize a synchronization object to a given state. - * - * @param obj The sync object to initialize. - * @param initValue The initial value the object will be set to. - * - * @retval kSuccess The object was successfully created. - * @retval kError Invalid parameter or no more objects can be created. - */ -fsl_rtos_status sync_create(sync_object_t *obj, uint8_t initValue); - -/*! - * @brief Wait for the synchronization object. - * - * This function checks the sync object's counting value, if it is - * positive, decreases it and returns kSuccess, otherwise, timeout will be - * used for wait. - * - * @param obj Pointer to the synchronization object. - * @param timeout The maximum number of milliseconds to wait for the object to be signalled. - * Pass the #kSyncWaitForever constant to wait indefinitely for someone to signal the object. - * A value of 0 should not be passed to this function. Instead, use sync_poll for - * a non blocking check. - * - * @retval kSuccess The object was signalled. - * @retval kTimeout A timeout occurred. - * @retval kError An incorrect parameter was passed. - * @retval kIdle The object has not been signalled. - * - * @note There could be only one process waiting for the object at the same time. - */ -fsl_rtos_status sync_wait(sync_object_t *obj, uint32_t timeout); - -/*! - * @brief Checks a synchronization object's status. - * - * This function is used to poll a sync object's status. - * If the sync object's counting value is positive, decrease it and return - * kSuccess. If the object's counting value is 0, the function will - * return kIdle immediately - * - * @param obj The synchronization object. - * - * @retval kSuccess The object was signalled. - * @retval kIdle The object was not signalled. - * @retval kError An incorrect parameter was passed. - */ -fsl_rtos_status sync_poll(sync_object_t *obj); - -/*! - * @brief Signal for someone waiting on the synchronization object to wake up. - * - * This function should not be called from an ISR. - * - * @param obj The synchronization object to signal. - * - * @retval kSuccess The object was successfully signaled. - * @retval kError The object can not be signaled or invalid parameter. - */ -fsl_rtos_status sync_signal(sync_object_t *obj); - -/*! - * @brief Signal for someone waiting on the synchronization object to wake up. - * - * This function should only be called from an ISR. - * - * @param obj The synchronization object to signal. - * - * @retval kSuccess The object was successfully signaled. - * @retval kError The object can not be signaled or invalid parameter. - */ -fsl_rtos_status sync_signal_from_isr(sync_object_t *obj); - -/*! - * @brief Destroy a previously created synchronization object. - * - * @param obj The synchronization object to destroy. - * - * @retval kSuccess The object was successfully destroyed. - * @retval kError Object destruction failed. - */ -fsl_rtos_status sync_destroy(sync_object_t *obj); - -/* @} */ - -/*! - * @name Resource locking - * @{ - */ - -/*! - * @brief Initialize a locking object. - * - * @param obj The lock object to initialize. - * - * @retval kSuccess The lock is created successfully. - * @retval kError Tke lock creation failed. - */ -fsl_rtos_status lock_create(lock_object_t *obj); - -/*! - * @brief Wait for the object to be unlocked and lock it. - * - * This function will wait for some time or wait forever if could not get the lock. - * - * @param obj The locking object. - * @param timeout The maximum number of milliseconds to wait for the mutex. - * Pass the #kSyncWaitForever constant to wait indefinitely for someone to unlock the object. - * A value of 0 should not be passed to this function. Instead, use lock_poll for a non - * blocking check. - * - * @retval kSuccess The lock was obtained. - * @retval kTimeout A timeout occurred. - * @retval kError An incorrect parameter was passed. - */ -fsl_rtos_status lock_wait(lock_object_t *obj, uint32_t timeout); - -/*! - * @brief Checks if a locking object can be locked and locks it if possible. - * - * This function returns instantly if could not get the lock. - * - * @param obj The locking object. - * - * @retval kSuccess The lock was obtained. - * @retval kIdle The lock could not be obtained. - * @retval kError An incorrect parameter was passed. - * - * @note There could be only one process waiting for the object at the same time. - * For RTOSes, wait for a lock recursively by one task is not supported. - * - */ -fsl_rtos_status lock_poll(lock_object_t *obj); - -/*! - * @brief Unlock a previously locked object. - * - * @param obj The locking object to unlock. - * - * @retval kSuccess The object was successfully unlocked. - * @retval kError The object can not be unlocked or invalid parameter. - */ -fsl_rtos_status lock_release(lock_object_t *obj); - -/*! - * @brief Destroy a previously created locking object. - * - * @param obj The locking object to destroy. - * - * @retval kSuccess The object was successfully destroyed. - * @retval kError Object destruction failed. - */ -fsl_rtos_status lock_destroy(lock_object_t *obj); - -/* @} */ - -/*! - * @name Event signaling - * @{ - */ - -/*! - * @brief Initializes the event object. - * - * When the object is created, the flags is 0. - * - * @param obj Pointer to the event object to initialize. - * @param clearType The event is auto-clear or manual-clear. - * - * @retval kSuccess The object was successfully created. - * @retval kError Incorrect parameter or no more objects can be created. - */ -fsl_rtos_status event_create(event_object_t *obj, event_clear_type clearType); - -/*! - * @brief Wait for any event flags to be set. - * - * This function will wait for some time or wait forever if no flags are set. Any flags set - * will wake up the function. - * - * @param obj The event object. - * @param timeout The maximum number of milliseconds to wait for the event. - * Pass the #kSyncWaitForever constant to wait indefinitely. A value of 0 should not be passed - * to this function. - * @param setFlags Pointer to receive the flags that were set. - * - * @retval kSuccess An event was set. - * @retval kTimeout A timeout occurred. - * @retval kError An incorrect parameter was passed. - */ -fsl_rtos_status event_wait(event_object_t *obj, uint32_t timeout, event_group_t *setFlags); - -/*! - * @brief Set one or more event flags of an event object. - * - * This function should not be called from an ISR. - * - * @param obj The event object. - * @param flags Event flags to be set. - * - * @retval kSuccess The flags were successfully set. - * @retval kError An incorrect parameter was passed. - * - * @note There could be only one process waiting for the event. - * - */ -fsl_rtos_status event_set(event_object_t *obj, event_group_t flags); - -/*! - * @brief Set one or more event flags of an event object. - * - * This function should only be called from an ISR. - * - * @param obj The event object. - * @param flags Event flags to be set. - * - * @retval kSuccess The flags were successfully set. - * @retval kError An incorrect parameter was passed. - */ -fsl_rtos_status event_set_from_isr(event_object_t *obj, event_group_t flags); - -/*! - * @brief Clear one or more events of an event object. - * - * This function should not be called from an ISR. - * - * @param obj The event object. - * @param flags Event flags to be clear. - * - * @retval kSuccess The flags were successfully cleared. - * @retval kError An incorrect parameter was passed. - */ -fsl_rtos_status event_clear(event_object_t *obj, event_group_t flags); - -/*! - * @brief Check the flags are set or not. - * - * @param obj The event object. - * @param flag The flag to check. - * - * @retval kFlagsSet The flags checked are set. - * @retval kFlagsNotSet The flags checked are not set or got an error. - */ -event_status event_check_flags(event_object_t *obj, event_group_t flag); - -/*! - * @brief Destroy a previously created event object. - * - * @param obj The event object to destroy. - * - * @retval kSuccess The object was successfully destroyed. - * @retval kError Event destruction failed. - */ -fsl_rtos_status event_destroy(event_object_t *obj); -/* @} */ - -/*! - * @name Thread management - * @{ - */ - -/*! - * @brief Create a task. - * - * This function is wrapped by the macro task_create. Generally, this function is for - * internal use only, applications must use FSL_RTOS_TASK_DEFINE to define resources for - * task statically then use task_create to create task. If applications have prepare - * the resouces for task dynamically, they can use this function to create the task. - * - * @param task The task function. - * @param name The name of this task. - * @param stackSize The stack size in byte. - * @param stackMem Pointer to the stack. For bare metal, MQX and FreeRTOS, this could be NULL. - * @param priority Initial priority of the task. - * @param param Pointer to be passed to the task when it is created. - * @param usesFloat This task will use float register or not. - * @param handler Pointer to the task handler. - * - * @retval kSuccess The task was successfully created. - * @retval kError The task could not be created. - * - * @note Different tasks can not use the same task function. - */ -fsl_rtos_status __task_create(task_t task, uint8_t *name, uint16_t stackSize, - task_stack_t *stackMem, uint16_t priority, - void *param, bool usesFloat, task_handler_t *handler); - -/*! - * @brief Destroy a previously created task. - * @note Depending on the RTOS, task resources may or may not be automatically freed, - * and this function may not return if the current task is destroyed. - * - * @param handler The handler of the task to destroy. Returned by the task_create function. - * - * @retval kSuccess The task was successfully destroyed. - * @retval kError Task destruction failed or invalid parameter. - */ -fsl_rtos_status task_destroy(task_handler_t handler); -/* @} */ - -/*! - * @name Message queues - * @{ - */ - -/*! - * @brief Initialize the message queue. - * - * This function will initialize the message queue that declared previously. - * Here is an example demonstrating how to use: - @code - msg_queue_handler_t handler; - MSG_QUEUE_DECLARE(my_message, msg_num, msg_size); - handler = msg_queue_create(&my_message, msg_num, msg_size); - @endcode - * - * @param queue The queue declared through the MSG_QUEUE_DECLARE macro. - * @param number The number of elements in the queue. - * @param size Size of every elements in words. - * - * @retval Handler to access the queue for put and get operations. If message queue - * created failed, return 0. - */ -msg_queue_handler_t msg_queue_create(msg_queue_t *queue, uint16_t number, uint16_t size); - -/*! - * @brief Introduce an element at the tail of the queue. - * - * @param handler Queue handler returned by the msg_queue_create function. - * @param item Pointer to the element to be introduced in the queue. - * - * @retval kSuccess Element successfully introduced in the queue. - * @retval kError The queue was full or an invalid parameter was passed. - */ -fsl_rtos_status msg_queue_put(msg_queue_handler_t handler, msg_queue_item_t item); - -/*! - * @brief Read and remove an element at the head of the queue. - * - * @param handler Queue handler returned by the msg_queue_create function. - * @param item Pointer to store a pointer to the element of the queue. - * @param timeout In case the queue is empty, the number of milliseconds to - * wait for an element to be introduced into the queue. Use 0 to return - * immediately or #kSyncWaitForever to wait indefinitely. - * - * @retval kSuccess Element successfully obtained from the queue. - * @retval kTimeout If a timeout was specified, the queue remained empty after timeout. - * @retval kError The queue was empty or the handler was invalid. - * @retval kIdle The queue was empty and the timeout has not expired. - * - * @note There should be only one process waiting on the queue. - */ -fsl_rtos_status msg_queue_get(msg_queue_handler_t handler, - msg_queue_item_t *item, - uint32_t timeout); - -/*! - * @brief Discards all elements in the queue and leaves the queue empty. - * - * @param handler Queue handler returned by the msg_queue_create function. - * - * @retval kSuccess Queue successfully emptied. - * @retval kError Emptying queue failed. - */ -fsl_rtos_status msg_queue_flush(msg_queue_handler_t handler); - -/*! - * @brief Destroy a previously created queue. - * - * @param handler Queue handler returned by the msg_queue_create function. - * - * @retval kSuccess The queue was successfully destroyed. - * @retval kError Message queue destruction failed. - */ -fsl_rtos_status msg_queue_destroy(msg_queue_handler_t handler); - -/* @} */ - -#ifndef FSL_RTOS_MBED -/*! - * @name Memory Management - * @{ - */ - -/*! - * @brief Reserves the requested amount of memory in bytes. - * - * @param size Amount of bytes to reserve. - * - * @retval Pointer to the reserved memory. NULL if memory could not be allocated. - */ -void * mem_allocate(size_t size); - -/*! - * @brief Reserves the requested amount of memory in bytes and initializes it to 0. - * - * @param size Amount of bytes to reserve. - * - * @retval Pointer to the reserved memory. NULL if memory could not be allocated. - */ -void * mem_allocate_zero(size_t size); - -/*! - * @brief Releases the memory previously reserved. - * - * @param ptr Pointer to the start of the memory block previously reserved. - * - * @retval kSuccess Memory correctly released. - */ -fsl_rtos_status mem_free(void *ptr); -#endif - -/* @} */ - -/*! - * @name Time management - * @{ - */ - -/*! - * @brief Delays execution for a number of milliseconds. - * - * @param delay The time in milliseconds to wait. - */ -void time_delay(uint32_t delay); - -/* @} */ - -/*! - * @name Interrupt management - * @{ - */ - -/*! - * @brief Install interrupt handler. - * - * @param irqNumber IRQ number of the interrupt. - * @param handler The interrupt handler to install. - * - * @retval kSuccess Handler is installed successfully. - * @retval kSuccess Handler could not be installed. - */ -fsl_rtos_status interrupt_handler_register(int32_t irqNumber, void (*handler)(void)); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_OS_ABSTRACTION_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction_mbed.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction_mbed.h deleted file mode 100644 index ac7669c5e83..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction_mbed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* fsl_os_mbed_abstraction.h */ -/* Copyright (C) 2012 mbed.org, MIT License - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING - * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef FSL_OS_ABSTRACTION_MBED_H_ -#define FSL_OS_ABSTRACTION_MBED_H_ - -// This is not really an "abstraction", but rather a set of quick&dirty -// defines to allow the KSDK to compile. Currently, this is relevant only -// in the context of the ENET driver (fsl_enet_driver.c) - -typedef int event_object_t; -typedef int lock_object_t; -typedef void sync_object_t; -typedef unsigned int event_group_t; -typedef int task_t; -typedef void task_stack_t; -typedef int task_handler_t; -typedef int msg_queue_handler_t; -typedef void msg_queue_t; -typedef int msg_queue_item_t; - -#endif // #ifdef FSL_OS_ABSTRACTION_MBED_H_ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_misc_utilities.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_misc_utilities.c deleted file mode 100644 index f9f1f77abfd..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_misc_utilities.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "fsl_misc_utilities.h" - -#if (defined(KEIL)) - -/*FUNCTION********************************************************************** - * - * Function Name : __aeabi_assert - * Description : called by assert in KEIL - * This function is called by the assert function in KEIL. - * - *END**************************************************************************/ -void __aeabi_assert(const char *expr, const char *file, int line) -{ - printf("assert failed:%s, file %s:%d\r\n",expr,file,line); -} - -#elif (defined(KDS)) - -/*FUNCTION********************************************************************** - * - * Function Name : _isatty - * Description : used to enable the overwrite of the _write - * This function is used to enable the overwrite of the _write. - * - *END**************************************************************************/ -int _isatty (int fd) -{ - return 1; -} - -#endif - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_os_abstraction_mbed.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_os_abstraction_mbed.c deleted file mode 100644 index 47849f40446..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_os_abstraction_mbed.c +++ /dev/null @@ -1,35 +0,0 @@ -/* fsl_os_mbed_abstraction.h */ -/* Copyright (C) 2012 mbed.org, MIT License - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING - * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "fsl_os_abstraction.h" -#include "wait_api.h" - -fsl_rtos_status lock_destroy(lock_object_t *obj) { - return kSuccess; -} - - -fsl_rtos_status event_set(event_object_t *obj, event_group_t flags) { - return kSuccess; -} - -void time_delay(uint32_t delay) { - wait_ms(delay); -} - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/sw_timer.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/sw_timer.h deleted file mode 100644 index fbd46605176..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/sw_timer.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__SW_TIMER_H__) -#define __SW_TIMER_H__ - -#include -#include - -/*! @addtogroup sw_timer Software Timer - * @brief This module is used to interface with Abstract Timer HAL to generate periodical timeouts - * required through different modules of the AOA protocol. This block will be based on 1ms - * ticks for all the timeout calculations. The HAL Interface block used to communicate with - * this must have the same 1ms timeout configured. This module can generate different - * software timer channels based on the same 1ms. - */ -/*! @{*/ - -/*! Definition of the possible status of a software channel timer. */ -typedef enum SwTimerChannelStatus -{ - kSwTimerChannelExpired = 0x00, /*!< Indicates the timer channel has counted the given ms*/ - kSwTimerChannelStillCounting = 0x01, /*!< Indicates the timeout of the channel has not expired - and the timer is still counting.*/ - kSwTimerChannelIsDisable = 0x02, /*!< Indicates the timer channel is not reserved. */ - kSwTimerChannelNotAvailable = 0xFF /*!< Indicates there are not available channels to reserve - or the requested channel is not available.*/ -}sw_timer_channel_status_t; - -/*! List of status and errors. */ -enum _sw_timer_errors -{ - kSwTimerStatusSuccess, /*!< The execution was successful.*/ - kSwTimerStatusFail, /*!< The execution failed.*/ - kSwTimerStatusInvalidChannel /*!< The given channel is not valid. Valid channels are 0 to - (SW_TIMER_NUMBER_CHANNELS - 1). */ -}; - -/*! - * Data type of the counter of each timer channel. If it is an int8_t the counter will count - * up to 127ms, int16_t up to 32767ms and int32_t up to 2147483647ms. - */ -typedef int32_t time_counter_t; - -/*! Max timeout value according to size of the time counter */ -enum sw_timer_timeouts -{ - kSwTimerMaxTimeout = 2147483647 -}; - -/*! - * Data type of the free running counter. This data type should be unsigned and will count up to - * 255ms if it is uint8_t, 65535ms for uint16_t and 4294967295ms for uint32_t. - */ -typedef uint32_t time_free_counter_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Initializes the software timer module. Prepares variables and HAL layer to provide timer - * services. Starts the free running counter which will be available to get its value any - * time while the service is running; it is useful whenever a module wants to keep track of - * time, but do not wants to reserve a channel. - * - * @return status_t Returns software timer status after initialization. - * @retval kSwTimerStatusSuccess The initialization was successful and the software timer is ready - * to provide services. - * @retval kSwTimerStatusFail The initialization failed. - */ -uint32_t sw_timer_init_service(void); - -/*! - * @brief Deinitializes the software timer module. Shutdown HAL layer, so no timer service can be - * provided after the execution of this function. - * - * @return void - */ -void sw_timer_shutdown_service(void); - -/*! - * @brief Reserves a free timer channel to be used by any module and returns its identifier. - * - * @return uint8_t Returns the number of the channel that was reserved. - * @retval Any value between 0 and SW_TIMER_NUMBER_CHANNELS is a valid channel. It indicates the - * channel was reserved and can be used. - * @retval kSwTimerChannelNotAvailable If there is not any available channel, because all - * channels are already reserved. - */ -uint8_t sw_timer_reserve_channel(void); - -/*! - * @brief Returns the actual status of the given timer channel. The timer has to be previously - * started to return a valid status. - * - * @param timerChannel [in] Indicates the timer channel which status is going to be returned. - * - * @return sw_timer_channel_status_t Current status of the given timer channel. - * @retval kSwTimerChannelExpired Indicates the timer channel has counted the given ms. - * @retval kSwTimerChannelStillCounting Indicates the timeout of the channel has not expired and - the timer is still counting. - * @retval kSwTimerChannelIsDisable Indicates the timer channel is not reserved. - * @retval kSwTimerChannelNotAvailable Indicates the timer channel is invalid. - */ -sw_timer_channel_status_t sw_timer_get_channel_status(uint8_t timerChannel); - -/*! - * @brief Starts the count down of the given timer channel. The timer channel has to be previously - * reserved. - * - * @param timerChannel [in] Indicates the timer channel that is going to be started. - * @param timeout [in] Time in ms that the timer channel will count. The timeout should be - a multiple of count unit of the timer, otherwise it will be taken - the integer part of the division and the exact count will not be - achieved - * - * @return status_t Reports failures in the execution of the function. - * @retval kSwTimerStatusSuccess A channel was started successfully. - * @retval kSwTimerStatusInvalidChannel The timer channel is invalid, it does not exist. - */ -uint32_t sw_timer_start_channel(uint8_t timerChannel, time_counter_t timeout); - -/*! - * @brief Releases the given timer channel, so it can be used by someone else. - * - * @param timerChannel [in] Identifier of the timer channel. - * - * @return status_t Reports failures in the execution of the function. - * @retval kSwTimerStatusSuccess A channel was released successfully. - * @retval kSwTimerStatusInvalidChannel The timer channel is invalid, it does not exist. - */ -uint32_t sw_timer_release_channel(uint8_t timerChannel); - -/*! - * @brief Gets the current value of the free running counter. Any module can keep track of the time - * by reading this counter and calculates time difference. No reservation of timer channel - * is needed. Consider for calculations that when the counter overflows it will start from - * 0 again. - * - * @return time_free_counter_t Returns current count of the free running counter. - */ -time_free_counter_t sw_timer_get_free_counter(void); - -/*! - * @brief This function is called every 1ms by the interruption and update count down values of all - * timer channels. - * - * @return void - */ -void sw_timer_update_counters(void); - - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ -/*! @}*/ -/*Group sw_timer*/ - -#endif /* __SW_TIMER_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.c deleted file mode 100644 index 81a8b4d36c7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.c +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sim_hal.h" -#include "fsl_clock_manager.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Table of base addresses for instances. */ -extern const uint32_t g_simBaseAddr[]; -extern const uint32_t g_mcgBaseAddr[]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetDmaFreq - * Description : Gets the clock frequency for DMA module - * This function gets the clock frequency for DMA moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kSystemClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetDmamuxFreq - * Description : Gets the clock frequency for DMAMUX module - * This function gets the clock frequency for DMAMUX moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetPortFreq - * Description : Gets the clock frequency for PORT module - * This function gets the clock frequency for PORT moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kLpoClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetMpuFreq - * Description : Gets the clock frequency for MPU module - * This function gets the clock frequency for MPU moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetMpuFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kSystemClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetEwmFreq - * Description : Gets the clock frequency for Ewm module - * This function gets the clock frequency for Ewm moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kLpoClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFlexbusFreq - * Description : Gets the clock frequency for FLEXBUS module - * This function gets the clock frequency for FLEXBUS moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kSystemClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFtfFreq - * Description : Gets the clock frequency for FTF module. (Flash Memory) - * This function gets the clock frequency for FTF moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kFlashClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetCrcFreq - * Description : Gets the clock frequency for CRC module - * This function gets the clock frequency for CRC moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetRngaFreq - * Description : Gets the clock frequency for RNGA module - * This function gets the clock frequency for RNGA moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetAdcFreq - * Description : Gets the clock frequency for ADC module - * This function gets the clock frequency for ADC moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kOsc0ErClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetCmpFreq - * Description : Gets the clock frequency for CMP module - * This function gets the clock frequency for CMP moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetVrefFreq - * Description : Gets the clock frequency for VREF module - * This function gets the clock frequency for VREF moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetPdbFreq - * Description : Gets the clock frequency for PDB module - * This function gets the clock frequency for PDB moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetFtmFreq - * Description : Gets the clock frequency for FTM module. (FlexTimers) - * This function gets the clock frequency for FTM moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kMcgFfClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetPitFreq - * Description : Gets the clock frequency for Pit module. - * This function gets the clock frequency for Pit moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetCmtFreq - * Description : Gets the clock frequency for CMT module. - * This function gets the clock frequency for CMT moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetEnetRmiiFreq - * Description : Gets the clock frequency for ENET module RMII clock. - * This function gets the clock frequency for ENET moudle RMII clock. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint8_t setting; - clock_names_t clockName; - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockRmiiSrc, &setting) != kSimHalSuccess) - { - return freq; - } - - if ((sim_rmii_clock_source_t)setting == kSimRmiiSrcExtalClk) - { - clockName = kEXTAL_Clock; - } - else - { - clockName = kENET_1588_CLKIN; - } - - CLOCK_SYS_GetFreq(clockName, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetEnetTimeStampFreq - * Description : Gets the clock frequency for ENET module TIME clock. - * This function gets the clock frequency for ENET moudle TIME clock. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint8_t setting; - clock_names_t clockName; - - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockTimeSrc, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_time_clock_source_t)setting) - { - case kSimTimeSrcCoreSysClk: /* Core/system clock */ - clockName = kCoreClock; - break; - case kSimTimeSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */ - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_pllfll_clock_sel_t)setting) - { - case kSimPllFllSelFll: /* Fll clock */ - clockName = kMcgFllClock; - break; - case kSimPllFllSelPll: /* Pll0 clock */ - clockName = kMcgPll0Clock; - break; - default: - clockName = kReserved; - break; - } - break; - case kSimTimeSrcOscerclk: /* OSCERCLK clock */ - clockName = kOsc0ErClock; - break; - case kSimTimeSrcExt: /* Enet 1588 clock */ - clockName = kENET_1588_CLKIN; - break; - default: - clockName = kReserved; - break; - } - - /* Get ref clock freq */ - CLOCK_SYS_GetFreq(clockName, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetUsbFreq - * Description : Gets the clock frequency for USB FS OTG module. - * This function gets the clock frequency for USB FS OTG moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint8_t setting; - clock_names_t clockName; - uint32_t frac = 0; - uint32_t divider = 0; - - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockUsbSrc, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_usb_clock_source_t)setting) - { - case kSimUsbSrcClkIn: /* Core/system clock */ - clockName = kUSB_CLKIN; - break; - case kSimUsbSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */ - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_pllfll_clock_sel_t)setting) - { - case kSimPllFllSelFll: /* Fll clock */ - clockName = kMcgFllClock; - break; - case kSimPllFllSelPll: /* Pll0 clock */ - clockName = kMcgPll0Clock; - break; - default: - clockName = kReserved; - break; - } - break; - default: - clockName = kReserved; - break; - } - - /* Get ref clock freq */ - CLOCK_SYS_GetFreq(clockName, &freq); - - /* Get divider and frac */ - CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbDiv, ÷r); - CLOCK_HAL_GetDivider(g_simBaseAddr[0], kClockDividerUsbFrac, &frac); - - /* Divider output clock = Divider input clock × [ (FRAC+1) / (DIV+1) ]*/ - freq = (freq) * (frac + 1) / (divider + 1); - - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetUsbdcdFreq - * Description : Gets the clock frequency for USB DCD module. - * This function gets the clock frequency for USB DCD moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSpiFreq - * Description : Gets the clock frequency for SPI module. - * This function gets the clock frequency for SPI moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetI2cFreq - * Description : Gets the clock frequency for I2C module. - * This function gets the clock frequency for I2C moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetUartFreq - * Description : Gets the clock frequency for UART module. - * This function gets the clock frequency for UART moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance) -{ - uint32_t freq = 0; - - switch (instance) - { - case 0: - case 1: - CLOCK_SYS_GetFreq(kSystemClock, &freq); - break; - case 2: - case 3: - case 4: - case 5: - CLOCK_SYS_GetFreq(kBusClock, &freq); - break; - default: - break; - } - - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSdhcFreq - * Description : Gets the clock frequency for SDHC module - * This function gets the clock frequency for SDHC moudle - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance) -{ - uint32_t freq = 0; - uint8_t setting; - clock_names_t clockName; - - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockSdhcSrc, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_sdhc_clock_source_t)setting) - { - case kSimSdhcSrcCoreSysClk: /* Core/system clock */ - clockName = kCoreClock; - break; - case kSimSdhcSrcPllFllSel: /* clock as selected by SOPT2[PLLFLLSEL]. */ - /* get the sim clock source setting*/ - if (CLOCK_HAL_GetSource(g_simBaseAddr[0], kClockPllfllSel, &setting) != kSimHalSuccess) - { - return freq; - } - - switch ((sim_pllfll_clock_sel_t)setting) - { - case kSimPllFllSelFll: /* Fll clock */ - clockName = kMcgFllClock; - break; - case kSimPllFllSelPll: /* Pll0 clock */ - clockName = kMcgPll0Clock; - break; - default: - clockName = kReserved; - break; - } - break; - case kSimSdhcSrcOscerclk: /* OSCERCLK clock */ - clockName = kOsc0ErClock; - break; - case kSimSdhcSrcExt: /* SDHC CLKIN clock */ - clockName = kSDHC0_CLKIN; - break; - default: - clockName = kReserved; - break; - } - - /* Get ref clock freq */ - CLOCK_SYS_GetFreq(clockName, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetSaiFreq - * Description : Gets the clock frequency for I2S module - * This function gets the clock frequency for I2S moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance) -{ - uint32_t freq = 0; - CLOCK_SYS_GetFreq(kBusClock, &freq); - return freq; -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_SYS_GetGpioFreq - * Description : Gets the clock frequency for GPIO module. - * This function gets the clock frequency for GPIO moudle. - * - *END**************************************************************************/ -uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance) -{ - uint32_t freq = 0; - - CLOCK_SYS_GetFreq(kSystemClock, &freq); - - return freq; -} -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.h deleted file mode 100644 index 56583a42a13..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.h +++ /dev/null @@ -1,1248 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_CLOCK_K64F12_H__) -#define __FSL_CLOCK_K64F12__H__ - -/*! @addtogroup clock_manager*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief Gets the clock frequency for DMA module. - * - * This function gets the clock frequence for DMA moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetDmaFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for DMAMUX module. - * - * This function gets the clock frequence for DMAMUX moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetDmamuxFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for PORT module. - * - * This function gets the clock frequence for PORT moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for MPU module. - * - * This function gets the clock frequence for MPU moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetMpuFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for EWM module. - * - * This function gets the clock frequence for EWM moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for FLEXBUS module. - * - * This function gets the clock frequence for FLEXBUS moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for FTF module. (Flash Memory) - * - * This function gets the clock frequence for FTF module. (Flash Memory) - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for CRC module. - * - * This function gets the clock frequence for CRC module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for RNGA module. - * - * This function gets the clock frequence for RNGA module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for ADC module. - * - * This function gets the clock frequence for ADC module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for CMP module. - * - * This function gets the clock frequence for CMP module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetCmpFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for VREF module. - * - * This function gets the clock frequence for VREF module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetVrefFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for PDB module. - * - * This function gets the clock frequence for PDB module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetPdbFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for FTM module. (FlexTimer) - * - * This function gets the clock frequence for FTM module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetFtmFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for PIT module. - * - * This function gets the clock frequence for PIT module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetPitFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for CMT module. - * - * This function gets the clock frequence for CMT module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetCmtFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for ENET module RMII clock. - * - * This function gets the clock frequence for ENET module RMII clock.. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetEnetRmiiFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for ENET module TIME clock. - * - * This function gets the clock frequence for ENET module TIME clock.. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetEnetTimeStampFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for USB FS OTG module - * - * This function gets the clock frequence for USB FS OTG module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for USB DCD module - * - * This function gets the clock frequence for USB DCD module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetUsbdcdFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for SPI module - * - * This function gets the clock frequence for SPI module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for I2C module - * - * This function gets the clock frequence for I2C module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetI2cFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for UART module - * - * This function gets the clock frequence for UART module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for SDHC module. - * - * This function gets the clock frequence for SDHC moudle. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetSdhcFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for I2S module. - * - * This function gets the clock frequence for I2S module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetSaiFreq(uint32_t instance); - -/*! - * @brief Gets the clock frequency for GPIO module - * - * This function gets the clock frequence for GPIO module. - * @param instance module device instance - * @return freq clock frequence for this module - */ -uint32_t CLOCK_SYS_GetGpioFreq(uint32_t instance); - -/*! - * @brief Enable the clock for DMA module. - * - * This function enables the clock for DMA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableDmaClock(uint32_t instance) -{ - SIM_HAL_EnableDmaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for DMA module. - * - * This function disables the clock for DMA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableDmaClock(uint32_t instance) -{ - SIM_HAL_DisableDmaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for DMA module. - * - * This function will get the clock gate state for DMA moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetDmaGateCmd(uint32_t instance) -{ - return SIM_HAL_GetDmaGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for DMAMUX module. - * - * This function enables the clock for DMAMUX moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableDmamuxClock(uint32_t instance) -{ - SIM_HAL_EnableDmamuxClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for DMAMUX module. - * - * This function disables the clock for DMAMUX moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableDmamuxClock(uint32_t instance) -{ - SIM_HAL_DisableDmamuxClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for DMAMUX module. - * - * This function will get the clock gate state for DMAMUX moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetDmamuxGateCmd(uint32_t instance) -{ - return SIM_HAL_GetDmamuxGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for PORT module. - * - * This function enables the clock for PORT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnablePortClock(uint32_t instance) -{ - SIM_HAL_EnablePortClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for PORT module. - * - * This function disables the clock for PORT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisablePortClock(uint32_t instance) -{ - SIM_HAL_DisablePortClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for PORT module. - * - * This function will get the clock gate state for PORT moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetPortGateCmd(uint32_t instance) -{ - return SIM_HAL_GetPortGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for MPU module. - * - * This function enables the clock for MPU moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableMpuClock(uint32_t instance) -{ - SIM_HAL_EnableMpuClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for MPU module. - * - * This function disables the clock for MPU moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableMpuClock(uint32_t instance) -{ - SIM_HAL_DisableMpuClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for MPU module. - * - * This function will get the clock gate state for MPU moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetMpuGateCmd(uint32_t instance) -{ - return SIM_HAL_GetMpuGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for EWM module. - * - * This function enables the clock for EWM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableEwmClock(uint32_t instance) -{ - SIM_HAL_EnableEwmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for EWM module. - * - * This function disables the clock for EWM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableEwmClock(uint32_t instance) -{ - SIM_HAL_DisableEwmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for EWM module. - * - * This function will get the clock gate state for EWM moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance) -{ - return SIM_HAL_GetEwmGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FLEXBUS module. - * - * This function enables the clock for FLEXBUS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance) -{ - SIM_HAL_EnableFlexbusClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FLEXBUS module. - * - * This function disables the clock for FLEXBUS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance) -{ - SIM_HAL_DisableFlexbusClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FLEXBUS module. - * - * This function will get the clock gate state for FLEXBUS moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFlexbusGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FTF module. - * - * This function enables the clock for FTF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFtfClock(uint32_t instance) -{ - SIM_HAL_EnableFtfClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FTF module. - * - * This function disables the clock for FTF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFtfClock(uint32_t instance) -{ - SIM_HAL_DisableFtfClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FTF module. - * - * This function will get the clock gate state for FTF moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFtfGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFtfGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for CRC module. - * - * This function enables the clock for CRC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableCrcClock(uint32_t instance) -{ - SIM_HAL_EnableCrcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for CRC module. - * - * This function disables the clock for CRC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableCrcClock(uint32_t instance) -{ - SIM_HAL_DisableCrcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for CRC module. - * - * This function will get the clock gate state for CRC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetCrcGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for RNGA module. - * - * This function enables the clock for RNGA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance) -{ - SIM_HAL_EnableRngaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for RNGA module. - * - * This function disables the clock for RNGA moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance) -{ - SIM_HAL_DisableRngaClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for RNGA module. - * - * This function will get the clock gate state for RNGA moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance) -{ - return SIM_HAL_GetRngaGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for ADC module. - * - * This function enables the clock for ADC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableAdcClock(uint32_t instance) -{ - SIM_HAL_EnableAdcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for ADC module. - * - * This function disables the clock for ADC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableAdcClock(uint32_t instance) -{ - SIM_HAL_DisableAdcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for ADC module. - * - * This function will get the clock gate state for ADC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetAdcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetAdcGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for CMP module. - * - * This function enables the clock for CMP moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableCmpClock(uint32_t instance) -{ - SIM_HAL_EnableCmpClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for CMP module. - * - * This function disables the clock for CMP moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableCmpClock(uint32_t instance) -{ - SIM_HAL_DisableCmpClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for CMP module. - * - * This function will get the clock gate state for CMP moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetCmpGateCmd(uint32_t instance) -{ - return SIM_HAL_GetCmpGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for DAC module. - * - * This function enables the clock for DAC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableDacClock(uint32_t instance) -{ - SIM_HAL_EnableDacClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for DAC module. - * - * This function disables the clock for DAC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableDacClock(uint32_t instance) -{ - SIM_HAL_DisableDacClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for DAC module. - * - * This function will get the clock gate state for DAC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetDacGateCmd(uint32_t instance) -{ - return SIM_HAL_GetDacGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for VREF module. - * - * This function enables the clock for VREF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableVrefClock(uint32_t instance) -{ - SIM_HAL_EnableVrefClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for VREF module. - * - * This function disables the clock for VREF moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableVrefClock(uint32_t instance) -{ - SIM_HAL_DisableVrefClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for VREF module. - * - * This function will get the clock gate state for VREF moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetVrefGateCmd(uint32_t instance) -{ - return SIM_HAL_GetVrefGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for SAI module. - * - * This function enables the clock for SAI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableSaiClock(uint32_t instance) -{ - SIM_HAL_EnableSaiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for SAI module. - * - * This function disables the clock for SAI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableSaiClock(uint32_t instance) -{ - SIM_HAL_DisableSaiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for SAI module. - * - * This function will get the clock gate state for SAI moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetSaiGateCmd(uint32_t instance) -{ - return SIM_HAL_GetSaiGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for PDB module. - * - * This function enables the clock for PDB moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnablePdbClock(uint32_t instance) -{ - SIM_HAL_EnablePdbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for PDB module. - * - * This function disables the clock for PDB moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisablePdbClock(uint32_t instance) -{ - SIM_HAL_DisablePdbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for PDB module. - * - * This function will get the clock gate state for PDB moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetPdbGateCmd(uint32_t instance) -{ - return SIM_HAL_GetPdbGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FTM module. - * - * This function enables the clock for FTM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFtmClock(uint32_t instance) -{ - SIM_HAL_EnableFtmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FTM module. - * - * This function disables the clock for FTM moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFtmClock(uint32_t instance) -{ - SIM_HAL_DisableFtmClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FTM module. - * - * This function will get the clock gate state for FTM moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFtmGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFtmGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for PIT module. - * - * This function enables the clock for PIT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnablePitClock(uint32_t instance) -{ - SIM_HAL_EnablePitClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for PIT module. - * - * This function disables the clock for PIT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisablePitClock(uint32_t instance) -{ - SIM_HAL_DisablePitClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for PIT module. - * - * This function will get the clock gate state for PIT moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetPitGateCmd(uint32_t instance) -{ - return SIM_HAL_GetPitGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for LPTIMER module. - * - * This function enables the clock for LPTIMER moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableLptimerClock(uint32_t instance) -{ - SIM_HAL_EnableLptimerClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for LPTIMER module. - * - * This function disables the clock for LPTIMER moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableLptimerClock(uint32_t instance) -{ - SIM_HAL_DisableLptimerClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for LPTIMER module. - * - * This function will get the clock gate state for LPTIMER moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetLptimerGateCmd(uint32_t instance) -{ - return SIM_HAL_GetLptimerGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for CMT module. - * - * This function enables the clock for CMT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableCmtClock(uint32_t instance) -{ - SIM_HAL_EnableCmtClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for CMT module. - * - * This function disables the clock for CMT moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableCmtClock(uint32_t instance) -{ - SIM_HAL_DisableCmtClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for CMT module. - * - * This function will get the clock gate state for CMT moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetCmtGateCmd(uint32_t instance) -{ - return SIM_HAL_GetCmtGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for RTC module. - * - * This function enables the clock for RTC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableRtcClock(uint32_t instance) -{ - SIM_HAL_EnableRtcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for RTC module. - * - * This function disables the clock for RTC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableRtcClock(uint32_t instance) -{ - SIM_HAL_DisableRtcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for RTC module. - * - * This function will get the clock gate state for RTC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetRtcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetRtcGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for ENET module. - * - * This function enables the clock for ENET moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableEnetClock(uint32_t instance) -{ - SIM_HAL_EnableEnetClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for ENET module. - * - * This function disables the clock for ENET moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableEnetClock(uint32_t instance) -{ - SIM_HAL_DisableEnetClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for ENET module. - * - * This function will get the clock gate state for ENET moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetEnetGateCmd(uint32_t instance) -{ - return SIM_HAL_GetEnetGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for USBFS module. - * - * This function enables the clock for USBFS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableUsbClock(uint32_t instance) -{ - SIM_HAL_EnableUsbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for USBFS module. - * - * This function disables the clock for USBFS moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableUsbClock(uint32_t instance) -{ - SIM_HAL_DisableUsbClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for USB module. - * - * This function will get the clock gate state for USB moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetUsbGateCmd(uint32_t instance) -{ - return SIM_HAL_GetUsbGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for USBDCD module. - * - * This function enables the clock for USBDCD moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableUsbdcdClock(uint32_t instance) -{ - SIM_HAL_EnableUsbdcdClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for USBDCD module. - * - * This function disables the clock for USBDCD moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableUsbdcdClock(uint32_t instance) -{ - SIM_HAL_DisableUsbdcdClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for USBDCD module. - * - * This function will get the clock gate state for USBDCD moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetUsbdcdGateCmd(uint32_t instance) -{ - return SIM_HAL_GetUsbdcdGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for FLEXCAN module. - * - * This function enables the clock for FLEXCAN moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableFlexcanClock(uint32_t instance) -{ - SIM_HAL_EnableFlexcanClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for FLEXCAN module. - * - * This function disables the clock for FLEXCAN moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableFlexcanClock(uint32_t instance) -{ - SIM_HAL_DisableFlexcanClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for FLEXCAN module. - * - * This function will get the clock gate state for FLEXCAN moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetFlexcanGateCmd(uint32_t instance) -{ - return SIM_HAL_GetFlexcanGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for SPI module. - * - * This function enables the clock for SPI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableSpiClock(uint32_t instance) -{ - SIM_HAL_EnableSpiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for SPI module. - * - * This function disables the clock for SPI moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableSpiClock(uint32_t instance) -{ - SIM_HAL_DisableSpiClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for SPI module. - * - * This function will get the clock gate state for SPI moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetSpiGateCmd(uint32_t instance) -{ - return SIM_HAL_GetSpiGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for I2C module. - * - * This function enables the clock for I2C moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableI2cClock(uint32_t instance) -{ - SIM_HAL_EnableI2cClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for I2C module. - * - * This function disables the clock for I2C moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableI2cClock(uint32_t instance) -{ - SIM_HAL_DisableI2cClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for I2C module. - * - * This function will get the clock gate state for I2C moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetI2cGateCmd(uint32_t instance) -{ - return SIM_HAL_GetI2cGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for UART module. - * - * This function enables the clock for UART moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableUartClock(uint32_t instance) -{ - SIM_HAL_EnableUartClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for UART module. - * - * This function disables the clock for UART moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableUartClock(uint32_t instance) -{ - SIM_HAL_DisableUartClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for UART module. - * - * This function will get the clock gate state for UART moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetUartGateCmd(uint32_t instance) -{ - return SIM_HAL_GetUartGateCmd(g_simBaseAddr[0], instance); -} - -/*! - * @brief Enable the clock for SDHC module. - * - * This function enables the clock for SDHC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_EnableSdhcClock(uint32_t instance) -{ - SIM_HAL_EnableSdhcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Disable the clock for SDHC module. - * - * This function disables the clock for SDHC moudle. - * @param instance module device instance - */ -static inline void CLOCK_SYS_DisableSdhcClock(uint32_t instance) -{ - SIM_HAL_DisableSdhcClock(g_simBaseAddr[0], instance); -} - -/*! - * @brief Get the the clock gate state for SDHC module. - * - * This function will get the clock gate state for SDHC moudle. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -static inline bool CLOCK_SYS_GetSdhcGateCmd(uint32_t instance) -{ - return SIM_HAL_GetSdhcGateCmd(g_simBaseAddr[0], instance); -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __FSL_CLOCK_K64F12_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.c deleted file mode 100644 index 9ab02eccd47..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.c +++ /dev/null @@ -1,1410 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "fsl_device_registers.h" -#include "fsl_sim_hal_K64F12.h" -#include "fsl_sim_hal.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief CLOCK name config table for K64*/ -const clock_name_config_t kClockNameConfigTable [] = { - {false, kSystemClock, kClockDividerOutdiv1}, - {false, kSystemClock, kClockDividerOutdiv1}, - {false, kSystemClock, kClockDividerOutdiv1}, - {false, kSystemClock, kClockDividerOutdiv2}, - {false, kSystemClock, kClockDividerOutdiv3}, - {false, kSystemClock, kClockDividerOutdiv4} -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableDmaClock - * Description : Enable the clock for DMA module - * This function enables the clock for DMA moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_DMA(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableDmaClock - * Description : Disable the clock for DMA module - * This function disables the clock for DMA moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableDmaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_DMA(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetDmaGateCmd - * Description : Get the the clock gate state for DMA module - * This function will get the clock gate state for DMA moudle - * - *END**************************************************************************/ -bool SIM_HAL_GetDmaGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC7_DMA(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableDmamuxClock - * Description : Enable the clock for DMAMUX module - * This function enables the clock for DMAMUX moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableDmamuxClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_DMAMUX(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableDmamuxClock - * Description : Disable the clock for DMAMUX module - * This function disables the clock for DMAMUX moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableDmamuxClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_DMAMUX(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetDmamuxGateCmd - * Description : Get the the clock gate state for DMAMUX module - * This function will get the clock gate state for DMAMUX moudle - * - *END**************************************************************************/ -bool SIM_HAL_GetDmamuxGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_DMAMUX(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnablePortClock - * Description : Enable the clock for PORT module - * This function enables the clock for PORT moudle - * - *END**************************************************************************/ -void SIM_HAL_EnablePortClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC5_PORTA(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC5_PORTB(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC5_PORTC(baseAddr, 1); - break; - case 3: - BW_SIM_SCGC5_PORTD(baseAddr, 1); - break; - case 4: - BW_SIM_SCGC5_PORTE(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisablePortClock - * Description : Disable the clock for PORT module - * This function disables the clock for PORT moudle - * - *END**************************************************************************/ -void SIM_HAL_DisablePortClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC5_PORTA(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC5_PORTB(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC5_PORTC(baseAddr, 0); - break; - case 3: - BW_SIM_SCGC5_PORTD(baseAddr, 0); - break; - case 4: - BW_SIM_SCGC5_PORTE(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetPortGateCmd - * Description : Get the the clock gate state for PORT module - * This function will get the clock gate state for PORT moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetPortGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC5_PORTA(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC5_PORTB(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC5_PORTC(baseAddr); - break; - case 3: - retValue = BR_SIM_SCGC5_PORTD(baseAddr); - break; - case 4: - retValue = BR_SIM_SCGC5_PORTE(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableMpuClock - * Description : Enable the clock for MPU module - * This function enables the clock for MPU moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableMpuClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_MPU(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableMpuClock - * Description : Disable the clock for MPU module. - * This function disables the clock for MPU moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableMpuClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_MPU(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetMpuGateCmd - * Description : Get the the clock gate state for MPU module - * This function will get the clock gate state for MPU moudl. - * - *END**************************************************************************/ -bool SIM_HAL_GetMpuGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC7_MPU(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableEwmClock - * Description : Enable the clock for EWM module - * This function enables the clock for EWM moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableEwmClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_EWM(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableEwmClock - * Description : Disable the clock for EWM modul - * This function disables the clock for EWM moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_EWM(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetEwmGateCmd - * Description : Get the the clock gate state for EWM module - * This function will get the clock gate state for EWM moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_EWM(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFlexbusClock - * Description : Enable the clock for FLEXBUS module - * This function enables the clock for FLEXBUS moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_FLEXBUS(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFlexbusClock - * Description : Disable the clock for FLEXBUS module - * This function disables the clock for FLEXBUS moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC7_FLEXBUS(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFlexbusGateCmd - * Description : Get the the clock gate state for FLEXBUS module - * This function will get the clock gate state for FLEXBUS moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC7_FLEXBUS(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFtfClock - * Description : Enable the clock for FTF module - * This function enables the clock for FTF moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableFtfClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_FTF(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFtfClock - * Description : Disable the clock for FTF module - * This function disables the clock for FTF moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableFtfClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_FTF(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtfGateCmd - * Description : Get the the clock gate state for FTF module - * This function will get the clock gate state for FTF moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFtfGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_FTF(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableCrcClock - * Description : Enable the clock for CRC module - * This function enables the clock for CRC moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableCrcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_CRC(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableCrcClock - * Description : Disable the clock for CRC module - * This function disables the clock for CRC moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_CRC(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetCrcGateCmd - * Description : Get the the clock gate state for CRC module - * This function will get the clock gate state for CRC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_CRC(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableRngaClock - * Description : Enable the clock for RNGA module - * This function enables the clock for RNGA moudle. - * - *END**************************************************************************/ -void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RNGA(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableRngaClock - * Description : Disable the clock for RNGA module - * This function disables the clock for RNGA moudle. - * - *END**************************************************************************/ -void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RNGA(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetRngaGateCmd - * Description : Get the the clock gate state for RNGA module - * This function will get the clock gate state for RNGA moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_RNGA(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableAdcClock - * Description : Enable the clock for ADC module - * This function enables the clock for ADC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableAdcClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_ADC0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC3_ADC1(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableAdcClock - * Description : Disable the clock for ADC module - * This function disables the clock for ADC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableAdcClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_ADC0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC3_ADC1(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetAdcGateCmd - * Description : Get the the clock gate state for ADC module - * This function will get the clock gate state for ADC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetAdcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_ADC0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC3_ADC1(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableCmpClock - * Description : Enable the clock for CMP module - * This function enables the clock for CMP moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableCmpClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_CMP(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableCmpClock - * Description : Disable the clock for CMP module - * This function disables the clock for CMP moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableCmpClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_CMP(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetCmpGateCmd - * Description : Get the the clock gate state for CMP module - * This function will get the clock gate state for CMP moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetCmpGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_CMP(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableDacClock - * Description : Enable the clock for DAC module - * This function enables the clock for DAC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC2_DAC0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC2_DAC1(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableDacClock - * Description : Disable the clock for DAC module - * This function disables the clock for DAC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC2_DAC0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC2_DAC1(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetDacGateCmd - * Description : Get the the clock gate state for DAC module - * This function will get the clock gate state for DAC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC2_DAC0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC2_DAC1(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableVrefClock - * Description : Enable the clock for VREF module - * This function enables the clock for VREF moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableVrefClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_VREF(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableVrefClock - * Description : Disable the clock for VREF module - * This function disables the clock for VREF moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableVrefClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_VREF(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetVrefGateCmd - * Description : Get the the clock gate state for VREF module - * This function will get the clock gate state for VREF moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetVrefGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_VREF(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableSaiClock - * Description : Enable the clock for SAI module - * This function enables the clock for SAI moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableSaiClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_I2S(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableSaiClock - * Description : Disable the clock for SAI module - * This function disables the clock for SAI moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableSaiClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_I2S(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetSaiGateCmd - * Description : Get the the clock gate state for SAI module - * This function will get the clock gate state for SAI moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetSaiGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_I2S(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnablePdbClock - * Description : Enable the clock for PDB module - * This function enables the clock for PDB moudle - * - *END**************************************************************************/ -void SIM_HAL_EnablePdbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PDB(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisablePdbClock - * Description : Disable the clock for PDB module - * This function disables the clock for PDB moudle - * - *END**************************************************************************/ -void SIM_HAL_DisablePdbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PDB(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetPdbGateCmd - * Description : Get the the clock gate state for PDB module - * This function will get the clock gate state for PDB moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetPdbGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_PDB(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFtmClock - * Description : Enable the clock for FTM module - * This function enables the clock for FTM moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_FTM0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC6_FTM1(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC6_FTM2(baseAddr, 1); - break; - case 3: - BW_SIM_SCGC3_FTM3(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFtmClock - * Description : Disable the clock for FTM module - * This function disables the clock for FTM moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_FTM0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC6_FTM1(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC6_FTM2(baseAddr, 0); - break; - case 3: - BW_SIM_SCGC3_FTM3(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFtmGateCmd - * Description : Get the the clock gate state for FTM module - * This function will get the clock gate state for FTM moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_FTM0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC6_FTM1(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC6_FTM2(baseAddr); - break; - case 3: - retValue = BR_SIM_SCGC3_FTM3(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnablePitClock - * Description : Enable the clock for PIT module - * This function enables the clock for PIT moudle - * - *END**************************************************************************/ -void SIM_HAL_EnablePitClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PIT(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisablePitClock - * Description : Disable the clock for PIT module - * This function disables the clock for PIT moudle - * - *END**************************************************************************/ -void SIM_HAL_DisablePitClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_PIT(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetPitGateCmd - * Description : Get the the clock gate state for PIT module - * This function will get the clock gate state for PIT moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetPitGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_PIT(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableLptimerClock - * Description : Enable the clock for LPTIMER module - * This function enables the clock for LPTIMER moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableLptimerClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC5_LPTMR(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableLptimerClock - * Description : Disable the clock for LPTIMER module - * This function disables the clock for LPTIMER moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableLptimerClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC5_LPTMR(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetLptimerGateCmd - * Description : Get the the clock gate state for LPTIMER module - * This function will get the clock gate state for LPTIMER moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetLptimerGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC5_LPTMR(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableCmtClock - * Description : Enable the clock for CMT module - * This function enables the clock for CMT moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableCmtClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_CMT(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableCmtClock - * Description : Disable the clock for CMT module - * This function disables the clock for CMT moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableCmtClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_CMT(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetCmtGateCmd - * Description : Get the the clock gate state for CMT module - * This function will get the clock gate state for CMT moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetCmtGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_CMT(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableRtcClock - * Description : Enable the clock for RTC module - * This function enables the clock for RTC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableRtcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RTC(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableRtcClock - * Description : Disable the clock for RTC module - * This function disables the clock for RTC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableRtcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_RTC(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetRtcGateCmd - * Description : Get the the clock gate state for RTC module - * This function will get the clock gate state for RTC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetRtcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_RTC(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableEnetClock - * Description : Enable the clock for ENET module - * This function enables the clock for ENET moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableEnetClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC2_ENET(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableEnetClock - * Description : Disable the clock for ENET module - * This function disables the clock for ENET moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableEnetClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC2_ENET(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetEnetGateCmd - * Description : Get the the clock gate state for ENET module - * This function will get the clock gate state for ENET moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetEnetGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC2_ENET(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableUsbClock - * Description : Enable the clock for USBFS module - * This function enables the clock for USBFS moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableUsbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_USBOTG(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableUsbClock - * Description : Disable the clock for USBFS module - * This function disables the clock for USBFS moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableUsbClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC4_USBOTG(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUsbGateCmd - * Description : Get the the clock gate state for USB module - * This function will get the clock gate state for USB moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetUsbGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC4_USBOTG(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableUsbdcdClock - * Description : Enable the clock for USBDCD module - * This function enables the clock for USBDCD moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableUsbdcdClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_USBDCD(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableUsbdcdClock - * Description : Disable the clock for USBDCD module - * This function disables the clock for USBDCD moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableUsbdcdClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_USBDCD(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUsbdcdGateCmd - * Description : Get the the clock gate state for USBDCD module - * This function will get the clock gate state for USBDCD moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetUsbdcdGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_USBDCD(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableFlexcanClock - * Description : Enable the clock for FLEXCAN module - * This function enables the clock for FLEXCAN moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableFlexcanClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_FLEXCAN0(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableFlexcanClock - * Description : Disable the clock for FLEXCAN module - * This function disables the clock for FLEXCAN moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableFlexcanClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC6_FLEXCAN0(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetFlexcanGateCmd - * Description : Get the the clock gate state for FLEXCAN module - * This function will get the clock gate state for FLEXCAN moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetFlexcanGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC6_FLEXCAN0(baseAddr); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableSpiClock - * Description : Enable the clock for SPI module - * This function enables the clock for SPI moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableSpiClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_SPI0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC6_SPI1(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC3_SPI2(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableSpiClock - * Description : Disable the clock for SPI module - * This function disables the clock for SPI moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableSpiClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC6_SPI0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC6_SPI1(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC3_SPI2(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetSpiGateCmd - * Description : Get the the clock gate state for SPI module - * This function will get the clock gate state for SPI moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetSpiGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC6_SPI0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC6_SPI1(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC3_SPI2(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableI2cClock - * Description : Enable the clock for I2C module - * This function enables the clock for I2C moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableI2cClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_I2C0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC4_I2C1(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC1_I2C2(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableI2cClock - * Description : Disable the clock for I2C module - * This function disables the clock for I2C moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableI2cClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_I2C0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC4_I2C1(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC1_I2C2(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetI2cGateCmd - * Description : Get the the clock gate state for I2C module - * This function will get the clock gate state for I2C moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetI2cGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC4_I2C0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC4_I2C1(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC1_I2C2(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableUartClock - * Description : Enable the clock for UART module - * This function enables the clock for UART moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableUartClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_UART0(baseAddr, 1); - break; - case 1: - BW_SIM_SCGC4_UART1(baseAddr, 1); - break; - case 2: - BW_SIM_SCGC4_UART2(baseAddr, 1); - break; - case 3: - BW_SIM_SCGC4_UART3(baseAddr, 1); - break; - case 4: - BW_SIM_SCGC1_UART4(baseAddr, 1); - break; - case 5: - BW_SIM_SCGC1_UART5(baseAddr, 1); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableUartClock - * Description : Disable the clock for UART module - * This function disables the clock for UART moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableUartClock(uint32_t baseAddr, uint32_t instance) -{ - switch (instance) - { - case 0: - BW_SIM_SCGC4_UART0(baseAddr, 0); - break; - case 1: - BW_SIM_SCGC4_UART1(baseAddr, 0); - break; - case 2: - BW_SIM_SCGC4_UART2(baseAddr, 0); - break; - case 3: - BW_SIM_SCGC4_UART3(baseAddr, 0); - break; - case 4: - BW_SIM_SCGC1_UART4(baseAddr, 0); - break; - case 5: - BW_SIM_SCGC1_UART5(baseAddr, 0); - break; - default: - break; - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetUartGateCmd - * Description : Get the the clock gate state for UART module - * This function will get the clock gate state for UART moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetUartGateCmd(uint32_t baseAddr, uint32_t instance) -{ - bool retValue = false; - - switch (instance) - { - case 0: - retValue = BR_SIM_SCGC4_UART0(baseAddr); - break; - case 1: - retValue = BR_SIM_SCGC4_UART1(baseAddr); - break; - case 2: - retValue = BR_SIM_SCGC4_UART2(baseAddr); - break; - case 3: - retValue = BR_SIM_SCGC4_UART3(baseAddr); - break; - case 4: - retValue = BR_SIM_SCGC1_UART4(baseAddr); - break; - case 5: - retValue = BR_SIM_SCGC1_UART5(baseAddr); - break; - default: - retValue = false; - break; - } - - return retValue; -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_EnableSdhcClock - * Description : Enable the clock for SDHC module - * This function enables the clock for SDHC moudle - * - *END**************************************************************************/ -void SIM_HAL_EnableSdhcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC3_SDHC(baseAddr, 1); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_DisableSdhcClock - * Description : Disable the clock for SDHC module - * This function disables the clock for SDHC moudle - * - *END**************************************************************************/ -void SIM_HAL_DisableSdhcClock(uint32_t baseAddr, uint32_t instance) -{ - BW_SIM_SCGC3_SDHC(baseAddr, 0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : SIM_HAL_GetSdhcGateCmd - * Description : Get the the clock gate state for SDHC module - * This function will get the clock gate state for SDHC moudle. - * - *END**************************************************************************/ -bool SIM_HAL_GetSdhcGateCmd(uint32_t baseAddr, uint32_t instance) -{ - return BR_SIM_SCGC3_SDHC(baseAddr); -} -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.h deleted file mode 100644 index 0baa9f17e49..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.h +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(__FSL_SIM_HAL_K64F12_H__) -#define __FSL_SIM_HAL_K64F12_H__ - -/*! @addtogroup sim_hal*/ -/*! @{*/ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief SIM SDHC clock source */ -typedef enum _sim_sdhc_clock_source -{ - kSimSdhcSrcCoreSysClk, /* Core/system clock */ - kSimSdhcSrcPllFllSel, /* clock as selected by SOPT2[PLLFLLSEL]. */ - kSimSdhcSrcOscerclk, /* OSCERCLK clock */ - kSimSdhcSrcExt /* External bypass clock (SDHC0_CLKIN) */ -} sim_sdhc_clock_source_t; - -/*! @brief SIM TIME clock source */ -typedef enum _sim_time_clock_source -{ - kSimTimeSrcCoreSysClk, /* Core/system clock */ - kSimTimeSrcPllFllSel, /* clock as selected by SOPT2[PLLFLLSEL]. */ - kSimTimeSrcOscerclk, /* OSCERCLK clock */ - kSimTimeSrcExt /* ENET 1588 clock in (ENET_1588_CLKIN) */ -} sim_time_clock_source_t; - -/*! @brief SIM RMII clock source */ -typedef enum _sim_rmii_clock_source -{ - kSimRmiiSrcExtalClk, /* EXTAL Clock */ - kSimRmiiSrcExt /* ENET 1588 clock in (ENET_1588_CLKIN) */ -} sim_rmii_clock_source_t; - -/*! @brief SIM USB clock source */ -typedef enum _sim_usb_clock_source -{ - kSimUsbSrcClkIn, /* USB CLKIN Clock */ - kSimUsbSrcPllFllSel /* clock as selected by SOPT2[PLLFLLSEL] */ -} sim_usb_clock_source_t; - -/*! @brief SIM PLLFLLSEL clock source select */ -typedef enum _sim_pllfll_clock_sel -{ - kSimPllFllSelFll, /* Fll clock */ - kSimPllFllSelPll /* Pll0 clock */ -} sim_pllfll_clock_sel_t; - -/*! @brief SIM OSC32KSEL clock source select */ -typedef enum _sim_osc32k_clock_sel -{ - kSimOsc32kSelOsc32k, /* OSC 32k clock */ - kSimOsc32kSelReserved, /* Reserved */ - kSimOsc32kSelRtc32k, /* RTC 32k clock */ - kSimOsc32kSelLpo /* LPO clock */ -} sim_osc32k_clock_sel_t; - -/*! @brief SIM TRACESEL clock source select */ -typedef enum _sim_trace_clock_sel -{ - kSimTraceMcgoutClk, /* MCG out clock */ - kSimTraceCoreClk /* core clock */ -} sim_trace_clock_sel_t; - -/*! @brief SIM CLKOUT_SEL clock source select */ -typedef enum _sim_clkout_clock_sel -{ - kSimClkoutFlexbusClk, /* Flexbus clock */ - kSimClkoutReserved, /* Reserved */ - kSimClkoutFlashClk, /* Flash clock */ - kSimClkoutLpoClk, /* LPO clock */ - kSimClkoutMcgIrcClk, /* MCG out clock */ - kSimClkoutRtc32kClk, /* RTC 32k clock */ - kSimClkoutReserved1 -} sim_clkout_clock_sel_t; - -/*! @brief SIM RTCCLKOUTSEL clock source select */ -typedef enum _sim_rtcclkout_clock_sel -{ - kSimRtcClkout1hzClk, /* 1Hz clock */ - kSimRtcClkout32kClk /* 32KHz clock */ -} sim_rtcclkout_clock_sel_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name IP related clock feature APIs*/ -/*@{*/ - -/*! - * @brief Enable the clock for DMA module. - * - * This function enables the clock for DMA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for DMA module. - * - * This function disables the clock for DMA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableDmaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for DMA module. - * - * This function will get the clock gate state for DMA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetDmaGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for DMAMUX module. - * - * This function enables the clock for DMAMUX moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableDmamuxClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for DMAMUX module. - * - * This function disables the clock for DMAMUX moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableDmamuxClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for DMAMUX module. - * - * This function will get the clock gate state for DMAMUX moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetDmamuxGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for PORT module. - * - * This function enables the clock for PORT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnablePortClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for PORT module. - * - * This function disables the clock for PORT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisablePortClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for PORT module. - * - * This function will get the clock gate state for PORT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetPortGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for MPU module. - * - * This function enables the clock for MPU moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableMpuClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for MPU module. - * - * This function disables the clock for MPU moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableMpuClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for MPU module. - * - * This function will get the clock gate state for MPU moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetMpuGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for EWM module. - * - * This function enables the clock for EWM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableEwmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for EWM module. - * - * This function disables the clock for EWM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for EWM module. - * - * This function will get the clock gate state for EWM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FLEXBUS module. - * - * This function enables the clock for FLEXBUS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FLEXBUS module. - * - * This function disables the clock for FLEXBUS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FLEXBUS module. - * - * This function will get the clock gate state for FLEXBUS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FTF module. - * - * This function enables the clock for FTF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFtfClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FTF module. - * - * This function disables the clock for FTF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFtfClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FTF module. - * - * This function will get the clock gate state for FTF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFtfGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for CRC module. - * - * This function enables the clock for CRC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableCrcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for CRC module. - * - * This function disables the clock for CRC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for CRC module. - * - * This function will get the clock gate state for CRC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for RNGA module. - * - * This function enables the clock for RNGA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for RNGA module. - * - * This function disables the clock for RNGA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for RNGA module. - * - * This function will get the clock gate state for RNGA moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for ADC module. - * - * This function enables the clock for ADC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableAdcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for ADC module. - * - * This function disables the clock for ADC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableAdcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for ADC module. - * - * This function will get the clock gate state for ADC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetAdcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for CMP module. - * - * This function enables the clock for CMP moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableCmpClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for CMP module. - * - * This function disables the clock for CMP moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableCmpClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for CMP module. - * - * This function will get the clock gate state for CMP moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetCmpGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for DAC module. - * - * This function enables the clock for DAC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for DAC module. - * - * This function disables the clock for DAC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for DAC module. - * - * This function will get the clock gate state for DAC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for VREF module. - * - * This function enables the clock for VREF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableVrefClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for VREF module. - * - * This function disables the clock for VREF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableVrefClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for VREF module. - * - * This function will get the clock gate state for VREF moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetVrefGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for SAI module. - * - * This function enables the clock for SAI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableSaiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for SAI module. - * - * This function disables the clock for SAI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableSaiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for SAI module. - * - * This function will get the clock gate state for SAI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetSaiGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for PDB module. - * - * This function enables the clock for PDB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnablePdbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for PDB module. - * - * This function disables the clock for PDB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisablePdbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for PDB module. - * - * This function will get the clock gate state for PDB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetPdbGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FTM module. - * - * This function enables the clock for FTM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FTM module. - * - * This function disables the clock for FTM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FTM module. - * - * This function will get the clock gate state for FTM moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for PIT module. - * - * This function enables the clock for PIT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnablePitClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for PIT module. - * - * This function disables the clock for PIT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisablePitClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for PIT module. - * - * This function will get the clock gate state for PIT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetPitGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for LPTIMER module. - * - * This function enables the clock for LPTIMER moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableLptimerClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for LPTIMER module. - * - * This function disables the clock for LPTIMER moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableLptimerClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for LPTIMER module. - * - * This function will get the clock gate state for LPTIMER moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetLptimerGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for CMT module. - * - * This function enables the clock for CMT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableCmtClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for CMT module. - * - * This function disables the clock for CMT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableCmtClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for CMT module. - * - * This function will get the clock gate state for CMT moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetCmtGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for RTC module. - * - * This function enables the clock for RTC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableRtcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for RTC module. - * - * This function disables the clock for RTC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableRtcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for RTC module. - * - * This function will get the clock gate state for RTC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetRtcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for ENET module. - * - * This function enables the clock for ENET moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableEnetClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for ENET module. - * - * This function disables the clock for ENET moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableEnetClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for ENET module. - * - * This function will get the clock gate state for ENET moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetEnetGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for USBFS module. - * - * This function enables the clock for USBFS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableUsbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for USBFS module. - * - * This function disables the clock for USBFS moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableUsbClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for USB module. - * - * This function will get the clock gate state for USB moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetUsbGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for USBDCD module. - * - * This function enables the clock for USBDCD moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableUsbdcdClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for USBDCD module. - * - * This function disables the clock for USBDCD moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableUsbdcdClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for USBDCD module. - * - * This function will get the clock gate state for USBDCD moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetUsbdcdGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for FLEXCAN module. - * - * This function enables the clock for FLEXCAN moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableFlexcanClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for FLEXCAN module. - * - * This function disables the clock for FLEXCAN moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableFlexcanClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for FLEXCAN module. - * - * This function will get the clock gate state for FLEXCAN moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetFlexcanGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for SPI module. - * - * This function enables the clock for SPI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableSpiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for SPI module. - * - * This function disables the clock for SPI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableSpiClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for SPI module. - * - * This function will get the clock gate state for SPI moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetSpiGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for I2C module. - * - * This function enables the clock for I2C moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableI2cClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for I2C module. - * - * This function disables the clock for I2C moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableI2cClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for I2C module. - * - * This function will get the clock gate state for I2C moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetI2cGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for UART module. - * - * This function enables the clock for UART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableUartClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for UART module. - * - * This function disables the clock for UART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableUartClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for UART module. - * - * This function will get the clock gate state for UART moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetUartGateCmd(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Enable the clock for SDHC module. - * - * This function enables the clock for SDHC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_EnableSdhcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Disable the clock for SDHC module. - * - * This function disables the clock for SDHC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - */ -void SIM_HAL_DisableSdhcClock(uint32_t baseAddr, uint32_t instance); - -/*! - * @brief Get the the clock gate state for SDHC module. - * - * This function will get the clock gate state for SDHC moudle. - * - * @param baseAddr Base address for current SIM instance. - * @param instance module device instance - * @return state true - ungated(Enabled), false - gated (Disabled) - */ -bool SIM_HAL_GetSdhcGateCmd(uint32_t baseAddr, uint32_t instance); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - - -/*! @}*/ - -#endif /* __FSL_SIM_HAL_K64F12_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralNames.h deleted file mode 100644 index ca94da8667d..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_0 = 0, - UART_1 = 1, - UART_2 = 2, - UART_3 = 3, - UART_4 = 4, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = 0, - I2C_1 = 1, - I2C_2 = 2, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 - PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 - PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 - PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 - PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 - PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 - PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 - PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 - PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 - PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 - PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 - PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 - PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 - // could be 4 or could be 3... not sure what register - // this is for... too much abstraction - PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 - PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 - PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 - PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 - PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 - PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 - PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 - PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 -typedef enum { - ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, - ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, - ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, - ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, - ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, - ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, - ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, - ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, - ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, - ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, - ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, - ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, - ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, - ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, - ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, - ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, - ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, - ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, - ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, - ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, - ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, - ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, - ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, - ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, - ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, - ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_0 = 0, - SPI_1 = 1, - SPI_2 = 2, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralPins.c deleted file mode 100644 index 92009d72410..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralPins.c +++ /dev/null @@ -1,208 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTA17, ADC1_SE17, 0}, - {PTB0 , ADC0_SE8 , 0}, - {PTB1 , ADC0_SE9 , 0}, - {PTB2 , ADC0_SE12, 0}, - {PTB3 , ADC0_SE13, 0}, - {PTB6 , ADC1_SE12, 0}, - {PTB7 , ADC1_SE13, 0}, - {PTB10, ADC1_SE14, 0}, - {PTB11, ADC1_SE15, 0}, - {PTC0 , ADC0_SE14, 0}, - {PTC1 , ADC0_SE15, 0}, - {PTC2, ADC0_SE4b, 0}, - {PTC8, ADC1_SE4b, 0}, - {PTC9, ADC1_SE5b, 0}, - {PTC10, ADC1_SE6b, 0}, - {PTC11, ADC1_SE7b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {PTE0, ADC1_SE4a, 0}, - {PTE1, ADC1_SE5a, 0}, - {PTE2, ADC1_SE6a, 0}, - {PTE3, ADC1_SE7a, 0}, - //{PTE24, ADC0_SE17, 0}, //I2C pull up - //{PTE25, ADC0_SE18, 0}, //I2C pull up - {NC , NC , 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {DAC0_OUT, DAC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTE25, I2C_0, 5}, - {PTB1 , I2C_0, 2}, - {PTB3 , I2C_0, 2}, - {PTC11, I2C_1, 2}, - {PTA13, I2C_2, 5}, - {PTD3 , I2C_0, 7}, - {PTE0 , I2C_1, 6}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTE24, I2C_0, 5}, - {PTB0 , I2C_0, 2}, - {PTB2 , I2C_0, 2}, - {PTC10, I2C_1, 2}, - {PTA12, I2C_2, 5}, - {PTA14, I2C_2, 5}, - {PTD2 , I2C_0, 7}, - {PTE1 , I2C_1, 6}, - {NC , NC , 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTB17, UART_0, 3}, - {PTC17, UART_3, 3}, - {PTD7 , UART_0, 3}, - {PTD3 , UART_2, 3}, - {PTC4 , UART_1, 3}, - {PTC15, UART_4, 3}, - {PTB11, UART_3, 3}, - {PTA14, UART_0, 3}, - {PTE24, UART_4, 3}, - {PTE4 , UART_3, 3}, - {PTE0, UART_1, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTB16, UART_0, 3}, - {PTE1 , UART_1, 3}, - {PTE5 , UART_3, 3}, - {PTE25, UART_4, 3}, - {PTA15, UART_0, 3}, - {PTC16, UART_3, 3}, - {PTB10, UART_3, 3}, - {PTC3 , UART_1, 3}, - {PTC14, UART_4, 3}, - {PTD2 , UART_2, 3}, - {PTD6 , UART_0, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTD1 , SPI_0, 2}, - {PTE2 , SPI_1, 2}, - {PTA15, SPI_0, 2}, - {PTB11, SPI_1, 2}, - {PTB21, SPI_2, 2}, - {PTC5 , SPI_0, 2}, - {PTD5 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTD2 , SPI_0, 2}, - {PTE1 , SPI_1, 2}, - {PTE3 , SPI_1, 7}, - {PTA16, SPI_0, 2}, - {PTB16, SPI_1, 2}, - {PTB22, SPI_2, 2}, - {PTC6 , SPI_0, 2}, - {PTD6 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTD3 , SPI_0, 2}, - {PTE1 , SPI_1, 7}, - {PTE3 , SPI_1, 2}, - {PTA17, SPI_0, 2}, - {PTB17, SPI_1, 2}, - {PTB23, SPI_2, 2}, - {PTC7 , SPI_0, 2}, - {PTD7 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTD0 , SPI_0, 2}, - {PTE4 , SPI_1, 2}, - {PTA14, SPI_0, 2}, - {PTB10, SPI_1, 2}, - {PTB20, SPI_2, 2}, - {PTC4 , SPI_0, 2}, - {PTD4 , SPI_1, 7}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PTA0 , PWM_6 , 3}, - {PTA1 , PWM_7 , 3}, - {PTA2 , PWM_8 , 3}, - {PTA3 , PWM_1 , 3}, - {PTA4 , PWM_2 , 3}, - {PTA5 , PWM_3 , 3}, - {PTA6 , PWM_4 , 3}, - {PTA7 , PWM_5 , 3}, - {PTA8 , PWM_9 , 3}, - {PTA9 , PWM_10, 3}, - {PTA10, PWM_17, 3}, - {PTA11, PWM_18, 3}, - {PTA12, PWM_9 , 3}, - {PTA13, PWM_10, 3}, - - {PTB0 , PWM_9 , 3}, - {PTB1 , PWM_10, 3}, - {PTB18, PWM_17, 3}, - {PTB19, PWM_18, 3}, - - {PTC1 , PWM_1 , 4}, - {PTC2 , PWM_2 , 4}, - {PTC3 , PWM_3 , 4}, - {PTC4 , PWM_4 , 4}, - {PTC5 , PWM_3 , 7}, - {PTC8 , PWM_29, 3}, - {PTC9 , PWM_30, 3}, - {PTC10, PWM_31, 3}, - {PTC11, PWM_32, 3}, - - {PTD0 , PWM_25, 4}, - {PTD1 , PWM_26, 4}, - {PTD2 , PWM_27, 4}, - {PTD3 , PWM_28, 4}, - {PTD4 , PWM_5 , 4}, - {PTD5 , PWM_6 , 4}, - {PTD6 , PWM_7 , 4}, - {PTD4 , PWM_5 , 4}, - {PTD7 , PWM_8 , 4}, - - {PTE5 , PWM_25, 6}, - {PTE6 , PWM_26, 6}, - - {NC , NC , 0} -}; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h deleted file mode 100644 index 92b0f35217f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h +++ /dev/null @@ -1,258 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define GPIO_PORT_SHIFT 12 - -typedef enum { - PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), - PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), - PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), - PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), - PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), - PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), - PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), - PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), - PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), - PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), - PTA10 = (0 << GPIO_PORT_SHIFT | 10), - PTA11 = (0 << GPIO_PORT_SHIFT | 11), - PTA12 = (0 << GPIO_PORT_SHIFT | 12), - PTA13 = (0 << GPIO_PORT_SHIFT | 13), - PTA14 = (0 << GPIO_PORT_SHIFT | 14), - PTA15 = (0 << GPIO_PORT_SHIFT | 15), - PTA16 = (0 << GPIO_PORT_SHIFT | 16), - PTA17 = (0 << GPIO_PORT_SHIFT | 17), - PTA18 = (0 << GPIO_PORT_SHIFT | 18), - PTA19 = (0 << GPIO_PORT_SHIFT | 19), - PTA20 = (0 << GPIO_PORT_SHIFT | 20), - PTA21 = (0 << GPIO_PORT_SHIFT | 21), - PTA22 = (0 << GPIO_PORT_SHIFT | 22), - PTA23 = (0 << GPIO_PORT_SHIFT | 23), - PTA24 = (0 << GPIO_PORT_SHIFT | 24), - PTA25 = (0 << GPIO_PORT_SHIFT | 25), - PTA26 = (0 << GPIO_PORT_SHIFT | 26), - PTA27 = (0 << GPIO_PORT_SHIFT | 27), - PTA28 = (0 << GPIO_PORT_SHIFT | 28), - PTA29 = (0 << GPIO_PORT_SHIFT | 29), - PTA30 = (0 << GPIO_PORT_SHIFT | 30), - PTA31 = (0 << GPIO_PORT_SHIFT | 31), - PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), - PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), - PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), - PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), - PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), - PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), - PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), - PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), - PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), - PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), - PTB10 = (1 << GPIO_PORT_SHIFT | 10), - PTB11 = (1 << GPIO_PORT_SHIFT | 11), - PTB12 = (1 << GPIO_PORT_SHIFT | 12), - PTB13 = (1 << GPIO_PORT_SHIFT | 13), - PTB14 = (1 << GPIO_PORT_SHIFT | 14), - PTB15 = (1 << GPIO_PORT_SHIFT | 15), - PTB16 = (1 << GPIO_PORT_SHIFT | 16), - PTB17 = (1 << GPIO_PORT_SHIFT | 17), - PTB18 = (1 << GPIO_PORT_SHIFT | 18), - PTB19 = (1 << GPIO_PORT_SHIFT | 19), - PTB20 = (1 << GPIO_PORT_SHIFT | 20), - PTB21 = (1 << GPIO_PORT_SHIFT | 21), - PTB22 = (1 << GPIO_PORT_SHIFT | 22), - PTB23 = (1 << GPIO_PORT_SHIFT | 23), - PTB24 = (1 << GPIO_PORT_SHIFT | 24), - PTB25 = (1 << GPIO_PORT_SHIFT | 25), - PTB26 = (1 << GPIO_PORT_SHIFT | 26), - PTB27 = (1 << GPIO_PORT_SHIFT | 27), - PTB28 = (1 << GPIO_PORT_SHIFT | 28), - PTB29 = (1 << GPIO_PORT_SHIFT | 29), - PTB30 = (1 << GPIO_PORT_SHIFT | 30), - PTB31 = (1 << GPIO_PORT_SHIFT | 31), - PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), - PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), - PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), - PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), - PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), - PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), - PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), - PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), - PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), - PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), - PTC10 = (2 << GPIO_PORT_SHIFT | 10), - PTC11 = (2 << GPIO_PORT_SHIFT | 11), - PTC12 = (2 << GPIO_PORT_SHIFT | 12), - PTC13 = (2 << GPIO_PORT_SHIFT | 13), - PTC14 = (2 << GPIO_PORT_SHIFT | 14), - PTC15 = (2 << GPIO_PORT_SHIFT | 15), - PTC16 = (2 << GPIO_PORT_SHIFT | 16), - PTC17 = (2 << GPIO_PORT_SHIFT | 17), - PTC18 = (2 << GPIO_PORT_SHIFT | 18), - PTC19 = (2 << GPIO_PORT_SHIFT | 19), - PTC20 = (2 << GPIO_PORT_SHIFT | 20), - PTC21 = (2 << GPIO_PORT_SHIFT | 21), - PTC22 = (2 << GPIO_PORT_SHIFT | 22), - PTC23 = (2 << GPIO_PORT_SHIFT | 23), - PTC24 = (2 << GPIO_PORT_SHIFT | 24), - PTC25 = (2 << GPIO_PORT_SHIFT | 25), - PTC26 = (2 << GPIO_PORT_SHIFT | 26), - PTC27 = (2 << GPIO_PORT_SHIFT | 27), - PTC28 = (2 << GPIO_PORT_SHIFT | 28), - PTC29 = (2 << GPIO_PORT_SHIFT | 29), - PTC30 = (2 << GPIO_PORT_SHIFT | 30), - PTC31 = (2 << GPIO_PORT_SHIFT | 31), - PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), - PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), - PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), - PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), - PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), - PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), - PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), - PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), - PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), - PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), - PTD10 = (3 << GPIO_PORT_SHIFT | 10), - PTD11 = (3 << GPIO_PORT_SHIFT | 11), - PTD12 = (3 << GPIO_PORT_SHIFT | 12), - PTD13 = (3 << GPIO_PORT_SHIFT | 13), - PTD14 = (3 << GPIO_PORT_SHIFT | 14), - PTD15 = (3 << GPIO_PORT_SHIFT | 15), - PTD16 = (3 << GPIO_PORT_SHIFT | 16), - PTD17 = (3 << GPIO_PORT_SHIFT | 17), - PTD18 = (3 << GPIO_PORT_SHIFT | 18), - PTD19 = (3 << GPIO_PORT_SHIFT | 19), - PTD20 = (3 << GPIO_PORT_SHIFT | 20), - PTD21 = (3 << GPIO_PORT_SHIFT | 21), - PTD22 = (3 << GPIO_PORT_SHIFT | 22), - PTD23 = (3 << GPIO_PORT_SHIFT | 23), - PTD24 = (3 << GPIO_PORT_SHIFT | 24), - PTD25 = (3 << GPIO_PORT_SHIFT | 25), - PTD26 = (3 << GPIO_PORT_SHIFT | 26), - PTD27 = (3 << GPIO_PORT_SHIFT | 27), - PTD28 = (3 << GPIO_PORT_SHIFT | 28), - PTD29 = (3 << GPIO_PORT_SHIFT | 29), - PTD30 = (3 << GPIO_PORT_SHIFT | 30), - PTD31 = (3 << GPIO_PORT_SHIFT | 31), - PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), - PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), - PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), - PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), - PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), - PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), - PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), - PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), - PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), - PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), - PTE10 = (4 << GPIO_PORT_SHIFT | 10), - PTE11 = (4 << GPIO_PORT_SHIFT | 11), - PTE12 = (4 << GPIO_PORT_SHIFT | 12), - PTE13 = (4 << GPIO_PORT_SHIFT | 13), - PTE14 = (4 << GPIO_PORT_SHIFT | 14), - PTE15 = (4 << GPIO_PORT_SHIFT | 15), - PTE16 = (4 << GPIO_PORT_SHIFT | 16), - PTE17 = (4 << GPIO_PORT_SHIFT | 17), - PTE18 = (4 << GPIO_PORT_SHIFT | 18), - PTE19 = (4 << GPIO_PORT_SHIFT | 19), - PTE20 = (4 << GPIO_PORT_SHIFT | 20), - PTE21 = (4 << GPIO_PORT_SHIFT | 21), - PTE22 = (4 << GPIO_PORT_SHIFT | 22), - PTE23 = (4 << GPIO_PORT_SHIFT | 23), - PTE24 = (4 << GPIO_PORT_SHIFT | 24), - PTE25 = (4 << GPIO_PORT_SHIFT | 25), - PTE26 = (4 << GPIO_PORT_SHIFT | 26), - PTE27 = (4 << GPIO_PORT_SHIFT | 27), - PTE28 = (4 << GPIO_PORT_SHIFT | 28), - PTE29 = (4 << GPIO_PORT_SHIFT | 29), - PTE30 = (4 << GPIO_PORT_SHIFT | 30), - PTE31 = (4 << GPIO_PORT_SHIFT | 31), - - LED_RED = PTB22, - LED_GREEN = PTE26, - LED_BLUE = PTB21, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_RED, - - //Push buttons - SW2 = PTC6, - SW3 = PTA4, - - // USB Pins - USBTX = PTB17, - USBRX = PTB16, - - // Arduino Headers - D0 = PTC16, - D1 = PTC17, - D2 = PTB9, - D3 = PTA1, - D4 = PTB23, - D5 = PTA2, - D6 = PTC2, - D7 = PTC3, - D8 = PTA0, - D9 = PTC4, - D10 = PTD0, - D11 = PTD2, - D12 = PTD3, - D13 = PTD1, - D14 = PTE25, - D15 = PTE24, - - I2C_SCL = D15, - I2C_SDA = D14, - - A0 = PTB2, - A1 = PTB3, - A2 = PTB10, - A3 = PTB11, - A4 = PTC11, - A5 = PTC10, - - DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.c deleted file mode 100644 index 7e2d7e7c516..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.c +++ /dev/null @@ -1,234 +0,0 @@ -/********************************************************************** - * - * Filename: crc.c - * - * Description: Slow and fast implementations of the CRC standards. - * - * Notes: The parameters for each supported CRC standard are - * defined in the header file crc.h. The implementations - * here should stand up to further additions to that list. - * - * - * Copyright (c) 2000 by Michael Barr. This software is placed into - * the public domain and may be used for any purpose. However, this - * notice must not be changed or removed and no warranty is either - * expressed or implied by its publication or distribution. - **********************************************************************/ - -#include "crc.h" - - -/* - * Derive parameters from the standard-specific parameters in crc.h. - */ -#define WIDTH (8 * sizeof(crc)) -#define TOPBIT (1 << (WIDTH - 1)) - -#if (REFLECT_DATA == TRUE) -#undef REFLECT_DATA -#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8)) -#else -#undef REFLECT_DATA -#define REFLECT_DATA(X) (X) -#endif - -#if (REFLECT_REMAINDER == TRUE) -#undef REFLECT_REMAINDER -#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH)) -#else -#undef REFLECT_REMAINDER -#define REFLECT_REMAINDER(X) (X) -#endif - - -/********************************************************************* - * - * Function: reflect() - * - * Description: Reorder the bits of a binary sequence, by reflecting - * them about the middle position. - * - * Notes: No checking is done that nBits <= 32. - * - * Returns: The reflection of the original data. - * - *********************************************************************/ -static unsigned long -reflect(unsigned long data, unsigned char nBits) -{ - unsigned long reflection = 0x00000000; - unsigned char bit; - - /* - * Reflect the data about the center bit. - */ - for (bit = 0; bit < nBits; ++bit) - { - /* - * If the LSB bit is set, set the reflection of it. - */ - if (data & 0x01) - { - reflection |= (1 << ((nBits - 1) - bit)); - } - - data = (data >> 1); - } - - return (reflection); - -} /* reflect() */ - - -/********************************************************************* - * - * Function: crcSlow() - * - * Description: Compute the CRC of a given message. - * - * Notes: - * - * Returns: The CRC of the message. - * - *********************************************************************/ -crc -crcSlow(unsigned char const message[], int nBytes) -{ - crc remainder = INITIAL_REMAINDER; - int byte; - unsigned char bit; - - - /* - * Perform modulo-2 division, a byte at a time. - */ - for (byte = 0; byte < nBytes; ++byte) - { - /* - * Bring the next byte into the remainder. - */ - remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8)); - - /* - * Perform modulo-2 division, a bit at a time. - */ - for (bit = 8; bit > 0; --bit) - { - /* - * Try to divide the current data bit. - */ - if (remainder & TOPBIT) - { - remainder = (remainder << 1) ^ POLYNOMIAL; - } - else - { - remainder = (remainder << 1); - } - } - } - - /* - * The final remainder is the CRC result. - */ - return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); - -} /* crcSlow() */ - - -crc crcTable[256]; - - -/********************************************************************* - * - * Function: crcInit() - * - * Description: Populate the partial CRC lookup table. - * - * Notes: This function must be rerun any time the CRC standard - * is changed. If desired, it can be run "offline" and - * the table results stored in an embedded system's ROM. - * - * Returns: None defined. - * - *********************************************************************/ -void -crcInit(void) -{ - crc remainder; - int dividend; - unsigned char bit; - - - /* - * Compute the remainder of each possible dividend. - */ - for (dividend = 0; dividend < 256; ++dividend) - { - /* - * Start with the dividend followed by zeros. - */ - remainder = dividend << (WIDTH - 8); - - /* - * Perform modulo-2 division, a bit at a time. - */ - for (bit = 8; bit > 0; --bit) - { - /* - * Try to divide the current data bit. - */ - if (remainder & TOPBIT) - { - remainder = (remainder << 1) ^ POLYNOMIAL; - } - else - { - remainder = (remainder << 1); - } - } - - /* - * Store the result into the table. - */ - crcTable[dividend] = remainder; - } - -} /* crcInit() */ - - -/********************************************************************* - * - * Function: crcFast() - * - * Description: Compute the CRC of a given message. - * - * Notes: crcInit() must be called first. - * - * Returns: The CRC of the message. - * - *********************************************************************/ -crc -crcFast(unsigned char const message[], int nBytes) -{ - crc remainder = INITIAL_REMAINDER; - unsigned char data; - int byte; - - - /* - * Divide the message by the polynomial, a byte at a time. - */ - for (byte = 0; byte < nBytes; ++byte) - { - data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8)); - remainder = crcTable[data] ^ (remainder << 8); - } - - /* - * The final remainder is the CRC. - */ - return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); - -} /* crcFast() */ - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.h deleted file mode 100644 index fae66ae4bcc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.h +++ /dev/null @@ -1,77 +0,0 @@ -/********************************************************************** - * - * Filename: crc.h - * - * Description: A header file describing the various CRC standards. - * - * Notes: - * - * - * Copyright (c) 2000 by Michael Barr. This software is placed into - * the public domain and may be used for any purpose. However, this - * notice must not be changed or removed and no warranty is either - * expressed or implied by its publication or distribution. - **********************************************************************/ - -#ifndef _crc_h -#define _crc_h - - -#define FALSE 0 -#define TRUE !FALSE - -/* - * Select the CRC standard from the list that follows. - */ -#define CRC16 - - -#if defined(CRC_CCITT) - -typedef unsigned short crc; - -#define CRC_NAME "CRC-CCITT" -#define POLYNOMIAL 0x1021 -#define INITIAL_REMAINDER 0xFFFF -#define FINAL_XOR_VALUE 0x0000 -#define REFLECT_DATA FALSE -#define REFLECT_REMAINDER FALSE -#define CHECK_VALUE 0x29B1 - -#elif defined(CRC16) - -typedef unsigned short crc; - -#define CRC_NAME "CRC-16" -#define POLYNOMIAL 0x8005 -#define INITIAL_REMAINDER 0x0000 -#define FINAL_XOR_VALUE 0x0000 -#define REFLECT_DATA TRUE -#define REFLECT_REMAINDER TRUE -#define CHECK_VALUE 0xBB3D - -#elif defined(CRC32) - -typedef unsigned long crc; - -#define CRC_NAME "CRC-32" -#define POLYNOMIAL 0x04C11DB7 -#define INITIAL_REMAINDER 0xFFFFFFFF -#define FINAL_XOR_VALUE 0xFFFFFFFF -#define REFLECT_DATA TRUE -#define REFLECT_REMAINDER TRUE -#define CHECK_VALUE 0xCBF43926 - -#else - -#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." - -#endif - - -void crcInit(void); -crc crcSlow(unsigned char const message[], int nBytes); -crc crcFast(unsigned char const message[], int nBytes); - - -#endif /* _crc_h */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/device.h deleted file mode 100644 index 8f3ef7e1252..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/device.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c deleted file mode 100644 index 0d7160e0100..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c +++ /dev/null @@ -1,72 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" - -#define CRC16 -#include "crc.h" - -// called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//void mbed_sdk_init() -//{ -// -//} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - gpio_t gpio; - gpio_init_in(&gpio, PTA4); -} - -// Provide ethernet devices with a semi-unique MAC address from the UUID -void mbed_mac_address(char *mac) -{ - - unsigned int UUID_LOC_BASE = 0x40048054; // First adddress of the 4-word UUID - char uuid[16]; // So we can take a local copy of the UUID - uint32_t MAC[3]; // 3 16 bits words for the MAC - - // copy the UUID to the variable MAC[] - memcpy(uuid,(const void*)UUID_LOC_BASE,sizeof(uuid)); - - // generate three CRC16's using different slices of the UUID - MAC[0] = crcSlow(uuid, 8); // most significant half-word - MAC[1] = crcSlow(uuid, 12); - MAC[2] = crcSlow(uuid, 16); // least significant half word - - // The network stack expects an array of 6 bytes - // so we copy, and shift and copy from the half-word array to the byte array - mac[0] = MAC[0] >> 8; - mac[1] = MAC[0]; - mac[2] = MAC[1] >> 8; - mac[3] = MAC[1]; - mac[4] = MAC[2] >> 8; - mac[5] = MAC[2]; - - // We want to force bits [1:0] of the most significant byte [0] - // to be "10" - // http://en.wikipedia.org/wiki/MAC_address - - mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered" - mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast - -} - - - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h deleted file mode 100644 index 077ca4a5561..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h +++ /dev/null @@ -1,133 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_0 = 0, - UART_2 = 2, - UART_3 = 3, - UART_5 = 5, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = 0, - I2C_1 = 1, -} I2CName; - - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 - PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 - PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 - PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 - PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 - PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 - PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 - PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 - PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 - PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 - PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 - PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 - PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 - // could be 4 or could be 3... not sure what register - // this is for... too much abstraction - PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 - PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 - PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 - PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 - PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 - PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 - PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 - PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 -} PWMName; - - - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 -typedef enum { - ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, - ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, - ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, - ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, - ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, - ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, - ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, - ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, - ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, - ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4, - ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5, - ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6, - ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7, - ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, - ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, - ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, - ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, - ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, - ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, - ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, - ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, - ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, -} ADCName; - - - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_0 = 0, - SPI_1 = 1, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c deleted file mode 100644 index dd0721fb5fe..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c +++ /dev/null @@ -1,112 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTE25, I2C_0, 5}, - {PTB1 , I2C_0, 2}, - {PTB3 , I2C_0, 2}, - {PTC11, I2C_1, 2}, - {PTD3 , I2C_0, 7}, - {PTE0 , I2C_1, 6}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTE24, I2C_0, 5}, - {PTB0 , I2C_0, 2}, - {PTB2 , I2C_0, 2}, - {PTC10, I2C_1, 2}, - {PTD2 , I2C_0, 7}, - {PTE1 , I2C_1, 6}, - {NC , NC , 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTB17, UART_0, 3}, - {PTC17, UART_3, 3}, - {PTD7 , UART_0, 3}, - {PTD3 , UART_2, 3}, - {PTB11, UART_3, 3}, - {PTA14, UART_0, 3}, - {PTE4 , UART_3, 3}, - {PTE8 , UART_5, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTB16, UART_0, 3}, - {PTE5 , UART_3, 3}, - {PTA15, UART_0, 3}, - {PTC16, UART_3, 3}, - {PTB10, UART_3, 3}, - {PTD2 , UART_2, 3}, - {PTC6 , UART_0, 3}, - {PTE9 , UART_5, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTD1 , SPI_0, 2}, - {PTE2 , SPI_1, 2}, - {PTA15, SPI_0, 2}, - {PTB11, SPI_1, 2}, - {PTC5 , SPI_0, 2}, - {PTD5 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTD2 , SPI_0, 2}, - {PTE1 , SPI_1, 2}, - {PTE3 , SPI_1, 7}, - {PTA16, SPI_0, 2}, - {PTB16, SPI_1, 2}, - {PTC6 , SPI_0, 2}, - {PTD6 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTD3 , SPI_0, 2}, - {PTE1 , SPI_1, 7}, - {PTE3 , SPI_1, 2}, - {PTA17, SPI_0, 2}, - {PTB17, SPI_1, 2}, - {PTC7 , SPI_0, 2}, - {PTD7 , SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTD0 , SPI_0, 2}, - {PTE4 , SPI_1, 2}, - {PTA14, SPI_0, 2}, - {PTB10, SPI_1, 2}, - {PTC4 , SPI_0, 2}, - {PTD4 , SPI_1, 7}, - {NC , NC , 0} -}; - diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PinNames.h deleted file mode 100644 index 1e3fc8dcd15..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PinNames.h +++ /dev/null @@ -1,268 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define GPIO_PORT_SHIFT 12 - -typedef enum { - PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), - PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), - PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), - PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), - PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), - PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), - PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), - PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), - PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), - PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), - PTA10 = (0 << GPIO_PORT_SHIFT | 10), - PTA11 = (0 << GPIO_PORT_SHIFT | 11), - PTA12 = (0 << GPIO_PORT_SHIFT | 12), - PTA13 = (0 << GPIO_PORT_SHIFT | 13), - PTA14 = (0 << GPIO_PORT_SHIFT | 14), - PTA15 = (0 << GPIO_PORT_SHIFT | 15), - PTA16 = (0 << GPIO_PORT_SHIFT | 16), - PTA17 = (0 << GPIO_PORT_SHIFT | 17), - PTA18 = (0 << GPIO_PORT_SHIFT | 18), - PTA19 = (0 << GPIO_PORT_SHIFT | 19), - PTA20 = (0 << GPIO_PORT_SHIFT | 20), - PTA21 = (0 << GPIO_PORT_SHIFT | 21), - PTA22 = (0 << GPIO_PORT_SHIFT | 22), - PTA23 = (0 << GPIO_PORT_SHIFT | 23), - PTA24 = (0 << GPIO_PORT_SHIFT | 24), - PTA25 = (0 << GPIO_PORT_SHIFT | 25), - PTA26 = (0 << GPIO_PORT_SHIFT | 26), - PTA27 = (0 << GPIO_PORT_SHIFT | 27), - PTA28 = (0 << GPIO_PORT_SHIFT | 28), - PTA29 = (0 << GPIO_PORT_SHIFT | 29), - PTA30 = (0 << GPIO_PORT_SHIFT | 30), - PTA31 = (0 << GPIO_PORT_SHIFT | 31), - PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), - PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), - PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), - PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), - PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), - PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), - PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), - PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), - PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), - PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), - PTB10 = (1 << GPIO_PORT_SHIFT | 10), - PTB11 = (1 << GPIO_PORT_SHIFT | 11), - PTB12 = (1 << GPIO_PORT_SHIFT | 12), - PTB13 = (1 << GPIO_PORT_SHIFT | 13), - PTB14 = (1 << GPIO_PORT_SHIFT | 14), - PTB15 = (1 << GPIO_PORT_SHIFT | 15), - PTB16 = (1 << GPIO_PORT_SHIFT | 16), - PTB17 = (1 << GPIO_PORT_SHIFT | 17), - PTB18 = (1 << GPIO_PORT_SHIFT | 18), - PTB19 = (1 << GPIO_PORT_SHIFT | 19), - PTB20 = (1 << GPIO_PORT_SHIFT | 20), - PTB21 = (1 << GPIO_PORT_SHIFT | 21), - PTB22 = (1 << GPIO_PORT_SHIFT | 22), - PTB23 = (1 << GPIO_PORT_SHIFT | 23), - PTB24 = (1 << GPIO_PORT_SHIFT | 24), - PTB25 = (1 << GPIO_PORT_SHIFT | 25), - PTB26 = (1 << GPIO_PORT_SHIFT | 26), - PTB27 = (1 << GPIO_PORT_SHIFT | 27), - PTB28 = (1 << GPIO_PORT_SHIFT | 28), - PTB29 = (1 << GPIO_PORT_SHIFT | 29), - PTB30 = (1 << GPIO_PORT_SHIFT | 30), - PTB31 = (1 << GPIO_PORT_SHIFT | 31), - PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), - PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), - PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), - PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), - PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), - PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), - PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), - PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), - PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), - PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), - PTC10 = (2 << GPIO_PORT_SHIFT | 10), - PTC11 = (2 << GPIO_PORT_SHIFT | 11), - PTC12 = (2 << GPIO_PORT_SHIFT | 12), - PTC13 = (2 << GPIO_PORT_SHIFT | 13), - PTC14 = (2 << GPIO_PORT_SHIFT | 14), - PTC15 = (2 << GPIO_PORT_SHIFT | 15), - PTC16 = (2 << GPIO_PORT_SHIFT | 16), - PTC17 = (2 << GPIO_PORT_SHIFT | 17), - PTC18 = (2 << GPIO_PORT_SHIFT | 18), - PTC19 = (2 << GPIO_PORT_SHIFT | 19), - PTC20 = (2 << GPIO_PORT_SHIFT | 20), - PTC21 = (2 << GPIO_PORT_SHIFT | 21), - PTC22 = (2 << GPIO_PORT_SHIFT | 22), - PTC23 = (2 << GPIO_PORT_SHIFT | 23), - PTC24 = (2 << GPIO_PORT_SHIFT | 24), - PTC25 = (2 << GPIO_PORT_SHIFT | 25), - PTC26 = (2 << GPIO_PORT_SHIFT | 26), - PTC27 = (2 << GPIO_PORT_SHIFT | 27), - PTC28 = (2 << GPIO_PORT_SHIFT | 28), - PTC29 = (2 << GPIO_PORT_SHIFT | 29), - PTC30 = (2 << GPIO_PORT_SHIFT | 30), - PTC31 = (2 << GPIO_PORT_SHIFT | 31), - PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), - PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), - PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), - PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), - PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), - PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), - PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), - PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), - PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), - PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), - PTD10 = (3 << GPIO_PORT_SHIFT | 10), - PTD11 = (3 << GPIO_PORT_SHIFT | 11), - PTD12 = (3 << GPIO_PORT_SHIFT | 12), - PTD13 = (3 << GPIO_PORT_SHIFT | 13), - PTD14 = (3 << GPIO_PORT_SHIFT | 14), - PTD15 = (3 << GPIO_PORT_SHIFT | 15), - PTD16 = (3 << GPIO_PORT_SHIFT | 16), - PTD17 = (3 << GPIO_PORT_SHIFT | 17), - PTD18 = (3 << GPIO_PORT_SHIFT | 18), - PTD19 = (3 << GPIO_PORT_SHIFT | 19), - PTD20 = (3 << GPIO_PORT_SHIFT | 20), - PTD21 = (3 << GPIO_PORT_SHIFT | 21), - PTD22 = (3 << GPIO_PORT_SHIFT | 22), - PTD23 = (3 << GPIO_PORT_SHIFT | 23), - PTD24 = (3 << GPIO_PORT_SHIFT | 24), - PTD25 = (3 << GPIO_PORT_SHIFT | 25), - PTD26 = (3 << GPIO_PORT_SHIFT | 26), - PTD27 = (3 << GPIO_PORT_SHIFT | 27), - PTD28 = (3 << GPIO_PORT_SHIFT | 28), - PTD29 = (3 << GPIO_PORT_SHIFT | 29), - PTD30 = (3 << GPIO_PORT_SHIFT | 30), - PTD31 = (3 << GPIO_PORT_SHIFT | 31), - PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), - PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), - PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), - PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), - PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), - PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), - PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), - PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), - PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), - PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), - PTE10 = (4 << GPIO_PORT_SHIFT | 10), - PTE11 = (4 << GPIO_PORT_SHIFT | 11), - PTE12 = (4 << GPIO_PORT_SHIFT | 12), - PTE13 = (4 << GPIO_PORT_SHIFT | 13), - PTE14 = (4 << GPIO_PORT_SHIFT | 14), - PTE15 = (4 << GPIO_PORT_SHIFT | 15), - PTE16 = (4 << GPIO_PORT_SHIFT | 16), - PTE17 = (4 << GPIO_PORT_SHIFT | 17), - PTE18 = (4 << GPIO_PORT_SHIFT | 18), - PTE19 = (4 << GPIO_PORT_SHIFT | 19), - PTE20 = (4 << GPIO_PORT_SHIFT | 20), - PTE21 = (4 << GPIO_PORT_SHIFT | 21), - PTE22 = (4 << GPIO_PORT_SHIFT | 22), - PTE23 = (4 << GPIO_PORT_SHIFT | 23), - PTE24 = (4 << GPIO_PORT_SHIFT | 24), - PTE25 = (4 << GPIO_PORT_SHIFT | 25), - PTE26 = (4 << GPIO_PORT_SHIFT | 26), - PTE27 = (4 << GPIO_PORT_SHIFT | 27), - PTE28 = (4 << GPIO_PORT_SHIFT | 28), - PTE29 = (4 << GPIO_PORT_SHIFT | 29), - PTE30 = (4 << GPIO_PORT_SHIFT | 30), - PTE31 = (4 << GPIO_PORT_SHIFT | 31), - - // led color naming - LED_GREEN = PTC0, - - // mbed original LED naming - LED1 = PTD15, - LED2 = PTD14, - LED3 = PTD13, - LED4 = PTD11, - LED5 = PTD12, - STATUS = LED_GREEN, - - // USB Pins - USBTX = PTB17, - USBRX = PTB16, - - // SPI Pins - SPI0_SOUT = PTC6, - SPI0_SIN = PTC7, - SPI0_SCK = PTC5, - - SPI1_SOUT = PTE3, - SPI1_SIN = PTE1, - SPI1_SCK = PTE2, - - // SPI Chip Select Pins - SPI0_NCS0 = PTC4, - SPI0_NCS1 = PTC3, - SPI0_NCS2 = PTC2, - SPI0_NCS3 = PTC1, - - SPI1_NCS0 = PTE4, - SPI1_NCS1 = PTE0, - SPI1_NCS2 = PTE5, - SPI1_NCS3 = PTE6, - - // GPIO's - AP1_GPIO1 = PTB7, - AP1_GPIO2 = PTB6, - AP1_GPIO3 = PTB5, - AP1_GPIO4 = PTB4, - - AP2_GPIO1 = PTA27, - AP2_GPIO2 = PTA26, - AP2_GPIO3 = PTA25, - AP2_GPIO4 = PTA24, - - // Cellular Radio Serial Pins - RADIO_SERIAL_TX = PTE8, - RADIO_SERIAL_RX = PTE9, - RADIO_SERIAL_RTS = PTE11, - RADIO_SERIAL_CTS = PTE10, - RADIO_SERIAL_DTR = PTE26, - RADIO_SERIAL_DSR = PTE25, - RADIO_SERIAL_RI = PTE24, - RADIO_SERIAL_CD = PTE12, - - DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/device.h deleted file mode 100644 index 109924b210c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/device.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 0 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 0 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 0 - -#include "objects.h" - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c deleted file mode 100644 index a4b6b177e6f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" - -// called before main - implement here if board needs it ortherwise, let -// the application override this if necessary -//void mbed_sdk_init() -//{ -// -//} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h deleted file mode 100644 index 6f928970b08..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h +++ /dev/null @@ -1,529 +0,0 @@ -/* -** ################################################################### -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Register bit field access macros. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - - -#ifndef _FSL_BITACCESS_H -#define _FSL_BITACCESS_H 1 - -#include -#include - -/** - * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/** - * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/** - * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/* - * Macros for single instance registers - */ - -#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) -#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) -#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) - -#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) -#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) -#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) - -#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym - -#define BF_RD(reg, field) HW_##reg.B.field -#define BF_WR(reg, field, v) BW_##reg##_##field(v) - -#define BF_CS1(reg, f1, v1) \ - (HW_##reg##_CLR(BM_##reg##_##f1), \ - HW_##reg##_SET(BF_##reg##_##f1(v1))) - -#define BF_CS2(reg, f1, v1, f2, v2) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2))) - -#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3))) - -#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4))) - -#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5))) - -#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6))) - -#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7))) - -#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8))) - -/* - * Macros for multiple instance registers - */ - -#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) -#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) -#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) - -#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) -#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) -#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) - -#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym - -#define BF_RDn(reg, n, field) HW_##reg(n).B.field -#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) - -#define BF_CS1n(reg, n, f1, v1) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) - -#define BF_CS2n(reg, n, f1, v1, f2, v2) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2)))) - -#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3)))) - -#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4)))) - -#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5)))) - -#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6)))) - -#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7)))) - -#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8)))) - -/* - * Macros for single instance MULTI-BLOCK registers - */ - -#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) -#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) -#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) - -#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) -#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) -#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) - -#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym - -#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field -#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) - -#define BFn_CS1(reg, blk, f1, v1) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) - -#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2))) - -#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3))) - -#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4))) - -#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5))) - -#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6))) - -#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7))) - -#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8))) - -/* - * Macros for MULTI-BLOCK multiple instance registers - */ - -#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) -#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) -#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) - -#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) -#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) -#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) - -#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym - -#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field -#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) - -#define BFn_CS1n(reg, blk, n, f1, v1) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) - -#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2)))) - -#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3)))) - -#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4)))) - -#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5)))) - -#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6)))) - -#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7)))) - -#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8)))) - -#endif /* _FSL_BITACCESS_H */ - -/******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12.h deleted file mode 100644 index 28a78cedcde..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12.h +++ /dev/null @@ -1,14420 +0,0 @@ -/* -** ################################################################### -** Processors: MK64FN1M0VDC12 -** MK64FN1M0VLL12 -** MK64FN1M0VLQ12 -** MK64FN1M0VMD12 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK64F12 -** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK64F12.h - * @version 2.5 - * @date 2014-02-10 - * @brief CMSIS Peripheral Access Layer for MK64F12 - * - * CMSIS Peripheral Access Layer for MK64F12 - */ - - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK64F12_H_) /* Check if memory map has not been already included */ -#define MK64F12_H_ -#define MCU_MK64F12 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0005u - -/** - * @brief Macro to calculate address of an aliased word in the peripheral - * bitband area for a peripheral register and bit (bit band region 0x40000000 to - * 0x400FFFFF). - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Address of the aliased word in the peripheral bitband area. - */ -#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 32bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 16bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 8bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ - DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ - DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ - DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ - DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ - DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ - DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ - DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ - DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ - DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ - DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ - DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ - DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ - DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ - DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ - DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ - MCM_IRQn = 17, /**< Normal Interrupt */ - FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ - Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG Interrupt */ - RNG_IRQn = 23, /**< RNG Interrupt */ - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, /**< I2C1 interrupt */ - SPI0_IRQn = 26, /**< SPI0 Interrupt */ - SPI1_IRQn = 27, /**< SPI1 Interrupt */ - I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ - UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ - UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ - UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ - UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ - UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ - UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ - UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ - UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ - UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ - ADC0_IRQn = 39, /**< ADC0 interrupt */ - CMP0_IRQn = 40, /**< CMP0 interrupt */ - CMP1_IRQn = 41, /**< CMP1 interrupt */ - FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ - CMT_IRQn = 45, /**< CMT interrupt */ - RTC_IRQn = 46, /**< RTC interrupt */ - RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ - PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 52, /**< PDB0 Interrupt */ - USB0_IRQn = 53, /**< USB0 interrupt */ - USBDCD_IRQn = 54, /**< USBDCD Interrupt */ - Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ - DAC0_IRQn = 56, /**< DAC0 interrupt */ - MCG_IRQn = 57, /**< MCG Interrupt */ - LPTimer_IRQn = 58, /**< LPTimer interrupt */ - PORTA_IRQn = 59, /**< Port A interrupt */ - PORTB_IRQn = 60, /**< Port B interrupt */ - PORTC_IRQn = 61, /**< Port C interrupt */ - PORTD_IRQn = 62, /**< Port D interrupt */ - PORTE_IRQn = 63, /**< Port E interrupt */ - SWI_IRQn = 64, /**< Software interrupt */ - SPI2_IRQn = 65, /**< SPI2 Interrupt */ - UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ - UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ - UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ - UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ - CMP2_IRQn = 70, /**< CMP2 interrupt */ - FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ - DAC1_IRQn = 72, /**< DAC1 interrupt */ - ADC1_IRQn = 73, /**< ADC1 interrupt */ - I2C2_IRQn = 74, /**< I2C2 interrupt */ - CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ - CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ - CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ - CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ - CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ - CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ - SDHC_IRQn = 81, /**< SDHC interrupt */ - ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ - ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ - ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ - ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK64F12.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) -#define AIPS_PACRA_REG(base) ((base)->PACRA) -#define AIPS_PACRB_REG(base) ((base)->PACRB) -#define AIPS_PACRC_REG(base) ((base)->PACRC) -#define AIPS_PACRD_REG(base) ((base)->PACRD) -#define AIPS_PACRE_REG(base) ((base)->PACRE) -#define AIPS_PACRF_REG(base) ((base)->PACRF) -#define AIPS_PACRG_REG(base) ((base)->PACRG) -#define AIPS_PACRH_REG(base) ((base)->PACRH) -#define AIPS_PACRI_REG(base) ((base)->PACRI) -#define AIPS_PACRJ_REG(base) ((base)->PACRJ) -#define AIPS_PACRK_REG(base) ((base)->PACRK) -#define AIPS_PACRL_REG(base) ((base)->PACRL) -#define AIPS_PACRM_REG(base) ((base)->PACRM) -#define AIPS_PACRN_REG(base) ((base)->PACRN) -#define AIPS_PACRO_REG(base) ((base)->PACRO) -#define AIPS_PACRP_REG(base) ((base)->PACRP) -#define AIPS_PACRU_REG(base) ((base)->PACRU) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- AIPS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPS_Register_Masks AIPS Register Masks - * @{ - */ - -/* MPRA Bit Fields */ -#define AIPS_MPRA_MPL5_MASK 0x100u -#define AIPS_MPRA_MPL5_SHIFT 8 -#define AIPS_MPRA_MTW5_MASK 0x200u -#define AIPS_MPRA_MTW5_SHIFT 9 -#define AIPS_MPRA_MTR5_MASK 0x400u -#define AIPS_MPRA_MTR5_SHIFT 10 -#define AIPS_MPRA_MPL4_MASK 0x1000u -#define AIPS_MPRA_MPL4_SHIFT 12 -#define AIPS_MPRA_MTW4_MASK 0x2000u -#define AIPS_MPRA_MTW4_SHIFT 13 -#define AIPS_MPRA_MTR4_MASK 0x4000u -#define AIPS_MPRA_MTR4_SHIFT 14 -#define AIPS_MPRA_MPL3_MASK 0x10000u -#define AIPS_MPRA_MPL3_SHIFT 16 -#define AIPS_MPRA_MTW3_MASK 0x20000u -#define AIPS_MPRA_MTW3_SHIFT 17 -#define AIPS_MPRA_MTR3_MASK 0x40000u -#define AIPS_MPRA_MTR3_SHIFT 18 -#define AIPS_MPRA_MPL2_MASK 0x100000u -#define AIPS_MPRA_MPL2_SHIFT 20 -#define AIPS_MPRA_MTW2_MASK 0x200000u -#define AIPS_MPRA_MTW2_SHIFT 21 -#define AIPS_MPRA_MTR2_MASK 0x400000u -#define AIPS_MPRA_MTR2_SHIFT 22 -#define AIPS_MPRA_MPL1_MASK 0x1000000u -#define AIPS_MPRA_MPL1_SHIFT 24 -#define AIPS_MPRA_MTW1_MASK 0x2000000u -#define AIPS_MPRA_MTW1_SHIFT 25 -#define AIPS_MPRA_MTR1_MASK 0x4000000u -#define AIPS_MPRA_MTR1_SHIFT 26 -#define AIPS_MPRA_MPL0_MASK 0x10000000u -#define AIPS_MPRA_MPL0_SHIFT 28 -#define AIPS_MPRA_MTW0_MASK 0x20000000u -#define AIPS_MPRA_MTW0_SHIFT 29 -#define AIPS_MPRA_MTR0_MASK 0x40000000u -#define AIPS_MPRA_MTR0_SHIFT 30 -/* PACRA Bit Fields */ -#define AIPS_PACRA_TP7_MASK 0x1u -#define AIPS_PACRA_TP7_SHIFT 0 -#define AIPS_PACRA_WP7_MASK 0x2u -#define AIPS_PACRA_WP7_SHIFT 1 -#define AIPS_PACRA_SP7_MASK 0x4u -#define AIPS_PACRA_SP7_SHIFT 2 -#define AIPS_PACRA_TP6_MASK 0x10u -#define AIPS_PACRA_TP6_SHIFT 4 -#define AIPS_PACRA_WP6_MASK 0x20u -#define AIPS_PACRA_WP6_SHIFT 5 -#define AIPS_PACRA_SP6_MASK 0x40u -#define AIPS_PACRA_SP6_SHIFT 6 -#define AIPS_PACRA_TP5_MASK 0x100u -#define AIPS_PACRA_TP5_SHIFT 8 -#define AIPS_PACRA_WP5_MASK 0x200u -#define AIPS_PACRA_WP5_SHIFT 9 -#define AIPS_PACRA_SP5_MASK 0x400u -#define AIPS_PACRA_SP5_SHIFT 10 -#define AIPS_PACRA_TP4_MASK 0x1000u -#define AIPS_PACRA_TP4_SHIFT 12 -#define AIPS_PACRA_WP4_MASK 0x2000u -#define AIPS_PACRA_WP4_SHIFT 13 -#define AIPS_PACRA_SP4_MASK 0x4000u -#define AIPS_PACRA_SP4_SHIFT 14 -#define AIPS_PACRA_TP3_MASK 0x10000u -#define AIPS_PACRA_TP3_SHIFT 16 -#define AIPS_PACRA_WP3_MASK 0x20000u -#define AIPS_PACRA_WP3_SHIFT 17 -#define AIPS_PACRA_SP3_MASK 0x40000u -#define AIPS_PACRA_SP3_SHIFT 18 -#define AIPS_PACRA_TP2_MASK 0x100000u -#define AIPS_PACRA_TP2_SHIFT 20 -#define AIPS_PACRA_WP2_MASK 0x200000u -#define AIPS_PACRA_WP2_SHIFT 21 -#define AIPS_PACRA_SP2_MASK 0x400000u -#define AIPS_PACRA_SP2_SHIFT 22 -#define AIPS_PACRA_TP1_MASK 0x1000000u -#define AIPS_PACRA_TP1_SHIFT 24 -#define AIPS_PACRA_WP1_MASK 0x2000000u -#define AIPS_PACRA_WP1_SHIFT 25 -#define AIPS_PACRA_SP1_MASK 0x4000000u -#define AIPS_PACRA_SP1_SHIFT 26 -#define AIPS_PACRA_TP0_MASK 0x10000000u -#define AIPS_PACRA_TP0_SHIFT 28 -#define AIPS_PACRA_WP0_MASK 0x20000000u -#define AIPS_PACRA_WP0_SHIFT 29 -#define AIPS_PACRA_SP0_MASK 0x40000000u -#define AIPS_PACRA_SP0_SHIFT 30 -/* PACRB Bit Fields */ -#define AIPS_PACRB_TP7_MASK 0x1u -#define AIPS_PACRB_TP7_SHIFT 0 -#define AIPS_PACRB_WP7_MASK 0x2u -#define AIPS_PACRB_WP7_SHIFT 1 -#define AIPS_PACRB_SP7_MASK 0x4u -#define AIPS_PACRB_SP7_SHIFT 2 -#define AIPS_PACRB_TP6_MASK 0x10u -#define AIPS_PACRB_TP6_SHIFT 4 -#define AIPS_PACRB_WP6_MASK 0x20u -#define AIPS_PACRB_WP6_SHIFT 5 -#define AIPS_PACRB_SP6_MASK 0x40u -#define AIPS_PACRB_SP6_SHIFT 6 -#define AIPS_PACRB_TP5_MASK 0x100u -#define AIPS_PACRB_TP5_SHIFT 8 -#define AIPS_PACRB_WP5_MASK 0x200u -#define AIPS_PACRB_WP5_SHIFT 9 -#define AIPS_PACRB_SP5_MASK 0x400u -#define AIPS_PACRB_SP5_SHIFT 10 -#define AIPS_PACRB_TP4_MASK 0x1000u -#define AIPS_PACRB_TP4_SHIFT 12 -#define AIPS_PACRB_WP4_MASK 0x2000u -#define AIPS_PACRB_WP4_SHIFT 13 -#define AIPS_PACRB_SP4_MASK 0x4000u -#define AIPS_PACRB_SP4_SHIFT 14 -#define AIPS_PACRB_TP3_MASK 0x10000u -#define AIPS_PACRB_TP3_SHIFT 16 -#define AIPS_PACRB_WP3_MASK 0x20000u -#define AIPS_PACRB_WP3_SHIFT 17 -#define AIPS_PACRB_SP3_MASK 0x40000u -#define AIPS_PACRB_SP3_SHIFT 18 -#define AIPS_PACRB_TP2_MASK 0x100000u -#define AIPS_PACRB_TP2_SHIFT 20 -#define AIPS_PACRB_WP2_MASK 0x200000u -#define AIPS_PACRB_WP2_SHIFT 21 -#define AIPS_PACRB_SP2_MASK 0x400000u -#define AIPS_PACRB_SP2_SHIFT 22 -#define AIPS_PACRB_TP1_MASK 0x1000000u -#define AIPS_PACRB_TP1_SHIFT 24 -#define AIPS_PACRB_WP1_MASK 0x2000000u -#define AIPS_PACRB_WP1_SHIFT 25 -#define AIPS_PACRB_SP1_MASK 0x4000000u -#define AIPS_PACRB_SP1_SHIFT 26 -#define AIPS_PACRB_TP0_MASK 0x10000000u -#define AIPS_PACRB_TP0_SHIFT 28 -#define AIPS_PACRB_WP0_MASK 0x20000000u -#define AIPS_PACRB_WP0_SHIFT 29 -#define AIPS_PACRB_SP0_MASK 0x40000000u -#define AIPS_PACRB_SP0_SHIFT 30 -/* PACRC Bit Fields */ -#define AIPS_PACRC_TP7_MASK 0x1u -#define AIPS_PACRC_TP7_SHIFT 0 -#define AIPS_PACRC_WP7_MASK 0x2u -#define AIPS_PACRC_WP7_SHIFT 1 -#define AIPS_PACRC_SP7_MASK 0x4u -#define AIPS_PACRC_SP7_SHIFT 2 -#define AIPS_PACRC_TP6_MASK 0x10u -#define AIPS_PACRC_TP6_SHIFT 4 -#define AIPS_PACRC_WP6_MASK 0x20u -#define AIPS_PACRC_WP6_SHIFT 5 -#define AIPS_PACRC_SP6_MASK 0x40u -#define AIPS_PACRC_SP6_SHIFT 6 -#define AIPS_PACRC_TP5_MASK 0x100u -#define AIPS_PACRC_TP5_SHIFT 8 -#define AIPS_PACRC_WP5_MASK 0x200u -#define AIPS_PACRC_WP5_SHIFT 9 -#define AIPS_PACRC_SP5_MASK 0x400u -#define AIPS_PACRC_SP5_SHIFT 10 -#define AIPS_PACRC_TP4_MASK 0x1000u -#define AIPS_PACRC_TP4_SHIFT 12 -#define AIPS_PACRC_WP4_MASK 0x2000u -#define AIPS_PACRC_WP4_SHIFT 13 -#define AIPS_PACRC_SP4_MASK 0x4000u -#define AIPS_PACRC_SP4_SHIFT 14 -#define AIPS_PACRC_TP3_MASK 0x10000u -#define AIPS_PACRC_TP3_SHIFT 16 -#define AIPS_PACRC_WP3_MASK 0x20000u -#define AIPS_PACRC_WP3_SHIFT 17 -#define AIPS_PACRC_SP3_MASK 0x40000u -#define AIPS_PACRC_SP3_SHIFT 18 -#define AIPS_PACRC_TP2_MASK 0x100000u -#define AIPS_PACRC_TP2_SHIFT 20 -#define AIPS_PACRC_WP2_MASK 0x200000u -#define AIPS_PACRC_WP2_SHIFT 21 -#define AIPS_PACRC_SP2_MASK 0x400000u -#define AIPS_PACRC_SP2_SHIFT 22 -#define AIPS_PACRC_TP1_MASK 0x1000000u -#define AIPS_PACRC_TP1_SHIFT 24 -#define AIPS_PACRC_WP1_MASK 0x2000000u -#define AIPS_PACRC_WP1_SHIFT 25 -#define AIPS_PACRC_SP1_MASK 0x4000000u -#define AIPS_PACRC_SP1_SHIFT 26 -#define AIPS_PACRC_TP0_MASK 0x10000000u -#define AIPS_PACRC_TP0_SHIFT 28 -#define AIPS_PACRC_WP0_MASK 0x20000000u -#define AIPS_PACRC_WP0_SHIFT 29 -#define AIPS_PACRC_SP0_MASK 0x40000000u -#define AIPS_PACRC_SP0_SHIFT 30 -/* PACRD Bit Fields */ -#define AIPS_PACRD_TP7_MASK 0x1u -#define AIPS_PACRD_TP7_SHIFT 0 -#define AIPS_PACRD_WP7_MASK 0x2u -#define AIPS_PACRD_WP7_SHIFT 1 -#define AIPS_PACRD_SP7_MASK 0x4u -#define AIPS_PACRD_SP7_SHIFT 2 -#define AIPS_PACRD_TP6_MASK 0x10u -#define AIPS_PACRD_TP6_SHIFT 4 -#define AIPS_PACRD_WP6_MASK 0x20u -#define AIPS_PACRD_WP6_SHIFT 5 -#define AIPS_PACRD_SP6_MASK 0x40u -#define AIPS_PACRD_SP6_SHIFT 6 -#define AIPS_PACRD_TP5_MASK 0x100u -#define AIPS_PACRD_TP5_SHIFT 8 -#define AIPS_PACRD_WP5_MASK 0x200u -#define AIPS_PACRD_WP5_SHIFT 9 -#define AIPS_PACRD_SP5_MASK 0x400u -#define AIPS_PACRD_SP5_SHIFT 10 -#define AIPS_PACRD_TP4_MASK 0x1000u -#define AIPS_PACRD_TP4_SHIFT 12 -#define AIPS_PACRD_WP4_MASK 0x2000u -#define AIPS_PACRD_WP4_SHIFT 13 -#define AIPS_PACRD_SP4_MASK 0x4000u -#define AIPS_PACRD_SP4_SHIFT 14 -#define AIPS_PACRD_TP3_MASK 0x10000u -#define AIPS_PACRD_TP3_SHIFT 16 -#define AIPS_PACRD_WP3_MASK 0x20000u -#define AIPS_PACRD_WP3_SHIFT 17 -#define AIPS_PACRD_SP3_MASK 0x40000u -#define AIPS_PACRD_SP3_SHIFT 18 -#define AIPS_PACRD_TP2_MASK 0x100000u -#define AIPS_PACRD_TP2_SHIFT 20 -#define AIPS_PACRD_WP2_MASK 0x200000u -#define AIPS_PACRD_WP2_SHIFT 21 -#define AIPS_PACRD_SP2_MASK 0x400000u -#define AIPS_PACRD_SP2_SHIFT 22 -#define AIPS_PACRD_TP1_MASK 0x1000000u -#define AIPS_PACRD_TP1_SHIFT 24 -#define AIPS_PACRD_WP1_MASK 0x2000000u -#define AIPS_PACRD_WP1_SHIFT 25 -#define AIPS_PACRD_SP1_MASK 0x4000000u -#define AIPS_PACRD_SP1_SHIFT 26 -#define AIPS_PACRD_TP0_MASK 0x10000000u -#define AIPS_PACRD_TP0_SHIFT 28 -#define AIPS_PACRD_WP0_MASK 0x20000000u -#define AIPS_PACRD_WP0_SHIFT 29 -#define AIPS_PACRD_SP0_MASK 0x40000000u -#define AIPS_PACRD_SP0_SHIFT 30 -/* PACRE Bit Fields */ -#define AIPS_PACRE_TP7_MASK 0x1u -#define AIPS_PACRE_TP7_SHIFT 0 -#define AIPS_PACRE_WP7_MASK 0x2u -#define AIPS_PACRE_WP7_SHIFT 1 -#define AIPS_PACRE_SP7_MASK 0x4u -#define AIPS_PACRE_SP7_SHIFT 2 -#define AIPS_PACRE_TP6_MASK 0x10u -#define AIPS_PACRE_TP6_SHIFT 4 -#define AIPS_PACRE_WP6_MASK 0x20u -#define AIPS_PACRE_WP6_SHIFT 5 -#define AIPS_PACRE_SP6_MASK 0x40u -#define AIPS_PACRE_SP6_SHIFT 6 -#define AIPS_PACRE_TP5_MASK 0x100u -#define AIPS_PACRE_TP5_SHIFT 8 -#define AIPS_PACRE_WP5_MASK 0x200u -#define AIPS_PACRE_WP5_SHIFT 9 -#define AIPS_PACRE_SP5_MASK 0x400u -#define AIPS_PACRE_SP5_SHIFT 10 -#define AIPS_PACRE_TP4_MASK 0x1000u -#define AIPS_PACRE_TP4_SHIFT 12 -#define AIPS_PACRE_WP4_MASK 0x2000u -#define AIPS_PACRE_WP4_SHIFT 13 -#define AIPS_PACRE_SP4_MASK 0x4000u -#define AIPS_PACRE_SP4_SHIFT 14 -#define AIPS_PACRE_TP3_MASK 0x10000u -#define AIPS_PACRE_TP3_SHIFT 16 -#define AIPS_PACRE_WP3_MASK 0x20000u -#define AIPS_PACRE_WP3_SHIFT 17 -#define AIPS_PACRE_SP3_MASK 0x40000u -#define AIPS_PACRE_SP3_SHIFT 18 -#define AIPS_PACRE_TP2_MASK 0x100000u -#define AIPS_PACRE_TP2_SHIFT 20 -#define AIPS_PACRE_WP2_MASK 0x200000u -#define AIPS_PACRE_WP2_SHIFT 21 -#define AIPS_PACRE_SP2_MASK 0x400000u -#define AIPS_PACRE_SP2_SHIFT 22 -#define AIPS_PACRE_TP1_MASK 0x1000000u -#define AIPS_PACRE_TP1_SHIFT 24 -#define AIPS_PACRE_WP1_MASK 0x2000000u -#define AIPS_PACRE_WP1_SHIFT 25 -#define AIPS_PACRE_SP1_MASK 0x4000000u -#define AIPS_PACRE_SP1_SHIFT 26 -#define AIPS_PACRE_TP0_MASK 0x10000000u -#define AIPS_PACRE_TP0_SHIFT 28 -#define AIPS_PACRE_WP0_MASK 0x20000000u -#define AIPS_PACRE_WP0_SHIFT 29 -#define AIPS_PACRE_SP0_MASK 0x40000000u -#define AIPS_PACRE_SP0_SHIFT 30 -/* PACRF Bit Fields */ -#define AIPS_PACRF_TP7_MASK 0x1u -#define AIPS_PACRF_TP7_SHIFT 0 -#define AIPS_PACRF_WP7_MASK 0x2u -#define AIPS_PACRF_WP7_SHIFT 1 -#define AIPS_PACRF_SP7_MASK 0x4u -#define AIPS_PACRF_SP7_SHIFT 2 -#define AIPS_PACRF_TP6_MASK 0x10u -#define AIPS_PACRF_TP6_SHIFT 4 -#define AIPS_PACRF_WP6_MASK 0x20u -#define AIPS_PACRF_WP6_SHIFT 5 -#define AIPS_PACRF_SP6_MASK 0x40u -#define AIPS_PACRF_SP6_SHIFT 6 -#define AIPS_PACRF_TP5_MASK 0x100u -#define AIPS_PACRF_TP5_SHIFT 8 -#define AIPS_PACRF_WP5_MASK 0x200u -#define AIPS_PACRF_WP5_SHIFT 9 -#define AIPS_PACRF_SP5_MASK 0x400u -#define AIPS_PACRF_SP5_SHIFT 10 -#define AIPS_PACRF_TP4_MASK 0x1000u -#define AIPS_PACRF_TP4_SHIFT 12 -#define AIPS_PACRF_WP4_MASK 0x2000u -#define AIPS_PACRF_WP4_SHIFT 13 -#define AIPS_PACRF_SP4_MASK 0x4000u -#define AIPS_PACRF_SP4_SHIFT 14 -#define AIPS_PACRF_TP3_MASK 0x10000u -#define AIPS_PACRF_TP3_SHIFT 16 -#define AIPS_PACRF_WP3_MASK 0x20000u -#define AIPS_PACRF_WP3_SHIFT 17 -#define AIPS_PACRF_SP3_MASK 0x40000u -#define AIPS_PACRF_SP3_SHIFT 18 -#define AIPS_PACRF_TP2_MASK 0x100000u -#define AIPS_PACRF_TP2_SHIFT 20 -#define AIPS_PACRF_WP2_MASK 0x200000u -#define AIPS_PACRF_WP2_SHIFT 21 -#define AIPS_PACRF_SP2_MASK 0x400000u -#define AIPS_PACRF_SP2_SHIFT 22 -#define AIPS_PACRF_TP1_MASK 0x1000000u -#define AIPS_PACRF_TP1_SHIFT 24 -#define AIPS_PACRF_WP1_MASK 0x2000000u -#define AIPS_PACRF_WP1_SHIFT 25 -#define AIPS_PACRF_SP1_MASK 0x4000000u -#define AIPS_PACRF_SP1_SHIFT 26 -#define AIPS_PACRF_TP0_MASK 0x10000000u -#define AIPS_PACRF_TP0_SHIFT 28 -#define AIPS_PACRF_WP0_MASK 0x20000000u -#define AIPS_PACRF_WP0_SHIFT 29 -#define AIPS_PACRF_SP0_MASK 0x40000000u -#define AIPS_PACRF_SP0_SHIFT 30 -/* PACRG Bit Fields */ -#define AIPS_PACRG_TP7_MASK 0x1u -#define AIPS_PACRG_TP7_SHIFT 0 -#define AIPS_PACRG_WP7_MASK 0x2u -#define AIPS_PACRG_WP7_SHIFT 1 -#define AIPS_PACRG_SP7_MASK 0x4u -#define AIPS_PACRG_SP7_SHIFT 2 -#define AIPS_PACRG_TP6_MASK 0x10u -#define AIPS_PACRG_TP6_SHIFT 4 -#define AIPS_PACRG_WP6_MASK 0x20u -#define AIPS_PACRG_WP6_SHIFT 5 -#define AIPS_PACRG_SP6_MASK 0x40u -#define AIPS_PACRG_SP6_SHIFT 6 -#define AIPS_PACRG_TP5_MASK 0x100u -#define AIPS_PACRG_TP5_SHIFT 8 -#define AIPS_PACRG_WP5_MASK 0x200u -#define AIPS_PACRG_WP5_SHIFT 9 -#define AIPS_PACRG_SP5_MASK 0x400u -#define AIPS_PACRG_SP5_SHIFT 10 -#define AIPS_PACRG_TP4_MASK 0x1000u -#define AIPS_PACRG_TP4_SHIFT 12 -#define AIPS_PACRG_WP4_MASK 0x2000u -#define AIPS_PACRG_WP4_SHIFT 13 -#define AIPS_PACRG_SP4_MASK 0x4000u -#define AIPS_PACRG_SP4_SHIFT 14 -#define AIPS_PACRG_TP3_MASK 0x10000u -#define AIPS_PACRG_TP3_SHIFT 16 -#define AIPS_PACRG_WP3_MASK 0x20000u -#define AIPS_PACRG_WP3_SHIFT 17 -#define AIPS_PACRG_SP3_MASK 0x40000u -#define AIPS_PACRG_SP3_SHIFT 18 -#define AIPS_PACRG_TP2_MASK 0x100000u -#define AIPS_PACRG_TP2_SHIFT 20 -#define AIPS_PACRG_WP2_MASK 0x200000u -#define AIPS_PACRG_WP2_SHIFT 21 -#define AIPS_PACRG_SP2_MASK 0x400000u -#define AIPS_PACRG_SP2_SHIFT 22 -#define AIPS_PACRG_TP1_MASK 0x1000000u -#define AIPS_PACRG_TP1_SHIFT 24 -#define AIPS_PACRG_WP1_MASK 0x2000000u -#define AIPS_PACRG_WP1_SHIFT 25 -#define AIPS_PACRG_SP1_MASK 0x4000000u -#define AIPS_PACRG_SP1_SHIFT 26 -#define AIPS_PACRG_TP0_MASK 0x10000000u -#define AIPS_PACRG_TP0_SHIFT 28 -#define AIPS_PACRG_WP0_MASK 0x20000000u -#define AIPS_PACRG_WP0_SHIFT 29 -#define AIPS_PACRG_SP0_MASK 0x40000000u -#define AIPS_PACRG_SP0_SHIFT 30 -/* PACRH Bit Fields */ -#define AIPS_PACRH_TP7_MASK 0x1u -#define AIPS_PACRH_TP7_SHIFT 0 -#define AIPS_PACRH_WP7_MASK 0x2u -#define AIPS_PACRH_WP7_SHIFT 1 -#define AIPS_PACRH_SP7_MASK 0x4u -#define AIPS_PACRH_SP7_SHIFT 2 -#define AIPS_PACRH_TP6_MASK 0x10u -#define AIPS_PACRH_TP6_SHIFT 4 -#define AIPS_PACRH_WP6_MASK 0x20u -#define AIPS_PACRH_WP6_SHIFT 5 -#define AIPS_PACRH_SP6_MASK 0x40u -#define AIPS_PACRH_SP6_SHIFT 6 -#define AIPS_PACRH_TP5_MASK 0x100u -#define AIPS_PACRH_TP5_SHIFT 8 -#define AIPS_PACRH_WP5_MASK 0x200u -#define AIPS_PACRH_WP5_SHIFT 9 -#define AIPS_PACRH_SP5_MASK 0x400u -#define AIPS_PACRH_SP5_SHIFT 10 -#define AIPS_PACRH_TP4_MASK 0x1000u -#define AIPS_PACRH_TP4_SHIFT 12 -#define AIPS_PACRH_WP4_MASK 0x2000u -#define AIPS_PACRH_WP4_SHIFT 13 -#define AIPS_PACRH_SP4_MASK 0x4000u -#define AIPS_PACRH_SP4_SHIFT 14 -#define AIPS_PACRH_TP3_MASK 0x10000u -#define AIPS_PACRH_TP3_SHIFT 16 -#define AIPS_PACRH_WP3_MASK 0x20000u -#define AIPS_PACRH_WP3_SHIFT 17 -#define AIPS_PACRH_SP3_MASK 0x40000u -#define AIPS_PACRH_SP3_SHIFT 18 -#define AIPS_PACRH_TP2_MASK 0x100000u -#define AIPS_PACRH_TP2_SHIFT 20 -#define AIPS_PACRH_WP2_MASK 0x200000u -#define AIPS_PACRH_WP2_SHIFT 21 -#define AIPS_PACRH_SP2_MASK 0x400000u -#define AIPS_PACRH_SP2_SHIFT 22 -#define AIPS_PACRH_TP1_MASK 0x1000000u -#define AIPS_PACRH_TP1_SHIFT 24 -#define AIPS_PACRH_WP1_MASK 0x2000000u -#define AIPS_PACRH_WP1_SHIFT 25 -#define AIPS_PACRH_SP1_MASK 0x4000000u -#define AIPS_PACRH_SP1_SHIFT 26 -#define AIPS_PACRH_TP0_MASK 0x10000000u -#define AIPS_PACRH_TP0_SHIFT 28 -#define AIPS_PACRH_WP0_MASK 0x20000000u -#define AIPS_PACRH_WP0_SHIFT 29 -#define AIPS_PACRH_SP0_MASK 0x40000000u -#define AIPS_PACRH_SP0_SHIFT 30 -/* PACRI Bit Fields */ -#define AIPS_PACRI_TP7_MASK 0x1u -#define AIPS_PACRI_TP7_SHIFT 0 -#define AIPS_PACRI_WP7_MASK 0x2u -#define AIPS_PACRI_WP7_SHIFT 1 -#define AIPS_PACRI_SP7_MASK 0x4u -#define AIPS_PACRI_SP7_SHIFT 2 -#define AIPS_PACRI_TP6_MASK 0x10u -#define AIPS_PACRI_TP6_SHIFT 4 -#define AIPS_PACRI_WP6_MASK 0x20u -#define AIPS_PACRI_WP6_SHIFT 5 -#define AIPS_PACRI_SP6_MASK 0x40u -#define AIPS_PACRI_SP6_SHIFT 6 -#define AIPS_PACRI_TP5_MASK 0x100u -#define AIPS_PACRI_TP5_SHIFT 8 -#define AIPS_PACRI_WP5_MASK 0x200u -#define AIPS_PACRI_WP5_SHIFT 9 -#define AIPS_PACRI_SP5_MASK 0x400u -#define AIPS_PACRI_SP5_SHIFT 10 -#define AIPS_PACRI_TP4_MASK 0x1000u -#define AIPS_PACRI_TP4_SHIFT 12 -#define AIPS_PACRI_WP4_MASK 0x2000u -#define AIPS_PACRI_WP4_SHIFT 13 -#define AIPS_PACRI_SP4_MASK 0x4000u -#define AIPS_PACRI_SP4_SHIFT 14 -#define AIPS_PACRI_TP3_MASK 0x10000u -#define AIPS_PACRI_TP3_SHIFT 16 -#define AIPS_PACRI_WP3_MASK 0x20000u -#define AIPS_PACRI_WP3_SHIFT 17 -#define AIPS_PACRI_SP3_MASK 0x40000u -#define AIPS_PACRI_SP3_SHIFT 18 -#define AIPS_PACRI_TP2_MASK 0x100000u -#define AIPS_PACRI_TP2_SHIFT 20 -#define AIPS_PACRI_WP2_MASK 0x200000u -#define AIPS_PACRI_WP2_SHIFT 21 -#define AIPS_PACRI_SP2_MASK 0x400000u -#define AIPS_PACRI_SP2_SHIFT 22 -#define AIPS_PACRI_TP1_MASK 0x1000000u -#define AIPS_PACRI_TP1_SHIFT 24 -#define AIPS_PACRI_WP1_MASK 0x2000000u -#define AIPS_PACRI_WP1_SHIFT 25 -#define AIPS_PACRI_SP1_MASK 0x4000000u -#define AIPS_PACRI_SP1_SHIFT 26 -#define AIPS_PACRI_TP0_MASK 0x10000000u -#define AIPS_PACRI_TP0_SHIFT 28 -#define AIPS_PACRI_WP0_MASK 0x20000000u -#define AIPS_PACRI_WP0_SHIFT 29 -#define AIPS_PACRI_SP0_MASK 0x40000000u -#define AIPS_PACRI_SP0_SHIFT 30 -/* PACRJ Bit Fields */ -#define AIPS_PACRJ_TP7_MASK 0x1u -#define AIPS_PACRJ_TP7_SHIFT 0 -#define AIPS_PACRJ_WP7_MASK 0x2u -#define AIPS_PACRJ_WP7_SHIFT 1 -#define AIPS_PACRJ_SP7_MASK 0x4u -#define AIPS_PACRJ_SP7_SHIFT 2 -#define AIPS_PACRJ_TP6_MASK 0x10u -#define AIPS_PACRJ_TP6_SHIFT 4 -#define AIPS_PACRJ_WP6_MASK 0x20u -#define AIPS_PACRJ_WP6_SHIFT 5 -#define AIPS_PACRJ_SP6_MASK 0x40u -#define AIPS_PACRJ_SP6_SHIFT 6 -#define AIPS_PACRJ_TP5_MASK 0x100u -#define AIPS_PACRJ_TP5_SHIFT 8 -#define AIPS_PACRJ_WP5_MASK 0x200u -#define AIPS_PACRJ_WP5_SHIFT 9 -#define AIPS_PACRJ_SP5_MASK 0x400u -#define AIPS_PACRJ_SP5_SHIFT 10 -#define AIPS_PACRJ_TP4_MASK 0x1000u -#define AIPS_PACRJ_TP4_SHIFT 12 -#define AIPS_PACRJ_WP4_MASK 0x2000u -#define AIPS_PACRJ_WP4_SHIFT 13 -#define AIPS_PACRJ_SP4_MASK 0x4000u -#define AIPS_PACRJ_SP4_SHIFT 14 -#define AIPS_PACRJ_TP3_MASK 0x10000u -#define AIPS_PACRJ_TP3_SHIFT 16 -#define AIPS_PACRJ_WP3_MASK 0x20000u -#define AIPS_PACRJ_WP3_SHIFT 17 -#define AIPS_PACRJ_SP3_MASK 0x40000u -#define AIPS_PACRJ_SP3_SHIFT 18 -#define AIPS_PACRJ_TP2_MASK 0x100000u -#define AIPS_PACRJ_TP2_SHIFT 20 -#define AIPS_PACRJ_WP2_MASK 0x200000u -#define AIPS_PACRJ_WP2_SHIFT 21 -#define AIPS_PACRJ_SP2_MASK 0x400000u -#define AIPS_PACRJ_SP2_SHIFT 22 -#define AIPS_PACRJ_TP1_MASK 0x1000000u -#define AIPS_PACRJ_TP1_SHIFT 24 -#define AIPS_PACRJ_WP1_MASK 0x2000000u -#define AIPS_PACRJ_WP1_SHIFT 25 -#define AIPS_PACRJ_SP1_MASK 0x4000000u -#define AIPS_PACRJ_SP1_SHIFT 26 -#define AIPS_PACRJ_TP0_MASK 0x10000000u -#define AIPS_PACRJ_TP0_SHIFT 28 -#define AIPS_PACRJ_WP0_MASK 0x20000000u -#define AIPS_PACRJ_WP0_SHIFT 29 -#define AIPS_PACRJ_SP0_MASK 0x40000000u -#define AIPS_PACRJ_SP0_SHIFT 30 -/* PACRK Bit Fields */ -#define AIPS_PACRK_TP7_MASK 0x1u -#define AIPS_PACRK_TP7_SHIFT 0 -#define AIPS_PACRK_WP7_MASK 0x2u -#define AIPS_PACRK_WP7_SHIFT 1 -#define AIPS_PACRK_SP7_MASK 0x4u -#define AIPS_PACRK_SP7_SHIFT 2 -#define AIPS_PACRK_TP6_MASK 0x10u -#define AIPS_PACRK_TP6_SHIFT 4 -#define AIPS_PACRK_WP6_MASK 0x20u -#define AIPS_PACRK_WP6_SHIFT 5 -#define AIPS_PACRK_SP6_MASK 0x40u -#define AIPS_PACRK_SP6_SHIFT 6 -#define AIPS_PACRK_TP5_MASK 0x100u -#define AIPS_PACRK_TP5_SHIFT 8 -#define AIPS_PACRK_WP5_MASK 0x200u -#define AIPS_PACRK_WP5_SHIFT 9 -#define AIPS_PACRK_SP5_MASK 0x400u -#define AIPS_PACRK_SP5_SHIFT 10 -#define AIPS_PACRK_TP4_MASK 0x1000u -#define AIPS_PACRK_TP4_SHIFT 12 -#define AIPS_PACRK_WP4_MASK 0x2000u -#define AIPS_PACRK_WP4_SHIFT 13 -#define AIPS_PACRK_SP4_MASK 0x4000u -#define AIPS_PACRK_SP4_SHIFT 14 -#define AIPS_PACRK_TP3_MASK 0x10000u -#define AIPS_PACRK_TP3_SHIFT 16 -#define AIPS_PACRK_WP3_MASK 0x20000u -#define AIPS_PACRK_WP3_SHIFT 17 -#define AIPS_PACRK_SP3_MASK 0x40000u -#define AIPS_PACRK_SP3_SHIFT 18 -#define AIPS_PACRK_TP2_MASK 0x100000u -#define AIPS_PACRK_TP2_SHIFT 20 -#define AIPS_PACRK_WP2_MASK 0x200000u -#define AIPS_PACRK_WP2_SHIFT 21 -#define AIPS_PACRK_SP2_MASK 0x400000u -#define AIPS_PACRK_SP2_SHIFT 22 -#define AIPS_PACRK_TP1_MASK 0x1000000u -#define AIPS_PACRK_TP1_SHIFT 24 -#define AIPS_PACRK_WP1_MASK 0x2000000u -#define AIPS_PACRK_WP1_SHIFT 25 -#define AIPS_PACRK_SP1_MASK 0x4000000u -#define AIPS_PACRK_SP1_SHIFT 26 -#define AIPS_PACRK_TP0_MASK 0x10000000u -#define AIPS_PACRK_TP0_SHIFT 28 -#define AIPS_PACRK_WP0_MASK 0x20000000u -#define AIPS_PACRK_WP0_SHIFT 29 -#define AIPS_PACRK_SP0_MASK 0x40000000u -#define AIPS_PACRK_SP0_SHIFT 30 -/* PACRL Bit Fields */ -#define AIPS_PACRL_TP7_MASK 0x1u -#define AIPS_PACRL_TP7_SHIFT 0 -#define AIPS_PACRL_WP7_MASK 0x2u -#define AIPS_PACRL_WP7_SHIFT 1 -#define AIPS_PACRL_SP7_MASK 0x4u -#define AIPS_PACRL_SP7_SHIFT 2 -#define AIPS_PACRL_TP6_MASK 0x10u -#define AIPS_PACRL_TP6_SHIFT 4 -#define AIPS_PACRL_WP6_MASK 0x20u -#define AIPS_PACRL_WP6_SHIFT 5 -#define AIPS_PACRL_SP6_MASK 0x40u -#define AIPS_PACRL_SP6_SHIFT 6 -#define AIPS_PACRL_TP5_MASK 0x100u -#define AIPS_PACRL_TP5_SHIFT 8 -#define AIPS_PACRL_WP5_MASK 0x200u -#define AIPS_PACRL_WP5_SHIFT 9 -#define AIPS_PACRL_SP5_MASK 0x400u -#define AIPS_PACRL_SP5_SHIFT 10 -#define AIPS_PACRL_TP4_MASK 0x1000u -#define AIPS_PACRL_TP4_SHIFT 12 -#define AIPS_PACRL_WP4_MASK 0x2000u -#define AIPS_PACRL_WP4_SHIFT 13 -#define AIPS_PACRL_SP4_MASK 0x4000u -#define AIPS_PACRL_SP4_SHIFT 14 -#define AIPS_PACRL_TP3_MASK 0x10000u -#define AIPS_PACRL_TP3_SHIFT 16 -#define AIPS_PACRL_WP3_MASK 0x20000u -#define AIPS_PACRL_WP3_SHIFT 17 -#define AIPS_PACRL_SP3_MASK 0x40000u -#define AIPS_PACRL_SP3_SHIFT 18 -#define AIPS_PACRL_TP2_MASK 0x100000u -#define AIPS_PACRL_TP2_SHIFT 20 -#define AIPS_PACRL_WP2_MASK 0x200000u -#define AIPS_PACRL_WP2_SHIFT 21 -#define AIPS_PACRL_SP2_MASK 0x400000u -#define AIPS_PACRL_SP2_SHIFT 22 -#define AIPS_PACRL_TP1_MASK 0x1000000u -#define AIPS_PACRL_TP1_SHIFT 24 -#define AIPS_PACRL_WP1_MASK 0x2000000u -#define AIPS_PACRL_WP1_SHIFT 25 -#define AIPS_PACRL_SP1_MASK 0x4000000u -#define AIPS_PACRL_SP1_SHIFT 26 -#define AIPS_PACRL_TP0_MASK 0x10000000u -#define AIPS_PACRL_TP0_SHIFT 28 -#define AIPS_PACRL_WP0_MASK 0x20000000u -#define AIPS_PACRL_WP0_SHIFT 29 -#define AIPS_PACRL_SP0_MASK 0x40000000u -#define AIPS_PACRL_SP0_SHIFT 30 -/* PACRM Bit Fields */ -#define AIPS_PACRM_TP7_MASK 0x1u -#define AIPS_PACRM_TP7_SHIFT 0 -#define AIPS_PACRM_WP7_MASK 0x2u -#define AIPS_PACRM_WP7_SHIFT 1 -#define AIPS_PACRM_SP7_MASK 0x4u -#define AIPS_PACRM_SP7_SHIFT 2 -#define AIPS_PACRM_TP6_MASK 0x10u -#define AIPS_PACRM_TP6_SHIFT 4 -#define AIPS_PACRM_WP6_MASK 0x20u -#define AIPS_PACRM_WP6_SHIFT 5 -#define AIPS_PACRM_SP6_MASK 0x40u -#define AIPS_PACRM_SP6_SHIFT 6 -#define AIPS_PACRM_TP5_MASK 0x100u -#define AIPS_PACRM_TP5_SHIFT 8 -#define AIPS_PACRM_WP5_MASK 0x200u -#define AIPS_PACRM_WP5_SHIFT 9 -#define AIPS_PACRM_SP5_MASK 0x400u -#define AIPS_PACRM_SP5_SHIFT 10 -#define AIPS_PACRM_TP4_MASK 0x1000u -#define AIPS_PACRM_TP4_SHIFT 12 -#define AIPS_PACRM_WP4_MASK 0x2000u -#define AIPS_PACRM_WP4_SHIFT 13 -#define AIPS_PACRM_SP4_MASK 0x4000u -#define AIPS_PACRM_SP4_SHIFT 14 -#define AIPS_PACRM_TP3_MASK 0x10000u -#define AIPS_PACRM_TP3_SHIFT 16 -#define AIPS_PACRM_WP3_MASK 0x20000u -#define AIPS_PACRM_WP3_SHIFT 17 -#define AIPS_PACRM_SP3_MASK 0x40000u -#define AIPS_PACRM_SP3_SHIFT 18 -#define AIPS_PACRM_TP2_MASK 0x100000u -#define AIPS_PACRM_TP2_SHIFT 20 -#define AIPS_PACRM_WP2_MASK 0x200000u -#define AIPS_PACRM_WP2_SHIFT 21 -#define AIPS_PACRM_SP2_MASK 0x400000u -#define AIPS_PACRM_SP2_SHIFT 22 -#define AIPS_PACRM_TP1_MASK 0x1000000u -#define AIPS_PACRM_TP1_SHIFT 24 -#define AIPS_PACRM_WP1_MASK 0x2000000u -#define AIPS_PACRM_WP1_SHIFT 25 -#define AIPS_PACRM_SP1_MASK 0x4000000u -#define AIPS_PACRM_SP1_SHIFT 26 -#define AIPS_PACRM_TP0_MASK 0x10000000u -#define AIPS_PACRM_TP0_SHIFT 28 -#define AIPS_PACRM_WP0_MASK 0x20000000u -#define AIPS_PACRM_WP0_SHIFT 29 -#define AIPS_PACRM_SP0_MASK 0x40000000u -#define AIPS_PACRM_SP0_SHIFT 30 -/* PACRN Bit Fields */ -#define AIPS_PACRN_TP7_MASK 0x1u -#define AIPS_PACRN_TP7_SHIFT 0 -#define AIPS_PACRN_WP7_MASK 0x2u -#define AIPS_PACRN_WP7_SHIFT 1 -#define AIPS_PACRN_SP7_MASK 0x4u -#define AIPS_PACRN_SP7_SHIFT 2 -#define AIPS_PACRN_TP6_MASK 0x10u -#define AIPS_PACRN_TP6_SHIFT 4 -#define AIPS_PACRN_WP6_MASK 0x20u -#define AIPS_PACRN_WP6_SHIFT 5 -#define AIPS_PACRN_SP6_MASK 0x40u -#define AIPS_PACRN_SP6_SHIFT 6 -#define AIPS_PACRN_TP5_MASK 0x100u -#define AIPS_PACRN_TP5_SHIFT 8 -#define AIPS_PACRN_WP5_MASK 0x200u -#define AIPS_PACRN_WP5_SHIFT 9 -#define AIPS_PACRN_SP5_MASK 0x400u -#define AIPS_PACRN_SP5_SHIFT 10 -#define AIPS_PACRN_TP4_MASK 0x1000u -#define AIPS_PACRN_TP4_SHIFT 12 -#define AIPS_PACRN_WP4_MASK 0x2000u -#define AIPS_PACRN_WP4_SHIFT 13 -#define AIPS_PACRN_SP4_MASK 0x4000u -#define AIPS_PACRN_SP4_SHIFT 14 -#define AIPS_PACRN_TP3_MASK 0x10000u -#define AIPS_PACRN_TP3_SHIFT 16 -#define AIPS_PACRN_WP3_MASK 0x20000u -#define AIPS_PACRN_WP3_SHIFT 17 -#define AIPS_PACRN_SP3_MASK 0x40000u -#define AIPS_PACRN_SP3_SHIFT 18 -#define AIPS_PACRN_TP2_MASK 0x100000u -#define AIPS_PACRN_TP2_SHIFT 20 -#define AIPS_PACRN_WP2_MASK 0x200000u -#define AIPS_PACRN_WP2_SHIFT 21 -#define AIPS_PACRN_SP2_MASK 0x400000u -#define AIPS_PACRN_SP2_SHIFT 22 -#define AIPS_PACRN_TP1_MASK 0x1000000u -#define AIPS_PACRN_TP1_SHIFT 24 -#define AIPS_PACRN_WP1_MASK 0x2000000u -#define AIPS_PACRN_WP1_SHIFT 25 -#define AIPS_PACRN_SP1_MASK 0x4000000u -#define AIPS_PACRN_SP1_SHIFT 26 -#define AIPS_PACRN_TP0_MASK 0x10000000u -#define AIPS_PACRN_TP0_SHIFT 28 -#define AIPS_PACRN_WP0_MASK 0x20000000u -#define AIPS_PACRN_WP0_SHIFT 29 -#define AIPS_PACRN_SP0_MASK 0x40000000u -#define AIPS_PACRN_SP0_SHIFT 30 -/* PACRO Bit Fields */ -#define AIPS_PACRO_TP7_MASK 0x1u -#define AIPS_PACRO_TP7_SHIFT 0 -#define AIPS_PACRO_WP7_MASK 0x2u -#define AIPS_PACRO_WP7_SHIFT 1 -#define AIPS_PACRO_SP7_MASK 0x4u -#define AIPS_PACRO_SP7_SHIFT 2 -#define AIPS_PACRO_TP6_MASK 0x10u -#define AIPS_PACRO_TP6_SHIFT 4 -#define AIPS_PACRO_WP6_MASK 0x20u -#define AIPS_PACRO_WP6_SHIFT 5 -#define AIPS_PACRO_SP6_MASK 0x40u -#define AIPS_PACRO_SP6_SHIFT 6 -#define AIPS_PACRO_TP5_MASK 0x100u -#define AIPS_PACRO_TP5_SHIFT 8 -#define AIPS_PACRO_WP5_MASK 0x200u -#define AIPS_PACRO_WP5_SHIFT 9 -#define AIPS_PACRO_SP5_MASK 0x400u -#define AIPS_PACRO_SP5_SHIFT 10 -#define AIPS_PACRO_TP4_MASK 0x1000u -#define AIPS_PACRO_TP4_SHIFT 12 -#define AIPS_PACRO_WP4_MASK 0x2000u -#define AIPS_PACRO_WP4_SHIFT 13 -#define AIPS_PACRO_SP4_MASK 0x4000u -#define AIPS_PACRO_SP4_SHIFT 14 -#define AIPS_PACRO_TP3_MASK 0x10000u -#define AIPS_PACRO_TP3_SHIFT 16 -#define AIPS_PACRO_WP3_MASK 0x20000u -#define AIPS_PACRO_WP3_SHIFT 17 -#define AIPS_PACRO_SP3_MASK 0x40000u -#define AIPS_PACRO_SP3_SHIFT 18 -#define AIPS_PACRO_TP2_MASK 0x100000u -#define AIPS_PACRO_TP2_SHIFT 20 -#define AIPS_PACRO_WP2_MASK 0x200000u -#define AIPS_PACRO_WP2_SHIFT 21 -#define AIPS_PACRO_SP2_MASK 0x400000u -#define AIPS_PACRO_SP2_SHIFT 22 -#define AIPS_PACRO_TP1_MASK 0x1000000u -#define AIPS_PACRO_TP1_SHIFT 24 -#define AIPS_PACRO_WP1_MASK 0x2000000u -#define AIPS_PACRO_WP1_SHIFT 25 -#define AIPS_PACRO_SP1_MASK 0x4000000u -#define AIPS_PACRO_SP1_SHIFT 26 -#define AIPS_PACRO_TP0_MASK 0x10000000u -#define AIPS_PACRO_TP0_SHIFT 28 -#define AIPS_PACRO_WP0_MASK 0x20000000u -#define AIPS_PACRO_WP0_SHIFT 29 -#define AIPS_PACRO_SP0_MASK 0x40000000u -#define AIPS_PACRO_SP0_SHIFT 30 -/* PACRP Bit Fields */ -#define AIPS_PACRP_TP7_MASK 0x1u -#define AIPS_PACRP_TP7_SHIFT 0 -#define AIPS_PACRP_WP7_MASK 0x2u -#define AIPS_PACRP_WP7_SHIFT 1 -#define AIPS_PACRP_SP7_MASK 0x4u -#define AIPS_PACRP_SP7_SHIFT 2 -#define AIPS_PACRP_TP6_MASK 0x10u -#define AIPS_PACRP_TP6_SHIFT 4 -#define AIPS_PACRP_WP6_MASK 0x20u -#define AIPS_PACRP_WP6_SHIFT 5 -#define AIPS_PACRP_SP6_MASK 0x40u -#define AIPS_PACRP_SP6_SHIFT 6 -#define AIPS_PACRP_TP5_MASK 0x100u -#define AIPS_PACRP_TP5_SHIFT 8 -#define AIPS_PACRP_WP5_MASK 0x200u -#define AIPS_PACRP_WP5_SHIFT 9 -#define AIPS_PACRP_SP5_MASK 0x400u -#define AIPS_PACRP_SP5_SHIFT 10 -#define AIPS_PACRP_TP4_MASK 0x1000u -#define AIPS_PACRP_TP4_SHIFT 12 -#define AIPS_PACRP_WP4_MASK 0x2000u -#define AIPS_PACRP_WP4_SHIFT 13 -#define AIPS_PACRP_SP4_MASK 0x4000u -#define AIPS_PACRP_SP4_SHIFT 14 -#define AIPS_PACRP_TP3_MASK 0x10000u -#define AIPS_PACRP_TP3_SHIFT 16 -#define AIPS_PACRP_WP3_MASK 0x20000u -#define AIPS_PACRP_WP3_SHIFT 17 -#define AIPS_PACRP_SP3_MASK 0x40000u -#define AIPS_PACRP_SP3_SHIFT 18 -#define AIPS_PACRP_TP2_MASK 0x100000u -#define AIPS_PACRP_TP2_SHIFT 20 -#define AIPS_PACRP_WP2_MASK 0x200000u -#define AIPS_PACRP_WP2_SHIFT 21 -#define AIPS_PACRP_SP2_MASK 0x400000u -#define AIPS_PACRP_SP2_SHIFT 22 -#define AIPS_PACRP_TP1_MASK 0x1000000u -#define AIPS_PACRP_TP1_SHIFT 24 -#define AIPS_PACRP_WP1_MASK 0x2000000u -#define AIPS_PACRP_WP1_SHIFT 25 -#define AIPS_PACRP_SP1_MASK 0x4000000u -#define AIPS_PACRP_SP1_SHIFT 26 -#define AIPS_PACRP_TP0_MASK 0x10000000u -#define AIPS_PACRP_TP0_SHIFT 28 -#define AIPS_PACRP_WP0_MASK 0x20000000u -#define AIPS_PACRP_WP0_SHIFT 29 -#define AIPS_PACRP_SP0_MASK 0x40000000u -#define AIPS_PACRP_SP0_SHIFT 30 -/* PACRU Bit Fields */ -#define AIPS_PACRU_TP1_MASK 0x1000000u -#define AIPS_PACRU_TP1_SHIFT 24 -#define AIPS_PACRU_WP1_MASK 0x2000000u -#define AIPS_PACRU_WP1_SHIFT 25 -#define AIPS_PACRU_SP1_MASK 0x4000000u -#define AIPS_PACRU_SP1_SHIFT 26 -#define AIPS_PACRU_TP0_MASK 0x10000000u -#define AIPS_PACRU_TP0_SHIFT 28 -#define AIPS_PACRU_WP0_MASK 0x20000000u -#define AIPS_PACRU_WP0_SHIFT 29 -#define AIPS_PACRU_SP0_MASK 0x40000000u -#define AIPS_PACRU_SP0_SHIFT 30 - -/*! - * @} - */ /* end of group AIPS_Register_Masks */ - - -/* AIPS - Peripheral instance base addresses */ -/** Peripheral AIPS0 base address */ -#define AIPS0_BASE (0x40000000u) -/** Peripheral AIPS0 base pointer */ -#define AIPS0 ((AIPS_Type *)AIPS0_BASE) -#define AIPS0_BASE_PTR (AIPS0) -/** Peripheral AIPS1 base address */ -#define AIPS1_BASE (0x40080000u) -/** Peripheral AIPS1 base pointer */ -#define AIPS1 ((AIPS_Type *)AIPS1_BASE) -#define AIPS1_BASE_PTR (AIPS1) -/** Array initializer of AIPS peripheral base addresses */ -#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } -/** Array initializer of AIPS peripheral base pointers */ -#define AIPS_BASE_PTRS { AIPS0, AIPS1 } - -/* ---------------------------------------------------------------------------- - -- AIPS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros - * @{ - */ - - -/* AIPS - Register instance definitions */ -/* AIPS0 */ -#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) -#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) -#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) -#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) -#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) -#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) -#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) -#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) -#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) -#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) -#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) -#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) -#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) -#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) -#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) -#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) -#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) -#define AIPS0_PACRU AIPS_PACRU_REG(AIPS0) -/* AIPS1 */ -#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) -#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) -#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) -#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) -#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) -#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) -#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) -#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) -#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) -#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) -#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) -#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) -#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) -#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) -#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) -#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) -#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) -#define AIPS1_PACRU AIPS_PACRU_REG(AIPS1) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group AIPS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AXBS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer - * @{ - */ - -/** AXBS - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ - uint8_t RESERVED_0[12]; - __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_1[236]; - } SLAVE[5]; - uint8_t RESERVED_0[768]; - __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ - uint8_t RESERVED_1[252]; - __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ - uint8_t RESERVED_2[252]; - __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ - uint8_t RESERVED_3[252]; - __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ - uint8_t RESERVED_4[252]; - __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ - uint8_t RESERVED_5[252]; - __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ -} AXBS_Type, *AXBS_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- AXBS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros - * @{ - */ - - -/* AXBS - Register accessors */ -#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) -#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) -#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) -#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) -#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) -#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) -#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) -#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) - -/*! - * @} - */ /* end of group AXBS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- AXBS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Masks AXBS Register Masks - * @{ - */ - -/* PRS Bit Fields */ -#define AXBS_PRS_M0_MASK 0x7u -#define AXBS_PRS_M0_SHIFT 0 -#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define CAN_CTRL1_REG(base) ((base)->CTRL1) -#define CAN_TIMER_REG(base) ((base)->TIMER) -#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) -#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) -#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) -#define CAN_ECR_REG(base) ((base)->ECR) -#define CAN_ESR1_REG(base) ((base)->ESR1) -#define CAN_IMASK1_REG(base) ((base)->IMASK1) -#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) -#define CAN_CTRL2_REG(base) ((base)->CTRL2) -#define CAN_ESR2_REG(base) ((base)->ESR2) -#define CAN_CRCR_REG(base) ((base)->CRCR) -#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) -#define CAN_RXFIR_REG(base) ((base)->RXFIR) -#define CAN_CS_REG(base,index) ((base)->MB[index].CS) -#define CAN_ID_REG(base,index) ((base)->MB[index].ID) -#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) -#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) -#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) - -/*! - * @} - */ /* end of group CAN_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define CAN_MCR_MAXMB_MASK 0x7Fu -#define CAN_MCR_MAXMB_SHIFT 0 -#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index]) -#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) -#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) -#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) -#define CAU_STR_CASR_REG(base) ((base)->STR_CASR) -#define CAU_STR_CAA_REG(base) ((base)->STR_CAA) -#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) -#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) -#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) -#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) -#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) -#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) -#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) -#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) -#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) -#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) -#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) -#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) -#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) -#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) -#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) -#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) -#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) -#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) -#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) - -/*! - * @} - */ /* end of group CAU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CAU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU_Register_Masks CAU Register Masks - * @{ - */ - -/* DIRECT Bit Fields */ -#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu -#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 -#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) -#define CMT_CGL1_REG(base) ((base)->CGL1) -#define CMT_CGH2_REG(base) ((base)->CGH2) -#define CMT_CGL2_REG(base) ((base)->CGL2) -#define CMT_OC_REG(base) ((base)->OC) -#define CMT_MSC_REG(base) ((base)->MSC) -#define CMT_CMD1_REG(base) ((base)->CMD1) -#define CMT_CMD2_REG(base) ((base)->CMD2) -#define CMT_CMD3_REG(base) ((base)->CMD3) -#define CMT_CMD4_REG(base) ((base)->CMD4) -#define CMT_PPS_REG(base) ((base)->PPS) -#define CMT_DMA_REG(base) ((base)->DMA) - -/*! - * @} - */ /* end of group CMT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMT_Register_Masks CMT Register Masks - * @{ - */ - -/* CGH1 Bit Fields */ -#define CMT_CGH1_PH_MASK 0xFFu -#define CMT_CGH1_PH_SHIFT 0 -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) -#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) -#define CRC_DATA_REG(base) ((base)->DATA) -#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) -#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) -#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) -#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/* DATAL Bit Fields */ -#define CRC_DATAL_DATAL_MASK 0xFFFFu -#define CRC_DATAL_DATAL_SHIFT 0 -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<EIR) -#define ENET_EIMR_REG(base) ((base)->EIMR) -#define ENET_RDAR_REG(base) ((base)->RDAR) -#define ENET_TDAR_REG(base) ((base)->TDAR) -#define ENET_ECR_REG(base) ((base)->ECR) -#define ENET_MMFR_REG(base) ((base)->MMFR) -#define ENET_MSCR_REG(base) ((base)->MSCR) -#define ENET_MIBC_REG(base) ((base)->MIBC) -#define ENET_RCR_REG(base) ((base)->RCR) -#define ENET_TCR_REG(base) ((base)->TCR) -#define ENET_PALR_REG(base) ((base)->PALR) -#define ENET_PAUR_REG(base) ((base)->PAUR) -#define ENET_OPD_REG(base) ((base)->OPD) -#define ENET_IAUR_REG(base) ((base)->IAUR) -#define ENET_IALR_REG(base) ((base)->IALR) -#define ENET_GAUR_REG(base) ((base)->GAUR) -#define ENET_GALR_REG(base) ((base)->GALR) -#define ENET_TFWR_REG(base) ((base)->TFWR) -#define ENET_RDSR_REG(base) ((base)->RDSR) -#define ENET_TDSR_REG(base) ((base)->TDSR) -#define ENET_MRBR_REG(base) ((base)->MRBR) -#define ENET_RSFL_REG(base) ((base)->RSFL) -#define ENET_RSEM_REG(base) ((base)->RSEM) -#define ENET_RAEM_REG(base) ((base)->RAEM) -#define ENET_RAFL_REG(base) ((base)->RAFL) -#define ENET_TSEM_REG(base) ((base)->TSEM) -#define ENET_TAEM_REG(base) ((base)->TAEM) -#define ENET_TAFL_REG(base) ((base)->TAFL) -#define ENET_TIPG_REG(base) ((base)->TIPG) -#define ENET_FTRL_REG(base) ((base)->FTRL) -#define ENET_TACC_REG(base) ((base)->TACC) -#define ENET_RACC_REG(base) ((base)->RACC) -#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) -#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) -#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) -#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) -#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) -#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) -#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) -#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) -#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) -#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) -#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) -#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) -#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) -#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) -#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) -#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) -#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) -#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) -#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) -#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) -#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) -#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) -#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) -#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) -#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) -#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) -#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) -#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) -#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) -#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) -#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) -#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) -#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) -#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) -#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) -#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) -#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) -#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) -#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) -#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) -#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) -#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) -#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) -#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) -#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) -#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) -#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) -#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) -#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) -#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) -#define ENET_ATCR_REG(base) ((base)->ATCR) -#define ENET_ATVR_REG(base) ((base)->ATVR) -#define ENET_ATOFF_REG(base) ((base)->ATOFF) -#define ENET_ATPER_REG(base) ((base)->ATPER) -#define ENET_ATCOR_REG(base) ((base)->ATCOR) -#define ENET_ATINC_REG(base) ((base)->ATINC) -#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) -#define ENET_TGSR_REG(base) ((base)->TGSR) -#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) -#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) - -/*! - * @} - */ /* end of group ENET_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ENET Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Register_Masks ENET Register Masks - * @{ - */ - -/* EIR Bit Fields */ -#define ENET_EIR_TS_TIMER_MASK 0x8000u -#define ENET_EIR_TS_TIMER_SHIFT 15 -#define ENET_EIR_TS_AVAIL_MASK 0x10000u -#define ENET_EIR_TS_AVAIL_SHIFT 16 -#define ENET_EIR_WAKEUP_MASK 0x20000u -#define ENET_EIR_WAKEUP_SHIFT 17 -#define ENET_EIR_PLR_MASK 0x40000u -#define ENET_EIR_PLR_SHIFT 18 -#define ENET_EIR_UN_MASK 0x80000u -#define ENET_EIR_UN_SHIFT 19 -#define ENET_EIR_RL_MASK 0x100000u -#define ENET_EIR_RL_SHIFT 20 -#define ENET_EIR_LC_MASK 0x200000u -#define ENET_EIR_LC_SHIFT 21 -#define ENET_EIR_EBERR_MASK 0x400000u -#define ENET_EIR_EBERR_SHIFT 22 -#define ENET_EIR_MII_MASK 0x800000u -#define ENET_EIR_MII_SHIFT 23 -#define ENET_EIR_RXB_MASK 0x1000000u -#define ENET_EIR_RXB_SHIFT 24 -#define ENET_EIR_RXF_MASK 0x2000000u -#define ENET_EIR_RXF_SHIFT 25 -#define ENET_EIR_TXB_MASK 0x4000000u -#define ENET_EIR_TXB_SHIFT 26 -#define ENET_EIR_TXF_MASK 0x8000000u -#define ENET_EIR_TXF_SHIFT 27 -#define ENET_EIR_GRA_MASK 0x10000000u -#define ENET_EIR_GRA_SHIFT 28 -#define ENET_EIR_BABT_MASK 0x20000000u -#define ENET_EIR_BABT_SHIFT 29 -#define ENET_EIR_BABR_MASK 0x40000000u -#define ENET_EIR_BABR_SHIFT 30 -/* EIMR Bit Fields */ -#define ENET_EIMR_TS_TIMER_MASK 0x8000u -#define ENET_EIMR_TS_TIMER_SHIFT 15 -#define ENET_EIMR_TS_AVAIL_MASK 0x10000u -#define ENET_EIMR_TS_AVAIL_SHIFT 16 -#define ENET_EIMR_WAKEUP_MASK 0x20000u -#define ENET_EIMR_WAKEUP_SHIFT 17 -#define ENET_EIMR_PLR_MASK 0x40000u -#define ENET_EIMR_PLR_SHIFT 18 -#define ENET_EIMR_UN_MASK 0x80000u -#define ENET_EIMR_UN_SHIFT 19 -#define ENET_EIMR_RL_MASK 0x100000u -#define ENET_EIMR_RL_SHIFT 20 -#define ENET_EIMR_LC_MASK 0x200000u -#define ENET_EIMR_LC_SHIFT 21 -#define ENET_EIMR_EBERR_MASK 0x400000u -#define ENET_EIMR_EBERR_SHIFT 22 -#define ENET_EIMR_MII_MASK 0x800000u -#define ENET_EIMR_MII_SHIFT 23 -#define ENET_EIMR_RXB_MASK 0x1000000u -#define ENET_EIMR_RXB_SHIFT 24 -#define ENET_EIMR_RXF_MASK 0x2000000u -#define ENET_EIMR_RXF_SHIFT 25 -#define ENET_EIMR_TXB_MASK 0x4000000u -#define ENET_EIMR_TXB_SHIFT 26 -#define ENET_EIMR_TXF_MASK 0x8000000u -#define ENET_EIMR_TXF_SHIFT 27 -#define ENET_EIMR_GRA_MASK 0x10000000u -#define ENET_EIMR_GRA_SHIFT 28 -#define ENET_EIMR_BABT_MASK 0x20000000u -#define ENET_EIMR_BABT_SHIFT 29 -#define ENET_EIMR_BABR_MASK 0x40000000u -#define ENET_EIMR_BABR_SHIFT 30 -/* RDAR Bit Fields */ -#define ENET_RDAR_RDAR_MASK 0x1000000u -#define ENET_RDAR_RDAR_SHIFT 24 -/* TDAR Bit Fields */ -#define ENET_TDAR_TDAR_MASK 0x1000000u -#define ENET_TDAR_TDAR_SHIFT 24 -/* ECR Bit Fields */ -#define ENET_ECR_RESET_MASK 0x1u -#define ENET_ECR_RESET_SHIFT 0 -#define ENET_ECR_ETHEREN_MASK 0x2u -#define ENET_ECR_ETHEREN_SHIFT 1 -#define ENET_ECR_MAGICEN_MASK 0x4u -#define ENET_ECR_MAGICEN_SHIFT 2 -#define ENET_ECR_SLEEP_MASK 0x8u -#define ENET_ECR_SLEEP_SHIFT 3 -#define ENET_ECR_EN1588_MASK 0x10u -#define ENET_ECR_EN1588_SHIFT 4 -#define ENET_ECR_DBGEN_MASK 0x40u -#define ENET_ECR_DBGEN_SHIFT 6 -#define ENET_ECR_STOPEN_MASK 0x80u -#define ENET_ECR_STOPEN_SHIFT 7 -#define ENET_ECR_DBSWP_MASK 0x100u -#define ENET_ECR_DBSWP_SHIFT 8 -/* MMFR Bit Fields */ -#define ENET_MMFR_DATA_MASK 0xFFFFu -#define ENET_MMFR_DATA_SHIFT 0 -#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Register_Masks FB Register Masks - * @{ - */ - -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) -#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) -#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) -#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFE_FCNFG_REG(base) ((base)->FCNFG) -#define FTFE_FSEC_REG(base) ((base)->FSEC) -#define FTFE_FOPT_REG(base) ((base)->FOPT) -#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFE_FPROT3_REG(base) ((base)->FPROT3) -#define FTFE_FPROT2_REG(base) ((base)->FPROT2) -#define FTFE_FPROT1_REG(base) ((base)->FPROT1) -#define FTFE_FPROT0_REG(base) ((base)->FPROT0) -#define FTFE_FEPROT_REG(base) ((base)->FEPROT) -#define FTFE_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group FTFE_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTFE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFE_Register_Masks FTFE Register Masks - * @{ - */ - -/* FSTAT Bit Fields */ -#define FTFE_FSTAT_MGSTAT0_MASK 0x1u -#define FTFE_FSTAT_MGSTAT0_SHIFT 0 -#define FTFE_FSTAT_FPVIOL_MASK 0x10u -#define FTFE_FSTAT_FPVIOL_SHIFT 4 -#define FTFE_FSTAT_ACCERR_MASK 0x20u -#define FTFE_FSTAT_ACCERR_SHIFT 5 -#define FTFE_FSTAT_RDCOLERR_MASK 0x40u -#define FTFE_FSTAT_RDCOLERR_SHIFT 6 -#define FTFE_FSTAT_CCIF_MASK 0x80u -#define FTFE_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFE_FCNFG_EEERDY_MASK 0x1u -#define FTFE_FCNFG_EEERDY_SHIFT 0 -#define FTFE_FCNFG_RAMRDY_MASK 0x2u -#define FTFE_FCNFG_RAMRDY_SHIFT 1 -#define FTFE_FCNFG_PFLSH_MASK 0x4u -#define FTFE_FCNFG_PFLSH_SHIFT 2 -#define FTFE_FCNFG_SWAP_MASK 0x8u -#define FTFE_FCNFG_SWAP_SHIFT 3 -#define FTFE_FCNFG_ERSSUSP_MASK 0x10u -#define FTFE_FCNFG_ERSSUSP_SHIFT 4 -#define FTFE_FCNFG_ERSAREQ_MASK 0x20u -#define FTFE_FCNFG_ERSAREQ_SHIFT 5 -#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFE_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFE_FCNFG_CCIE_MASK 0x80u -#define FTFE_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFE_FSEC_SEC_MASK 0x3u -#define FTFE_FSEC_SEC_SHIFT 0 -#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTM_Register_Masks FTM Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) -#define LLWU_RST_REG(base) ((base)->RST) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_CR_REG(base) ((base)->CR) -#define MCM_ISCR_REG(base) ((base)->ISCR) -#define MCM_ETBCC_REG(base) ((base)->ETBCC) -#define MCM_ETBRL_REG(base) ((base)->ETBRL) -#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) -#define MCM_PID_REG(base) ((base)->PID) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) -#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) -#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) -#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) -#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) - -/*! - * @} - */ /* end of group MPU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MPU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MPU_Register_Masks MPU Register Masks - * @{ - */ - -/* CESR Bit Fields */ -#define MPU_CESR_VLD_MASK 0x1u -#define MPU_CESR_VLD_SHIFT 0 -#define MPU_CESR_NRGD_MASK 0xF00u -#define MPU_CESR_NRGD_SHIFT 8 -#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) -#define NV_FEPROT_REG(base) ((base)->FEPROT) -#define NV_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 - -/*! - * @} - */ /* end of group OSC_Register_Masks */ - - -/* OSC - Peripheral instance base addresses */ -/** Peripheral OSC base address */ -#define OSC_BASE (0x40065000u) -/** Peripheral OSC base pointer */ -#define OSC ((OSC_Type *)OSC_BASE) -#define OSC_BASE_PTR (OSC) -/** Array initializer of OSC peripheral base addresses */ -#define OSC_BASE_ADDRS { OSC_BASE } -/** Array initializer of OSC peripheral base pointers */ -#define OSC_BASE_PTRS { OSC } - -/* ---------------------------------------------------------------------------- - -- OSC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros - * @{ - */ - - -/* OSC - Register instance definitions */ -/* OSC */ -#define OSC_CR OSC_CR_REG(OSC) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group OSC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PDB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer - * @{ - */ - -/** PDB - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ - __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ - __I uint32_t CNT; /**< Counter register, offset: 0x8 */ - __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ - struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ - __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ - __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ - uint8_t RESERVED_0[24]; - } CH[2]; - uint8_t RESERVED_0[240]; - struct { /* offset: 0x150, array step: 0x8 */ - __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ - __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ - } DAC[2]; - uint8_t RESERVED_1[48]; - __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ - __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ -} PDB_Type, *PDB_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- PDB - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros - * @{ - */ - - -/* PDB - Register accessors */ -#define PDB_SC_REG(base) ((base)->SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PDB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Masks PDB Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFVBAT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_HA_MASK 0x2u -#define RNG_CR_HA_SHIFT 1 -#define RNG_CR_INTM_MASK 0x4u -#define RNG_CR_INTM_SHIFT 2 -#define RNG_CR_CLRI_MASK 0x8u -#define RNG_CR_CLRI_SHIFT 3 -#define RNG_CR_SLP_MASK 0x10u -#define RNG_CR_SLP_SHIFT 4 -/* SR Bit Fields */ -#define RNG_SR_SECV_MASK 0x1u -#define RNG_SR_SECV_SHIFT 0 -#define RNG_SR_LRS_MASK 0x2u -#define RNG_SR_LRS_SHIFT 1 -#define RNG_SR_ORU_MASK 0x4u -#define RNG_SR_ORU_SHIFT 2 -#define RNG_SR_ERRI_MASK 0x8u -#define RNG_SR_ERRI_SHIFT 3 -#define RNG_SR_SLP_MASK 0x10u -#define RNG_SR_SLP_SHIFT 4 -#define RNG_SR_OREG_LVL_MASK 0xFF00u -#define RNG_SR_OREG_LVL_SHIFT 8 -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) -#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) -#define SDHC_CMDARG_REG(base) ((base)->CMDARG) -#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) -#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) -#define SDHC_DATPORT_REG(base) ((base)->DATPORT) -#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) -#define SDHC_PROCTL_REG(base) ((base)->PROCTL) -#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) -#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) -#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) -#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) -#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) -#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) -#define SDHC_WML_REG(base) ((base)->WML) -#define SDHC_FEVT_REG(base) ((base)->FEVT) -#define SDHC_ADMAES_REG(base) ((base)->ADMAES) -#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) -#define SDHC_VENDOR_REG(base) ((base)->VENDOR) -#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) -#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) - -/*! - * @} - */ /* end of group SDHC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDHC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDHC_Register_Masks SDHC Register Masks - * @{ - */ - -/* DSADDR Bit Fields */ -#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu -#define SDHC_DSADDR_DSADDR_SHIFT 2 -#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC1_REG(base) ((base)->SCGC1) -#define SIM_SCGC2_REG(base) ((base)->SCGC2) -#define SIM_SCGC3_REG(base) ((base)->SCGC3) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816T0_REG(base) ((base)->WP7816T0) -#define UART_WP7816T1_REG(base) ((base)->WP7816T1) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) -#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) -#define USBDCD_STATUS_REG(base) ((base)->STATUS) -#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) -#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) -#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11) -#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12) - -/*! - * @} - */ /* end of group USBDCD_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USBDCD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBDCD_Register_Masks USBDCD Register Masks - * @{ - */ - -/* CONTROL Bit Fields */ -#define USBDCD_CONTROL_IACK_MASK 0x1u -#define USBDCD_CONTROL_IACK_SHIFT 0 -#define USBDCD_CONTROL_IF_MASK 0x100u -#define USBDCD_CONTROL_IF_SHIFT 8 -#define USBDCD_CONTROL_IE_MASK 0x10000u -#define USBDCD_CONTROL_IE_SHIFT 16 -#define USBDCD_CONTROL_BC12_MASK 0x20000u -#define USBDCD_CONTROL_BC12_SHIFT 17 -#define USBDCD_CONTROL_START_MASK 0x1000000u -#define USBDCD_CONTROL_START_SHIFT 24 -#define USBDCD_CONTROL_SR_MASK 0x2000000u -#define USBDCD_CONTROL_SR_SHIFT 25 -/* CLOCK Bit Fields */ -#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u -#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 -#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu -#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 -#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<&HW_ADC(ADC0_BASE). */ -#define HW_ADC(x) (*(hw_adc_t *)(x)) - -#endif /* __HW_ADC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_aips.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_aips.h deleted file mode 100644 index 0ca874e58ac..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_aips.h +++ /dev/null @@ -1,12467 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_AIPS_REGISTERS_H__ -#define __HW_AIPS_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 AIPS - * - * AIPS-Lite Bridge - * - * Registers defined in this header file: - * - HW_AIPS_MPRA - Master Privilege Register A - * - HW_AIPS_PACRA - Peripheral Access Control Register - * - HW_AIPS_PACRB - Peripheral Access Control Register - * - HW_AIPS_PACRC - Peripheral Access Control Register - * - HW_AIPS_PACRD - Peripheral Access Control Register - * - HW_AIPS_PACRE - Peripheral Access Control Register - * - HW_AIPS_PACRF - Peripheral Access Control Register - * - HW_AIPS_PACRG - Peripheral Access Control Register - * - HW_AIPS_PACRH - Peripheral Access Control Register - * - HW_AIPS_PACRI - Peripheral Access Control Register - * - HW_AIPS_PACRJ - Peripheral Access Control Register - * - HW_AIPS_PACRK - Peripheral Access Control Register - * - HW_AIPS_PACRL - Peripheral Access Control Register - * - HW_AIPS_PACRM - Peripheral Access Control Register - * - HW_AIPS_PACRN - Peripheral Access Control Register - * - HW_AIPS_PACRO - Peripheral Access Control Register - * - HW_AIPS_PACRP - Peripheral Access Control Register - * - HW_AIPS_PACRU - Peripheral Access Control Register - * - * - hw_aips_t - Struct containing all module registers. - */ - -#define HW_AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */ -#define HW_AIPS0 (0U) /*!< Instance number for AIPS0. */ -#define HW_AIPS1 (1U) /*!< Instance number for AIPS1. */ - -/******************************************************************************* - * HW_AIPS_MPRA - Master Privilege Register A - ******************************************************************************/ - -/*! - * @brief HW_AIPS_MPRA - Master Privilege Register A (RW) - * - * Reset value: 0x77700000U - * - * The MPRA specifies identical 4-bit fields defining the access-privilege level - * associated with a bus master to various peripherals on the chip. The register - * provides one field per bus master. At reset, the default value loaded into - * the MPRA fields is chip-specific. See the chip configuration details for the - * value of a particular device. A register field that maps to an unimplemented - * master or peripheral behaves as read-only-zero. Each master is assigned a logical - * ID from 0 to 15. See the master logical ID assignment table in the - * chip-specific AIPS information. - */ -typedef union _hw_aips_mpra -{ - uint32_t U; - struct _hw_aips_mpra_bitfields - { - uint32_t RESERVED0 : 8; /*!< [7:0] */ - uint32_t MPL5 : 1; /*!< [8] Master 5 Privilege Level */ - uint32_t MTW5 : 1; /*!< [9] Master 5 Trusted For Writes */ - uint32_t MTR5 : 1; /*!< [10] Master 5 Trusted For Read */ - uint32_t RESERVED1 : 1; /*!< [11] */ - uint32_t MPL4 : 1; /*!< [12] Master 4 Privilege Level */ - uint32_t MTW4 : 1; /*!< [13] Master 4 Trusted For Writes */ - uint32_t MTR4 : 1; /*!< [14] Master 4 Trusted For Read */ - uint32_t RESERVED2 : 1; /*!< [15] */ - uint32_t MPL3 : 1; /*!< [16] Master 3 Privilege Level */ - uint32_t MTW3 : 1; /*!< [17] Master 3 Trusted For Writes */ - uint32_t MTR3 : 1; /*!< [18] Master 3 Trusted For Read */ - uint32_t RESERVED3 : 1; /*!< [19] */ - uint32_t MPL2 : 1; /*!< [20] Master 2 Privilege Level */ - uint32_t MTW2 : 1; /*!< [21] Master 2 Trusted For Writes */ - uint32_t MTR2 : 1; /*!< [22] Master 2 Trusted For Read */ - uint32_t RESERVED4 : 1; /*!< [23] */ - uint32_t MPL1 : 1; /*!< [24] Master 1 Privilege Level */ - uint32_t MTW1 : 1; /*!< [25] Master 1 Trusted for Writes */ - uint32_t MTR1 : 1; /*!< [26] Master 1 Trusted for Read */ - uint32_t RESERVED5 : 1; /*!< [27] */ - uint32_t MPL0 : 1; /*!< [28] Master 0 Privilege Level */ - uint32_t MTW0 : 1; /*!< [29] Master 0 Trusted For Writes */ - uint32_t MTR0 : 1; /*!< [30] Master 0 Trusted For Read */ - uint32_t RESERVED6 : 1; /*!< [31] */ - } B; -} hw_aips_mpra_t; - -/*! - * @name Constants and macros for entire AIPS_MPRA register - */ -/*@{*/ -#define HW_AIPS_MPRA_ADDR(x) ((x) + 0x0U) - -#define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x)) -#define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U) -#define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v)) -#define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v))) -#define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v))) -#define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_MPRA bitfields - */ - -/*! - * @name Register AIPS_MPRA, field MPL5[8] (RW) - * - * Specifies how the privilege level of the master is determined. - * - * Values: - * - 0 - Accesses from this master are forced to user-mode. - * - 1 - Accesses from this master are not forced to user-mode. - */ -/*@{*/ -#define BP_AIPS_MPRA_MPL5 (8U) /*!< Bit position for AIPS_MPRA_MPL5. */ -#define BM_AIPS_MPRA_MPL5 (0x00000100U) /*!< Bit mask for AIPS_MPRA_MPL5. */ -#define BS_AIPS_MPRA_MPL5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL5. */ - -/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */ -#define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5)) - -/*! @brief Format value for bitfield AIPS_MPRA_MPL5. */ -#define BF_AIPS_MPRA_MPL5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL5) & BM_AIPS_MPRA_MPL5) - -/*! @brief Set the MPL5 field to a new value. */ -#define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTW5[9] (RW) - * - * Determines whether the master is trusted for write accesses. - * - * Values: - * - 0 - This master is not trusted for write accesses. - * - 1 - This master is trusted for write accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTW5 (9U) /*!< Bit position for AIPS_MPRA_MTW5. */ -#define BM_AIPS_MPRA_MTW5 (0x00000200U) /*!< Bit mask for AIPS_MPRA_MTW5. */ -#define BS_AIPS_MPRA_MTW5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW5. */ - -/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */ -#define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTW5. */ -#define BF_AIPS_MPRA_MTW5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW5) & BM_AIPS_MPRA_MTW5) - -/*! @brief Set the MTW5 field to a new value. */ -#define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTR5[10] (RW) - * - * Determines whether the master is trusted for read accesses. - * - * Values: - * - 0 - This master is not trusted for read accesses. - * - 1 - This master is trusted for read accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTR5 (10U) /*!< Bit position for AIPS_MPRA_MTR5. */ -#define BM_AIPS_MPRA_MTR5 (0x00000400U) /*!< Bit mask for AIPS_MPRA_MTR5. */ -#define BS_AIPS_MPRA_MTR5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR5. */ - -/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */ -#define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTR5. */ -#define BF_AIPS_MPRA_MTR5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR5) & BM_AIPS_MPRA_MTR5) - -/*! @brief Set the MTR5 field to a new value. */ -#define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MPL4[12] (RW) - * - * Specifies how the privilege level of the master is determined. - * - * Values: - * - 0 - Accesses from this master are forced to user-mode. - * - 1 - Accesses from this master are not forced to user-mode. - */ -/*@{*/ -#define BP_AIPS_MPRA_MPL4 (12U) /*!< Bit position for AIPS_MPRA_MPL4. */ -#define BM_AIPS_MPRA_MPL4 (0x00001000U) /*!< Bit mask for AIPS_MPRA_MPL4. */ -#define BS_AIPS_MPRA_MPL4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL4. */ - -/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */ -#define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4)) - -/*! @brief Format value for bitfield AIPS_MPRA_MPL4. */ -#define BF_AIPS_MPRA_MPL4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL4) & BM_AIPS_MPRA_MPL4) - -/*! @brief Set the MPL4 field to a new value. */ -#define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTW4[13] (RW) - * - * Determines whether the master is trusted for write accesses. - * - * Values: - * - 0 - This master is not trusted for write accesses. - * - 1 - This master is trusted for write accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTW4 (13U) /*!< Bit position for AIPS_MPRA_MTW4. */ -#define BM_AIPS_MPRA_MTW4 (0x00002000U) /*!< Bit mask for AIPS_MPRA_MTW4. */ -#define BS_AIPS_MPRA_MTW4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW4. */ - -/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */ -#define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTW4. */ -#define BF_AIPS_MPRA_MTW4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW4) & BM_AIPS_MPRA_MTW4) - -/*! @brief Set the MTW4 field to a new value. */ -#define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTR4[14] (RW) - * - * Determines whether the master is trusted for read accesses. - * - * Values: - * - 0 - This master is not trusted for read accesses. - * - 1 - This master is trusted for read accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTR4 (14U) /*!< Bit position for AIPS_MPRA_MTR4. */ -#define BM_AIPS_MPRA_MTR4 (0x00004000U) /*!< Bit mask for AIPS_MPRA_MTR4. */ -#define BS_AIPS_MPRA_MTR4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR4. */ - -/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */ -#define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTR4. */ -#define BF_AIPS_MPRA_MTR4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR4) & BM_AIPS_MPRA_MTR4) - -/*! @brief Set the MTR4 field to a new value. */ -#define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MPL3[16] (RW) - * - * Specifies how the privilege level of the master is determined. - * - * Values: - * - 0 - Accesses from this master are forced to user-mode. - * - 1 - Accesses from this master are not forced to user-mode. - */ -/*@{*/ -#define BP_AIPS_MPRA_MPL3 (16U) /*!< Bit position for AIPS_MPRA_MPL3. */ -#define BM_AIPS_MPRA_MPL3 (0x00010000U) /*!< Bit mask for AIPS_MPRA_MPL3. */ -#define BS_AIPS_MPRA_MPL3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL3. */ - -/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */ -#define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3)) - -/*! @brief Format value for bitfield AIPS_MPRA_MPL3. */ -#define BF_AIPS_MPRA_MPL3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL3) & BM_AIPS_MPRA_MPL3) - -/*! @brief Set the MPL3 field to a new value. */ -#define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTW3[17] (RW) - * - * Determines whether the master is trusted for write accesses. - * - * Values: - * - 0 - This master is not trusted for write accesses. - * - 1 - This master is trusted for write accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTW3 (17U) /*!< Bit position for AIPS_MPRA_MTW3. */ -#define BM_AIPS_MPRA_MTW3 (0x00020000U) /*!< Bit mask for AIPS_MPRA_MTW3. */ -#define BS_AIPS_MPRA_MTW3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW3. */ - -/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */ -#define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTW3. */ -#define BF_AIPS_MPRA_MTW3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW3) & BM_AIPS_MPRA_MTW3) - -/*! @brief Set the MTW3 field to a new value. */ -#define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTR3[18] (RW) - * - * Determines whether the master is trusted for read accesses. - * - * Values: - * - 0 - This master is not trusted for read accesses. - * - 1 - This master is trusted for read accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTR3 (18U) /*!< Bit position for AIPS_MPRA_MTR3. */ -#define BM_AIPS_MPRA_MTR3 (0x00040000U) /*!< Bit mask for AIPS_MPRA_MTR3. */ -#define BS_AIPS_MPRA_MTR3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR3. */ - -/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */ -#define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTR3. */ -#define BF_AIPS_MPRA_MTR3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR3) & BM_AIPS_MPRA_MTR3) - -/*! @brief Set the MTR3 field to a new value. */ -#define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MPL2[20] (RW) - * - * Specifies how the privilege level of the master is determined. - * - * Values: - * - 0 - Accesses from this master are forced to user-mode. - * - 1 - Accesses from this master are not forced to user-mode. - */ -/*@{*/ -#define BP_AIPS_MPRA_MPL2 (20U) /*!< Bit position for AIPS_MPRA_MPL2. */ -#define BM_AIPS_MPRA_MPL2 (0x00100000U) /*!< Bit mask for AIPS_MPRA_MPL2. */ -#define BS_AIPS_MPRA_MPL2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL2. */ - -/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */ -#define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2)) - -/*! @brief Format value for bitfield AIPS_MPRA_MPL2. */ -#define BF_AIPS_MPRA_MPL2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL2) & BM_AIPS_MPRA_MPL2) - -/*! @brief Set the MPL2 field to a new value. */ -#define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTW2[21] (RW) - * - * Determines whether the master is trusted for write accesses. - * - * Values: - * - 0 - This master is not trusted for write accesses. - * - 1 - This master is trusted for write accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTW2 (21U) /*!< Bit position for AIPS_MPRA_MTW2. */ -#define BM_AIPS_MPRA_MTW2 (0x00200000U) /*!< Bit mask for AIPS_MPRA_MTW2. */ -#define BS_AIPS_MPRA_MTW2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW2. */ - -/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */ -#define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTW2. */ -#define BF_AIPS_MPRA_MTW2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW2) & BM_AIPS_MPRA_MTW2) - -/*! @brief Set the MTW2 field to a new value. */ -#define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTR2[22] (RW) - * - * Determines whether the master is trusted for read accesses. - * - * Values: - * - 0 - This master is not trusted for read accesses. - * - 1 - This master is trusted for read accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTR2 (22U) /*!< Bit position for AIPS_MPRA_MTR2. */ -#define BM_AIPS_MPRA_MTR2 (0x00400000U) /*!< Bit mask for AIPS_MPRA_MTR2. */ -#define BS_AIPS_MPRA_MTR2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR2. */ - -/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */ -#define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTR2. */ -#define BF_AIPS_MPRA_MTR2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR2) & BM_AIPS_MPRA_MTR2) - -/*! @brief Set the MTR2 field to a new value. */ -#define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MPL1[24] (RW) - * - * Specifies how the privilege level of the master is determined. - * - * Values: - * - 0 - Accesses from this master are forced to user-mode. - * - 1 - Accesses from this master are not forced to user-mode. - */ -/*@{*/ -#define BP_AIPS_MPRA_MPL1 (24U) /*!< Bit position for AIPS_MPRA_MPL1. */ -#define BM_AIPS_MPRA_MPL1 (0x01000000U) /*!< Bit mask for AIPS_MPRA_MPL1. */ -#define BS_AIPS_MPRA_MPL1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL1. */ - -/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */ -#define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1)) - -/*! @brief Format value for bitfield AIPS_MPRA_MPL1. */ -#define BF_AIPS_MPRA_MPL1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL1) & BM_AIPS_MPRA_MPL1) - -/*! @brief Set the MPL1 field to a new value. */ -#define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTW1[25] (RW) - * - * Determines whether the master is trusted for write accesses. - * - * Values: - * - 0 - This master is not trusted for write accesses. - * - 1 - This master is trusted for write accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTW1 (25U) /*!< Bit position for AIPS_MPRA_MTW1. */ -#define BM_AIPS_MPRA_MTW1 (0x02000000U) /*!< Bit mask for AIPS_MPRA_MTW1. */ -#define BS_AIPS_MPRA_MTW1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW1. */ - -/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */ -#define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTW1. */ -#define BF_AIPS_MPRA_MTW1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW1) & BM_AIPS_MPRA_MTW1) - -/*! @brief Set the MTW1 field to a new value. */ -#define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTR1[26] (RW) - * - * Determines whether the master is trusted for read accesses. - * - * Values: - * - 0 - This master is not trusted for read accesses. - * - 1 - This master is trusted for read accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTR1 (26U) /*!< Bit position for AIPS_MPRA_MTR1. */ -#define BM_AIPS_MPRA_MTR1 (0x04000000U) /*!< Bit mask for AIPS_MPRA_MTR1. */ -#define BS_AIPS_MPRA_MTR1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR1. */ - -/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */ -#define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTR1. */ -#define BF_AIPS_MPRA_MTR1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR1) & BM_AIPS_MPRA_MTR1) - -/*! @brief Set the MTR1 field to a new value. */ -#define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MPL0[28] (RW) - * - * Specifies how the privilege level of the master is determined. - * - * Values: - * - 0 - Accesses from this master are forced to user-mode. - * - 1 - Accesses from this master are not forced to user-mode. - */ -/*@{*/ -#define BP_AIPS_MPRA_MPL0 (28U) /*!< Bit position for AIPS_MPRA_MPL0. */ -#define BM_AIPS_MPRA_MPL0 (0x10000000U) /*!< Bit mask for AIPS_MPRA_MPL0. */ -#define BS_AIPS_MPRA_MPL0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL0. */ - -/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */ -#define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0)) - -/*! @brief Format value for bitfield AIPS_MPRA_MPL0. */ -#define BF_AIPS_MPRA_MPL0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL0) & BM_AIPS_MPRA_MPL0) - -/*! @brief Set the MPL0 field to a new value. */ -#define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTW0[29] (RW) - * - * Determines whether the master is trusted for write accesses. - * - * Values: - * - 0 - This master is not trusted for write accesses. - * - 1 - This master is trusted for write accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTW0 (29U) /*!< Bit position for AIPS_MPRA_MTW0. */ -#define BM_AIPS_MPRA_MTW0 (0x20000000U) /*!< Bit mask for AIPS_MPRA_MTW0. */ -#define BS_AIPS_MPRA_MTW0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW0. */ - -/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */ -#define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTW0. */ -#define BF_AIPS_MPRA_MTW0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW0) & BM_AIPS_MPRA_MTW0) - -/*! @brief Set the MTW0 field to a new value. */ -#define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_MPRA, field MTR0[30] (RW) - * - * Determines whether the master is trusted for read accesses. - * - * Values: - * - 0 - This master is not trusted for read accesses. - * - 1 - This master is trusted for read accesses. - */ -/*@{*/ -#define BP_AIPS_MPRA_MTR0 (30U) /*!< Bit position for AIPS_MPRA_MTR0. */ -#define BM_AIPS_MPRA_MTR0 (0x40000000U) /*!< Bit mask for AIPS_MPRA_MTR0. */ -#define BS_AIPS_MPRA_MTR0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR0. */ - -/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */ -#define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0)) - -/*! @brief Format value for bitfield AIPS_MPRA_MTR0. */ -#define BF_AIPS_MPRA_MTR0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR0) & BM_AIPS_MPRA_MTR0) - -/*! @brief Set the MTR0 field to a new value. */ -#define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRA - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW) - * - * Reset value: 0x50004000U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral slot's PACR field - * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 - * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC - * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 - * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 - * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 - * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 - * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 - * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 - * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 - * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 - * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 - * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 - * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR - * A-D, which control peripheral slots 0-31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacra -{ - uint32_t U; - struct _hw_aips_pacra_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacra_t; - -/*! - * @name Constants and macros for entire AIPS_PACRA register - */ -/*@{*/ -#define HW_AIPS_PACRA_ADDR(x) ((x) + 0x20U) - -#define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x)) -#define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U) -#define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v)) -#define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v))) -#define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v))) -#define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRA bitfields - */ - -/*! - * @name Register AIPS_PACRA, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP7 (0U) /*!< Bit position for AIPS_PACRA_TP7. */ -#define BM_AIPS_PACRA_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRA_TP7. */ -#define BS_AIPS_PACRA_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP7. */ - -/*! @brief Read current value of the AIPS_PACRA_TP7 field. */ -#define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP7. */ -#define BF_AIPS_PACRA_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP7) & BM_AIPS_PACRA_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP7 (1U) /*!< Bit position for AIPS_PACRA_WP7. */ -#define BM_AIPS_PACRA_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRA_WP7. */ -#define BS_AIPS_PACRA_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP7. */ - -/*! @brief Read current value of the AIPS_PACRA_WP7 field. */ -#define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP7. */ -#define BF_AIPS_PACRA_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP7) & BM_AIPS_PACRA_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP7 (2U) /*!< Bit position for AIPS_PACRA_SP7. */ -#define BM_AIPS_PACRA_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRA_SP7. */ -#define BS_AIPS_PACRA_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP7. */ - -/*! @brief Read current value of the AIPS_PACRA_SP7 field. */ -#define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP7. */ -#define BF_AIPS_PACRA_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP7) & BM_AIPS_PACRA_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP6 (4U) /*!< Bit position for AIPS_PACRA_TP6. */ -#define BM_AIPS_PACRA_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRA_TP6. */ -#define BS_AIPS_PACRA_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP6. */ - -/*! @brief Read current value of the AIPS_PACRA_TP6 field. */ -#define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP6. */ -#define BF_AIPS_PACRA_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP6) & BM_AIPS_PACRA_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP6 (5U) /*!< Bit position for AIPS_PACRA_WP6. */ -#define BM_AIPS_PACRA_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRA_WP6. */ -#define BS_AIPS_PACRA_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP6. */ - -/*! @brief Read current value of the AIPS_PACRA_WP6 field. */ -#define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP6. */ -#define BF_AIPS_PACRA_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP6) & BM_AIPS_PACRA_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP6 (6U) /*!< Bit position for AIPS_PACRA_SP6. */ -#define BM_AIPS_PACRA_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRA_SP6. */ -#define BS_AIPS_PACRA_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP6. */ - -/*! @brief Read current value of the AIPS_PACRA_SP6 field. */ -#define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP6. */ -#define BF_AIPS_PACRA_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP6) & BM_AIPS_PACRA_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP5 (8U) /*!< Bit position for AIPS_PACRA_TP5. */ -#define BM_AIPS_PACRA_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRA_TP5. */ -#define BS_AIPS_PACRA_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP5. */ - -/*! @brief Read current value of the AIPS_PACRA_TP5 field. */ -#define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP5. */ -#define BF_AIPS_PACRA_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP5) & BM_AIPS_PACRA_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP5 (9U) /*!< Bit position for AIPS_PACRA_WP5. */ -#define BM_AIPS_PACRA_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRA_WP5. */ -#define BS_AIPS_PACRA_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP5. */ - -/*! @brief Read current value of the AIPS_PACRA_WP5 field. */ -#define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP5. */ -#define BF_AIPS_PACRA_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP5) & BM_AIPS_PACRA_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP5 (10U) /*!< Bit position for AIPS_PACRA_SP5. */ -#define BM_AIPS_PACRA_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRA_SP5. */ -#define BS_AIPS_PACRA_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP5. */ - -/*! @brief Read current value of the AIPS_PACRA_SP5 field. */ -#define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP5. */ -#define BF_AIPS_PACRA_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP5) & BM_AIPS_PACRA_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP4 (12U) /*!< Bit position for AIPS_PACRA_TP4. */ -#define BM_AIPS_PACRA_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRA_TP4. */ -#define BS_AIPS_PACRA_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP4. */ - -/*! @brief Read current value of the AIPS_PACRA_TP4 field. */ -#define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP4. */ -#define BF_AIPS_PACRA_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP4) & BM_AIPS_PACRA_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP4 (13U) /*!< Bit position for AIPS_PACRA_WP4. */ -#define BM_AIPS_PACRA_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRA_WP4. */ -#define BS_AIPS_PACRA_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP4. */ - -/*! @brief Read current value of the AIPS_PACRA_WP4 field. */ -#define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP4. */ -#define BF_AIPS_PACRA_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP4) & BM_AIPS_PACRA_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP4 (14U) /*!< Bit position for AIPS_PACRA_SP4. */ -#define BM_AIPS_PACRA_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRA_SP4. */ -#define BS_AIPS_PACRA_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP4. */ - -/*! @brief Read current value of the AIPS_PACRA_SP4 field. */ -#define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP4. */ -#define BF_AIPS_PACRA_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP4) & BM_AIPS_PACRA_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP3 (16U) /*!< Bit position for AIPS_PACRA_TP3. */ -#define BM_AIPS_PACRA_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRA_TP3. */ -#define BS_AIPS_PACRA_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP3. */ - -/*! @brief Read current value of the AIPS_PACRA_TP3 field. */ -#define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP3. */ -#define BF_AIPS_PACRA_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP3) & BM_AIPS_PACRA_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP3 (17U) /*!< Bit position for AIPS_PACRA_WP3. */ -#define BM_AIPS_PACRA_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRA_WP3. */ -#define BS_AIPS_PACRA_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP3. */ - -/*! @brief Read current value of the AIPS_PACRA_WP3 field. */ -#define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP3. */ -#define BF_AIPS_PACRA_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP3) & BM_AIPS_PACRA_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP3 (18U) /*!< Bit position for AIPS_PACRA_SP3. */ -#define BM_AIPS_PACRA_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRA_SP3. */ -#define BS_AIPS_PACRA_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP3. */ - -/*! @brief Read current value of the AIPS_PACRA_SP3 field. */ -#define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP3. */ -#define BF_AIPS_PACRA_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP3) & BM_AIPS_PACRA_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP2 (20U) /*!< Bit position for AIPS_PACRA_TP2. */ -#define BM_AIPS_PACRA_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRA_TP2. */ -#define BS_AIPS_PACRA_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP2. */ - -/*! @brief Read current value of the AIPS_PACRA_TP2 field. */ -#define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP2. */ -#define BF_AIPS_PACRA_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP2) & BM_AIPS_PACRA_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP2 (21U) /*!< Bit position for AIPS_PACRA_WP2. */ -#define BM_AIPS_PACRA_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRA_WP2. */ -#define BS_AIPS_PACRA_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP2. */ - -/*! @brief Read current value of the AIPS_PACRA_WP2 field. */ -#define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP2. */ -#define BF_AIPS_PACRA_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP2) & BM_AIPS_PACRA_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP2 (22U) /*!< Bit position for AIPS_PACRA_SP2. */ -#define BM_AIPS_PACRA_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRA_SP2. */ -#define BS_AIPS_PACRA_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP2. */ - -/*! @brief Read current value of the AIPS_PACRA_SP2 field. */ -#define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP2. */ -#define BF_AIPS_PACRA_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP2) & BM_AIPS_PACRA_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP1 (24U) /*!< Bit position for AIPS_PACRA_TP1. */ -#define BM_AIPS_PACRA_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRA_TP1. */ -#define BS_AIPS_PACRA_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP1. */ - -/*! @brief Read current value of the AIPS_PACRA_TP1 field. */ -#define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP1. */ -#define BF_AIPS_PACRA_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP1) & BM_AIPS_PACRA_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP1 (25U) /*!< Bit position for AIPS_PACRA_WP1. */ -#define BM_AIPS_PACRA_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRA_WP1. */ -#define BS_AIPS_PACRA_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP1. */ - -/*! @brief Read current value of the AIPS_PACRA_WP1 field. */ -#define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP1. */ -#define BF_AIPS_PACRA_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP1) & BM_AIPS_PACRA_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP1 (26U) /*!< Bit position for AIPS_PACRA_SP1. */ -#define BM_AIPS_PACRA_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRA_SP1. */ -#define BS_AIPS_PACRA_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP1. */ - -/*! @brief Read current value of the AIPS_PACRA_SP1 field. */ -#define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP1. */ -#define BF_AIPS_PACRA_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP1) & BM_AIPS_PACRA_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRA_TP0 (28U) /*!< Bit position for AIPS_PACRA_TP0. */ -#define BM_AIPS_PACRA_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRA_TP0. */ -#define BS_AIPS_PACRA_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP0. */ - -/*! @brief Read current value of the AIPS_PACRA_TP0 field. */ -#define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRA_TP0. */ -#define BF_AIPS_PACRA_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP0) & BM_AIPS_PACRA_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRA_WP0 (29U) /*!< Bit position for AIPS_PACRA_WP0. */ -#define BM_AIPS_PACRA_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRA_WP0. */ -#define BS_AIPS_PACRA_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP0. */ - -/*! @brief Read current value of the AIPS_PACRA_WP0 field. */ -#define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRA_WP0. */ -#define BF_AIPS_PACRA_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP0) & BM_AIPS_PACRA_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRA, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRA_SP0 (30U) /*!< Bit position for AIPS_PACRA_SP0. */ -#define BM_AIPS_PACRA_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRA_SP0. */ -#define BS_AIPS_PACRA_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP0. */ - -/*! @brief Read current value of the AIPS_PACRA_SP0 field. */ -#define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRA_SP0. */ -#define BF_AIPS_PACRA_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP0) & BM_AIPS_PACRA_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRB - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW) - * - * Reset value: 0x44004400U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral slot's PACR field - * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 - * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC - * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 - * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 - * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 - * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 - * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 - * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 - * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 - * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 - * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 - * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 - * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR - * A-D, which control peripheral slots 0-31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacrb -{ - uint32_t U; - struct _hw_aips_pacrb_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrb_t; - -/*! - * @name Constants and macros for entire AIPS_PACRB register - */ -/*@{*/ -#define HW_AIPS_PACRB_ADDR(x) ((x) + 0x24U) - -#define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x)) -#define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U) -#define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v)) -#define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v))) -#define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v))) -#define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRB bitfields - */ - -/*! - * @name Register AIPS_PACRB, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP7 (0U) /*!< Bit position for AIPS_PACRB_TP7. */ -#define BM_AIPS_PACRB_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRB_TP7. */ -#define BS_AIPS_PACRB_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP7. */ - -/*! @brief Read current value of the AIPS_PACRB_TP7 field. */ -#define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP7. */ -#define BF_AIPS_PACRB_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP7) & BM_AIPS_PACRB_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP7 (1U) /*!< Bit position for AIPS_PACRB_WP7. */ -#define BM_AIPS_PACRB_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRB_WP7. */ -#define BS_AIPS_PACRB_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP7. */ - -/*! @brief Read current value of the AIPS_PACRB_WP7 field. */ -#define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP7. */ -#define BF_AIPS_PACRB_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP7) & BM_AIPS_PACRB_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP7 (2U) /*!< Bit position for AIPS_PACRB_SP7. */ -#define BM_AIPS_PACRB_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRB_SP7. */ -#define BS_AIPS_PACRB_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP7. */ - -/*! @brief Read current value of the AIPS_PACRB_SP7 field. */ -#define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP7. */ -#define BF_AIPS_PACRB_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP7) & BM_AIPS_PACRB_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP6 (4U) /*!< Bit position for AIPS_PACRB_TP6. */ -#define BM_AIPS_PACRB_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRB_TP6. */ -#define BS_AIPS_PACRB_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP6. */ - -/*! @brief Read current value of the AIPS_PACRB_TP6 field. */ -#define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP6. */ -#define BF_AIPS_PACRB_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP6) & BM_AIPS_PACRB_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP6 (5U) /*!< Bit position for AIPS_PACRB_WP6. */ -#define BM_AIPS_PACRB_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRB_WP6. */ -#define BS_AIPS_PACRB_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP6. */ - -/*! @brief Read current value of the AIPS_PACRB_WP6 field. */ -#define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP6. */ -#define BF_AIPS_PACRB_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP6) & BM_AIPS_PACRB_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP6 (6U) /*!< Bit position for AIPS_PACRB_SP6. */ -#define BM_AIPS_PACRB_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRB_SP6. */ -#define BS_AIPS_PACRB_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP6. */ - -/*! @brief Read current value of the AIPS_PACRB_SP6 field. */ -#define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP6. */ -#define BF_AIPS_PACRB_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP6) & BM_AIPS_PACRB_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP5 (8U) /*!< Bit position for AIPS_PACRB_TP5. */ -#define BM_AIPS_PACRB_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRB_TP5. */ -#define BS_AIPS_PACRB_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP5. */ - -/*! @brief Read current value of the AIPS_PACRB_TP5 field. */ -#define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP5. */ -#define BF_AIPS_PACRB_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP5) & BM_AIPS_PACRB_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP5 (9U) /*!< Bit position for AIPS_PACRB_WP5. */ -#define BM_AIPS_PACRB_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRB_WP5. */ -#define BS_AIPS_PACRB_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP5. */ - -/*! @brief Read current value of the AIPS_PACRB_WP5 field. */ -#define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP5. */ -#define BF_AIPS_PACRB_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP5) & BM_AIPS_PACRB_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP5 (10U) /*!< Bit position for AIPS_PACRB_SP5. */ -#define BM_AIPS_PACRB_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRB_SP5. */ -#define BS_AIPS_PACRB_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP5. */ - -/*! @brief Read current value of the AIPS_PACRB_SP5 field. */ -#define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP5. */ -#define BF_AIPS_PACRB_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP5) & BM_AIPS_PACRB_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP4 (12U) /*!< Bit position for AIPS_PACRB_TP4. */ -#define BM_AIPS_PACRB_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRB_TP4. */ -#define BS_AIPS_PACRB_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP4. */ - -/*! @brief Read current value of the AIPS_PACRB_TP4 field. */ -#define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP4. */ -#define BF_AIPS_PACRB_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP4) & BM_AIPS_PACRB_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP4 (13U) /*!< Bit position for AIPS_PACRB_WP4. */ -#define BM_AIPS_PACRB_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRB_WP4. */ -#define BS_AIPS_PACRB_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP4. */ - -/*! @brief Read current value of the AIPS_PACRB_WP4 field. */ -#define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP4. */ -#define BF_AIPS_PACRB_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP4) & BM_AIPS_PACRB_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP4 (14U) /*!< Bit position for AIPS_PACRB_SP4. */ -#define BM_AIPS_PACRB_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRB_SP4. */ -#define BS_AIPS_PACRB_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP4. */ - -/*! @brief Read current value of the AIPS_PACRB_SP4 field. */ -#define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP4. */ -#define BF_AIPS_PACRB_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP4) & BM_AIPS_PACRB_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP3 (16U) /*!< Bit position for AIPS_PACRB_TP3. */ -#define BM_AIPS_PACRB_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRB_TP3. */ -#define BS_AIPS_PACRB_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP3. */ - -/*! @brief Read current value of the AIPS_PACRB_TP3 field. */ -#define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP3. */ -#define BF_AIPS_PACRB_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP3) & BM_AIPS_PACRB_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP3 (17U) /*!< Bit position for AIPS_PACRB_WP3. */ -#define BM_AIPS_PACRB_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRB_WP3. */ -#define BS_AIPS_PACRB_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP3. */ - -/*! @brief Read current value of the AIPS_PACRB_WP3 field. */ -#define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP3. */ -#define BF_AIPS_PACRB_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP3) & BM_AIPS_PACRB_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP3 (18U) /*!< Bit position for AIPS_PACRB_SP3. */ -#define BM_AIPS_PACRB_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRB_SP3. */ -#define BS_AIPS_PACRB_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP3. */ - -/*! @brief Read current value of the AIPS_PACRB_SP3 field. */ -#define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP3. */ -#define BF_AIPS_PACRB_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP3) & BM_AIPS_PACRB_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP2 (20U) /*!< Bit position for AIPS_PACRB_TP2. */ -#define BM_AIPS_PACRB_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRB_TP2. */ -#define BS_AIPS_PACRB_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP2. */ - -/*! @brief Read current value of the AIPS_PACRB_TP2 field. */ -#define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP2. */ -#define BF_AIPS_PACRB_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP2) & BM_AIPS_PACRB_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP2 (21U) /*!< Bit position for AIPS_PACRB_WP2. */ -#define BM_AIPS_PACRB_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRB_WP2. */ -#define BS_AIPS_PACRB_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP2. */ - -/*! @brief Read current value of the AIPS_PACRB_WP2 field. */ -#define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP2. */ -#define BF_AIPS_PACRB_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP2) & BM_AIPS_PACRB_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP2 (22U) /*!< Bit position for AIPS_PACRB_SP2. */ -#define BM_AIPS_PACRB_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRB_SP2. */ -#define BS_AIPS_PACRB_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP2. */ - -/*! @brief Read current value of the AIPS_PACRB_SP2 field. */ -#define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP2. */ -#define BF_AIPS_PACRB_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP2) & BM_AIPS_PACRB_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP1 (24U) /*!< Bit position for AIPS_PACRB_TP1. */ -#define BM_AIPS_PACRB_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRB_TP1. */ -#define BS_AIPS_PACRB_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP1. */ - -/*! @brief Read current value of the AIPS_PACRB_TP1 field. */ -#define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP1. */ -#define BF_AIPS_PACRB_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP1) & BM_AIPS_PACRB_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP1 (25U) /*!< Bit position for AIPS_PACRB_WP1. */ -#define BM_AIPS_PACRB_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRB_WP1. */ -#define BS_AIPS_PACRB_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP1. */ - -/*! @brief Read current value of the AIPS_PACRB_WP1 field. */ -#define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP1. */ -#define BF_AIPS_PACRB_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP1) & BM_AIPS_PACRB_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP1 (26U) /*!< Bit position for AIPS_PACRB_SP1. */ -#define BM_AIPS_PACRB_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRB_SP1. */ -#define BS_AIPS_PACRB_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP1. */ - -/*! @brief Read current value of the AIPS_PACRB_SP1 field. */ -#define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP1. */ -#define BF_AIPS_PACRB_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP1) & BM_AIPS_PACRB_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRB_TP0 (28U) /*!< Bit position for AIPS_PACRB_TP0. */ -#define BM_AIPS_PACRB_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRB_TP0. */ -#define BS_AIPS_PACRB_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP0. */ - -/*! @brief Read current value of the AIPS_PACRB_TP0 field. */ -#define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRB_TP0. */ -#define BF_AIPS_PACRB_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP0) & BM_AIPS_PACRB_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRB_WP0 (29U) /*!< Bit position for AIPS_PACRB_WP0. */ -#define BM_AIPS_PACRB_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRB_WP0. */ -#define BS_AIPS_PACRB_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP0. */ - -/*! @brief Read current value of the AIPS_PACRB_WP0 field. */ -#define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRB_WP0. */ -#define BF_AIPS_PACRB_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP0) & BM_AIPS_PACRB_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRB, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRB_SP0 (30U) /*!< Bit position for AIPS_PACRB_SP0. */ -#define BM_AIPS_PACRB_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRB_SP0. */ -#define BS_AIPS_PACRB_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP0. */ - -/*! @brief Read current value of the AIPS_PACRB_SP0 field. */ -#define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRB_SP0. */ -#define BF_AIPS_PACRB_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP0) & BM_AIPS_PACRB_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRC - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000000U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral slot's PACR field - * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 - * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC - * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 - * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 - * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 - * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 - * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 - * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 - * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 - * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 - * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 - * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 - * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR - * A-D, which control peripheral slots 0-31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacrc -{ - uint32_t U; - struct _hw_aips_pacrc_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrc_t; - -/*! - * @name Constants and macros for entire AIPS_PACRC register - */ -/*@{*/ -#define HW_AIPS_PACRC_ADDR(x) ((x) + 0x28U) - -#define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x)) -#define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U) -#define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v)) -#define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v))) -#define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v))) -#define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRC bitfields - */ - -/*! - * @name Register AIPS_PACRC, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP7 (0U) /*!< Bit position for AIPS_PACRC_TP7. */ -#define BM_AIPS_PACRC_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRC_TP7. */ -#define BS_AIPS_PACRC_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP7. */ - -/*! @brief Read current value of the AIPS_PACRC_TP7 field. */ -#define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP7. */ -#define BF_AIPS_PACRC_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP7) & BM_AIPS_PACRC_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP7 (1U) /*!< Bit position for AIPS_PACRC_WP7. */ -#define BM_AIPS_PACRC_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRC_WP7. */ -#define BS_AIPS_PACRC_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP7. */ - -/*! @brief Read current value of the AIPS_PACRC_WP7 field. */ -#define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP7. */ -#define BF_AIPS_PACRC_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP7) & BM_AIPS_PACRC_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP7 (2U) /*!< Bit position for AIPS_PACRC_SP7. */ -#define BM_AIPS_PACRC_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRC_SP7. */ -#define BS_AIPS_PACRC_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP7. */ - -/*! @brief Read current value of the AIPS_PACRC_SP7 field. */ -#define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP7. */ -#define BF_AIPS_PACRC_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP7) & BM_AIPS_PACRC_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP6 (4U) /*!< Bit position for AIPS_PACRC_TP6. */ -#define BM_AIPS_PACRC_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRC_TP6. */ -#define BS_AIPS_PACRC_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP6. */ - -/*! @brief Read current value of the AIPS_PACRC_TP6 field. */ -#define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP6. */ -#define BF_AIPS_PACRC_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP6) & BM_AIPS_PACRC_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP6 (5U) /*!< Bit position for AIPS_PACRC_WP6. */ -#define BM_AIPS_PACRC_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRC_WP6. */ -#define BS_AIPS_PACRC_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP6. */ - -/*! @brief Read current value of the AIPS_PACRC_WP6 field. */ -#define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP6. */ -#define BF_AIPS_PACRC_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP6) & BM_AIPS_PACRC_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP6 (6U) /*!< Bit position for AIPS_PACRC_SP6. */ -#define BM_AIPS_PACRC_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRC_SP6. */ -#define BS_AIPS_PACRC_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP6. */ - -/*! @brief Read current value of the AIPS_PACRC_SP6 field. */ -#define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP6. */ -#define BF_AIPS_PACRC_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP6) & BM_AIPS_PACRC_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP5 (8U) /*!< Bit position for AIPS_PACRC_TP5. */ -#define BM_AIPS_PACRC_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRC_TP5. */ -#define BS_AIPS_PACRC_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP5. */ - -/*! @brief Read current value of the AIPS_PACRC_TP5 field. */ -#define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP5. */ -#define BF_AIPS_PACRC_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP5) & BM_AIPS_PACRC_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP5 (9U) /*!< Bit position for AIPS_PACRC_WP5. */ -#define BM_AIPS_PACRC_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRC_WP5. */ -#define BS_AIPS_PACRC_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP5. */ - -/*! @brief Read current value of the AIPS_PACRC_WP5 field. */ -#define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP5. */ -#define BF_AIPS_PACRC_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP5) & BM_AIPS_PACRC_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP5 (10U) /*!< Bit position for AIPS_PACRC_SP5. */ -#define BM_AIPS_PACRC_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRC_SP5. */ -#define BS_AIPS_PACRC_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP5. */ - -/*! @brief Read current value of the AIPS_PACRC_SP5 field. */ -#define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP5. */ -#define BF_AIPS_PACRC_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP5) & BM_AIPS_PACRC_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP4 (12U) /*!< Bit position for AIPS_PACRC_TP4. */ -#define BM_AIPS_PACRC_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRC_TP4. */ -#define BS_AIPS_PACRC_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP4. */ - -/*! @brief Read current value of the AIPS_PACRC_TP4 field. */ -#define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP4. */ -#define BF_AIPS_PACRC_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP4) & BM_AIPS_PACRC_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP4 (13U) /*!< Bit position for AIPS_PACRC_WP4. */ -#define BM_AIPS_PACRC_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRC_WP4. */ -#define BS_AIPS_PACRC_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP4. */ - -/*! @brief Read current value of the AIPS_PACRC_WP4 field. */ -#define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP4. */ -#define BF_AIPS_PACRC_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP4) & BM_AIPS_PACRC_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP4 (14U) /*!< Bit position for AIPS_PACRC_SP4. */ -#define BM_AIPS_PACRC_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRC_SP4. */ -#define BS_AIPS_PACRC_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP4. */ - -/*! @brief Read current value of the AIPS_PACRC_SP4 field. */ -#define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP4. */ -#define BF_AIPS_PACRC_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP4) & BM_AIPS_PACRC_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP3 (16U) /*!< Bit position for AIPS_PACRC_TP3. */ -#define BM_AIPS_PACRC_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRC_TP3. */ -#define BS_AIPS_PACRC_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP3. */ - -/*! @brief Read current value of the AIPS_PACRC_TP3 field. */ -#define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP3. */ -#define BF_AIPS_PACRC_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP3) & BM_AIPS_PACRC_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP3 (17U) /*!< Bit position for AIPS_PACRC_WP3. */ -#define BM_AIPS_PACRC_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRC_WP3. */ -#define BS_AIPS_PACRC_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP3. */ - -/*! @brief Read current value of the AIPS_PACRC_WP3 field. */ -#define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP3. */ -#define BF_AIPS_PACRC_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP3) & BM_AIPS_PACRC_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP3 (18U) /*!< Bit position for AIPS_PACRC_SP3. */ -#define BM_AIPS_PACRC_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRC_SP3. */ -#define BS_AIPS_PACRC_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP3. */ - -/*! @brief Read current value of the AIPS_PACRC_SP3 field. */ -#define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP3. */ -#define BF_AIPS_PACRC_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP3) & BM_AIPS_PACRC_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP2 (20U) /*!< Bit position for AIPS_PACRC_TP2. */ -#define BM_AIPS_PACRC_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRC_TP2. */ -#define BS_AIPS_PACRC_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP2. */ - -/*! @brief Read current value of the AIPS_PACRC_TP2 field. */ -#define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP2. */ -#define BF_AIPS_PACRC_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP2) & BM_AIPS_PACRC_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP2 (21U) /*!< Bit position for AIPS_PACRC_WP2. */ -#define BM_AIPS_PACRC_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRC_WP2. */ -#define BS_AIPS_PACRC_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP2. */ - -/*! @brief Read current value of the AIPS_PACRC_WP2 field. */ -#define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP2. */ -#define BF_AIPS_PACRC_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP2) & BM_AIPS_PACRC_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP2 (22U) /*!< Bit position for AIPS_PACRC_SP2. */ -#define BM_AIPS_PACRC_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRC_SP2. */ -#define BS_AIPS_PACRC_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP2. */ - -/*! @brief Read current value of the AIPS_PACRC_SP2 field. */ -#define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP2. */ -#define BF_AIPS_PACRC_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP2) & BM_AIPS_PACRC_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP1 (24U) /*!< Bit position for AIPS_PACRC_TP1. */ -#define BM_AIPS_PACRC_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRC_TP1. */ -#define BS_AIPS_PACRC_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP1. */ - -/*! @brief Read current value of the AIPS_PACRC_TP1 field. */ -#define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP1. */ -#define BF_AIPS_PACRC_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP1) & BM_AIPS_PACRC_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP1 (25U) /*!< Bit position for AIPS_PACRC_WP1. */ -#define BM_AIPS_PACRC_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRC_WP1. */ -#define BS_AIPS_PACRC_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP1. */ - -/*! @brief Read current value of the AIPS_PACRC_WP1 field. */ -#define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP1. */ -#define BF_AIPS_PACRC_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP1) & BM_AIPS_PACRC_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP1 (26U) /*!< Bit position for AIPS_PACRC_SP1. */ -#define BM_AIPS_PACRC_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRC_SP1. */ -#define BS_AIPS_PACRC_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP1. */ - -/*! @brief Read current value of the AIPS_PACRC_SP1 field. */ -#define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP1. */ -#define BF_AIPS_PACRC_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP1) & BM_AIPS_PACRC_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRC_TP0 (28U) /*!< Bit position for AIPS_PACRC_TP0. */ -#define BM_AIPS_PACRC_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRC_TP0. */ -#define BS_AIPS_PACRC_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP0. */ - -/*! @brief Read current value of the AIPS_PACRC_TP0 field. */ -#define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRC_TP0. */ -#define BF_AIPS_PACRC_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP0) & BM_AIPS_PACRC_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRC_WP0 (29U) /*!< Bit position for AIPS_PACRC_WP0. */ -#define BM_AIPS_PACRC_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRC_WP0. */ -#define BS_AIPS_PACRC_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP0. */ - -/*! @brief Read current value of the AIPS_PACRC_WP0 field. */ -#define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRC_WP0. */ -#define BF_AIPS_PACRC_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP0) & BM_AIPS_PACRC_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRC, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRC_SP0 (30U) /*!< Bit position for AIPS_PACRC_SP0. */ -#define BM_AIPS_PACRC_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRC_SP0. */ -#define BS_AIPS_PACRC_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP0. */ - -/*! @brief Read current value of the AIPS_PACRC_SP0 field. */ -#define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRC_SP0. */ -#define BF_AIPS_PACRC_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP0) & BM_AIPS_PACRC_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRD - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW) - * - * Reset value: 0x00000004U - * - * Each PACR register consists of eight 4-bit PACR fields. Each PACR field - * defines the access levels for a particular peripheral. The mapping between a - * peripheral and its PACR field is shown in the table below. The peripheral assignment - * to each PACR is defined by the memory map slot that the peripheral is - * assigned to. See this chip's memory map for the assignment of a particular - * peripheral. The following table shows the location of each peripheral slot's PACR field - * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] - * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 - * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC - * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 - * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 - * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 - * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 - * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH - * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 - * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 - * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 - * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 - * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 - * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 - * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 - * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 - * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR - * A-D, which control peripheral slots 0-31, are shown below. The following - * section, PACRPeripheral Access Control Register , shows the register field - * descriptions for PACR E-P. All PACR registers are identical. They are divided into two - * sections because they occupy two non-contiguous address spaces. - */ -typedef union _hw_aips_pacrd -{ - uint32_t U; - struct _hw_aips_pacrd_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrd_t; - -/*! - * @name Constants and macros for entire AIPS_PACRD register - */ -/*@{*/ -#define HW_AIPS_PACRD_ADDR(x) ((x) + 0x2CU) - -#define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x)) -#define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U) -#define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v)) -#define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v))) -#define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v))) -#define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRD bitfields - */ - -/*! - * @name Register AIPS_PACRD, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP7 (0U) /*!< Bit position for AIPS_PACRD_TP7. */ -#define BM_AIPS_PACRD_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRD_TP7. */ -#define BS_AIPS_PACRD_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP7. */ - -/*! @brief Read current value of the AIPS_PACRD_TP7 field. */ -#define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP7. */ -#define BF_AIPS_PACRD_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP7) & BM_AIPS_PACRD_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP7 (1U) /*!< Bit position for AIPS_PACRD_WP7. */ -#define BM_AIPS_PACRD_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRD_WP7. */ -#define BS_AIPS_PACRD_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP7. */ - -/*! @brief Read current value of the AIPS_PACRD_WP7 field. */ -#define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP7. */ -#define BF_AIPS_PACRD_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP7) & BM_AIPS_PACRD_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP7 (2U) /*!< Bit position for AIPS_PACRD_SP7. */ -#define BM_AIPS_PACRD_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRD_SP7. */ -#define BS_AIPS_PACRD_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP7. */ - -/*! @brief Read current value of the AIPS_PACRD_SP7 field. */ -#define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP7. */ -#define BF_AIPS_PACRD_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP7) & BM_AIPS_PACRD_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP6 (4U) /*!< Bit position for AIPS_PACRD_TP6. */ -#define BM_AIPS_PACRD_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRD_TP6. */ -#define BS_AIPS_PACRD_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP6. */ - -/*! @brief Read current value of the AIPS_PACRD_TP6 field. */ -#define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP6. */ -#define BF_AIPS_PACRD_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP6) & BM_AIPS_PACRD_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP6 (5U) /*!< Bit position for AIPS_PACRD_WP6. */ -#define BM_AIPS_PACRD_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRD_WP6. */ -#define BS_AIPS_PACRD_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP6. */ - -/*! @brief Read current value of the AIPS_PACRD_WP6 field. */ -#define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP6. */ -#define BF_AIPS_PACRD_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP6) & BM_AIPS_PACRD_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP6 (6U) /*!< Bit position for AIPS_PACRD_SP6. */ -#define BM_AIPS_PACRD_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRD_SP6. */ -#define BS_AIPS_PACRD_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP6. */ - -/*! @brief Read current value of the AIPS_PACRD_SP6 field. */ -#define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP6. */ -#define BF_AIPS_PACRD_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP6) & BM_AIPS_PACRD_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP5 (8U) /*!< Bit position for AIPS_PACRD_TP5. */ -#define BM_AIPS_PACRD_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRD_TP5. */ -#define BS_AIPS_PACRD_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP5. */ - -/*! @brief Read current value of the AIPS_PACRD_TP5 field. */ -#define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP5. */ -#define BF_AIPS_PACRD_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP5) & BM_AIPS_PACRD_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP5 (9U) /*!< Bit position for AIPS_PACRD_WP5. */ -#define BM_AIPS_PACRD_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRD_WP5. */ -#define BS_AIPS_PACRD_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP5. */ - -/*! @brief Read current value of the AIPS_PACRD_WP5 field. */ -#define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP5. */ -#define BF_AIPS_PACRD_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP5) & BM_AIPS_PACRD_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP5 (10U) /*!< Bit position for AIPS_PACRD_SP5. */ -#define BM_AIPS_PACRD_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRD_SP5. */ -#define BS_AIPS_PACRD_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP5. */ - -/*! @brief Read current value of the AIPS_PACRD_SP5 field. */ -#define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP5. */ -#define BF_AIPS_PACRD_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP5) & BM_AIPS_PACRD_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP4 (12U) /*!< Bit position for AIPS_PACRD_TP4. */ -#define BM_AIPS_PACRD_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRD_TP4. */ -#define BS_AIPS_PACRD_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP4. */ - -/*! @brief Read current value of the AIPS_PACRD_TP4 field. */ -#define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP4. */ -#define BF_AIPS_PACRD_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP4) & BM_AIPS_PACRD_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP4 (13U) /*!< Bit position for AIPS_PACRD_WP4. */ -#define BM_AIPS_PACRD_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRD_WP4. */ -#define BS_AIPS_PACRD_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP4. */ - -/*! @brief Read current value of the AIPS_PACRD_WP4 field. */ -#define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP4. */ -#define BF_AIPS_PACRD_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP4) & BM_AIPS_PACRD_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP4 (14U) /*!< Bit position for AIPS_PACRD_SP4. */ -#define BM_AIPS_PACRD_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRD_SP4. */ -#define BS_AIPS_PACRD_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP4. */ - -/*! @brief Read current value of the AIPS_PACRD_SP4 field. */ -#define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP4. */ -#define BF_AIPS_PACRD_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP4) & BM_AIPS_PACRD_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP3 (16U) /*!< Bit position for AIPS_PACRD_TP3. */ -#define BM_AIPS_PACRD_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRD_TP3. */ -#define BS_AIPS_PACRD_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP3. */ - -/*! @brief Read current value of the AIPS_PACRD_TP3 field. */ -#define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP3. */ -#define BF_AIPS_PACRD_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP3) & BM_AIPS_PACRD_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP3 (17U) /*!< Bit position for AIPS_PACRD_WP3. */ -#define BM_AIPS_PACRD_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRD_WP3. */ -#define BS_AIPS_PACRD_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP3. */ - -/*! @brief Read current value of the AIPS_PACRD_WP3 field. */ -#define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP3. */ -#define BF_AIPS_PACRD_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP3) & BM_AIPS_PACRD_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP3 (18U) /*!< Bit position for AIPS_PACRD_SP3. */ -#define BM_AIPS_PACRD_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRD_SP3. */ -#define BS_AIPS_PACRD_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP3. */ - -/*! @brief Read current value of the AIPS_PACRD_SP3 field. */ -#define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP3. */ -#define BF_AIPS_PACRD_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP3) & BM_AIPS_PACRD_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP2 (20U) /*!< Bit position for AIPS_PACRD_TP2. */ -#define BM_AIPS_PACRD_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRD_TP2. */ -#define BS_AIPS_PACRD_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP2. */ - -/*! @brief Read current value of the AIPS_PACRD_TP2 field. */ -#define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP2. */ -#define BF_AIPS_PACRD_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP2) & BM_AIPS_PACRD_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP2 (21U) /*!< Bit position for AIPS_PACRD_WP2. */ -#define BM_AIPS_PACRD_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRD_WP2. */ -#define BS_AIPS_PACRD_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP2. */ - -/*! @brief Read current value of the AIPS_PACRD_WP2 field. */ -#define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP2. */ -#define BF_AIPS_PACRD_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP2) & BM_AIPS_PACRD_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP2 (22U) /*!< Bit position for AIPS_PACRD_SP2. */ -#define BM_AIPS_PACRD_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRD_SP2. */ -#define BS_AIPS_PACRD_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP2. */ - -/*! @brief Read current value of the AIPS_PACRD_SP2 field. */ -#define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP2. */ -#define BF_AIPS_PACRD_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP2) & BM_AIPS_PACRD_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP1 (24U) /*!< Bit position for AIPS_PACRD_TP1. */ -#define BM_AIPS_PACRD_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRD_TP1. */ -#define BS_AIPS_PACRD_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP1. */ - -/*! @brief Read current value of the AIPS_PACRD_TP1 field. */ -#define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP1. */ -#define BF_AIPS_PACRD_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP1) & BM_AIPS_PACRD_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP1 (25U) /*!< Bit position for AIPS_PACRD_WP1. */ -#define BM_AIPS_PACRD_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRD_WP1. */ -#define BS_AIPS_PACRD_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP1. */ - -/*! @brief Read current value of the AIPS_PACRD_WP1 field. */ -#define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP1. */ -#define BF_AIPS_PACRD_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP1) & BM_AIPS_PACRD_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP1 (26U) /*!< Bit position for AIPS_PACRD_SP1. */ -#define BM_AIPS_PACRD_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRD_SP1. */ -#define BS_AIPS_PACRD_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP1. */ - -/*! @brief Read current value of the AIPS_PACRD_SP1 field. */ -#define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP1. */ -#define BF_AIPS_PACRD_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP1) & BM_AIPS_PACRD_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRD_TP0 (28U) /*!< Bit position for AIPS_PACRD_TP0. */ -#define BM_AIPS_PACRD_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRD_TP0. */ -#define BS_AIPS_PACRD_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP0. */ - -/*! @brief Read current value of the AIPS_PACRD_TP0 field. */ -#define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRD_TP0. */ -#define BF_AIPS_PACRD_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP0) & BM_AIPS_PACRD_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRD_WP0 (29U) /*!< Bit position for AIPS_PACRD_WP0. */ -#define BM_AIPS_PACRD_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRD_WP0. */ -#define BS_AIPS_PACRD_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP0. */ - -/*! @brief Read current value of the AIPS_PACRD_WP0 field. */ -#define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRD_WP0. */ -#define BF_AIPS_PACRD_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP0) & BM_AIPS_PACRD_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRD, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRD_SP0 (30U) /*!< Bit position for AIPS_PACRD_SP0. */ -#define BM_AIPS_PACRD_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRD_SP0. */ -#define BS_AIPS_PACRD_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP0. */ - -/*! @brief Read current value of the AIPS_PACRD_SP0 field. */ -#define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRD_SP0. */ -#define BF_AIPS_PACRD_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP0) & BM_AIPS_PACRD_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRE - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacre -{ - uint32_t U; - struct _hw_aips_pacre_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacre_t; - -/*! - * @name Constants and macros for entire AIPS_PACRE register - */ -/*@{*/ -#define HW_AIPS_PACRE_ADDR(x) ((x) + 0x40U) - -#define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x)) -#define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U) -#define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v)) -#define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v))) -#define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v))) -#define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRE bitfields - */ - -/*! - * @name Register AIPS_PACRE, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP7 (0U) /*!< Bit position for AIPS_PACRE_TP7. */ -#define BM_AIPS_PACRE_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRE_TP7. */ -#define BS_AIPS_PACRE_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP7. */ - -/*! @brief Read current value of the AIPS_PACRE_TP7 field. */ -#define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP7. */ -#define BF_AIPS_PACRE_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP7) & BM_AIPS_PACRE_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP7 (1U) /*!< Bit position for AIPS_PACRE_WP7. */ -#define BM_AIPS_PACRE_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRE_WP7. */ -#define BS_AIPS_PACRE_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP7. */ - -/*! @brief Read current value of the AIPS_PACRE_WP7 field. */ -#define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP7. */ -#define BF_AIPS_PACRE_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP7) & BM_AIPS_PACRE_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP7 (2U) /*!< Bit position for AIPS_PACRE_SP7. */ -#define BM_AIPS_PACRE_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRE_SP7. */ -#define BS_AIPS_PACRE_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP7. */ - -/*! @brief Read current value of the AIPS_PACRE_SP7 field. */ -#define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP7. */ -#define BF_AIPS_PACRE_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP7) & BM_AIPS_PACRE_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP6 (4U) /*!< Bit position for AIPS_PACRE_TP6. */ -#define BM_AIPS_PACRE_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRE_TP6. */ -#define BS_AIPS_PACRE_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP6. */ - -/*! @brief Read current value of the AIPS_PACRE_TP6 field. */ -#define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP6. */ -#define BF_AIPS_PACRE_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP6) & BM_AIPS_PACRE_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP6 (5U) /*!< Bit position for AIPS_PACRE_WP6. */ -#define BM_AIPS_PACRE_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRE_WP6. */ -#define BS_AIPS_PACRE_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP6. */ - -/*! @brief Read current value of the AIPS_PACRE_WP6 field. */ -#define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP6. */ -#define BF_AIPS_PACRE_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP6) & BM_AIPS_PACRE_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP6 (6U) /*!< Bit position for AIPS_PACRE_SP6. */ -#define BM_AIPS_PACRE_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRE_SP6. */ -#define BS_AIPS_PACRE_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP6. */ - -/*! @brief Read current value of the AIPS_PACRE_SP6 field. */ -#define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP6. */ -#define BF_AIPS_PACRE_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP6) & BM_AIPS_PACRE_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP5 (8U) /*!< Bit position for AIPS_PACRE_TP5. */ -#define BM_AIPS_PACRE_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRE_TP5. */ -#define BS_AIPS_PACRE_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP5. */ - -/*! @brief Read current value of the AIPS_PACRE_TP5 field. */ -#define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP5. */ -#define BF_AIPS_PACRE_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP5) & BM_AIPS_PACRE_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP5 (9U) /*!< Bit position for AIPS_PACRE_WP5. */ -#define BM_AIPS_PACRE_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRE_WP5. */ -#define BS_AIPS_PACRE_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP5. */ - -/*! @brief Read current value of the AIPS_PACRE_WP5 field. */ -#define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP5. */ -#define BF_AIPS_PACRE_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP5) & BM_AIPS_PACRE_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP5 (10U) /*!< Bit position for AIPS_PACRE_SP5. */ -#define BM_AIPS_PACRE_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRE_SP5. */ -#define BS_AIPS_PACRE_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP5. */ - -/*! @brief Read current value of the AIPS_PACRE_SP5 field. */ -#define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP5. */ -#define BF_AIPS_PACRE_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP5) & BM_AIPS_PACRE_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP4 (12U) /*!< Bit position for AIPS_PACRE_TP4. */ -#define BM_AIPS_PACRE_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRE_TP4. */ -#define BS_AIPS_PACRE_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP4. */ - -/*! @brief Read current value of the AIPS_PACRE_TP4 field. */ -#define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP4. */ -#define BF_AIPS_PACRE_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP4) & BM_AIPS_PACRE_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP4 (13U) /*!< Bit position for AIPS_PACRE_WP4. */ -#define BM_AIPS_PACRE_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRE_WP4. */ -#define BS_AIPS_PACRE_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP4. */ - -/*! @brief Read current value of the AIPS_PACRE_WP4 field. */ -#define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP4. */ -#define BF_AIPS_PACRE_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP4) & BM_AIPS_PACRE_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP4 (14U) /*!< Bit position for AIPS_PACRE_SP4. */ -#define BM_AIPS_PACRE_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRE_SP4. */ -#define BS_AIPS_PACRE_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP4. */ - -/*! @brief Read current value of the AIPS_PACRE_SP4 field. */ -#define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP4. */ -#define BF_AIPS_PACRE_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP4) & BM_AIPS_PACRE_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP3 (16U) /*!< Bit position for AIPS_PACRE_TP3. */ -#define BM_AIPS_PACRE_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRE_TP3. */ -#define BS_AIPS_PACRE_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP3. */ - -/*! @brief Read current value of the AIPS_PACRE_TP3 field. */ -#define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP3. */ -#define BF_AIPS_PACRE_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP3) & BM_AIPS_PACRE_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP3 (17U) /*!< Bit position for AIPS_PACRE_WP3. */ -#define BM_AIPS_PACRE_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRE_WP3. */ -#define BS_AIPS_PACRE_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP3. */ - -/*! @brief Read current value of the AIPS_PACRE_WP3 field. */ -#define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP3. */ -#define BF_AIPS_PACRE_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP3) & BM_AIPS_PACRE_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP3 (18U) /*!< Bit position for AIPS_PACRE_SP3. */ -#define BM_AIPS_PACRE_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRE_SP3. */ -#define BS_AIPS_PACRE_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP3. */ - -/*! @brief Read current value of the AIPS_PACRE_SP3 field. */ -#define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP3. */ -#define BF_AIPS_PACRE_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP3) & BM_AIPS_PACRE_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP2 (20U) /*!< Bit position for AIPS_PACRE_TP2. */ -#define BM_AIPS_PACRE_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRE_TP2. */ -#define BS_AIPS_PACRE_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP2. */ - -/*! @brief Read current value of the AIPS_PACRE_TP2 field. */ -#define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP2. */ -#define BF_AIPS_PACRE_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP2) & BM_AIPS_PACRE_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP2 (21U) /*!< Bit position for AIPS_PACRE_WP2. */ -#define BM_AIPS_PACRE_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRE_WP2. */ -#define BS_AIPS_PACRE_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP2. */ - -/*! @brief Read current value of the AIPS_PACRE_WP2 field. */ -#define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP2. */ -#define BF_AIPS_PACRE_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP2) & BM_AIPS_PACRE_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP2 (22U) /*!< Bit position for AIPS_PACRE_SP2. */ -#define BM_AIPS_PACRE_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRE_SP2. */ -#define BS_AIPS_PACRE_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP2. */ - -/*! @brief Read current value of the AIPS_PACRE_SP2 field. */ -#define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP2. */ -#define BF_AIPS_PACRE_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP2) & BM_AIPS_PACRE_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP1 (24U) /*!< Bit position for AIPS_PACRE_TP1. */ -#define BM_AIPS_PACRE_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRE_TP1. */ -#define BS_AIPS_PACRE_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP1. */ - -/*! @brief Read current value of the AIPS_PACRE_TP1 field. */ -#define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP1. */ -#define BF_AIPS_PACRE_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP1) & BM_AIPS_PACRE_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP1 (25U) /*!< Bit position for AIPS_PACRE_WP1. */ -#define BM_AIPS_PACRE_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRE_WP1. */ -#define BS_AIPS_PACRE_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP1. */ - -/*! @brief Read current value of the AIPS_PACRE_WP1 field. */ -#define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP1. */ -#define BF_AIPS_PACRE_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP1) & BM_AIPS_PACRE_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP1 (26U) /*!< Bit position for AIPS_PACRE_SP1. */ -#define BM_AIPS_PACRE_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRE_SP1. */ -#define BS_AIPS_PACRE_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP1. */ - -/*! @brief Read current value of the AIPS_PACRE_SP1 field. */ -#define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP1. */ -#define BF_AIPS_PACRE_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP1) & BM_AIPS_PACRE_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRE_TP0 (28U) /*!< Bit position for AIPS_PACRE_TP0. */ -#define BM_AIPS_PACRE_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRE_TP0. */ -#define BS_AIPS_PACRE_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP0. */ - -/*! @brief Read current value of the AIPS_PACRE_TP0 field. */ -#define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRE_TP0. */ -#define BF_AIPS_PACRE_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP0) & BM_AIPS_PACRE_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRE_WP0 (29U) /*!< Bit position for AIPS_PACRE_WP0. */ -#define BM_AIPS_PACRE_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRE_WP0. */ -#define BS_AIPS_PACRE_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP0. */ - -/*! @brief Read current value of the AIPS_PACRE_WP0 field. */ -#define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRE_WP0. */ -#define BF_AIPS_PACRE_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP0) & BM_AIPS_PACRE_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRE, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRE_SP0 (30U) /*!< Bit position for AIPS_PACRE_SP0. */ -#define BM_AIPS_PACRE_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRE_SP0. */ -#define BS_AIPS_PACRE_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP0. */ - -/*! @brief Read current value of the AIPS_PACRE_SP0 field. */ -#define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRE_SP0. */ -#define BF_AIPS_PACRE_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP0) & BM_AIPS_PACRE_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRF - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrf -{ - uint32_t U; - struct _hw_aips_pacrf_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrf_t; - -/*! - * @name Constants and macros for entire AIPS_PACRF register - */ -/*@{*/ -#define HW_AIPS_PACRF_ADDR(x) ((x) + 0x44U) - -#define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x)) -#define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U) -#define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v)) -#define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v))) -#define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v))) -#define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRF bitfields - */ - -/*! - * @name Register AIPS_PACRF, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP7 (0U) /*!< Bit position for AIPS_PACRF_TP7. */ -#define BM_AIPS_PACRF_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRF_TP7. */ -#define BS_AIPS_PACRF_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP7. */ - -/*! @brief Read current value of the AIPS_PACRF_TP7 field. */ -#define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP7. */ -#define BF_AIPS_PACRF_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP7) & BM_AIPS_PACRF_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP7 (1U) /*!< Bit position for AIPS_PACRF_WP7. */ -#define BM_AIPS_PACRF_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRF_WP7. */ -#define BS_AIPS_PACRF_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP7. */ - -/*! @brief Read current value of the AIPS_PACRF_WP7 field. */ -#define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP7. */ -#define BF_AIPS_PACRF_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP7) & BM_AIPS_PACRF_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP7 (2U) /*!< Bit position for AIPS_PACRF_SP7. */ -#define BM_AIPS_PACRF_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRF_SP7. */ -#define BS_AIPS_PACRF_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP7. */ - -/*! @brief Read current value of the AIPS_PACRF_SP7 field. */ -#define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP7. */ -#define BF_AIPS_PACRF_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP7) & BM_AIPS_PACRF_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP6 (4U) /*!< Bit position for AIPS_PACRF_TP6. */ -#define BM_AIPS_PACRF_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRF_TP6. */ -#define BS_AIPS_PACRF_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP6. */ - -/*! @brief Read current value of the AIPS_PACRF_TP6 field. */ -#define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP6. */ -#define BF_AIPS_PACRF_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP6) & BM_AIPS_PACRF_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP6 (5U) /*!< Bit position for AIPS_PACRF_WP6. */ -#define BM_AIPS_PACRF_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRF_WP6. */ -#define BS_AIPS_PACRF_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP6. */ - -/*! @brief Read current value of the AIPS_PACRF_WP6 field. */ -#define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP6. */ -#define BF_AIPS_PACRF_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP6) & BM_AIPS_PACRF_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP6 (6U) /*!< Bit position for AIPS_PACRF_SP6. */ -#define BM_AIPS_PACRF_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRF_SP6. */ -#define BS_AIPS_PACRF_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP6. */ - -/*! @brief Read current value of the AIPS_PACRF_SP6 field. */ -#define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP6. */ -#define BF_AIPS_PACRF_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP6) & BM_AIPS_PACRF_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP5 (8U) /*!< Bit position for AIPS_PACRF_TP5. */ -#define BM_AIPS_PACRF_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRF_TP5. */ -#define BS_AIPS_PACRF_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP5. */ - -/*! @brief Read current value of the AIPS_PACRF_TP5 field. */ -#define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP5. */ -#define BF_AIPS_PACRF_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP5) & BM_AIPS_PACRF_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP5 (9U) /*!< Bit position for AIPS_PACRF_WP5. */ -#define BM_AIPS_PACRF_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRF_WP5. */ -#define BS_AIPS_PACRF_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP5. */ - -/*! @brief Read current value of the AIPS_PACRF_WP5 field. */ -#define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP5. */ -#define BF_AIPS_PACRF_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP5) & BM_AIPS_PACRF_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP5 (10U) /*!< Bit position for AIPS_PACRF_SP5. */ -#define BM_AIPS_PACRF_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRF_SP5. */ -#define BS_AIPS_PACRF_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP5. */ - -/*! @brief Read current value of the AIPS_PACRF_SP5 field. */ -#define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP5. */ -#define BF_AIPS_PACRF_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP5) & BM_AIPS_PACRF_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP4 (12U) /*!< Bit position for AIPS_PACRF_TP4. */ -#define BM_AIPS_PACRF_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRF_TP4. */ -#define BS_AIPS_PACRF_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP4. */ - -/*! @brief Read current value of the AIPS_PACRF_TP4 field. */ -#define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP4. */ -#define BF_AIPS_PACRF_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP4) & BM_AIPS_PACRF_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP4 (13U) /*!< Bit position for AIPS_PACRF_WP4. */ -#define BM_AIPS_PACRF_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRF_WP4. */ -#define BS_AIPS_PACRF_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP4. */ - -/*! @brief Read current value of the AIPS_PACRF_WP4 field. */ -#define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP4. */ -#define BF_AIPS_PACRF_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP4) & BM_AIPS_PACRF_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP4 (14U) /*!< Bit position for AIPS_PACRF_SP4. */ -#define BM_AIPS_PACRF_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRF_SP4. */ -#define BS_AIPS_PACRF_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP4. */ - -/*! @brief Read current value of the AIPS_PACRF_SP4 field. */ -#define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP4. */ -#define BF_AIPS_PACRF_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP4) & BM_AIPS_PACRF_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP3 (16U) /*!< Bit position for AIPS_PACRF_TP3. */ -#define BM_AIPS_PACRF_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRF_TP3. */ -#define BS_AIPS_PACRF_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP3. */ - -/*! @brief Read current value of the AIPS_PACRF_TP3 field. */ -#define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP3. */ -#define BF_AIPS_PACRF_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP3) & BM_AIPS_PACRF_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP3 (17U) /*!< Bit position for AIPS_PACRF_WP3. */ -#define BM_AIPS_PACRF_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRF_WP3. */ -#define BS_AIPS_PACRF_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP3. */ - -/*! @brief Read current value of the AIPS_PACRF_WP3 field. */ -#define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP3. */ -#define BF_AIPS_PACRF_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP3) & BM_AIPS_PACRF_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP3 (18U) /*!< Bit position for AIPS_PACRF_SP3. */ -#define BM_AIPS_PACRF_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRF_SP3. */ -#define BS_AIPS_PACRF_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP3. */ - -/*! @brief Read current value of the AIPS_PACRF_SP3 field. */ -#define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP3. */ -#define BF_AIPS_PACRF_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP3) & BM_AIPS_PACRF_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP2 (20U) /*!< Bit position for AIPS_PACRF_TP2. */ -#define BM_AIPS_PACRF_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRF_TP2. */ -#define BS_AIPS_PACRF_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP2. */ - -/*! @brief Read current value of the AIPS_PACRF_TP2 field. */ -#define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP2. */ -#define BF_AIPS_PACRF_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP2) & BM_AIPS_PACRF_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP2 (21U) /*!< Bit position for AIPS_PACRF_WP2. */ -#define BM_AIPS_PACRF_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRF_WP2. */ -#define BS_AIPS_PACRF_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP2. */ - -/*! @brief Read current value of the AIPS_PACRF_WP2 field. */ -#define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP2. */ -#define BF_AIPS_PACRF_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP2) & BM_AIPS_PACRF_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP2 (22U) /*!< Bit position for AIPS_PACRF_SP2. */ -#define BM_AIPS_PACRF_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRF_SP2. */ -#define BS_AIPS_PACRF_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP2. */ - -/*! @brief Read current value of the AIPS_PACRF_SP2 field. */ -#define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP2. */ -#define BF_AIPS_PACRF_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP2) & BM_AIPS_PACRF_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP1 (24U) /*!< Bit position for AIPS_PACRF_TP1. */ -#define BM_AIPS_PACRF_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRF_TP1. */ -#define BS_AIPS_PACRF_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP1. */ - -/*! @brief Read current value of the AIPS_PACRF_TP1 field. */ -#define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP1. */ -#define BF_AIPS_PACRF_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP1) & BM_AIPS_PACRF_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP1 (25U) /*!< Bit position for AIPS_PACRF_WP1. */ -#define BM_AIPS_PACRF_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRF_WP1. */ -#define BS_AIPS_PACRF_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP1. */ - -/*! @brief Read current value of the AIPS_PACRF_WP1 field. */ -#define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP1. */ -#define BF_AIPS_PACRF_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP1) & BM_AIPS_PACRF_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP1 (26U) /*!< Bit position for AIPS_PACRF_SP1. */ -#define BM_AIPS_PACRF_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRF_SP1. */ -#define BS_AIPS_PACRF_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP1. */ - -/*! @brief Read current value of the AIPS_PACRF_SP1 field. */ -#define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP1. */ -#define BF_AIPS_PACRF_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP1) & BM_AIPS_PACRF_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRF_TP0 (28U) /*!< Bit position for AIPS_PACRF_TP0. */ -#define BM_AIPS_PACRF_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRF_TP0. */ -#define BS_AIPS_PACRF_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP0. */ - -/*! @brief Read current value of the AIPS_PACRF_TP0 field. */ -#define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRF_TP0. */ -#define BF_AIPS_PACRF_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP0) & BM_AIPS_PACRF_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRF_WP0 (29U) /*!< Bit position for AIPS_PACRF_WP0. */ -#define BM_AIPS_PACRF_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRF_WP0. */ -#define BS_AIPS_PACRF_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP0. */ - -/*! @brief Read current value of the AIPS_PACRF_WP0 field. */ -#define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRF_WP0. */ -#define BF_AIPS_PACRF_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP0) & BM_AIPS_PACRF_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRF, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRF_SP0 (30U) /*!< Bit position for AIPS_PACRF_SP0. */ -#define BM_AIPS_PACRF_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRF_SP0. */ -#define BS_AIPS_PACRF_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP0. */ - -/*! @brief Read current value of the AIPS_PACRF_SP0 field. */ -#define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRF_SP0. */ -#define BF_AIPS_PACRF_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP0) & BM_AIPS_PACRF_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRG - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrg -{ - uint32_t U; - struct _hw_aips_pacrg_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrg_t; - -/*! - * @name Constants and macros for entire AIPS_PACRG register - */ -/*@{*/ -#define HW_AIPS_PACRG_ADDR(x) ((x) + 0x48U) - -#define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x)) -#define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U) -#define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v)) -#define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v))) -#define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v))) -#define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRG bitfields - */ - -/*! - * @name Register AIPS_PACRG, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP7 (0U) /*!< Bit position for AIPS_PACRG_TP7. */ -#define BM_AIPS_PACRG_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRG_TP7. */ -#define BS_AIPS_PACRG_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP7. */ - -/*! @brief Read current value of the AIPS_PACRG_TP7 field. */ -#define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP7. */ -#define BF_AIPS_PACRG_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP7) & BM_AIPS_PACRG_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP7 (1U) /*!< Bit position for AIPS_PACRG_WP7. */ -#define BM_AIPS_PACRG_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRG_WP7. */ -#define BS_AIPS_PACRG_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP7. */ - -/*! @brief Read current value of the AIPS_PACRG_WP7 field. */ -#define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP7. */ -#define BF_AIPS_PACRG_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP7) & BM_AIPS_PACRG_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP7 (2U) /*!< Bit position for AIPS_PACRG_SP7. */ -#define BM_AIPS_PACRG_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRG_SP7. */ -#define BS_AIPS_PACRG_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP7. */ - -/*! @brief Read current value of the AIPS_PACRG_SP7 field. */ -#define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP7. */ -#define BF_AIPS_PACRG_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP7) & BM_AIPS_PACRG_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP6 (4U) /*!< Bit position for AIPS_PACRG_TP6. */ -#define BM_AIPS_PACRG_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRG_TP6. */ -#define BS_AIPS_PACRG_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP6. */ - -/*! @brief Read current value of the AIPS_PACRG_TP6 field. */ -#define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP6. */ -#define BF_AIPS_PACRG_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP6) & BM_AIPS_PACRG_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP6 (5U) /*!< Bit position for AIPS_PACRG_WP6. */ -#define BM_AIPS_PACRG_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRG_WP6. */ -#define BS_AIPS_PACRG_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP6. */ - -/*! @brief Read current value of the AIPS_PACRG_WP6 field. */ -#define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP6. */ -#define BF_AIPS_PACRG_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP6) & BM_AIPS_PACRG_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP6 (6U) /*!< Bit position for AIPS_PACRG_SP6. */ -#define BM_AIPS_PACRG_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRG_SP6. */ -#define BS_AIPS_PACRG_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP6. */ - -/*! @brief Read current value of the AIPS_PACRG_SP6 field. */ -#define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP6. */ -#define BF_AIPS_PACRG_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP6) & BM_AIPS_PACRG_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP5 (8U) /*!< Bit position for AIPS_PACRG_TP5. */ -#define BM_AIPS_PACRG_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRG_TP5. */ -#define BS_AIPS_PACRG_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP5. */ - -/*! @brief Read current value of the AIPS_PACRG_TP5 field. */ -#define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP5. */ -#define BF_AIPS_PACRG_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP5) & BM_AIPS_PACRG_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP5 (9U) /*!< Bit position for AIPS_PACRG_WP5. */ -#define BM_AIPS_PACRG_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRG_WP5. */ -#define BS_AIPS_PACRG_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP5. */ - -/*! @brief Read current value of the AIPS_PACRG_WP5 field. */ -#define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP5. */ -#define BF_AIPS_PACRG_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP5) & BM_AIPS_PACRG_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP5 (10U) /*!< Bit position for AIPS_PACRG_SP5. */ -#define BM_AIPS_PACRG_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRG_SP5. */ -#define BS_AIPS_PACRG_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP5. */ - -/*! @brief Read current value of the AIPS_PACRG_SP5 field. */ -#define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP5. */ -#define BF_AIPS_PACRG_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP5) & BM_AIPS_PACRG_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP4 (12U) /*!< Bit position for AIPS_PACRG_TP4. */ -#define BM_AIPS_PACRG_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRG_TP4. */ -#define BS_AIPS_PACRG_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP4. */ - -/*! @brief Read current value of the AIPS_PACRG_TP4 field. */ -#define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP4. */ -#define BF_AIPS_PACRG_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP4) & BM_AIPS_PACRG_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP4 (13U) /*!< Bit position for AIPS_PACRG_WP4. */ -#define BM_AIPS_PACRG_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRG_WP4. */ -#define BS_AIPS_PACRG_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP4. */ - -/*! @brief Read current value of the AIPS_PACRG_WP4 field. */ -#define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP4. */ -#define BF_AIPS_PACRG_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP4) & BM_AIPS_PACRG_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP4 (14U) /*!< Bit position for AIPS_PACRG_SP4. */ -#define BM_AIPS_PACRG_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRG_SP4. */ -#define BS_AIPS_PACRG_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP4. */ - -/*! @brief Read current value of the AIPS_PACRG_SP4 field. */ -#define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP4. */ -#define BF_AIPS_PACRG_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP4) & BM_AIPS_PACRG_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP3 (16U) /*!< Bit position for AIPS_PACRG_TP3. */ -#define BM_AIPS_PACRG_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRG_TP3. */ -#define BS_AIPS_PACRG_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP3. */ - -/*! @brief Read current value of the AIPS_PACRG_TP3 field. */ -#define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP3. */ -#define BF_AIPS_PACRG_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP3) & BM_AIPS_PACRG_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP3 (17U) /*!< Bit position for AIPS_PACRG_WP3. */ -#define BM_AIPS_PACRG_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRG_WP3. */ -#define BS_AIPS_PACRG_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP3. */ - -/*! @brief Read current value of the AIPS_PACRG_WP3 field. */ -#define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP3. */ -#define BF_AIPS_PACRG_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP3) & BM_AIPS_PACRG_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP3 (18U) /*!< Bit position for AIPS_PACRG_SP3. */ -#define BM_AIPS_PACRG_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRG_SP3. */ -#define BS_AIPS_PACRG_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP3. */ - -/*! @brief Read current value of the AIPS_PACRG_SP3 field. */ -#define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP3. */ -#define BF_AIPS_PACRG_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP3) & BM_AIPS_PACRG_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP2 (20U) /*!< Bit position for AIPS_PACRG_TP2. */ -#define BM_AIPS_PACRG_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRG_TP2. */ -#define BS_AIPS_PACRG_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP2. */ - -/*! @brief Read current value of the AIPS_PACRG_TP2 field. */ -#define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP2. */ -#define BF_AIPS_PACRG_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP2) & BM_AIPS_PACRG_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP2 (21U) /*!< Bit position for AIPS_PACRG_WP2. */ -#define BM_AIPS_PACRG_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRG_WP2. */ -#define BS_AIPS_PACRG_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP2. */ - -/*! @brief Read current value of the AIPS_PACRG_WP2 field. */ -#define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP2. */ -#define BF_AIPS_PACRG_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP2) & BM_AIPS_PACRG_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP2 (22U) /*!< Bit position for AIPS_PACRG_SP2. */ -#define BM_AIPS_PACRG_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRG_SP2. */ -#define BS_AIPS_PACRG_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP2. */ - -/*! @brief Read current value of the AIPS_PACRG_SP2 field. */ -#define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP2. */ -#define BF_AIPS_PACRG_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP2) & BM_AIPS_PACRG_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP1 (24U) /*!< Bit position for AIPS_PACRG_TP1. */ -#define BM_AIPS_PACRG_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRG_TP1. */ -#define BS_AIPS_PACRG_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP1. */ - -/*! @brief Read current value of the AIPS_PACRG_TP1 field. */ -#define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP1. */ -#define BF_AIPS_PACRG_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP1) & BM_AIPS_PACRG_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP1 (25U) /*!< Bit position for AIPS_PACRG_WP1. */ -#define BM_AIPS_PACRG_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRG_WP1. */ -#define BS_AIPS_PACRG_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP1. */ - -/*! @brief Read current value of the AIPS_PACRG_WP1 field. */ -#define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP1. */ -#define BF_AIPS_PACRG_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP1) & BM_AIPS_PACRG_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP1 (26U) /*!< Bit position for AIPS_PACRG_SP1. */ -#define BM_AIPS_PACRG_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRG_SP1. */ -#define BS_AIPS_PACRG_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP1. */ - -/*! @brief Read current value of the AIPS_PACRG_SP1 field. */ -#define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP1. */ -#define BF_AIPS_PACRG_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP1) & BM_AIPS_PACRG_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRG_TP0 (28U) /*!< Bit position for AIPS_PACRG_TP0. */ -#define BM_AIPS_PACRG_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRG_TP0. */ -#define BS_AIPS_PACRG_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP0. */ - -/*! @brief Read current value of the AIPS_PACRG_TP0 field. */ -#define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRG_TP0. */ -#define BF_AIPS_PACRG_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP0) & BM_AIPS_PACRG_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRG_WP0 (29U) /*!< Bit position for AIPS_PACRG_WP0. */ -#define BM_AIPS_PACRG_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRG_WP0. */ -#define BS_AIPS_PACRG_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP0. */ - -/*! @brief Read current value of the AIPS_PACRG_WP0 field. */ -#define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRG_WP0. */ -#define BF_AIPS_PACRG_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP0) & BM_AIPS_PACRG_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRG, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRG_SP0 (30U) /*!< Bit position for AIPS_PACRG_SP0. */ -#define BM_AIPS_PACRG_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRG_SP0. */ -#define BS_AIPS_PACRG_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP0. */ - -/*! @brief Read current value of the AIPS_PACRG_SP0 field. */ -#define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRG_SP0. */ -#define BF_AIPS_PACRG_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP0) & BM_AIPS_PACRG_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRH - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrh -{ - uint32_t U; - struct _hw_aips_pacrh_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrh_t; - -/*! - * @name Constants and macros for entire AIPS_PACRH register - */ -/*@{*/ -#define HW_AIPS_PACRH_ADDR(x) ((x) + 0x4CU) - -#define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x)) -#define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U) -#define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v)) -#define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v))) -#define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v))) -#define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRH bitfields - */ - -/*! - * @name Register AIPS_PACRH, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP7 (0U) /*!< Bit position for AIPS_PACRH_TP7. */ -#define BM_AIPS_PACRH_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRH_TP7. */ -#define BS_AIPS_PACRH_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP7. */ - -/*! @brief Read current value of the AIPS_PACRH_TP7 field. */ -#define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP7. */ -#define BF_AIPS_PACRH_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP7) & BM_AIPS_PACRH_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP7 (1U) /*!< Bit position for AIPS_PACRH_WP7. */ -#define BM_AIPS_PACRH_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRH_WP7. */ -#define BS_AIPS_PACRH_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP7. */ - -/*! @brief Read current value of the AIPS_PACRH_WP7 field. */ -#define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP7. */ -#define BF_AIPS_PACRH_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP7) & BM_AIPS_PACRH_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP7 (2U) /*!< Bit position for AIPS_PACRH_SP7. */ -#define BM_AIPS_PACRH_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRH_SP7. */ -#define BS_AIPS_PACRH_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP7. */ - -/*! @brief Read current value of the AIPS_PACRH_SP7 field. */ -#define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP7. */ -#define BF_AIPS_PACRH_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP7) & BM_AIPS_PACRH_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP6 (4U) /*!< Bit position for AIPS_PACRH_TP6. */ -#define BM_AIPS_PACRH_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRH_TP6. */ -#define BS_AIPS_PACRH_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP6. */ - -/*! @brief Read current value of the AIPS_PACRH_TP6 field. */ -#define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP6. */ -#define BF_AIPS_PACRH_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP6) & BM_AIPS_PACRH_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP6 (5U) /*!< Bit position for AIPS_PACRH_WP6. */ -#define BM_AIPS_PACRH_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRH_WP6. */ -#define BS_AIPS_PACRH_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP6. */ - -/*! @brief Read current value of the AIPS_PACRH_WP6 field. */ -#define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP6. */ -#define BF_AIPS_PACRH_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP6) & BM_AIPS_PACRH_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP6 (6U) /*!< Bit position for AIPS_PACRH_SP6. */ -#define BM_AIPS_PACRH_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRH_SP6. */ -#define BS_AIPS_PACRH_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP6. */ - -/*! @brief Read current value of the AIPS_PACRH_SP6 field. */ -#define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP6. */ -#define BF_AIPS_PACRH_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP6) & BM_AIPS_PACRH_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP5 (8U) /*!< Bit position for AIPS_PACRH_TP5. */ -#define BM_AIPS_PACRH_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRH_TP5. */ -#define BS_AIPS_PACRH_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP5. */ - -/*! @brief Read current value of the AIPS_PACRH_TP5 field. */ -#define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP5. */ -#define BF_AIPS_PACRH_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP5) & BM_AIPS_PACRH_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP5 (9U) /*!< Bit position for AIPS_PACRH_WP5. */ -#define BM_AIPS_PACRH_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRH_WP5. */ -#define BS_AIPS_PACRH_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP5. */ - -/*! @brief Read current value of the AIPS_PACRH_WP5 field. */ -#define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP5. */ -#define BF_AIPS_PACRH_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP5) & BM_AIPS_PACRH_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP5 (10U) /*!< Bit position for AIPS_PACRH_SP5. */ -#define BM_AIPS_PACRH_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRH_SP5. */ -#define BS_AIPS_PACRH_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP5. */ - -/*! @brief Read current value of the AIPS_PACRH_SP5 field. */ -#define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP5. */ -#define BF_AIPS_PACRH_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP5) & BM_AIPS_PACRH_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP4 (12U) /*!< Bit position for AIPS_PACRH_TP4. */ -#define BM_AIPS_PACRH_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRH_TP4. */ -#define BS_AIPS_PACRH_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP4. */ - -/*! @brief Read current value of the AIPS_PACRH_TP4 field. */ -#define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP4. */ -#define BF_AIPS_PACRH_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP4) & BM_AIPS_PACRH_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP4 (13U) /*!< Bit position for AIPS_PACRH_WP4. */ -#define BM_AIPS_PACRH_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRH_WP4. */ -#define BS_AIPS_PACRH_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP4. */ - -/*! @brief Read current value of the AIPS_PACRH_WP4 field. */ -#define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP4. */ -#define BF_AIPS_PACRH_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP4) & BM_AIPS_PACRH_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP4 (14U) /*!< Bit position for AIPS_PACRH_SP4. */ -#define BM_AIPS_PACRH_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRH_SP4. */ -#define BS_AIPS_PACRH_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP4. */ - -/*! @brief Read current value of the AIPS_PACRH_SP4 field. */ -#define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP4. */ -#define BF_AIPS_PACRH_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP4) & BM_AIPS_PACRH_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP3 (16U) /*!< Bit position for AIPS_PACRH_TP3. */ -#define BM_AIPS_PACRH_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRH_TP3. */ -#define BS_AIPS_PACRH_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP3. */ - -/*! @brief Read current value of the AIPS_PACRH_TP3 field. */ -#define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP3. */ -#define BF_AIPS_PACRH_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP3) & BM_AIPS_PACRH_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP3 (17U) /*!< Bit position for AIPS_PACRH_WP3. */ -#define BM_AIPS_PACRH_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRH_WP3. */ -#define BS_AIPS_PACRH_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP3. */ - -/*! @brief Read current value of the AIPS_PACRH_WP3 field. */ -#define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP3. */ -#define BF_AIPS_PACRH_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP3) & BM_AIPS_PACRH_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP3 (18U) /*!< Bit position for AIPS_PACRH_SP3. */ -#define BM_AIPS_PACRH_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRH_SP3. */ -#define BS_AIPS_PACRH_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP3. */ - -/*! @brief Read current value of the AIPS_PACRH_SP3 field. */ -#define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP3. */ -#define BF_AIPS_PACRH_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP3) & BM_AIPS_PACRH_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP2 (20U) /*!< Bit position for AIPS_PACRH_TP2. */ -#define BM_AIPS_PACRH_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRH_TP2. */ -#define BS_AIPS_PACRH_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP2. */ - -/*! @brief Read current value of the AIPS_PACRH_TP2 field. */ -#define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP2. */ -#define BF_AIPS_PACRH_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP2) & BM_AIPS_PACRH_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP2 (21U) /*!< Bit position for AIPS_PACRH_WP2. */ -#define BM_AIPS_PACRH_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRH_WP2. */ -#define BS_AIPS_PACRH_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP2. */ - -/*! @brief Read current value of the AIPS_PACRH_WP2 field. */ -#define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP2. */ -#define BF_AIPS_PACRH_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP2) & BM_AIPS_PACRH_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP2 (22U) /*!< Bit position for AIPS_PACRH_SP2. */ -#define BM_AIPS_PACRH_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRH_SP2. */ -#define BS_AIPS_PACRH_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP2. */ - -/*! @brief Read current value of the AIPS_PACRH_SP2 field. */ -#define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP2. */ -#define BF_AIPS_PACRH_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP2) & BM_AIPS_PACRH_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP1 (24U) /*!< Bit position for AIPS_PACRH_TP1. */ -#define BM_AIPS_PACRH_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRH_TP1. */ -#define BS_AIPS_PACRH_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP1. */ - -/*! @brief Read current value of the AIPS_PACRH_TP1 field. */ -#define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP1. */ -#define BF_AIPS_PACRH_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP1) & BM_AIPS_PACRH_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP1 (25U) /*!< Bit position for AIPS_PACRH_WP1. */ -#define BM_AIPS_PACRH_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRH_WP1. */ -#define BS_AIPS_PACRH_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP1. */ - -/*! @brief Read current value of the AIPS_PACRH_WP1 field. */ -#define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP1. */ -#define BF_AIPS_PACRH_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP1) & BM_AIPS_PACRH_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP1 (26U) /*!< Bit position for AIPS_PACRH_SP1. */ -#define BM_AIPS_PACRH_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRH_SP1. */ -#define BS_AIPS_PACRH_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP1. */ - -/*! @brief Read current value of the AIPS_PACRH_SP1 field. */ -#define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP1. */ -#define BF_AIPS_PACRH_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP1) & BM_AIPS_PACRH_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRH_TP0 (28U) /*!< Bit position for AIPS_PACRH_TP0. */ -#define BM_AIPS_PACRH_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRH_TP0. */ -#define BS_AIPS_PACRH_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP0. */ - -/*! @brief Read current value of the AIPS_PACRH_TP0 field. */ -#define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRH_TP0. */ -#define BF_AIPS_PACRH_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP0) & BM_AIPS_PACRH_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRH_WP0 (29U) /*!< Bit position for AIPS_PACRH_WP0. */ -#define BM_AIPS_PACRH_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRH_WP0. */ -#define BS_AIPS_PACRH_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP0. */ - -/*! @brief Read current value of the AIPS_PACRH_WP0 field. */ -#define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRH_WP0. */ -#define BF_AIPS_PACRH_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP0) & BM_AIPS_PACRH_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRH, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRH_SP0 (30U) /*!< Bit position for AIPS_PACRH_SP0. */ -#define BM_AIPS_PACRH_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRH_SP0. */ -#define BS_AIPS_PACRH_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP0. */ - -/*! @brief Read current value of the AIPS_PACRH_SP0 field. */ -#define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRH_SP0. */ -#define BF_AIPS_PACRH_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP0) & BM_AIPS_PACRH_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRI - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacri -{ - uint32_t U; - struct _hw_aips_pacri_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacri_t; - -/*! - * @name Constants and macros for entire AIPS_PACRI register - */ -/*@{*/ -#define HW_AIPS_PACRI_ADDR(x) ((x) + 0x50U) - -#define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x)) -#define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U) -#define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v)) -#define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v))) -#define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v))) -#define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRI bitfields - */ - -/*! - * @name Register AIPS_PACRI, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP7 (0U) /*!< Bit position for AIPS_PACRI_TP7. */ -#define BM_AIPS_PACRI_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRI_TP7. */ -#define BS_AIPS_PACRI_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP7. */ - -/*! @brief Read current value of the AIPS_PACRI_TP7 field. */ -#define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP7. */ -#define BF_AIPS_PACRI_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP7) & BM_AIPS_PACRI_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP7 (1U) /*!< Bit position for AIPS_PACRI_WP7. */ -#define BM_AIPS_PACRI_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRI_WP7. */ -#define BS_AIPS_PACRI_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP7. */ - -/*! @brief Read current value of the AIPS_PACRI_WP7 field. */ -#define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP7. */ -#define BF_AIPS_PACRI_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP7) & BM_AIPS_PACRI_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP7 (2U) /*!< Bit position for AIPS_PACRI_SP7. */ -#define BM_AIPS_PACRI_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRI_SP7. */ -#define BS_AIPS_PACRI_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP7. */ - -/*! @brief Read current value of the AIPS_PACRI_SP7 field. */ -#define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP7. */ -#define BF_AIPS_PACRI_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP7) & BM_AIPS_PACRI_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP6 (4U) /*!< Bit position for AIPS_PACRI_TP6. */ -#define BM_AIPS_PACRI_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRI_TP6. */ -#define BS_AIPS_PACRI_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP6. */ - -/*! @brief Read current value of the AIPS_PACRI_TP6 field. */ -#define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP6. */ -#define BF_AIPS_PACRI_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP6) & BM_AIPS_PACRI_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP6 (5U) /*!< Bit position for AIPS_PACRI_WP6. */ -#define BM_AIPS_PACRI_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRI_WP6. */ -#define BS_AIPS_PACRI_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP6. */ - -/*! @brief Read current value of the AIPS_PACRI_WP6 field. */ -#define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP6. */ -#define BF_AIPS_PACRI_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP6) & BM_AIPS_PACRI_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP6 (6U) /*!< Bit position for AIPS_PACRI_SP6. */ -#define BM_AIPS_PACRI_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRI_SP6. */ -#define BS_AIPS_PACRI_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP6. */ - -/*! @brief Read current value of the AIPS_PACRI_SP6 field. */ -#define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP6. */ -#define BF_AIPS_PACRI_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP6) & BM_AIPS_PACRI_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP5 (8U) /*!< Bit position for AIPS_PACRI_TP5. */ -#define BM_AIPS_PACRI_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRI_TP5. */ -#define BS_AIPS_PACRI_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP5. */ - -/*! @brief Read current value of the AIPS_PACRI_TP5 field. */ -#define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP5. */ -#define BF_AIPS_PACRI_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP5) & BM_AIPS_PACRI_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP5 (9U) /*!< Bit position for AIPS_PACRI_WP5. */ -#define BM_AIPS_PACRI_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRI_WP5. */ -#define BS_AIPS_PACRI_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP5. */ - -/*! @brief Read current value of the AIPS_PACRI_WP5 field. */ -#define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP5. */ -#define BF_AIPS_PACRI_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP5) & BM_AIPS_PACRI_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP5 (10U) /*!< Bit position for AIPS_PACRI_SP5. */ -#define BM_AIPS_PACRI_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRI_SP5. */ -#define BS_AIPS_PACRI_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP5. */ - -/*! @brief Read current value of the AIPS_PACRI_SP5 field. */ -#define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP5. */ -#define BF_AIPS_PACRI_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP5) & BM_AIPS_PACRI_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP4 (12U) /*!< Bit position for AIPS_PACRI_TP4. */ -#define BM_AIPS_PACRI_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRI_TP4. */ -#define BS_AIPS_PACRI_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP4. */ - -/*! @brief Read current value of the AIPS_PACRI_TP4 field. */ -#define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP4. */ -#define BF_AIPS_PACRI_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP4) & BM_AIPS_PACRI_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP4 (13U) /*!< Bit position for AIPS_PACRI_WP4. */ -#define BM_AIPS_PACRI_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRI_WP4. */ -#define BS_AIPS_PACRI_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP4. */ - -/*! @brief Read current value of the AIPS_PACRI_WP4 field. */ -#define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP4. */ -#define BF_AIPS_PACRI_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP4) & BM_AIPS_PACRI_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP4 (14U) /*!< Bit position for AIPS_PACRI_SP4. */ -#define BM_AIPS_PACRI_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRI_SP4. */ -#define BS_AIPS_PACRI_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP4. */ - -/*! @brief Read current value of the AIPS_PACRI_SP4 field. */ -#define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP4. */ -#define BF_AIPS_PACRI_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP4) & BM_AIPS_PACRI_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP3 (16U) /*!< Bit position for AIPS_PACRI_TP3. */ -#define BM_AIPS_PACRI_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRI_TP3. */ -#define BS_AIPS_PACRI_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP3. */ - -/*! @brief Read current value of the AIPS_PACRI_TP3 field. */ -#define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP3. */ -#define BF_AIPS_PACRI_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP3) & BM_AIPS_PACRI_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP3 (17U) /*!< Bit position for AIPS_PACRI_WP3. */ -#define BM_AIPS_PACRI_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRI_WP3. */ -#define BS_AIPS_PACRI_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP3. */ - -/*! @brief Read current value of the AIPS_PACRI_WP3 field. */ -#define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP3. */ -#define BF_AIPS_PACRI_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP3) & BM_AIPS_PACRI_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP3 (18U) /*!< Bit position for AIPS_PACRI_SP3. */ -#define BM_AIPS_PACRI_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRI_SP3. */ -#define BS_AIPS_PACRI_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP3. */ - -/*! @brief Read current value of the AIPS_PACRI_SP3 field. */ -#define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP3. */ -#define BF_AIPS_PACRI_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP3) & BM_AIPS_PACRI_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP2 (20U) /*!< Bit position for AIPS_PACRI_TP2. */ -#define BM_AIPS_PACRI_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRI_TP2. */ -#define BS_AIPS_PACRI_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP2. */ - -/*! @brief Read current value of the AIPS_PACRI_TP2 field. */ -#define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP2. */ -#define BF_AIPS_PACRI_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP2) & BM_AIPS_PACRI_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP2 (21U) /*!< Bit position for AIPS_PACRI_WP2. */ -#define BM_AIPS_PACRI_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRI_WP2. */ -#define BS_AIPS_PACRI_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP2. */ - -/*! @brief Read current value of the AIPS_PACRI_WP2 field. */ -#define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP2. */ -#define BF_AIPS_PACRI_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP2) & BM_AIPS_PACRI_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP2 (22U) /*!< Bit position for AIPS_PACRI_SP2. */ -#define BM_AIPS_PACRI_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRI_SP2. */ -#define BS_AIPS_PACRI_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP2. */ - -/*! @brief Read current value of the AIPS_PACRI_SP2 field. */ -#define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP2. */ -#define BF_AIPS_PACRI_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP2) & BM_AIPS_PACRI_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP1 (24U) /*!< Bit position for AIPS_PACRI_TP1. */ -#define BM_AIPS_PACRI_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRI_TP1. */ -#define BS_AIPS_PACRI_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP1. */ - -/*! @brief Read current value of the AIPS_PACRI_TP1 field. */ -#define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP1. */ -#define BF_AIPS_PACRI_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP1) & BM_AIPS_PACRI_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP1 (25U) /*!< Bit position for AIPS_PACRI_WP1. */ -#define BM_AIPS_PACRI_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRI_WP1. */ -#define BS_AIPS_PACRI_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP1. */ - -/*! @brief Read current value of the AIPS_PACRI_WP1 field. */ -#define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP1. */ -#define BF_AIPS_PACRI_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP1) & BM_AIPS_PACRI_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP1 (26U) /*!< Bit position for AIPS_PACRI_SP1. */ -#define BM_AIPS_PACRI_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRI_SP1. */ -#define BS_AIPS_PACRI_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP1. */ - -/*! @brief Read current value of the AIPS_PACRI_SP1 field. */ -#define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP1. */ -#define BF_AIPS_PACRI_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP1) & BM_AIPS_PACRI_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRI_TP0 (28U) /*!< Bit position for AIPS_PACRI_TP0. */ -#define BM_AIPS_PACRI_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRI_TP0. */ -#define BS_AIPS_PACRI_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP0. */ - -/*! @brief Read current value of the AIPS_PACRI_TP0 field. */ -#define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRI_TP0. */ -#define BF_AIPS_PACRI_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP0) & BM_AIPS_PACRI_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRI_WP0 (29U) /*!< Bit position for AIPS_PACRI_WP0. */ -#define BM_AIPS_PACRI_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRI_WP0. */ -#define BS_AIPS_PACRI_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP0. */ - -/*! @brief Read current value of the AIPS_PACRI_WP0 field. */ -#define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRI_WP0. */ -#define BF_AIPS_PACRI_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP0) & BM_AIPS_PACRI_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRI, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRI_SP0 (30U) /*!< Bit position for AIPS_PACRI_SP0. */ -#define BM_AIPS_PACRI_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRI_SP0. */ -#define BS_AIPS_PACRI_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP0. */ - -/*! @brief Read current value of the AIPS_PACRI_SP0 field. */ -#define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRI_SP0. */ -#define BF_AIPS_PACRI_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP0) & BM_AIPS_PACRI_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRJ - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrj -{ - uint32_t U; - struct _hw_aips_pacrj_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrj_t; - -/*! - * @name Constants and macros for entire AIPS_PACRJ register - */ -/*@{*/ -#define HW_AIPS_PACRJ_ADDR(x) ((x) + 0x54U) - -#define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x)) -#define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U) -#define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v)) -#define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v))) -#define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v))) -#define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRJ bitfields - */ - -/*! - * @name Register AIPS_PACRJ, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP7 (0U) /*!< Bit position for AIPS_PACRJ_TP7. */ -#define BM_AIPS_PACRJ_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRJ_TP7. */ -#define BS_AIPS_PACRJ_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP7. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */ -#define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP7. */ -#define BF_AIPS_PACRJ_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP7) & BM_AIPS_PACRJ_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP7 (1U) /*!< Bit position for AIPS_PACRJ_WP7. */ -#define BM_AIPS_PACRJ_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRJ_WP7. */ -#define BS_AIPS_PACRJ_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP7. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */ -#define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP7. */ -#define BF_AIPS_PACRJ_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP7) & BM_AIPS_PACRJ_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP7 (2U) /*!< Bit position for AIPS_PACRJ_SP7. */ -#define BM_AIPS_PACRJ_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRJ_SP7. */ -#define BS_AIPS_PACRJ_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP7. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */ -#define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP7. */ -#define BF_AIPS_PACRJ_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP7) & BM_AIPS_PACRJ_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP6 (4U) /*!< Bit position for AIPS_PACRJ_TP6. */ -#define BM_AIPS_PACRJ_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRJ_TP6. */ -#define BS_AIPS_PACRJ_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP6. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */ -#define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP6. */ -#define BF_AIPS_PACRJ_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP6) & BM_AIPS_PACRJ_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP6 (5U) /*!< Bit position for AIPS_PACRJ_WP6. */ -#define BM_AIPS_PACRJ_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRJ_WP6. */ -#define BS_AIPS_PACRJ_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP6. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */ -#define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP6. */ -#define BF_AIPS_PACRJ_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP6) & BM_AIPS_PACRJ_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP6 (6U) /*!< Bit position for AIPS_PACRJ_SP6. */ -#define BM_AIPS_PACRJ_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRJ_SP6. */ -#define BS_AIPS_PACRJ_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP6. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */ -#define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP6. */ -#define BF_AIPS_PACRJ_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP6) & BM_AIPS_PACRJ_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP5 (8U) /*!< Bit position for AIPS_PACRJ_TP5. */ -#define BM_AIPS_PACRJ_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRJ_TP5. */ -#define BS_AIPS_PACRJ_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP5. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */ -#define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP5. */ -#define BF_AIPS_PACRJ_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP5) & BM_AIPS_PACRJ_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP5 (9U) /*!< Bit position for AIPS_PACRJ_WP5. */ -#define BM_AIPS_PACRJ_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRJ_WP5. */ -#define BS_AIPS_PACRJ_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP5. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */ -#define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP5. */ -#define BF_AIPS_PACRJ_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP5) & BM_AIPS_PACRJ_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP5 (10U) /*!< Bit position for AIPS_PACRJ_SP5. */ -#define BM_AIPS_PACRJ_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRJ_SP5. */ -#define BS_AIPS_PACRJ_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP5. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */ -#define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP5. */ -#define BF_AIPS_PACRJ_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP5) & BM_AIPS_PACRJ_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP4 (12U) /*!< Bit position for AIPS_PACRJ_TP4. */ -#define BM_AIPS_PACRJ_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRJ_TP4. */ -#define BS_AIPS_PACRJ_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP4. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */ -#define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP4. */ -#define BF_AIPS_PACRJ_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP4) & BM_AIPS_PACRJ_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP4 (13U) /*!< Bit position for AIPS_PACRJ_WP4. */ -#define BM_AIPS_PACRJ_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRJ_WP4. */ -#define BS_AIPS_PACRJ_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP4. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */ -#define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP4. */ -#define BF_AIPS_PACRJ_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP4) & BM_AIPS_PACRJ_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP4 (14U) /*!< Bit position for AIPS_PACRJ_SP4. */ -#define BM_AIPS_PACRJ_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRJ_SP4. */ -#define BS_AIPS_PACRJ_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP4. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */ -#define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP4. */ -#define BF_AIPS_PACRJ_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP4) & BM_AIPS_PACRJ_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP3 (16U) /*!< Bit position for AIPS_PACRJ_TP3. */ -#define BM_AIPS_PACRJ_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRJ_TP3. */ -#define BS_AIPS_PACRJ_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP3. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */ -#define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP3. */ -#define BF_AIPS_PACRJ_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP3) & BM_AIPS_PACRJ_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP3 (17U) /*!< Bit position for AIPS_PACRJ_WP3. */ -#define BM_AIPS_PACRJ_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRJ_WP3. */ -#define BS_AIPS_PACRJ_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP3. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */ -#define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP3. */ -#define BF_AIPS_PACRJ_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP3) & BM_AIPS_PACRJ_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP3 (18U) /*!< Bit position for AIPS_PACRJ_SP3. */ -#define BM_AIPS_PACRJ_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRJ_SP3. */ -#define BS_AIPS_PACRJ_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP3. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */ -#define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP3. */ -#define BF_AIPS_PACRJ_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP3) & BM_AIPS_PACRJ_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP2 (20U) /*!< Bit position for AIPS_PACRJ_TP2. */ -#define BM_AIPS_PACRJ_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRJ_TP2. */ -#define BS_AIPS_PACRJ_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP2. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */ -#define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP2. */ -#define BF_AIPS_PACRJ_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP2) & BM_AIPS_PACRJ_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP2 (21U) /*!< Bit position for AIPS_PACRJ_WP2. */ -#define BM_AIPS_PACRJ_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRJ_WP2. */ -#define BS_AIPS_PACRJ_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP2. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */ -#define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP2. */ -#define BF_AIPS_PACRJ_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP2) & BM_AIPS_PACRJ_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP2 (22U) /*!< Bit position for AIPS_PACRJ_SP2. */ -#define BM_AIPS_PACRJ_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRJ_SP2. */ -#define BS_AIPS_PACRJ_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP2. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */ -#define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP2. */ -#define BF_AIPS_PACRJ_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP2) & BM_AIPS_PACRJ_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP1 (24U) /*!< Bit position for AIPS_PACRJ_TP1. */ -#define BM_AIPS_PACRJ_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRJ_TP1. */ -#define BS_AIPS_PACRJ_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP1. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */ -#define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP1. */ -#define BF_AIPS_PACRJ_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP1) & BM_AIPS_PACRJ_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP1 (25U) /*!< Bit position for AIPS_PACRJ_WP1. */ -#define BM_AIPS_PACRJ_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRJ_WP1. */ -#define BS_AIPS_PACRJ_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP1. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */ -#define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP1. */ -#define BF_AIPS_PACRJ_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP1) & BM_AIPS_PACRJ_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP1 (26U) /*!< Bit position for AIPS_PACRJ_SP1. */ -#define BM_AIPS_PACRJ_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRJ_SP1. */ -#define BS_AIPS_PACRJ_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP1. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */ -#define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP1. */ -#define BF_AIPS_PACRJ_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP1) & BM_AIPS_PACRJ_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRJ_TP0 (28U) /*!< Bit position for AIPS_PACRJ_TP0. */ -#define BM_AIPS_PACRJ_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRJ_TP0. */ -#define BS_AIPS_PACRJ_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP0. */ - -/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */ -#define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRJ_TP0. */ -#define BF_AIPS_PACRJ_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP0) & BM_AIPS_PACRJ_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRJ_WP0 (29U) /*!< Bit position for AIPS_PACRJ_WP0. */ -#define BM_AIPS_PACRJ_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRJ_WP0. */ -#define BS_AIPS_PACRJ_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP0. */ - -/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */ -#define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRJ_WP0. */ -#define BF_AIPS_PACRJ_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP0) & BM_AIPS_PACRJ_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRJ, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRJ_SP0 (30U) /*!< Bit position for AIPS_PACRJ_SP0. */ -#define BM_AIPS_PACRJ_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRJ_SP0. */ -#define BS_AIPS_PACRJ_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP0. */ - -/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */ -#define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRJ_SP0. */ -#define BF_AIPS_PACRJ_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP0) & BM_AIPS_PACRJ_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRK - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrk -{ - uint32_t U; - struct _hw_aips_pacrk_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrk_t; - -/*! - * @name Constants and macros for entire AIPS_PACRK register - */ -/*@{*/ -#define HW_AIPS_PACRK_ADDR(x) ((x) + 0x58U) - -#define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x)) -#define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U) -#define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v)) -#define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v))) -#define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v))) -#define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRK bitfields - */ - -/*! - * @name Register AIPS_PACRK, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP7 (0U) /*!< Bit position for AIPS_PACRK_TP7. */ -#define BM_AIPS_PACRK_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRK_TP7. */ -#define BS_AIPS_PACRK_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP7. */ - -/*! @brief Read current value of the AIPS_PACRK_TP7 field. */ -#define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP7. */ -#define BF_AIPS_PACRK_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP7) & BM_AIPS_PACRK_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP7 (1U) /*!< Bit position for AIPS_PACRK_WP7. */ -#define BM_AIPS_PACRK_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRK_WP7. */ -#define BS_AIPS_PACRK_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP7. */ - -/*! @brief Read current value of the AIPS_PACRK_WP7 field. */ -#define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP7. */ -#define BF_AIPS_PACRK_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP7) & BM_AIPS_PACRK_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP7 (2U) /*!< Bit position for AIPS_PACRK_SP7. */ -#define BM_AIPS_PACRK_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRK_SP7. */ -#define BS_AIPS_PACRK_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP7. */ - -/*! @brief Read current value of the AIPS_PACRK_SP7 field. */ -#define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP7. */ -#define BF_AIPS_PACRK_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP7) & BM_AIPS_PACRK_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP6 (4U) /*!< Bit position for AIPS_PACRK_TP6. */ -#define BM_AIPS_PACRK_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRK_TP6. */ -#define BS_AIPS_PACRK_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP6. */ - -/*! @brief Read current value of the AIPS_PACRK_TP6 field. */ -#define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP6. */ -#define BF_AIPS_PACRK_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP6) & BM_AIPS_PACRK_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP6 (5U) /*!< Bit position for AIPS_PACRK_WP6. */ -#define BM_AIPS_PACRK_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRK_WP6. */ -#define BS_AIPS_PACRK_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP6. */ - -/*! @brief Read current value of the AIPS_PACRK_WP6 field. */ -#define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP6. */ -#define BF_AIPS_PACRK_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP6) & BM_AIPS_PACRK_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP6 (6U) /*!< Bit position for AIPS_PACRK_SP6. */ -#define BM_AIPS_PACRK_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRK_SP6. */ -#define BS_AIPS_PACRK_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP6. */ - -/*! @brief Read current value of the AIPS_PACRK_SP6 field. */ -#define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP6. */ -#define BF_AIPS_PACRK_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP6) & BM_AIPS_PACRK_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP5 (8U) /*!< Bit position for AIPS_PACRK_TP5. */ -#define BM_AIPS_PACRK_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRK_TP5. */ -#define BS_AIPS_PACRK_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP5. */ - -/*! @brief Read current value of the AIPS_PACRK_TP5 field. */ -#define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP5. */ -#define BF_AIPS_PACRK_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP5) & BM_AIPS_PACRK_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP5 (9U) /*!< Bit position for AIPS_PACRK_WP5. */ -#define BM_AIPS_PACRK_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRK_WP5. */ -#define BS_AIPS_PACRK_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP5. */ - -/*! @brief Read current value of the AIPS_PACRK_WP5 field. */ -#define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP5. */ -#define BF_AIPS_PACRK_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP5) & BM_AIPS_PACRK_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP5 (10U) /*!< Bit position for AIPS_PACRK_SP5. */ -#define BM_AIPS_PACRK_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRK_SP5. */ -#define BS_AIPS_PACRK_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP5. */ - -/*! @brief Read current value of the AIPS_PACRK_SP5 field. */ -#define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP5. */ -#define BF_AIPS_PACRK_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP5) & BM_AIPS_PACRK_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP4 (12U) /*!< Bit position for AIPS_PACRK_TP4. */ -#define BM_AIPS_PACRK_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRK_TP4. */ -#define BS_AIPS_PACRK_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP4. */ - -/*! @brief Read current value of the AIPS_PACRK_TP4 field. */ -#define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP4. */ -#define BF_AIPS_PACRK_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP4) & BM_AIPS_PACRK_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP4 (13U) /*!< Bit position for AIPS_PACRK_WP4. */ -#define BM_AIPS_PACRK_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRK_WP4. */ -#define BS_AIPS_PACRK_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP4. */ - -/*! @brief Read current value of the AIPS_PACRK_WP4 field. */ -#define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP4. */ -#define BF_AIPS_PACRK_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP4) & BM_AIPS_PACRK_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP4 (14U) /*!< Bit position for AIPS_PACRK_SP4. */ -#define BM_AIPS_PACRK_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRK_SP4. */ -#define BS_AIPS_PACRK_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP4. */ - -/*! @brief Read current value of the AIPS_PACRK_SP4 field. */ -#define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP4. */ -#define BF_AIPS_PACRK_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP4) & BM_AIPS_PACRK_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP3 (16U) /*!< Bit position for AIPS_PACRK_TP3. */ -#define BM_AIPS_PACRK_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRK_TP3. */ -#define BS_AIPS_PACRK_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP3. */ - -/*! @brief Read current value of the AIPS_PACRK_TP3 field. */ -#define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP3. */ -#define BF_AIPS_PACRK_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP3) & BM_AIPS_PACRK_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP3 (17U) /*!< Bit position for AIPS_PACRK_WP3. */ -#define BM_AIPS_PACRK_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRK_WP3. */ -#define BS_AIPS_PACRK_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP3. */ - -/*! @brief Read current value of the AIPS_PACRK_WP3 field. */ -#define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP3. */ -#define BF_AIPS_PACRK_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP3) & BM_AIPS_PACRK_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP3 (18U) /*!< Bit position for AIPS_PACRK_SP3. */ -#define BM_AIPS_PACRK_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRK_SP3. */ -#define BS_AIPS_PACRK_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP3. */ - -/*! @brief Read current value of the AIPS_PACRK_SP3 field. */ -#define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP3. */ -#define BF_AIPS_PACRK_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP3) & BM_AIPS_PACRK_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP2 (20U) /*!< Bit position for AIPS_PACRK_TP2. */ -#define BM_AIPS_PACRK_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRK_TP2. */ -#define BS_AIPS_PACRK_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP2. */ - -/*! @brief Read current value of the AIPS_PACRK_TP2 field. */ -#define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP2. */ -#define BF_AIPS_PACRK_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP2) & BM_AIPS_PACRK_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP2 (21U) /*!< Bit position for AIPS_PACRK_WP2. */ -#define BM_AIPS_PACRK_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRK_WP2. */ -#define BS_AIPS_PACRK_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP2. */ - -/*! @brief Read current value of the AIPS_PACRK_WP2 field. */ -#define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP2. */ -#define BF_AIPS_PACRK_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP2) & BM_AIPS_PACRK_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP2 (22U) /*!< Bit position for AIPS_PACRK_SP2. */ -#define BM_AIPS_PACRK_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRK_SP2. */ -#define BS_AIPS_PACRK_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP2. */ - -/*! @brief Read current value of the AIPS_PACRK_SP2 field. */ -#define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP2. */ -#define BF_AIPS_PACRK_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP2) & BM_AIPS_PACRK_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP1 (24U) /*!< Bit position for AIPS_PACRK_TP1. */ -#define BM_AIPS_PACRK_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRK_TP1. */ -#define BS_AIPS_PACRK_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP1. */ - -/*! @brief Read current value of the AIPS_PACRK_TP1 field. */ -#define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP1. */ -#define BF_AIPS_PACRK_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP1) & BM_AIPS_PACRK_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP1 (25U) /*!< Bit position for AIPS_PACRK_WP1. */ -#define BM_AIPS_PACRK_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRK_WP1. */ -#define BS_AIPS_PACRK_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP1. */ - -/*! @brief Read current value of the AIPS_PACRK_WP1 field. */ -#define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP1. */ -#define BF_AIPS_PACRK_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP1) & BM_AIPS_PACRK_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP1 (26U) /*!< Bit position for AIPS_PACRK_SP1. */ -#define BM_AIPS_PACRK_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRK_SP1. */ -#define BS_AIPS_PACRK_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP1. */ - -/*! @brief Read current value of the AIPS_PACRK_SP1 field. */ -#define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP1. */ -#define BF_AIPS_PACRK_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP1) & BM_AIPS_PACRK_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRK_TP0 (28U) /*!< Bit position for AIPS_PACRK_TP0. */ -#define BM_AIPS_PACRK_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRK_TP0. */ -#define BS_AIPS_PACRK_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP0. */ - -/*! @brief Read current value of the AIPS_PACRK_TP0 field. */ -#define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRK_TP0. */ -#define BF_AIPS_PACRK_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP0) & BM_AIPS_PACRK_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRK_WP0 (29U) /*!< Bit position for AIPS_PACRK_WP0. */ -#define BM_AIPS_PACRK_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRK_WP0. */ -#define BS_AIPS_PACRK_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP0. */ - -/*! @brief Read current value of the AIPS_PACRK_WP0 field. */ -#define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRK_WP0. */ -#define BF_AIPS_PACRK_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP0) & BM_AIPS_PACRK_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRK, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRK_SP0 (30U) /*!< Bit position for AIPS_PACRK_SP0. */ -#define BM_AIPS_PACRK_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRK_SP0. */ -#define BS_AIPS_PACRK_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP0. */ - -/*! @brief Read current value of the AIPS_PACRK_SP0 field. */ -#define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRK_SP0. */ -#define BF_AIPS_PACRK_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP0) & BM_AIPS_PACRK_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRL - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrl -{ - uint32_t U; - struct _hw_aips_pacrl_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrl_t; - -/*! - * @name Constants and macros for entire AIPS_PACRL register - */ -/*@{*/ -#define HW_AIPS_PACRL_ADDR(x) ((x) + 0x5CU) - -#define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x)) -#define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U) -#define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v)) -#define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v))) -#define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v))) -#define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRL bitfields - */ - -/*! - * @name Register AIPS_PACRL, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP7 (0U) /*!< Bit position for AIPS_PACRL_TP7. */ -#define BM_AIPS_PACRL_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRL_TP7. */ -#define BS_AIPS_PACRL_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP7. */ - -/*! @brief Read current value of the AIPS_PACRL_TP7 field. */ -#define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP7. */ -#define BF_AIPS_PACRL_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP7) & BM_AIPS_PACRL_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP7 (1U) /*!< Bit position for AIPS_PACRL_WP7. */ -#define BM_AIPS_PACRL_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRL_WP7. */ -#define BS_AIPS_PACRL_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP7. */ - -/*! @brief Read current value of the AIPS_PACRL_WP7 field. */ -#define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP7. */ -#define BF_AIPS_PACRL_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP7) & BM_AIPS_PACRL_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP7 (2U) /*!< Bit position for AIPS_PACRL_SP7. */ -#define BM_AIPS_PACRL_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRL_SP7. */ -#define BS_AIPS_PACRL_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP7. */ - -/*! @brief Read current value of the AIPS_PACRL_SP7 field. */ -#define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP7. */ -#define BF_AIPS_PACRL_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP7) & BM_AIPS_PACRL_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP6 (4U) /*!< Bit position for AIPS_PACRL_TP6. */ -#define BM_AIPS_PACRL_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRL_TP6. */ -#define BS_AIPS_PACRL_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP6. */ - -/*! @brief Read current value of the AIPS_PACRL_TP6 field. */ -#define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP6. */ -#define BF_AIPS_PACRL_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP6) & BM_AIPS_PACRL_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP6 (5U) /*!< Bit position for AIPS_PACRL_WP6. */ -#define BM_AIPS_PACRL_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRL_WP6. */ -#define BS_AIPS_PACRL_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP6. */ - -/*! @brief Read current value of the AIPS_PACRL_WP6 field. */ -#define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP6. */ -#define BF_AIPS_PACRL_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP6) & BM_AIPS_PACRL_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP6 (6U) /*!< Bit position for AIPS_PACRL_SP6. */ -#define BM_AIPS_PACRL_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRL_SP6. */ -#define BS_AIPS_PACRL_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP6. */ - -/*! @brief Read current value of the AIPS_PACRL_SP6 field. */ -#define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP6. */ -#define BF_AIPS_PACRL_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP6) & BM_AIPS_PACRL_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP5 (8U) /*!< Bit position for AIPS_PACRL_TP5. */ -#define BM_AIPS_PACRL_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRL_TP5. */ -#define BS_AIPS_PACRL_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP5. */ - -/*! @brief Read current value of the AIPS_PACRL_TP5 field. */ -#define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP5. */ -#define BF_AIPS_PACRL_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP5) & BM_AIPS_PACRL_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP5 (9U) /*!< Bit position for AIPS_PACRL_WP5. */ -#define BM_AIPS_PACRL_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRL_WP5. */ -#define BS_AIPS_PACRL_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP5. */ - -/*! @brief Read current value of the AIPS_PACRL_WP5 field. */ -#define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP5. */ -#define BF_AIPS_PACRL_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP5) & BM_AIPS_PACRL_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP5 (10U) /*!< Bit position for AIPS_PACRL_SP5. */ -#define BM_AIPS_PACRL_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRL_SP5. */ -#define BS_AIPS_PACRL_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP5. */ - -/*! @brief Read current value of the AIPS_PACRL_SP5 field. */ -#define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP5. */ -#define BF_AIPS_PACRL_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP5) & BM_AIPS_PACRL_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP4 (12U) /*!< Bit position for AIPS_PACRL_TP4. */ -#define BM_AIPS_PACRL_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRL_TP4. */ -#define BS_AIPS_PACRL_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP4. */ - -/*! @brief Read current value of the AIPS_PACRL_TP4 field. */ -#define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP4. */ -#define BF_AIPS_PACRL_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP4) & BM_AIPS_PACRL_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP4 (13U) /*!< Bit position for AIPS_PACRL_WP4. */ -#define BM_AIPS_PACRL_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRL_WP4. */ -#define BS_AIPS_PACRL_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP4. */ - -/*! @brief Read current value of the AIPS_PACRL_WP4 field. */ -#define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP4. */ -#define BF_AIPS_PACRL_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP4) & BM_AIPS_PACRL_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP4 (14U) /*!< Bit position for AIPS_PACRL_SP4. */ -#define BM_AIPS_PACRL_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRL_SP4. */ -#define BS_AIPS_PACRL_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP4. */ - -/*! @brief Read current value of the AIPS_PACRL_SP4 field. */ -#define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP4. */ -#define BF_AIPS_PACRL_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP4) & BM_AIPS_PACRL_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP3 (16U) /*!< Bit position for AIPS_PACRL_TP3. */ -#define BM_AIPS_PACRL_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRL_TP3. */ -#define BS_AIPS_PACRL_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP3. */ - -/*! @brief Read current value of the AIPS_PACRL_TP3 field. */ -#define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP3. */ -#define BF_AIPS_PACRL_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP3) & BM_AIPS_PACRL_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP3 (17U) /*!< Bit position for AIPS_PACRL_WP3. */ -#define BM_AIPS_PACRL_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRL_WP3. */ -#define BS_AIPS_PACRL_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP3. */ - -/*! @brief Read current value of the AIPS_PACRL_WP3 field. */ -#define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP3. */ -#define BF_AIPS_PACRL_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP3) & BM_AIPS_PACRL_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP3 (18U) /*!< Bit position for AIPS_PACRL_SP3. */ -#define BM_AIPS_PACRL_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRL_SP3. */ -#define BS_AIPS_PACRL_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP3. */ - -/*! @brief Read current value of the AIPS_PACRL_SP3 field. */ -#define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP3. */ -#define BF_AIPS_PACRL_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP3) & BM_AIPS_PACRL_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP2 (20U) /*!< Bit position for AIPS_PACRL_TP2. */ -#define BM_AIPS_PACRL_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRL_TP2. */ -#define BS_AIPS_PACRL_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP2. */ - -/*! @brief Read current value of the AIPS_PACRL_TP2 field. */ -#define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP2. */ -#define BF_AIPS_PACRL_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP2) & BM_AIPS_PACRL_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP2 (21U) /*!< Bit position for AIPS_PACRL_WP2. */ -#define BM_AIPS_PACRL_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRL_WP2. */ -#define BS_AIPS_PACRL_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP2. */ - -/*! @brief Read current value of the AIPS_PACRL_WP2 field. */ -#define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP2. */ -#define BF_AIPS_PACRL_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP2) & BM_AIPS_PACRL_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP2 (22U) /*!< Bit position for AIPS_PACRL_SP2. */ -#define BM_AIPS_PACRL_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRL_SP2. */ -#define BS_AIPS_PACRL_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP2. */ - -/*! @brief Read current value of the AIPS_PACRL_SP2 field. */ -#define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP2. */ -#define BF_AIPS_PACRL_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP2) & BM_AIPS_PACRL_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP1 (24U) /*!< Bit position for AIPS_PACRL_TP1. */ -#define BM_AIPS_PACRL_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRL_TP1. */ -#define BS_AIPS_PACRL_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP1. */ - -/*! @brief Read current value of the AIPS_PACRL_TP1 field. */ -#define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP1. */ -#define BF_AIPS_PACRL_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP1) & BM_AIPS_PACRL_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP1 (25U) /*!< Bit position for AIPS_PACRL_WP1. */ -#define BM_AIPS_PACRL_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRL_WP1. */ -#define BS_AIPS_PACRL_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP1. */ - -/*! @brief Read current value of the AIPS_PACRL_WP1 field. */ -#define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP1. */ -#define BF_AIPS_PACRL_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP1) & BM_AIPS_PACRL_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP1 (26U) /*!< Bit position for AIPS_PACRL_SP1. */ -#define BM_AIPS_PACRL_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRL_SP1. */ -#define BS_AIPS_PACRL_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP1. */ - -/*! @brief Read current value of the AIPS_PACRL_SP1 field. */ -#define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP1. */ -#define BF_AIPS_PACRL_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP1) & BM_AIPS_PACRL_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRL_TP0 (28U) /*!< Bit position for AIPS_PACRL_TP0. */ -#define BM_AIPS_PACRL_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRL_TP0. */ -#define BS_AIPS_PACRL_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP0. */ - -/*! @brief Read current value of the AIPS_PACRL_TP0 field. */ -#define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRL_TP0. */ -#define BF_AIPS_PACRL_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP0) & BM_AIPS_PACRL_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRL_WP0 (29U) /*!< Bit position for AIPS_PACRL_WP0. */ -#define BM_AIPS_PACRL_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRL_WP0. */ -#define BS_AIPS_PACRL_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP0. */ - -/*! @brief Read current value of the AIPS_PACRL_WP0 field. */ -#define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRL_WP0. */ -#define BF_AIPS_PACRL_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP0) & BM_AIPS_PACRL_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRL, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRL_SP0 (30U) /*!< Bit position for AIPS_PACRL_SP0. */ -#define BM_AIPS_PACRL_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRL_SP0. */ -#define BS_AIPS_PACRL_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP0. */ - -/*! @brief Read current value of the AIPS_PACRL_SP0 field. */ -#define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRL_SP0. */ -#define BF_AIPS_PACRL_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP0) & BM_AIPS_PACRL_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRM - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrm -{ - uint32_t U; - struct _hw_aips_pacrm_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrm_t; - -/*! - * @name Constants and macros for entire AIPS_PACRM register - */ -/*@{*/ -#define HW_AIPS_PACRM_ADDR(x) ((x) + 0x60U) - -#define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x)) -#define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U) -#define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v)) -#define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v))) -#define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v))) -#define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRM bitfields - */ - -/*! - * @name Register AIPS_PACRM, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP7 (0U) /*!< Bit position for AIPS_PACRM_TP7. */ -#define BM_AIPS_PACRM_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRM_TP7. */ -#define BS_AIPS_PACRM_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP7. */ - -/*! @brief Read current value of the AIPS_PACRM_TP7 field. */ -#define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP7. */ -#define BF_AIPS_PACRM_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP7) & BM_AIPS_PACRM_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP7 (1U) /*!< Bit position for AIPS_PACRM_WP7. */ -#define BM_AIPS_PACRM_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRM_WP7. */ -#define BS_AIPS_PACRM_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP7. */ - -/*! @brief Read current value of the AIPS_PACRM_WP7 field. */ -#define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP7. */ -#define BF_AIPS_PACRM_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP7) & BM_AIPS_PACRM_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP7 (2U) /*!< Bit position for AIPS_PACRM_SP7. */ -#define BM_AIPS_PACRM_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRM_SP7. */ -#define BS_AIPS_PACRM_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP7. */ - -/*! @brief Read current value of the AIPS_PACRM_SP7 field. */ -#define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP7. */ -#define BF_AIPS_PACRM_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP7) & BM_AIPS_PACRM_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP6 (4U) /*!< Bit position for AIPS_PACRM_TP6. */ -#define BM_AIPS_PACRM_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRM_TP6. */ -#define BS_AIPS_PACRM_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP6. */ - -/*! @brief Read current value of the AIPS_PACRM_TP6 field. */ -#define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP6. */ -#define BF_AIPS_PACRM_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP6) & BM_AIPS_PACRM_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP6 (5U) /*!< Bit position for AIPS_PACRM_WP6. */ -#define BM_AIPS_PACRM_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRM_WP6. */ -#define BS_AIPS_PACRM_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP6. */ - -/*! @brief Read current value of the AIPS_PACRM_WP6 field. */ -#define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP6. */ -#define BF_AIPS_PACRM_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP6) & BM_AIPS_PACRM_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP6 (6U) /*!< Bit position for AIPS_PACRM_SP6. */ -#define BM_AIPS_PACRM_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRM_SP6. */ -#define BS_AIPS_PACRM_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP6. */ - -/*! @brief Read current value of the AIPS_PACRM_SP6 field. */ -#define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP6. */ -#define BF_AIPS_PACRM_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP6) & BM_AIPS_PACRM_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP5 (8U) /*!< Bit position for AIPS_PACRM_TP5. */ -#define BM_AIPS_PACRM_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRM_TP5. */ -#define BS_AIPS_PACRM_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP5. */ - -/*! @brief Read current value of the AIPS_PACRM_TP5 field. */ -#define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP5. */ -#define BF_AIPS_PACRM_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP5) & BM_AIPS_PACRM_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP5 (9U) /*!< Bit position for AIPS_PACRM_WP5. */ -#define BM_AIPS_PACRM_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRM_WP5. */ -#define BS_AIPS_PACRM_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP5. */ - -/*! @brief Read current value of the AIPS_PACRM_WP5 field. */ -#define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP5. */ -#define BF_AIPS_PACRM_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP5) & BM_AIPS_PACRM_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP5 (10U) /*!< Bit position for AIPS_PACRM_SP5. */ -#define BM_AIPS_PACRM_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRM_SP5. */ -#define BS_AIPS_PACRM_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP5. */ - -/*! @brief Read current value of the AIPS_PACRM_SP5 field. */ -#define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP5. */ -#define BF_AIPS_PACRM_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP5) & BM_AIPS_PACRM_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP4 (12U) /*!< Bit position for AIPS_PACRM_TP4. */ -#define BM_AIPS_PACRM_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRM_TP4. */ -#define BS_AIPS_PACRM_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP4. */ - -/*! @brief Read current value of the AIPS_PACRM_TP4 field. */ -#define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP4. */ -#define BF_AIPS_PACRM_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP4) & BM_AIPS_PACRM_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP4 (13U) /*!< Bit position for AIPS_PACRM_WP4. */ -#define BM_AIPS_PACRM_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRM_WP4. */ -#define BS_AIPS_PACRM_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP4. */ - -/*! @brief Read current value of the AIPS_PACRM_WP4 field. */ -#define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP4. */ -#define BF_AIPS_PACRM_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP4) & BM_AIPS_PACRM_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP4 (14U) /*!< Bit position for AIPS_PACRM_SP4. */ -#define BM_AIPS_PACRM_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRM_SP4. */ -#define BS_AIPS_PACRM_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP4. */ - -/*! @brief Read current value of the AIPS_PACRM_SP4 field. */ -#define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP4. */ -#define BF_AIPS_PACRM_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP4) & BM_AIPS_PACRM_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP3 (16U) /*!< Bit position for AIPS_PACRM_TP3. */ -#define BM_AIPS_PACRM_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRM_TP3. */ -#define BS_AIPS_PACRM_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP3. */ - -/*! @brief Read current value of the AIPS_PACRM_TP3 field. */ -#define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP3. */ -#define BF_AIPS_PACRM_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP3) & BM_AIPS_PACRM_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP3 (17U) /*!< Bit position for AIPS_PACRM_WP3. */ -#define BM_AIPS_PACRM_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRM_WP3. */ -#define BS_AIPS_PACRM_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP3. */ - -/*! @brief Read current value of the AIPS_PACRM_WP3 field. */ -#define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP3. */ -#define BF_AIPS_PACRM_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP3) & BM_AIPS_PACRM_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP3 (18U) /*!< Bit position for AIPS_PACRM_SP3. */ -#define BM_AIPS_PACRM_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRM_SP3. */ -#define BS_AIPS_PACRM_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP3. */ - -/*! @brief Read current value of the AIPS_PACRM_SP3 field. */ -#define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP3. */ -#define BF_AIPS_PACRM_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP3) & BM_AIPS_PACRM_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP2 (20U) /*!< Bit position for AIPS_PACRM_TP2. */ -#define BM_AIPS_PACRM_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRM_TP2. */ -#define BS_AIPS_PACRM_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP2. */ - -/*! @brief Read current value of the AIPS_PACRM_TP2 field. */ -#define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP2. */ -#define BF_AIPS_PACRM_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP2) & BM_AIPS_PACRM_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP2 (21U) /*!< Bit position for AIPS_PACRM_WP2. */ -#define BM_AIPS_PACRM_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRM_WP2. */ -#define BS_AIPS_PACRM_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP2. */ - -/*! @brief Read current value of the AIPS_PACRM_WP2 field. */ -#define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP2. */ -#define BF_AIPS_PACRM_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP2) & BM_AIPS_PACRM_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP2 (22U) /*!< Bit position for AIPS_PACRM_SP2. */ -#define BM_AIPS_PACRM_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRM_SP2. */ -#define BS_AIPS_PACRM_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP2. */ - -/*! @brief Read current value of the AIPS_PACRM_SP2 field. */ -#define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP2. */ -#define BF_AIPS_PACRM_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP2) & BM_AIPS_PACRM_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP1 (24U) /*!< Bit position for AIPS_PACRM_TP1. */ -#define BM_AIPS_PACRM_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRM_TP1. */ -#define BS_AIPS_PACRM_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP1. */ - -/*! @brief Read current value of the AIPS_PACRM_TP1 field. */ -#define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP1. */ -#define BF_AIPS_PACRM_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP1) & BM_AIPS_PACRM_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP1 (25U) /*!< Bit position for AIPS_PACRM_WP1. */ -#define BM_AIPS_PACRM_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRM_WP1. */ -#define BS_AIPS_PACRM_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP1. */ - -/*! @brief Read current value of the AIPS_PACRM_WP1 field. */ -#define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP1. */ -#define BF_AIPS_PACRM_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP1) & BM_AIPS_PACRM_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP1 (26U) /*!< Bit position for AIPS_PACRM_SP1. */ -#define BM_AIPS_PACRM_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRM_SP1. */ -#define BS_AIPS_PACRM_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP1. */ - -/*! @brief Read current value of the AIPS_PACRM_SP1 field. */ -#define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP1. */ -#define BF_AIPS_PACRM_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP1) & BM_AIPS_PACRM_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRM_TP0 (28U) /*!< Bit position for AIPS_PACRM_TP0. */ -#define BM_AIPS_PACRM_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRM_TP0. */ -#define BS_AIPS_PACRM_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP0. */ - -/*! @brief Read current value of the AIPS_PACRM_TP0 field. */ -#define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRM_TP0. */ -#define BF_AIPS_PACRM_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP0) & BM_AIPS_PACRM_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRM_WP0 (29U) /*!< Bit position for AIPS_PACRM_WP0. */ -#define BM_AIPS_PACRM_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRM_WP0. */ -#define BS_AIPS_PACRM_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP0. */ - -/*! @brief Read current value of the AIPS_PACRM_WP0 field. */ -#define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRM_WP0. */ -#define BF_AIPS_PACRM_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP0) & BM_AIPS_PACRM_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRM, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRM_SP0 (30U) /*!< Bit position for AIPS_PACRM_SP0. */ -#define BM_AIPS_PACRM_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRM_SP0. */ -#define BS_AIPS_PACRM_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP0. */ - -/*! @brief Read current value of the AIPS_PACRM_SP0 field. */ -#define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRM_SP0. */ -#define BF_AIPS_PACRM_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP0) & BM_AIPS_PACRM_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRN - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrn -{ - uint32_t U; - struct _hw_aips_pacrn_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrn_t; - -/*! - * @name Constants and macros for entire AIPS_PACRN register - */ -/*@{*/ -#define HW_AIPS_PACRN_ADDR(x) ((x) + 0x64U) - -#define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x)) -#define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U) -#define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v)) -#define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v))) -#define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v))) -#define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRN bitfields - */ - -/*! - * @name Register AIPS_PACRN, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP7 (0U) /*!< Bit position for AIPS_PACRN_TP7. */ -#define BM_AIPS_PACRN_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRN_TP7. */ -#define BS_AIPS_PACRN_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP7. */ - -/*! @brief Read current value of the AIPS_PACRN_TP7 field. */ -#define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP7. */ -#define BF_AIPS_PACRN_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP7) & BM_AIPS_PACRN_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP7 (1U) /*!< Bit position for AIPS_PACRN_WP7. */ -#define BM_AIPS_PACRN_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRN_WP7. */ -#define BS_AIPS_PACRN_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP7. */ - -/*! @brief Read current value of the AIPS_PACRN_WP7 field. */ -#define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP7. */ -#define BF_AIPS_PACRN_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP7) & BM_AIPS_PACRN_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP7 (2U) /*!< Bit position for AIPS_PACRN_SP7. */ -#define BM_AIPS_PACRN_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRN_SP7. */ -#define BS_AIPS_PACRN_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP7. */ - -/*! @brief Read current value of the AIPS_PACRN_SP7 field. */ -#define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP7. */ -#define BF_AIPS_PACRN_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP7) & BM_AIPS_PACRN_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP6 (4U) /*!< Bit position for AIPS_PACRN_TP6. */ -#define BM_AIPS_PACRN_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRN_TP6. */ -#define BS_AIPS_PACRN_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP6. */ - -/*! @brief Read current value of the AIPS_PACRN_TP6 field. */ -#define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP6. */ -#define BF_AIPS_PACRN_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP6) & BM_AIPS_PACRN_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP6 (5U) /*!< Bit position for AIPS_PACRN_WP6. */ -#define BM_AIPS_PACRN_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRN_WP6. */ -#define BS_AIPS_PACRN_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP6. */ - -/*! @brief Read current value of the AIPS_PACRN_WP6 field. */ -#define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP6. */ -#define BF_AIPS_PACRN_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP6) & BM_AIPS_PACRN_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP6 (6U) /*!< Bit position for AIPS_PACRN_SP6. */ -#define BM_AIPS_PACRN_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRN_SP6. */ -#define BS_AIPS_PACRN_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP6. */ - -/*! @brief Read current value of the AIPS_PACRN_SP6 field. */ -#define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP6. */ -#define BF_AIPS_PACRN_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP6) & BM_AIPS_PACRN_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP5 (8U) /*!< Bit position for AIPS_PACRN_TP5. */ -#define BM_AIPS_PACRN_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRN_TP5. */ -#define BS_AIPS_PACRN_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP5. */ - -/*! @brief Read current value of the AIPS_PACRN_TP5 field. */ -#define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP5. */ -#define BF_AIPS_PACRN_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP5) & BM_AIPS_PACRN_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP5 (9U) /*!< Bit position for AIPS_PACRN_WP5. */ -#define BM_AIPS_PACRN_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRN_WP5. */ -#define BS_AIPS_PACRN_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP5. */ - -/*! @brief Read current value of the AIPS_PACRN_WP5 field. */ -#define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP5. */ -#define BF_AIPS_PACRN_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP5) & BM_AIPS_PACRN_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP5 (10U) /*!< Bit position for AIPS_PACRN_SP5. */ -#define BM_AIPS_PACRN_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRN_SP5. */ -#define BS_AIPS_PACRN_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP5. */ - -/*! @brief Read current value of the AIPS_PACRN_SP5 field. */ -#define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP5. */ -#define BF_AIPS_PACRN_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP5) & BM_AIPS_PACRN_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP4 (12U) /*!< Bit position for AIPS_PACRN_TP4. */ -#define BM_AIPS_PACRN_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRN_TP4. */ -#define BS_AIPS_PACRN_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP4. */ - -/*! @brief Read current value of the AIPS_PACRN_TP4 field. */ -#define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP4. */ -#define BF_AIPS_PACRN_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP4) & BM_AIPS_PACRN_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP4 (13U) /*!< Bit position for AIPS_PACRN_WP4. */ -#define BM_AIPS_PACRN_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRN_WP4. */ -#define BS_AIPS_PACRN_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP4. */ - -/*! @brief Read current value of the AIPS_PACRN_WP4 field. */ -#define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP4. */ -#define BF_AIPS_PACRN_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP4) & BM_AIPS_PACRN_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP4 (14U) /*!< Bit position for AIPS_PACRN_SP4. */ -#define BM_AIPS_PACRN_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRN_SP4. */ -#define BS_AIPS_PACRN_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP4. */ - -/*! @brief Read current value of the AIPS_PACRN_SP4 field. */ -#define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP4. */ -#define BF_AIPS_PACRN_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP4) & BM_AIPS_PACRN_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP3 (16U) /*!< Bit position for AIPS_PACRN_TP3. */ -#define BM_AIPS_PACRN_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRN_TP3. */ -#define BS_AIPS_PACRN_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP3. */ - -/*! @brief Read current value of the AIPS_PACRN_TP3 field. */ -#define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP3. */ -#define BF_AIPS_PACRN_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP3) & BM_AIPS_PACRN_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP3 (17U) /*!< Bit position for AIPS_PACRN_WP3. */ -#define BM_AIPS_PACRN_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRN_WP3. */ -#define BS_AIPS_PACRN_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP3. */ - -/*! @brief Read current value of the AIPS_PACRN_WP3 field. */ -#define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP3. */ -#define BF_AIPS_PACRN_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP3) & BM_AIPS_PACRN_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP3 (18U) /*!< Bit position for AIPS_PACRN_SP3. */ -#define BM_AIPS_PACRN_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRN_SP3. */ -#define BS_AIPS_PACRN_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP3. */ - -/*! @brief Read current value of the AIPS_PACRN_SP3 field. */ -#define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP3. */ -#define BF_AIPS_PACRN_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP3) & BM_AIPS_PACRN_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP2 (20U) /*!< Bit position for AIPS_PACRN_TP2. */ -#define BM_AIPS_PACRN_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRN_TP2. */ -#define BS_AIPS_PACRN_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP2. */ - -/*! @brief Read current value of the AIPS_PACRN_TP2 field. */ -#define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP2. */ -#define BF_AIPS_PACRN_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP2) & BM_AIPS_PACRN_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP2 (21U) /*!< Bit position for AIPS_PACRN_WP2. */ -#define BM_AIPS_PACRN_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRN_WP2. */ -#define BS_AIPS_PACRN_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP2. */ - -/*! @brief Read current value of the AIPS_PACRN_WP2 field. */ -#define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP2. */ -#define BF_AIPS_PACRN_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP2) & BM_AIPS_PACRN_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP2 (22U) /*!< Bit position for AIPS_PACRN_SP2. */ -#define BM_AIPS_PACRN_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRN_SP2. */ -#define BS_AIPS_PACRN_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP2. */ - -/*! @brief Read current value of the AIPS_PACRN_SP2 field. */ -#define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP2. */ -#define BF_AIPS_PACRN_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP2) & BM_AIPS_PACRN_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP1 (24U) /*!< Bit position for AIPS_PACRN_TP1. */ -#define BM_AIPS_PACRN_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRN_TP1. */ -#define BS_AIPS_PACRN_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP1. */ - -/*! @brief Read current value of the AIPS_PACRN_TP1 field. */ -#define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP1. */ -#define BF_AIPS_PACRN_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP1) & BM_AIPS_PACRN_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP1 (25U) /*!< Bit position for AIPS_PACRN_WP1. */ -#define BM_AIPS_PACRN_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRN_WP1. */ -#define BS_AIPS_PACRN_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP1. */ - -/*! @brief Read current value of the AIPS_PACRN_WP1 field. */ -#define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP1. */ -#define BF_AIPS_PACRN_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP1) & BM_AIPS_PACRN_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP1 (26U) /*!< Bit position for AIPS_PACRN_SP1. */ -#define BM_AIPS_PACRN_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRN_SP1. */ -#define BS_AIPS_PACRN_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP1. */ - -/*! @brief Read current value of the AIPS_PACRN_SP1 field. */ -#define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP1. */ -#define BF_AIPS_PACRN_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP1) & BM_AIPS_PACRN_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRN_TP0 (28U) /*!< Bit position for AIPS_PACRN_TP0. */ -#define BM_AIPS_PACRN_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRN_TP0. */ -#define BS_AIPS_PACRN_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP0. */ - -/*! @brief Read current value of the AIPS_PACRN_TP0 field. */ -#define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRN_TP0. */ -#define BF_AIPS_PACRN_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP0) & BM_AIPS_PACRN_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRN_WP0 (29U) /*!< Bit position for AIPS_PACRN_WP0. */ -#define BM_AIPS_PACRN_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRN_WP0. */ -#define BS_AIPS_PACRN_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP0. */ - -/*! @brief Read current value of the AIPS_PACRN_WP0 field. */ -#define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRN_WP0. */ -#define BF_AIPS_PACRN_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP0) & BM_AIPS_PACRN_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRN, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRN_SP0 (30U) /*!< Bit position for AIPS_PACRN_SP0. */ -#define BM_AIPS_PACRN_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRN_SP0. */ -#define BS_AIPS_PACRN_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP0. */ - -/*! @brief Read current value of the AIPS_PACRN_SP0 field. */ -#define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRN_SP0. */ -#define BF_AIPS_PACRN_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP0) & BM_AIPS_PACRN_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRO - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacro -{ - uint32_t U; - struct _hw_aips_pacro_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacro_t; - -/*! - * @name Constants and macros for entire AIPS_PACRO register - */ -/*@{*/ -#define HW_AIPS_PACRO_ADDR(x) ((x) + 0x68U) - -#define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x)) -#define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U) -#define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v)) -#define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v))) -#define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v))) -#define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRO bitfields - */ - -/*! - * @name Register AIPS_PACRO, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP7 (0U) /*!< Bit position for AIPS_PACRO_TP7. */ -#define BM_AIPS_PACRO_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRO_TP7. */ -#define BS_AIPS_PACRO_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP7. */ - -/*! @brief Read current value of the AIPS_PACRO_TP7 field. */ -#define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP7. */ -#define BF_AIPS_PACRO_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP7) & BM_AIPS_PACRO_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP7 (1U) /*!< Bit position for AIPS_PACRO_WP7. */ -#define BM_AIPS_PACRO_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRO_WP7. */ -#define BS_AIPS_PACRO_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP7. */ - -/*! @brief Read current value of the AIPS_PACRO_WP7 field. */ -#define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP7. */ -#define BF_AIPS_PACRO_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP7) & BM_AIPS_PACRO_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP7 (2U) /*!< Bit position for AIPS_PACRO_SP7. */ -#define BM_AIPS_PACRO_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRO_SP7. */ -#define BS_AIPS_PACRO_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP7. */ - -/*! @brief Read current value of the AIPS_PACRO_SP7 field. */ -#define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP7. */ -#define BF_AIPS_PACRO_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP7) & BM_AIPS_PACRO_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP6 (4U) /*!< Bit position for AIPS_PACRO_TP6. */ -#define BM_AIPS_PACRO_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRO_TP6. */ -#define BS_AIPS_PACRO_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP6. */ - -/*! @brief Read current value of the AIPS_PACRO_TP6 field. */ -#define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP6. */ -#define BF_AIPS_PACRO_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP6) & BM_AIPS_PACRO_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP6 (5U) /*!< Bit position for AIPS_PACRO_WP6. */ -#define BM_AIPS_PACRO_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRO_WP6. */ -#define BS_AIPS_PACRO_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP6. */ - -/*! @brief Read current value of the AIPS_PACRO_WP6 field. */ -#define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP6. */ -#define BF_AIPS_PACRO_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP6) & BM_AIPS_PACRO_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP6 (6U) /*!< Bit position for AIPS_PACRO_SP6. */ -#define BM_AIPS_PACRO_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRO_SP6. */ -#define BS_AIPS_PACRO_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP6. */ - -/*! @brief Read current value of the AIPS_PACRO_SP6 field. */ -#define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP6. */ -#define BF_AIPS_PACRO_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP6) & BM_AIPS_PACRO_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP5 (8U) /*!< Bit position for AIPS_PACRO_TP5. */ -#define BM_AIPS_PACRO_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRO_TP5. */ -#define BS_AIPS_PACRO_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP5. */ - -/*! @brief Read current value of the AIPS_PACRO_TP5 field. */ -#define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP5. */ -#define BF_AIPS_PACRO_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP5) & BM_AIPS_PACRO_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP5 (9U) /*!< Bit position for AIPS_PACRO_WP5. */ -#define BM_AIPS_PACRO_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRO_WP5. */ -#define BS_AIPS_PACRO_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP5. */ - -/*! @brief Read current value of the AIPS_PACRO_WP5 field. */ -#define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP5. */ -#define BF_AIPS_PACRO_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP5) & BM_AIPS_PACRO_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP5 (10U) /*!< Bit position for AIPS_PACRO_SP5. */ -#define BM_AIPS_PACRO_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRO_SP5. */ -#define BS_AIPS_PACRO_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP5. */ - -/*! @brief Read current value of the AIPS_PACRO_SP5 field. */ -#define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP5. */ -#define BF_AIPS_PACRO_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP5) & BM_AIPS_PACRO_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP4 (12U) /*!< Bit position for AIPS_PACRO_TP4. */ -#define BM_AIPS_PACRO_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRO_TP4. */ -#define BS_AIPS_PACRO_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP4. */ - -/*! @brief Read current value of the AIPS_PACRO_TP4 field. */ -#define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP4. */ -#define BF_AIPS_PACRO_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP4) & BM_AIPS_PACRO_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP4 (13U) /*!< Bit position for AIPS_PACRO_WP4. */ -#define BM_AIPS_PACRO_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRO_WP4. */ -#define BS_AIPS_PACRO_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP4. */ - -/*! @brief Read current value of the AIPS_PACRO_WP4 field. */ -#define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP4. */ -#define BF_AIPS_PACRO_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP4) & BM_AIPS_PACRO_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP4 (14U) /*!< Bit position for AIPS_PACRO_SP4. */ -#define BM_AIPS_PACRO_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRO_SP4. */ -#define BS_AIPS_PACRO_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP4. */ - -/*! @brief Read current value of the AIPS_PACRO_SP4 field. */ -#define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP4. */ -#define BF_AIPS_PACRO_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP4) & BM_AIPS_PACRO_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP3 (16U) /*!< Bit position for AIPS_PACRO_TP3. */ -#define BM_AIPS_PACRO_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRO_TP3. */ -#define BS_AIPS_PACRO_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP3. */ - -/*! @brief Read current value of the AIPS_PACRO_TP3 field. */ -#define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP3. */ -#define BF_AIPS_PACRO_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP3) & BM_AIPS_PACRO_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP3 (17U) /*!< Bit position for AIPS_PACRO_WP3. */ -#define BM_AIPS_PACRO_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRO_WP3. */ -#define BS_AIPS_PACRO_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP3. */ - -/*! @brief Read current value of the AIPS_PACRO_WP3 field. */ -#define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP3. */ -#define BF_AIPS_PACRO_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP3) & BM_AIPS_PACRO_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP3 (18U) /*!< Bit position for AIPS_PACRO_SP3. */ -#define BM_AIPS_PACRO_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRO_SP3. */ -#define BS_AIPS_PACRO_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP3. */ - -/*! @brief Read current value of the AIPS_PACRO_SP3 field. */ -#define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP3. */ -#define BF_AIPS_PACRO_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP3) & BM_AIPS_PACRO_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP2 (20U) /*!< Bit position for AIPS_PACRO_TP2. */ -#define BM_AIPS_PACRO_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRO_TP2. */ -#define BS_AIPS_PACRO_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP2. */ - -/*! @brief Read current value of the AIPS_PACRO_TP2 field. */ -#define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP2. */ -#define BF_AIPS_PACRO_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP2) & BM_AIPS_PACRO_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP2 (21U) /*!< Bit position for AIPS_PACRO_WP2. */ -#define BM_AIPS_PACRO_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRO_WP2. */ -#define BS_AIPS_PACRO_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP2. */ - -/*! @brief Read current value of the AIPS_PACRO_WP2 field. */ -#define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP2. */ -#define BF_AIPS_PACRO_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP2) & BM_AIPS_PACRO_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP2 (22U) /*!< Bit position for AIPS_PACRO_SP2. */ -#define BM_AIPS_PACRO_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRO_SP2. */ -#define BS_AIPS_PACRO_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP2. */ - -/*! @brief Read current value of the AIPS_PACRO_SP2 field. */ -#define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP2. */ -#define BF_AIPS_PACRO_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP2) & BM_AIPS_PACRO_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP1 (24U) /*!< Bit position for AIPS_PACRO_TP1. */ -#define BM_AIPS_PACRO_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRO_TP1. */ -#define BS_AIPS_PACRO_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP1. */ - -/*! @brief Read current value of the AIPS_PACRO_TP1 field. */ -#define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP1. */ -#define BF_AIPS_PACRO_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP1) & BM_AIPS_PACRO_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP1 (25U) /*!< Bit position for AIPS_PACRO_WP1. */ -#define BM_AIPS_PACRO_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRO_WP1. */ -#define BS_AIPS_PACRO_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP1. */ - -/*! @brief Read current value of the AIPS_PACRO_WP1 field. */ -#define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP1. */ -#define BF_AIPS_PACRO_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP1) & BM_AIPS_PACRO_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP1 (26U) /*!< Bit position for AIPS_PACRO_SP1. */ -#define BM_AIPS_PACRO_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRO_SP1. */ -#define BS_AIPS_PACRO_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP1. */ - -/*! @brief Read current value of the AIPS_PACRO_SP1 field. */ -#define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP1. */ -#define BF_AIPS_PACRO_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP1) & BM_AIPS_PACRO_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRO_TP0 (28U) /*!< Bit position for AIPS_PACRO_TP0. */ -#define BM_AIPS_PACRO_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRO_TP0. */ -#define BS_AIPS_PACRO_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP0. */ - -/*! @brief Read current value of the AIPS_PACRO_TP0 field. */ -#define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRO_TP0. */ -#define BF_AIPS_PACRO_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP0) & BM_AIPS_PACRO_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRO_WP0 (29U) /*!< Bit position for AIPS_PACRO_WP0. */ -#define BM_AIPS_PACRO_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRO_WP0. */ -#define BS_AIPS_PACRO_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP0. */ - -/*! @brief Read current value of the AIPS_PACRO_WP0 field. */ -#define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRO_WP0. */ -#define BF_AIPS_PACRO_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP0) & BM_AIPS_PACRO_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRO, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRO_SP0 (30U) /*!< Bit position for AIPS_PACRO_SP0. */ -#define BM_AIPS_PACRO_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRO_SP0. */ -#define BS_AIPS_PACRO_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP0. */ - -/*! @brief Read current value of the AIPS_PACRO_SP0 field. */ -#define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRO_SP0. */ -#define BF_AIPS_PACRO_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP0) & BM_AIPS_PACRO_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRP - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW) - * - * Reset value: 0x44444444U - * - * This section describes PACR registers E-P, which control peripheral slots - * 32-127. See PACRPeripheral Access Control Register for the description of these - * registers. - */ -typedef union _hw_aips_pacrp -{ - uint32_t U; - struct _hw_aips_pacrp_bitfields - { - uint32_t TP7 : 1; /*!< [0] Trusted Protect */ - uint32_t WP7 : 1; /*!< [1] Write Protect */ - uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TP6 : 1; /*!< [4] Trusted Protect */ - uint32_t WP6 : 1; /*!< [5] Write Protect */ - uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t TP5 : 1; /*!< [8] Trusted Protect */ - uint32_t WP5 : 1; /*!< [9] Write Protect */ - uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t TP4 : 1; /*!< [12] Trusted Protect */ - uint32_t WP4 : 1; /*!< [13] Write Protect */ - uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t TP3 : 1; /*!< [16] Trusted Protect */ - uint32_t WP3 : 1; /*!< [17] Write Protect */ - uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t TP2 : 1; /*!< [20] Trusted Protect */ - uint32_t WP2 : 1; /*!< [21] Write Protect */ - uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ - uint32_t RESERVED5 : 1; /*!< [23] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED6 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED7 : 1; /*!< [31] */ - } B; -} hw_aips_pacrp_t; - -/*! - * @name Constants and macros for entire AIPS_PACRP register - */ -/*@{*/ -#define HW_AIPS_PACRP_ADDR(x) ((x) + 0x6CU) - -#define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x)) -#define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U) -#define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v)) -#define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v))) -#define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v))) -#define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRP bitfields - */ - -/*! - * @name Register AIPS_PACRP, field TP7[0] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP7 (0U) /*!< Bit position for AIPS_PACRP_TP7. */ -#define BM_AIPS_PACRP_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRP_TP7. */ -#define BS_AIPS_PACRP_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP7. */ - -/*! @brief Read current value of the AIPS_PACRP_TP7 field. */ -#define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP7. */ -#define BF_AIPS_PACRP_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP7) & BM_AIPS_PACRP_TP7) - -/*! @brief Set the TP7 field to a new value. */ -#define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP7[1] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP7 (1U) /*!< Bit position for AIPS_PACRP_WP7. */ -#define BM_AIPS_PACRP_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRP_WP7. */ -#define BS_AIPS_PACRP_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP7. */ - -/*! @brief Read current value of the AIPS_PACRP_WP7 field. */ -#define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP7. */ -#define BF_AIPS_PACRP_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP7) & BM_AIPS_PACRP_WP7) - -/*! @brief Set the WP7 field to a new value. */ -#define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP7[2] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP7 (2U) /*!< Bit position for AIPS_PACRP_SP7. */ -#define BM_AIPS_PACRP_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRP_SP7. */ -#define BS_AIPS_PACRP_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP7. */ - -/*! @brief Read current value of the AIPS_PACRP_SP7 field. */ -#define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP7. */ -#define BF_AIPS_PACRP_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP7) & BM_AIPS_PACRP_SP7) - -/*! @brief Set the SP7 field to a new value. */ -#define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP6[4] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP6 (4U) /*!< Bit position for AIPS_PACRP_TP6. */ -#define BM_AIPS_PACRP_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRP_TP6. */ -#define BS_AIPS_PACRP_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP6. */ - -/*! @brief Read current value of the AIPS_PACRP_TP6 field. */ -#define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP6. */ -#define BF_AIPS_PACRP_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP6) & BM_AIPS_PACRP_TP6) - -/*! @brief Set the TP6 field to a new value. */ -#define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP6[5] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP6 (5U) /*!< Bit position for AIPS_PACRP_WP6. */ -#define BM_AIPS_PACRP_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRP_WP6. */ -#define BS_AIPS_PACRP_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP6. */ - -/*! @brief Read current value of the AIPS_PACRP_WP6 field. */ -#define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP6. */ -#define BF_AIPS_PACRP_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP6) & BM_AIPS_PACRP_WP6) - -/*! @brief Set the WP6 field to a new value. */ -#define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP6[6] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP6 (6U) /*!< Bit position for AIPS_PACRP_SP6. */ -#define BM_AIPS_PACRP_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRP_SP6. */ -#define BS_AIPS_PACRP_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP6. */ - -/*! @brief Read current value of the AIPS_PACRP_SP6 field. */ -#define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP6. */ -#define BF_AIPS_PACRP_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP6) & BM_AIPS_PACRP_SP6) - -/*! @brief Set the SP6 field to a new value. */ -#define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP5[8] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP5 (8U) /*!< Bit position for AIPS_PACRP_TP5. */ -#define BM_AIPS_PACRP_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRP_TP5. */ -#define BS_AIPS_PACRP_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP5. */ - -/*! @brief Read current value of the AIPS_PACRP_TP5 field. */ -#define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP5. */ -#define BF_AIPS_PACRP_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP5) & BM_AIPS_PACRP_TP5) - -/*! @brief Set the TP5 field to a new value. */ -#define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP5[9] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP5 (9U) /*!< Bit position for AIPS_PACRP_WP5. */ -#define BM_AIPS_PACRP_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRP_WP5. */ -#define BS_AIPS_PACRP_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP5. */ - -/*! @brief Read current value of the AIPS_PACRP_WP5 field. */ -#define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP5. */ -#define BF_AIPS_PACRP_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP5) & BM_AIPS_PACRP_WP5) - -/*! @brief Set the WP5 field to a new value. */ -#define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP5[10] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP5 (10U) /*!< Bit position for AIPS_PACRP_SP5. */ -#define BM_AIPS_PACRP_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRP_SP5. */ -#define BS_AIPS_PACRP_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP5. */ - -/*! @brief Read current value of the AIPS_PACRP_SP5 field. */ -#define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP5. */ -#define BF_AIPS_PACRP_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP5) & BM_AIPS_PACRP_SP5) - -/*! @brief Set the SP5 field to a new value. */ -#define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP4[12] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP4 (12U) /*!< Bit position for AIPS_PACRP_TP4. */ -#define BM_AIPS_PACRP_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRP_TP4. */ -#define BS_AIPS_PACRP_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP4. */ - -/*! @brief Read current value of the AIPS_PACRP_TP4 field. */ -#define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP4. */ -#define BF_AIPS_PACRP_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP4) & BM_AIPS_PACRP_TP4) - -/*! @brief Set the TP4 field to a new value. */ -#define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP4[13] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP4 (13U) /*!< Bit position for AIPS_PACRP_WP4. */ -#define BM_AIPS_PACRP_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRP_WP4. */ -#define BS_AIPS_PACRP_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP4. */ - -/*! @brief Read current value of the AIPS_PACRP_WP4 field. */ -#define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP4. */ -#define BF_AIPS_PACRP_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP4) & BM_AIPS_PACRP_WP4) - -/*! @brief Set the WP4 field to a new value. */ -#define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP4[14] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP4 (14U) /*!< Bit position for AIPS_PACRP_SP4. */ -#define BM_AIPS_PACRP_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRP_SP4. */ -#define BS_AIPS_PACRP_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP4. */ - -/*! @brief Read current value of the AIPS_PACRP_SP4 field. */ -#define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP4. */ -#define BF_AIPS_PACRP_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP4) & BM_AIPS_PACRP_SP4) - -/*! @brief Set the SP4 field to a new value. */ -#define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP3[16] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP3 (16U) /*!< Bit position for AIPS_PACRP_TP3. */ -#define BM_AIPS_PACRP_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRP_TP3. */ -#define BS_AIPS_PACRP_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP3. */ - -/*! @brief Read current value of the AIPS_PACRP_TP3 field. */ -#define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP3. */ -#define BF_AIPS_PACRP_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP3) & BM_AIPS_PACRP_TP3) - -/*! @brief Set the TP3 field to a new value. */ -#define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP3[17] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP3 (17U) /*!< Bit position for AIPS_PACRP_WP3. */ -#define BM_AIPS_PACRP_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRP_WP3. */ -#define BS_AIPS_PACRP_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP3. */ - -/*! @brief Read current value of the AIPS_PACRP_WP3 field. */ -#define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP3. */ -#define BF_AIPS_PACRP_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP3) & BM_AIPS_PACRP_WP3) - -/*! @brief Set the WP3 field to a new value. */ -#define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP3[18] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP3 (18U) /*!< Bit position for AIPS_PACRP_SP3. */ -#define BM_AIPS_PACRP_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRP_SP3. */ -#define BS_AIPS_PACRP_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP3. */ - -/*! @brief Read current value of the AIPS_PACRP_SP3 field. */ -#define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP3. */ -#define BF_AIPS_PACRP_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP3) & BM_AIPS_PACRP_SP3) - -/*! @brief Set the SP3 field to a new value. */ -#define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP2[20] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP2 (20U) /*!< Bit position for AIPS_PACRP_TP2. */ -#define BM_AIPS_PACRP_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRP_TP2. */ -#define BS_AIPS_PACRP_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP2. */ - -/*! @brief Read current value of the AIPS_PACRP_TP2 field. */ -#define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP2. */ -#define BF_AIPS_PACRP_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP2) & BM_AIPS_PACRP_TP2) - -/*! @brief Set the TP2 field to a new value. */ -#define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP2[21] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP2 (21U) /*!< Bit position for AIPS_PACRP_WP2. */ -#define BM_AIPS_PACRP_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRP_WP2. */ -#define BS_AIPS_PACRP_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP2. */ - -/*! @brief Read current value of the AIPS_PACRP_WP2 field. */ -#define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP2. */ -#define BF_AIPS_PACRP_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP2) & BM_AIPS_PACRP_WP2) - -/*! @brief Set the WP2 field to a new value. */ -#define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP2[22] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP2 (22U) /*!< Bit position for AIPS_PACRP_SP2. */ -#define BM_AIPS_PACRP_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRP_SP2. */ -#define BS_AIPS_PACRP_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP2. */ - -/*! @brief Read current value of the AIPS_PACRP_SP2 field. */ -#define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP2. */ -#define BF_AIPS_PACRP_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP2) & BM_AIPS_PACRP_SP2) - -/*! @brief Set the SP2 field to a new value. */ -#define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP1 (24U) /*!< Bit position for AIPS_PACRP_TP1. */ -#define BM_AIPS_PACRP_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRP_TP1. */ -#define BS_AIPS_PACRP_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP1. */ - -/*! @brief Read current value of the AIPS_PACRP_TP1 field. */ -#define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP1. */ -#define BF_AIPS_PACRP_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP1) & BM_AIPS_PACRP_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP1 (25U) /*!< Bit position for AIPS_PACRP_WP1. */ -#define BM_AIPS_PACRP_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRP_WP1. */ -#define BS_AIPS_PACRP_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP1. */ - -/*! @brief Read current value of the AIPS_PACRP_WP1 field. */ -#define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP1. */ -#define BF_AIPS_PACRP_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP1) & BM_AIPS_PACRP_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master must - * be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP1 (26U) /*!< Bit position for AIPS_PACRP_SP1. */ -#define BM_AIPS_PACRP_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRP_SP1. */ -#define BS_AIPS_PACRP_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP1. */ - -/*! @brief Read current value of the AIPS_PACRP_SP1 field. */ -#define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP1. */ -#define BF_AIPS_PACRP_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP1) & BM_AIPS_PACRP_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this bit is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRP_TP0 (28U) /*!< Bit position for AIPS_PACRP_TP0. */ -#define BM_AIPS_PACRP_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRP_TP0. */ -#define BS_AIPS_PACRP_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP0. */ - -/*! @brief Read current value of the AIPS_PACRP_TP0 field. */ -#define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRP_TP0. */ -#define BF_AIPS_PACRP_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP0) & BM_AIPS_PACRP_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRP_WP0 (29U) /*!< Bit position for AIPS_PACRP_WP0. */ -#define BM_AIPS_PACRP_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRP_WP0. */ -#define BS_AIPS_PACRP_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP0. */ - -/*! @brief Read current value of the AIPS_PACRP_WP0 field. */ -#define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRP_WP0. */ -#define BF_AIPS_PACRP_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP0) & BM_AIPS_PACRP_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRP, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRP_SP0 (30U) /*!< Bit position for AIPS_PACRP_SP0. */ -#define BM_AIPS_PACRP_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRP_SP0. */ -#define BS_AIPS_PACRP_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP0. */ - -/*! @brief Read current value of the AIPS_PACRP_SP0 field. */ -#define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRP_SP0. */ -#define BF_AIPS_PACRP_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP0) & BM_AIPS_PACRP_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AIPS_PACRU - Peripheral Access Control Register - ******************************************************************************/ - -/*! - * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW) - * - * Reset value: 0x44000000U - * - * PACRU defines the access levels for the two global spaces. - */ -typedef union _hw_aips_pacru -{ - uint32_t U; - struct _hw_aips_pacru_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t TP1 : 1; /*!< [24] Trusted Protect */ - uint32_t WP1 : 1; /*!< [25] Write Protect */ - uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ - uint32_t RESERVED1 : 1; /*!< [27] */ - uint32_t TP0 : 1; /*!< [28] Trusted Protect */ - uint32_t WP0 : 1; /*!< [29] Write Protect */ - uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ - uint32_t RESERVED2 : 1; /*!< [31] */ - } B; -} hw_aips_pacru_t; - -/*! - * @name Constants and macros for entire AIPS_PACRU register - */ -/*@{*/ -#define HW_AIPS_PACRU_ADDR(x) ((x) + 0x80U) - -#define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x)) -#define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U) -#define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v)) -#define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v))) -#define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v))) -#define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AIPS_PACRU bitfields - */ - -/*! - * @name Register AIPS_PACRU, field TP1[24] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRU_TP1 (24U) /*!< Bit position for AIPS_PACRU_TP1. */ -#define BM_AIPS_PACRU_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRU_TP1. */ -#define BS_AIPS_PACRU_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP1. */ - -/*! @brief Read current value of the AIPS_PACRU_TP1 field. */ -#define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1)) - -/*! @brief Format value for bitfield AIPS_PACRU_TP1. */ -#define BF_AIPS_PACRU_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP1) & BM_AIPS_PACRU_TP1) - -/*! @brief Set the TP1 field to a new value. */ -#define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRU, field WP1[25] (RW) - * - * Determines whether the peripheral allows write accesss. When this bit is set - * and a write access is attempted, access terminates with an error response and - * no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRU_WP1 (25U) /*!< Bit position for AIPS_PACRU_WP1. */ -#define BM_AIPS_PACRU_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRU_WP1. */ -#define BS_AIPS_PACRU_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP1. */ - -/*! @brief Read current value of the AIPS_PACRU_WP1 field. */ -#define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1)) - -/*! @brief Format value for bitfield AIPS_PACRU_WP1. */ -#define BF_AIPS_PACRU_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP1) & BM_AIPS_PACRU_WP1) - -/*! @brief Set the WP1 field to a new value. */ -#define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRU, field SP1[26] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * accesses. When this field is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control field for the master - * must be set. If not, access terminates with an error response and no peripheral - * access initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRU_SP1 (26U) /*!< Bit position for AIPS_PACRU_SP1. */ -#define BM_AIPS_PACRU_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRU_SP1. */ -#define BS_AIPS_PACRU_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP1. */ - -/*! @brief Read current value of the AIPS_PACRU_SP1 field. */ -#define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1)) - -/*! @brief Format value for bitfield AIPS_PACRU_SP1. */ -#define BF_AIPS_PACRU_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP1) & BM_AIPS_PACRU_SP1) - -/*! @brief Set the SP1 field to a new value. */ -#define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRU, field TP0[28] (RW) - * - * Determines whether the peripheral allows accesses from an untrusted master. - * When this field is set and an access is attempted by an untrusted master, the - * access terminates with an error response and no peripheral access initiates. - * - * Values: - * - 0 - Accesses from an untrusted master are allowed. - * - 1 - Accesses from an untrusted master are not allowed. - */ -/*@{*/ -#define BP_AIPS_PACRU_TP0 (28U) /*!< Bit position for AIPS_PACRU_TP0. */ -#define BM_AIPS_PACRU_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRU_TP0. */ -#define BS_AIPS_PACRU_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP0. */ - -/*! @brief Read current value of the AIPS_PACRU_TP0 field. */ -#define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0)) - -/*! @brief Format value for bitfield AIPS_PACRU_TP0. */ -#define BF_AIPS_PACRU_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP0) & BM_AIPS_PACRU_TP0) - -/*! @brief Set the TP0 field to a new value. */ -#define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRU, field WP0[29] (RW) - * - * Determines whether the peripheral allows write accesses. When this field is - * set and a write access is attempted, access terminates with an error response - * and no peripheral access initiates. - * - * Values: - * - 0 - This peripheral allows write accesses. - * - 1 - This peripheral is write protected. - */ -/*@{*/ -#define BP_AIPS_PACRU_WP0 (29U) /*!< Bit position for AIPS_PACRU_WP0. */ -#define BM_AIPS_PACRU_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRU_WP0. */ -#define BS_AIPS_PACRU_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP0. */ - -/*! @brief Read current value of the AIPS_PACRU_WP0 field. */ -#define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0)) - -/*! @brief Format value for bitfield AIPS_PACRU_WP0. */ -#define BF_AIPS_PACRU_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP0) & BM_AIPS_PACRU_WP0) - -/*! @brief Set the WP0 field to a new value. */ -#define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v)) -/*@}*/ - -/*! - * @name Register AIPS_PACRU, field SP0[30] (RW) - * - * Determines whether the peripheral requires supervisor privilege level for - * access. When this bit is set, the master privilege level must indicate the - * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be - * set. If not, access terminates with an error response and no peripheral access - * initiates. - * - * Values: - * - 0 - This peripheral does not require supervisor privilege level for - * accesses. - * - 1 - This peripheral requires supervisor privilege level for accesses. - */ -/*@{*/ -#define BP_AIPS_PACRU_SP0 (30U) /*!< Bit position for AIPS_PACRU_SP0. */ -#define BM_AIPS_PACRU_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRU_SP0. */ -#define BS_AIPS_PACRU_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP0. */ - -/*! @brief Read current value of the AIPS_PACRU_SP0 field. */ -#define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0)) - -/*! @brief Format value for bitfield AIPS_PACRU_SP0. */ -#define BF_AIPS_PACRU_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP0) & BM_AIPS_PACRU_SP0) - -/*! @brief Set the SP0 field to a new value. */ -#define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_aips_t - module struct - ******************************************************************************/ -/*! - * @brief All AIPS module registers. - */ -#pragma pack(1) -typedef struct _hw_aips -{ - __IO hw_aips_mpra_t MPRA; /*!< [0x0] Master Privilege Register A */ - uint8_t _reserved0[28]; - __IO hw_aips_pacra_t PACRA; /*!< [0x20] Peripheral Access Control Register */ - __IO hw_aips_pacrb_t PACRB; /*!< [0x24] Peripheral Access Control Register */ - __IO hw_aips_pacrc_t PACRC; /*!< [0x28] Peripheral Access Control Register */ - __IO hw_aips_pacrd_t PACRD; /*!< [0x2C] Peripheral Access Control Register */ - uint8_t _reserved1[16]; - __IO hw_aips_pacre_t PACRE; /*!< [0x40] Peripheral Access Control Register */ - __IO hw_aips_pacrf_t PACRF; /*!< [0x44] Peripheral Access Control Register */ - __IO hw_aips_pacrg_t PACRG; /*!< [0x48] Peripheral Access Control Register */ - __IO hw_aips_pacrh_t PACRH; /*!< [0x4C] Peripheral Access Control Register */ - __IO hw_aips_pacri_t PACRI; /*!< [0x50] Peripheral Access Control Register */ - __IO hw_aips_pacrj_t PACRJ; /*!< [0x54] Peripheral Access Control Register */ - __IO hw_aips_pacrk_t PACRK; /*!< [0x58] Peripheral Access Control Register */ - __IO hw_aips_pacrl_t PACRL; /*!< [0x5C] Peripheral Access Control Register */ - __IO hw_aips_pacrm_t PACRM; /*!< [0x60] Peripheral Access Control Register */ - __IO hw_aips_pacrn_t PACRN; /*!< [0x64] Peripheral Access Control Register */ - __IO hw_aips_pacro_t PACRO; /*!< [0x68] Peripheral Access Control Register */ - __IO hw_aips_pacrp_t PACRP; /*!< [0x6C] Peripheral Access Control Register */ - uint8_t _reserved2[16]; - __IO hw_aips_pacru_t PACRU; /*!< [0x80] Peripheral Access Control Register */ -} hw_aips_t; -#pragma pack() - -/*! @brief Macro to access all AIPS registers. */ -/*! @param x AIPS module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_AIPS(AIPS0_BASE). */ -#define HW_AIPS(x) (*(hw_aips_t *)(x)) - -#endif /* __HW_AIPS_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h deleted file mode 100644 index aff1b368c98..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h +++ /dev/null @@ -1,1030 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_AXBS_REGISTERS_H__ -#define __HW_AXBS_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 AXBS - * - * Crossbar switch - * - * Registers defined in this header file: - * - HW_AXBS_PRSn - Priority Registers Slave - * - HW_AXBS_CRSn - Control Register - * - HW_AXBS_MGPCR0 - Master General Purpose Control Register - * - HW_AXBS_MGPCR1 - Master General Purpose Control Register - * - HW_AXBS_MGPCR2 - Master General Purpose Control Register - * - HW_AXBS_MGPCR3 - Master General Purpose Control Register - * - HW_AXBS_MGPCR4 - Master General Purpose Control Register - * - HW_AXBS_MGPCR5 - Master General Purpose Control Register - * - * - hw_axbs_t - Struct containing all module registers. - */ - -#define HW_AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */ - -/******************************************************************************* - * HW_AXBS_PRSn - Priority Registers Slave - ******************************************************************************/ - -/*! - * @brief HW_AXBS_PRSn - Priority Registers Slave (RW) - * - * Reset value: 0x00543210U - * - * The priority registers (PRSn) set the priority of each master port on a per - * slave port basis and reside in each slave port. The priority register can be - * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn - * register can only be read; attempts to write to it have no effect on PRSn and - * result in a bus-error response to the master initiating the write. Two available - * masters must not be programmed with the same priority level. Attempts to - * program two or more masters with the same priority level result in a bus-error - * response and the PRSn is not updated. Valid values for the Mn priority fields - * depend on which masters are available on the chip. This information can be found in - * the chip-specific information for the crossbar. If the chip contains less - * than five masters, values 0 to 3 are valid. Writing other values will result in - * an error. If the chip contains five or more masters, valid values are 0 to n-1, - * where n is the number of masters attached to the AXBS module. Other values - * will result in an error. - */ -typedef union _hw_axbs_prsn -{ - uint32_t U; - struct _hw_axbs_prsn_bitfields - { - uint32_t M0 : 3; /*!< [2:0] Master 0 Priority. Sets the arbitration - * priority for this port on the associated slave port. */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t M1 : 3; /*!< [6:4] Master 1 Priority. Sets the arbitration - * priority for this port on the associated slave port. */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t M2 : 3; /*!< [10:8] Master 2 Priority. Sets the arbitration - * priority for this port on the associated slave port. */ - uint32_t RESERVED2 : 1; /*!< [11] */ - uint32_t M3 : 3; /*!< [14:12] Master 3 Priority. Sets the arbitration - * priority for this port on the associated slave port. */ - uint32_t RESERVED3 : 1; /*!< [15] */ - uint32_t M4 : 3; /*!< [18:16] Master 4 Priority. Sets the arbitration - * priority for this port on the associated slave port. */ - uint32_t RESERVED4 : 1; /*!< [19] */ - uint32_t M5 : 3; /*!< [22:20] Master 5 Priority. Sets the arbitration - * priority for this port on the associated slave port. */ - uint32_t RESERVED5 : 9; /*!< [31:23] */ - } B; -} hw_axbs_prsn_t; - -/*! - * @name Constants and macros for entire AXBS_PRSn register - */ -/*@{*/ -#define HW_AXBS_PRSn_COUNT (5U) - -#define HW_AXBS_PRSn_ADDR(x, n) ((x) + 0x0U + (0x100U * (n))) - -#define HW_AXBS_PRSn(x, n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(x, n)) -#define HW_AXBS_PRSn_RD(x, n) (HW_AXBS_PRSn(x, n).U) -#define HW_AXBS_PRSn_WR(x, n, v) (HW_AXBS_PRSn(x, n).U = (v)) -#define HW_AXBS_PRSn_SET(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) | (v))) -#define HW_AXBS_PRSn_CLR(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) & ~(v))) -#define HW_AXBS_PRSn_TOG(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_PRSn bitfields - */ - -/*! - * @name Register AXBS_PRSn, field M0[2:0] (RW) - * - * Values: - * - 000 - This master has level 1, or highest, priority when accessing the - * slave port. - * - 001 - This master has level 2 priority when accessing the slave port. - * - 010 - This master has level 3 priority when accessing the slave port. - * - 011 - This master has level 4 priority when accessing the slave port. - * - 100 - This master has level 5 priority when accessing the slave port. - * - 101 - This master has level 6 priority when accessing the slave port. - * - 110 - This master has level 7 priority when accessing the slave port. - * - 111 - This master has level 8, or lowest, priority when accessing the slave - * port. - */ -/*@{*/ -#define BP_AXBS_PRSn_M0 (0U) /*!< Bit position for AXBS_PRSn_M0. */ -#define BM_AXBS_PRSn_M0 (0x00000007U) /*!< Bit mask for AXBS_PRSn_M0. */ -#define BS_AXBS_PRSn_M0 (3U) /*!< Bit field size in bits for AXBS_PRSn_M0. */ - -/*! @brief Read current value of the AXBS_PRSn_M0 field. */ -#define BR_AXBS_PRSn_M0(x, n) (HW_AXBS_PRSn(x, n).B.M0) - -/*! @brief Format value for bitfield AXBS_PRSn_M0. */ -#define BF_AXBS_PRSn_M0(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M0) & BM_AXBS_PRSn_M0) - -/*! @brief Set the M0 field to a new value. */ -#define BW_AXBS_PRSn_M0(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v))) -/*@}*/ - -/*! - * @name Register AXBS_PRSn, field M1[6:4] (RW) - * - * Values: - * - 000 - This master has level 1, or highest, priority when accessing the - * slave port. - * - 001 - This master has level 2 priority when accessing the slave port. - * - 010 - This master has level 3 priority when accessing the slave port. - * - 011 - This master has level 4 priority when accessing the slave port. - * - 100 - This master has level 5 priority when accessing the slave port. - * - 101 - This master has level 6 priority when accessing the slave port. - * - 110 - This master has level 7 priority when accessing the slave port. - * - 111 - This master has level 8, or lowest, priority when accessing the slave - * port. - */ -/*@{*/ -#define BP_AXBS_PRSn_M1 (4U) /*!< Bit position for AXBS_PRSn_M1. */ -#define BM_AXBS_PRSn_M1 (0x00000070U) /*!< Bit mask for AXBS_PRSn_M1. */ -#define BS_AXBS_PRSn_M1 (3U) /*!< Bit field size in bits for AXBS_PRSn_M1. */ - -/*! @brief Read current value of the AXBS_PRSn_M1 field. */ -#define BR_AXBS_PRSn_M1(x, n) (HW_AXBS_PRSn(x, n).B.M1) - -/*! @brief Format value for bitfield AXBS_PRSn_M1. */ -#define BF_AXBS_PRSn_M1(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M1) & BM_AXBS_PRSn_M1) - -/*! @brief Set the M1 field to a new value. */ -#define BW_AXBS_PRSn_M1(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v))) -/*@}*/ - -/*! - * @name Register AXBS_PRSn, field M2[10:8] (RW) - * - * Values: - * - 000 - This master has level 1, or highest, priority when accessing the - * slave port. - * - 001 - This master has level 2 priority when accessing the slave port. - * - 010 - This master has level 3 priority when accessing the slave port. - * - 011 - This master has level 4 priority when accessing the slave port. - * - 100 - This master has level 5 priority when accessing the slave port. - * - 101 - This master has level 6 priority when accessing the slave port. - * - 110 - This master has level 7 priority when accessing the slave port. - * - 111 - This master has level 8, or lowest, priority when accessing the slave - * port. - */ -/*@{*/ -#define BP_AXBS_PRSn_M2 (8U) /*!< Bit position for AXBS_PRSn_M2. */ -#define BM_AXBS_PRSn_M2 (0x00000700U) /*!< Bit mask for AXBS_PRSn_M2. */ -#define BS_AXBS_PRSn_M2 (3U) /*!< Bit field size in bits for AXBS_PRSn_M2. */ - -/*! @brief Read current value of the AXBS_PRSn_M2 field. */ -#define BR_AXBS_PRSn_M2(x, n) (HW_AXBS_PRSn(x, n).B.M2) - -/*! @brief Format value for bitfield AXBS_PRSn_M2. */ -#define BF_AXBS_PRSn_M2(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M2) & BM_AXBS_PRSn_M2) - -/*! @brief Set the M2 field to a new value. */ -#define BW_AXBS_PRSn_M2(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v))) -/*@}*/ - -/*! - * @name Register AXBS_PRSn, field M3[14:12] (RW) - * - * Values: - * - 000 - This master has level 1, or highest, priority when accessing the - * slave port. - * - 001 - This master has level 2 priority when accessing the slave port. - * - 010 - This master has level 3 priority when accessing the slave port. - * - 011 - This master has level 4 priority when accessing the slave port. - * - 100 - This master has level 5 priority when accessing the slave port. - * - 101 - This master has level 6 priority when accessing the slave port. - * - 110 - This master has level 7 priority when accessing the slave port. - * - 111 - This master has level 8, or lowest, priority when accessing the slave - * port. - */ -/*@{*/ -#define BP_AXBS_PRSn_M3 (12U) /*!< Bit position for AXBS_PRSn_M3. */ -#define BM_AXBS_PRSn_M3 (0x00007000U) /*!< Bit mask for AXBS_PRSn_M3. */ -#define BS_AXBS_PRSn_M3 (3U) /*!< Bit field size in bits for AXBS_PRSn_M3. */ - -/*! @brief Read current value of the AXBS_PRSn_M3 field. */ -#define BR_AXBS_PRSn_M3(x, n) (HW_AXBS_PRSn(x, n).B.M3) - -/*! @brief Format value for bitfield AXBS_PRSn_M3. */ -#define BF_AXBS_PRSn_M3(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M3) & BM_AXBS_PRSn_M3) - -/*! @brief Set the M3 field to a new value. */ -#define BW_AXBS_PRSn_M3(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v))) -/*@}*/ - -/*! - * @name Register AXBS_PRSn, field M4[18:16] (RW) - * - * Values: - * - 000 - This master has level 1, or highest, priority when accessing the - * slave port. - * - 001 - This master has level 2 priority when accessing the slave port. - * - 010 - This master has level 3 priority when accessing the slave port. - * - 011 - This master has level 4 priority when accessing the slave port. - * - 100 - This master has level 5 priority when accessing the slave port. - * - 101 - This master has level 6 priority when accessing the slave port. - * - 110 - This master has level 7 priority when accessing the slave port. - * - 111 - This master has level 8, or lowest, priority when accessing the slave - * port. - */ -/*@{*/ -#define BP_AXBS_PRSn_M4 (16U) /*!< Bit position for AXBS_PRSn_M4. */ -#define BM_AXBS_PRSn_M4 (0x00070000U) /*!< Bit mask for AXBS_PRSn_M4. */ -#define BS_AXBS_PRSn_M4 (3U) /*!< Bit field size in bits for AXBS_PRSn_M4. */ - -/*! @brief Read current value of the AXBS_PRSn_M4 field. */ -#define BR_AXBS_PRSn_M4(x, n) (HW_AXBS_PRSn(x, n).B.M4) - -/*! @brief Format value for bitfield AXBS_PRSn_M4. */ -#define BF_AXBS_PRSn_M4(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M4) & BM_AXBS_PRSn_M4) - -/*! @brief Set the M4 field to a new value. */ -#define BW_AXBS_PRSn_M4(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v))) -/*@}*/ - -/*! - * @name Register AXBS_PRSn, field M5[22:20] (RW) - * - * Values: - * - 000 - This master has level 1, or highest, priority when accessing the - * slave port. - * - 001 - This master has level 2 priority when accessing the slave port. - * - 010 - This master has level 3 priority when accessing the slave port. - * - 011 - This master has level 4 priority when accessing the slave port. - * - 100 - This master has level 5 priority when accessing the slave port. - * - 101 - This master has level 6 priority when accessing the slave port. - * - 110 - This master has level 7 priority when accessing the slave port. - * - 111 - This master has level 8, or lowest, priority when accessing the slave - * port. - */ -/*@{*/ -#define BP_AXBS_PRSn_M5 (20U) /*!< Bit position for AXBS_PRSn_M5. */ -#define BM_AXBS_PRSn_M5 (0x00700000U) /*!< Bit mask for AXBS_PRSn_M5. */ -#define BS_AXBS_PRSn_M5 (3U) /*!< Bit field size in bits for AXBS_PRSn_M5. */ - -/*! @brief Read current value of the AXBS_PRSn_M5 field. */ -#define BR_AXBS_PRSn_M5(x, n) (HW_AXBS_PRSn(x, n).B.M5) - -/*! @brief Format value for bitfield AXBS_PRSn_M5. */ -#define BF_AXBS_PRSn_M5(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M5) & BM_AXBS_PRSn_M5) - -/*! @brief Set the M5 field to a new value. */ -#define BW_AXBS_PRSn_M5(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v))) -/*@}*/ -/******************************************************************************* - * HW_AXBS_CRSn - Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_CRSn - Control Register (RW) - * - * Reset value: 0x00000000U - * - * These registers control several features of each slave port and must be - * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read; - * attempts to write to it have no effect and result in an error response. - */ -typedef union _hw_axbs_crsn -{ - uint32_t U; - struct _hw_axbs_crsn_bitfields - { - uint32_t PARK : 3; /*!< [2:0] Park */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t PCTL : 2; /*!< [5:4] Parking Control */ - uint32_t RESERVED1 : 2; /*!< [7:6] */ - uint32_t ARB : 2; /*!< [9:8] Arbitration Mode */ - uint32_t RESERVED2 : 20; /*!< [29:10] */ - uint32_t HLP : 1; /*!< [30] Halt Low Priority */ - uint32_t RO : 1; /*!< [31] Read Only */ - } B; -} hw_axbs_crsn_t; - -/*! - * @name Constants and macros for entire AXBS_CRSn register - */ -/*@{*/ -#define HW_AXBS_CRSn_COUNT (5U) - -#define HW_AXBS_CRSn_ADDR(x, n) ((x) + 0x10U + (0x100U * (n))) - -#define HW_AXBS_CRSn(x, n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(x, n)) -#define HW_AXBS_CRSn_RD(x, n) (HW_AXBS_CRSn(x, n).U) -#define HW_AXBS_CRSn_WR(x, n, v) (HW_AXBS_CRSn(x, n).U = (v)) -#define HW_AXBS_CRSn_SET(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) | (v))) -#define HW_AXBS_CRSn_CLR(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) & ~(v))) -#define HW_AXBS_CRSn_TOG(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_CRSn bitfields - */ - -/*! - * @name Register AXBS_CRSn, field PARK[2:0] (RW) - * - * Determines which master port the current slave port parks on when no masters - * are actively making requests and the PCTL bits are cleared. Select only master - * ports that are present on the chip. Otherwise, undefined behavior might occur. - * - * Values: - * - 000 - Park on master port M0 - * - 001 - Park on master port M1 - * - 010 - Park on master port M2 - * - 011 - Park on master port M3 - * - 100 - Park on master port M4 - * - 101 - Park on master port M5 - * - 110 - Park on master port M6 - * - 111 - Park on master port M7 - */ -/*@{*/ -#define BP_AXBS_CRSn_PARK (0U) /*!< Bit position for AXBS_CRSn_PARK. */ -#define BM_AXBS_CRSn_PARK (0x00000007U) /*!< Bit mask for AXBS_CRSn_PARK. */ -#define BS_AXBS_CRSn_PARK (3U) /*!< Bit field size in bits for AXBS_CRSn_PARK. */ - -/*! @brief Read current value of the AXBS_CRSn_PARK field. */ -#define BR_AXBS_CRSn_PARK(x, n) (HW_AXBS_CRSn(x, n).B.PARK) - -/*! @brief Format value for bitfield AXBS_CRSn_PARK. */ -#define BF_AXBS_CRSn_PARK(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PARK) & BM_AXBS_CRSn_PARK) - -/*! @brief Set the PARK field to a new value. */ -#define BW_AXBS_CRSn_PARK(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v))) -/*@}*/ - -/*! - * @name Register AXBS_CRSn, field PCTL[5:4] (RW) - * - * Determines the slave port's parking control. The low-power park feature - * results in an overall power savings if the slave port is not saturated. However, - * this forces an extra latency clock when any master tries to access the slave - * port while not in use because it is not parked on any master. - * - * Values: - * - 00 - When no master makes a request, the arbiter parks the slave port on - * the master port defined by the PARK field - * - 01 - When no master makes a request, the arbiter parks the slave port on - * the last master to be in control of the slave port - * - 10 - When no master makes a request, the slave port is not parked on a - * master and the arbiter drives all outputs to a constant safe state - * - 11 - Reserved - */ -/*@{*/ -#define BP_AXBS_CRSn_PCTL (4U) /*!< Bit position for AXBS_CRSn_PCTL. */ -#define BM_AXBS_CRSn_PCTL (0x00000030U) /*!< Bit mask for AXBS_CRSn_PCTL. */ -#define BS_AXBS_CRSn_PCTL (2U) /*!< Bit field size in bits for AXBS_CRSn_PCTL. */ - -/*! @brief Read current value of the AXBS_CRSn_PCTL field. */ -#define BR_AXBS_CRSn_PCTL(x, n) (HW_AXBS_CRSn(x, n).B.PCTL) - -/*! @brief Format value for bitfield AXBS_CRSn_PCTL. */ -#define BF_AXBS_CRSn_PCTL(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PCTL) & BM_AXBS_CRSn_PCTL) - -/*! @brief Set the PCTL field to a new value. */ -#define BW_AXBS_CRSn_PCTL(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v))) -/*@}*/ - -/*! - * @name Register AXBS_CRSn, field ARB[9:8] (RW) - * - * Selects the arbitration policy for the slave port. - * - * Values: - * - 00 - Fixed priority - * - 01 - Round-robin, or rotating, priority - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_AXBS_CRSn_ARB (8U) /*!< Bit position for AXBS_CRSn_ARB. */ -#define BM_AXBS_CRSn_ARB (0x00000300U) /*!< Bit mask for AXBS_CRSn_ARB. */ -#define BS_AXBS_CRSn_ARB (2U) /*!< Bit field size in bits for AXBS_CRSn_ARB. */ - -/*! @brief Read current value of the AXBS_CRSn_ARB field. */ -#define BR_AXBS_CRSn_ARB(x, n) (HW_AXBS_CRSn(x, n).B.ARB) - -/*! @brief Format value for bitfield AXBS_CRSn_ARB. */ -#define BF_AXBS_CRSn_ARB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_ARB) & BM_AXBS_CRSn_ARB) - -/*! @brief Set the ARB field to a new value. */ -#define BW_AXBS_CRSn_ARB(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v))) -/*@}*/ - -/*! - * @name Register AXBS_CRSn, field HLP[30] (RW) - * - * Sets the initial arbitration priority for low power mode requests . Setting - * this bit will not affect the request for low power mode from attaining highest - * priority once it has control of the slave ports. - * - * Values: - * - 0 - The low power mode request has the highest priority for arbitration on - * this slave port - * - 1 - The low power mode request has the lowest initial priority for - * arbitration on this slave port - */ -/*@{*/ -#define BP_AXBS_CRSn_HLP (30U) /*!< Bit position for AXBS_CRSn_HLP. */ -#define BM_AXBS_CRSn_HLP (0x40000000U) /*!< Bit mask for AXBS_CRSn_HLP. */ -#define BS_AXBS_CRSn_HLP (1U) /*!< Bit field size in bits for AXBS_CRSn_HLP. */ - -/*! @brief Read current value of the AXBS_CRSn_HLP field. */ -#define BR_AXBS_CRSn_HLP(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP)) - -/*! @brief Format value for bitfield AXBS_CRSn_HLP. */ -#define BF_AXBS_CRSn_HLP(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_HLP) & BM_AXBS_CRSn_HLP) - -/*! @brief Set the HLP field to a new value. */ -#define BW_AXBS_CRSn_HLP(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP) = (v)) -/*@}*/ - -/*! - * @name Register AXBS_CRSn, field RO[31] (RW) - * - * Forces the slave port's CSRn and PRSn registers to be read-only. After set, - * only a hardware reset clears it. - * - * Values: - * - 0 - The slave port's registers are writeable - * - 1 - The slave port's registers are read-only and cannot be written. - * Attempted writes have no effect on the registers and result in a bus error - * response. - */ -/*@{*/ -#define BP_AXBS_CRSn_RO (31U) /*!< Bit position for AXBS_CRSn_RO. */ -#define BM_AXBS_CRSn_RO (0x80000000U) /*!< Bit mask for AXBS_CRSn_RO. */ -#define BS_AXBS_CRSn_RO (1U) /*!< Bit field size in bits for AXBS_CRSn_RO. */ - -/*! @brief Read current value of the AXBS_CRSn_RO field. */ -#define BR_AXBS_CRSn_RO(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO)) - -/*! @brief Format value for bitfield AXBS_CRSn_RO. */ -#define BF_AXBS_CRSn_RO(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_RO) & BM_AXBS_CRSn_RO) - -/*! @brief Set the RO field to a new value. */ -#define BW_AXBS_CRSn_RO(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_AXBS_MGPCR0 - Master General Purpose Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MGPCR controls only whether the master's undefined length burst accesses - * are allowed to complete uninterrupted or whether they can be broken by - * requests from higher priority masters. The MGPCR can be accessed only in Supervisor - * mode with 32-bit accesses. - */ -typedef union _hw_axbs_mgpcr0 -{ - uint32_t U; - struct _hw_axbs_mgpcr0_bitfields - { - uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_axbs_mgpcr0_t; - -/*! - * @name Constants and macros for entire AXBS_MGPCR0 register - */ -/*@{*/ -#define HW_AXBS_MGPCR0_ADDR(x) ((x) + 0x800U) - -#define HW_AXBS_MGPCR0(x) (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR(x)) -#define HW_AXBS_MGPCR0_RD(x) (HW_AXBS_MGPCR0(x).U) -#define HW_AXBS_MGPCR0_WR(x, v) (HW_AXBS_MGPCR0(x).U = (v)) -#define HW_AXBS_MGPCR0_SET(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) | (v))) -#define HW_AXBS_MGPCR0_CLR(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) & ~(v))) -#define HW_AXBS_MGPCR0_TOG(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_MGPCR0 bitfields - */ - -/*! - * @name Register AXBS_MGPCR0, field AULB[2:0] (RW) - * - * Determines whether, and when, the crossbar switch arbitrates away the slave - * port the master owns when the master is performing undefined length burst - * accesses. - * - * Values: - * - 000 - No arbitration is allowed during an undefined length burst - * - 001 - Arbitration is allowed at any time during an undefined length burst - * - 010 - Arbitration is allowed after four beats of an undefined length burst - * - 011 - Arbitration is allowed after eight beats of an undefined length burst - * - 100 - Arbitration is allowed after 16 beats of an undefined length burst - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_AXBS_MGPCR0_AULB (0U) /*!< Bit position for AXBS_MGPCR0_AULB. */ -#define BM_AXBS_MGPCR0_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR0_AULB. */ -#define BS_AXBS_MGPCR0_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR0_AULB. */ - -/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */ -#define BR_AXBS_MGPCR0_AULB(x) (HW_AXBS_MGPCR0(x).B.AULB) - -/*! @brief Format value for bitfield AXBS_MGPCR0_AULB. */ -#define BF_AXBS_MGPCR0_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR0_AULB) & BM_AXBS_MGPCR0_AULB) - -/*! @brief Set the AULB field to a new value. */ -#define BW_AXBS_MGPCR0_AULB(x, v) (HW_AXBS_MGPCR0_WR(x, (HW_AXBS_MGPCR0_RD(x) & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v))) -/*@}*/ - -/******************************************************************************* - * HW_AXBS_MGPCR1 - Master General Purpose Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MGPCR controls only whether the master's undefined length burst accesses - * are allowed to complete uninterrupted or whether they can be broken by - * requests from higher priority masters. The MGPCR can be accessed only in Supervisor - * mode with 32-bit accesses. - */ -typedef union _hw_axbs_mgpcr1 -{ - uint32_t U; - struct _hw_axbs_mgpcr1_bitfields - { - uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_axbs_mgpcr1_t; - -/*! - * @name Constants and macros for entire AXBS_MGPCR1 register - */ -/*@{*/ -#define HW_AXBS_MGPCR1_ADDR(x) ((x) + 0x900U) - -#define HW_AXBS_MGPCR1(x) (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR(x)) -#define HW_AXBS_MGPCR1_RD(x) (HW_AXBS_MGPCR1(x).U) -#define HW_AXBS_MGPCR1_WR(x, v) (HW_AXBS_MGPCR1(x).U = (v)) -#define HW_AXBS_MGPCR1_SET(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) | (v))) -#define HW_AXBS_MGPCR1_CLR(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) & ~(v))) -#define HW_AXBS_MGPCR1_TOG(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_MGPCR1 bitfields - */ - -/*! - * @name Register AXBS_MGPCR1, field AULB[2:0] (RW) - * - * Determines whether, and when, the crossbar switch arbitrates away the slave - * port the master owns when the master is performing undefined length burst - * accesses. - * - * Values: - * - 000 - No arbitration is allowed during an undefined length burst - * - 001 - Arbitration is allowed at any time during an undefined length burst - * - 010 - Arbitration is allowed after four beats of an undefined length burst - * - 011 - Arbitration is allowed after eight beats of an undefined length burst - * - 100 - Arbitration is allowed after 16 beats of an undefined length burst - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_AXBS_MGPCR1_AULB (0U) /*!< Bit position for AXBS_MGPCR1_AULB. */ -#define BM_AXBS_MGPCR1_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR1_AULB. */ -#define BS_AXBS_MGPCR1_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR1_AULB. */ - -/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */ -#define BR_AXBS_MGPCR1_AULB(x) (HW_AXBS_MGPCR1(x).B.AULB) - -/*! @brief Format value for bitfield AXBS_MGPCR1_AULB. */ -#define BF_AXBS_MGPCR1_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR1_AULB) & BM_AXBS_MGPCR1_AULB) - -/*! @brief Set the AULB field to a new value. */ -#define BW_AXBS_MGPCR1_AULB(x, v) (HW_AXBS_MGPCR1_WR(x, (HW_AXBS_MGPCR1_RD(x) & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v))) -/*@}*/ - -/******************************************************************************* - * HW_AXBS_MGPCR2 - Master General Purpose Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MGPCR controls only whether the master's undefined length burst accesses - * are allowed to complete uninterrupted or whether they can be broken by - * requests from higher priority masters. The MGPCR can be accessed only in Supervisor - * mode with 32-bit accesses. - */ -typedef union _hw_axbs_mgpcr2 -{ - uint32_t U; - struct _hw_axbs_mgpcr2_bitfields - { - uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_axbs_mgpcr2_t; - -/*! - * @name Constants and macros for entire AXBS_MGPCR2 register - */ -/*@{*/ -#define HW_AXBS_MGPCR2_ADDR(x) ((x) + 0xA00U) - -#define HW_AXBS_MGPCR2(x) (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR(x)) -#define HW_AXBS_MGPCR2_RD(x) (HW_AXBS_MGPCR2(x).U) -#define HW_AXBS_MGPCR2_WR(x, v) (HW_AXBS_MGPCR2(x).U = (v)) -#define HW_AXBS_MGPCR2_SET(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) | (v))) -#define HW_AXBS_MGPCR2_CLR(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) & ~(v))) -#define HW_AXBS_MGPCR2_TOG(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_MGPCR2 bitfields - */ - -/*! - * @name Register AXBS_MGPCR2, field AULB[2:0] (RW) - * - * Determines whether, and when, the crossbar switch arbitrates away the slave - * port the master owns when the master is performing undefined length burst - * accesses. - * - * Values: - * - 000 - No arbitration is allowed during an undefined length burst - * - 001 - Arbitration is allowed at any time during an undefined length burst - * - 010 - Arbitration is allowed after four beats of an undefined length burst - * - 011 - Arbitration is allowed after eight beats of an undefined length burst - * - 100 - Arbitration is allowed after 16 beats of an undefined length burst - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_AXBS_MGPCR2_AULB (0U) /*!< Bit position for AXBS_MGPCR2_AULB. */ -#define BM_AXBS_MGPCR2_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR2_AULB. */ -#define BS_AXBS_MGPCR2_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR2_AULB. */ - -/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */ -#define BR_AXBS_MGPCR2_AULB(x) (HW_AXBS_MGPCR2(x).B.AULB) - -/*! @brief Format value for bitfield AXBS_MGPCR2_AULB. */ -#define BF_AXBS_MGPCR2_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR2_AULB) & BM_AXBS_MGPCR2_AULB) - -/*! @brief Set the AULB field to a new value. */ -#define BW_AXBS_MGPCR2_AULB(x, v) (HW_AXBS_MGPCR2_WR(x, (HW_AXBS_MGPCR2_RD(x) & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v))) -/*@}*/ - -/******************************************************************************* - * HW_AXBS_MGPCR3 - Master General Purpose Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MGPCR controls only whether the master's undefined length burst accesses - * are allowed to complete uninterrupted or whether they can be broken by - * requests from higher priority masters. The MGPCR can be accessed only in Supervisor - * mode with 32-bit accesses. - */ -typedef union _hw_axbs_mgpcr3 -{ - uint32_t U; - struct _hw_axbs_mgpcr3_bitfields - { - uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_axbs_mgpcr3_t; - -/*! - * @name Constants and macros for entire AXBS_MGPCR3 register - */ -/*@{*/ -#define HW_AXBS_MGPCR3_ADDR(x) ((x) + 0xB00U) - -#define HW_AXBS_MGPCR3(x) (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR(x)) -#define HW_AXBS_MGPCR3_RD(x) (HW_AXBS_MGPCR3(x).U) -#define HW_AXBS_MGPCR3_WR(x, v) (HW_AXBS_MGPCR3(x).U = (v)) -#define HW_AXBS_MGPCR3_SET(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) | (v))) -#define HW_AXBS_MGPCR3_CLR(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) & ~(v))) -#define HW_AXBS_MGPCR3_TOG(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_MGPCR3 bitfields - */ - -/*! - * @name Register AXBS_MGPCR3, field AULB[2:0] (RW) - * - * Determines whether, and when, the crossbar switch arbitrates away the slave - * port the master owns when the master is performing undefined length burst - * accesses. - * - * Values: - * - 000 - No arbitration is allowed during an undefined length burst - * - 001 - Arbitration is allowed at any time during an undefined length burst - * - 010 - Arbitration is allowed after four beats of an undefined length burst - * - 011 - Arbitration is allowed after eight beats of an undefined length burst - * - 100 - Arbitration is allowed after 16 beats of an undefined length burst - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_AXBS_MGPCR3_AULB (0U) /*!< Bit position for AXBS_MGPCR3_AULB. */ -#define BM_AXBS_MGPCR3_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR3_AULB. */ -#define BS_AXBS_MGPCR3_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR3_AULB. */ - -/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */ -#define BR_AXBS_MGPCR3_AULB(x) (HW_AXBS_MGPCR3(x).B.AULB) - -/*! @brief Format value for bitfield AXBS_MGPCR3_AULB. */ -#define BF_AXBS_MGPCR3_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR3_AULB) & BM_AXBS_MGPCR3_AULB) - -/*! @brief Set the AULB field to a new value. */ -#define BW_AXBS_MGPCR3_AULB(x, v) (HW_AXBS_MGPCR3_WR(x, (HW_AXBS_MGPCR3_RD(x) & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v))) -/*@}*/ - -/******************************************************************************* - * HW_AXBS_MGPCR4 - Master General Purpose Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MGPCR controls only whether the master's undefined length burst accesses - * are allowed to complete uninterrupted or whether they can be broken by - * requests from higher priority masters. The MGPCR can be accessed only in Supervisor - * mode with 32-bit accesses. - */ -typedef union _hw_axbs_mgpcr4 -{ - uint32_t U; - struct _hw_axbs_mgpcr4_bitfields - { - uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_axbs_mgpcr4_t; - -/*! - * @name Constants and macros for entire AXBS_MGPCR4 register - */ -/*@{*/ -#define HW_AXBS_MGPCR4_ADDR(x) ((x) + 0xC00U) - -#define HW_AXBS_MGPCR4(x) (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR(x)) -#define HW_AXBS_MGPCR4_RD(x) (HW_AXBS_MGPCR4(x).U) -#define HW_AXBS_MGPCR4_WR(x, v) (HW_AXBS_MGPCR4(x).U = (v)) -#define HW_AXBS_MGPCR4_SET(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) | (v))) -#define HW_AXBS_MGPCR4_CLR(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) & ~(v))) -#define HW_AXBS_MGPCR4_TOG(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_MGPCR4 bitfields - */ - -/*! - * @name Register AXBS_MGPCR4, field AULB[2:0] (RW) - * - * Determines whether, and when, the crossbar switch arbitrates away the slave - * port the master owns when the master is performing undefined length burst - * accesses. - * - * Values: - * - 000 - No arbitration is allowed during an undefined length burst - * - 001 - Arbitration is allowed at any time during an undefined length burst - * - 010 - Arbitration is allowed after four beats of an undefined length burst - * - 011 - Arbitration is allowed after eight beats of an undefined length burst - * - 100 - Arbitration is allowed after 16 beats of an undefined length burst - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_AXBS_MGPCR4_AULB (0U) /*!< Bit position for AXBS_MGPCR4_AULB. */ -#define BM_AXBS_MGPCR4_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR4_AULB. */ -#define BS_AXBS_MGPCR4_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR4_AULB. */ - -/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */ -#define BR_AXBS_MGPCR4_AULB(x) (HW_AXBS_MGPCR4(x).B.AULB) - -/*! @brief Format value for bitfield AXBS_MGPCR4_AULB. */ -#define BF_AXBS_MGPCR4_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR4_AULB) & BM_AXBS_MGPCR4_AULB) - -/*! @brief Set the AULB field to a new value. */ -#define BW_AXBS_MGPCR4_AULB(x, v) (HW_AXBS_MGPCR4_WR(x, (HW_AXBS_MGPCR4_RD(x) & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v))) -/*@}*/ - -/******************************************************************************* - * HW_AXBS_MGPCR5 - Master General Purpose Control Register - ******************************************************************************/ - -/*! - * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MGPCR controls only whether the master's undefined length burst accesses - * are allowed to complete uninterrupted or whether they can be broken by - * requests from higher priority masters. The MGPCR can be accessed only in Supervisor - * mode with 32-bit accesses. - */ -typedef union _hw_axbs_mgpcr5 -{ - uint32_t U; - struct _hw_axbs_mgpcr5_bitfields - { - uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_axbs_mgpcr5_t; - -/*! - * @name Constants and macros for entire AXBS_MGPCR5 register - */ -/*@{*/ -#define HW_AXBS_MGPCR5_ADDR(x) ((x) + 0xD00U) - -#define HW_AXBS_MGPCR5(x) (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR(x)) -#define HW_AXBS_MGPCR5_RD(x) (HW_AXBS_MGPCR5(x).U) -#define HW_AXBS_MGPCR5_WR(x, v) (HW_AXBS_MGPCR5(x).U = (v)) -#define HW_AXBS_MGPCR5_SET(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) | (v))) -#define HW_AXBS_MGPCR5_CLR(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) & ~(v))) -#define HW_AXBS_MGPCR5_TOG(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual AXBS_MGPCR5 bitfields - */ - -/*! - * @name Register AXBS_MGPCR5, field AULB[2:0] (RW) - * - * Determines whether, and when, the crossbar switch arbitrates away the slave - * port the master owns when the master is performing undefined length burst - * accesses. - * - * Values: - * - 000 - No arbitration is allowed during an undefined length burst - * - 001 - Arbitration is allowed at any time during an undefined length burst - * - 010 - Arbitration is allowed after four beats of an undefined length burst - * - 011 - Arbitration is allowed after eight beats of an undefined length burst - * - 100 - Arbitration is allowed after 16 beats of an undefined length burst - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_AXBS_MGPCR5_AULB (0U) /*!< Bit position for AXBS_MGPCR5_AULB. */ -#define BM_AXBS_MGPCR5_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR5_AULB. */ -#define BS_AXBS_MGPCR5_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR5_AULB. */ - -/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */ -#define BR_AXBS_MGPCR5_AULB(x) (HW_AXBS_MGPCR5(x).B.AULB) - -/*! @brief Format value for bitfield AXBS_MGPCR5_AULB. */ -#define BF_AXBS_MGPCR5_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR5_AULB) & BM_AXBS_MGPCR5_AULB) - -/*! @brief Set the AULB field to a new value. */ -#define BW_AXBS_MGPCR5_AULB(x, v) (HW_AXBS_MGPCR5_WR(x, (HW_AXBS_MGPCR5_RD(x) & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v))) -/*@}*/ - -/******************************************************************************* - * hw_axbs_t - module struct - ******************************************************************************/ -/*! - * @brief All AXBS module registers. - */ -#pragma pack(1) -typedef struct _hw_axbs -{ - struct { - __IO hw_axbs_prsn_t PRSn; /*!< [0x0] Priority Registers Slave */ - uint8_t _reserved0[12]; - __IO hw_axbs_crsn_t CRSn; /*!< [0x10] Control Register */ - uint8_t _reserved1[236]; - } SLAVE[5]; - uint8_t _reserved0[768]; - __IO hw_axbs_mgpcr0_t MGPCR0; /*!< [0x800] Master General Purpose Control Register */ - uint8_t _reserved1[252]; - __IO hw_axbs_mgpcr1_t MGPCR1; /*!< [0x900] Master General Purpose Control Register */ - uint8_t _reserved2[252]; - __IO hw_axbs_mgpcr2_t MGPCR2; /*!< [0xA00] Master General Purpose Control Register */ - uint8_t _reserved3[252]; - __IO hw_axbs_mgpcr3_t MGPCR3; /*!< [0xB00] Master General Purpose Control Register */ - uint8_t _reserved4[252]; - __IO hw_axbs_mgpcr4_t MGPCR4; /*!< [0xC00] Master General Purpose Control Register */ - uint8_t _reserved5[252]; - __IO hw_axbs_mgpcr5_t MGPCR5; /*!< [0xD00] Master General Purpose Control Register */ -} hw_axbs_t; -#pragma pack() - -/*! @brief Macro to access all AXBS registers. */ -/*! @param x AXBS module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_AXBS(AXBS_BASE). */ -#define HW_AXBS(x) (*(hw_axbs_t *)(x)) - -#endif /* __HW_AXBS_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_can.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_can.h deleted file mode 100644 index 34ed3797bbf..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_can.h +++ /dev/null @@ -1,3579 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CAN_REGISTERS_H__ -#define __HW_CAN_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 CAN - * - * Flex Controller Area Network module - * - * Registers defined in this header file: - * - HW_CAN_MCR - Module Configuration Register - * - HW_CAN_CTRL1 - Control 1 register - * - HW_CAN_TIMER - Free Running Timer - * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register - * - HW_CAN_RX14MASK - Rx 14 Mask register - * - HW_CAN_RX15MASK - Rx 15 Mask register - * - HW_CAN_ECR - Error Counter - * - HW_CAN_ESR1 - Error and Status 1 register - * - HW_CAN_IMASK1 - Interrupt Masks 1 register - * - HW_CAN_IFLAG1 - Interrupt Flags 1 register - * - HW_CAN_CTRL2 - Control 2 register - * - HW_CAN_ESR2 - Error and Status 2 register - * - HW_CAN_CRCR - CRC Register - * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register - * - HW_CAN_RXFIR - Rx FIFO Information Register - * - HW_CAN_CSn - Message Buffer 0 CS Register - * - HW_CAN_IDn - Message Buffer 0 ID Register - * - HW_CAN_WORD0n - Message Buffer 0 WORD0 Register - * - HW_CAN_WORD1n - Message Buffer 0 WORD1 Register - * - HW_CAN_RXIMRn - Rx Individual Mask Registers - * - * - hw_can_t - Struct containing all module registers. - */ - -#define HW_CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */ - -/******************************************************************************* - * HW_CAN_MCR - Module Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_MCR - Module Configuration Register (RW) - * - * Reset value: 0xD890000FU - * - * This register defines global system configurations, such as the module - * operation modes and the maximum message buffer configuration. - */ -typedef union _hw_can_mcr -{ - uint32_t U; - struct _hw_can_mcr_bitfields - { - uint32_t MAXMB : 7; /*!< [6:0] Number Of The Last Message Buffer */ - uint32_t RESERVED0 : 1; /*!< [7] */ - uint32_t IDAM : 2; /*!< [9:8] ID Acceptance Mode */ - uint32_t RESERVED1 : 2; /*!< [11:10] */ - uint32_t AEN : 1; /*!< [12] Abort Enable */ - uint32_t LPRIOEN : 1; /*!< [13] Local Priority Enable */ - uint32_t RESERVED2 : 2; /*!< [15:14] */ - uint32_t IRMQ : 1; /*!< [16] Individual Rx Masking And Queue Enable */ - uint32_t SRXDIS : 1; /*!< [17] Self Reception Disable */ - uint32_t RESERVED3 : 1; /*!< [18] */ - uint32_t WAKSRC : 1; /*!< [19] Wake Up Source */ - uint32_t LPMACK : 1; /*!< [20] Low-Power Mode Acknowledge */ - uint32_t WRNEN : 1; /*!< [21] Warning Interrupt Enable */ - uint32_t SLFWAK : 1; /*!< [22] Self Wake Up */ - uint32_t SUPV : 1; /*!< [23] Supervisor Mode */ - uint32_t FRZACK : 1; /*!< [24] Freeze Mode Acknowledge */ - uint32_t SOFTRST : 1; /*!< [25] Soft Reset */ - uint32_t WAKMSK : 1; /*!< [26] Wake Up Interrupt Mask */ - uint32_t NOTRDY : 1; /*!< [27] FlexCAN Not Ready */ - uint32_t HALT : 1; /*!< [28] Halt FlexCAN */ - uint32_t RFEN : 1; /*!< [29] Rx FIFO Enable */ - uint32_t FRZ : 1; /*!< [30] Freeze Enable */ - uint32_t MDIS : 1; /*!< [31] Module Disable */ - } B; -} hw_can_mcr_t; - -/*! - * @name Constants and macros for entire CAN_MCR register - */ -/*@{*/ -#define HW_CAN_MCR_ADDR(x) ((x) + 0x0U) - -#define HW_CAN_MCR(x) (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x)) -#define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U) -#define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v)) -#define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) | (v))) -#define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v))) -#define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_MCR bitfields - */ - -/*! - * @name Register CAN_MCR, field MAXMB[6:0] (RW) - * - * This 7-bit field defines the number of the last Message Buffers that will - * take part in the matching and arbitration processes. The reset value (0x0F) is - * equivalent to a 16 MB configuration. This field can be written only in Freeze - * mode because it is blocked by hardware in other modes. Number of the last MB = - * MAXMB MAXMB must be programmed with a value smaller than the parameter - * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be: - * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size - * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number - * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between - * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and - * Matching Timing"). - */ -/*@{*/ -#define BP_CAN_MCR_MAXMB (0U) /*!< Bit position for CAN_MCR_MAXMB. */ -#define BM_CAN_MCR_MAXMB (0x0000007FU) /*!< Bit mask for CAN_MCR_MAXMB. */ -#define BS_CAN_MCR_MAXMB (7U) /*!< Bit field size in bits for CAN_MCR_MAXMB. */ - -/*! @brief Read current value of the CAN_MCR_MAXMB field. */ -#define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB) - -/*! @brief Format value for bitfield CAN_MCR_MAXMB. */ -#define BF_CAN_MCR_MAXMB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MAXMB) & BM_CAN_MCR_MAXMB) - -/*! @brief Set the MAXMB field to a new value. */ -#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v))) -/*@}*/ - -/*! - * @name Register CAN_MCR, field IDAM[9:8] (RW) - * - * This 2-bit field identifies the format of the Rx FIFO ID Filter Table - * elements. Note that all elements of the table are configured at the same time by this - * field (they are all the same format). See Section "Rx FIFO Structure". This - * field can be written only in Freeze mode because it is blocked by hardware in - * other modes. - * - * Values: - * - 00 - Format A: One full ID (standard and extended) per ID Filter Table - * element. - * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and - * extended) IDs per ID Filter Table element. - * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element. - * - 11 - Format D: All frames rejected. - */ -/*@{*/ -#define BP_CAN_MCR_IDAM (8U) /*!< Bit position for CAN_MCR_IDAM. */ -#define BM_CAN_MCR_IDAM (0x00000300U) /*!< Bit mask for CAN_MCR_IDAM. */ -#define BS_CAN_MCR_IDAM (2U) /*!< Bit field size in bits for CAN_MCR_IDAM. */ - -/*! @brief Read current value of the CAN_MCR_IDAM field. */ -#define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM) - -/*! @brief Format value for bitfield CAN_MCR_IDAM. */ -#define BF_CAN_MCR_IDAM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IDAM) & BM_CAN_MCR_IDAM) - -/*! @brief Set the IDAM field to a new value. */ -#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v))) -/*@}*/ - -/*! - * @name Register CAN_MCR, field AEN[12] (RW) - * - * This bit is supplied for backwards compatibility with legacy applications. - * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a - * safe procedure for aborting a pending transmission, so that no frame is sent in - * the CAN bus without notification. This bit can be written only in Freeze mode - * because it is blocked by hardware in other modes. When MCR[AEN] is asserted, - * only the abort mechanism (see Section "Transmission Abort Mechanism") must be - * used for updating Mailboxes configured for transmission. Writing the Abort code - * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is - * asserted. - * - * Values: - * - 0 - Abort disabled. - * - 1 - Abort enabled. - */ -/*@{*/ -#define BP_CAN_MCR_AEN (12U) /*!< Bit position for CAN_MCR_AEN. */ -#define BM_CAN_MCR_AEN (0x00001000U) /*!< Bit mask for CAN_MCR_AEN. */ -#define BS_CAN_MCR_AEN (1U) /*!< Bit field size in bits for CAN_MCR_AEN. */ - -/*! @brief Read current value of the CAN_MCR_AEN field. */ -#define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN)) - -/*! @brief Format value for bitfield CAN_MCR_AEN. */ -#define BF_CAN_MCR_AEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_AEN) & BM_CAN_MCR_AEN) - -/*! @brief Set the AEN field to a new value. */ -#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field LPRIOEN[13] (RW) - * - * This bit is provided for backwards compatibility with legacy applications. It - * controls whether the local priority feature is enabled or not. It is used to - * expand the ID used during the arbitration process. With this expanded ID - * concept, the arbitration process is done based on the full 32-bit word, but the - * actual transmitted ID still has 11-bit for standard frames and 29-bit for - * extended frames. This bit can be written only in Freeze mode because it is blocked by - * hardware in other modes. - * - * Values: - * - 0 - Local Priority disabled. - * - 1 - Local Priority enabled. - */ -/*@{*/ -#define BP_CAN_MCR_LPRIOEN (13U) /*!< Bit position for CAN_MCR_LPRIOEN. */ -#define BM_CAN_MCR_LPRIOEN (0x00002000U) /*!< Bit mask for CAN_MCR_LPRIOEN. */ -#define BS_CAN_MCR_LPRIOEN (1U) /*!< Bit field size in bits for CAN_MCR_LPRIOEN. */ - -/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */ -#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN)) - -/*! @brief Format value for bitfield CAN_MCR_LPRIOEN. */ -#define BF_CAN_MCR_LPRIOEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_LPRIOEN) & BM_CAN_MCR_LPRIOEN) - -/*! @brief Set the LPRIOEN field to a new value. */ -#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field IRMQ[16] (RW) - * - * This bit indicates whether Rx matching process will be based either on - * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and - * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is - * blocked by hardware in other modes. - * - * Values: - * - 0 - Individual Rx masking and queue feature are disabled. For backward - * compatibility with legacy applications, the reading of C/S word locks the MB - * even if it is EMPTY. - * - 1 - Individual Rx masking and queue feature are enabled. - */ -/*@{*/ -#define BP_CAN_MCR_IRMQ (16U) /*!< Bit position for CAN_MCR_IRMQ. */ -#define BM_CAN_MCR_IRMQ (0x00010000U) /*!< Bit mask for CAN_MCR_IRMQ. */ -#define BS_CAN_MCR_IRMQ (1U) /*!< Bit field size in bits for CAN_MCR_IRMQ. */ - -/*! @brief Read current value of the CAN_MCR_IRMQ field. */ -#define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ)) - -/*! @brief Format value for bitfield CAN_MCR_IRMQ. */ -#define BF_CAN_MCR_IRMQ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IRMQ) & BM_CAN_MCR_IRMQ) - -/*! @brief Set the IRMQ field to a new value. */ -#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field SRXDIS[17] (RW) - * - * This bit defines whether FlexCAN is allowed to receive frames transmitted by - * itself. If this bit is asserted, frames transmitted by the module will not be - * stored in any MB, regardless if the MB is programmed with an ID that matches - * the transmitted frame, and no interrupt flag or interrupt signal will be - * generated due to the frame reception. This bit can be written only in Freeze mode - * because it is blocked by hardware in other modes. - * - * Values: - * - 0 - Self reception enabled. - * - 1 - Self reception disabled. - */ -/*@{*/ -#define BP_CAN_MCR_SRXDIS (17U) /*!< Bit position for CAN_MCR_SRXDIS. */ -#define BM_CAN_MCR_SRXDIS (0x00020000U) /*!< Bit mask for CAN_MCR_SRXDIS. */ -#define BS_CAN_MCR_SRXDIS (1U) /*!< Bit field size in bits for CAN_MCR_SRXDIS. */ - -/*! @brief Read current value of the CAN_MCR_SRXDIS field. */ -#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS)) - -/*! @brief Format value for bitfield CAN_MCR_SRXDIS. */ -#define BF_CAN_MCR_SRXDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SRXDIS) & BM_CAN_MCR_SRXDIS) - -/*! @brief Set the SRXDIS field to a new value. */ -#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field WAKSRC[19] (RW) - * - * This bit defines whether the integrated low-pass filter is applied to protect - * the Rx CAN input from spurious wake up. This bit can be written only in - * Freeze mode because it is blocked by hardware in other modes. - * - * Values: - * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant - * edges on the CAN bus. - * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant - * edges on the CAN bus. - */ -/*@{*/ -#define BP_CAN_MCR_WAKSRC (19U) /*!< Bit position for CAN_MCR_WAKSRC. */ -#define BM_CAN_MCR_WAKSRC (0x00080000U) /*!< Bit mask for CAN_MCR_WAKSRC. */ -#define BS_CAN_MCR_WAKSRC (1U) /*!< Bit field size in bits for CAN_MCR_WAKSRC. */ - -/*! @brief Read current value of the CAN_MCR_WAKSRC field. */ -#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC)) - -/*! @brief Format value for bitfield CAN_MCR_WAKSRC. */ -#define BF_CAN_MCR_WAKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKSRC) & BM_CAN_MCR_WAKSRC) - -/*! @brief Set the WAKSRC field to a new value. */ -#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field LPMACK[20] (RO) - * - * This read-only bit indicates that FlexCAN is in a low-power mode (Disable - * mode , Stop mode ). A low-power mode cannot be entered until all current - * transmission or reception processes have finished, so the CPU can poll the LPMACK bit - * to know when FlexCAN has actually entered low power mode. LPMACK will be - * asserted within 180 CAN bits from the low-power mode request by the CPU, and - * negated within 2 CAN bits after the low-power mode request removal (see Section - * "Protocol Timing"). - * - * Values: - * - 0 - FlexCAN is not in a low-power mode. - * - 1 - FlexCAN is in a low-power mode. - */ -/*@{*/ -#define BP_CAN_MCR_LPMACK (20U) /*!< Bit position for CAN_MCR_LPMACK. */ -#define BM_CAN_MCR_LPMACK (0x00100000U) /*!< Bit mask for CAN_MCR_LPMACK. */ -#define BS_CAN_MCR_LPMACK (1U) /*!< Bit field size in bits for CAN_MCR_LPMACK. */ - -/*! @brief Read current value of the CAN_MCR_LPMACK field. */ -#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field WRNEN[21] (RW) - * - * When asserted, this bit enables the generation of the TWRNINT and RWRNINT - * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and - * RWRNINT flags will always be zero, independent of the values of the error - * counters, and no warning interrupt will ever be generated. This bit can be written - * only in Freeze mode because it is blocked by hardware in other modes. - * - * Values: - * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the - * error counters. - * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter - * transitions from less than 96 to greater than or equal to 96. - */ -/*@{*/ -#define BP_CAN_MCR_WRNEN (21U) /*!< Bit position for CAN_MCR_WRNEN. */ -#define BM_CAN_MCR_WRNEN (0x00200000U) /*!< Bit mask for CAN_MCR_WRNEN. */ -#define BS_CAN_MCR_WRNEN (1U) /*!< Bit field size in bits for CAN_MCR_WRNEN. */ - -/*! @brief Read current value of the CAN_MCR_WRNEN field. */ -#define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN)) - -/*! @brief Format value for bitfield CAN_MCR_WRNEN. */ -#define BF_CAN_MCR_WRNEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WRNEN) & BM_CAN_MCR_WRNEN) - -/*! @brief Set the WRNEN field to a new value. */ -#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field SLFWAK[22] (RW) - * - * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode - * other than Disable mode. When this feature is enabled, the FlexCAN module - * monitors the bus for wake up event, that is, a recessive-to-dominant transition. - * If a wake up event is detected during Stop mode, then FlexCAN generates, if - * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode - * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a - * low-power mode other than Disable mode, this bit cannot be written as it is - * blocked by hardware. - * - * Values: - * - 0 - FlexCAN Self Wake Up feature is disabled. - * - 1 - FlexCAN Self Wake Up feature is enabled. - */ -/*@{*/ -#define BP_CAN_MCR_SLFWAK (22U) /*!< Bit position for CAN_MCR_SLFWAK. */ -#define BM_CAN_MCR_SLFWAK (0x00400000U) /*!< Bit mask for CAN_MCR_SLFWAK. */ -#define BS_CAN_MCR_SLFWAK (1U) /*!< Bit field size in bits for CAN_MCR_SLFWAK. */ - -/*! @brief Read current value of the CAN_MCR_SLFWAK field. */ -#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK)) - -/*! @brief Format value for bitfield CAN_MCR_SLFWAK. */ -#define BF_CAN_MCR_SLFWAK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SLFWAK) & BM_CAN_MCR_SLFWAK) - -/*! @brief Set the SLFWAK field to a new value. */ -#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field SUPV[23] (RW) - * - * This bit configures the FlexCAN to be either in Supervisor or User mode. The - * registers affected by this bit are marked as S/U in the Access Type column of - * the module memory map. Reset value of this bit is 1, so the affected registers - * start with Supervisor access allowance only . This bit can be written only in - * Freeze mode because it is blocked by hardware in other modes. - * - * Values: - * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and - * Unrestricted accesses . - * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor - * access. Unrestricted access behaves as though the access was done to an - * unimplemented register location . - */ -/*@{*/ -#define BP_CAN_MCR_SUPV (23U) /*!< Bit position for CAN_MCR_SUPV. */ -#define BM_CAN_MCR_SUPV (0x00800000U) /*!< Bit mask for CAN_MCR_SUPV. */ -#define BS_CAN_MCR_SUPV (1U) /*!< Bit field size in bits for CAN_MCR_SUPV. */ - -/*! @brief Read current value of the CAN_MCR_SUPV field. */ -#define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV)) - -/*! @brief Format value for bitfield CAN_MCR_SUPV. */ -#define BF_CAN_MCR_SUPV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SUPV) & BM_CAN_MCR_SUPV) - -/*! @brief Set the SUPV field to a new value. */ -#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field FRZACK[24] (RO) - * - * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler - * is stopped. The Freeze mode request cannot be granted until current - * transmission or reception processes have finished. Therefore the software can poll the - * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze - * Mode request is negated, then this bit is negated after the FlexCAN prescaler is - * running again. If Freeze mode is requested while FlexCAN is in a low power - * mode, then the FRZACK bit will be set only when the low-power mode is exited. - * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the - * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze - * mode request removal (see Section "Protocol Timing"). - * - * Values: - * - 0 - FlexCAN not in Freeze mode, prescaler running. - * - 1 - FlexCAN in Freeze mode, prescaler stopped. - */ -/*@{*/ -#define BP_CAN_MCR_FRZACK (24U) /*!< Bit position for CAN_MCR_FRZACK. */ -#define BM_CAN_MCR_FRZACK (0x01000000U) /*!< Bit mask for CAN_MCR_FRZACK. */ -#define BS_CAN_MCR_FRZACK (1U) /*!< Bit field size in bits for CAN_MCR_FRZACK. */ - -/*! @brief Read current value of the CAN_MCR_FRZACK field. */ -#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field SOFTRST[25] (RW) - * - * When this bit is asserted, FlexCAN resets its internal state machines and - * some of the memory mapped registers. The following registers are reset: MCR - * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and - * CRCR. Configuration registers that control the interface to the CAN bus are - * not affected by soft reset. The following registers are unaffected: CTRL1, - * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all - * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it - * writes to the MCR Register, but it is also asserted when global soft reset is - * requested at MCU level . Because soft reset is synchronous and has to follow a - * request/acknowledge procedure across clock domains, it may take some time to - * fully propagate its effect. The SOFTRST bit remains asserted while reset is - * pending, and is automatically negated when reset completes. Therefore, software can - * poll this bit to know when the soft reset has completed. Soft reset cannot be - * applied while clocks are shut down in a low power mode. The module should be - * first removed from low power mode, and then soft reset can be applied. - * - * Values: - * - 0 - No reset request. - * - 1 - Resets the registers affected by soft reset. - */ -/*@{*/ -#define BP_CAN_MCR_SOFTRST (25U) /*!< Bit position for CAN_MCR_SOFTRST. */ -#define BM_CAN_MCR_SOFTRST (0x02000000U) /*!< Bit mask for CAN_MCR_SOFTRST. */ -#define BS_CAN_MCR_SOFTRST (1U) /*!< Bit field size in bits for CAN_MCR_SOFTRST. */ - -/*! @brief Read current value of the CAN_MCR_SOFTRST field. */ -#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST)) - -/*! @brief Format value for bitfield CAN_MCR_SOFTRST. */ -#define BF_CAN_MCR_SOFTRST(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SOFTRST) & BM_CAN_MCR_SOFTRST) - -/*! @brief Set the SOFTRST field to a new value. */ -#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field WAKMSK[26] (RW) - * - * This bit enables the Wake Up Interrupt generation under Self Wake Up - * mechanism. - * - * Values: - * - 0 - Wake Up Interrupt is disabled. - * - 1 - Wake Up Interrupt is enabled. - */ -/*@{*/ -#define BP_CAN_MCR_WAKMSK (26U) /*!< Bit position for CAN_MCR_WAKMSK. */ -#define BM_CAN_MCR_WAKMSK (0x04000000U) /*!< Bit mask for CAN_MCR_WAKMSK. */ -#define BS_CAN_MCR_WAKMSK (1U) /*!< Bit field size in bits for CAN_MCR_WAKMSK. */ - -/*! @brief Read current value of the CAN_MCR_WAKMSK field. */ -#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK)) - -/*! @brief Format value for bitfield CAN_MCR_WAKMSK. */ -#define BF_CAN_MCR_WAKMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKMSK) & BM_CAN_MCR_WAKMSK) - -/*! @brief Set the WAKMSK field to a new value. */ -#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field NOTRDY[27] (RO) - * - * This read-only bit indicates that FlexCAN is either in Disable mode , Stop - * mode or Freeze mode. It is negated once FlexCAN has exited these modes. - * - * Values: - * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back - * mode. - * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode. - */ -/*@{*/ -#define BP_CAN_MCR_NOTRDY (27U) /*!< Bit position for CAN_MCR_NOTRDY. */ -#define BM_CAN_MCR_NOTRDY (0x08000000U) /*!< Bit mask for CAN_MCR_NOTRDY. */ -#define BS_CAN_MCR_NOTRDY (1U) /*!< Bit field size in bits for CAN_MCR_NOTRDY. */ - -/*! @brief Read current value of the CAN_MCR_NOTRDY field. */ -#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field HALT[28] (RW) - * - * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU - * should clear it after initializing the Message Buffers and Control Register. No - * reception or transmission is performed by FlexCAN before this bit is cleared. - * Freeze mode cannot be entered while FlexCAN is in a low power mode. - * - * Values: - * - 0 - No Freeze mode request. - * - 1 - Enters Freeze mode if the FRZ bit is asserted. - */ -/*@{*/ -#define BP_CAN_MCR_HALT (28U) /*!< Bit position for CAN_MCR_HALT. */ -#define BM_CAN_MCR_HALT (0x10000000U) /*!< Bit mask for CAN_MCR_HALT. */ -#define BS_CAN_MCR_HALT (1U) /*!< Bit field size in bits for CAN_MCR_HALT. */ - -/*! @brief Read current value of the CAN_MCR_HALT field. */ -#define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT)) - -/*! @brief Format value for bitfield CAN_MCR_HALT. */ -#define BF_CAN_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_HALT) & BM_CAN_MCR_HALT) - -/*! @brief Set the HALT field to a new value. */ -#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field RFEN[29] (RW) - * - * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is - * set, MBs 0 to 5 cannot be used for normal reception and transmission because - * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well - * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used - * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the - * minimum number of peripheral clocks per CAN bit as described in the table - * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section - * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode - * because it is blocked by hardware in other modes. - * - * Values: - * - 0 - Rx FIFO not enabled. - * - 1 - Rx FIFO enabled. - */ -/*@{*/ -#define BP_CAN_MCR_RFEN (29U) /*!< Bit position for CAN_MCR_RFEN. */ -#define BM_CAN_MCR_RFEN (0x20000000U) /*!< Bit mask for CAN_MCR_RFEN. */ -#define BS_CAN_MCR_RFEN (1U) /*!< Bit field size in bits for CAN_MCR_RFEN. */ - -/*! @brief Read current value of the CAN_MCR_RFEN field. */ -#define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN)) - -/*! @brief Format value for bitfield CAN_MCR_RFEN. */ -#define BF_CAN_MCR_RFEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_RFEN) & BM_CAN_MCR_RFEN) - -/*! @brief Set the RFEN field to a new value. */ -#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field FRZ[30] (RW) - * - * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR - * Register is set or when Debug mode is requested at MCU level . When FRZ is - * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes - * FlexCAN to exit from Freeze mode. - * - * Values: - * - 0 - Not enabled to enter Freeze mode. - * - 1 - Enabled to enter Freeze mode. - */ -/*@{*/ -#define BP_CAN_MCR_FRZ (30U) /*!< Bit position for CAN_MCR_FRZ. */ -#define BM_CAN_MCR_FRZ (0x40000000U) /*!< Bit mask for CAN_MCR_FRZ. */ -#define BS_CAN_MCR_FRZ (1U) /*!< Bit field size in bits for CAN_MCR_FRZ. */ - -/*! @brief Read current value of the CAN_MCR_FRZ field. */ -#define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ)) - -/*! @brief Format value for bitfield CAN_MCR_FRZ. */ -#define BF_CAN_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_FRZ) & BM_CAN_MCR_FRZ) - -/*! @brief Set the FRZ field to a new value. */ -#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v)) -/*@}*/ - -/*! - * @name Register CAN_MCR, field MDIS[31] (RW) - * - * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN - * disables the clocks to the CAN Protocol Engine and Controller Host Interface - * sub-modules. This is the only bit within this register not affected by soft - * reset. - * - * Values: - * - 0 - Enable the FlexCAN module. - * - 1 - Disable the FlexCAN module. - */ -/*@{*/ -#define BP_CAN_MCR_MDIS (31U) /*!< Bit position for CAN_MCR_MDIS. */ -#define BM_CAN_MCR_MDIS (0x80000000U) /*!< Bit mask for CAN_MCR_MDIS. */ -#define BS_CAN_MCR_MDIS (1U) /*!< Bit field size in bits for CAN_MCR_MDIS. */ - -/*! @brief Read current value of the CAN_MCR_MDIS field. */ -#define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS)) - -/*! @brief Format value for bitfield CAN_MCR_MDIS. */ -#define BF_CAN_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MDIS) & BM_CAN_MCR_MDIS) - -/*! @brief Set the MDIS field to a new value. */ -#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_CTRL1 - Control 1 register - ******************************************************************************/ - -/*! - * @brief HW_CAN_CTRL1 - Control 1 register (RW) - * - * Reset value: 0x00000000U - * - * This register is defined for specific FlexCAN control features related to the - * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop - * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling - * (Bus-Off, Error, Warning). It also determines the Division Factor for the - * clock prescaler. - */ -typedef union _hw_can_ctrl1 -{ - uint32_t U; - struct _hw_can_ctrl1_bitfields - { - uint32_t PROPSEG : 3; /*!< [2:0] Propagation Segment */ - uint32_t LOM : 1; /*!< [3] Listen-Only Mode */ - uint32_t LBUF : 1; /*!< [4] Lowest Buffer Transmitted First */ - uint32_t TSYN : 1; /*!< [5] Timer Sync */ - uint32_t BOFFREC : 1; /*!< [6] Bus Off Recovery */ - uint32_t SMP : 1; /*!< [7] CAN Bit Sampling */ - uint32_t RESERVED0 : 2; /*!< [9:8] */ - uint32_t RWRNMSK : 1; /*!< [10] Rx Warning Interrupt Mask */ - uint32_t TWRNMSK : 1; /*!< [11] Tx Warning Interrupt Mask */ - uint32_t LPB : 1; /*!< [12] Loop Back Mode */ - uint32_t CLKSRC : 1; /*!< [13] CAN Engine Clock Source */ - uint32_t ERRMSK : 1; /*!< [14] Error Mask */ - uint32_t BOFFMSK : 1; /*!< [15] Bus Off Mask */ - uint32_t PSEG2 : 3; /*!< [18:16] Phase Segment 2 */ - uint32_t PSEG1 : 3; /*!< [21:19] Phase Segment 1 */ - uint32_t RJW : 2; /*!< [23:22] Resync Jump Width */ - uint32_t PRESDIV : 8; /*!< [31:24] Prescaler Division Factor */ - } B; -} hw_can_ctrl1_t; - -/*! - * @name Constants and macros for entire CAN_CTRL1 register - */ -/*@{*/ -#define HW_CAN_CTRL1_ADDR(x) ((x) + 0x4U) - -#define HW_CAN_CTRL1(x) (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x)) -#define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U) -#define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v)) -#define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) | (v))) -#define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v))) -#define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_CTRL1 bitfields - */ - -/*! - * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW) - * - * This 3-bit field defines the length of the Propagation Segment in the bit - * time. The valid programmable values are 0-7. This field can be written only in - * Freeze mode because it is blocked by hardware in other modes. Propagation - * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period. - */ -/*@{*/ -#define BP_CAN_CTRL1_PROPSEG (0U) /*!< Bit position for CAN_CTRL1_PROPSEG. */ -#define BM_CAN_CTRL1_PROPSEG (0x00000007U) /*!< Bit mask for CAN_CTRL1_PROPSEG. */ -#define BS_CAN_CTRL1_PROPSEG (3U) /*!< Bit field size in bits for CAN_CTRL1_PROPSEG. */ - -/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */ -#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG) - -/*! @brief Format value for bitfield CAN_CTRL1_PROPSEG. */ -#define BF_CAN_CTRL1_PROPSEG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PROPSEG) & BM_CAN_CTRL1_PROPSEG) - -/*! @brief Set the PROPSEG field to a new value. */ -#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v))) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field LOM[3] (RW) - * - * This bit configures FlexCAN to operate in Listen-Only mode. In this mode, - * transmission is disabled, all error counters are frozen and the module operates - * in a CAN Error Passive mode. Only messages acknowledged by another CAN station - * will be received. If FlexCAN detects a message that has not been acknowledged, - * it will flag a BIT0 error without changing the REC, as if it was trying to - * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the - * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is - * entered. There can be some delay between the Listen-Only mode request and - * acknowledge. This bit can be written only in Freeze mode because it is blocked by - * hardware in other modes. - * - * Values: - * - 0 - Listen-Only mode is deactivated. - * - 1 - FlexCAN module operates in Listen-Only mode. - */ -/*@{*/ -#define BP_CAN_CTRL1_LOM (3U) /*!< Bit position for CAN_CTRL1_LOM. */ -#define BM_CAN_CTRL1_LOM (0x00000008U) /*!< Bit mask for CAN_CTRL1_LOM. */ -#define BS_CAN_CTRL1_LOM (1U) /*!< Bit field size in bits for CAN_CTRL1_LOM. */ - -/*! @brief Read current value of the CAN_CTRL1_LOM field. */ -#define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM)) - -/*! @brief Format value for bitfield CAN_CTRL1_LOM. */ -#define BF_CAN_CTRL1_LOM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LOM) & BM_CAN_CTRL1_LOM) - -/*! @brief Set the LOM field to a new value. */ -#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field LBUF[4] (RW) - * - * This bit defines the ordering mechanism for Message Buffer transmission. When - * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit - * can be written only in Freeze mode because it is blocked by hardware in other - * modes. - * - * Values: - * - 0 - Buffer with highest priority is transmitted first. - * - 1 - Lowest number buffer is transmitted first. - */ -/*@{*/ -#define BP_CAN_CTRL1_LBUF (4U) /*!< Bit position for CAN_CTRL1_LBUF. */ -#define BM_CAN_CTRL1_LBUF (0x00000010U) /*!< Bit mask for CAN_CTRL1_LBUF. */ -#define BS_CAN_CTRL1_LBUF (1U) /*!< Bit field size in bits for CAN_CTRL1_LBUF. */ - -/*! @brief Read current value of the CAN_CTRL1_LBUF field. */ -#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF)) - -/*! @brief Format value for bitfield CAN_CTRL1_LBUF. */ -#define BF_CAN_CTRL1_LBUF(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LBUF) & BM_CAN_CTRL1_LBUF) - -/*! @brief Set the LBUF field to a new value. */ -#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field TSYN[5] (RW) - * - * This bit enables a mechanism that resets the free-running timer each time a - * message is received in Message Buffer 0. This feature provides means to - * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global - * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first - * available Mailbox, according to CTRL2[RFFN] setting, is used for timer - * synchronization instead of MB0. This bit can be written only in Freeze mode because it is - * blocked by hardware in other modes. - * - * Values: - * - 0 - Timer Sync feature disabled - * - 1 - Timer Sync feature enabled - */ -/*@{*/ -#define BP_CAN_CTRL1_TSYN (5U) /*!< Bit position for CAN_CTRL1_TSYN. */ -#define BM_CAN_CTRL1_TSYN (0x00000020U) /*!< Bit mask for CAN_CTRL1_TSYN. */ -#define BS_CAN_CTRL1_TSYN (1U) /*!< Bit field size in bits for CAN_CTRL1_TSYN. */ - -/*! @brief Read current value of the CAN_CTRL1_TSYN field. */ -#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN)) - -/*! @brief Format value for bitfield CAN_CTRL1_TSYN. */ -#define BF_CAN_CTRL1_TSYN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TSYN) & BM_CAN_CTRL1_TSYN) - -/*! @brief Set the TSYN field to a new value. */ -#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field BOFFREC[6] (RW) - * - * This bit defines how FlexCAN recovers from Bus Off state. If this bit is - * negated, automatic recovering from Bus Off state occurs according to the CAN - * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is - * disabled and the module remains in Bus Off state until the bit is negated by the - * user. If the negation occurs before 128 sequences of 11 recessive bits are - * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had - * never been asserted. If the negation occurs after 128 sequences of 11 - * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for - * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can - * be re-asserted again during Bus Off, but it will be effective only the next - * time the module enters Bus Off. If BOFFREC was negated when the module entered - * Bus Off, asserting it during Bus Off will not be effective for the current Bus - * Off recovery. - * - * Values: - * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec - * 2.0 part B. - * - 1 - Automatic recovering from Bus Off state disabled. - */ -/*@{*/ -#define BP_CAN_CTRL1_BOFFREC (6U) /*!< Bit position for CAN_CTRL1_BOFFREC. */ -#define BM_CAN_CTRL1_BOFFREC (0x00000040U) /*!< Bit mask for CAN_CTRL1_BOFFREC. */ -#define BS_CAN_CTRL1_BOFFREC (1U) /*!< Bit field size in bits for CAN_CTRL1_BOFFREC. */ - -/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */ -#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC)) - -/*! @brief Format value for bitfield CAN_CTRL1_BOFFREC. */ -#define BF_CAN_CTRL1_BOFFREC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFREC) & BM_CAN_CTRL1_BOFFREC) - -/*! @brief Set the BOFFREC field to a new value. */ -#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field SMP[7] (RW) - * - * This bit defines the sampling mode of CAN bits at the Rx input. This bit can - * be written only in Freeze mode because it is blocked by hardware in other - * modes. - * - * Values: - * - 0 - Just one sample is used to determine the bit value. - * - 1 - Three samples are used to determine the value of the received bit: the - * regular one (sample point) and 2 preceding samples; a majority rule is - * used. - */ -/*@{*/ -#define BP_CAN_CTRL1_SMP (7U) /*!< Bit position for CAN_CTRL1_SMP. */ -#define BM_CAN_CTRL1_SMP (0x00000080U) /*!< Bit mask for CAN_CTRL1_SMP. */ -#define BS_CAN_CTRL1_SMP (1U) /*!< Bit field size in bits for CAN_CTRL1_SMP. */ - -/*! @brief Read current value of the CAN_CTRL1_SMP field. */ -#define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP)) - -/*! @brief Format value for bitfield CAN_CTRL1_SMP. */ -#define BF_CAN_CTRL1_SMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_SMP) & BM_CAN_CTRL1_SMP) - -/*! @brief Set the SMP field to a new value. */ -#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field RWRNMSK[10] (RW) - * - * This bit provides a mask for the Rx Warning Interrupt associated with the - * RWRNINT flag in the Error and Status Register. This bit is read as zero when - * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is - * asserted. - * - * Values: - * - 0 - Rx Warning Interrupt disabled. - * - 1 - Rx Warning Interrupt enabled. - */ -/*@{*/ -#define BP_CAN_CTRL1_RWRNMSK (10U) /*!< Bit position for CAN_CTRL1_RWRNMSK. */ -#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) /*!< Bit mask for CAN_CTRL1_RWRNMSK. */ -#define BS_CAN_CTRL1_RWRNMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_RWRNMSK. */ - -/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */ -#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK)) - -/*! @brief Format value for bitfield CAN_CTRL1_RWRNMSK. */ -#define BF_CAN_CTRL1_RWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RWRNMSK) & BM_CAN_CTRL1_RWRNMSK) - -/*! @brief Set the RWRNMSK field to a new value. */ -#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field TWRNMSK[11] (RW) - * - * This bit provides a mask for the Tx Warning Interrupt associated with the - * TWRNINT flag in the Error and Status Register. This bit is read as zero when - * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is - * asserted. - * - * Values: - * - 0 - Tx Warning Interrupt disabled. - * - 1 - Tx Warning Interrupt enabled. - */ -/*@{*/ -#define BP_CAN_CTRL1_TWRNMSK (11U) /*!< Bit position for CAN_CTRL1_TWRNMSK. */ -#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) /*!< Bit mask for CAN_CTRL1_TWRNMSK. */ -#define BS_CAN_CTRL1_TWRNMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_TWRNMSK. */ - -/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */ -#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK)) - -/*! @brief Format value for bitfield CAN_CTRL1_TWRNMSK. */ -#define BF_CAN_CTRL1_TWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TWRNMSK) & BM_CAN_CTRL1_TWRNMSK) - -/*! @brief Set the TWRNMSK field to a new value. */ -#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field LPB[12] (RW) - * - * This bit configures FlexCAN to operate in Loop-Back mode. In this mode, - * FlexCAN performs an internal loop back that can be used for self test operation. - * The bit stream output of the transmitter is fed back internally to the receiver - * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the - * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting, - * and treats its own transmitted message as a message received from a remote - * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN - * frame acknowledge field, generating an internal acknowledge bit to ensure proper - * reception of its own message. Both transmit and receive interrupts are - * generated. This bit can be written only in Freeze mode because it is blocked by - * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because - * this will impede the self reception of a transmitted message. - * - * Values: - * - 0 - Loop Back disabled. - * - 1 - Loop Back enabled. - */ -/*@{*/ -#define BP_CAN_CTRL1_LPB (12U) /*!< Bit position for CAN_CTRL1_LPB. */ -#define BM_CAN_CTRL1_LPB (0x00001000U) /*!< Bit mask for CAN_CTRL1_LPB. */ -#define BS_CAN_CTRL1_LPB (1U) /*!< Bit field size in bits for CAN_CTRL1_LPB. */ - -/*! @brief Read current value of the CAN_CTRL1_LPB field. */ -#define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB)) - -/*! @brief Format value for bitfield CAN_CTRL1_LPB. */ -#define BF_CAN_CTRL1_LPB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LPB) & BM_CAN_CTRL1_LPB) - -/*! @brief Set the LPB field to a new value. */ -#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field CLKSRC[13] (RW) - * - * This bit selects the clock source to the CAN Protocol Engine (PE) to be - * either the peripheral clock (driven by the PLL) or the crystal oscillator clock. - * The selected clock is the one fed to the prescaler to generate the Serial Clock - * (Sclock). In order to guarantee reliable operation, this bit can be written - * only in Disable mode because it is blocked by hardware in other modes. See - * Section "Protocol Timing". - * - * Values: - * - 0 - The CAN engine clock source is the oscillator clock. Under this - * condition, the oscillator clock frequency must be lower than the bus clock. - * - 1 - The CAN engine clock source is the peripheral clock. - */ -/*@{*/ -#define BP_CAN_CTRL1_CLKSRC (13U) /*!< Bit position for CAN_CTRL1_CLKSRC. */ -#define BM_CAN_CTRL1_CLKSRC (0x00002000U) /*!< Bit mask for CAN_CTRL1_CLKSRC. */ -#define BS_CAN_CTRL1_CLKSRC (1U) /*!< Bit field size in bits for CAN_CTRL1_CLKSRC. */ - -/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */ -#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC)) - -/*! @brief Format value for bitfield CAN_CTRL1_CLKSRC. */ -#define BF_CAN_CTRL1_CLKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_CLKSRC) & BM_CAN_CTRL1_CLKSRC) - -/*! @brief Set the CLKSRC field to a new value. */ -#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field ERRMSK[14] (RW) - * - * This bit provides a mask for the Error Interrupt. - * - * Values: - * - 0 - Error interrupt disabled. - * - 1 - Error interrupt enabled. - */ -/*@{*/ -#define BP_CAN_CTRL1_ERRMSK (14U) /*!< Bit position for CAN_CTRL1_ERRMSK. */ -#define BM_CAN_CTRL1_ERRMSK (0x00004000U) /*!< Bit mask for CAN_CTRL1_ERRMSK. */ -#define BS_CAN_CTRL1_ERRMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_ERRMSK. */ - -/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */ -#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK)) - -/*! @brief Format value for bitfield CAN_CTRL1_ERRMSK. */ -#define BF_CAN_CTRL1_ERRMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_ERRMSK) & BM_CAN_CTRL1_ERRMSK) - -/*! @brief Set the ERRMSK field to a new value. */ -#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field BOFFMSK[15] (RW) - * - * This bit provides a mask for the Bus Off Interrupt. - * - * Values: - * - 0 - Bus Off interrupt disabled. - * - 1 - Bus Off interrupt enabled. - */ -/*@{*/ -#define BP_CAN_CTRL1_BOFFMSK (15U) /*!< Bit position for CAN_CTRL1_BOFFMSK. */ -#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) /*!< Bit mask for CAN_CTRL1_BOFFMSK. */ -#define BS_CAN_CTRL1_BOFFMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_BOFFMSK. */ - -/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */ -#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK)) - -/*! @brief Format value for bitfield CAN_CTRL1_BOFFMSK. */ -#define BF_CAN_CTRL1_BOFFMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFMSK) & BM_CAN_CTRL1_BOFFMSK) - -/*! @brief Set the BOFFMSK field to a new value. */ -#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field PSEG2[18:16] (RW) - * - * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit - * time. The valid programmable values are 1-7. This field can be written only in - * Freeze mode because it is blocked by hardware in other modes. Phase Buffer - * Segment 2 = (PSEG2 + 1) * Time-Quanta. - */ -/*@{*/ -#define BP_CAN_CTRL1_PSEG2 (16U) /*!< Bit position for CAN_CTRL1_PSEG2. */ -#define BM_CAN_CTRL1_PSEG2 (0x00070000U) /*!< Bit mask for CAN_CTRL1_PSEG2. */ -#define BS_CAN_CTRL1_PSEG2 (3U) /*!< Bit field size in bits for CAN_CTRL1_PSEG2. */ - -/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */ -#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2) - -/*! @brief Format value for bitfield CAN_CTRL1_PSEG2. */ -#define BF_CAN_CTRL1_PSEG2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG2) & BM_CAN_CTRL1_PSEG2) - -/*! @brief Set the PSEG2 field to a new value. */ -#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v))) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field PSEG1[21:19] (RW) - * - * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit - * time. The valid programmable values are 0-7. This field can be written only in - * Freeze mode because it is blocked by hardware in other modes. Phase Buffer - * Segment 1 = (PSEG1 + 1) * Time-Quanta. - */ -/*@{*/ -#define BP_CAN_CTRL1_PSEG1 (19U) /*!< Bit position for CAN_CTRL1_PSEG1. */ -#define BM_CAN_CTRL1_PSEG1 (0x00380000U) /*!< Bit mask for CAN_CTRL1_PSEG1. */ -#define BS_CAN_CTRL1_PSEG1 (3U) /*!< Bit field size in bits for CAN_CTRL1_PSEG1. */ - -/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */ -#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1) - -/*! @brief Format value for bitfield CAN_CTRL1_PSEG1. */ -#define BF_CAN_CTRL1_PSEG1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG1) & BM_CAN_CTRL1_PSEG1) - -/*! @brief Set the PSEG1 field to a new value. */ -#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v))) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field RJW[23:22] (RW) - * - * This 2-bit field defines the maximum number of time quanta that a bit time - * can be changed by one re-synchronization. One time quantum is equal to the - * Sclock period. The valid programmable values are 0-3. This field can be written - * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump - * Width = RJW + 1. - */ -/*@{*/ -#define BP_CAN_CTRL1_RJW (22U) /*!< Bit position for CAN_CTRL1_RJW. */ -#define BM_CAN_CTRL1_RJW (0x00C00000U) /*!< Bit mask for CAN_CTRL1_RJW. */ -#define BS_CAN_CTRL1_RJW (2U) /*!< Bit field size in bits for CAN_CTRL1_RJW. */ - -/*! @brief Read current value of the CAN_CTRL1_RJW field. */ -#define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW) - -/*! @brief Format value for bitfield CAN_CTRL1_RJW. */ -#define BF_CAN_CTRL1_RJW(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RJW) & BM_CAN_CTRL1_RJW) - -/*! @brief Set the RJW field to a new value. */ -#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v))) -/*@}*/ - -/*! - * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW) - * - * This 8-bit field defines the ratio between the PE clock frequency and the - * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of - * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE - * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum - * Sclock frequency equal to the PE clock frequency divided by 256. See Section - * "Protocol Timing". This field can be written only in Freeze mode because it is - * blocked by hardware in other modes. Sclock frequency = PE clock frequency / - * (PRESDIV + 1) - */ -/*@{*/ -#define BP_CAN_CTRL1_PRESDIV (24U) /*!< Bit position for CAN_CTRL1_PRESDIV. */ -#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) /*!< Bit mask for CAN_CTRL1_PRESDIV. */ -#define BS_CAN_CTRL1_PRESDIV (8U) /*!< Bit field size in bits for CAN_CTRL1_PRESDIV. */ - -/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */ -#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV) - -/*! @brief Format value for bitfield CAN_CTRL1_PRESDIV. */ -#define BF_CAN_CTRL1_PRESDIV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PRESDIV) & BM_CAN_CTRL1_PRESDIV) - -/*! @brief Set the PRESDIV field to a new value. */ -#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v))) -/*@}*/ - -/******************************************************************************* - * HW_CAN_TIMER - Free Running Timer - ******************************************************************************/ - -/*! - * @brief HW_CAN_TIMER - Free Running Timer (RW) - * - * Reset value: 0x00000000U - * - * This register represents a 16-bit free running counter that can be read and - * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to - * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which - * defines the baud rate on the CAN bus. During a message transmission/reception, - * it increments by one for each bit that is received or transmitted. When there - * is no message on the bus, it counts using the previously programmed baud - * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The - * timer value is captured when the second bit of the identifier field of any frame - * is on the CAN bus. This captured value is written into the Time Stamp entry - * in a message buffer after a successful reception or transmission of a message. - * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is - * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU - * can write to this register anytime. However, if the write occurs at the same - * time that the Timer is being reset by a reception in the first Mailbox, then - * the write value is discarded. Reading this register affects the Mailbox - * Unlocking procedure; see Section "Mailbox Lock Mechanism". - */ -typedef union _hw_can_timer -{ - uint32_t U; - struct _hw_can_timer_bitfields - { - uint32_t TIMER : 16; /*!< [15:0] Timer Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_can_timer_t; - -/*! - * @name Constants and macros for entire CAN_TIMER register - */ -/*@{*/ -#define HW_CAN_TIMER_ADDR(x) ((x) + 0x8U) - -#define HW_CAN_TIMER(x) (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x)) -#define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U) -#define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v)) -#define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) | (v))) -#define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v))) -#define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_TIMER bitfields - */ - -/*! - * @name Register CAN_TIMER, field TIMER[15:0] (RW) - * - * Contains the free-running counter value. - */ -/*@{*/ -#define BP_CAN_TIMER_TIMER (0U) /*!< Bit position for CAN_TIMER_TIMER. */ -#define BM_CAN_TIMER_TIMER (0x0000FFFFU) /*!< Bit mask for CAN_TIMER_TIMER. */ -#define BS_CAN_TIMER_TIMER (16U) /*!< Bit field size in bits for CAN_TIMER_TIMER. */ - -/*! @brief Read current value of the CAN_TIMER_TIMER field. */ -#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER) - -/*! @brief Format value for bitfield CAN_TIMER_TIMER. */ -#define BF_CAN_TIMER_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_CAN_TIMER_TIMER) & BM_CAN_TIMER_TIMER) - -/*! @brief Set the TIMER field to a new value. */ -#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v))) -/*@}*/ - -/******************************************************************************* - * HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW) - * - * Reset value: 0xFFFFFFFFU - * - * This register is located in RAM. RXMGMASK is provided for legacy application - * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When - * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to - * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual - * mask registers. This register can only be written in Freeze mode as it is - * blocked by hardware in other modes. - */ -typedef union _hw_can_rxmgmask -{ - uint32_t U; - struct _hw_can_rxmgmask_bitfields - { - uint32_t MG : 32; /*!< [31:0] Rx Mailboxes Global Mask Bits */ - } B; -} hw_can_rxmgmask_t; - -/*! - * @name Constants and macros for entire CAN_RXMGMASK register - */ -/*@{*/ -#define HW_CAN_RXMGMASK_ADDR(x) ((x) + 0x10U) - -#define HW_CAN_RXMGMASK(x) (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x)) -#define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U) -#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v)) -#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) | (v))) -#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v))) -#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_RXMGMASK bitfields - */ - -/*! - * @name Register CAN_RXMGMASK, field MG[31:0] (RW) - * - * These bits mask the Mailbox filter bits. Note that the alignment with the ID - * word of the Mailbox is not perfect as the two most significant MG bits affect - * the fields RTR and IDE, which are located in the Control and Status word of - * the Mailbox. The following table shows in detail which MG bits mask each Mailbox - * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an - * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN] - * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the - * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit - * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit - * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0] - * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - - - * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29] - * - * Values: - * - 0 - The corresponding bit in the filter is "don't care." - * - 1 - The corresponding bit in the filter is checked. - */ -/*@{*/ -#define BP_CAN_RXMGMASK_MG (0U) /*!< Bit position for CAN_RXMGMASK_MG. */ -#define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) /*!< Bit mask for CAN_RXMGMASK_MG. */ -#define BS_CAN_RXMGMASK_MG (32U) /*!< Bit field size in bits for CAN_RXMGMASK_MG. */ - -/*! @brief Read current value of the CAN_RXMGMASK_MG field. */ -#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U) - -/*! @brief Format value for bitfield CAN_RXMGMASK_MG. */ -#define BF_CAN_RXMGMASK_MG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXMGMASK_MG) & BM_CAN_RXMGMASK_MG) - -/*! @brief Set the MG field to a new value. */ -#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_RX14MASK - Rx 14 Mask register - ******************************************************************************/ - -/*! - * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW) - * - * Reset value: 0xFFFFFFFFU - * - * This register is located in RAM. RX14MASK is provided for legacy application - * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK - * is used to mask the filter fields of Message Buffer 14. This register can only - * be programmed while the module is in Freeze mode as it is blocked by hardware - * in other modes. - */ -typedef union _hw_can_rx14mask -{ - uint32_t U; - struct _hw_can_rx14mask_bitfields - { - uint32_t RX14M : 32; /*!< [31:0] Rx Buffer 14 Mask Bits */ - } B; -} hw_can_rx14mask_t; - -/*! - * @name Constants and macros for entire CAN_RX14MASK register - */ -/*@{*/ -#define HW_CAN_RX14MASK_ADDR(x) ((x) + 0x14U) - -#define HW_CAN_RX14MASK(x) (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x)) -#define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U) -#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v)) -#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) | (v))) -#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v))) -#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_RX14MASK bitfields - */ - -/*! - * @name Register CAN_RX14MASK, field RX14M[31:0] (RW) - * - * Each mask bit masks the corresponding Mailbox 14 filter field in the same way - * that RXMGMASK masks other Mailboxes' filters. See the description of the - * CAN_RXMGMASK register. - * - * Values: - * - 0 - The corresponding bit in the filter is "don't care." - * - 1 - The corresponding bit in the filter is checked. - */ -/*@{*/ -#define BP_CAN_RX14MASK_RX14M (0U) /*!< Bit position for CAN_RX14MASK_RX14M. */ -#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX14MASK_RX14M. */ -#define BS_CAN_RX14MASK_RX14M (32U) /*!< Bit field size in bits for CAN_RX14MASK_RX14M. */ - -/*! @brief Read current value of the CAN_RX14MASK_RX14M field. */ -#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U) - -/*! @brief Format value for bitfield CAN_RX14MASK_RX14M. */ -#define BF_CAN_RX14MASK_RX14M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX14MASK_RX14M) & BM_CAN_RX14MASK_RX14M) - -/*! @brief Set the RX14M field to a new value. */ -#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_RX15MASK - Rx 15 Mask register - ******************************************************************************/ - -/*! - * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW) - * - * Reset value: 0xFFFFFFFFU - * - * This register is located in RAM. RX15MASK is provided for legacy application - * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK - * is used to mask the filter fields of Message Buffer 15. This register can be - * programmed only while the module is in Freeze mode because it is blocked by - * hardware in other modes. - */ -typedef union _hw_can_rx15mask -{ - uint32_t U; - struct _hw_can_rx15mask_bitfields - { - uint32_t RX15M : 32; /*!< [31:0] Rx Buffer 15 Mask Bits */ - } B; -} hw_can_rx15mask_t; - -/*! - * @name Constants and macros for entire CAN_RX15MASK register - */ -/*@{*/ -#define HW_CAN_RX15MASK_ADDR(x) ((x) + 0x18U) - -#define HW_CAN_RX15MASK(x) (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x)) -#define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U) -#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v)) -#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) | (v))) -#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v))) -#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_RX15MASK bitfields - */ - -/*! - * @name Register CAN_RX15MASK, field RX15M[31:0] (RW) - * - * Each mask bit masks the corresponding Mailbox 15 filter field in the same way - * that RXMGMASK masks other Mailboxes' filters. See the description of the - * CAN_RXMGMASK register. - * - * Values: - * - 0 - The corresponding bit in the filter is "don't care." - * - 1 - The corresponding bit in the filter is checked. - */ -/*@{*/ -#define BP_CAN_RX15MASK_RX15M (0U) /*!< Bit position for CAN_RX15MASK_RX15M. */ -#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX15MASK_RX15M. */ -#define BS_CAN_RX15MASK_RX15M (32U) /*!< Bit field size in bits for CAN_RX15MASK_RX15M. */ - -/*! @brief Read current value of the CAN_RX15MASK_RX15M field. */ -#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U) - -/*! @brief Format value for bitfield CAN_RX15MASK_RX15M. */ -#define BF_CAN_RX15MASK_RX15M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX15MASK_RX15M) & BM_CAN_RX15MASK_RX15M) - -/*! @brief Set the RX15M field to a new value. */ -#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_ECR - Error Counter - ******************************************************************************/ - -/*! - * @brief HW_CAN_ECR - Error Counter (RW) - * - * Reset value: 0x00000000U - * - * This register has two 8-bit fields reflecting the value of two FlexCAN error - * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter - * (RXERRCNT field). The rules for increasing and decreasing these counters are - * described in the CAN protocol and are completely implemented in the FlexCAN - * module. Both counters are read-only except in Freeze mode, where they can be - * written by the CPU. FlexCAN responds to any bus state as described in the protocol, - * for example, transmit Error Active or Error Passive flag, delay its - * transmission start time (Error Passive) and avoid any influence on the bus when in Bus - * Off state. The following are the basic rules for FlexCAN bus state transitions: - * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to - * 128, the FLTCONF field in the Error and Status Register is updated to reflect - * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either - * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the - * other already satisfies this condition, the FLTCONF field in the Error and - * Status Register is updated to reflect 'Error Active' state. If the value of - * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status - * Register is updated to reflect 'Bus Off' state, and an interrupt may be - * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off' - * state, then TXERRCNT is cascaded together with another internal counter to count - * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, - * TXERRCNT is reset to zero and counts in a manner where the internal counter counts - * 11 such bits and then wraps around while incrementing the TXERRCNT. When - * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status - * Register is updated to be 'Error Active' and both error counters are reset to zero. - * At any instance of dominant bit following a stream of less than 11 - * consecutive recessive bits, the internal counter resets itself to zero without affecting - * the TXERRCNT value. If during system start-up, only one node is operating, - * then its TXERRCNT increases in each message it is trying to transmit, as a - * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status - * Register). After the transition to 'Error Passive' state, the TXERRCNT does not - * increment anymore by acknowledge errors. Therefore the device never goes to - * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it - * is not incremented further, even if more errors are detected while being a - * receiver. At the next successful message reception, the counter is set to a value - * between 119 and 127 to resume to 'Error Active' state. - */ -typedef union _hw_can_ecr -{ - uint32_t U; - struct _hw_can_ecr_bitfields - { - uint32_t TXERRCNT : 8; /*!< [7:0] Transmit Error Counter */ - uint32_t RXERRCNT : 8; /*!< [15:8] Receive Error Counter */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_can_ecr_t; - -/*! - * @name Constants and macros for entire CAN_ECR register - */ -/*@{*/ -#define HW_CAN_ECR_ADDR(x) ((x) + 0x1CU) - -#define HW_CAN_ECR(x) (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x)) -#define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U) -#define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v)) -#define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) | (v))) -#define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v))) -#define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_ECR bitfields - */ - -/*! - * @name Register CAN_ECR, field TXERRCNT[7:0] (RW) - */ -/*@{*/ -#define BP_CAN_ECR_TXERRCNT (0U) /*!< Bit position for CAN_ECR_TXERRCNT. */ -#define BM_CAN_ECR_TXERRCNT (0x000000FFU) /*!< Bit mask for CAN_ECR_TXERRCNT. */ -#define BS_CAN_ECR_TXERRCNT (8U) /*!< Bit field size in bits for CAN_ECR_TXERRCNT. */ - -/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */ -#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT) - -/*! @brief Format value for bitfield CAN_ECR_TXERRCNT. */ -#define BF_CAN_ECR_TXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_TXERRCNT) & BM_CAN_ECR_TXERRCNT) - -/*! @brief Set the TXERRCNT field to a new value. */ -#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v))) -/*@}*/ - -/*! - * @name Register CAN_ECR, field RXERRCNT[15:8] (RW) - */ -/*@{*/ -#define BP_CAN_ECR_RXERRCNT (8U) /*!< Bit position for CAN_ECR_RXERRCNT. */ -#define BM_CAN_ECR_RXERRCNT (0x0000FF00U) /*!< Bit mask for CAN_ECR_RXERRCNT. */ -#define BS_CAN_ECR_RXERRCNT (8U) /*!< Bit field size in bits for CAN_ECR_RXERRCNT. */ - -/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */ -#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT) - -/*! @brief Format value for bitfield CAN_ECR_RXERRCNT. */ -#define BF_CAN_ECR_RXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_RXERRCNT) & BM_CAN_ECR_RXERRCNT) - -/*! @brief Set the RXERRCNT field to a new value. */ -#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_CAN_ESR1 - Error and Status 1 register - ******************************************************************************/ - -/*! - * @brief HW_CAN_ESR1 - Error and Status 1 register (RW) - * - * Reset value: 0x00000000U - * - * This register reflects various error conditions, some general status of the - * device and it is the source of interrupts to the CPU. The CPU read action - * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those - * that occurred since the last time the CPU read this register. Bits 9-3 are - * status bits. The following table shows the FlexCAN state variables and their - * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX - * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0 - * Transmitting 1 0 0 1 Receiving - */ -typedef union _hw_can_esr1 -{ - uint32_t U; - struct _hw_can_esr1_bitfields - { - uint32_t WAKINT : 1; /*!< [0] Wake-Up Interrupt */ - uint32_t ERRINT : 1; /*!< [1] Error Interrupt */ - uint32_t BOFFINT : 1; /*!< [2] Bus Off Interrupt */ - uint32_t RX : 1; /*!< [3] FlexCAN In Reception */ - uint32_t FLTCONF : 2; /*!< [5:4] Fault Confinement State */ - uint32_t TX : 1; /*!< [6] FlexCAN In Transmission */ - uint32_t IDLE : 1; /*!< [7] */ - uint32_t RXWRN : 1; /*!< [8] Rx Error Warning */ - uint32_t TXWRN : 1; /*!< [9] TX Error Warning */ - uint32_t STFERR : 1; /*!< [10] Stuffing Error */ - uint32_t FRMERR : 1; /*!< [11] Form Error */ - uint32_t CRCERR : 1; /*!< [12] Cyclic Redundancy Check Error */ - uint32_t ACKERR : 1; /*!< [13] Acknowledge Error */ - uint32_t BIT0ERR : 1; /*!< [14] Bit0 Error */ - uint32_t BIT1ERR : 1; /*!< [15] Bit1 Error */ - uint32_t RWRNINT : 1; /*!< [16] Rx Warning Interrupt Flag */ - uint32_t TWRNINT : 1; /*!< [17] Tx Warning Interrupt Flag */ - uint32_t SYNCH : 1; /*!< [18] CAN Synchronization Status */ - uint32_t RESERVED0 : 13; /*!< [31:19] */ - } B; -} hw_can_esr1_t; - -/*! - * @name Constants and macros for entire CAN_ESR1 register - */ -/*@{*/ -#define HW_CAN_ESR1_ADDR(x) ((x) + 0x20U) - -#define HW_CAN_ESR1(x) (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x)) -#define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U) -#define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v)) -#define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) | (v))) -#define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v))) -#define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_ESR1 bitfields - */ - -/*! - * @name Register CAN_ESR1, field WAKINT[0] (W1C) - * - * This field applies when FlexCAN is in low-power mode under Self Wake Up - * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN - * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU. - * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag - * is masked. The CPU must clear this flag before disabling the bit. Otherwise - * it will be set when the SLFWAK is set again. Writing 0 has no effect. - * - * Values: - * - 0 - No such occurrence. - * - 1 - Indicates a recessive to dominant transition was received on the CAN - * bus. - */ -/*@{*/ -#define BP_CAN_ESR1_WAKINT (0U) /*!< Bit position for CAN_ESR1_WAKINT. */ -#define BM_CAN_ESR1_WAKINT (0x00000001U) /*!< Bit mask for CAN_ESR1_WAKINT. */ -#define BS_CAN_ESR1_WAKINT (1U) /*!< Bit field size in bits for CAN_ESR1_WAKINT. */ - -/*! @brief Read current value of the CAN_ESR1_WAKINT field. */ -#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT)) - -/*! @brief Format value for bitfield CAN_ESR1_WAKINT. */ -#define BF_CAN_ESR1_WAKINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_WAKINT) & BM_CAN_ESR1_WAKINT) - -/*! @brief Set the WAKINT field to a new value. */ -#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field ERRINT[1] (W1C) - * - * This bit indicates that at least one of the Error Bits (bits 15-10) is set. - * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated - * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect. - * - * Values: - * - 0 - No such occurrence. - * - 1 - Indicates setting of any Error Bit in the Error and Status Register. - */ -/*@{*/ -#define BP_CAN_ESR1_ERRINT (1U) /*!< Bit position for CAN_ESR1_ERRINT. */ -#define BM_CAN_ESR1_ERRINT (0x00000002U) /*!< Bit mask for CAN_ESR1_ERRINT. */ -#define BS_CAN_ESR1_ERRINT (1U) /*!< Bit field size in bits for CAN_ESR1_ERRINT. */ - -/*! @brief Read current value of the CAN_ESR1_ERRINT field. */ -#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT)) - -/*! @brief Format value for bitfield CAN_ESR1_ERRINT. */ -#define BF_CAN_ESR1_ERRINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_ERRINT) & BM_CAN_ESR1_ERRINT) - -/*! @brief Set the ERRINT field to a new value. */ -#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field BOFFINT[2] (W1C) - * - * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding - * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to - * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect. - * - * Values: - * - 0 - No such occurrence. - * - 1 - FlexCAN module entered Bus Off state. - */ -/*@{*/ -#define BP_CAN_ESR1_BOFFINT (2U) /*!< Bit position for CAN_ESR1_BOFFINT. */ -#define BM_CAN_ESR1_BOFFINT (0x00000004U) /*!< Bit mask for CAN_ESR1_BOFFINT. */ -#define BS_CAN_ESR1_BOFFINT (1U) /*!< Bit field size in bits for CAN_ESR1_BOFFINT. */ - -/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */ -#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT)) - -/*! @brief Format value for bitfield CAN_ESR1_BOFFINT. */ -#define BF_CAN_ESR1_BOFFINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_BOFFINT) & BM_CAN_ESR1_BOFFINT) - -/*! @brief Set the BOFFINT field to a new value. */ -#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field RX[3] (RO) - * - * This bit indicates if FlexCAN is receiving a message. See the table in the - * overall CAN_ESR1 register description. - * - * Values: - * - 0 - FlexCAN is not receiving a message. - * - 1 - FlexCAN is receiving a message. - */ -/*@{*/ -#define BP_CAN_ESR1_RX (3U) /*!< Bit position for CAN_ESR1_RX. */ -#define BM_CAN_ESR1_RX (0x00000008U) /*!< Bit mask for CAN_ESR1_RX. */ -#define BS_CAN_ESR1_RX (1U) /*!< Bit field size in bits for CAN_ESR1_RX. */ - -/*! @brief Read current value of the CAN_ESR1_RX field. */ -#define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field FLTCONF[5:4] (RO) - * - * This 2-bit field indicates the Confinement State of the FlexCAN module. If - * the LOM bit in the Control Register is asserted, after some delay that depends - * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very - * same delay affects the way how FLTCONF reflects an update to ECR register by - * the CPU. It may be necessary up to one CAN bit time to get them coherent - * again. Because the Control Register is not affected by soft reset, the FLTCONF - * field will not be affected by soft reset if the LOM bit is asserted. - * - * Values: - * - 00 - Error Active - * - 01 - Error Passive - * - 1x - Bus Off - */ -/*@{*/ -#define BP_CAN_ESR1_FLTCONF (4U) /*!< Bit position for CAN_ESR1_FLTCONF. */ -#define BM_CAN_ESR1_FLTCONF (0x00000030U) /*!< Bit mask for CAN_ESR1_FLTCONF. */ -#define BS_CAN_ESR1_FLTCONF (2U) /*!< Bit field size in bits for CAN_ESR1_FLTCONF. */ - -/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */ -#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field TX[6] (RO) - * - * This bit indicates if FlexCAN is transmitting a message. See the table in the - * overall CAN_ESR1 register description. - * - * Values: - * - 0 - FlexCAN is not transmitting a message. - * - 1 - FlexCAN is transmitting a message. - */ -/*@{*/ -#define BP_CAN_ESR1_TX (6U) /*!< Bit position for CAN_ESR1_TX. */ -#define BM_CAN_ESR1_TX (0x00000040U) /*!< Bit mask for CAN_ESR1_TX. */ -#define BS_CAN_ESR1_TX (1U) /*!< Bit field size in bits for CAN_ESR1_TX. */ - -/*! @brief Read current value of the CAN_ESR1_TX field. */ -#define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field IDLE[7] (RO) - * - * This bit indicates when CAN bus is in IDLE state. See the table in the - * overall CAN_ESR1 register description. - * - * Values: - * - 0 - No such occurrence. - * - 1 - CAN bus is now IDLE. - */ -/*@{*/ -#define BP_CAN_ESR1_IDLE (7U) /*!< Bit position for CAN_ESR1_IDLE. */ -#define BM_CAN_ESR1_IDLE (0x00000080U) /*!< Bit mask for CAN_ESR1_IDLE. */ -#define BS_CAN_ESR1_IDLE (1U) /*!< Bit field size in bits for CAN_ESR1_IDLE. */ - -/*! @brief Read current value of the CAN_ESR1_IDLE field. */ -#define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field RXWRN[8] (RO) - * - * This bit indicates when repetitive errors are occurring during message - * reception. This bit is not updated during Freeze mode. - * - * Values: - * - 0 - No such occurrence. - * - 1 - RXERRCNT is greater than or equal to 96. - */ -/*@{*/ -#define BP_CAN_ESR1_RXWRN (8U) /*!< Bit position for CAN_ESR1_RXWRN. */ -#define BM_CAN_ESR1_RXWRN (0x00000100U) /*!< Bit mask for CAN_ESR1_RXWRN. */ -#define BS_CAN_ESR1_RXWRN (1U) /*!< Bit field size in bits for CAN_ESR1_RXWRN. */ - -/*! @brief Read current value of the CAN_ESR1_RXWRN field. */ -#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field TXWRN[9] (RO) - * - * This bit indicates when repetitive errors are occurring during message - * transmission. This bit is not updated during Freeze mode. - * - * Values: - * - 0 - No such occurrence. - * - 1 - TXERRCNT is greater than or equal to 96. - */ -/*@{*/ -#define BP_CAN_ESR1_TXWRN (9U) /*!< Bit position for CAN_ESR1_TXWRN. */ -#define BM_CAN_ESR1_TXWRN (0x00000200U) /*!< Bit mask for CAN_ESR1_TXWRN. */ -#define BS_CAN_ESR1_TXWRN (1U) /*!< Bit field size in bits for CAN_ESR1_TXWRN. */ - -/*! @brief Read current value of the CAN_ESR1_TXWRN field. */ -#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field STFERR[10] (RO) - * - * This bit indicates that a Stuffing Error has been etected. - * - * Values: - * - 0 - No such occurrence. - * - 1 - A Stuffing Error occurred since last read of this register. - */ -/*@{*/ -#define BP_CAN_ESR1_STFERR (10U) /*!< Bit position for CAN_ESR1_STFERR. */ -#define BM_CAN_ESR1_STFERR (0x00000400U) /*!< Bit mask for CAN_ESR1_STFERR. */ -#define BS_CAN_ESR1_STFERR (1U) /*!< Bit field size in bits for CAN_ESR1_STFERR. */ - -/*! @brief Read current value of the CAN_ESR1_STFERR field. */ -#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field FRMERR[11] (RO) - * - * This bit indicates that a Form Error has been detected by the receiver node, - * that is, a fixed-form bit field contains at least one illegal bit. - * - * Values: - * - 0 - No such occurrence. - * - 1 - A Form Error occurred since last read of this register. - */ -/*@{*/ -#define BP_CAN_ESR1_FRMERR (11U) /*!< Bit position for CAN_ESR1_FRMERR. */ -#define BM_CAN_ESR1_FRMERR (0x00000800U) /*!< Bit mask for CAN_ESR1_FRMERR. */ -#define BS_CAN_ESR1_FRMERR (1U) /*!< Bit field size in bits for CAN_ESR1_FRMERR. */ - -/*! @brief Read current value of the CAN_ESR1_FRMERR field. */ -#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field CRCERR[12] (RO) - * - * This bit indicates that a CRC Error has been detected by the receiver node, - * that is, the calculated CRC is different from the received. - * - * Values: - * - 0 - No such occurrence. - * - 1 - A CRC error occurred since last read of this register. - */ -/*@{*/ -#define BP_CAN_ESR1_CRCERR (12U) /*!< Bit position for CAN_ESR1_CRCERR. */ -#define BM_CAN_ESR1_CRCERR (0x00001000U) /*!< Bit mask for CAN_ESR1_CRCERR. */ -#define BS_CAN_ESR1_CRCERR (1U) /*!< Bit field size in bits for CAN_ESR1_CRCERR. */ - -/*! @brief Read current value of the CAN_ESR1_CRCERR field. */ -#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field ACKERR[13] (RO) - * - * This bit indicates that an Acknowledge Error has been detected by the - * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT. - * - * Values: - * - 0 - No such occurrence. - * - 1 - An ACK error occurred since last read of this register. - */ -/*@{*/ -#define BP_CAN_ESR1_ACKERR (13U) /*!< Bit position for CAN_ESR1_ACKERR. */ -#define BM_CAN_ESR1_ACKERR (0x00002000U) /*!< Bit mask for CAN_ESR1_ACKERR. */ -#define BS_CAN_ESR1_ACKERR (1U) /*!< Bit field size in bits for CAN_ESR1_ACKERR. */ - -/*! @brief Read current value of the CAN_ESR1_ACKERR field. */ -#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field BIT0ERR[14] (RO) - * - * This bit indicates when an inconsistency occurs between the transmitted and - * the received bit in a message. - * - * Values: - * - 0 - No such occurrence. - * - 1 - At least one bit sent as dominant is received as recessive. - */ -/*@{*/ -#define BP_CAN_ESR1_BIT0ERR (14U) /*!< Bit position for CAN_ESR1_BIT0ERR. */ -#define BM_CAN_ESR1_BIT0ERR (0x00004000U) /*!< Bit mask for CAN_ESR1_BIT0ERR. */ -#define BS_CAN_ESR1_BIT0ERR (1U) /*!< Bit field size in bits for CAN_ESR1_BIT0ERR. */ - -/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */ -#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field BIT1ERR[15] (RO) - * - * This bit indicates when an inconsistency occurs between the transmitted and - * the received bit in a message. This bit is not set by a transmitter in case of - * arbitration field or ACK slot, or in case of a node sending a passive error - * flag that detects dominant bits. - * - * Values: - * - 0 - No such occurrence. - * - 1 - At least one bit sent as recessive is received as dominant. - */ -/*@{*/ -#define BP_CAN_ESR1_BIT1ERR (15U) /*!< Bit position for CAN_ESR1_BIT1ERR. */ -#define BM_CAN_ESR1_BIT1ERR (0x00008000U) /*!< Bit mask for CAN_ESR1_BIT1ERR. */ -#define BS_CAN_ESR1_BIT1ERR (1U) /*!< Bit field size in bits for CAN_ESR1_BIT1ERR. */ - -/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */ -#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field RWRNINT[16] (W1C) - * - * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN - * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If - * the corresponding mask bit in the Control Register (RWRNMSK) is set, an - * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When - * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling - * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no - * effect. This bit is not updated during Freeze mode. - * - * Values: - * - 0 - No such occurrence. - * - 1 - The Rx error counter transitioned from less than 96 to greater than or - * equal to 96. - */ -/*@{*/ -#define BP_CAN_ESR1_RWRNINT (16U) /*!< Bit position for CAN_ESR1_RWRNINT. */ -#define BM_CAN_ESR1_RWRNINT (0x00010000U) /*!< Bit mask for CAN_ESR1_RWRNINT. */ -#define BS_CAN_ESR1_RWRNINT (1U) /*!< Bit field size in bits for CAN_ESR1_RWRNINT. */ - -/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */ -#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT)) - -/*! @brief Format value for bitfield CAN_ESR1_RWRNINT. */ -#define BF_CAN_ESR1_RWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_RWRNINT) & BM_CAN_ESR1_RWRNINT) - -/*! @brief Set the RWRNINT field to a new value. */ -#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field TWRNINT[17] (W1C) - * - * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN - * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If - * the corresponding mask bit in the Control Register (TWRNMSK) is set, an - * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN - * is negated, this flag is masked. CPU must clear this flag before disabling - * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no - * effect. This flag is not generated during Bus Off state. This bit is not - * updated during Freeze mode. - * - * Values: - * - 0 - No such occurrence. - * - 1 - The Tx error counter transitioned from less than 96 to greater than or - * equal to 96. - */ -/*@{*/ -#define BP_CAN_ESR1_TWRNINT (17U) /*!< Bit position for CAN_ESR1_TWRNINT. */ -#define BM_CAN_ESR1_TWRNINT (0x00020000U) /*!< Bit mask for CAN_ESR1_TWRNINT. */ -#define BS_CAN_ESR1_TWRNINT (1U) /*!< Bit field size in bits for CAN_ESR1_TWRNINT. */ - -/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */ -#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT)) - -/*! @brief Format value for bitfield CAN_ESR1_TWRNINT. */ -#define BF_CAN_ESR1_TWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_TWRNINT) & BM_CAN_ESR1_TWRNINT) - -/*! @brief Set the TWRNINT field to a new value. */ -#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v)) -/*@}*/ - -/*! - * @name Register CAN_ESR1, field SYNCH[18] (RO) - * - * This read-only flag indicates whether the FlexCAN is synchronized to the CAN - * bus and able to participate in the communication process. It is set and - * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description. - * - * Values: - * - 0 - FlexCAN is not synchronized to the CAN bus. - * - 1 - FlexCAN is synchronized to the CAN bus. - */ -/*@{*/ -#define BP_CAN_ESR1_SYNCH (18U) /*!< Bit position for CAN_ESR1_SYNCH. */ -#define BM_CAN_ESR1_SYNCH (0x00040000U) /*!< Bit mask for CAN_ESR1_SYNCH. */ -#define BS_CAN_ESR1_SYNCH (1U) /*!< Bit field size in bits for CAN_ESR1_SYNCH. */ - -/*! @brief Read current value of the CAN_ESR1_SYNCH field. */ -#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_IMASK1 - Interrupt Masks 1 register - ******************************************************************************/ - -/*! - * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW) - * - * Reset value: 0x00000000U - * - * This register allows any number of a range of the 32 Message Buffer - * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask - * bit per buffer, enabling the CPU to determine which buffer generates an - * interrupt after a successful transmission or reception, that is, when the - * corresponding IFLAG1 bit is set. - */ -typedef union _hw_can_imask1 -{ - uint32_t U; - struct _hw_can_imask1_bitfields - { - uint32_t BUFLM : 32; /*!< [31:0] Buffer MB i Mask */ - } B; -} hw_can_imask1_t; - -/*! - * @name Constants and macros for entire CAN_IMASK1 register - */ -/*@{*/ -#define HW_CAN_IMASK1_ADDR(x) ((x) + 0x28U) - -#define HW_CAN_IMASK1(x) (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x)) -#define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U) -#define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v)) -#define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) | (v))) -#define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v))) -#define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_IMASK1 bitfields - */ - -/*! - * @name Register CAN_IMASK1, field BUFLM[31:0] (RW) - * - * Each bit enables or disables the corresponding FlexCAN Message Buffer - * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can - * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set. - * - * Values: - * - 0 - The corresponding buffer Interrupt is disabled. - * - 1 - The corresponding buffer Interrupt is enabled. - */ -/*@{*/ -#define BP_CAN_IMASK1_BUFLM (0U) /*!< Bit position for CAN_IMASK1_BUFLM. */ -#define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) /*!< Bit mask for CAN_IMASK1_BUFLM. */ -#define BS_CAN_IMASK1_BUFLM (32U) /*!< Bit field size in bits for CAN_IMASK1_BUFLM. */ - -/*! @brief Read current value of the CAN_IMASK1_BUFLM field. */ -#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U) - -/*! @brief Format value for bitfield CAN_IMASK1_BUFLM. */ -#define BF_CAN_IMASK1_BUFLM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IMASK1_BUFLM) & BM_CAN_IMASK1_BUFLM) - -/*! @brief Set the BUFLM field to a new value. */ -#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_IFLAG1 - Interrupt Flags 1 register - ******************************************************************************/ - -/*! - * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C) - * - * Reset value: 0x00000000U - * - * This register defines the flags for the 32 Message Buffer interrupts for MB31 - * to MB0. It contains one interrupt flag bit per buffer. Each successful - * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding - * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be - * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags - * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the - * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags - * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of - * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU - * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx - * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now - * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated, - * the FIFO flags must be cleared. The same care must be taken when an RFFN - * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is - * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits - * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1 - * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise, - * they will remain set and be inconsistent with the number of MBs available. - */ -typedef union _hw_can_iflag1 -{ - uint32_t U; - struct _hw_can_iflag1_bitfields - { - uint32_t BUF0I : 1; /*!< [0] Buffer MB0 Interrupt Or "reserved" */ - uint32_t BUF4TO1I : 4; /*!< [4:1] Buffer MB i Interrupt Or "reserved" - * */ - uint32_t BUF5I : 1; /*!< [5] Buffer MB5 Interrupt Or "Frames - * available in Rx FIFO" */ - uint32_t BUF6I : 1; /*!< [6] Buffer MB6 Interrupt Or "Rx FIFO - * Warning" */ - uint32_t BUF7I : 1; /*!< [7] Buffer MB7 Interrupt Or "Rx FIFO - * Overflow" */ - uint32_t BUF31TO8I : 24; /*!< [31:8] Buffer MBi Interrupt */ - } B; -} hw_can_iflag1_t; - -/*! - * @name Constants and macros for entire CAN_IFLAG1 register - */ -/*@{*/ -#define HW_CAN_IFLAG1_ADDR(x) ((x) + 0x30U) - -#define HW_CAN_IFLAG1(x) (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x)) -#define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U) -#define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v)) -#define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) | (v))) -#define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v))) -#define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_IFLAG1 bitfields - */ - -/*! - * @name Register CAN_IFLAG1, field BUF0I[0] (W1C) - * - * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags - * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit - * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is - * set. - * - * Values: - * - 0 - The corresponding buffer has no occurrence of successfully completed - * transmission or reception when MCR[RFEN]=0. - * - 1 - The corresponding buffer has successfully completed transmission or - * reception when MCR[RFEN]=0. - */ -/*@{*/ -#define BP_CAN_IFLAG1_BUF0I (0U) /*!< Bit position for CAN_IFLAG1_BUF0I. */ -#define BM_CAN_IFLAG1_BUF0I (0x00000001U) /*!< Bit mask for CAN_IFLAG1_BUF0I. */ -#define BS_CAN_IFLAG1_BUF0I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF0I. */ - -/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */ -#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I)) - -/*! @brief Format value for bitfield CAN_IFLAG1_BUF0I. */ -#define BF_CAN_IFLAG1_BUF0I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF0I) & BM_CAN_IFLAG1_BUF0I) - -/*! @brief Set the BUF0I field to a new value. */ -#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v)) -/*@}*/ - -/*! - * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C) - * - * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag - * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever - * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved - * when MCR[RFEN] is set. - * - * Values: - * - 0 - The corresponding buffer has no occurrence of successfully completed - * transmission or reception when MCR[RFEN]=0. - * - 1 - The corresponding buffer has successfully completed transmission or - * reception when MCR[RFEN]=0. - */ -/*@{*/ -#define BP_CAN_IFLAG1_BUF4TO1I (1U) /*!< Bit position for CAN_IFLAG1_BUF4TO1I. */ -#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) /*!< Bit mask for CAN_IFLAG1_BUF4TO1I. */ -#define BS_CAN_IFLAG1_BUF4TO1I (4U) /*!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I. */ - -/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */ -#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I) - -/*! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I. */ -#define BF_CAN_IFLAG1_BUF4TO1I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF4TO1I) & BM_CAN_IFLAG1_BUF4TO1I) - -/*! @brief Set the BUF4TO1I field to a new value. */ -#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v))) -/*@}*/ - -/*! - * @name Register CAN_IFLAG1, field BUF5I[5] (W1C) - * - * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags - * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit - * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in - * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at - * least one frame is available to be read from the Rx FIFO. - * - * Values: - * - 0 - No occurrence of MB5 completing transmission/reception when - * MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 - * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) - * available in the Rx FIFO when MCR[RFEN]=1 - */ -/*@{*/ -#define BP_CAN_IFLAG1_BUF5I (5U) /*!< Bit position for CAN_IFLAG1_BUF5I. */ -#define BM_CAN_IFLAG1_BUF5I (0x00000020U) /*!< Bit mask for CAN_IFLAG1_BUF5I. */ -#define BS_CAN_IFLAG1_BUF5I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF5I. */ - -/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */ -#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I)) - -/*! @brief Format value for bitfield CAN_IFLAG1_BUF5I. */ -#define BF_CAN_IFLAG1_BUF5I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF5I) & BM_CAN_IFLAG1_BUF5I) - -/*! @brief Set the BUF5I field to a new value. */ -#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v)) -/*@}*/ - -/*! - * @name Register CAN_IFLAG1, field BUF6I[6] (W1C) - * - * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags - * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit - * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning" - * when MCR[RFEN] is set. In this case, the flag indicates when the number of - * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of - * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is - * cleared while the number of unread messages is greater than 4, it does not - * assert again until the number of unread messages within the Rx FIFO is decreased - * to be equal to or less than 4. - * - * Values: - * - 0 - No occurrence of MB6 completing transmission/reception when - * MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 - * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO - * almost full when MCR[RFEN]=1 - */ -/*@{*/ -#define BP_CAN_IFLAG1_BUF6I (6U) /*!< Bit position for CAN_IFLAG1_BUF6I. */ -#define BM_CAN_IFLAG1_BUF6I (0x00000040U) /*!< Bit mask for CAN_IFLAG1_BUF6I. */ -#define BS_CAN_IFLAG1_BUF6I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF6I. */ - -/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */ -#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I)) - -/*! @brief Format value for bitfield CAN_IFLAG1_BUF6I. */ -#define BF_CAN_IFLAG1_BUF6I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF6I) & BM_CAN_IFLAG1_BUF6I) - -/*! @brief Set the BUF6I field to a new value. */ -#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v)) -/*@}*/ - -/*! - * @name Register CAN_IFLAG1, field BUF7I[7] (W1C) - * - * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags - * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit - * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow" - * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost - * because the Rx FIFO is full. Note that the flag will not be asserted when the - * Rx FIFO is full and the message was captured by a Mailbox. - * - * Values: - * - 0 - No occurrence of MB7 completing transmission/reception when - * MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 - * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO - * overflow when MCR[RFEN]=1 - */ -/*@{*/ -#define BP_CAN_IFLAG1_BUF7I (7U) /*!< Bit position for CAN_IFLAG1_BUF7I. */ -#define BM_CAN_IFLAG1_BUF7I (0x00000080U) /*!< Bit mask for CAN_IFLAG1_BUF7I. */ -#define BS_CAN_IFLAG1_BUF7I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF7I. */ - -/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */ -#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I)) - -/*! @brief Format value for bitfield CAN_IFLAG1_BUF7I. */ -#define BF_CAN_IFLAG1_BUF7I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF7I) & BM_CAN_IFLAG1_BUF7I) - -/*! @brief Set the BUF7I field to a new value. */ -#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v)) -/*@}*/ - -/*! - * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C) - * - * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to - * MB8. - * - * Values: - * - 0 - The corresponding buffer has no occurrence of successfully completed - * transmission or reception. - * - 1 - The corresponding buffer has successfully completed transmission or - * reception. - */ -/*@{*/ -#define BP_CAN_IFLAG1_BUF31TO8I (8U) /*!< Bit position for CAN_IFLAG1_BUF31TO8I. */ -#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) /*!< Bit mask for CAN_IFLAG1_BUF31TO8I. */ -#define BS_CAN_IFLAG1_BUF31TO8I (24U) /*!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I. */ - -/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */ -#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I) - -/*! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I. */ -#define BF_CAN_IFLAG1_BUF31TO8I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF31TO8I) & BM_CAN_IFLAG1_BUF31TO8I) - -/*! @brief Set the BUF31TO8I field to a new value. */ -#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v))) -/*@}*/ - -/******************************************************************************* - * HW_CAN_CTRL2 - Control 2 register - ******************************************************************************/ - -/*! - * @brief HW_CAN_CTRL2 - Control 2 register (RW) - * - * Reset value: 0x00B00000U - * - * This register contains control bits for CAN errors, FIFO features, and mode - * selection. - */ -typedef union _hw_can_ctrl2 -{ - uint32_t U; - struct _hw_can_ctrl2_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t EACEN : 1; /*!< [16] Entire Frame Arbitration Field - * Comparison Enable For Rx Mailboxes */ - uint32_t RRS : 1; /*!< [17] Remote Request Storing */ - uint32_t MRP : 1; /*!< [18] Mailboxes Reception Priority */ - uint32_t TASD : 5; /*!< [23:19] Tx Arbitration Start Delay */ - uint32_t RFFN : 4; /*!< [27:24] Number Of Rx FIFO Filters */ - uint32_t WRMFRZ : 1; /*!< [28] Write-Access To Memory In Freeze Mode - * */ - uint32_t RESERVED1 : 3; /*!< [31:29] */ - } B; -} hw_can_ctrl2_t; - -/*! - * @name Constants and macros for entire CAN_CTRL2 register - */ -/*@{*/ -#define HW_CAN_CTRL2_ADDR(x) ((x) + 0x34U) - -#define HW_CAN_CTRL2(x) (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x)) -#define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U) -#define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v)) -#define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) | (v))) -#define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v))) -#define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_CTRL2 bitfields - */ - -/*! - * @name Register CAN_CTRL2, field EACEN[16] (RW) - * - * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes - * filters with their corresponding bits in the incoming frame by the matching - * process. This bit does not affect matching for Rx FIFO. This bit can be written - * only in Freeze mode because it is blocked by hardware in other modes. - * - * Values: - * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never - * compared despite mask bits. - * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with - * their corresponding bits within the incoming frame. Mask bits do apply. - */ -/*@{*/ -#define BP_CAN_CTRL2_EACEN (16U) /*!< Bit position for CAN_CTRL2_EACEN. */ -#define BM_CAN_CTRL2_EACEN (0x00010000U) /*!< Bit mask for CAN_CTRL2_EACEN. */ -#define BS_CAN_CTRL2_EACEN (1U) /*!< Bit field size in bits for CAN_CTRL2_EACEN. */ - -/*! @brief Read current value of the CAN_CTRL2_EACEN field. */ -#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN)) - -/*! @brief Format value for bitfield CAN_CTRL2_EACEN. */ -#define BF_CAN_CTRL2_EACEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_EACEN) & BM_CAN_CTRL2_EACEN) - -/*! @brief Set the EACEN field to a new value. */ -#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL2, field RRS[17] (RW) - * - * If this bit is asserted Remote Request Frame is submitted to a matching - * process and stored in the corresponding Message Buffer in the same fashion of a - * Data Frame. No automatic Remote Response Frame will be generated. If this bit is - * negated the Remote Request Frame is submitted to a matching process and an - * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010 - * is found with the same ID. This bit can be written only in Freeze mode - * because it is blocked by hardware in other modes. - * - * Values: - * - 0 - Remote Response Frame is generated. - * - 1 - Remote Request Frame is stored. - */ -/*@{*/ -#define BP_CAN_CTRL2_RRS (17U) /*!< Bit position for CAN_CTRL2_RRS. */ -#define BM_CAN_CTRL2_RRS (0x00020000U) /*!< Bit mask for CAN_CTRL2_RRS. */ -#define BS_CAN_CTRL2_RRS (1U) /*!< Bit field size in bits for CAN_CTRL2_RRS. */ - -/*! @brief Read current value of the CAN_CTRL2_RRS field. */ -#define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS)) - -/*! @brief Format value for bitfield CAN_CTRL2_RRS. */ -#define BF_CAN_CTRL2_RRS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RRS) & BM_CAN_CTRL2_RRS) - -/*! @brief Set the RRS field to a new value. */ -#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL2, field MRP[18] (RW) - * - * If this bit is set the matching process starts from the Mailboxes and if no - * match occurs the matching continues on the Rx FIFO. This bit can be written - * only in Freeze mode because it is blocked by hardware in other modes. - * - * Values: - * - 0 - Matching starts from Rx FIFO and continues on Mailboxes. - * - 1 - Matching starts from Mailboxes and continues on Rx FIFO. - */ -/*@{*/ -#define BP_CAN_CTRL2_MRP (18U) /*!< Bit position for CAN_CTRL2_MRP. */ -#define BM_CAN_CTRL2_MRP (0x00040000U) /*!< Bit mask for CAN_CTRL2_MRP. */ -#define BS_CAN_CTRL2_MRP (1U) /*!< Bit field size in bits for CAN_CTRL2_MRP. */ - -/*! @brief Read current value of the CAN_CTRL2_MRP field. */ -#define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP)) - -/*! @brief Format value for bitfield CAN_CTRL2_MRP. */ -#define BF_CAN_CTRL2_MRP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_MRP) & BM_CAN_CTRL2_MRP) - -/*! @brief Set the MRP field to a new value. */ -#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CTRL2, field TASD[23:19] (RW) - * - * This 5-bit field indicates how many CAN bits the Tx arbitration process start - * point can be delayed from the first bit of CRC field on CAN bus. This field - * can be written only in Freeze mode because it is blocked by hardware in other - * modes. This field is useful to optimize the transmit performance based on - * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs. - * The duration of an arbitration process, in terms of CAN bits, is directly - * proportional to the number of available MBs and CAN baud rate and inversely - * proportional to the peripheral clock frequency. The optimal arbitration timing is - * that in which the last MB is scanned right before the first bit of the - * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial - * clock ratio is high and the CAN baud rate is low then the arbitration can be - * delayed and vice-versa. If TASD is 0 then the arbitration start is not - * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration, - * but more time is reserved for arbitration. On the other hand, if TASD is 24 then - * the CPU can configure a Tx MB later and less time is reserved for - * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able - * to find winner MBs in time to compete with other nodes for the CAN bus. If the - * arbitration ends too much time before the first bit of Intermission field then - * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is - * not the best to be transmitted. The optimal configuration for TASD can be - * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN * - * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f - * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in - * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB] - * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field - * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2] - * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in - * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol - * Timing" for more details. - */ -/*@{*/ -#define BP_CAN_CTRL2_TASD (19U) /*!< Bit position for CAN_CTRL2_TASD. */ -#define BM_CAN_CTRL2_TASD (0x00F80000U) /*!< Bit mask for CAN_CTRL2_TASD. */ -#define BS_CAN_CTRL2_TASD (5U) /*!< Bit field size in bits for CAN_CTRL2_TASD. */ - -/*! @brief Read current value of the CAN_CTRL2_TASD field. */ -#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD) - -/*! @brief Format value for bitfield CAN_CTRL2_TASD. */ -#define BF_CAN_CTRL2_TASD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_TASD) & BM_CAN_CTRL2_TASD) - -/*! @brief Set the TASD field to a new value. */ -#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v))) -/*@}*/ - -/*! - * @name Register CAN_CTRL2, field RFFN[27:24] (RW) - * - * This 4-bit field defines the number of Rx FIFO filters, as shown in the - * following table. The maximum selectable number of filters is determined by the MCU. - * This field can only be written in Freeze mode as it is blocked by hardware in - * other modes. This field must not be programmed with values that make the - * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of - * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies - * a memory space equivalent to two Message Buffers which means that the more - * filters are implemented the less Mailboxes will be available. Considering that - * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should - * be programmed with a value correponding to a number of filters not greater - * than the number of available memory words which can be calculated as follows: - * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB. - * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN * - * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the - * SETUP_MB value (memory space available) the exceeding ones will not be functional. - * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID - * Filter Table Remaining Available MailboxesThe number of the last remaining - * available mailboxes is defined by the least value between the parameter - * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected - * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then - * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter - * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB - * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2 - * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63 - * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39 - * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63 - * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63 - * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63 - * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements - * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB - * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31 - * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB - * 0-37 MB 38-63 Elements 0-31 Elements 32-127 - */ -/*@{*/ -#define BP_CAN_CTRL2_RFFN (24U) /*!< Bit position for CAN_CTRL2_RFFN. */ -#define BM_CAN_CTRL2_RFFN (0x0F000000U) /*!< Bit mask for CAN_CTRL2_RFFN. */ -#define BS_CAN_CTRL2_RFFN (4U) /*!< Bit field size in bits for CAN_CTRL2_RFFN. */ - -/*! @brief Read current value of the CAN_CTRL2_RFFN field. */ -#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN) - -/*! @brief Format value for bitfield CAN_CTRL2_RFFN. */ -#define BF_CAN_CTRL2_RFFN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RFFN) & BM_CAN_CTRL2_RFFN) - -/*! @brief Set the RFFN field to a new value. */ -#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v))) -/*@}*/ - -/*! - * @name Register CAN_CTRL2, field WRMFRZ[28] (RW) - * - * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit - * can only be written in Freeze mode and has no effect out of Freeze mode. - * - * Values: - * - 0 - Maintain the write access restrictions. - * - 1 - Enable unrestricted write access to FlexCAN memory. - */ -/*@{*/ -#define BP_CAN_CTRL2_WRMFRZ (28U) /*!< Bit position for CAN_CTRL2_WRMFRZ. */ -#define BM_CAN_CTRL2_WRMFRZ (0x10000000U) /*!< Bit mask for CAN_CTRL2_WRMFRZ. */ -#define BS_CAN_CTRL2_WRMFRZ (1U) /*!< Bit field size in bits for CAN_CTRL2_WRMFRZ. */ - -/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */ -#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ)) - -/*! @brief Format value for bitfield CAN_CTRL2_WRMFRZ. */ -#define BF_CAN_CTRL2_WRMFRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_WRMFRZ) & BM_CAN_CTRL2_WRMFRZ) - -/*! @brief Set the WRMFRZ field to a new value. */ -#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_ESR2 - Error and Status 2 register - ******************************************************************************/ - -/*! - * @brief HW_CAN_ESR2 - Error and Status 2 register (RO) - * - * Reset value: 0x00000000U - * - * This register reflects various interrupt flags and some general status. - */ -typedef union _hw_can_esr2 -{ - uint32_t U; - struct _hw_can_esr2_bitfields - { - uint32_t RESERVED0 : 13; /*!< [12:0] */ - uint32_t IMB : 1; /*!< [13] Inactive Mailbox */ - uint32_t VPS : 1; /*!< [14] Valid Priority Status */ - uint32_t RESERVED1 : 1; /*!< [15] */ - uint32_t LPTM : 7; /*!< [22:16] Lowest Priority Tx Mailbox */ - uint32_t RESERVED2 : 9; /*!< [31:23] */ - } B; -} hw_can_esr2_t; - -/*! - * @name Constants and macros for entire CAN_ESR2 register - */ -/*@{*/ -#define HW_CAN_ESR2_ADDR(x) ((x) + 0x38U) - -#define HW_CAN_ESR2(x) (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x)) -#define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAN_ESR2 bitfields - */ - -/*! - * @name Register CAN_ESR2, field IMB[13] (RO) - * - * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive - * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the - * following cases: During arbitration, if an LPTM is found and it is inactive. If - * IMB is not asserted and a frame is transmitted successfully. This bit is - * cleared in all start of arbitration (see Section "Arbitration process"). LPTM - * mechanism have the following behavior: if an MB is successfully transmitted and - * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and - * the index related to the MB just transmitted is loaded into ESR2[LPTM]. - * - * Values: - * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. - * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM - * content is the number of the first one. - */ -/*@{*/ -#define BP_CAN_ESR2_IMB (13U) /*!< Bit position for CAN_ESR2_IMB. */ -#define BM_CAN_ESR2_IMB (0x00002000U) /*!< Bit mask for CAN_ESR2_IMB. */ -#define BS_CAN_ESR2_IMB (1U) /*!< Bit field size in bits for CAN_ESR2_IMB. */ - -/*! @brief Read current value of the CAN_ESR2_IMB field. */ -#define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB)) -/*@}*/ - -/*! - * @name Register CAN_ESR2, field VPS[14] (RO) - * - * This bit indicates whether IMB and LPTM contents are currently valid or not. - * VPS is asserted upon every complete Tx arbitration process unless the CPU - * writes to Control and Status word of a Mailbox that has already been scanned, that - * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process. - * If there is no inactive Mailbox and only one Tx Mailbox that is being - * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx - * arbitration process or upon a write to Control and Status word of any Mailbox. - * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is - * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write - * in C/S of a MB that is being transmitted (pending abort), or any write attempt - * into a Tx MB with IFLAG set is blocked. - * - * Values: - * - 0 - Contents of IMB and LPTM are invalid. - * - 1 - Contents of IMB and LPTM are valid. - */ -/*@{*/ -#define BP_CAN_ESR2_VPS (14U) /*!< Bit position for CAN_ESR2_VPS. */ -#define BM_CAN_ESR2_VPS (0x00004000U) /*!< Bit mask for CAN_ESR2_VPS. */ -#define BS_CAN_ESR2_VPS (1U) /*!< Bit field size in bits for CAN_ESR2_VPS. */ - -/*! @brief Read current value of the CAN_ESR2_VPS field. */ -#define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS)) -/*@}*/ - -/*! - * @name Register CAN_ESR2, field LPTM[22:16] (RO) - * - * If ESR2[VPS] is asserted, this field indicates the lowest number inactive - * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the - * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is - * negated then the Mailbox indicated is the one that has the greatest arbitration - * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is - * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If - * a Tx Mailbox is being transmitted it is not considered in LPTM calculation. - * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is - * updated with its Mailbox number. - */ -/*@{*/ -#define BP_CAN_ESR2_LPTM (16U) /*!< Bit position for CAN_ESR2_LPTM. */ -#define BM_CAN_ESR2_LPTM (0x007F0000U) /*!< Bit mask for CAN_ESR2_LPTM. */ -#define BS_CAN_ESR2_LPTM (7U) /*!< Bit field size in bits for CAN_ESR2_LPTM. */ - -/*! @brief Read current value of the CAN_ESR2_LPTM field. */ -#define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM) -/*@}*/ - -/******************************************************************************* - * HW_CAN_CRCR - CRC Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_CRCR - CRC Register (RO) - * - * Reset value: 0x00000000U - * - * This register provides information about the CRC of transmitted messages. - */ -typedef union _hw_can_crcr -{ - uint32_t U; - struct _hw_can_crcr_bitfields - { - uint32_t TXCRC : 15; /*!< [14:0] CRC Transmitted */ - uint32_t RESERVED0 : 1; /*!< [15] */ - uint32_t MBCRC : 7; /*!< [22:16] CRC Mailbox */ - uint32_t RESERVED1 : 9; /*!< [31:23] */ - } B; -} hw_can_crcr_t; - -/*! - * @name Constants and macros for entire CAN_CRCR register - */ -/*@{*/ -#define HW_CAN_CRCR_ADDR(x) ((x) + 0x44U) - -#define HW_CAN_CRCR(x) (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x)) -#define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAN_CRCR bitfields - */ - -/*! - * @name Register CAN_CRCR, field TXCRC[14:0] (RO) - * - * This field indicates the CRC value of the last message transmitted. This - * field is updated at the same time the Tx Interrupt Flag is asserted. - */ -/*@{*/ -#define BP_CAN_CRCR_TXCRC (0U) /*!< Bit position for CAN_CRCR_TXCRC. */ -#define BM_CAN_CRCR_TXCRC (0x00007FFFU) /*!< Bit mask for CAN_CRCR_TXCRC. */ -#define BS_CAN_CRCR_TXCRC (15U) /*!< Bit field size in bits for CAN_CRCR_TXCRC. */ - -/*! @brief Read current value of the CAN_CRCR_TXCRC field. */ -#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC) -/*@}*/ - -/*! - * @name Register CAN_CRCR, field MBCRC[22:16] (RO) - * - * This field indicates the number of the Mailbox corresponding to the value in - * TXCRC field. - */ -/*@{*/ -#define BP_CAN_CRCR_MBCRC (16U) /*!< Bit position for CAN_CRCR_MBCRC. */ -#define BM_CAN_CRCR_MBCRC (0x007F0000U) /*!< Bit mask for CAN_CRCR_MBCRC. */ -#define BS_CAN_CRCR_MBCRC (7U) /*!< Bit field size in bits for CAN_CRCR_MBCRC. */ - -/*! @brief Read current value of the CAN_CRCR_MBCRC field. */ -#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC) -/*@}*/ - -/******************************************************************************* - * HW_CAN_RXFGMASK - Rx FIFO Global Mask register - ******************************************************************************/ - -/*! - * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW) - * - * Reset value: 0xFFFFFFFFU - * - * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to - * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR - * according to CTRL2[RFFN] field setting. This register can only be written in - * Freeze mode as it is blocked by hardware in other modes. - */ -typedef union _hw_can_rxfgmask -{ - uint32_t U; - struct _hw_can_rxfgmask_bitfields - { - uint32_t FGM : 32; /*!< [31:0] Rx FIFO Global Mask Bits */ - } B; -} hw_can_rxfgmask_t; - -/*! - * @name Constants and macros for entire CAN_RXFGMASK register - */ -/*@{*/ -#define HW_CAN_RXFGMASK_ADDR(x) ((x) + 0x48U) - -#define HW_CAN_RXFGMASK(x) (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x)) -#define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U) -#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v)) -#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) | (v))) -#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v))) -#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_RXFGMASK bitfields - */ - -/*! - * @name Register CAN_RXFGMASK, field FGM[31:0] (RW) - * - * These bits mask the ID Filter Table elements bits in a perfect alignment. The - * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO - * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter - * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only - * the fourteen most significant bits of the Identifier of the incoming frame are - * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to - * the format C only the eight most significant bits of the Identifier of the - * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30] - * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0] - * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0] - * - * Values: - * - 0 - The corresponding bit in the filter is "don't care." - * - 1 - The corresponding bit in the filter is checked. - */ -/*@{*/ -#define BP_CAN_RXFGMASK_FGM (0U) /*!< Bit position for CAN_RXFGMASK_FGM. */ -#define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) /*!< Bit mask for CAN_RXFGMASK_FGM. */ -#define BS_CAN_RXFGMASK_FGM (32U) /*!< Bit field size in bits for CAN_RXFGMASK_FGM. */ - -/*! @brief Read current value of the CAN_RXFGMASK_FGM field. */ -#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U) - -/*! @brief Format value for bitfield CAN_RXFGMASK_FGM. */ -#define BF_CAN_RXFGMASK_FGM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXFGMASK_FGM) & BM_CAN_RXFGMASK_FGM) - -/*! @brief Set the FGM field to a new value. */ -#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CAN_RXFIR - Rx FIFO Information Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO) - * - * Reset value: 0x00000000U - * - * RXFIR provides information on Rx FIFO. This register is the port through - * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO - * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as - * well as its output is updated whenever the output of the Rx FIFO is updated - * with the next message. See Section "Rx FIFO" for instructions on reading this - * register. - */ -typedef union _hw_can_rxfir -{ - uint32_t U; - struct _hw_can_rxfir_bitfields - { - uint32_t IDHIT : 9; /*!< [8:0] Identifier Acceptance Filter Hit - * Indicator */ - uint32_t RESERVED0 : 23; /*!< [31:9] */ - } B; -} hw_can_rxfir_t; - -/*! - * @name Constants and macros for entire CAN_RXFIR register - */ -/*@{*/ -#define HW_CAN_RXFIR_ADDR(x) ((x) + 0x4CU) - -#define HW_CAN_RXFIR(x) (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x)) -#define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAN_RXFIR bitfields - */ - -/*! - * @name Register CAN_RXFIR, field IDHIT[8:0] (RO) - * - * This field indicates which Identifier Acceptance Filter was hit by the - * received message that is in the output of the Rx FIFO. If multiple filters match the - * incoming message ID then the first matching IDAF found (lowest number) by the - * matching process is indicated. This field is valid only while the - * IFLAG[BUF5I] is asserted. - */ -/*@{*/ -#define BP_CAN_RXFIR_IDHIT (0U) /*!< Bit position for CAN_RXFIR_IDHIT. */ -#define BM_CAN_RXFIR_IDHIT (0x000001FFU) /*!< Bit mask for CAN_RXFIR_IDHIT. */ -#define BS_CAN_RXFIR_IDHIT (9U) /*!< Bit field size in bits for CAN_RXFIR_IDHIT. */ - -/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */ -#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT) -/*@}*/ - -/******************************************************************************* - * HW_CAN_CSn - Message Buffer 0 CS Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_CSn - Message Buffer 0 CS Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_can_csn -{ - uint32_t U; - struct _hw_can_csn_bitfields - { - uint32_t TIME_STAMP : 16; /*!< [15:0] Free-Running Counter Time - * stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx - * and Rx frames at the time when the beginning of the Identifier field - * appears on the CAN bus. */ - uint32_t DLC : 4; /*!< [19:16] Length of the data to be - * stored/transmitted. */ - uint32_t RTR : 1; /*!< [20] Remote Transmission Request. One/zero for - * remote/data frame. */ - uint32_t IDE : 1; /*!< [21] ID Extended. One/zero for - * extended/standard format frame. */ - uint32_t SRR : 1; /*!< [22] Substitute Remote Request. Contains a - * fixed recessive bit. */ - uint32_t RESERVED0 : 1; /*!< [23] Reserved */ - uint32_t CODE : 4; /*!< [27:24] Reserved */ - uint32_t RESERVED1 : 4; /*!< [31:28] Reserved */ - } B; -} hw_can_csn_t; - -/*! - * @name Constants and macros for entire CAN_CSn register - */ -/*@{*/ -#define HW_CAN_CSn_COUNT (16U) - -#define HW_CAN_CSn_ADDR(x, n) ((x) + 0x80U + (0x10U * (n))) - -#define HW_CAN_CSn(x, n) (*(__IO hw_can_csn_t *) HW_CAN_CSn_ADDR(x, n)) -#define HW_CAN_CSn_RD(x, n) (HW_CAN_CSn(x, n).U) -#define HW_CAN_CSn_WR(x, n, v) (HW_CAN_CSn(x, n).U = (v)) -#define HW_CAN_CSn_SET(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) | (v))) -#define HW_CAN_CSn_CLR(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) & ~(v))) -#define HW_CAN_CSn_TOG(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_CSn bitfields - */ - -/*! - * @name Register CAN_CSn, field TIME_STAMP[15:0] (RW) - */ -/*@{*/ -#define BP_CAN_CSn_TIME_STAMP (0U) /*!< Bit position for CAN_CSn_TIME_STAMP. */ -#define BM_CAN_CSn_TIME_STAMP (0x0000FFFFU) /*!< Bit mask for CAN_CSn_TIME_STAMP. */ -#define BS_CAN_CSn_TIME_STAMP (16U) /*!< Bit field size in bits for CAN_CSn_TIME_STAMP. */ - -/*! @brief Read current value of the CAN_CSn_TIME_STAMP field. */ -#define BR_CAN_CSn_TIME_STAMP(x, n) (HW_CAN_CSn(x, n).B.TIME_STAMP) - -/*! @brief Format value for bitfield CAN_CSn_TIME_STAMP. */ -#define BF_CAN_CSn_TIME_STAMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_TIME_STAMP) & BM_CAN_CSn_TIME_STAMP) - -/*! @brief Set the TIME_STAMP field to a new value. */ -#define BW_CAN_CSn_TIME_STAMP(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_TIME_STAMP) | BF_CAN_CSn_TIME_STAMP(v))) -/*@}*/ - -/*! - * @name Register CAN_CSn, field DLC[19:16] (RW) - */ -/*@{*/ -#define BP_CAN_CSn_DLC (16U) /*!< Bit position for CAN_CSn_DLC. */ -#define BM_CAN_CSn_DLC (0x000F0000U) /*!< Bit mask for CAN_CSn_DLC. */ -#define BS_CAN_CSn_DLC (4U) /*!< Bit field size in bits for CAN_CSn_DLC. */ - -/*! @brief Read current value of the CAN_CSn_DLC field. */ -#define BR_CAN_CSn_DLC(x, n) (HW_CAN_CSn(x, n).B.DLC) - -/*! @brief Format value for bitfield CAN_CSn_DLC. */ -#define BF_CAN_CSn_DLC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_DLC) & BM_CAN_CSn_DLC) - -/*! @brief Set the DLC field to a new value. */ -#define BW_CAN_CSn_DLC(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_DLC) | BF_CAN_CSn_DLC(v))) -/*@}*/ - -/*! - * @name Register CAN_CSn, field RTR[20] (RW) - */ -/*@{*/ -#define BP_CAN_CSn_RTR (20U) /*!< Bit position for CAN_CSn_RTR. */ -#define BM_CAN_CSn_RTR (0x00100000U) /*!< Bit mask for CAN_CSn_RTR. */ -#define BS_CAN_CSn_RTR (1U) /*!< Bit field size in bits for CAN_CSn_RTR. */ - -/*! @brief Read current value of the CAN_CSn_RTR field. */ -#define BR_CAN_CSn_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR)) - -/*! @brief Format value for bitfield CAN_CSn_RTR. */ -#define BF_CAN_CSn_RTR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_RTR) & BM_CAN_CSn_RTR) - -/*! @brief Set the RTR field to a new value. */ -#define BW_CAN_CSn_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CSn, field IDE[21] (RW) - */ -/*@{*/ -#define BP_CAN_CSn_IDE (21U) /*!< Bit position for CAN_CSn_IDE. */ -#define BM_CAN_CSn_IDE (0x00200000U) /*!< Bit mask for CAN_CSn_IDE. */ -#define BS_CAN_CSn_IDE (1U) /*!< Bit field size in bits for CAN_CSn_IDE. */ - -/*! @brief Read current value of the CAN_CSn_IDE field. */ -#define BR_CAN_CSn_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE)) - -/*! @brief Format value for bitfield CAN_CSn_IDE. */ -#define BF_CAN_CSn_IDE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_IDE) & BM_CAN_CSn_IDE) - -/*! @brief Set the IDE field to a new value. */ -#define BW_CAN_CSn_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CSn, field SRR[22] (RW) - */ -/*@{*/ -#define BP_CAN_CSn_SRR (22U) /*!< Bit position for CAN_CSn_SRR. */ -#define BM_CAN_CSn_SRR (0x00400000U) /*!< Bit mask for CAN_CSn_SRR. */ -#define BS_CAN_CSn_SRR (1U) /*!< Bit field size in bits for CAN_CSn_SRR. */ - -/*! @brief Read current value of the CAN_CSn_SRR field. */ -#define BR_CAN_CSn_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR)) - -/*! @brief Format value for bitfield CAN_CSn_SRR. */ -#define BF_CAN_CSn_SRR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_SRR) & BM_CAN_CSn_SRR) - -/*! @brief Set the SRR field to a new value. */ -#define BW_CAN_CSn_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR) = (v)) -/*@}*/ - -/*! - * @name Register CAN_CSn, field CODE[27:24] (RW) - */ -/*@{*/ -#define BP_CAN_CSn_CODE (24U) /*!< Bit position for CAN_CSn_CODE. */ -#define BM_CAN_CSn_CODE (0x0F000000U) /*!< Bit mask for CAN_CSn_CODE. */ -#define BS_CAN_CSn_CODE (4U) /*!< Bit field size in bits for CAN_CSn_CODE. */ - -/*! @brief Read current value of the CAN_CSn_CODE field. */ -#define BR_CAN_CSn_CODE(x, n) (HW_CAN_CSn(x, n).B.CODE) - -/*! @brief Format value for bitfield CAN_CSn_CODE. */ -#define BF_CAN_CSn_CODE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_CODE) & BM_CAN_CSn_CODE) - -/*! @brief Set the CODE field to a new value. */ -#define BW_CAN_CSn_CODE(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_CODE) | BF_CAN_CSn_CODE(v))) -/*@}*/ -/******************************************************************************* - * HW_CAN_IDn - Message Buffer 0 ID Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_IDn - Message Buffer 0 ID Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_can_idn -{ - uint32_t U; - struct _hw_can_idn_bitfields - { - uint32_t EXT : 18; /*!< [17:0] Contains extended (LOW word) - * identifier of message buffer. */ - uint32_t STD : 11; /*!< [28:18] Contains standard/extended (HIGH - * word) identifier of message buffer. */ - uint32_t PRIO : 3; /*!< [31:29] Local priority. This 3-bit fieldis - * only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx - * buffers. These bits are not transmitted. They are appended to the regular - * ID to define the transmission priority. */ - } B; -} hw_can_idn_t; - -/*! - * @name Constants and macros for entire CAN_IDn register - */ -/*@{*/ -#define HW_CAN_IDn_COUNT (16U) - -#define HW_CAN_IDn_ADDR(x, n) ((x) + 0x84U + (0x10U * (n))) - -#define HW_CAN_IDn(x, n) (*(__IO hw_can_idn_t *) HW_CAN_IDn_ADDR(x, n)) -#define HW_CAN_IDn_RD(x, n) (HW_CAN_IDn(x, n).U) -#define HW_CAN_IDn_WR(x, n, v) (HW_CAN_IDn(x, n).U = (v)) -#define HW_CAN_IDn_SET(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) | (v))) -#define HW_CAN_IDn_CLR(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) & ~(v))) -#define HW_CAN_IDn_TOG(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_IDn bitfields - */ - -/*! - * @name Register CAN_IDn, field EXT[17:0] (RW) - */ -/*@{*/ -#define BP_CAN_IDn_EXT (0U) /*!< Bit position for CAN_IDn_EXT. */ -#define BM_CAN_IDn_EXT (0x0003FFFFU) /*!< Bit mask for CAN_IDn_EXT. */ -#define BS_CAN_IDn_EXT (18U) /*!< Bit field size in bits for CAN_IDn_EXT. */ - -/*! @brief Read current value of the CAN_IDn_EXT field. */ -#define BR_CAN_IDn_EXT(x, n) (HW_CAN_IDn(x, n).B.EXT) - -/*! @brief Format value for bitfield CAN_IDn_EXT. */ -#define BF_CAN_IDn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_EXT) & BM_CAN_IDn_EXT) - -/*! @brief Set the EXT field to a new value. */ -#define BW_CAN_IDn_EXT(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_EXT) | BF_CAN_IDn_EXT(v))) -/*@}*/ - -/*! - * @name Register CAN_IDn, field STD[28:18] (RW) - */ -/*@{*/ -#define BP_CAN_IDn_STD (18U) /*!< Bit position for CAN_IDn_STD. */ -#define BM_CAN_IDn_STD (0x1FFC0000U) /*!< Bit mask for CAN_IDn_STD. */ -#define BS_CAN_IDn_STD (11U) /*!< Bit field size in bits for CAN_IDn_STD. */ - -/*! @brief Read current value of the CAN_IDn_STD field. */ -#define BR_CAN_IDn_STD(x, n) (HW_CAN_IDn(x, n).B.STD) - -/*! @brief Format value for bitfield CAN_IDn_STD. */ -#define BF_CAN_IDn_STD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_STD) & BM_CAN_IDn_STD) - -/*! @brief Set the STD field to a new value. */ -#define BW_CAN_IDn_STD(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_STD) | BF_CAN_IDn_STD(v))) -/*@}*/ - -/*! - * @name Register CAN_IDn, field PRIO[31:29] (RW) - */ -/*@{*/ -#define BP_CAN_IDn_PRIO (29U) /*!< Bit position for CAN_IDn_PRIO. */ -#define BM_CAN_IDn_PRIO (0xE0000000U) /*!< Bit mask for CAN_IDn_PRIO. */ -#define BS_CAN_IDn_PRIO (3U) /*!< Bit field size in bits for CAN_IDn_PRIO. */ - -/*! @brief Read current value of the CAN_IDn_PRIO field. */ -#define BR_CAN_IDn_PRIO(x, n) (HW_CAN_IDn(x, n).B.PRIO) - -/*! @brief Format value for bitfield CAN_IDn_PRIO. */ -#define BF_CAN_IDn_PRIO(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_PRIO) & BM_CAN_IDn_PRIO) - -/*! @brief Set the PRIO field to a new value. */ -#define BW_CAN_IDn_PRIO(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_PRIO) | BF_CAN_IDn_PRIO(v))) -/*@}*/ -/******************************************************************************* - * HW_CAN_WORD0n - Message Buffer 0 WORD0 Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_WORD0n - Message Buffer 0 WORD0 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_can_word0n -{ - uint32_t U; - struct _hw_can_word0n_bitfields - { - uint32_t DATA_BYTE_3 : 8; /*!< [7:0] Data byte 3 of Rx/Tx frame. */ - uint32_t DATA_BYTE_2 : 8; /*!< [15:8] Data byte 2 of Rx/Tx frame. */ - uint32_t DATA_BYTE_1 : 8; /*!< [23:16] Data byte 1 of Rx/Tx frame. */ - uint32_t DATA_BYTE_0 : 8; /*!< [31:24] Data byte 0 of Rx/Tx frame. */ - } B; -} hw_can_word0n_t; - -/*! - * @name Constants and macros for entire CAN_WORD0n register - */ -/*@{*/ -#define HW_CAN_WORD0n_COUNT (16U) - -#define HW_CAN_WORD0n_ADDR(x, n) ((x) + 0x88U + (0x10U * (n))) - -#define HW_CAN_WORD0n(x, n) (*(__IO hw_can_word0n_t *) HW_CAN_WORD0n_ADDR(x, n)) -#define HW_CAN_WORD0n_RD(x, n) (HW_CAN_WORD0n(x, n).U) -#define HW_CAN_WORD0n_WR(x, n, v) (HW_CAN_WORD0n(x, n).U = (v)) -#define HW_CAN_WORD0n_SET(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) | (v))) -#define HW_CAN_WORD0n_CLR(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) & ~(v))) -#define HW_CAN_WORD0n_TOG(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_WORD0n bitfields - */ - -/*! - * @name Register CAN_WORD0n, field DATA_BYTE_3[7:0] (RW) - */ -/*@{*/ -#define BP_CAN_WORD0n_DATA_BYTE_3 (0U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_3. */ -#define BM_CAN_WORD0n_DATA_BYTE_3 (0x000000FFU) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_3. */ -#define BS_CAN_WORD0n_DATA_BYTE_3 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_3. */ - -/*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_3 field. */ -#define BR_CAN_WORD0n_DATA_BYTE_3(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_3) - -/*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_3. */ -#define BF_CAN_WORD0n_DATA_BYTE_3(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_3) & BM_CAN_WORD0n_DATA_BYTE_3) - -/*! @brief Set the DATA_BYTE_3 field to a new value. */ -#define BW_CAN_WORD0n_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_3) | BF_CAN_WORD0n_DATA_BYTE_3(v))) -/*@}*/ - -/*! - * @name Register CAN_WORD0n, field DATA_BYTE_2[15:8] (RW) - */ -/*@{*/ -#define BP_CAN_WORD0n_DATA_BYTE_2 (8U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_2. */ -#define BM_CAN_WORD0n_DATA_BYTE_2 (0x0000FF00U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_2. */ -#define BS_CAN_WORD0n_DATA_BYTE_2 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_2. */ - -/*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_2 field. */ -#define BR_CAN_WORD0n_DATA_BYTE_2(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_2) - -/*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_2. */ -#define BF_CAN_WORD0n_DATA_BYTE_2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_2) & BM_CAN_WORD0n_DATA_BYTE_2) - -/*! @brief Set the DATA_BYTE_2 field to a new value. */ -#define BW_CAN_WORD0n_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_2) | BF_CAN_WORD0n_DATA_BYTE_2(v))) -/*@}*/ - -/*! - * @name Register CAN_WORD0n, field DATA_BYTE_1[23:16] (RW) - */ -/*@{*/ -#define BP_CAN_WORD0n_DATA_BYTE_1 (16U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_1. */ -#define BM_CAN_WORD0n_DATA_BYTE_1 (0x00FF0000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_1. */ -#define BS_CAN_WORD0n_DATA_BYTE_1 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_1. */ - -/*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_1 field. */ -#define BR_CAN_WORD0n_DATA_BYTE_1(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_1) - -/*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_1. */ -#define BF_CAN_WORD0n_DATA_BYTE_1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_1) & BM_CAN_WORD0n_DATA_BYTE_1) - -/*! @brief Set the DATA_BYTE_1 field to a new value. */ -#define BW_CAN_WORD0n_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_1) | BF_CAN_WORD0n_DATA_BYTE_1(v))) -/*@}*/ - -/*! - * @name Register CAN_WORD0n, field DATA_BYTE_0[31:24] (RW) - */ -/*@{*/ -#define BP_CAN_WORD0n_DATA_BYTE_0 (24U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_0. */ -#define BM_CAN_WORD0n_DATA_BYTE_0 (0xFF000000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_0. */ -#define BS_CAN_WORD0n_DATA_BYTE_0 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_0. */ - -/*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_0 field. */ -#define BR_CAN_WORD0n_DATA_BYTE_0(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_0) - -/*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_0. */ -#define BF_CAN_WORD0n_DATA_BYTE_0(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_0) & BM_CAN_WORD0n_DATA_BYTE_0) - -/*! @brief Set the DATA_BYTE_0 field to a new value. */ -#define BW_CAN_WORD0n_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_0) | BF_CAN_WORD0n_DATA_BYTE_0(v))) -/*@}*/ -/******************************************************************************* - * HW_CAN_WORD1n - Message Buffer 0 WORD1 Register - ******************************************************************************/ - -/*! - * @brief HW_CAN_WORD1n - Message Buffer 0 WORD1 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_can_word1n -{ - uint32_t U; - struct _hw_can_word1n_bitfields - { - uint32_t DATA_BYTE_7 : 8; /*!< [7:0] Data byte 7 of Rx/Tx frame. */ - uint32_t DATA_BYTE_6 : 8; /*!< [15:8] Data byte 6 of Rx/Tx frame. */ - uint32_t DATA_BYTE_5 : 8; /*!< [23:16] Data byte 5 of Rx/Tx frame. */ - uint32_t DATA_BYTE_4 : 8; /*!< [31:24] Data byte 4 of Rx/Tx frame. */ - } B; -} hw_can_word1n_t; - -/*! - * @name Constants and macros for entire CAN_WORD1n register - */ -/*@{*/ -#define HW_CAN_WORD1n_COUNT (16U) - -#define HW_CAN_WORD1n_ADDR(x, n) ((x) + 0x8CU + (0x10U * (n))) - -#define HW_CAN_WORD1n(x, n) (*(__IO hw_can_word1n_t *) HW_CAN_WORD1n_ADDR(x, n)) -#define HW_CAN_WORD1n_RD(x, n) (HW_CAN_WORD1n(x, n).U) -#define HW_CAN_WORD1n_WR(x, n, v) (HW_CAN_WORD1n(x, n).U = (v)) -#define HW_CAN_WORD1n_SET(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) | (v))) -#define HW_CAN_WORD1n_CLR(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) & ~(v))) -#define HW_CAN_WORD1n_TOG(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_WORD1n bitfields - */ - -/*! - * @name Register CAN_WORD1n, field DATA_BYTE_7[7:0] (RW) - */ -/*@{*/ -#define BP_CAN_WORD1n_DATA_BYTE_7 (0U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_7. */ -#define BM_CAN_WORD1n_DATA_BYTE_7 (0x000000FFU) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_7. */ -#define BS_CAN_WORD1n_DATA_BYTE_7 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_7. */ - -/*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_7 field. */ -#define BR_CAN_WORD1n_DATA_BYTE_7(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_7) - -/*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_7. */ -#define BF_CAN_WORD1n_DATA_BYTE_7(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_7) & BM_CAN_WORD1n_DATA_BYTE_7) - -/*! @brief Set the DATA_BYTE_7 field to a new value. */ -#define BW_CAN_WORD1n_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_7) | BF_CAN_WORD1n_DATA_BYTE_7(v))) -/*@}*/ - -/*! - * @name Register CAN_WORD1n, field DATA_BYTE_6[15:8] (RW) - */ -/*@{*/ -#define BP_CAN_WORD1n_DATA_BYTE_6 (8U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_6. */ -#define BM_CAN_WORD1n_DATA_BYTE_6 (0x0000FF00U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_6. */ -#define BS_CAN_WORD1n_DATA_BYTE_6 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_6. */ - -/*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_6 field. */ -#define BR_CAN_WORD1n_DATA_BYTE_6(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_6) - -/*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_6. */ -#define BF_CAN_WORD1n_DATA_BYTE_6(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_6) & BM_CAN_WORD1n_DATA_BYTE_6) - -/*! @brief Set the DATA_BYTE_6 field to a new value. */ -#define BW_CAN_WORD1n_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_6) | BF_CAN_WORD1n_DATA_BYTE_6(v))) -/*@}*/ - -/*! - * @name Register CAN_WORD1n, field DATA_BYTE_5[23:16] (RW) - */ -/*@{*/ -#define BP_CAN_WORD1n_DATA_BYTE_5 (16U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_5. */ -#define BM_CAN_WORD1n_DATA_BYTE_5 (0x00FF0000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_5. */ -#define BS_CAN_WORD1n_DATA_BYTE_5 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_5. */ - -/*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_5 field. */ -#define BR_CAN_WORD1n_DATA_BYTE_5(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_5) - -/*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_5. */ -#define BF_CAN_WORD1n_DATA_BYTE_5(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_5) & BM_CAN_WORD1n_DATA_BYTE_5) - -/*! @brief Set the DATA_BYTE_5 field to a new value. */ -#define BW_CAN_WORD1n_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_5) | BF_CAN_WORD1n_DATA_BYTE_5(v))) -/*@}*/ - -/*! - * @name Register CAN_WORD1n, field DATA_BYTE_4[31:24] (RW) - */ -/*@{*/ -#define BP_CAN_WORD1n_DATA_BYTE_4 (24U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_4. */ -#define BM_CAN_WORD1n_DATA_BYTE_4 (0xFF000000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_4. */ -#define BS_CAN_WORD1n_DATA_BYTE_4 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_4. */ - -/*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_4 field. */ -#define BR_CAN_WORD1n_DATA_BYTE_4(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_4) - -/*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_4. */ -#define BF_CAN_WORD1n_DATA_BYTE_4(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_4) & BM_CAN_WORD1n_DATA_BYTE_4) - -/*! @brief Set the DATA_BYTE_4 field to a new value. */ -#define BW_CAN_WORD1n_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_4) | BF_CAN_WORD1n_DATA_BYTE_4(v))) -/*@}*/ - -/******************************************************************************* - * HW_CAN_RXIMRn - Rx Individual Mask Registers - ******************************************************************************/ - -/*! - * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW) - * - * Reset value: 0x00000000U - * - * These registers are located in RAM. RXIMR are used as acceptance masks for ID - * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask - * register is provided for each available Mailbox, providing ID masking - * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is - * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter - * Table elements on a one-to-one correspondence depending on the setting of - * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze - * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers - * are not affected by reset and must be explicitly initialized prior to any - * reception. - */ -typedef union _hw_can_rximrn -{ - uint32_t U; - struct _hw_can_rximrn_bitfields - { - uint32_t MI : 32; /*!< [31:0] Individual Mask Bits */ - } B; -} hw_can_rximrn_t; - -/*! - * @name Constants and macros for entire CAN_RXIMRn register - */ -/*@{*/ -#define HW_CAN_RXIMRn_COUNT (16U) - -#define HW_CAN_RXIMRn_ADDR(x, n) ((x) + 0x880U + (0x4U * (n))) - -#define HW_CAN_RXIMRn(x, n) (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n)) -#define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U) -#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v)) -#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) | (v))) -#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v))) -#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CAN_RXIMRn bitfields - */ - -/*! - * @name Register CAN_RXIMRn, field MI[31:0] (RW) - * - * Each Individual Mask Bit masks the corresponding bit in both the Mailbox - * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters, - * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements, - * see the RXFGMASK register description. - * - * Values: - * - 0 - The corresponding bit in the filter is "don't care." - * - 1 - The corresponding bit in the filter is checked. - */ -/*@{*/ -#define BP_CAN_RXIMRn_MI (0U) /*!< Bit position for CAN_RXIMRn_MI. */ -#define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) /*!< Bit mask for CAN_RXIMRn_MI. */ -#define BS_CAN_RXIMRn_MI (32U) /*!< Bit field size in bits for CAN_RXIMRn_MI. */ - -/*! @brief Read current value of the CAN_RXIMRn_MI field. */ -#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U) - -/*! @brief Format value for bitfield CAN_RXIMRn_MI. */ -#define BF_CAN_RXIMRn_MI(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXIMRn_MI) & BM_CAN_RXIMRn_MI) - -/*! @brief Set the MI field to a new value. */ -#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * hw_can_t - module struct - ******************************************************************************/ -/*! - * @brief All CAN module registers. - */ -#pragma pack(1) -typedef struct _hw_can -{ - __IO hw_can_mcr_t MCR; /*!< [0x0] Module Configuration Register */ - __IO hw_can_ctrl1_t CTRL1; /*!< [0x4] Control 1 register */ - __IO hw_can_timer_t TIMER; /*!< [0x8] Free Running Timer */ - uint8_t _reserved0[4]; - __IO hw_can_rxmgmask_t RXMGMASK; /*!< [0x10] Rx Mailboxes Global Mask Register */ - __IO hw_can_rx14mask_t RX14MASK; /*!< [0x14] Rx 14 Mask register */ - __IO hw_can_rx15mask_t RX15MASK; /*!< [0x18] Rx 15 Mask register */ - __IO hw_can_ecr_t ECR; /*!< [0x1C] Error Counter */ - __IO hw_can_esr1_t ESR1; /*!< [0x20] Error and Status 1 register */ - uint8_t _reserved1[4]; - __IO hw_can_imask1_t IMASK1; /*!< [0x28] Interrupt Masks 1 register */ - uint8_t _reserved2[4]; - __IO hw_can_iflag1_t IFLAG1; /*!< [0x30] Interrupt Flags 1 register */ - __IO hw_can_ctrl2_t CTRL2; /*!< [0x34] Control 2 register */ - __I hw_can_esr2_t ESR2; /*!< [0x38] Error and Status 2 register */ - uint8_t _reserved3[8]; - __I hw_can_crcr_t CRCR; /*!< [0x44] CRC Register */ - __IO hw_can_rxfgmask_t RXFGMASK; /*!< [0x48] Rx FIFO Global Mask register */ - __I hw_can_rxfir_t RXFIR; /*!< [0x4C] Rx FIFO Information Register */ - uint8_t _reserved4[48]; - struct { - __IO hw_can_csn_t CSn; /*!< [0x80] Message Buffer 0 CS Register */ - __IO hw_can_idn_t IDn; /*!< [0x84] Message Buffer 0 ID Register */ - __IO hw_can_word0n_t WORD0n; /*!< [0x88] Message Buffer 0 WORD0 Register */ - __IO hw_can_word1n_t WORD1n; /*!< [0x8C] Message Buffer 0 WORD1 Register */ - } MB[16]; - uint8_t _reserved5[1792]; - __IO hw_can_rximrn_t RXIMRn[16]; /*!< [0x880] Rx Individual Mask Registers */ -} hw_can_t; -#pragma pack() - -/*! @brief Macro to access all CAN registers. */ -/*! @param x CAN module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CAN(CAN0_BASE). */ -#define HW_CAN(x) (*(hw_can_t *)(x)) - -#endif /* __HW_CAN_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cau.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cau.h deleted file mode 100644 index aaeb60b7f10..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cau.h +++ /dev/null @@ -1,5229 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CAU_REGISTERS_H__ -#define __HW_CAU_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 CAU - * - * Memory Mapped Cryptographic Acceleration Unit (MMCAU) - * - * Registers defined in this header file: - * - HW_CAU_DIRECT0 - Direct access register 0 - * - HW_CAU_DIRECT1 - Direct access register 1 - * - HW_CAU_DIRECT2 - Direct access register 2 - * - HW_CAU_DIRECT3 - Direct access register 3 - * - HW_CAU_DIRECT4 - Direct access register 4 - * - HW_CAU_DIRECT5 - Direct access register 5 - * - HW_CAU_DIRECT6 - Direct access register 6 - * - HW_CAU_DIRECT7 - Direct access register 7 - * - HW_CAU_DIRECT8 - Direct access register 8 - * - HW_CAU_DIRECT9 - Direct access register 9 - * - HW_CAU_DIRECT10 - Direct access register 10 - * - HW_CAU_DIRECT11 - Direct access register 11 - * - HW_CAU_DIRECT12 - Direct access register 12 - * - HW_CAU_DIRECT13 - Direct access register 13 - * - HW_CAU_DIRECT14 - Direct access register 14 - * - HW_CAU_DIRECT15 - Direct access register 15 - * - HW_CAU_LDR_CASR - Status register - Load Register command - * - HW_CAU_LDR_CAA - Accumulator register - Load Register command - * - HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command - * - HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command - * - HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command - * - HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command - * - HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command - * - HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command - * - HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command - * - HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command - * - HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command - * - HW_CAU_STR_CASR - Status register - Store Register command - * - HW_CAU_STR_CAA - Accumulator register - Store Register command - * - HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command - * - HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command - * - HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command - * - HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command - * - HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command - * - HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command - * - HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command - * - HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command - * - HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command - * - HW_CAU_ADR_CASR - Status register - Add Register command - * - HW_CAU_ADR_CAA - Accumulator register - Add to register command - * - HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command - * - HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command - * - HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command - * - HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command - * - HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command - * - HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command - * - HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command - * - HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command - * - HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command - * - HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command - * - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command - * - HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command - * - HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command - * - HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command - * - HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command - * - HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command - * - HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command - * - HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command - * - HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command - * - HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command - * - HW_CAU_XOR_CASR - Status register - Exclusive Or command - * - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command - * - HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command - * - HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command - * - HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command - * - HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command - * - HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command - * - HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command - * - HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command - * - HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command - * - HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command - * - HW_CAU_ROTL_CASR - Status register - Rotate Left command - * - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command - * - HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command - * - HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command - * - HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command - * - HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command - * - HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command - * - HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command - * - HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command - * - HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command - * - HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command - * - HW_CAU_AESC_CASR - Status register - AES Column Operation command - * - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command - * - HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command - * - HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command - * - HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command - * - HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command - * - HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command - * - HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command - * - HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command - * - HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command - * - HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command - * - HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command - * - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command - * - HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command - * - * - hw_cau_t - Struct containing all module registers. - */ - -#define HW_CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */ - -/******************************************************************************* - * HW_CAU_DIRECT0 - Direct access register 0 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT0 - Direct access register 0 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct0 -{ - uint32_t U; - struct _hw_cau_direct0_bitfields - { - uint32_t CAU_DIRECT0b : 32; /*!< [31:0] Direct register 0 */ - } B; -} hw_cau_direct0_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT0 register - */ -/*@{*/ -#define HW_CAU_DIRECT0_ADDR(x) ((x) + 0x0U) - -#define HW_CAU_DIRECT0(x) (*(__O hw_cau_direct0_t *) HW_CAU_DIRECT0_ADDR(x)) -#define HW_CAU_DIRECT0_WR(x, v) (HW_CAU_DIRECT0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT0 bitfields - */ - -/*! - * @name Register CAU_DIRECT0, field CAU_DIRECT0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT0_CAU_DIRECT0 (0U) /*!< Bit position for CAU_DIRECT0_CAU_DIRECT0. */ -#define BM_CAU_DIRECT0_CAU_DIRECT0 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT0_CAU_DIRECT0. */ -#define BS_CAU_DIRECT0_CAU_DIRECT0 (32U) /*!< Bit field size in bits for CAU_DIRECT0_CAU_DIRECT0. */ - -/*! @brief Format value for bitfield CAU_DIRECT0_CAU_DIRECT0. */ -#define BF_CAU_DIRECT0_CAU_DIRECT0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT0_CAU_DIRECT0) & BM_CAU_DIRECT0_CAU_DIRECT0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT1 - Direct access register 1 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT1 - Direct access register 1 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct1 -{ - uint32_t U; - struct _hw_cau_direct1_bitfields - { - uint32_t CAU_DIRECT1b : 32; /*!< [31:0] Direct register 1 */ - } B; -} hw_cau_direct1_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT1 register - */ -/*@{*/ -#define HW_CAU_DIRECT1_ADDR(x) ((x) + 0x4U) - -#define HW_CAU_DIRECT1(x) (*(__O hw_cau_direct1_t *) HW_CAU_DIRECT1_ADDR(x)) -#define HW_CAU_DIRECT1_WR(x, v) (HW_CAU_DIRECT1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT1 bitfields - */ - -/*! - * @name Register CAU_DIRECT1, field CAU_DIRECT1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT1_CAU_DIRECT1 (0U) /*!< Bit position for CAU_DIRECT1_CAU_DIRECT1. */ -#define BM_CAU_DIRECT1_CAU_DIRECT1 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT1_CAU_DIRECT1. */ -#define BS_CAU_DIRECT1_CAU_DIRECT1 (32U) /*!< Bit field size in bits for CAU_DIRECT1_CAU_DIRECT1. */ - -/*! @brief Format value for bitfield CAU_DIRECT1_CAU_DIRECT1. */ -#define BF_CAU_DIRECT1_CAU_DIRECT1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT1_CAU_DIRECT1) & BM_CAU_DIRECT1_CAU_DIRECT1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT2 - Direct access register 2 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT2 - Direct access register 2 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct2 -{ - uint32_t U; - struct _hw_cau_direct2_bitfields - { - uint32_t CAU_DIRECT2b : 32; /*!< [31:0] Direct register 2 */ - } B; -} hw_cau_direct2_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT2 register - */ -/*@{*/ -#define HW_CAU_DIRECT2_ADDR(x) ((x) + 0x8U) - -#define HW_CAU_DIRECT2(x) (*(__O hw_cau_direct2_t *) HW_CAU_DIRECT2_ADDR(x)) -#define HW_CAU_DIRECT2_WR(x, v) (HW_CAU_DIRECT2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT2 bitfields - */ - -/*! - * @name Register CAU_DIRECT2, field CAU_DIRECT2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT2_CAU_DIRECT2 (0U) /*!< Bit position for CAU_DIRECT2_CAU_DIRECT2. */ -#define BM_CAU_DIRECT2_CAU_DIRECT2 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT2_CAU_DIRECT2. */ -#define BS_CAU_DIRECT2_CAU_DIRECT2 (32U) /*!< Bit field size in bits for CAU_DIRECT2_CAU_DIRECT2. */ - -/*! @brief Format value for bitfield CAU_DIRECT2_CAU_DIRECT2. */ -#define BF_CAU_DIRECT2_CAU_DIRECT2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT2_CAU_DIRECT2) & BM_CAU_DIRECT2_CAU_DIRECT2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT3 - Direct access register 3 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT3 - Direct access register 3 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct3 -{ - uint32_t U; - struct _hw_cau_direct3_bitfields - { - uint32_t CAU_DIRECT3b : 32; /*!< [31:0] Direct register 3 */ - } B; -} hw_cau_direct3_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT3 register - */ -/*@{*/ -#define HW_CAU_DIRECT3_ADDR(x) ((x) + 0xCU) - -#define HW_CAU_DIRECT3(x) (*(__O hw_cau_direct3_t *) HW_CAU_DIRECT3_ADDR(x)) -#define HW_CAU_DIRECT3_WR(x, v) (HW_CAU_DIRECT3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT3 bitfields - */ - -/*! - * @name Register CAU_DIRECT3, field CAU_DIRECT3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT3_CAU_DIRECT3 (0U) /*!< Bit position for CAU_DIRECT3_CAU_DIRECT3. */ -#define BM_CAU_DIRECT3_CAU_DIRECT3 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT3_CAU_DIRECT3. */ -#define BS_CAU_DIRECT3_CAU_DIRECT3 (32U) /*!< Bit field size in bits for CAU_DIRECT3_CAU_DIRECT3. */ - -/*! @brief Format value for bitfield CAU_DIRECT3_CAU_DIRECT3. */ -#define BF_CAU_DIRECT3_CAU_DIRECT3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT3_CAU_DIRECT3) & BM_CAU_DIRECT3_CAU_DIRECT3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT4 - Direct access register 4 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT4 - Direct access register 4 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct4 -{ - uint32_t U; - struct _hw_cau_direct4_bitfields - { - uint32_t CAU_DIRECT4b : 32; /*!< [31:0] Direct register 4 */ - } B; -} hw_cau_direct4_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT4 register - */ -/*@{*/ -#define HW_CAU_DIRECT4_ADDR(x) ((x) + 0x10U) - -#define HW_CAU_DIRECT4(x) (*(__O hw_cau_direct4_t *) HW_CAU_DIRECT4_ADDR(x)) -#define HW_CAU_DIRECT4_WR(x, v) (HW_CAU_DIRECT4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT4 bitfields - */ - -/*! - * @name Register CAU_DIRECT4, field CAU_DIRECT4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT4_CAU_DIRECT4 (0U) /*!< Bit position for CAU_DIRECT4_CAU_DIRECT4. */ -#define BM_CAU_DIRECT4_CAU_DIRECT4 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT4_CAU_DIRECT4. */ -#define BS_CAU_DIRECT4_CAU_DIRECT4 (32U) /*!< Bit field size in bits for CAU_DIRECT4_CAU_DIRECT4. */ - -/*! @brief Format value for bitfield CAU_DIRECT4_CAU_DIRECT4. */ -#define BF_CAU_DIRECT4_CAU_DIRECT4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT4_CAU_DIRECT4) & BM_CAU_DIRECT4_CAU_DIRECT4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT5 - Direct access register 5 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT5 - Direct access register 5 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct5 -{ - uint32_t U; - struct _hw_cau_direct5_bitfields - { - uint32_t CAU_DIRECT5b : 32; /*!< [31:0] Direct register 5 */ - } B; -} hw_cau_direct5_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT5 register - */ -/*@{*/ -#define HW_CAU_DIRECT5_ADDR(x) ((x) + 0x14U) - -#define HW_CAU_DIRECT5(x) (*(__O hw_cau_direct5_t *) HW_CAU_DIRECT5_ADDR(x)) -#define HW_CAU_DIRECT5_WR(x, v) (HW_CAU_DIRECT5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT5 bitfields - */ - -/*! - * @name Register CAU_DIRECT5, field CAU_DIRECT5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT5_CAU_DIRECT5 (0U) /*!< Bit position for CAU_DIRECT5_CAU_DIRECT5. */ -#define BM_CAU_DIRECT5_CAU_DIRECT5 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT5_CAU_DIRECT5. */ -#define BS_CAU_DIRECT5_CAU_DIRECT5 (32U) /*!< Bit field size in bits for CAU_DIRECT5_CAU_DIRECT5. */ - -/*! @brief Format value for bitfield CAU_DIRECT5_CAU_DIRECT5. */ -#define BF_CAU_DIRECT5_CAU_DIRECT5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT5_CAU_DIRECT5) & BM_CAU_DIRECT5_CAU_DIRECT5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT6 - Direct access register 6 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT6 - Direct access register 6 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct6 -{ - uint32_t U; - struct _hw_cau_direct6_bitfields - { - uint32_t CAU_DIRECT6b : 32; /*!< [31:0] Direct register 6 */ - } B; -} hw_cau_direct6_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT6 register - */ -/*@{*/ -#define HW_CAU_DIRECT6_ADDR(x) ((x) + 0x18U) - -#define HW_CAU_DIRECT6(x) (*(__O hw_cau_direct6_t *) HW_CAU_DIRECT6_ADDR(x)) -#define HW_CAU_DIRECT6_WR(x, v) (HW_CAU_DIRECT6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT6 bitfields - */ - -/*! - * @name Register CAU_DIRECT6, field CAU_DIRECT6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT6_CAU_DIRECT6 (0U) /*!< Bit position for CAU_DIRECT6_CAU_DIRECT6. */ -#define BM_CAU_DIRECT6_CAU_DIRECT6 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT6_CAU_DIRECT6. */ -#define BS_CAU_DIRECT6_CAU_DIRECT6 (32U) /*!< Bit field size in bits for CAU_DIRECT6_CAU_DIRECT6. */ - -/*! @brief Format value for bitfield CAU_DIRECT6_CAU_DIRECT6. */ -#define BF_CAU_DIRECT6_CAU_DIRECT6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT6_CAU_DIRECT6) & BM_CAU_DIRECT6_CAU_DIRECT6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT7 - Direct access register 7 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT7 - Direct access register 7 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct7 -{ - uint32_t U; - struct _hw_cau_direct7_bitfields - { - uint32_t CAU_DIRECT7b : 32; /*!< [31:0] Direct register 7 */ - } B; -} hw_cau_direct7_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT7 register - */ -/*@{*/ -#define HW_CAU_DIRECT7_ADDR(x) ((x) + 0x1CU) - -#define HW_CAU_DIRECT7(x) (*(__O hw_cau_direct7_t *) HW_CAU_DIRECT7_ADDR(x)) -#define HW_CAU_DIRECT7_WR(x, v) (HW_CAU_DIRECT7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT7 bitfields - */ - -/*! - * @name Register CAU_DIRECT7, field CAU_DIRECT7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT7_CAU_DIRECT7 (0U) /*!< Bit position for CAU_DIRECT7_CAU_DIRECT7. */ -#define BM_CAU_DIRECT7_CAU_DIRECT7 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT7_CAU_DIRECT7. */ -#define BS_CAU_DIRECT7_CAU_DIRECT7 (32U) /*!< Bit field size in bits for CAU_DIRECT7_CAU_DIRECT7. */ - -/*! @brief Format value for bitfield CAU_DIRECT7_CAU_DIRECT7. */ -#define BF_CAU_DIRECT7_CAU_DIRECT7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT7_CAU_DIRECT7) & BM_CAU_DIRECT7_CAU_DIRECT7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT8 - Direct access register 8 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT8 - Direct access register 8 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct8 -{ - uint32_t U; - struct _hw_cau_direct8_bitfields - { - uint32_t CAU_DIRECT8b : 32; /*!< [31:0] Direct register 8 */ - } B; -} hw_cau_direct8_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT8 register - */ -/*@{*/ -#define HW_CAU_DIRECT8_ADDR(x) ((x) + 0x20U) - -#define HW_CAU_DIRECT8(x) (*(__O hw_cau_direct8_t *) HW_CAU_DIRECT8_ADDR(x)) -#define HW_CAU_DIRECT8_WR(x, v) (HW_CAU_DIRECT8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT8 bitfields - */ - -/*! - * @name Register CAU_DIRECT8, field CAU_DIRECT8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT8_CAU_DIRECT8 (0U) /*!< Bit position for CAU_DIRECT8_CAU_DIRECT8. */ -#define BM_CAU_DIRECT8_CAU_DIRECT8 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT8_CAU_DIRECT8. */ -#define BS_CAU_DIRECT8_CAU_DIRECT8 (32U) /*!< Bit field size in bits for CAU_DIRECT8_CAU_DIRECT8. */ - -/*! @brief Format value for bitfield CAU_DIRECT8_CAU_DIRECT8. */ -#define BF_CAU_DIRECT8_CAU_DIRECT8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT8_CAU_DIRECT8) & BM_CAU_DIRECT8_CAU_DIRECT8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT9 - Direct access register 9 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT9 - Direct access register 9 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct9 -{ - uint32_t U; - struct _hw_cau_direct9_bitfields - { - uint32_t CAU_DIRECT9b : 32; /*!< [31:0] Direct register 9 */ - } B; -} hw_cau_direct9_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT9 register - */ -/*@{*/ -#define HW_CAU_DIRECT9_ADDR(x) ((x) + 0x24U) - -#define HW_CAU_DIRECT9(x) (*(__O hw_cau_direct9_t *) HW_CAU_DIRECT9_ADDR(x)) -#define HW_CAU_DIRECT9_WR(x, v) (HW_CAU_DIRECT9(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT9 bitfields - */ - -/*! - * @name Register CAU_DIRECT9, field CAU_DIRECT9[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT9_CAU_DIRECT9 (0U) /*!< Bit position for CAU_DIRECT9_CAU_DIRECT9. */ -#define BM_CAU_DIRECT9_CAU_DIRECT9 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT9_CAU_DIRECT9. */ -#define BS_CAU_DIRECT9_CAU_DIRECT9 (32U) /*!< Bit field size in bits for CAU_DIRECT9_CAU_DIRECT9. */ - -/*! @brief Format value for bitfield CAU_DIRECT9_CAU_DIRECT9. */ -#define BF_CAU_DIRECT9_CAU_DIRECT9(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT9_CAU_DIRECT9) & BM_CAU_DIRECT9_CAU_DIRECT9) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT10 - Direct access register 10 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT10 - Direct access register 10 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct10 -{ - uint32_t U; - struct _hw_cau_direct10_bitfields - { - uint32_t CAU_DIRECT10b : 32; /*!< [31:0] Direct register 10 */ - } B; -} hw_cau_direct10_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT10 register - */ -/*@{*/ -#define HW_CAU_DIRECT10_ADDR(x) ((x) + 0x28U) - -#define HW_CAU_DIRECT10(x) (*(__O hw_cau_direct10_t *) HW_CAU_DIRECT10_ADDR(x)) -#define HW_CAU_DIRECT10_WR(x, v) (HW_CAU_DIRECT10(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT10 bitfields - */ - -/*! - * @name Register CAU_DIRECT10, field CAU_DIRECT10[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT10_CAU_DIRECT10 (0U) /*!< Bit position for CAU_DIRECT10_CAU_DIRECT10. */ -#define BM_CAU_DIRECT10_CAU_DIRECT10 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT10_CAU_DIRECT10. */ -#define BS_CAU_DIRECT10_CAU_DIRECT10 (32U) /*!< Bit field size in bits for CAU_DIRECT10_CAU_DIRECT10. */ - -/*! @brief Format value for bitfield CAU_DIRECT10_CAU_DIRECT10. */ -#define BF_CAU_DIRECT10_CAU_DIRECT10(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT10_CAU_DIRECT10) & BM_CAU_DIRECT10_CAU_DIRECT10) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT11 - Direct access register 11 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT11 - Direct access register 11 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct11 -{ - uint32_t U; - struct _hw_cau_direct11_bitfields - { - uint32_t CAU_DIRECT11b : 32; /*!< [31:0] Direct register 11 */ - } B; -} hw_cau_direct11_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT11 register - */ -/*@{*/ -#define HW_CAU_DIRECT11_ADDR(x) ((x) + 0x2CU) - -#define HW_CAU_DIRECT11(x) (*(__O hw_cau_direct11_t *) HW_CAU_DIRECT11_ADDR(x)) -#define HW_CAU_DIRECT11_WR(x, v) (HW_CAU_DIRECT11(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT11 bitfields - */ - -/*! - * @name Register CAU_DIRECT11, field CAU_DIRECT11[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT11_CAU_DIRECT11 (0U) /*!< Bit position for CAU_DIRECT11_CAU_DIRECT11. */ -#define BM_CAU_DIRECT11_CAU_DIRECT11 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT11_CAU_DIRECT11. */ -#define BS_CAU_DIRECT11_CAU_DIRECT11 (32U) /*!< Bit field size in bits for CAU_DIRECT11_CAU_DIRECT11. */ - -/*! @brief Format value for bitfield CAU_DIRECT11_CAU_DIRECT11. */ -#define BF_CAU_DIRECT11_CAU_DIRECT11(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT11_CAU_DIRECT11) & BM_CAU_DIRECT11_CAU_DIRECT11) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT12 - Direct access register 12 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT12 - Direct access register 12 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct12 -{ - uint32_t U; - struct _hw_cau_direct12_bitfields - { - uint32_t CAU_DIRECT12b : 32; /*!< [31:0] Direct register 12 */ - } B; -} hw_cau_direct12_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT12 register - */ -/*@{*/ -#define HW_CAU_DIRECT12_ADDR(x) ((x) + 0x30U) - -#define HW_CAU_DIRECT12(x) (*(__O hw_cau_direct12_t *) HW_CAU_DIRECT12_ADDR(x)) -#define HW_CAU_DIRECT12_WR(x, v) (HW_CAU_DIRECT12(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT12 bitfields - */ - -/*! - * @name Register CAU_DIRECT12, field CAU_DIRECT12[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT12_CAU_DIRECT12 (0U) /*!< Bit position for CAU_DIRECT12_CAU_DIRECT12. */ -#define BM_CAU_DIRECT12_CAU_DIRECT12 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT12_CAU_DIRECT12. */ -#define BS_CAU_DIRECT12_CAU_DIRECT12 (32U) /*!< Bit field size in bits for CAU_DIRECT12_CAU_DIRECT12. */ - -/*! @brief Format value for bitfield CAU_DIRECT12_CAU_DIRECT12. */ -#define BF_CAU_DIRECT12_CAU_DIRECT12(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT12_CAU_DIRECT12) & BM_CAU_DIRECT12_CAU_DIRECT12) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT13 - Direct access register 13 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT13 - Direct access register 13 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct13 -{ - uint32_t U; - struct _hw_cau_direct13_bitfields - { - uint32_t CAU_DIRECT13b : 32; /*!< [31:0] Direct register 13 */ - } B; -} hw_cau_direct13_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT13 register - */ -/*@{*/ -#define HW_CAU_DIRECT13_ADDR(x) ((x) + 0x34U) - -#define HW_CAU_DIRECT13(x) (*(__O hw_cau_direct13_t *) HW_CAU_DIRECT13_ADDR(x)) -#define HW_CAU_DIRECT13_WR(x, v) (HW_CAU_DIRECT13(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT13 bitfields - */ - -/*! - * @name Register CAU_DIRECT13, field CAU_DIRECT13[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT13_CAU_DIRECT13 (0U) /*!< Bit position for CAU_DIRECT13_CAU_DIRECT13. */ -#define BM_CAU_DIRECT13_CAU_DIRECT13 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT13_CAU_DIRECT13. */ -#define BS_CAU_DIRECT13_CAU_DIRECT13 (32U) /*!< Bit field size in bits for CAU_DIRECT13_CAU_DIRECT13. */ - -/*! @brief Format value for bitfield CAU_DIRECT13_CAU_DIRECT13. */ -#define BF_CAU_DIRECT13_CAU_DIRECT13(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT13_CAU_DIRECT13) & BM_CAU_DIRECT13_CAU_DIRECT13) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT14 - Direct access register 14 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT14 - Direct access register 14 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct14 -{ - uint32_t U; - struct _hw_cau_direct14_bitfields - { - uint32_t CAU_DIRECT14b : 32; /*!< [31:0] Direct register 14 */ - } B; -} hw_cau_direct14_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT14 register - */ -/*@{*/ -#define HW_CAU_DIRECT14_ADDR(x) ((x) + 0x38U) - -#define HW_CAU_DIRECT14(x) (*(__O hw_cau_direct14_t *) HW_CAU_DIRECT14_ADDR(x)) -#define HW_CAU_DIRECT14_WR(x, v) (HW_CAU_DIRECT14(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT14 bitfields - */ - -/*! - * @name Register CAU_DIRECT14, field CAU_DIRECT14[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT14_CAU_DIRECT14 (0U) /*!< Bit position for CAU_DIRECT14_CAU_DIRECT14. */ -#define BM_CAU_DIRECT14_CAU_DIRECT14 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT14_CAU_DIRECT14. */ -#define BS_CAU_DIRECT14_CAU_DIRECT14 (32U) /*!< Bit field size in bits for CAU_DIRECT14_CAU_DIRECT14. */ - -/*! @brief Format value for bitfield CAU_DIRECT14_CAU_DIRECT14. */ -#define BF_CAU_DIRECT14_CAU_DIRECT14(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT14_CAU_DIRECT14) & BM_CAU_DIRECT14_CAU_DIRECT14) -/*@}*/ - -/******************************************************************************* - * HW_CAU_DIRECT15 - Direct access register 15 - ******************************************************************************/ - -/*! - * @brief HW_CAU_DIRECT15 - Direct access register 15 (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_direct15 -{ - uint32_t U; - struct _hw_cau_direct15_bitfields - { - uint32_t CAU_DIRECT15b : 32; /*!< [31:0] Direct register 15 */ - } B; -} hw_cau_direct15_t; - -/*! - * @name Constants and macros for entire CAU_DIRECT15 register - */ -/*@{*/ -#define HW_CAU_DIRECT15_ADDR(x) ((x) + 0x3CU) - -#define HW_CAU_DIRECT15(x) (*(__O hw_cau_direct15_t *) HW_CAU_DIRECT15_ADDR(x)) -#define HW_CAU_DIRECT15_WR(x, v) (HW_CAU_DIRECT15(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_DIRECT15 bitfields - */ - -/*! - * @name Register CAU_DIRECT15, field CAU_DIRECT15[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_DIRECT15_CAU_DIRECT15 (0U) /*!< Bit position for CAU_DIRECT15_CAU_DIRECT15. */ -#define BM_CAU_DIRECT15_CAU_DIRECT15 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT15_CAU_DIRECT15. */ -#define BS_CAU_DIRECT15_CAU_DIRECT15 (32U) /*!< Bit field size in bits for CAU_DIRECT15_CAU_DIRECT15. */ - -/*! @brief Format value for bitfield CAU_DIRECT15_CAU_DIRECT15. */ -#define BF_CAU_DIRECT15_CAU_DIRECT15(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT15_CAU_DIRECT15) & BM_CAU_DIRECT15_CAU_DIRECT15) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CASR - Status register - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CASR - Status register - Load Register command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_ldr_casr -{ - uint32_t U; - struct _hw_cau_ldr_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_ldr_casr_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CASR register - */ -/*@{*/ -#define HW_CAU_LDR_CASR_ADDR(x) ((x) + 0x840U) - -#define HW_CAU_LDR_CASR(x) (*(__O hw_cau_ldr_casr_t *) HW_CAU_LDR_CASR_ADDR(x)) -#define HW_CAU_LDR_CASR_WR(x, v) (HW_CAU_LDR_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CASR bitfields - */ - -/*! - * @name Register CAU_LDR_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_LDR_CASR_IC (0U) /*!< Bit position for CAU_LDR_CASR_IC. */ -#define BM_CAU_LDR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_LDR_CASR_IC. */ -#define BS_CAU_LDR_CASR_IC (1U) /*!< Bit field size in bits for CAU_LDR_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_LDR_CASR_IC. */ -#define BF_CAU_LDR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_IC) & BM_CAU_LDR_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_LDR_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_LDR_CASR_DPE (1U) /*!< Bit position for CAU_LDR_CASR_DPE. */ -#define BM_CAU_LDR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_LDR_CASR_DPE. */ -#define BS_CAU_LDR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_LDR_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_LDR_CASR_DPE. */ -#define BF_CAU_LDR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_DPE) & BM_CAU_LDR_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_LDR_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_LDR_CASR_VER (28U) /*!< Bit position for CAU_LDR_CASR_VER. */ -#define BM_CAU_LDR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_LDR_CASR_VER. */ -#define BS_CAU_LDR_CASR_VER (4U) /*!< Bit field size in bits for CAU_LDR_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_LDR_CASR_VER. */ -#define BF_CAU_LDR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_VER) & BM_CAU_LDR_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CAA - Accumulator register - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_caa -{ - uint32_t U; - struct _hw_cau_ldr_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_ldr_caa_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CAA register - */ -/*@{*/ -#define HW_CAU_LDR_CAA_ADDR(x) ((x) + 0x844U) - -#define HW_CAU_LDR_CAA(x) (*(__O hw_cau_ldr_caa_t *) HW_CAU_LDR_CAA_ADDR(x)) -#define HW_CAU_LDR_CAA_WR(x, v) (HW_CAU_LDR_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CAA bitfields - */ - -/*! - * @name Register CAU_LDR_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CAA_ACC (0U) /*!< Bit position for CAU_LDR_CAA_ACC. */ -#define BM_CAU_LDR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CAA_ACC. */ -#define BS_CAU_LDR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_LDR_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_LDR_CAA_ACC. */ -#define BF_CAU_LDR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CAA_ACC) & BM_CAU_LDR_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca0 -{ - uint32_t U; - struct _hw_cau_ldr_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_ldr_ca0_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA0 register - */ -/*@{*/ -#define HW_CAU_LDR_CA0_ADDR(x) ((x) + 0x848U) - -#define HW_CAU_LDR_CA0(x) (*(__O hw_cau_ldr_ca0_t *) HW_CAU_LDR_CA0_ADDR(x)) -#define HW_CAU_LDR_CA0_WR(x, v) (HW_CAU_LDR_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA0 bitfields - */ - -/*! - * @name Register CAU_LDR_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA0_CA0 (0U) /*!< Bit position for CAU_LDR_CA0_CA0. */ -#define BM_CAU_LDR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA0_CA0. */ -#define BS_CAU_LDR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_LDR_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_LDR_CA0_CA0. */ -#define BF_CAU_LDR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA0_CA0) & BM_CAU_LDR_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca1 -{ - uint32_t U; - struct _hw_cau_ldr_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_ldr_ca1_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA1 register - */ -/*@{*/ -#define HW_CAU_LDR_CA1_ADDR(x) ((x) + 0x84CU) - -#define HW_CAU_LDR_CA1(x) (*(__O hw_cau_ldr_ca1_t *) HW_CAU_LDR_CA1_ADDR(x)) -#define HW_CAU_LDR_CA1_WR(x, v) (HW_CAU_LDR_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA1 bitfields - */ - -/*! - * @name Register CAU_LDR_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA1_CA1 (0U) /*!< Bit position for CAU_LDR_CA1_CA1. */ -#define BM_CAU_LDR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA1_CA1. */ -#define BS_CAU_LDR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_LDR_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_LDR_CA1_CA1. */ -#define BF_CAU_LDR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA1_CA1) & BM_CAU_LDR_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca2 -{ - uint32_t U; - struct _hw_cau_ldr_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_ldr_ca2_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA2 register - */ -/*@{*/ -#define HW_CAU_LDR_CA2_ADDR(x) ((x) + 0x850U) - -#define HW_CAU_LDR_CA2(x) (*(__O hw_cau_ldr_ca2_t *) HW_CAU_LDR_CA2_ADDR(x)) -#define HW_CAU_LDR_CA2_WR(x, v) (HW_CAU_LDR_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA2 bitfields - */ - -/*! - * @name Register CAU_LDR_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA2_CA2 (0U) /*!< Bit position for CAU_LDR_CA2_CA2. */ -#define BM_CAU_LDR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA2_CA2. */ -#define BS_CAU_LDR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_LDR_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_LDR_CA2_CA2. */ -#define BF_CAU_LDR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA2_CA2) & BM_CAU_LDR_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca3 -{ - uint32_t U; - struct _hw_cau_ldr_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_ldr_ca3_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA3 register - */ -/*@{*/ -#define HW_CAU_LDR_CA3_ADDR(x) ((x) + 0x854U) - -#define HW_CAU_LDR_CA3(x) (*(__O hw_cau_ldr_ca3_t *) HW_CAU_LDR_CA3_ADDR(x)) -#define HW_CAU_LDR_CA3_WR(x, v) (HW_CAU_LDR_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA3 bitfields - */ - -/*! - * @name Register CAU_LDR_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA3_CA3 (0U) /*!< Bit position for CAU_LDR_CA3_CA3. */ -#define BM_CAU_LDR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA3_CA3. */ -#define BS_CAU_LDR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_LDR_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_LDR_CA3_CA3. */ -#define BF_CAU_LDR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA3_CA3) & BM_CAU_LDR_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca4 -{ - uint32_t U; - struct _hw_cau_ldr_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_ldr_ca4_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA4 register - */ -/*@{*/ -#define HW_CAU_LDR_CA4_ADDR(x) ((x) + 0x858U) - -#define HW_CAU_LDR_CA4(x) (*(__O hw_cau_ldr_ca4_t *) HW_CAU_LDR_CA4_ADDR(x)) -#define HW_CAU_LDR_CA4_WR(x, v) (HW_CAU_LDR_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA4 bitfields - */ - -/*! - * @name Register CAU_LDR_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA4_CA4 (0U) /*!< Bit position for CAU_LDR_CA4_CA4. */ -#define BM_CAU_LDR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA4_CA4. */ -#define BS_CAU_LDR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_LDR_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_LDR_CA4_CA4. */ -#define BF_CAU_LDR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA4_CA4) & BM_CAU_LDR_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca5 -{ - uint32_t U; - struct _hw_cau_ldr_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_ldr_ca5_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA5 register - */ -/*@{*/ -#define HW_CAU_LDR_CA5_ADDR(x) ((x) + 0x85CU) - -#define HW_CAU_LDR_CA5(x) (*(__O hw_cau_ldr_ca5_t *) HW_CAU_LDR_CA5_ADDR(x)) -#define HW_CAU_LDR_CA5_WR(x, v) (HW_CAU_LDR_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA5 bitfields - */ - -/*! - * @name Register CAU_LDR_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA5_CA5 (0U) /*!< Bit position for CAU_LDR_CA5_CA5. */ -#define BM_CAU_LDR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA5_CA5. */ -#define BS_CAU_LDR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_LDR_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_LDR_CA5_CA5. */ -#define BF_CAU_LDR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA5_CA5) & BM_CAU_LDR_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca6 -{ - uint32_t U; - struct _hw_cau_ldr_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_ldr_ca6_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA6 register - */ -/*@{*/ -#define HW_CAU_LDR_CA6_ADDR(x) ((x) + 0x860U) - -#define HW_CAU_LDR_CA6(x) (*(__O hw_cau_ldr_ca6_t *) HW_CAU_LDR_CA6_ADDR(x)) -#define HW_CAU_LDR_CA6_WR(x, v) (HW_CAU_LDR_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA6 bitfields - */ - -/*! - * @name Register CAU_LDR_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA6_CA6 (0U) /*!< Bit position for CAU_LDR_CA6_CA6. */ -#define BM_CAU_LDR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA6_CA6. */ -#define BS_CAU_LDR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_LDR_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_LDR_CA6_CA6. */ -#define BF_CAU_LDR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA6_CA6) & BM_CAU_LDR_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca7 -{ - uint32_t U; - struct _hw_cau_ldr_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_ldr_ca7_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA7 register - */ -/*@{*/ -#define HW_CAU_LDR_CA7_ADDR(x) ((x) + 0x864U) - -#define HW_CAU_LDR_CA7(x) (*(__O hw_cau_ldr_ca7_t *) HW_CAU_LDR_CA7_ADDR(x)) -#define HW_CAU_LDR_CA7_WR(x, v) (HW_CAU_LDR_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA7 bitfields - */ - -/*! - * @name Register CAU_LDR_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA7_CA7 (0U) /*!< Bit position for CAU_LDR_CA7_CA7. */ -#define BM_CAU_LDR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA7_CA7. */ -#define BS_CAU_LDR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_LDR_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_LDR_CA7_CA7. */ -#define BF_CAU_LDR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA7_CA7) & BM_CAU_LDR_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_ldr_ca8 -{ - uint32_t U; - struct _hw_cau_ldr_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_ldr_ca8_t; - -/*! - * @name Constants and macros for entire CAU_LDR_CA8 register - */ -/*@{*/ -#define HW_CAU_LDR_CA8_ADDR(x) ((x) + 0x868U) - -#define HW_CAU_LDR_CA8(x) (*(__O hw_cau_ldr_ca8_t *) HW_CAU_LDR_CA8_ADDR(x)) -#define HW_CAU_LDR_CA8_WR(x, v) (HW_CAU_LDR_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_LDR_CA8 bitfields - */ - -/*! - * @name Register CAU_LDR_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_LDR_CA8_CA8 (0U) /*!< Bit position for CAU_LDR_CA8_CA8. */ -#define BM_CAU_LDR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA8_CA8. */ -#define BS_CAU_LDR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_LDR_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_LDR_CA8_CA8. */ -#define BF_CAU_LDR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA8_CA8) & BM_CAU_LDR_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CASR - Status register - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CASR - Status register - Store Register command (RO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_str_casr -{ - uint32_t U; - struct _hw_cau_str_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_str_casr_t; - -/*! - * @name Constants and macros for entire CAU_STR_CASR register - */ -/*@{*/ -#define HW_CAU_STR_CASR_ADDR(x) ((x) + 0x880U) - -#define HW_CAU_STR_CASR(x) (*(__I hw_cau_str_casr_t *) HW_CAU_STR_CASR_ADDR(x)) -#define HW_CAU_STR_CASR_RD(x) (HW_CAU_STR_CASR(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CASR bitfields - */ - -/*! - * @name Register CAU_STR_CASR, field IC[0] (RO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_STR_CASR_IC (0U) /*!< Bit position for CAU_STR_CASR_IC. */ -#define BM_CAU_STR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_STR_CASR_IC. */ -#define BS_CAU_STR_CASR_IC (1U) /*!< Bit field size in bits for CAU_STR_CASR_IC. */ - -/*! @brief Read current value of the CAU_STR_CASR_IC field. */ -#define BR_CAU_STR_CASR_IC(x) (HW_CAU_STR_CASR(x).B.IC) -/*@}*/ - -/*! - * @name Register CAU_STR_CASR, field DPE[1] (RO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_STR_CASR_DPE (1U) /*!< Bit position for CAU_STR_CASR_DPE. */ -#define BM_CAU_STR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_STR_CASR_DPE. */ -#define BS_CAU_STR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_STR_CASR_DPE. */ - -/*! @brief Read current value of the CAU_STR_CASR_DPE field. */ -#define BR_CAU_STR_CASR_DPE(x) (HW_CAU_STR_CASR(x).B.DPE) -/*@}*/ - -/*! - * @name Register CAU_STR_CASR, field VER[31:28] (RO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_STR_CASR_VER (28U) /*!< Bit position for CAU_STR_CASR_VER. */ -#define BM_CAU_STR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_STR_CASR_VER. */ -#define BS_CAU_STR_CASR_VER (4U) /*!< Bit field size in bits for CAU_STR_CASR_VER. */ - -/*! @brief Read current value of the CAU_STR_CASR_VER field. */ -#define BR_CAU_STR_CASR_VER(x) (HW_CAU_STR_CASR(x).B.VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CAA - Accumulator register - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_caa -{ - uint32_t U; - struct _hw_cau_str_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_str_caa_t; - -/*! - * @name Constants and macros for entire CAU_STR_CAA register - */ -/*@{*/ -#define HW_CAU_STR_CAA_ADDR(x) ((x) + 0x884U) - -#define HW_CAU_STR_CAA(x) (*(__I hw_cau_str_caa_t *) HW_CAU_STR_CAA_ADDR(x)) -#define HW_CAU_STR_CAA_RD(x) (HW_CAU_STR_CAA(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CAA bitfields - */ - -/*! - * @name Register CAU_STR_CAA, field ACC[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CAA_ACC (0U) /*!< Bit position for CAU_STR_CAA_ACC. */ -#define BM_CAU_STR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CAA_ACC. */ -#define BS_CAU_STR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_STR_CAA_ACC. */ - -/*! @brief Read current value of the CAU_STR_CAA_ACC field. */ -#define BR_CAU_STR_CAA_ACC(x) (HW_CAU_STR_CAA(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca0 -{ - uint32_t U; - struct _hw_cau_str_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_str_ca0_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA0 register - */ -/*@{*/ -#define HW_CAU_STR_CA0_ADDR(x) ((x) + 0x888U) - -#define HW_CAU_STR_CA0(x) (*(__I hw_cau_str_ca0_t *) HW_CAU_STR_CA0_ADDR(x)) -#define HW_CAU_STR_CA0_RD(x) (HW_CAU_STR_CA0(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA0 bitfields - */ - -/*! - * @name Register CAU_STR_CA0, field CA0[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA0_CA0 (0U) /*!< Bit position for CAU_STR_CA0_CA0. */ -#define BM_CAU_STR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA0_CA0. */ -#define BS_CAU_STR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_STR_CA0_CA0. */ - -/*! @brief Read current value of the CAU_STR_CA0_CA0 field. */ -#define BR_CAU_STR_CA0_CA0(x) (HW_CAU_STR_CA0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca1 -{ - uint32_t U; - struct _hw_cau_str_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_str_ca1_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA1 register - */ -/*@{*/ -#define HW_CAU_STR_CA1_ADDR(x) ((x) + 0x88CU) - -#define HW_CAU_STR_CA1(x) (*(__I hw_cau_str_ca1_t *) HW_CAU_STR_CA1_ADDR(x)) -#define HW_CAU_STR_CA1_RD(x) (HW_CAU_STR_CA1(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA1 bitfields - */ - -/*! - * @name Register CAU_STR_CA1, field CA1[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA1_CA1 (0U) /*!< Bit position for CAU_STR_CA1_CA1. */ -#define BM_CAU_STR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA1_CA1. */ -#define BS_CAU_STR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_STR_CA1_CA1. */ - -/*! @brief Read current value of the CAU_STR_CA1_CA1 field. */ -#define BR_CAU_STR_CA1_CA1(x) (HW_CAU_STR_CA1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca2 -{ - uint32_t U; - struct _hw_cau_str_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_str_ca2_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA2 register - */ -/*@{*/ -#define HW_CAU_STR_CA2_ADDR(x) ((x) + 0x890U) - -#define HW_CAU_STR_CA2(x) (*(__I hw_cau_str_ca2_t *) HW_CAU_STR_CA2_ADDR(x)) -#define HW_CAU_STR_CA2_RD(x) (HW_CAU_STR_CA2(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA2 bitfields - */ - -/*! - * @name Register CAU_STR_CA2, field CA2[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA2_CA2 (0U) /*!< Bit position for CAU_STR_CA2_CA2. */ -#define BM_CAU_STR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA2_CA2. */ -#define BS_CAU_STR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_STR_CA2_CA2. */ - -/*! @brief Read current value of the CAU_STR_CA2_CA2 field. */ -#define BR_CAU_STR_CA2_CA2(x) (HW_CAU_STR_CA2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca3 -{ - uint32_t U; - struct _hw_cau_str_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_str_ca3_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA3 register - */ -/*@{*/ -#define HW_CAU_STR_CA3_ADDR(x) ((x) + 0x894U) - -#define HW_CAU_STR_CA3(x) (*(__I hw_cau_str_ca3_t *) HW_CAU_STR_CA3_ADDR(x)) -#define HW_CAU_STR_CA3_RD(x) (HW_CAU_STR_CA3(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA3 bitfields - */ - -/*! - * @name Register CAU_STR_CA3, field CA3[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA3_CA3 (0U) /*!< Bit position for CAU_STR_CA3_CA3. */ -#define BM_CAU_STR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA3_CA3. */ -#define BS_CAU_STR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_STR_CA3_CA3. */ - -/*! @brief Read current value of the CAU_STR_CA3_CA3 field. */ -#define BR_CAU_STR_CA3_CA3(x) (HW_CAU_STR_CA3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca4 -{ - uint32_t U; - struct _hw_cau_str_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_str_ca4_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA4 register - */ -/*@{*/ -#define HW_CAU_STR_CA4_ADDR(x) ((x) + 0x898U) - -#define HW_CAU_STR_CA4(x) (*(__I hw_cau_str_ca4_t *) HW_CAU_STR_CA4_ADDR(x)) -#define HW_CAU_STR_CA4_RD(x) (HW_CAU_STR_CA4(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA4 bitfields - */ - -/*! - * @name Register CAU_STR_CA4, field CA4[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA4_CA4 (0U) /*!< Bit position for CAU_STR_CA4_CA4. */ -#define BM_CAU_STR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA4_CA4. */ -#define BS_CAU_STR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_STR_CA4_CA4. */ - -/*! @brief Read current value of the CAU_STR_CA4_CA4 field. */ -#define BR_CAU_STR_CA4_CA4(x) (HW_CAU_STR_CA4(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca5 -{ - uint32_t U; - struct _hw_cau_str_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_str_ca5_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA5 register - */ -/*@{*/ -#define HW_CAU_STR_CA5_ADDR(x) ((x) + 0x89CU) - -#define HW_CAU_STR_CA5(x) (*(__I hw_cau_str_ca5_t *) HW_CAU_STR_CA5_ADDR(x)) -#define HW_CAU_STR_CA5_RD(x) (HW_CAU_STR_CA5(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA5 bitfields - */ - -/*! - * @name Register CAU_STR_CA5, field CA5[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA5_CA5 (0U) /*!< Bit position for CAU_STR_CA5_CA5. */ -#define BM_CAU_STR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA5_CA5. */ -#define BS_CAU_STR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_STR_CA5_CA5. */ - -/*! @brief Read current value of the CAU_STR_CA5_CA5 field. */ -#define BR_CAU_STR_CA5_CA5(x) (HW_CAU_STR_CA5(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca6 -{ - uint32_t U; - struct _hw_cau_str_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_str_ca6_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA6 register - */ -/*@{*/ -#define HW_CAU_STR_CA6_ADDR(x) ((x) + 0x8A0U) - -#define HW_CAU_STR_CA6(x) (*(__I hw_cau_str_ca6_t *) HW_CAU_STR_CA6_ADDR(x)) -#define HW_CAU_STR_CA6_RD(x) (HW_CAU_STR_CA6(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA6 bitfields - */ - -/*! - * @name Register CAU_STR_CA6, field CA6[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA6_CA6 (0U) /*!< Bit position for CAU_STR_CA6_CA6. */ -#define BM_CAU_STR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA6_CA6. */ -#define BS_CAU_STR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_STR_CA6_CA6. */ - -/*! @brief Read current value of the CAU_STR_CA6_CA6 field. */ -#define BR_CAU_STR_CA6_CA6(x) (HW_CAU_STR_CA6(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca7 -{ - uint32_t U; - struct _hw_cau_str_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_str_ca7_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA7 register - */ -/*@{*/ -#define HW_CAU_STR_CA7_ADDR(x) ((x) + 0x8A4U) - -#define HW_CAU_STR_CA7(x) (*(__I hw_cau_str_ca7_t *) HW_CAU_STR_CA7_ADDR(x)) -#define HW_CAU_STR_CA7_RD(x) (HW_CAU_STR_CA7(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA7 bitfields - */ - -/*! - * @name Register CAU_STR_CA7, field CA7[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA7_CA7 (0U) /*!< Bit position for CAU_STR_CA7_CA7. */ -#define BM_CAU_STR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA7_CA7. */ -#define BS_CAU_STR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_STR_CA7_CA7. */ - -/*! @brief Read current value of the CAU_STR_CA7_CA7 field. */ -#define BR_CAU_STR_CA7_CA7(x) (HW_CAU_STR_CA7(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_str_ca8 -{ - uint32_t U; - struct _hw_cau_str_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_str_ca8_t; - -/*! - * @name Constants and macros for entire CAU_STR_CA8 register - */ -/*@{*/ -#define HW_CAU_STR_CA8_ADDR(x) ((x) + 0x8A8U) - -#define HW_CAU_STR_CA8(x) (*(__I hw_cau_str_ca8_t *) HW_CAU_STR_CA8_ADDR(x)) -#define HW_CAU_STR_CA8_RD(x) (HW_CAU_STR_CA8(x).U) -/*@}*/ - -/* - * Constants & macros for individual CAU_STR_CA8 bitfields - */ - -/*! - * @name Register CAU_STR_CA8, field CA8[31:0] (RO) - */ -/*@{*/ -#define BP_CAU_STR_CA8_CA8 (0U) /*!< Bit position for CAU_STR_CA8_CA8. */ -#define BM_CAU_STR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA8_CA8. */ -#define BS_CAU_STR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_STR_CA8_CA8. */ - -/*! @brief Read current value of the CAU_STR_CA8_CA8 field. */ -#define BR_CAU_STR_CA8_CA8(x) (HW_CAU_STR_CA8(x).U) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CASR - Status register - Add Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CASR - Status register - Add Register command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_adr_casr -{ - uint32_t U; - struct _hw_cau_adr_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_adr_casr_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CASR register - */ -/*@{*/ -#define HW_CAU_ADR_CASR_ADDR(x) ((x) + 0x8C0U) - -#define HW_CAU_ADR_CASR(x) (*(__O hw_cau_adr_casr_t *) HW_CAU_ADR_CASR_ADDR(x)) -#define HW_CAU_ADR_CASR_WR(x, v) (HW_CAU_ADR_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CASR bitfields - */ - -/*! - * @name Register CAU_ADR_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_ADR_CASR_IC (0U) /*!< Bit position for CAU_ADR_CASR_IC. */ -#define BM_CAU_ADR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_ADR_CASR_IC. */ -#define BS_CAU_ADR_CASR_IC (1U) /*!< Bit field size in bits for CAU_ADR_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_ADR_CASR_IC. */ -#define BF_CAU_ADR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_IC) & BM_CAU_ADR_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_ADR_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_ADR_CASR_DPE (1U) /*!< Bit position for CAU_ADR_CASR_DPE. */ -#define BM_CAU_ADR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_ADR_CASR_DPE. */ -#define BS_CAU_ADR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_ADR_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_ADR_CASR_DPE. */ -#define BF_CAU_ADR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_DPE) & BM_CAU_ADR_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_ADR_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_ADR_CASR_VER (28U) /*!< Bit position for CAU_ADR_CASR_VER. */ -#define BM_CAU_ADR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_ADR_CASR_VER. */ -#define BS_CAU_ADR_CASR_VER (4U) /*!< Bit field size in bits for CAU_ADR_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_ADR_CASR_VER. */ -#define BF_CAU_ADR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_VER) & BM_CAU_ADR_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CAA - Accumulator register - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_caa -{ - uint32_t U; - struct _hw_cau_adr_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_adr_caa_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CAA register - */ -/*@{*/ -#define HW_CAU_ADR_CAA_ADDR(x) ((x) + 0x8C4U) - -#define HW_CAU_ADR_CAA(x) (*(__O hw_cau_adr_caa_t *) HW_CAU_ADR_CAA_ADDR(x)) -#define HW_CAU_ADR_CAA_WR(x, v) (HW_CAU_ADR_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CAA bitfields - */ - -/*! - * @name Register CAU_ADR_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CAA_ACC (0U) /*!< Bit position for CAU_ADR_CAA_ACC. */ -#define BM_CAU_ADR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CAA_ACC. */ -#define BS_CAU_ADR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_ADR_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_ADR_CAA_ACC. */ -#define BF_CAU_ADR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CAA_ACC) & BM_CAU_ADR_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca0 -{ - uint32_t U; - struct _hw_cau_adr_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_adr_ca0_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA0 register - */ -/*@{*/ -#define HW_CAU_ADR_CA0_ADDR(x) ((x) + 0x8C8U) - -#define HW_CAU_ADR_CA0(x) (*(__O hw_cau_adr_ca0_t *) HW_CAU_ADR_CA0_ADDR(x)) -#define HW_CAU_ADR_CA0_WR(x, v) (HW_CAU_ADR_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA0 bitfields - */ - -/*! - * @name Register CAU_ADR_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA0_CA0 (0U) /*!< Bit position for CAU_ADR_CA0_CA0. */ -#define BM_CAU_ADR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA0_CA0. */ -#define BS_CAU_ADR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_ADR_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_ADR_CA0_CA0. */ -#define BF_CAU_ADR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA0_CA0) & BM_CAU_ADR_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca1 -{ - uint32_t U; - struct _hw_cau_adr_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_adr_ca1_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA1 register - */ -/*@{*/ -#define HW_CAU_ADR_CA1_ADDR(x) ((x) + 0x8CCU) - -#define HW_CAU_ADR_CA1(x) (*(__O hw_cau_adr_ca1_t *) HW_CAU_ADR_CA1_ADDR(x)) -#define HW_CAU_ADR_CA1_WR(x, v) (HW_CAU_ADR_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA1 bitfields - */ - -/*! - * @name Register CAU_ADR_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA1_CA1 (0U) /*!< Bit position for CAU_ADR_CA1_CA1. */ -#define BM_CAU_ADR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA1_CA1. */ -#define BS_CAU_ADR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_ADR_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_ADR_CA1_CA1. */ -#define BF_CAU_ADR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA1_CA1) & BM_CAU_ADR_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca2 -{ - uint32_t U; - struct _hw_cau_adr_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_adr_ca2_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA2 register - */ -/*@{*/ -#define HW_CAU_ADR_CA2_ADDR(x) ((x) + 0x8D0U) - -#define HW_CAU_ADR_CA2(x) (*(__O hw_cau_adr_ca2_t *) HW_CAU_ADR_CA2_ADDR(x)) -#define HW_CAU_ADR_CA2_WR(x, v) (HW_CAU_ADR_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA2 bitfields - */ - -/*! - * @name Register CAU_ADR_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA2_CA2 (0U) /*!< Bit position for CAU_ADR_CA2_CA2. */ -#define BM_CAU_ADR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA2_CA2. */ -#define BS_CAU_ADR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_ADR_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_ADR_CA2_CA2. */ -#define BF_CAU_ADR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA2_CA2) & BM_CAU_ADR_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca3 -{ - uint32_t U; - struct _hw_cau_adr_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_adr_ca3_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA3 register - */ -/*@{*/ -#define HW_CAU_ADR_CA3_ADDR(x) ((x) + 0x8D4U) - -#define HW_CAU_ADR_CA3(x) (*(__O hw_cau_adr_ca3_t *) HW_CAU_ADR_CA3_ADDR(x)) -#define HW_CAU_ADR_CA3_WR(x, v) (HW_CAU_ADR_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA3 bitfields - */ - -/*! - * @name Register CAU_ADR_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA3_CA3 (0U) /*!< Bit position for CAU_ADR_CA3_CA3. */ -#define BM_CAU_ADR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA3_CA3. */ -#define BS_CAU_ADR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_ADR_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_ADR_CA3_CA3. */ -#define BF_CAU_ADR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA3_CA3) & BM_CAU_ADR_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca4 -{ - uint32_t U; - struct _hw_cau_adr_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_adr_ca4_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA4 register - */ -/*@{*/ -#define HW_CAU_ADR_CA4_ADDR(x) ((x) + 0x8D8U) - -#define HW_CAU_ADR_CA4(x) (*(__O hw_cau_adr_ca4_t *) HW_CAU_ADR_CA4_ADDR(x)) -#define HW_CAU_ADR_CA4_WR(x, v) (HW_CAU_ADR_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA4 bitfields - */ - -/*! - * @name Register CAU_ADR_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA4_CA4 (0U) /*!< Bit position for CAU_ADR_CA4_CA4. */ -#define BM_CAU_ADR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA4_CA4. */ -#define BS_CAU_ADR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_ADR_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_ADR_CA4_CA4. */ -#define BF_CAU_ADR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA4_CA4) & BM_CAU_ADR_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca5 -{ - uint32_t U; - struct _hw_cau_adr_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_adr_ca5_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA5 register - */ -/*@{*/ -#define HW_CAU_ADR_CA5_ADDR(x) ((x) + 0x8DCU) - -#define HW_CAU_ADR_CA5(x) (*(__O hw_cau_adr_ca5_t *) HW_CAU_ADR_CA5_ADDR(x)) -#define HW_CAU_ADR_CA5_WR(x, v) (HW_CAU_ADR_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA5 bitfields - */ - -/*! - * @name Register CAU_ADR_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA5_CA5 (0U) /*!< Bit position for CAU_ADR_CA5_CA5. */ -#define BM_CAU_ADR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA5_CA5. */ -#define BS_CAU_ADR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_ADR_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_ADR_CA5_CA5. */ -#define BF_CAU_ADR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA5_CA5) & BM_CAU_ADR_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca6 -{ - uint32_t U; - struct _hw_cau_adr_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_adr_ca6_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA6 register - */ -/*@{*/ -#define HW_CAU_ADR_CA6_ADDR(x) ((x) + 0x8E0U) - -#define HW_CAU_ADR_CA6(x) (*(__O hw_cau_adr_ca6_t *) HW_CAU_ADR_CA6_ADDR(x)) -#define HW_CAU_ADR_CA6_WR(x, v) (HW_CAU_ADR_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA6 bitfields - */ - -/*! - * @name Register CAU_ADR_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA6_CA6 (0U) /*!< Bit position for CAU_ADR_CA6_CA6. */ -#define BM_CAU_ADR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA6_CA6. */ -#define BS_CAU_ADR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_ADR_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_ADR_CA6_CA6. */ -#define BF_CAU_ADR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA6_CA6) & BM_CAU_ADR_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca7 -{ - uint32_t U; - struct _hw_cau_adr_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_adr_ca7_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA7 register - */ -/*@{*/ -#define HW_CAU_ADR_CA7_ADDR(x) ((x) + 0x8E4U) - -#define HW_CAU_ADR_CA7(x) (*(__O hw_cau_adr_ca7_t *) HW_CAU_ADR_CA7_ADDR(x)) -#define HW_CAU_ADR_CA7_WR(x, v) (HW_CAU_ADR_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA7 bitfields - */ - -/*! - * @name Register CAU_ADR_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA7_CA7 (0U) /*!< Bit position for CAU_ADR_CA7_CA7. */ -#define BM_CAU_ADR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA7_CA7. */ -#define BS_CAU_ADR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_ADR_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_ADR_CA7_CA7. */ -#define BF_CAU_ADR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA7_CA7) & BM_CAU_ADR_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_adr_ca8 -{ - uint32_t U; - struct _hw_cau_adr_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_adr_ca8_t; - -/*! - * @name Constants and macros for entire CAU_ADR_CA8 register - */ -/*@{*/ -#define HW_CAU_ADR_CA8_ADDR(x) ((x) + 0x8E8U) - -#define HW_CAU_ADR_CA8(x) (*(__O hw_cau_adr_ca8_t *) HW_CAU_ADR_CA8_ADDR(x)) -#define HW_CAU_ADR_CA8_WR(x, v) (HW_CAU_ADR_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ADR_CA8 bitfields - */ - -/*! - * @name Register CAU_ADR_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ADR_CA8_CA8 (0U) /*!< Bit position for CAU_ADR_CA8_CA8. */ -#define BM_CAU_ADR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA8_CA8. */ -#define BS_CAU_ADR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_ADR_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_ADR_CA8_CA8. */ -#define BF_CAU_ADR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA8_CA8) & BM_CAU_ADR_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_radr_casr -{ - uint32_t U; - struct _hw_cau_radr_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_radr_casr_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CASR register - */ -/*@{*/ -#define HW_CAU_RADR_CASR_ADDR(x) ((x) + 0x900U) - -#define HW_CAU_RADR_CASR(x) (*(__O hw_cau_radr_casr_t *) HW_CAU_RADR_CASR_ADDR(x)) -#define HW_CAU_RADR_CASR_WR(x, v) (HW_CAU_RADR_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CASR bitfields - */ - -/*! - * @name Register CAU_RADR_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_RADR_CASR_IC (0U) /*!< Bit position for CAU_RADR_CASR_IC. */ -#define BM_CAU_RADR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_RADR_CASR_IC. */ -#define BS_CAU_RADR_CASR_IC (1U) /*!< Bit field size in bits for CAU_RADR_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_RADR_CASR_IC. */ -#define BF_CAU_RADR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_IC) & BM_CAU_RADR_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_RADR_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_RADR_CASR_DPE (1U) /*!< Bit position for CAU_RADR_CASR_DPE. */ -#define BM_CAU_RADR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_RADR_CASR_DPE. */ -#define BS_CAU_RADR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_RADR_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_RADR_CASR_DPE. */ -#define BF_CAU_RADR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_DPE) & BM_CAU_RADR_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_RADR_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_RADR_CASR_VER (28U) /*!< Bit position for CAU_RADR_CASR_VER. */ -#define BM_CAU_RADR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_RADR_CASR_VER. */ -#define BS_CAU_RADR_CASR_VER (4U) /*!< Bit field size in bits for CAU_RADR_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_RADR_CASR_VER. */ -#define BF_CAU_RADR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_VER) & BM_CAU_RADR_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_caa -{ - uint32_t U; - struct _hw_cau_radr_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_radr_caa_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CAA register - */ -/*@{*/ -#define HW_CAU_RADR_CAA_ADDR(x) ((x) + 0x904U) - -#define HW_CAU_RADR_CAA(x) (*(__O hw_cau_radr_caa_t *) HW_CAU_RADR_CAA_ADDR(x)) -#define HW_CAU_RADR_CAA_WR(x, v) (HW_CAU_RADR_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CAA bitfields - */ - -/*! - * @name Register CAU_RADR_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CAA_ACC (0U) /*!< Bit position for CAU_RADR_CAA_ACC. */ -#define BM_CAU_RADR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CAA_ACC. */ -#define BS_CAU_RADR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_RADR_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_RADR_CAA_ACC. */ -#define BF_CAU_RADR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CAA_ACC) & BM_CAU_RADR_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca0 -{ - uint32_t U; - struct _hw_cau_radr_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_radr_ca0_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA0 register - */ -/*@{*/ -#define HW_CAU_RADR_CA0_ADDR(x) ((x) + 0x908U) - -#define HW_CAU_RADR_CA0(x) (*(__O hw_cau_radr_ca0_t *) HW_CAU_RADR_CA0_ADDR(x)) -#define HW_CAU_RADR_CA0_WR(x, v) (HW_CAU_RADR_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA0 bitfields - */ - -/*! - * @name Register CAU_RADR_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA0_CA0 (0U) /*!< Bit position for CAU_RADR_CA0_CA0. */ -#define BM_CAU_RADR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA0_CA0. */ -#define BS_CAU_RADR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_RADR_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_RADR_CA0_CA0. */ -#define BF_CAU_RADR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA0_CA0) & BM_CAU_RADR_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca1 -{ - uint32_t U; - struct _hw_cau_radr_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_radr_ca1_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA1 register - */ -/*@{*/ -#define HW_CAU_RADR_CA1_ADDR(x) ((x) + 0x90CU) - -#define HW_CAU_RADR_CA1(x) (*(__O hw_cau_radr_ca1_t *) HW_CAU_RADR_CA1_ADDR(x)) -#define HW_CAU_RADR_CA1_WR(x, v) (HW_CAU_RADR_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA1 bitfields - */ - -/*! - * @name Register CAU_RADR_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA1_CA1 (0U) /*!< Bit position for CAU_RADR_CA1_CA1. */ -#define BM_CAU_RADR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA1_CA1. */ -#define BS_CAU_RADR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_RADR_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_RADR_CA1_CA1. */ -#define BF_CAU_RADR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA1_CA1) & BM_CAU_RADR_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca2 -{ - uint32_t U; - struct _hw_cau_radr_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_radr_ca2_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA2 register - */ -/*@{*/ -#define HW_CAU_RADR_CA2_ADDR(x) ((x) + 0x910U) - -#define HW_CAU_RADR_CA2(x) (*(__O hw_cau_radr_ca2_t *) HW_CAU_RADR_CA2_ADDR(x)) -#define HW_CAU_RADR_CA2_WR(x, v) (HW_CAU_RADR_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA2 bitfields - */ - -/*! - * @name Register CAU_RADR_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA2_CA2 (0U) /*!< Bit position for CAU_RADR_CA2_CA2. */ -#define BM_CAU_RADR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA2_CA2. */ -#define BS_CAU_RADR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_RADR_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_RADR_CA2_CA2. */ -#define BF_CAU_RADR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA2_CA2) & BM_CAU_RADR_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca3 -{ - uint32_t U; - struct _hw_cau_radr_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_radr_ca3_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA3 register - */ -/*@{*/ -#define HW_CAU_RADR_CA3_ADDR(x) ((x) + 0x914U) - -#define HW_CAU_RADR_CA3(x) (*(__O hw_cau_radr_ca3_t *) HW_CAU_RADR_CA3_ADDR(x)) -#define HW_CAU_RADR_CA3_WR(x, v) (HW_CAU_RADR_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA3 bitfields - */ - -/*! - * @name Register CAU_RADR_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA3_CA3 (0U) /*!< Bit position for CAU_RADR_CA3_CA3. */ -#define BM_CAU_RADR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA3_CA3. */ -#define BS_CAU_RADR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_RADR_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_RADR_CA3_CA3. */ -#define BF_CAU_RADR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA3_CA3) & BM_CAU_RADR_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca4 -{ - uint32_t U; - struct _hw_cau_radr_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_radr_ca4_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA4 register - */ -/*@{*/ -#define HW_CAU_RADR_CA4_ADDR(x) ((x) + 0x918U) - -#define HW_CAU_RADR_CA4(x) (*(__O hw_cau_radr_ca4_t *) HW_CAU_RADR_CA4_ADDR(x)) -#define HW_CAU_RADR_CA4_WR(x, v) (HW_CAU_RADR_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA4 bitfields - */ - -/*! - * @name Register CAU_RADR_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA4_CA4 (0U) /*!< Bit position for CAU_RADR_CA4_CA4. */ -#define BM_CAU_RADR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA4_CA4. */ -#define BS_CAU_RADR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_RADR_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_RADR_CA4_CA4. */ -#define BF_CAU_RADR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA4_CA4) & BM_CAU_RADR_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca5 -{ - uint32_t U; - struct _hw_cau_radr_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_radr_ca5_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA5 register - */ -/*@{*/ -#define HW_CAU_RADR_CA5_ADDR(x) ((x) + 0x91CU) - -#define HW_CAU_RADR_CA5(x) (*(__O hw_cau_radr_ca5_t *) HW_CAU_RADR_CA5_ADDR(x)) -#define HW_CAU_RADR_CA5_WR(x, v) (HW_CAU_RADR_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA5 bitfields - */ - -/*! - * @name Register CAU_RADR_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA5_CA5 (0U) /*!< Bit position for CAU_RADR_CA5_CA5. */ -#define BM_CAU_RADR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA5_CA5. */ -#define BS_CAU_RADR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_RADR_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_RADR_CA5_CA5. */ -#define BF_CAU_RADR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA5_CA5) & BM_CAU_RADR_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca6 -{ - uint32_t U; - struct _hw_cau_radr_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_radr_ca6_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA6 register - */ -/*@{*/ -#define HW_CAU_RADR_CA6_ADDR(x) ((x) + 0x920U) - -#define HW_CAU_RADR_CA6(x) (*(__O hw_cau_radr_ca6_t *) HW_CAU_RADR_CA6_ADDR(x)) -#define HW_CAU_RADR_CA6_WR(x, v) (HW_CAU_RADR_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA6 bitfields - */ - -/*! - * @name Register CAU_RADR_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA6_CA6 (0U) /*!< Bit position for CAU_RADR_CA6_CA6. */ -#define BM_CAU_RADR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA6_CA6. */ -#define BS_CAU_RADR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_RADR_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_RADR_CA6_CA6. */ -#define BF_CAU_RADR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA6_CA6) & BM_CAU_RADR_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca7 -{ - uint32_t U; - struct _hw_cau_radr_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_radr_ca7_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA7 register - */ -/*@{*/ -#define HW_CAU_RADR_CA7_ADDR(x) ((x) + 0x924U) - -#define HW_CAU_RADR_CA7(x) (*(__O hw_cau_radr_ca7_t *) HW_CAU_RADR_CA7_ADDR(x)) -#define HW_CAU_RADR_CA7_WR(x, v) (HW_CAU_RADR_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA7 bitfields - */ - -/*! - * @name Register CAU_RADR_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA7_CA7 (0U) /*!< Bit position for CAU_RADR_CA7_CA7. */ -#define BM_CAU_RADR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA7_CA7. */ -#define BS_CAU_RADR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_RADR_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_RADR_CA7_CA7. */ -#define BF_CAU_RADR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA7_CA7) & BM_CAU_RADR_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command - ******************************************************************************/ - -/*! - * @brief HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_radr_ca8 -{ - uint32_t U; - struct _hw_cau_radr_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_radr_ca8_t; - -/*! - * @name Constants and macros for entire CAU_RADR_CA8 register - */ -/*@{*/ -#define HW_CAU_RADR_CA8_ADDR(x) ((x) + 0x928U) - -#define HW_CAU_RADR_CA8(x) (*(__O hw_cau_radr_ca8_t *) HW_CAU_RADR_CA8_ADDR(x)) -#define HW_CAU_RADR_CA8_WR(x, v) (HW_CAU_RADR_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_RADR_CA8 bitfields - */ - -/*! - * @name Register CAU_RADR_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_RADR_CA8_CA8 (0U) /*!< Bit position for CAU_RADR_CA8_CA8. */ -#define BM_CAU_RADR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA8_CA8. */ -#define BS_CAU_RADR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_RADR_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_RADR_CA8_CA8. */ -#define BF_CAU_RADR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA8_CA8) & BM_CAU_RADR_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CASR - Status register - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CASR - Status register - Exclusive Or command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_xor_casr -{ - uint32_t U; - struct _hw_cau_xor_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_xor_casr_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CASR register - */ -/*@{*/ -#define HW_CAU_XOR_CASR_ADDR(x) ((x) + 0x980U) - -#define HW_CAU_XOR_CASR(x) (*(__O hw_cau_xor_casr_t *) HW_CAU_XOR_CASR_ADDR(x)) -#define HW_CAU_XOR_CASR_WR(x, v) (HW_CAU_XOR_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CASR bitfields - */ - -/*! - * @name Register CAU_XOR_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_XOR_CASR_IC (0U) /*!< Bit position for CAU_XOR_CASR_IC. */ -#define BM_CAU_XOR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_XOR_CASR_IC. */ -#define BS_CAU_XOR_CASR_IC (1U) /*!< Bit field size in bits for CAU_XOR_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_XOR_CASR_IC. */ -#define BF_CAU_XOR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_IC) & BM_CAU_XOR_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_XOR_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_XOR_CASR_DPE (1U) /*!< Bit position for CAU_XOR_CASR_DPE. */ -#define BM_CAU_XOR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_XOR_CASR_DPE. */ -#define BS_CAU_XOR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_XOR_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_XOR_CASR_DPE. */ -#define BF_CAU_XOR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_DPE) & BM_CAU_XOR_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_XOR_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_XOR_CASR_VER (28U) /*!< Bit position for CAU_XOR_CASR_VER. */ -#define BM_CAU_XOR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_XOR_CASR_VER. */ -#define BS_CAU_XOR_CASR_VER (4U) /*!< Bit field size in bits for CAU_XOR_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_XOR_CASR_VER. */ -#define BF_CAU_XOR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_VER) & BM_CAU_XOR_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_caa -{ - uint32_t U; - struct _hw_cau_xor_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_xor_caa_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CAA register - */ -/*@{*/ -#define HW_CAU_XOR_CAA_ADDR(x) ((x) + 0x984U) - -#define HW_CAU_XOR_CAA(x) (*(__O hw_cau_xor_caa_t *) HW_CAU_XOR_CAA_ADDR(x)) -#define HW_CAU_XOR_CAA_WR(x, v) (HW_CAU_XOR_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CAA bitfields - */ - -/*! - * @name Register CAU_XOR_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CAA_ACC (0U) /*!< Bit position for CAU_XOR_CAA_ACC. */ -#define BM_CAU_XOR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CAA_ACC. */ -#define BS_CAU_XOR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_XOR_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_XOR_CAA_ACC. */ -#define BF_CAU_XOR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CAA_ACC) & BM_CAU_XOR_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca0 -{ - uint32_t U; - struct _hw_cau_xor_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_xor_ca0_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA0 register - */ -/*@{*/ -#define HW_CAU_XOR_CA0_ADDR(x) ((x) + 0x988U) - -#define HW_CAU_XOR_CA0(x) (*(__O hw_cau_xor_ca0_t *) HW_CAU_XOR_CA0_ADDR(x)) -#define HW_CAU_XOR_CA0_WR(x, v) (HW_CAU_XOR_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA0 bitfields - */ - -/*! - * @name Register CAU_XOR_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA0_CA0 (0U) /*!< Bit position for CAU_XOR_CA0_CA0. */ -#define BM_CAU_XOR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA0_CA0. */ -#define BS_CAU_XOR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_XOR_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_XOR_CA0_CA0. */ -#define BF_CAU_XOR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA0_CA0) & BM_CAU_XOR_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca1 -{ - uint32_t U; - struct _hw_cau_xor_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_xor_ca1_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA1 register - */ -/*@{*/ -#define HW_CAU_XOR_CA1_ADDR(x) ((x) + 0x98CU) - -#define HW_CAU_XOR_CA1(x) (*(__O hw_cau_xor_ca1_t *) HW_CAU_XOR_CA1_ADDR(x)) -#define HW_CAU_XOR_CA1_WR(x, v) (HW_CAU_XOR_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA1 bitfields - */ - -/*! - * @name Register CAU_XOR_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA1_CA1 (0U) /*!< Bit position for CAU_XOR_CA1_CA1. */ -#define BM_CAU_XOR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA1_CA1. */ -#define BS_CAU_XOR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_XOR_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_XOR_CA1_CA1. */ -#define BF_CAU_XOR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA1_CA1) & BM_CAU_XOR_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca2 -{ - uint32_t U; - struct _hw_cau_xor_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_xor_ca2_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA2 register - */ -/*@{*/ -#define HW_CAU_XOR_CA2_ADDR(x) ((x) + 0x990U) - -#define HW_CAU_XOR_CA2(x) (*(__O hw_cau_xor_ca2_t *) HW_CAU_XOR_CA2_ADDR(x)) -#define HW_CAU_XOR_CA2_WR(x, v) (HW_CAU_XOR_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA2 bitfields - */ - -/*! - * @name Register CAU_XOR_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA2_CA2 (0U) /*!< Bit position for CAU_XOR_CA2_CA2. */ -#define BM_CAU_XOR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA2_CA2. */ -#define BS_CAU_XOR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_XOR_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_XOR_CA2_CA2. */ -#define BF_CAU_XOR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA2_CA2) & BM_CAU_XOR_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca3 -{ - uint32_t U; - struct _hw_cau_xor_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_xor_ca3_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA3 register - */ -/*@{*/ -#define HW_CAU_XOR_CA3_ADDR(x) ((x) + 0x994U) - -#define HW_CAU_XOR_CA3(x) (*(__O hw_cau_xor_ca3_t *) HW_CAU_XOR_CA3_ADDR(x)) -#define HW_CAU_XOR_CA3_WR(x, v) (HW_CAU_XOR_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA3 bitfields - */ - -/*! - * @name Register CAU_XOR_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA3_CA3 (0U) /*!< Bit position for CAU_XOR_CA3_CA3. */ -#define BM_CAU_XOR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA3_CA3. */ -#define BS_CAU_XOR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_XOR_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_XOR_CA3_CA3. */ -#define BF_CAU_XOR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA3_CA3) & BM_CAU_XOR_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca4 -{ - uint32_t U; - struct _hw_cau_xor_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_xor_ca4_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA4 register - */ -/*@{*/ -#define HW_CAU_XOR_CA4_ADDR(x) ((x) + 0x998U) - -#define HW_CAU_XOR_CA4(x) (*(__O hw_cau_xor_ca4_t *) HW_CAU_XOR_CA4_ADDR(x)) -#define HW_CAU_XOR_CA4_WR(x, v) (HW_CAU_XOR_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA4 bitfields - */ - -/*! - * @name Register CAU_XOR_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA4_CA4 (0U) /*!< Bit position for CAU_XOR_CA4_CA4. */ -#define BM_CAU_XOR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA4_CA4. */ -#define BS_CAU_XOR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_XOR_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_XOR_CA4_CA4. */ -#define BF_CAU_XOR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA4_CA4) & BM_CAU_XOR_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca5 -{ - uint32_t U; - struct _hw_cau_xor_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_xor_ca5_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA5 register - */ -/*@{*/ -#define HW_CAU_XOR_CA5_ADDR(x) ((x) + 0x99CU) - -#define HW_CAU_XOR_CA5(x) (*(__O hw_cau_xor_ca5_t *) HW_CAU_XOR_CA5_ADDR(x)) -#define HW_CAU_XOR_CA5_WR(x, v) (HW_CAU_XOR_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA5 bitfields - */ - -/*! - * @name Register CAU_XOR_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA5_CA5 (0U) /*!< Bit position for CAU_XOR_CA5_CA5. */ -#define BM_CAU_XOR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA5_CA5. */ -#define BS_CAU_XOR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_XOR_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_XOR_CA5_CA5. */ -#define BF_CAU_XOR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA5_CA5) & BM_CAU_XOR_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca6 -{ - uint32_t U; - struct _hw_cau_xor_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_xor_ca6_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA6 register - */ -/*@{*/ -#define HW_CAU_XOR_CA6_ADDR(x) ((x) + 0x9A0U) - -#define HW_CAU_XOR_CA6(x) (*(__O hw_cau_xor_ca6_t *) HW_CAU_XOR_CA6_ADDR(x)) -#define HW_CAU_XOR_CA6_WR(x, v) (HW_CAU_XOR_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA6 bitfields - */ - -/*! - * @name Register CAU_XOR_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA6_CA6 (0U) /*!< Bit position for CAU_XOR_CA6_CA6. */ -#define BM_CAU_XOR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA6_CA6. */ -#define BS_CAU_XOR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_XOR_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_XOR_CA6_CA6. */ -#define BF_CAU_XOR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA6_CA6) & BM_CAU_XOR_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca7 -{ - uint32_t U; - struct _hw_cau_xor_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_xor_ca7_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA7 register - */ -/*@{*/ -#define HW_CAU_XOR_CA7_ADDR(x) ((x) + 0x9A4U) - -#define HW_CAU_XOR_CA7(x) (*(__O hw_cau_xor_ca7_t *) HW_CAU_XOR_CA7_ADDR(x)) -#define HW_CAU_XOR_CA7_WR(x, v) (HW_CAU_XOR_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA7 bitfields - */ - -/*! - * @name Register CAU_XOR_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA7_CA7 (0U) /*!< Bit position for CAU_XOR_CA7_CA7. */ -#define BM_CAU_XOR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA7_CA7. */ -#define BS_CAU_XOR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_XOR_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_XOR_CA7_CA7. */ -#define BF_CAU_XOR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA7_CA7) & BM_CAU_XOR_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command - ******************************************************************************/ - -/*! - * @brief HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_xor_ca8 -{ - uint32_t U; - struct _hw_cau_xor_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_xor_ca8_t; - -/*! - * @name Constants and macros for entire CAU_XOR_CA8 register - */ -/*@{*/ -#define HW_CAU_XOR_CA8_ADDR(x) ((x) + 0x9A8U) - -#define HW_CAU_XOR_CA8(x) (*(__O hw_cau_xor_ca8_t *) HW_CAU_XOR_CA8_ADDR(x)) -#define HW_CAU_XOR_CA8_WR(x, v) (HW_CAU_XOR_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_XOR_CA8 bitfields - */ - -/*! - * @name Register CAU_XOR_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_XOR_CA8_CA8 (0U) /*!< Bit position for CAU_XOR_CA8_CA8. */ -#define BM_CAU_XOR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA8_CA8. */ -#define BS_CAU_XOR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_XOR_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_XOR_CA8_CA8. */ -#define BF_CAU_XOR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA8_CA8) & BM_CAU_XOR_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CASR - Status register - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CASR - Status register - Rotate Left command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_rotl_casr -{ - uint32_t U; - struct _hw_cau_rotl_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_rotl_casr_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CASR register - */ -/*@{*/ -#define HW_CAU_ROTL_CASR_ADDR(x) ((x) + 0x9C0U) - -#define HW_CAU_ROTL_CASR(x) (*(__O hw_cau_rotl_casr_t *) HW_CAU_ROTL_CASR_ADDR(x)) -#define HW_CAU_ROTL_CASR_WR(x, v) (HW_CAU_ROTL_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CASR bitfields - */ - -/*! - * @name Register CAU_ROTL_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_ROTL_CASR_IC (0U) /*!< Bit position for CAU_ROTL_CASR_IC. */ -#define BM_CAU_ROTL_CASR_IC (0x00000001U) /*!< Bit mask for CAU_ROTL_CASR_IC. */ -#define BS_CAU_ROTL_CASR_IC (1U) /*!< Bit field size in bits for CAU_ROTL_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_ROTL_CASR_IC. */ -#define BF_CAU_ROTL_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_IC) & BM_CAU_ROTL_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_ROTL_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_ROTL_CASR_DPE (1U) /*!< Bit position for CAU_ROTL_CASR_DPE. */ -#define BM_CAU_ROTL_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_ROTL_CASR_DPE. */ -#define BS_CAU_ROTL_CASR_DPE (1U) /*!< Bit field size in bits for CAU_ROTL_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_ROTL_CASR_DPE. */ -#define BF_CAU_ROTL_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_DPE) & BM_CAU_ROTL_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_ROTL_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_ROTL_CASR_VER (28U) /*!< Bit position for CAU_ROTL_CASR_VER. */ -#define BM_CAU_ROTL_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_ROTL_CASR_VER. */ -#define BS_CAU_ROTL_CASR_VER (4U) /*!< Bit field size in bits for CAU_ROTL_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_ROTL_CASR_VER. */ -#define BF_CAU_ROTL_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_VER) & BM_CAU_ROTL_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_caa -{ - uint32_t U; - struct _hw_cau_rotl_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_rotl_caa_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CAA register - */ -/*@{*/ -#define HW_CAU_ROTL_CAA_ADDR(x) ((x) + 0x9C4U) - -#define HW_CAU_ROTL_CAA(x) (*(__O hw_cau_rotl_caa_t *) HW_CAU_ROTL_CAA_ADDR(x)) -#define HW_CAU_ROTL_CAA_WR(x, v) (HW_CAU_ROTL_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CAA bitfields - */ - -/*! - * @name Register CAU_ROTL_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CAA_ACC (0U) /*!< Bit position for CAU_ROTL_CAA_ACC. */ -#define BM_CAU_ROTL_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CAA_ACC. */ -#define BS_CAU_ROTL_CAA_ACC (32U) /*!< Bit field size in bits for CAU_ROTL_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_ROTL_CAA_ACC. */ -#define BF_CAU_ROTL_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CAA_ACC) & BM_CAU_ROTL_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca0 -{ - uint32_t U; - struct _hw_cau_rotl_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_rotl_ca0_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA0 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA0_ADDR(x) ((x) + 0x9C8U) - -#define HW_CAU_ROTL_CA0(x) (*(__O hw_cau_rotl_ca0_t *) HW_CAU_ROTL_CA0_ADDR(x)) -#define HW_CAU_ROTL_CA0_WR(x, v) (HW_CAU_ROTL_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA0 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA0_CA0 (0U) /*!< Bit position for CAU_ROTL_CA0_CA0. */ -#define BM_CAU_ROTL_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA0_CA0. */ -#define BS_CAU_ROTL_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_ROTL_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA0_CA0. */ -#define BF_CAU_ROTL_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA0_CA0) & BM_CAU_ROTL_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca1 -{ - uint32_t U; - struct _hw_cau_rotl_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_rotl_ca1_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA1 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA1_ADDR(x) ((x) + 0x9CCU) - -#define HW_CAU_ROTL_CA1(x) (*(__O hw_cau_rotl_ca1_t *) HW_CAU_ROTL_CA1_ADDR(x)) -#define HW_CAU_ROTL_CA1_WR(x, v) (HW_CAU_ROTL_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA1 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA1_CA1 (0U) /*!< Bit position for CAU_ROTL_CA1_CA1. */ -#define BM_CAU_ROTL_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA1_CA1. */ -#define BS_CAU_ROTL_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_ROTL_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA1_CA1. */ -#define BF_CAU_ROTL_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA1_CA1) & BM_CAU_ROTL_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca2 -{ - uint32_t U; - struct _hw_cau_rotl_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_rotl_ca2_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA2 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA2_ADDR(x) ((x) + 0x9D0U) - -#define HW_CAU_ROTL_CA2(x) (*(__O hw_cau_rotl_ca2_t *) HW_CAU_ROTL_CA2_ADDR(x)) -#define HW_CAU_ROTL_CA2_WR(x, v) (HW_CAU_ROTL_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA2 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA2_CA2 (0U) /*!< Bit position for CAU_ROTL_CA2_CA2. */ -#define BM_CAU_ROTL_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA2_CA2. */ -#define BS_CAU_ROTL_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_ROTL_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA2_CA2. */ -#define BF_CAU_ROTL_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA2_CA2) & BM_CAU_ROTL_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca3 -{ - uint32_t U; - struct _hw_cau_rotl_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_rotl_ca3_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA3 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA3_ADDR(x) ((x) + 0x9D4U) - -#define HW_CAU_ROTL_CA3(x) (*(__O hw_cau_rotl_ca3_t *) HW_CAU_ROTL_CA3_ADDR(x)) -#define HW_CAU_ROTL_CA3_WR(x, v) (HW_CAU_ROTL_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA3 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA3_CA3 (0U) /*!< Bit position for CAU_ROTL_CA3_CA3. */ -#define BM_CAU_ROTL_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA3_CA3. */ -#define BS_CAU_ROTL_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_ROTL_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA3_CA3. */ -#define BF_CAU_ROTL_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA3_CA3) & BM_CAU_ROTL_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca4 -{ - uint32_t U; - struct _hw_cau_rotl_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_rotl_ca4_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA4 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA4_ADDR(x) ((x) + 0x9D8U) - -#define HW_CAU_ROTL_CA4(x) (*(__O hw_cau_rotl_ca4_t *) HW_CAU_ROTL_CA4_ADDR(x)) -#define HW_CAU_ROTL_CA4_WR(x, v) (HW_CAU_ROTL_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA4 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA4_CA4 (0U) /*!< Bit position for CAU_ROTL_CA4_CA4. */ -#define BM_CAU_ROTL_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA4_CA4. */ -#define BS_CAU_ROTL_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_ROTL_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA4_CA4. */ -#define BF_CAU_ROTL_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA4_CA4) & BM_CAU_ROTL_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca5 -{ - uint32_t U; - struct _hw_cau_rotl_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_rotl_ca5_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA5 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA5_ADDR(x) ((x) + 0x9DCU) - -#define HW_CAU_ROTL_CA5(x) (*(__O hw_cau_rotl_ca5_t *) HW_CAU_ROTL_CA5_ADDR(x)) -#define HW_CAU_ROTL_CA5_WR(x, v) (HW_CAU_ROTL_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA5 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA5_CA5 (0U) /*!< Bit position for CAU_ROTL_CA5_CA5. */ -#define BM_CAU_ROTL_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA5_CA5. */ -#define BS_CAU_ROTL_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_ROTL_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA5_CA5. */ -#define BF_CAU_ROTL_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA5_CA5) & BM_CAU_ROTL_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca6 -{ - uint32_t U; - struct _hw_cau_rotl_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_rotl_ca6_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA6 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA6_ADDR(x) ((x) + 0x9E0U) - -#define HW_CAU_ROTL_CA6(x) (*(__O hw_cau_rotl_ca6_t *) HW_CAU_ROTL_CA6_ADDR(x)) -#define HW_CAU_ROTL_CA6_WR(x, v) (HW_CAU_ROTL_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA6 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA6_CA6 (0U) /*!< Bit position for CAU_ROTL_CA6_CA6. */ -#define BM_CAU_ROTL_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA6_CA6. */ -#define BS_CAU_ROTL_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_ROTL_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA6_CA6. */ -#define BF_CAU_ROTL_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA6_CA6) & BM_CAU_ROTL_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca7 -{ - uint32_t U; - struct _hw_cau_rotl_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_rotl_ca7_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA7 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA7_ADDR(x) ((x) + 0x9E4U) - -#define HW_CAU_ROTL_CA7(x) (*(__O hw_cau_rotl_ca7_t *) HW_CAU_ROTL_CA7_ADDR(x)) -#define HW_CAU_ROTL_CA7_WR(x, v) (HW_CAU_ROTL_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA7 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA7_CA7 (0U) /*!< Bit position for CAU_ROTL_CA7_CA7. */ -#define BM_CAU_ROTL_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA7_CA7. */ -#define BS_CAU_ROTL_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_ROTL_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA7_CA7. */ -#define BF_CAU_ROTL_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA7_CA7) & BM_CAU_ROTL_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command - ******************************************************************************/ - -/*! - * @brief HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_rotl_ca8 -{ - uint32_t U; - struct _hw_cau_rotl_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_rotl_ca8_t; - -/*! - * @name Constants and macros for entire CAU_ROTL_CA8 register - */ -/*@{*/ -#define HW_CAU_ROTL_CA8_ADDR(x) ((x) + 0x9E8U) - -#define HW_CAU_ROTL_CA8(x) (*(__O hw_cau_rotl_ca8_t *) HW_CAU_ROTL_CA8_ADDR(x)) -#define HW_CAU_ROTL_CA8_WR(x, v) (HW_CAU_ROTL_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_ROTL_CA8 bitfields - */ - -/*! - * @name Register CAU_ROTL_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_ROTL_CA8_CA8 (0U) /*!< Bit position for CAU_ROTL_CA8_CA8. */ -#define BM_CAU_ROTL_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA8_CA8. */ -#define BS_CAU_ROTL_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_ROTL_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_ROTL_CA8_CA8. */ -#define BF_CAU_ROTL_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA8_CA8) & BM_CAU_ROTL_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CASR - Status register - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CASR - Status register - AES Column Operation command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_aesc_casr -{ - uint32_t U; - struct _hw_cau_aesc_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_aesc_casr_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CASR register - */ -/*@{*/ -#define HW_CAU_AESC_CASR_ADDR(x) ((x) + 0xB00U) - -#define HW_CAU_AESC_CASR(x) (*(__O hw_cau_aesc_casr_t *) HW_CAU_AESC_CASR_ADDR(x)) -#define HW_CAU_AESC_CASR_WR(x, v) (HW_CAU_AESC_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CASR bitfields - */ - -/*! - * @name Register CAU_AESC_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_AESC_CASR_IC (0U) /*!< Bit position for CAU_AESC_CASR_IC. */ -#define BM_CAU_AESC_CASR_IC (0x00000001U) /*!< Bit mask for CAU_AESC_CASR_IC. */ -#define BS_CAU_AESC_CASR_IC (1U) /*!< Bit field size in bits for CAU_AESC_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_AESC_CASR_IC. */ -#define BF_CAU_AESC_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_IC) & BM_CAU_AESC_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_AESC_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_AESC_CASR_DPE (1U) /*!< Bit position for CAU_AESC_CASR_DPE. */ -#define BM_CAU_AESC_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_AESC_CASR_DPE. */ -#define BS_CAU_AESC_CASR_DPE (1U) /*!< Bit field size in bits for CAU_AESC_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_AESC_CASR_DPE. */ -#define BF_CAU_AESC_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_DPE) & BM_CAU_AESC_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_AESC_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_AESC_CASR_VER (28U) /*!< Bit position for CAU_AESC_CASR_VER. */ -#define BM_CAU_AESC_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_AESC_CASR_VER. */ -#define BS_CAU_AESC_CASR_VER (4U) /*!< Bit field size in bits for CAU_AESC_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_AESC_CASR_VER. */ -#define BF_CAU_AESC_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_VER) & BM_CAU_AESC_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_caa -{ - uint32_t U; - struct _hw_cau_aesc_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_aesc_caa_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CAA register - */ -/*@{*/ -#define HW_CAU_AESC_CAA_ADDR(x) ((x) + 0xB04U) - -#define HW_CAU_AESC_CAA(x) (*(__O hw_cau_aesc_caa_t *) HW_CAU_AESC_CAA_ADDR(x)) -#define HW_CAU_AESC_CAA_WR(x, v) (HW_CAU_AESC_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CAA bitfields - */ - -/*! - * @name Register CAU_AESC_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CAA_ACC (0U) /*!< Bit position for CAU_AESC_CAA_ACC. */ -#define BM_CAU_AESC_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CAA_ACC. */ -#define BS_CAU_AESC_CAA_ACC (32U) /*!< Bit field size in bits for CAU_AESC_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_AESC_CAA_ACC. */ -#define BF_CAU_AESC_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CAA_ACC) & BM_CAU_AESC_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca0 -{ - uint32_t U; - struct _hw_cau_aesc_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_aesc_ca0_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA0 register - */ -/*@{*/ -#define HW_CAU_AESC_CA0_ADDR(x) ((x) + 0xB08U) - -#define HW_CAU_AESC_CA0(x) (*(__O hw_cau_aesc_ca0_t *) HW_CAU_AESC_CA0_ADDR(x)) -#define HW_CAU_AESC_CA0_WR(x, v) (HW_CAU_AESC_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA0 bitfields - */ - -/*! - * @name Register CAU_AESC_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA0_CA0 (0U) /*!< Bit position for CAU_AESC_CA0_CA0. */ -#define BM_CAU_AESC_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA0_CA0. */ -#define BS_CAU_AESC_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_AESC_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_AESC_CA0_CA0. */ -#define BF_CAU_AESC_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA0_CA0) & BM_CAU_AESC_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca1 -{ - uint32_t U; - struct _hw_cau_aesc_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_aesc_ca1_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA1 register - */ -/*@{*/ -#define HW_CAU_AESC_CA1_ADDR(x) ((x) + 0xB0CU) - -#define HW_CAU_AESC_CA1(x) (*(__O hw_cau_aesc_ca1_t *) HW_CAU_AESC_CA1_ADDR(x)) -#define HW_CAU_AESC_CA1_WR(x, v) (HW_CAU_AESC_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA1 bitfields - */ - -/*! - * @name Register CAU_AESC_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA1_CA1 (0U) /*!< Bit position for CAU_AESC_CA1_CA1. */ -#define BM_CAU_AESC_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA1_CA1. */ -#define BS_CAU_AESC_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_AESC_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_AESC_CA1_CA1. */ -#define BF_CAU_AESC_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA1_CA1) & BM_CAU_AESC_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca2 -{ - uint32_t U; - struct _hw_cau_aesc_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_aesc_ca2_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA2 register - */ -/*@{*/ -#define HW_CAU_AESC_CA2_ADDR(x) ((x) + 0xB10U) - -#define HW_CAU_AESC_CA2(x) (*(__O hw_cau_aesc_ca2_t *) HW_CAU_AESC_CA2_ADDR(x)) -#define HW_CAU_AESC_CA2_WR(x, v) (HW_CAU_AESC_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA2 bitfields - */ - -/*! - * @name Register CAU_AESC_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA2_CA2 (0U) /*!< Bit position for CAU_AESC_CA2_CA2. */ -#define BM_CAU_AESC_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA2_CA2. */ -#define BS_CAU_AESC_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_AESC_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_AESC_CA2_CA2. */ -#define BF_CAU_AESC_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA2_CA2) & BM_CAU_AESC_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca3 -{ - uint32_t U; - struct _hw_cau_aesc_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_aesc_ca3_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA3 register - */ -/*@{*/ -#define HW_CAU_AESC_CA3_ADDR(x) ((x) + 0xB14U) - -#define HW_CAU_AESC_CA3(x) (*(__O hw_cau_aesc_ca3_t *) HW_CAU_AESC_CA3_ADDR(x)) -#define HW_CAU_AESC_CA3_WR(x, v) (HW_CAU_AESC_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA3 bitfields - */ - -/*! - * @name Register CAU_AESC_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA3_CA3 (0U) /*!< Bit position for CAU_AESC_CA3_CA3. */ -#define BM_CAU_AESC_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA3_CA3. */ -#define BS_CAU_AESC_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_AESC_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_AESC_CA3_CA3. */ -#define BF_CAU_AESC_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA3_CA3) & BM_CAU_AESC_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca4 -{ - uint32_t U; - struct _hw_cau_aesc_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_aesc_ca4_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA4 register - */ -/*@{*/ -#define HW_CAU_AESC_CA4_ADDR(x) ((x) + 0xB18U) - -#define HW_CAU_AESC_CA4(x) (*(__O hw_cau_aesc_ca4_t *) HW_CAU_AESC_CA4_ADDR(x)) -#define HW_CAU_AESC_CA4_WR(x, v) (HW_CAU_AESC_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA4 bitfields - */ - -/*! - * @name Register CAU_AESC_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA4_CA4 (0U) /*!< Bit position for CAU_AESC_CA4_CA4. */ -#define BM_CAU_AESC_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA4_CA4. */ -#define BS_CAU_AESC_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_AESC_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_AESC_CA4_CA4. */ -#define BF_CAU_AESC_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA4_CA4) & BM_CAU_AESC_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca5 -{ - uint32_t U; - struct _hw_cau_aesc_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_aesc_ca5_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA5 register - */ -/*@{*/ -#define HW_CAU_AESC_CA5_ADDR(x) ((x) + 0xB1CU) - -#define HW_CAU_AESC_CA5(x) (*(__O hw_cau_aesc_ca5_t *) HW_CAU_AESC_CA5_ADDR(x)) -#define HW_CAU_AESC_CA5_WR(x, v) (HW_CAU_AESC_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA5 bitfields - */ - -/*! - * @name Register CAU_AESC_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA5_CA5 (0U) /*!< Bit position for CAU_AESC_CA5_CA5. */ -#define BM_CAU_AESC_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA5_CA5. */ -#define BS_CAU_AESC_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_AESC_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_AESC_CA5_CA5. */ -#define BF_CAU_AESC_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA5_CA5) & BM_CAU_AESC_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca6 -{ - uint32_t U; - struct _hw_cau_aesc_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_aesc_ca6_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA6 register - */ -/*@{*/ -#define HW_CAU_AESC_CA6_ADDR(x) ((x) + 0xB20U) - -#define HW_CAU_AESC_CA6(x) (*(__O hw_cau_aesc_ca6_t *) HW_CAU_AESC_CA6_ADDR(x)) -#define HW_CAU_AESC_CA6_WR(x, v) (HW_CAU_AESC_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA6 bitfields - */ - -/*! - * @name Register CAU_AESC_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA6_CA6 (0U) /*!< Bit position for CAU_AESC_CA6_CA6. */ -#define BM_CAU_AESC_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA6_CA6. */ -#define BS_CAU_AESC_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_AESC_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_AESC_CA6_CA6. */ -#define BF_CAU_AESC_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA6_CA6) & BM_CAU_AESC_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca7 -{ - uint32_t U; - struct _hw_cau_aesc_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_aesc_ca7_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA7 register - */ -/*@{*/ -#define HW_CAU_AESC_CA7_ADDR(x) ((x) + 0xB24U) - -#define HW_CAU_AESC_CA7(x) (*(__O hw_cau_aesc_ca7_t *) HW_CAU_AESC_CA7_ADDR(x)) -#define HW_CAU_AESC_CA7_WR(x, v) (HW_CAU_AESC_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA7 bitfields - */ - -/*! - * @name Register CAU_AESC_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA7_CA7 (0U) /*!< Bit position for CAU_AESC_CA7_CA7. */ -#define BM_CAU_AESC_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA7_CA7. */ -#define BS_CAU_AESC_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_AESC_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_AESC_CA7_CA7. */ -#define BF_CAU_AESC_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA7_CA7) & BM_CAU_AESC_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesc_ca8 -{ - uint32_t U; - struct _hw_cau_aesc_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_aesc_ca8_t; - -/*! - * @name Constants and macros for entire CAU_AESC_CA8 register - */ -/*@{*/ -#define HW_CAU_AESC_CA8_ADDR(x) ((x) + 0xB28U) - -#define HW_CAU_AESC_CA8(x) (*(__O hw_cau_aesc_ca8_t *) HW_CAU_AESC_CA8_ADDR(x)) -#define HW_CAU_AESC_CA8_WR(x, v) (HW_CAU_AESC_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESC_CA8 bitfields - */ - -/*! - * @name Register CAU_AESC_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESC_CA8_CA8 (0U) /*!< Bit position for CAU_AESC_CA8_CA8. */ -#define BM_CAU_AESC_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA8_CA8. */ -#define BS_CAU_AESC_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_AESC_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_AESC_CA8_CA8. */ -#define BF_CAU_AESC_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA8_CA8) & BM_CAU_AESC_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO) - * - * Reset value: 0x20000000U - */ -typedef union _hw_cau_aesic_casr -{ - uint32_t U; - struct _hw_cau_aesic_casr_bitfields - { - uint32_t IC : 1; /*!< [0] */ - uint32_t DPE : 1; /*!< [1] */ - uint32_t RESERVED0 : 26; /*!< [27:2] */ - uint32_t VER : 4; /*!< [31:28] CAU version */ - } B; -} hw_cau_aesic_casr_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CASR register - */ -/*@{*/ -#define HW_CAU_AESIC_CASR_ADDR(x) ((x) + 0xB40U) - -#define HW_CAU_AESIC_CASR(x) (*(__O hw_cau_aesic_casr_t *) HW_CAU_AESIC_CASR_ADDR(x)) -#define HW_CAU_AESIC_CASR_WR(x, v) (HW_CAU_AESIC_CASR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CASR bitfields - */ - -/*! - * @name Register CAU_AESIC_CASR, field IC[0] (WO) - * - * Values: - * - 0 - No illegal commands issued - * - 1 - Illegal command issued - */ -/*@{*/ -#define BP_CAU_AESIC_CASR_IC (0U) /*!< Bit position for CAU_AESIC_CASR_IC. */ -#define BM_CAU_AESIC_CASR_IC (0x00000001U) /*!< Bit mask for CAU_AESIC_CASR_IC. */ -#define BS_CAU_AESIC_CASR_IC (1U) /*!< Bit field size in bits for CAU_AESIC_CASR_IC. */ - -/*! @brief Format value for bitfield CAU_AESIC_CASR_IC. */ -#define BF_CAU_AESIC_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_IC) & BM_CAU_AESIC_CASR_IC) -/*@}*/ - -/*! - * @name Register CAU_AESIC_CASR, field DPE[1] (WO) - * - * Values: - * - 0 - No error detected - * - 1 - DES key parity error detected - */ -/*@{*/ -#define BP_CAU_AESIC_CASR_DPE (1U) /*!< Bit position for CAU_AESIC_CASR_DPE. */ -#define BM_CAU_AESIC_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_AESIC_CASR_DPE. */ -#define BS_CAU_AESIC_CASR_DPE (1U) /*!< Bit field size in bits for CAU_AESIC_CASR_DPE. */ - -/*! @brief Format value for bitfield CAU_AESIC_CASR_DPE. */ -#define BF_CAU_AESIC_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_DPE) & BM_CAU_AESIC_CASR_DPE) -/*@}*/ - -/*! - * @name Register CAU_AESIC_CASR, field VER[31:28] (WO) - * - * Values: - * - 0001 - Initial CAU version - * - 0010 - Second version, added support for SHA-256 algorithm.(This is the - * value on this device) - */ -/*@{*/ -#define BP_CAU_AESIC_CASR_VER (28U) /*!< Bit position for CAU_AESIC_CASR_VER. */ -#define BM_CAU_AESIC_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_AESIC_CASR_VER. */ -#define BS_CAU_AESIC_CASR_VER (4U) /*!< Bit field size in bits for CAU_AESIC_CASR_VER. */ - -/*! @brief Format value for bitfield CAU_AESIC_CASR_VER. */ -#define BF_CAU_AESIC_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_VER) & BM_CAU_AESIC_CASR_VER) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_caa -{ - uint32_t U; - struct _hw_cau_aesic_caa_bitfields - { - uint32_t ACC : 32; /*!< [31:0] ACC */ - } B; -} hw_cau_aesic_caa_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CAA register - */ -/*@{*/ -#define HW_CAU_AESIC_CAA_ADDR(x) ((x) + 0xB44U) - -#define HW_CAU_AESIC_CAA(x) (*(__O hw_cau_aesic_caa_t *) HW_CAU_AESIC_CAA_ADDR(x)) -#define HW_CAU_AESIC_CAA_WR(x, v) (HW_CAU_AESIC_CAA(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CAA bitfields - */ - -/*! - * @name Register CAU_AESIC_CAA, field ACC[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CAA_ACC (0U) /*!< Bit position for CAU_AESIC_CAA_ACC. */ -#define BM_CAU_AESIC_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CAA_ACC. */ -#define BS_CAU_AESIC_CAA_ACC (32U) /*!< Bit field size in bits for CAU_AESIC_CAA_ACC. */ - -/*! @brief Format value for bitfield CAU_AESIC_CAA_ACC. */ -#define BF_CAU_AESIC_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CAA_ACC) & BM_CAU_AESIC_CAA_ACC) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca0 -{ - uint32_t U; - struct _hw_cau_aesic_ca0_bitfields - { - uint32_t CA0 : 32; /*!< [31:0] CA0 */ - } B; -} hw_cau_aesic_ca0_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA0 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA0_ADDR(x) ((x) + 0xB48U) - -#define HW_CAU_AESIC_CA0(x) (*(__O hw_cau_aesic_ca0_t *) HW_CAU_AESIC_CA0_ADDR(x)) -#define HW_CAU_AESIC_CA0_WR(x, v) (HW_CAU_AESIC_CA0(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA0 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA0, field CA0[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA0_CA0 (0U) /*!< Bit position for CAU_AESIC_CA0_CA0. */ -#define BM_CAU_AESIC_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA0_CA0. */ -#define BS_CAU_AESIC_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_AESIC_CA0_CA0. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA0_CA0. */ -#define BF_CAU_AESIC_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA0_CA0) & BM_CAU_AESIC_CA0_CA0) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca1 -{ - uint32_t U; - struct _hw_cau_aesic_ca1_bitfields - { - uint32_t CA1 : 32; /*!< [31:0] CA1 */ - } B; -} hw_cau_aesic_ca1_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA1 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA1_ADDR(x) ((x) + 0xB4CU) - -#define HW_CAU_AESIC_CA1(x) (*(__O hw_cau_aesic_ca1_t *) HW_CAU_AESIC_CA1_ADDR(x)) -#define HW_CAU_AESIC_CA1_WR(x, v) (HW_CAU_AESIC_CA1(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA1 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA1, field CA1[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA1_CA1 (0U) /*!< Bit position for CAU_AESIC_CA1_CA1. */ -#define BM_CAU_AESIC_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA1_CA1. */ -#define BS_CAU_AESIC_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_AESIC_CA1_CA1. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA1_CA1. */ -#define BF_CAU_AESIC_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA1_CA1) & BM_CAU_AESIC_CA1_CA1) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca2 -{ - uint32_t U; - struct _hw_cau_aesic_ca2_bitfields - { - uint32_t CA2 : 32; /*!< [31:0] CA2 */ - } B; -} hw_cau_aesic_ca2_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA2 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA2_ADDR(x) ((x) + 0xB50U) - -#define HW_CAU_AESIC_CA2(x) (*(__O hw_cau_aesic_ca2_t *) HW_CAU_AESIC_CA2_ADDR(x)) -#define HW_CAU_AESIC_CA2_WR(x, v) (HW_CAU_AESIC_CA2(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA2 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA2, field CA2[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA2_CA2 (0U) /*!< Bit position for CAU_AESIC_CA2_CA2. */ -#define BM_CAU_AESIC_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA2_CA2. */ -#define BS_CAU_AESIC_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_AESIC_CA2_CA2. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA2_CA2. */ -#define BF_CAU_AESIC_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA2_CA2) & BM_CAU_AESIC_CA2_CA2) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca3 -{ - uint32_t U; - struct _hw_cau_aesic_ca3_bitfields - { - uint32_t CA3 : 32; /*!< [31:0] CA3 */ - } B; -} hw_cau_aesic_ca3_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA3 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA3_ADDR(x) ((x) + 0xB54U) - -#define HW_CAU_AESIC_CA3(x) (*(__O hw_cau_aesic_ca3_t *) HW_CAU_AESIC_CA3_ADDR(x)) -#define HW_CAU_AESIC_CA3_WR(x, v) (HW_CAU_AESIC_CA3(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA3 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA3, field CA3[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA3_CA3 (0U) /*!< Bit position for CAU_AESIC_CA3_CA3. */ -#define BM_CAU_AESIC_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA3_CA3. */ -#define BS_CAU_AESIC_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_AESIC_CA3_CA3. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA3_CA3. */ -#define BF_CAU_AESIC_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA3_CA3) & BM_CAU_AESIC_CA3_CA3) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca4 -{ - uint32_t U; - struct _hw_cau_aesic_ca4_bitfields - { - uint32_t CA4 : 32; /*!< [31:0] CA4 */ - } B; -} hw_cau_aesic_ca4_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA4 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA4_ADDR(x) ((x) + 0xB58U) - -#define HW_CAU_AESIC_CA4(x) (*(__O hw_cau_aesic_ca4_t *) HW_CAU_AESIC_CA4_ADDR(x)) -#define HW_CAU_AESIC_CA4_WR(x, v) (HW_CAU_AESIC_CA4(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA4 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA4, field CA4[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA4_CA4 (0U) /*!< Bit position for CAU_AESIC_CA4_CA4. */ -#define BM_CAU_AESIC_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA4_CA4. */ -#define BS_CAU_AESIC_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_AESIC_CA4_CA4. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA4_CA4. */ -#define BF_CAU_AESIC_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA4_CA4) & BM_CAU_AESIC_CA4_CA4) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca5 -{ - uint32_t U; - struct _hw_cau_aesic_ca5_bitfields - { - uint32_t CA5 : 32; /*!< [31:0] CA5 */ - } B; -} hw_cau_aesic_ca5_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA5 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA5_ADDR(x) ((x) + 0xB5CU) - -#define HW_CAU_AESIC_CA5(x) (*(__O hw_cau_aesic_ca5_t *) HW_CAU_AESIC_CA5_ADDR(x)) -#define HW_CAU_AESIC_CA5_WR(x, v) (HW_CAU_AESIC_CA5(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA5 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA5, field CA5[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA5_CA5 (0U) /*!< Bit position for CAU_AESIC_CA5_CA5. */ -#define BM_CAU_AESIC_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA5_CA5. */ -#define BS_CAU_AESIC_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_AESIC_CA5_CA5. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA5_CA5. */ -#define BF_CAU_AESIC_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA5_CA5) & BM_CAU_AESIC_CA5_CA5) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca6 -{ - uint32_t U; - struct _hw_cau_aesic_ca6_bitfields - { - uint32_t CA6 : 32; /*!< [31:0] CA6 */ - } B; -} hw_cau_aesic_ca6_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA6 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA6_ADDR(x) ((x) + 0xB60U) - -#define HW_CAU_AESIC_CA6(x) (*(__O hw_cau_aesic_ca6_t *) HW_CAU_AESIC_CA6_ADDR(x)) -#define HW_CAU_AESIC_CA6_WR(x, v) (HW_CAU_AESIC_CA6(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA6 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA6, field CA6[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA6_CA6 (0U) /*!< Bit position for CAU_AESIC_CA6_CA6. */ -#define BM_CAU_AESIC_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA6_CA6. */ -#define BS_CAU_AESIC_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_AESIC_CA6_CA6. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA6_CA6. */ -#define BF_CAU_AESIC_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA6_CA6) & BM_CAU_AESIC_CA6_CA6) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca7 -{ - uint32_t U; - struct _hw_cau_aesic_ca7_bitfields - { - uint32_t CA7 : 32; /*!< [31:0] CA7 */ - } B; -} hw_cau_aesic_ca7_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA7 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA7_ADDR(x) ((x) + 0xB64U) - -#define HW_CAU_AESIC_CA7(x) (*(__O hw_cau_aesic_ca7_t *) HW_CAU_AESIC_CA7_ADDR(x)) -#define HW_CAU_AESIC_CA7_WR(x, v) (HW_CAU_AESIC_CA7(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA7 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA7, field CA7[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA7_CA7 (0U) /*!< Bit position for CAU_AESIC_CA7_CA7. */ -#define BM_CAU_AESIC_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA7_CA7. */ -#define BS_CAU_AESIC_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_AESIC_CA7_CA7. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA7_CA7. */ -#define BF_CAU_AESIC_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA7_CA7) & BM_CAU_AESIC_CA7_CA7) -/*@}*/ - -/******************************************************************************* - * HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command - ******************************************************************************/ - -/*! - * @brief HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command (WO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_cau_aesic_ca8 -{ - uint32_t U; - struct _hw_cau_aesic_ca8_bitfields - { - uint32_t CA8 : 32; /*!< [31:0] CA8 */ - } B; -} hw_cau_aesic_ca8_t; - -/*! - * @name Constants and macros for entire CAU_AESIC_CA8 register - */ -/*@{*/ -#define HW_CAU_AESIC_CA8_ADDR(x) ((x) + 0xB68U) - -#define HW_CAU_AESIC_CA8(x) (*(__O hw_cau_aesic_ca8_t *) HW_CAU_AESIC_CA8_ADDR(x)) -#define HW_CAU_AESIC_CA8_WR(x, v) (HW_CAU_AESIC_CA8(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual CAU_AESIC_CA8 bitfields - */ - -/*! - * @name Register CAU_AESIC_CA8, field CA8[31:0] (WO) - */ -/*@{*/ -#define BP_CAU_AESIC_CA8_CA8 (0U) /*!< Bit position for CAU_AESIC_CA8_CA8. */ -#define BM_CAU_AESIC_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA8_CA8. */ -#define BS_CAU_AESIC_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_AESIC_CA8_CA8. */ - -/*! @brief Format value for bitfield CAU_AESIC_CA8_CA8. */ -#define BF_CAU_AESIC_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA8_CA8) & BM_CAU_AESIC_CA8_CA8) -/*@}*/ - -/******************************************************************************* - * hw_cau_t - module struct - ******************************************************************************/ -/*! - * @brief All CAU module registers. - */ -#pragma pack(1) -typedef struct _hw_cau -{ - __O hw_cau_direct0_t DIRECT0; /*!< [0x0] Direct access register 0 */ - __O hw_cau_direct1_t DIRECT1; /*!< [0x4] Direct access register 1 */ - __O hw_cau_direct2_t DIRECT2; /*!< [0x8] Direct access register 2 */ - __O hw_cau_direct3_t DIRECT3; /*!< [0xC] Direct access register 3 */ - __O hw_cau_direct4_t DIRECT4; /*!< [0x10] Direct access register 4 */ - __O hw_cau_direct5_t DIRECT5; /*!< [0x14] Direct access register 5 */ - __O hw_cau_direct6_t DIRECT6; /*!< [0x18] Direct access register 6 */ - __O hw_cau_direct7_t DIRECT7; /*!< [0x1C] Direct access register 7 */ - __O hw_cau_direct8_t DIRECT8; /*!< [0x20] Direct access register 8 */ - __O hw_cau_direct9_t DIRECT9; /*!< [0x24] Direct access register 9 */ - __O hw_cau_direct10_t DIRECT10; /*!< [0x28] Direct access register 10 */ - __O hw_cau_direct11_t DIRECT11; /*!< [0x2C] Direct access register 11 */ - __O hw_cau_direct12_t DIRECT12; /*!< [0x30] Direct access register 12 */ - __O hw_cau_direct13_t DIRECT13; /*!< [0x34] Direct access register 13 */ - __O hw_cau_direct14_t DIRECT14; /*!< [0x38] Direct access register 14 */ - __O hw_cau_direct15_t DIRECT15; /*!< [0x3C] Direct access register 15 */ - uint8_t _reserved0[2048]; - __O hw_cau_ldr_casr_t LDR_CASR; /*!< [0x840] Status register - Load Register command */ - __O hw_cau_ldr_caa_t LDR_CAA; /*!< [0x844] Accumulator register - Load Register command */ - __O hw_cau_ldr_ca0_t LDR_CA0; /*!< [0x848] General Purpose Register 0 - Load Register command */ - __O hw_cau_ldr_ca1_t LDR_CA1; /*!< [0x84C] General Purpose Register 1 - Load Register command */ - __O hw_cau_ldr_ca2_t LDR_CA2; /*!< [0x850] General Purpose Register 2 - Load Register command */ - __O hw_cau_ldr_ca3_t LDR_CA3; /*!< [0x854] General Purpose Register 3 - Load Register command */ - __O hw_cau_ldr_ca4_t LDR_CA4; /*!< [0x858] General Purpose Register 4 - Load Register command */ - __O hw_cau_ldr_ca5_t LDR_CA5; /*!< [0x85C] General Purpose Register 5 - Load Register command */ - __O hw_cau_ldr_ca6_t LDR_CA6; /*!< [0x860] General Purpose Register 6 - Load Register command */ - __O hw_cau_ldr_ca7_t LDR_CA7; /*!< [0x864] General Purpose Register 7 - Load Register command */ - __O hw_cau_ldr_ca8_t LDR_CA8; /*!< [0x868] General Purpose Register 8 - Load Register command */ - uint8_t _reserved1[20]; - __I hw_cau_str_casr_t STR_CASR; /*!< [0x880] Status register - Store Register command */ - __I hw_cau_str_caa_t STR_CAA; /*!< [0x884] Accumulator register - Store Register command */ - __I hw_cau_str_ca0_t STR_CA0; /*!< [0x888] General Purpose Register 0 - Store Register command */ - __I hw_cau_str_ca1_t STR_CA1; /*!< [0x88C] General Purpose Register 1 - Store Register command */ - __I hw_cau_str_ca2_t STR_CA2; /*!< [0x890] General Purpose Register 2 - Store Register command */ - __I hw_cau_str_ca3_t STR_CA3; /*!< [0x894] General Purpose Register 3 - Store Register command */ - __I hw_cau_str_ca4_t STR_CA4; /*!< [0x898] General Purpose Register 4 - Store Register command */ - __I hw_cau_str_ca5_t STR_CA5; /*!< [0x89C] General Purpose Register 5 - Store Register command */ - __I hw_cau_str_ca6_t STR_CA6; /*!< [0x8A0] General Purpose Register 6 - Store Register command */ - __I hw_cau_str_ca7_t STR_CA7; /*!< [0x8A4] General Purpose Register 7 - Store Register command */ - __I hw_cau_str_ca8_t STR_CA8; /*!< [0x8A8] General Purpose Register 8 - Store Register command */ - uint8_t _reserved2[20]; - __O hw_cau_adr_casr_t ADR_CASR; /*!< [0x8C0] Status register - Add Register command */ - __O hw_cau_adr_caa_t ADR_CAA; /*!< [0x8C4] Accumulator register - Add to register command */ - __O hw_cau_adr_ca0_t ADR_CA0; /*!< [0x8C8] General Purpose Register 0 - Add to register command */ - __O hw_cau_adr_ca1_t ADR_CA1; /*!< [0x8CC] General Purpose Register 1 - Add to register command */ - __O hw_cau_adr_ca2_t ADR_CA2; /*!< [0x8D0] General Purpose Register 2 - Add to register command */ - __O hw_cau_adr_ca3_t ADR_CA3; /*!< [0x8D4] General Purpose Register 3 - Add to register command */ - __O hw_cau_adr_ca4_t ADR_CA4; /*!< [0x8D8] General Purpose Register 4 - Add to register command */ - __O hw_cau_adr_ca5_t ADR_CA5; /*!< [0x8DC] General Purpose Register 5 - Add to register command */ - __O hw_cau_adr_ca6_t ADR_CA6; /*!< [0x8E0] General Purpose Register 6 - Add to register command */ - __O hw_cau_adr_ca7_t ADR_CA7; /*!< [0x8E4] General Purpose Register 7 - Add to register command */ - __O hw_cau_adr_ca8_t ADR_CA8; /*!< [0x8E8] General Purpose Register 8 - Add to register command */ - uint8_t _reserved3[20]; - __O hw_cau_radr_casr_t RADR_CASR; /*!< [0x900] Status register - Reverse and Add to Register command */ - __O hw_cau_radr_caa_t RADR_CAA; /*!< [0x904] Accumulator register - Reverse and Add to Register command */ - __O hw_cau_radr_ca0_t RADR_CA0; /*!< [0x908] General Purpose Register 0 - Reverse and Add to Register command */ - __O hw_cau_radr_ca1_t RADR_CA1; /*!< [0x90C] General Purpose Register 1 - Reverse and Add to Register command */ - __O hw_cau_radr_ca2_t RADR_CA2; /*!< [0x910] General Purpose Register 2 - Reverse and Add to Register command */ - __O hw_cau_radr_ca3_t RADR_CA3; /*!< [0x914] General Purpose Register 3 - Reverse and Add to Register command */ - __O hw_cau_radr_ca4_t RADR_CA4; /*!< [0x918] General Purpose Register 4 - Reverse and Add to Register command */ - __O hw_cau_radr_ca5_t RADR_CA5; /*!< [0x91C] General Purpose Register 5 - Reverse and Add to Register command */ - __O hw_cau_radr_ca6_t RADR_CA6; /*!< [0x920] General Purpose Register 6 - Reverse and Add to Register command */ - __O hw_cau_radr_ca7_t RADR_CA7; /*!< [0x924] General Purpose Register 7 - Reverse and Add to Register command */ - __O hw_cau_radr_ca8_t RADR_CA8; /*!< [0x928] General Purpose Register 8 - Reverse and Add to Register command */ - uint8_t _reserved4[84]; - __O hw_cau_xor_casr_t XOR_CASR; /*!< [0x980] Status register - Exclusive Or command */ - __O hw_cau_xor_caa_t XOR_CAA; /*!< [0x984] Accumulator register - Exclusive Or command */ - __O hw_cau_xor_ca0_t XOR_CA0; /*!< [0x988] General Purpose Register 0 - Exclusive Or command */ - __O hw_cau_xor_ca1_t XOR_CA1; /*!< [0x98C] General Purpose Register 1 - Exclusive Or command */ - __O hw_cau_xor_ca2_t XOR_CA2; /*!< [0x990] General Purpose Register 2 - Exclusive Or command */ - __O hw_cau_xor_ca3_t XOR_CA3; /*!< [0x994] General Purpose Register 3 - Exclusive Or command */ - __O hw_cau_xor_ca4_t XOR_CA4; /*!< [0x998] General Purpose Register 4 - Exclusive Or command */ - __O hw_cau_xor_ca5_t XOR_CA5; /*!< [0x99C] General Purpose Register 5 - Exclusive Or command */ - __O hw_cau_xor_ca6_t XOR_CA6; /*!< [0x9A0] General Purpose Register 6 - Exclusive Or command */ - __O hw_cau_xor_ca7_t XOR_CA7; /*!< [0x9A4] General Purpose Register 7 - Exclusive Or command */ - __O hw_cau_xor_ca8_t XOR_CA8; /*!< [0x9A8] General Purpose Register 8 - Exclusive Or command */ - uint8_t _reserved5[20]; - __O hw_cau_rotl_casr_t ROTL_CASR; /*!< [0x9C0] Status register - Rotate Left command */ - __O hw_cau_rotl_caa_t ROTL_CAA; /*!< [0x9C4] Accumulator register - Rotate Left command */ - __O hw_cau_rotl_ca0_t ROTL_CA0; /*!< [0x9C8] General Purpose Register 0 - Rotate Left command */ - __O hw_cau_rotl_ca1_t ROTL_CA1; /*!< [0x9CC] General Purpose Register 1 - Rotate Left command */ - __O hw_cau_rotl_ca2_t ROTL_CA2; /*!< [0x9D0] General Purpose Register 2 - Rotate Left command */ - __O hw_cau_rotl_ca3_t ROTL_CA3; /*!< [0x9D4] General Purpose Register 3 - Rotate Left command */ - __O hw_cau_rotl_ca4_t ROTL_CA4; /*!< [0x9D8] General Purpose Register 4 - Rotate Left command */ - __O hw_cau_rotl_ca5_t ROTL_CA5; /*!< [0x9DC] General Purpose Register 5 - Rotate Left command */ - __O hw_cau_rotl_ca6_t ROTL_CA6; /*!< [0x9E0] General Purpose Register 6 - Rotate Left command */ - __O hw_cau_rotl_ca7_t ROTL_CA7; /*!< [0x9E4] General Purpose Register 7 - Rotate Left command */ - __O hw_cau_rotl_ca8_t ROTL_CA8; /*!< [0x9E8] General Purpose Register 8 - Rotate Left command */ - uint8_t _reserved6[276]; - __O hw_cau_aesc_casr_t AESC_CASR; /*!< [0xB00] Status register - AES Column Operation command */ - __O hw_cau_aesc_caa_t AESC_CAA; /*!< [0xB04] Accumulator register - AES Column Operation command */ - __O hw_cau_aesc_ca0_t AESC_CA0; /*!< [0xB08] General Purpose Register 0 - AES Column Operation command */ - __O hw_cau_aesc_ca1_t AESC_CA1; /*!< [0xB0C] General Purpose Register 1 - AES Column Operation command */ - __O hw_cau_aesc_ca2_t AESC_CA2; /*!< [0xB10] General Purpose Register 2 - AES Column Operation command */ - __O hw_cau_aesc_ca3_t AESC_CA3; /*!< [0xB14] General Purpose Register 3 - AES Column Operation command */ - __O hw_cau_aesc_ca4_t AESC_CA4; /*!< [0xB18] General Purpose Register 4 - AES Column Operation command */ - __O hw_cau_aesc_ca5_t AESC_CA5; /*!< [0xB1C] General Purpose Register 5 - AES Column Operation command */ - __O hw_cau_aesc_ca6_t AESC_CA6; /*!< [0xB20] General Purpose Register 6 - AES Column Operation command */ - __O hw_cau_aesc_ca7_t AESC_CA7; /*!< [0xB24] General Purpose Register 7 - AES Column Operation command */ - __O hw_cau_aesc_ca8_t AESC_CA8; /*!< [0xB28] General Purpose Register 8 - AES Column Operation command */ - uint8_t _reserved7[20]; - __O hw_cau_aesic_casr_t AESIC_CASR; /*!< [0xB40] Status register - AES Inverse Column Operation command */ - __O hw_cau_aesic_caa_t AESIC_CAA; /*!< [0xB44] Accumulator register - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca0_t AESIC_CA0; /*!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca1_t AESIC_CA1; /*!< [0xB4C] General Purpose Register 1 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca2_t AESIC_CA2; /*!< [0xB50] General Purpose Register 2 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca3_t AESIC_CA3; /*!< [0xB54] General Purpose Register 3 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca4_t AESIC_CA4; /*!< [0xB58] General Purpose Register 4 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca5_t AESIC_CA5; /*!< [0xB5C] General Purpose Register 5 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca6_t AESIC_CA6; /*!< [0xB60] General Purpose Register 6 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca7_t AESIC_CA7; /*!< [0xB64] General Purpose Register 7 - AES Inverse Column Operation command */ - __O hw_cau_aesic_ca8_t AESIC_CA8; /*!< [0xB68] General Purpose Register 8 - AES Inverse Column Operation command */ -} hw_cau_t; -#pragma pack() - -/*! @brief Macro to access all CAU registers. */ -/*! @param x CAU module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CAU(CAU_BASE). */ -#define HW_CAU(x) (*(hw_cau_t *)(x)) - -#endif /* __HW_CAU_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmp.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmp.h deleted file mode 100644 index f308ec602dd..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmp.h +++ /dev/null @@ -1,942 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CMP_REGISTERS_H__ -#define __HW_CMP_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 CMP - * - * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) - * - * Registers defined in this header file: - * - HW_CMP_CR0 - CMP Control Register 0 - * - HW_CMP_CR1 - CMP Control Register 1 - * - HW_CMP_FPR - CMP Filter Period Register - * - HW_CMP_SCR - CMP Status and Control Register - * - HW_CMP_DACCR - DAC Control Register - * - HW_CMP_MUXCR - MUX Control Register - * - * - hw_cmp_t - Struct containing all module registers. - */ - -#define HW_CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */ -#define HW_CMP0 (0U) /*!< Instance number for CMP0. */ -#define HW_CMP1 (1U) /*!< Instance number for CMP1. */ -#define HW_CMP2 (2U) /*!< Instance number for CMP2. */ - -/******************************************************************************* - * HW_CMP_CR0 - CMP Control Register 0 - ******************************************************************************/ - -/*! - * @brief HW_CMP_CR0 - CMP Control Register 0 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_cr0 -{ - uint8_t U; - struct _hw_cmp_cr0_bitfields - { - uint8_t HYSTCTR : 2; /*!< [1:0] Comparator hard block hysteresis - * control */ - uint8_t RESERVED0 : 2; /*!< [3:2] */ - uint8_t FILTER_CNT : 3; /*!< [6:4] Filter Sample Count */ - uint8_t RESERVED1 : 1; /*!< [7] */ - } B; -} hw_cmp_cr0_t; - -/*! - * @name Constants and macros for entire CMP_CR0 register - */ -/*@{*/ -#define HW_CMP_CR0_ADDR(x) ((x) + 0x0U) - -#define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x)) -#define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U) -#define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v)) -#define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v))) -#define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v))) -#define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_CR0 bitfields - */ - -/*! - * @name Register CMP_CR0, field HYSTCTR[1:0] (RW) - * - * Defines the programmable hysteresis level. The hysteresis values associated - * with each level are device-specific. See the Data Sheet of the device for the - * exact values. - * - * Values: - * - 00 - Level 0 - * - 01 - Level 1 - * - 10 - Level 2 - * - 11 - Level 3 - */ -/*@{*/ -#define BP_CMP_CR0_HYSTCTR (0U) /*!< Bit position for CMP_CR0_HYSTCTR. */ -#define BM_CMP_CR0_HYSTCTR (0x03U) /*!< Bit mask for CMP_CR0_HYSTCTR. */ -#define BS_CMP_CR0_HYSTCTR (2U) /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */ - -/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */ -#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR) - -/*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */ -#define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR) - -/*! @brief Set the HYSTCTR field to a new value. */ -#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v))) -/*@}*/ - -/*! - * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW) - * - * Represents the number of consecutive samples that must agree prior to the - * comparator ouput filter accepting a new output state. For information regarding - * filter programming and latency, see the Functional descriptionThe CMP module - * can be used to compare two analog input voltages applied to INP and INM. . - * - * Values: - * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a - * legal state, and is not recommended. If SE = 0, COUT = COUTA. - * - 001 - One sample must agree. The comparator output is simply sampled. - * - 010 - 2 consecutive samples must agree. - * - 011 - 3 consecutive samples must agree. - * - 100 - 4 consecutive samples must agree. - * - 101 - 5 consecutive samples must agree. - * - 110 - 6 consecutive samples must agree. - * - 111 - 7 consecutive samples must agree. - */ -/*@{*/ -#define BP_CMP_CR0_FILTER_CNT (4U) /*!< Bit position for CMP_CR0_FILTER_CNT. */ -#define BM_CMP_CR0_FILTER_CNT (0x70U) /*!< Bit mask for CMP_CR0_FILTER_CNT. */ -#define BS_CMP_CR0_FILTER_CNT (3U) /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */ - -/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */ -#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT) - -/*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */ -#define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT) - -/*! @brief Set the FILTER_CNT field to a new value. */ -#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_CMP_CR1 - CMP Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_CMP_CR1 - CMP Control Register 1 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_cr1 -{ - uint8_t U; - struct _hw_cmp_cr1_bitfields - { - uint8_t EN : 1; /*!< [0] Comparator Module Enable */ - uint8_t OPE : 1; /*!< [1] Comparator Output Pin Enable */ - uint8_t COS : 1; /*!< [2] Comparator Output Select */ - uint8_t INV : 1; /*!< [3] Comparator INVERT */ - uint8_t PMODE : 1; /*!< [4] Power Mode Select */ - uint8_t RESERVED0 : 1; /*!< [5] */ - uint8_t WE : 1; /*!< [6] Windowing Enable */ - uint8_t SE : 1; /*!< [7] Sample Enable */ - } B; -} hw_cmp_cr1_t; - -/*! - * @name Constants and macros for entire CMP_CR1 register - */ -/*@{*/ -#define HW_CMP_CR1_ADDR(x) ((x) + 0x1U) - -#define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x)) -#define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U) -#define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v)) -#define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v))) -#define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v))) -#define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_CR1 bitfields - */ - -/*! - * @name Register CMP_CR1, field EN[0] (RW) - * - * Enables the Analog Comparator module. When the module is not enabled, it - * remains in the off state, and consumes no power. When the user selects the same - * input from analog mux to the positive and negative port, the comparator is - * disabled automatically. - * - * Values: - * - 0 - Analog Comparator is disabled. - * - 1 - Analog Comparator is enabled. - */ -/*@{*/ -#define BP_CMP_CR1_EN (0U) /*!< Bit position for CMP_CR1_EN. */ -#define BM_CMP_CR1_EN (0x01U) /*!< Bit mask for CMP_CR1_EN. */ -#define BS_CMP_CR1_EN (1U) /*!< Bit field size in bits for CMP_CR1_EN. */ - -/*! @brief Read current value of the CMP_CR1_EN field. */ -#define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN)) - -/*! @brief Format value for bitfield CMP_CR1_EN. */ -#define BF_CMP_CR1_EN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN) - -/*! @brief Set the EN field to a new value. */ -#define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field OPE[1] (RW) - * - * Values: - * - 0 - CMPO is not available on the associated CMPO output pin. If the - * comparator does not own the pin, this field has no effect. - * - 1 - CMPO is available on the associated CMPO output pin. The comparator - * output (CMPO) is driven out on the associated CMPO output pin if the - * comparator owns the pin. If the comparator does not own the field, this bit has no - * effect. - */ -/*@{*/ -#define BP_CMP_CR1_OPE (1U) /*!< Bit position for CMP_CR1_OPE. */ -#define BM_CMP_CR1_OPE (0x02U) /*!< Bit mask for CMP_CR1_OPE. */ -#define BS_CMP_CR1_OPE (1U) /*!< Bit field size in bits for CMP_CR1_OPE. */ - -/*! @brief Read current value of the CMP_CR1_OPE field. */ -#define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE)) - -/*! @brief Format value for bitfield CMP_CR1_OPE. */ -#define BF_CMP_CR1_OPE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE) - -/*! @brief Set the OPE field to a new value. */ -#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field COS[2] (RW) - * - * Values: - * - 0 - Set the filtered comparator output (CMPO) to equal COUT. - * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA. - */ -/*@{*/ -#define BP_CMP_CR1_COS (2U) /*!< Bit position for CMP_CR1_COS. */ -#define BM_CMP_CR1_COS (0x04U) /*!< Bit mask for CMP_CR1_COS. */ -#define BS_CMP_CR1_COS (1U) /*!< Bit field size in bits for CMP_CR1_COS. */ - -/*! @brief Read current value of the CMP_CR1_COS field. */ -#define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS)) - -/*! @brief Format value for bitfield CMP_CR1_COS. */ -#define BF_CMP_CR1_COS(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS) - -/*! @brief Set the COS field to a new value. */ -#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field INV[3] (RW) - * - * Allows selection of the polarity of the analog comparator function. It is - * also driven to the COUT output, on both the device pin and as SCR[COUT], when - * OPE=0. - * - * Values: - * - 0 - Does not invert the comparator output. - * - 1 - Inverts the comparator output. - */ -/*@{*/ -#define BP_CMP_CR1_INV (3U) /*!< Bit position for CMP_CR1_INV. */ -#define BM_CMP_CR1_INV (0x08U) /*!< Bit mask for CMP_CR1_INV. */ -#define BS_CMP_CR1_INV (1U) /*!< Bit field size in bits for CMP_CR1_INV. */ - -/*! @brief Read current value of the CMP_CR1_INV field. */ -#define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV)) - -/*! @brief Format value for bitfield CMP_CR1_INV. */ -#define BF_CMP_CR1_INV(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV) - -/*! @brief Set the INV field to a new value. */ -#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field PMODE[4] (RW) - * - * See the electrical specifications table in the device Data Sheet for details. - * - * Values: - * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower - * output propagation delay and lower current consumption. - * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster - * output propagation delay and higher current consumption. - */ -/*@{*/ -#define BP_CMP_CR1_PMODE (4U) /*!< Bit position for CMP_CR1_PMODE. */ -#define BM_CMP_CR1_PMODE (0x10U) /*!< Bit mask for CMP_CR1_PMODE. */ -#define BS_CMP_CR1_PMODE (1U) /*!< Bit field size in bits for CMP_CR1_PMODE. */ - -/*! @brief Read current value of the CMP_CR1_PMODE field. */ -#define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE)) - -/*! @brief Format value for bitfield CMP_CR1_PMODE. */ -#define BF_CMP_CR1_PMODE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE) - -/*! @brief Set the PMODE field to a new value. */ -#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field WE[6] (RW) - * - * At any given time, either SE or WE can be set. If a write to this register - * attempts to set both, then SE is set and WE is cleared. However, avoid writing - * 1s to both field locations because this "11" case is reserved and may change in - * future implementations. - * - * Values: - * - 0 - Windowing mode is not selected. - * - 1 - Windowing mode is selected. - */ -/*@{*/ -#define BP_CMP_CR1_WE (6U) /*!< Bit position for CMP_CR1_WE. */ -#define BM_CMP_CR1_WE (0x40U) /*!< Bit mask for CMP_CR1_WE. */ -#define BS_CMP_CR1_WE (1U) /*!< Bit field size in bits for CMP_CR1_WE. */ - -/*! @brief Read current value of the CMP_CR1_WE field. */ -#define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE)) - -/*! @brief Format value for bitfield CMP_CR1_WE. */ -#define BF_CMP_CR1_WE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE) - -/*! @brief Set the WE field to a new value. */ -#define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v)) -/*@}*/ - -/*! - * @name Register CMP_CR1, field SE[7] (RW) - * - * At any given time, either SE or WE can be set. If a write to this register - * attempts to set both, then SE is set and WE is cleared. However, avoid writing - * 1s to both field locations because this "11" case is reserved and may change in - * future implementations. - * - * Values: - * - 0 - Sampling mode is not selected. - * - 1 - Sampling mode is selected. - */ -/*@{*/ -#define BP_CMP_CR1_SE (7U) /*!< Bit position for CMP_CR1_SE. */ -#define BM_CMP_CR1_SE (0x80U) /*!< Bit mask for CMP_CR1_SE. */ -#define BS_CMP_CR1_SE (1U) /*!< Bit field size in bits for CMP_CR1_SE. */ - -/*! @brief Read current value of the CMP_CR1_SE field. */ -#define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE)) - -/*! @brief Format value for bitfield CMP_CR1_SE. */ -#define BF_CMP_CR1_SE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE) - -/*! @brief Set the SE field to a new value. */ -#define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_FPR - CMP Filter Period Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_FPR - CMP Filter Period Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_fpr -{ - uint8_t U; - struct _hw_cmp_fpr_bitfields - { - uint8_t FILT_PER : 8; /*!< [7:0] Filter Sample Period */ - } B; -} hw_cmp_fpr_t; - -/*! - * @name Constants and macros for entire CMP_FPR register - */ -/*@{*/ -#define HW_CMP_FPR_ADDR(x) ((x) + 0x2U) - -#define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x)) -#define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U) -#define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v)) -#define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v))) -#define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v))) -#define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_FPR bitfields - */ - -/*! - * @name Register CMP_FPR, field FILT_PER[7:0] (RW) - * - * Specifies the sampling period, in bus clock cycles, of the comparator output - * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter - * programming and latency details appear in the Functional descriptionThe CMP - * module can be used to compare two analog input voltages applied to INP and INM. . - * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE - * signal is used to determine the sampling period. - */ -/*@{*/ -#define BP_CMP_FPR_FILT_PER (0U) /*!< Bit position for CMP_FPR_FILT_PER. */ -#define BM_CMP_FPR_FILT_PER (0xFFU) /*!< Bit mask for CMP_FPR_FILT_PER. */ -#define BS_CMP_FPR_FILT_PER (8U) /*!< Bit field size in bits for CMP_FPR_FILT_PER. */ - -/*! @brief Read current value of the CMP_FPR_FILT_PER field. */ -#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U) - -/*! @brief Format value for bitfield CMP_FPR_FILT_PER. */ -#define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER) - -/*! @brief Set the FILT_PER field to a new value. */ -#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_SCR - CMP Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_SCR - CMP Status and Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_scr -{ - uint8_t U; - struct _hw_cmp_scr_bitfields - { - uint8_t COUT : 1; /*!< [0] Analog Comparator Output */ - uint8_t CFF : 1; /*!< [1] Analog Comparator Flag Falling */ - uint8_t CFR : 1; /*!< [2] Analog Comparator Flag Rising */ - uint8_t IEF : 1; /*!< [3] Comparator Interrupt Enable Falling */ - uint8_t IER : 1; /*!< [4] Comparator Interrupt Enable Rising */ - uint8_t RESERVED0 : 1; /*!< [5] */ - uint8_t DMAEN : 1; /*!< [6] DMA Enable Control */ - uint8_t RESERVED1 : 1; /*!< [7] */ - } B; -} hw_cmp_scr_t; - -/*! - * @name Constants and macros for entire CMP_SCR register - */ -/*@{*/ -#define HW_CMP_SCR_ADDR(x) ((x) + 0x3U) - -#define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x)) -#define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U) -#define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v)) -#define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v))) -#define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v))) -#define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_SCR bitfields - */ - -/*! - * @name Register CMP_SCR, field COUT[0] (RO) - * - * Returns the current value of the Analog Comparator output, when read. The - * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module - * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored. - */ -/*@{*/ -#define BP_CMP_SCR_COUT (0U) /*!< Bit position for CMP_SCR_COUT. */ -#define BM_CMP_SCR_COUT (0x01U) /*!< Bit mask for CMP_SCR_COUT. */ -#define BS_CMP_SCR_COUT (1U) /*!< Bit field size in bits for CMP_SCR_COUT. */ - -/*! @brief Read current value of the CMP_SCR_COUT field. */ -#define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field CFF[1] (W1C) - * - * Detects a falling-edge on COUT, when set, during normal operation. CFF is - * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge - * sensitive . - * - * Values: - * - 0 - Falling-edge on COUT has not been detected. - * - 1 - Falling-edge on COUT has occurred. - */ -/*@{*/ -#define BP_CMP_SCR_CFF (1U) /*!< Bit position for CMP_SCR_CFF. */ -#define BM_CMP_SCR_CFF (0x02U) /*!< Bit mask for CMP_SCR_CFF. */ -#define BS_CMP_SCR_CFF (1U) /*!< Bit field size in bits for CMP_SCR_CFF. */ - -/*! @brief Read current value of the CMP_SCR_CFF field. */ -#define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF)) - -/*! @brief Format value for bitfield CMP_SCR_CFF. */ -#define BF_CMP_SCR_CFF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF) - -/*! @brief Set the CFF field to a new value. */ -#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field CFR[2] (W1C) - * - * Detects a rising-edge on COUT, when set, during normal operation. CFR is - * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge - * sensitive . - * - * Values: - * - 0 - Rising-edge on COUT has not been detected. - * - 1 - Rising-edge on COUT has occurred. - */ -/*@{*/ -#define BP_CMP_SCR_CFR (2U) /*!< Bit position for CMP_SCR_CFR. */ -#define BM_CMP_SCR_CFR (0x04U) /*!< Bit mask for CMP_SCR_CFR. */ -#define BS_CMP_SCR_CFR (1U) /*!< Bit field size in bits for CMP_SCR_CFR. */ - -/*! @brief Read current value of the CMP_SCR_CFR field. */ -#define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR)) - -/*! @brief Format value for bitfield CMP_SCR_CFR. */ -#define BF_CMP_SCR_CFR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR) - -/*! @brief Set the CFR field to a new value. */ -#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field IEF[3] (RW) - * - * Enables the CFF interrupt from the CMP. When this field is set, an interrupt - * will be asserted when CFF is set. - * - * Values: - * - 0 - Interrupt is disabled. - * - 1 - Interrupt is enabled. - */ -/*@{*/ -#define BP_CMP_SCR_IEF (3U) /*!< Bit position for CMP_SCR_IEF. */ -#define BM_CMP_SCR_IEF (0x08U) /*!< Bit mask for CMP_SCR_IEF. */ -#define BS_CMP_SCR_IEF (1U) /*!< Bit field size in bits for CMP_SCR_IEF. */ - -/*! @brief Read current value of the CMP_SCR_IEF field. */ -#define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF)) - -/*! @brief Format value for bitfield CMP_SCR_IEF. */ -#define BF_CMP_SCR_IEF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF) - -/*! @brief Set the IEF field to a new value. */ -#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field IER[4] (RW) - * - * Enables the CFR interrupt from the CMP. When this field is set, an interrupt - * will be asserted when CFR is set. - * - * Values: - * - 0 - Interrupt is disabled. - * - 1 - Interrupt is enabled. - */ -/*@{*/ -#define BP_CMP_SCR_IER (4U) /*!< Bit position for CMP_SCR_IER. */ -#define BM_CMP_SCR_IER (0x10U) /*!< Bit mask for CMP_SCR_IER. */ -#define BS_CMP_SCR_IER (1U) /*!< Bit field size in bits for CMP_SCR_IER. */ - -/*! @brief Read current value of the CMP_SCR_IER field. */ -#define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER)) - -/*! @brief Format value for bitfield CMP_SCR_IER. */ -#define BF_CMP_SCR_IER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER) - -/*! @brief Set the IER field to a new value. */ -#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v)) -/*@}*/ - -/*! - * @name Register CMP_SCR, field DMAEN[6] (RW) - * - * Enables the DMA transfer triggered from the CMP module. When this field is - * set, a DMA request is asserted when CFR or CFF is set. - * - * Values: - * - 0 - DMA is disabled. - * - 1 - DMA is enabled. - */ -/*@{*/ -#define BP_CMP_SCR_DMAEN (6U) /*!< Bit position for CMP_SCR_DMAEN. */ -#define BM_CMP_SCR_DMAEN (0x40U) /*!< Bit mask for CMP_SCR_DMAEN. */ -#define BS_CMP_SCR_DMAEN (1U) /*!< Bit field size in bits for CMP_SCR_DMAEN. */ - -/*! @brief Read current value of the CMP_SCR_DMAEN field. */ -#define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN)) - -/*! @brief Format value for bitfield CMP_SCR_DMAEN. */ -#define BF_CMP_SCR_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_DACCR - DAC Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_DACCR - DAC Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_daccr -{ - uint8_t U; - struct _hw_cmp_daccr_bitfields - { - uint8_t VOSEL : 6; /*!< [5:0] DAC Output Voltage Select */ - uint8_t VRSEL : 1; /*!< [6] Supply Voltage Reference Source Select */ - uint8_t DACEN : 1; /*!< [7] DAC Enable */ - } B; -} hw_cmp_daccr_t; - -/*! - * @name Constants and macros for entire CMP_DACCR register - */ -/*@{*/ -#define HW_CMP_DACCR_ADDR(x) ((x) + 0x4U) - -#define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x)) -#define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U) -#define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v)) -#define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v))) -#define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v))) -#define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_DACCR bitfields - */ - -/*! - * @name Register CMP_DACCR, field VOSEL[5:0] (RW) - * - * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) * - * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in . - */ -/*@{*/ -#define BP_CMP_DACCR_VOSEL (0U) /*!< Bit position for CMP_DACCR_VOSEL. */ -#define BM_CMP_DACCR_VOSEL (0x3FU) /*!< Bit mask for CMP_DACCR_VOSEL. */ -#define BS_CMP_DACCR_VOSEL (6U) /*!< Bit field size in bits for CMP_DACCR_VOSEL. */ - -/*! @brief Read current value of the CMP_DACCR_VOSEL field. */ -#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL) - -/*! @brief Format value for bitfield CMP_DACCR_VOSEL. */ -#define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL) - -/*! @brief Set the VOSEL field to a new value. */ -#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v))) -/*@}*/ - -/*! - * @name Register CMP_DACCR, field VRSEL[6] (RW) - * - * Values: - * - 0 - V is selected as resistor ladder network supply reference V. in1 in - * - 1 - V is selected as resistor ladder network supply reference V. in2 in - */ -/*@{*/ -#define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */ -#define BM_CMP_DACCR_VRSEL (0x40U) /*!< Bit mask for CMP_DACCR_VRSEL. */ -#define BS_CMP_DACCR_VRSEL (1U) /*!< Bit field size in bits for CMP_DACCR_VRSEL. */ - -/*! @brief Read current value of the CMP_DACCR_VRSEL field. */ -#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL)) - -/*! @brief Format value for bitfield CMP_DACCR_VRSEL. */ -#define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL) - -/*! @brief Set the VRSEL field to a new value. */ -#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v)) -/*@}*/ - -/*! - * @name Register CMP_DACCR, field DACEN[7] (RW) - * - * Enables the DAC. When the DAC is disabled, it is powered down to conserve - * power. - * - * Values: - * - 0 - DAC is disabled. - * - 1 - DAC is enabled. - */ -/*@{*/ -#define BP_CMP_DACCR_DACEN (7U) /*!< Bit position for CMP_DACCR_DACEN. */ -#define BM_CMP_DACCR_DACEN (0x80U) /*!< Bit mask for CMP_DACCR_DACEN. */ -#define BS_CMP_DACCR_DACEN (1U) /*!< Bit field size in bits for CMP_DACCR_DACEN. */ - -/*! @brief Read current value of the CMP_DACCR_DACEN field. */ -#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN)) - -/*! @brief Format value for bitfield CMP_DACCR_DACEN. */ -#define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN) - -/*! @brief Set the DACEN field to a new value. */ -#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMP_MUXCR - MUX Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMP_MUXCR - MUX Control Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_cmp_muxcr -{ - uint8_t U; - struct _hw_cmp_muxcr_bitfields - { - uint8_t MSEL : 3; /*!< [2:0] Minus Input Mux Control */ - uint8_t PSEL : 3; /*!< [5:3] Plus Input Mux Control */ - uint8_t RESERVED0 : 1; /*!< [6] */ - uint8_t PSTM : 1; /*!< [7] Pass Through Mode Enable */ - } B; -} hw_cmp_muxcr_t; - -/*! - * @name Constants and macros for entire CMP_MUXCR register - */ -/*@{*/ -#define HW_CMP_MUXCR_ADDR(x) ((x) + 0x5U) - -#define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x)) -#define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U) -#define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v)) -#define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v))) -#define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v))) -#define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMP_MUXCR bitfields - */ - -/*! - * @name Register CMP_MUXCR, field MSEL[2:0] (RW) - * - * Determines which input is selected for the minus input of the comparator. For - * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate - * operation selects the same input for both muxes, the comparator automatically - * shuts down to prevent itself from becoming a noise generator. - * - * Values: - * - 000 - IN0 - * - 001 - IN1 - * - 010 - IN2 - * - 011 - IN3 - * - 100 - IN4 - * - 101 - IN5 - * - 110 - IN6 - * - 111 - IN7 - */ -/*@{*/ -#define BP_CMP_MUXCR_MSEL (0U) /*!< Bit position for CMP_MUXCR_MSEL. */ -#define BM_CMP_MUXCR_MSEL (0x07U) /*!< Bit mask for CMP_MUXCR_MSEL. */ -#define BS_CMP_MUXCR_MSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_MSEL. */ - -/*! @brief Read current value of the CMP_MUXCR_MSEL field. */ -#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL) - -/*! @brief Format value for bitfield CMP_MUXCR_MSEL. */ -#define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL) - -/*! @brief Set the MSEL field to a new value. */ -#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v))) -/*@}*/ - -/*! - * @name Register CMP_MUXCR, field PSEL[5:3] (RW) - * - * Determines which input is selected for the plus input of the comparator. For - * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate - * operation selects the same input for both muxes, the comparator automatically - * shuts down to prevent itself from becoming a noise generator. - * - * Values: - * - 000 - IN0 - * - 001 - IN1 - * - 010 - IN2 - * - 011 - IN3 - * - 100 - IN4 - * - 101 - IN5 - * - 110 - IN6 - * - 111 - IN7 - */ -/*@{*/ -#define BP_CMP_MUXCR_PSEL (3U) /*!< Bit position for CMP_MUXCR_PSEL. */ -#define BM_CMP_MUXCR_PSEL (0x38U) /*!< Bit mask for CMP_MUXCR_PSEL. */ -#define BS_CMP_MUXCR_PSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_PSEL. */ - -/*! @brief Read current value of the CMP_MUXCR_PSEL field. */ -#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL) - -/*! @brief Format value for bitfield CMP_MUXCR_PSEL. */ -#define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL) - -/*! @brief Set the PSEL field to a new value. */ -#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v))) -/*@}*/ - -/*! - * @name Register CMP_MUXCR, field PSTM[7] (RW) - * - * This bit is used to enable to MUX pass through mode. Pass through mode is - * always available but for some devices this feature must be always disabled due to - * the lack of package pins. - * - * Values: - * - 0 - Pass Through Mode is disabled. - * - 1 - Pass Through Mode is enabled. - */ -/*@{*/ -#define BP_CMP_MUXCR_PSTM (7U) /*!< Bit position for CMP_MUXCR_PSTM. */ -#define BM_CMP_MUXCR_PSTM (0x80U) /*!< Bit mask for CMP_MUXCR_PSTM. */ -#define BS_CMP_MUXCR_PSTM (1U) /*!< Bit field size in bits for CMP_MUXCR_PSTM. */ - -/*! @brief Read current value of the CMP_MUXCR_PSTM field. */ -#define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM)) - -/*! @brief Format value for bitfield CMP_MUXCR_PSTM. */ -#define BF_CMP_MUXCR_PSTM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSTM) & BM_CMP_MUXCR_PSTM) - -/*! @brief Set the PSTM field to a new value. */ -#define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_cmp_t - module struct - ******************************************************************************/ -/*! - * @brief All CMP module registers. - */ -#pragma pack(1) -typedef struct _hw_cmp -{ - __IO hw_cmp_cr0_t CR0; /*!< [0x0] CMP Control Register 0 */ - __IO hw_cmp_cr1_t CR1; /*!< [0x1] CMP Control Register 1 */ - __IO hw_cmp_fpr_t FPR; /*!< [0x2] CMP Filter Period Register */ - __IO hw_cmp_scr_t SCR; /*!< [0x3] CMP Status and Control Register */ - __IO hw_cmp_daccr_t DACCR; /*!< [0x4] DAC Control Register */ - __IO hw_cmp_muxcr_t MUXCR; /*!< [0x5] MUX Control Register */ -} hw_cmp_t; -#pragma pack() - -/*! @brief Macro to access all CMP registers. */ -/*! @param x CMP module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CMP(CMP0_BASE). */ -#define HW_CMP(x) (*(hw_cmp_t *)(x)) - -#endif /* __HW_CMP_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmt.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmt.h deleted file mode 100644 index 66df1fc89e0..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmt.h +++ /dev/null @@ -1,1120 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CMT_REGISTERS_H__ -#define __HW_CMT_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 CMT - * - * Carrier Modulator Transmitter - * - * Registers defined in this header file: - * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 - * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 - * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 - * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 - * - HW_CMT_OC - CMT Output Control Register - * - HW_CMT_MSC - CMT Modulator Status and Control Register - * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High - * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low - * - HW_CMT_CMD3 - CMT Modulator Data Register Space High - * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low - * - HW_CMT_PPS - CMT Primary Prescaler Register - * - HW_CMT_DMA - CMT Direct Memory Access Register - * - * - hw_cmt_t - Struct containing all module registers. - */ - -#define HW_CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */ - -/******************************************************************************* - * HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 - ******************************************************************************/ - -/*! - * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW) - * - * Reset value: 0x00U - * - * This data register contains the primary high value for generating the carrier - * output. - */ -typedef union _hw_cmt_cgh1 -{ - uint8_t U; - struct _hw_cmt_cgh1_bitfields - { - uint8_t PH : 8; /*!< [7:0] Primary Carrier High Time Data Value */ - } B; -} hw_cmt_cgh1_t; - -/*! - * @name Constants and macros for entire CMT_CGH1 register - */ -/*@{*/ -#define HW_CMT_CGH1_ADDR(x) ((x) + 0x0U) - -#define HW_CMT_CGH1(x) (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR(x)) -#define HW_CMT_CGH1_RD(x) (HW_CMT_CGH1(x).U) -#define HW_CMT_CGH1_WR(x, v) (HW_CMT_CGH1(x).U = (v)) -#define HW_CMT_CGH1_SET(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) | (v))) -#define HW_CMT_CGH1_CLR(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) & ~(v))) -#define HW_CMT_CGH1_TOG(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CGH1 bitfields - */ - -/*! - * @name Register CMT_CGH1, field PH[7:0] (RW) - * - * Contains the number of input clocks required to generate the carrier high - * time period. When operating in Time mode, this register is always selected. When - * operating in FSK mode, this register and the secondary register pair are - * alternately selected under the control of the modulator. The primary carrier high - * time value is undefined out of reset. This register must be written to nonzero - * values before the carrier generator is enabled to avoid spurious results. - */ -/*@{*/ -#define BP_CMT_CGH1_PH (0U) /*!< Bit position for CMT_CGH1_PH. */ -#define BM_CMT_CGH1_PH (0xFFU) /*!< Bit mask for CMT_CGH1_PH. */ -#define BS_CMT_CGH1_PH (8U) /*!< Bit field size in bits for CMT_CGH1_PH. */ - -/*! @brief Read current value of the CMT_CGH1_PH field. */ -#define BR_CMT_CGH1_PH(x) (HW_CMT_CGH1(x).U) - -/*! @brief Format value for bitfield CMT_CGH1_PH. */ -#define BF_CMT_CGH1_PH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH1_PH) & BM_CMT_CGH1_PH) - -/*! @brief Set the PH field to a new value. */ -#define BW_CMT_CGH1_PH(x, v) (HW_CMT_CGH1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 - ******************************************************************************/ - -/*! - * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW) - * - * Reset value: 0x00U - * - * This data register contains the primary low value for generating the carrier - * output. - */ -typedef union _hw_cmt_cgl1 -{ - uint8_t U; - struct _hw_cmt_cgl1_bitfields - { - uint8_t PL : 8; /*!< [7:0] Primary Carrier Low Time Data Value */ - } B; -} hw_cmt_cgl1_t; - -/*! - * @name Constants and macros for entire CMT_CGL1 register - */ -/*@{*/ -#define HW_CMT_CGL1_ADDR(x) ((x) + 0x1U) - -#define HW_CMT_CGL1(x) (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR(x)) -#define HW_CMT_CGL1_RD(x) (HW_CMT_CGL1(x).U) -#define HW_CMT_CGL1_WR(x, v) (HW_CMT_CGL1(x).U = (v)) -#define HW_CMT_CGL1_SET(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) | (v))) -#define HW_CMT_CGL1_CLR(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) & ~(v))) -#define HW_CMT_CGL1_TOG(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CGL1 bitfields - */ - -/*! - * @name Register CMT_CGL1, field PL[7:0] (RW) - * - * Contains the number of input clocks required to generate the carrier low time - * period. When operating in Time mode, this register is always selected. When - * operating in FSK mode, this register and the secondary register pair are - * alternately selected under the control of the modulator. The primary carrier low - * time value is undefined out of reset. This register must be written to nonzero - * values before the carrier generator is enabled to avoid spurious results. - */ -/*@{*/ -#define BP_CMT_CGL1_PL (0U) /*!< Bit position for CMT_CGL1_PL. */ -#define BM_CMT_CGL1_PL (0xFFU) /*!< Bit mask for CMT_CGL1_PL. */ -#define BS_CMT_CGL1_PL (8U) /*!< Bit field size in bits for CMT_CGL1_PL. */ - -/*! @brief Read current value of the CMT_CGL1_PL field. */ -#define BR_CMT_CGL1_PL(x) (HW_CMT_CGL1(x).U) - -/*! @brief Format value for bitfield CMT_CGL1_PL. */ -#define BF_CMT_CGL1_PL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL1_PL) & BM_CMT_CGL1_PL) - -/*! @brief Set the PL field to a new value. */ -#define BW_CMT_CGL1_PL(x, v) (HW_CMT_CGL1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 - ******************************************************************************/ - -/*! - * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW) - * - * Reset value: 0x00U - * - * This data register contains the secondary high value for generating the - * carrier output. - */ -typedef union _hw_cmt_cgh2 -{ - uint8_t U; - struct _hw_cmt_cgh2_bitfields - { - uint8_t SH : 8; /*!< [7:0] Secondary Carrier High Time Data Value */ - } B; -} hw_cmt_cgh2_t; - -/*! - * @name Constants and macros for entire CMT_CGH2 register - */ -/*@{*/ -#define HW_CMT_CGH2_ADDR(x) ((x) + 0x2U) - -#define HW_CMT_CGH2(x) (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR(x)) -#define HW_CMT_CGH2_RD(x) (HW_CMT_CGH2(x).U) -#define HW_CMT_CGH2_WR(x, v) (HW_CMT_CGH2(x).U = (v)) -#define HW_CMT_CGH2_SET(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) | (v))) -#define HW_CMT_CGH2_CLR(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) & ~(v))) -#define HW_CMT_CGH2_TOG(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CGH2 bitfields - */ - -/*! - * @name Register CMT_CGH2, field SH[7:0] (RW) - * - * Contains the number of input clocks required to generate the carrier high - * time period. When operating in Time mode, this register is never selected. When - * operating in FSK mode, this register and the primary register pair are - * alternately selected under control of the modulator. The secondary carrier high time - * value is undefined out of reset. This register must be written to nonzero - * values before the carrier generator is enabled when operating in FSK mode. - */ -/*@{*/ -#define BP_CMT_CGH2_SH (0U) /*!< Bit position for CMT_CGH2_SH. */ -#define BM_CMT_CGH2_SH (0xFFU) /*!< Bit mask for CMT_CGH2_SH. */ -#define BS_CMT_CGH2_SH (8U) /*!< Bit field size in bits for CMT_CGH2_SH. */ - -/*! @brief Read current value of the CMT_CGH2_SH field. */ -#define BR_CMT_CGH2_SH(x) (HW_CMT_CGH2(x).U) - -/*! @brief Format value for bitfield CMT_CGH2_SH. */ -#define BF_CMT_CGH2_SH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH2_SH) & BM_CMT_CGH2_SH) - -/*! @brief Set the SH field to a new value. */ -#define BW_CMT_CGH2_SH(x, v) (HW_CMT_CGH2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 - ******************************************************************************/ - -/*! - * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW) - * - * Reset value: 0x00U - * - * This data register contains the secondary low value for generating the - * carrier output. - */ -typedef union _hw_cmt_cgl2 -{ - uint8_t U; - struct _hw_cmt_cgl2_bitfields - { - uint8_t SL : 8; /*!< [7:0] Secondary Carrier Low Time Data Value */ - } B; -} hw_cmt_cgl2_t; - -/*! - * @name Constants and macros for entire CMT_CGL2 register - */ -/*@{*/ -#define HW_CMT_CGL2_ADDR(x) ((x) + 0x3U) - -#define HW_CMT_CGL2(x) (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR(x)) -#define HW_CMT_CGL2_RD(x) (HW_CMT_CGL2(x).U) -#define HW_CMT_CGL2_WR(x, v) (HW_CMT_CGL2(x).U = (v)) -#define HW_CMT_CGL2_SET(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) | (v))) -#define HW_CMT_CGL2_CLR(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) & ~(v))) -#define HW_CMT_CGL2_TOG(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CGL2 bitfields - */ - -/*! - * @name Register CMT_CGL2, field SL[7:0] (RW) - * - * Contains the number of input clocks required to generate the carrier low time - * period. When operating in Time mode, this register is never selected. When - * operating in FSK mode, this register and the primary register pair are - * alternately selected under the control of the modulator. The secondary carrier low time - * value is undefined out of reset. This register must be written to nonzero - * values before the carrier generator is enabled when operating in FSK mode. - */ -/*@{*/ -#define BP_CMT_CGL2_SL (0U) /*!< Bit position for CMT_CGL2_SL. */ -#define BM_CMT_CGL2_SL (0xFFU) /*!< Bit mask for CMT_CGL2_SL. */ -#define BS_CMT_CGL2_SL (8U) /*!< Bit field size in bits for CMT_CGL2_SL. */ - -/*! @brief Read current value of the CMT_CGL2_SL field. */ -#define BR_CMT_CGL2_SL(x) (HW_CMT_CGL2(x).U) - -/*! @brief Format value for bitfield CMT_CGL2_SL. */ -#define BF_CMT_CGL2_SL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL2_SL) & BM_CMT_CGL2_SL) - -/*! @brief Set the SL field to a new value. */ -#define BW_CMT_CGL2_SL(x, v) (HW_CMT_CGL2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_OC - CMT Output Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMT_OC - CMT Output Control Register (RW) - * - * Reset value: 0x00U - * - * This register is used to control the IRO signal of the CMT module. - */ -typedef union _hw_cmt_oc -{ - uint8_t U; - struct _hw_cmt_oc_bitfields - { - uint8_t RESERVED0 : 5; /*!< [4:0] */ - uint8_t IROPEN : 1; /*!< [5] IRO Pin Enable */ - uint8_t CMTPOL : 1; /*!< [6] CMT Output Polarity */ - uint8_t IROL : 1; /*!< [7] IRO Latch Control */ - } B; -} hw_cmt_oc_t; - -/*! - * @name Constants and macros for entire CMT_OC register - */ -/*@{*/ -#define HW_CMT_OC_ADDR(x) ((x) + 0x4U) - -#define HW_CMT_OC(x) (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR(x)) -#define HW_CMT_OC_RD(x) (HW_CMT_OC(x).U) -#define HW_CMT_OC_WR(x, v) (HW_CMT_OC(x).U = (v)) -#define HW_CMT_OC_SET(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) | (v))) -#define HW_CMT_OC_CLR(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) & ~(v))) -#define HW_CMT_OC_TOG(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_OC bitfields - */ - -/*! - * @name Register CMT_OC, field IROPEN[5] (RW) - * - * Enables and disables the IRO signal. When the IRO signal is enabled, it is an - * output that drives out either the CMT transmitter output or the state of IROL - * depending on whether MSC[MCGEN] is set or not. Also, the state of output is - * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO - * signal is disabled, it is in a high-impedance state and is unable to draw any - * current. This signal is disabled during reset. - * - * Values: - * - 0 - The IRO signal is disabled. - * - 1 - The IRO signal is enabled as output. - */ -/*@{*/ -#define BP_CMT_OC_IROPEN (5U) /*!< Bit position for CMT_OC_IROPEN. */ -#define BM_CMT_OC_IROPEN (0x20U) /*!< Bit mask for CMT_OC_IROPEN. */ -#define BS_CMT_OC_IROPEN (1U) /*!< Bit field size in bits for CMT_OC_IROPEN. */ - -/*! @brief Read current value of the CMT_OC_IROPEN field. */ -#define BR_CMT_OC_IROPEN(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN)) - -/*! @brief Format value for bitfield CMT_OC_IROPEN. */ -#define BF_CMT_OC_IROPEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROPEN) & BM_CMT_OC_IROPEN) - -/*! @brief Set the IROPEN field to a new value. */ -#define BW_CMT_OC_IROPEN(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN) = (v)) -/*@}*/ - -/*! - * @name Register CMT_OC, field CMTPOL[6] (RW) - * - * Controls the polarity of the IRO signal. - * - * Values: - * - 0 - The IRO signal is active-low. - * - 1 - The IRO signal is active-high. - */ -/*@{*/ -#define BP_CMT_OC_CMTPOL (6U) /*!< Bit position for CMT_OC_CMTPOL. */ -#define BM_CMT_OC_CMTPOL (0x40U) /*!< Bit mask for CMT_OC_CMTPOL. */ -#define BS_CMT_OC_CMTPOL (1U) /*!< Bit field size in bits for CMT_OC_CMTPOL. */ - -/*! @brief Read current value of the CMT_OC_CMTPOL field. */ -#define BR_CMT_OC_CMTPOL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL)) - -/*! @brief Format value for bitfield CMT_OC_CMTPOL. */ -#define BF_CMT_OC_CMTPOL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_CMTPOL) & BM_CMT_OC_CMTPOL) - -/*! @brief Set the CMTPOL field to a new value. */ -#define BW_CMT_OC_CMTPOL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL) = (v)) -/*@}*/ - -/*! - * @name Register CMT_OC, field IROL[7] (RW) - * - * Reads the state of the IRO latch. Writing to IROL changes the state of the - * IRO signal when MSC[MCGEN] is cleared and IROPEN is set. - */ -/*@{*/ -#define BP_CMT_OC_IROL (7U) /*!< Bit position for CMT_OC_IROL. */ -#define BM_CMT_OC_IROL (0x80U) /*!< Bit mask for CMT_OC_IROL. */ -#define BS_CMT_OC_IROL (1U) /*!< Bit field size in bits for CMT_OC_IROL. */ - -/*! @brief Read current value of the CMT_OC_IROL field. */ -#define BR_CMT_OC_IROL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL)) - -/*! @brief Format value for bitfield CMT_OC_IROL. */ -#define BF_CMT_OC_IROL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROL) & BM_CMT_OC_IROL) - -/*! @brief Set the IROL field to a new value. */ -#define BW_CMT_OC_IROL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_MSC - CMT Modulator Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW) - * - * Reset value: 0x00U - * - * This register contains the modulator and carrier generator enable (MCGEN), - * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable - * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle - * (EOCF) status bit. - */ -typedef union _hw_cmt_msc -{ - uint8_t U; - struct _hw_cmt_msc_bitfields - { - uint8_t MCGEN : 1; /*!< [0] Modulator and Carrier Generator Enable */ - uint8_t EOCIE : 1; /*!< [1] End of Cycle Interrupt Enable */ - uint8_t FSK : 1; /*!< [2] FSK Mode Select */ - uint8_t BASE : 1; /*!< [3] Baseband Enable */ - uint8_t EXSPC : 1; /*!< [4] Extended Space Enable */ - uint8_t CMTDIV : 2; /*!< [6:5] CMT Clock Divide Prescaler */ - uint8_t EOCF : 1; /*!< [7] End Of Cycle Status Flag */ - } B; -} hw_cmt_msc_t; - -/*! - * @name Constants and macros for entire CMT_MSC register - */ -/*@{*/ -#define HW_CMT_MSC_ADDR(x) ((x) + 0x5U) - -#define HW_CMT_MSC(x) (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR(x)) -#define HW_CMT_MSC_RD(x) (HW_CMT_MSC(x).U) -#define HW_CMT_MSC_WR(x, v) (HW_CMT_MSC(x).U = (v)) -#define HW_CMT_MSC_SET(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) | (v))) -#define HW_CMT_MSC_CLR(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) & ~(v))) -#define HW_CMT_MSC_TOG(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_MSC bitfields - */ - -/*! - * @name Register CMT_MSC, field MCGEN[0] (RW) - * - * Setting MCGEN will initialize the carrier generator and modulator and will - * enable all clocks. When enabled, the carrier generator and modulator will - * function continuously. When MCGEN is cleared, the current modulator cycle will be - * allowed to expire before all carrier and modulator clocks are disabled to save - * power and the modulator output is forced low. To prevent spurious operation, - * the user should initialize all data and control registers before enabling the - * system. - * - * Values: - * - 0 - Modulator and carrier generator disabled - * - 1 - Modulator and carrier generator enabled - */ -/*@{*/ -#define BP_CMT_MSC_MCGEN (0U) /*!< Bit position for CMT_MSC_MCGEN. */ -#define BM_CMT_MSC_MCGEN (0x01U) /*!< Bit mask for CMT_MSC_MCGEN. */ -#define BS_CMT_MSC_MCGEN (1U) /*!< Bit field size in bits for CMT_MSC_MCGEN. */ - -/*! @brief Read current value of the CMT_MSC_MCGEN field. */ -#define BR_CMT_MSC_MCGEN(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN)) - -/*! @brief Format value for bitfield CMT_MSC_MCGEN. */ -#define BF_CMT_MSC_MCGEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_MCGEN) & BM_CMT_MSC_MCGEN) - -/*! @brief Set the MCGEN field to a new value. */ -#define BW_CMT_MSC_MCGEN(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN) = (v)) -/*@}*/ - -/*! - * @name Register CMT_MSC, field EOCIE[1] (RW) - * - * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high. - * - * Values: - * - 0 - CPU interrupt is disabled. - * - 1 - CPU interrupt is enabled. - */ -/*@{*/ -#define BP_CMT_MSC_EOCIE (1U) /*!< Bit position for CMT_MSC_EOCIE. */ -#define BM_CMT_MSC_EOCIE (0x02U) /*!< Bit mask for CMT_MSC_EOCIE. */ -#define BS_CMT_MSC_EOCIE (1U) /*!< Bit field size in bits for CMT_MSC_EOCIE. */ - -/*! @brief Read current value of the CMT_MSC_EOCIE field. */ -#define BR_CMT_MSC_EOCIE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE)) - -/*! @brief Format value for bitfield CMT_MSC_EOCIE. */ -#define BF_CMT_MSC_EOCIE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EOCIE) & BM_CMT_MSC_EOCIE) - -/*! @brief Set the EOCIE field to a new value. */ -#define BW_CMT_MSC_EOCIE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE) = (v)) -/*@}*/ - -/*! - * @name Register CMT_MSC, field FSK[2] (RW) - * - * Enables FSK operation. - * - * Values: - * - 0 - The CMT operates in Time or Baseband mode. - * - 1 - The CMT operates in FSK mode. - */ -/*@{*/ -#define BP_CMT_MSC_FSK (2U) /*!< Bit position for CMT_MSC_FSK. */ -#define BM_CMT_MSC_FSK (0x04U) /*!< Bit mask for CMT_MSC_FSK. */ -#define BS_CMT_MSC_FSK (1U) /*!< Bit field size in bits for CMT_MSC_FSK. */ - -/*! @brief Read current value of the CMT_MSC_FSK field. */ -#define BR_CMT_MSC_FSK(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK)) - -/*! @brief Format value for bitfield CMT_MSC_FSK. */ -#define BF_CMT_MSC_FSK(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_FSK) & BM_CMT_MSC_FSK) - -/*! @brief Set the FSK field to a new value. */ -#define BW_CMT_MSC_FSK(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK) = (v)) -/*@}*/ - -/*! - * @name Register CMT_MSC, field BASE[3] (RW) - * - * When set, BASE disables the carrier generator and forces the carrier output - * high for generation of baseband protocols. When BASE is cleared, the carrier - * generator is enabled and the carrier output toggles at the frequency determined - * by values stored in the carrier data registers. This field is cleared by - * reset. This field is not double-buffered and must not be written to during a - * transmission. - * - * Values: - * - 0 - Baseband mode is disabled. - * - 1 - Baseband mode is enabled. - */ -/*@{*/ -#define BP_CMT_MSC_BASE (3U) /*!< Bit position for CMT_MSC_BASE. */ -#define BM_CMT_MSC_BASE (0x08U) /*!< Bit mask for CMT_MSC_BASE. */ -#define BS_CMT_MSC_BASE (1U) /*!< Bit field size in bits for CMT_MSC_BASE. */ - -/*! @brief Read current value of the CMT_MSC_BASE field. */ -#define BR_CMT_MSC_BASE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE)) - -/*! @brief Format value for bitfield CMT_MSC_BASE. */ -#define BF_CMT_MSC_BASE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_BASE) & BM_CMT_MSC_BASE) - -/*! @brief Set the BASE field to a new value. */ -#define BW_CMT_MSC_BASE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE) = (v)) -/*@}*/ - -/*! - * @name Register CMT_MSC, field EXSPC[4] (RW) - * - * Enables the extended space operation. - * - * Values: - * - 0 - Extended space is disabled. - * - 1 - Extended space is enabled. - */ -/*@{*/ -#define BP_CMT_MSC_EXSPC (4U) /*!< Bit position for CMT_MSC_EXSPC. */ -#define BM_CMT_MSC_EXSPC (0x10U) /*!< Bit mask for CMT_MSC_EXSPC. */ -#define BS_CMT_MSC_EXSPC (1U) /*!< Bit field size in bits for CMT_MSC_EXSPC. */ - -/*! @brief Read current value of the CMT_MSC_EXSPC field. */ -#define BR_CMT_MSC_EXSPC(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC)) - -/*! @brief Format value for bitfield CMT_MSC_EXSPC. */ -#define BF_CMT_MSC_EXSPC(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EXSPC) & BM_CMT_MSC_EXSPC) - -/*! @brief Set the EXSPC field to a new value. */ -#define BW_CMT_MSC_EXSPC(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC) = (v)) -/*@}*/ - -/*! - * @name Register CMT_MSC, field CMTDIV[6:5] (RW) - * - * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency - * divided by 2 ,4, or 8 . This field must not be changed during a transmission - * because it is not double-buffered. - * - * Values: - * - 00 - IF * 1 - * - 01 - IF * 2 - * - 10 - IF * 4 - * - 11 - IF * 8 - */ -/*@{*/ -#define BP_CMT_MSC_CMTDIV (5U) /*!< Bit position for CMT_MSC_CMTDIV. */ -#define BM_CMT_MSC_CMTDIV (0x60U) /*!< Bit mask for CMT_MSC_CMTDIV. */ -#define BS_CMT_MSC_CMTDIV (2U) /*!< Bit field size in bits for CMT_MSC_CMTDIV. */ - -/*! @brief Read current value of the CMT_MSC_CMTDIV field. */ -#define BR_CMT_MSC_CMTDIV(x) (HW_CMT_MSC(x).B.CMTDIV) - -/*! @brief Format value for bitfield CMT_MSC_CMTDIV. */ -#define BF_CMT_MSC_CMTDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_CMTDIV) & BM_CMT_MSC_CMTDIV) - -/*! @brief Set the CMTDIV field to a new value. */ -#define BW_CMT_MSC_CMTDIV(x, v) (HW_CMT_MSC_WR(x, (HW_CMT_MSC_RD(x) & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v))) -/*@}*/ - -/*! - * @name Register CMT_MSC, field EOCF[7] (RO) - * - * Sets when: The modulator is not currently active and MCGEN is set to begin - * the initial CMT transmission. At the end of each modulation cycle while MCGEN is - * set. This is recognized when a match occurs between the contents of the space - * period register and the down counter. At this time, the counter is - * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and - * the space period register is loaded with, possibly new contents of the space - * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an - * access of CMD2 or CMD4, or by the DMA transfer. - * - * Values: - * - 0 - End of modulation cycle has not occured since the flag last cleared. - * - 1 - End of modulator cycle has occurred. - */ -/*@{*/ -#define BP_CMT_MSC_EOCF (7U) /*!< Bit position for CMT_MSC_EOCF. */ -#define BM_CMT_MSC_EOCF (0x80U) /*!< Bit mask for CMT_MSC_EOCF. */ -#define BS_CMT_MSC_EOCF (1U) /*!< Bit field size in bits for CMT_MSC_EOCF. */ - -/*! @brief Read current value of the CMT_MSC_EOCF field. */ -#define BR_CMT_MSC_EOCF(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCF)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CMD1 - CMT Modulator Data Register Mark High - ******************************************************************************/ - -/*! - * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW) - * - * Reset value: 0x00U - * - * The contents of this register are transferred to the modulator down counter - * upon the completion of a modulation period. - */ -typedef union _hw_cmt_cmd1 -{ - uint8_t U; - struct _hw_cmt_cmd1_bitfields - { - uint8_t MB : 8; /*!< [7:0] */ - } B; -} hw_cmt_cmd1_t; - -/*! - * @name Constants and macros for entire CMT_CMD1 register - */ -/*@{*/ -#define HW_CMT_CMD1_ADDR(x) ((x) + 0x6U) - -#define HW_CMT_CMD1(x) (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR(x)) -#define HW_CMT_CMD1_RD(x) (HW_CMT_CMD1(x).U) -#define HW_CMT_CMD1_WR(x, v) (HW_CMT_CMD1(x).U = (v)) -#define HW_CMT_CMD1_SET(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) | (v))) -#define HW_CMT_CMD1_CLR(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) & ~(v))) -#define HW_CMT_CMD1_TOG(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CMD1 bitfields - */ - -/*! - * @name Register CMT_CMD1, field MB[7:0] (RW) - * - * Controls the upper mark periods of the modulator for all modes. - */ -/*@{*/ -#define BP_CMT_CMD1_MB (0U) /*!< Bit position for CMT_CMD1_MB. */ -#define BM_CMT_CMD1_MB (0xFFU) /*!< Bit mask for CMT_CMD1_MB. */ -#define BS_CMT_CMD1_MB (8U) /*!< Bit field size in bits for CMT_CMD1_MB. */ - -/*! @brief Read current value of the CMT_CMD1_MB field. */ -#define BR_CMT_CMD1_MB(x) (HW_CMT_CMD1(x).U) - -/*! @brief Format value for bitfield CMT_CMD1_MB. */ -#define BF_CMT_CMD1_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD1_MB) & BM_CMT_CMD1_MB) - -/*! @brief Set the MB field to a new value. */ -#define BW_CMT_CMD1_MB(x, v) (HW_CMT_CMD1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CMD2 - CMT Modulator Data Register Mark Low - ******************************************************************************/ - -/*! - * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW) - * - * Reset value: 0x00U - * - * The contents of this register are transferred to the modulator down counter - * upon the completion of a modulation period. - */ -typedef union _hw_cmt_cmd2 -{ - uint8_t U; - struct _hw_cmt_cmd2_bitfields - { - uint8_t MB : 8; /*!< [7:0] */ - } B; -} hw_cmt_cmd2_t; - -/*! - * @name Constants and macros for entire CMT_CMD2 register - */ -/*@{*/ -#define HW_CMT_CMD2_ADDR(x) ((x) + 0x7U) - -#define HW_CMT_CMD2(x) (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR(x)) -#define HW_CMT_CMD2_RD(x) (HW_CMT_CMD2(x).U) -#define HW_CMT_CMD2_WR(x, v) (HW_CMT_CMD2(x).U = (v)) -#define HW_CMT_CMD2_SET(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) | (v))) -#define HW_CMT_CMD2_CLR(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) & ~(v))) -#define HW_CMT_CMD2_TOG(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CMD2 bitfields - */ - -/*! - * @name Register CMT_CMD2, field MB[7:0] (RW) - * - * Controls the lower mark periods of the modulator for all modes. - */ -/*@{*/ -#define BP_CMT_CMD2_MB (0U) /*!< Bit position for CMT_CMD2_MB. */ -#define BM_CMT_CMD2_MB (0xFFU) /*!< Bit mask for CMT_CMD2_MB. */ -#define BS_CMT_CMD2_MB (8U) /*!< Bit field size in bits for CMT_CMD2_MB. */ - -/*! @brief Read current value of the CMT_CMD2_MB field. */ -#define BR_CMT_CMD2_MB(x) (HW_CMT_CMD2(x).U) - -/*! @brief Format value for bitfield CMT_CMD2_MB. */ -#define BF_CMT_CMD2_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD2_MB) & BM_CMT_CMD2_MB) - -/*! @brief Set the MB field to a new value. */ -#define BW_CMT_CMD2_MB(x, v) (HW_CMT_CMD2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CMD3 - CMT Modulator Data Register Space High - ******************************************************************************/ - -/*! - * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW) - * - * Reset value: 0x00U - * - * The contents of this register are transferred to the space period register - * upon the completion of a modulation period. - */ -typedef union _hw_cmt_cmd3 -{ - uint8_t U; - struct _hw_cmt_cmd3_bitfields - { - uint8_t SB : 8; /*!< [7:0] */ - } B; -} hw_cmt_cmd3_t; - -/*! - * @name Constants and macros for entire CMT_CMD3 register - */ -/*@{*/ -#define HW_CMT_CMD3_ADDR(x) ((x) + 0x8U) - -#define HW_CMT_CMD3(x) (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR(x)) -#define HW_CMT_CMD3_RD(x) (HW_CMT_CMD3(x).U) -#define HW_CMT_CMD3_WR(x, v) (HW_CMT_CMD3(x).U = (v)) -#define HW_CMT_CMD3_SET(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) | (v))) -#define HW_CMT_CMD3_CLR(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) & ~(v))) -#define HW_CMT_CMD3_TOG(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CMD3 bitfields - */ - -/*! - * @name Register CMT_CMD3, field SB[7:0] (RW) - * - * Controls the upper space periods of the modulator for all modes. - */ -/*@{*/ -#define BP_CMT_CMD3_SB (0U) /*!< Bit position for CMT_CMD3_SB. */ -#define BM_CMT_CMD3_SB (0xFFU) /*!< Bit mask for CMT_CMD3_SB. */ -#define BS_CMT_CMD3_SB (8U) /*!< Bit field size in bits for CMT_CMD3_SB. */ - -/*! @brief Read current value of the CMT_CMD3_SB field. */ -#define BR_CMT_CMD3_SB(x) (HW_CMT_CMD3(x).U) - -/*! @brief Format value for bitfield CMT_CMD3_SB. */ -#define BF_CMT_CMD3_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD3_SB) & BM_CMT_CMD3_SB) - -/*! @brief Set the SB field to a new value. */ -#define BW_CMT_CMD3_SB(x, v) (HW_CMT_CMD3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_CMD4 - CMT Modulator Data Register Space Low - ******************************************************************************/ - -/*! - * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW) - * - * Reset value: 0x00U - * - * The contents of this register are transferred to the space period register - * upon the completion of a modulation period. - */ -typedef union _hw_cmt_cmd4 -{ - uint8_t U; - struct _hw_cmt_cmd4_bitfields - { - uint8_t SB : 8; /*!< [7:0] */ - } B; -} hw_cmt_cmd4_t; - -/*! - * @name Constants and macros for entire CMT_CMD4 register - */ -/*@{*/ -#define HW_CMT_CMD4_ADDR(x) ((x) + 0x9U) - -#define HW_CMT_CMD4(x) (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR(x)) -#define HW_CMT_CMD4_RD(x) (HW_CMT_CMD4(x).U) -#define HW_CMT_CMD4_WR(x, v) (HW_CMT_CMD4(x).U = (v)) -#define HW_CMT_CMD4_SET(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) | (v))) -#define HW_CMT_CMD4_CLR(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) & ~(v))) -#define HW_CMT_CMD4_TOG(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_CMD4 bitfields - */ - -/*! - * @name Register CMT_CMD4, field SB[7:0] (RW) - * - * Controls the lower space periods of the modulator for all modes. - */ -/*@{*/ -#define BP_CMT_CMD4_SB (0U) /*!< Bit position for CMT_CMD4_SB. */ -#define BM_CMT_CMD4_SB (0xFFU) /*!< Bit mask for CMT_CMD4_SB. */ -#define BS_CMT_CMD4_SB (8U) /*!< Bit field size in bits for CMT_CMD4_SB. */ - -/*! @brief Read current value of the CMT_CMD4_SB field. */ -#define BR_CMT_CMD4_SB(x) (HW_CMT_CMD4(x).U) - -/*! @brief Format value for bitfield CMT_CMD4_SB. */ -#define BF_CMT_CMD4_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD4_SB) & BM_CMT_CMD4_SB) - -/*! @brief Set the SB field to a new value. */ -#define BW_CMT_CMD4_SB(x, v) (HW_CMT_CMD4_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CMT_PPS - CMT Primary Prescaler Register - ******************************************************************************/ - -/*! - * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW) - * - * Reset value: 0x00U - * - * This register is used to set the Primary Prescaler Divider field (PPSDIV). - */ -typedef union _hw_cmt_pps -{ - uint8_t U; - struct _hw_cmt_pps_bitfields - { - uint8_t PPSDIV : 4; /*!< [3:0] Primary Prescaler Divider */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_cmt_pps_t; - -/*! - * @name Constants and macros for entire CMT_PPS register - */ -/*@{*/ -#define HW_CMT_PPS_ADDR(x) ((x) + 0xAU) - -#define HW_CMT_PPS(x) (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR(x)) -#define HW_CMT_PPS_RD(x) (HW_CMT_PPS(x).U) -#define HW_CMT_PPS_WR(x, v) (HW_CMT_PPS(x).U = (v)) -#define HW_CMT_PPS_SET(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) | (v))) -#define HW_CMT_PPS_CLR(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) & ~(v))) -#define HW_CMT_PPS_TOG(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_PPS bitfields - */ - -/*! - * @name Register CMT_PPS, field PPSDIV[3:0] (RW) - * - * Divides the CMT clock to generate the Intermediate Frequency clock enable to - * the secondary prescaler. - * - * Values: - * - 0000 - Bus clock * 1 - * - 0001 - Bus clock * 2 - * - 0010 - Bus clock * 3 - * - 0011 - Bus clock * 4 - * - 0100 - Bus clock * 5 - * - 0101 - Bus clock * 6 - * - 0110 - Bus clock * 7 - * - 0111 - Bus clock * 8 - * - 1000 - Bus clock * 9 - * - 1001 - Bus clock * 10 - * - 1010 - Bus clock * 11 - * - 1011 - Bus clock * 12 - * - 1100 - Bus clock * 13 - * - 1101 - Bus clock * 14 - * - 1110 - Bus clock * 15 - * - 1111 - Bus clock * 16 - */ -/*@{*/ -#define BP_CMT_PPS_PPSDIV (0U) /*!< Bit position for CMT_PPS_PPSDIV. */ -#define BM_CMT_PPS_PPSDIV (0x0FU) /*!< Bit mask for CMT_PPS_PPSDIV. */ -#define BS_CMT_PPS_PPSDIV (4U) /*!< Bit field size in bits for CMT_PPS_PPSDIV. */ - -/*! @brief Read current value of the CMT_PPS_PPSDIV field. */ -#define BR_CMT_PPS_PPSDIV(x) (HW_CMT_PPS(x).B.PPSDIV) - -/*! @brief Format value for bitfield CMT_PPS_PPSDIV. */ -#define BF_CMT_PPS_PPSDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_PPS_PPSDIV) & BM_CMT_PPS_PPSDIV) - -/*! @brief Set the PPSDIV field to a new value. */ -#define BW_CMT_PPS_PPSDIV(x, v) (HW_CMT_PPS_WR(x, (HW_CMT_PPS_RD(x) & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v))) -/*@}*/ - -/******************************************************************************* - * HW_CMT_DMA - CMT Direct Memory Access Register - ******************************************************************************/ - -/*! - * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW) - * - * Reset value: 0x00U - * - * This register is used to enable/disable direct memory access (DMA). - */ -typedef union _hw_cmt_dma -{ - uint8_t U; - struct _hw_cmt_dma_bitfields - { - uint8_t DMA : 1; /*!< [0] DMA Enable */ - uint8_t RESERVED0 : 7; /*!< [7:1] */ - } B; -} hw_cmt_dma_t; - -/*! - * @name Constants and macros for entire CMT_DMA register - */ -/*@{*/ -#define HW_CMT_DMA_ADDR(x) ((x) + 0xBU) - -#define HW_CMT_DMA(x) (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR(x)) -#define HW_CMT_DMA_RD(x) (HW_CMT_DMA(x).U) -#define HW_CMT_DMA_WR(x, v) (HW_CMT_DMA(x).U = (v)) -#define HW_CMT_DMA_SET(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) | (v))) -#define HW_CMT_DMA_CLR(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) & ~(v))) -#define HW_CMT_DMA_TOG(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CMT_DMA bitfields - */ - -/*! - * @name Register CMT_DMA, field DMA[0] (RW) - * - * Enables the DMA protocol. - * - * Values: - * - 0 - DMA transfer request and done are disabled. - * - 1 - DMA transfer request and done are enabled. - */ -/*@{*/ -#define BP_CMT_DMA_DMA (0U) /*!< Bit position for CMT_DMA_DMA. */ -#define BM_CMT_DMA_DMA (0x01U) /*!< Bit mask for CMT_DMA_DMA. */ -#define BS_CMT_DMA_DMA (1U) /*!< Bit field size in bits for CMT_DMA_DMA. */ - -/*! @brief Read current value of the CMT_DMA_DMA field. */ -#define BR_CMT_DMA_DMA(x) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA)) - -/*! @brief Format value for bitfield CMT_DMA_DMA. */ -#define BF_CMT_DMA_DMA(v) ((uint8_t)((uint8_t)(v) << BP_CMT_DMA_DMA) & BM_CMT_DMA_DMA) - -/*! @brief Set the DMA field to a new value. */ -#define BW_CMT_DMA_DMA(x, v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_cmt_t - module struct - ******************************************************************************/ -/*! - * @brief All CMT module registers. - */ -#pragma pack(1) -typedef struct _hw_cmt -{ - __IO hw_cmt_cgh1_t CGH1; /*!< [0x0] CMT Carrier Generator High Data Register 1 */ - __IO hw_cmt_cgl1_t CGL1; /*!< [0x1] CMT Carrier Generator Low Data Register 1 */ - __IO hw_cmt_cgh2_t CGH2; /*!< [0x2] CMT Carrier Generator High Data Register 2 */ - __IO hw_cmt_cgl2_t CGL2; /*!< [0x3] CMT Carrier Generator Low Data Register 2 */ - __IO hw_cmt_oc_t OC; /*!< [0x4] CMT Output Control Register */ - __IO hw_cmt_msc_t MSC; /*!< [0x5] CMT Modulator Status and Control Register */ - __IO hw_cmt_cmd1_t CMD1; /*!< [0x6] CMT Modulator Data Register Mark High */ - __IO hw_cmt_cmd2_t CMD2; /*!< [0x7] CMT Modulator Data Register Mark Low */ - __IO hw_cmt_cmd3_t CMD3; /*!< [0x8] CMT Modulator Data Register Space High */ - __IO hw_cmt_cmd4_t CMD4; /*!< [0x9] CMT Modulator Data Register Space Low */ - __IO hw_cmt_pps_t PPS; /*!< [0xA] CMT Primary Prescaler Register */ - __IO hw_cmt_dma_t DMA; /*!< [0xB] CMT Direct Memory Access Register */ -} hw_cmt_t; -#pragma pack() - -/*! @brief Macro to access all CMT registers. */ -/*! @param x CMT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CMT(CMT_BASE). */ -#define HW_CMT(x) (*(hw_cmt_t *)(x)) - -#endif /* __HW_CMT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_crc.h deleted file mode 100644 index 740bf238c0b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_crc.h +++ /dev/null @@ -1,1409 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_CRC_REGISTERS_H__ -#define __HW_CRC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 CRC - * - * Cyclic Redundancy Check - * - * Registers defined in this header file: - * - HW_CRC_DATAL - CRC_DATAL register. - * - HW_CRC_DATAH - CRC_DATAH register. - * - HW_CRC_DATALL - CRC_DATALL register. - * - HW_CRC_DATALU - CRC_DATALU register. - * - HW_CRC_DATAHL - CRC_DATAHL register. - * - HW_CRC_DATAHU - CRC_DATAHU register. - * - HW_CRC_DATA - CRC Data register - * - HW_CRC_GPOLY - CRC Polynomial register - * - HW_CRC_GPOLYL - CRC_GPOLYL register. - * - HW_CRC_GPOLYH - CRC_GPOLYH register. - * - HW_CRC_GPOLYLL - CRC_GPOLYLL register. - * - HW_CRC_GPOLYLU - CRC_GPOLYLU register. - * - HW_CRC_GPOLYHL - CRC_GPOLYHL register. - * - HW_CRC_GPOLYHU - CRC_GPOLYHU register. - * - HW_CRC_CTRL - CRC Control register - * - HW_CRC_CTRLHU - CRC_CTRLHU register. - * - * - hw_crc_t - Struct containing all module registers. - */ - -#define HW_CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */ - -/******************************************************************************* - * HW_CRC_DATAL - CRC_DATAL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAL - CRC_DATAL register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_datal -{ - uint16_t U; - struct _hw_crc_datal_bitfields - { - uint16_t DATAL : 16; /*!< [15:0] DATAL stores the lower 16 bits of - * the 16/32 bit CRC */ - } B; -} hw_crc_datal_t; - -/*! - * @name Constants and macros for entire CRC_DATAL register - */ -/*@{*/ -#define HW_CRC_DATAL_ADDR(x) ((x) + 0x0U) - -#define HW_CRC_DATAL(x) (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR(x)) -#define HW_CRC_DATAL_RD(x) (HW_CRC_DATAL(x).U) -#define HW_CRC_DATAL_WR(x, v) (HW_CRC_DATAL(x).U = (v)) -#define HW_CRC_DATAL_SET(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) | (v))) -#define HW_CRC_DATAL_CLR(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v))) -#define HW_CRC_DATAL_TOG(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAL bitfields - */ - -/*! - * @name Register CRC_DATAL, field DATAL[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAL_DATAL (0U) /*!< Bit position for CRC_DATAL_DATAL. */ -#define BM_CRC_DATAL_DATAL (0xFFFFU) /*!< Bit mask for CRC_DATAL_DATAL. */ -#define BS_CRC_DATAL_DATAL (16U) /*!< Bit field size in bits for CRC_DATAL_DATAL. */ - -/*! @brief Read current value of the CRC_DATAL_DATAL field. */ -#define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U) - -/*! @brief Format value for bitfield CRC_DATAL_DATAL. */ -#define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL) - -/*! @brief Set the DATAL field to a new value. */ -#define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATAH - CRC_DATAH register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAH - CRC_DATAH register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_datah -{ - uint16_t U; - struct _hw_crc_datah_bitfields - { - uint16_t DATAH : 16; /*!< [15:0] DATAH stores the high 16 bits of the - * 16/32 bit CRC */ - } B; -} hw_crc_datah_t; - -/*! - * @name Constants and macros for entire CRC_DATAH register - */ -/*@{*/ -#define HW_CRC_DATAH_ADDR(x) ((x) + 0x2U) - -#define HW_CRC_DATAH(x) (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR(x)) -#define HW_CRC_DATAH_RD(x) (HW_CRC_DATAH(x).U) -#define HW_CRC_DATAH_WR(x, v) (HW_CRC_DATAH(x).U = (v)) -#define HW_CRC_DATAH_SET(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) | (v))) -#define HW_CRC_DATAH_CLR(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v))) -#define HW_CRC_DATAH_TOG(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAH bitfields - */ - -/*! - * @name Register CRC_DATAH, field DATAH[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAH_DATAH (0U) /*!< Bit position for CRC_DATAH_DATAH. */ -#define BM_CRC_DATAH_DATAH (0xFFFFU) /*!< Bit mask for CRC_DATAH_DATAH. */ -#define BS_CRC_DATAH_DATAH (16U) /*!< Bit field size in bits for CRC_DATAH_DATAH. */ - -/*! @brief Read current value of the CRC_DATAH_DATAH field. */ -#define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U) - -/*! @brief Format value for bitfield CRC_DATAH_DATAH. */ -#define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH) - -/*! @brief Set the DATAH field to a new value. */ -#define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATALL - CRC_DATALL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATALL - CRC_DATALL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datall -{ - uint8_t U; - struct _hw_crc_datall_bitfields - { - uint8_t DATALL : 8; /*!< [7:0] CRCLL stores the first 8 bits of the - * 32 bit DATA */ - } B; -} hw_crc_datall_t; - -/*! - * @name Constants and macros for entire CRC_DATALL register - */ -/*@{*/ -#define HW_CRC_DATALL_ADDR(x) ((x) + 0x0U) - -#define HW_CRC_DATALL(x) (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR(x)) -#define HW_CRC_DATALL_RD(x) (HW_CRC_DATALL(x).U) -#define HW_CRC_DATALL_WR(x, v) (HW_CRC_DATALL(x).U = (v)) -#define HW_CRC_DATALL_SET(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) | (v))) -#define HW_CRC_DATALL_CLR(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v))) -#define HW_CRC_DATALL_TOG(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATALL bitfields - */ - -/*! - * @name Register CRC_DATALL, field DATALL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATALL_DATALL (0U) /*!< Bit position for CRC_DATALL_DATALL. */ -#define BM_CRC_DATALL_DATALL (0xFFU) /*!< Bit mask for CRC_DATALL_DATALL. */ -#define BS_CRC_DATALL_DATALL (8U) /*!< Bit field size in bits for CRC_DATALL_DATALL. */ - -/*! @brief Read current value of the CRC_DATALL_DATALL field. */ -#define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U) - -/*! @brief Format value for bitfield CRC_DATALL_DATALL. */ -#define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL) - -/*! @brief Set the DATALL field to a new value. */ -#define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATALU - CRC_DATALU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATALU - CRC_DATALU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datalu -{ - uint8_t U; - struct _hw_crc_datalu_bitfields - { - uint8_t DATALU : 8; /*!< [7:0] DATALL stores the second 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_datalu_t; - -/*! - * @name Constants and macros for entire CRC_DATALU register - */ -/*@{*/ -#define HW_CRC_DATALU_ADDR(x) ((x) + 0x1U) - -#define HW_CRC_DATALU(x) (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR(x)) -#define HW_CRC_DATALU_RD(x) (HW_CRC_DATALU(x).U) -#define HW_CRC_DATALU_WR(x, v) (HW_CRC_DATALU(x).U = (v)) -#define HW_CRC_DATALU_SET(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) | (v))) -#define HW_CRC_DATALU_CLR(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v))) -#define HW_CRC_DATALU_TOG(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATALU bitfields - */ - -/*! - * @name Register CRC_DATALU, field DATALU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATALU_DATALU (0U) /*!< Bit position for CRC_DATALU_DATALU. */ -#define BM_CRC_DATALU_DATALU (0xFFU) /*!< Bit mask for CRC_DATALU_DATALU. */ -#define BS_CRC_DATALU_DATALU (8U) /*!< Bit field size in bits for CRC_DATALU_DATALU. */ - -/*! @brief Read current value of the CRC_DATALU_DATALU field. */ -#define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U) - -/*! @brief Format value for bitfield CRC_DATALU_DATALU. */ -#define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU) - -/*! @brief Set the DATALU field to a new value. */ -#define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATAHL - CRC_DATAHL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datahl -{ - uint8_t U; - struct _hw_crc_datahl_bitfields - { - uint8_t DATAHL : 8; /*!< [7:0] DATAHL stores the third 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_datahl_t; - -/*! - * @name Constants and macros for entire CRC_DATAHL register - */ -/*@{*/ -#define HW_CRC_DATAHL_ADDR(x) ((x) + 0x2U) - -#define HW_CRC_DATAHL(x) (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR(x)) -#define HW_CRC_DATAHL_RD(x) (HW_CRC_DATAHL(x).U) -#define HW_CRC_DATAHL_WR(x, v) (HW_CRC_DATAHL(x).U = (v)) -#define HW_CRC_DATAHL_SET(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) | (v))) -#define HW_CRC_DATAHL_CLR(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v))) -#define HW_CRC_DATAHL_TOG(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAHL bitfields - */ - -/*! - * @name Register CRC_DATAHL, field DATAHL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAHL_DATAHL (0U) /*!< Bit position for CRC_DATAHL_DATAHL. */ -#define BM_CRC_DATAHL_DATAHL (0xFFU) /*!< Bit mask for CRC_DATAHL_DATAHL. */ -#define BS_CRC_DATAHL_DATAHL (8U) /*!< Bit field size in bits for CRC_DATAHL_DATAHL. */ - -/*! @brief Read current value of the CRC_DATAHL_DATAHL field. */ -#define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U) - -/*! @brief Format value for bitfield CRC_DATAHL_DATAHL. */ -#define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL) - -/*! @brief Set the DATAHL field to a new value. */ -#define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATAHU - CRC_DATAHU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_datahu -{ - uint8_t U; - struct _hw_crc_datahu_bitfields - { - uint8_t DATAHU : 8; /*!< [7:0] DATAHU stores the fourth 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_datahu_t; - -/*! - * @name Constants and macros for entire CRC_DATAHU register - */ -/*@{*/ -#define HW_CRC_DATAHU_ADDR(x) ((x) + 0x3U) - -#define HW_CRC_DATAHU(x) (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR(x)) -#define HW_CRC_DATAHU_RD(x) (HW_CRC_DATAHU(x).U) -#define HW_CRC_DATAHU_WR(x, v) (HW_CRC_DATAHU(x).U = (v)) -#define HW_CRC_DATAHU_SET(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) | (v))) -#define HW_CRC_DATAHU_CLR(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v))) -#define HW_CRC_DATAHU_TOG(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATAHU bitfields - */ - -/*! - * @name Register CRC_DATAHU, field DATAHU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_DATAHU_DATAHU (0U) /*!< Bit position for CRC_DATAHU_DATAHU. */ -#define BM_CRC_DATAHU_DATAHU (0xFFU) /*!< Bit mask for CRC_DATAHU_DATAHU. */ -#define BS_CRC_DATAHU_DATAHU (8U) /*!< Bit field size in bits for CRC_DATAHU_DATAHU. */ - -/*! @brief Read current value of the CRC_DATAHU_DATAHU field. */ -#define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U) - -/*! @brief Format value for bitfield CRC_DATAHU_DATAHU. */ -#define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU) - -/*! @brief Set the DATAHU field to a new value. */ -#define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_DATA - CRC Data register - ******************************************************************************/ - -/*! - * @brief HW_CRC_DATA - CRC Data register (RW) - * - * Reset value: 0xFFFFFFFFU - * - * The CRC Data register contains the value of the seed, data, and checksum. - * When CTRL[WAS] is set, any write to the data register is regarded as the seed - * value. When CTRL[WAS] is cleared, any write to the data register is regarded as - * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are - * not used for programming the seed value, and reads of these fields return an - * indeterminate value. In 32-bit CRC mode, all fields are used for programming - * the seed value. When programming data values, the values can be written 8 bits, - * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of - * data value written first. After all data values are written, the CRC result - * can be read from this data register. In 16-bit CRC mode, the CRC result is - * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the - * result. Reads of this register at any time return the intermediate CRC value, - * provided the CRC module is configured. - */ -typedef union _hw_crc_data -{ - uint32_t U; - struct _hw_crc_data_bitfields - { - uint32_t LL : 8; /*!< [7:0] CRC Low Lower Byte */ - uint32_t LU : 8; /*!< [15:8] CRC Low Upper Byte */ - uint32_t HL : 8; /*!< [23:16] CRC High Lower Byte */ - uint32_t HU : 8; /*!< [31:24] CRC High Upper Byte */ - } B; -} hw_crc_data_t; - -/*! - * @name Constants and macros for entire CRC_DATA register - */ -/*@{*/ -#define HW_CRC_DATA_ADDR(x) ((x) + 0x0U) - -#define HW_CRC_DATA(x) (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR(x)) -#define HW_CRC_DATA_RD(x) (HW_CRC_DATA(x).U) -#define HW_CRC_DATA_WR(x, v) (HW_CRC_DATA(x).U = (v)) -#define HW_CRC_DATA_SET(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) | (v))) -#define HW_CRC_DATA_CLR(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v))) -#define HW_CRC_DATA_TOG(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_DATA bitfields - */ - -/*! - * @name Register CRC_DATA, field LL[7:0] (RW) - * - * When CTRL[WAS] is 1, values written to this field are part of the seed value. - * When CTRL[WAS] is 0, data written to this field is used for CRC checksum - * generation. - */ -/*@{*/ -#define BP_CRC_DATA_LL (0U) /*!< Bit position for CRC_DATA_LL. */ -#define BM_CRC_DATA_LL (0x000000FFU) /*!< Bit mask for CRC_DATA_LL. */ -#define BS_CRC_DATA_LL (8U) /*!< Bit field size in bits for CRC_DATA_LL. */ - -/*! @brief Read current value of the CRC_DATA_LL field. */ -#define BR_CRC_DATA_LL(x) (HW_CRC_DATA(x).B.LL) - -/*! @brief Format value for bitfield CRC_DATA_LL. */ -#define BF_CRC_DATA_LL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL) - -/*! @brief Set the LL field to a new value. */ -#define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v))) -/*@}*/ - -/*! - * @name Register CRC_DATA, field LU[15:8] (RW) - * - * When CTRL[WAS] is 1, values written to this field are part of the seed value. - * When CTRL[WAS] is 0, data written to this field is used for CRC checksum - * generation. - */ -/*@{*/ -#define BP_CRC_DATA_LU (8U) /*!< Bit position for CRC_DATA_LU. */ -#define BM_CRC_DATA_LU (0x0000FF00U) /*!< Bit mask for CRC_DATA_LU. */ -#define BS_CRC_DATA_LU (8U) /*!< Bit field size in bits for CRC_DATA_LU. */ - -/*! @brief Read current value of the CRC_DATA_LU field. */ -#define BR_CRC_DATA_LU(x) (HW_CRC_DATA(x).B.LU) - -/*! @brief Format value for bitfield CRC_DATA_LU. */ -#define BF_CRC_DATA_LU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU) - -/*! @brief Set the LU field to a new value. */ -#define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v))) -/*@}*/ - -/*! - * @name Register CRC_DATA, field HL[23:16] (RW) - * - * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming - * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this - * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data - * written to this field is used for CRC checksum generation in both 16-bit and - * 32-bit CRC modes. - */ -/*@{*/ -#define BP_CRC_DATA_HL (16U) /*!< Bit position for CRC_DATA_HL. */ -#define BM_CRC_DATA_HL (0x00FF0000U) /*!< Bit mask for CRC_DATA_HL. */ -#define BS_CRC_DATA_HL (8U) /*!< Bit field size in bits for CRC_DATA_HL. */ - -/*! @brief Read current value of the CRC_DATA_HL field. */ -#define BR_CRC_DATA_HL(x) (HW_CRC_DATA(x).B.HL) - -/*! @brief Format value for bitfield CRC_DATA_HL. */ -#define BF_CRC_DATA_HL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL) - -/*! @brief Set the HL field to a new value. */ -#define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v))) -/*@}*/ - -/*! - * @name Register CRC_DATA, field HU[31:24] (RW) - * - * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming - * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this - * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data - * written to this field is used for CRC checksum generation in both 16-bit and - * 32-bit CRC modes. - */ -/*@{*/ -#define BP_CRC_DATA_HU (24U) /*!< Bit position for CRC_DATA_HU. */ -#define BM_CRC_DATA_HU (0xFF000000U) /*!< Bit mask for CRC_DATA_HU. */ -#define BS_CRC_DATA_HU (8U) /*!< Bit field size in bits for CRC_DATA_HU. */ - -/*! @brief Read current value of the CRC_DATA_HU field. */ -#define BR_CRC_DATA_HU(x) (HW_CRC_DATA(x).B.HU) - -/*! @brief Format value for bitfield CRC_DATA_HU. */ -#define BF_CRC_DATA_HU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU) - -/*! @brief Set the HU field to a new value. */ -#define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v))) -/*@}*/ - -/******************************************************************************* - * HW_CRC_GPOLY - CRC Polynomial register - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLY - CRC Polynomial register (RW) - * - * Reset value: 0x00001021U - * - * This register contains the value of the polynomial for the CRC calculation. - * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used - * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC - * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are - * used in both 16- and 32-bit CRC modes. - */ -typedef union _hw_crc_gpoly -{ - uint32_t U; - struct _hw_crc_gpoly_bitfields - { - uint32_t LOW : 16; /*!< [15:0] Low Polynominal Half-word */ - uint32_t HIGH : 16; /*!< [31:16] High Polynominal Half-word */ - } B; -} hw_crc_gpoly_t; - -/*! - * @name Constants and macros for entire CRC_GPOLY register - */ -/*@{*/ -#define HW_CRC_GPOLY_ADDR(x) ((x) + 0x4U) - -#define HW_CRC_GPOLY(x) (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR(x)) -#define HW_CRC_GPOLY_RD(x) (HW_CRC_GPOLY(x).U) -#define HW_CRC_GPOLY_WR(x, v) (HW_CRC_GPOLY(x).U = (v)) -#define HW_CRC_GPOLY_SET(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) | (v))) -#define HW_CRC_GPOLY_CLR(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v))) -#define HW_CRC_GPOLY_TOG(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLY bitfields - */ - -/*! - * @name Register CRC_GPOLY, field LOW[15:0] (RW) - * - * Writable and readable in both 32-bit and 16-bit CRC modes. - */ -/*@{*/ -#define BP_CRC_GPOLY_LOW (0U) /*!< Bit position for CRC_GPOLY_LOW. */ -#define BM_CRC_GPOLY_LOW (0x0000FFFFU) /*!< Bit mask for CRC_GPOLY_LOW. */ -#define BS_CRC_GPOLY_LOW (16U) /*!< Bit field size in bits for CRC_GPOLY_LOW. */ - -/*! @brief Read current value of the CRC_GPOLY_LOW field. */ -#define BR_CRC_GPOLY_LOW(x) (HW_CRC_GPOLY(x).B.LOW) - -/*! @brief Format value for bitfield CRC_GPOLY_LOW. */ -#define BF_CRC_GPOLY_LOW(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW) - -/*! @brief Set the LOW field to a new value. */ -#define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v))) -/*@}*/ - -/*! - * @name Register CRC_GPOLY, field HIGH[31:16] (RW) - * - * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not - * writable in 16-bit CRC mode (CTRL[TCRC] is 0). - */ -/*@{*/ -#define BP_CRC_GPOLY_HIGH (16U) /*!< Bit position for CRC_GPOLY_HIGH. */ -#define BM_CRC_GPOLY_HIGH (0xFFFF0000U) /*!< Bit mask for CRC_GPOLY_HIGH. */ -#define BS_CRC_GPOLY_HIGH (16U) /*!< Bit field size in bits for CRC_GPOLY_HIGH. */ - -/*! @brief Read current value of the CRC_GPOLY_HIGH field. */ -#define BR_CRC_GPOLY_HIGH(x) (HW_CRC_GPOLY(x).B.HIGH) - -/*! @brief Format value for bitfield CRC_GPOLY_HIGH. */ -#define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH) - -/*! @brief Set the HIGH field to a new value. */ -#define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v))) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYL - CRC_GPOLYL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_gpolyl -{ - uint16_t U; - struct _hw_crc_gpolyl_bitfields - { - uint16_t GPOLYL : 16; /*!< [15:0] POLYL stores the lower 16 bits of - * the 16/32 bit CRC polynomial value */ - } B; -} hw_crc_gpolyl_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYL register - */ -/*@{*/ -#define HW_CRC_GPOLYL_ADDR(x) ((x) + 0x4U) - -#define HW_CRC_GPOLYL(x) (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR(x)) -#define HW_CRC_GPOLYL_RD(x) (HW_CRC_GPOLYL(x).U) -#define HW_CRC_GPOLYL_WR(x, v) (HW_CRC_GPOLYL(x).U = (v)) -#define HW_CRC_GPOLYL_SET(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) | (v))) -#define HW_CRC_GPOLYL_CLR(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v))) -#define HW_CRC_GPOLYL_TOG(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYL bitfields - */ - -/*! - * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYL_GPOLYL (0U) /*!< Bit position for CRC_GPOLYL_GPOLYL. */ -#define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) /*!< Bit mask for CRC_GPOLYL_GPOLYL. */ -#define BS_CRC_GPOLYL_GPOLYL (16U) /*!< Bit field size in bits for CRC_GPOLYL_GPOLYL. */ - -/*! @brief Read current value of the CRC_GPOLYL_GPOLYL field. */ -#define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. */ -#define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL) - -/*! @brief Set the GPOLYL field to a new value. */ -#define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYH - CRC_GPOLYH register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW) - * - * Reset value: 0xFFFFU - */ -typedef union _hw_crc_gpolyh -{ - uint16_t U; - struct _hw_crc_gpolyh_bitfields - { - uint16_t GPOLYH : 16; /*!< [15:0] POLYH stores the high 16 bits of - * the 16/32 bit CRC polynomial value */ - } B; -} hw_crc_gpolyh_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYH register - */ -/*@{*/ -#define HW_CRC_GPOLYH_ADDR(x) ((x) + 0x6U) - -#define HW_CRC_GPOLYH(x) (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR(x)) -#define HW_CRC_GPOLYH_RD(x) (HW_CRC_GPOLYH(x).U) -#define HW_CRC_GPOLYH_WR(x, v) (HW_CRC_GPOLYH(x).U = (v)) -#define HW_CRC_GPOLYH_SET(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) | (v))) -#define HW_CRC_GPOLYH_CLR(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v))) -#define HW_CRC_GPOLYH_TOG(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYH bitfields - */ - -/*! - * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYH_GPOLYH (0U) /*!< Bit position for CRC_GPOLYH_GPOLYH. */ -#define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) /*!< Bit mask for CRC_GPOLYH_GPOLYH. */ -#define BS_CRC_GPOLYH_GPOLYH (16U) /*!< Bit field size in bits for CRC_GPOLYH_GPOLYH. */ - -/*! @brief Read current value of the CRC_GPOLYH_GPOLYH field. */ -#define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. */ -#define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH) - -/*! @brief Set the GPOLYH field to a new value. */ -#define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYLL - CRC_GPOLYLL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolyll -{ - uint8_t U; - struct _hw_crc_gpolyll_bitfields - { - uint8_t GPOLYLL : 8; /*!< [7:0] POLYLL stores the first 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_gpolyll_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYLL register - */ -/*@{*/ -#define HW_CRC_GPOLYLL_ADDR(x) ((x) + 0x4U) - -#define HW_CRC_GPOLYLL(x) (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR(x)) -#define HW_CRC_GPOLYLL_RD(x) (HW_CRC_GPOLYLL(x).U) -#define HW_CRC_GPOLYLL_WR(x, v) (HW_CRC_GPOLYLL(x).U = (v)) -#define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) | (v))) -#define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v))) -#define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYLL bitfields - */ - -/*! - * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYLL_GPOLYLL (0U) /*!< Bit position for CRC_GPOLYLL_GPOLYLL. */ -#define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) /*!< Bit mask for CRC_GPOLYLL_GPOLYLL. */ -#define BS_CRC_GPOLYLL_GPOLYLL (8U) /*!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. */ - -/*! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. */ -#define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. */ -#define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL) - -/*! @brief Set the GPOLYLL field to a new value. */ -#define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYLU - CRC_GPOLYLU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolylu -{ - uint8_t U; - struct _hw_crc_gpolylu_bitfields - { - uint8_t GPOLYLU : 8; /*!< [7:0] POLYLL stores the second 8 bits of - * the 32 bit CRC */ - } B; -} hw_crc_gpolylu_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYLU register - */ -/*@{*/ -#define HW_CRC_GPOLYLU_ADDR(x) ((x) + 0x5U) - -#define HW_CRC_GPOLYLU(x) (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR(x)) -#define HW_CRC_GPOLYLU_RD(x) (HW_CRC_GPOLYLU(x).U) -#define HW_CRC_GPOLYLU_WR(x, v) (HW_CRC_GPOLYLU(x).U = (v)) -#define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) | (v))) -#define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v))) -#define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYLU bitfields - */ - -/*! - * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYLU_GPOLYLU (0U) /*!< Bit position for CRC_GPOLYLU_GPOLYLU. */ -#define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) /*!< Bit mask for CRC_GPOLYLU_GPOLYLU. */ -#define BS_CRC_GPOLYLU_GPOLYLU (8U) /*!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. */ - -/*! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. */ -#define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. */ -#define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU) - -/*! @brief Set the GPOLYLU field to a new value. */ -#define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYHL - CRC_GPOLYHL register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolyhl -{ - uint8_t U; - struct _hw_crc_gpolyhl_bitfields - { - uint8_t GPOLYHL : 8; /*!< [7:0] POLYHL stores the third 8 bits of the - * 32 bit CRC */ - } B; -} hw_crc_gpolyhl_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYHL register - */ -/*@{*/ -#define HW_CRC_GPOLYHL_ADDR(x) ((x) + 0x6U) - -#define HW_CRC_GPOLYHL(x) (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR(x)) -#define HW_CRC_GPOLYHL_RD(x) (HW_CRC_GPOLYHL(x).U) -#define HW_CRC_GPOLYHL_WR(x, v) (HW_CRC_GPOLYHL(x).U = (v)) -#define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) | (v))) -#define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v))) -#define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYHL bitfields - */ - -/*! - * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYHL_GPOLYHL (0U) /*!< Bit position for CRC_GPOLYHL_GPOLYHL. */ -#define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) /*!< Bit mask for CRC_GPOLYHL_GPOLYHL. */ -#define BS_CRC_GPOLYHL_GPOLYHL (8U) /*!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. */ - -/*! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. */ -#define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. */ -#define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL) - -/*! @brief Set the GPOLYHL field to a new value. */ -#define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_CRC_GPOLYHU - CRC_GPOLYHU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW) - * - * Reset value: 0xFFU - */ -typedef union _hw_crc_gpolyhu -{ - uint8_t U; - struct _hw_crc_gpolyhu_bitfields - { - uint8_t GPOLYHU : 8; /*!< [7:0] POLYHU stores the fourth 8 bits of - * the 32 bit CRC */ - } B; -} hw_crc_gpolyhu_t; - -/*! - * @name Constants and macros for entire CRC_GPOLYHU register - */ -/*@{*/ -#define HW_CRC_GPOLYHU_ADDR(x) ((x) + 0x7U) - -#define HW_CRC_GPOLYHU(x) (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR(x)) -#define HW_CRC_GPOLYHU_RD(x) (HW_CRC_GPOLYHU(x).U) -#define HW_CRC_GPOLYHU_WR(x, v) (HW_CRC_GPOLYHU(x).U = (v)) -#define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) | (v))) -#define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v))) -#define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_GPOLYHU bitfields - */ - -/*! - * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW) - */ -/*@{*/ -#define BP_CRC_GPOLYHU_GPOLYHU (0U) /*!< Bit position for CRC_GPOLYHU_GPOLYHU. */ -#define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) /*!< Bit mask for CRC_GPOLYHU_GPOLYHU. */ -#define BS_CRC_GPOLYHU_GPOLYHU (8U) /*!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. */ - -/*! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. */ -#define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U) - -/*! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. */ -#define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU) - -/*! @brief Set the GPOLYHU field to a new value. */ -#define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_CRC_CTRL - CRC Control register - ******************************************************************************/ - -/*! - * @brief HW_CRC_CTRL - CRC Control register (RW) - * - * Reset value: 0x00000000U - * - * This register controls the configuration and working of the CRC module. - * Appropriate bits must be set before starting a new CRC calculation. A new CRC - * calculation is initialized by asserting CTRL[WAS] and then writing the seed into - * the CRC data register. - */ -typedef union _hw_crc_ctrl -{ - uint32_t U; - struct _hw_crc_ctrl_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t TCRC : 1; /*!< [24] */ - uint32_t WAS : 1; /*!< [25] Write CRC Data Register As Seed */ - uint32_t FXOR : 1; /*!< [26] Complement Read Of CRC Data Register */ - uint32_t RESERVED1 : 1; /*!< [27] */ - uint32_t TOTR : 2; /*!< [29:28] Type Of Transpose For Read */ - uint32_t TOT : 2; /*!< [31:30] Type Of Transpose For Writes */ - } B; -} hw_crc_ctrl_t; - -/*! - * @name Constants and macros for entire CRC_CTRL register - */ -/*@{*/ -#define HW_CRC_CTRL_ADDR(x) ((x) + 0x8U) - -#define HW_CRC_CTRL(x) (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR(x)) -#define HW_CRC_CTRL_RD(x) (HW_CRC_CTRL(x).U) -#define HW_CRC_CTRL_WR(x, v) (HW_CRC_CTRL(x).U = (v)) -#define HW_CRC_CTRL_SET(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) | (v))) -#define HW_CRC_CTRL_CLR(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v))) -#define HW_CRC_CTRL_TOG(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_CTRL bitfields - */ - -/*! - * @name Register CRC_CTRL, field TCRC[24] (RW) - * - * Width of CRC protocol. - * - * Values: - * - 0 - 16-bit CRC protocol. - * - 1 - 32-bit CRC protocol. - */ -/*@{*/ -#define BP_CRC_CTRL_TCRC (24U) /*!< Bit position for CRC_CTRL_TCRC. */ -#define BM_CRC_CTRL_TCRC (0x01000000U) /*!< Bit mask for CRC_CTRL_TCRC. */ -#define BS_CRC_CTRL_TCRC (1U) /*!< Bit field size in bits for CRC_CTRL_TCRC. */ - -/*! @brief Read current value of the CRC_CTRL_TCRC field. */ -#define BR_CRC_CTRL_TCRC(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC)) - -/*! @brief Format value for bitfield CRC_CTRL_TCRC. */ -#define BF_CRC_CTRL_TCRC(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC) - -/*! @brief Set the TCRC field to a new value. */ -#define BW_CRC_CTRL_TCRC(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field WAS[25] (RW) - * - * When asserted, a value written to the CRC data register is considered a seed - * value. When deasserted, a value written to the CRC data register is taken as - * data for CRC computation. - * - * Values: - * - 0 - Writes to the CRC data register are data values. - * - 1 - Writes to the CRC data register are seed values. - */ -/*@{*/ -#define BP_CRC_CTRL_WAS (25U) /*!< Bit position for CRC_CTRL_WAS. */ -#define BM_CRC_CTRL_WAS (0x02000000U) /*!< Bit mask for CRC_CTRL_WAS. */ -#define BS_CRC_CTRL_WAS (1U) /*!< Bit field size in bits for CRC_CTRL_WAS. */ - -/*! @brief Read current value of the CRC_CTRL_WAS field. */ -#define BR_CRC_CTRL_WAS(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS)) - -/*! @brief Format value for bitfield CRC_CTRL_WAS. */ -#define BF_CRC_CTRL_WAS(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS) - -/*! @brief Set the WAS field to a new value. */ -#define BW_CRC_CTRL_WAS(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field FXOR[26] (RW) - * - * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or - * 0xFFFF. Asserting this bit enables on the fly complementing of read data. - * - * Values: - * - 0 - No XOR on reading. - * - 1 - Invert or complement the read value of the CRC Data register. - */ -/*@{*/ -#define BP_CRC_CTRL_FXOR (26U) /*!< Bit position for CRC_CTRL_FXOR. */ -#define BM_CRC_CTRL_FXOR (0x04000000U) /*!< Bit mask for CRC_CTRL_FXOR. */ -#define BS_CRC_CTRL_FXOR (1U) /*!< Bit field size in bits for CRC_CTRL_FXOR. */ - -/*! @brief Read current value of the CRC_CTRL_FXOR field. */ -#define BR_CRC_CTRL_FXOR(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR)) - -/*! @brief Format value for bitfield CRC_CTRL_FXOR. */ -#define BF_CRC_CTRL_FXOR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR) - -/*! @brief Set the FXOR field to a new value. */ -#define BW_CRC_CTRL_FXOR(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field TOTR[29:28] (RW) - * - * Identifies the transpose configuration of the value read from the CRC Data - * register. See the description of the transpose feature for the available - * transpose options. - * - * Values: - * - 00 - No transposition. - * - 01 - Bits in bytes are transposed; bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRL_TOTR (28U) /*!< Bit position for CRC_CTRL_TOTR. */ -#define BM_CRC_CTRL_TOTR (0x30000000U) /*!< Bit mask for CRC_CTRL_TOTR. */ -#define BS_CRC_CTRL_TOTR (2U) /*!< Bit field size in bits for CRC_CTRL_TOTR. */ - -/*! @brief Read current value of the CRC_CTRL_TOTR field. */ -#define BR_CRC_CTRL_TOTR(x) (HW_CRC_CTRL(x).B.TOTR) - -/*! @brief Format value for bitfield CRC_CTRL_TOTR. */ -#define BF_CRC_CTRL_TOTR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR) - -/*! @brief Set the TOTR field to a new value. */ -#define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v))) -/*@}*/ - -/*! - * @name Register CRC_CTRL, field TOT[31:30] (RW) - * - * Defines the transpose configuration of the data written to the CRC data - * register. See the description of the transpose feature for the available transpose - * options. - * - * Values: - * - 00 - No transposition. - * - 01 - Bits in bytes are transposed; bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRL_TOT (30U) /*!< Bit position for CRC_CTRL_TOT. */ -#define BM_CRC_CTRL_TOT (0xC0000000U) /*!< Bit mask for CRC_CTRL_TOT. */ -#define BS_CRC_CTRL_TOT (2U) /*!< Bit field size in bits for CRC_CTRL_TOT. */ - -/*! @brief Read current value of the CRC_CTRL_TOT field. */ -#define BR_CRC_CTRL_TOT(x) (HW_CRC_CTRL(x).B.TOT) - -/*! @brief Format value for bitfield CRC_CTRL_TOT. */ -#define BF_CRC_CTRL_TOT(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT) - -/*! @brief Set the TOT field to a new value. */ -#define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v))) -/*@}*/ -/******************************************************************************* - * HW_CRC_CTRLHU - CRC_CTRLHU register. - ******************************************************************************/ - -/*! - * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_crc_ctrlhu -{ - uint8_t U; - struct _hw_crc_ctrlhu_bitfields - { - uint8_t TCRC : 1; /*!< [0] */ - uint8_t WAS : 1; /*!< [1] */ - uint8_t FXOR : 1; /*!< [2] */ - uint8_t RESERVED0 : 1; /*!< [3] */ - uint8_t TOTR : 2; /*!< [5:4] */ - uint8_t TOT : 2; /*!< [7:6] */ - } B; -} hw_crc_ctrlhu_t; - -/*! - * @name Constants and macros for entire CRC_CTRLHU register - */ -/*@{*/ -#define HW_CRC_CTRLHU_ADDR(x) ((x) + 0xBU) - -#define HW_CRC_CTRLHU(x) (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR(x)) -#define HW_CRC_CTRLHU_RD(x) (HW_CRC_CTRLHU(x).U) -#define HW_CRC_CTRLHU_WR(x, v) (HW_CRC_CTRLHU(x).U = (v)) -#define HW_CRC_CTRLHU_SET(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) | (v))) -#define HW_CRC_CTRLHU_CLR(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v))) -#define HW_CRC_CTRLHU_TOG(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual CRC_CTRLHU bitfields - */ - -/*! - * @name Register CRC_CTRLHU, field TCRC[0] (RW) - * - * Values: - * - 0 - 16-bit CRC protocol. - * - 1 - 32-bit CRC protocol. - */ -/*@{*/ -#define BP_CRC_CTRLHU_TCRC (0U) /*!< Bit position for CRC_CTRLHU_TCRC. */ -#define BM_CRC_CTRLHU_TCRC (0x01U) /*!< Bit mask for CRC_CTRLHU_TCRC. */ -#define BS_CRC_CTRLHU_TCRC (1U) /*!< Bit field size in bits for CRC_CTRLHU_TCRC. */ - -/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */ -#define BR_CRC_CTRLHU_TCRC(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC)) - -/*! @brief Format value for bitfield CRC_CTRLHU_TCRC. */ -#define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC) - -/*! @brief Set the TCRC field to a new value. */ -#define BW_CRC_CTRLHU_TCRC(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field WAS[1] (RW) - * - * Values: - * - 0 - Writes to CRC data register are data values. - * - 1 - Writes to CRC data reguster are seed values. - */ -/*@{*/ -#define BP_CRC_CTRLHU_WAS (1U) /*!< Bit position for CRC_CTRLHU_WAS. */ -#define BM_CRC_CTRLHU_WAS (0x02U) /*!< Bit mask for CRC_CTRLHU_WAS. */ -#define BS_CRC_CTRLHU_WAS (1U) /*!< Bit field size in bits for CRC_CTRLHU_WAS. */ - -/*! @brief Read current value of the CRC_CTRLHU_WAS field. */ -#define BR_CRC_CTRLHU_WAS(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS)) - -/*! @brief Format value for bitfield CRC_CTRLHU_WAS. */ -#define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS) - -/*! @brief Set the WAS field to a new value. */ -#define BW_CRC_CTRLHU_WAS(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field FXOR[2] (RW) - * - * Values: - * - 0 - No XOR on reading. - * - 1 - Invert or complement the read value of CRC data register. - */ -/*@{*/ -#define BP_CRC_CTRLHU_FXOR (2U) /*!< Bit position for CRC_CTRLHU_FXOR. */ -#define BM_CRC_CTRLHU_FXOR (0x04U) /*!< Bit mask for CRC_CTRLHU_FXOR. */ -#define BS_CRC_CTRLHU_FXOR (1U) /*!< Bit field size in bits for CRC_CTRLHU_FXOR. */ - -/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */ -#define BR_CRC_CTRLHU_FXOR(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR)) - -/*! @brief Format value for bitfield CRC_CTRLHU_FXOR. */ -#define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR) - -/*! @brief Set the FXOR field to a new value. */ -#define BW_CRC_CTRLHU_FXOR(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR) = (v)) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field TOTR[5:4] (RW) - * - * Values: - * - 00 - No Transposition. - * - 01 - Bits in bytes are transposed, bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRLHU_TOTR (4U) /*!< Bit position for CRC_CTRLHU_TOTR. */ -#define BM_CRC_CTRLHU_TOTR (0x30U) /*!< Bit mask for CRC_CTRLHU_TOTR. */ -#define BS_CRC_CTRLHU_TOTR (2U) /*!< Bit field size in bits for CRC_CTRLHU_TOTR. */ - -/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */ -#define BR_CRC_CTRLHU_TOTR(x) (HW_CRC_CTRLHU(x).B.TOTR) - -/*! @brief Format value for bitfield CRC_CTRLHU_TOTR. */ -#define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR) - -/*! @brief Set the TOTR field to a new value. */ -#define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v))) -/*@}*/ - -/*! - * @name Register CRC_CTRLHU, field TOT[7:6] (RW) - * - * Values: - * - 00 - No Transposition. - * - 01 - Bits in bytes are transposed, bytes are not transposed. - * - 10 - Both bits in bytes and bytes are transposed. - * - 11 - Only bytes are transposed; no bits in a byte are transposed. - */ -/*@{*/ -#define BP_CRC_CTRLHU_TOT (6U) /*!< Bit position for CRC_CTRLHU_TOT. */ -#define BM_CRC_CTRLHU_TOT (0xC0U) /*!< Bit mask for CRC_CTRLHU_TOT. */ -#define BS_CRC_CTRLHU_TOT (2U) /*!< Bit field size in bits for CRC_CTRLHU_TOT. */ - -/*! @brief Read current value of the CRC_CTRLHU_TOT field. */ -#define BR_CRC_CTRLHU_TOT(x) (HW_CRC_CTRLHU(x).B.TOT) - -/*! @brief Format value for bitfield CRC_CTRLHU_TOT. */ -#define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT) - -/*! @brief Set the TOT field to a new value. */ -#define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v))) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_crc_t - module struct - ******************************************************************************/ -/*! - * @brief All CRC module registers. - */ -#pragma pack(1) -typedef struct _hw_crc -{ - union { - struct { - __IO hw_crc_datal_t DATAL; /*!< [0x0] CRC_DATAL register. */ - __IO hw_crc_datah_t DATAH; /*!< [0x2] CRC_DATAH register. */ - } ACCESS16BIT; - struct { - __IO hw_crc_datall_t DATALL; /*!< [0x0] CRC_DATALL register. */ - __IO hw_crc_datalu_t DATALU; /*!< [0x1] CRC_DATALU register. */ - __IO hw_crc_datahl_t DATAHL; /*!< [0x2] CRC_DATAHL register. */ - __IO hw_crc_datahu_t DATAHU; /*!< [0x3] CRC_DATAHU register. */ - } ACCESS8BIT; - __IO hw_crc_data_t DATA; /*!< [0x0] CRC Data register */ - }; - union { - __IO hw_crc_gpoly_t GPOLY; /*!< [0x4] CRC Polynomial register */ - struct { - __IO hw_crc_gpolyl_t GPOLYL; /*!< [0x4] CRC_GPOLYL register. */ - __IO hw_crc_gpolyh_t GPOLYH; /*!< [0x6] CRC_GPOLYH register. */ - } GPOLY_ACCESS16BIT; - struct { - __IO hw_crc_gpolyll_t GPOLYLL; /*!< [0x4] CRC_GPOLYLL register. */ - __IO hw_crc_gpolylu_t GPOLYLU; /*!< [0x5] CRC_GPOLYLU register. */ - __IO hw_crc_gpolyhl_t GPOLYHL; /*!< [0x6] CRC_GPOLYHL register. */ - __IO hw_crc_gpolyhu_t GPOLYHU; /*!< [0x7] CRC_GPOLYHU register. */ - } GPOLY_ACCESS8BIT; - }; - union { - __IO hw_crc_ctrl_t CTRL; /*!< [0x8] CRC Control register */ - struct { - uint8_t _reserved0[3]; - __IO hw_crc_ctrlhu_t CTRLHU; /*!< [0xB] CRC_CTRLHU register. */ - } CTRL_ACCESS8BIT; - }; -} hw_crc_t; -#pragma pack() - -/*! @brief Macro to access all CRC registers. */ -/*! @param x CRC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_CRC(CRC_BASE). */ -#define HW_CRC(x) (*(hw_crc_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_CRC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dac.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dac.h deleted file mode 100644 index ab8fcf5364b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dac.h +++ /dev/null @@ -1,818 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_DAC_REGISTERS_H__ -#define __HW_DAC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 DAC - * - * 12-Bit Digital-to-Analog Converter - * - * Registers defined in this header file: - * - HW_DAC_DATnL - DAC Data Low Register - * - HW_DAC_DATnH - DAC Data High Register - * - HW_DAC_SR - DAC Status Register - * - HW_DAC_C0 - DAC Control Register - * - HW_DAC_C1 - DAC Control Register 1 - * - HW_DAC_C2 - DAC Control Register 2 - * - * - hw_dac_t - Struct containing all module registers. - */ - -#define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */ -#define HW_DAC0 (0U) /*!< Instance number for DAC0. */ -#define HW_DAC1 (1U) /*!< Instance number for DAC1. */ - -/******************************************************************************* - * HW_DAC_DATnL - DAC Data Low Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_DATnL - DAC Data Low Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_dac_datnl -{ - uint8_t U; - struct _hw_dac_datnl_bitfields - { - uint8_t DATA0 : 8; /*!< [7:0] */ - } B; -} hw_dac_datnl_t; - -/*! - * @name Constants and macros for entire DAC_DATnL register - */ -/*@{*/ -#define HW_DAC_DATnL_COUNT (16U) - -#define HW_DAC_DATnL_ADDR(x, n) ((x) + 0x0U + (0x2U * (n))) - -#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n)) -#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U) -#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v)) -#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v))) -#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v))) -#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_DATnL bitfields - */ - -/*! - * @name Register DAC_DATnL, field DATA0[7:0] (RW) - * - * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage - * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the - * DAC buffer is enabled, DATA is mapped to the 16-word buffer. - */ -/*@{*/ -#define BP_DAC_DATnL_DATA0 (0U) /*!< Bit position for DAC_DATnL_DATA0. */ -#define BM_DAC_DATnL_DATA0 (0xFFU) /*!< Bit mask for DAC_DATnL_DATA0. */ -#define BS_DAC_DATnL_DATA0 (8U) /*!< Bit field size in bits for DAC_DATnL_DATA0. */ - -/*! @brief Read current value of the DAC_DATnL_DATA0 field. */ -#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U) - -/*! @brief Format value for bitfield DAC_DATnL_DATA0. */ -#define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0) - -/*! @brief Set the DATA0 field to a new value. */ -#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DAC_DATnH - DAC Data High Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_DATnH - DAC Data High Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_dac_datnh -{ - uint8_t U; - struct _hw_dac_datnh_bitfields - { - uint8_t DATA1 : 4; /*!< [3:0] */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_dac_datnh_t; - -/*! - * @name Constants and macros for entire DAC_DATnH register - */ -/*@{*/ -#define HW_DAC_DATnH_COUNT (16U) - -#define HW_DAC_DATnH_ADDR(x, n) ((x) + 0x1U + (0x2U * (n))) - -#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n)) -#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U) -#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v)) -#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v))) -#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v))) -#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_DATnH bitfields - */ - -/*! - * @name Register DAC_DATnH, field DATA1[3:0] (RW) - * - * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage - * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the - * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. - */ -/*@{*/ -#define BP_DAC_DATnH_DATA1 (0U) /*!< Bit position for DAC_DATnH_DATA1. */ -#define BM_DAC_DATnH_DATA1 (0x0FU) /*!< Bit mask for DAC_DATnH_DATA1. */ -#define BS_DAC_DATnH_DATA1 (4U) /*!< Bit field size in bits for DAC_DATnH_DATA1. */ - -/*! @brief Read current value of the DAC_DATnH_DATA1 field. */ -#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1) - -/*! @brief Format value for bitfield DAC_DATnH_DATA1. */ -#define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1) - -/*! @brief Set the DATA1 field to a new value. */ -#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v))) -/*@}*/ - -/******************************************************************************* - * HW_DAC_SR - DAC Status Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_SR - DAC Status Register (RW) - * - * Reset value: 0x02U - * - * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA - * request is done. Writing 0 to a field clears it whereas writing 1 has no - * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed. - * The flags are set only when the data buffer status is changed. Do not use - * 32/16-bit accesses to this register. - */ -typedef union _hw_dac_sr -{ - uint8_t U; - struct _hw_dac_sr_bitfields - { - uint8_t DACBFRPBF : 1; /*!< [0] DAC Buffer Read Pointer Bottom - * Position Flag */ - uint8_t DACBFRPTF : 1; /*!< [1] DAC Buffer Read Pointer Top Position - * Flag */ - uint8_t DACBFWMF : 1; /*!< [2] DAC Buffer Watermark Flag */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_dac_sr_t; - -/*! - * @name Constants and macros for entire DAC_SR register - */ -/*@{*/ -#define HW_DAC_SR_ADDR(x) ((x) + 0x20U) - -#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x)) -#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U) -#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v)) -#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v))) -#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v))) -#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_SR bitfields - */ - -/*! - * @name Register DAC_SR, field DACBFRPBF[0] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP]. - * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP]. - */ -/*@{*/ -#define BP_DAC_SR_DACBFRPBF (0U) /*!< Bit position for DAC_SR_DACBFRPBF. */ -#define BM_DAC_SR_DACBFRPBF (0x01U) /*!< Bit mask for DAC_SR_DACBFRPBF. */ -#define BS_DAC_SR_DACBFRPBF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */ - -/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */ -#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF)) - -/*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */ -#define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF) - -/*! @brief Set the DACBFRPBF field to a new value. */ -#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v)) -/*@}*/ - -/*! - * @name Register DAC_SR, field DACBFRPTF[1] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer is not zero. - * - 1 - The DAC buffer read pointer is zero. - */ -/*@{*/ -#define BP_DAC_SR_DACBFRPTF (1U) /*!< Bit position for DAC_SR_DACBFRPTF. */ -#define BM_DAC_SR_DACBFRPTF (0x02U) /*!< Bit mask for DAC_SR_DACBFRPTF. */ -#define BS_DAC_SR_DACBFRPTF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */ - -/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */ -#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF)) - -/*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */ -#define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF) - -/*! @brief Set the DACBFRPTF field to a new value. */ -#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v)) -/*@}*/ - -/*! - * @name Register DAC_SR, field DACBFWMF[2] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer has not reached the watermark level. - * - 1 - The DAC buffer read pointer has reached the watermark level. - */ -/*@{*/ -#define BP_DAC_SR_DACBFWMF (2U) /*!< Bit position for DAC_SR_DACBFWMF. */ -#define BM_DAC_SR_DACBFWMF (0x04U) /*!< Bit mask for DAC_SR_DACBFWMF. */ -#define BS_DAC_SR_DACBFWMF (1U) /*!< Bit field size in bits for DAC_SR_DACBFWMF. */ - -/*! @brief Read current value of the DAC_SR_DACBFWMF field. */ -#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF)) - -/*! @brief Format value for bitfield DAC_SR_DACBFWMF. */ -#define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF) - -/*! @brief Set the DACBFWMF field to a new value. */ -#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DAC_C0 - DAC Control Register - ******************************************************************************/ - -/*! - * @brief HW_DAC_C0 - DAC Control Register (RW) - * - * Reset value: 0x00U - * - * Do not use 32- or 16-bit accesses to this register. - */ -typedef union _hw_dac_c0 -{ - uint8_t U; - struct _hw_dac_c0_bitfields - { - uint8_t DACBBIEN : 1; /*!< [0] DAC Buffer Read Pointer Bottom Flag - * Interrupt Enable */ - uint8_t DACBTIEN : 1; /*!< [1] DAC Buffer Read Pointer Top Flag - * Interrupt Enable */ - uint8_t DACBWIEN : 1; /*!< [2] DAC Buffer Watermark Interrupt Enable - * */ - uint8_t LPEN : 1; /*!< [3] DAC Low Power Control */ - uint8_t DACSWTRG : 1; /*!< [4] DAC Software Trigger */ - uint8_t DACTRGSEL : 1; /*!< [5] DAC Trigger Select */ - uint8_t DACRFS : 1; /*!< [6] DAC Reference Select */ - uint8_t DACEN : 1; /*!< [7] DAC Enable */ - } B; -} hw_dac_c0_t; - -/*! - * @name Constants and macros for entire DAC_C0 register - */ -/*@{*/ -#define HW_DAC_C0_ADDR(x) ((x) + 0x21U) - -#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x)) -#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U) -#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v)) -#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v))) -#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v))) -#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_C0 bitfields - */ - -/*! - * @name Register DAC_C0, field DACBBIEN[0] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled. - * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACBBIEN (0U) /*!< Bit position for DAC_C0_DACBBIEN. */ -#define BM_DAC_C0_DACBBIEN (0x01U) /*!< Bit mask for DAC_C0_DACBBIEN. */ -#define BS_DAC_C0_DACBBIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBBIEN. */ - -/*! @brief Read current value of the DAC_C0_DACBBIEN field. */ -#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN)) - -/*! @brief Format value for bitfield DAC_C0_DACBBIEN. */ -#define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN) - -/*! @brief Set the DACBBIEN field to a new value. */ -#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACBTIEN[1] (RW) - * - * Values: - * - 0 - The DAC buffer read pointer top flag interrupt is disabled. - * - 1 - The DAC buffer read pointer top flag interrupt is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACBTIEN (1U) /*!< Bit position for DAC_C0_DACBTIEN. */ -#define BM_DAC_C0_DACBTIEN (0x02U) /*!< Bit mask for DAC_C0_DACBTIEN. */ -#define BS_DAC_C0_DACBTIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBTIEN. */ - -/*! @brief Read current value of the DAC_C0_DACBTIEN field. */ -#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN)) - -/*! @brief Format value for bitfield DAC_C0_DACBTIEN. */ -#define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN) - -/*! @brief Set the DACBTIEN field to a new value. */ -#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACBWIEN[2] (RW) - * - * Values: - * - 0 - The DAC buffer watermark interrupt is disabled. - * - 1 - The DAC buffer watermark interrupt is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACBWIEN (2U) /*!< Bit position for DAC_C0_DACBWIEN. */ -#define BM_DAC_C0_DACBWIEN (0x04U) /*!< Bit mask for DAC_C0_DACBWIEN. */ -#define BS_DAC_C0_DACBWIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBWIEN. */ - -/*! @brief Read current value of the DAC_C0_DACBWIEN field. */ -#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN)) - -/*! @brief Format value for bitfield DAC_C0_DACBWIEN. */ -#define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN) - -/*! @brief Set the DACBWIEN field to a new value. */ -#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field LPEN[3] (RW) - * - * See the 12-bit DAC electrical characteristics of the device data sheet for - * details on the impact of the modes below. - * - * Values: - * - 0 - High-Power mode - * - 1 - Low-Power mode - */ -/*@{*/ -#define BP_DAC_C0_LPEN (3U) /*!< Bit position for DAC_C0_LPEN. */ -#define BM_DAC_C0_LPEN (0x08U) /*!< Bit mask for DAC_C0_LPEN. */ -#define BS_DAC_C0_LPEN (1U) /*!< Bit field size in bits for DAC_C0_LPEN. */ - -/*! @brief Read current value of the DAC_C0_LPEN field. */ -#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN)) - -/*! @brief Format value for bitfield DAC_C0_LPEN. */ -#define BF_DAC_C0_LPEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN) - -/*! @brief Set the LPEN field to a new value. */ -#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACSWTRG[4] (WORZ) - * - * Active high. This is a write-only field, which always reads 0. If DAC - * software trigger is selected and buffer is enabled, writing 1 to this field will - * advance the buffer read pointer once. - * - * Values: - * - 0 - The DAC soft trigger is not valid. - * - 1 - The DAC soft trigger is valid. - */ -/*@{*/ -#define BP_DAC_C0_DACSWTRG (4U) /*!< Bit position for DAC_C0_DACSWTRG. */ -#define BM_DAC_C0_DACSWTRG (0x10U) /*!< Bit mask for DAC_C0_DACSWTRG. */ -#define BS_DAC_C0_DACSWTRG (1U) /*!< Bit field size in bits for DAC_C0_DACSWTRG. */ - -/*! @brief Format value for bitfield DAC_C0_DACSWTRG. */ -#define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG) - -/*! @brief Set the DACSWTRG field to a new value. */ -#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACTRGSEL[5] (RW) - * - * Values: - * - 0 - The DAC hardware trigger is selected. - * - 1 - The DAC software trigger is selected. - */ -/*@{*/ -#define BP_DAC_C0_DACTRGSEL (5U) /*!< Bit position for DAC_C0_DACTRGSEL. */ -#define BM_DAC_C0_DACTRGSEL (0x20U) /*!< Bit mask for DAC_C0_DACTRGSEL. */ -#define BS_DAC_C0_DACTRGSEL (1U) /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */ - -/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */ -#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL)) - -/*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */ -#define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL) - -/*! @brief Set the DACTRGSEL field to a new value. */ -#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACRFS[6] (RW) - * - * Values: - * - 0 - The DAC selects DACREF_1 as the reference voltage. - * - 1 - The DAC selects DACREF_2 as the reference voltage. - */ -/*@{*/ -#define BP_DAC_C0_DACRFS (6U) /*!< Bit position for DAC_C0_DACRFS. */ -#define BM_DAC_C0_DACRFS (0x40U) /*!< Bit mask for DAC_C0_DACRFS. */ -#define BS_DAC_C0_DACRFS (1U) /*!< Bit field size in bits for DAC_C0_DACRFS. */ - -/*! @brief Read current value of the DAC_C0_DACRFS field. */ -#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS)) - -/*! @brief Format value for bitfield DAC_C0_DACRFS. */ -#define BF_DAC_C0_DACRFS(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS) - -/*! @brief Set the DACRFS field to a new value. */ -#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C0, field DACEN[7] (RW) - * - * Starts the Programmable Reference Generator operation. - * - * Values: - * - 0 - The DAC system is disabled. - * - 1 - The DAC system is enabled. - */ -/*@{*/ -#define BP_DAC_C0_DACEN (7U) /*!< Bit position for DAC_C0_DACEN. */ -#define BM_DAC_C0_DACEN (0x80U) /*!< Bit mask for DAC_C0_DACEN. */ -#define BS_DAC_C0_DACEN (1U) /*!< Bit field size in bits for DAC_C0_DACEN. */ - -/*! @brief Read current value of the DAC_C0_DACEN field. */ -#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN)) - -/*! @brief Format value for bitfield DAC_C0_DACEN. */ -#define BF_DAC_C0_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN) - -/*! @brief Set the DACEN field to a new value. */ -#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DAC_C1 - DAC Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_DAC_C1 - DAC Control Register 1 (RW) - * - * Reset value: 0x00U - * - * Do not use 32- or 16-bit accesses to this register. - */ -typedef union _hw_dac_c1 -{ - uint8_t U; - struct _hw_dac_c1_bitfields - { - uint8_t DACBFEN : 1; /*!< [0] DAC Buffer Enable */ - uint8_t DACBFMD : 2; /*!< [2:1] DAC Buffer Work Mode Select */ - uint8_t DACBFWM : 2; /*!< [4:3] DAC Buffer Watermark Select */ - uint8_t RESERVED0 : 2; /*!< [6:5] */ - uint8_t DMAEN : 1; /*!< [7] DMA Enable Select */ - } B; -} hw_dac_c1_t; - -/*! - * @name Constants and macros for entire DAC_C1 register - */ -/*@{*/ -#define HW_DAC_C1_ADDR(x) ((x) + 0x22U) - -#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x)) -#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U) -#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v)) -#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v))) -#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v))) -#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_C1 bitfields - */ - -/*! - * @name Register DAC_C1, field DACBFEN[0] (RW) - * - * Values: - * - 0 - Buffer read pointer is disabled. The converted data is always the first - * word of the buffer. - * - 1 - Buffer read pointer is enabled. The converted data is the word that the - * read pointer points to. It means converted data can be from any word of - * the buffer. - */ -/*@{*/ -#define BP_DAC_C1_DACBFEN (0U) /*!< Bit position for DAC_C1_DACBFEN. */ -#define BM_DAC_C1_DACBFEN (0x01U) /*!< Bit mask for DAC_C1_DACBFEN. */ -#define BS_DAC_C1_DACBFEN (1U) /*!< Bit field size in bits for DAC_C1_DACBFEN. */ - -/*! @brief Read current value of the DAC_C1_DACBFEN field. */ -#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN)) - -/*! @brief Format value for bitfield DAC_C1_DACBFEN. */ -#define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN) - -/*! @brief Set the DACBFEN field to a new value. */ -#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v)) -/*@}*/ - -/*! - * @name Register DAC_C1, field DACBFMD[2:1] (RW) - * - * Values: - * - 00 - Normal mode - * - 01 - Swing mode - * - 10 - One-Time Scan mode - * - 11 - Reserved - */ -/*@{*/ -#define BP_DAC_C1_DACBFMD (1U) /*!< Bit position for DAC_C1_DACBFMD. */ -#define BM_DAC_C1_DACBFMD (0x06U) /*!< Bit mask for DAC_C1_DACBFMD. */ -#define BS_DAC_C1_DACBFMD (2U) /*!< Bit field size in bits for DAC_C1_DACBFMD. */ - -/*! @brief Read current value of the DAC_C1_DACBFMD field. */ -#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD) - -/*! @brief Format value for bitfield DAC_C1_DACBFMD. */ -#define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD) - -/*! @brief Set the DACBFMD field to a new value. */ -#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v))) -/*@}*/ - -/*! - * @name Register DAC_C1, field DACBFWM[4:3] (RW) - * - * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches - * the word defined by this field, which is 1-4 words away from the upper limit - * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the - * watermark interrupt. - * - * Values: - * - 00 - 1 word - * - 01 - 2 words - * - 10 - 3 words - * - 11 - 4 words - */ -/*@{*/ -#define BP_DAC_C1_DACBFWM (3U) /*!< Bit position for DAC_C1_DACBFWM. */ -#define BM_DAC_C1_DACBFWM (0x18U) /*!< Bit mask for DAC_C1_DACBFWM. */ -#define BS_DAC_C1_DACBFWM (2U) /*!< Bit field size in bits for DAC_C1_DACBFWM. */ - -/*! @brief Read current value of the DAC_C1_DACBFWM field. */ -#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM) - -/*! @brief Format value for bitfield DAC_C1_DACBFWM. */ -#define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM) - -/*! @brief Set the DACBFWM field to a new value. */ -#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v))) -/*@}*/ - -/*! - * @name Register DAC_C1, field DMAEN[7] (RW) - * - * Values: - * - 0 - DMA is disabled. - * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated - * by original interrupts. The interrupts will not be presented on this - * module at the same time. - */ -/*@{*/ -#define BP_DAC_C1_DMAEN (7U) /*!< Bit position for DAC_C1_DMAEN. */ -#define BM_DAC_C1_DMAEN (0x80U) /*!< Bit mask for DAC_C1_DMAEN. */ -#define BS_DAC_C1_DMAEN (1U) /*!< Bit field size in bits for DAC_C1_DMAEN. */ - -/*! @brief Read current value of the DAC_C1_DMAEN field. */ -#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN)) - -/*! @brief Format value for bitfield DAC_C1_DMAEN. */ -#define BF_DAC_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DAC_C2 - DAC Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_DAC_C2 - DAC Control Register 2 (RW) - * - * Reset value: 0x0FU - */ -typedef union _hw_dac_c2 -{ - uint8_t U; - struct _hw_dac_c2_bitfields - { - uint8_t DACBFUP : 4; /*!< [3:0] DAC Buffer Upper Limit */ - uint8_t DACBFRP : 4; /*!< [7:4] DAC Buffer Read Pointer */ - } B; -} hw_dac_c2_t; - -/*! - * @name Constants and macros for entire DAC_C2 register - */ -/*@{*/ -#define HW_DAC_C2_ADDR(x) ((x) + 0x23U) - -#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x)) -#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U) -#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v)) -#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v))) -#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v))) -#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DAC_C2 bitfields - */ - -/*! - * @name Register DAC_C2, field DACBFUP[3:0] (RW) - * - * Selects the upper limit of the DAC buffer. The buffer read pointer cannot - * exceed it. - */ -/*@{*/ -#define BP_DAC_C2_DACBFUP (0U) /*!< Bit position for DAC_C2_DACBFUP. */ -#define BM_DAC_C2_DACBFUP (0x0FU) /*!< Bit mask for DAC_C2_DACBFUP. */ -#define BS_DAC_C2_DACBFUP (4U) /*!< Bit field size in bits for DAC_C2_DACBFUP. */ - -/*! @brief Read current value of the DAC_C2_DACBFUP field. */ -#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP) - -/*! @brief Format value for bitfield DAC_C2_DACBFUP. */ -#define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP) - -/*! @brief Set the DACBFUP field to a new value. */ -#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v))) -/*@}*/ - -/*! - * @name Register DAC_C2, field DACBFRP[7:4] (RW) - * - * Keeps the current value of the buffer read pointer. - */ -/*@{*/ -#define BP_DAC_C2_DACBFRP (4U) /*!< Bit position for DAC_C2_DACBFRP. */ -#define BM_DAC_C2_DACBFRP (0xF0U) /*!< Bit mask for DAC_C2_DACBFRP. */ -#define BS_DAC_C2_DACBFRP (4U) /*!< Bit field size in bits for DAC_C2_DACBFRP. */ - -/*! @brief Read current value of the DAC_C2_DACBFRP field. */ -#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP) - -/*! @brief Format value for bitfield DAC_C2_DACBFRP. */ -#define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP) - -/*! @brief Set the DACBFRP field to a new value. */ -#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v))) -/*@}*/ - -/******************************************************************************* - * hw_dac_t - module struct - ******************************************************************************/ -/*! - * @brief All DAC module registers. - */ -#pragma pack(1) -typedef struct _hw_dac -{ - struct { - __IO hw_dac_datnl_t DATnL; /*!< [0x0] DAC Data Low Register */ - __IO hw_dac_datnh_t DATnH; /*!< [0x1] DAC Data High Register */ - } DAT[16]; - __IO hw_dac_sr_t SR; /*!< [0x20] DAC Status Register */ - __IO hw_dac_c0_t C0; /*!< [0x21] DAC Control Register */ - __IO hw_dac_c1_t C1; /*!< [0x22] DAC Control Register 1 */ - __IO hw_dac_c2_t C2; /*!< [0x23] DAC Control Register 2 */ -} hw_dac_t; -#pragma pack() - -/*! @brief Macro to access all DAC registers. */ -/*! @param x DAC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_DAC(DAC0_BASE). */ -#define HW_DAC(x) (*(hw_dac_t *)(x)) - -#endif /* __HW_DAC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dma.h deleted file mode 100644 index af6fdc05722..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dma.h +++ /dev/null @@ -1,5365 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_DMA_REGISTERS_H__ -#define __HW_DMA_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 DMA - * - * Enhanced direct memory access controller - * - * Registers defined in this header file: - * - HW_DMA_CR - Control Register - * - HW_DMA_ES - Error Status Register - * - HW_DMA_ERQ - Enable Request Register - * - HW_DMA_EEI - Enable Error Interrupt Register - * - HW_DMA_CEEI - Clear Enable Error Interrupt Register - * - HW_DMA_SEEI - Set Enable Error Interrupt Register - * - HW_DMA_CERQ - Clear Enable Request Register - * - HW_DMA_SERQ - Set Enable Request Register - * - HW_DMA_CDNE - Clear DONE Status Bit Register - * - HW_DMA_SSRT - Set START Bit Register - * - HW_DMA_CERR - Clear Error Register - * - HW_DMA_CINT - Clear Interrupt Request Register - * - HW_DMA_INT - Interrupt Request Register - * - HW_DMA_ERR - Error Register - * - HW_DMA_HRS - Hardware Request Status Register - * - HW_DMA_DCHPRIn - Channel n Priority Register - * - HW_DMA_TCDn_SADDR - TCD Source Address - * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset - * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes - * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) - * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) - * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) - * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment - * - HW_DMA_TCDn_DADDR - TCD Destination Address - * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset - * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) - * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) - * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address - * - HW_DMA_TCDn_CSR - TCD Control and Status - * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) - * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) - * - * - hw_dma_t - Struct containing all module registers. - */ - -#define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */ - -/******************************************************************************* - * HW_DMA_CR - Control Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CR - Control Register (RW) - * - * Reset value: 0x00000000U - * - * The CR defines the basic operating configuration of the DMA. Arbitration can - * be configured to use either a fixed-priority or a round-robin scheme. For - * fixed-priority arbitration, the highest priority channel requesting service is - * selected to execute. The channel priority registers assign the priorities; see - * the DCHPRIn registers. For round-robin arbitration, the channel priorities are - * ignored and channels are cycled through (from high to low channel number) - * without regard to priority. For correct operation, writes to the CR register must - * be performed only when the DMA channels are inactive; that is, when - * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to - * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon - * minor loop completion. When minor loop offsets are enabled, the minor loop - * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final - * destination address (TCDn_DADDR), or to both prior to the addresses being - * written back into the TCD. If the major loop is complete, the minor loop offset is - * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are - * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop - * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 - * is used to specify multiple fields: a source enable bit (SMLOE) to specify - * the minor loop offset should be applied to the source address (TCDn_SADDR) upon - * minor loop completion, a destination enable bit (DMLOE) to specify the minor - * loop offset should be applied to the destination address (TCDn_DADDR) upon - * minor loop completion, and the sign extended minor loop offset value (MLOFF). The - * same offset value (MLOFF) is used for both source and destination minor loop - * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the - * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled - * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When - * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are - * assigned to the NBYTES field. - */ -typedef union _hw_dma_cr -{ - uint32_t U; - struct _hw_dma_cr_bitfields - { - uint32_t RESERVED0 : 1; /*!< [0] Reserved. */ - uint32_t EDBG : 1; /*!< [1] Enable Debug */ - uint32_t ERCA : 1; /*!< [2] Enable Round Robin Channel Arbitration */ - uint32_t RESERVED1 : 1; /*!< [3] Reserved. */ - uint32_t HOE : 1; /*!< [4] Halt On Error */ - uint32_t HALT : 1; /*!< [5] Halt DMA Operations */ - uint32_t CLM : 1; /*!< [6] Continuous Link Mode */ - uint32_t EMLM : 1; /*!< [7] Enable Minor Loop Mapping */ - uint32_t RESERVED2 : 8; /*!< [15:8] */ - uint32_t ECX : 1; /*!< [16] Error Cancel Transfer */ - uint32_t CX : 1; /*!< [17] Cancel Transfer */ - uint32_t RESERVED3 : 14; /*!< [31:18] */ - } B; -} hw_dma_cr_t; - -/*! - * @name Constants and macros for entire DMA_CR register - */ -/*@{*/ -#define HW_DMA_CR_ADDR(x) ((x) + 0x0U) - -#define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x)) -#define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U) -#define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v)) -#define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v))) -#define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v))) -#define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_CR bitfields - */ - -/*! - * @name Register DMA_CR, field EDBG[1] (RW) - * - * Values: - * - 0 - When in debug mode, the DMA continues to operate. - * - 1 - When in debug mode, the DMA stalls the start of a new channel. - * Executing channels are allowed to complete. Channel execution resumes when the - * system exits debug mode or the EDBG bit is cleared. - */ -/*@{*/ -#define BP_DMA_CR_EDBG (1U) /*!< Bit position for DMA_CR_EDBG. */ -#define BM_DMA_CR_EDBG (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */ -#define BS_DMA_CR_EDBG (1U) /*!< Bit field size in bits for DMA_CR_EDBG. */ - -/*! @brief Read current value of the DMA_CR_EDBG field. */ -#define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG)) - -/*! @brief Format value for bitfield DMA_CR_EDBG. */ -#define BF_DMA_CR_EDBG(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG) - -/*! @brief Set the EDBG field to a new value. */ -#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field ERCA[2] (RW) - * - * Values: - * - 0 - Fixed priority arbitration is used for channel selection . - * - 1 - Round robin arbitration is used for channel selection . - */ -/*@{*/ -#define BP_DMA_CR_ERCA (2U) /*!< Bit position for DMA_CR_ERCA. */ -#define BM_DMA_CR_ERCA (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */ -#define BS_DMA_CR_ERCA (1U) /*!< Bit field size in bits for DMA_CR_ERCA. */ - -/*! @brief Read current value of the DMA_CR_ERCA field. */ -#define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA)) - -/*! @brief Format value for bitfield DMA_CR_ERCA. */ -#define BF_DMA_CR_ERCA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA) - -/*! @brief Set the ERCA field to a new value. */ -#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field HOE[4] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Any error causes the HALT bit to set. Subsequently, all service - * requests are ignored until the HALT bit is cleared. - */ -/*@{*/ -#define BP_DMA_CR_HOE (4U) /*!< Bit position for DMA_CR_HOE. */ -#define BM_DMA_CR_HOE (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */ -#define BS_DMA_CR_HOE (1U) /*!< Bit field size in bits for DMA_CR_HOE. */ - -/*! @brief Read current value of the DMA_CR_HOE field. */ -#define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE)) - -/*! @brief Format value for bitfield DMA_CR_HOE. */ -#define BF_DMA_CR_HOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE) - -/*! @brief Set the HOE field to a new value. */ -#define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field HALT[5] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Stall the start of any new channels. Executing channels are allowed to - * complete. Channel execution resumes when this bit is cleared. - */ -/*@{*/ -#define BP_DMA_CR_HALT (5U) /*!< Bit position for DMA_CR_HALT. */ -#define BM_DMA_CR_HALT (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */ -#define BS_DMA_CR_HALT (1U) /*!< Bit field size in bits for DMA_CR_HALT. */ - -/*! @brief Read current value of the DMA_CR_HALT field. */ -#define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT)) - -/*! @brief Format value for bitfield DMA_CR_HALT. */ -#define BF_DMA_CR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT) - -/*! @brief Set the HALT field to a new value. */ -#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field CLM[6] (RW) - * - * Values: - * - 0 - A minor loop channel link made to itself goes through channel - * arbitration before being activated again. - * - 1 - A minor loop channel link made to itself does not go through channel - * arbitration before being activated again. Upon minor loop completion, the - * channel activates again if that channel has a minor loop channel link - * enabled and the link channel is itself. This effectively applies the minor loop - * offsets and restarts the next minor loop. - */ -/*@{*/ -#define BP_DMA_CR_CLM (6U) /*!< Bit position for DMA_CR_CLM. */ -#define BM_DMA_CR_CLM (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */ -#define BS_DMA_CR_CLM (1U) /*!< Bit field size in bits for DMA_CR_CLM. */ - -/*! @brief Read current value of the DMA_CR_CLM field. */ -#define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM)) - -/*! @brief Format value for bitfield DMA_CR_CLM. */ -#define BF_DMA_CR_CLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM) - -/*! @brief Set the CLM field to a new value. */ -#define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field EMLM[7] (RW) - * - * Values: - * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. - * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields, - * an offset field, and the NBYTES field. The individual enable fields allow - * the minor loop offset to be applied to the source address, the destination - * address, or both. The NBYTES field is reduced when either offset is - * enabled. - */ -/*@{*/ -#define BP_DMA_CR_EMLM (7U) /*!< Bit position for DMA_CR_EMLM. */ -#define BM_DMA_CR_EMLM (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */ -#define BS_DMA_CR_EMLM (1U) /*!< Bit field size in bits for DMA_CR_EMLM. */ - -/*! @brief Read current value of the DMA_CR_EMLM field. */ -#define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM)) - -/*! @brief Format value for bitfield DMA_CR_EMLM. */ -#define BF_DMA_CR_EMLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM) - -/*! @brief Set the EMLM field to a new value. */ -#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field ECX[16] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit. - * Stop the executing channel and force the minor loop to finish. The cancel - * takes effect after the last write of the current read/write sequence. The - * ECX bit clears itself after the cancel is honored. In addition to - * cancelling the transfer, ECX treats the cancel as an error condition, thus updating - * the Error Status register (DMAx_ES) and generating an optional error - * interrupt. - */ -/*@{*/ -#define BP_DMA_CR_ECX (16U) /*!< Bit position for DMA_CR_ECX. */ -#define BM_DMA_CR_ECX (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */ -#define BS_DMA_CR_ECX (1U) /*!< Bit field size in bits for DMA_CR_ECX. */ - -/*! @brief Read current value of the DMA_CR_ECX field. */ -#define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX)) - -/*! @brief Format value for bitfield DMA_CR_ECX. */ -#define BF_DMA_CR_ECX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX) - -/*! @brief Set the ECX field to a new value. */ -#define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CR, field CX[17] (RW) - * - * Values: - * - 0 - Normal operation - * - 1 - Cancel the remaining data transfer. Stop the executing channel and - * force the minor loop to finish. The cancel takes effect after the last write - * of the current read/write sequence. The CX bit clears itself after the - * cancel has been honored. This cancel retires the channel normally as if the - * minor loop was completed. - */ -/*@{*/ -#define BP_DMA_CR_CX (17U) /*!< Bit position for DMA_CR_CX. */ -#define BM_DMA_CR_CX (0x00020000U) /*!< Bit mask for DMA_CR_CX. */ -#define BS_DMA_CR_CX (1U) /*!< Bit field size in bits for DMA_CR_CX. */ - -/*! @brief Read current value of the DMA_CR_CX field. */ -#define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX)) - -/*! @brief Format value for bitfield DMA_CR_CX. */ -#define BF_DMA_CR_CX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX) - -/*! @brief Set the CX field to a new value. */ -#define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_ES - Error Status Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_ES - Error Status Register (RO) - * - * Reset value: 0x00000000U - * - * The ES provides information concerning the last recorded channel error. - * Channel errors can be caused by: A configuration error, that is: An illegal setting - * in the transfer-control descriptor, or An illegal priority register setting - * in fixed-arbitration An error termination to a bus master read or write cycle - * See the Error Reporting and Handling section for more details. - */ -typedef union _hw_dma_es -{ - uint32_t U; - struct _hw_dma_es_bitfields - { - uint32_t DBE : 1; /*!< [0] Destination Bus Error */ - uint32_t SBE : 1; /*!< [1] Source Bus Error */ - uint32_t SGE : 1; /*!< [2] Scatter/Gather Configuration Error */ - uint32_t NCE : 1; /*!< [3] NBYTES/CITER Configuration Error */ - uint32_t DOE : 1; /*!< [4] Destination Offset Error */ - uint32_t DAE : 1; /*!< [5] Destination Address Error */ - uint32_t SOE : 1; /*!< [6] Source Offset Error */ - uint32_t SAE : 1; /*!< [7] Source Address Error */ - uint32_t ERRCHN : 4; /*!< [11:8] Error Channel Number or Canceled - * Channel Number */ - uint32_t RESERVED0 : 2; /*!< [13:12] */ - uint32_t CPE : 1; /*!< [14] Channel Priority Error */ - uint32_t RESERVED1 : 1; /*!< [15] */ - uint32_t ECX : 1; /*!< [16] Transfer Canceled */ - uint32_t RESERVED2 : 14; /*!< [30:17] */ - uint32_t VLD : 1; /*!< [31] */ - } B; -} hw_dma_es_t; - -/*! - * @name Constants and macros for entire DMA_ES register - */ -/*@{*/ -#define HW_DMA_ES_ADDR(x) ((x) + 0x4U) - -#define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x)) -#define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U) -/*@}*/ - -/* - * Constants & macros for individual DMA_ES bitfields - */ - -/*! - * @name Register DMA_ES, field DBE[0] (RO) - * - * Values: - * - 0 - No destination bus error - * - 1 - The last recorded error was a bus error on a destination write - */ -/*@{*/ -#define BP_DMA_ES_DBE (0U) /*!< Bit position for DMA_ES_DBE. */ -#define BM_DMA_ES_DBE (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */ -#define BS_DMA_ES_DBE (1U) /*!< Bit field size in bits for DMA_ES_DBE. */ - -/*! @brief Read current value of the DMA_ES_DBE field. */ -#define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SBE[1] (RO) - * - * Values: - * - 0 - No source bus error - * - 1 - The last recorded error was a bus error on a source read - */ -/*@{*/ -#define BP_DMA_ES_SBE (1U) /*!< Bit position for DMA_ES_SBE. */ -#define BM_DMA_ES_SBE (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */ -#define BS_DMA_ES_SBE (1U) /*!< Bit field size in bits for DMA_ES_SBE. */ - -/*! @brief Read current value of the DMA_ES_SBE field. */ -#define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SGE[2] (RO) - * - * Values: - * - 0 - No scatter/gather configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather - * operation after major loop completion if TCDn_CSR[ESG] is enabled. - * TCDn_DLASTSGA is not on a 32 byte boundary. - */ -/*@{*/ -#define BP_DMA_ES_SGE (2U) /*!< Bit position for DMA_ES_SGE. */ -#define BM_DMA_ES_SGE (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */ -#define BS_DMA_ES_SGE (1U) /*!< Bit field size in bits for DMA_ES_SGE. */ - -/*! @brief Read current value of the DMA_ES_SGE field. */ -#define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field NCE[3] (RO) - * - * Values: - * - 0 - No NBYTES/CITER configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of - * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or - * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] - */ -/*@{*/ -#define BP_DMA_ES_NCE (3U) /*!< Bit position for DMA_ES_NCE. */ -#define BM_DMA_ES_NCE (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */ -#define BS_DMA_ES_NCE (1U) /*!< Bit field size in bits for DMA_ES_NCE. */ - -/*! @brief Read current value of the DMA_ES_NCE field. */ -#define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field DOE[4] (RO) - * - * Values: - * - 0 - No destination offset configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_DOE (4U) /*!< Bit position for DMA_ES_DOE. */ -#define BM_DMA_ES_DOE (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */ -#define BS_DMA_ES_DOE (1U) /*!< Bit field size in bits for DMA_ES_DOE. */ - -/*! @brief Read current value of the DMA_ES_DOE field. */ -#define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field DAE[5] (RO) - * - * Values: - * - 0 - No destination address configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_DAE (5U) /*!< Bit position for DMA_ES_DAE. */ -#define BM_DMA_ES_DAE (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */ -#define BS_DMA_ES_DAE (1U) /*!< Bit field size in bits for DMA_ES_DAE. */ - -/*! @brief Read current value of the DMA_ES_DAE field. */ -#define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SOE[6] (RO) - * - * Values: - * - 0 - No source offset configuration error - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_SOE (6U) /*!< Bit position for DMA_ES_SOE. */ -#define BM_DMA_ES_SOE (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */ -#define BS_DMA_ES_SOE (1U) /*!< Bit field size in bits for DMA_ES_SOE. */ - -/*! @brief Read current value of the DMA_ES_SOE field. */ -#define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field SAE[7] (RO) - * - * Values: - * - 0 - No source address configuration error. - * - 1 - The last recorded error was a configuration error detected in the - * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. - */ -/*@{*/ -#define BP_DMA_ES_SAE (7U) /*!< Bit position for DMA_ES_SAE. */ -#define BM_DMA_ES_SAE (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */ -#define BS_DMA_ES_SAE (1U) /*!< Bit field size in bits for DMA_ES_SAE. */ - -/*! @brief Read current value of the DMA_ES_SAE field. */ -#define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field ERRCHN[11:8] (RO) - * - * The channel number of the last recorded error (excluding CPE errors) or last - * recorded error canceled transfer. - */ -/*@{*/ -#define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */ -#define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */ -#define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */ - -/*! @brief Read current value of the DMA_ES_ERRCHN field. */ -#define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN) -/*@}*/ - -/*! - * @name Register DMA_ES, field CPE[14] (RO) - * - * Values: - * - 0 - No channel priority error - * - 1 - The last recorded error was a configuration error in the channel - * priorities . Channel priorities are not unique. - */ -/*@{*/ -#define BP_DMA_ES_CPE (14U) /*!< Bit position for DMA_ES_CPE. */ -#define BM_DMA_ES_CPE (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */ -#define BS_DMA_ES_CPE (1U) /*!< Bit field size in bits for DMA_ES_CPE. */ - -/*! @brief Read current value of the DMA_ES_CPE field. */ -#define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE)) -/*@}*/ - -/*! - * @name Register DMA_ES, field ECX[16] (RO) - * - * Values: - * - 0 - No canceled transfers - * - 1 - The last recorded entry was a canceled transfer by the error cancel - * transfer input - */ -/*@{*/ -#define BP_DMA_ES_ECX (16U) /*!< Bit position for DMA_ES_ECX. */ -#define BM_DMA_ES_ECX (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */ -#define BS_DMA_ES_ECX (1U) /*!< Bit field size in bits for DMA_ES_ECX. */ - -/*! @brief Read current value of the DMA_ES_ECX field. */ -#define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX)) -/*@}*/ - -/*! - * @name Register DMA_ES, field VLD[31] (RO) - * - * Logical OR of all ERR status bits - * - * Values: - * - 0 - No ERR bits are set - * - 1 - At least one ERR bit is set indicating a valid error exists that has - * not been cleared - */ -/*@{*/ -#define BP_DMA_ES_VLD (31U) /*!< Bit position for DMA_ES_VLD. */ -#define BM_DMA_ES_VLD (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */ -#define BS_DMA_ES_VLD (1U) /*!< Bit field size in bits for DMA_ES_VLD. */ - -/*! @brief Read current value of the DMA_ES_VLD field. */ -#define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_ERQ - Enable Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_ERQ - Enable Request Register (RW) - * - * Reset value: 0x00000000U - * - * The ERQ register provides a bit map for the 16 implemented channels to enable - * the request signal for each channel. The state of any given channel enable is - * directly affected by writes to this register; it is also affected by writes - * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable - * for a single channel can easily be modified without needing to perform a - * read-modify-write sequence to the ERQ. DMA request input signals and this enable - * request flag must be asserted before a channel's hardware service request is - * accepted. The state of the DMA enable request flag does not affect a channel - * service request made explicitly through software or a linked channel request. - */ -typedef union _hw_dma_erq -{ - uint32_t U; - struct _hw_dma_erq_bitfields - { - uint32_t ERQ0 : 1; /*!< [0] Enable DMA Request 0 */ - uint32_t ERQ1 : 1; /*!< [1] Enable DMA Request 1 */ - uint32_t ERQ2 : 1; /*!< [2] Enable DMA Request 2 */ - uint32_t ERQ3 : 1; /*!< [3] Enable DMA Request 3 */ - uint32_t ERQ4 : 1; /*!< [4] Enable DMA Request 4 */ - uint32_t ERQ5 : 1; /*!< [5] Enable DMA Request 5 */ - uint32_t ERQ6 : 1; /*!< [6] Enable DMA Request 6 */ - uint32_t ERQ7 : 1; /*!< [7] Enable DMA Request 7 */ - uint32_t ERQ8 : 1; /*!< [8] Enable DMA Request 8 */ - uint32_t ERQ9 : 1; /*!< [9] Enable DMA Request 9 */ - uint32_t ERQ10 : 1; /*!< [10] Enable DMA Request 10 */ - uint32_t ERQ11 : 1; /*!< [11] Enable DMA Request 11 */ - uint32_t ERQ12 : 1; /*!< [12] Enable DMA Request 12 */ - uint32_t ERQ13 : 1; /*!< [13] Enable DMA Request 13 */ - uint32_t ERQ14 : 1; /*!< [14] Enable DMA Request 14 */ - uint32_t ERQ15 : 1; /*!< [15] Enable DMA Request 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_erq_t; - -/*! - * @name Constants and macros for entire DMA_ERQ register - */ -/*@{*/ -#define HW_DMA_ERQ_ADDR(x) ((x) + 0xCU) - -#define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x)) -#define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U) -#define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v)) -#define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v))) -#define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v))) -#define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_ERQ bitfields - */ - -/*! - * @name Register DMA_ERQ, field ERQ0[0] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ0 (0U) /*!< Bit position for DMA_ERQ_ERQ0. */ -#define BM_DMA_ERQ_ERQ0 (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */ -#define BS_DMA_ERQ_ERQ0 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ0. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */ -#define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ0. */ -#define BF_DMA_ERQ_ERQ0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0) - -/*! @brief Set the ERQ0 field to a new value. */ -#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ1[1] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ1 (1U) /*!< Bit position for DMA_ERQ_ERQ1. */ -#define BM_DMA_ERQ_ERQ1 (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */ -#define BS_DMA_ERQ_ERQ1 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ1. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */ -#define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ1. */ -#define BF_DMA_ERQ_ERQ1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1) - -/*! @brief Set the ERQ1 field to a new value. */ -#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ2[2] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ2 (2U) /*!< Bit position for DMA_ERQ_ERQ2. */ -#define BM_DMA_ERQ_ERQ2 (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */ -#define BS_DMA_ERQ_ERQ2 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ2. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */ -#define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ2. */ -#define BF_DMA_ERQ_ERQ2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2) - -/*! @brief Set the ERQ2 field to a new value. */ -#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ3[3] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ3 (3U) /*!< Bit position for DMA_ERQ_ERQ3. */ -#define BM_DMA_ERQ_ERQ3 (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */ -#define BS_DMA_ERQ_ERQ3 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ3. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */ -#define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ3. */ -#define BF_DMA_ERQ_ERQ3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3) - -/*! @brief Set the ERQ3 field to a new value. */ -#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ4[4] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */ -#define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */ -#define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */ -#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ4. */ -#define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4) - -/*! @brief Set the ERQ4 field to a new value. */ -#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ5[5] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */ -#define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */ -#define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */ -#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ5. */ -#define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5) - -/*! @brief Set the ERQ5 field to a new value. */ -#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ6[6] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */ -#define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */ -#define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */ -#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ6. */ -#define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6) - -/*! @brief Set the ERQ6 field to a new value. */ -#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ7[7] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */ -#define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */ -#define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */ -#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ7. */ -#define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7) - -/*! @brief Set the ERQ7 field to a new value. */ -#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ8[8] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */ -#define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */ -#define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */ -#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ8. */ -#define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8) - -/*! @brief Set the ERQ8 field to a new value. */ -#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ9[9] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */ -#define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */ -#define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */ -#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ9. */ -#define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9) - -/*! @brief Set the ERQ9 field to a new value. */ -#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ10[10] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */ -#define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */ -#define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */ -#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ10. */ -#define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10) - -/*! @brief Set the ERQ10 field to a new value. */ -#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ11[11] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */ -#define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */ -#define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */ -#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ11. */ -#define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11) - -/*! @brief Set the ERQ11 field to a new value. */ -#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ12[12] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */ -#define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */ -#define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */ -#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ12. */ -#define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12) - -/*! @brief Set the ERQ12 field to a new value. */ -#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ13[13] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */ -#define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */ -#define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */ -#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ13. */ -#define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13) - -/*! @brief Set the ERQ13 field to a new value. */ -#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ14[14] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */ -#define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */ -#define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */ -#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ14. */ -#define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14) - -/*! @brief Set the ERQ14 field to a new value. */ -#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERQ, field ERQ15[15] (RW) - * - * Values: - * - 0 - The DMA request signal for the corresponding channel is disabled - * - 1 - The DMA request signal for the corresponding channel is enabled - */ -/*@{*/ -#define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */ -#define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */ -#define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */ - -/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */ -#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15)) - -/*! @brief Format value for bitfield DMA_ERQ_ERQ15. */ -#define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15) - -/*! @brief Set the ERQ15 field to a new value. */ -#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_EEI - Enable Error Interrupt Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW) - * - * Reset value: 0x00000000U - * - * The EEI register provides a bit map for the 16 channels to enable the error - * interrupt signal for each channel. The state of any given channel's error - * interrupt enable is directly affected by writes to this register; it is also - * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error - * interrupt enable for a single channel can easily be modified without the need to - * perform a read-modify-write sequence to the EEI register. The DMA error - * indicator and the error interrupt enable flag must be asserted before an error - * interrupt request for a given channel is asserted to the interrupt controller. - */ -typedef union _hw_dma_eei -{ - uint32_t U; - struct _hw_dma_eei_bitfields - { - uint32_t EEI0 : 1; /*!< [0] Enable Error Interrupt 0 */ - uint32_t EEI1 : 1; /*!< [1] Enable Error Interrupt 1 */ - uint32_t EEI2 : 1; /*!< [2] Enable Error Interrupt 2 */ - uint32_t EEI3 : 1; /*!< [3] Enable Error Interrupt 3 */ - uint32_t EEI4 : 1; /*!< [4] Enable Error Interrupt 4 */ - uint32_t EEI5 : 1; /*!< [5] Enable Error Interrupt 5 */ - uint32_t EEI6 : 1; /*!< [6] Enable Error Interrupt 6 */ - uint32_t EEI7 : 1; /*!< [7] Enable Error Interrupt 7 */ - uint32_t EEI8 : 1; /*!< [8] Enable Error Interrupt 8 */ - uint32_t EEI9 : 1; /*!< [9] Enable Error Interrupt 9 */ - uint32_t EEI10 : 1; /*!< [10] Enable Error Interrupt 10 */ - uint32_t EEI11 : 1; /*!< [11] Enable Error Interrupt 11 */ - uint32_t EEI12 : 1; /*!< [12] Enable Error Interrupt 12 */ - uint32_t EEI13 : 1; /*!< [13] Enable Error Interrupt 13 */ - uint32_t EEI14 : 1; /*!< [14] Enable Error Interrupt 14 */ - uint32_t EEI15 : 1; /*!< [15] Enable Error Interrupt 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_eei_t; - -/*! - * @name Constants and macros for entire DMA_EEI register - */ -/*@{*/ -#define HW_DMA_EEI_ADDR(x) ((x) + 0x14U) - -#define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x)) -#define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U) -#define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v)) -#define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v))) -#define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v))) -#define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_EEI bitfields - */ - -/*! - * @name Register DMA_EEI, field EEI0[0] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI0 (0U) /*!< Bit position for DMA_EEI_EEI0. */ -#define BM_DMA_EEI_EEI0 (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */ -#define BS_DMA_EEI_EEI0 (1U) /*!< Bit field size in bits for DMA_EEI_EEI0. */ - -/*! @brief Read current value of the DMA_EEI_EEI0 field. */ -#define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0)) - -/*! @brief Format value for bitfield DMA_EEI_EEI0. */ -#define BF_DMA_EEI_EEI0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0) - -/*! @brief Set the EEI0 field to a new value. */ -#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI1[1] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI1 (1U) /*!< Bit position for DMA_EEI_EEI1. */ -#define BM_DMA_EEI_EEI1 (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */ -#define BS_DMA_EEI_EEI1 (1U) /*!< Bit field size in bits for DMA_EEI_EEI1. */ - -/*! @brief Read current value of the DMA_EEI_EEI1 field. */ -#define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1)) - -/*! @brief Format value for bitfield DMA_EEI_EEI1. */ -#define BF_DMA_EEI_EEI1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1) - -/*! @brief Set the EEI1 field to a new value. */ -#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI2[2] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI2 (2U) /*!< Bit position for DMA_EEI_EEI2. */ -#define BM_DMA_EEI_EEI2 (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */ -#define BS_DMA_EEI_EEI2 (1U) /*!< Bit field size in bits for DMA_EEI_EEI2. */ - -/*! @brief Read current value of the DMA_EEI_EEI2 field. */ -#define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2)) - -/*! @brief Format value for bitfield DMA_EEI_EEI2. */ -#define BF_DMA_EEI_EEI2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2) - -/*! @brief Set the EEI2 field to a new value. */ -#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI3[3] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI3 (3U) /*!< Bit position for DMA_EEI_EEI3. */ -#define BM_DMA_EEI_EEI3 (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */ -#define BS_DMA_EEI_EEI3 (1U) /*!< Bit field size in bits for DMA_EEI_EEI3. */ - -/*! @brief Read current value of the DMA_EEI_EEI3 field. */ -#define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3)) - -/*! @brief Format value for bitfield DMA_EEI_EEI3. */ -#define BF_DMA_EEI_EEI3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3) - -/*! @brief Set the EEI3 field to a new value. */ -#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI4[4] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */ -#define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */ -#define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */ - -/*! @brief Read current value of the DMA_EEI_EEI4 field. */ -#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4)) - -/*! @brief Format value for bitfield DMA_EEI_EEI4. */ -#define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4) - -/*! @brief Set the EEI4 field to a new value. */ -#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI5[5] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */ -#define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */ -#define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */ - -/*! @brief Read current value of the DMA_EEI_EEI5 field. */ -#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5)) - -/*! @brief Format value for bitfield DMA_EEI_EEI5. */ -#define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5) - -/*! @brief Set the EEI5 field to a new value. */ -#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI6[6] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */ -#define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */ -#define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */ - -/*! @brief Read current value of the DMA_EEI_EEI6 field. */ -#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6)) - -/*! @brief Format value for bitfield DMA_EEI_EEI6. */ -#define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6) - -/*! @brief Set the EEI6 field to a new value. */ -#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI7[7] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */ -#define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */ -#define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */ - -/*! @brief Read current value of the DMA_EEI_EEI7 field. */ -#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7)) - -/*! @brief Format value for bitfield DMA_EEI_EEI7. */ -#define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7) - -/*! @brief Set the EEI7 field to a new value. */ -#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI8[8] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */ -#define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */ -#define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */ - -/*! @brief Read current value of the DMA_EEI_EEI8 field. */ -#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8)) - -/*! @brief Format value for bitfield DMA_EEI_EEI8. */ -#define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8) - -/*! @brief Set the EEI8 field to a new value. */ -#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI9[9] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */ -#define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */ -#define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */ - -/*! @brief Read current value of the DMA_EEI_EEI9 field. */ -#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9)) - -/*! @brief Format value for bitfield DMA_EEI_EEI9. */ -#define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9) - -/*! @brief Set the EEI9 field to a new value. */ -#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI10[10] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */ -#define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */ -#define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */ - -/*! @brief Read current value of the DMA_EEI_EEI10 field. */ -#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10)) - -/*! @brief Format value for bitfield DMA_EEI_EEI10. */ -#define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10) - -/*! @brief Set the EEI10 field to a new value. */ -#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI11[11] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */ -#define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */ -#define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */ - -/*! @brief Read current value of the DMA_EEI_EEI11 field. */ -#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11)) - -/*! @brief Format value for bitfield DMA_EEI_EEI11. */ -#define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11) - -/*! @brief Set the EEI11 field to a new value. */ -#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI12[12] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */ -#define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */ -#define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */ - -/*! @brief Read current value of the DMA_EEI_EEI12 field. */ -#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12)) - -/*! @brief Format value for bitfield DMA_EEI_EEI12. */ -#define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12) - -/*! @brief Set the EEI12 field to a new value. */ -#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI13[13] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */ -#define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */ -#define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */ - -/*! @brief Read current value of the DMA_EEI_EEI13 field. */ -#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13)) - -/*! @brief Format value for bitfield DMA_EEI_EEI13. */ -#define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13) - -/*! @brief Set the EEI13 field to a new value. */ -#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI14[14] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */ -#define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */ -#define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */ - -/*! @brief Read current value of the DMA_EEI_EEI14 field. */ -#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14)) - -/*! @brief Format value for bitfield DMA_EEI_EEI14. */ -#define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14) - -/*! @brief Set the EEI14 field to a new value. */ -#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_EEI, field EEI15[15] (RW) - * - * Values: - * - 0 - The error signal for corresponding channel does not generate an error - * interrupt - * - 1 - The assertion of the error signal for corresponding channel generates - * an error interrupt request - */ -/*@{*/ -#define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */ -#define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */ -#define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */ - -/*! @brief Read current value of the DMA_EEI_EEI15 field. */ -#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15)) - -/*! @brief Format value for bitfield DMA_EEI_EEI15. */ -#define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15) - -/*! @brief Set the EEI15 field to a new value. */ -#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CEEI - Clear Enable Error Interrupt Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO) - * - * Reset value: 0x00U - * - * The CEEI provides a simple memory-mapped mechanism to clear a given bit in - * the EEI to disable the error interrupt for a given channel. The data value on a - * register write causes the corresponding bit in the EEI to be cleared. Setting - * the CAEE bit provides a global clear function, forcing the EEI contents to be - * cleared, disabling all DMA request inputs. If the NOP bit is set, the command - * is ignored. This allows you to write multiple-byte registers as a 32-bit word. - * Reads of this register return all zeroes. - */ -typedef union _hw_dma_ceei -{ - uint8_t U; - struct _hw_dma_ceei_bitfields - { - uint8_t CEEI : 4; /*!< [3:0] Clear Enable Error Interrupt */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAEE : 1; /*!< [6] Clear All Enable Error Interrupts */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_ceei_t; - -/*! - * @name Constants and macros for entire DMA_CEEI register - */ -/*@{*/ -#define HW_DMA_CEEI_ADDR(x) ((x) + 0x18U) - -#define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x)) -#define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U) -#define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CEEI bitfields - */ - -/*! - * @name Register DMA_CEEI, field CEEI[3:0] (WORZ) - * - * Clears the corresponding bit in EEI - */ -/*@{*/ -#define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */ -#define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */ -#define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */ - -/*! @brief Format value for bitfield DMA_CEEI_CEEI. */ -#define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI) - -/*! @brief Set the CEEI field to a new value. */ -#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v))) -/*@}*/ - -/*! - * @name Register DMA_CEEI, field CAEE[6] (WORZ) - * - * Values: - * - 0 - Clear only the EEI bit specified in the CEEI field - * - 1 - Clear all bits in EEI - */ -/*@{*/ -#define BP_DMA_CEEI_CAEE (6U) /*!< Bit position for DMA_CEEI_CAEE. */ -#define BM_DMA_CEEI_CAEE (0x40U) /*!< Bit mask for DMA_CEEI_CAEE. */ -#define BS_DMA_CEEI_CAEE (1U) /*!< Bit field size in bits for DMA_CEEI_CAEE. */ - -/*! @brief Format value for bitfield DMA_CEEI_CAEE. */ -#define BF_DMA_CEEI_CAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE) - -/*! @brief Set the CAEE field to a new value. */ -#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CEEI, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CEEI_NOP (7U) /*!< Bit position for DMA_CEEI_NOP. */ -#define BM_DMA_CEEI_NOP (0x80U) /*!< Bit mask for DMA_CEEI_NOP. */ -#define BS_DMA_CEEI_NOP (1U) /*!< Bit field size in bits for DMA_CEEI_NOP. */ - -/*! @brief Format value for bitfield DMA_CEEI_NOP. */ -#define BF_DMA_CEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_SEEI - Set Enable Error Interrupt Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO) - * - * Reset value: 0x00U - * - * The SEEI provides a simple memory-mapped mechanism to set a given bit in the - * EEI to enable the error interrupt for a given channel. The data value on a - * register write causes the corresponding bit in the EEI to be set. Setting the - * SAEE bit provides a global set function, forcing the entire EEI contents to be - * set. If the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all - * zeroes. - */ -typedef union _hw_dma_seei -{ - uint8_t U; - struct _hw_dma_seei_bitfields - { - uint8_t SEEI : 4; /*!< [3:0] Set Enable Error Interrupt */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t SAEE : 1; /*!< [6] Sets All Enable Error Interrupts */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_seei_t; - -/*! - * @name Constants and macros for entire DMA_SEEI register - */ -/*@{*/ -#define HW_DMA_SEEI_ADDR(x) ((x) + 0x19U) - -#define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x)) -#define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U) -#define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_SEEI bitfields - */ - -/*! - * @name Register DMA_SEEI, field SEEI[3:0] (WORZ) - * - * Sets the corresponding bit in EEI - */ -/*@{*/ -#define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */ -#define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */ -#define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */ - -/*! @brief Format value for bitfield DMA_SEEI_SEEI. */ -#define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI) - -/*! @brief Set the SEEI field to a new value. */ -#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v))) -/*@}*/ - -/*! - * @name Register DMA_SEEI, field SAEE[6] (WORZ) - * - * Values: - * - 0 - Set only the EEI bit specified in the SEEI field. - * - 1 - Sets all bits in EEI - */ -/*@{*/ -#define BP_DMA_SEEI_SAEE (6U) /*!< Bit position for DMA_SEEI_SAEE. */ -#define BM_DMA_SEEI_SAEE (0x40U) /*!< Bit mask for DMA_SEEI_SAEE. */ -#define BS_DMA_SEEI_SAEE (1U) /*!< Bit field size in bits for DMA_SEEI_SAEE. */ - -/*! @brief Format value for bitfield DMA_SEEI_SAEE. */ -#define BF_DMA_SEEI_SAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE) - -/*! @brief Set the SAEE field to a new value. */ -#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_SEEI, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_SEEI_NOP (7U) /*!< Bit position for DMA_SEEI_NOP. */ -#define BM_DMA_SEEI_NOP (0x80U) /*!< Bit mask for DMA_SEEI_NOP. */ -#define BS_DMA_SEEI_NOP (1U) /*!< Bit field size in bits for DMA_SEEI_NOP. */ - -/*! @brief Format value for bitfield DMA_SEEI_NOP. */ -#define BF_DMA_SEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CERQ - Clear Enable Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CERQ - Clear Enable Request Register (WO) - * - * Reset value: 0x00U - * - * The CERQ provides a simple memory-mapped mechanism to clear a given bit in - * the ERQ to disable the DMA request for a given channel. The data value on a - * register write causes the corresponding bit in the ERQ to be cleared. Setting the - * CAER bit provides a global clear function, forcing the entire contents of the - * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the - * command is ignored. This allows you to write multiple-byte registers as a 32-bit - * word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_cerq -{ - uint8_t U; - struct _hw_dma_cerq_bitfields - { - uint8_t CERQ : 4; /*!< [3:0] Clear Enable Request */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAER : 1; /*!< [6] Clear All Enable Requests */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cerq_t; - -/*! - * @name Constants and macros for entire DMA_CERQ register - */ -/*@{*/ -#define HW_DMA_CERQ_ADDR(x) ((x) + 0x1AU) - -#define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x)) -#define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U) -#define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CERQ bitfields - */ - -/*! - * @name Register DMA_CERQ, field CERQ[3:0] (WORZ) - * - * Clears the corresponding bit in ERQ - */ -/*@{*/ -#define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */ -#define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */ -#define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */ - -/*! @brief Format value for bitfield DMA_CERQ_CERQ. */ -#define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ) - -/*! @brief Set the CERQ field to a new value. */ -#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v))) -/*@}*/ - -/*! - * @name Register DMA_CERQ, field CAER[6] (WORZ) - * - * Values: - * - 0 - Clear only the ERQ bit specified in the CERQ field - * - 1 - Clear all bits in ERQ - */ -/*@{*/ -#define BP_DMA_CERQ_CAER (6U) /*!< Bit position for DMA_CERQ_CAER. */ -#define BM_DMA_CERQ_CAER (0x40U) /*!< Bit mask for DMA_CERQ_CAER. */ -#define BS_DMA_CERQ_CAER (1U) /*!< Bit field size in bits for DMA_CERQ_CAER. */ - -/*! @brief Format value for bitfield DMA_CERQ_CAER. */ -#define BF_DMA_CERQ_CAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER) - -/*! @brief Set the CAER field to a new value. */ -#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CERQ, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CERQ_NOP (7U) /*!< Bit position for DMA_CERQ_NOP. */ -#define BM_DMA_CERQ_NOP (0x80U) /*!< Bit mask for DMA_CERQ_NOP. */ -#define BS_DMA_CERQ_NOP (1U) /*!< Bit field size in bits for DMA_CERQ_NOP. */ - -/*! @brief Format value for bitfield DMA_CERQ_NOP. */ -#define BF_DMA_CERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_SERQ - Set Enable Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_SERQ - Set Enable Request Register (WO) - * - * Reset value: 0x00U - * - * The SERQ provides a simple memory-mapped mechanism to set a given bit in the - * ERQ to enable the DMA request for a given channel. The data value on a - * register write causes the corresponding bit in the ERQ to be set. Setting the SAER - * bit provides a global set function, forcing the entire contents of ERQ to be - * set. If the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_serq -{ - uint8_t U; - struct _hw_dma_serq_bitfields - { - uint8_t SERQ : 4; /*!< [3:0] Set enable request */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t SAER : 1; /*!< [6] Set All Enable Requests */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_serq_t; - -/*! - * @name Constants and macros for entire DMA_SERQ register - */ -/*@{*/ -#define HW_DMA_SERQ_ADDR(x) ((x) + 0x1BU) - -#define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x)) -#define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U) -#define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_SERQ bitfields - */ - -/*! - * @name Register DMA_SERQ, field SERQ[3:0] (WORZ) - * - * Sets the corresponding bit in ERQ - */ -/*@{*/ -#define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */ -#define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */ -#define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */ - -/*! @brief Format value for bitfield DMA_SERQ_SERQ. */ -#define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ) - -/*! @brief Set the SERQ field to a new value. */ -#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v))) -/*@}*/ - -/*! - * @name Register DMA_SERQ, field SAER[6] (WORZ) - * - * Values: - * - 0 - Set only the ERQ bit specified in the SERQ field - * - 1 - Set all bits in ERQ - */ -/*@{*/ -#define BP_DMA_SERQ_SAER (6U) /*!< Bit position for DMA_SERQ_SAER. */ -#define BM_DMA_SERQ_SAER (0x40U) /*!< Bit mask for DMA_SERQ_SAER. */ -#define BS_DMA_SERQ_SAER (1U) /*!< Bit field size in bits for DMA_SERQ_SAER. */ - -/*! @brief Format value for bitfield DMA_SERQ_SAER. */ -#define BF_DMA_SERQ_SAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER) - -/*! @brief Set the SAER field to a new value. */ -#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v)) -/*@}*/ - -/*! - * @name Register DMA_SERQ, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_SERQ_NOP (7U) /*!< Bit position for DMA_SERQ_NOP. */ -#define BM_DMA_SERQ_NOP (0x80U) /*!< Bit mask for DMA_SERQ_NOP. */ -#define BS_DMA_SERQ_NOP (1U) /*!< Bit field size in bits for DMA_SERQ_NOP. */ - -/*! @brief Format value for bitfield DMA_SERQ_NOP. */ -#define BF_DMA_SERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CDNE - Clear DONE Status Bit Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO) - * - * Reset value: 0x00U - * - * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in - * the TCD of the given channel. The data value on a register write causes the - * DONE bit in the corresponding transfer control descriptor to be cleared. Setting - * the CADN bit provides a global clear function, forcing all DONE bits to be - * cleared. If the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all - * zeroes. - */ -typedef union _hw_dma_cdne -{ - uint8_t U; - struct _hw_dma_cdne_bitfields - { - uint8_t CDNE : 4; /*!< [3:0] Clear DONE Bit */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CADN : 1; /*!< [6] Clears All DONE Bits */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cdne_t; - -/*! - * @name Constants and macros for entire DMA_CDNE register - */ -/*@{*/ -#define HW_DMA_CDNE_ADDR(x) ((x) + 0x1CU) - -#define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x)) -#define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U) -#define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CDNE bitfields - */ - -/*! - * @name Register DMA_CDNE, field CDNE[3:0] (WORZ) - * - * Clears the corresponding bit in TCDn_CSR[DONE] - */ -/*@{*/ -#define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */ -#define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */ -#define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */ - -/*! @brief Format value for bitfield DMA_CDNE_CDNE. */ -#define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE) - -/*! @brief Set the CDNE field to a new value. */ -#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v))) -/*@}*/ - -/*! - * @name Register DMA_CDNE, field CADN[6] (WORZ) - * - * Values: - * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field - * - 1 - Clears all bits in TCDn_CSR[DONE] - */ -/*@{*/ -#define BP_DMA_CDNE_CADN (6U) /*!< Bit position for DMA_CDNE_CADN. */ -#define BM_DMA_CDNE_CADN (0x40U) /*!< Bit mask for DMA_CDNE_CADN. */ -#define BS_DMA_CDNE_CADN (1U) /*!< Bit field size in bits for DMA_CDNE_CADN. */ - -/*! @brief Format value for bitfield DMA_CDNE_CADN. */ -#define BF_DMA_CDNE_CADN(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN) - -/*! @brief Set the CADN field to a new value. */ -#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CDNE, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CDNE_NOP (7U) /*!< Bit position for DMA_CDNE_NOP. */ -#define BM_DMA_CDNE_NOP (0x80U) /*!< Bit mask for DMA_CDNE_NOP. */ -#define BS_DMA_CDNE_NOP (1U) /*!< Bit field size in bits for DMA_CDNE_NOP. */ - -/*! @brief Format value for bitfield DMA_CDNE_NOP. */ -#define BF_DMA_CDNE_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_SSRT - Set START Bit Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_SSRT - Set START Bit Register (WO) - * - * Reset value: 0x00U - * - * The SSRT provides a simple memory-mapped mechanism to set the START bit in - * the TCD of the given channel. The data value on a register write causes the - * START bit in the corresponding transfer control descriptor to be set. Setting the - * SAST bit provides a global set function, forcing all START bits to be set. If - * the NOP bit is set, the command is ignored. This allows you to write - * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_ssrt -{ - uint8_t U; - struct _hw_dma_ssrt_bitfields - { - uint8_t SSRT : 4; /*!< [3:0] Set START Bit */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t SAST : 1; /*!< [6] Set All START Bits (activates all - * channels) */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_ssrt_t; - -/*! - * @name Constants and macros for entire DMA_SSRT register - */ -/*@{*/ -#define HW_DMA_SSRT_ADDR(x) ((x) + 0x1DU) - -#define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x)) -#define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U) -#define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_SSRT bitfields - */ - -/*! - * @name Register DMA_SSRT, field SSRT[3:0] (WORZ) - * - * Sets the corresponding bit in TCDn_CSR[START] - */ -/*@{*/ -#define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */ -#define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */ -#define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */ - -/*! @brief Format value for bitfield DMA_SSRT_SSRT. */ -#define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT) - -/*! @brief Set the SSRT field to a new value. */ -#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v))) -/*@}*/ - -/*! - * @name Register DMA_SSRT, field SAST[6] (WORZ) - * - * Values: - * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field - * - 1 - Set all bits in TCDn_CSR[START] - */ -/*@{*/ -#define BP_DMA_SSRT_SAST (6U) /*!< Bit position for DMA_SSRT_SAST. */ -#define BM_DMA_SSRT_SAST (0x40U) /*!< Bit mask for DMA_SSRT_SAST. */ -#define BS_DMA_SSRT_SAST (1U) /*!< Bit field size in bits for DMA_SSRT_SAST. */ - -/*! @brief Format value for bitfield DMA_SSRT_SAST. */ -#define BF_DMA_SSRT_SAST(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST) - -/*! @brief Set the SAST field to a new value. */ -#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v)) -/*@}*/ - -/*! - * @name Register DMA_SSRT, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_SSRT_NOP (7U) /*!< Bit position for DMA_SSRT_NOP. */ -#define BM_DMA_SSRT_NOP (0x80U) /*!< Bit mask for DMA_SSRT_NOP. */ -#define BS_DMA_SSRT_NOP (1U) /*!< Bit field size in bits for DMA_SSRT_NOP. */ - -/*! @brief Format value for bitfield DMA_SSRT_NOP. */ -#define BF_DMA_SSRT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CERR - Clear Error Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CERR - Clear Error Register (WO) - * - * Reset value: 0x00U - * - * The CERR provides a simple memory-mapped mechanism to clear a given bit in - * the ERR to disable the error condition flag for a given channel. The given value - * on a register write causes the corresponding bit in the ERR to be cleared. - * Setting the CAEI bit provides a global clear function, forcing the ERR contents - * to be cleared, clearing all channel error indicators. If the NOP bit is set, - * the command is ignored. This allows you to write multiple-byte registers as a - * 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_cerr -{ - uint8_t U; - struct _hw_dma_cerr_bitfields - { - uint8_t CERR : 4; /*!< [3:0] Clear Error Indicator */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAEI : 1; /*!< [6] Clear All Error Indicators */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cerr_t; - -/*! - * @name Constants and macros for entire DMA_CERR register - */ -/*@{*/ -#define HW_DMA_CERR_ADDR(x) ((x) + 0x1EU) - -#define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x)) -#define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U) -#define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CERR bitfields - */ - -/*! - * @name Register DMA_CERR, field CERR[3:0] (WORZ) - * - * Clears the corresponding bit in ERR - */ -/*@{*/ -#define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */ -#define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */ -#define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */ - -/*! @brief Format value for bitfield DMA_CERR_CERR. */ -#define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR) - -/*! @brief Set the CERR field to a new value. */ -#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v))) -/*@}*/ - -/*! - * @name Register DMA_CERR, field CAEI[6] (WORZ) - * - * Values: - * - 0 - Clear only the ERR bit specified in the CERR field - * - 1 - Clear all bits in ERR - */ -/*@{*/ -#define BP_DMA_CERR_CAEI (6U) /*!< Bit position for DMA_CERR_CAEI. */ -#define BM_DMA_CERR_CAEI (0x40U) /*!< Bit mask for DMA_CERR_CAEI. */ -#define BS_DMA_CERR_CAEI (1U) /*!< Bit field size in bits for DMA_CERR_CAEI. */ - -/*! @brief Format value for bitfield DMA_CERR_CAEI. */ -#define BF_DMA_CERR_CAEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI) - -/*! @brief Set the CAEI field to a new value. */ -#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CERR, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CERR_NOP (7U) /*!< Bit position for DMA_CERR_NOP. */ -#define BM_DMA_CERR_NOP (0x80U) /*!< Bit mask for DMA_CERR_NOP. */ -#define BS_DMA_CERR_NOP (1U) /*!< Bit field size in bits for DMA_CERR_NOP. */ - -/*! @brief Format value for bitfield DMA_CERR_NOP. */ -#define BF_DMA_CERR_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_CINT - Clear Interrupt Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO) - * - * Reset value: 0x00U - * - * The CINT provides a simple, memory-mapped mechanism to clear a given bit in - * the INT to disable the interrupt request for a given channel. The given value - * on a register write causes the corresponding bit in the INT to be cleared. - * Setting the CAIR bit provides a global clear function, forcing the entire contents - * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP - * bit is set, the command is ignored. This allows you to write multiple-byte - * registers as a 32-bit word. Reads of this register return all zeroes. - */ -typedef union _hw_dma_cint -{ - uint8_t U; - struct _hw_dma_cint_bitfields - { - uint8_t CINT : 4; /*!< [3:0] Clear Interrupt Request */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t CAIR : 1; /*!< [6] Clear All Interrupt Requests */ - uint8_t NOP : 1; /*!< [7] No Op enable */ - } B; -} hw_dma_cint_t; - -/*! - * @name Constants and macros for entire DMA_CINT register - */ -/*@{*/ -#define HW_DMA_CINT_ADDR(x) ((x) + 0x1FU) - -#define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x)) -#define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U) -#define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual DMA_CINT bitfields - */ - -/*! - * @name Register DMA_CINT, field CINT[3:0] (WORZ) - * - * Clears the corresponding bit in INT - */ -/*@{*/ -#define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */ -#define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */ -#define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */ - -/*! @brief Format value for bitfield DMA_CINT_CINT. */ -#define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT) - -/*! @brief Set the CINT field to a new value. */ -#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v))) -/*@}*/ - -/*! - * @name Register DMA_CINT, field CAIR[6] (WORZ) - * - * Values: - * - 0 - Clear only the INT bit specified in the CINT field - * - 1 - Clear all bits in INT - */ -/*@{*/ -#define BP_DMA_CINT_CAIR (6U) /*!< Bit position for DMA_CINT_CAIR. */ -#define BM_DMA_CINT_CAIR (0x40U) /*!< Bit mask for DMA_CINT_CAIR. */ -#define BS_DMA_CINT_CAIR (1U) /*!< Bit field size in bits for DMA_CINT_CAIR. */ - -/*! @brief Format value for bitfield DMA_CINT_CAIR. */ -#define BF_DMA_CINT_CAIR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR) - -/*! @brief Set the CAIR field to a new value. */ -#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v)) -/*@}*/ - -/*! - * @name Register DMA_CINT, field NOP[7] (WORZ) - * - * Values: - * - 0 - Normal operation - * - 1 - No operation, ignore the other bits in this register - */ -/*@{*/ -#define BP_DMA_CINT_NOP (7U) /*!< Bit position for DMA_CINT_NOP. */ -#define BM_DMA_CINT_NOP (0x80U) /*!< Bit mask for DMA_CINT_NOP. */ -#define BS_DMA_CINT_NOP (1U) /*!< Bit field size in bits for DMA_CINT_NOP. */ - -/*! @brief Format value for bitfield DMA_CINT_NOP. */ -#define BF_DMA_CINT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP) - -/*! @brief Set the NOP field to a new value. */ -#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_INT - Interrupt Request Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_INT - Interrupt Request Register (RW) - * - * Reset value: 0x00000000U - * - * The INT register provides a bit map for the 16 channels signaling the - * presence of an interrupt request for each channel. Depending on the appropriate bit - * setting in the transfer-control descriptors, the eDMA engine generates an - * interrupt on data transfer completion. The outputs of this register are directly - * routed to the interrupt controller (INTC). During the interrupt-service routine - * associated with any given channel, it is the software's responsibility to - * clear the appropriate bit, negating the interrupt request. Typically, a write to - * the CINT register in the interrupt service routine is used for this purpose. - * The state of any given channel's interrupt request is directly affected by - * writes to this register; it is also affected by writes to the CINT register. On - * writes to INT, a 1 in any bit position clears the corresponding channel's - * interrupt request. A zero in any bit position has no affect on the corresponding - * channel's current interrupt status. The CINT register is provided so the interrupt - * request for a single channel can easily be cleared without the need to - * perform a read-modify-write sequence to the INT register. - */ -typedef union _hw_dma_int -{ - uint32_t U; - struct _hw_dma_int_bitfields - { - uint32_t INT0 : 1; /*!< [0] Interrupt Request 0 */ - uint32_t INT1 : 1; /*!< [1] Interrupt Request 1 */ - uint32_t INT2 : 1; /*!< [2] Interrupt Request 2 */ - uint32_t INT3 : 1; /*!< [3] Interrupt Request 3 */ - uint32_t INT4 : 1; /*!< [4] Interrupt Request 4 */ - uint32_t INT5 : 1; /*!< [5] Interrupt Request 5 */ - uint32_t INT6 : 1; /*!< [6] Interrupt Request 6 */ - uint32_t INT7 : 1; /*!< [7] Interrupt Request 7 */ - uint32_t INT8 : 1; /*!< [8] Interrupt Request 8 */ - uint32_t INT9 : 1; /*!< [9] Interrupt Request 9 */ - uint32_t INT10 : 1; /*!< [10] Interrupt Request 10 */ - uint32_t INT11 : 1; /*!< [11] Interrupt Request 11 */ - uint32_t INT12 : 1; /*!< [12] Interrupt Request 12 */ - uint32_t INT13 : 1; /*!< [13] Interrupt Request 13 */ - uint32_t INT14 : 1; /*!< [14] Interrupt Request 14 */ - uint32_t INT15 : 1; /*!< [15] Interrupt Request 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_int_t; - -/*! - * @name Constants and macros for entire DMA_INT register - */ -/*@{*/ -#define HW_DMA_INT_ADDR(x) ((x) + 0x24U) - -#define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x)) -#define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U) -#define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v)) -#define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v))) -#define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v))) -#define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_INT bitfields - */ - -/*! - * @name Register DMA_INT, field INT0[0] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT0 (0U) /*!< Bit position for DMA_INT_INT0. */ -#define BM_DMA_INT_INT0 (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */ -#define BS_DMA_INT_INT0 (1U) /*!< Bit field size in bits for DMA_INT_INT0. */ - -/*! @brief Read current value of the DMA_INT_INT0 field. */ -#define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0)) - -/*! @brief Format value for bitfield DMA_INT_INT0. */ -#define BF_DMA_INT_INT0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0) - -/*! @brief Set the INT0 field to a new value. */ -#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT1[1] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT1 (1U) /*!< Bit position for DMA_INT_INT1. */ -#define BM_DMA_INT_INT1 (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */ -#define BS_DMA_INT_INT1 (1U) /*!< Bit field size in bits for DMA_INT_INT1. */ - -/*! @brief Read current value of the DMA_INT_INT1 field. */ -#define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1)) - -/*! @brief Format value for bitfield DMA_INT_INT1. */ -#define BF_DMA_INT_INT1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1) - -/*! @brief Set the INT1 field to a new value. */ -#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT2[2] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT2 (2U) /*!< Bit position for DMA_INT_INT2. */ -#define BM_DMA_INT_INT2 (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */ -#define BS_DMA_INT_INT2 (1U) /*!< Bit field size in bits for DMA_INT_INT2. */ - -/*! @brief Read current value of the DMA_INT_INT2 field. */ -#define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2)) - -/*! @brief Format value for bitfield DMA_INT_INT2. */ -#define BF_DMA_INT_INT2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2) - -/*! @brief Set the INT2 field to a new value. */ -#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT3[3] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT3 (3U) /*!< Bit position for DMA_INT_INT3. */ -#define BM_DMA_INT_INT3 (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */ -#define BS_DMA_INT_INT3 (1U) /*!< Bit field size in bits for DMA_INT_INT3. */ - -/*! @brief Read current value of the DMA_INT_INT3 field. */ -#define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3)) - -/*! @brief Format value for bitfield DMA_INT_INT3. */ -#define BF_DMA_INT_INT3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3) - -/*! @brief Set the INT3 field to a new value. */ -#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT4[4] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */ -#define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */ -#define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */ - -/*! @brief Read current value of the DMA_INT_INT4 field. */ -#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4)) - -/*! @brief Format value for bitfield DMA_INT_INT4. */ -#define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4) - -/*! @brief Set the INT4 field to a new value. */ -#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT5[5] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */ -#define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */ -#define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */ - -/*! @brief Read current value of the DMA_INT_INT5 field. */ -#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5)) - -/*! @brief Format value for bitfield DMA_INT_INT5. */ -#define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5) - -/*! @brief Set the INT5 field to a new value. */ -#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT6[6] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */ -#define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */ -#define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */ - -/*! @brief Read current value of the DMA_INT_INT6 field. */ -#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6)) - -/*! @brief Format value for bitfield DMA_INT_INT6. */ -#define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6) - -/*! @brief Set the INT6 field to a new value. */ -#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT7[7] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */ -#define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */ -#define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */ - -/*! @brief Read current value of the DMA_INT_INT7 field. */ -#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7)) - -/*! @brief Format value for bitfield DMA_INT_INT7. */ -#define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7) - -/*! @brief Set the INT7 field to a new value. */ -#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT8[8] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */ -#define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */ -#define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */ - -/*! @brief Read current value of the DMA_INT_INT8 field. */ -#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8)) - -/*! @brief Format value for bitfield DMA_INT_INT8. */ -#define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8) - -/*! @brief Set the INT8 field to a new value. */ -#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT9[9] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */ -#define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */ -#define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */ - -/*! @brief Read current value of the DMA_INT_INT9 field. */ -#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9)) - -/*! @brief Format value for bitfield DMA_INT_INT9. */ -#define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9) - -/*! @brief Set the INT9 field to a new value. */ -#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT10[10] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */ -#define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */ -#define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */ - -/*! @brief Read current value of the DMA_INT_INT10 field. */ -#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10)) - -/*! @brief Format value for bitfield DMA_INT_INT10. */ -#define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10) - -/*! @brief Set the INT10 field to a new value. */ -#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT11[11] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */ -#define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */ -#define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */ - -/*! @brief Read current value of the DMA_INT_INT11 field. */ -#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11)) - -/*! @brief Format value for bitfield DMA_INT_INT11. */ -#define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11) - -/*! @brief Set the INT11 field to a new value. */ -#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT12[12] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */ -#define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */ -#define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */ - -/*! @brief Read current value of the DMA_INT_INT12 field. */ -#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12)) - -/*! @brief Format value for bitfield DMA_INT_INT12. */ -#define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12) - -/*! @brief Set the INT12 field to a new value. */ -#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT13[13] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */ -#define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */ -#define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */ - -/*! @brief Read current value of the DMA_INT_INT13 field. */ -#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13)) - -/*! @brief Format value for bitfield DMA_INT_INT13. */ -#define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13) - -/*! @brief Set the INT13 field to a new value. */ -#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT14[14] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */ -#define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */ -#define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */ - -/*! @brief Read current value of the DMA_INT_INT14 field. */ -#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14)) - -/*! @brief Format value for bitfield DMA_INT_INT14. */ -#define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14) - -/*! @brief Set the INT14 field to a new value. */ -#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_INT, field INT15[15] (W1C) - * - * Values: - * - 0 - The interrupt request for corresponding channel is cleared - * - 1 - The interrupt request for corresponding channel is active - */ -/*@{*/ -#define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */ -#define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */ -#define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */ - -/*! @brief Read current value of the DMA_INT_INT15 field. */ -#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15)) - -/*! @brief Format value for bitfield DMA_INT_INT15. */ -#define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15) - -/*! @brief Set the INT15 field to a new value. */ -#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_ERR - Error Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_ERR - Error Register (RW) - * - * Reset value: 0x00000000U - * - * The ERR provides a bit map for the 16 channels, signaling the presence of an - * error for each channel. The eDMA engine signals the occurrence of an error - * condition by setting the appropriate bit in this register. The outputs of this - * register are enabled by the contents of the EEI, and then routed to the - * interrupt controller. During the execution of the interrupt-service routine associated - * with any DMA errors, it is software's responsibility to clear the appropriate - * bit, negating the error-interrupt request. Typically, a write to the CERR in - * the interrupt-service routine is used for this purpose. The normal DMA channel - * completion indicators (setting the transfer control descriptor DONE flag and - * the possible assertion of an interrupt request) are not affected when an error - * is detected. The contents of this register can also be polled because a - * non-zero value indicates the presence of a channel error regardless of the state of - * the EEI. The state of any given channel's error indicators is affected by - * writes to this register; it is also affected by writes to the CERR. On writes to - * the ERR, a one in any bit position clears the corresponding channel's error - * status. A zero in any bit position has no affect on the corresponding channel's - * current error status. The CERR is provided so the error indicator for a single - * channel can easily be cleared. - */ -typedef union _hw_dma_err -{ - uint32_t U; - struct _hw_dma_err_bitfields - { - uint32_t ERR0 : 1; /*!< [0] Error In Channel 0 */ - uint32_t ERR1 : 1; /*!< [1] Error In Channel 1 */ - uint32_t ERR2 : 1; /*!< [2] Error In Channel 2 */ - uint32_t ERR3 : 1; /*!< [3] Error In Channel 3 */ - uint32_t ERR4 : 1; /*!< [4] Error In Channel 4 */ - uint32_t ERR5 : 1; /*!< [5] Error In Channel 5 */ - uint32_t ERR6 : 1; /*!< [6] Error In Channel 6 */ - uint32_t ERR7 : 1; /*!< [7] Error In Channel 7 */ - uint32_t ERR8 : 1; /*!< [8] Error In Channel 8 */ - uint32_t ERR9 : 1; /*!< [9] Error In Channel 9 */ - uint32_t ERR10 : 1; /*!< [10] Error In Channel 10 */ - uint32_t ERR11 : 1; /*!< [11] Error In Channel 11 */ - uint32_t ERR12 : 1; /*!< [12] Error In Channel 12 */ - uint32_t ERR13 : 1; /*!< [13] Error In Channel 13 */ - uint32_t ERR14 : 1; /*!< [14] Error In Channel 14 */ - uint32_t ERR15 : 1; /*!< [15] Error In Channel 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_dma_err_t; - -/*! - * @name Constants and macros for entire DMA_ERR register - */ -/*@{*/ -#define HW_DMA_ERR_ADDR(x) ((x) + 0x2CU) - -#define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x)) -#define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U) -#define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v)) -#define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v))) -#define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v))) -#define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_ERR bitfields - */ - -/*! - * @name Register DMA_ERR, field ERR0[0] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR0 (0U) /*!< Bit position for DMA_ERR_ERR0. */ -#define BM_DMA_ERR_ERR0 (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */ -#define BS_DMA_ERR_ERR0 (1U) /*!< Bit field size in bits for DMA_ERR_ERR0. */ - -/*! @brief Read current value of the DMA_ERR_ERR0 field. */ -#define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0)) - -/*! @brief Format value for bitfield DMA_ERR_ERR0. */ -#define BF_DMA_ERR_ERR0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0) - -/*! @brief Set the ERR0 field to a new value. */ -#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR1[1] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR1 (1U) /*!< Bit position for DMA_ERR_ERR1. */ -#define BM_DMA_ERR_ERR1 (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */ -#define BS_DMA_ERR_ERR1 (1U) /*!< Bit field size in bits for DMA_ERR_ERR1. */ - -/*! @brief Read current value of the DMA_ERR_ERR1 field. */ -#define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1)) - -/*! @brief Format value for bitfield DMA_ERR_ERR1. */ -#define BF_DMA_ERR_ERR1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1) - -/*! @brief Set the ERR1 field to a new value. */ -#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR2[2] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR2 (2U) /*!< Bit position for DMA_ERR_ERR2. */ -#define BM_DMA_ERR_ERR2 (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */ -#define BS_DMA_ERR_ERR2 (1U) /*!< Bit field size in bits for DMA_ERR_ERR2. */ - -/*! @brief Read current value of the DMA_ERR_ERR2 field. */ -#define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2)) - -/*! @brief Format value for bitfield DMA_ERR_ERR2. */ -#define BF_DMA_ERR_ERR2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2) - -/*! @brief Set the ERR2 field to a new value. */ -#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR3[3] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR3 (3U) /*!< Bit position for DMA_ERR_ERR3. */ -#define BM_DMA_ERR_ERR3 (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */ -#define BS_DMA_ERR_ERR3 (1U) /*!< Bit field size in bits for DMA_ERR_ERR3. */ - -/*! @brief Read current value of the DMA_ERR_ERR3 field. */ -#define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3)) - -/*! @brief Format value for bitfield DMA_ERR_ERR3. */ -#define BF_DMA_ERR_ERR3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3) - -/*! @brief Set the ERR3 field to a new value. */ -#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR4[4] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */ -#define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */ -#define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */ - -/*! @brief Read current value of the DMA_ERR_ERR4 field. */ -#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4)) - -/*! @brief Format value for bitfield DMA_ERR_ERR4. */ -#define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4) - -/*! @brief Set the ERR4 field to a new value. */ -#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR5[5] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */ -#define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */ -#define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */ - -/*! @brief Read current value of the DMA_ERR_ERR5 field. */ -#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5)) - -/*! @brief Format value for bitfield DMA_ERR_ERR5. */ -#define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5) - -/*! @brief Set the ERR5 field to a new value. */ -#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR6[6] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */ -#define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */ -#define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */ - -/*! @brief Read current value of the DMA_ERR_ERR6 field. */ -#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6)) - -/*! @brief Format value for bitfield DMA_ERR_ERR6. */ -#define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6) - -/*! @brief Set the ERR6 field to a new value. */ -#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR7[7] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */ -#define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */ -#define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */ - -/*! @brief Read current value of the DMA_ERR_ERR7 field. */ -#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7)) - -/*! @brief Format value for bitfield DMA_ERR_ERR7. */ -#define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7) - -/*! @brief Set the ERR7 field to a new value. */ -#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR8[8] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */ -#define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */ -#define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */ - -/*! @brief Read current value of the DMA_ERR_ERR8 field. */ -#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8)) - -/*! @brief Format value for bitfield DMA_ERR_ERR8. */ -#define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8) - -/*! @brief Set the ERR8 field to a new value. */ -#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR9[9] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */ -#define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */ -#define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */ - -/*! @brief Read current value of the DMA_ERR_ERR9 field. */ -#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9)) - -/*! @brief Format value for bitfield DMA_ERR_ERR9. */ -#define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9) - -/*! @brief Set the ERR9 field to a new value. */ -#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR10[10] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */ -#define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */ -#define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */ - -/*! @brief Read current value of the DMA_ERR_ERR10 field. */ -#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10)) - -/*! @brief Format value for bitfield DMA_ERR_ERR10. */ -#define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10) - -/*! @brief Set the ERR10 field to a new value. */ -#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR11[11] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */ -#define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */ -#define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */ - -/*! @brief Read current value of the DMA_ERR_ERR11 field. */ -#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11)) - -/*! @brief Format value for bitfield DMA_ERR_ERR11. */ -#define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11) - -/*! @brief Set the ERR11 field to a new value. */ -#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR12[12] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */ -#define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */ -#define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */ - -/*! @brief Read current value of the DMA_ERR_ERR12 field. */ -#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12)) - -/*! @brief Format value for bitfield DMA_ERR_ERR12. */ -#define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12) - -/*! @brief Set the ERR12 field to a new value. */ -#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR13[13] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */ -#define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */ -#define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */ - -/*! @brief Read current value of the DMA_ERR_ERR13 field. */ -#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13)) - -/*! @brief Format value for bitfield DMA_ERR_ERR13. */ -#define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13) - -/*! @brief Set the ERR13 field to a new value. */ -#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR14[14] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */ -#define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */ -#define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */ - -/*! @brief Read current value of the DMA_ERR_ERR14 field. */ -#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14)) - -/*! @brief Format value for bitfield DMA_ERR_ERR14. */ -#define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14) - -/*! @brief Set the ERR14 field to a new value. */ -#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v)) -/*@}*/ - -/*! - * @name Register DMA_ERR, field ERR15[15] (W1C) - * - * Values: - * - 0 - An error in the corresponding channel has not occurred - * - 1 - An error in the corresponding channel has occurred - */ -/*@{*/ -#define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */ -#define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */ -#define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */ - -/*! @brief Read current value of the DMA_ERR_ERR15 field. */ -#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15)) - -/*! @brief Format value for bitfield DMA_ERR_ERR15. */ -#define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15) - -/*! @brief Set the ERR15 field to a new value. */ -#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_HRS - Hardware Request Status Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_HRS - Hardware Request Status Register (RO) - * - * Reset value: 0x00000000U - * - * The HRS register provides a bit map for the DMA channels, signaling the - * presence of a hardware request for each channel. The hardware request status bits - * reflect the current state of the register and qualified (via the ERQ fields) - * DMA request signals as seen by the DMA's arbitration logic. This view into the - * hardware request signals may be used for debug purposes. These bits reflect the - * state of the request as seen by the arbitration logic. Therefore, this status - * is affected by the ERQ bits. - */ -typedef union _hw_dma_hrs -{ - uint32_t U; - struct _hw_dma_hrs_bitfields - { - uint32_t HRS0 : 1; /*!< [0] Hardware Request Status Channel 0 */ - uint32_t HRS1 : 1; /*!< [1] Hardware Request Status Channel 1 */ - uint32_t HRS2 : 1; /*!< [2] Hardware Request Status Channel 2 */ - uint32_t HRS3 : 1; /*!< [3] Hardware Request Status Channel 3 */ - uint32_t HRS4 : 1; /*!< [4] Hardware Request Status Channel 4 */ - uint32_t HRS5 : 1; /*!< [5] Hardware Request Status Channel 5 */ - uint32_t HRS6 : 1; /*!< [6] Hardware Request Status Channel 6 */ - uint32_t HRS7 : 1; /*!< [7] Hardware Request Status Channel 7 */ - uint32_t HRS8 : 1; /*!< [8] Hardware Request Status Channel 8 */ - uint32_t HRS9 : 1; /*!< [9] Hardware Request Status Channel 9 */ - uint32_t HRS10 : 1; /*!< [10] Hardware Request Status Channel 10 */ - uint32_t HRS11 : 1; /*!< [11] Hardware Request Status Channel 11 */ - uint32_t HRS12 : 1; /*!< [12] Hardware Request Status Channel 12 */ - uint32_t HRS13 : 1; /*!< [13] Hardware Request Status Channel 13 */ - uint32_t HRS14 : 1; /*!< [14] Hardware Request Status Channel 14 */ - uint32_t HRS15 : 1; /*!< [15] Hardware Request Status Channel 15 */ - uint32_t RESERVED0 : 16; /*!< [31:16] Reserved */ - } B; -} hw_dma_hrs_t; - -/*! - * @name Constants and macros for entire DMA_HRS register - */ -/*@{*/ -#define HW_DMA_HRS_ADDR(x) ((x) + 0x34U) - -#define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x)) -#define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U) -/*@}*/ - -/* - * Constants & macros for individual DMA_HRS bitfields - */ - -/*! - * @name Register DMA_HRS, field HRS0[0] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 0 is not present - * - 1 - A hardware service request for channel 0 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS0 (0U) /*!< Bit position for DMA_HRS_HRS0. */ -#define BM_DMA_HRS_HRS0 (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */ -#define BS_DMA_HRS_HRS0 (1U) /*!< Bit field size in bits for DMA_HRS_HRS0. */ - -/*! @brief Read current value of the DMA_HRS_HRS0 field. */ -#define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS1[1] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 1 is not present - * - 1 - A hardware service request for channel 1 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS1 (1U) /*!< Bit position for DMA_HRS_HRS1. */ -#define BM_DMA_HRS_HRS1 (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */ -#define BS_DMA_HRS_HRS1 (1U) /*!< Bit field size in bits for DMA_HRS_HRS1. */ - -/*! @brief Read current value of the DMA_HRS_HRS1 field. */ -#define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS2[2] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 2 is not present - * - 1 - A hardware service request for channel 2 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS2 (2U) /*!< Bit position for DMA_HRS_HRS2. */ -#define BM_DMA_HRS_HRS2 (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */ -#define BS_DMA_HRS_HRS2 (1U) /*!< Bit field size in bits for DMA_HRS_HRS2. */ - -/*! @brief Read current value of the DMA_HRS_HRS2 field. */ -#define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS3[3] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 3 is not present - * - 1 - A hardware service request for channel 3 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS3 (3U) /*!< Bit position for DMA_HRS_HRS3. */ -#define BM_DMA_HRS_HRS3 (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */ -#define BS_DMA_HRS_HRS3 (1U) /*!< Bit field size in bits for DMA_HRS_HRS3. */ - -/*! @brief Read current value of the DMA_HRS_HRS3 field. */ -#define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS4[4] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 4 is not present - * - 1 - A hardware service request for channel 4 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */ -#define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */ -#define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */ - -/*! @brief Read current value of the DMA_HRS_HRS4 field. */ -#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS5[5] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 5 is not present - * - 1 - A hardware service request for channel 5 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */ -#define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */ -#define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */ - -/*! @brief Read current value of the DMA_HRS_HRS5 field. */ -#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS6[6] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 6 is not present - * - 1 - A hardware service request for channel 6 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */ -#define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */ -#define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */ - -/*! @brief Read current value of the DMA_HRS_HRS6 field. */ -#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS7[7] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 7 is not present - * - 1 - A hardware service request for channel 7 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */ -#define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */ -#define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */ - -/*! @brief Read current value of the DMA_HRS_HRS7 field. */ -#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS8[8] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 8 is not present - * - 1 - A hardware service request for channel 8 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */ -#define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */ -#define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */ - -/*! @brief Read current value of the DMA_HRS_HRS8 field. */ -#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS9[9] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 9 is not present - * - 1 - A hardware service request for channel 9 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */ -#define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */ -#define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */ - -/*! @brief Read current value of the DMA_HRS_HRS9 field. */ -#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS10[10] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 10 is not present - * - 1 - A hardware service request for channel 10 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */ -#define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */ -#define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */ - -/*! @brief Read current value of the DMA_HRS_HRS10 field. */ -#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS11[11] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 11 is not present - * - 1 - A hardware service request for channel 11 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */ -#define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */ -#define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */ - -/*! @brief Read current value of the DMA_HRS_HRS11 field. */ -#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS12[12] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 12 is not present - * - 1 - A hardware service request for channel 12 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */ -#define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */ -#define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */ - -/*! @brief Read current value of the DMA_HRS_HRS12 field. */ -#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS13[13] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 13 is not present - * - 1 - A hardware service request for channel 13 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */ -#define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */ -#define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */ - -/*! @brief Read current value of the DMA_HRS_HRS13 field. */ -#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS14[14] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 14 is not present - * - 1 - A hardware service request for channel 14 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */ -#define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */ -#define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */ - -/*! @brief Read current value of the DMA_HRS_HRS14 field. */ -#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14)) -/*@}*/ - -/*! - * @name Register DMA_HRS, field HRS15[15] (RO) - * - * The HRS bit for its respective channel remains asserted for the period when a - * Hardware Request is Present on the Channel. After the Request is completed - * and Channel is free , the HRS bit is automatically cleared by hardware. - * - * Values: - * - 0 - A hardware service request for channel 15 is not present - * - 1 - A hardware service request for channel 15 is present - */ -/*@{*/ -#define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */ -#define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */ -#define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */ - -/*! @brief Read current value of the DMA_HRS_HRS15 field. */ -#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_DCHPRIn - Channel n Priority Register - ******************************************************************************/ - -/*! - * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW) - * - * Reset value: 0x00U - * - * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the - * contents of these registers define the unique priorities associated with each - * channel . The channel priorities are evaluated by numeric value; for example, 0 is - * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must - * program the channel priorities with unique values; otherwise, a configuration - * error is reported. The range of the priority value is limited to the values of 0 - * through 15. - */ -typedef union _hw_dma_dchprin -{ - uint8_t U; - struct _hw_dma_dchprin_bitfields - { - uint8_t CHPRI : 4; /*!< [3:0] Channel n Arbitration Priority */ - uint8_t RESERVED0 : 2; /*!< [5:4] */ - uint8_t DPA : 1; /*!< [6] Disable Preempt Ability */ - uint8_t ECP : 1; /*!< [7] Enable Channel Preemption */ - } B; -} hw_dma_dchprin_t; - -/*! - * @name Constants and macros for entire DMA_DCHPRIn register - */ -/*@{*/ -#define HW_DMA_DCHPRIn_COUNT (16U) - -#define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n))) - -/* DMA channel index to DMA channel priority register array index conversion macro */ -#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U))) - -#define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n)) -#define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U) -#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v)) -#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v))) -#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v))) -#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_DCHPRIn bitfields - */ - -/*! - * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW) - * - * Channel priority when fixed-priority arbitration is enabled Reset value for - * the channel priority fields, CHPRI, is equal to the corresponding channel - * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. - */ -/*@{*/ -#define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */ -#define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */ -#define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */ - -/*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */ -#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI) - -/*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */ -#define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI) - -/*! @brief Set the CHPRI field to a new value. */ -#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v))) -/*@}*/ - -/*! - * @name Register DMA_DCHPRIn, field DPA[6] (RW) - * - * Values: - * - 0 - Channel n can suspend a lower priority channel - * - 1 - Channel n cannot suspend any channel, regardless of channel priority - */ -/*@{*/ -#define BP_DMA_DCHPRIn_DPA (6U) /*!< Bit position for DMA_DCHPRIn_DPA. */ -#define BM_DMA_DCHPRIn_DPA (0x40U) /*!< Bit mask for DMA_DCHPRIn_DPA. */ -#define BS_DMA_DCHPRIn_DPA (1U) /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */ - -/*! @brief Read current value of the DMA_DCHPRIn_DPA field. */ -#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA)) - -/*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */ -#define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA) - -/*! @brief Set the DPA field to a new value. */ -#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v)) -/*@}*/ - -/*! - * @name Register DMA_DCHPRIn, field ECP[7] (RW) - * - * Values: - * - 0 - Channel n cannot be suspended by a higher priority channel's service - * request - * - 1 - Channel n can be temporarily suspended by the service request of a - * higher priority channel - */ -/*@{*/ -#define BP_DMA_DCHPRIn_ECP (7U) /*!< Bit position for DMA_DCHPRIn_ECP. */ -#define BM_DMA_DCHPRIn_ECP (0x80U) /*!< Bit mask for DMA_DCHPRIn_ECP. */ -#define BS_DMA_DCHPRIn_ECP (1U) /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */ - -/*! @brief Read current value of the DMA_DCHPRIn_ECP field. */ -#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP)) - -/*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */ -#define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP) - -/*! @brief Set the ECP field to a new value. */ -#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_DMA_TCDn_SADDR - TCD Source Address - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_saddr -{ - uint32_t U; - struct _hw_dma_tcdn_saddr_bitfields - { - uint32_t SADDR : 32; /*!< [31:0] Source Address */ - } B; -} hw_dma_tcdn_saddr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_SADDR register - */ -/*@{*/ -#define HW_DMA_TCDn_SADDR_COUNT (16U) - -#define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n))) - -#define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n)) -#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U) -#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v)) -#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v))) -#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_SADDR bitfields - */ - -/*! - * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW) - * - * Memory address pointing to the source data. - */ -/*@{*/ -#define BP_DMA_TCDn_SADDR_SADDR (0U) /*!< Bit position for DMA_TCDn_SADDR_SADDR. */ -#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */ -#define BS_DMA_TCDn_SADDR_SADDR (32U) /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */ - -/*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */ -#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */ -#define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR) - -/*! @brief Set the SADDR field to a new value. */ -#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_soff -{ - uint16_t U; - struct _hw_dma_tcdn_soff_bitfields - { - uint16_t SOFF : 16; /*!< [15:0] Source address signed offset */ - } B; -} hw_dma_tcdn_soff_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_SOFF register - */ -/*@{*/ -#define HW_DMA_TCDn_SOFF_COUNT (16U) - -#define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n))) - -#define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n)) -#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U) -#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v)) -#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v))) -#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_SOFF bitfields - */ - -/*! - * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW) - * - * Sign-extended offset applied to the current source address to form the - * next-state value as each source read is completed. - */ -/*@{*/ -#define BP_DMA_TCDn_SOFF_SOFF (0U) /*!< Bit position for DMA_TCDn_SOFF_SOFF. */ -#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */ -#define BS_DMA_TCDn_SOFF_SOFF (16U) /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */ - -/*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */ -#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */ -#define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF) - -/*! @brief Set the SOFF field to a new value. */ -#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_ATTR - TCD Transfer Attributes - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_attr -{ - uint16_t U; - struct _hw_dma_tcdn_attr_bitfields - { - uint16_t DSIZE : 3; /*!< [2:0] Destination Data Transfer Size */ - uint16_t DMOD : 5; /*!< [7:3] Destination Address Modulo */ - uint16_t SSIZE : 3; /*!< [10:8] Source data transfer size */ - uint16_t SMOD : 5; /*!< [15:11] Source Address Modulo. */ - } B; -} hw_dma_tcdn_attr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_ATTR register - */ -/*@{*/ -#define HW_DMA_TCDn_ATTR_COUNT (16U) - -#define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n))) - -#define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n)) -#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U) -#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v)) -#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v))) -#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_ATTR bitfields - */ - -/*! - * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW) - * - * See the SSIZE definition - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_DSIZE (0U) /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */ -#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */ -#define BS_DMA_TCDn_ATTR_DSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */ -#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */ -#define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE) - -/*! @brief Set the DSIZE field to a new value. */ -#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW) - * - * See the SMOD definition - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_DMOD (3U) /*!< Bit position for DMA_TCDn_ATTR_DMOD. */ -#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */ -#define BS_DMA_TCDn_ATTR_DMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */ -#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */ -#define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD) - -/*! @brief Set the DMOD field to a new value. */ -#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW) - * - * The attempted use of a Reserved encoding causes a configuration error. - * - * Values: - * - 000 - 8-bit - * - 001 - 16-bit - * - 010 - 32-bit - * - 011 - Reserved - * - 100 - 16-byte - * - 101 - 32-byte - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_SSIZE (8U) /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */ -#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */ -#define BS_DMA_TCDn_ATTR_SSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */ -#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */ -#define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE) - -/*! @brief Set the SSIZE field to a new value. */ -#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW) - * - * Values: - * - 0 - Source address modulo feature is disabled - */ -/*@{*/ -#define BP_DMA_TCDn_ATTR_SMOD (11U) /*!< Bit position for DMA_TCDn_ATTR_SMOD. */ -#define BM_DMA_TCDn_ATTR_SMOD (0xF800U) /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */ -#define BS_DMA_TCDn_ATTR_SMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */ - -/*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */ -#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD) - -/*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */ -#define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD) - -/*! @brief Set the SMOD field to a new value. */ -#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v))) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW) - * - * Reset value: 0x00000000U - * - * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO, - * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which - * register to use depends on whether minor loop mapping is disabled, enabled but not - * used for this channel, or enabled and used. TCD word 2 is defined as follows - * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is - * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions - * for TCD word 2's definition. - */ -typedef union _hw_dma_tcdn_nbytes_mlno -{ - uint32_t U; - struct _hw_dma_tcdn_nbytes_mlno_bitfields - { - uint32_t NBYTES : 32; /*!< [31:0] Minor Byte Transfer Count */ - } B; -} hw_dma_tcdn_nbytes_mlno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register - */ -/*@{*/ -#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U) - -#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) - -#define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n)) -#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U) -#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v)) -#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields - */ - -/*! - * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW) - * - * Number of bytes to be transferred in each service request of the channel. As - * a channel activates, the appropriate TCD contents load into the eDMA engine, - * and the appropriate reads and writes perform until the minor byte transfer - * count has transferred. This is an indivisible operation and cannot be halted. - * (Although, it may be stalled by using the bandwidth control field, or via - * preemption.) After the minor count is exhausted, the SADDR and DADDR values are - * written back into the TCD memory, the major iteration count is decremented and - * restored to the TCD memory. If the major iteration count is completed, additional - * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4 - * GB transfer. - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */ -#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */ -#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */ -#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */ -#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES) - -/*! @brief Set the NBYTES field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW) - * - * Reset value: 0x00000000U - * - * One of three registers (this register, TCD_NBYTES_MLNO, or - * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use - * depends on whether minor loop mapping is disabled, enabled but not used for - * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor - * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor - * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the - * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to - * the TCD_NBYTES_MLNO register description. - */ -typedef union _hw_dma_tcdn_nbytes_mloffno -{ - uint32_t U; - struct _hw_dma_tcdn_nbytes_mloffno_bitfields - { - uint32_t NBYTES : 30; /*!< [29:0] Minor Byte Transfer Count */ - uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */ - uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */ - } B; -} hw_dma_tcdn_nbytes_mloffno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register - */ -/*@{*/ -#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U) - -#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) - -#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n)) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v)) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields - */ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW) - * - * Number of bytes to be transferred in each service request of the channel. As - * a channel activates, the appropriate TCD contents load into the eDMA engine, - * and the appropriate reads and writes perform until the minor byte transfer - * count has transferred. This is an indivisible operation and cannot be halted; - * although, it may be stalled by using the bandwidth control field, or via - * preemption. After the minor count is exhausted, the SADDR and DADDR values are written - * back into the TCD memory, the major iteration count is decremented and - * restored to the TCD memory. If the major iteration count is completed, additional - * processing is performed. - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ -#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ -#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */ -#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) - -/*! @brief Set the NBYTES field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW) - * - * Selects whether the minor loop offset is applied to the destination address - * upon minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the DADDR - * - 1 - The minor loop offset is applied to the DADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) - -/*! @brief Set the DMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW) - * - * Selects whether the minor loop offset is applied to the source address upon - * minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the SADDR - * - 1 - The minor loop offset is applied to the SADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) - -/*! @brief Set the SMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW) - * - * Reset value: 0x00000000U - * - * One of three registers (this register, TCD_NBYTES_MLNO, or - * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use - * depends on whether minor loop mapping is disabled, enabled but not used for - * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor - * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE - * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared, - * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop - * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. - */ -typedef union _hw_dma_tcdn_nbytes_mloffyes -{ - uint32_t U; - struct _hw_dma_tcdn_nbytes_mloffyes_bitfields - { - uint32_t NBYTES : 10; /*!< [9:0] Minor Byte Transfer Count */ - uint32_t MLOFF : 20; /*!< [29:10] If SMLOE or DMLOE is set, this - * field represents a sign-extended offset applied to the source or destination - * address to form the next-state value after the minor loop completes. */ - uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */ - uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */ - } B; -} hw_dma_tcdn_nbytes_mloffyes_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register - */ -/*@{*/ -#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U) - -#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) - -#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n)) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v)) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v))) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields - */ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW) - * - * Number of bytes to be transferred in each service request of the channel. As - * a channel activates, the appropriate TCD contents load into the eDMA engine, - * and the appropriate reads and writes perform until the minor byte transfer - * count has transferred. This is an indivisible operation and cannot be halted. - * (Although, it may be stalled by using the bandwidth control field, or via - * preemption.) After the minor count is exhausted, the SADDR and DADDR values are - * written back into the TCD memory, the major iteration count is decremented and - * restored to the TCD memory. If the major iteration count is completed, additional - * processing is performed. - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) - -/*! @brief Set the NBYTES field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW) - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) - -/*! @brief Set the MLOFF field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW) - * - * Selects whether the minor loop offset is applied to the destination address - * upon minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the DADDR - * - 1 - The minor loop offset is applied to the DADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) - -/*! @brief Set the DMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW) - * - * Selects whether the minor loop offset is applied to the source address upon - * minor loop completion. - * - * Values: - * - 0 - The minor loop offset is not applied to the SADDR - * - 1 - The minor loop offset is applied to the SADDR - */ -/*@{*/ -#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ -#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ -#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ - -/*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */ -#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)) - -/*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */ -#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) - -/*! @brief Set the SMLOE field to a new value. */ -#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_slast -{ - uint32_t U; - struct _hw_dma_tcdn_slast_bitfields - { - uint32_t SLAST : 32; /*!< [31:0] Last source Address Adjustment */ - } B; -} hw_dma_tcdn_slast_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_SLAST register - */ -/*@{*/ -#define HW_DMA_TCDn_SLAST_COUNT (16U) - -#define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n))) - -#define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n)) -#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U) -#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v)) -#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v))) -#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_SLAST bitfields - */ - -/*! - * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW) - * - * Adjustment value added to the source address at the completion of the major - * iteration count. This value can be applied to restore the source address to the - * initial value, or adjust the address to reference the next data structure. - * This register uses two's complement notation; the overflow bit is discarded. - */ -/*@{*/ -#define BP_DMA_TCDn_SLAST_SLAST (0U) /*!< Bit position for DMA_TCDn_SLAST_SLAST. */ -#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */ -#define BS_DMA_TCDn_SLAST_SLAST (32U) /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */ - -/*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */ -#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */ -#define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST) - -/*! @brief Set the SLAST field to a new value. */ -#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_DADDR - TCD Destination Address - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_daddr -{ - uint32_t U; - struct _hw_dma_tcdn_daddr_bitfields - { - uint32_t DADDR : 32; /*!< [31:0] Destination Address */ - } B; -} hw_dma_tcdn_daddr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_DADDR register - */ -/*@{*/ -#define HW_DMA_TCDn_DADDR_COUNT (16U) - -#define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n))) - -#define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n)) -#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U) -#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v)) -#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v))) -#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_DADDR bitfields - */ - -/*! - * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW) - * - * Memory address pointing to the destination data. - */ -/*@{*/ -#define BP_DMA_TCDn_DADDR_DADDR (0U) /*!< Bit position for DMA_TCDn_DADDR_DADDR. */ -#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */ -#define BS_DMA_TCDn_DADDR_DADDR (32U) /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */ - -/*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */ -#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */ -#define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR) - -/*! @brief Set the DADDR field to a new value. */ -#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_doff -{ - uint16_t U; - struct _hw_dma_tcdn_doff_bitfields - { - uint16_t DOFF : 16; /*!< [15:0] Destination Address Signed offset */ - } B; -} hw_dma_tcdn_doff_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_DOFF register - */ -/*@{*/ -#define HW_DMA_TCDn_DOFF_COUNT (16U) - -#define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n))) - -#define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n)) -#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U) -#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v)) -#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v))) -#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_DOFF bitfields - */ - -/*! - * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW) - * - * Sign-extended offset applied to the current destination address to form the - * next-state value as each destination write is completed. - */ -/*@{*/ -#define BP_DMA_TCDn_DOFF_DOFF (0U) /*!< Bit position for DMA_TCDn_DOFF_DOFF. */ -#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */ -#define BS_DMA_TCDn_DOFF_DOFF (16U) /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */ - -/*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */ -#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */ -#define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF) - -/*! @brief Set the DOFF field to a new value. */ -#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW) - * - * Reset value: 0x0000U - * - * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as - * follows. - */ -typedef union _hw_dma_tcdn_citer_elinkno -{ - uint16_t U; - struct _hw_dma_tcdn_citer_elinkno_bitfields - { - uint16_t CITER : 15; /*!< [14:0] Current Major Iteration Count */ - uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on - * minor-loop complete */ - } B; -} hw_dma_tcdn_citer_elinkno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register - */ -/*@{*/ -#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U) - -#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n))) - -#define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n)) -#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U) -#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v)) -#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields - */ - -/*! - * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW) - * - * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current - * major loop count for the channel. It is decremented each time the minor loop is - * completed and updated in the transfer control descriptor memory. After the - * major iteration count is exhausted, the channel performs a number of operations - * (e.g., final source and destination address calculations), optionally generating - * an interrupt to signal channel completion before reloading the CITER field - * from the beginning iteration count (BITER) field. When the CITER field is - * initially loaded by software, it must be set to the same value as that contained in - * the BITER field. If the channel is configured to execute a single service - * request, the initial values of BITER and CITER should be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */ -#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */ -#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */ -#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */ -#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER) - -/*! @brief Set the CITER field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables linking to another - * channel, defined by the LINKCH field. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking is disabled, the CITER value - * is extended to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK - * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a - * configuration error is reported. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */ -#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */ -#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */ -#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */ -#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW) - * - * Reset value: 0x0000U - * - * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. - */ -typedef union _hw_dma_tcdn_citer_elinkyes -{ - uint16_t U; - struct _hw_dma_tcdn_citer_elinkyes_bitfields - { - uint16_t CITER : 9; /*!< [8:0] Current Major Iteration Count */ - uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */ - uint16_t RESERVED0 : 2; /*!< [14:13] */ - uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on - * minor-loop complete */ - } B; -} hw_dma_tcdn_citer_elinkyes_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register - */ -/*@{*/ -#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U) - -#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n))) - -#define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n)) -#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U) -#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v)) -#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v))) -#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields - */ - -/*! - * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW) - * - * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current - * major loop count for the channel. It is decremented each time the minor loop is - * completed and updated in the transfer control descriptor memory. After the - * major iteration count is exhausted, the channel performs a number of operations - * (e.g., final source and destination address calculations), optionally generating - * an interrupt to signal channel completion before reloading the CITER field - * from the beginning iteration count (BITER) field. When the CITER field is - * initially loaded by software, it must be set to the same value as that contained in - * the BITER field. If the channel is configured to execute a single service - * request, the initial values of BITER and CITER should be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */ -#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */ -#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */ -#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */ -#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER) - -/*! @brief Set the CITER field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW) - * - * If channel-to-channel linking is enabled (ELINK = 1), then after the minor - * loop is exhausted, the eDMA engine initiates a channel service request to the - * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit. - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */ -#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH) - -/*! @brief Set the LINKCH field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables linking to another - * channel, defined by the LINKCH field. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking is disabled, the CITER value - * is extended to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK - * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a - * configuration error is reported. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */ -#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */ -#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */ -#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */ -#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_dma_tcdn_dlastsga -{ - uint32_t U; - struct _hw_dma_tcdn_dlastsga_bitfields - { - uint32_t DLASTSGA : 32; /*!< [31:0] */ - } B; -} hw_dma_tcdn_dlastsga_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_DLASTSGA register - */ -/*@{*/ -#define HW_DMA_TCDn_DLASTSGA_COUNT (16U) - -#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n))) - -#define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n)) -#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U) -#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v)) -#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v))) -#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields - */ - -/*! - * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW) - * - * Destination last address adjustment or the memory address for the next - * transfer control descriptor to be loaded into this channel (scatter/gather). If - * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at - * the completion of the major iteration count. This value can apply to restore the - * destination address to the initial value or adjust the address to reference - * the next data structure. This field uses two's complement notation for the - * final destination address adjustment. Otherwise: This address points to the - * beginning of a 0-modulo-32-byte region containing the next transfer control - * descriptor to be loaded into this channel. This channel reload is performed as the - * major iteration count completes. The scatter/gather address must be - * 0-modulo-32-byte, else a configuration error is reported. - */ -/*@{*/ -#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */ -#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */ -#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */ - -/*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */ -#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U) - -/*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */ -#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA) - -/*! @brief Set the DLASTSGA field to a new value. */ -#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_CSR - TCD Control and Status - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_dma_tcdn_csr -{ - uint16_t U; - struct _hw_dma_tcdn_csr_bitfields - { - uint16_t START : 1; /*!< [0] Channel Start */ - uint16_t INTMAJOR : 1; /*!< [1] Enable an interrupt when major - * iteration count completes */ - uint16_t INTHALF : 1; /*!< [2] Enable an interrupt when major counter - * is half complete. */ - uint16_t DREQ : 1; /*!< [3] Disable Request */ - uint16_t ESG : 1; /*!< [4] Enable Scatter/Gather Processing */ - uint16_t MAJORELINK : 1; /*!< [5] Enable channel-to-channel linking - * on major loop complete */ - uint16_t ACTIVE : 1; /*!< [6] Channel Active */ - uint16_t DONE : 1; /*!< [7] Channel Done */ - uint16_t MAJORLINKCH : 4; /*!< [11:8] Link Channel Number */ - uint16_t RESERVED0 : 2; /*!< [13:12] */ - uint16_t BWC : 2; /*!< [15:14] Bandwidth Control */ - } B; -} hw_dma_tcdn_csr_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_CSR register - */ -/*@{*/ -#define HW_DMA_TCDn_CSR_COUNT (16U) - -#define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n))) - -#define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n)) -#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U) -#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v)) -#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v))) -#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_CSR bitfields - */ - -/*! - * @name Register DMA_TCDn_CSR, field START[0] (RW) - * - * If this flag is set, the channel is requesting service. The eDMA hardware - * automatically clears this flag after the channel begins execution. - * - * Values: - * - 0 - The channel is not explicitly started - * - 1 - The channel is explicitly started via a software initiated service - * request - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_START (0U) /*!< Bit position for DMA_TCDn_CSR_START. */ -#define BM_DMA_TCDn_CSR_START (0x0001U) /*!< Bit mask for DMA_TCDn_CSR_START. */ -#define BS_DMA_TCDn_CSR_START (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_START. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_START field. */ -#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_START. */ -#define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START) - -/*! @brief Set the START field to a new value. */ -#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW) - * - * If this flag is set, the channel generates an interrupt request by setting - * the appropriate bit in the INT when the current major iteration count reaches - * zero. - * - * Values: - * - 0 - The end-of-major loop interrupt is disabled - * - 1 - The end-of-major loop interrupt is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */ -#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */ -#define BS_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */ -#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */ -#define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR) - -/*! @brief Set the INTMAJOR field to a new value. */ -#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW) - * - * If this flag is set, the channel generates an interrupt request by setting - * the appropriate bit in the INT register when the current major iteration count - * reaches the halfway point. Specifically, the comparison performed by the eDMA - * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is - * provided to support double-buffered (aka ping-pong) schemes or other types of data - * movement where the processor needs an early indication of the transfer's - * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead. - * - * Values: - * - 0 - The half-point interrupt is disabled - * - 1 - The half-point interrupt is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_INTHALF (2U) /*!< Bit position for DMA_TCDn_CSR_INTHALF. */ -#define BM_DMA_TCDn_CSR_INTHALF (0x0004U) /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */ -#define BS_DMA_TCDn_CSR_INTHALF (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */ -#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */ -#define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF) - -/*! @brief Set the INTHALF field to a new value. */ -#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field DREQ[3] (RW) - * - * If this flag is set, the eDMA hardware automatically clears the corresponding - * ERQ bit when the current major iteration count reaches zero. - * - * Values: - * - 0 - The channel's ERQ bit is not affected - * - 1 - The channel's ERQ bit is cleared when the major loop is complete - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_DREQ (3U) /*!< Bit position for DMA_TCDn_CSR_DREQ. */ -#define BM_DMA_TCDn_CSR_DREQ (0x0008U) /*!< Bit mask for DMA_TCDn_CSR_DREQ. */ -#define BS_DMA_TCDn_CSR_DREQ (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */ -#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */ -#define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ) - -/*! @brief Set the DREQ field to a new value. */ -#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field ESG[4] (RW) - * - * As the channel completes the major loop, this flag enables scatter/gather - * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a - * memory pointer to a 0-modulo-32 address containing a 32-byte data structure - * loaded as the transfer control descriptor into the local memory. To support the - * dynamic scatter/gather coherency model, this field is forced to zero when - * written to while the TCDn_CSR[DONE] bit is set. - * - * Values: - * - 0 - The current channel's TCD is normal format. - * - 1 - The current channel's TCD specifies a scatter gather format. The - * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this - * channel after the major loop completes its execution. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_ESG (4U) /*!< Bit position for DMA_TCDn_CSR_ESG. */ -#define BM_DMA_TCDn_CSR_ESG (0x0010U) /*!< Bit mask for DMA_TCDn_CSR_ESG. */ -#define BS_DMA_TCDn_CSR_ESG (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */ -#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */ -#define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG) - -/*! @brief Set the ESG field to a new value. */ -#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW) - * - * As the channel completes the major loop, this flag enables the linking to - * another channel, defined by MAJORLINKCH. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. To support the dynamic linking coherency model, - * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_MAJORELINK (5U) /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */ -#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */ -#define BS_DMA_TCDn_CSR_MAJORELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */ -#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */ -#define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK) - -/*! @brief Set the MAJORELINK field to a new value. */ -#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW) - * - * This flag signals the channel is currently in execution. It is set when - * channel service begins, and the eDMA clears it as the minor loop completes or if - * any error condition is detected. This bit resets to zero. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_ACTIVE (6U) /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */ -#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */ -#define BS_DMA_TCDn_CSR_ACTIVE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */ -#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */ -#define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE) - -/*! @brief Set the ACTIVE field to a new value. */ -#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field DONE[7] (RW) - * - * This flag indicates the eDMA has completed the major loop. The eDMA engine - * sets it as the CITER count reaches zero; The software clears it, or the hardware - * when the channel is activated. This bit must be cleared to write the - * MAJORELINK or ESG bits. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_DONE (7U) /*!< Bit position for DMA_TCDn_CSR_DONE. */ -#define BM_DMA_TCDn_CSR_DONE (0x0080U) /*!< Bit mask for DMA_TCDn_CSR_DONE. */ -#define BS_DMA_TCDn_CSR_DONE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */ -#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE)) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */ -#define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE) - -/*! @brief Set the DONE field to a new value. */ -#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v)) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW) - * - * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is - * performed after the major loop counter is exhausted. else After the major loop - * counter is exhausted, the eDMA engine initiates a channel service request at the - * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit. - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */ -#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */ -#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */ -#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */ -#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH) - -/*! @brief Set the MAJORLINKCH field to a new value. */ -#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW) - * - * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as - * the eDMA processes the minor loop, it continuously generates read/write - * sequences until the minor count is exhausted. This field forces the eDMA to stall - * after the completion of each read/write access to control the bus request - * bandwidth seen by the crossbar switch. If the source and destination sizes are equal, - * this field is ignored between the first and second transfers and after the - * last write of each minor loop. This behavior is a side effect of reducing - * start-up latency. - * - * Values: - * - 00 - No eDMA engine stalls - * - 01 - Reserved - * - 10 - eDMA engine stalls for 4 cycles after each r/w - * - 11 - eDMA engine stalls for 8 cycles after each r/w - */ -/*@{*/ -#define BP_DMA_TCDn_CSR_BWC (14U) /*!< Bit position for DMA_TCDn_CSR_BWC. */ -#define BM_DMA_TCDn_CSR_BWC (0xC000U) /*!< Bit mask for DMA_TCDn_CSR_BWC. */ -#define BS_DMA_TCDn_CSR_BWC (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */ - -/*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */ -#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC) - -/*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */ -#define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC) - -/*! @brief Set the BWC field to a new value. */ -#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v))) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW) - * - * Reset value: 0x0000U - * - * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined - * as follows. - */ -typedef union _hw_dma_tcdn_biter_elinkno -{ - uint16_t U; - struct _hw_dma_tcdn_biter_elinkno_bitfields - { - uint16_t BITER : 15; /*!< [14:0] Starting Major Iteration Count */ - uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on - * minor loop complete */ - } B; -} hw_dma_tcdn_biter_elinkno_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register - */ -/*@{*/ -#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U) - -#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n))) - -#define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n)) -#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U) -#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v)) -#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v))) -#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields - */ - -/*! - * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW) - * - * As the transfer control descriptor is first loaded by software, this 9-bit - * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER - * field. As the major iteration count is exhausted, the contents of this field - * are reloaded into the CITER field. When the software loads the TCD, this field - * must be set equal to the corresponding CITER field; otherwise, a configuration - * error is reported. As the major iteration count is exhausted, the contents of - * this field is reloaded into the CITER field. If the channel is configured to - * execute a single service request, the initial values of BITER and CITER should - * be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */ -#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */ -#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */ -#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */ -#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER) - -/*! @brief Set the BITER field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables the linking to - * another channel, defined by BITER[LINKCH]. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking is disabled, the BITER value - * extends to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel - * linking. When the software loads the TCD, this field must be set equal to the - * corresponding CITER field; otherwise, a configuration error is reported. As the - * major iteration count is exhausted, the contents of this field is reloaded - * into the CITER field. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */ -#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */ -#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */ -#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */ -#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v)) -/*@}*/ -/******************************************************************************* - * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) - ******************************************************************************/ - -/*! - * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW) - * - * Reset value: 0x0000U - * - * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as - * follows. - */ -typedef union _hw_dma_tcdn_biter_elinkyes -{ - uint16_t U; - struct _hw_dma_tcdn_biter_elinkyes_bitfields - { - uint16_t BITER : 9; /*!< [8:0] Starting Major Iteration Count */ - uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */ - uint16_t RESERVED0 : 2; /*!< [14:13] */ - uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on - * minor loop complete */ - } B; -} hw_dma_tcdn_biter_elinkyes_t; - -/*! - * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register - */ -/*@{*/ -#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U) - -#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n))) - -#define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n)) -#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U) -#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v)) -#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v))) -#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v))) -#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields - */ - -/*! - * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW) - * - * As the transfer control descriptor is first loaded by software, this 9-bit - * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER - * field. As the major iteration count is exhausted, the contents of this field - * are reloaded into the CITER field. When the software loads the TCD, this field - * must be set equal to the corresponding CITER field; otherwise, a configuration - * error is reported. As the major iteration count is exhausted, the contents of - * this field is reloaded into the CITER field. If the channel is configured to - * execute a single service request, the initial values of BITER and CITER should - * be 0x0001. - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */ -#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */ -#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */ -#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */ -#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER) - -/*! @brief Set the BITER field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW) - * - * If channel-to-channel linking is enabled (ELINK = 1), then after the minor - * loop is exhausted, the eDMA engine initiates a channel service request at the - * channel defined by these four bits by setting that channel's TCDn_CSR[START] - * bit. When the software loads the TCD, this field must be set equal to the - * corresponding CITER field; otherwise, a configuration error is reported. As the major - * iteration count is exhausted, the contents of this field is reloaded into the - * CITER field. - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */ -#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH) - -/*! @brief Set the LINKCH field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v))) -/*@}*/ - -/*! - * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW) - * - * As the channel completes the minor loop, this flag enables the linking to - * another channel, defined by BITER[LINKCH]. The link target channel initiates a - * channel service request via an internal mechanism that sets the TCDn_CSR[START] - * bit of the specified channel. If channel linking disables, the BITER value - * extends to 15 bits in place of a link channel number. If the major loop is - * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel - * linking. When the software loads the TCD, this field must be set equal to the - * corresponding CITER field; otherwise, a configuration error is reported. As the - * major iteration count is exhausted, the contents of this field is reloaded into - * the CITER field. - * - * Values: - * - 0 - The channel-to-channel linking is disabled - * - 1 - The channel-to-channel linking is enabled - */ -/*@{*/ -#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */ -#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */ -#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */ - -/*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */ -#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK)) - -/*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */ -#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK) - -/*! @brief Set the ELINK field to a new value. */ -#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v)) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_dma_t - module struct - ******************************************************************************/ -/*! - * @brief All DMA module registers. - */ -#pragma pack(1) -typedef struct _hw_dma -{ - __IO hw_dma_cr_t CR; /*!< [0x0] Control Register */ - __I hw_dma_es_t ES; /*!< [0x4] Error Status Register */ - uint8_t _reserved0[4]; - __IO hw_dma_erq_t ERQ; /*!< [0xC] Enable Request Register */ - uint8_t _reserved1[4]; - __IO hw_dma_eei_t EEI; /*!< [0x14] Enable Error Interrupt Register */ - __O hw_dma_ceei_t CEEI; /*!< [0x18] Clear Enable Error Interrupt Register */ - __O hw_dma_seei_t SEEI; /*!< [0x19] Set Enable Error Interrupt Register */ - __O hw_dma_cerq_t CERQ; /*!< [0x1A] Clear Enable Request Register */ - __O hw_dma_serq_t SERQ; /*!< [0x1B] Set Enable Request Register */ - __O hw_dma_cdne_t CDNE; /*!< [0x1C] Clear DONE Status Bit Register */ - __O hw_dma_ssrt_t SSRT; /*!< [0x1D] Set START Bit Register */ - __O hw_dma_cerr_t CERR; /*!< [0x1E] Clear Error Register */ - __O hw_dma_cint_t CINT; /*!< [0x1F] Clear Interrupt Request Register */ - uint8_t _reserved2[4]; - __IO hw_dma_int_t INT; /*!< [0x24] Interrupt Request Register */ - uint8_t _reserved3[4]; - __IO hw_dma_err_t ERR; /*!< [0x2C] Error Register */ - uint8_t _reserved4[4]; - __I hw_dma_hrs_t HRS; /*!< [0x34] Hardware Request Status Register */ - uint8_t _reserved5[200]; - __IO hw_dma_dchprin_t DCHPRIn[16]; /*!< [0x100] Channel n Priority Register */ - uint8_t _reserved6[3824]; - struct { - __IO hw_dma_tcdn_saddr_t TCDn_SADDR; /*!< [0x1000] TCD Source Address */ - __IO hw_dma_tcdn_soff_t TCDn_SOFF; /*!< [0x1004] TCD Signed Source Address Offset */ - __IO hw_dma_tcdn_attr_t TCDn_ATTR; /*!< [0x1006] TCD Transfer Attributes */ - union { - __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */ - __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ - __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ - }; - __IO hw_dma_tcdn_slast_t TCDn_SLAST; /*!< [0x100C] TCD Last Source Address Adjustment */ - __IO hw_dma_tcdn_daddr_t TCDn_DADDR; /*!< [0x1010] TCD Destination Address */ - __IO hw_dma_tcdn_doff_t TCDn_DOFF; /*!< [0x1014] TCD Signed Destination Address Offset */ - union { - __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ - __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ - }; - __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */ - __IO hw_dma_tcdn_csr_t TCDn_CSR; /*!< [0x101C] TCD Control and Status */ - union { - __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ - __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ - }; - } TCD[16]; -} hw_dma_t; -#pragma pack() - -/*! @brief Macro to access all DMA registers. */ -/*! @param x DMA module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_DMA(DMA_BASE). */ -#define HW_DMA(x) (*(hw_dma_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_DMA_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dmamux.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dmamux.h deleted file mode 100644 index 29c452af561..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dmamux.h +++ /dev/null @@ -1,241 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_DMAMUX_REGISTERS_H__ -#define __HW_DMAMUX_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 DMAMUX - * - * DMA channel multiplexor - * - * Registers defined in this header file: - * - HW_DMAMUX_CHCFGn - Channel Configuration register - * - * - hw_dmamux_t - Struct containing all module registers. - */ - -#define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */ - -/******************************************************************************* - * HW_DMAMUX_CHCFGn - Channel Configuration register - ******************************************************************************/ - -/*! - * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW) - * - * Reset value: 0x00U - * - * Each of the DMA channels can be independently enabled/disabled and associated - * with one of the DMA slots (peripheral slots or always-on slots) in the - * system. Setting multiple CHCFG registers with the same source value will result in - * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). - * Before changing the trigger or source settings, a DMA channel must be disabled - * via CHCFGn[ENBL]. - */ -typedef union _hw_dmamux_chcfgn -{ - uint8_t U; - struct _hw_dmamux_chcfgn_bitfields - { - uint8_t SOURCE : 6; /*!< [5:0] DMA Channel Source (Slot) */ - uint8_t TRIG : 1; /*!< [6] DMA Channel Trigger Enable */ - uint8_t ENBL : 1; /*!< [7] DMA Channel Enable */ - } B; -} hw_dmamux_chcfgn_t; - -/*! - * @name Constants and macros for entire DMAMUX_CHCFGn register - */ -/*@{*/ -#define HW_DMAMUX_CHCFGn_COUNT (16U) - -#define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n))) - -#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n)) -#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U) -#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v)) -#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v))) -#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v))) -#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual DMAMUX_CHCFGn bitfields - */ - -/*! - * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW) - * - * Specifies which DMA source, if any, is routed to a particular DMA channel. - * See your device's chip configuration details for information about the - * peripherals and their slot numbers. - */ -/*@{*/ -#define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */ -#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */ -#define BS_DMAMUX_CHCFGn_SOURCE (6U) /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */ - -/*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */ -#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE) - -/*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */ -#define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE) - -/*! @brief Set the SOURCE field to a new value. */ -#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v))) -/*@}*/ - -/*! - * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW) - * - * Enables the periodic trigger capability for the triggered DMA channel. - * - * Values: - * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the - * DMA Channel will simply route the specified source to the DMA channel. - * (Normal mode) - * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the - * DMAMUX is in Periodic Trigger mode. - */ -/*@{*/ -#define BP_DMAMUX_CHCFGn_TRIG (6U) /*!< Bit position for DMAMUX_CHCFGn_TRIG. */ -#define BM_DMAMUX_CHCFGn_TRIG (0x40U) /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */ -#define BS_DMAMUX_CHCFGn_TRIG (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */ - -/*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */ -#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG)) - -/*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */ -#define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG) - -/*! @brief Set the TRIG field to a new value. */ -#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v)) -/*@}*/ - -/*! - * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW) - * - * Enables the DMA channel. - * - * Values: - * - 0 - DMA channel is disabled. This mode is primarily used during - * configuration of the DMAMux. The DMA has separate channel enables/disables, which - * should be used to disable or reconfigure a DMA channel. - * - 1 - DMA channel is enabled - */ -/*@{*/ -#define BP_DMAMUX_CHCFGn_ENBL (7U) /*!< Bit position for DMAMUX_CHCFGn_ENBL. */ -#define BM_DMAMUX_CHCFGn_ENBL (0x80U) /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */ -#define BS_DMAMUX_CHCFGn_ENBL (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */ - -/*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */ -#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL)) - -/*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */ -#define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL) - -/*! @brief Set the ENBL field to a new value. */ -#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_dmamux_t - module struct - ******************************************************************************/ -/*! - * @brief All DMAMUX module registers. - */ -#pragma pack(1) -typedef struct _hw_dmamux -{ - __IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */ -} hw_dmamux_t; -#pragma pack() - -/*! @brief Macro to access all DMAMUX registers. */ -/*! @param x DMAMUX module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_DMAMUX(DMAMUX_BASE). */ -#define HW_DMAMUX(x) (*(hw_dmamux_t *)(x)) - -#endif /* __HW_DMAMUX_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_enet.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_enet.h deleted file mode 100644 index 48e92c683e5..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_enet.h +++ /dev/null @@ -1,7497 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_ENET_REGISTERS_H__ -#define __HW_ENET_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 ENET - * - * Ethernet MAC-NET Core - * - * Registers defined in this header file: - * - HW_ENET_EIR - Interrupt Event Register - * - HW_ENET_EIMR - Interrupt Mask Register - * - HW_ENET_RDAR - Receive Descriptor Active Register - * - HW_ENET_TDAR - Transmit Descriptor Active Register - * - HW_ENET_ECR - Ethernet Control Register - * - HW_ENET_MMFR - MII Management Frame Register - * - HW_ENET_MSCR - MII Speed Control Register - * - HW_ENET_MIBC - MIB Control Register - * - HW_ENET_RCR - Receive Control Register - * - HW_ENET_TCR - Transmit Control Register - * - HW_ENET_PALR - Physical Address Lower Register - * - HW_ENET_PAUR - Physical Address Upper Register - * - HW_ENET_OPD - Opcode/Pause Duration Register - * - HW_ENET_IAUR - Descriptor Individual Upper Address Register - * - HW_ENET_IALR - Descriptor Individual Lower Address Register - * - HW_ENET_GAUR - Descriptor Group Upper Address Register - * - HW_ENET_GALR - Descriptor Group Lower Address Register - * - HW_ENET_TFWR - Transmit FIFO Watermark Register - * - HW_ENET_RDSR - Receive Descriptor Ring Start Register - * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register - * - HW_ENET_MRBR - Maximum Receive Buffer Size Register - * - HW_ENET_RSFL - Receive FIFO Section Full Threshold - * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold - * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold - * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold - * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold - * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold - * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold - * - HW_ENET_TIPG - Transmit Inter-Packet Gap - * - HW_ENET_FTRL - Frame Truncation Length - * - HW_ENET_TACC - Transmit Accelerator Function Configuration - * - HW_ENET_RACC - Receive Accelerator Function Configuration - * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register - * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register - * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register - * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register - * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register - * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register - * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register - * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register - * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register - * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register - * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register - * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register - * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register - * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register - * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register - * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register - * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register - * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register - * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register - * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register - * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register - * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register - * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register - * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register - * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register - * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register - * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register - * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register - * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register - * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register - * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register - * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register - * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register - * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register - * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register - * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register - * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register - * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register - * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register - * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register - * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register - * - HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register - * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register - * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register - * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register - * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register - * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register - * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register - * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register - * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register - * - HW_ENET_ATCR - Adjustable Timer Control Register - * - HW_ENET_ATVR - Timer Value Register - * - HW_ENET_ATOFF - Timer Offset Register - * - HW_ENET_ATPER - Timer Period Register - * - HW_ENET_ATCOR - Timer Correction Register - * - HW_ENET_ATINC - Time-Stamping Clock Period Register - * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame - * - HW_ENET_TGSR - Timer Global Status Register - * - HW_ENET_TCSRn - Timer Control Status Register - * - HW_ENET_TCCRn - Timer Compare Capture Register - * - * - hw_enet_t - Struct containing all module registers. - */ - -#define HW_ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */ - -/******************************************************************************* - * HW_ENET_EIR - Interrupt Event Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_EIR - Interrupt Event Register (RW) - * - * Reset value: 0x00000000U - * - * When an event occurs that sets a bit in EIR, an interrupt occurs if the - * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to - * an EIR bit clears it; writing 0 has no effect. This register is cleared upon - * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the - * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1. - * Legacy mode does not require these flags to be enabled. - */ -typedef union _hw_enet_eir -{ - uint32_t U; - struct _hw_enet_eir_bitfields - { - uint32_t RESERVED0 : 15; /*!< [14:0] */ - uint32_t TS_TIMER : 1; /*!< [15] Timestamp Timer */ - uint32_t TS_AVAIL : 1; /*!< [16] Transmit Timestamp Available */ - uint32_t WAKEUP : 1; /*!< [17] Node Wakeup Request Indication */ - uint32_t PLR : 1; /*!< [18] Payload Receive Error */ - uint32_t UN : 1; /*!< [19] Transmit FIFO Underrun */ - uint32_t RL : 1; /*!< [20] Collision Retry Limit */ - uint32_t LC : 1; /*!< [21] Late Collision */ - uint32_t EBERR : 1; /*!< [22] Ethernet Bus Error */ - uint32_t MII : 1; /*!< [23] MII Interrupt. */ - uint32_t RXB : 1; /*!< [24] Receive Buffer Interrupt */ - uint32_t RXF : 1; /*!< [25] Receive Frame Interrupt */ - uint32_t TXB : 1; /*!< [26] Transmit Buffer Interrupt */ - uint32_t TXF : 1; /*!< [27] Transmit Frame Interrupt */ - uint32_t GRA : 1; /*!< [28] Graceful Stop Complete */ - uint32_t BABT : 1; /*!< [29] Babbling Transmit Error */ - uint32_t BABR : 1; /*!< [30] Babbling Receive Error */ - uint32_t RESERVED1 : 1; /*!< [31] */ - } B; -} hw_enet_eir_t; - -/*! - * @name Constants and macros for entire ENET_EIR register - */ -/*@{*/ -#define HW_ENET_EIR_ADDR(x) ((x) + 0x4U) - -#define HW_ENET_EIR(x) (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x)) -#define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U) -#define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v)) -#define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) | (v))) -#define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v))) -#define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_EIR bitfields - */ - -/*! - * @name Register ENET_EIR, field TS_TIMER[15] (W1C) - * - * The adjustable timer reached the period event. A period event interrupt can - * be generated if ATCR[PEREN] is set and the timer wraps according to the - * periodic setting in the ATPER register. Set the timer period value before setting - * ATCR[PEREN]. - */ -/*@{*/ -#define BP_ENET_EIR_TS_TIMER (15U) /*!< Bit position for ENET_EIR_TS_TIMER. */ -#define BM_ENET_EIR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIR_TS_TIMER. */ -#define BS_ENET_EIR_TS_TIMER (1U) /*!< Bit field size in bits for ENET_EIR_TS_TIMER. */ - -/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */ -#define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER)) - -/*! @brief Format value for bitfield ENET_EIR_TS_TIMER. */ -#define BF_ENET_EIR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_TIMER) & BM_ENET_EIR_TS_TIMER) - -/*! @brief Set the TS_TIMER field to a new value. */ -#define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field TS_AVAIL[16] (W1C) - * - * Indicates that the timestamp of the last transmitted timing frame is - * available in the ATSTMP register. - */ -/*@{*/ -#define BP_ENET_EIR_TS_AVAIL (16U) /*!< Bit position for ENET_EIR_TS_AVAIL. */ -#define BM_ENET_EIR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIR_TS_AVAIL. */ -#define BS_ENET_EIR_TS_AVAIL (1U) /*!< Bit field size in bits for ENET_EIR_TS_AVAIL. */ - -/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */ -#define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL)) - -/*! @brief Format value for bitfield ENET_EIR_TS_AVAIL. */ -#define BF_ENET_EIR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_AVAIL) & BM_ENET_EIR_TS_AVAIL) - -/*! @brief Set the TS_AVAIL field to a new value. */ -#define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field WAKEUP[17] (W1C) - * - * Read-only status bit to indicate that a magic packet has been detected. Will - * act only if ECR[MAGICEN] is set. - */ -/*@{*/ -#define BP_ENET_EIR_WAKEUP (17U) /*!< Bit position for ENET_EIR_WAKEUP. */ -#define BM_ENET_EIR_WAKEUP (0x00020000U) /*!< Bit mask for ENET_EIR_WAKEUP. */ -#define BS_ENET_EIR_WAKEUP (1U) /*!< Bit field size in bits for ENET_EIR_WAKEUP. */ - -/*! @brief Read current value of the ENET_EIR_WAKEUP field. */ -#define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP)) - -/*! @brief Format value for bitfield ENET_EIR_WAKEUP. */ -#define BF_ENET_EIR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_WAKEUP) & BM_ENET_EIR_WAKEUP) - -/*! @brief Set the WAKEUP field to a new value. */ -#define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field PLR[18] (W1C) - * - * Indicates a frame was received with a payload length error. See Frame - * Length/Type Verification: Payload Length Check for more information. - */ -/*@{*/ -#define BP_ENET_EIR_PLR (18U) /*!< Bit position for ENET_EIR_PLR. */ -#define BM_ENET_EIR_PLR (0x00040000U) /*!< Bit mask for ENET_EIR_PLR. */ -#define BS_ENET_EIR_PLR (1U) /*!< Bit field size in bits for ENET_EIR_PLR. */ - -/*! @brief Read current value of the ENET_EIR_PLR field. */ -#define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR)) - -/*! @brief Format value for bitfield ENET_EIR_PLR. */ -#define BF_ENET_EIR_PLR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_PLR) & BM_ENET_EIR_PLR) - -/*! @brief Set the PLR field to a new value. */ -#define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field UN[19] (W1C) - * - * Indicates the transmit FIFO became empty before the complete frame was - * transmitted. A bad CRC is appended to the frame fragment and the remainder of the - * frame is discarded. - */ -/*@{*/ -#define BP_ENET_EIR_UN (19U) /*!< Bit position for ENET_EIR_UN. */ -#define BM_ENET_EIR_UN (0x00080000U) /*!< Bit mask for ENET_EIR_UN. */ -#define BS_ENET_EIR_UN (1U) /*!< Bit field size in bits for ENET_EIR_UN. */ - -/*! @brief Read current value of the ENET_EIR_UN field. */ -#define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN)) - -/*! @brief Format value for bitfield ENET_EIR_UN. */ -#define BF_ENET_EIR_UN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_UN) & BM_ENET_EIR_UN) - -/*! @brief Set the UN field to a new value. */ -#define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field RL[20] (W1C) - * - * Indicates a collision occurred on each of 16 successive attempts to transmit - * the frame. The frame is discarded without being transmitted and transmission - * of the next frame commences. This error can only occur in half-duplex mode. - */ -/*@{*/ -#define BP_ENET_EIR_RL (20U) /*!< Bit position for ENET_EIR_RL. */ -#define BM_ENET_EIR_RL (0x00100000U) /*!< Bit mask for ENET_EIR_RL. */ -#define BS_ENET_EIR_RL (1U) /*!< Bit field size in bits for ENET_EIR_RL. */ - -/*! @brief Read current value of the ENET_EIR_RL field. */ -#define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL)) - -/*! @brief Format value for bitfield ENET_EIR_RL. */ -#define BF_ENET_EIR_RL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RL) & BM_ENET_EIR_RL) - -/*! @brief Set the RL field to a new value. */ -#define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field LC[21] (W1C) - * - * Indicates a collision occurred beyond the collision window (slot time) in - * half-duplex mode. The frame truncates with a bad CRC and the remainder of the - * frame is discarded. - */ -/*@{*/ -#define BP_ENET_EIR_LC (21U) /*!< Bit position for ENET_EIR_LC. */ -#define BM_ENET_EIR_LC (0x00200000U) /*!< Bit mask for ENET_EIR_LC. */ -#define BS_ENET_EIR_LC (1U) /*!< Bit field size in bits for ENET_EIR_LC. */ - -/*! @brief Read current value of the ENET_EIR_LC field. */ -#define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC)) - -/*! @brief Format value for bitfield ENET_EIR_LC. */ -#define BF_ENET_EIR_LC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_LC) & BM_ENET_EIR_LC) - -/*! @brief Set the LC field to a new value. */ -#define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field EBERR[22] (W1C) - * - * Indicates a system bus error occurred when a uDMA transaction is underway. - * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the - * MAC. When this occurs, software must ensure proper actions, possibly resetting - * the system, to resume normal operation. - */ -/*@{*/ -#define BP_ENET_EIR_EBERR (22U) /*!< Bit position for ENET_EIR_EBERR. */ -#define BM_ENET_EIR_EBERR (0x00400000U) /*!< Bit mask for ENET_EIR_EBERR. */ -#define BS_ENET_EIR_EBERR (1U) /*!< Bit field size in bits for ENET_EIR_EBERR. */ - -/*! @brief Read current value of the ENET_EIR_EBERR field. */ -#define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR)) - -/*! @brief Format value for bitfield ENET_EIR_EBERR. */ -#define BF_ENET_EIR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_EBERR) & BM_ENET_EIR_EBERR) - -/*! @brief Set the EBERR field to a new value. */ -#define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field MII[23] (W1C) - * - * Indicates that the MII has completed the data transfer requested. - */ -/*@{*/ -#define BP_ENET_EIR_MII (23U) /*!< Bit position for ENET_EIR_MII. */ -#define BM_ENET_EIR_MII (0x00800000U) /*!< Bit mask for ENET_EIR_MII. */ -#define BS_ENET_EIR_MII (1U) /*!< Bit field size in bits for ENET_EIR_MII. */ - -/*! @brief Read current value of the ENET_EIR_MII field. */ -#define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII)) - -/*! @brief Format value for bitfield ENET_EIR_MII. */ -#define BF_ENET_EIR_MII(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_MII) & BM_ENET_EIR_MII) - -/*! @brief Set the MII field to a new value. */ -#define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field RXB[24] (W1C) - * - * Indicates a receive buffer descriptor is not the last in the frame has been - * updated. - */ -/*@{*/ -#define BP_ENET_EIR_RXB (24U) /*!< Bit position for ENET_EIR_RXB. */ -#define BM_ENET_EIR_RXB (0x01000000U) /*!< Bit mask for ENET_EIR_RXB. */ -#define BS_ENET_EIR_RXB (1U) /*!< Bit field size in bits for ENET_EIR_RXB. */ - -/*! @brief Read current value of the ENET_EIR_RXB field. */ -#define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB)) - -/*! @brief Format value for bitfield ENET_EIR_RXB. */ -#define BF_ENET_EIR_RXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXB) & BM_ENET_EIR_RXB) - -/*! @brief Set the RXB field to a new value. */ -#define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field RXF[25] (W1C) - * - * Indicates a frame has been received and the last corresponding buffer - * descriptor has been updated. - */ -/*@{*/ -#define BP_ENET_EIR_RXF (25U) /*!< Bit position for ENET_EIR_RXF. */ -#define BM_ENET_EIR_RXF (0x02000000U) /*!< Bit mask for ENET_EIR_RXF. */ -#define BS_ENET_EIR_RXF (1U) /*!< Bit field size in bits for ENET_EIR_RXF. */ - -/*! @brief Read current value of the ENET_EIR_RXF field. */ -#define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF)) - -/*! @brief Format value for bitfield ENET_EIR_RXF. */ -#define BF_ENET_EIR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXF) & BM_ENET_EIR_RXF) - -/*! @brief Set the RXF field to a new value. */ -#define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field TXB[26] (W1C) - * - * Indicates a transmit buffer descriptor has been updated. - */ -/*@{*/ -#define BP_ENET_EIR_TXB (26U) /*!< Bit position for ENET_EIR_TXB. */ -#define BM_ENET_EIR_TXB (0x04000000U) /*!< Bit mask for ENET_EIR_TXB. */ -#define BS_ENET_EIR_TXB (1U) /*!< Bit field size in bits for ENET_EIR_TXB. */ - -/*! @brief Read current value of the ENET_EIR_TXB field. */ -#define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB)) - -/*! @brief Format value for bitfield ENET_EIR_TXB. */ -#define BF_ENET_EIR_TXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXB) & BM_ENET_EIR_TXB) - -/*! @brief Set the TXB field to a new value. */ -#define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field TXF[27] (W1C) - * - * Indicates a frame has been transmitted and the last corresponding buffer - * descriptor has been updated. - */ -/*@{*/ -#define BP_ENET_EIR_TXF (27U) /*!< Bit position for ENET_EIR_TXF. */ -#define BM_ENET_EIR_TXF (0x08000000U) /*!< Bit mask for ENET_EIR_TXF. */ -#define BS_ENET_EIR_TXF (1U) /*!< Bit field size in bits for ENET_EIR_TXF. */ - -/*! @brief Read current value of the ENET_EIR_TXF field. */ -#define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF)) - -/*! @brief Format value for bitfield ENET_EIR_TXF. */ -#define BF_ENET_EIR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXF) & BM_ENET_EIR_TXF) - -/*! @brief Set the TXF field to a new value. */ -#define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field GRA[28] (W1C) - * - * This interrupt is asserted after the transmitter is put into a pause state - * after completion of the frame currently being transmitted. See Graceful Transmit - * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is - * asserted only when the TX transitions into the stopped state. If this bit is - * cleared by writing 1 and the TX is still stopped, the bit is not set again. - */ -/*@{*/ -#define BP_ENET_EIR_GRA (28U) /*!< Bit position for ENET_EIR_GRA. */ -#define BM_ENET_EIR_GRA (0x10000000U) /*!< Bit mask for ENET_EIR_GRA. */ -#define BS_ENET_EIR_GRA (1U) /*!< Bit field size in bits for ENET_EIR_GRA. */ - -/*! @brief Read current value of the ENET_EIR_GRA field. */ -#define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA)) - -/*! @brief Format value for bitfield ENET_EIR_GRA. */ -#define BF_ENET_EIR_GRA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_GRA) & BM_ENET_EIR_GRA) - -/*! @brief Set the GRA field to a new value. */ -#define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field BABT[29] (W1C) - * - * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually - * this condition is caused when a frame that is too long is placed into the - * transmit data buffer(s). Truncation does not occur. - */ -/*@{*/ -#define BP_ENET_EIR_BABT (29U) /*!< Bit position for ENET_EIR_BABT. */ -#define BM_ENET_EIR_BABT (0x20000000U) /*!< Bit mask for ENET_EIR_BABT. */ -#define BS_ENET_EIR_BABT (1U) /*!< Bit field size in bits for ENET_EIR_BABT. */ - -/*! @brief Read current value of the ENET_EIR_BABT field. */ -#define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT)) - -/*! @brief Format value for bitfield ENET_EIR_BABT. */ -#define BF_ENET_EIR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABT) & BM_ENET_EIR_BABT) - -/*! @brief Set the BABT field to a new value. */ -#define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIR, field BABR[30] (W1C) - * - * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes. - */ -/*@{*/ -#define BP_ENET_EIR_BABR (30U) /*!< Bit position for ENET_EIR_BABR. */ -#define BM_ENET_EIR_BABR (0x40000000U) /*!< Bit mask for ENET_EIR_BABR. */ -#define BS_ENET_EIR_BABR (1U) /*!< Bit field size in bits for ENET_EIR_BABR. */ - -/*! @brief Read current value of the ENET_EIR_BABR field. */ -#define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR)) - -/*! @brief Format value for bitfield ENET_EIR_BABR. */ -#define BF_ENET_EIR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABR) & BM_ENET_EIR_BABR) - -/*! @brief Set the BABR field to a new value. */ -#define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_EIMR - Interrupt Mask Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_EIMR - Interrupt Mask Register (RW) - * - * Reset value: 0x00000000U - * - * EIMR controls which interrupt events are allowed to generate actual - * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR - * and EIMR registers are set, an interrupt is generated. The interrupt signal - * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a - * 0 is written to the EIMR field. - */ -typedef union _hw_enet_eimr -{ - uint32_t U; - struct _hw_enet_eimr_bitfields - { - uint32_t RESERVED0 : 15; /*!< [14:0] */ - uint32_t TS_TIMER : 1; /*!< [15] TS_TIMER Interrupt Mask */ - uint32_t TS_AVAIL : 1; /*!< [16] TS_AVAIL Interrupt Mask */ - uint32_t WAKEUP : 1; /*!< [17] WAKEUP Interrupt Mask */ - uint32_t PLR : 1; /*!< [18] PLR Interrupt Mask */ - uint32_t UN : 1; /*!< [19] UN Interrupt Mask */ - uint32_t RL : 1; /*!< [20] RL Interrupt Mask */ - uint32_t LC : 1; /*!< [21] LC Interrupt Mask */ - uint32_t EBERR : 1; /*!< [22] EBERR Interrupt Mask */ - uint32_t MII : 1; /*!< [23] MII Interrupt Mask */ - uint32_t RXB : 1; /*!< [24] RXB Interrupt Mask */ - uint32_t RXF : 1; /*!< [25] RXF Interrupt Mask */ - uint32_t TXB : 1; /*!< [26] TXB Interrupt Mask */ - uint32_t TXF : 1; /*!< [27] TXF Interrupt Mask */ - uint32_t GRA : 1; /*!< [28] GRA Interrupt Mask */ - uint32_t BABT : 1; /*!< [29] BABT Interrupt Mask */ - uint32_t BABR : 1; /*!< [30] BABR Interrupt Mask */ - uint32_t RESERVED1 : 1; /*!< [31] */ - } B; -} hw_enet_eimr_t; - -/*! - * @name Constants and macros for entire ENET_EIMR register - */ -/*@{*/ -#define HW_ENET_EIMR_ADDR(x) ((x) + 0x8U) - -#define HW_ENET_EIMR(x) (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x)) -#define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U) -#define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v)) -#define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) | (v))) -#define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v))) -#define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_EIMR bitfields - */ - -/*! - * @name Register ENET_EIMR, field TS_TIMER[15] (RW) - * - * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether - * an interrupt condition can generate an interrupt. At every module clock, the - * EIR samples the signal generated by the interrupting source. The corresponding - * EIR TS_TIMER field reflects the state of the interrupt signal even if the - * corresponding EIMR field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_TS_TIMER (15U) /*!< Bit position for ENET_EIMR_TS_TIMER. */ -#define BM_ENET_EIMR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIMR_TS_TIMER. */ -#define BS_ENET_EIMR_TS_TIMER (1U) /*!< Bit field size in bits for ENET_EIMR_TS_TIMER. */ - -/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */ -#define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER)) - -/*! @brief Format value for bitfield ENET_EIMR_TS_TIMER. */ -#define BF_ENET_EIMR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_TIMER) & BM_ENET_EIMR_TS_TIMER) - -/*! @brief Set the TS_TIMER field to a new value. */ -#define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field TS_AVAIL[16] (RW) - * - * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether - * an interrupt condition can generate an interrupt. At every module clock, the - * EIR samples the signal generated by the interrupting source. The corresponding - * EIR TS_AVAIL field reflects the state of the interrupt signal even if the - * corresponding EIMR field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_TS_AVAIL (16U) /*!< Bit position for ENET_EIMR_TS_AVAIL. */ -#define BM_ENET_EIMR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIMR_TS_AVAIL. */ -#define BS_ENET_EIMR_TS_AVAIL (1U) /*!< Bit field size in bits for ENET_EIMR_TS_AVAIL. */ - -/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */ -#define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL)) - -/*! @brief Format value for bitfield ENET_EIMR_TS_AVAIL. */ -#define BF_ENET_EIMR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_AVAIL) & BM_ENET_EIMR_TS_AVAIL) - -/*! @brief Set the TS_AVAIL field to a new value. */ -#define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field WAKEUP[17] (RW) - * - * Corresponds to interrupt source EIR[WAKEUP] register and determines whether - * an interrupt condition can generate an interrupt. At every module clock, the - * EIR samples the signal generated by the interrupting source. The corresponding - * EIR WAKEUP field reflects the state of the interrupt signal even if the - * corresponding EIMR field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_WAKEUP (17U) /*!< Bit position for ENET_EIMR_WAKEUP. */ -#define BM_ENET_EIMR_WAKEUP (0x00020000U) /*!< Bit mask for ENET_EIMR_WAKEUP. */ -#define BS_ENET_EIMR_WAKEUP (1U) /*!< Bit field size in bits for ENET_EIMR_WAKEUP. */ - -/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */ -#define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP)) - -/*! @brief Format value for bitfield ENET_EIMR_WAKEUP. */ -#define BF_ENET_EIMR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_WAKEUP) & BM_ENET_EIMR_WAKEUP) - -/*! @brief Set the WAKEUP field to a new value. */ -#define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field PLR[18] (RW) - * - * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR PLR field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_PLR (18U) /*!< Bit position for ENET_EIMR_PLR. */ -#define BM_ENET_EIMR_PLR (0x00040000U) /*!< Bit mask for ENET_EIMR_PLR. */ -#define BS_ENET_EIMR_PLR (1U) /*!< Bit field size in bits for ENET_EIMR_PLR. */ - -/*! @brief Read current value of the ENET_EIMR_PLR field. */ -#define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR)) - -/*! @brief Format value for bitfield ENET_EIMR_PLR. */ -#define BF_ENET_EIMR_PLR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_PLR) & BM_ENET_EIMR_PLR) - -/*! @brief Set the PLR field to a new value. */ -#define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field UN[19] (RW) - * - * Corresponds to interrupt source EIR[UN] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples the - * signal generated by the interrupting source. The corresponding EIR UN field - * reflects the state of the interrupt signal even if the corresponding EIMR field - * is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_UN (19U) /*!< Bit position for ENET_EIMR_UN. */ -#define BM_ENET_EIMR_UN (0x00080000U) /*!< Bit mask for ENET_EIMR_UN. */ -#define BS_ENET_EIMR_UN (1U) /*!< Bit field size in bits for ENET_EIMR_UN. */ - -/*! @brief Read current value of the ENET_EIMR_UN field. */ -#define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN)) - -/*! @brief Format value for bitfield ENET_EIMR_UN. */ -#define BF_ENET_EIMR_UN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_UN) & BM_ENET_EIMR_UN) - -/*! @brief Set the UN field to a new value. */ -#define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field RL[20] (RW) - * - * Corresponds to interrupt source EIR[RL] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples the - * signal generated by the interrupting source. The corresponding EIR RL field - * reflects the state of the interrupt signal even if the corresponding EIMR field - * is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_RL (20U) /*!< Bit position for ENET_EIMR_RL. */ -#define BM_ENET_EIMR_RL (0x00100000U) /*!< Bit mask for ENET_EIMR_RL. */ -#define BS_ENET_EIMR_RL (1U) /*!< Bit field size in bits for ENET_EIMR_RL. */ - -/*! @brief Read current value of the ENET_EIMR_RL field. */ -#define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL)) - -/*! @brief Format value for bitfield ENET_EIMR_RL. */ -#define BF_ENET_EIMR_RL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RL) & BM_ENET_EIMR_RL) - -/*! @brief Set the RL field to a new value. */ -#define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field LC[21] (RW) - * - * Corresponds to interrupt source EIR[LC] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples the - * signal generated by the interrupting source. The corresponding EIR LC field - * reflects the state of the interrupt signal even if the corresponding EIMR field - * is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_LC (21U) /*!< Bit position for ENET_EIMR_LC. */ -#define BM_ENET_EIMR_LC (0x00200000U) /*!< Bit mask for ENET_EIMR_LC. */ -#define BS_ENET_EIMR_LC (1U) /*!< Bit field size in bits for ENET_EIMR_LC. */ - -/*! @brief Read current value of the ENET_EIMR_LC field. */ -#define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC)) - -/*! @brief Format value for bitfield ENET_EIMR_LC. */ -#define BF_ENET_EIMR_LC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_LC) & BM_ENET_EIMR_LC) - -/*! @brief Set the LC field to a new value. */ -#define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field EBERR[22] (RW) - * - * Corresponds to interrupt source EIR[EBERR] and determines whether an - * interrupt condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR EBERR - * field reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_EBERR (22U) /*!< Bit position for ENET_EIMR_EBERR. */ -#define BM_ENET_EIMR_EBERR (0x00400000U) /*!< Bit mask for ENET_EIMR_EBERR. */ -#define BS_ENET_EIMR_EBERR (1U) /*!< Bit field size in bits for ENET_EIMR_EBERR. */ - -/*! @brief Read current value of the ENET_EIMR_EBERR field. */ -#define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR)) - -/*! @brief Format value for bitfield ENET_EIMR_EBERR. */ -#define BF_ENET_EIMR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_EBERR) & BM_ENET_EIMR_EBERR) - -/*! @brief Set the EBERR field to a new value. */ -#define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field MII[23] (RW) - * - * Corresponds to interrupt source EIR[MII] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR MII field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_MII (23U) /*!< Bit position for ENET_EIMR_MII. */ -#define BM_ENET_EIMR_MII (0x00800000U) /*!< Bit mask for ENET_EIMR_MII. */ -#define BS_ENET_EIMR_MII (1U) /*!< Bit field size in bits for ENET_EIMR_MII. */ - -/*! @brief Read current value of the ENET_EIMR_MII field. */ -#define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII)) - -/*! @brief Format value for bitfield ENET_EIMR_MII. */ -#define BF_ENET_EIMR_MII(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_MII) & BM_ENET_EIMR_MII) - -/*! @brief Set the MII field to a new value. */ -#define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field RXB[24] (RW) - * - * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR RXB field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_RXB (24U) /*!< Bit position for ENET_EIMR_RXB. */ -#define BM_ENET_EIMR_RXB (0x01000000U) /*!< Bit mask for ENET_EIMR_RXB. */ -#define BS_ENET_EIMR_RXB (1U) /*!< Bit field size in bits for ENET_EIMR_RXB. */ - -/*! @brief Read current value of the ENET_EIMR_RXB field. */ -#define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB)) - -/*! @brief Format value for bitfield ENET_EIMR_RXB. */ -#define BF_ENET_EIMR_RXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXB) & BM_ENET_EIMR_RXB) - -/*! @brief Set the RXB field to a new value. */ -#define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field RXF[25] (RW) - * - * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR RXF field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - */ -/*@{*/ -#define BP_ENET_EIMR_RXF (25U) /*!< Bit position for ENET_EIMR_RXF. */ -#define BM_ENET_EIMR_RXF (0x02000000U) /*!< Bit mask for ENET_EIMR_RXF. */ -#define BS_ENET_EIMR_RXF (1U) /*!< Bit field size in bits for ENET_EIMR_RXF. */ - -/*! @brief Read current value of the ENET_EIMR_RXF field. */ -#define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF)) - -/*! @brief Format value for bitfield ENET_EIMR_RXF. */ -#define BF_ENET_EIMR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXF) & BM_ENET_EIMR_RXF) - -/*! @brief Set the RXF field to a new value. */ -#define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field TXB[26] (RW) - * - * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR TXF field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - * - * Values: - * - 0 - The corresponding interrupt source is masked. - * - 1 - The corresponding interrupt source is not masked. - */ -/*@{*/ -#define BP_ENET_EIMR_TXB (26U) /*!< Bit position for ENET_EIMR_TXB. */ -#define BM_ENET_EIMR_TXB (0x04000000U) /*!< Bit mask for ENET_EIMR_TXB. */ -#define BS_ENET_EIMR_TXB (1U) /*!< Bit field size in bits for ENET_EIMR_TXB. */ - -/*! @brief Read current value of the ENET_EIMR_TXB field. */ -#define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB)) - -/*! @brief Format value for bitfield ENET_EIMR_TXB. */ -#define BF_ENET_EIMR_TXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXB) & BM_ENET_EIMR_TXB) - -/*! @brief Set the TXB field to a new value. */ -#define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field TXF[27] (RW) - * - * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR TXF field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - * - * Values: - * - 0 - The corresponding interrupt source is masked. - * - 1 - The corresponding interrupt source is not masked. - */ -/*@{*/ -#define BP_ENET_EIMR_TXF (27U) /*!< Bit position for ENET_EIMR_TXF. */ -#define BM_ENET_EIMR_TXF (0x08000000U) /*!< Bit mask for ENET_EIMR_TXF. */ -#define BS_ENET_EIMR_TXF (1U) /*!< Bit field size in bits for ENET_EIMR_TXF. */ - -/*! @brief Read current value of the ENET_EIMR_TXF field. */ -#define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF)) - -/*! @brief Format value for bitfield ENET_EIMR_TXF. */ -#define BF_ENET_EIMR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXF) & BM_ENET_EIMR_TXF) - -/*! @brief Set the TXF field to a new value. */ -#define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field GRA[28] (RW) - * - * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR GRA field - * reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - * - * Values: - * - 0 - The corresponding interrupt source is masked. - * - 1 - The corresponding interrupt source is not masked. - */ -/*@{*/ -#define BP_ENET_EIMR_GRA (28U) /*!< Bit position for ENET_EIMR_GRA. */ -#define BM_ENET_EIMR_GRA (0x10000000U) /*!< Bit mask for ENET_EIMR_GRA. */ -#define BS_ENET_EIMR_GRA (1U) /*!< Bit field size in bits for ENET_EIMR_GRA. */ - -/*! @brief Read current value of the ENET_EIMR_GRA field. */ -#define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA)) - -/*! @brief Format value for bitfield ENET_EIMR_GRA. */ -#define BF_ENET_EIMR_GRA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_GRA) & BM_ENET_EIMR_GRA) - -/*! @brief Set the GRA field to a new value. */ -#define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field BABT[29] (RW) - * - * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR BABT - * field reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - * - * Values: - * - 0 - The corresponding interrupt source is masked. - * - 1 - The corresponding interrupt source is not masked. - */ -/*@{*/ -#define BP_ENET_EIMR_BABT (29U) /*!< Bit position for ENET_EIMR_BABT. */ -#define BM_ENET_EIMR_BABT (0x20000000U) /*!< Bit mask for ENET_EIMR_BABT. */ -#define BS_ENET_EIMR_BABT (1U) /*!< Bit field size in bits for ENET_EIMR_BABT. */ - -/*! @brief Read current value of the ENET_EIMR_BABT field. */ -#define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT)) - -/*! @brief Format value for bitfield ENET_EIMR_BABT. */ -#define BF_ENET_EIMR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABT) & BM_ENET_EIMR_BABT) - -/*! @brief Set the BABT field to a new value. */ -#define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v)) -/*@}*/ - -/*! - * @name Register ENET_EIMR, field BABR[30] (RW) - * - * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt - * condition can generate an interrupt. At every module clock, the EIR samples - * the signal generated by the interrupting source. The corresponding EIR BABR - * field reflects the state of the interrupt signal even if the corresponding EIMR - * field is cleared. - * - * Values: - * - 0 - The corresponding interrupt source is masked. - * - 1 - The corresponding interrupt source is not masked. - */ -/*@{*/ -#define BP_ENET_EIMR_BABR (30U) /*!< Bit position for ENET_EIMR_BABR. */ -#define BM_ENET_EIMR_BABR (0x40000000U) /*!< Bit mask for ENET_EIMR_BABR. */ -#define BS_ENET_EIMR_BABR (1U) /*!< Bit field size in bits for ENET_EIMR_BABR. */ - -/*! @brief Read current value of the ENET_EIMR_BABR field. */ -#define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR)) - -/*! @brief Format value for bitfield ENET_EIMR_BABR. */ -#define BF_ENET_EIMR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABR) & BM_ENET_EIMR_BABR) - -/*! @brief Set the BABR field to a new value. */ -#define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RDAR - Receive Descriptor Active Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW) - * - * Reset value: 0x00000000U - * - * RDAR is a command register, written by the user, to indicate that the receive - * descriptor ring has been updated, that is, that the driver produced empty - * receive buffers with the empty bit set. - */ -typedef union _hw_enet_rdar -{ - uint32_t U; - struct _hw_enet_rdar_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t RDAR : 1; /*!< [24] Receive Descriptor Active */ - uint32_t RESERVED1 : 7; /*!< [31:25] */ - } B; -} hw_enet_rdar_t; - -/*! - * @name Constants and macros for entire ENET_RDAR register - */ -/*@{*/ -#define HW_ENET_RDAR_ADDR(x) ((x) + 0x10U) - -#define HW_ENET_RDAR(x) (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x)) -#define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U) -#define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v)) -#define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) | (v))) -#define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v))) -#define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RDAR bitfields - */ - -/*! - * @name Register ENET_RDAR, field RDAR[24] (RW) - * - * Always set to 1 when this register is written, regardless of the value - * written. This field is cleared by the MAC device when no additional empty - * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions - * from set to cleared or when ECR[RESET] is set. - */ -/*@{*/ -#define BP_ENET_RDAR_RDAR (24U) /*!< Bit position for ENET_RDAR_RDAR. */ -#define BM_ENET_RDAR_RDAR (0x01000000U) /*!< Bit mask for ENET_RDAR_RDAR. */ -#define BS_ENET_RDAR_RDAR (1U) /*!< Bit field size in bits for ENET_RDAR_RDAR. */ - -/*! @brief Read current value of the ENET_RDAR_RDAR field. */ -#define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR)) - -/*! @brief Format value for bitfield ENET_RDAR_RDAR. */ -#define BF_ENET_RDAR_RDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDAR_RDAR) & BM_ENET_RDAR_RDAR) - -/*! @brief Set the RDAR field to a new value. */ -#define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TDAR - Transmit Descriptor Active Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW) - * - * Reset value: 0x00000000U - * - * The TDAR is a command register that the user writes to indicate that the - * transmit descriptor ring has been updated, that is, that transmit buffers have - * been produced by the driver with the ready bit set in the buffer descriptor. The - * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to - * cleared, or when ECR[RESET] is set. - */ -typedef union _hw_enet_tdar -{ - uint32_t U; - struct _hw_enet_tdar_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t TDAR : 1; /*!< [24] Transmit Descriptor Active */ - uint32_t RESERVED1 : 7; /*!< [31:25] */ - } B; -} hw_enet_tdar_t; - -/*! - * @name Constants and macros for entire ENET_TDAR register - */ -/*@{*/ -#define HW_ENET_TDAR_ADDR(x) ((x) + 0x14U) - -#define HW_ENET_TDAR(x) (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x)) -#define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U) -#define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v)) -#define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) | (v))) -#define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v))) -#define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TDAR bitfields - */ - -/*! - * @name Register ENET_TDAR, field TDAR[24] (RW) - * - * Always set to 1 when this register is written, regardless of the value - * written. This bit is cleared by the MAC device when no additional ready descriptors - * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from - * set to cleared or when ECR[RESET] is set. - */ -/*@{*/ -#define BP_ENET_TDAR_TDAR (24U) /*!< Bit position for ENET_TDAR_TDAR. */ -#define BM_ENET_TDAR_TDAR (0x01000000U) /*!< Bit mask for ENET_TDAR_TDAR. */ -#define BS_ENET_TDAR_TDAR (1U) /*!< Bit field size in bits for ENET_TDAR_TDAR. */ - -/*! @brief Read current value of the ENET_TDAR_TDAR field. */ -#define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR)) - -/*! @brief Format value for bitfield ENET_TDAR_TDAR. */ -#define BF_ENET_TDAR_TDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDAR_TDAR) & BM_ENET_TDAR_TDAR) - -/*! @brief Set the TDAR field to a new value. */ -#define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ECR - Ethernet Control Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ECR - Ethernet Control Register (RW) - * - * Reset value: 0xF0000000U - * - * ECR is a read/write user register, though hardware may also alter fields in - * this register. It controls many of the high level features of the Ethernet MAC, - * including legacy FEC support through the EN1588 field. - */ -typedef union _hw_enet_ecr -{ - uint32_t U; - struct _hw_enet_ecr_bitfields - { - uint32_t RESET : 1; /*!< [0] Ethernet MAC Reset */ - uint32_t ETHEREN : 1; /*!< [1] Ethernet Enable */ - uint32_t MAGICEN : 1; /*!< [2] Magic Packet Detection Enable */ - uint32_t SLEEP : 1; /*!< [3] Sleep Mode Enable */ - uint32_t EN1588 : 1; /*!< [4] EN1588 Enable */ - uint32_t RESERVED0 : 1; /*!< [5] */ - uint32_t DBGEN : 1; /*!< [6] Debug Enable */ - uint32_t STOPEN : 1; /*!< [7] STOPEN Signal Control */ - uint32_t DBSWP : 1; /*!< [8] Descriptor Byte Swapping Enable */ - uint32_t RESERVED1 : 23; /*!< [31:9] */ - } B; -} hw_enet_ecr_t; - -/*! - * @name Constants and macros for entire ENET_ECR register - */ -/*@{*/ -#define HW_ENET_ECR_ADDR(x) ((x) + 0x24U) - -#define HW_ENET_ECR(x) (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x)) -#define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U) -#define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v)) -#define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) | (v))) -#define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v))) -#define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ECR bitfields - */ - -/*! - * @name Register ENET_ECR, field RESET[0] (RW) - * - * When this field is set, it clears the ETHEREN field. - */ -/*@{*/ -#define BP_ENET_ECR_RESET (0U) /*!< Bit position for ENET_ECR_RESET. */ -#define BM_ENET_ECR_RESET (0x00000001U) /*!< Bit mask for ENET_ECR_RESET. */ -#define BS_ENET_ECR_RESET (1U) /*!< Bit field size in bits for ENET_ECR_RESET. */ - -/*! @brief Read current value of the ENET_ECR_RESET field. */ -#define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET)) - -/*! @brief Format value for bitfield ENET_ECR_RESET. */ -#define BF_ENET_ECR_RESET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_RESET) & BM_ENET_ECR_RESET) - -/*! @brief Set the RESET field to a new value. */ -#define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field ETHEREN[1] (RW) - * - * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer - * descriptors for an aborted transmit frame are not updated. The uDMA, buffer - * descriptor, and FIFO control logic are reset, including the buffer descriptor and - * FIFO pointers. Hardware clears this field under the following conditions: RESET - * is set by software An error condition causes the EBERR field to set. ETHEREN - * must be set at the very last step during ENET - * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN - * is cleared to 0 by software then then next time ETHEREN is set, the EIR - * interrupts must cleared to 0 due to previous pending interrupts. - * - * Values: - * - 0 - Reception immediately stops and transmission stops after a bad CRC is - * appended to any currently transmitted frame. - * - 1 - MAC is enabled, and reception and transmission are possible. - */ -/*@{*/ -#define BP_ENET_ECR_ETHEREN (1U) /*!< Bit position for ENET_ECR_ETHEREN. */ -#define BM_ENET_ECR_ETHEREN (0x00000002U) /*!< Bit mask for ENET_ECR_ETHEREN. */ -#define BS_ENET_ECR_ETHEREN (1U) /*!< Bit field size in bits for ENET_ECR_ETHEREN. */ - -/*! @brief Read current value of the ENET_ECR_ETHEREN field. */ -#define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN)) - -/*! @brief Format value for bitfield ENET_ECR_ETHEREN. */ -#define BF_ENET_ECR_ETHEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_ETHEREN) & BM_ENET_ECR_ETHEREN) - -/*! @brief Set the ETHEREN field to a new value. */ -#define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field MAGICEN[2] (RW) - * - * Enables/disables magic packet detection. MAGICEN is relevant only if the - * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables - * sleep mode and magic packet detection. - * - * Values: - * - 0 - Magic detection logic disabled. - * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame - * is detected. - */ -/*@{*/ -#define BP_ENET_ECR_MAGICEN (2U) /*!< Bit position for ENET_ECR_MAGICEN. */ -#define BM_ENET_ECR_MAGICEN (0x00000004U) /*!< Bit mask for ENET_ECR_MAGICEN. */ -#define BS_ENET_ECR_MAGICEN (1U) /*!< Bit field size in bits for ENET_ECR_MAGICEN. */ - -/*! @brief Read current value of the ENET_ECR_MAGICEN field. */ -#define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN)) - -/*! @brief Format value for bitfield ENET_ECR_MAGICEN. */ -#define BF_ENET_ECR_MAGICEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_MAGICEN) & BM_ENET_ECR_MAGICEN) - -/*! @brief Set the MAGICEN field to a new value. */ -#define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field SLEEP[3] (RW) - * - * Values: - * - 0 - Normal operating mode. - * - 1 - Sleep mode. - */ -/*@{*/ -#define BP_ENET_ECR_SLEEP (3U) /*!< Bit position for ENET_ECR_SLEEP. */ -#define BM_ENET_ECR_SLEEP (0x00000008U) /*!< Bit mask for ENET_ECR_SLEEP. */ -#define BS_ENET_ECR_SLEEP (1U) /*!< Bit field size in bits for ENET_ECR_SLEEP. */ - -/*! @brief Read current value of the ENET_ECR_SLEEP field. */ -#define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP)) - -/*! @brief Format value for bitfield ENET_ECR_SLEEP. */ -#define BF_ENET_ECR_SLEEP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_SLEEP) & BM_ENET_ECR_SLEEP) - -/*! @brief Set the SLEEP field to a new value. */ -#define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field EN1588[4] (RW) - * - * Enables enhanced functionality of the MAC. - * - * Values: - * - 0 - Legacy FEC buffer descriptors and functions enabled. - * - 1 - Enhanced frame time-stamping functions enabled. - */ -/*@{*/ -#define BP_ENET_ECR_EN1588 (4U) /*!< Bit position for ENET_ECR_EN1588. */ -#define BM_ENET_ECR_EN1588 (0x00000010U) /*!< Bit mask for ENET_ECR_EN1588. */ -#define BS_ENET_ECR_EN1588 (1U) /*!< Bit field size in bits for ENET_ECR_EN1588. */ - -/*! @brief Read current value of the ENET_ECR_EN1588 field. */ -#define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588)) - -/*! @brief Format value for bitfield ENET_ECR_EN1588. */ -#define BF_ENET_ECR_EN1588(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_EN1588) & BM_ENET_ECR_EN1588) - -/*! @brief Set the EN1588 field to a new value. */ -#define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field DBGEN[6] (RW) - * - * Enables the MAC to enter hardware freeze mode when the device enters debug - * mode. - * - * Values: - * - 0 - MAC continues operation in debug mode. - * - 1 - MAC enters hardware freeze mode when the processor is in debug mode. - */ -/*@{*/ -#define BP_ENET_ECR_DBGEN (6U) /*!< Bit position for ENET_ECR_DBGEN. */ -#define BM_ENET_ECR_DBGEN (0x00000040U) /*!< Bit mask for ENET_ECR_DBGEN. */ -#define BS_ENET_ECR_DBGEN (1U) /*!< Bit field size in bits for ENET_ECR_DBGEN. */ - -/*! @brief Read current value of the ENET_ECR_DBGEN field. */ -#define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN)) - -/*! @brief Format value for bitfield ENET_ECR_DBGEN. */ -#define BF_ENET_ECR_DBGEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBGEN) & BM_ENET_ECR_DBGEN) - -/*! @brief Set the DBGEN field to a new value. */ -#define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field STOPEN[7] (RW) - * - * Controls device behavior in doze mode. In doze mode, if this field is set - * then all the clocks of the ENET assembly are disabled, except the RMII /MII - * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly - * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module - * can still wake the system after receiving a magic packet in stop mode. MAGICEN - * must be set prior to entering sleep/stop mode. - */ -/*@{*/ -#define BP_ENET_ECR_STOPEN (7U) /*!< Bit position for ENET_ECR_STOPEN. */ -#define BM_ENET_ECR_STOPEN (0x00000080U) /*!< Bit mask for ENET_ECR_STOPEN. */ -#define BS_ENET_ECR_STOPEN (1U) /*!< Bit field size in bits for ENET_ECR_STOPEN. */ - -/*! @brief Read current value of the ENET_ECR_STOPEN field. */ -#define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN)) - -/*! @brief Format value for bitfield ENET_ECR_STOPEN. */ -#define BF_ENET_ECR_STOPEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_STOPEN) & BM_ENET_ECR_STOPEN) - -/*! @brief Set the STOPEN field to a new value. */ -#define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ECR, field DBSWP[8] (RW) - * - * Swaps the byte locations of the buffer descriptors. This field must be - * written to 1 after reset. - * - * Values: - * - 0 - The buffer descriptor bytes are not swapped to support big-endian - * devices. - * - 1 - The buffer descriptor bytes are swapped to support little-endian - * devices. - */ -/*@{*/ -#define BP_ENET_ECR_DBSWP (8U) /*!< Bit position for ENET_ECR_DBSWP. */ -#define BM_ENET_ECR_DBSWP (0x00000100U) /*!< Bit mask for ENET_ECR_DBSWP. */ -#define BS_ENET_ECR_DBSWP (1U) /*!< Bit field size in bits for ENET_ECR_DBSWP. */ - -/*! @brief Read current value of the ENET_ECR_DBSWP field. */ -#define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP)) - -/*! @brief Format value for bitfield ENET_ECR_DBSWP. */ -#define BF_ENET_ECR_DBSWP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBSWP) & BM_ENET_ECR_DBSWP) - -/*! @brief Set the DBSWP field to a new value. */ -#define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_MMFR - MII Management Frame Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_MMFR - MII Management Frame Register (RW) - * - * Reset value: 0x00000000U - * - * Writing to MMFR triggers a management frame transaction to the PHY device - * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero - * during a write to MMFR, an MII frame is generated with the data previously written - * to the MMFR. This allows MMFR and MSCR to be programmed in either order if - * MSCR is currently zero. If the MMFR register is written while frame generation is - * in progress, the frame contents are altered. Software must use the EIR[MII] - * interrupt indication to avoid writing to the MMFR register while frame - * generation is in progress. - */ -typedef union _hw_enet_mmfr -{ - uint32_t U; - struct _hw_enet_mmfr_bitfields - { - uint32_t DATA : 16; /*!< [15:0] Management Frame Data */ - uint32_t TA : 2; /*!< [17:16] Turn Around */ - uint32_t RA : 5; /*!< [22:18] Register Address */ - uint32_t PA : 5; /*!< [27:23] PHY Address */ - uint32_t OP : 2; /*!< [29:28] Operation Code */ - uint32_t ST : 2; /*!< [31:30] Start Of Frame Delimiter */ - } B; -} hw_enet_mmfr_t; - -/*! - * @name Constants and macros for entire ENET_MMFR register - */ -/*@{*/ -#define HW_ENET_MMFR_ADDR(x) ((x) + 0x40U) - -#define HW_ENET_MMFR(x) (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x)) -#define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U) -#define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v)) -#define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) | (v))) -#define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v))) -#define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_MMFR bitfields - */ - -/*! - * @name Register ENET_MMFR, field DATA[15:0] (RW) - * - * This is the field for data to be written to or read from the PHY register. - */ -/*@{*/ -#define BP_ENET_MMFR_DATA (0U) /*!< Bit position for ENET_MMFR_DATA. */ -#define BM_ENET_MMFR_DATA (0x0000FFFFU) /*!< Bit mask for ENET_MMFR_DATA. */ -#define BS_ENET_MMFR_DATA (16U) /*!< Bit field size in bits for ENET_MMFR_DATA. */ - -/*! @brief Read current value of the ENET_MMFR_DATA field. */ -#define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA) - -/*! @brief Format value for bitfield ENET_MMFR_DATA. */ -#define BF_ENET_MMFR_DATA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_DATA) & BM_ENET_MMFR_DATA) - -/*! @brief Set the DATA field to a new value. */ -#define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v))) -/*@}*/ - -/*! - * @name Register ENET_MMFR, field TA[17:16] (RW) - * - * This field must be programmed to 10 to generate a valid MII management frame. - */ -/*@{*/ -#define BP_ENET_MMFR_TA (16U) /*!< Bit position for ENET_MMFR_TA. */ -#define BM_ENET_MMFR_TA (0x00030000U) /*!< Bit mask for ENET_MMFR_TA. */ -#define BS_ENET_MMFR_TA (2U) /*!< Bit field size in bits for ENET_MMFR_TA. */ - -/*! @brief Read current value of the ENET_MMFR_TA field. */ -#define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA) - -/*! @brief Format value for bitfield ENET_MMFR_TA. */ -#define BF_ENET_MMFR_TA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_TA) & BM_ENET_MMFR_TA) - -/*! @brief Set the TA field to a new value. */ -#define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v))) -/*@}*/ - -/*! - * @name Register ENET_MMFR, field RA[22:18] (RW) - * - * Specifies one of up to 32 registers within the specified PHY device. - */ -/*@{*/ -#define BP_ENET_MMFR_RA (18U) /*!< Bit position for ENET_MMFR_RA. */ -#define BM_ENET_MMFR_RA (0x007C0000U) /*!< Bit mask for ENET_MMFR_RA. */ -#define BS_ENET_MMFR_RA (5U) /*!< Bit field size in bits for ENET_MMFR_RA. */ - -/*! @brief Read current value of the ENET_MMFR_RA field. */ -#define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA) - -/*! @brief Format value for bitfield ENET_MMFR_RA. */ -#define BF_ENET_MMFR_RA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_RA) & BM_ENET_MMFR_RA) - -/*! @brief Set the RA field to a new value. */ -#define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v))) -/*@}*/ - -/*! - * @name Register ENET_MMFR, field PA[27:23] (RW) - * - * Specifies one of up to 32 attached PHY devices. - */ -/*@{*/ -#define BP_ENET_MMFR_PA (23U) /*!< Bit position for ENET_MMFR_PA. */ -#define BM_ENET_MMFR_PA (0x0F800000U) /*!< Bit mask for ENET_MMFR_PA. */ -#define BS_ENET_MMFR_PA (5U) /*!< Bit field size in bits for ENET_MMFR_PA. */ - -/*! @brief Read current value of the ENET_MMFR_PA field. */ -#define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA) - -/*! @brief Format value for bitfield ENET_MMFR_PA. */ -#define BF_ENET_MMFR_PA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_PA) & BM_ENET_MMFR_PA) - -/*! @brief Set the PA field to a new value. */ -#define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v))) -/*@}*/ - -/*! - * @name Register ENET_MMFR, field OP[29:28] (RW) - * - * Determines the frame operation. - * - * Values: - * - 00 - Write frame operation, but not MII compliant. - * - 01 - Write frame operation for a valid MII management frame. - * - 10 - Read frame operation for a valid MII management frame. - * - 11 - Read frame operation, but not MII compliant. - */ -/*@{*/ -#define BP_ENET_MMFR_OP (28U) /*!< Bit position for ENET_MMFR_OP. */ -#define BM_ENET_MMFR_OP (0x30000000U) /*!< Bit mask for ENET_MMFR_OP. */ -#define BS_ENET_MMFR_OP (2U) /*!< Bit field size in bits for ENET_MMFR_OP. */ - -/*! @brief Read current value of the ENET_MMFR_OP field. */ -#define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP) - -/*! @brief Format value for bitfield ENET_MMFR_OP. */ -#define BF_ENET_MMFR_OP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_OP) & BM_ENET_MMFR_OP) - -/*! @brief Set the OP field to a new value. */ -#define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v))) -/*@}*/ - -/*! - * @name Register ENET_MMFR, field ST[31:30] (RW) - * - * These fields must be programmed to 01 for a valid MII management frame. - */ -/*@{*/ -#define BP_ENET_MMFR_ST (30U) /*!< Bit position for ENET_MMFR_ST. */ -#define BM_ENET_MMFR_ST (0xC0000000U) /*!< Bit mask for ENET_MMFR_ST. */ -#define BS_ENET_MMFR_ST (2U) /*!< Bit field size in bits for ENET_MMFR_ST. */ - -/*! @brief Read current value of the ENET_MMFR_ST field. */ -#define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST) - -/*! @brief Format value for bitfield ENET_MMFR_ST. */ -#define BF_ENET_MMFR_ST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_ST) & BM_ENET_MMFR_ST) - -/*! @brief Set the ST field to a new value. */ -#define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_MSCR - MII Speed Control Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_MSCR - MII Speed Control Register (RW) - * - * Reset value: 0x00000000U - * - * MSCR provides control of the MII clock (MDC pin) frequency and allows a - * preamble drop on the MII management frame. The MII_SPEED field must be programmed - * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be - * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to - * a non-zero value to source a read or write management frame. After the - * management frame is complete, the MSCR register may optionally be cleared to turn - * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED - * changes during operation. This change takes effect following a rising or falling - * edge of MDC. If the internal module clock is 25 MHz, programming this register - * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz - * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for - * MII_SPEED as a function of internal module clock frequency. Programming Examples - * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz - * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz - * 0xD 2.36 MHz - */ -typedef union _hw_enet_mscr -{ - uint32_t U; - struct _hw_enet_mscr_bitfields - { - uint32_t RESERVED0 : 1; /*!< [0] */ - uint32_t MII_SPEED : 6; /*!< [6:1] MII Speed */ - uint32_t DIS_PRE : 1; /*!< [7] Disable Preamble */ - uint32_t HOLDTIME : 3; /*!< [10:8] Hold time On MDIO Output */ - uint32_t RESERVED1 : 21; /*!< [31:11] */ - } B; -} hw_enet_mscr_t; - -/*! - * @name Constants and macros for entire ENET_MSCR register - */ -/*@{*/ -#define HW_ENET_MSCR_ADDR(x) ((x) + 0x44U) - -#define HW_ENET_MSCR(x) (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x)) -#define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U) -#define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v)) -#define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) | (v))) -#define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v))) -#define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_MSCR bitfields - */ - -/*! - * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW) - * - * Controls the frequency of the MII management interface clock (MDC) relative - * to the internal module clock. A value of 0 in this field turns off MDC and - * leaves it in low voltage state. Any non-zero value results in the MDC frequency - * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency - */ -/*@{*/ -#define BP_ENET_MSCR_MII_SPEED (1U) /*!< Bit position for ENET_MSCR_MII_SPEED. */ -#define BM_ENET_MSCR_MII_SPEED (0x0000007EU) /*!< Bit mask for ENET_MSCR_MII_SPEED. */ -#define BS_ENET_MSCR_MII_SPEED (6U) /*!< Bit field size in bits for ENET_MSCR_MII_SPEED. */ - -/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */ -#define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED) - -/*! @brief Format value for bitfield ENET_MSCR_MII_SPEED. */ -#define BF_ENET_MSCR_MII_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_MII_SPEED) & BM_ENET_MSCR_MII_SPEED) - -/*! @brief Set the MII_SPEED field to a new value. */ -#define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v))) -/*@}*/ - -/*! - * @name Register ENET_MSCR, field DIS_PRE[7] (RW) - * - * Enables/disables prepending a preamble to the MII management frame. The MII - * standard allows the preamble to be dropped if the attached PHY devices do not - * require it. - * - * Values: - * - 0 - Preamble enabled. - * - 1 - Preamble (32 ones) is not prepended to the MII management frame. - */ -/*@{*/ -#define BP_ENET_MSCR_DIS_PRE (7U) /*!< Bit position for ENET_MSCR_DIS_PRE. */ -#define BM_ENET_MSCR_DIS_PRE (0x00000080U) /*!< Bit mask for ENET_MSCR_DIS_PRE. */ -#define BS_ENET_MSCR_DIS_PRE (1U) /*!< Bit field size in bits for ENET_MSCR_DIS_PRE. */ - -/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */ -#define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE)) - -/*! @brief Format value for bitfield ENET_MSCR_DIS_PRE. */ -#define BF_ENET_MSCR_DIS_PRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_DIS_PRE) & BM_ENET_MSCR_DIS_PRE) - -/*! @brief Set the DIS_PRE field to a new value. */ -#define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW) - * - * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO - * output. Depending on the host bus frequency, the setting may need to be - * increased. - * - * Values: - * - 000 - 1 internal module clock cycle - * - 001 - 2 internal module clock cycles - * - 010 - 3 internal module clock cycles - * - 111 - 8 internal module clock cycles - */ -/*@{*/ -#define BP_ENET_MSCR_HOLDTIME (8U) /*!< Bit position for ENET_MSCR_HOLDTIME. */ -#define BM_ENET_MSCR_HOLDTIME (0x00000700U) /*!< Bit mask for ENET_MSCR_HOLDTIME. */ -#define BS_ENET_MSCR_HOLDTIME (3U) /*!< Bit field size in bits for ENET_MSCR_HOLDTIME. */ - -/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */ -#define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME) - -/*! @brief Format value for bitfield ENET_MSCR_HOLDTIME. */ -#define BF_ENET_MSCR_HOLDTIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_HOLDTIME) & BM_ENET_MSCR_HOLDTIME) - -/*! @brief Set the HOLDTIME field to a new value. */ -#define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_MIBC - MIB Control Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_MIBC - MIB Control Register (RW) - * - * Reset value: 0xC0000000U - * - * MIBC is a read/write register controlling and observing the state of the MIB - * block. Access this register to disable the MIB block operation or clear the - * MIB counters. The MIB_DIS field resets to 1. - */ -typedef union _hw_enet_mibc -{ - uint32_t U; - struct _hw_enet_mibc_bitfields - { - uint32_t RESERVED0 : 29; /*!< [28:0] */ - uint32_t MIB_CLEAR : 1; /*!< [29] MIB Clear */ - uint32_t MIB_IDLE : 1; /*!< [30] MIB Idle */ - uint32_t MIB_DIS : 1; /*!< [31] Disable MIB Logic */ - } B; -} hw_enet_mibc_t; - -/*! - * @name Constants and macros for entire ENET_MIBC register - */ -/*@{*/ -#define HW_ENET_MIBC_ADDR(x) ((x) + 0x64U) - -#define HW_ENET_MIBC(x) (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x)) -#define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U) -#define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v)) -#define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) | (v))) -#define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v))) -#define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_MIBC bitfields - */ - -/*! - * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW) - * - * If set, all statistics counters are reset to 0. This field is not - * self-clearing. To clear the MIB counters set and then clear the field. - */ -/*@{*/ -#define BP_ENET_MIBC_MIB_CLEAR (29U) /*!< Bit position for ENET_MIBC_MIB_CLEAR. */ -#define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) /*!< Bit mask for ENET_MIBC_MIB_CLEAR. */ -#define BS_ENET_MIBC_MIB_CLEAR (1U) /*!< Bit field size in bits for ENET_MIBC_MIB_CLEAR. */ - -/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */ -#define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR)) - -/*! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR. */ -#define BF_ENET_MIBC_MIB_CLEAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_CLEAR) & BM_ENET_MIBC_MIB_CLEAR) - -/*! @brief Set the MIB_CLEAR field to a new value. */ -#define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v)) -/*@}*/ - -/*! - * @name Register ENET_MIBC, field MIB_IDLE[30] (RO) - * - * If this status field is set, the MIB block is not currently updating any MIB - * counters. - */ -/*@{*/ -#define BP_ENET_MIBC_MIB_IDLE (30U) /*!< Bit position for ENET_MIBC_MIB_IDLE. */ -#define BM_ENET_MIBC_MIB_IDLE (0x40000000U) /*!< Bit mask for ENET_MIBC_MIB_IDLE. */ -#define BS_ENET_MIBC_MIB_IDLE (1U) /*!< Bit field size in bits for ENET_MIBC_MIB_IDLE. */ - -/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */ -#define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE)) -/*@}*/ - -/*! - * @name Register ENET_MIBC, field MIB_DIS[31] (RW) - * - * If this control field is set, the MIB logic halts and does not update any MIB - * counters. - */ -/*@{*/ -#define BP_ENET_MIBC_MIB_DIS (31U) /*!< Bit position for ENET_MIBC_MIB_DIS. */ -#define BM_ENET_MIBC_MIB_DIS (0x80000000U) /*!< Bit mask for ENET_MIBC_MIB_DIS. */ -#define BS_ENET_MIBC_MIB_DIS (1U) /*!< Bit field size in bits for ENET_MIBC_MIB_DIS. */ - -/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */ -#define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS)) - -/*! @brief Format value for bitfield ENET_MIBC_MIB_DIS. */ -#define BF_ENET_MIBC_MIB_DIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_DIS) & BM_ENET_MIBC_MIB_DIS) - -/*! @brief Set the MIB_DIS field to a new value. */ -#define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RCR - Receive Control Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RCR - Receive Control Register (RW) - * - * Reset value: 0x05EE0001U - */ -typedef union _hw_enet_rcr -{ - uint32_t U; - struct _hw_enet_rcr_bitfields - { - uint32_t LOOP : 1; /*!< [0] Internal Loopback */ - uint32_t DRT : 1; /*!< [1] Disable Receive On Transmit */ - uint32_t MII_MODE : 1; /*!< [2] Media Independent Interface Mode */ - uint32_t PROM : 1; /*!< [3] Promiscuous Mode */ - uint32_t BC_REJ : 1; /*!< [4] Broadcast Frame Reject */ - uint32_t FCE : 1; /*!< [5] Flow Control Enable */ - uint32_t RESERVED0 : 2; /*!< [7:6] */ - uint32_t RMII_MODE : 1; /*!< [8] RMII Mode Enable */ - uint32_t RMII_10T : 1; /*!< [9] */ - uint32_t RESERVED1 : 2; /*!< [11:10] */ - uint32_t PADEN : 1; /*!< [12] Enable Frame Padding Remove On Receive - * */ - uint32_t PAUFWD : 1; /*!< [13] Terminate/Forward Pause Frames */ - uint32_t CRCFWD : 1; /*!< [14] Terminate/Forward Received CRC */ - uint32_t CFEN : 1; /*!< [15] MAC Control Frame Enable */ - uint32_t MAX_FL : 14; /*!< [29:16] Maximum Frame Length */ - uint32_t NLC : 1; /*!< [30] Payload Length Check Disable */ - uint32_t GRS : 1; /*!< [31] Graceful Receive Stopped */ - } B; -} hw_enet_rcr_t; - -/*! - * @name Constants and macros for entire ENET_RCR register - */ -/*@{*/ -#define HW_ENET_RCR_ADDR(x) ((x) + 0x84U) - -#define HW_ENET_RCR(x) (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x)) -#define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U) -#define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v)) -#define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) | (v))) -#define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v))) -#define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RCR bitfields - */ - -/*! - * @name Register ENET_RCR, field LOOP[0] (RW) - * - * This is an MII internal loopback, therefore MII_MODE must be written to 1 and - * RMII_MODE must be written to 0. - * - * Values: - * - 0 - Loopback disabled. - * - 1 - Transmitted frames are looped back internal to the device and transmit - * MII output signals are not asserted. DRT must be cleared. - */ -/*@{*/ -#define BP_ENET_RCR_LOOP (0U) /*!< Bit position for ENET_RCR_LOOP. */ -#define BM_ENET_RCR_LOOP (0x00000001U) /*!< Bit mask for ENET_RCR_LOOP. */ -#define BS_ENET_RCR_LOOP (1U) /*!< Bit field size in bits for ENET_RCR_LOOP. */ - -/*! @brief Read current value of the ENET_RCR_LOOP field. */ -#define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP)) - -/*! @brief Format value for bitfield ENET_RCR_LOOP. */ -#define BF_ENET_RCR_LOOP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_LOOP) & BM_ENET_RCR_LOOP) - -/*! @brief Set the LOOP field to a new value. */ -#define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field DRT[1] (RW) - * - * Values: - * - 0 - Receive path operates independently of transmit. Used for full-duplex - * or to monitor transmit activity in half-duplex mode. - * - 1 - Disable reception of frames while transmitting. Normally used for - * half-duplex mode. - */ -/*@{*/ -#define BP_ENET_RCR_DRT (1U) /*!< Bit position for ENET_RCR_DRT. */ -#define BM_ENET_RCR_DRT (0x00000002U) /*!< Bit mask for ENET_RCR_DRT. */ -#define BS_ENET_RCR_DRT (1U) /*!< Bit field size in bits for ENET_RCR_DRT. */ - -/*! @brief Read current value of the ENET_RCR_DRT field. */ -#define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT)) - -/*! @brief Format value for bitfield ENET_RCR_DRT. */ -#define BF_ENET_RCR_DRT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_DRT) & BM_ENET_RCR_DRT) - -/*! @brief Set the DRT field to a new value. */ -#define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field MII_MODE[2] (RW) - * - * This field must always be set. - * - * Values: - * - 0 - Reserved. - * - 1 - MII or RMII mode, as indicated by the RMII_MODE field. - */ -/*@{*/ -#define BP_ENET_RCR_MII_MODE (2U) /*!< Bit position for ENET_RCR_MII_MODE. */ -#define BM_ENET_RCR_MII_MODE (0x00000004U) /*!< Bit mask for ENET_RCR_MII_MODE. */ -#define BS_ENET_RCR_MII_MODE (1U) /*!< Bit field size in bits for ENET_RCR_MII_MODE. */ - -/*! @brief Read current value of the ENET_RCR_MII_MODE field. */ -#define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE)) - -/*! @brief Format value for bitfield ENET_RCR_MII_MODE. */ -#define BF_ENET_RCR_MII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MII_MODE) & BM_ENET_RCR_MII_MODE) - -/*! @brief Set the MII_MODE field to a new value. */ -#define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field PROM[3] (RW) - * - * All frames are accepted regardless of address matching. - * - * Values: - * - 0 - Disabled. - * - 1 - Enabled. - */ -/*@{*/ -#define BP_ENET_RCR_PROM (3U) /*!< Bit position for ENET_RCR_PROM. */ -#define BM_ENET_RCR_PROM (0x00000008U) /*!< Bit mask for ENET_RCR_PROM. */ -#define BS_ENET_RCR_PROM (1U) /*!< Bit field size in bits for ENET_RCR_PROM. */ - -/*! @brief Read current value of the ENET_RCR_PROM field. */ -#define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM)) - -/*! @brief Format value for bitfield ENET_RCR_PROM. */ -#define BF_ENET_RCR_PROM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PROM) & BM_ENET_RCR_PROM) - -/*! @brief Set the PROM field to a new value. */ -#define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field BC_REJ[4] (RW) - * - * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are - * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with - * broadcast DA are accepted and the MISS (M) is set in the receive buffer - * descriptor. - */ -/*@{*/ -#define BP_ENET_RCR_BC_REJ (4U) /*!< Bit position for ENET_RCR_BC_REJ. */ -#define BM_ENET_RCR_BC_REJ (0x00000010U) /*!< Bit mask for ENET_RCR_BC_REJ. */ -#define BS_ENET_RCR_BC_REJ (1U) /*!< Bit field size in bits for ENET_RCR_BC_REJ. */ - -/*! @brief Read current value of the ENET_RCR_BC_REJ field. */ -#define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ)) - -/*! @brief Format value for bitfield ENET_RCR_BC_REJ. */ -#define BF_ENET_RCR_BC_REJ(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_BC_REJ) & BM_ENET_RCR_BC_REJ) - -/*! @brief Set the BC_REJ field to a new value. */ -#define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field FCE[5] (RW) - * - * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the - * transmitter stops transmitting data frames for a given duration. - */ -/*@{*/ -#define BP_ENET_RCR_FCE (5U) /*!< Bit position for ENET_RCR_FCE. */ -#define BM_ENET_RCR_FCE (0x00000020U) /*!< Bit mask for ENET_RCR_FCE. */ -#define BS_ENET_RCR_FCE (1U) /*!< Bit field size in bits for ENET_RCR_FCE. */ - -/*! @brief Read current value of the ENET_RCR_FCE field. */ -#define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE)) - -/*! @brief Format value for bitfield ENET_RCR_FCE. */ -#define BF_ENET_RCR_FCE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_FCE) & BM_ENET_RCR_FCE) - -/*! @brief Set the FCE field to a new value. */ -#define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field RMII_MODE[8] (RW) - * - * Specifies whether the MAC is configured for MII mode or RMII operation . - * - * Values: - * - 0 - MAC configured for MII mode. - * - 1 - MAC configured for RMII operation. - */ -/*@{*/ -#define BP_ENET_RCR_RMII_MODE (8U) /*!< Bit position for ENET_RCR_RMII_MODE. */ -#define BM_ENET_RCR_RMII_MODE (0x00000100U) /*!< Bit mask for ENET_RCR_RMII_MODE. */ -#define BS_ENET_RCR_RMII_MODE (1U) /*!< Bit field size in bits for ENET_RCR_RMII_MODE. */ - -/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */ -#define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE)) - -/*! @brief Format value for bitfield ENET_RCR_RMII_MODE. */ -#define BF_ENET_RCR_RMII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_MODE) & BM_ENET_RCR_RMII_MODE) - -/*! @brief Set the RMII_MODE field to a new value. */ -#define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field RMII_10T[9] (RW) - * - * Enables 10-Mbps mode of the RMII . - * - * Values: - * - 0 - 100 Mbps operation. - * - 1 - 10 Mbps operation. - */ -/*@{*/ -#define BP_ENET_RCR_RMII_10T (9U) /*!< Bit position for ENET_RCR_RMII_10T. */ -#define BM_ENET_RCR_RMII_10T (0x00000200U) /*!< Bit mask for ENET_RCR_RMII_10T. */ -#define BS_ENET_RCR_RMII_10T (1U) /*!< Bit field size in bits for ENET_RCR_RMII_10T. */ - -/*! @brief Read current value of the ENET_RCR_RMII_10T field. */ -#define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T)) - -/*! @brief Format value for bitfield ENET_RCR_RMII_10T. */ -#define BF_ENET_RCR_RMII_10T(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_10T) & BM_ENET_RCR_RMII_10T) - -/*! @brief Set the RMII_10T field to a new value. */ -#define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field PADEN[12] (RW) - * - * Specifies whether the MAC removes padding from received frames. - * - * Values: - * - 0 - No padding is removed on receive by the MAC. - * - 1 - Padding is removed from received frames. - */ -/*@{*/ -#define BP_ENET_RCR_PADEN (12U) /*!< Bit position for ENET_RCR_PADEN. */ -#define BM_ENET_RCR_PADEN (0x00001000U) /*!< Bit mask for ENET_RCR_PADEN. */ -#define BS_ENET_RCR_PADEN (1U) /*!< Bit field size in bits for ENET_RCR_PADEN. */ - -/*! @brief Read current value of the ENET_RCR_PADEN field. */ -#define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN)) - -/*! @brief Format value for bitfield ENET_RCR_PADEN. */ -#define BF_ENET_RCR_PADEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PADEN) & BM_ENET_RCR_PADEN) - -/*! @brief Set the PADEN field to a new value. */ -#define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field PAUFWD[13] (RW) - * - * Specifies whether pause frames are terminated or forwarded. - * - * Values: - * - 0 - Pause frames are terminated and discarded in the MAC. - * - 1 - Pause frames are forwarded to the user application. - */ -/*@{*/ -#define BP_ENET_RCR_PAUFWD (13U) /*!< Bit position for ENET_RCR_PAUFWD. */ -#define BM_ENET_RCR_PAUFWD (0x00002000U) /*!< Bit mask for ENET_RCR_PAUFWD. */ -#define BS_ENET_RCR_PAUFWD (1U) /*!< Bit field size in bits for ENET_RCR_PAUFWD. */ - -/*! @brief Read current value of the ENET_RCR_PAUFWD field. */ -#define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD)) - -/*! @brief Format value for bitfield ENET_RCR_PAUFWD. */ -#define BF_ENET_RCR_PAUFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PAUFWD) & BM_ENET_RCR_PAUFWD) - -/*! @brief Set the PAUFWD field to a new value. */ -#define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field CRCFWD[14] (RW) - * - * Specifies whether the CRC field of received frames is transmitted or - * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC - * field is checked and always terminated and removed. - * - * Values: - * - 0 - The CRC field of received frames is transmitted to the user application. - * - 1 - The CRC field is stripped from the frame. - */ -/*@{*/ -#define BP_ENET_RCR_CRCFWD (14U) /*!< Bit position for ENET_RCR_CRCFWD. */ -#define BM_ENET_RCR_CRCFWD (0x00004000U) /*!< Bit mask for ENET_RCR_CRCFWD. */ -#define BS_ENET_RCR_CRCFWD (1U) /*!< Bit field size in bits for ENET_RCR_CRCFWD. */ - -/*! @brief Read current value of the ENET_RCR_CRCFWD field. */ -#define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD)) - -/*! @brief Format value for bitfield ENET_RCR_CRCFWD. */ -#define BF_ENET_RCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CRCFWD) & BM_ENET_RCR_CRCFWD) - -/*! @brief Set the CRCFWD field to a new value. */ -#define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field CFEN[15] (RW) - * - * Enables/disables the MAC control frame. - * - * Values: - * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are - * accepted and forwarded to the client interface. - * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are - * silently discarded. - */ -/*@{*/ -#define BP_ENET_RCR_CFEN (15U) /*!< Bit position for ENET_RCR_CFEN. */ -#define BM_ENET_RCR_CFEN (0x00008000U) /*!< Bit mask for ENET_RCR_CFEN. */ -#define BS_ENET_RCR_CFEN (1U) /*!< Bit field size in bits for ENET_RCR_CFEN. */ - -/*! @brief Read current value of the ENET_RCR_CFEN field. */ -#define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN)) - -/*! @brief Format value for bitfield ENET_RCR_CFEN. */ -#define BF_ENET_RCR_CFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CFEN) & BM_ENET_RCR_CFEN) - -/*! @brief Set the CFEN field to a new value. */ -#define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field MAX_FL[29:16] (RW) - * - * Resets to decimal 1518. Length is measured starting at DA and includes the - * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT - * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt - * to occur and set the LG field in the end of frame receive buffer descriptor. - * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are - * supported. - */ -/*@{*/ -#define BP_ENET_RCR_MAX_FL (16U) /*!< Bit position for ENET_RCR_MAX_FL. */ -#define BM_ENET_RCR_MAX_FL (0x3FFF0000U) /*!< Bit mask for ENET_RCR_MAX_FL. */ -#define BS_ENET_RCR_MAX_FL (14U) /*!< Bit field size in bits for ENET_RCR_MAX_FL. */ - -/*! @brief Read current value of the ENET_RCR_MAX_FL field. */ -#define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL) - -/*! @brief Format value for bitfield ENET_RCR_MAX_FL. */ -#define BF_ENET_RCR_MAX_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MAX_FL) & BM_ENET_RCR_MAX_FL) - -/*! @brief Set the MAX_FL field to a new value. */ -#define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v))) -/*@}*/ - -/*! - * @name Register ENET_RCR, field NLC[30] (RW) - * - * Enables/disables a payload length check. - * - * Values: - * - 0 - The payload length check is disabled. - * - 1 - The core checks the frame's payload length with the frame length/type - * field. Errors are indicated in the EIR[PLC] field. - */ -/*@{*/ -#define BP_ENET_RCR_NLC (30U) /*!< Bit position for ENET_RCR_NLC. */ -#define BM_ENET_RCR_NLC (0x40000000U) /*!< Bit mask for ENET_RCR_NLC. */ -#define BS_ENET_RCR_NLC (1U) /*!< Bit field size in bits for ENET_RCR_NLC. */ - -/*! @brief Read current value of the ENET_RCR_NLC field. */ -#define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC)) - -/*! @brief Format value for bitfield ENET_RCR_NLC. */ -#define BF_ENET_RCR_NLC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_NLC) & BM_ENET_RCR_NLC) - -/*! @brief Set the NLC field to a new value. */ -#define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RCR, field GRS[31] (RO) - * - * Read-only status indicating that the MAC receive datapath is stopped. - */ -/*@{*/ -#define BP_ENET_RCR_GRS (31U) /*!< Bit position for ENET_RCR_GRS. */ -#define BM_ENET_RCR_GRS (0x80000000U) /*!< Bit mask for ENET_RCR_GRS. */ -#define BS_ENET_RCR_GRS (1U) /*!< Bit field size in bits for ENET_RCR_GRS. */ - -/*! @brief Read current value of the ENET_RCR_GRS field. */ -#define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TCR - Transmit Control Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TCR - Transmit Control Register (RW) - * - * Reset value: 0x00000000U - * - * TCR is read/write and configures the transmit block. This register is cleared - * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared. - */ -typedef union _hw_enet_tcr -{ - uint32_t U; - struct _hw_enet_tcr_bitfields - { - uint32_t GTS : 1; /*!< [0] Graceful Transmit Stop */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t FDEN : 1; /*!< [2] Full-Duplex Enable */ - uint32_t TFC_PAUSE : 1; /*!< [3] Transmit Frame Control Pause */ - uint32_t RFC_PAUSE : 1; /*!< [4] Receive Frame Control Pause */ - uint32_t ADDSEL : 3; /*!< [7:5] Source MAC Address Select On Transmit - * */ - uint32_t ADDINS : 1; /*!< [8] Set MAC Address On Transmit */ - uint32_t CRCFWD : 1; /*!< [9] Forward Frame From Application With CRC - * */ - uint32_t RESERVED1 : 22; /*!< [31:10] */ - } B; -} hw_enet_tcr_t; - -/*! - * @name Constants and macros for entire ENET_TCR register - */ -/*@{*/ -#define HW_ENET_TCR_ADDR(x) ((x) + 0xC4U) - -#define HW_ENET_TCR(x) (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x)) -#define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U) -#define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v)) -#define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) | (v))) -#define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v))) -#define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TCR bitfields - */ - -/*! - * @name Register ENET_TCR, field GTS[0] (RW) - * - * When this field is set, MAC stops transmission after any frame currently - * transmitted is complete and EIR[GRA] is set. If frame transmission is not - * currently underway, the GRA interrupt is asserted immediately. After transmission - * finishes, clear GTS to restart. The next frame in the transmit FIFO is then - * transmitted. If an early collision occurs during transmission when GTS is set, - * transmission stops after the collision. The frame is transmitted again after GTS is - * cleared. There may be old frames in the transmit FIFO that transmit when GTS - * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt. - */ -/*@{*/ -#define BP_ENET_TCR_GTS (0U) /*!< Bit position for ENET_TCR_GTS. */ -#define BM_ENET_TCR_GTS (0x00000001U) /*!< Bit mask for ENET_TCR_GTS. */ -#define BS_ENET_TCR_GTS (1U) /*!< Bit field size in bits for ENET_TCR_GTS. */ - -/*! @brief Read current value of the ENET_TCR_GTS field. */ -#define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS)) - -/*! @brief Format value for bitfield ENET_TCR_GTS. */ -#define BF_ENET_TCR_GTS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_GTS) & BM_ENET_TCR_GTS) - -/*! @brief Set the GTS field to a new value. */ -#define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TCR, field FDEN[2] (RW) - * - * If this field is set, frames transmit independent of carrier sense and - * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared. - */ -/*@{*/ -#define BP_ENET_TCR_FDEN (2U) /*!< Bit position for ENET_TCR_FDEN. */ -#define BM_ENET_TCR_FDEN (0x00000004U) /*!< Bit mask for ENET_TCR_FDEN. */ -#define BS_ENET_TCR_FDEN (1U) /*!< Bit field size in bits for ENET_TCR_FDEN. */ - -/*! @brief Read current value of the ENET_TCR_FDEN field. */ -#define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN)) - -/*! @brief Format value for bitfield ENET_TCR_FDEN. */ -#define BF_ENET_TCR_FDEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_FDEN) & BM_ENET_TCR_FDEN) - -/*! @brief Set the FDEN field to a new value. */ -#define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TCR, field TFC_PAUSE[3] (RW) - * - * Pauses frame transmission. When this field is set, EIR[GRA] is set. With - * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame. - * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the - * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, - * the MAC may continue transmitting a MAC control PAUSE frame. - * - * Values: - * - 0 - No PAUSE frame transmitted. - * - 1 - The MAC stops transmission of data frames after the current - * transmission is complete. - */ -/*@{*/ -#define BP_ENET_TCR_TFC_PAUSE (3U) /*!< Bit position for ENET_TCR_TFC_PAUSE. */ -#define BM_ENET_TCR_TFC_PAUSE (0x00000008U) /*!< Bit mask for ENET_TCR_TFC_PAUSE. */ -#define BS_ENET_TCR_TFC_PAUSE (1U) /*!< Bit field size in bits for ENET_TCR_TFC_PAUSE. */ - -/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */ -#define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE)) - -/*! @brief Format value for bitfield ENET_TCR_TFC_PAUSE. */ -#define BF_ENET_TCR_TFC_PAUSE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_TFC_PAUSE) & BM_ENET_TCR_TFC_PAUSE) - -/*! @brief Set the TFC_PAUSE field to a new value. */ -#define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TCR, field RFC_PAUSE[4] (RO) - * - * This status field is set when a full-duplex flow control pause frame is - * received and the transmitter pauses for the duration defined in this pause frame. - * This field automatically clears when the pause duration is complete. - */ -/*@{*/ -#define BP_ENET_TCR_RFC_PAUSE (4U) /*!< Bit position for ENET_TCR_RFC_PAUSE. */ -#define BM_ENET_TCR_RFC_PAUSE (0x00000010U) /*!< Bit mask for ENET_TCR_RFC_PAUSE. */ -#define BS_ENET_TCR_RFC_PAUSE (1U) /*!< Bit field size in bits for ENET_TCR_RFC_PAUSE. */ - -/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */ -#define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE)) -/*@}*/ - -/*! - * @name Register ENET_TCR, field ADDSEL[7:5] (RW) - * - * If ADDINS is set, indicates the MAC address that overwrites the source MAC - * address. - * - * Values: - * - 000 - Node MAC address programmed on PADDR1/2 registers. - * - 100 - Reserved. - * - 101 - Reserved. - * - 110 - Reserved. - */ -/*@{*/ -#define BP_ENET_TCR_ADDSEL (5U) /*!< Bit position for ENET_TCR_ADDSEL. */ -#define BM_ENET_TCR_ADDSEL (0x000000E0U) /*!< Bit mask for ENET_TCR_ADDSEL. */ -#define BS_ENET_TCR_ADDSEL (3U) /*!< Bit field size in bits for ENET_TCR_ADDSEL. */ - -/*! @brief Read current value of the ENET_TCR_ADDSEL field. */ -#define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL) - -/*! @brief Format value for bitfield ENET_TCR_ADDSEL. */ -#define BF_ENET_TCR_ADDSEL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDSEL) & BM_ENET_TCR_ADDSEL) - -/*! @brief Set the ADDSEL field to a new value. */ -#define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v))) -/*@}*/ - -/*! - * @name Register ENET_TCR, field ADDINS[8] (RW) - * - * Values: - * - 0 - The source MAC address is not modified by the MAC. - * - 1 - The MAC overwrites the source MAC address with the programmed MAC - * address according to ADDSEL. - */ -/*@{*/ -#define BP_ENET_TCR_ADDINS (8U) /*!< Bit position for ENET_TCR_ADDINS. */ -#define BM_ENET_TCR_ADDINS (0x00000100U) /*!< Bit mask for ENET_TCR_ADDINS. */ -#define BS_ENET_TCR_ADDINS (1U) /*!< Bit field size in bits for ENET_TCR_ADDINS. */ - -/*! @brief Read current value of the ENET_TCR_ADDINS field. */ -#define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS)) - -/*! @brief Format value for bitfield ENET_TCR_ADDINS. */ -#define BF_ENET_TCR_ADDINS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDINS) & BM_ENET_TCR_ADDINS) - -/*! @brief Set the ADDINS field to a new value. */ -#define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TCR, field CRCFWD[9] (RW) - * - * Values: - * - 0 - TxBD[TC] controls whether the frame has a CRC from the application. - * - 1 - The transmitter does not append any CRC to transmitted frames, as it is - * expecting a frame with CRC from the application. - */ -/*@{*/ -#define BP_ENET_TCR_CRCFWD (9U) /*!< Bit position for ENET_TCR_CRCFWD. */ -#define BM_ENET_TCR_CRCFWD (0x00000200U) /*!< Bit mask for ENET_TCR_CRCFWD. */ -#define BS_ENET_TCR_CRCFWD (1U) /*!< Bit field size in bits for ENET_TCR_CRCFWD. */ - -/*! @brief Read current value of the ENET_TCR_CRCFWD field. */ -#define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD)) - -/*! @brief Format value for bitfield ENET_TCR_CRCFWD. */ -#define BF_ENET_TCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_CRCFWD) & BM_ENET_TCR_CRCFWD) - -/*! @brief Set the CRCFWD field to a new value. */ -#define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_PALR - Physical Address Lower Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_PALR - Physical Address Lower Register (RW) - * - * Reset value: 0x00000000U - * - * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used - * in the address recognition process to compare with the destination address - * (DA) field of receive frames with an individual DA. In addition, this register - * is used in bytes 0 through 3 of the six-byte source address field when - * transmitting PAUSE frames. This register is not reset and you must initialize it. - */ -typedef union _hw_enet_palr -{ - uint32_t U; - struct _hw_enet_palr_bitfields - { - uint32_t PADDR1 : 32; /*!< [31:0] Pause Address */ - } B; -} hw_enet_palr_t; - -/*! - * @name Constants and macros for entire ENET_PALR register - */ -/*@{*/ -#define HW_ENET_PALR_ADDR(x) ((x) + 0xE4U) - -#define HW_ENET_PALR(x) (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x)) -#define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U) -#define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v)) -#define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) | (v))) -#define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v))) -#define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_PALR bitfields - */ - -/*! - * @name Register ENET_PALR, field PADDR1[31:0] (RW) - * - * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the - * 6-byte individual address are used for exact match and the source address - * field in PAUSE frames. - */ -/*@{*/ -#define BP_ENET_PALR_PADDR1 (0U) /*!< Bit position for ENET_PALR_PADDR1. */ -#define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) /*!< Bit mask for ENET_PALR_PADDR1. */ -#define BS_ENET_PALR_PADDR1 (32U) /*!< Bit field size in bits for ENET_PALR_PADDR1. */ - -/*! @brief Read current value of the ENET_PALR_PADDR1 field. */ -#define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U) - -/*! @brief Format value for bitfield ENET_PALR_PADDR1. */ -#define BF_ENET_PALR_PADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PALR_PADDR1) & BM_ENET_PALR_PADDR1) - -/*! @brief Set the PADDR1 field to a new value. */ -#define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_PAUR - Physical Address Upper Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_PAUR - Physical Address Upper Register (RW) - * - * Reset value: 0x00008808U - * - * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in - * the address recognition process to compare with the destination address (DA) - * field of receive frames with an individual DA. In addition, this register is - * used in bytes 4 and 5 of the six-byte source address field when transmitting - * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for - * transmission of PAUSE frames. The upper 16 bits of this register are not reset and - * you must initialize it. - */ -typedef union _hw_enet_paur -{ - uint32_t U; - struct _hw_enet_paur_bitfields - { - uint32_t TYPE : 16; /*!< [15:0] Type Field In PAUSE Frames */ - uint32_t PADDR2 : 16; /*!< [31:16] */ - } B; -} hw_enet_paur_t; - -/*! - * @name Constants and macros for entire ENET_PAUR register - */ -/*@{*/ -#define HW_ENET_PAUR_ADDR(x) ((x) + 0xE8U) - -#define HW_ENET_PAUR(x) (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x)) -#define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U) -#define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v)) -#define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) | (v))) -#define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v))) -#define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_PAUR bitfields - */ - -/*! - * @name Register ENET_PAUR, field TYPE[15:0] (RO) - * - * These fields have a constant value of 0x8808. - */ -/*@{*/ -#define BP_ENET_PAUR_TYPE (0U) /*!< Bit position for ENET_PAUR_TYPE. */ -#define BM_ENET_PAUR_TYPE (0x0000FFFFU) /*!< Bit mask for ENET_PAUR_TYPE. */ -#define BS_ENET_PAUR_TYPE (16U) /*!< Bit field size in bits for ENET_PAUR_TYPE. */ - -/*! @brief Read current value of the ENET_PAUR_TYPE field. */ -#define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE) -/*@}*/ - -/*! - * @name Register ENET_PAUR, field PADDR2[31:16] (RW) - * - * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used - * for exact match, and the source address field in PAUSE frames. - */ -/*@{*/ -#define BP_ENET_PAUR_PADDR2 (16U) /*!< Bit position for ENET_PAUR_PADDR2. */ -#define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) /*!< Bit mask for ENET_PAUR_PADDR2. */ -#define BS_ENET_PAUR_PADDR2 (16U) /*!< Bit field size in bits for ENET_PAUR_PADDR2. */ - -/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */ -#define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2) - -/*! @brief Format value for bitfield ENET_PAUR_PADDR2. */ -#define BF_ENET_PAUR_PADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PAUR_PADDR2) & BM_ENET_PAUR_PADDR2) - -/*! @brief Set the PADDR2 field to a new value. */ -#define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_OPD - Opcode/Pause Duration Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW) - * - * Reset value: 0x00010000U - * - * OPD is read/write accessible. This register contains the 16-bit opcode and - * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode - * field is a constant value, 0x0001. When another node detects a PAUSE frame, - * that node pauses transmission for the duration specified in the pause duration - * field. The lower 16 bits of this register are not reset and you must initialize - * it. - */ -typedef union _hw_enet_opd -{ - uint32_t U; - struct _hw_enet_opd_bitfields - { - uint32_t PAUSE_DUR : 16; /*!< [15:0] Pause Duration */ - uint32_t OPCODE : 16; /*!< [31:16] Opcode Field In PAUSE Frames */ - } B; -} hw_enet_opd_t; - -/*! - * @name Constants and macros for entire ENET_OPD register - */ -/*@{*/ -#define HW_ENET_OPD_ADDR(x) ((x) + 0xECU) - -#define HW_ENET_OPD(x) (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x)) -#define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U) -#define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v)) -#define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) | (v))) -#define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v))) -#define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_OPD bitfields - */ - -/*! - * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW) - * - * Pause duration field used in PAUSE frames. - */ -/*@{*/ -#define BP_ENET_OPD_PAUSE_DUR (0U) /*!< Bit position for ENET_OPD_PAUSE_DUR. */ -#define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) /*!< Bit mask for ENET_OPD_PAUSE_DUR. */ -#define BS_ENET_OPD_PAUSE_DUR (16U) /*!< Bit field size in bits for ENET_OPD_PAUSE_DUR. */ - -/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */ -#define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR) - -/*! @brief Format value for bitfield ENET_OPD_PAUSE_DUR. */ -#define BF_ENET_OPD_PAUSE_DUR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_OPD_PAUSE_DUR) & BM_ENET_OPD_PAUSE_DUR) - -/*! @brief Set the PAUSE_DUR field to a new value. */ -#define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v))) -/*@}*/ - -/*! - * @name Register ENET_OPD, field OPCODE[31:16] (RO) - * - * These fields have a constant value of 0x0001. - */ -/*@{*/ -#define BP_ENET_OPD_OPCODE (16U) /*!< Bit position for ENET_OPD_OPCODE. */ -#define BM_ENET_OPD_OPCODE (0xFFFF0000U) /*!< Bit mask for ENET_OPD_OPCODE. */ -#define BS_ENET_OPD_OPCODE (16U) /*!< Bit field size in bits for ENET_OPD_OPCODE. */ - -/*! @brief Read current value of the ENET_OPD_OPCODE field. */ -#define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IAUR - Descriptor Individual Upper Address Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW) - * - * Reset value: 0x00000000U - * - * IAUR contains the upper 32 bits of the 64-bit individual address hash table. - * The address recognition process uses this table to check for a possible match - * with the destination address (DA) field of receive frames with an individual - * DA. This register is not reset and you must initialize it. - */ -typedef union _hw_enet_iaur -{ - uint32_t U; - struct _hw_enet_iaur_bitfields - { - uint32_t IADDR1 : 32; /*!< [31:0] */ - } B; -} hw_enet_iaur_t; - -/*! - * @name Constants and macros for entire ENET_IAUR register - */ -/*@{*/ -#define HW_ENET_IAUR_ADDR(x) ((x) + 0x118U) - -#define HW_ENET_IAUR(x) (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x)) -#define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U) -#define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v)) -#define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) | (v))) -#define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v))) -#define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_IAUR bitfields - */ - -/*! - * @name Register ENET_IAUR, field IADDR1[31:0] (RW) - * - * Contains the upper 32 bits of the 64-bit hash table used in the address - * recognition process for receive frames with a unicast address. Bit 31 of IADDR1 - * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. - */ -/*@{*/ -#define BP_ENET_IAUR_IADDR1 (0U) /*!< Bit position for ENET_IAUR_IADDR1. */ -#define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) /*!< Bit mask for ENET_IAUR_IADDR1. */ -#define BS_ENET_IAUR_IADDR1 (32U) /*!< Bit field size in bits for ENET_IAUR_IADDR1. */ - -/*! @brief Read current value of the ENET_IAUR_IADDR1 field. */ -#define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U) - -/*! @brief Format value for bitfield ENET_IAUR_IADDR1. */ -#define BF_ENET_IAUR_IADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IAUR_IADDR1) & BM_ENET_IAUR_IADDR1) - -/*! @brief Set the IADDR1 field to a new value. */ -#define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IALR - Descriptor Individual Lower Address Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW) - * - * Reset value: 0x00000000U - * - * IALR contains the lower 32 bits of the 64-bit individual address hash table. - * The address recognition process uses this table to check for a possible match - * with the DA field of receive frames with an individual DA. This register is - * not reset and you must initialize it. - */ -typedef union _hw_enet_ialr -{ - uint32_t U; - struct _hw_enet_ialr_bitfields - { - uint32_t IADDR2 : 32; /*!< [31:0] */ - } B; -} hw_enet_ialr_t; - -/*! - * @name Constants and macros for entire ENET_IALR register - */ -/*@{*/ -#define HW_ENET_IALR_ADDR(x) ((x) + 0x11CU) - -#define HW_ENET_IALR(x) (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x)) -#define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U) -#define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v)) -#define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) | (v))) -#define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v))) -#define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_IALR bitfields - */ - -/*! - * @name Register ENET_IALR, field IADDR2[31:0] (RW) - * - * Contains the lower 32 bits of the 64-bit hash table used in the address - * recognition process for receive frames with a unicast address. Bit 31 of IADDR2 - * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. - */ -/*@{*/ -#define BP_ENET_IALR_IADDR2 (0U) /*!< Bit position for ENET_IALR_IADDR2. */ -#define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) /*!< Bit mask for ENET_IALR_IADDR2. */ -#define BS_ENET_IALR_IADDR2 (32U) /*!< Bit field size in bits for ENET_IALR_IADDR2. */ - -/*! @brief Read current value of the ENET_IALR_IADDR2 field. */ -#define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U) - -/*! @brief Format value for bitfield ENET_IALR_IADDR2. */ -#define BF_ENET_IALR_IADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IALR_IADDR2) & BM_ENET_IALR_IADDR2) - -/*! @brief Set the IADDR2 field to a new value. */ -#define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_GAUR - Descriptor Group Upper Address Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW) - * - * Reset value: 0x00000000U - * - * GAUR contains the upper 32 bits of the 64-bit hash table used in the address - * recognition process for receive frames with a multicast address. You must - * initialize this register. - */ -typedef union _hw_enet_gaur -{ - uint32_t U; - struct _hw_enet_gaur_bitfields - { - uint32_t GADDR1 : 32; /*!< [31:0] */ - } B; -} hw_enet_gaur_t; - -/*! - * @name Constants and macros for entire ENET_GAUR register - */ -/*@{*/ -#define HW_ENET_GAUR_ADDR(x) ((x) + 0x120U) - -#define HW_ENET_GAUR(x) (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x)) -#define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U) -#define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v)) -#define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) | (v))) -#define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v))) -#define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_GAUR bitfields - */ - -/*! - * @name Register ENET_GAUR, field GADDR1[31:0] (RW) - * - * Contains the upper 32 bits of the 64-bit hash table used in the address - * recognition process for receive frames with a multicast address. Bit 31 of GADDR1 - * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32. - */ -/*@{*/ -#define BP_ENET_GAUR_GADDR1 (0U) /*!< Bit position for ENET_GAUR_GADDR1. */ -#define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) /*!< Bit mask for ENET_GAUR_GADDR1. */ -#define BS_ENET_GAUR_GADDR1 (32U) /*!< Bit field size in bits for ENET_GAUR_GADDR1. */ - -/*! @brief Read current value of the ENET_GAUR_GADDR1 field. */ -#define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U) - -/*! @brief Format value for bitfield ENET_GAUR_GADDR1. */ -#define BF_ENET_GAUR_GADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GAUR_GADDR1) & BM_ENET_GAUR_GADDR1) - -/*! @brief Set the GADDR1 field to a new value. */ -#define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_GALR - Descriptor Group Lower Address Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW) - * - * Reset value: 0x00000000U - * - * GALR contains the lower 32 bits of the 64-bit hash table used in the address - * recognition process for receive frames with a multicast address. You must - * initialize this register. - */ -typedef union _hw_enet_galr -{ - uint32_t U; - struct _hw_enet_galr_bitfields - { - uint32_t GADDR2 : 32; /*!< [31:0] */ - } B; -} hw_enet_galr_t; - -/*! - * @name Constants and macros for entire ENET_GALR register - */ -/*@{*/ -#define HW_ENET_GALR_ADDR(x) ((x) + 0x124U) - -#define HW_ENET_GALR(x) (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x)) -#define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U) -#define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v)) -#define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) | (v))) -#define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v))) -#define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_GALR bitfields - */ - -/*! - * @name Register ENET_GALR, field GADDR2[31:0] (RW) - * - * Contains the lower 32 bits of the 64-bit hash table used in the address - * recognition process for receive frames with a multicast address. Bit 31 of GADDR2 - * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. - */ -/*@{*/ -#define BP_ENET_GALR_GADDR2 (0U) /*!< Bit position for ENET_GALR_GADDR2. */ -#define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) /*!< Bit mask for ENET_GALR_GADDR2. */ -#define BS_ENET_GALR_GADDR2 (32U) /*!< Bit field size in bits for ENET_GALR_GADDR2. */ - -/*! @brief Read current value of the ENET_GALR_GADDR2 field. */ -#define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U) - -/*! @brief Format value for bitfield ENET_GALR_GADDR2. */ -#define BF_ENET_GALR_GADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GALR_GADDR2) & BM_ENET_GALR_GADDR2) - -/*! @brief Set the GADDR2 field to a new value. */ -#define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TFWR - Transmit FIFO Watermark Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW) - * - * Reset value: 0x00000000U - * - * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required - * in the transmit FIFO before transmission of a frame can begin. This allows you - * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access - * latency (TFWR = 11) due to contention for the system bus. Setting the - * watermark to a high value minimizes the risk of transmit FIFO underrun due to - * contention for the system bus. The byte counts associated with the TFWR field may need - * to be modified to match a given system requirement. For example, worst case - * bus access latency by the transmit data DMA channel. When the FIFO level - * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC - * transmit control logic starts frame transmission even before the end-of-frame is - * available in the FIFO (cut-through operation). If a complete frame has a size - * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame - * to the line. To enable store and forward on the Transmit path, set STR_FWD to - * '1'. In this case, the MAC starts to transmit data only when a complete frame - * is stored in the Transmit FIFO. - */ -typedef union _hw_enet_tfwr -{ - uint32_t U; - struct _hw_enet_tfwr_bitfields - { - uint32_t TFWR : 6; /*!< [5:0] Transmit FIFO Write */ - uint32_t RESERVED0 : 2; /*!< [7:6] */ - uint32_t STRFWD : 1; /*!< [8] Store And Forward Enable */ - uint32_t RESERVED1 : 23; /*!< [31:9] */ - } B; -} hw_enet_tfwr_t; - -/*! - * @name Constants and macros for entire ENET_TFWR register - */ -/*@{*/ -#define HW_ENET_TFWR_ADDR(x) ((x) + 0x144U) - -#define HW_ENET_TFWR(x) (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x)) -#define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U) -#define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v)) -#define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) | (v))) -#define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v))) -#define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TFWR bitfields - */ - -/*! - * @name Register ENET_TFWR, field TFWR[5:0] (RW) - * - * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in - * steps of 64 bytes, written to the transmit FIFO before transmission of a frame - * begins. If a frame with less than the threshold is written, it is still sent - * independently of this threshold setting. The threshold is relevant only if the - * frame is larger than the threshold given. This chip may not support the maximum - * number of bytes written shown below. See the chip-specific information for the - * ENET module for this value. - * - * Values: - * - 000000 - 64 bytes written. - * - 000001 - 64 bytes written. - * - 000010 - 128 bytes written. - * - 000011 - 192 bytes written. - * - 111110 - 3968 bytes written. - * - 111111 - 4032 bytes written. - */ -/*@{*/ -#define BP_ENET_TFWR_TFWR (0U) /*!< Bit position for ENET_TFWR_TFWR. */ -#define BM_ENET_TFWR_TFWR (0x0000003FU) /*!< Bit mask for ENET_TFWR_TFWR. */ -#define BS_ENET_TFWR_TFWR (6U) /*!< Bit field size in bits for ENET_TFWR_TFWR. */ - -/*! @brief Read current value of the ENET_TFWR_TFWR field. */ -#define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR) - -/*! @brief Format value for bitfield ENET_TFWR_TFWR. */ -#define BF_ENET_TFWR_TFWR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_TFWR) & BM_ENET_TFWR_TFWR) - -/*! @brief Set the TFWR field to a new value. */ -#define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v))) -/*@}*/ - -/*! - * @name Register ENET_TFWR, field STRFWD[8] (RW) - * - * Values: - * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR]. - * - 1 - Enabled. - */ -/*@{*/ -#define BP_ENET_TFWR_STRFWD (8U) /*!< Bit position for ENET_TFWR_STRFWD. */ -#define BM_ENET_TFWR_STRFWD (0x00000100U) /*!< Bit mask for ENET_TFWR_STRFWD. */ -#define BS_ENET_TFWR_STRFWD (1U) /*!< Bit field size in bits for ENET_TFWR_STRFWD. */ - -/*! @brief Read current value of the ENET_TFWR_STRFWD field. */ -#define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD)) - -/*! @brief Format value for bitfield ENET_TFWR_STRFWD. */ -#define BF_ENET_TFWR_STRFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_STRFWD) & BM_ENET_TFWR_STRFWD) - -/*! @brief Set the STRFWD field to a new value. */ -#define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RDSR - Receive Descriptor Ring Start Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW) - * - * Reset value: 0x00000000U - * - * RDSR points to the beginning of the circular receive buffer descriptor queue - * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be - * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible - * by 16. This register must be initialized prior to operation - */ -typedef union _hw_enet_rdsr -{ - uint32_t U; - struct _hw_enet_rdsr_bitfields - { - uint32_t RESERVED0 : 3; /*!< [2:0] */ - uint32_t R_DES_START : 29; /*!< [31:3] */ - } B; -} hw_enet_rdsr_t; - -/*! - * @name Constants and macros for entire ENET_RDSR register - */ -/*@{*/ -#define HW_ENET_RDSR_ADDR(x) ((x) + 0x180U) - -#define HW_ENET_RDSR(x) (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x)) -#define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U) -#define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v)) -#define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) | (v))) -#define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v))) -#define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RDSR bitfields - */ - -/*! - * @name Register ENET_RDSR, field R_DES_START[31:3] (RW) - * - * Pointer to the beginning of the receive buffer descriptor queue. - */ -/*@{*/ -#define BP_ENET_RDSR_R_DES_START (3U) /*!< Bit position for ENET_RDSR_R_DES_START. */ -#define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_RDSR_R_DES_START. */ -#define BS_ENET_RDSR_R_DES_START (29U) /*!< Bit field size in bits for ENET_RDSR_R_DES_START. */ - -/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */ -#define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START) - -/*! @brief Format value for bitfield ENET_RDSR_R_DES_START. */ -#define BF_ENET_RDSR_R_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDSR_R_DES_START) & BM_ENET_RDSR_R_DES_START) - -/*! @brief Set the R_DES_START field to a new value. */ -#define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW) - * - * Reset value: 0x00000000U - * - * TDSR provides a pointer to the beginning of the circular transmit buffer - * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0 - * must be zero); however, it is recommended to be 128-bit aligned, that is, - * evenly divisible by 16. This register must be initialized prior to operation. - */ -typedef union _hw_enet_tdsr -{ - uint32_t U; - struct _hw_enet_tdsr_bitfields - { - uint32_t RESERVED0 : 3; /*!< [2:0] */ - uint32_t X_DES_START : 29; /*!< [31:3] */ - } B; -} hw_enet_tdsr_t; - -/*! - * @name Constants and macros for entire ENET_TDSR register - */ -/*@{*/ -#define HW_ENET_TDSR_ADDR(x) ((x) + 0x184U) - -#define HW_ENET_TDSR(x) (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x)) -#define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U) -#define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v)) -#define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) | (v))) -#define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v))) -#define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TDSR bitfields - */ - -/*! - * @name Register ENET_TDSR, field X_DES_START[31:3] (RW) - * - * Pointer to the beginning of the transmit buffer descriptor queue. - */ -/*@{*/ -#define BP_ENET_TDSR_X_DES_START (3U) /*!< Bit position for ENET_TDSR_X_DES_START. */ -#define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_TDSR_X_DES_START. */ -#define BS_ENET_TDSR_X_DES_START (29U) /*!< Bit field size in bits for ENET_TDSR_X_DES_START. */ - -/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */ -#define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START) - -/*! @brief Format value for bitfield ENET_TDSR_X_DES_START. */ -#define BF_ENET_TDSR_X_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDSR_X_DES_START) & BM_ENET_TDSR_X_DES_START) - -/*! @brief Set the X_DES_START field to a new value. */ -#define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_MRBR - Maximum Receive Buffer Size Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW) - * - * Reset value: 0x00000000U - * - * The MRBR is a user-programmable register that dictates the maximum size of - * all receive buffers. This value should take into consideration that the receive - * CRC is always written into the last receive buffer. To allow one maximum size - * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align - * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are - * set to zero by the device. To minimize bus usage (descriptor fetches), set - * MRBR greater than or equal to 256 bytes. This register must be initialized - * before operation. - */ -typedef union _hw_enet_mrbr -{ - uint32_t U; - struct _hw_enet_mrbr_bitfields - { - uint32_t RESERVED0 : 4; /*!< [3:0] */ - uint32_t R_BUF_SIZE : 10; /*!< [13:4] */ - uint32_t RESERVED1 : 18; /*!< [31:14] */ - } B; -} hw_enet_mrbr_t; - -/*! - * @name Constants and macros for entire ENET_MRBR register - */ -/*@{*/ -#define HW_ENET_MRBR_ADDR(x) ((x) + 0x188U) - -#define HW_ENET_MRBR(x) (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x)) -#define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U) -#define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v)) -#define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) | (v))) -#define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v))) -#define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_MRBR bitfields - */ - -/*! - * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW) - * - * Receive buffer size in bytes. - */ -/*@{*/ -#define BP_ENET_MRBR_R_BUF_SIZE (4U) /*!< Bit position for ENET_MRBR_R_BUF_SIZE. */ -#define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) /*!< Bit mask for ENET_MRBR_R_BUF_SIZE. */ -#define BS_ENET_MRBR_R_BUF_SIZE (10U) /*!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE. */ - -/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */ -#define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE) - -/*! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE. */ -#define BF_ENET_MRBR_R_BUF_SIZE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MRBR_R_BUF_SIZE) & BM_ENET_MRBR_R_BUF_SIZE) - -/*! @brief Set the R_BUF_SIZE field to a new value. */ -#define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RSFL - Receive FIFO Section Full Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rsfl -{ - uint32_t U; - struct _hw_enet_rsfl_bitfields - { - uint32_t RX_SECTION_FULL : 8; /*!< [7:0] Value Of Receive FIFO - * Section Full Threshold */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_enet_rsfl_t; - -/*! - * @name Constants and macros for entire ENET_RSFL register - */ -/*@{*/ -#define HW_ENET_RSFL_ADDR(x) ((x) + 0x190U) - -#define HW_ENET_RSFL(x) (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x)) -#define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U) -#define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v)) -#define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) | (v))) -#define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v))) -#define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RSFL bitfields - */ - -/*! - * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW) - * - * Value, in 64-bit words, of the receive FIFO section full threshold. Clear - * this field to enable store and forward on the RX FIFO. When programming a value - * greater than 0 (cut-through operation), it must be greater than - * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available - * in the Receive FIFO (cut-through operation). - */ -/*@{*/ -#define BP_ENET_RSFL_RX_SECTION_FULL (0U) /*!< Bit position for ENET_RSFL_RX_SECTION_FULL. */ -#define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) /*!< Bit mask for ENET_RSFL_RX_SECTION_FULL. */ -#define BS_ENET_RSFL_RX_SECTION_FULL (8U) /*!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL. */ - -/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */ -#define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL) - -/*! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL. */ -#define BF_ENET_RSFL_RX_SECTION_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSFL_RX_SECTION_FULL) & BM_ENET_RSFL_RX_SECTION_FULL) - -/*! @brief Set the RX_SECTION_FULL field to a new value. */ -#define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RSEM - Receive FIFO Section Empty Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rsem -{ - uint32_t U; - struct _hw_enet_rsem_bitfields - { - uint32_t RX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO - * Section Empty Threshold */ - uint32_t RESERVED0 : 8; /*!< [15:8] */ - uint32_t STAT_SECTION_EMPTY : 5; /*!< [20:16] RX Status FIFO Section - * Empty Threshold */ - uint32_t RESERVED1 : 11; /*!< [31:21] */ - } B; -} hw_enet_rsem_t; - -/*! - * @name Constants and macros for entire ENET_RSEM register - */ -/*@{*/ -#define HW_ENET_RSEM_ADDR(x) ((x) + 0x194U) - -#define HW_ENET_RSEM(x) (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x)) -#define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U) -#define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v)) -#define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) | (v))) -#define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v))) -#define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RSEM bitfields - */ - -/*! - * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW) - * - * Value, in 64-bit words, of the receive FIFO section empty threshold. When the - * FIFO has reached this level, a pause frame will be issued. A value of 0 - * disables automatic pause frame generation. When the FIFO level goes below the value - * programmed in this field, an XON pause frame is issued to indicate the FIFO - * congestion is cleared to the remote Ethernet client. The section-empty - * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation. - */ -/*@{*/ -#define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) /*!< Bit position for ENET_RSEM_RX_SECTION_EMPTY. */ -#define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY. */ -#define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY. */ - -/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */ -#define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY) - -/*! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY. */ -#define BF_ENET_RSEM_RX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_RX_SECTION_EMPTY) & BM_ENET_RSEM_RX_SECTION_EMPTY) - -/*! @brief Set the RX_SECTION_EMPTY field to a new value. */ -#define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v))) -/*@}*/ - -/*! - * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW) - * - * Defines number of frames in the receive FIFO, independent of its size, that - * can be accepted. If the limit is reached, reception will continue normally, - * however a pause frame will be triggered to indicate a possible congestion to the - * remote device to avoid FIFO overflow. A value of 0 disables automatic pause - * frame generation - */ -/*@{*/ -#define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) /*!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY. */ -#define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) /*!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY. */ -#define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) /*!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY. */ - -/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */ -#define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY) - -/*! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY. */ -#define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_STAT_SECTION_EMPTY) & BM_ENET_RSEM_STAT_SECTION_EMPTY) - -/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */ -#define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RAEM - Receive FIFO Almost Empty Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW) - * - * Reset value: 0x00000004U - */ -typedef union _hw_enet_raem -{ - uint32_t U; - struct _hw_enet_raem_bitfields - { - uint32_t RX_ALMOST_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO - * Almost Empty Threshold */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_enet_raem_t; - -/*! - * @name Constants and macros for entire ENET_RAEM register - */ -/*@{*/ -#define HW_ENET_RAEM_ADDR(x) ((x) + 0x198U) - -#define HW_ENET_RAEM(x) (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x)) -#define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U) -#define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v)) -#define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) | (v))) -#define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v))) -#define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RAEM bitfields - */ - -/*! - * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW) - * - * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the - * FIFO level reaches the value programmed in this field and the end-of-frame has - * not been received for the frame yet, the core receive read control stops FIFO - * read (and subsequently stops transferring data to the MAC client - * application). It continues to deliver the frame, if again more data than the threshold or - * the end-of-frame is available in the FIFO. A minimum value of 4 should be set. - */ -/*@{*/ -#define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) /*!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY. */ -#define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY. */ -#define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) /*!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY. */ - -/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */ -#define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY) - -/*! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY. */ -#define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAEM_RX_ALMOST_EMPTY) & BM_ENET_RAEM_RX_ALMOST_EMPTY) - -/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */ -#define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RAFL - Receive FIFO Almost Full Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW) - * - * Reset value: 0x00000004U - */ -typedef union _hw_enet_rafl -{ - uint32_t U; - struct _hw_enet_rafl_bitfields - { - uint32_t RX_ALMOST_FULL : 8; /*!< [7:0] Value Of The Receive FIFO - * Almost Full Threshold */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_enet_rafl_t; - -/*! - * @name Constants and macros for entire ENET_RAFL register - */ -/*@{*/ -#define HW_ENET_RAFL_ADDR(x) ((x) + 0x19CU) - -#define HW_ENET_RAFL(x) (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x)) -#define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U) -#define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v)) -#define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) | (v))) -#define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v))) -#define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RAFL bitfields - */ - -/*! - * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW) - * - * Value, in 64-bit words, of the receive FIFO almost full threshold. When the - * FIFO level comes close to the maximum, so that there is no more space for at - * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and - * truncates the received frame to avoid FIFO overflow. The corresponding error - * status will be set when the frame is delivered to the application. A minimum - * value of 4 should be set. - */ -/*@{*/ -#define BP_ENET_RAFL_RX_ALMOST_FULL (0U) /*!< Bit position for ENET_RAFL_RX_ALMOST_FULL. */ -#define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_RAFL_RX_ALMOST_FULL. */ -#define BS_ENET_RAFL_RX_ALMOST_FULL (8U) /*!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL. */ - -/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */ -#define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL) - -/*! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL. */ -#define BF_ENET_RAFL_RX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAFL_RX_ALMOST_FULL) & BM_ENET_RAFL_RX_ALMOST_FULL) - -/*! @brief Set the RX_ALMOST_FULL field to a new value. */ -#define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TSEM - Transmit FIFO Section Empty Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_tsem -{ - uint32_t U; - struct _hw_enet_tsem_bitfields - { - uint32_t TX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Transmit FIFO - * Section Empty Threshold */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_enet_tsem_t; - -/*! - * @name Constants and macros for entire ENET_TSEM register - */ -/*@{*/ -#define HW_ENET_TSEM_ADDR(x) ((x) + 0x1A0U) - -#define HW_ENET_TSEM(x) (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x)) -#define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U) -#define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v)) -#define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) | (v))) -#define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v))) -#define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TSEM bitfields - */ - -/*! - * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW) - * - * Value, in 64-bit words, of the transmit FIFO section empty threshold. See - * Transmit FIFOFour programmable thresholds are available which control the core - * operation. for more information. - */ -/*@{*/ -#define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) /*!< Bit position for ENET_TSEM_TX_SECTION_EMPTY. */ -#define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY. */ -#define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY. */ - -/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */ -#define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY) - -/*! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY. */ -#define BF_ENET_TSEM_TX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TSEM_TX_SECTION_EMPTY) & BM_ENET_TSEM_TX_SECTION_EMPTY) - -/*! @brief Set the TX_SECTION_EMPTY field to a new value. */ -#define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW) - * - * Reset value: 0x00000004U - */ -typedef union _hw_enet_taem -{ - uint32_t U; - struct _hw_enet_taem_bitfields - { - uint32_t TX_ALMOST_EMPTY : 8; /*!< [7:0] Value of Transmit FIFO - * Almost Empty Threshold */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_enet_taem_t; - -/*! - * @name Constants and macros for entire ENET_TAEM register - */ -/*@{*/ -#define HW_ENET_TAEM_ADDR(x) ((x) + 0x1A4U) - -#define HW_ENET_TAEM(x) (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x)) -#define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U) -#define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v)) -#define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) | (v))) -#define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v))) -#define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TAEM bitfields - */ - -/*! - * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW) - * - * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the - * FIFO level reaches the value programmed in this field, and no end-of-frame is - * available for the frame, the MAC transmit logic, to avoid FIFO underflow, - * stops reading the FIFO and transmits a frame with an MII error indication. See - * Transmit FIFOFour programmable thresholds are available which control the core - * operation. for more information. A minimum value of 4 should be set. - */ -/*@{*/ -#define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) /*!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY. */ -#define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY. */ -#define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) /*!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY. */ - -/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */ -#define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY) - -/*! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY. */ -#define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAEM_TX_ALMOST_EMPTY) & BM_ENET_TAEM_TX_ALMOST_EMPTY) - -/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */ -#define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TAFL - Transmit FIFO Almost Full Threshold - ******************************************************************************/ - -/*! - * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW) - * - * Reset value: 0x00000008U - */ -typedef union _hw_enet_tafl -{ - uint32_t U; - struct _hw_enet_tafl_bitfields - { - uint32_t TX_ALMOST_FULL : 8; /*!< [7:0] Value Of The Transmit FIFO - * Almost Full Threshold */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_enet_tafl_t; - -/*! - * @name Constants and macros for entire ENET_TAFL register - */ -/*@{*/ -#define HW_ENET_TAFL_ADDR(x) ((x) + 0x1A8U) - -#define HW_ENET_TAFL(x) (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x)) -#define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U) -#define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v)) -#define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) | (v))) -#define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v))) -#define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TAFL bitfields - */ - -/*! - * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW) - * - * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum - * value of six is required . A recommended value of at least 8 should be set - * allowing a latency of two clock cycles to the application. If more latency is - * required the value can be increased as necessary (latency = TAFL - 5). When the - * FIFO level comes close to the maximum, so that there is no more space for at - * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the - * application does not react on this signal, the FIFO write control logic, to - * avoid FIFO overflow, truncates the current frame and sets the error status. As a - * result, the frame will be transmitted with an GMII/MII error indication. See - * Transmit FIFOFour programmable thresholds are available which control the core - * operation. for more information. A FIFO overflow is a fatal error and requires - * a global reset on the transmit datapath or at least deassertion of ETHEREN. - */ -/*@{*/ -#define BP_ENET_TAFL_TX_ALMOST_FULL (0U) /*!< Bit position for ENET_TAFL_TX_ALMOST_FULL. */ -#define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_TAFL_TX_ALMOST_FULL. */ -#define BS_ENET_TAFL_TX_ALMOST_FULL (8U) /*!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL. */ - -/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */ -#define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL) - -/*! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL. */ -#define BF_ENET_TAFL_TX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAFL_TX_ALMOST_FULL) & BM_ENET_TAFL_TX_ALMOST_FULL) - -/*! @brief Set the TX_ALMOST_FULL field to a new value. */ -#define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TIPG - Transmit Inter-Packet Gap - ******************************************************************************/ - -/*! - * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW) - * - * Reset value: 0x0000000CU - */ -typedef union _hw_enet_tipg -{ - uint32_t U; - struct _hw_enet_tipg_bitfields - { - uint32_t IPG : 5; /*!< [4:0] Transmit Inter-Packet Gap */ - uint32_t RESERVED0 : 27; /*!< [31:5] */ - } B; -} hw_enet_tipg_t; - -/*! - * @name Constants and macros for entire ENET_TIPG register - */ -/*@{*/ -#define HW_ENET_TIPG_ADDR(x) ((x) + 0x1ACU) - -#define HW_ENET_TIPG(x) (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x)) -#define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U) -#define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v)) -#define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) | (v))) -#define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v))) -#define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TIPG bitfields - */ - -/*! - * @name Register ENET_TIPG, field IPG[4:0] (RW) - * - * Indicates the IPG, in bytes, between transmitted frames. Valid values range - * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than - * 27, the IPG is 27. - */ -/*@{*/ -#define BP_ENET_TIPG_IPG (0U) /*!< Bit position for ENET_TIPG_IPG. */ -#define BM_ENET_TIPG_IPG (0x0000001FU) /*!< Bit mask for ENET_TIPG_IPG. */ -#define BS_ENET_TIPG_IPG (5U) /*!< Bit field size in bits for ENET_TIPG_IPG. */ - -/*! @brief Read current value of the ENET_TIPG_IPG field. */ -#define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG) - -/*! @brief Format value for bitfield ENET_TIPG_IPG. */ -#define BF_ENET_TIPG_IPG(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TIPG_IPG) & BM_ENET_TIPG_IPG) - -/*! @brief Set the IPG field to a new value. */ -#define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_FTRL - Frame Truncation Length - ******************************************************************************/ - -/*! - * @brief HW_ENET_FTRL - Frame Truncation Length (RW) - * - * Reset value: 0x000007FFU - */ -typedef union _hw_enet_ftrl -{ - uint32_t U; - struct _hw_enet_ftrl_bitfields - { - uint32_t TRUNC_FL : 14; /*!< [13:0] Frame Truncation Length */ - uint32_t RESERVED0 : 18; /*!< [31:14] */ - } B; -} hw_enet_ftrl_t; - -/*! - * @name Constants and macros for entire ENET_FTRL register - */ -/*@{*/ -#define HW_ENET_FTRL_ADDR(x) ((x) + 0x1B0U) - -#define HW_ENET_FTRL(x) (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x)) -#define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U) -#define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v)) -#define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) | (v))) -#define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v))) -#define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_FTRL bitfields - */ - -/*! - * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW) - * - * Indicates the value a receive frame is truncated, if it is greater than this - * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at - * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive - * less data, guaranteeing that it never receives more than the set limit. - */ -/*@{*/ -#define BP_ENET_FTRL_TRUNC_FL (0U) /*!< Bit position for ENET_FTRL_TRUNC_FL. */ -#define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) /*!< Bit mask for ENET_FTRL_TRUNC_FL. */ -#define BS_ENET_FTRL_TRUNC_FL (14U) /*!< Bit field size in bits for ENET_FTRL_TRUNC_FL. */ - -/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */ -#define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL) - -/*! @brief Format value for bitfield ENET_FTRL_TRUNC_FL. */ -#define BF_ENET_FTRL_TRUNC_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_FTRL_TRUNC_FL) & BM_ENET_FTRL_TRUNC_FL) - -/*! @brief Set the TRUNC_FL field to a new value. */ -#define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TACC - Transmit Accelerator Function Configuration - ******************************************************************************/ - -/*! - * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW) - * - * Reset value: 0x00000000U - * - * TACC controls accelerator actions when sending frames. The register can be - * changed before or after each frame, but it must remain unmodified during frame - * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the - * checksum feature. - */ -typedef union _hw_enet_tacc -{ - uint32_t U; - struct _hw_enet_tacc_bitfields - { - uint32_t SHIFT16 : 1; /*!< [0] TX FIFO Shift-16 */ - uint32_t RESERVED0 : 2; /*!< [2:1] */ - uint32_t IPCHK : 1; /*!< [3] */ - uint32_t PROCHK : 1; /*!< [4] */ - uint32_t RESERVED1 : 27; /*!< [31:5] */ - } B; -} hw_enet_tacc_t; - -/*! - * @name Constants and macros for entire ENET_TACC register - */ -/*@{*/ -#define HW_ENET_TACC_ADDR(x) ((x) + 0x1C0U) - -#define HW_ENET_TACC(x) (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x)) -#define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U) -#define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v)) -#define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) | (v))) -#define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v))) -#define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TACC bitfields - */ - -/*! - * @name Register ENET_TACC, field SHIFT16[0] (RW) - * - * Values: - * - 0 - Disabled. - * - 1 - Indicates to the transmit data FIFO that the written frames contain two - * additional octets before the frame data. This means the actual frame - * begins at bit 16 of the first word written into the FIFO. This function allows - * putting the frame payload on a 32-bit boundary in memory, as the 14-byte - * Ethernet header is extended to a 16-byte header. - */ -/*@{*/ -#define BP_ENET_TACC_SHIFT16 (0U) /*!< Bit position for ENET_TACC_SHIFT16. */ -#define BM_ENET_TACC_SHIFT16 (0x00000001U) /*!< Bit mask for ENET_TACC_SHIFT16. */ -#define BS_ENET_TACC_SHIFT16 (1U) /*!< Bit field size in bits for ENET_TACC_SHIFT16. */ - -/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */ -#define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16)) - -/*! @brief Format value for bitfield ENET_TACC_SHIFT16. */ -#define BF_ENET_TACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_SHIFT16) & BM_ENET_TACC_SHIFT16) - -/*! @brief Set the SHIFT16 field to a new value. */ -#define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TACC, field IPCHK[3] (RW) - * - * Enables insertion of IP header checksum. - * - * Values: - * - 0 - Checksum is not inserted. - * - 1 - If an IP frame is transmitted, the checksum is inserted automatically. - * The IP header checksum field must be cleared. If a non-IP frame is - * transmitted the frame is not modified. - */ -/*@{*/ -#define BP_ENET_TACC_IPCHK (3U) /*!< Bit position for ENET_TACC_IPCHK. */ -#define BM_ENET_TACC_IPCHK (0x00000008U) /*!< Bit mask for ENET_TACC_IPCHK. */ -#define BS_ENET_TACC_IPCHK (1U) /*!< Bit field size in bits for ENET_TACC_IPCHK. */ - -/*! @brief Read current value of the ENET_TACC_IPCHK field. */ -#define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK)) - -/*! @brief Format value for bitfield ENET_TACC_IPCHK. */ -#define BF_ENET_TACC_IPCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_IPCHK) & BM_ENET_TACC_IPCHK) - -/*! @brief Set the IPCHK field to a new value. */ -#define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TACC, field PROCHK[4] (RW) - * - * Enables insertion of protocol checksum. - * - * Values: - * - 0 - Checksum not inserted. - * - 1 - If an IP frame with a known protocol is transmitted, the checksum is - * inserted automatically into the frame. The checksum field must be cleared. - * The other frames are not modified. - */ -/*@{*/ -#define BP_ENET_TACC_PROCHK (4U) /*!< Bit position for ENET_TACC_PROCHK. */ -#define BM_ENET_TACC_PROCHK (0x00000010U) /*!< Bit mask for ENET_TACC_PROCHK. */ -#define BS_ENET_TACC_PROCHK (1U) /*!< Bit field size in bits for ENET_TACC_PROCHK. */ - -/*! @brief Read current value of the ENET_TACC_PROCHK field. */ -#define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK)) - -/*! @brief Format value for bitfield ENET_TACC_PROCHK. */ -#define BF_ENET_TACC_PROCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_PROCHK) & BM_ENET_TACC_PROCHK) - -/*! @brief Set the PROCHK field to a new value. */ -#define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RACC - Receive Accelerator Function Configuration - ******************************************************************************/ - -/*! - * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_racc -{ - uint32_t U; - struct _hw_enet_racc_bitfields - { - uint32_t PADREM : 1; /*!< [0] Enable Padding Removal For Short IP - * Frames */ - uint32_t IPDIS : 1; /*!< [1] Enable Discard Of Frames With Wrong IPv4 - * Header Checksum */ - uint32_t PRODIS : 1; /*!< [2] Enable Discard Of Frames With Wrong - * Protocol Checksum */ - uint32_t RESERVED0 : 3; /*!< [5:3] */ - uint32_t LINEDIS : 1; /*!< [6] Enable Discard Of Frames With MAC - * Layer Errors */ - uint32_t SHIFT16 : 1; /*!< [7] RX FIFO Shift-16 */ - uint32_t RESERVED1 : 24; /*!< [31:8] */ - } B; -} hw_enet_racc_t; - -/*! - * @name Constants and macros for entire ENET_RACC register - */ -/*@{*/ -#define HW_ENET_RACC_ADDR(x) ((x) + 0x1C4U) - -#define HW_ENET_RACC(x) (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x)) -#define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U) -#define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v)) -#define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) | (v))) -#define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v))) -#define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_RACC bitfields - */ - -/*! - * @name Register ENET_RACC, field PADREM[0] (RW) - * - * Values: - * - 0 - Padding not removed. - * - 1 - Any bytes following the IP payload section of the frame are removed - * from the frame. - */ -/*@{*/ -#define BP_ENET_RACC_PADREM (0U) /*!< Bit position for ENET_RACC_PADREM. */ -#define BM_ENET_RACC_PADREM (0x00000001U) /*!< Bit mask for ENET_RACC_PADREM. */ -#define BS_ENET_RACC_PADREM (1U) /*!< Bit field size in bits for ENET_RACC_PADREM. */ - -/*! @brief Read current value of the ENET_RACC_PADREM field. */ -#define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM)) - -/*! @brief Format value for bitfield ENET_RACC_PADREM. */ -#define BF_ENET_RACC_PADREM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PADREM) & BM_ENET_RACC_PADREM) - -/*! @brief Set the PADREM field to a new value. */ -#define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RACC, field IPDIS[1] (RW) - * - * Values: - * - 0 - Frames with wrong IPv4 header checksum are not discarded. - * - 1 - If an IPv4 frame is received with a mismatching header checksum, the - * frame is discarded. IPv6 has no header checksum and is not affected by this - * setting. Discarding is only available when the RX FIFO operates in store - * and forward mode (RSFL cleared). - */ -/*@{*/ -#define BP_ENET_RACC_IPDIS (1U) /*!< Bit position for ENET_RACC_IPDIS. */ -#define BM_ENET_RACC_IPDIS (0x00000002U) /*!< Bit mask for ENET_RACC_IPDIS. */ -#define BS_ENET_RACC_IPDIS (1U) /*!< Bit field size in bits for ENET_RACC_IPDIS. */ - -/*! @brief Read current value of the ENET_RACC_IPDIS field. */ -#define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS)) - -/*! @brief Format value for bitfield ENET_RACC_IPDIS. */ -#define BF_ENET_RACC_IPDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_IPDIS) & BM_ENET_RACC_IPDIS) - -/*! @brief Set the IPDIS field to a new value. */ -#define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RACC, field PRODIS[2] (RW) - * - * Values: - * - 0 - Frames with wrong checksum are not discarded. - * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, - * UDP, or ICMP checksum, the frame is discarded. Discarding is only - * available when the RX FIFO operates in store and forward mode (RSFL cleared). - */ -/*@{*/ -#define BP_ENET_RACC_PRODIS (2U) /*!< Bit position for ENET_RACC_PRODIS. */ -#define BM_ENET_RACC_PRODIS (0x00000004U) /*!< Bit mask for ENET_RACC_PRODIS. */ -#define BS_ENET_RACC_PRODIS (1U) /*!< Bit field size in bits for ENET_RACC_PRODIS. */ - -/*! @brief Read current value of the ENET_RACC_PRODIS field. */ -#define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS)) - -/*! @brief Format value for bitfield ENET_RACC_PRODIS. */ -#define BF_ENET_RACC_PRODIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PRODIS) & BM_ENET_RACC_PRODIS) - -/*! @brief Set the PRODIS field to a new value. */ -#define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RACC, field LINEDIS[6] (RW) - * - * Values: - * - 0 - Frames with errors are not discarded. - * - 1 - Any frame received with a CRC, length, or PHY error is automatically - * discarded and not forwarded to the user application interface. - */ -/*@{*/ -#define BP_ENET_RACC_LINEDIS (6U) /*!< Bit position for ENET_RACC_LINEDIS. */ -#define BM_ENET_RACC_LINEDIS (0x00000040U) /*!< Bit mask for ENET_RACC_LINEDIS. */ -#define BS_ENET_RACC_LINEDIS (1U) /*!< Bit field size in bits for ENET_RACC_LINEDIS. */ - -/*! @brief Read current value of the ENET_RACC_LINEDIS field. */ -#define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS)) - -/*! @brief Format value for bitfield ENET_RACC_LINEDIS. */ -#define BF_ENET_RACC_LINEDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_LINEDIS) & BM_ENET_RACC_LINEDIS) - -/*! @brief Set the LINEDIS field to a new value. */ -#define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v)) -/*@}*/ - -/*! - * @name Register ENET_RACC, field SHIFT16[7] (RW) - * - * When this field is set, the actual frame data starts at bit 16 of the first - * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary. - * This function only affects the FIFO storage and has no influence on the - * statistics, which use the actual length of the frame received. - * - * Values: - * - 0 - Disabled. - * - 1 - Instructs the MAC to write two additional bytes in front of each frame - * received into the RX FIFO. - */ -/*@{*/ -#define BP_ENET_RACC_SHIFT16 (7U) /*!< Bit position for ENET_RACC_SHIFT16. */ -#define BM_ENET_RACC_SHIFT16 (0x00000080U) /*!< Bit mask for ENET_RACC_SHIFT16. */ -#define BS_ENET_RACC_SHIFT16 (1U) /*!< Bit field size in bits for ENET_RACC_SHIFT16. */ - -/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */ -#define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16)) - -/*! @brief Format value for bitfield ENET_RACC_SHIFT16. */ -#define BF_ENET_RACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_SHIFT16) & BM_ENET_RACC_SHIFT16) - -/*! @brief Set the SHIFT16 field to a new value. */ -#define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_packets -{ - uint32_t U; - struct _hw_enet_rmon_t_packets_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_packets_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_PACKETS register - */ -/*@{*/ -#define HW_ENET_RMON_T_PACKETS_ADDR(x) ((x) + 0x204U) - -#define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x)) -#define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_PACKETS bitfields - */ - -/*! - * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_PACKETS_TXPKTS. */ -#define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS. */ -#define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */ -#define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - * - * RMON Tx Broadcast Packets - */ -typedef union _hw_enet_rmon_t_bc_pkt -{ - uint32_t U; - struct _hw_enet_rmon_t_bc_pkt_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Broadcast packets */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_bc_pkt_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_BC_PKT register - */ -/*@{*/ -#define HW_ENET_RMON_T_BC_PKT_ADDR(x) ((x) + 0x208U) - -#define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x)) -#define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields - */ - -/*! - * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS. */ -#define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS. */ -#define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */ -#define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_mc_pkt -{ - uint32_t U; - struct _hw_enet_rmon_t_mc_pkt_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Multicast packets */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_mc_pkt_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_MC_PKT register - */ -/*@{*/ -#define HW_ENET_RMON_T_MC_PKT_ADDR(x) ((x) + 0x20CU) - -#define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x)) -#define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields - */ - -/*! - * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS. */ -#define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS. */ -#define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */ -#define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_crc_align -{ - uint32_t U; - struct _hw_enet_rmon_t_crc_align_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packets with CRC/align error */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_crc_align_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register - */ -/*@{*/ -#define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) ((x) + 0x210U) - -#define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x)) -#define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields - */ - -/*! - * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS. */ -#define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS. */ -#define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */ -#define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_undersize -{ - uint32_t U; - struct _hw_enet_rmon_t_undersize_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_undersize_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register - */ -/*@{*/ -#define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) ((x) + 0x214U) - -#define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x)) -#define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields - */ - -/*! - * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS. */ -#define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS. */ -#define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */ -#define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_oversize -{ - uint32_t U; - struct _hw_enet_rmon_t_oversize_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_oversize_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register - */ -/*@{*/ -#define HW_ENET_RMON_T_OVERSIZE_ADDR(x) ((x) + 0x218U) - -#define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x)) -#define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields - */ - -/*! - * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS. */ -#define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS. */ -#define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */ -#define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - * - * . - */ -typedef union _hw_enet_rmon_t_frag -{ - uint32_t U; - struct _hw_enet_rmon_t_frag_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_frag_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_FRAG register - */ -/*@{*/ -#define HW_ENET_RMON_T_FRAG_ADDR(x) ((x) + 0x21CU) - -#define HW_ENET_RMON_T_FRAG(x) (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x)) -#define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_FRAG bitfields - */ - -/*! - * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_FRAG_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_FRAG_TXPKTS. */ -#define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_FRAG_TXPKTS. */ -#define BS_ENET_RMON_T_FRAG_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */ -#define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_jab -{ - uint32_t U; - struct _hw_enet_rmon_t_jab_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_jab_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_JAB register - */ -/*@{*/ -#define HW_ENET_RMON_T_JAB_ADDR(x) ((x) + 0x220U) - -#define HW_ENET_RMON_T_JAB(x) (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x)) -#define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_JAB bitfields - */ - -/*! - * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_JAB_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_JAB_TXPKTS. */ -#define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_JAB_TXPKTS. */ -#define BS_ENET_RMON_T_JAB_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */ -#define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_col -{ - uint32_t U; - struct _hw_enet_rmon_t_col_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_col_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_COL register - */ -/*@{*/ -#define HW_ENET_RMON_T_COL_ADDR(x) ((x) + 0x224U) - -#define HW_ENET_RMON_T_COL(x) (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x)) -#define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_COL bitfields - */ - -/*! - * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_COL_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_COL_TXPKTS. */ -#define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_COL_TXPKTS. */ -#define BS_ENET_RMON_T_COL_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */ -#define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - * - * . - */ -typedef union _hw_enet_rmon_t_p64 -{ - uint32_t U; - struct _hw_enet_rmon_t_p64_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p64_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P64 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P64_ADDR(x) ((x) + 0x228U) - -#define HW_ENET_RMON_T_P64(x) (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x)) -#define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P64 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P64_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P64_TXPKTS. */ -#define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P64_TXPKTS. */ -#define BS_ENET_RMON_T_P64_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */ -#define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_p65to127 -{ - uint32_t U; - struct _hw_enet_rmon_t_p65to127_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p65to127_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P65TO127 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P65TO127_ADDR(x) ((x) + 0x22CU) - -#define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x)) -#define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P65TO127_TXPKTS. */ -#define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS. */ -#define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */ -#define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_p128to255 -{ - uint32_t U; - struct _hw_enet_rmon_t_p128to255_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p128to255_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P128TO255 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P128TO255_ADDR(x) ((x) + 0x230U) - -#define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x)) -#define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P128TO255_TXPKTS. */ -#define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS. */ -#define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */ -#define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_p256to511 -{ - uint32_t U; - struct _hw_enet_rmon_t_p256to511_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p256to511_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P256TO511 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P256TO511_ADDR(x) ((x) + 0x234U) - -#define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x)) -#define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P256TO511_TXPKTS. */ -#define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS. */ -#define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */ -#define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - * - * . - */ -typedef union _hw_enet_rmon_t_p512to1023 -{ - uint32_t U; - struct _hw_enet_rmon_t_p512to1023_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p512to1023_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P512TO1023_ADDR(x) ((x) + 0x238U) - -#define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x)) -#define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS. */ -#define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS. */ -#define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */ -#define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_p1024to2047 -{ - uint32_t U; - struct _hw_enet_rmon_t_p1024to2047_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p1024to2047_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P1024TO2047_ADDR(x) ((x) + 0x23CU) - -#define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x)) -#define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS. */ -#define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS. */ -#define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */ -#define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_p_gte2048 -{ - uint32_t U; - struct _hw_enet_rmon_t_p_gte2048_bitfields - { - uint32_t TXPKTS : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_t_p_gte2048_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register - */ -/*@{*/ -#define HW_ENET_RMON_T_P_GTE2048_ADDR(x) ((x) + 0x240U) - -#define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x)) -#define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields - */ - -/*! - * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS. */ -#define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS. */ -#define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS. */ - -/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */ -#define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_t_octets -{ - uint32_t U; - struct _hw_enet_rmon_t_octets_bitfields - { - uint32_t TXOCTS : 32; /*!< [31:0] Octet count */ - } B; -} hw_enet_rmon_t_octets_t; - -/*! - * @name Constants and macros for entire ENET_RMON_T_OCTETS register - */ -/*@{*/ -#define HW_ENET_RMON_T_OCTETS_ADDR(x) ((x) + 0x244U) - -#define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x)) -#define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_T_OCTETS bitfields - */ - -/*! - * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) /*!< Bit position for ENET_RMON_T_OCTETS_TXOCTS. */ -#define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS. */ -#define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) /*!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS. */ - -/*! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field. */ -#define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_frame_ok -{ - uint32_t U; - struct _hw_enet_ieee_t_frame_ok_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_frame_ok_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register - */ -/*@{*/ -#define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) ((x) + 0x24CU) - -#define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x)) -#define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields - */ - -/*! - * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT. */ -#define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT. */ -#define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */ -#define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_1col -{ - uint32_t U; - struct _hw_enet_ieee_t_1col_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_1col_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_1COL register - */ -/*@{*/ -#define HW_ENET_IEEE_T_1COL_ADDR(x) ((x) + 0x250U) - -#define HW_ENET_IEEE_T_1COL(x) (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x)) -#define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_1COL bitfields - */ - -/*! - * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_1COL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_1COL_COUNT. */ -#define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_1COL_COUNT. */ -#define BS_ENET_IEEE_T_1COL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */ -#define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_mcol -{ - uint32_t U; - struct _hw_enet_ieee_t_mcol_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_mcol_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_MCOL register - */ -/*@{*/ -#define HW_ENET_IEEE_T_MCOL_ADDR(x) ((x) + 0x254U) - -#define HW_ENET_IEEE_T_MCOL(x) (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x)) -#define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_MCOL bitfields - */ - -/*! - * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_MCOL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_MCOL_COUNT. */ -#define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MCOL_COUNT. */ -#define BS_ENET_IEEE_T_MCOL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */ -#define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_def -{ - uint32_t U; - struct _hw_enet_ieee_t_def_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_def_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_DEF register - */ -/*@{*/ -#define HW_ENET_IEEE_T_DEF_ADDR(x) ((x) + 0x258U) - -#define HW_ENET_IEEE_T_DEF(x) (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x)) -#define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_DEF bitfields - */ - -/*! - * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_DEF_COUNT (0U) /*!< Bit position for ENET_IEEE_T_DEF_COUNT. */ -#define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_DEF_COUNT. */ -#define BS_ENET_IEEE_T_DEF_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */ -#define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_lcol -{ - uint32_t U; - struct _hw_enet_ieee_t_lcol_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_lcol_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_LCOL register - */ -/*@{*/ -#define HW_ENET_IEEE_T_LCOL_ADDR(x) ((x) + 0x25CU) - -#define HW_ENET_IEEE_T_LCOL(x) (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x)) -#define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_LCOL bitfields - */ - -/*! - * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_LCOL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_LCOL_COUNT. */ -#define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_LCOL_COUNT. */ -#define BS_ENET_IEEE_T_LCOL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */ -#define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_excol -{ - uint32_t U; - struct _hw_enet_ieee_t_excol_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_excol_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_EXCOL register - */ -/*@{*/ -#define HW_ENET_IEEE_T_EXCOL_ADDR(x) ((x) + 0x260U) - -#define HW_ENET_IEEE_T_EXCOL(x) (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x)) -#define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields - */ - -/*! - * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_EXCOL_COUNT (0U) /*!< Bit position for ENET_IEEE_T_EXCOL_COUNT. */ -#define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_EXCOL_COUNT. */ -#define BS_ENET_IEEE_T_EXCOL_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */ -#define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_macerr -{ - uint32_t U; - struct _hw_enet_ieee_t_macerr_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_macerr_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_MACERR register - */ -/*@{*/ -#define HW_ENET_IEEE_T_MACERR_ADDR(x) ((x) + 0x264U) - -#define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x)) -#define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_MACERR bitfields - */ - -/*! - * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_MACERR_COUNT (0U) /*!< Bit position for ENET_IEEE_T_MACERR_COUNT. */ -#define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MACERR_COUNT. */ -#define BS_ENET_IEEE_T_MACERR_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */ -#define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_cserr -{ - uint32_t U; - struct _hw_enet_ieee_t_cserr_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_cserr_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_CSERR register - */ -/*@{*/ -#define HW_ENET_IEEE_T_CSERR_ADDR(x) ((x) + 0x268U) - -#define HW_ENET_IEEE_T_CSERR(x) (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x)) -#define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_CSERR bitfields - */ - -/*! - * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_CSERR_COUNT (0U) /*!< Bit position for ENET_IEEE_T_CSERR_COUNT. */ -#define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_CSERR_COUNT. */ -#define BS_ENET_IEEE_T_CSERR_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */ -#define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_t_fdxfc -{ - uint32_t U; - struct _hw_enet_ieee_t_fdxfc_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_t_fdxfc_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_FDXFC register - */ -/*@{*/ -#define HW_ENET_IEEE_T_FDXFC_ADDR(x) ((x) + 0x270U) - -#define HW_ENET_IEEE_T_FDXFC(x) (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x)) -#define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields - */ - -/*! - * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_FDXFC_COUNT (0U) /*!< Bit position for ENET_IEEE_T_FDXFC_COUNT. */ -#define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FDXFC_COUNT. */ -#define BS_ENET_IEEE_T_FDXFC_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */ -#define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO) - * - * Reset value: 0x00000000U - * - * Counts total octets (includes header and FCS fields). - */ -typedef union _hw_enet_ieee_t_octets_ok -{ - uint32_t U; - struct _hw_enet_ieee_t_octets_ok_bitfields - { - uint32_t COUNT : 32; /*!< [31:0] Octet count */ - } B; -} hw_enet_ieee_t_octets_ok_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register - */ -/*@{*/ -#define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) ((x) + 0x274U) - -#define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x)) -#define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields - */ - -/*! - * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT. */ -#define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT. */ -#define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field. */ -#define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_packets -{ - uint32_t U; - struct _hw_enet_rmon_r_packets_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_packets_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_PACKETS register - */ -/*@{*/ -#define HW_ENET_RMON_R_PACKETS_ADDR(x) ((x) + 0x284U) - -#define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x)) -#define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_PACKETS bitfields - */ - -/*! - * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_PACKETS_COUNT (0U) /*!< Bit position for ENET_RMON_R_PACKETS_COUNT. */ -#define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_PACKETS_COUNT. */ -#define BS_ENET_RMON_R_PACKETS_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */ -#define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_bc_pkt -{ - uint32_t U; - struct _hw_enet_rmon_r_bc_pkt_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_bc_pkt_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_BC_PKT register - */ -/*@{*/ -#define HW_ENET_RMON_R_BC_PKT_ADDR(x) ((x) + 0x288U) - -#define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x)) -#define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields - */ - -/*! - * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_BC_PKT_COUNT (0U) /*!< Bit position for ENET_RMON_R_BC_PKT_COUNT. */ -#define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_BC_PKT_COUNT. */ -#define BS_ENET_RMON_R_BC_PKT_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */ -#define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_mc_pkt -{ - uint32_t U; - struct _hw_enet_rmon_r_mc_pkt_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_mc_pkt_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_MC_PKT register - */ -/*@{*/ -#define HW_ENET_RMON_R_MC_PKT_ADDR(x) ((x) + 0x28CU) - -#define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x)) -#define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields - */ - -/*! - * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_MC_PKT_COUNT (0U) /*!< Bit position for ENET_RMON_R_MC_PKT_COUNT. */ -#define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_MC_PKT_COUNT. */ -#define BS_ENET_RMON_R_MC_PKT_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */ -#define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_crc_align -{ - uint32_t U; - struct _hw_enet_rmon_r_crc_align_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_crc_align_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register - */ -/*@{*/ -#define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) ((x) + 0x290U) - -#define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x)) -#define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields - */ - -/*! - * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) /*!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT. */ -#define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT. */ -#define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */ -#define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_undersize -{ - uint32_t U; - struct _hw_enet_rmon_r_undersize_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_undersize_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register - */ -/*@{*/ -#define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) ((x) + 0x294U) - -#define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x)) -#define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields - */ - -/*! - * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT. */ -#define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT. */ -#define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */ -#define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_oversize -{ - uint32_t U; - struct _hw_enet_rmon_r_oversize_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_oversize_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register - */ -/*@{*/ -#define HW_ENET_RMON_R_OVERSIZE_ADDR(x) ((x) + 0x298U) - -#define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x)) -#define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields - */ - -/*! - * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_OVERSIZE_COUNT. */ -#define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT. */ -#define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */ -#define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_frag -{ - uint32_t U; - struct _hw_enet_rmon_r_frag_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_frag_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_FRAG register - */ -/*@{*/ -#define HW_ENET_RMON_R_FRAG_ADDR(x) ((x) + 0x29CU) - -#define HW_ENET_RMON_R_FRAG(x) (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x)) -#define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_FRAG bitfields - */ - -/*! - * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_FRAG_COUNT (0U) /*!< Bit position for ENET_RMON_R_FRAG_COUNT. */ -#define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_FRAG_COUNT. */ -#define BS_ENET_RMON_R_FRAG_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */ -#define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_jab -{ - uint32_t U; - struct _hw_enet_rmon_r_jab_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_jab_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_JAB register - */ -/*@{*/ -#define HW_ENET_RMON_R_JAB_ADDR(x) ((x) + 0x2A0U) - -#define HW_ENET_RMON_R_JAB(x) (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x)) -#define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_JAB bitfields - */ - -/*! - * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_JAB_COUNT (0U) /*!< Bit position for ENET_RMON_R_JAB_COUNT. */ -#define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_JAB_COUNT. */ -#define BS_ENET_RMON_R_JAB_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_JAB_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */ -#define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p64 -{ - uint32_t U; - struct _hw_enet_rmon_r_p64_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p64_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P64 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P64_ADDR(x) ((x) + 0x2A8U) - -#define HW_ENET_RMON_R_P64(x) (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x)) -#define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P64 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P64_COUNT (0U) /*!< Bit position for ENET_RMON_R_P64_COUNT. */ -#define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P64_COUNT. */ -#define BS_ENET_RMON_R_P64_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P64_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */ -#define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p65to127 -{ - uint32_t U; - struct _hw_enet_rmon_r_p65to127_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p65to127_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P65TO127 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P65TO127_ADDR(x) ((x) + 0x2ACU) - -#define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x)) -#define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P65TO127_COUNT (0U) /*!< Bit position for ENET_RMON_R_P65TO127_COUNT. */ -#define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P65TO127_COUNT. */ -#define BS_ENET_RMON_R_P65TO127_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */ -#define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p128to255 -{ - uint32_t U; - struct _hw_enet_rmon_r_p128to255_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p128to255_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P128TO255 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P128TO255_ADDR(x) ((x) + 0x2B0U) - -#define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x)) -#define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P128TO255_COUNT (0U) /*!< Bit position for ENET_RMON_R_P128TO255_COUNT. */ -#define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P128TO255_COUNT. */ -#define BS_ENET_RMON_R_P128TO255_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */ -#define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p256to511 -{ - uint32_t U; - struct _hw_enet_rmon_r_p256to511_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p256to511_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P256TO511 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P256TO511_ADDR(x) ((x) + 0x2B4U) - -#define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x)) -#define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P256TO511_COUNT (0U) /*!< Bit position for ENET_RMON_R_P256TO511_COUNT. */ -#define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P256TO511_COUNT. */ -#define BS_ENET_RMON_R_P256TO511_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */ -#define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p512to1023 -{ - uint32_t U; - struct _hw_enet_rmon_r_p512to1023_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p512to1023_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P512TO1023_ADDR(x) ((x) + 0x2B8U) - -#define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x)) -#define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P512TO1023_COUNT (0U) /*!< Bit position for ENET_RMON_R_P512TO1023_COUNT. */ -#define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P512TO1023_COUNT. */ -#define BS_ENET_RMON_R_P512TO1023_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */ -#define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p1024to2047 -{ - uint32_t U; - struct _hw_enet_rmon_r_p1024to2047_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p1024to2047_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P1024TO2047_ADDR(x) ((x) + 0x2BCU) - -#define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x)) -#define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) /*!< Bit position for ENET_RMON_R_P1024TO2047_COUNT. */ -#define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT. */ -#define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */ -#define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_p_gte2048 -{ - uint32_t U; - struct _hw_enet_rmon_r_p_gte2048_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Packet count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_rmon_r_p_gte2048_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register - */ -/*@{*/ -#define HW_ENET_RMON_R_P_GTE2048_ADDR(x) ((x) + 0x2C0U) - -#define HW_ENET_RMON_R_P_GTE2048(x) (*(__I hw_enet_rmon_r_p_gte2048_t *) HW_ENET_RMON_R_P_GTE2048_ADDR(x)) -#define HW_ENET_RMON_R_P_GTE2048_RD(x) (HW_ENET_RMON_R_P_GTE2048(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields - */ - -/*! - * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_P_GTE2048_COUNT (0U) /*!< Bit position for ENET_RMON_R_P_GTE2048_COUNT. */ -#define BM_ENET_RMON_R_P_GTE2048_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P_GTE2048_COUNT. */ -#define BS_ENET_RMON_R_P_GTE2048_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P_GTE2048_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */ -#define BR_ENET_RMON_R_P_GTE2048_COUNT(x) (HW_ENET_RMON_R_P_GTE2048(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_rmon_r_octets -{ - uint32_t U; - struct _hw_enet_rmon_r_octets_bitfields - { - uint32_t COUNT : 32; /*!< [31:0] Octet count */ - } B; -} hw_enet_rmon_r_octets_t; - -/*! - * @name Constants and macros for entire ENET_RMON_R_OCTETS register - */ -/*@{*/ -#define HW_ENET_RMON_R_OCTETS_ADDR(x) ((x) + 0x2C4U) - -#define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x)) -#define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_RMON_R_OCTETS bitfields - */ - -/*! - * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO) - */ -/*@{*/ -#define BP_ENET_RMON_R_OCTETS_COUNT (0U) /*!< Bit position for ENET_RMON_R_OCTETS_COUNT. */ -#define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_R_OCTETS_COUNT. */ -#define BS_ENET_RMON_R_OCTETS_COUNT (32U) /*!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT. */ - -/*! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field. */ -#define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO) - * - * Reset value: 0x00000000U - * - * Counter increments if a frame with invalid or missing SFD character is - * detected and has been dropped. None of the other counters increments if this counter - * increments. - */ -typedef union _hw_enet_ieee_r_drop -{ - uint32_t U; - struct _hw_enet_ieee_r_drop_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_r_drop_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_DROP register - */ -/*@{*/ -#define HW_ENET_IEEE_R_DROP_ADDR(x) ((x) + 0x2C8U) - -#define HW_ENET_IEEE_R_DROP(x) (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x)) -#define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_DROP bitfields - */ - -/*! - * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_DROP_COUNT (0U) /*!< Bit position for ENET_IEEE_R_DROP_COUNT. */ -#define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_DROP_COUNT. */ -#define BS_ENET_IEEE_R_DROP_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */ -#define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_r_frame_ok -{ - uint32_t U; - struct _hw_enet_ieee_r_frame_ok_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_r_frame_ok_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register - */ -/*@{*/ -#define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) ((x) + 0x2CCU) - -#define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x)) -#define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields - */ - -/*! - * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT. */ -#define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT. */ -#define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */ -#define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_r_crc -{ - uint32_t U; - struct _hw_enet_ieee_r_crc_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_r_crc_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_CRC register - */ -/*@{*/ -#define HW_ENET_IEEE_R_CRC_ADDR(x) ((x) + 0x2D0U) - -#define HW_ENET_IEEE_R_CRC(x) (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x)) -#define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_CRC bitfields - */ - -/*! - * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_CRC_COUNT (0U) /*!< Bit position for ENET_IEEE_R_CRC_COUNT. */ -#define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_CRC_COUNT. */ -#define BS_ENET_IEEE_R_CRC_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */ -#define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_r_align -{ - uint32_t U; - struct _hw_enet_ieee_r_align_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_r_align_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_ALIGN register - */ -/*@{*/ -#define HW_ENET_IEEE_R_ALIGN_ADDR(x) ((x) + 0x2D4U) - -#define HW_ENET_IEEE_R_ALIGN(x) (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x)) -#define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields - */ - -/*! - * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_ALIGN_COUNT (0U) /*!< Bit position for ENET_IEEE_R_ALIGN_COUNT. */ -#define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_ALIGN_COUNT. */ -#define BS_ENET_IEEE_R_ALIGN_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */ -#define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_r_macerr -{ - uint32_t U; - struct _hw_enet_ieee_r_macerr_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_r_macerr_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_MACERR register - */ -/*@{*/ -#define HW_ENET_IEEE_R_MACERR_ADDR(x) ((x) + 0x2D8U) - -#define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x)) -#define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_MACERR bitfields - */ - -/*! - * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_MACERR_COUNT (0U) /*!< Bit position for ENET_IEEE_R_MACERR_COUNT. */ -#define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_MACERR_COUNT. */ -#define BS_ENET_IEEE_R_MACERR_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */ -#define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_r_fdxfc -{ - uint32_t U; - struct _hw_enet_ieee_r_fdxfc_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Pause frame count */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_enet_ieee_r_fdxfc_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_FDXFC register - */ -/*@{*/ -#define HW_ENET_IEEE_R_FDXFC_ADDR(x) ((x) + 0x2DCU) - -#define HW_ENET_IEEE_R_FDXFC(x) (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x)) -#define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields - */ - -/*! - * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_FDXFC_COUNT (0U) /*!< Bit position for ENET_IEEE_R_FDXFC_COUNT. */ -#define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FDXFC_COUNT. */ -#define BS_ENET_IEEE_R_FDXFC_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */ -#define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT) -/*@}*/ - -/******************************************************************************* - * HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_ieee_r_octets_ok -{ - uint32_t U; - struct _hw_enet_ieee_r_octets_ok_bitfields - { - uint32_t COUNT : 32; /*!< [31:0] Octet count */ - } B; -} hw_enet_ieee_r_octets_ok_t; - -/*! - * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register - */ -/*@{*/ -#define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) ((x) + 0x2E0U) - -#define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x)) -#define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields - */ - -/*! - * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO) - */ -/*@{*/ -#define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT. */ -#define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT. */ -#define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT. */ - -/*! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field. */ -#define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATCR - Adjustable Timer Control Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW) - * - * Reset value: 0x00000000U - * - * ATCR command fields can trigger the corresponding events directly. It is not - * necessary to preserve any of the configuration fields when a command field is - * set in the register, that is, no read-modify-write is required. The fields are - * automatically cleared after the command completes. - */ -typedef union _hw_enet_atcr -{ - uint32_t U; - struct _hw_enet_atcr_bitfields - { - uint32_t EN : 1; /*!< [0] Enable Timer */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t OFFEN : 1; /*!< [2] Enable One-Shot Offset Event */ - uint32_t OFFRST : 1; /*!< [3] Reset Timer On Offset Event */ - uint32_t PEREN : 1; /*!< [4] Enable Periodical Event */ - uint32_t RESERVED1 : 2; /*!< [6:5] */ - uint32_t PINPER : 1; /*!< [7] */ - uint32_t RESERVED2 : 1; /*!< [8] */ - uint32_t RESTART : 1; /*!< [9] Reset Timer */ - uint32_t RESERVED3 : 1; /*!< [10] */ - uint32_t CAPTURE : 1; /*!< [11] Capture Timer Value */ - uint32_t RESERVED4 : 1; /*!< [12] */ - uint32_t SLAVE : 1; /*!< [13] Enable Timer Slave Mode */ - uint32_t RESERVED5 : 18; /*!< [31:14] */ - } B; -} hw_enet_atcr_t; - -/*! - * @name Constants and macros for entire ENET_ATCR register - */ -/*@{*/ -#define HW_ENET_ATCR_ADDR(x) ((x) + 0x400U) - -#define HW_ENET_ATCR(x) (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x)) -#define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U) -#define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v)) -#define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) | (v))) -#define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v))) -#define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATCR bitfields - */ - -/*! - * @name Register ENET_ATCR, field EN[0] (RW) - * - * Values: - * - 0 - The timer stops at the current value. - * - 1 - The timer starts incrementing. - */ -/*@{*/ -#define BP_ENET_ATCR_EN (0U) /*!< Bit position for ENET_ATCR_EN. */ -#define BM_ENET_ATCR_EN (0x00000001U) /*!< Bit mask for ENET_ATCR_EN. */ -#define BS_ENET_ATCR_EN (1U) /*!< Bit field size in bits for ENET_ATCR_EN. */ - -/*! @brief Read current value of the ENET_ATCR_EN field. */ -#define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN)) - -/*! @brief Format value for bitfield ENET_ATCR_EN. */ -#define BF_ENET_ATCR_EN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_EN) & BM_ENET_ATCR_EN) - -/*! @brief Set the EN field to a new value. */ -#define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field OFFEN[2] (RW) - * - * Values: - * - 0 - Disable. - * - 1 - The timer can be reset to zero when the given offset time is reached - * (offset event). The field is cleared when the offset event is reached, so no - * further event occurs until the field is set again. The timer offset value - * must be set before setting this field. - */ -/*@{*/ -#define BP_ENET_ATCR_OFFEN (2U) /*!< Bit position for ENET_ATCR_OFFEN. */ -#define BM_ENET_ATCR_OFFEN (0x00000004U) /*!< Bit mask for ENET_ATCR_OFFEN. */ -#define BS_ENET_ATCR_OFFEN (1U) /*!< Bit field size in bits for ENET_ATCR_OFFEN. */ - -/*! @brief Read current value of the ENET_ATCR_OFFEN field. */ -#define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN)) - -/*! @brief Format value for bitfield ENET_ATCR_OFFEN. */ -#define BF_ENET_ATCR_OFFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFEN) & BM_ENET_ATCR_OFFEN) - -/*! @brief Set the OFFEN field to a new value. */ -#define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field OFFRST[3] (RW) - * - * Values: - * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN, - * when the offset is reached. - * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is - * reached. The offset event does not cause a timer interrupt. - */ -/*@{*/ -#define BP_ENET_ATCR_OFFRST (3U) /*!< Bit position for ENET_ATCR_OFFRST. */ -#define BM_ENET_ATCR_OFFRST (0x00000008U) /*!< Bit mask for ENET_ATCR_OFFRST. */ -#define BS_ENET_ATCR_OFFRST (1U) /*!< Bit field size in bits for ENET_ATCR_OFFRST. */ - -/*! @brief Read current value of the ENET_ATCR_OFFRST field. */ -#define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST)) - -/*! @brief Format value for bitfield ENET_ATCR_OFFRST. */ -#define BF_ENET_ATCR_OFFRST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFRST) & BM_ENET_ATCR_OFFRST) - -/*! @brief Set the OFFRST field to a new value. */ -#define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field PEREN[4] (RW) - * - * Values: - * - 0 - Disable. - * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event - * signal output is asserted when the timer wraps around according to the - * periodic setting ATPER. The timer period value must be set before setting - * this bit. Not all devices contain the event signal output. See the chip - * configuration details. - */ -/*@{*/ -#define BP_ENET_ATCR_PEREN (4U) /*!< Bit position for ENET_ATCR_PEREN. */ -#define BM_ENET_ATCR_PEREN (0x00000010U) /*!< Bit mask for ENET_ATCR_PEREN. */ -#define BS_ENET_ATCR_PEREN (1U) /*!< Bit field size in bits for ENET_ATCR_PEREN. */ - -/*! @brief Read current value of the ENET_ATCR_PEREN field. */ -#define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN)) - -/*! @brief Format value for bitfield ENET_ATCR_PEREN. */ -#define BF_ENET_ATCR_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PEREN) & BM_ENET_ATCR_PEREN) - -/*! @brief Set the PEREN field to a new value. */ -#define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field PINPER[7] (RW) - * - * Enables event signal output assertion on period event. Not all devices - * contain the event signal output. See the chip configuration details. - * - * Values: - * - 0 - Disable. - * - 1 - Enable. - */ -/*@{*/ -#define BP_ENET_ATCR_PINPER (7U) /*!< Bit position for ENET_ATCR_PINPER. */ -#define BM_ENET_ATCR_PINPER (0x00000080U) /*!< Bit mask for ENET_ATCR_PINPER. */ -#define BS_ENET_ATCR_PINPER (1U) /*!< Bit field size in bits for ENET_ATCR_PINPER. */ - -/*! @brief Read current value of the ENET_ATCR_PINPER field. */ -#define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER)) - -/*! @brief Format value for bitfield ENET_ATCR_PINPER. */ -#define BF_ENET_ATCR_PINPER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PINPER) & BM_ENET_ATCR_PINPER) - -/*! @brief Set the PINPER field to a new value. */ -#define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field RESTART[9] (RW) - * - * Resets the timer to zero. This has no effect on the counter enable. If the - * counter is enabled when this field is set, the timer is reset to zero and starts - * counting from there. When set, all other fields are ignored during a write. - */ -/*@{*/ -#define BP_ENET_ATCR_RESTART (9U) /*!< Bit position for ENET_ATCR_RESTART. */ -#define BM_ENET_ATCR_RESTART (0x00000200U) /*!< Bit mask for ENET_ATCR_RESTART. */ -#define BS_ENET_ATCR_RESTART (1U) /*!< Bit field size in bits for ENET_ATCR_RESTART. */ - -/*! @brief Read current value of the ENET_ATCR_RESTART field. */ -#define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART)) - -/*! @brief Format value for bitfield ENET_ATCR_RESTART. */ -#define BF_ENET_ATCR_RESTART(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_RESTART) & BM_ENET_ATCR_RESTART) - -/*! @brief Set the RESTART field to a new value. */ -#define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field CAPTURE[11] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - The current time is captured and can be read from the ATVR register. - */ -/*@{*/ -#define BP_ENET_ATCR_CAPTURE (11U) /*!< Bit position for ENET_ATCR_CAPTURE. */ -#define BM_ENET_ATCR_CAPTURE (0x00000800U) /*!< Bit mask for ENET_ATCR_CAPTURE. */ -#define BS_ENET_ATCR_CAPTURE (1U) /*!< Bit field size in bits for ENET_ATCR_CAPTURE. */ - -/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */ -#define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE)) - -/*! @brief Format value for bitfield ENET_ATCR_CAPTURE. */ -#define BF_ENET_ATCR_CAPTURE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_CAPTURE) & BM_ENET_ATCR_CAPTURE) - -/*! @brief Set the CAPTURE field to a new value. */ -#define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_ATCR, field SLAVE[13] (RW) - * - * Values: - * - 0 - The timer is active and all configuration fields in this register are - * relevant. - * - 1 - The internal timer is disabled and the externally provided timer value - * is used. All other fields, except CAPTURE, in this register have no - * effect. CAPTURE can still be used to capture the current timer value. - */ -/*@{*/ -#define BP_ENET_ATCR_SLAVE (13U) /*!< Bit position for ENET_ATCR_SLAVE. */ -#define BM_ENET_ATCR_SLAVE (0x00002000U) /*!< Bit mask for ENET_ATCR_SLAVE. */ -#define BS_ENET_ATCR_SLAVE (1U) /*!< Bit field size in bits for ENET_ATCR_SLAVE. */ - -/*! @brief Read current value of the ENET_ATCR_SLAVE field. */ -#define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE)) - -/*! @brief Format value for bitfield ENET_ATCR_SLAVE. */ -#define BF_ENET_ATCR_SLAVE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_SLAVE) & BM_ENET_ATCR_SLAVE) - -/*! @brief Set the SLAVE field to a new value. */ -#define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATVR - Timer Value Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATVR - Timer Value Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_atvr -{ - uint32_t U; - struct _hw_enet_atvr_bitfields - { - uint32_t ATIME : 32; /*!< [31:0] */ - } B; -} hw_enet_atvr_t; - -/*! - * @name Constants and macros for entire ENET_ATVR register - */ -/*@{*/ -#define HW_ENET_ATVR_ADDR(x) ((x) + 0x404U) - -#define HW_ENET_ATVR(x) (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x)) -#define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U) -#define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v)) -#define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) | (v))) -#define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v))) -#define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATVR bitfields - */ - -/*! - * @name Register ENET_ATVR, field ATIME[31:0] (RW) - * - * A write sets the timer. A read returns the last captured value. To read the - * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading - * this register. - */ -/*@{*/ -#define BP_ENET_ATVR_ATIME (0U) /*!< Bit position for ENET_ATVR_ATIME. */ -#define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) /*!< Bit mask for ENET_ATVR_ATIME. */ -#define BS_ENET_ATVR_ATIME (32U) /*!< Bit field size in bits for ENET_ATVR_ATIME. */ - -/*! @brief Read current value of the ENET_ATVR_ATIME field. */ -#define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U) - -/*! @brief Format value for bitfield ENET_ATVR_ATIME. */ -#define BF_ENET_ATVR_ATIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATVR_ATIME) & BM_ENET_ATVR_ATIME) - -/*! @brief Set the ATIME field to a new value. */ -#define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATOFF - Timer Offset Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATOFF - Timer Offset Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_atoff -{ - uint32_t U; - struct _hw_enet_atoff_bitfields - { - uint32_t OFFSET : 32; /*!< [31:0] */ - } B; -} hw_enet_atoff_t; - -/*! - * @name Constants and macros for entire ENET_ATOFF register - */ -/*@{*/ -#define HW_ENET_ATOFF_ADDR(x) ((x) + 0x408U) - -#define HW_ENET_ATOFF(x) (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x)) -#define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U) -#define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v)) -#define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) | (v))) -#define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v))) -#define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATOFF bitfields - */ - -/*! - * @name Register ENET_ATOFF, field OFFSET[31:0] (RW) - * - * Offset value for one-shot event generation. When the timer reaches the value, - * an event can be generated to reset the counter. If the increment value in - * ATINC is given in true nanoseconds, this value is also given in true nanoseconds. - */ -/*@{*/ -#define BP_ENET_ATOFF_OFFSET (0U) /*!< Bit position for ENET_ATOFF_OFFSET. */ -#define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) /*!< Bit mask for ENET_ATOFF_OFFSET. */ -#define BS_ENET_ATOFF_OFFSET (32U) /*!< Bit field size in bits for ENET_ATOFF_OFFSET. */ - -/*! @brief Read current value of the ENET_ATOFF_OFFSET field. */ -#define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U) - -/*! @brief Format value for bitfield ENET_ATOFF_OFFSET. */ -#define BF_ENET_ATOFF_OFFSET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATOFF_OFFSET) & BM_ENET_ATOFF_OFFSET) - -/*! @brief Set the OFFSET field to a new value. */ -#define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATPER - Timer Period Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATPER - Timer Period Register (RW) - * - * Reset value: 0x3B9ACA00U - */ -typedef union _hw_enet_atper -{ - uint32_t U; - struct _hw_enet_atper_bitfields - { - uint32_t PERIOD : 32; /*!< [31:0] */ - } B; -} hw_enet_atper_t; - -/*! - * @name Constants and macros for entire ENET_ATPER register - */ -/*@{*/ -#define HW_ENET_ATPER_ADDR(x) ((x) + 0x40CU) - -#define HW_ENET_ATPER(x) (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x)) -#define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U) -#define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v)) -#define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) | (v))) -#define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v))) -#define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATPER bitfields - */ - -/*! - * @name Register ENET_ATPER, field PERIOD[31:0] (RW) - * - * Value for generating periodic events. Each instance the timer reaches this - * value, the period event occurs and the timer restarts. If the increment value in - * ATINC is given in true nanoseconds, this value is also given in true - * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent - * a timer wrap around of one second. The increment value set in ATINC should be - * set to the true nanoseconds of the period of clock ts_clk, hence implementing - * a true 1 second counter. - */ -/*@{*/ -#define BP_ENET_ATPER_PERIOD (0U) /*!< Bit position for ENET_ATPER_PERIOD. */ -#define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) /*!< Bit mask for ENET_ATPER_PERIOD. */ -#define BS_ENET_ATPER_PERIOD (32U) /*!< Bit field size in bits for ENET_ATPER_PERIOD. */ - -/*! @brief Read current value of the ENET_ATPER_PERIOD field. */ -#define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U) - -/*! @brief Format value for bitfield ENET_ATPER_PERIOD. */ -#define BF_ENET_ATPER_PERIOD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATPER_PERIOD) & BM_ENET_ATPER_PERIOD) - -/*! @brief Set the PERIOD field to a new value. */ -#define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATCOR - Timer Correction Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATCOR - Timer Correction Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_atcor -{ - uint32_t U; - struct _hw_enet_atcor_bitfields - { - uint32_t COR : 31; /*!< [30:0] Correction Counter Wrap-Around Value */ - uint32_t RESERVED0 : 1; /*!< [31] */ - } B; -} hw_enet_atcor_t; - -/*! - * @name Constants and macros for entire ENET_ATCOR register - */ -/*@{*/ -#define HW_ENET_ATCOR_ADDR(x) ((x) + 0x410U) - -#define HW_ENET_ATCOR(x) (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x)) -#define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U) -#define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v)) -#define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) | (v))) -#define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v))) -#define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATCOR bitfields - */ - -/*! - * @name Register ENET_ATCOR, field COR[30:0] (RW) - * - * Defines after how many timer clock cycles (ts_clk) the correction counter - * should be reset and trigger a correction increment on the timer. The amount of - * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction - * counter and no corrections occur. This value is given in clock cycles, not in - * nanoseconds as all other values. - */ -/*@{*/ -#define BP_ENET_ATCOR_COR (0U) /*!< Bit position for ENET_ATCOR_COR. */ -#define BM_ENET_ATCOR_COR (0x7FFFFFFFU) /*!< Bit mask for ENET_ATCOR_COR. */ -#define BS_ENET_ATCOR_COR (31U) /*!< Bit field size in bits for ENET_ATCOR_COR. */ - -/*! @brief Read current value of the ENET_ATCOR_COR field. */ -#define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR) - -/*! @brief Format value for bitfield ENET_ATCOR_COR. */ -#define BF_ENET_ATCOR_COR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCOR_COR) & BM_ENET_ATCOR_COR) - -/*! @brief Set the COR field to a new value. */ -#define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATINC - Time-Stamping Clock Period Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_atinc -{ - uint32_t U; - struct _hw_enet_atinc_bitfields - { - uint32_t INC : 7; /*!< [6:0] Clock Period Of The Timestamping Clock - * (ts_clk) In Nanoseconds */ - uint32_t RESERVED0 : 1; /*!< [7] */ - uint32_t INC_CORR : 7; /*!< [14:8] Correction Increment Value */ - uint32_t RESERVED1 : 17; /*!< [31:15] */ - } B; -} hw_enet_atinc_t; - -/*! - * @name Constants and macros for entire ENET_ATINC register - */ -/*@{*/ -#define HW_ENET_ATINC_ADDR(x) ((x) + 0x414U) - -#define HW_ENET_ATINC(x) (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x)) -#define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U) -#define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v)) -#define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) | (v))) -#define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v))) -#define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATINC bitfields - */ - -/*! - * @name Register ENET_ATINC, field INC[6:0] (RW) - * - * The timer increments by this amount each clock cycle. For example, set to 10 - * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value - * that is an integer fraction of the period set in ATPER. - */ -/*@{*/ -#define BP_ENET_ATINC_INC (0U) /*!< Bit position for ENET_ATINC_INC. */ -#define BM_ENET_ATINC_INC (0x0000007FU) /*!< Bit mask for ENET_ATINC_INC. */ -#define BS_ENET_ATINC_INC (7U) /*!< Bit field size in bits for ENET_ATINC_INC. */ - -/*! @brief Read current value of the ENET_ATINC_INC field. */ -#define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC) - -/*! @brief Format value for bitfield ENET_ATINC_INC. */ -#define BF_ENET_ATINC_INC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC) & BM_ENET_ATINC_INC) - -/*! @brief Set the INC field to a new value. */ -#define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v))) -/*@}*/ - -/*! - * @name Register ENET_ATINC, field INC_CORR[14:8] (RW) - * - * This value is added every time the correction timer expires (every clock - * cycle given in ATCOR). A value less than INC slows down the timer. A value greater - * than INC speeds up the timer. - */ -/*@{*/ -#define BP_ENET_ATINC_INC_CORR (8U) /*!< Bit position for ENET_ATINC_INC_CORR. */ -#define BM_ENET_ATINC_INC_CORR (0x00007F00U) /*!< Bit mask for ENET_ATINC_INC_CORR. */ -#define BS_ENET_ATINC_INC_CORR (7U) /*!< Bit field size in bits for ENET_ATINC_INC_CORR. */ - -/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */ -#define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR) - -/*! @brief Format value for bitfield ENET_ATINC_INC_CORR. */ -#define BF_ENET_ATINC_INC_CORR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC_CORR) & BM_ENET_ATINC_INC_CORR) - -/*! @brief Set the INC_CORR field to a new value. */ -#define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v))) -/*@}*/ - -/******************************************************************************* - * HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame - ******************************************************************************/ - -/*! - * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_atstmp -{ - uint32_t U; - struct _hw_enet_atstmp_bitfields - { - uint32_t TIMESTAMP : 32; /*!< [31:0] */ - } B; -} hw_enet_atstmp_t; - -/*! - * @name Constants and macros for entire ENET_ATSTMP register - */ -/*@{*/ -#define HW_ENET_ATSTMP_ADDR(x) ((x) + 0x418U) - -#define HW_ENET_ATSTMP(x) (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x)) -#define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U) -/*@}*/ - -/* - * Constants & macros for individual ENET_ATSTMP bitfields - */ - -/*! - * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO) - * - * Timestamp of the last frame transmitted by the core that had TxBD[TS] set . - * This register is only valid when EIR[TS_AVAIL] is set. - */ -/*@{*/ -#define BP_ENET_ATSTMP_TIMESTAMP (0U) /*!< Bit position for ENET_ATSTMP_TIMESTAMP. */ -#define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) /*!< Bit mask for ENET_ATSTMP_TIMESTAMP. */ -#define BS_ENET_ATSTMP_TIMESTAMP (32U) /*!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP. */ - -/*! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field. */ -#define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TGSR - Timer Global Status Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TGSR - Timer Global Status Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_tgsr -{ - uint32_t U; - struct _hw_enet_tgsr_bitfields - { - uint32_t TF0 : 1; /*!< [0] Copy Of Timer Flag For Channel 0 */ - uint32_t TF1 : 1; /*!< [1] Copy Of Timer Flag For Channel 1 */ - uint32_t TF2 : 1; /*!< [2] Copy Of Timer Flag For Channel 2 */ - uint32_t TF3 : 1; /*!< [3] Copy Of Timer Flag For Channel 3 */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_enet_tgsr_t; - -/*! - * @name Constants and macros for entire ENET_TGSR register - */ -/*@{*/ -#define HW_ENET_TGSR_ADDR(x) ((x) + 0x604U) - -#define HW_ENET_TGSR(x) (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x)) -#define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U) -#define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v)) -#define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) | (v))) -#define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v))) -#define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TGSR bitfields - */ - -/*! - * @name Register ENET_TGSR, field TF0[0] (W1C) - * - * Values: - * - 0 - Timer Flag for Channel 0 is clear - * - 1 - Timer Flag for Channel 0 is set - */ -/*@{*/ -#define BP_ENET_TGSR_TF0 (0U) /*!< Bit position for ENET_TGSR_TF0. */ -#define BM_ENET_TGSR_TF0 (0x00000001U) /*!< Bit mask for ENET_TGSR_TF0. */ -#define BS_ENET_TGSR_TF0 (1U) /*!< Bit field size in bits for ENET_TGSR_TF0. */ - -/*! @brief Read current value of the ENET_TGSR_TF0 field. */ -#define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0)) - -/*! @brief Format value for bitfield ENET_TGSR_TF0. */ -#define BF_ENET_TGSR_TF0(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF0) & BM_ENET_TGSR_TF0) - -/*! @brief Set the TF0 field to a new value. */ -#define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TGSR, field TF1[1] (W1C) - * - * Values: - * - 0 - Timer Flag for Channel 1 is clear - * - 1 - Timer Flag for Channel 1 is set - */ -/*@{*/ -#define BP_ENET_TGSR_TF1 (1U) /*!< Bit position for ENET_TGSR_TF1. */ -#define BM_ENET_TGSR_TF1 (0x00000002U) /*!< Bit mask for ENET_TGSR_TF1. */ -#define BS_ENET_TGSR_TF1 (1U) /*!< Bit field size in bits for ENET_TGSR_TF1. */ - -/*! @brief Read current value of the ENET_TGSR_TF1 field. */ -#define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1)) - -/*! @brief Format value for bitfield ENET_TGSR_TF1. */ -#define BF_ENET_TGSR_TF1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF1) & BM_ENET_TGSR_TF1) - -/*! @brief Set the TF1 field to a new value. */ -#define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TGSR, field TF2[2] (W1C) - * - * Values: - * - 0 - Timer Flag for Channel 2 is clear - * - 1 - Timer Flag for Channel 2 is set - */ -/*@{*/ -#define BP_ENET_TGSR_TF2 (2U) /*!< Bit position for ENET_TGSR_TF2. */ -#define BM_ENET_TGSR_TF2 (0x00000004U) /*!< Bit mask for ENET_TGSR_TF2. */ -#define BS_ENET_TGSR_TF2 (1U) /*!< Bit field size in bits for ENET_TGSR_TF2. */ - -/*! @brief Read current value of the ENET_TGSR_TF2 field. */ -#define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2)) - -/*! @brief Format value for bitfield ENET_TGSR_TF2. */ -#define BF_ENET_TGSR_TF2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF2) & BM_ENET_TGSR_TF2) - -/*! @brief Set the TF2 field to a new value. */ -#define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TGSR, field TF3[3] (W1C) - * - * Values: - * - 0 - Timer Flag for Channel 3 is clear - * - 1 - Timer Flag for Channel 3 is set - */ -/*@{*/ -#define BP_ENET_TGSR_TF3 (3U) /*!< Bit position for ENET_TGSR_TF3. */ -#define BM_ENET_TGSR_TF3 (0x00000008U) /*!< Bit mask for ENET_TGSR_TF3. */ -#define BS_ENET_TGSR_TF3 (1U) /*!< Bit field size in bits for ENET_TGSR_TF3. */ - -/*! @brief Read current value of the ENET_TGSR_TF3 field. */ -#define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3)) - -/*! @brief Format value for bitfield ENET_TGSR_TF3. */ -#define BF_ENET_TGSR_TF3(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF3) & BM_ENET_TGSR_TF3) - -/*! @brief Set the TF3 field to a new value. */ -#define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_ENET_TCSRn - Timer Control Status Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TCSRn - Timer Control Status Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_tcsrn -{ - uint32_t U; - struct _hw_enet_tcsrn_bitfields - { - uint32_t TDRE : 1; /*!< [0] Timer DMA Request Enable */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t TMODE : 4; /*!< [5:2] Timer Mode */ - uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */ - uint32_t TF : 1; /*!< [7] Timer Flag */ - uint32_t RESERVED1 : 24; /*!< [31:8] */ - } B; -} hw_enet_tcsrn_t; - -/*! - * @name Constants and macros for entire ENET_TCSRn register - */ -/*@{*/ -#define HW_ENET_TCSRn_COUNT (4U) - -#define HW_ENET_TCSRn_ADDR(x, n) ((x) + 0x608U + (0x8U * (n))) - -#define HW_ENET_TCSRn(x, n) (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n)) -#define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U) -#define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v)) -#define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) | (v))) -#define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v))) -#define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TCSRn bitfields - */ - -/*! - * @name Register ENET_TCSRn, field TDRE[0] (RW) - * - * Values: - * - 0 - DMA request is disabled - * - 1 - DMA request is enabled - */ -/*@{*/ -#define BP_ENET_TCSRn_TDRE (0U) /*!< Bit position for ENET_TCSRn_TDRE. */ -#define BM_ENET_TCSRn_TDRE (0x00000001U) /*!< Bit mask for ENET_TCSRn_TDRE. */ -#define BS_ENET_TCSRn_TDRE (1U) /*!< Bit field size in bits for ENET_TCSRn_TDRE. */ - -/*! @brief Read current value of the ENET_TCSRn_TDRE field. */ -#define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE)) - -/*! @brief Format value for bitfield ENET_TCSRn_TDRE. */ -#define BF_ENET_TCSRn_TDRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TDRE) & BM_ENET_TCSRn_TDRE) - -/*! @brief Set the TDRE field to a new value. */ -#define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TCSRn, field TMODE[5:2] (RW) - * - * Updating the Timer Mode field takes a few cycles to register because it is - * synchronized to the 1588 clock. The version of Timer Mode returned on a read is - * from the 1588 clock domain. When changing Timer Mode, always disable the - * channel and read this register to verify the channel is disabled first. - * - * Values: - * - 0000 - Timer Channel is disabled. - * - 0001 - Timer Channel is configured for Input Capture on rising edge - * - 0010 - Timer Channel is configured for Input Capture on falling edge - * - 0011 - Timer Channel is configured for Input Capture on both edges - * - 0100 - Timer Channel is configured for Output Compare - software only - * - 0101 - Timer Channel is configured for Output Compare - toggle output on - * compare - * - 0110 - Timer Channel is configured for Output Compare - clear output on - * compare - * - 0111 - Timer Channel is configured for Output Compare - set output on - * compare - * - 1000 - Reserved - * - 1010 - Timer Channel is configured for Output Compare - clear output on - * compare, set output on overflow - * - 10x1 - Timer Channel is configured for Output Compare - set output on - * compare, clear output on overflow - * - 1100 - Reserved - * - 1110 - Timer Channel is configured for Output Compare - pulse output low on - * compare for one 1588 clock cycle - * - 1111 - Timer Channel is configured for Output Compare - pulse output high - * on compare for one 1588 clock cycle - */ -/*@{*/ -#define BP_ENET_TCSRn_TMODE (2U) /*!< Bit position for ENET_TCSRn_TMODE. */ -#define BM_ENET_TCSRn_TMODE (0x0000003CU) /*!< Bit mask for ENET_TCSRn_TMODE. */ -#define BS_ENET_TCSRn_TMODE (4U) /*!< Bit field size in bits for ENET_TCSRn_TMODE. */ - -/*! @brief Read current value of the ENET_TCSRn_TMODE field. */ -#define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE) - -/*! @brief Format value for bitfield ENET_TCSRn_TMODE. */ -#define BF_ENET_TCSRn_TMODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TMODE) & BM_ENET_TCSRn_TMODE) - -/*! @brief Set the TMODE field to a new value. */ -#define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v))) -/*@}*/ - -/*! - * @name Register ENET_TCSRn, field TIE[6] (RW) - * - * Values: - * - 0 - Interrupt is disabled - * - 1 - Interrupt is enabled - */ -/*@{*/ -#define BP_ENET_TCSRn_TIE (6U) /*!< Bit position for ENET_TCSRn_TIE. */ -#define BM_ENET_TCSRn_TIE (0x00000040U) /*!< Bit mask for ENET_TCSRn_TIE. */ -#define BS_ENET_TCSRn_TIE (1U) /*!< Bit field size in bits for ENET_TCSRn_TIE. */ - -/*! @brief Read current value of the ENET_TCSRn_TIE field. */ -#define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE)) - -/*! @brief Format value for bitfield ENET_TCSRn_TIE. */ -#define BF_ENET_TCSRn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TIE) & BM_ENET_TCSRn_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v)) -/*@}*/ - -/*! - * @name Register ENET_TCSRn, field TF[7] (W1C) - * - * Sets when input capture or output compare occurs. This flag is double - * buffered between the module clock and 1588 clock domains. When this field is 1, it - * can be cleared to 0 by writing 1 to it. - * - * Values: - * - 0 - Input Capture or Output Compare has not occurred - * - 1 - Input Capture or Output Compare has occurred - */ -/*@{*/ -#define BP_ENET_TCSRn_TF (7U) /*!< Bit position for ENET_TCSRn_TF. */ -#define BM_ENET_TCSRn_TF (0x00000080U) /*!< Bit mask for ENET_TCSRn_TF. */ -#define BS_ENET_TCSRn_TF (1U) /*!< Bit field size in bits for ENET_TCSRn_TF. */ - -/*! @brief Read current value of the ENET_TCSRn_TF field. */ -#define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF)) - -/*! @brief Format value for bitfield ENET_TCSRn_TF. */ -#define BF_ENET_TCSRn_TF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TF) & BM_ENET_TCSRn_TF) - -/*! @brief Set the TF field to a new value. */ -#define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v)) -/*@}*/ -/******************************************************************************* - * HW_ENET_TCCRn - Timer Compare Capture Register - ******************************************************************************/ - -/*! - * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_enet_tccrn -{ - uint32_t U; - struct _hw_enet_tccrn_bitfields - { - uint32_t TCC : 32; /*!< [31:0] Timer Capture Compare */ - } B; -} hw_enet_tccrn_t; - -/*! - * @name Constants and macros for entire ENET_TCCRn register - */ -/*@{*/ -#define HW_ENET_TCCRn_COUNT (4U) - -#define HW_ENET_TCCRn_ADDR(x, n) ((x) + 0x60CU + (0x8U * (n))) - -#define HW_ENET_TCCRn(x, n) (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n)) -#define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U) -#define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v)) -#define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) | (v))) -#define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v))) -#define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual ENET_TCCRn bitfields - */ - -/*! - * @name Register ENET_TCCRn, field TCC[31:0] (RW) - * - * This register is double buffered between the module clock and 1588 clock - * domains. When configured for compare, the 1588 clock domain updates with the value - * in the module clock domain whenever the Timer Channel is first enabled and on - * each subsequent compare. Write to this register with the first compare value - * before enabling the Timer Channel. When the Timer Channel is enabled, write - * the second compare value either immediately, or at least before the first - * compare occurs. After each compare, write the next compare value before the previous - * compare occurs and before clearing the Timer Flag. The compare occurs one - * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in - * the 1588 clock domain. If the compare value is less than the value of the - * 1588 Counter when the Timer Channel is first enabled, then the compare does not - * occur until following the next overflow of the 1588 Counter. If the compare - * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or - * the compare value is less than the value of the IEEE 1588 Counter after the - * overflow, then the compare occurs one 1588 clock cycle following the overflow. - * When configured for Capture, the value of the IEEE 1588 Counter is captured into - * the 1588 clock domain and then updated into the module clock domain, provided - * the Timer Flag is clear. Always read the capture value before clearing the - * Timer Flag. - */ -/*@{*/ -#define BP_ENET_TCCRn_TCC (0U) /*!< Bit position for ENET_TCCRn_TCC. */ -#define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) /*!< Bit mask for ENET_TCCRn_TCC. */ -#define BS_ENET_TCCRn_TCC (32U) /*!< Bit field size in bits for ENET_TCCRn_TCC. */ - -/*! @brief Read current value of the ENET_TCCRn_TCC field. */ -#define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U) - -/*! @brief Format value for bitfield ENET_TCCRn_TCC. */ -#define BF_ENET_TCCRn_TCC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCCRn_TCC) & BM_ENET_TCCRn_TCC) - -/*! @brief Set the TCC field to a new value. */ -#define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * hw_enet_t - module struct - ******************************************************************************/ -/*! - * @brief All ENET module registers. - */ -#pragma pack(1) -typedef struct _hw_enet -{ - uint8_t _reserved0[4]; - __IO hw_enet_eir_t EIR; /*!< [0x4] Interrupt Event Register */ - __IO hw_enet_eimr_t EIMR; /*!< [0x8] Interrupt Mask Register */ - uint8_t _reserved1[4]; - __IO hw_enet_rdar_t RDAR; /*!< [0x10] Receive Descriptor Active Register */ - __IO hw_enet_tdar_t TDAR; /*!< [0x14] Transmit Descriptor Active Register */ - uint8_t _reserved2[12]; - __IO hw_enet_ecr_t ECR; /*!< [0x24] Ethernet Control Register */ - uint8_t _reserved3[24]; - __IO hw_enet_mmfr_t MMFR; /*!< [0x40] MII Management Frame Register */ - __IO hw_enet_mscr_t MSCR; /*!< [0x44] MII Speed Control Register */ - uint8_t _reserved4[28]; - __IO hw_enet_mibc_t MIBC; /*!< [0x64] MIB Control Register */ - uint8_t _reserved5[28]; - __IO hw_enet_rcr_t RCR; /*!< [0x84] Receive Control Register */ - uint8_t _reserved6[60]; - __IO hw_enet_tcr_t TCR; /*!< [0xC4] Transmit Control Register */ - uint8_t _reserved7[28]; - __IO hw_enet_palr_t PALR; /*!< [0xE4] Physical Address Lower Register */ - __IO hw_enet_paur_t PAUR; /*!< [0xE8] Physical Address Upper Register */ - __IO hw_enet_opd_t OPD; /*!< [0xEC] Opcode/Pause Duration Register */ - uint8_t _reserved8[40]; - __IO hw_enet_iaur_t IAUR; /*!< [0x118] Descriptor Individual Upper Address Register */ - __IO hw_enet_ialr_t IALR; /*!< [0x11C] Descriptor Individual Lower Address Register */ - __IO hw_enet_gaur_t GAUR; /*!< [0x120] Descriptor Group Upper Address Register */ - __IO hw_enet_galr_t GALR; /*!< [0x124] Descriptor Group Lower Address Register */ - uint8_t _reserved9[28]; - __IO hw_enet_tfwr_t TFWR; /*!< [0x144] Transmit FIFO Watermark Register */ - uint8_t _reserved10[56]; - __IO hw_enet_rdsr_t RDSR; /*!< [0x180] Receive Descriptor Ring Start Register */ - __IO hw_enet_tdsr_t TDSR; /*!< [0x184] Transmit Buffer Descriptor Ring Start Register */ - __IO hw_enet_mrbr_t MRBR; /*!< [0x188] Maximum Receive Buffer Size Register */ - uint8_t _reserved11[4]; - __IO hw_enet_rsfl_t RSFL; /*!< [0x190] Receive FIFO Section Full Threshold */ - __IO hw_enet_rsem_t RSEM; /*!< [0x194] Receive FIFO Section Empty Threshold */ - __IO hw_enet_raem_t RAEM; /*!< [0x198] Receive FIFO Almost Empty Threshold */ - __IO hw_enet_rafl_t RAFL; /*!< [0x19C] Receive FIFO Almost Full Threshold */ - __IO hw_enet_tsem_t TSEM; /*!< [0x1A0] Transmit FIFO Section Empty Threshold */ - __IO hw_enet_taem_t TAEM; /*!< [0x1A4] Transmit FIFO Almost Empty Threshold */ - __IO hw_enet_tafl_t TAFL; /*!< [0x1A8] Transmit FIFO Almost Full Threshold */ - __IO hw_enet_tipg_t TIPG; /*!< [0x1AC] Transmit Inter-Packet Gap */ - __IO hw_enet_ftrl_t FTRL; /*!< [0x1B0] Frame Truncation Length */ - uint8_t _reserved12[12]; - __IO hw_enet_tacc_t TACC; /*!< [0x1C0] Transmit Accelerator Function Configuration */ - __IO hw_enet_racc_t RACC; /*!< [0x1C4] Receive Accelerator Function Configuration */ - uint8_t _reserved13[60]; - __I hw_enet_rmon_t_packets_t RMON_T_PACKETS; /*!< [0x204] Tx Packet Count Statistic Register */ - __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; /*!< [0x208] Tx Broadcast Packets Statistic Register */ - __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; /*!< [0x20C] Tx Multicast Packets Statistic Register */ - __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; /*!< [0x210] Tx Packets with CRC/Align Error Statistic Register */ - __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; /*!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register */ - __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; /*!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ - __I hw_enet_rmon_t_frag_t RMON_T_FRAG; /*!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ - __I hw_enet_rmon_t_jab_t RMON_T_JAB; /*!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ - __I hw_enet_rmon_t_col_t RMON_T_COL; /*!< [0x224] Tx Collision Count Statistic Register */ - __I hw_enet_rmon_t_p64_t RMON_T_P64; /*!< [0x228] Tx 64-Byte Packets Statistic Register */ - __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; /*!< [0x22C] Tx 65- to 127-byte Packets Statistic Register */ - __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; /*!< [0x230] Tx 128- to 255-byte Packets Statistic Register */ - __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; /*!< [0x234] Tx 256- to 511-byte Packets Statistic Register */ - __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; /*!< [0x238] Tx 512- to 1023-byte Packets Statistic Register */ - __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; /*!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register */ - __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; /*!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register */ - __I hw_enet_rmon_t_octets_t RMON_T_OCTETS; /*!< [0x244] Tx Octets Statistic Register */ - uint8_t _reserved14[4]; - __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; /*!< [0x24C] Frames Transmitted OK Statistic Register */ - __I hw_enet_ieee_t_1col_t IEEE_T_1COL; /*!< [0x250] Frames Transmitted with Single Collision Statistic Register */ - __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; /*!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register */ - __I hw_enet_ieee_t_def_t IEEE_T_DEF; /*!< [0x258] Frames Transmitted after Deferral Delay Statistic Register */ - __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; /*!< [0x25C] Frames Transmitted with Late Collision Statistic Register */ - __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; /*!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register */ - __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; /*!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register */ - __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; /*!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register */ - uint8_t _reserved15[4]; - __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; /*!< [0x270] Flow Control Pause Frames Transmitted Statistic Register */ - __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; /*!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register */ - uint8_t _reserved16[12]; - __I hw_enet_rmon_r_packets_t RMON_R_PACKETS; /*!< [0x284] Rx Packet Count Statistic Register */ - __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; /*!< [0x288] Rx Broadcast Packets Statistic Register */ - __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; /*!< [0x28C] Rx Multicast Packets Statistic Register */ - __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; /*!< [0x290] Rx Packets with CRC/Align Error Statistic Register */ - __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; /*!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ - __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; /*!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ - __I hw_enet_rmon_r_frag_t RMON_R_FRAG; /*!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ - __I hw_enet_rmon_r_jab_t RMON_R_JAB; /*!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ - uint8_t _reserved17[4]; - __I hw_enet_rmon_r_p64_t RMON_R_P64; /*!< [0x2A8] Rx 64-Byte Packets Statistic Register */ - __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; /*!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register */ - __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; /*!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register */ - __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; /*!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register */ - __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; /*!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register */ - __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; /*!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register */ - __I hw_enet_rmon_r_p_gte2048_t RMON_R_P_GTE2048; /*!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register */ - __I hw_enet_rmon_r_octets_t RMON_R_OCTETS; /*!< [0x2C4] Rx Octets Statistic Register */ - __I hw_enet_ieee_r_drop_t IEEE_R_DROP; /*!< [0x2C8] Frames not Counted Correctly Statistic Register */ - __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; /*!< [0x2CC] Frames Received OK Statistic Register */ - __I hw_enet_ieee_r_crc_t IEEE_R_CRC; /*!< [0x2D0] Frames Received with CRC Error Statistic Register */ - __I hw_enet_ieee_r_align_t IEEE_R_ALIGN; /*!< [0x2D4] Frames Received with Alignment Error Statistic Register */ - __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; /*!< [0x2D8] Receive FIFO Overflow Count Statistic Register */ - __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; /*!< [0x2DC] Flow Control Pause Frames Received Statistic Register */ - __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; /*!< [0x2E0] Octet Count for Frames Received without Error Statistic Register */ - uint8_t _reserved18[284]; - __IO hw_enet_atcr_t ATCR; /*!< [0x400] Adjustable Timer Control Register */ - __IO hw_enet_atvr_t ATVR; /*!< [0x404] Timer Value Register */ - __IO hw_enet_atoff_t ATOFF; /*!< [0x408] Timer Offset Register */ - __IO hw_enet_atper_t ATPER; /*!< [0x40C] Timer Period Register */ - __IO hw_enet_atcor_t ATCOR; /*!< [0x410] Timer Correction Register */ - __IO hw_enet_atinc_t ATINC; /*!< [0x414] Time-Stamping Clock Period Register */ - __I hw_enet_atstmp_t ATSTMP; /*!< [0x418] Timestamp of Last Transmitted Frame */ - uint8_t _reserved19[488]; - __IO hw_enet_tgsr_t TGSR; /*!< [0x604] Timer Global Status Register */ - struct { - __IO hw_enet_tcsrn_t TCSRn; /*!< [0x608] Timer Control Status Register */ - __IO hw_enet_tccrn_t TCCRn; /*!< [0x60C] Timer Compare Capture Register */ - } CHANNEL[4]; -} hw_enet_t; -#pragma pack() - -/*! @brief Macro to access all ENET registers. */ -/*! @param x ENET module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_ENET(ENET_BASE). */ -#define HW_ENET(x) (*(hw_enet_t *)(x)) - -#endif /* __HW_ENET_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ewm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ewm.h deleted file mode 100644 index 5290a8ea5d5..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ewm.h +++ /dev/null @@ -1,440 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_EWM_REGISTERS_H__ -#define __HW_EWM_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 EWM - * - * External Watchdog Monitor - * - * Registers defined in this header file: - * - HW_EWM_CTRL - Control Register - * - HW_EWM_SERV - Service Register - * - HW_EWM_CMPL - Compare Low Register - * - HW_EWM_CMPH - Compare High Register - * - * - hw_ewm_t - Struct containing all module registers. - */ - -#define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */ - -/******************************************************************************* - * HW_EWM_CTRL - Control Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CTRL - Control Register (RW) - * - * Reset value: 0x00U - * - * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be - * written once after a CPU reset. Modifying these bits more than once, generates - * a bus transfer error. - */ -typedef union _hw_ewm_ctrl -{ - uint8_t U; - struct _hw_ewm_ctrl_bitfields - { - uint8_t EWMEN : 1; /*!< [0] EWM enable. */ - uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */ - uint8_t INEN : 1; /*!< [2] Input Enable. */ - uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_ewm_ctrl_t; - -/*! - * @name Constants and macros for entire EWM_CTRL register - */ -/*@{*/ -#define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U) - -#define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x)) -#define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U) -#define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v)) -#define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v))) -#define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v))) -#define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CTRL bitfields - */ - -/*! - * @name Register EWM_CTRL, field EWMEN[0] (RW) - * - * This bit when set, enables the EWM module. This resets the EWM counter to - * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and - * therefore it cannot be enabled until a reset occurs, due to the write-once - * nature of this bit. - */ -/*@{*/ -#define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */ -#define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */ -#define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */ - -/*! @brief Read current value of the EWM_CTRL_EWMEN field. */ -#define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN)) - -/*! @brief Format value for bitfield EWM_CTRL_EWMEN. */ -#define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN) - -/*! @brief Set the EWMEN field to a new value. */ -#define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v)) -/*@}*/ - -/*! - * @name Register EWM_CTRL, field ASSIN[1] (RW) - * - * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit - * inverts the assert state to a logic one. - */ -/*@{*/ -#define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */ -#define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */ -#define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */ - -/*! @brief Read current value of the EWM_CTRL_ASSIN field. */ -#define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN)) - -/*! @brief Format value for bitfield EWM_CTRL_ASSIN. */ -#define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN) - -/*! @brief Set the ASSIN field to a new value. */ -#define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v)) -/*@}*/ - -/*! - * @name Register EWM_CTRL, field INEN[2] (RW) - * - * This bit when set, enables the EWM_in port. - */ -/*@{*/ -#define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */ -#define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */ -#define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */ - -/*! @brief Read current value of the EWM_CTRL_INEN field. */ -#define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN)) - -/*! @brief Format value for bitfield EWM_CTRL_INEN. */ -#define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN) - -/*! @brief Set the INEN field to a new value. */ -#define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v)) -/*@}*/ - -/*! - * @name Register EWM_CTRL, field INTEN[3] (RW) - * - * This bit when set and EWM_out is asserted, an interrupt request is generated. - * To de-assert interrupt request, user should clear this bit by writing 0. - */ -/*@{*/ -#define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */ -#define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */ -#define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */ - -/*! @brief Read current value of the EWM_CTRL_INTEN field. */ -#define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN)) - -/*! @brief Format value for bitfield EWM_CTRL_INTEN. */ -#define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN) - -/*! @brief Set the INTEN field to a new value. */ -#define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_SERV - Service Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_SERV - Service Register (WORZ) - * - * Reset value: 0x00U - * - * The SERV register provides the interface from the CPU to the EWM module. It - * is write-only and reads of this register return zero. - */ -typedef union _hw_ewm_serv -{ - uint8_t U; - struct _hw_ewm_serv_bitfields - { - uint8_t SERVICE : 8; /*!< [7:0] */ - } B; -} hw_ewm_serv_t; - -/*! - * @name Constants and macros for entire EWM_SERV register - */ -/*@{*/ -#define HW_EWM_SERV_ADDR(x) ((x) + 0x1U) - -#define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x)) -#define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U) -#define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual EWM_SERV bitfields - */ - -/*! - * @name Register EWM_SERV, field SERVICE[7:0] (WORZ) - * - * The EWM service mechanism requires the CPU to write two values to the SERV - * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The - * EWM service is illegal if either of the following conditions is true. The - * first or second data byte is not written correctly. The second data byte is not - * written within a fixed number of peripheral bus cycles of the first data byte. - * This fixed number of cycles is called EWM_service_time. - */ -/*@{*/ -#define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */ -#define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */ -#define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */ - -/*! @brief Format value for bitfield EWM_SERV_SERVICE. */ -#define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE) - -/*! @brief Set the SERVICE field to a new value. */ -#define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_CMPL - Compare Low Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CMPL - Compare Low Register (RW) - * - * Reset value: 0x00U - * - * The CMPL register is reset to zero after a CPU reset. This provides no - * minimum time for the CPU to service the EWM counter. This register can be written - * only once after a CPU reset. Writing this register more than once generates a - * bus transfer error. - */ -typedef union _hw_ewm_cmpl -{ - uint8_t U; - struct _hw_ewm_cmpl_bitfields - { - uint8_t COMPAREL : 8; /*!< [7:0] */ - } B; -} hw_ewm_cmpl_t; - -/*! - * @name Constants and macros for entire EWM_CMPL register - */ -/*@{*/ -#define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U) - -#define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x)) -#define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U) -#define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v)) -#define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v))) -#define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v))) -#define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CMPL bitfields - */ - -/*! - * @name Register EWM_CMPL, field COMPAREL[7:0] (RW) - * - * To prevent runaway code from changing this field, software should write to - * this field after a CPU reset even if the (default) minimum service time is - * required. - */ -/*@{*/ -#define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */ -#define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */ -#define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */ - -/*! @brief Read current value of the EWM_CMPL_COMPAREL field. */ -#define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U) - -/*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */ -#define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL) - -/*! @brief Set the COMPAREL field to a new value. */ -#define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_EWM_CMPH - Compare High Register - ******************************************************************************/ - -/*! - * @brief HW_EWM_CMPH - Compare High Register (RW) - * - * Reset value: 0xFFU - * - * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum - * of 256 clocks time, for the CPU to service the EWM counter. This register can - * be written only once after a CPU reset. Writing this register more than once - * generates a bus transfer error. The valid values for CMPH are up to 0xFE - * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only - * if EWM counter is greater than CMPH. - */ -typedef union _hw_ewm_cmph -{ - uint8_t U; - struct _hw_ewm_cmph_bitfields - { - uint8_t COMPAREH : 8; /*!< [7:0] */ - } B; -} hw_ewm_cmph_t; - -/*! - * @name Constants and macros for entire EWM_CMPH register - */ -/*@{*/ -#define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U) - -#define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x)) -#define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U) -#define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v)) -#define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v))) -#define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v))) -#define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual EWM_CMPH bitfields - */ - -/*! - * @name Register EWM_CMPH, field COMPAREH[7:0] (RW) - * - * To prevent runaway code from changing this field, software should write to - * this field after a CPU reset even if the (default) maximum service time is - * required. - */ -/*@{*/ -#define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */ -#define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */ -#define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */ - -/*! @brief Read current value of the EWM_CMPH_COMPAREH field. */ -#define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U) - -/*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */ -#define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH) - -/*! @brief Set the COMPAREH field to a new value. */ -#define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_ewm_t - module struct - ******************************************************************************/ -/*! - * @brief All EWM module registers. - */ -#pragma pack(1) -typedef struct _hw_ewm -{ - __IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */ - __O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */ - __IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */ - __IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */ -} hw_ewm_t; -#pragma pack() - -/*! @brief Macro to access all EWM registers. */ -/*! @param x EWM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_EWM(EWM_BASE). */ -#define HW_EWM(x) (*(hw_ewm_t *)(x)) - -#endif /* __HW_EWM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fb.h deleted file mode 100644 index 95682a818a8..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fb.h +++ /dev/null @@ -1,907 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FB_REGISTERS_H__ -#define __HW_FB_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 FB - * - * FlexBus external bus interface - * - * Registers defined in this header file: - * - HW_FB_CSARn - Chip Select Address Register - * - HW_FB_CSMRn - Chip Select Mask Register - * - HW_FB_CSCRn - Chip Select Control Register - * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register - * - * - hw_fb_t - Struct containing all module registers. - */ - -#define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */ - -/******************************************************************************* - * HW_FB_CSARn - Chip Select Address Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSARn - Chip Select Address Register (RW) - * - * Reset value: 0x00000000U - * - * Specifies the associated chip-select's base address. - */ -typedef union _hw_fb_csarn -{ - uint32_t U; - struct _hw_fb_csarn_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t BA : 16; /*!< [31:16] Base Address */ - } B; -} hw_fb_csarn_t; - -/*! - * @name Constants and macros for entire FB_CSARn register - */ -/*@{*/ -#define HW_FB_CSARn_COUNT (6U) - -#define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n))) - -#define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n)) -#define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U) -#define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v)) -#define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v))) -#define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v))) -#define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSARn bitfields - */ - -/*! - * @name Register FB_CSARn, field BA[31:16] (RW) - * - * Defines the base address for memory dedicated to the associated chip-select. - * BA is compared to bits 31-16 on the internal address bus to determine if the - * associated chip-select's memory is being accessed. Because the FlexBus module - * is one of the slaves connected to the crossbar switch, it is only accessible - * within a certain memory range. See the chip memory map for the applicable - * FlexBus "expansion" address range for which the chip-selects can be active. Set the - * CSARn and CSMRn registers appropriately before accessing this region. - */ -/*@{*/ -#define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */ -#define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */ -#define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */ - -/*! @brief Read current value of the FB_CSARn_BA field. */ -#define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA) - -/*! @brief Format value for bitfield FB_CSARn_BA. */ -#define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA) - -/*! @brief Set the BA field to a new value. */ -#define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v))) -/*@}*/ -/******************************************************************************* - * HW_FB_CSMRn - Chip Select Mask Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSMRn - Chip Select Mask Register (RW) - * - * Reset value: 0x00000000U - * - * Specifies the address mask and allowable access types for the associated - * chip-select. - */ -typedef union _hw_fb_csmrn -{ - uint32_t U; - struct _hw_fb_csmrn_bitfields - { - uint32_t V : 1; /*!< [0] Valid */ - uint32_t RESERVED0 : 7; /*!< [7:1] */ - uint32_t WP : 1; /*!< [8] Write Protect */ - uint32_t RESERVED1 : 7; /*!< [15:9] */ - uint32_t BAM : 16; /*!< [31:16] Base Address Mask */ - } B; -} hw_fb_csmrn_t; - -/*! - * @name Constants and macros for entire FB_CSMRn register - */ -/*@{*/ -#define HW_FB_CSMRn_COUNT (6U) - -#define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n))) - -#define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n)) -#define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U) -#define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v)) -#define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v))) -#define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v))) -#define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSMRn bitfields - */ - -/*! - * @name Register FB_CSMRn, field V[0] (RW) - * - * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. - * Programmed chip-selects do not assert until the V bit is 1b (except for - * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any - * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip - * select initialization sequence to allow other chip selects to function as - * programmed. - * - * Values: - * - 0 - Chip-select is invalid. - * - 1 - Chip-select is valid. - */ -/*@{*/ -#define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */ -#define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */ -#define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */ - -/*! @brief Read current value of the FB_CSMRn_V field. */ -#define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V)) - -/*! @brief Format value for bitfield FB_CSMRn_V. */ -#define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V) - -/*! @brief Set the V field to a new value. */ -#define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSMRn, field WP[8] (RW) - * - * Controls write accesses to the address range in the corresponding CSAR. - * - * Values: - * - 0 - Write accesses are allowed. - * - 1 - Write accesses are not allowed. Attempting to write to the range of - * addresses for which the WP bit is set results in a bus error termination of - * the internal cycle and no external cycle. - */ -/*@{*/ -#define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */ -#define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */ -#define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */ - -/*! @brief Read current value of the FB_CSMRn_WP field. */ -#define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP)) - -/*! @brief Format value for bitfield FB_CSMRn_WP. */ -#define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP) - -/*! @brief Set the WP field to a new value. */ -#define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSMRn, field BAM[31:16] (RW) - * - * Defines the associated chip-select's block size by masking address bits. - * - * Values: - * - 0 - The corresponding address bit in CSAR is used in the chip-select decode. - * - 1 - The corresponding address bit in CSAR is a don't care in the - * chip-select decode. - */ -/*@{*/ -#define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */ -#define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */ -#define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */ - -/*! @brief Read current value of the FB_CSMRn_BAM field. */ -#define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM) - -/*! @brief Format value for bitfield FB_CSMRn_BAM. */ -#define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM) - -/*! @brief Set the BAM field to a new value. */ -#define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v))) -/*@}*/ -/******************************************************************************* - * HW_FB_CSCRn - Chip Select Control Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSCRn - Chip Select Control Register (RW) - * - * Reset value: 0x003FFC00U - * - * Controls the auto-acknowledge, address setup and hold times, port size, burst - * capability, and number of wait states for the associated chip select. To - * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the - * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3 - * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your - * particular chip for information on the exact CSCR0 reset value. - */ -typedef union _hw_fb_cscrn -{ - uint32_t U; - struct _hw_fb_cscrn_bitfields - { - uint32_t RESERVED0 : 3; /*!< [2:0] */ - uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */ - uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */ - uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */ - uint32_t PS : 2; /*!< [7:6] Port Size */ - uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */ - uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */ - uint32_t WS : 6; /*!< [15:10] Wait States */ - uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */ - uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */ - uint32_t ASET : 2; /*!< [21:20] Address Setup */ - uint32_t EXTS : 1; /*!< [22] */ - uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */ - uint32_t RESERVED1 : 2; /*!< [25:24] */ - uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */ - } B; -} hw_fb_cscrn_t; - -/*! - * @name Constants and macros for entire FB_CSCRn register - */ -/*@{*/ -#define HW_FB_CSCRn_COUNT (6U) - -#define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n))) - -#define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n)) -#define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U) -#define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v)) -#define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v))) -#define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v))) -#define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSCRn bitfields - */ - -/*! - * @name Register FB_CSCRn, field BSTW[3] (RW) - * - * Specifies whether burst writes are enabled for memory associated with each - * chip select. - * - * Values: - * - 0 - Disabled. Data exceeding the specified port size is broken into - * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit - * port takes four byte writes. - * - 1 - Enabled. Enables burst write of data larger than the specified port - * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit - * ports, and line writes to 8-, 16-, and 32-bit ports. - */ -/*@{*/ -#define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */ -#define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */ -#define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */ - -/*! @brief Read current value of the FB_CSCRn_BSTW field. */ -#define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW)) - -/*! @brief Format value for bitfield FB_CSCRn_BSTW. */ -#define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW) - -/*! @brief Set the BSTW field to a new value. */ -#define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field BSTR[4] (RW) - * - * Specifies whether burst reads are enabled for memory associated with each - * chip select. - * - * Values: - * - 0 - Disabled. Data exceeding the specified port size is broken into - * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit - * port is broken into four 8-bit reads. - * - 1 - Enabled. Enables data burst reads larger than the specified port size, - * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit - * ports, and line reads from 8-, 16-, and 32-bit ports. - */ -/*@{*/ -#define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */ -#define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */ -#define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */ - -/*! @brief Read current value of the FB_CSCRn_BSTR field. */ -#define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR)) - -/*! @brief Format value for bitfield FB_CSCRn_BSTR. */ -#define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR) - -/*! @brief Set the BSTR field to a new value. */ -#define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field BEM[5] (RW) - * - * Specifies whether the corresponding FB_BE is asserted for read accesses. - * Certain memories have byte enables that must be asserted during reads and writes. - * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode - * of byte enable support for these SRAMs. - * - * Values: - * - 0 - FB_BE is asserted for data write only. - * - 1 - FB_BE is asserted for data read and write accesses. - */ -/*@{*/ -#define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */ -#define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */ -#define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */ - -/*! @brief Read current value of the FB_CSCRn_BEM field. */ -#define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM)) - -/*! @brief Format value for bitfield FB_CSCRn_BEM. */ -#define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM) - -/*! @brief Set the BEM field to a new value. */ -#define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field PS[7:6] (RW) - * - * Specifies the data port width of the associated chip-select, and determines - * where data is driven during write cycles and where data is sampled during read - * cycles. - * - * Values: - * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. - * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when - * BLS is 0b, or FB_D[7:0] when BLS is 1b. - */ -/*@{*/ -#define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */ -#define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */ -#define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */ - -/*! @brief Read current value of the FB_CSCRn_PS field. */ -#define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS) - -/*! @brief Format value for bitfield FB_CSCRn_PS. */ -#define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS) - -/*! @brief Set the PS field to a new value. */ -#define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field AA[8] (RW) - * - * Asserts the internal transfer acknowledge for accesses specified by the - * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system - * asserts an external FB_TA before the wait-state countdown asserts the - * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus - * between each internal termination. This field must be 1b if CSPMCR disables FB_TA. - * - * Values: - * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is - * terminated externally. - * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS. - */ -/*@{*/ -#define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */ -#define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */ -#define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */ - -/*! @brief Read current value of the FB_CSCRn_AA field. */ -#define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA)) - -/*! @brief Format value for bitfield FB_CSCRn_AA. */ -#define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA) - -/*! @brief Set the AA field to a new value. */ -#define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field BLS[9] (RW) - * - * Specifies if data on FB_AD appears left-aligned or right-aligned during the - * data phase of a FlexBus access. - * - * Values: - * - 0 - Not shifted. Data is left-aligned on FB_AD. - * - 1 - Shifted. Data is right-aligned on FB_AD. - */ -/*@{*/ -#define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */ -#define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */ -#define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */ - -/*! @brief Read current value of the FB_CSCRn_BLS field. */ -#define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS)) - -/*! @brief Format value for bitfield FB_CSCRn_BLS. */ -#define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS) - -/*! @brief Set the BLS field to a new value. */ -#define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field WS[15:10] (RW) - * - * Specifies the number of wait states inserted after FlexBus asserts the - * associated chip-select and before an internal transfer acknowledge is generated (WS - * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states). - */ -/*@{*/ -#define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */ -#define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */ -#define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */ - -/*! @brief Read current value of the FB_CSCRn_WS field. */ -#define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS) - -/*! @brief Format value for bitfield FB_CSCRn_WS. */ -#define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS) - -/*! @brief Set the WS field to a new value. */ -#define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field WRAH[17:16] (RW) - * - * Controls the address, data, and attribute hold time after the termination of - * a write cycle that hits in the associated chip-select's address space. The - * hold time applies only at the end of a transfer. Therefore, during a burst - * transfer or a transfer to a port size smaller than the transfer size, the hold time - * is only added after the last bus cycle. - * - * Values: - * - 00 - 1 cycle (default for all but FB_CS0 ) - * - 01 - 2 cycles - * - 10 - 3 cycles - * - 11 - 4 cycles (default for FB_CS0 ) - */ -/*@{*/ -#define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */ -#define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */ -#define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */ - -/*! @brief Read current value of the FB_CSCRn_WRAH field. */ -#define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH) - -/*! @brief Format value for bitfield FB_CSCRn_WRAH. */ -#define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH) - -/*! @brief Set the WRAH field to a new value. */ -#define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field RDAH[19:18] (RW) - * - * Controls the address and attribute hold time after the termination during a - * read cycle that hits in the associated chip-select's address space. The hold - * time applies only at the end of a transfer. Therefore, during a burst transfer - * or a transfer to a port size smaller than the transfer size, the hold time is - * only added after the last bus cycle. The number of cycles the address and - * attributes are held after FB_CSn deassertion depends on the value of the AA bit. - * - * Values: - * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. - * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. - * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. - * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. - */ -/*@{*/ -#define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */ -#define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */ -#define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */ - -/*! @brief Read current value of the FB_CSCRn_RDAH field. */ -#define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH) - -/*! @brief Format value for bitfield FB_CSCRn_RDAH. */ -#define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH) - -/*! @brief Set the RDAH field to a new value. */ -#define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field ASET[21:20] (RW) - * - * Controls when the chip-select is asserted with respect to assertion of a - * valid address and attributes. - * - * Values: - * - 00 - Assert FB_CSn on the first rising clock edge after the address is - * asserted (default for all but FB_CS0 ). - * - 01 - Assert FB_CSn on the second rising clock edge after the address is - * asserted. - * - 10 - Assert FB_CSn on the third rising clock edge after the address is - * asserted. - * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is - * asserted (default for FB_CS0 ). - */ -/*@{*/ -#define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */ -#define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */ -#define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */ - -/*! @brief Read current value of the FB_CSCRn_ASET field. */ -#define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET) - -/*! @brief Format value for bitfield FB_CSCRn_ASET. */ -#define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET) - -/*! @brief Set the ASET field to a new value. */ -#define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v))) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field EXTS[22] (RW) - * - * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS - * /FB_ALE is asserted. - * - * Values: - * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. - * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock - * edge after FB_CSn asserts. - */ -/*@{*/ -#define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */ -#define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */ -#define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */ - -/*! @brief Read current value of the FB_CSCRn_EXTS field. */ -#define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS)) - -/*! @brief Format value for bitfield FB_CSCRn_EXTS. */ -#define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS) - -/*! @brief Set the EXTS field to a new value. */ -#define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field SWSEN[23] (RW) - * - * Values: - * - 0 - Disabled. A number of wait states (specified by WS) are inserted before - * an internal transfer acknowledge is generated for all transfers. - * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before - * an internal transfer acknowledge is generated for burst transfer - * secondary terminations. - */ -/*@{*/ -#define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */ -#define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */ -#define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */ - -/*! @brief Read current value of the FB_CSCRn_SWSEN field. */ -#define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN)) - -/*! @brief Format value for bitfield FB_CSCRn_SWSEN. */ -#define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN) - -/*! @brief Set the SWSEN field to a new value. */ -#define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v)) -/*@}*/ - -/*! - * @name Register FB_CSCRn, field SWS[31:26] (RW) - * - * Used only when the SWSEN bit is 1b. Specifies the number of wait states - * inserted before an internal transfer acknowledge is generated for a burst transfer - * (except for the first termination, which is controlled by WS). - */ -/*@{*/ -#define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */ -#define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */ -#define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */ - -/*! @brief Read current value of the FB_CSCRn_SWS field. */ -#define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS) - -/*! @brief Format value for bitfield FB_CSCRn_SWS. */ -#define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS) - -/*! @brief Set the SWS field to a new value. */ -#define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v))) -/*@}*/ - -/******************************************************************************* - * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register - ******************************************************************************/ - -/*! - * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW) - * - * Reset value: 0x00000000U - * - * Controls the multiplexing of the FlexBus signals. A bus error occurs when you - * do any of the following: Write to a reserved address Write to a reserved - * field in this register, or Access this register using a size other than 32 bits. - */ -typedef union _hw_fb_cspmcr -{ - uint32_t U; - struct _hw_fb_cspmcr_bitfields - { - uint32_t RESERVED0 : 12; /*!< [11:0] */ - uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex - * control */ - uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex - * control */ - uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex - * control */ - uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex - * control */ - uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex - * control */ - } B; -} hw_fb_cspmcr_t; - -/*! - * @name Constants and macros for entire FB_CSPMCR register - */ -/*@{*/ -#define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U) - -#define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x)) -#define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U) -#define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v)) -#define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v))) -#define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v))) -#define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FB_CSPMCR bitfields - */ - -/*! - * @name Register FB_CSPMCR, field GROUP5[15:12] (RW) - * - * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When - * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the - * bus hangs during a transfer. - * - * Values: - * - 0000 - FB_TA - * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA]. - * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA]. - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */ -#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */ -#define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */ -#define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */ -#define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5) - -/*! @brief Set the GROUP5 field to a new value. */ -#define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP4[19:16] (RW) - * - * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals. - * - * Values: - * - 0000 - FB_TBST - * - 0001 - FB_CS2 - * - 0010 - FB_BE_15_8 - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */ -#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */ -#define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */ -#define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */ -#define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4) - -/*! @brief Set the GROUP4 field to a new value. */ -#define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP3[23:20] (RW) - * - * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals. - * - * Values: - * - 0000 - FB_CS5 - * - 0001 - FB_TSIZ1 - * - 0010 - FB_BE_23_16 - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */ -#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */ -#define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */ -#define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */ -#define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3) - -/*! @brief Set the GROUP3 field to a new value. */ -#define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP2[27:24] (RW) - * - * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals. - * - * Values: - * - 0000 - FB_CS4 - * - 0001 - FB_TSIZ0 - * - 0010 - FB_BE_31_24 - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */ -#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */ -#define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */ -#define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */ -#define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2) - -/*! @brief Set the GROUP2 field to a new value. */ -#define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v))) -/*@}*/ - -/*! - * @name Register FB_CSPMCR, field GROUP1[31:28] (RW) - * - * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals. - * - * Values: - * - 0000 - FB_ALE - * - 0001 - FB_CS1 - * - 0010 - FB_TS - */ -/*@{*/ -#define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */ -#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */ -#define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */ - -/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */ -#define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1) - -/*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */ -#define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1) - -/*! @brief Set the GROUP1 field to a new value. */ -#define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v))) -/*@}*/ - -/******************************************************************************* - * hw_fb_t - module struct - ******************************************************************************/ -/*! - * @brief All FB module registers. - */ -#pragma pack(1) -typedef struct _hw_fb -{ - struct { - __IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */ - __IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */ - __IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */ - } CS[6]; - uint8_t _reserved0[24]; - __IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */ -} hw_fb_t; -#pragma pack() - -/*! @brief Macro to access all FB registers. */ -/*! @param x FB module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FB(FB_BASE). */ -#define HW_FB(x) (*(hw_fb_t *)(x)) - -#endif /* __HW_FB_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fmc.h deleted file mode 100644 index a94e78c50e4..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fmc.h +++ /dev/null @@ -1,1982 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FMC_REGISTERS_H__ -#define __HW_FMC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 FMC - * - * Flash Memory Controller - * - * Registers defined in this header file: - * - HW_FMC_PFAPR - Flash Access Protection Register - * - HW_FMC_PFB0CR - Flash Bank 0 Control Register - * - HW_FMC_PFB1CR - Flash Bank 1 Control Register - * - HW_FMC_TAGVDW0Sn - Cache Tag Storage - * - HW_FMC_TAGVDW1Sn - Cache Tag Storage - * - HW_FMC_TAGVDW2Sn - Cache Tag Storage - * - HW_FMC_TAGVDW3Sn - Cache Tag Storage - * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word) - * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word) - * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word) - * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word) - * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word) - * - * - hw_fmc_t - Struct containing all module registers. - */ - -#define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */ - -/******************************************************************************* - * HW_FMC_PFAPR - Flash Access Protection Register - ******************************************************************************/ - -/*! - * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW) - * - * Reset value: 0x00F8003FU - */ -typedef union _hw_fmc_pfapr -{ - uint32_t U; - struct _hw_fmc_pfapr_bitfields - { - uint32_t M0AP : 2; /*!< [1:0] Master 0 Access Protection */ - uint32_t M1AP : 2; /*!< [3:2] Master 1 Access Protection */ - uint32_t M2AP : 2; /*!< [5:4] Master 2 Access Protection */ - uint32_t M3AP : 2; /*!< [7:6] Master 3 Access Protection */ - uint32_t M4AP : 2; /*!< [9:8] Master 4 Access Protection */ - uint32_t M5AP : 2; /*!< [11:10] Master 5 Access Protection */ - uint32_t M6AP : 2; /*!< [13:12] Master 6 Access Protection */ - uint32_t M7AP : 2; /*!< [15:14] Master 7 Access Protection */ - uint32_t M0PFD : 1; /*!< [16] Master 0 Prefetch Disable */ - uint32_t M1PFD : 1; /*!< [17] Master 1 Prefetch Disable */ - uint32_t M2PFD : 1; /*!< [18] Master 2 Prefetch Disable */ - uint32_t M3PFD : 1; /*!< [19] Master 3 Prefetch Disable */ - uint32_t M4PFD : 1; /*!< [20] Master 4 Prefetch Disable */ - uint32_t M5PFD : 1; /*!< [21] Master 5 Prefetch Disable */ - uint32_t M6PFD : 1; /*!< [22] Master 6 Prefetch Disable */ - uint32_t M7PFD : 1; /*!< [23] Master 7 Prefetch Disable */ - uint32_t RESERVED0 : 8; /*!< [31:24] */ - } B; -} hw_fmc_pfapr_t; - -/*! - * @name Constants and macros for entire FMC_PFAPR register - */ -/*@{*/ -#define HW_FMC_PFAPR_ADDR(x) ((x) + 0x0U) - -#define HW_FMC_PFAPR(x) (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x)) -#define HW_FMC_PFAPR_RD(x) (HW_FMC_PFAPR(x).U) -#define HW_FMC_PFAPR_WR(x, v) (HW_FMC_PFAPR(x).U = (v)) -#define HW_FMC_PFAPR_SET(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) | (v))) -#define HW_FMC_PFAPR_CLR(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v))) -#define HW_FMC_PFAPR_TOG(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_PFAPR bitfields - */ - -/*! - * @name Register FMC_PFAPR, field M0AP[1:0] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M0AP (0U) /*!< Bit position for FMC_PFAPR_M0AP. */ -#define BM_FMC_PFAPR_M0AP (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */ -#define BS_FMC_PFAPR_M0AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M0AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M0AP field. */ -#define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M0AP. */ -#define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP) - -/*! @brief Set the M0AP field to a new value. */ -#define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M1AP[3:2] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M1AP (2U) /*!< Bit position for FMC_PFAPR_M1AP. */ -#define BM_FMC_PFAPR_M1AP (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */ -#define BS_FMC_PFAPR_M1AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M1AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M1AP field. */ -#define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M1AP. */ -#define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP) - -/*! @brief Set the M1AP field to a new value. */ -#define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M2AP[5:4] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M2AP (4U) /*!< Bit position for FMC_PFAPR_M2AP. */ -#define BM_FMC_PFAPR_M2AP (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */ -#define BS_FMC_PFAPR_M2AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M2AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M2AP field. */ -#define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M2AP. */ -#define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP) - -/*! @brief Set the M2AP field to a new value. */ -#define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M3AP[7:6] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M3AP (6U) /*!< Bit position for FMC_PFAPR_M3AP. */ -#define BM_FMC_PFAPR_M3AP (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */ -#define BS_FMC_PFAPR_M3AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M3AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M3AP field. */ -#define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M3AP. */ -#define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP) - -/*! @brief Set the M3AP field to a new value. */ -#define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M4AP[9:8] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M4AP (8U) /*!< Bit position for FMC_PFAPR_M4AP. */ -#define BM_FMC_PFAPR_M4AP (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */ -#define BS_FMC_PFAPR_M4AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M4AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M4AP field. */ -#define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M4AP. */ -#define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP) - -/*! @brief Set the M4AP field to a new value. */ -#define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M5AP[11:10] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M5AP (10U) /*!< Bit position for FMC_PFAPR_M5AP. */ -#define BM_FMC_PFAPR_M5AP (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */ -#define BS_FMC_PFAPR_M5AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M5AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M5AP field. */ -#define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M5AP. */ -#define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP) - -/*! @brief Set the M5AP field to a new value. */ -#define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M6AP[13:12] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master - * - 01 - Only read accesses may be performed by this master - * - 10 - Only write accesses may be performed by this master - * - 11 - Both read and write accesses may be performed by this master - */ -/*@{*/ -#define BP_FMC_PFAPR_M6AP (12U) /*!< Bit position for FMC_PFAPR_M6AP. */ -#define BM_FMC_PFAPR_M6AP (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */ -#define BS_FMC_PFAPR_M6AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M6AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M6AP field. */ -#define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M6AP. */ -#define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP) - -/*! @brief Set the M6AP field to a new value. */ -#define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M7AP[15:14] (RW) - * - * This field controls whether read and write access to the flash are allowed - * based on the logical master number of the requesting crossbar switch master. - * - * Values: - * - 00 - No access may be performed by this master. - * - 01 - Only read accesses may be performed by this master. - * - 10 - Only write accesses may be performed by this master. - * - 11 - Both read and write accesses may be performed by this master. - */ -/*@{*/ -#define BP_FMC_PFAPR_M7AP (14U) /*!< Bit position for FMC_PFAPR_M7AP. */ -#define BM_FMC_PFAPR_M7AP (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */ -#define BS_FMC_PFAPR_M7AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M7AP. */ - -/*! @brief Read current value of the FMC_PFAPR_M7AP field. */ -#define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP) - -/*! @brief Format value for bitfield FMC_PFAPR_M7AP. */ -#define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP) - -/*! @brief Set the M7AP field to a new value. */ -#define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v))) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M0PFD[16] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M0PFD (16U) /*!< Bit position for FMC_PFAPR_M0PFD. */ -#define BM_FMC_PFAPR_M0PFD (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */ -#define BS_FMC_PFAPR_M0PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */ -#define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */ -#define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD) - -/*! @brief Set the M0PFD field to a new value. */ -#define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M1PFD[17] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M1PFD (17U) /*!< Bit position for FMC_PFAPR_M1PFD. */ -#define BM_FMC_PFAPR_M1PFD (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */ -#define BS_FMC_PFAPR_M1PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */ -#define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */ -#define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD) - -/*! @brief Set the M1PFD field to a new value. */ -#define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M2PFD[18] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M2PFD (18U) /*!< Bit position for FMC_PFAPR_M2PFD. */ -#define BM_FMC_PFAPR_M2PFD (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */ -#define BS_FMC_PFAPR_M2PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */ -#define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */ -#define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD) - -/*! @brief Set the M2PFD field to a new value. */ -#define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M3PFD[19] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M3PFD (19U) /*!< Bit position for FMC_PFAPR_M3PFD. */ -#define BM_FMC_PFAPR_M3PFD (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */ -#define BS_FMC_PFAPR_M3PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */ -#define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */ -#define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD) - -/*! @brief Set the M3PFD field to a new value. */ -#define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M4PFD[20] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M4PFD (20U) /*!< Bit position for FMC_PFAPR_M4PFD. */ -#define BM_FMC_PFAPR_M4PFD (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */ -#define BS_FMC_PFAPR_M4PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */ -#define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */ -#define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD) - -/*! @brief Set the M4PFD field to a new value. */ -#define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M5PFD[21] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M5PFD (21U) /*!< Bit position for FMC_PFAPR_M5PFD. */ -#define BM_FMC_PFAPR_M5PFD (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */ -#define BS_FMC_PFAPR_M5PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */ -#define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */ -#define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD) - -/*! @brief Set the M5PFD field to a new value. */ -#define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M6PFD[22] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M6PFD (22U) /*!< Bit position for FMC_PFAPR_M6PFD. */ -#define BM_FMC_PFAPR_M6PFD (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */ -#define BS_FMC_PFAPR_M6PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */ -#define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */ -#define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD) - -/*! @brief Set the M6PFD field to a new value. */ -#define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFAPR, field M7PFD[23] (RW) - * - * These bits control whether prefetching is enabled based on the logical number - * of the requesting crossbar switch master. This field is further qualified by - * the PFBnCR[BxDPE,BxIPE] bits. - * - * Values: - * - 0 - Prefetching for this master is enabled. - * - 1 - Prefetching for this master is disabled. - */ -/*@{*/ -#define BP_FMC_PFAPR_M7PFD (23U) /*!< Bit position for FMC_PFAPR_M7PFD. */ -#define BM_FMC_PFAPR_M7PFD (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */ -#define BS_FMC_PFAPR_M7PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */ - -/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */ -#define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD)) - -/*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */ -#define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD) - -/*! @brief Set the M7PFD field to a new value. */ -#define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_PFB0CR - Flash Bank 0 Control Register - ******************************************************************************/ - -/*! - * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW) - * - * Reset value: 0x3004001FU - */ -typedef union _hw_fmc_pfb0cr -{ - uint32_t U; - struct _hw_fmc_pfb0cr_bitfields - { - uint32_t B0SEBE : 1; /*!< [0] Bank 0 Single Entry Buffer Enable */ - uint32_t B0IPE : 1; /*!< [1] Bank 0 Instruction Prefetch Enable */ - uint32_t B0DPE : 1; /*!< [2] Bank 0 Data Prefetch Enable */ - uint32_t B0ICE : 1; /*!< [3] Bank 0 Instruction Cache Enable */ - uint32_t B0DCE : 1; /*!< [4] Bank 0 Data Cache Enable */ - uint32_t CRC : 3; /*!< [7:5] Cache Replacement Control */ - uint32_t RESERVED0 : 9; /*!< [16:8] */ - uint32_t B0MW : 2; /*!< [18:17] Bank 0 Memory Width */ - uint32_t S_B_INV : 1; /*!< [19] Invalidate Prefetch Speculation - * Buffer */ - uint32_t CINV_WAY : 4; /*!< [23:20] Cache Invalidate Way x */ - uint32_t CLCK_WAY : 4; /*!< [27:24] Cache Lock Way x */ - uint32_t B0RWSC : 4; /*!< [31:28] Bank 0 Read Wait State Control */ - } B; -} hw_fmc_pfb0cr_t; - -/*! - * @name Constants and macros for entire FMC_PFB0CR register - */ -/*@{*/ -#define HW_FMC_PFB0CR_ADDR(x) ((x) + 0x4U) - -#define HW_FMC_PFB0CR(x) (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x)) -#define HW_FMC_PFB0CR_RD(x) (HW_FMC_PFB0CR(x).U) -#define HW_FMC_PFB0CR_WR(x, v) (HW_FMC_PFB0CR(x).U = (v)) -#define HW_FMC_PFB0CR_SET(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) | (v))) -#define HW_FMC_PFB0CR_CLR(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v))) -#define HW_FMC_PFB0CR_TOG(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_PFB0CR bitfields - */ - -/*! - * @name Register FMC_PFB0CR, field B0SEBE[0] (RW) - * - * This bit controls whether the single entry page buffer is enabled in response - * to flash read accesses. Its operation is independent from bank 1's cache. A - * high-to-low transition of this enable forces the page buffer to be invalidated. - * - * Values: - * - 0 - Single entry buffer is disabled. - * - 1 - Single entry buffer is enabled. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0SEBE (0U) /*!< Bit position for FMC_PFB0CR_B0SEBE. */ -#define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */ -#define BS_FMC_PFB0CR_B0SEBE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */ -#define BR_FMC_PFB0CR_B0SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */ -#define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE) - -/*! @brief Set the B0SEBE field to a new value. */ -#define BW_FMC_PFB0CR_B0SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0IPE[1] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to instruction fetches. - * - * Values: - * - 0 - Do not prefetch in response to instruction fetches. - * - 1 - Enable prefetches in response to instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0IPE (1U) /*!< Bit position for FMC_PFB0CR_B0IPE. */ -#define BM_FMC_PFB0CR_B0IPE (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */ -#define BS_FMC_PFB0CR_B0IPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */ -#define BR_FMC_PFB0CR_B0IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */ -#define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE) - -/*! @brief Set the B0IPE field to a new value. */ -#define BW_FMC_PFB0CR_B0IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0DPE[2] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to data references. - * - * Values: - * - 0 - Do not prefetch in response to data references. - * - 1 - Enable prefetches in response to data references. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0DPE (2U) /*!< Bit position for FMC_PFB0CR_B0DPE. */ -#define BM_FMC_PFB0CR_B0DPE (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */ -#define BS_FMC_PFB0CR_B0DPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */ -#define BR_FMC_PFB0CR_B0DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */ -#define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE) - -/*! @brief Set the B0DPE field to a new value. */ -#define BW_FMC_PFB0CR_B0DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0ICE[3] (RW) - * - * This bit controls whether instruction fetches are loaded into the cache. - * - * Values: - * - 0 - Do not cache instruction fetches. - * - 1 - Cache instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0ICE (3U) /*!< Bit position for FMC_PFB0CR_B0ICE. */ -#define BM_FMC_PFB0CR_B0ICE (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */ -#define BS_FMC_PFB0CR_B0ICE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */ -#define BR_FMC_PFB0CR_B0ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */ -#define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE) - -/*! @brief Set the B0ICE field to a new value. */ -#define BW_FMC_PFB0CR_B0ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0DCE[4] (RW) - * - * This bit controls whether data references are loaded into the cache. - * - * Values: - * - 0 - Do not cache data references. - * - 1 - Cache data references. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0DCE (4U) /*!< Bit position for FMC_PFB0CR_B0DCE. */ -#define BM_FMC_PFB0CR_B0DCE (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */ -#define BS_FMC_PFB0CR_B0DCE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */ -#define BR_FMC_PFB0CR_B0DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE)) - -/*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */ -#define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE) - -/*! @brief Set the B0DCE field to a new value. */ -#define BW_FMC_PFB0CR_B0DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field CRC[7:5] (RW) - * - * This 3-bit field defines the replacement algorithm for accesses that are - * cached. - * - * Values: - * - 000 - LRU replacement algorithm per set across all four ways - * - 001 - Reserved - * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data - * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data - * - 1xx - Reserved - */ -/*@{*/ -#define BP_FMC_PFB0CR_CRC (5U) /*!< Bit position for FMC_PFB0CR_CRC. */ -#define BM_FMC_PFB0CR_CRC (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */ -#define BS_FMC_PFB0CR_CRC (3U) /*!< Bit field size in bits for FMC_PFB0CR_CRC. */ - -/*! @brief Read current value of the FMC_PFB0CR_CRC field. */ -#define BR_FMC_PFB0CR_CRC(x) (HW_FMC_PFB0CR(x).B.CRC) - -/*! @brief Format value for bitfield FMC_PFB0CR_CRC. */ -#define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC) - -/*! @brief Set the CRC field to a new value. */ -#define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v))) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0MW[18:17] (RO) - * - * This read-only field defines the width of the bank 0 memory. - * - * Values: - * - 00 - 32 bits - * - 01 - 64 bits - * - 10 - 128 bits - * - 11 - Reserved - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0MW (17U) /*!< Bit position for FMC_PFB0CR_B0MW. */ -#define BM_FMC_PFB0CR_B0MW (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */ -#define BS_FMC_PFB0CR_B0MW (2U) /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */ -#define BR_FMC_PFB0CR_B0MW(x) (HW_FMC_PFB0CR(x).B.B0MW) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ) - * - * This bit determines if the FMC's prefetch speculation buffer and the single - * entry page buffer are to be invalidated (cleared). When this bit is written, - * the speculation buffer and single entry buffer are immediately cleared. This bit - * always reads as zero. - * - * Values: - * - 0 - Speculation buffer and single entry buffer are not affected. - * - 1 - Invalidate (clear) speculation buffer and single entry buffer. - */ -/*@{*/ -#define BP_FMC_PFB0CR_S_B_INV (19U) /*!< Bit position for FMC_PFB0CR_S_B_INV. */ -#define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */ -#define BS_FMC_PFB0CR_S_B_INV (1U) /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */ - -/*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */ -#define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV) - -/*! @brief Set the S_B_INV field to a new value. */ -#define BW_FMC_PFB0CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ) - * - * These bits determine if the given cache way is to be invalidated (cleared). - * When a bit within this field is written, the corresponding cache way is - * immediately invalidated: the way's tag, data, and valid contents are cleared. This - * field always reads as zero. Cache invalidation takes precedence over locking. - * The cache is invalidated by system reset. System software is required to - * maintain memory coherency when any segment of the flash memory is programmed or - * erased. Accordingly, cache invalidations must occur after a programming or erase - * event is completed and before the new memory image is accessed. The bit setting - * definitions are for each bit in the field. - * - * Values: - * - 0 - No cache way invalidation for the corresponding cache - * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data, - * and vld bits of ways selected - */ -/*@{*/ -#define BP_FMC_PFB0CR_CINV_WAY (20U) /*!< Bit position for FMC_PFB0CR_CINV_WAY. */ -#define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */ -#define BS_FMC_PFB0CR_CINV_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */ - -/*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */ -#define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY) - -/*! @brief Set the CINV_WAY field to a new value. */ -#define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v))) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW) - * - * These bits determine if the given cache way is locked such that its contents - * will not be displaced by future misses. The bit setting definitions are for - * each bit in the field. - * - * Values: - * - 0 - Cache way is unlocked and may be displaced - * - 1 - Cache way is locked and its contents are not displaced - */ -/*@{*/ -#define BP_FMC_PFB0CR_CLCK_WAY (24U) /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */ -#define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */ -#define BS_FMC_PFB0CR_CLCK_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */ - -/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */ -#define BR_FMC_PFB0CR_CLCK_WAY(x) (HW_FMC_PFB0CR(x).B.CLCK_WAY) - -/*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */ -#define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY) - -/*! @brief Set the CLCK_WAY field to a new value. */ -#define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v))) -/*@}*/ - -/*! - * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO) - * - * This read-only field defines the number of wait states required to access the - * bank 0 flash memory. The relationship between the read access time of the - * flash array (expressed in system clock cycles) and RWSC is defined as: Access - * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates - * this value based on the ratio of the system clock speed to the flash clock - * speed. For example, when this ratio is 4:1, the field's value is 3h. - */ -/*@{*/ -#define BP_FMC_PFB0CR_B0RWSC (28U) /*!< Bit position for FMC_PFB0CR_B0RWSC. */ -#define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */ -#define BS_FMC_PFB0CR_B0RWSC (4U) /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */ - -/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */ -#define BR_FMC_PFB0CR_B0RWSC(x) (HW_FMC_PFB0CR(x).B.B0RWSC) -/*@}*/ - -/******************************************************************************* - * HW_FMC_PFB1CR - Flash Bank 1 Control Register - ******************************************************************************/ - -/*! - * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW) - * - * Reset value: 0x3004001FU - * - * This register has a format similar to that for PFB0CR, except it controls the - * operation of flash bank 1, and the "global" cache control fields are empty. - */ -typedef union _hw_fmc_pfb1cr -{ - uint32_t U; - struct _hw_fmc_pfb1cr_bitfields - { - uint32_t B1SEBE : 1; /*!< [0] Bank 1 Single Entry Buffer Enable */ - uint32_t B1IPE : 1; /*!< [1] Bank 1 Instruction Prefetch Enable */ - uint32_t B1DPE : 1; /*!< [2] Bank 1 Data Prefetch Enable */ - uint32_t B1ICE : 1; /*!< [3] Bank 1 Instruction Cache Enable */ - uint32_t B1DCE : 1; /*!< [4] Bank 1 Data Cache Enable */ - uint32_t RESERVED0 : 12; /*!< [16:5] */ - uint32_t B1MW : 2; /*!< [18:17] Bank 1 Memory Width */ - uint32_t RESERVED1 : 9; /*!< [27:19] */ - uint32_t B1RWSC : 4; /*!< [31:28] Bank 1 Read Wait State Control */ - } B; -} hw_fmc_pfb1cr_t; - -/*! - * @name Constants and macros for entire FMC_PFB1CR register - */ -/*@{*/ -#define HW_FMC_PFB1CR_ADDR(x) ((x) + 0x8U) - -#define HW_FMC_PFB1CR(x) (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x)) -#define HW_FMC_PFB1CR_RD(x) (HW_FMC_PFB1CR(x).U) -#define HW_FMC_PFB1CR_WR(x, v) (HW_FMC_PFB1CR(x).U = (v)) -#define HW_FMC_PFB1CR_SET(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) | (v))) -#define HW_FMC_PFB1CR_CLR(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v))) -#define HW_FMC_PFB1CR_TOG(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_PFB1CR bitfields - */ - -/*! - * @name Register FMC_PFB1CR, field B1SEBE[0] (RW) - * - * This bit controls whether the single entry buffer is enabled in response to - * flash read accesses. Its operation is independent from bank 0's cache. A - * high-to-low transition of this enable forces the page buffer to be invalidated. - * - * Values: - * - 0 - Single entry buffer is disabled. - * - 1 - Single entry buffer is enabled. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1SEBE (0U) /*!< Bit position for FMC_PFB1CR_B1SEBE. */ -#define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */ -#define BS_FMC_PFB1CR_B1SEBE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */ -#define BR_FMC_PFB1CR_B1SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */ -#define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE) - -/*! @brief Set the B1SEBE field to a new value. */ -#define BW_FMC_PFB1CR_B1SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1IPE[1] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to instruction fetches. - * - * Values: - * - 0 - Do not prefetch in response to instruction fetches. - * - 1 - Enable prefetches in response to instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1IPE (1U) /*!< Bit position for FMC_PFB1CR_B1IPE. */ -#define BM_FMC_PFB1CR_B1IPE (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */ -#define BS_FMC_PFB1CR_B1IPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */ -#define BR_FMC_PFB1CR_B1IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */ -#define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE) - -/*! @brief Set the B1IPE field to a new value. */ -#define BW_FMC_PFB1CR_B1IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1DPE[2] (RW) - * - * This bit controls whether prefetches (or speculative accesses) are initiated - * in response to data references. - * - * Values: - * - 0 - Do not prefetch in response to data references. - * - 1 - Enable prefetches in response to data references. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1DPE (2U) /*!< Bit position for FMC_PFB1CR_B1DPE. */ -#define BM_FMC_PFB1CR_B1DPE (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */ -#define BS_FMC_PFB1CR_B1DPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */ -#define BR_FMC_PFB1CR_B1DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */ -#define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE) - -/*! @brief Set the B1DPE field to a new value. */ -#define BW_FMC_PFB1CR_B1DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1ICE[3] (RW) - * - * This bit controls whether instruction fetches are loaded into the cache. - * - * Values: - * - 0 - Do not cache instruction fetches. - * - 1 - Cache instruction fetches. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1ICE (3U) /*!< Bit position for FMC_PFB1CR_B1ICE. */ -#define BM_FMC_PFB1CR_B1ICE (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */ -#define BS_FMC_PFB1CR_B1ICE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */ -#define BR_FMC_PFB1CR_B1ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */ -#define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE) - -/*! @brief Set the B1ICE field to a new value. */ -#define BW_FMC_PFB1CR_B1ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1DCE[4] (RW) - * - * This bit controls whether data references are loaded into the cache. - * - * Values: - * - 0 - Do not cache data references. - * - 1 - Cache data references. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1DCE (4U) /*!< Bit position for FMC_PFB1CR_B1DCE. */ -#define BM_FMC_PFB1CR_B1DCE (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */ -#define BS_FMC_PFB1CR_B1DCE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */ -#define BR_FMC_PFB1CR_B1DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE)) - -/*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */ -#define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE) - -/*! @brief Set the B1DCE field to a new value. */ -#define BW_FMC_PFB1CR_B1DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE) = (v)) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1MW[18:17] (RO) - * - * This read-only field defines the width of the bank 1 memory. - * - * Values: - * - 00 - 32 bits - * - 01 - 64 bits - * - 10 - 128 bits - * - 11 - Reserved - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1MW (17U) /*!< Bit position for FMC_PFB1CR_B1MW. */ -#define BM_FMC_PFB1CR_B1MW (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */ -#define BS_FMC_PFB1CR_B1MW (2U) /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */ -#define BR_FMC_PFB1CR_B1MW(x) (HW_FMC_PFB1CR(x).B.B1MW) -/*@}*/ - -/*! - * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO) - * - * This read-only field defines the number of wait states required to access the - * bank 1 flash memory. The relationship between the read access time of the - * flash array (expressed in system clock cycles) and RWSC is defined as: Access - * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates - * this value based on the ratio of the system clock speed to the flash clock - * speed. For example, when this ratio is 4:1, the field's value is 3h. - */ -/*@{*/ -#define BP_FMC_PFB1CR_B1RWSC (28U) /*!< Bit position for FMC_PFB1CR_B1RWSC. */ -#define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */ -#define BS_FMC_PFB1CR_B1RWSC (4U) /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */ - -/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */ -#define BR_FMC_PFB1CR_B1RWSC(x) (HW_FMC_PFB1CR(x).B.B1RWSC) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW0Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 4 sets. The ways are - * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw0sn -{ - uint32_t U; - struct _hw_fmc_tagvdw0sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw0sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW0Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW0Sn_COUNT (4U) - -#define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n))) - -#define HW_FMC_TAGVDW0Sn(x, n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U) -#define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW0Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW0Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW0Sn_valid (0U) /*!< Bit position for FMC_TAGVDW0Sn_valid. */ -#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */ -#define BS_FMC_TAGVDW0Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */ -#define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */ -#define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW0Sn_tag (5U) /*!< Bit position for FMC_TAGVDW0Sn_tag. */ -#define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */ -#define BS_FMC_TAGVDW0Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */ -#define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */ -#define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW1Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 4 sets. The ways are - * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw1sn -{ - uint32_t U; - struct _hw_fmc_tagvdw1sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw1sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW1Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW1Sn_COUNT (4U) - -#define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x110U + (0x4U * (n))) - -#define HW_FMC_TAGVDW1Sn(x, n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U) -#define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW1Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW1Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW1Sn_valid (0U) /*!< Bit position for FMC_TAGVDW1Sn_valid. */ -#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */ -#define BS_FMC_TAGVDW1Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */ -#define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */ -#define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW1Sn_tag (5U) /*!< Bit position for FMC_TAGVDW1Sn_tag. */ -#define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */ -#define BS_FMC_TAGVDW1Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */ -#define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */ -#define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW2Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 4 sets. The ways are - * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw2sn -{ - uint32_t U; - struct _hw_fmc_tagvdw2sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw2sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW2Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW2Sn_COUNT (4U) - -#define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n))) - -#define HW_FMC_TAGVDW2Sn(x, n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U) -#define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW2Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW2Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW2Sn_valid (0U) /*!< Bit position for FMC_TAGVDW2Sn_valid. */ -#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */ -#define BS_FMC_TAGVDW2Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */ -#define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */ -#define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW2Sn_tag (5U) /*!< Bit position for FMC_TAGVDW2Sn_tag. */ -#define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */ -#define BS_FMC_TAGVDW2Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */ -#define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */ -#define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_TAGVDW3Sn - Cache Tag Storage - ******************************************************************************/ - -/*! - * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW) - * - * Reset value: 0x00000000U - * - * The cache is a 4-way, set-associative cache with 4 sets. The ways are - * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y - * denotes the set. This section represents tag/vld information for all sets in the - * indicated way. - */ -typedef union _hw_fmc_tagvdw3sn -{ - uint32_t U; - struct _hw_fmc_tagvdw3sn_bitfields - { - uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ - uint32_t RESERVED0 : 4; /*!< [4:1] */ - uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ - uint32_t RESERVED1 : 13; /*!< [31:19] */ - } B; -} hw_fmc_tagvdw3sn_t; - -/*! - * @name Constants and macros for entire FMC_TAGVDW3Sn register - */ -/*@{*/ -#define HW_FMC_TAGVDW3Sn_COUNT (4U) - -#define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x130U + (0x4U * (n))) - -#define HW_FMC_TAGVDW3Sn(x, n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n)) -#define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U) -#define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v)) -#define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) | (v))) -#define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v))) -#define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_TAGVDW3Sn bitfields - */ - -/*! - * @name Register FMC_TAGVDW3Sn, field valid[0] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW3Sn_valid (0U) /*!< Bit position for FMC_TAGVDW3Sn_valid. */ -#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */ -#define BS_FMC_TAGVDW3Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */ - -/*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */ -#define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid)) - -/*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */ -#define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid) - -/*! @brief Set the valid field to a new value. */ -#define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v)) -/*@}*/ - -/*! - * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW) - */ -/*@{*/ -#define BP_FMC_TAGVDW3Sn_tag (5U) /*!< Bit position for FMC_TAGVDW3Sn_tag. */ -#define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */ -#define BS_FMC_TAGVDW3Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */ - -/*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */ -#define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag) - -/*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */ -#define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag) - -/*! @brief Set the tag field to a new value. */ -#define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v))) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW0SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw0snu -{ - uint32_t U; - struct _hw_fmc_dataw0snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw0snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW0SnU register - */ -/*@{*/ -#define HW_FMC_DATAW0SnU_COUNT (4U) - -#define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n))) - -#define HW_FMC_DATAW0SnU(x, n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n)) -#define HW_FMC_DATAW0SnU_RD(x, n) (HW_FMC_DATAW0SnU(x, n).U) -#define HW_FMC_DATAW0SnU_WR(x, n, v) (HW_FMC_DATAW0SnU(x, n).U = (v)) -#define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW0SnU bitfields - */ - -/*! - * @name Register FMC_DATAW0SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW0SnU_data (0U) /*!< Bit position for FMC_DATAW0SnU_data. */ -#define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */ -#define BS_FMC_DATAW0SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW0SnU_data field. */ -#define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW0SnU_data. */ -#define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW0SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw0snl -{ - uint32_t U; - struct _hw_fmc_dataw0snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw0snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW0SnL register - */ -/*@{*/ -#define HW_FMC_DATAW0SnL_COUNT (4U) - -#define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n))) - -#define HW_FMC_DATAW0SnL(x, n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n)) -#define HW_FMC_DATAW0SnL_RD(x, n) (HW_FMC_DATAW0SnL(x, n).U) -#define HW_FMC_DATAW0SnL_WR(x, n, v) (HW_FMC_DATAW0SnL(x, n).U = (v)) -#define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW0SnL bitfields - */ - -/*! - * @name Register FMC_DATAW0SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW0SnL_data (0U) /*!< Bit position for FMC_DATAW0SnL_data. */ -#define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */ -#define BS_FMC_DATAW0SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW0SnL_data field. */ -#define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW0SnL_data. */ -#define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW1SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw1snu -{ - uint32_t U; - struct _hw_fmc_dataw1snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw1snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW1SnU register - */ -/*@{*/ -#define HW_FMC_DATAW1SnU_COUNT (4U) - -#define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x220U + (0x8U * (n))) - -#define HW_FMC_DATAW1SnU(x, n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n)) -#define HW_FMC_DATAW1SnU_RD(x, n) (HW_FMC_DATAW1SnU(x, n).U) -#define HW_FMC_DATAW1SnU_WR(x, n, v) (HW_FMC_DATAW1SnU(x, n).U = (v)) -#define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW1SnU bitfields - */ - -/*! - * @name Register FMC_DATAW1SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW1SnU_data (0U) /*!< Bit position for FMC_DATAW1SnU_data. */ -#define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */ -#define BS_FMC_DATAW1SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW1SnU_data field. */ -#define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW1SnU_data. */ -#define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW1SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw1snl -{ - uint32_t U; - struct _hw_fmc_dataw1snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw1snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW1SnL register - */ -/*@{*/ -#define HW_FMC_DATAW1SnL_COUNT (4U) - -#define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x224U + (0x8U * (n))) - -#define HW_FMC_DATAW1SnL(x, n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n)) -#define HW_FMC_DATAW1SnL_RD(x, n) (HW_FMC_DATAW1SnL(x, n).U) -#define HW_FMC_DATAW1SnL_WR(x, n, v) (HW_FMC_DATAW1SnL(x, n).U = (v)) -#define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW1SnL bitfields - */ - -/*! - * @name Register FMC_DATAW1SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW1SnL_data (0U) /*!< Bit position for FMC_DATAW1SnL_data. */ -#define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */ -#define BS_FMC_DATAW1SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW1SnL_data field. */ -#define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW1SnL_data. */ -#define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW2SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw2snu -{ - uint32_t U; - struct _hw_fmc_dataw2snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw2snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW2SnU register - */ -/*@{*/ -#define HW_FMC_DATAW2SnU_COUNT (4U) - -#define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n))) - -#define HW_FMC_DATAW2SnU(x, n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n)) -#define HW_FMC_DATAW2SnU_RD(x, n) (HW_FMC_DATAW2SnU(x, n).U) -#define HW_FMC_DATAW2SnU_WR(x, n, v) (HW_FMC_DATAW2SnU(x, n).U = (v)) -#define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW2SnU bitfields - */ - -/*! - * @name Register FMC_DATAW2SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW2SnU_data (0U) /*!< Bit position for FMC_DATAW2SnU_data. */ -#define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */ -#define BS_FMC_DATAW2SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW2SnU_data field. */ -#define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW2SnU_data. */ -#define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW2SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw2snl -{ - uint32_t U; - struct _hw_fmc_dataw2snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw2snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW2SnL register - */ -/*@{*/ -#define HW_FMC_DATAW2SnL_COUNT (4U) - -#define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n))) - -#define HW_FMC_DATAW2SnL(x, n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n)) -#define HW_FMC_DATAW2SnL_RD(x, n) (HW_FMC_DATAW2SnL(x, n).U) -#define HW_FMC_DATAW2SnL_WR(x, n, v) (HW_FMC_DATAW2SnL(x, n).U = (v)) -#define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW2SnL bitfields - */ - -/*! - * @name Register FMC_DATAW2SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW2SnL_data (0U) /*!< Bit position for FMC_DATAW2SnL_data. */ -#define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */ -#define BS_FMC_DATAW2SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW2SnL_data field. */ -#define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW2SnL_data. */ -#define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_FMC_DATAW3SnU - Cache Data Storage (upper word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the upper word (bits - * [63:32]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw3snu -{ - uint32_t U; - struct _hw_fmc_dataw3snu_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ - } B; -} hw_fmc_dataw3snu_t; - -/*! - * @name Constants and macros for entire FMC_DATAW3SnU register - */ -/*@{*/ -#define HW_FMC_DATAW3SnU_COUNT (4U) - -#define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x260U + (0x8U * (n))) - -#define HW_FMC_DATAW3SnU(x, n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n)) -#define HW_FMC_DATAW3SnU_RD(x, n) (HW_FMC_DATAW3SnU(x, n).U) -#define HW_FMC_DATAW3SnU_WR(x, n, v) (HW_FMC_DATAW3SnU(x, n).U = (v)) -#define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) | (v))) -#define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v))) -#define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW3SnU bitfields - */ - -/*! - * @name Register FMC_DATAW3SnU, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW3SnU_data (0U) /*!< Bit position for FMC_DATAW3SnU_data. */ -#define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */ -#define BS_FMC_DATAW3SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnU_data. */ - -/*! @brief Read current value of the FMC_DATAW3SnU_data field. */ -#define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW3SnU_data. */ -#define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_FMC_DATAW3SnL - Cache Data Storage (lower word) - ******************************************************************************/ - -/*! - * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW) - * - * Reset value: 0x00000000U - * - * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. - * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and - * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and - * lower word, respectively. This section represents data for the lower word (bits - * [31:0]) of all sets in the indicated way. - */ -typedef union _hw_fmc_dataw3snl -{ - uint32_t U; - struct _hw_fmc_dataw3snl_bitfields - { - uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ - } B; -} hw_fmc_dataw3snl_t; - -/*! - * @name Constants and macros for entire FMC_DATAW3SnL register - */ -/*@{*/ -#define HW_FMC_DATAW3SnL_COUNT (4U) - -#define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x264U + (0x8U * (n))) - -#define HW_FMC_DATAW3SnL(x, n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n)) -#define HW_FMC_DATAW3SnL_RD(x, n) (HW_FMC_DATAW3SnL(x, n).U) -#define HW_FMC_DATAW3SnL_WR(x, n, v) (HW_FMC_DATAW3SnL(x, n).U = (v)) -#define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) | (v))) -#define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v))) -#define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FMC_DATAW3SnL bitfields - */ - -/*! - * @name Register FMC_DATAW3SnL, field data[31:0] (RW) - */ -/*@{*/ -#define BP_FMC_DATAW3SnL_data (0U) /*!< Bit position for FMC_DATAW3SnL_data. */ -#define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */ -#define BS_FMC_DATAW3SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnL_data. */ - -/*! @brief Read current value of the FMC_DATAW3SnL_data field. */ -#define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U) - -/*! @brief Format value for bitfield FMC_DATAW3SnL_data. */ -#define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data) - -/*! @brief Set the data field to a new value. */ -#define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * hw_fmc_t - module struct - ******************************************************************************/ -/*! - * @brief All FMC module registers. - */ -#pragma pack(1) -typedef struct _hw_fmc -{ - __IO hw_fmc_pfapr_t PFAPR; /*!< [0x0] Flash Access Protection Register */ - __IO hw_fmc_pfb0cr_t PFB0CR; /*!< [0x4] Flash Bank 0 Control Register */ - __IO hw_fmc_pfb1cr_t PFB1CR; /*!< [0x8] Flash Bank 1 Control Register */ - uint8_t _reserved0[244]; - __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4]; /*!< [0x100] Cache Tag Storage */ - __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4]; /*!< [0x110] Cache Tag Storage */ - __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4]; /*!< [0x120] Cache Tag Storage */ - __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4]; /*!< [0x130] Cache Tag Storage */ - uint8_t _reserved1[192]; - struct { - __IO hw_fmc_dataw0snu_t DATAW0SnU; /*!< [0x200] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw0snl_t DATAW0SnL; /*!< [0x204] Cache Data Storage (lower word) */ - } DATAW0Sn[4]; - struct { - __IO hw_fmc_dataw1snu_t DATAW1SnU; /*!< [0x220] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw1snl_t DATAW1SnL; /*!< [0x224] Cache Data Storage (lower word) */ - } DATAW1Sn[4]; - struct { - __IO hw_fmc_dataw2snu_t DATAW2SnU; /*!< [0x240] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw2snl_t DATAW2SnL; /*!< [0x244] Cache Data Storage (lower word) */ - } DATAW2Sn[4]; - struct { - __IO hw_fmc_dataw3snu_t DATAW3SnU; /*!< [0x260] Cache Data Storage (upper word) */ - __IO hw_fmc_dataw3snl_t DATAW3SnL; /*!< [0x264] Cache Data Storage (lower word) */ - } DATAW3Sn[4]; -} hw_fmc_t; -#pragma pack() - -/*! @brief Macro to access all FMC registers. */ -/*! @param x FMC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FMC(FMC_BASE). */ -#define HW_FMC(x) (*(hw_fmc_t *)(x)) - -#endif /* __HW_FMC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftfe.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftfe.h deleted file mode 100644 index 6ee62253fb6..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftfe.h +++ /dev/null @@ -1,2344 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FTFE_REGISTERS_H__ -#define __HW_FTFE_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 FTFE - * - * Flash Memory Interface - * - * Registers defined in this header file: - * - HW_FTFE_FSTAT - Flash Status Register - * - HW_FTFE_FCNFG - Flash Configuration Register - * - HW_FTFE_FSEC - Flash Security Register - * - HW_FTFE_FOPT - Flash Option Register - * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers - * - HW_FTFE_FCCOBB - Flash Common Command Object Registers - * - HW_FTFE_FCCOBA - Flash Common Command Object Registers - * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers - * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers - * - HW_FTFE_FPROT3 - Program Flash Protection Registers - * - HW_FTFE_FPROT2 - Program Flash Protection Registers - * - HW_FTFE_FPROT1 - Program Flash Protection Registers - * - HW_FTFE_FPROT0 - Program Flash Protection Registers - * - HW_FTFE_FEPROT - EEPROM Protection Register - * - HW_FTFE_FDPROT - Data Flash Protection Register - * - * - hw_ftfe_t - Struct containing all module registers. - */ - -#define HW_FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */ - -/******************************************************************************* - * HW_FTFE_FSTAT - Flash Status Register - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FSTAT - Flash Status Register (RW) - * - * Reset value: 0x00U - * - * The FSTAT register reports the operational status of the FTFE module. The - * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 - * bit is read only. The unassigned bits read 0 and are not writable. When set, the - * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this - * register prevent the launch of any more commands or writes to the FlexRAM (when - * EEERDY is set) until the flag is cleared (by writing a one to it). - */ -typedef union _hw_ftfe_fstat -{ - uint8_t U; - struct _hw_ftfe_fstat_bitfields - { - uint8_t MGSTAT0 : 1; /*!< [0] Memory Controller Command Completion - * Status Flag */ - uint8_t RESERVED0 : 3; /*!< [3:1] */ - uint8_t FPVIOL : 1; /*!< [4] Flash Protection Violation Flag */ - uint8_t ACCERR : 1; /*!< [5] Flash Access Error Flag */ - uint8_t RDCOLERR : 1; /*!< [6] FTFE Read Collision Error Flag */ - uint8_t CCIF : 1; /*!< [7] Command Complete Interrupt Flag */ - } B; -} hw_ftfe_fstat_t; - -/*! - * @name Constants and macros for entire FTFE_FSTAT register - */ -/*@{*/ -#define HW_FTFE_FSTAT_ADDR(x) ((x) + 0x0U) - -#define HW_FTFE_FSTAT(x) (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR(x)) -#define HW_FTFE_FSTAT_RD(x) (HW_FTFE_FSTAT(x).U) -#define HW_FTFE_FSTAT_WR(x, v) (HW_FTFE_FSTAT(x).U = (v)) -#define HW_FTFE_FSTAT_SET(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) | (v))) -#define HW_FTFE_FSTAT_CLR(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) & ~(v))) -#define HW_FTFE_FSTAT_TOG(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FSTAT bitfields - */ - -/*! - * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO) - * - * The MGSTAT0 status flag is set if an error is detected during execution of an - * FTFE command or during the flash reset sequence. As a status flag, this bit - * cannot (and need not) be cleared by the user like the other error flags in this - * register. The value of the MGSTAT0 bit for "command-N" is valid only at the - * end of the "command-N" execution when CCIF=1 and before the next command has - * been launched. At some point during the execution of "command-N+1," the previous - * result is discarded and any previous error is cleared. - */ -/*@{*/ -#define BP_FTFE_FSTAT_MGSTAT0 (0U) /*!< Bit position for FTFE_FSTAT_MGSTAT0. */ -#define BM_FTFE_FSTAT_MGSTAT0 (0x01U) /*!< Bit mask for FTFE_FSTAT_MGSTAT0. */ -#define BS_FTFE_FSTAT_MGSTAT0 (1U) /*!< Bit field size in bits for FTFE_FSTAT_MGSTAT0. */ - -/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */ -#define BR_FTFE_FSTAT_MGSTAT0(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_MGSTAT0)) -/*@}*/ - -/*! - * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C) - * - * The FPVIOL error bit indicates an attempt was made to program or erase an - * address in a protected area of program flash or data flash memory during a - * command write sequence or a write was attempted to a protected area of the FlexRAM - * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared - * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a - * 0 to the FPVIOL bit has no effect. - * - * Values: - * - 0 - No protection violation detected - * - 1 - Protection violation detected - */ -/*@{*/ -#define BP_FTFE_FSTAT_FPVIOL (4U) /*!< Bit position for FTFE_FSTAT_FPVIOL. */ -#define BM_FTFE_FSTAT_FPVIOL (0x10U) /*!< Bit mask for FTFE_FSTAT_FPVIOL. */ -#define BS_FTFE_FSTAT_FPVIOL (1U) /*!< Bit field size in bits for FTFE_FSTAT_FPVIOL. */ - -/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */ -#define BR_FTFE_FSTAT_FPVIOL(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL)) - -/*! @brief Format value for bitfield FTFE_FSTAT_FPVIOL. */ -#define BF_FTFE_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_FPVIOL) & BM_FTFE_FSTAT_FPVIOL) - -/*! @brief Set the FPVIOL field to a new value. */ -#define BW_FTFE_FSTAT_FPVIOL(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL) = (v)) -/*@}*/ - -/*! - * @name Register FTFE_FSTAT, field ACCERR[5] (W1C) - * - * The ACCERR error bit indicates an illegal access has occurred to an FTFE - * resource caused by a violation of the command write sequence or issuing an illegal - * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch - * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the - * ACCERR bit has no effect. - * - * Values: - * - 0 - No access error detected - * - 1 - Access error detected - */ -/*@{*/ -#define BP_FTFE_FSTAT_ACCERR (5U) /*!< Bit position for FTFE_FSTAT_ACCERR. */ -#define BM_FTFE_FSTAT_ACCERR (0x20U) /*!< Bit mask for FTFE_FSTAT_ACCERR. */ -#define BS_FTFE_FSTAT_ACCERR (1U) /*!< Bit field size in bits for FTFE_FSTAT_ACCERR. */ - -/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */ -#define BR_FTFE_FSTAT_ACCERR(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR)) - -/*! @brief Format value for bitfield FTFE_FSTAT_ACCERR. */ -#define BF_FTFE_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_ACCERR) & BM_FTFE_FSTAT_ACCERR) - -/*! @brief Set the ACCERR field to a new value. */ -#define BW_FTFE_FSTAT_ACCERR(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR) = (v)) -/*@}*/ - -/*! - * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C) - * - * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE - * resource that was being manipulated by an FTFE command (CCIF=0). Any - * simultaneous access is detected as a collision error by the block arbitration logic. The - * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by - * writing a 1 to it. Writing a 0 to RDCOLERR has no effect. - * - * Values: - * - 0 - No collision error detected - * - 1 - Collision error detected - */ -/*@{*/ -#define BP_FTFE_FSTAT_RDCOLERR (6U) /*!< Bit position for FTFE_FSTAT_RDCOLERR. */ -#define BM_FTFE_FSTAT_RDCOLERR (0x40U) /*!< Bit mask for FTFE_FSTAT_RDCOLERR. */ -#define BS_FTFE_FSTAT_RDCOLERR (1U) /*!< Bit field size in bits for FTFE_FSTAT_RDCOLERR. */ - -/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */ -#define BR_FTFE_FSTAT_RDCOLERR(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR)) - -/*! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR. */ -#define BF_FTFE_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_RDCOLERR) & BM_FTFE_FSTAT_RDCOLERR) - -/*! @brief Set the RDCOLERR field to a new value. */ -#define BW_FTFE_FSTAT_RDCOLERR(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR) = (v)) -/*@}*/ - -/*! - * @name Register FTFE_FSTAT, field CCIF[7] (W1C) - * - * The CCIF flag indicates that a FTFE command or EEPROM file system operation - * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a - * command, and CCIF stays low until command completion or command violation. The - * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE, - * and CCIF stays low until the EEPROM file system has created the associated - * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory - * controller at the end of the reset initialization sequence. Depending on how - * quickly the read occurs after reset release, the user may or may not see the 0 - * hardware reset value. - * - * Values: - * - 0 - FTFE command or EEPROM file system operation in progress - * - 1 - FTFE command or EEPROM file system operation has completed - */ -/*@{*/ -#define BP_FTFE_FSTAT_CCIF (7U) /*!< Bit position for FTFE_FSTAT_CCIF. */ -#define BM_FTFE_FSTAT_CCIF (0x80U) /*!< Bit mask for FTFE_FSTAT_CCIF. */ -#define BS_FTFE_FSTAT_CCIF (1U) /*!< Bit field size in bits for FTFE_FSTAT_CCIF. */ - -/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */ -#define BR_FTFE_FSTAT_CCIF(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF)) - -/*! @brief Format value for bitfield FTFE_FSTAT_CCIF. */ -#define BF_FTFE_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_CCIF) & BM_FTFE_FSTAT_CCIF) - -/*! @brief Set the CCIF field to a new value. */ -#define BW_FTFE_FSTAT_CCIF(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCNFG - Flash Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW) - * - * Reset value: 0x00U - * - * This register provides information on the current functional state of the - * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write - * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned - * bits read as noted and are not writable. The reset values for the SWAP, PFLSH, - * RAMRDY, and EEERDY bits are determined during the reset sequence. - */ -typedef union _hw_ftfe_fcnfg -{ - uint8_t U; - struct _hw_ftfe_fcnfg_bitfields - { - uint8_t EEERDY : 1; /*!< [0] */ - uint8_t RAMRDY : 1; /*!< [1] RAM Ready */ - uint8_t PFLSH : 1; /*!< [2] FTFE configuration */ - uint8_t SWAP : 1; /*!< [3] Swap */ - uint8_t ERSSUSP : 1; /*!< [4] Erase Suspend */ - uint8_t ERSAREQ : 1; /*!< [5] Erase All Request */ - uint8_t RDCOLLIE : 1; /*!< [6] Read Collision Error Interrupt Enable - * */ - uint8_t CCIE : 1; /*!< [7] Command Complete Interrupt Enable */ - } B; -} hw_ftfe_fcnfg_t; - -/*! - * @name Constants and macros for entire FTFE_FCNFG register - */ -/*@{*/ -#define HW_FTFE_FCNFG_ADDR(x) ((x) + 0x1U) - -#define HW_FTFE_FCNFG(x) (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR(x)) -#define HW_FTFE_FCNFG_RD(x) (HW_FTFE_FCNFG(x).U) -#define HW_FTFE_FCNFG_WR(x, v) (HW_FTFE_FCNFG(x).U = (v)) -#define HW_FTFE_FCNFG_SET(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) | (v))) -#define HW_FTFE_FCNFG_CLR(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) & ~(v))) -#define HW_FTFE_FCNFG_TOG(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCNFG bitfields - */ - -/*! - * @name Register FTFE_FCNFG, field EEERDY[0] (RO) - * - * For devices with FlexNVM: This flag indicates if the EEPROM backup data has - * been copied to the FlexRAM and is therefore available for read access. During - * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if - * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM: - * This bit is reserved. - * - * Values: - * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation. - * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations - * where: reads from the FlexRAM return data previously written to the FlexRAM - * in EEPROM mode and writes launch an EEPROM operation to store the written - * data in the FlexRAM and EEPROM backup. - */ -/*@{*/ -#define BP_FTFE_FCNFG_EEERDY (0U) /*!< Bit position for FTFE_FCNFG_EEERDY. */ -#define BM_FTFE_FCNFG_EEERDY (0x01U) /*!< Bit mask for FTFE_FCNFG_EEERDY. */ -#define BS_FTFE_FCNFG_EEERDY (1U) /*!< Bit field size in bits for FTFE_FCNFG_EEERDY. */ - -/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */ -#define BR_FTFE_FCNFG_EEERDY(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_EEERDY)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field RAMRDY[1] (RO) - * - * This flag indicates the current status of the FlexRAM/ programming - * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally - * controlled by the Set FlexRAM Function command. During the reset sequence, the - * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will - * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is - * cleared if the Program Partition command is run to partition the FlexNVM block - * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks - * command or execution of the erase-all operation triggered external to the FTFE. - * For devices without FlexNVM: This bit should always be set. - * - * Values: - * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM - * access. For devices without FlexNVM: Programming acceleration RAM is not - * available. - * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only; - * writes to the FlexRAM do not trigger EEPROM operations. For devices - * without FlexNVM: Programming acceleration RAM is available. - */ -/*@{*/ -#define BP_FTFE_FCNFG_RAMRDY (1U) /*!< Bit position for FTFE_FCNFG_RAMRDY. */ -#define BM_FTFE_FCNFG_RAMRDY (0x02U) /*!< Bit mask for FTFE_FCNFG_RAMRDY. */ -#define BS_FTFE_FCNFG_RAMRDY (1U) /*!< Bit field size in bits for FTFE_FCNFG_RAMRDY. */ - -/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */ -#define BR_FTFE_FCNFG_RAMRDY(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RAMRDY)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field PFLSH[2] (RO) - * - * Values: - * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash - * blocks and two FlexNVM blocks For devices with program flash only: - * Reserved - * - 1 - For devices with FlexNVM: Reserved For devices with program flash only: - * FTFE configuration supports four program flash blocks - */ -/*@{*/ -#define BP_FTFE_FCNFG_PFLSH (2U) /*!< Bit position for FTFE_FCNFG_PFLSH. */ -#define BM_FTFE_FCNFG_PFLSH (0x04U) /*!< Bit mask for FTFE_FCNFG_PFLSH. */ -#define BS_FTFE_FCNFG_PFLSH (1U) /*!< Bit field size in bits for FTFE_FCNFG_PFLSH. */ - -/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */ -#define BR_FTFE_FCNFG_PFLSH(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_PFLSH)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field SWAP[3] (RO) - * - * The SWAP flag indicates which half of the program flash space is located at - * relative address 0x0000. The state of the SWAP flag is set by the FTFE during - * the reset sequence. See for information on swap management. - * - * Values: - * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative - * address 0x0000 For devices with program flash only: Program flash 0 block - * is located at relative address 0x0000 - * - 1 - For devices with FlexNVM: Reserved For devices with program flash only: - * Program flash 1 block is located at relative address 0x0000 - */ -/*@{*/ -#define BP_FTFE_FCNFG_SWAP (3U) /*!< Bit position for FTFE_FCNFG_SWAP. */ -#define BM_FTFE_FCNFG_SWAP (0x08U) /*!< Bit mask for FTFE_FCNFG_SWAP. */ -#define BS_FTFE_FCNFG_SWAP (1U) /*!< Bit field size in bits for FTFE_FCNFG_SWAP. */ - -/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */ -#define BR_FTFE_FCNFG_SWAP(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_SWAP)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW) - * - * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector - * command while it is executing. - * - * Values: - * - 0 - No suspend requested - * - 1 - Suspend the current Erase Flash Sector command execution. - */ -/*@{*/ -#define BP_FTFE_FCNFG_ERSSUSP (4U) /*!< Bit position for FTFE_FCNFG_ERSSUSP. */ -#define BM_FTFE_FCNFG_ERSSUSP (0x10U) /*!< Bit mask for FTFE_FCNFG_ERSSUSP. */ -#define BS_FTFE_FCNFG_ERSSUSP (1U) /*!< Bit field size in bits for FTFE_FCNFG_ERSSUSP. */ - -/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */ -#define BR_FTFE_FCNFG_ERSSUSP(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP)) - -/*! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP. */ -#define BF_FTFE_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_ERSSUSP) & BM_FTFE_FCNFG_ERSSUSP) - -/*! @brief Set the ERSSUSP field to a new value. */ -#define BW_FTFE_FCNFG_ERSSUSP(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP) = (v)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO) - * - * This bit issues a request to the memory controller to execute the Erase All - * Blocks command and release security. ERSAREQ is not directly writable but is - * under indirect user control. Refer to the device's Chip Configuration details on - * how to request this command. The ERSAREQ bit sets when an erase all request - * is triggered external to the FTFE and CCIF is set (no command is currently - * being executed). ERSAREQ is cleared by the FTFE when the operation completes. - * - * Values: - * - 0 - No request or request complete - * - 1 - Request to: run the Erase All Blocks command, verify the erased state, - * program the security byte in the Flash Configuration Field to the unsecure - * state, and release MCU security by setting the FSEC[SEC] field to the - * unsecure state. - */ -/*@{*/ -#define BP_FTFE_FCNFG_ERSAREQ (5U) /*!< Bit position for FTFE_FCNFG_ERSAREQ. */ -#define BM_FTFE_FCNFG_ERSAREQ (0x20U) /*!< Bit mask for FTFE_FCNFG_ERSAREQ. */ -#define BS_FTFE_FCNFG_ERSAREQ (1U) /*!< Bit field size in bits for FTFE_FCNFG_ERSAREQ. */ - -/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */ -#define BR_FTFE_FCNFG_ERSAREQ(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSAREQ)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW) - * - * The RDCOLLIE bit controls interrupt generation when an FTFE read collision - * error occurs. - * - * Values: - * - 0 - Read collision error interrupt disabled - * - 1 - Read collision error interrupt enabled. An interrupt request is - * generated whenever an FTFE read collision error is detected (see the description - * of FSTAT[RDCOLERR]). - */ -/*@{*/ -#define BP_FTFE_FCNFG_RDCOLLIE (6U) /*!< Bit position for FTFE_FCNFG_RDCOLLIE. */ -#define BM_FTFE_FCNFG_RDCOLLIE (0x40U) /*!< Bit mask for FTFE_FCNFG_RDCOLLIE. */ -#define BS_FTFE_FCNFG_RDCOLLIE (1U) /*!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE. */ - -/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */ -#define BR_FTFE_FCNFG_RDCOLLIE(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE)) - -/*! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE. */ -#define BF_FTFE_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_RDCOLLIE) & BM_FTFE_FCNFG_RDCOLLIE) - -/*! @brief Set the RDCOLLIE field to a new value. */ -#define BW_FTFE_FCNFG_RDCOLLIE(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE) = (v)) -/*@}*/ - -/*! - * @name Register FTFE_FCNFG, field CCIE[7] (RW) - * - * The CCIE bit controls interrupt generation when an FTFE command completes. - * - * Values: - * - 0 - Command complete interrupt disabled - * - 1 - Command complete interrupt enabled. An interrupt request is generated - * whenever the FSTAT[CCIF] flag is set. - */ -/*@{*/ -#define BP_FTFE_FCNFG_CCIE (7U) /*!< Bit position for FTFE_FCNFG_CCIE. */ -#define BM_FTFE_FCNFG_CCIE (0x80U) /*!< Bit mask for FTFE_FCNFG_CCIE. */ -#define BS_FTFE_FCNFG_CCIE (1U) /*!< Bit field size in bits for FTFE_FCNFG_CCIE. */ - -/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */ -#define BR_FTFE_FCNFG_CCIE(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE)) - -/*! @brief Format value for bitfield FTFE_FCNFG_CCIE. */ -#define BF_FTFE_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_CCIE) & BM_FTFE_FCNFG_CCIE) - -/*! @brief Set the CCIE field to a new value. */ -#define BW_FTFE_FCNFG_CCIE(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FSEC - Flash Security Register - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FSEC - Flash Security Register (RO) - * - * Reset value: 0x00U - * - * This read-only register holds all bits associated with the security of the - * MCU and FTFE module. During the reset sequence, the register is loaded with the - * contents of the flash security byte in the Flash Configuration Field located - * in program flash memory. The Flash basis for the values is signified by X in - * the reset value. - */ -typedef union _hw_ftfe_fsec -{ - uint8_t U; - struct _hw_ftfe_fsec_bitfields - { - uint8_t SEC : 2; /*!< [1:0] Flash Security */ - uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code - * */ - uint8_t MEEN : 2; /*!< [5:4] Mass Erase Enable Bits */ - uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */ - } B; -} hw_ftfe_fsec_t; - -/*! - * @name Constants and macros for entire FTFE_FSEC register - */ -/*@{*/ -#define HW_FTFE_FSEC_ADDR(x) ((x) + 0x2U) - -#define HW_FTFE_FSEC(x) (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR(x)) -#define HW_FTFE_FSEC_RD(x) (HW_FTFE_FSEC(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FSEC bitfields - */ - -/*! - * @name Register FTFE_FSEC, field SEC[1:0] (RO) - * - * These bits define the security state of the MCU. In the secure state, the MCU - * limits access to FTFE module resources. The limitations are defined per - * device and are detailed in the Chip Configuration details. If the FTFE module is - * unsecured using backdoor key access, the SEC bits are forced to 10b. - * - * Values: - * - 00 - MCU security status is secure - * - 01 - MCU security status is secure - * - 10 - MCU security status is unsecure (The standard shipping condition of - * the FTFE is unsecure.) - * - 11 - MCU security status is secure - */ -/*@{*/ -#define BP_FTFE_FSEC_SEC (0U) /*!< Bit position for FTFE_FSEC_SEC. */ -#define BM_FTFE_FSEC_SEC (0x03U) /*!< Bit mask for FTFE_FSEC_SEC. */ -#define BS_FTFE_FSEC_SEC (2U) /*!< Bit field size in bits for FTFE_FSEC_SEC. */ - -/*! @brief Read current value of the FTFE_FSEC_SEC field. */ -#define BR_FTFE_FSEC_SEC(x) (HW_FTFE_FSEC(x).B.SEC) -/*@}*/ - -/*! - * @name Register FTFE_FSEC, field FSLACC[3:2] (RO) - * - * These bits enable or disable access to the flash memory contents during - * returned part failure analysis at Freescale. When SEC is secure and FSLACC is - * denied, access to the program flash contents is denied and any failure analysis - * performed by Freescale factory test must begin with a full erase to unsecure the - * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is - * granted), Freescale factory testing has visibility of the current flash - * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to - * secure. When the SEC field is set to unsecure, the FSLACC setting does not - * matter. - * - * Values: - * - 00 - Freescale factory access granted - * - 01 - Freescale factory access denied - * - 10 - Freescale factory access denied - * - 11 - Freescale factory access granted - */ -/*@{*/ -#define BP_FTFE_FSEC_FSLACC (2U) /*!< Bit position for FTFE_FSEC_FSLACC. */ -#define BM_FTFE_FSEC_FSLACC (0x0CU) /*!< Bit mask for FTFE_FSEC_FSLACC. */ -#define BS_FTFE_FSEC_FSLACC (2U) /*!< Bit field size in bits for FTFE_FSEC_FSLACC. */ - -/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */ -#define BR_FTFE_FSEC_FSLACC(x) (HW_FTFE_FSEC(x).B.FSLACC) -/*@}*/ - -/*! - * @name Register FTFE_FSEC, field MEEN[5:4] (RO) - * - * Enables and disables mass erase capability of the FTFE module. The state of - * the MEEN bits is only relevant when the SEC bits are set to secure outside of - * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does - * not matter. - * - * Values: - * - 00 - Mass erase is enabled - * - 01 - Mass erase is enabled - * - 10 - Mass erase is disabled - * - 11 - Mass erase is enabled - */ -/*@{*/ -#define BP_FTFE_FSEC_MEEN (4U) /*!< Bit position for FTFE_FSEC_MEEN. */ -#define BM_FTFE_FSEC_MEEN (0x30U) /*!< Bit mask for FTFE_FSEC_MEEN. */ -#define BS_FTFE_FSEC_MEEN (2U) /*!< Bit field size in bits for FTFE_FSEC_MEEN. */ - -/*! @brief Read current value of the FTFE_FSEC_MEEN field. */ -#define BR_FTFE_FSEC_MEEN(x) (HW_FTFE_FSEC(x).B.MEEN) -/*@}*/ - -/*! - * @name Register FTFE_FSEC, field KEYEN[7:6] (RO) - * - * These bits enable and disable backdoor key access to the FTFE module. - * - * Values: - * - 00 - Backdoor key access disabled - * - 01 - Backdoor key access disabled (preferred KEYEN state to disable - * backdoor key access) - * - 10 - Backdoor key access enabled - * - 11 - Backdoor key access disabled - */ -/*@{*/ -#define BP_FTFE_FSEC_KEYEN (6U) /*!< Bit position for FTFE_FSEC_KEYEN. */ -#define BM_FTFE_FSEC_KEYEN (0xC0U) /*!< Bit mask for FTFE_FSEC_KEYEN. */ -#define BS_FTFE_FSEC_KEYEN (2U) /*!< Bit field size in bits for FTFE_FSEC_KEYEN. */ - -/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */ -#define BR_FTFE_FSEC_KEYEN(x) (HW_FTFE_FSEC(x).B.KEYEN) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FOPT - Flash Option Register - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FOPT - Flash Option Register (RO) - * - * Reset value: 0x00U - * - * The flash option register allows the MCU to customize its operations by - * examining the state of these read-only bits, which are loaded from NVM at reset. - * The function of the bits is defined in the device's Chip Configuration details. - * All bits in the register are read-only. During the reset sequence, the - * register is loaded from the flash nonvolatile option byte in the Flash Configuration - * Field located in program flash memory. The flash basis for the values is - * signified by X in the reset value. - */ -typedef union _hw_ftfe_fopt -{ - uint8_t U; - struct _hw_ftfe_fopt_bitfields - { - uint8_t OPT : 8; /*!< [7:0] Nonvolatile Option */ - } B; -} hw_ftfe_fopt_t; - -/*! - * @name Constants and macros for entire FTFE_FOPT register - */ -/*@{*/ -#define HW_FTFE_FOPT_ADDR(x) ((x) + 0x3U) - -#define HW_FTFE_FOPT(x) (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR(x)) -#define HW_FTFE_FOPT_RD(x) (HW_FTFE_FOPT(x).U) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FOPT bitfields - */ - -/*! - * @name Register FTFE_FOPT, field OPT[7:0] (RO) - * - * These bits are loaded from flash to this register at reset. Refer to the - * device's Chip Configuration details for the definition and use of these bits. - */ -/*@{*/ -#define BP_FTFE_FOPT_OPT (0U) /*!< Bit position for FTFE_FOPT_OPT. */ -#define BM_FTFE_FOPT_OPT (0xFFU) /*!< Bit mask for FTFE_FOPT_OPT. */ -#define BS_FTFE_FOPT_OPT (8U) /*!< Bit field size in bits for FTFE_FOPT_OPT. */ - -/*! @brief Read current value of the FTFE_FOPT_OPT field. */ -#define BR_FTFE_FOPT_OPT(x) (HW_FTFE_FOPT(x).U) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB3 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob3 -{ - uint8_t U; - struct _hw_ftfe_fccob3_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob3_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB3 register - */ -/*@{*/ -#define HW_FTFE_FCCOB3_ADDR(x) ((x) + 0x4U) - -#define HW_FTFE_FCCOB3(x) (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR(x)) -#define HW_FTFE_FCCOB3_RD(x) (HW_FTFE_FCCOB3(x).U) -#define HW_FTFE_FCCOB3_WR(x, v) (HW_FTFE_FCCOB3(x).U = (v)) -#define HW_FTFE_FCCOB3_SET(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) | (v))) -#define HW_FTFE_FCCOB3_CLR(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) & ~(v))) -#define HW_FTFE_FCCOB3_TOG(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB3 bitfields - */ - -/*! - * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB3_CCOBn (0U) /*!< Bit position for FTFE_FCCOB3_CCOBn. */ -#define BM_FTFE_FCCOB3_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB3_CCOBn. */ -#define BS_FTFE_FCCOB3_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB3_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB3_CCOBn field. */ -#define BR_FTFE_FCCOB3_CCOBn(x) (HW_FTFE_FCCOB3(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB3_CCOBn. */ -#define BF_FTFE_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB3_CCOBn) & BM_FTFE_FCCOB3_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB3_CCOBn(x, v) (HW_FTFE_FCCOB3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB2 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob2 -{ - uint8_t U; - struct _hw_ftfe_fccob2_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob2_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB2 register - */ -/*@{*/ -#define HW_FTFE_FCCOB2_ADDR(x) ((x) + 0x5U) - -#define HW_FTFE_FCCOB2(x) (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR(x)) -#define HW_FTFE_FCCOB2_RD(x) (HW_FTFE_FCCOB2(x).U) -#define HW_FTFE_FCCOB2_WR(x, v) (HW_FTFE_FCCOB2(x).U = (v)) -#define HW_FTFE_FCCOB2_SET(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) | (v))) -#define HW_FTFE_FCCOB2_CLR(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) & ~(v))) -#define HW_FTFE_FCCOB2_TOG(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB2 bitfields - */ - -/*! - * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB2_CCOBn (0U) /*!< Bit position for FTFE_FCCOB2_CCOBn. */ -#define BM_FTFE_FCCOB2_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB2_CCOBn. */ -#define BS_FTFE_FCCOB2_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB2_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB2_CCOBn field. */ -#define BR_FTFE_FCCOB2_CCOBn(x) (HW_FTFE_FCCOB2(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB2_CCOBn. */ -#define BF_FTFE_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB2_CCOBn) & BM_FTFE_FCCOB2_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB2_CCOBn(x, v) (HW_FTFE_FCCOB2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB1 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob1 -{ - uint8_t U; - struct _hw_ftfe_fccob1_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob1_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB1 register - */ -/*@{*/ -#define HW_FTFE_FCCOB1_ADDR(x) ((x) + 0x6U) - -#define HW_FTFE_FCCOB1(x) (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR(x)) -#define HW_FTFE_FCCOB1_RD(x) (HW_FTFE_FCCOB1(x).U) -#define HW_FTFE_FCCOB1_WR(x, v) (HW_FTFE_FCCOB1(x).U = (v)) -#define HW_FTFE_FCCOB1_SET(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) | (v))) -#define HW_FTFE_FCCOB1_CLR(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) & ~(v))) -#define HW_FTFE_FCCOB1_TOG(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB1 bitfields - */ - -/*! - * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB1_CCOBn (0U) /*!< Bit position for FTFE_FCCOB1_CCOBn. */ -#define BM_FTFE_FCCOB1_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB1_CCOBn. */ -#define BS_FTFE_FCCOB1_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB1_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB1_CCOBn field. */ -#define BR_FTFE_FCCOB1_CCOBn(x) (HW_FTFE_FCCOB1(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB1_CCOBn. */ -#define BF_FTFE_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB1_CCOBn) & BM_FTFE_FCCOB1_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB1_CCOBn(x, v) (HW_FTFE_FCCOB1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB0 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob0 -{ - uint8_t U; - struct _hw_ftfe_fccob0_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob0_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB0 register - */ -/*@{*/ -#define HW_FTFE_FCCOB0_ADDR(x) ((x) + 0x7U) - -#define HW_FTFE_FCCOB0(x) (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR(x)) -#define HW_FTFE_FCCOB0_RD(x) (HW_FTFE_FCCOB0(x).U) -#define HW_FTFE_FCCOB0_WR(x, v) (HW_FTFE_FCCOB0(x).U = (v)) -#define HW_FTFE_FCCOB0_SET(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) | (v))) -#define HW_FTFE_FCCOB0_CLR(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) & ~(v))) -#define HW_FTFE_FCCOB0_TOG(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB0 bitfields - */ - -/*! - * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB0_CCOBn (0U) /*!< Bit position for FTFE_FCCOB0_CCOBn. */ -#define BM_FTFE_FCCOB0_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB0_CCOBn. */ -#define BS_FTFE_FCCOB0_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB0_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB0_CCOBn field. */ -#define BR_FTFE_FCCOB0_CCOBn(x) (HW_FTFE_FCCOB0(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB0_CCOBn. */ -#define BF_FTFE_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB0_CCOBn) & BM_FTFE_FCCOB0_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB0_CCOBn(x, v) (HW_FTFE_FCCOB0_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB7 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob7 -{ - uint8_t U; - struct _hw_ftfe_fccob7_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob7_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB7 register - */ -/*@{*/ -#define HW_FTFE_FCCOB7_ADDR(x) ((x) + 0x8U) - -#define HW_FTFE_FCCOB7(x) (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR(x)) -#define HW_FTFE_FCCOB7_RD(x) (HW_FTFE_FCCOB7(x).U) -#define HW_FTFE_FCCOB7_WR(x, v) (HW_FTFE_FCCOB7(x).U = (v)) -#define HW_FTFE_FCCOB7_SET(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) | (v))) -#define HW_FTFE_FCCOB7_CLR(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) & ~(v))) -#define HW_FTFE_FCCOB7_TOG(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB7 bitfields - */ - -/*! - * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB7_CCOBn (0U) /*!< Bit position for FTFE_FCCOB7_CCOBn. */ -#define BM_FTFE_FCCOB7_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB7_CCOBn. */ -#define BS_FTFE_FCCOB7_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB7_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB7_CCOBn field. */ -#define BR_FTFE_FCCOB7_CCOBn(x) (HW_FTFE_FCCOB7(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB7_CCOBn. */ -#define BF_FTFE_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB7_CCOBn) & BM_FTFE_FCCOB7_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB7_CCOBn(x, v) (HW_FTFE_FCCOB7_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB6 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob6 -{ - uint8_t U; - struct _hw_ftfe_fccob6_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob6_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB6 register - */ -/*@{*/ -#define HW_FTFE_FCCOB6_ADDR(x) ((x) + 0x9U) - -#define HW_FTFE_FCCOB6(x) (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR(x)) -#define HW_FTFE_FCCOB6_RD(x) (HW_FTFE_FCCOB6(x).U) -#define HW_FTFE_FCCOB6_WR(x, v) (HW_FTFE_FCCOB6(x).U = (v)) -#define HW_FTFE_FCCOB6_SET(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) | (v))) -#define HW_FTFE_FCCOB6_CLR(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) & ~(v))) -#define HW_FTFE_FCCOB6_TOG(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB6 bitfields - */ - -/*! - * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB6_CCOBn (0U) /*!< Bit position for FTFE_FCCOB6_CCOBn. */ -#define BM_FTFE_FCCOB6_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB6_CCOBn. */ -#define BS_FTFE_FCCOB6_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB6_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB6_CCOBn field. */ -#define BR_FTFE_FCCOB6_CCOBn(x) (HW_FTFE_FCCOB6(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB6_CCOBn. */ -#define BF_FTFE_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB6_CCOBn) & BM_FTFE_FCCOB6_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB6_CCOBn(x, v) (HW_FTFE_FCCOB6_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB5 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob5 -{ - uint8_t U; - struct _hw_ftfe_fccob5_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob5_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB5 register - */ -/*@{*/ -#define HW_FTFE_FCCOB5_ADDR(x) ((x) + 0xAU) - -#define HW_FTFE_FCCOB5(x) (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR(x)) -#define HW_FTFE_FCCOB5_RD(x) (HW_FTFE_FCCOB5(x).U) -#define HW_FTFE_FCCOB5_WR(x, v) (HW_FTFE_FCCOB5(x).U = (v)) -#define HW_FTFE_FCCOB5_SET(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) | (v))) -#define HW_FTFE_FCCOB5_CLR(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) & ~(v))) -#define HW_FTFE_FCCOB5_TOG(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB5 bitfields - */ - -/*! - * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB5_CCOBn (0U) /*!< Bit position for FTFE_FCCOB5_CCOBn. */ -#define BM_FTFE_FCCOB5_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB5_CCOBn. */ -#define BS_FTFE_FCCOB5_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB5_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB5_CCOBn field. */ -#define BR_FTFE_FCCOB5_CCOBn(x) (HW_FTFE_FCCOB5(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB5_CCOBn. */ -#define BF_FTFE_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB5_CCOBn) & BM_FTFE_FCCOB5_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB5_CCOBn(x, v) (HW_FTFE_FCCOB5_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB4 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob4 -{ - uint8_t U; - struct _hw_ftfe_fccob4_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob4_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB4 register - */ -/*@{*/ -#define HW_FTFE_FCCOB4_ADDR(x) ((x) + 0xBU) - -#define HW_FTFE_FCCOB4(x) (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR(x)) -#define HW_FTFE_FCCOB4_RD(x) (HW_FTFE_FCCOB4(x).U) -#define HW_FTFE_FCCOB4_WR(x, v) (HW_FTFE_FCCOB4(x).U = (v)) -#define HW_FTFE_FCCOB4_SET(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) | (v))) -#define HW_FTFE_FCCOB4_CLR(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) & ~(v))) -#define HW_FTFE_FCCOB4_TOG(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB4 bitfields - */ - -/*! - * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB4_CCOBn (0U) /*!< Bit position for FTFE_FCCOB4_CCOBn. */ -#define BM_FTFE_FCCOB4_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB4_CCOBn. */ -#define BS_FTFE_FCCOB4_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB4_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB4_CCOBn field. */ -#define BR_FTFE_FCCOB4_CCOBn(x) (HW_FTFE_FCCOB4(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB4_CCOBn. */ -#define BF_FTFE_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB4_CCOBn) & BM_FTFE_FCCOB4_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB4_CCOBn(x, v) (HW_FTFE_FCCOB4_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOBB - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccobb -{ - uint8_t U; - struct _hw_ftfe_fccobb_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccobb_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOBB register - */ -/*@{*/ -#define HW_FTFE_FCCOBB_ADDR(x) ((x) + 0xCU) - -#define HW_FTFE_FCCOBB(x) (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR(x)) -#define HW_FTFE_FCCOBB_RD(x) (HW_FTFE_FCCOBB(x).U) -#define HW_FTFE_FCCOBB_WR(x, v) (HW_FTFE_FCCOBB(x).U = (v)) -#define HW_FTFE_FCCOBB_SET(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) | (v))) -#define HW_FTFE_FCCOBB_CLR(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) & ~(v))) -#define HW_FTFE_FCCOBB_TOG(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOBB bitfields - */ - -/*! - * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOBB_CCOBn (0U) /*!< Bit position for FTFE_FCCOBB_CCOBn. */ -#define BM_FTFE_FCCOBB_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOBB_CCOBn. */ -#define BS_FTFE_FCCOBB_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOBB_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOBB_CCOBn field. */ -#define BR_FTFE_FCCOBB_CCOBn(x) (HW_FTFE_FCCOBB(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOBB_CCOBn. */ -#define BF_FTFE_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBB_CCOBn) & BM_FTFE_FCCOBB_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOBB_CCOBn(x, v) (HW_FTFE_FCCOBB_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOBA - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccoba -{ - uint8_t U; - struct _hw_ftfe_fccoba_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccoba_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOBA register - */ -/*@{*/ -#define HW_FTFE_FCCOBA_ADDR(x) ((x) + 0xDU) - -#define HW_FTFE_FCCOBA(x) (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR(x)) -#define HW_FTFE_FCCOBA_RD(x) (HW_FTFE_FCCOBA(x).U) -#define HW_FTFE_FCCOBA_WR(x, v) (HW_FTFE_FCCOBA(x).U = (v)) -#define HW_FTFE_FCCOBA_SET(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) | (v))) -#define HW_FTFE_FCCOBA_CLR(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) & ~(v))) -#define HW_FTFE_FCCOBA_TOG(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOBA bitfields - */ - -/*! - * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOBA_CCOBn (0U) /*!< Bit position for FTFE_FCCOBA_CCOBn. */ -#define BM_FTFE_FCCOBA_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOBA_CCOBn. */ -#define BS_FTFE_FCCOBA_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOBA_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOBA_CCOBn field. */ -#define BR_FTFE_FCCOBA_CCOBn(x) (HW_FTFE_FCCOBA(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOBA_CCOBn. */ -#define BF_FTFE_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBA_CCOBn) & BM_FTFE_FCCOBA_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOBA_CCOBn(x, v) (HW_FTFE_FCCOBA_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB9 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob9 -{ - uint8_t U; - struct _hw_ftfe_fccob9_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob9_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB9 register - */ -/*@{*/ -#define HW_FTFE_FCCOB9_ADDR(x) ((x) + 0xEU) - -#define HW_FTFE_FCCOB9(x) (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR(x)) -#define HW_FTFE_FCCOB9_RD(x) (HW_FTFE_FCCOB9(x).U) -#define HW_FTFE_FCCOB9_WR(x, v) (HW_FTFE_FCCOB9(x).U = (v)) -#define HW_FTFE_FCCOB9_SET(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) | (v))) -#define HW_FTFE_FCCOB9_CLR(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) & ~(v))) -#define HW_FTFE_FCCOB9_TOG(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB9 bitfields - */ - -/*! - * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB9_CCOBn (0U) /*!< Bit position for FTFE_FCCOB9_CCOBn. */ -#define BM_FTFE_FCCOB9_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB9_CCOBn. */ -#define BS_FTFE_FCCOB9_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB9_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB9_CCOBn field. */ -#define BR_FTFE_FCCOB9_CCOBn(x) (HW_FTFE_FCCOB9(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB9_CCOBn. */ -#define BF_FTFE_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB9_CCOBn) & BM_FTFE_FCCOB9_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB9_CCOBn(x, v) (HW_FTFE_FCCOB9_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FCCOB8 - Flash Common Command Object Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW) - * - * Reset value: 0x00U - * - * The FCCOB register group provides 12 bytes for command codes and parameters. - * The individual bytes within the set append a 0-B hex identifier to the FCCOB - * register name: FCCOB0, FCCOB1, ..., FCCOBB. - */ -typedef union _hw_ftfe_fccob8 -{ - uint8_t U; - struct _hw_ftfe_fccob8_bitfields - { - uint8_t CCOBn : 8; /*!< [7:0] */ - } B; -} hw_ftfe_fccob8_t; - -/*! - * @name Constants and macros for entire FTFE_FCCOB8 register - */ -/*@{*/ -#define HW_FTFE_FCCOB8_ADDR(x) ((x) + 0xFU) - -#define HW_FTFE_FCCOB8(x) (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR(x)) -#define HW_FTFE_FCCOB8_RD(x) (HW_FTFE_FCCOB8(x).U) -#define HW_FTFE_FCCOB8_WR(x, v) (HW_FTFE_FCCOB8(x).U = (v)) -#define HW_FTFE_FCCOB8_SET(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) | (v))) -#define HW_FTFE_FCCOB8_CLR(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) & ~(v))) -#define HW_FTFE_FCCOB8_TOG(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FCCOB8 bitfields - */ - -/*! - * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW) - * - * The FCCOB register provides a command code and relevant parameters to the - * memory controller. The individual registers that compose the FCCOB data set can - * be written in any order, but you must provide all needed values, which vary - * from command to command. First, set up all required FCCOB fields and then - * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears - * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed - * by the user until the command completes (CCIF returns to 1). No command - * buffering or queueing is provided; the next command can be loaded only after the - * current command completes. Some commands return information to the FCCOB - * registers. Any values returned to FCCOB are available for reading after the - * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a - * generic FTFE command format. The first FCCOB register, FCCOB0, always contains - * the command code. This 8-bit value defines the command to be executed. The - * command code is followed by the parameters required for this specific FTFE command, - * typically an address and/or data values. The command parameter table is - * written in terms of FCCOB Number (which is equivalent to the byte number). This - * number is a reference to the FCCOB register name and is not the register address. - * FCCOB NumberRefers to FCCOB register name, not register address Typical - * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 - * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 - * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data - * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB - * register group uses a big endian addressing convention. For all command parameter - * fields larger than 1 byte, the most significant data resides in the lowest FCCOB - * register number. The FCCOB register group may be read and written as - * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). - */ -/*@{*/ -#define BP_FTFE_FCCOB8_CCOBn (0U) /*!< Bit position for FTFE_FCCOB8_CCOBn. */ -#define BM_FTFE_FCCOB8_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB8_CCOBn. */ -#define BS_FTFE_FCCOB8_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB8_CCOBn. */ - -/*! @brief Read current value of the FTFE_FCCOB8_CCOBn field. */ -#define BR_FTFE_FCCOB8_CCOBn(x) (HW_FTFE_FCCOB8(x).U) - -/*! @brief Format value for bitfield FTFE_FCCOB8_CCOBn. */ -#define BF_FTFE_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB8_CCOBn) & BM_FTFE_FCCOB8_CCOBn) - -/*! @brief Set the CCOBn field to a new value. */ -#define BW_FTFE_FCCOB8_CCOBn(x, v) (HW_FTFE_FCCOB8_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FPROT3 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any FTFE command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions of equal - * memory size. Program flash protection register Program flash protection bits - * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During - * the reset sequence, the FPROT registers are loaded with the contents of the - * program flash protection bytes in the Flash Configuration Field as indicated in - * the following table. Program flash protection register Flash Configuration Field - * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To - * change the program flash protection that is loaded during the reset sequence, - * unprotect the sector of program flash memory that contains the Flash - * Configuration Field. Then, reprogram the program flash protection byte. - */ -typedef union _hw_ftfe_fprot3 -{ - uint8_t U; - struct _hw_ftfe_fprot3_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfe_fprot3_t; - -/*! - * @name Constants and macros for entire FTFE_FPROT3 register - */ -/*@{*/ -#define HW_FTFE_FPROT3_ADDR(x) ((x) + 0x10U) - -#define HW_FTFE_FPROT3(x) (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR(x)) -#define HW_FTFE_FPROT3_RD(x) (HW_FTFE_FPROT3(x).U) -#define HW_FTFE_FPROT3_WR(x, v) (HW_FTFE_FPROT3(x).U = (v)) -#define HW_FTFE_FPROT3_SET(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) | (v))) -#define HW_FTFE_FPROT3_CLR(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) & ~(v))) -#define HW_FTFE_FPROT3_TOG(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FPROT3 bitfields - */ - -/*! - * @name Register FTFE_FPROT3, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFE_FPROT3_PROT (0U) /*!< Bit position for FTFE_FPROT3_PROT. */ -#define BM_FTFE_FPROT3_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT3_PROT. */ -#define BS_FTFE_FPROT3_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT3_PROT. */ - -/*! @brief Read current value of the FTFE_FPROT3_PROT field. */ -#define BR_FTFE_FPROT3_PROT(x) (HW_FTFE_FPROT3(x).U) - -/*! @brief Format value for bitfield FTFE_FPROT3_PROT. */ -#define BF_FTFE_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT3_PROT) & BM_FTFE_FPROT3_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFE_FPROT3_PROT(x, v) (HW_FTFE_FPROT3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FPROT2 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any FTFE command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions of equal - * memory size. Program flash protection register Program flash protection bits - * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During - * the reset sequence, the FPROT registers are loaded with the contents of the - * program flash protection bytes in the Flash Configuration Field as indicated in - * the following table. Program flash protection register Flash Configuration Field - * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To - * change the program flash protection that is loaded during the reset sequence, - * unprotect the sector of program flash memory that contains the Flash - * Configuration Field. Then, reprogram the program flash protection byte. - */ -typedef union _hw_ftfe_fprot2 -{ - uint8_t U; - struct _hw_ftfe_fprot2_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfe_fprot2_t; - -/*! - * @name Constants and macros for entire FTFE_FPROT2 register - */ -/*@{*/ -#define HW_FTFE_FPROT2_ADDR(x) ((x) + 0x11U) - -#define HW_FTFE_FPROT2(x) (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR(x)) -#define HW_FTFE_FPROT2_RD(x) (HW_FTFE_FPROT2(x).U) -#define HW_FTFE_FPROT2_WR(x, v) (HW_FTFE_FPROT2(x).U = (v)) -#define HW_FTFE_FPROT2_SET(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) | (v))) -#define HW_FTFE_FPROT2_CLR(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) & ~(v))) -#define HW_FTFE_FPROT2_TOG(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FPROT2 bitfields - */ - -/*! - * @name Register FTFE_FPROT2, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFE_FPROT2_PROT (0U) /*!< Bit position for FTFE_FPROT2_PROT. */ -#define BM_FTFE_FPROT2_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT2_PROT. */ -#define BS_FTFE_FPROT2_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT2_PROT. */ - -/*! @brief Read current value of the FTFE_FPROT2_PROT field. */ -#define BR_FTFE_FPROT2_PROT(x) (HW_FTFE_FPROT2(x).U) - -/*! @brief Format value for bitfield FTFE_FPROT2_PROT. */ -#define BF_FTFE_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT2_PROT) & BM_FTFE_FPROT2_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFE_FPROT2_PROT(x, v) (HW_FTFE_FPROT2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FPROT1 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any FTFE command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions of equal - * memory size. Program flash protection register Program flash protection bits - * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During - * the reset sequence, the FPROT registers are loaded with the contents of the - * program flash protection bytes in the Flash Configuration Field as indicated in - * the following table. Program flash protection register Flash Configuration Field - * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To - * change the program flash protection that is loaded during the reset sequence, - * unprotect the sector of program flash memory that contains the Flash - * Configuration Field. Then, reprogram the program flash protection byte. - */ -typedef union _hw_ftfe_fprot1 -{ - uint8_t U; - struct _hw_ftfe_fprot1_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfe_fprot1_t; - -/*! - * @name Constants and macros for entire FTFE_FPROT1 register - */ -/*@{*/ -#define HW_FTFE_FPROT1_ADDR(x) ((x) + 0x12U) - -#define HW_FTFE_FPROT1(x) (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR(x)) -#define HW_FTFE_FPROT1_RD(x) (HW_FTFE_FPROT1(x).U) -#define HW_FTFE_FPROT1_WR(x, v) (HW_FTFE_FPROT1(x).U = (v)) -#define HW_FTFE_FPROT1_SET(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) | (v))) -#define HW_FTFE_FPROT1_CLR(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) & ~(v))) -#define HW_FTFE_FPROT1_TOG(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FPROT1 bitfields - */ - -/*! - * @name Register FTFE_FPROT1, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFE_FPROT1_PROT (0U) /*!< Bit position for FTFE_FPROT1_PROT. */ -#define BM_FTFE_FPROT1_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT1_PROT. */ -#define BS_FTFE_FPROT1_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT1_PROT. */ - -/*! @brief Read current value of the FTFE_FPROT1_PROT field. */ -#define BR_FTFE_FPROT1_PROT(x) (HW_FTFE_FPROT1(x).U) - -/*! @brief Format value for bitfield FTFE_FPROT1_PROT. */ -#define BF_FTFE_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT1_PROT) & BM_FTFE_FPROT1_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFE_FPROT1_PROT(x, v) (HW_FTFE_FPROT1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FPROT0 - Program Flash Protection Registers - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW) - * - * Reset value: 0x00U - * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any FTFE command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions of equal - * memory size. Program flash protection register Program flash protection bits - * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During - * the reset sequence, the FPROT registers are loaded with the contents of the - * program flash protection bytes in the Flash Configuration Field as indicated in - * the following table. Program flash protection register Flash Configuration Field - * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To - * change the program flash protection that is loaded during the reset sequence, - * unprotect the sector of program flash memory that contains the Flash - * Configuration Field. Then, reprogram the program flash protection byte. - */ -typedef union _hw_ftfe_fprot0 -{ - uint8_t U; - struct _hw_ftfe_fprot0_bitfields - { - uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */ - } B; -} hw_ftfe_fprot0_t; - -/*! - * @name Constants and macros for entire FTFE_FPROT0 register - */ -/*@{*/ -#define HW_FTFE_FPROT0_ADDR(x) ((x) + 0x13U) - -#define HW_FTFE_FPROT0(x) (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR(x)) -#define HW_FTFE_FPROT0_RD(x) (HW_FTFE_FPROT0(x).U) -#define HW_FTFE_FPROT0_WR(x, v) (HW_FTFE_FPROT0(x).U = (v)) -#define HW_FTFE_FPROT0_SET(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) | (v))) -#define HW_FTFE_FPROT0_CLR(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) & ~(v))) -#define HW_FTFE_FPROT0_TOG(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FPROT0 bitfields - */ - -/*! - * @name Register FTFE_FPROT0, field PROT[7:0] (RW) - * - * Each program flash region can be protected from program and erase operations - * by setting the associated PROT bit. In NVM Normal mode: The protection can - * only be increased, meaning that currently unprotected memory can be protected, - * but currently protected memory cannot be unprotected. Since unprotected regions - * are marked with a 1 and protected regions use a 0, only writes changing 1s to - * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit - * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with - * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are - * writable without restriction. Unprotected areas can be protected and protected - * areas can be unprotected. The user must never write to any FPROT register while - * a command is running (CCIF=0). Trying to alter data in any protected area in - * the program flash memory results in a protection violation error and sets the - * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible - * if it contains any protected region. - * - * Values: - * - 0 - Program flash region is protected. - * - 1 - Program flash region is not protected - */ -/*@{*/ -#define BP_FTFE_FPROT0_PROT (0U) /*!< Bit position for FTFE_FPROT0_PROT. */ -#define BM_FTFE_FPROT0_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT0_PROT. */ -#define BS_FTFE_FPROT0_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT0_PROT. */ - -/*! @brief Read current value of the FTFE_FPROT0_PROT field. */ -#define BR_FTFE_FPROT0_PROT(x) (HW_FTFE_FPROT0(x).U) - -/*! @brief Format value for bitfield FTFE_FPROT0_PROT. */ -#define BF_FTFE_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT0_PROT) & BM_FTFE_FPROT0_PROT) - -/*! @brief Set the PROT field to a new value. */ -#define BW_FTFE_FPROT0_PROT(x, v) (HW_FTFE_FPROT0_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FEPROT - EEPROM Protection Register - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW) - * - * Reset value: 0x00U - * - * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of - * the FlexRAM are protected against program and erase operations. Protected - * EEPROM regions cannot have their content changed by writing to it. Unprotected - * regions can be changed by writing to the FlexRAM. For devices with program flash - * only: This register is reserved and not used. - */ -typedef union _hw_ftfe_feprot -{ - uint8_t U; - struct _hw_ftfe_feprot_bitfields - { - uint8_t EPROT : 8; /*!< [7:0] EEPROM Region Protect */ - } B; -} hw_ftfe_feprot_t; - -/*! - * @name Constants and macros for entire FTFE_FEPROT register - */ -/*@{*/ -#define HW_FTFE_FEPROT_ADDR(x) ((x) + 0x16U) - -#define HW_FTFE_FEPROT(x) (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR(x)) -#define HW_FTFE_FEPROT_RD(x) (HW_FTFE_FEPROT(x).U) -#define HW_FTFE_FEPROT_WR(x, v) (HW_FTFE_FEPROT(x).U = (v)) -#define HW_FTFE_FEPROT_SET(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) | (v))) -#define HW_FTFE_FEPROT_CLR(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) & ~(v))) -#define HW_FTFE_FEPROT_TOG(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FEPROT bitfields - */ - -/*! - * @name Register FTFE_FEPROT, field EPROT[7:0] (RW) - * - * For devices with program flash only: Reserved For devices with FlexNVM: - * Individual EEPROM regions can be protected from alteration by setting the - * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is - * set to data flash only. When the FlexNVM Partition Code is set to data flash and - * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured - * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal - * mode: The protection can only be increased. This means that - * currently-unprotected memory can be protected, but currently-protected memory cannot be - * unprotected. Since unprotected regions are marked with a 1 and protected regions use a - * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is - * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions - * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special - * mode: All bits of the FEPROT register are writable without restriction. - * Unprotected areas can be protected and protected areas can be unprotected. Never - * write to the FEPROT register while a command is running (CCIF=0). Reset: During - * the reset sequence, the FEPROT register is loaded with the contents of the - * FlexRAM protection byte in the Flash Configuration Field located in program flash. - * The flash basis for the reset values is signified by X in the register - * diagram. To change the EEPROM protection that will be loaded during the reset - * sequence, the sector of program flash that contains the Flash Configuration Field - * must be unprotected; then the EEPROM protection byte must be erased and - * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM - * results in a protection violation error and sets the FSTAT[FPVIOL] bit. - * - * Values: - * - 0 - For devices with program flash only: Reserved For devices with FlexNVM: - * EEPROM region is protected - * - 1 - For devices with program flash only: Reserved For devices with FlexNVM: - * EEPROM region is not protected - */ -/*@{*/ -#define BP_FTFE_FEPROT_EPROT (0U) /*!< Bit position for FTFE_FEPROT_EPROT. */ -#define BM_FTFE_FEPROT_EPROT (0xFFU) /*!< Bit mask for FTFE_FEPROT_EPROT. */ -#define BS_FTFE_FEPROT_EPROT (8U) /*!< Bit field size in bits for FTFE_FEPROT_EPROT. */ - -/*! @brief Read current value of the FTFE_FEPROT_EPROT field. */ -#define BR_FTFE_FEPROT_EPROT(x) (HW_FTFE_FEPROT(x).U) - -/*! @brief Format value for bitfield FTFE_FEPROT_EPROT. */ -#define BF_FTFE_FEPROT_EPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FEPROT_EPROT) & BM_FTFE_FEPROT_EPROT) - -/*! @brief Set the EPROT field to a new value. */ -#define BW_FTFE_FEPROT_EPROT(x, v) (HW_FTFE_FEPROT_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_FTFE_FDPROT - Data Flash Protection Register - ******************************************************************************/ - -/*! - * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW) - * - * Reset value: 0x00U - * - * The FDPROT register defines which data flash regions are protected against - * program and erase operations. Protected Flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any FTFE command. Unprotected regions can be changed by both program and erase - * operations. - */ -typedef union _hw_ftfe_fdprot -{ - uint8_t U; - struct _hw_ftfe_fdprot_bitfields - { - uint8_t DPROT : 8; /*!< [7:0] Data Flash Region Protect */ - } B; -} hw_ftfe_fdprot_t; - -/*! - * @name Constants and macros for entire FTFE_FDPROT register - */ -/*@{*/ -#define HW_FTFE_FDPROT_ADDR(x) ((x) + 0x17U) - -#define HW_FTFE_FDPROT(x) (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR(x)) -#define HW_FTFE_FDPROT_RD(x) (HW_FTFE_FDPROT(x).U) -#define HW_FTFE_FDPROT_WR(x, v) (HW_FTFE_FDPROT(x).U = (v)) -#define HW_FTFE_FDPROT_SET(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) | (v))) -#define HW_FTFE_FDPROT_CLR(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) & ~(v))) -#define HW_FTFE_FDPROT_TOG(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTFE_FDPROT bitfields - */ - -/*! - * @name Register FTFE_FDPROT, field DPROT[7:0] (RW) - * - * Individual data flash regions can be protected from program and erase - * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of - * the partitioned data flash memory space. The granularity of data flash - * protection cannot be less than the data flash sector size. If an unused DPROT bit is - * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL] - * bit. In NVM Normal mode: The protection can only be increased, meaning that - * currently unprotected memory can be protected but currently protected memory - * cannot be unprotected. Since unprotected regions are marked with a 1 and - * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 - * transition check is performed on a bit-by-bit basis. Those FDPROT bits with - * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are - * ignored. In NVM Special mode: All bits of the FDPROT register are writable without - * restriction. Unprotected areas can be protected and protected areas can be - * unprotected. The user must never write to the FDPROT register while a command is - * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is - * loaded with the contents of the data flash protection byte in the Flash - * Configuration Field located in program flash memory. The flash basis for the reset values - * is signified by X in the register diagram. To change the data flash - * protection that will be loaded during the reset sequence, unprotect the sector of - * program flash that contains the Flash Configuration Field. Then, erase and - * reprogram the data flash protection byte. Trying to alter data with the program and - * erase commands in any protected area in the data flash memory results in a - * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any - * data flash memory block (see the Erase Flash Block command description) is not - * possible if the data flash block contains any protected region or if the FlexNVM - * memory has been partitioned for EEPROM. - * - * Values: - * - 0 - Data Flash region is protected - * - 1 - Data Flash region is not protected - */ -/*@{*/ -#define BP_FTFE_FDPROT_DPROT (0U) /*!< Bit position for FTFE_FDPROT_DPROT. */ -#define BM_FTFE_FDPROT_DPROT (0xFFU) /*!< Bit mask for FTFE_FDPROT_DPROT. */ -#define BS_FTFE_FDPROT_DPROT (8U) /*!< Bit field size in bits for FTFE_FDPROT_DPROT. */ - -/*! @brief Read current value of the FTFE_FDPROT_DPROT field. */ -#define BR_FTFE_FDPROT_DPROT(x) (HW_FTFE_FDPROT(x).U) - -/*! @brief Format value for bitfield FTFE_FDPROT_DPROT. */ -#define BF_FTFE_FDPROT_DPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FDPROT_DPROT) & BM_FTFE_FDPROT_DPROT) - -/*! @brief Set the DPROT field to a new value. */ -#define BW_FTFE_FDPROT_DPROT(x, v) (HW_FTFE_FDPROT_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_ftfe_t - module struct - ******************************************************************************/ -/*! - * @brief All FTFE module registers. - */ -#pragma pack(1) -typedef struct _hw_ftfe -{ - __IO hw_ftfe_fstat_t FSTAT; /*!< [0x0] Flash Status Register */ - __IO hw_ftfe_fcnfg_t FCNFG; /*!< [0x1] Flash Configuration Register */ - __I hw_ftfe_fsec_t FSEC; /*!< [0x2] Flash Security Register */ - __I hw_ftfe_fopt_t FOPT; /*!< [0x3] Flash Option Register */ - __IO hw_ftfe_fccob3_t FCCOB3; /*!< [0x4] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob2_t FCCOB2; /*!< [0x5] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob1_t FCCOB1; /*!< [0x6] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob0_t FCCOB0; /*!< [0x7] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob7_t FCCOB7; /*!< [0x8] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob6_t FCCOB6; /*!< [0x9] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob5_t FCCOB5; /*!< [0xA] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob4_t FCCOB4; /*!< [0xB] Flash Common Command Object Registers */ - __IO hw_ftfe_fccobb_t FCCOBB; /*!< [0xC] Flash Common Command Object Registers */ - __IO hw_ftfe_fccoba_t FCCOBA; /*!< [0xD] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob9_t FCCOB9; /*!< [0xE] Flash Common Command Object Registers */ - __IO hw_ftfe_fccob8_t FCCOB8; /*!< [0xF] Flash Common Command Object Registers */ - __IO hw_ftfe_fprot3_t FPROT3; /*!< [0x10] Program Flash Protection Registers */ - __IO hw_ftfe_fprot2_t FPROT2; /*!< [0x11] Program Flash Protection Registers */ - __IO hw_ftfe_fprot1_t FPROT1; /*!< [0x12] Program Flash Protection Registers */ - __IO hw_ftfe_fprot0_t FPROT0; /*!< [0x13] Program Flash Protection Registers */ - uint8_t _reserved0[2]; - __IO hw_ftfe_feprot_t FEPROT; /*!< [0x16] EEPROM Protection Register */ - __IO hw_ftfe_fdprot_t FDPROT; /*!< [0x17] Data Flash Protection Register */ -} hw_ftfe_t; -#pragma pack() - -/*! @brief Macro to access all FTFE registers. */ -/*! @param x FTFE module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FTFE(FTFE_BASE). */ -#define HW_FTFE(x) (*(hw_ftfe_t *)(x)) - -#endif /* __HW_FTFE_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftm.h deleted file mode 100644 index 8ac6fa45acf..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftm.h +++ /dev/null @@ -1,5910 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_FTM_REGISTERS_H__ -#define __HW_FTM_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 FTM - * - * FlexTimer Module - * - * Registers defined in this header file: - * - HW_FTM_SC - Status And Control - * - HW_FTM_CNT - Counter - * - HW_FTM_MOD - Modulo - * - HW_FTM_CnSC - Channel (n) Status And Control - * - HW_FTM_CnV - Channel (n) Value - * - HW_FTM_CNTIN - Counter Initial Value - * - HW_FTM_STATUS - Capture And Compare Status - * - HW_FTM_MODE - Features Mode Selection - * - HW_FTM_SYNC - Synchronization - * - HW_FTM_OUTINIT - Initial State For Channels Output - * - HW_FTM_OUTMASK - Output Mask - * - HW_FTM_COMBINE - Function For Linked Channels - * - HW_FTM_DEADTIME - Deadtime Insertion Control - * - HW_FTM_EXTTRIG - FTM External Trigger - * - HW_FTM_POL - Channels Polarity - * - HW_FTM_FMS - Fault Mode Status - * - HW_FTM_FILTER - Input Capture Filter Control - * - HW_FTM_FLTCTRL - Fault Control - * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status - * - HW_FTM_CONF - Configuration - * - HW_FTM_FLTPOL - FTM Fault Input Polarity - * - HW_FTM_SYNCONF - Synchronization Configuration - * - HW_FTM_INVCTRL - FTM Inverting Control - * - HW_FTM_SWOCTRL - FTM Software Output Control - * - HW_FTM_PWMLOAD - FTM PWM Load - * - * - hw_ftm_t - Struct containing all module registers. - */ - -#define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */ -#define HW_FTM0 (0U) /*!< Instance number for FTM0. */ -#define HW_FTM1 (1U) /*!< Instance number for FTM1. */ -#define HW_FTM2 (2U) /*!< Instance number for FTM2. */ -#define HW_FTM3 (3U) /*!< Instance number for FTM3. */ - -/******************************************************************************* - * HW_FTM_SC - Status And Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_SC - Status And Control (RW) - * - * Reset value: 0x00000000U - * - * SC contains the overflow status flag and control bits used to configure the - * interrupt enable, FTM configuration, clock source, and prescaler factor. These - * controls relate to all channels within this module. - */ -typedef union _hw_ftm_sc -{ - uint32_t U; - struct _hw_ftm_sc_bitfields - { - uint32_t PS : 3; /*!< [2:0] Prescale Factor Selection */ - uint32_t CLKS : 2; /*!< [4:3] Clock Source Selection */ - uint32_t CPWMS : 1; /*!< [5] Center-Aligned PWM Select */ - uint32_t TOIE : 1; /*!< [6] Timer Overflow Interrupt Enable */ - uint32_t TOF : 1; /*!< [7] Timer Overflow Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_sc_t; - -/*! - * @name Constants and macros for entire FTM_SC register - */ -/*@{*/ -#define HW_FTM_SC_ADDR(x) ((x) + 0x0U) - -#define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x)) -#define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U) -#define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v)) -#define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v))) -#define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v))) -#define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SC bitfields - */ - -/*! - * @name Register FTM_SC, field PS[2:0] (RW) - * - * Selects one of 8 division factors for the clock source selected by CLKS. The - * new prescaler factor affects the clock source on the next system clock cycle - * after the new value is updated into the register bits. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 000 - Divide by 1 - * - 001 - Divide by 2 - * - 010 - Divide by 4 - * - 011 - Divide by 8 - * - 100 - Divide by 16 - * - 101 - Divide by 32 - * - 110 - Divide by 64 - * - 111 - Divide by 128 - */ -/*@{*/ -#define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */ -#define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */ -#define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */ - -/*! @brief Read current value of the FTM_SC_PS field. */ -#define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS) - -/*! @brief Format value for bitfield FTM_SC_PS. */ -#define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS) - -/*! @brief Set the PS field to a new value. */ -#define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v))) -/*@}*/ - -/*! - * @name Register FTM_SC, field CLKS[4:3] (RW) - * - * Selects one of the three FTM counter clock sources. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 00 - No clock selected. This in effect disables the FTM counter. - * - 01 - System clock - * - 10 - Fixed frequency clock - * - 11 - External clock - */ -/*@{*/ -#define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */ -#define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */ -#define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */ - -/*! @brief Read current value of the FTM_SC_CLKS field. */ -#define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS) - -/*! @brief Format value for bitfield FTM_SC_CLKS. */ -#define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS) - -/*! @brief Set the CLKS field to a new value. */ -#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v))) -/*@}*/ - -/*! - * @name Register FTM_SC, field CPWMS[5] (RW) - * - * Selects CPWM mode. This mode configures the FTM to operate in Up-Down - * Counting mode. This field is write protected. It can be written only when MODE[WPDIS] - * = 1. - * - * Values: - * - 0 - FTM counter operates in Up Counting mode. - * - 1 - FTM counter operates in Up-Down Counting mode. - */ -/*@{*/ -#define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */ -#define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */ -#define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */ - -/*! @brief Read current value of the FTM_SC_CPWMS field. */ -#define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS)) - -/*! @brief Format value for bitfield FTM_SC_CPWMS. */ -#define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS) - -/*! @brief Set the CPWMS field to a new value. */ -#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SC, field TOIE[6] (RW) - * - * Enables FTM overflow interrupts. - * - * Values: - * - 0 - Disable TOF interrupts. Use software polling. - * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one. - */ -/*@{*/ -#define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */ -#define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */ -#define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */ - -/*! @brief Read current value of the FTM_SC_TOIE field. */ -#define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE)) - -/*! @brief Format value for bitfield FTM_SC_TOIE. */ -#define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE) - -/*! @brief Set the TOIE field to a new value. */ -#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SC, field TOF[7] (ROWZ) - * - * Set by hardware when the FTM counter passes the value in the MOD register. - * The TOF bit is cleared by reading the SC register while TOF is set and then - * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow - * occurs between the read and write operations, the write operation has no - * effect; therefore, TOF remains set indicating an overflow has occurred. In this - * case, a TOF interrupt request is not lost due to the clearing sequence for a - * previous TOF. - * - * Values: - * - 0 - FTM counter has not overflowed. - * - 1 - FTM counter has overflowed. - */ -/*@{*/ -#define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */ -#define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */ -#define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */ - -/*! @brief Read current value of the FTM_SC_TOF field. */ -#define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF)) - -/*! @brief Format value for bitfield FTM_SC_TOF. */ -#define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF) - -/*! @brief Set the TOF field to a new value. */ -#define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CNT - Counter - ******************************************************************************/ - -/*! - * @brief HW_FTM_CNT - Counter (RW) - * - * Reset value: 0x00000000U - * - * The CNT register contains the FTM counter value. Reset clears the CNT - * register. Writing any value to COUNT updates the counter with its initial value, - * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you - * may read. - */ -typedef union _hw_ftm_cnt -{ - uint32_t U; - struct _hw_ftm_cnt_bitfields - { - uint32_t COUNT : 16; /*!< [15:0] Counter Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_cnt_t; - -/*! - * @name Constants and macros for entire FTM_CNT register - */ -/*@{*/ -#define HW_FTM_CNT_ADDR(x) ((x) + 0x4U) - -#define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x)) -#define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U) -#define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v)) -#define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v))) -#define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v))) -#define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CNT bitfields - */ - -/*! - * @name Register FTM_CNT, field COUNT[15:0] (RW) - */ -/*@{*/ -#define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */ -#define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */ -#define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */ - -/*! @brief Read current value of the FTM_CNT_COUNT field. */ -#define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT) - -/*! @brief Format value for bitfield FTM_CNT_COUNT. */ -#define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT) - -/*! @brief Set the COUNT field to a new value. */ -#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_MOD - Modulo - ******************************************************************************/ - -/*! - * @brief HW_FTM_MOD - Modulo (RW) - * - * Reset value: 0x00000000U - * - * The Modulo register contains the modulo value for the FTM counter. After the - * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at - * the next clock, and the next value of FTM counter depends on the selected - * counting method; see Counter. Writing to the MOD register latches the value into a - * buffer. The MOD register is updated with the value of its write buffer - * according to Registers updated from write buffers. If FTMEN = 0, this write coherency - * mechanism may be manually reset by writing to the SC register whether BDM is - * active or not. Initialize the FTM counter, by writing to CNT, before writing - * to the MOD register to avoid confusion about when the first counter overflow - * will occur. - */ -typedef union _hw_ftm_mod -{ - uint32_t U; - struct _hw_ftm_mod_bitfields - { - uint32_t MOD : 16; /*!< [15:0] */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_mod_t; - -/*! - * @name Constants and macros for entire FTM_MOD register - */ -/*@{*/ -#define HW_FTM_MOD_ADDR(x) ((x) + 0x8U) - -#define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x)) -#define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U) -#define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v)) -#define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v))) -#define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v))) -#define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_MOD bitfields - */ - -/*! - * @name Register FTM_MOD, field MOD[15:0] (RW) - * - * Modulo Value - */ -/*@{*/ -#define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */ -#define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */ -#define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */ - -/*! @brief Read current value of the FTM_MOD_MOD field. */ -#define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD) - -/*! @brief Format value for bitfield FTM_MOD_MOD. */ -#define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD) - -/*! @brief Set the MOD field to a new value. */ -#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CnSC - Channel (n) Status And Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW) - * - * Reset value: 0x00000000U - * - * CnSC contains the channel-interrupt-status flag and control bits used to - * configure the interrupt enable, channel configuration, and pin function. Mode, - * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode - * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general - * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising - * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge - * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set - * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match) - * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true - * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1 - * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on - * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set - * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual - * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge - * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected - * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1 - * Enabled Rising and falling edges - */ -typedef union _hw_ftm_cnsc -{ - uint32_t U; - struct _hw_ftm_cnsc_bitfields - { - uint32_t DMA : 1; /*!< [0] DMA Enable */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t ELSA : 1; /*!< [2] Edge or Level Select */ - uint32_t ELSB : 1; /*!< [3] Edge or Level Select */ - uint32_t MSA : 1; /*!< [4] Channel Mode Select */ - uint32_t MSB : 1; /*!< [5] Channel Mode Select */ - uint32_t CHIE : 1; /*!< [6] Channel Interrupt Enable */ - uint32_t CHF : 1; /*!< [7] Channel Flag */ - uint32_t RESERVED1 : 24; /*!< [31:8] */ - } B; -} hw_ftm_cnsc_t; - -/*! - * @name Constants and macros for entire FTM_CnSC register - */ -/*@{*/ -#define HW_FTM_CnSC_COUNT (8U) - -#define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n))) - -#define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n)) -#define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U) -#define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v)) -#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v))) -#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v))) -#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CnSC bitfields - */ - -/*! - * @name Register FTM_CnSC, field DMA[0] (RW) - * - * Enables DMA transfers for the channel. - * - * Values: - * - 0 - Disable DMA transfers. - * - 1 - Enable DMA transfers. - */ -/*@{*/ -#define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */ -#define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */ -#define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */ - -/*! @brief Read current value of the FTM_CnSC_DMA field. */ -#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA)) - -/*! @brief Format value for bitfield FTM_CnSC_DMA. */ -#define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA) - -/*! @brief Set the DMA field to a new value. */ -#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field ELSA[2] (RW) - * - * The functionality of ELSB and ELSA depends on the channel mode. See - * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS] - * = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */ -#define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */ -#define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */ - -/*! @brief Read current value of the FTM_CnSC_ELSA field. */ -#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA)) - -/*! @brief Format value for bitfield FTM_CnSC_ELSA. */ -#define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA) - -/*! @brief Set the ELSA field to a new value. */ -#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field ELSB[3] (RW) - * - * The functionality of ELSB and ELSA depends on the channel mode. See - * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS] - * = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */ -#define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */ -#define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */ - -/*! @brief Read current value of the FTM_CnSC_ELSB field. */ -#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB)) - -/*! @brief Format value for bitfield FTM_CnSC_ELSB. */ -#define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB) - -/*! @brief Set the ELSB field to a new value. */ -#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field MSA[4] (RW) - * - * Used for further selections in the channel logic. Its functionality is - * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */ -#define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */ -#define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */ - -/*! @brief Read current value of the FTM_CnSC_MSA field. */ -#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA)) - -/*! @brief Format value for bitfield FTM_CnSC_MSA. */ -#define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA) - -/*! @brief Set the MSA field to a new value. */ -#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field MSB[5] (RW) - * - * Used for further selections in the channel logic. Its functionality is - * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - */ -/*@{*/ -#define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */ -#define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */ -#define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */ - -/*! @brief Read current value of the FTM_CnSC_MSB field. */ -#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB)) - -/*! @brief Format value for bitfield FTM_CnSC_MSB. */ -#define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB) - -/*! @brief Set the MSB field to a new value. */ -#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field CHIE[6] (RW) - * - * Enables channel interrupts. - * - * Values: - * - 0 - Disable channel interrupts. Use software polling. - * - 1 - Enable channel interrupts. - */ -/*@{*/ -#define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */ -#define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */ -#define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */ - -/*! @brief Read current value of the FTM_CnSC_CHIE field. */ -#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE)) - -/*! @brief Format value for bitfield FTM_CnSC_CHIE. */ -#define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE) - -/*! @brief Set the CHIE field to a new value. */ -#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CnSC, field CHF[7] (ROWZ) - * - * Set by hardware when an event occurs on the channel. CHF is cleared by - * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit. - * Writing a 1 to CHF has no effect. If another event occurs between the read and - * write operations, the write operation has no effect; therefore, CHF remains set - * indicating an event has occurred. In this case a CHF interrupt request is not - * lost due to the clearing sequence for a previous CHF. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */ -#define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */ -#define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */ - -/*! @brief Read current value of the FTM_CnSC_CHF field. */ -#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF)) - -/*! @brief Format value for bitfield FTM_CnSC_CHF. */ -#define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF) - -/*! @brief Set the CHF field to a new value. */ -#define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v)) -/*@}*/ -/******************************************************************************* - * HW_FTM_CnV - Channel (n) Value - ******************************************************************************/ - -/*! - * @brief HW_FTM_CnV - Channel (n) Value (RW) - * - * Reset value: 0x00000000U - * - * These registers contain the captured FTM counter value for the input modes or - * the match value for the output modes. In Input Capture, Capture Test, and - * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes, - * writing to a CnV register latches the value into a buffer. A CnV register is - * updated with the value of its write buffer according to Registers updated from - * write buffers. If FTMEN = 0, this write coherency mechanism may be manually - * reset by writing to the CnSC register whether BDM mode is active or not. - */ -typedef union _hw_ftm_cnv -{ - uint32_t U; - struct _hw_ftm_cnv_bitfields - { - uint32_t VAL : 16; /*!< [15:0] Channel Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_cnv_t; - -/*! - * @name Constants and macros for entire FTM_CnV register - */ -/*@{*/ -#define HW_FTM_CnV_COUNT (8U) - -#define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n))) - -#define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n)) -#define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U) -#define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v)) -#define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v))) -#define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v))) -#define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CnV bitfields - */ - -/*! - * @name Register FTM_CnV, field VAL[15:0] (RW) - * - * Captured FTM counter value of the input modes or the match value for the - * output modes - */ -/*@{*/ -#define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */ -#define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */ -#define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */ - -/*! @brief Read current value of the FTM_CnV_VAL field. */ -#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL) - -/*! @brief Format value for bitfield FTM_CnV_VAL. */ -#define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL) - -/*! @brief Set the VAL field to a new value. */ -#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CNTIN - Counter Initial Value - ******************************************************************************/ - -/*! - * @brief HW_FTM_CNTIN - Counter Initial Value (RW) - * - * Reset value: 0x00000000U - * - * The Counter Initial Value register contains the initial value for the FTM - * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN - * register is updated with the value of its write buffer according to Registers - * updated from write buffers. When the FTM clock is initially selected, by - * writing a non-zero value to the CLKS bits, the FTM counter starts with the value - * 0x0000. To avoid this behavior, before the first write to select the FTM clock, - * write the new value to the the CNTIN register and then initialize the FTM - * counter by writing any value to the CNT register. - */ -typedef union _hw_ftm_cntin -{ - uint32_t U; - struct _hw_ftm_cntin_bitfields - { - uint32_t INIT : 16; /*!< [15:0] */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_cntin_t; - -/*! - * @name Constants and macros for entire FTM_CNTIN register - */ -/*@{*/ -#define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU) - -#define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x)) -#define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U) -#define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v)) -#define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v))) -#define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v))) -#define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CNTIN bitfields - */ - -/*! - * @name Register FTM_CNTIN, field INIT[15:0] (RW) - * - * Initial Value Of The FTM Counter - */ -/*@{*/ -#define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */ -#define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */ -#define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */ - -/*! @brief Read current value of the FTM_CNTIN_INIT field. */ -#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT) - -/*! @brief Format value for bitfield FTM_CNTIN_INIT. */ -#define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT) - -/*! @brief Set the INIT field to a new value. */ -#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_STATUS - Capture And Compare Status - ******************************************************************************/ - -/*! - * @brief HW_FTM_STATUS - Capture And Compare Status (RW) - * - * Reset value: 0x00000000U - * - * The STATUS register contains a copy of the status flag CHnF bit in CnSC for - * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror - * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of - * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to - * STATUS. Hardware sets the individual channel flags when an event occurs on the - * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing - * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event - * occurs between the read and write operations, the write operation has no effect; - * therefore, CHnF remains set indicating an event has occurred. In this case, a - * CHnF interrupt request is not lost due to the clearing sequence for a previous - * CHnF. The STATUS register should be used only in Combine mode. - */ -typedef union _hw_ftm_status -{ - uint32_t U; - struct _hw_ftm_status_bitfields - { - uint32_t CH0F : 1; /*!< [0] Channel 0 Flag */ - uint32_t CH1F : 1; /*!< [1] Channel 1 Flag */ - uint32_t CH2F : 1; /*!< [2] Channel 2 Flag */ - uint32_t CH3F : 1; /*!< [3] Channel 3 Flag */ - uint32_t CH4F : 1; /*!< [4] Channel 4 Flag */ - uint32_t CH5F : 1; /*!< [5] Channel 5 Flag */ - uint32_t CH6F : 1; /*!< [6] Channel 6 Flag */ - uint32_t CH7F : 1; /*!< [7] Channel 7 Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_status_t; - -/*! - * @name Constants and macros for entire FTM_STATUS register - */ -/*@{*/ -#define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U) - -#define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x)) -#define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U) -#define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v)) -#define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v))) -#define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v))) -#define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_STATUS bitfields - */ - -/*! - * @name Register FTM_STATUS, field CH0F[0] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */ -#define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */ -#define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */ - -/*! @brief Read current value of the FTM_STATUS_CH0F field. */ -#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH0F. */ -#define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F) - -/*! @brief Set the CH0F field to a new value. */ -#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH1F[1] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */ -#define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */ -#define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */ - -/*! @brief Read current value of the FTM_STATUS_CH1F field. */ -#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH1F. */ -#define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F) - -/*! @brief Set the CH1F field to a new value. */ -#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH2F[2] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */ -#define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */ -#define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */ - -/*! @brief Read current value of the FTM_STATUS_CH2F field. */ -#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH2F. */ -#define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F) - -/*! @brief Set the CH2F field to a new value. */ -#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH3F[3] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */ -#define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */ -#define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */ - -/*! @brief Read current value of the FTM_STATUS_CH3F field. */ -#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH3F. */ -#define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F) - -/*! @brief Set the CH3F field to a new value. */ -#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH4F[4] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */ -#define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */ -#define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */ - -/*! @brief Read current value of the FTM_STATUS_CH4F field. */ -#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH4F. */ -#define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F) - -/*! @brief Set the CH4F field to a new value. */ -#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH5F[5] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */ -#define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */ -#define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */ - -/*! @brief Read current value of the FTM_STATUS_CH5F field. */ -#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH5F. */ -#define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F) - -/*! @brief Set the CH5F field to a new value. */ -#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH6F[6] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */ -#define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */ -#define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */ - -/*! @brief Read current value of the FTM_STATUS_CH6F field. */ -#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH6F. */ -#define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F) - -/*! @brief Set the CH6F field to a new value. */ -#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v)) -/*@}*/ - -/*! - * @name Register FTM_STATUS, field CH7F[7] (W1C) - * - * See the register description. - * - * Values: - * - 0 - No channel event has occurred. - * - 1 - A channel event has occurred. - */ -/*@{*/ -#define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */ -#define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */ -#define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */ - -/*! @brief Read current value of the FTM_STATUS_CH7F field. */ -#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F)) - -/*! @brief Format value for bitfield FTM_STATUS_CH7F. */ -#define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F) - -/*! @brief Set the CH7F field to a new value. */ -#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_MODE - Features Mode Selection - ******************************************************************************/ - -/*! - * @brief HW_FTM_MODE - Features Mode Selection (RW) - * - * Reset value: 0x00000004U - * - * This register contains the global enable bit for FTM-specific features and - * the control bits used to configure: Fault control mode and interrupt Capture - * Test mode PWM synchronization Write protection Channel output initialization - * These controls relate to all channels within this module. - */ -typedef union _hw_ftm_mode -{ - uint32_t U; - struct _hw_ftm_mode_bitfields - { - uint32_t FTMEN : 1; /*!< [0] FTM Enable */ - uint32_t INIT : 1; /*!< [1] Initialize The Channels Output */ - uint32_t WPDIS : 1; /*!< [2] Write Protection Disable */ - uint32_t PWMSYNC : 1; /*!< [3] PWM Synchronization Mode */ - uint32_t CAPTEST : 1; /*!< [4] Capture Test Mode Enable */ - uint32_t FAULTM : 2; /*!< [6:5] Fault Control Mode */ - uint32_t FAULTIE : 1; /*!< [7] Fault Interrupt Enable */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_mode_t; - -/*! - * @name Constants and macros for entire FTM_MODE register - */ -/*@{*/ -#define HW_FTM_MODE_ADDR(x) ((x) + 0x54U) - -#define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x)) -#define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U) -#define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v)) -#define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v))) -#define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v))) -#define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_MODE bitfields - */ - -/*! - * @name Register FTM_MODE, field FTMEN[0] (RW) - * - * This field is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Only the TPM-compatible registers (first set of registers) can be used - * without any restriction. Do not use the FTM-specific registers. - * - 1 - All registers including the FTM-specific registers (second set of - * registers) are available for use with no restrictions. - */ -/*@{*/ -#define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */ -#define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */ -#define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */ - -/*! @brief Read current value of the FTM_MODE_FTMEN field. */ -#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN)) - -/*! @brief Format value for bitfield FTM_MODE_FTMEN. */ -#define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN) - -/*! @brief Set the FTMEN field to a new value. */ -#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field INIT[1] (RW) - * - * When a 1 is written to INIT bit the channels output is initialized according - * to the state of their corresponding bit in the OUTINIT register. Writing a 0 - * to INIT bit has no effect. The INIT bit is always read as 0. - */ -/*@{*/ -#define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */ -#define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */ -#define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */ - -/*! @brief Read current value of the FTM_MODE_INIT field. */ -#define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT)) - -/*! @brief Format value for bitfield FTM_MODE_INIT. */ -#define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT) - -/*! @brief Set the INIT field to a new value. */ -#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field WPDIS[2] (RW) - * - * When write protection is enabled (WPDIS = 0), write protected bits cannot be - * written. When write protection is disabled (WPDIS = 1), write protected bits - * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared - * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then - * 1 is written to WPDIS. Writing 0 to WPDIS has no effect. - * - * Values: - * - 0 - Write protection is enabled. - * - 1 - Write protection is disabled. - */ -/*@{*/ -#define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */ -#define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */ -#define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */ - -/*! @brief Read current value of the FTM_MODE_WPDIS field. */ -#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS)) - -/*! @brief Format value for bitfield FTM_MODE_WPDIS. */ -#define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS) - -/*! @brief Set the WPDIS field to a new value. */ -#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field PWMSYNC[3] (RW) - * - * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter - * synchronization. See PWM synchronization. The PWMSYNC bit configures the - * synchronization when SYNCMODE is 0. - * - * Values: - * - 0 - No restrictions. Software and hardware triggers can be used by MOD, - * CnV, OUTMASK, and FTM counter synchronization. - * - 1 - Software trigger can only be used by MOD and CnV synchronization, and - * hardware triggers can only be used by OUTMASK and FTM counter - * synchronization. - */ -/*@{*/ -#define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */ -#define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */ -#define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */ - -/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */ -#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC)) - -/*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */ -#define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC) - -/*! @brief Set the PWMSYNC field to a new value. */ -#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field CAPTEST[4] (RW) - * - * Enables the capture test mode. This field is write protected. It can be - * written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Capture test mode is disabled. - * - 1 - Capture test mode is enabled. - */ -/*@{*/ -#define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */ -#define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */ -#define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */ - -/*! @brief Read current value of the FTM_MODE_CAPTEST field. */ -#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST)) - -/*! @brief Format value for bitfield FTM_MODE_CAPTEST. */ -#define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST) - -/*! @brief Set the CAPTEST field to a new value. */ -#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v)) -/*@}*/ - -/*! - * @name Register FTM_MODE, field FAULTM[6:5] (RW) - * - * Defines the FTM fault control mode. This field is write protected. It can be - * written only when MODE[WPDIS] = 1. - * - * Values: - * - 00 - Fault control is disabled for all channels. - * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and - * 6), and the selected mode is the manual fault clearing. - * - 10 - Fault control is enabled for all channels, and the selected mode is - * the manual fault clearing. - * - 11 - Fault control is enabled for all channels, and the selected mode is - * the automatic fault clearing. - */ -/*@{*/ -#define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */ -#define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */ -#define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */ - -/*! @brief Read current value of the FTM_MODE_FAULTM field. */ -#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM) - -/*! @brief Format value for bitfield FTM_MODE_FAULTM. */ -#define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM) - -/*! @brief Set the FAULTM field to a new value. */ -#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v))) -/*@}*/ - -/*! - * @name Register FTM_MODE, field FAULTIE[7] (RW) - * - * Enables the generation of an interrupt when a fault is detected by FTM and - * the FTM fault control is enabled. - * - * Values: - * - 0 - Fault control interrupt is disabled. - * - 1 - Fault control interrupt is enabled. - */ -/*@{*/ -#define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */ -#define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */ -#define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */ - -/*! @brief Read current value of the FTM_MODE_FAULTIE field. */ -#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE)) - -/*! @brief Format value for bitfield FTM_MODE_FAULTIE. */ -#define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE) - -/*! @brief Set the FAULTIE field to a new value. */ -#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_SYNC - Synchronization - ******************************************************************************/ - -/*! - * @brief HW_FTM_SYNC - Synchronization (RW) - * - * Reset value: 0x00000000U - * - * This register configures the PWM synchronization. A synchronization event can - * perform the synchronized update of MOD, CV, and OUTMASK registers with the - * value of their write buffer and the FTM counter initialization. The software - * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a - * potential conflict if used together when SYNCMODE = 0. Use only hardware or - * software triggers but not both at the same time, otherwise unpredictable behavior - * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN - * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across - * all enabled channels simultaneously. The use of the loading point selection - * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2 - * bits, is likely to result in unpredictable behavior. The synchronization - * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF - * register) bits. See PWM synchronization. - */ -typedef union _hw_ftm_sync -{ - uint32_t U; - struct _hw_ftm_sync_bitfields - { - uint32_t CNTMIN : 1; /*!< [0] Minimum Loading Point Enable */ - uint32_t CNTMAX : 1; /*!< [1] Maximum Loading Point Enable */ - uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By - * Synchronization (FTM counter synchronization) */ - uint32_t SYNCHOM : 1; /*!< [3] Output Mask Synchronization */ - uint32_t TRIG0 : 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */ - uint32_t TRIG1 : 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */ - uint32_t TRIG2 : 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */ - uint32_t SWSYNC : 1; /*!< [7] PWM Synchronization Software Trigger */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_sync_t; - -/*! - * @name Constants and macros for entire FTM_SYNC register - */ -/*@{*/ -#define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U) - -#define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x)) -#define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U) -#define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v)) -#define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v))) -#define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v))) -#define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SYNC bitfields - */ - -/*! - * @name Register FTM_SYNC, field CNTMIN[0] (RW) - * - * Selects the minimum loading point to PWM synchronization. See Boundary cycle - * and loading points. If CNTMIN is one, the selected loading point is when the - * FTM counter reaches its minimum value (CNTIN register). - * - * Values: - * - 0 - The minimum loading point is disabled. - * - 1 - The minimum loading point is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */ -#define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */ -#define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */ - -/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */ -#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN)) - -/*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */ -#define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN) - -/*! @brief Set the CNTMIN field to a new value. */ -#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field CNTMAX[1] (RW) - * - * Selects the maximum loading point to PWM synchronization. See Boundary cycle - * and loading points. If CNTMAX is 1, the selected loading point is when the FTM - * counter reaches its maximum value (MOD register). - * - * Values: - * - 0 - The maximum loading point is disabled. - * - 1 - The maximum loading point is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */ -#define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */ -#define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */ - -/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */ -#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX)) - -/*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */ -#define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX) - -/*! @brief Set the CNTMAX field to a new value. */ -#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field REINIT[2] (RW) - * - * Determines if the FTM counter is reinitialized when the selected trigger for - * the synchronization is detected. The REINIT bit configures the synchronization - * when SYNCMODE is zero. - * - * Values: - * - 0 - FTM counter continues to count normally. - * - 1 - FTM counter is updated with its initial value when the selected trigger - * is detected. - */ -/*@{*/ -#define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */ -#define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */ -#define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */ - -/*! @brief Read current value of the FTM_SYNC_REINIT field. */ -#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT)) - -/*! @brief Format value for bitfield FTM_SYNC_REINIT. */ -#define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT) - -/*! @brief Set the REINIT field to a new value. */ -#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field SYNCHOM[3] (RW) - * - * Selects when the OUTMASK register is updated with the value of its buffer. - * - * Values: - * - 0 - OUTMASK register is updated with the value of its buffer in all rising - * edges of the system clock. - * - 1 - OUTMASK register is updated with the value of its buffer only by the - * PWM synchronization. - */ -/*@{*/ -#define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */ -#define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */ -#define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */ - -/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */ -#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM)) - -/*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */ -#define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM) - -/*! @brief Set the SYNCHOM field to a new value. */ -#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field TRIG0[4] (RW) - * - * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0 - * occurs when a rising edge is detected at the trigger 0 input signal. - * - * Values: - * - 0 - Trigger is disabled. - * - 1 - Trigger is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */ -#define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */ -#define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */ - -/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */ -#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0)) - -/*! @brief Format value for bitfield FTM_SYNC_TRIG0. */ -#define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0) - -/*! @brief Set the TRIG0 field to a new value. */ -#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field TRIG1[5] (RW) - * - * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 - * happens when a rising edge is detected at the trigger 1 input signal. - * - * Values: - * - 0 - Trigger is disabled. - * - 1 - Trigger is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */ -#define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */ -#define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */ - -/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */ -#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1)) - -/*! @brief Format value for bitfield FTM_SYNC_TRIG1. */ -#define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1) - -/*! @brief Set the TRIG1 field to a new value. */ -#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field TRIG2[6] (RW) - * - * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 - * happens when a rising edge is detected at the trigger 2 input signal. - * - * Values: - * - 0 - Trigger is disabled. - * - 1 - Trigger is enabled. - */ -/*@{*/ -#define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */ -#define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */ -#define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */ - -/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */ -#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2)) - -/*! @brief Format value for bitfield FTM_SYNC_TRIG2. */ -#define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2) - -/*! @brief Set the TRIG2 field to a new value. */ -#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNC, field SWSYNC[7] (RW) - * - * Selects the software trigger as the PWM synchronization trigger. The software - * trigger happens when a 1 is written to SWSYNC bit. - * - * Values: - * - 0 - Software trigger is not selected. - * - 1 - Software trigger is selected. - */ -/*@{*/ -#define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */ -#define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */ -#define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */ - -/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */ -#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC)) - -/*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */ -#define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC) - -/*! @brief Set the SWSYNC field to a new value. */ -#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_OUTINIT - Initial State For Channels Output - ******************************************************************************/ - -/*! - * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_ftm_outinit -{ - uint32_t U; - struct _hw_ftm_outinit_bitfields - { - uint32_t CH0OI : 1; /*!< [0] Channel 0 Output Initialization Value */ - uint32_t CH1OI : 1; /*!< [1] Channel 1 Output Initialization Value */ - uint32_t CH2OI : 1; /*!< [2] Channel 2 Output Initialization Value */ - uint32_t CH3OI : 1; /*!< [3] Channel 3 Output Initialization Value */ - uint32_t CH4OI : 1; /*!< [4] Channel 4 Output Initialization Value */ - uint32_t CH5OI : 1; /*!< [5] Channel 5 Output Initialization Value */ - uint32_t CH6OI : 1; /*!< [6] Channel 6 Output Initialization Value */ - uint32_t CH7OI : 1; /*!< [7] Channel 7 Output Initialization Value */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_outinit_t; - -/*! - * @name Constants and macros for entire FTM_OUTINIT register - */ -/*@{*/ -#define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU) - -#define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x)) -#define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U) -#define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v)) -#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v))) -#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v))) -#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_OUTINIT bitfields - */ - -/*! - * @name Register FTM_OUTINIT, field CH0OI[0] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */ -#define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */ -#define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */ -#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */ -#define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI) - -/*! @brief Set the CH0OI field to a new value. */ -#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH1OI[1] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */ -#define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */ -#define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */ -#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */ -#define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI) - -/*! @brief Set the CH1OI field to a new value. */ -#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH2OI[2] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */ -#define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */ -#define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */ -#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */ -#define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI) - -/*! @brief Set the CH2OI field to a new value. */ -#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH3OI[3] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */ -#define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */ -#define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */ -#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */ -#define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI) - -/*! @brief Set the CH3OI field to a new value. */ -#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH4OI[4] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */ -#define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */ -#define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */ -#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */ -#define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI) - -/*! @brief Set the CH4OI field to a new value. */ -#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH5OI[5] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */ -#define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */ -#define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */ -#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */ -#define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI) - -/*! @brief Set the CH5OI field to a new value. */ -#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH6OI[6] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */ -#define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */ -#define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */ -#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */ -#define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI) - -/*! @brief Set the CH6OI field to a new value. */ -#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTINIT, field CH7OI[7] (RW) - * - * Selects the value that is forced into the channel output when the - * initialization occurs. - * - * Values: - * - 0 - The initialization value is 0. - * - 1 - The initialization value is 1. - */ -/*@{*/ -#define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */ -#define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */ -#define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */ - -/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */ -#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI)) - -/*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */ -#define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI) - -/*! @brief Set the CH7OI field to a new value. */ -#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_OUTMASK - Output Mask - ******************************************************************************/ - -/*! - * @brief HW_FTM_OUTMASK - Output Mask (RW) - * - * Reset value: 0x00000000U - * - * This register provides a mask for each FTM channel. The mask of a channel - * determines if its output responds, that is, it is masked or not, when a match - * occurs. This feature is used for BLDC control where the PWM signal is presented - * to an electric motor at specific times to provide electronic commutation. Any - * write to the OUTMASK register, stores the value in its write buffer. The - * register is updated with the value of its write buffer according to PWM - * synchronization. - */ -typedef union _hw_ftm_outmask -{ - uint32_t U; - struct _hw_ftm_outmask_bitfields - { - uint32_t CH0OM : 1; /*!< [0] Channel 0 Output Mask */ - uint32_t CH1OM : 1; /*!< [1] Channel 1 Output Mask */ - uint32_t CH2OM : 1; /*!< [2] Channel 2 Output Mask */ - uint32_t CH3OM : 1; /*!< [3] Channel 3 Output Mask */ - uint32_t CH4OM : 1; /*!< [4] Channel 4 Output Mask */ - uint32_t CH5OM : 1; /*!< [5] Channel 5 Output Mask */ - uint32_t CH6OM : 1; /*!< [6] Channel 6 Output Mask */ - uint32_t CH7OM : 1; /*!< [7] Channel 7 Output Mask */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_outmask_t; - -/*! - * @name Constants and macros for entire FTM_OUTMASK register - */ -/*@{*/ -#define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U) - -#define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x)) -#define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U) -#define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v)) -#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v))) -#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v))) -#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_OUTMASK bitfields - */ - -/*! - * @name Register FTM_OUTMASK, field CH0OM[0] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */ -#define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */ -#define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */ -#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */ -#define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM) - -/*! @brief Set the CH0OM field to a new value. */ -#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH1OM[1] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */ -#define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */ -#define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */ -#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */ -#define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM) - -/*! @brief Set the CH1OM field to a new value. */ -#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH2OM[2] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */ -#define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */ -#define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */ -#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */ -#define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM) - -/*! @brief Set the CH2OM field to a new value. */ -#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH3OM[3] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */ -#define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */ -#define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */ -#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */ -#define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM) - -/*! @brief Set the CH3OM field to a new value. */ -#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH4OM[4] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */ -#define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */ -#define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */ -#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */ -#define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM) - -/*! @brief Set the CH4OM field to a new value. */ -#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH5OM[5] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */ -#define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */ -#define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */ -#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */ -#define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM) - -/*! @brief Set the CH5OM field to a new value. */ -#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH6OM[6] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */ -#define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */ -#define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */ -#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */ -#define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM) - -/*! @brief Set the CH6OM field to a new value. */ -#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_OUTMASK, field CH7OM[7] (RW) - * - * Defines if the channel output is masked or unmasked. - * - * Values: - * - 0 - Channel output is not masked. It continues to operate normally. - * - 1 - Channel output is masked. It is forced to its inactive state. - */ -/*@{*/ -#define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */ -#define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */ -#define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */ - -/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */ -#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM)) - -/*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */ -#define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM) - -/*! @brief Set the CH7OM field to a new value. */ -#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_COMBINE - Function For Linked Channels - ******************************************************************************/ - -/*! - * @brief HW_FTM_COMBINE - Function For Linked Channels (RW) - * - * Reset value: 0x00000000U - * - * This register contains the control bits used to configure the fault control, - * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary, - * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, - * 4, and 6. - */ -typedef union _hw_ftm_combine -{ - uint32_t U; - struct _hw_ftm_combine_bitfields - { - uint32_t COMBINE0 : 1; /*!< [0] Combine Channels For n = 0 */ - uint32_t COMP0 : 1; /*!< [1] Complement Of Channel (n) For n = 0 */ - uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n = - * 0 */ - uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n = - * 0 */ - uint32_t DTEN0 : 1; /*!< [4] Deadtime Enable For n = 0 */ - uint32_t SYNCEN0 : 1; /*!< [5] Synchronization Enable For n = 0 */ - uint32_t FAULTEN0 : 1; /*!< [6] Fault Control Enable For n = 0 */ - uint32_t RESERVED0 : 1; /*!< [7] */ - uint32_t COMBINE1 : 1; /*!< [8] Combine Channels For n = 2 */ - uint32_t COMP1 : 1; /*!< [9] Complement Of Channel (n) For n = 2 */ - uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n - * = 2 */ - uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n - * = 2 */ - uint32_t DTEN1 : 1; /*!< [12] Deadtime Enable For n = 2 */ - uint32_t SYNCEN1 : 1; /*!< [13] Synchronization Enable For n = 2 */ - uint32_t FAULTEN1 : 1; /*!< [14] Fault Control Enable For n = 2 */ - uint32_t RESERVED1 : 1; /*!< [15] */ - uint32_t COMBINE2 : 1; /*!< [16] Combine Channels For n = 4 */ - uint32_t COMP2 : 1; /*!< [17] Complement Of Channel (n) For n = 4 */ - uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n - * = 4 */ - uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n - * = 4 */ - uint32_t DTEN2 : 1; /*!< [20] Deadtime Enable For n = 4 */ - uint32_t SYNCEN2 : 1; /*!< [21] Synchronization Enable For n = 4 */ - uint32_t FAULTEN2 : 1; /*!< [22] Fault Control Enable For n = 4 */ - uint32_t RESERVED2 : 1; /*!< [23] */ - uint32_t COMBINE3 : 1; /*!< [24] Combine Channels For n = 6 */ - uint32_t COMP3 : 1; /*!< [25] Complement Of Channel (n) for n = 6 */ - uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n - * = 6 */ - uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n - * = 6 */ - uint32_t DTEN3 : 1; /*!< [28] Deadtime Enable For n = 6 */ - uint32_t SYNCEN3 : 1; /*!< [29] Synchronization Enable For n = 6 */ - uint32_t FAULTEN3 : 1; /*!< [30] Fault Control Enable For n = 6 */ - uint32_t RESERVED3 : 1; /*!< [31] */ - } B; -} hw_ftm_combine_t; - -/*! - * @name Constants and macros for entire FTM_COMBINE register - */ -/*@{*/ -#define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U) - -#define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x)) -#define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U) -#define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v)) -#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v))) -#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v))) -#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_COMBINE bitfields - */ - -/*! - * @name Register FTM_COMBINE, field COMBINE0[0] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */ -#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */ -#define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */ -#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */ -#define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0) - -/*! @brief Set the COMBINE0 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP0[1] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */ -#define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */ -#define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */ -#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP0. */ -#define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0) - -/*! @brief Set the COMP0 field to a new value. */ -#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN0[2] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */ -#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */ -#define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */ -#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */ -#define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0) - -/*! @brief Set the DECAPEN0 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP0[3] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if dual edge capture - one-shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */ -#define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */ -#define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */ -#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */ -#define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0) - -/*! @brief Set the DECAP0 field to a new value. */ -#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN0[4] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */ -#define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */ -#define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */ -#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */ -#define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0) - -/*! @brief Set the DTEN0 field to a new value. */ -#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN0[5] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */ -#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */ -#define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */ -#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */ -#define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0) - -/*! @brief Set the SYNCEN0 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN0[6] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */ -#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */ -#define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */ -#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */ -#define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0) - -/*! @brief Set the FAULTEN0 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMBINE1[8] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */ -#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */ -#define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */ -#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */ -#define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1) - -/*! @brief Set the COMBINE1 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP1[9] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */ -#define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */ -#define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */ -#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP1. */ -#define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1) - -/*! @brief Set the COMP1 field to a new value. */ -#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN1[10] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */ -#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */ -#define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */ -#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */ -#define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1) - -/*! @brief Set the DECAPEN1 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP1[11] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */ -#define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */ -#define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */ -#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */ -#define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1) - -/*! @brief Set the DECAP1 field to a new value. */ -#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN1[12] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */ -#define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */ -#define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */ -#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */ -#define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1) - -/*! @brief Set the DTEN1 field to a new value. */ -#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN1[13] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */ -#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */ -#define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */ -#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */ -#define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1) - -/*! @brief Set the SYNCEN1 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN1[14] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */ -#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */ -#define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */ -#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */ -#define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1) - -/*! @brief Set the FAULTEN1 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMBINE2[16] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */ -#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */ -#define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */ -#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */ -#define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2) - -/*! @brief Set the COMBINE2 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP2[17] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */ -#define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */ -#define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */ -#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP2. */ -#define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2) - -/*! @brief Set the COMP2 field to a new value. */ -#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN2[18] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */ -#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */ -#define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */ -#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */ -#define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2) - -/*! @brief Set the DECAPEN2 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP2[19] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if dual edge capture - one-shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */ -#define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */ -#define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */ -#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */ -#define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2) - -/*! @brief Set the DECAP2 field to a new value. */ -#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN2[20] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */ -#define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */ -#define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */ -#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */ -#define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2) - -/*! @brief Set the DTEN2 field to a new value. */ -#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN2[21] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */ -#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */ -#define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */ -#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */ -#define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2) - -/*! @brief Set the SYNCEN2 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN2[22] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */ -#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */ -#define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */ -#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */ -#define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2) - -/*! @brief Set the FAULTEN2 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMBINE3[24] (RW) - * - * Enables the combine feature for channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Channels (n) and (n+1) are independent. - * - 1 - Channels (n) and (n+1) are combined. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */ -#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */ -#define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */ - -/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */ -#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */ -#define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3) - -/*! @brief Set the COMBINE3 field to a new value. */ -#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field COMP3[25] (RW) - * - * Enables Complementary mode for the combined channels. In Complementary mode - * the channel (n+1) output is the inverse of the channel (n) output. This field - * is write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel (n+1) output is the same as the channel (n) output. - * - 1 - The channel (n+1) output is the complement of the channel (n) output. - */ -/*@{*/ -#define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */ -#define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */ -#define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */ - -/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */ -#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3)) - -/*! @brief Format value for bitfield FTM_COMBINE_COMP3. */ -#define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3) - -/*! @brief Set the COMP3 field to a new value. */ -#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAPEN3[26] (RW) - * - * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit - * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field applies only - * when FTMEN = 1. This field is write protected. It can be written only when - * MODE[WPDIS] = 1. - * - * Values: - * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. - * - 1 - The Dual Edge Capture mode in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */ -#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */ -#define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */ -#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */ -#define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3) - -/*! @brief Set the DECAPEN3 field to a new value. */ -#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DECAP3[27] (RW) - * - * Enables the capture of the FTM counter value according to the channel (n) - * input event and the configuration of the dual edge capture bits. This field - * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by - * hardware if dual edge capture - one-shot mode is selected and when the capture - * of channel (n+1) event is made. - * - * Values: - * - 0 - The dual edge captures are inactive. - * - 1 - The dual edge captures are active. - */ -/*@{*/ -#define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */ -#define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */ -#define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */ - -/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */ -#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3)) - -/*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */ -#define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3) - -/*! @brief Set the DECAP3 field to a new value. */ -#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field DTEN3[28] (RW) - * - * Enables the deadtime insertion in the channels (n) and (n+1). This field is - * write protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The deadtime insertion in this pair of channels is disabled. - * - 1 - The deadtime insertion in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */ -#define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */ -#define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */ -#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */ -#define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3) - -/*! @brief Set the DTEN3 field to a new value. */ -#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field SYNCEN3[29] (RW) - * - * Enables PWM synchronization of registers C(n)V and C(n+1)V. - * - * Values: - * - 0 - The PWM synchronization in this pair of channels is disabled. - * - 1 - The PWM synchronization in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */ -#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */ -#define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */ -#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */ -#define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3) - -/*! @brief Set the SYNCEN3 field to a new value. */ -#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_COMBINE, field FAULTEN3[30] (RW) - * - * Enables the fault control in channels (n) and (n+1). This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault control in this pair of channels is disabled. - * - 1 - The fault control in this pair of channels is enabled. - */ -/*@{*/ -#define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */ -#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */ -#define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */ - -/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */ -#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3)) - -/*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */ -#define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3) - -/*! @brief Set the FAULTEN3 field to a new value. */ -#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_DEADTIME - Deadtime Insertion Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW) - * - * Reset value: 0x00000000U - * - * This register selects the deadtime prescaler factor and deadtime value. All - * FTM channels use this clock prescaler and this deadtime value for the deadtime - * insertion. - */ -typedef union _hw_ftm_deadtime -{ - uint32_t U; - struct _hw_ftm_deadtime_bitfields - { - uint32_t DTVAL : 6; /*!< [5:0] Deadtime Value */ - uint32_t DTPS : 2; /*!< [7:6] Deadtime Prescaler Value */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_deadtime_t; - -/*! - * @name Constants and macros for entire FTM_DEADTIME register - */ -/*@{*/ -#define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U) - -#define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x)) -#define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U) -#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v)) -#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v))) -#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v))) -#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_DEADTIME bitfields - */ - -/*! - * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW) - * - * Selects the deadtime insertion value for the deadtime counter. The deadtime - * counter is clocked by a scaled version of the system clock. See the description - * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of - * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted. - * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted. - * This pattern continues up to a possible 63 counts. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. - */ -/*@{*/ -#define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */ -#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */ -#define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */ - -/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */ -#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL) - -/*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */ -#define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL) - -/*! @brief Set the DTVAL field to a new value. */ -#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_DEADTIME, field DTPS[7:6] (RW) - * - * Selects the division factor of the system clock. This prescaled clock is used - * by the deadtime counter. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0x - Divide the system clock by 1. - * - 10 - Divide the system clock by 4. - * - 11 - Divide the system clock by 16. - */ -/*@{*/ -#define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */ -#define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */ -#define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */ - -/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */ -#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS) - -/*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */ -#define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS) - -/*! @brief Set the DTPS field to a new value. */ -#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_EXTTRIG - FTM External Trigger - ******************************************************************************/ - -/*! - * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW) - * - * Reset value: 0x00000000U - * - * This register: Indicates when a channel trigger was generated Enables the - * generation of a trigger when the FTM counter is equal to its initial value - * Selects which channels are used in the generation of the channel triggers Several - * channels can be selected to generate multiple triggers in one PWM period. - * Channels 6 and 7 are not used to generate channel triggers. - */ -typedef union _hw_ftm_exttrig -{ - uint32_t U; - struct _hw_ftm_exttrig_bitfields - { - uint32_t CH2TRIG : 1; /*!< [0] Channel 2 Trigger Enable */ - uint32_t CH3TRIG : 1; /*!< [1] Channel 3 Trigger Enable */ - uint32_t CH4TRIG : 1; /*!< [2] Channel 4 Trigger Enable */ - uint32_t CH5TRIG : 1; /*!< [3] Channel 5 Trigger Enable */ - uint32_t CH0TRIG : 1; /*!< [4] Channel 0 Trigger Enable */ - uint32_t CH1TRIG : 1; /*!< [5] Channel 1 Trigger Enable */ - uint32_t INITTRIGEN : 1; /*!< [6] Initialization Trigger Enable */ - uint32_t TRIGF : 1; /*!< [7] Channel Trigger Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_exttrig_t; - -/*! - * @name Constants and macros for entire FTM_EXTTRIG register - */ -/*@{*/ -#define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU) - -#define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x)) -#define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U) -#define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v)) -#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v))) -#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v))) -#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_EXTTRIG bitfields - */ - -/*! - * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */ -#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */ -#define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */ -#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */ -#define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG) - -/*! @brief Set the CH2TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */ -#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */ -#define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */ -#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */ -#define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG) - -/*! @brief Set the CH3TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */ -#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */ -#define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */ -#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */ -#define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG) - -/*! @brief Set the CH4TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */ -#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */ -#define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */ -#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */ -#define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG) - -/*! @brief Set the CH5TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */ -#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */ -#define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */ -#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */ -#define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG) - -/*! @brief Set the CH0TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW) - * - * Enables the generation of the channel trigger when the FTM counter is equal - * to the CnV register. - * - * Values: - * - 0 - The generation of the channel trigger is disabled. - * - 1 - The generation of the channel trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */ -#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */ -#define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */ - -/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */ -#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */ -#define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG) - -/*! @brief Set the CH1TRIG field to a new value. */ -#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW) - * - * Enables the generation of the trigger when the FTM counter is equal to the - * CNTIN register. - * - * Values: - * - 0 - The generation of initialization trigger is disabled. - * - 1 - The generation of initialization trigger is enabled. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */ -#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */ -#define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */ - -/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */ -#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */ -#define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN) - -/*! @brief Set the INITTRIGEN field to a new value. */ -#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ) - * - * Set by hardware when a channel trigger is generated. Clear TRIGF by reading - * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF - * has no effect. If another channel trigger is generated before the clearing - * sequence is completed, the sequence is reset so TRIGF remains set after the clear - * sequence is completed for the earlier TRIGF. - * - * Values: - * - 0 - No channel trigger was generated. - * - 1 - A channel trigger was generated. - */ -/*@{*/ -#define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */ -#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */ -#define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */ - -/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */ -#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF)) - -/*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */ -#define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF) - -/*! @brief Set the TRIGF field to a new value. */ -#define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_POL - Channels Polarity - ******************************************************************************/ - -/*! - * @brief HW_FTM_POL - Channels Polarity (RW) - * - * Reset value: 0x00000000U - * - * This register defines the output polarity of the FTM channels. The safe value - * that is driven in a channel output when the fault control is enabled and a - * fault condition is detected is the inactive state of the channel. That is, the - * safe value of a channel is the value of its POL bit. - */ -typedef union _hw_ftm_pol -{ - uint32_t U; - struct _hw_ftm_pol_bitfields - { - uint32_t POL0 : 1; /*!< [0] Channel 0 Polarity */ - uint32_t POL1 : 1; /*!< [1] Channel 1 Polarity */ - uint32_t POL2 : 1; /*!< [2] Channel 2 Polarity */ - uint32_t POL3 : 1; /*!< [3] Channel 3 Polarity */ - uint32_t POL4 : 1; /*!< [4] Channel 4 Polarity */ - uint32_t POL5 : 1; /*!< [5] Channel 5 Polarity */ - uint32_t POL6 : 1; /*!< [6] Channel 6 Polarity */ - uint32_t POL7 : 1; /*!< [7] Channel 7 Polarity */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_pol_t; - -/*! - * @name Constants and macros for entire FTM_POL register - */ -/*@{*/ -#define HW_FTM_POL_ADDR(x) ((x) + 0x70U) - -#define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x)) -#define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U) -#define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v)) -#define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v))) -#define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v))) -#define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_POL bitfields - */ - -/*! - * @name Register FTM_POL, field POL0[0] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */ -#define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */ -#define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */ - -/*! @brief Read current value of the FTM_POL_POL0 field. */ -#define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0)) - -/*! @brief Format value for bitfield FTM_POL_POL0. */ -#define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0) - -/*! @brief Set the POL0 field to a new value. */ -#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL1[1] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */ -#define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */ -#define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */ - -/*! @brief Read current value of the FTM_POL_POL1 field. */ -#define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1)) - -/*! @brief Format value for bitfield FTM_POL_POL1. */ -#define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1) - -/*! @brief Set the POL1 field to a new value. */ -#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL2[2] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */ -#define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */ -#define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */ - -/*! @brief Read current value of the FTM_POL_POL2 field. */ -#define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2)) - -/*! @brief Format value for bitfield FTM_POL_POL2. */ -#define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2) - -/*! @brief Set the POL2 field to a new value. */ -#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL3[3] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */ -#define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */ -#define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */ - -/*! @brief Read current value of the FTM_POL_POL3 field. */ -#define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3)) - -/*! @brief Format value for bitfield FTM_POL_POL3. */ -#define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3) - -/*! @brief Set the POL3 field to a new value. */ -#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL4[4] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */ -#define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */ -#define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */ - -/*! @brief Read current value of the FTM_POL_POL4 field. */ -#define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4)) - -/*! @brief Format value for bitfield FTM_POL_POL4. */ -#define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4) - -/*! @brief Set the POL4 field to a new value. */ -#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL5[5] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */ -#define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */ -#define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */ - -/*! @brief Read current value of the FTM_POL_POL5 field. */ -#define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5)) - -/*! @brief Format value for bitfield FTM_POL_POL5. */ -#define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5) - -/*! @brief Set the POL5 field to a new value. */ -#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL6[6] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */ -#define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */ -#define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */ - -/*! @brief Read current value of the FTM_POL_POL6 field. */ -#define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6)) - -/*! @brief Format value for bitfield FTM_POL_POL6. */ -#define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6) - -/*! @brief Set the POL6 field to a new value. */ -#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v)) -/*@}*/ - -/*! - * @name Register FTM_POL, field POL7[7] (RW) - * - * Defines the polarity of the channel output. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The channel polarity is active high. - * - 1 - The channel polarity is active low. - */ -/*@{*/ -#define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */ -#define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */ -#define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */ - -/*! @brief Read current value of the FTM_POL_POL7 field. */ -#define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7)) - -/*! @brief Format value for bitfield FTM_POL_POL7. */ -#define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7) - -/*! @brief Set the POL7 field to a new value. */ -#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FMS - Fault Mode Status - ******************************************************************************/ - -/*! - * @brief HW_FTM_FMS - Fault Mode Status (RW) - * - * Reset value: 0x00000000U - * - * This register contains the fault detection flags, write protection enable - * bit, and the logic OR of the enabled fault inputs. - */ -typedef union _hw_ftm_fms -{ - uint32_t U; - struct _hw_ftm_fms_bitfields - { - uint32_t FAULTF0 : 1; /*!< [0] Fault Detection Flag 0 */ - uint32_t FAULTF1 : 1; /*!< [1] Fault Detection Flag 1 */ - uint32_t FAULTF2 : 1; /*!< [2] Fault Detection Flag 2 */ - uint32_t FAULTF3 : 1; /*!< [3] Fault Detection Flag 3 */ - uint32_t RESERVED0 : 1; /*!< [4] */ - uint32_t FAULTIN : 1; /*!< [5] Fault Inputs */ - uint32_t WPEN : 1; /*!< [6] Write Protection Enable */ - uint32_t FAULTF : 1; /*!< [7] Fault Detection Flag */ - uint32_t RESERVED1 : 24; /*!< [31:8] */ - } B; -} hw_ftm_fms_t; - -/*! - * @name Constants and macros for entire FTM_FMS register - */ -/*@{*/ -#define HW_FTM_FMS_ADDR(x) ((x) + 0x74U) - -#define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x)) -#define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U) -#define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v)) -#define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v))) -#define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v))) -#define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FMS bitfields - */ - -/*! - * @name Register FTM_FMS, field FAULTF0[0] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF0 - * by reading the FMS register while FAULTF0 is set and then writing a 0 to - * FAULTF0 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF0 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */ -#define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */ -#define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */ -#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF0. */ -#define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0) - -/*! @brief Set the FAULTF0 field to a new value. */ -#define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF1[1] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF1 - * by reading the FMS register while FAULTF1 is set and then writing a 0 to - * FAULTF1 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF1 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */ -#define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */ -#define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */ -#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF1. */ -#define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1) - -/*! @brief Set the FAULTF1 field to a new value. */ -#define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF2[2] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF2 - * by reading the FMS register while FAULTF2 is set and then writing a 0 to - * FAULTF2 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF2 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */ -#define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */ -#define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */ -#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF2. */ -#define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2) - -/*! @brief Set the FAULTF2 field to a new value. */ -#define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF3[3] (ROWZ) - * - * Set by hardware when fault control is enabled, the corresponding fault input - * is enabled and a fault condition is detected at the fault input. Clear FAULTF3 - * by reading the FMS register while FAULTF3 is set and then writing a 0 to - * FAULTF3 while there is no existing fault condition at the corresponding fault - * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when - * FAULTF bit is cleared. If another fault condition is detected at the corresponding - * fault input before the clearing sequence is completed, the sequence is reset - * so FAULTF3 remains set after the clearing sequence is completed for the - * earlier fault condition. - * - * Values: - * - 0 - No fault condition was detected at the fault input. - * - 1 - A fault condition was detected at the fault input. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */ -#define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */ -#define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */ -#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF3. */ -#define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3) - -/*! @brief Set the FAULTF3 field to a new value. */ -#define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTIN[5] (RO) - * - * Represents the logic OR of the enabled fault inputs after their filter (if - * their filter is enabled) when fault control is enabled. - * - * Values: - * - 0 - The logic OR of the enabled fault inputs is 0. - * - 1 - The logic OR of the enabled fault inputs is 1. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */ -#define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */ -#define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */ - -/*! @brief Read current value of the FTM_FMS_FAULTIN field. */ -#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field WPEN[6] (RW) - * - * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written - * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to - * WPDIS. Writing 0 to WPEN has no effect. - * - * Values: - * - 0 - Write protection is disabled. Write protected bits can be written. - * - 1 - Write protection is enabled. Write protected bits cannot be written. - */ -/*@{*/ -#define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */ -#define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */ -#define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */ - -/*! @brief Read current value of the FTM_FMS_WPEN field. */ -#define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN)) - -/*! @brief Format value for bitfield FTM_FMS_WPEN. */ -#define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN) - -/*! @brief Set the WPEN field to a new value. */ -#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FMS, field FAULTF[7] (ROWZ) - * - * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0. - * Clear FAULTF by reading the FMS register while FAULTF is set and then writing - * a 0 to FAULTF while there is no existing fault condition at the enabled fault - * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is - * detected in an enabled fault input before the clearing sequence is completed, the - * sequence is reset so FAULTF remains set after the clearing sequence is - * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits - * are cleared individually. - * - * Values: - * - 0 - No fault condition was detected. - * - 1 - A fault condition was detected. - */ -/*@{*/ -#define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */ -#define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */ -#define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */ - -/*! @brief Read current value of the FTM_FMS_FAULTF field. */ -#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF)) - -/*! @brief Format value for bitfield FTM_FMS_FAULTF. */ -#define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF) - -/*! @brief Set the FAULTF field to a new value. */ -#define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FILTER - Input Capture Filter Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_FILTER - Input Capture Filter Control (RW) - * - * Reset value: 0x00000000U - * - * This register selects the filter value for the inputs of channels. Channels - * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has - * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not - * in input modes. Failure to do this could result in a missing valid signal. - */ -typedef union _hw_ftm_filter -{ - uint32_t U; - struct _hw_ftm_filter_bitfields - { - uint32_t CH0FVAL : 4; /*!< [3:0] Channel 0 Input Filter */ - uint32_t CH1FVAL : 4; /*!< [7:4] Channel 1 Input Filter */ - uint32_t CH2FVAL : 4; /*!< [11:8] Channel 2 Input Filter */ - uint32_t CH3FVAL : 4; /*!< [15:12] Channel 3 Input Filter */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_filter_t; - -/*! - * @name Constants and macros for entire FTM_FILTER register - */ -/*@{*/ -#define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U) - -#define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x)) -#define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U) -#define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v)) -#define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v))) -#define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v))) -#define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FILTER bitfields - */ - -/*! - * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */ -#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */ -#define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */ -#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */ -#define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL) - -/*! @brief Set the CH0FVAL field to a new value. */ -#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */ -#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */ -#define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */ -#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */ -#define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL) - -/*! @brief Set the CH1FVAL field to a new value. */ -#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */ -#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */ -#define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */ -#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */ -#define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL) - -/*! @brief Set the CH2FVAL field to a new value. */ -#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v))) -/*@}*/ - -/*! - * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW) - * - * Selects the filter value for the channel input. The filter is disabled when - * the value is zero. - */ -/*@{*/ -#define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */ -#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */ -#define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */ - -/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */ -#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL) - -/*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */ -#define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL) - -/*! @brief Set the CH3FVAL field to a new value. */ -#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FLTCTRL - Fault Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_FLTCTRL - Fault Control (RW) - * - * Reset value: 0x00000000U - * - * This register selects the filter value for the fault inputs, enables the - * fault inputs and the fault inputs filter. - */ -typedef union _hw_ftm_fltctrl -{ - uint32_t U; - struct _hw_ftm_fltctrl_bitfields - { - uint32_t FAULT0EN : 1; /*!< [0] Fault Input 0 Enable */ - uint32_t FAULT1EN : 1; /*!< [1] Fault Input 1 Enable */ - uint32_t FAULT2EN : 1; /*!< [2] Fault Input 2 Enable */ - uint32_t FAULT3EN : 1; /*!< [3] Fault Input 3 Enable */ - uint32_t FFLTR0EN : 1; /*!< [4] Fault Input 0 Filter Enable */ - uint32_t FFLTR1EN : 1; /*!< [5] Fault Input 1 Filter Enable */ - uint32_t FFLTR2EN : 1; /*!< [6] Fault Input 2 Filter Enable */ - uint32_t FFLTR3EN : 1; /*!< [7] Fault Input 3 Filter Enable */ - uint32_t FFVAL : 4; /*!< [11:8] Fault Input Filter */ - uint32_t RESERVED0 : 20; /*!< [31:12] */ - } B; -} hw_ftm_fltctrl_t; - -/*! - * @name Constants and macros for entire FTM_FLTCTRL register - */ -/*@{*/ -#define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU) - -#define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x)) -#define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U) -#define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v)) -#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v))) -#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v))) -#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FLTCTRL bitfields - */ - -/*! - * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */ -#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */ -#define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */ -#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */ -#define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN) - -/*! @brief Set the FAULT0EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */ -#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */ -#define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */ -#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */ -#define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN) - -/*! @brief Set the FAULT1EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */ -#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */ -#define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */ -#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */ -#define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN) - -/*! @brief Set the FAULT2EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW) - * - * Enables the fault input. This field is write protected. It can be written - * only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input is disabled. - * - 1 - Fault input is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */ -#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */ -#define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */ -#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */ -#define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN) - -/*! @brief Set the FAULT3EN field to a new value. */ -#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */ -#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */ -#define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */ -#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */ -#define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN) - -/*! @brief Set the FFLTR0EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */ -#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */ -#define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */ -#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */ -#define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN) - -/*! @brief Set the FFLTR1EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */ -#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */ -#define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */ -#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */ -#define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN) - -/*! @brief Set the FFLTR2EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW) - * - * Enables the filter for the fault input. This field is write protected. It can - * be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Fault input filter is disabled. - * - 1 - Fault input filter is enabled. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */ -#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */ -#define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */ -#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN)) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */ -#define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN) - -/*! @brief Set the FFLTR3EN field to a new value. */ -#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW) - * - * Selects the filter value for the fault inputs. The fault filter is disabled - * when the value is zero. Writing to this field has immediate effect and must be - * done only when the fault control or all fault inputs are disabled. Failure to - * do this could result in a missing fault detection. - */ -/*@{*/ -#define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */ -#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */ -#define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */ - -/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */ -#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL) - -/*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */ -#define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL) - -/*! @brief Set the FFVAL field to a new value. */ -#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v))) -/*@}*/ - -/******************************************************************************* - * HW_FTM_QDCTRL - Quadrature Decoder Control And Status - ******************************************************************************/ - -/*! - * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW) - * - * Reset value: 0x00000000U - * - * This register has the control and status bits for the Quadrature Decoder mode. - */ -typedef union _hw_ftm_qdctrl -{ - uint32_t U; - struct _hw_ftm_qdctrl_bitfields - { - uint32_t QUADEN : 1; /*!< [0] Quadrature Decoder Mode Enable */ - uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature - * Decoder Mode */ - uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature - * Decoder Mode */ - uint32_t QUADMODE : 1; /*!< [3] Quadrature Decoder Mode */ - uint32_t PHBPOL : 1; /*!< [4] Phase B Input Polarity */ - uint32_t PHAPOL : 1; /*!< [5] Phase A Input Polarity */ - uint32_t PHBFLTREN : 1; /*!< [6] Phase B Input Filter Enable */ - uint32_t PHAFLTREN : 1; /*!< [7] Phase A Input Filter Enable */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_ftm_qdctrl_t; - -/*! - * @name Constants and macros for entire FTM_QDCTRL register - */ -/*@{*/ -#define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U) - -#define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x)) -#define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U) -#define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v)) -#define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v))) -#define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v))) -#define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_QDCTRL bitfields - */ - -/*! - * @name Register FTM_QDCTRL, field QUADEN[0] (RW) - * - * Enables the Quadrature Decoder mode. In this mode, the phase A and B input - * signals control the FTM counter direction. The Quadrature Decoder mode has - * precedence over the other modes. See #ModeSel1Table. This field is write protected. - * It can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - Quadrature Decoder mode is disabled. - * - 1 - Quadrature Decoder mode is enabled. - */ -/*@{*/ -#define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */ -#define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */ -#define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */ - -/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */ -#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN)) - -/*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */ -#define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN) - -/*! @brief Set the QUADEN field to a new value. */ -#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field TOFDIR[1] (RO) - * - * Indicates if the TOF bit was set on the top or the bottom of counting. - * - * Values: - * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter - * decrement and FTM counter changes from its minimum value (CNTIN register) to - * its maximum value (MOD register). - * - 1 - TOF bit was set on the top of counting. There was an FTM counter - * increment and FTM counter changes from its maximum value (MOD register) to its - * minimum value (CNTIN register). - */ -/*@{*/ -#define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */ -#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */ -#define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */ - -/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */ -#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field QUADIR[2] (RO) - * - * Indicates the counting direction. - * - * Values: - * - 0 - Counting direction is decreasing (FTM counter decrement). - * - 1 - Counting direction is increasing (FTM counter increment). - */ -/*@{*/ -#define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */ -#define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */ -#define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */ - -/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */ -#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field QUADMODE[3] (RW) - * - * Selects the encoding mode used in the Quadrature Decoder mode. - * - * Values: - * - 0 - Phase A and phase B encoding mode. - * - 1 - Count and direction encoding mode. - */ -/*@{*/ -#define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */ -#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */ -#define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */ - -/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */ -#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE)) - -/*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */ -#define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE) - -/*! @brief Set the QUADMODE field to a new value. */ -#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHBPOL[4] (RW) - * - * Selects the polarity for the quadrature decoder phase B input. - * - * Values: - * - 0 - Normal polarity. Phase B input signal is not inverted before - * identifying the rising and falling edges of this signal. - * - 1 - Inverted polarity. Phase B input signal is inverted before identifying - * the rising and falling edges of this signal. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */ -#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */ -#define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */ -#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */ -#define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL) - -/*! @brief Set the PHBPOL field to a new value. */ -#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHAPOL[5] (RW) - * - * Selects the polarity for the quadrature decoder phase A input. - * - * Values: - * - 0 - Normal polarity. Phase A input signal is not inverted before - * identifying the rising and falling edges of this signal. - * - 1 - Inverted polarity. Phase A input signal is inverted before identifying - * the rising and falling edges of this signal. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */ -#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */ -#define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */ -#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */ -#define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL) - -/*! @brief Set the PHAPOL field to a new value. */ -#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW) - * - * Enables the filter for the quadrature decoder phase B input. The filter value - * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B - * filter is also disabled when CH1FVAL is zero. - * - * Values: - * - 0 - Phase B input filter is disabled. - * - 1 - Phase B input filter is enabled. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */ -#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */ -#define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */ -#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */ -#define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN) - -/*! @brief Set the PHBFLTREN field to a new value. */ -#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW) - * - * Enables the filter for the quadrature decoder phase A input. The filter value - * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A - * filter is also disabled when CH0FVAL is zero. - * - * Values: - * - 0 - Phase A input filter is disabled. - * - 1 - Phase A input filter is enabled. - */ -/*@{*/ -#define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */ -#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */ -#define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */ - -/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */ -#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN)) - -/*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */ -#define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN) - -/*! @brief Set the PHAFLTREN field to a new value. */ -#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_CONF - Configuration - ******************************************************************************/ - -/*! - * @brief HW_FTM_CONF - Configuration (RW) - * - * Reset value: 0x00000000U - * - * This register selects the number of times that the FTM counter overflow - * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use - * of an external global time base, and the global time base signal generation. - */ -typedef union _hw_ftm_conf -{ - uint32_t U; - struct _hw_ftm_conf_bitfields - { - uint32_t NUMTOF : 5; /*!< [4:0] TOF Frequency */ - uint32_t RESERVED0 : 1; /*!< [5] */ - uint32_t BDMMODE : 2; /*!< [7:6] BDM Mode */ - uint32_t RESERVED1 : 1; /*!< [8] */ - uint32_t GTBEEN : 1; /*!< [9] Global Time Base Enable */ - uint32_t GTBEOUT : 1; /*!< [10] Global Time Base Output */ - uint32_t RESERVED2 : 21; /*!< [31:11] */ - } B; -} hw_ftm_conf_t; - -/*! - * @name Constants and macros for entire FTM_CONF register - */ -/*@{*/ -#define HW_FTM_CONF_ADDR(x) ((x) + 0x84U) - -#define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x)) -#define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U) -#define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v)) -#define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v))) -#define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v))) -#define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_CONF bitfields - */ - -/*! - * @name Register FTM_CONF, field NUMTOF[4:0] (RW) - * - * Selects the ratio between the number of counter overflows to the number of - * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter - * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for - * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter - * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the - * first counter overflow but not for the next 3 overflows. This pattern continues - * up to a maximum of 31. - */ -/*@{*/ -#define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */ -#define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */ -#define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */ - -/*! @brief Read current value of the FTM_CONF_NUMTOF field. */ -#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF) - -/*! @brief Format value for bitfield FTM_CONF_NUMTOF. */ -#define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF) - -/*! @brief Set the NUMTOF field to a new value. */ -#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v))) -/*@}*/ - -/*! - * @name Register FTM_CONF, field BDMMODE[7:6] (RW) - * - * Selects the FTM behavior in BDM mode. See BDM mode. - */ -/*@{*/ -#define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */ -#define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */ -#define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */ - -/*! @brief Read current value of the FTM_CONF_BDMMODE field. */ -#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE) - -/*! @brief Format value for bitfield FTM_CONF_BDMMODE. */ -#define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE) - -/*! @brief Set the BDMMODE field to a new value. */ -#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v))) -/*@}*/ - -/*! - * @name Register FTM_CONF, field GTBEEN[9] (RW) - * - * Configures the FTM to use an external global time base signal that is - * generated by another FTM. - * - * Values: - * - 0 - Use of an external global time base is disabled. - * - 1 - Use of an external global time base is enabled. - */ -/*@{*/ -#define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */ -#define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */ -#define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */ - -/*! @brief Read current value of the FTM_CONF_GTBEEN field. */ -#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN)) - -/*! @brief Format value for bitfield FTM_CONF_GTBEEN. */ -#define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN) - -/*! @brief Set the GTBEEN field to a new value. */ -#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_CONF, field GTBEOUT[10] (RW) - * - * Enables the global time base signal generation to other FTMs. - * - * Values: - * - 0 - A global time base signal generation is disabled. - * - 1 - A global time base signal generation is enabled. - */ -/*@{*/ -#define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */ -#define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */ -#define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */ - -/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */ -#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT)) - -/*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */ -#define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT) - -/*! @brief Set the GTBEOUT field to a new value. */ -#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_FLTPOL - FTM Fault Input Polarity - ******************************************************************************/ - -/*! - * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW) - * - * Reset value: 0x00000000U - * - * This register defines the fault inputs polarity. - */ -typedef union _hw_ftm_fltpol -{ - uint32_t U; - struct _hw_ftm_fltpol_bitfields - { - uint32_t FLT0POL : 1; /*!< [0] Fault Input 0 Polarity */ - uint32_t FLT1POL : 1; /*!< [1] Fault Input 1 Polarity */ - uint32_t FLT2POL : 1; /*!< [2] Fault Input 2 Polarity */ - uint32_t FLT3POL : 1; /*!< [3] Fault Input 3 Polarity */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_ftm_fltpol_t; - -/*! - * @name Constants and macros for entire FTM_FLTPOL register - */ -/*@{*/ -#define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U) - -#define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x)) -#define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U) -#define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v)) -#define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v))) -#define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v))) -#define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_FLTPOL bitfields - */ - -/*! - * @name Register FTM_FLTPOL, field FLT0POL[0] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */ -#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */ -#define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */ -#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */ -#define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL) - -/*! @brief Set the FLT0POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTPOL, field FLT1POL[1] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */ -#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */ -#define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */ -#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */ -#define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL) - -/*! @brief Set the FLT1POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTPOL, field FLT2POL[2] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */ -#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */ -#define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */ -#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */ -#define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL) - -/*! @brief Set the FLT2POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_FLTPOL, field FLT3POL[3] (RW) - * - * Defines the polarity of the fault input. This field is write protected. It - * can be written only when MODE[WPDIS] = 1. - * - * Values: - * - 0 - The fault input polarity is active high. A 1 at the fault input - * indicates a fault. - * - 1 - The fault input polarity is active low. A 0 at the fault input - * indicates a fault. - */ -/*@{*/ -#define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */ -#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */ -#define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */ - -/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */ -#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL)) - -/*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */ -#define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL) - -/*! @brief Set the FLT3POL field to a new value. */ -#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_SYNCONF - Synchronization Configuration - ******************************************************************************/ - -/*! - * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW) - * - * Reset value: 0x00000000U - * - * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL - * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = - * 0, 1, 2, when the hardware trigger j is detected. - */ -typedef union _hw_ftm_synconf -{ - uint32_t U; - struct _hw_ftm_synconf_bitfields - { - uint32_t HWTRIGMODE : 1; /*!< [0] Hardware Trigger Mode */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t CNTINC : 1; /*!< [2] CNTIN Register Synchronization */ - uint32_t RESERVED1 : 1; /*!< [3] */ - uint32_t INVC : 1; /*!< [4] INVCTRL Register Synchronization */ - uint32_t SWOC : 1; /*!< [5] SWOCTRL Register Synchronization */ - uint32_t RESERVED2 : 1; /*!< [6] */ - uint32_t SYNCMODE : 1; /*!< [7] Synchronization Mode */ - uint32_t SWRSTCNT : 1; /*!< [8] */ - uint32_t SWWRBUF : 1; /*!< [9] */ - uint32_t SWOM : 1; /*!< [10] */ - uint32_t SWINVC : 1; /*!< [11] */ - uint32_t SWSOC : 1; /*!< [12] */ - uint32_t RESERVED3 : 3; /*!< [15:13] */ - uint32_t HWRSTCNT : 1; /*!< [16] */ - uint32_t HWWRBUF : 1; /*!< [17] */ - uint32_t HWOM : 1; /*!< [18] */ - uint32_t HWINVC : 1; /*!< [19] */ - uint32_t HWSOC : 1; /*!< [20] */ - uint32_t RESERVED4 : 11; /*!< [31:21] */ - } B; -} hw_ftm_synconf_t; - -/*! - * @name Constants and macros for entire FTM_SYNCONF register - */ -/*@{*/ -#define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU) - -#define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x)) -#define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U) -#define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v)) -#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v))) -#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v))) -#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SYNCONF bitfields - */ - -/*! - * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW) - * - * Values: - * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where - * j = 0, 1,2. - * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is - * detected, where j = 0, 1,2. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */ -#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */ -#define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */ -#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */ -#define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE) - -/*! @brief Set the HWTRIGMODE field to a new value. */ -#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field CNTINC[2] (RW) - * - * Values: - * - 0 - CNTIN register is updated with its buffer value at all rising edges of - * system clock. - * - 1 - CNTIN register is updated with its buffer value by the PWM - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */ -#define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */ -#define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */ - -/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */ -#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */ -#define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC) - -/*! @brief Set the CNTINC field to a new value. */ -#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field INVC[4] (RW) - * - * Values: - * - 0 - INVCTRL register is updated with its buffer value at all rising edges - * of system clock. - * - 1 - INVCTRL register is updated with its buffer value by the PWM - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */ -#define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */ -#define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */ - -/*! @brief Read current value of the FTM_SYNCONF_INVC field. */ -#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_INVC. */ -#define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC) - -/*! @brief Set the INVC field to a new value. */ -#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWOC[5] (RW) - * - * Values: - * - 0 - SWOCTRL register is updated with its buffer value at all rising edges - * of system clock. - * - 1 - SWOCTRL register is updated with its buffer value by the PWM - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */ -#define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */ -#define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */ -#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */ -#define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC) - -/*! @brief Set the SWOC field to a new value. */ -#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW) - * - * Selects the PWM Synchronization mode. - * - * Values: - * - 0 - Legacy PWM synchronization is selected. - * - 1 - Enhanced PWM synchronization is selected. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */ -#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */ -#define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */ - -/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */ -#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */ -#define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE) - -/*! @brief Set the SYNCMODE field to a new value. */ -#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW) - * - * FTM counter synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the FTM counter synchronization. - * - 1 - The software trigger activates the FTM counter synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */ -#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */ -#define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */ -#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */ -#define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT) - -/*! @brief Set the SWRSTCNT field to a new value. */ -#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW) - * - * MOD, CNTIN, and CV registers synchronization is activated by the software - * trigger. - * - * Values: - * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers - * synchronization. - * - 1 - The software trigger activates MOD, CNTIN, and CV registers - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */ -#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */ -#define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */ -#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */ -#define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF) - -/*! @brief Set the SWWRBUF field to a new value. */ -#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWOM[10] (RW) - * - * Output mask synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the OUTMASK register - * synchronization. - * - 1 - The software trigger activates the OUTMASK register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */ -#define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */ -#define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */ -#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */ -#define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM) - -/*! @brief Set the SWOM field to a new value. */ -#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWINVC[11] (RW) - * - * Inverting control synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the INVCTRL register - * synchronization. - * - 1 - The software trigger activates the INVCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */ -#define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */ -#define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */ -#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */ -#define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC) - -/*! @brief Set the SWINVC field to a new value. */ -#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field SWSOC[12] (RW) - * - * Software output control synchronization is activated by the software trigger. - * - * Values: - * - 0 - The software trigger does not activate the SWOCTRL register - * synchronization. - * - 1 - The software trigger activates the SWOCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */ -#define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */ -#define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */ - -/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */ -#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */ -#define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC) - -/*! @brief Set the SWSOC field to a new value. */ -#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW) - * - * FTM counter synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the FTM counter synchronization. - * - 1 - A hardware trigger activates the FTM counter synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */ -#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */ -#define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */ -#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */ -#define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT) - -/*! @brief Set the HWRSTCNT field to a new value. */ -#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW) - * - * MOD, CNTIN, and CV registers synchronization is activated by a hardware - * trigger. - * - * Values: - * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers - * synchronization. - * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers - * synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */ -#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */ -#define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */ -#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */ -#define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF) - -/*! @brief Set the HWWRBUF field to a new value. */ -#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWOM[18] (RW) - * - * Output mask synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the OUTMASK register - * synchronization. - * - 1 - A hardware trigger activates the OUTMASK register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */ -#define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */ -#define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */ -#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */ -#define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM) - -/*! @brief Set the HWOM field to a new value. */ -#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWINVC[19] (RW) - * - * Inverting control synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the INVCTRL register - * synchronization. - * - 1 - A hardware trigger activates the INVCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */ -#define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */ -#define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */ -#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */ -#define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC) - -/*! @brief Set the HWINVC field to a new value. */ -#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SYNCONF, field HWSOC[20] (RW) - * - * Software output control synchronization is activated by a hardware trigger. - * - * Values: - * - 0 - A hardware trigger does not activate the SWOCTRL register - * synchronization. - * - 1 - A hardware trigger activates the SWOCTRL register synchronization. - */ -/*@{*/ -#define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */ -#define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */ -#define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */ - -/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */ -#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC)) - -/*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */ -#define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC) - -/*! @brief Set the HWSOC field to a new value. */ -#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_INVCTRL - FTM Inverting Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW) - * - * Reset value: 0x00000000U - * - * This register controls when the channel (n) output becomes the channel (n+1) - * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN - * bit enables the inverting operation for the corresponding pair channels m. This - * register has a write buffer. The INVmEN bit is updated by the INVCTRL - * register synchronization. - */ -typedef union _hw_ftm_invctrl -{ - uint32_t U; - struct _hw_ftm_invctrl_bitfields - { - uint32_t INV0EN : 1; /*!< [0] Pair Channels 0 Inverting Enable */ - uint32_t INV1EN : 1; /*!< [1] Pair Channels 1 Inverting Enable */ - uint32_t INV2EN : 1; /*!< [2] Pair Channels 2 Inverting Enable */ - uint32_t INV3EN : 1; /*!< [3] Pair Channels 3 Inverting Enable */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_ftm_invctrl_t; - -/*! - * @name Constants and macros for entire FTM_INVCTRL register - */ -/*@{*/ -#define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U) - -#define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x)) -#define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U) -#define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v)) -#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v))) -#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v))) -#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_INVCTRL bitfields - */ - -/*! - * @name Register FTM_INVCTRL, field INV0EN[0] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */ -#define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */ -#define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */ -#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */ -#define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN) - -/*! @brief Set the INV0EN field to a new value. */ -#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_INVCTRL, field INV1EN[1] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */ -#define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */ -#define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */ -#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */ -#define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN) - -/*! @brief Set the INV1EN field to a new value. */ -#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_INVCTRL, field INV2EN[2] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */ -#define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */ -#define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */ -#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */ -#define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN) - -/*! @brief Set the INV2EN field to a new value. */ -#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v)) -/*@}*/ - -/*! - * @name Register FTM_INVCTRL, field INV3EN[3] (RW) - * - * Values: - * - 0 - Inverting is disabled. - * - 1 - Inverting is enabled. - */ -/*@{*/ -#define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */ -#define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */ -#define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */ - -/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */ -#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN)) - -/*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */ -#define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN) - -/*! @brief Set the INV3EN field to a new value. */ -#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_SWOCTRL - FTM Software Output Control - ******************************************************************************/ - -/*! - * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW) - * - * Reset value: 0x00000000U - * - * This register enables software control of channel (n) output and defines the - * value forced to the channel (n) output: The CHnOC bits enable the control of - * the corresponding channel (n) output by software. The CHnOCV bits select the - * value that is forced at the corresponding channel (n) output. This register has - * a write buffer. The fields are updated by the SWOCTRL register synchronization. - */ -typedef union _hw_ftm_swoctrl -{ - uint32_t U; - struct _hw_ftm_swoctrl_bitfields - { - uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable - * */ - uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable - * */ - uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable - * */ - uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable - * */ - uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable - * */ - uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable - * */ - uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable - * */ - uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable - * */ - uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value - * */ - uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value - * */ - uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control - * Value */ - uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control - * Value */ - uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control - * Value */ - uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control - * Value */ - uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control - * Value */ - uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control - * Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_ftm_swoctrl_t; - -/*! - * @name Constants and macros for entire FTM_SWOCTRL register - */ -/*@{*/ -#define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U) - -#define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x)) -#define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U) -#define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v)) -#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v))) -#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v))) -#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_SWOCTRL bitfields - */ - -/*! - * @name Register FTM_SWOCTRL, field CH0OC[0] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */ -#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */ -#define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */ -#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */ -#define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC) - -/*! @brief Set the CH0OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH1OC[1] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */ -#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */ -#define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */ -#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */ -#define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC) - -/*! @brief Set the CH1OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH2OC[2] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */ -#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */ -#define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */ -#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */ -#define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC) - -/*! @brief Set the CH2OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH3OC[3] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */ -#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */ -#define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */ -#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */ -#define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC) - -/*! @brief Set the CH3OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH4OC[4] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */ -#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */ -#define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */ -#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */ -#define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC) - -/*! @brief Set the CH4OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH5OC[5] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */ -#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */ -#define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */ -#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */ -#define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC) - -/*! @brief Set the CH5OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH6OC[6] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */ -#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */ -#define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */ -#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */ -#define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC) - -/*! @brief Set the CH6OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH7OC[7] (RW) - * - * Values: - * - 0 - The channel output is not affected by software output control. - * - 1 - The channel output is affected by software output control. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */ -#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */ -#define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */ -#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */ -#define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC) - -/*! @brief Set the CH7OC field to a new value. */ -#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */ -#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */ -#define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */ -#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */ -#define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV) - -/*! @brief Set the CH0OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */ -#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */ -#define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */ -#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */ -#define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV) - -/*! @brief Set the CH1OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */ -#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */ -#define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */ -#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */ -#define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV) - -/*! @brief Set the CH2OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */ -#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */ -#define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */ -#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */ -#define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV) - -/*! @brief Set the CH3OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */ -#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */ -#define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */ -#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */ -#define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV) - -/*! @brief Set the CH4OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */ -#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */ -#define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */ -#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */ -#define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV) - -/*! @brief Set the CH5OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */ -#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */ -#define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */ -#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */ -#define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV) - -/*! @brief Set the CH6OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v)) -/*@}*/ - -/*! - * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW) - * - * Values: - * - 0 - The software output control forces 0 to the channel output. - * - 1 - The software output control forces 1 to the channel output. - */ -/*@{*/ -#define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */ -#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */ -#define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */ - -/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */ -#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV)) - -/*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */ -#define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV) - -/*! @brief Set the CH7OCV field to a new value. */ -#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_FTM_PWMLOAD - FTM PWM Load - ******************************************************************************/ - -/*! - * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW) - * - * Reset value: 0x00000000U - * - * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the - * values of their write buffers when the FTM counter changes from the MOD - * register value to its next value or when a channel (j) match occurs. A match occurs - * for the channel (j) when FTM counter = C(j)V. - */ -typedef union _hw_ftm_pwmload -{ - uint32_t U; - struct _hw_ftm_pwmload_bitfields - { - uint32_t CH0SEL : 1; /*!< [0] Channel 0 Select */ - uint32_t CH1SEL : 1; /*!< [1] Channel 1 Select */ - uint32_t CH2SEL : 1; /*!< [2] Channel 2 Select */ - uint32_t CH3SEL : 1; /*!< [3] Channel 3 Select */ - uint32_t CH4SEL : 1; /*!< [4] Channel 4 Select */ - uint32_t CH5SEL : 1; /*!< [5] Channel 5 Select */ - uint32_t CH6SEL : 1; /*!< [6] Channel 6 Select */ - uint32_t CH7SEL : 1; /*!< [7] Channel 7 Select */ - uint32_t RESERVED0 : 1; /*!< [8] */ - uint32_t LDOK : 1; /*!< [9] Load Enable */ - uint32_t RESERVED1 : 22; /*!< [31:10] */ - } B; -} hw_ftm_pwmload_t; - -/*! - * @name Constants and macros for entire FTM_PWMLOAD register - */ -/*@{*/ -#define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U) - -#define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x)) -#define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U) -#define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v)) -#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v))) -#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v))) -#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual FTM_PWMLOAD bitfields - */ - -/*! - * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */ -#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */ -#define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */ -#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */ -#define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL) - -/*! @brief Set the CH0SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */ -#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */ -#define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */ -#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */ -#define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL) - -/*! @brief Set the CH1SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */ -#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */ -#define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */ -#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */ -#define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL) - -/*! @brief Set the CH2SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */ -#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */ -#define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */ -#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */ -#define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL) - -/*! @brief Set the CH3SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */ -#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */ -#define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */ -#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */ -#define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL) - -/*! @brief Set the CH4SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */ -#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */ -#define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */ -#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */ -#define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL) - -/*! @brief Set the CH5SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */ -#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */ -#define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */ -#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */ -#define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL) - -/*! @brief Set the CH6SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW) - * - * Values: - * - 0 - Do not include the channel in the matching process. - * - 1 - Include the channel in the matching process. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */ -#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */ -#define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */ - -/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */ -#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */ -#define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL) - -/*! @brief Set the CH7SEL field to a new value. */ -#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v)) -/*@}*/ - -/*! - * @name Register FTM_PWMLOAD, field LDOK[9] (RW) - * - * Enables the loading of the MOD, CNTIN, and CV registers with the values of - * their write buffers. - * - * Values: - * - 0 - Loading updated values is disabled. - * - 1 - Loading updated values is enabled. - */ -/*@{*/ -#define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */ -#define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */ -#define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */ - -/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */ -#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK)) - -/*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */ -#define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK) - -/*! @brief Set the LDOK field to a new value. */ -#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_ftm_t - module struct - ******************************************************************************/ -/*! - * @brief All FTM module registers. - */ -#pragma pack(1) -typedef struct _hw_ftm -{ - __IO hw_ftm_sc_t SC; /*!< [0x0] Status And Control */ - __IO hw_ftm_cnt_t CNT; /*!< [0x4] Counter */ - __IO hw_ftm_mod_t MOD; /*!< [0x8] Modulo */ - struct { - __IO hw_ftm_cnsc_t CnSC; /*!< [0xC] Channel (n) Status And Control */ - __IO hw_ftm_cnv_t CnV; /*!< [0x10] Channel (n) Value */ - } CONTROLS[8]; - __IO hw_ftm_cntin_t CNTIN; /*!< [0x4C] Counter Initial Value */ - __IO hw_ftm_status_t STATUS; /*!< [0x50] Capture And Compare Status */ - __IO hw_ftm_mode_t MODE; /*!< [0x54] Features Mode Selection */ - __IO hw_ftm_sync_t SYNC; /*!< [0x58] Synchronization */ - __IO hw_ftm_outinit_t OUTINIT; /*!< [0x5C] Initial State For Channels Output */ - __IO hw_ftm_outmask_t OUTMASK; /*!< [0x60] Output Mask */ - __IO hw_ftm_combine_t COMBINE; /*!< [0x64] Function For Linked Channels */ - __IO hw_ftm_deadtime_t DEADTIME; /*!< [0x68] Deadtime Insertion Control */ - __IO hw_ftm_exttrig_t EXTTRIG; /*!< [0x6C] FTM External Trigger */ - __IO hw_ftm_pol_t POL; /*!< [0x70] Channels Polarity */ - __IO hw_ftm_fms_t FMS; /*!< [0x74] Fault Mode Status */ - __IO hw_ftm_filter_t FILTER; /*!< [0x78] Input Capture Filter Control */ - __IO hw_ftm_fltctrl_t FLTCTRL; /*!< [0x7C] Fault Control */ - __IO hw_ftm_qdctrl_t QDCTRL; /*!< [0x80] Quadrature Decoder Control And Status */ - __IO hw_ftm_conf_t CONF; /*!< [0x84] Configuration */ - __IO hw_ftm_fltpol_t FLTPOL; /*!< [0x88] FTM Fault Input Polarity */ - __IO hw_ftm_synconf_t SYNCONF; /*!< [0x8C] Synchronization Configuration */ - __IO hw_ftm_invctrl_t INVCTRL; /*!< [0x90] FTM Inverting Control */ - __IO hw_ftm_swoctrl_t SWOCTRL; /*!< [0x94] FTM Software Output Control */ - __IO hw_ftm_pwmload_t PWMLOAD; /*!< [0x98] FTM PWM Load */ -} hw_ftm_t; -#pragma pack() - -/*! @brief Macro to access all FTM registers. */ -/*! @param x FTM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_FTM(FTM0_BASE). */ -#define HW_FTM(x) (*(hw_ftm_t *)(x)) - -#endif /* __HW_FTM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_gpio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_gpio.h deleted file mode 100644 index 906ba390f9f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_gpio.h +++ /dev/null @@ -1,490 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_GPIO_REGISTERS_H__ -#define __HW_GPIO_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 GPIO - * - * General Purpose Input/Output - * - * Registers defined in this header file: - * - HW_GPIO_PDOR - Port Data Output Register - * - HW_GPIO_PSOR - Port Set Output Register - * - HW_GPIO_PCOR - Port Clear Output Register - * - HW_GPIO_PTOR - Port Toggle Output Register - * - HW_GPIO_PDIR - Port Data Input Register - * - HW_GPIO_PDDR - Port Data Direction Register - * - * - hw_gpio_t - Struct containing all module registers. - */ - -#define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */ -#define HW_GPIOA (0U) /*!< Instance number for GPIOA. */ -#define HW_GPIOB (1U) /*!< Instance number for GPIOB. */ -#define HW_GPIOC (2U) /*!< Instance number for GPIOC. */ -#define HW_GPIOD (3U) /*!< Instance number for GPIOD. */ -#define HW_GPIOE (4U) /*!< Instance number for GPIOE. */ - -/******************************************************************************* - * HW_GPIO_PDOR - Port Data Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PDOR - Port Data Output Register (RW) - * - * Reset value: 0x00000000U - * - * This register configures the logic levels that are driven on each - * general-purpose output pins. Do not modify pin configuration registers associated with - * pins not available in your selected package. All unbonded pins not available in - * your package will default to DISABLE state for lowest power consumption. - */ -typedef union _hw_gpio_pdor -{ - uint32_t U; - struct _hw_gpio_pdor_bitfields - { - uint32_t PDO : 32; /*!< [31:0] Port Data Output */ - } B; -} hw_gpio_pdor_t; - -/*! - * @name Constants and macros for entire GPIO_PDOR register - */ -/*@{*/ -#define HW_GPIO_PDOR_ADDR(x) ((x) + 0x0U) - -#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x)) -#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U) -#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v)) -#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v))) -#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v))) -#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PDOR bitfields - */ - -/*! - * @name Register GPIO_PDOR, field PDO[31:0] (RW) - * - * Register bits for unbonded pins return a undefined value when read. - * - * Values: - * - 0 - Logic level 0 is driven on pin, provided pin is configured for - * general-purpose output. - * - 1 - Logic level 1 is driven on pin, provided pin is configured for - * general-purpose output. - */ -/*@{*/ -#define BP_GPIO_PDOR_PDO (0U) /*!< Bit position for GPIO_PDOR_PDO. */ -#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */ -#define BS_GPIO_PDOR_PDO (32U) /*!< Bit field size in bits for GPIO_PDOR_PDO. */ - -/*! @brief Read current value of the GPIO_PDOR_PDO field. */ -#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U) - -/*! @brief Format value for bitfield GPIO_PDOR_PDO. */ -#define BF_GPIO_PDOR_PDO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO) - -/*! @brief Set the PDO field to a new value. */ -#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PSOR - Port Set Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ) - * - * Reset value: 0x00000000U - * - * This register configures whether to set the fields of the PDOR. - */ -typedef union _hw_gpio_psor -{ - uint32_t U; - struct _hw_gpio_psor_bitfields - { - uint32_t PTSO : 32; /*!< [31:0] Port Set Output */ - } B; -} hw_gpio_psor_t; - -/*! - * @name Constants and macros for entire GPIO_PSOR register - */ -/*@{*/ -#define HW_GPIO_PSOR_ADDR(x) ((x) + 0x4U) - -#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x)) -#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U) -#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PSOR bitfields - */ - -/*! - * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ) - * - * Writing to this register will update the contents of the corresponding bit in - * the PDOR as follows: - * - * Values: - * - 0 - Corresponding bit in PDORn does not change. - * - 1 - Corresponding bit in PDORn is set to logic 1. - */ -/*@{*/ -#define BP_GPIO_PSOR_PTSO (0U) /*!< Bit position for GPIO_PSOR_PTSO. */ -#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */ -#define BS_GPIO_PSOR_PTSO (32U) /*!< Bit field size in bits for GPIO_PSOR_PTSO. */ - -/*! @brief Format value for bitfield GPIO_PSOR_PTSO. */ -#define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO) - -/*! @brief Set the PTSO field to a new value. */ -#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PCOR - Port Clear Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ) - * - * Reset value: 0x00000000U - * - * This register configures whether to clear the fields of PDOR. - */ -typedef union _hw_gpio_pcor -{ - uint32_t U; - struct _hw_gpio_pcor_bitfields - { - uint32_t PTCO : 32; /*!< [31:0] Port Clear Output */ - } B; -} hw_gpio_pcor_t; - -/*! - * @name Constants and macros for entire GPIO_PCOR register - */ -/*@{*/ -#define HW_GPIO_PCOR_ADDR(x) ((x) + 0x8U) - -#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x)) -#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U) -#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PCOR bitfields - */ - -/*! - * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ) - * - * Writing to this register will update the contents of the corresponding bit in - * the Port Data Output Register (PDOR) as follows: - * - * Values: - * - 0 - Corresponding bit in PDORn does not change. - * - 1 - Corresponding bit in PDORn is cleared to logic 0. - */ -/*@{*/ -#define BP_GPIO_PCOR_PTCO (0U) /*!< Bit position for GPIO_PCOR_PTCO. */ -#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */ -#define BS_GPIO_PCOR_PTCO (32U) /*!< Bit field size in bits for GPIO_PCOR_PTCO. */ - -/*! @brief Format value for bitfield GPIO_PCOR_PTCO. */ -#define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO) - -/*! @brief Set the PTCO field to a new value. */ -#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PTOR - Port Toggle Output Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ) - * - * Reset value: 0x00000000U - */ -typedef union _hw_gpio_ptor -{ - uint32_t U; - struct _hw_gpio_ptor_bitfields - { - uint32_t PTTO : 32; /*!< [31:0] Port Toggle Output */ - } B; -} hw_gpio_ptor_t; - -/*! - * @name Constants and macros for entire GPIO_PTOR register - */ -/*@{*/ -#define HW_GPIO_PTOR_ADDR(x) ((x) + 0xCU) - -#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x)) -#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U) -#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PTOR bitfields - */ - -/*! - * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ) - * - * Writing to this register will update the contents of the corresponding bit in - * the PDOR as follows: - * - * Values: - * - 0 - Corresponding bit in PDORn does not change. - * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic - * state. - */ -/*@{*/ -#define BP_GPIO_PTOR_PTTO (0U) /*!< Bit position for GPIO_PTOR_PTTO. */ -#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */ -#define BS_GPIO_PTOR_PTTO (32U) /*!< Bit field size in bits for GPIO_PTOR_PTTO. */ - -/*! @brief Format value for bitfield GPIO_PTOR_PTTO. */ -#define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO) - -/*! @brief Set the PTTO field to a new value. */ -#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PDIR - Port Data Input Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PDIR - Port Data Input Register (RO) - * - * Reset value: 0x00000000U - * - * Do not modify pin configuration registers associated with pins not available - * in your selected package. All unbonded pins not available in your package will - * default to DISABLE state for lowest power consumption. - */ -typedef union _hw_gpio_pdir -{ - uint32_t U; - struct _hw_gpio_pdir_bitfields - { - uint32_t PDI : 32; /*!< [31:0] Port Data Input */ - } B; -} hw_gpio_pdir_t; - -/*! - * @name Constants and macros for entire GPIO_PDIR register - */ -/*@{*/ -#define HW_GPIO_PDIR_ADDR(x) ((x) + 0x10U) - -#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x)) -#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PDIR bitfields - */ - -/*! - * @name Register GPIO_PDIR, field PDI[31:0] (RO) - * - * Reads 0 at the unimplemented pins for a particular device. Pins that are not - * configured for a digital function read 0. If the Port Control and Interrupt - * module is disabled, then the corresponding bit in PDIR does not update. - * - * Values: - * - 0 - Pin logic level is logic 0, or is not configured for use by digital - * function. - * - 1 - Pin logic level is logic 1. - */ -/*@{*/ -#define BP_GPIO_PDIR_PDI (0U) /*!< Bit position for GPIO_PDIR_PDI. */ -#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */ -#define BS_GPIO_PDIR_PDI (32U) /*!< Bit field size in bits for GPIO_PDIR_PDI. */ - -/*! @brief Read current value of the GPIO_PDIR_PDI field. */ -#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U) -/*@}*/ - -/******************************************************************************* - * HW_GPIO_PDDR - Port Data Direction Register - ******************************************************************************/ - -/*! - * @brief HW_GPIO_PDDR - Port Data Direction Register (RW) - * - * Reset value: 0x00000000U - * - * The PDDR configures the individual port pins for input or output. - */ -typedef union _hw_gpio_pddr -{ - uint32_t U; - struct _hw_gpio_pddr_bitfields - { - uint32_t PDD : 32; /*!< [31:0] Port Data Direction */ - } B; -} hw_gpio_pddr_t; - -/*! - * @name Constants and macros for entire GPIO_PDDR register - */ -/*@{*/ -#define HW_GPIO_PDDR_ADDR(x) ((x) + 0x14U) - -#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x)) -#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U) -#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v)) -#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v))) -#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v))) -#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual GPIO_PDDR bitfields - */ - -/*! - * @name Register GPIO_PDDR, field PDD[31:0] (RW) - * - * Configures individual port pins for input or output. - * - * Values: - * - 0 - Pin is configured as general-purpose input, for the GPIO function. - * - 1 - Pin is configured as general-purpose output, for the GPIO function. - */ -/*@{*/ -#define BP_GPIO_PDDR_PDD (0U) /*!< Bit position for GPIO_PDDR_PDD. */ -#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */ -#define BS_GPIO_PDDR_PDD (32U) /*!< Bit field size in bits for GPIO_PDDR_PDD. */ - -/*! @brief Read current value of the GPIO_PDDR_PDD field. */ -#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U) - -/*! @brief Format value for bitfield GPIO_PDDR_PDD. */ -#define BF_GPIO_PDDR_PDD(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD) - -/*! @brief Set the PDD field to a new value. */ -#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_gpio_t - module struct - ******************************************************************************/ -/*! - * @brief All GPIO module registers. - */ -#pragma pack(1) -typedef struct _hw_gpio -{ - __IO hw_gpio_pdor_t PDOR; /*!< [0x0] Port Data Output Register */ - __O hw_gpio_psor_t PSOR; /*!< [0x4] Port Set Output Register */ - __O hw_gpio_pcor_t PCOR; /*!< [0x8] Port Clear Output Register */ - __O hw_gpio_ptor_t PTOR; /*!< [0xC] Port Toggle Output Register */ - __I hw_gpio_pdir_t PDIR; /*!< [0x10] Port Data Input Register */ - __IO hw_gpio_pddr_t PDDR; /*!< [0x14] Port Data Direction Register */ -} hw_gpio_t; -#pragma pack() - -/*! @brief Macro to access all GPIO registers. */ -/*! @param x GPIO module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_GPIO(GPIOA_BASE). */ -#define HW_GPIO(x) (*(hw_gpio_t *)(x)) - -#endif /* __HW_GPIO_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2c.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2c.h deleted file mode 100644 index 50c59862b08..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2c.h +++ /dev/null @@ -1,1728 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_I2C_REGISTERS_H__ -#define __HW_I2C_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 I2C - * - * Inter-Integrated Circuit - * - * Registers defined in this header file: - * - HW_I2C_A1 - I2C Address Register 1 - * - HW_I2C_F - I2C Frequency Divider register - * - HW_I2C_C1 - I2C Control Register 1 - * - HW_I2C_S - I2C Status register - * - HW_I2C_D - I2C Data I/O register - * - HW_I2C_C2 - I2C Control Register 2 - * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register - * - HW_I2C_RA - I2C Range Address register - * - HW_I2C_SMB - I2C SMBus Control and Status register - * - HW_I2C_A2 - I2C Address Register 2 - * - HW_I2C_SLTH - I2C SCL Low Timeout Register High - * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low - * - * - hw_i2c_t - Struct containing all module registers. - */ - -#define HW_I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */ -#define HW_I2C0 (0U) /*!< Instance number for I2C0. */ -#define HW_I2C1 (1U) /*!< Instance number for I2C1. */ -#define HW_I2C2 (2U) /*!< Instance number for I2C2. */ - -/******************************************************************************* - * HW_I2C_A1 - I2C Address Register 1 - ******************************************************************************/ - -/*! - * @brief HW_I2C_A1 - I2C Address Register 1 (RW) - * - * Reset value: 0x00U - * - * This register contains the slave address to be used by the I2C module. - */ -typedef union _hw_i2c_a1 -{ - uint8_t U; - struct _hw_i2c_a1_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t AD : 7; /*!< [7:1] Address */ - } B; -} hw_i2c_a1_t; - -/*! - * @name Constants and macros for entire I2C_A1 register - */ -/*@{*/ -#define HW_I2C_A1_ADDR(x) ((x) + 0x0U) - -#define HW_I2C_A1(x) (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x)) -#define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U) -#define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v)) -#define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) | (v))) -#define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v))) -#define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_A1 bitfields - */ - -/*! - * @name Register I2C_A1, field AD[7:1] (RW) - * - * Contains the primary slave address used by the I2C module when it is - * addressed as a slave. This field is used in the 7-bit address scheme and the lower - * seven bits in the 10-bit address scheme. - */ -/*@{*/ -#define BP_I2C_A1_AD (1U) /*!< Bit position for I2C_A1_AD. */ -#define BM_I2C_A1_AD (0xFEU) /*!< Bit mask for I2C_A1_AD. */ -#define BS_I2C_A1_AD (7U) /*!< Bit field size in bits for I2C_A1_AD. */ - -/*! @brief Read current value of the I2C_A1_AD field. */ -#define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD) - -/*! @brief Format value for bitfield I2C_A1_AD. */ -#define BF_I2C_A1_AD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_A1_AD) & BM_I2C_A1_AD) - -/*! @brief Set the AD field to a new value. */ -#define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_F - I2C Frequency Divider register - ******************************************************************************/ - -/*! - * @brief HW_I2C_F - I2C Frequency Divider register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_f -{ - uint8_t U; - struct _hw_i2c_f_bitfields - { - uint8_t ICR : 6; /*!< [5:0] ClockRate */ - uint8_t MULT : 2; /*!< [7:6] Multiplier Factor */ - } B; -} hw_i2c_f_t; - -/*! - * @name Constants and macros for entire I2C_F register - */ -/*@{*/ -#define HW_I2C_F_ADDR(x) ((x) + 0x1U) - -#define HW_I2C_F(x) (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x)) -#define HW_I2C_F_RD(x) (HW_I2C_F(x).U) -#define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v)) -#define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) | (v))) -#define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v))) -#define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_F bitfields - */ - -/*! - * @name Register I2C_F, field ICR[5:0] (RW) - * - * Prescales the I2C module clock for bit rate selection. This field and the - * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold - * time, and the SCL stop hold time. For a list of values corresponding to each ICR - * setting, see I2C divider and hold values. The SCL divider multiplied by - * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module - * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the - * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time = - * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is - * the delay from the falling edge of SDA (I2C data) while SCL is high (start - * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C - * module clock period (s) * mul * SCL start hold value The SCL stop hold time is - * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C - * data) while SCL is high (stop condition). SCL stop hold time = I2C module - * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock - * speed is 8 MHz, the following table shows the possible hold time values with - * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s. - * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h - * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h - * 1.125 4.750 5.125 - */ -/*@{*/ -#define BP_I2C_F_ICR (0U) /*!< Bit position for I2C_F_ICR. */ -#define BM_I2C_F_ICR (0x3FU) /*!< Bit mask for I2C_F_ICR. */ -#define BS_I2C_F_ICR (6U) /*!< Bit field size in bits for I2C_F_ICR. */ - -/*! @brief Read current value of the I2C_F_ICR field. */ -#define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR) - -/*! @brief Format value for bitfield I2C_F_ICR. */ -#define BF_I2C_F_ICR(v) ((uint8_t)((uint8_t)(v) << BP_I2C_F_ICR) & BM_I2C_F_ICR) - -/*! @brief Set the ICR field to a new value. */ -#define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v))) -/*@}*/ - -/*! - * @name Register I2C_F, field MULT[7:6] (RW) - * - * Defines the multiplier factor (mul). This factor is used along with the SCL - * divider to generate the I2C baud rate. - * - * Values: - * - 00 - mul = 1 - * - 01 - mul = 2 - * - 10 - mul = 4 - * - 11 - Reserved - */ -/*@{*/ -#define BP_I2C_F_MULT (6U) /*!< Bit position for I2C_F_MULT. */ -#define BM_I2C_F_MULT (0xC0U) /*!< Bit mask for I2C_F_MULT. */ -#define BS_I2C_F_MULT (2U) /*!< Bit field size in bits for I2C_F_MULT. */ - -/*! @brief Read current value of the I2C_F_MULT field. */ -#define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT) - -/*! @brief Format value for bitfield I2C_F_MULT. */ -#define BF_I2C_F_MULT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_F_MULT) & BM_I2C_F_MULT) - -/*! @brief Set the MULT field to a new value. */ -#define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_C1 - I2C Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_I2C_C1 - I2C Control Register 1 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_c1 -{ - uint8_t U; - struct _hw_i2c_c1_bitfields - { - uint8_t DMAEN : 1; /*!< [0] DMA Enable */ - uint8_t WUEN : 1; /*!< [1] Wakeup Enable */ - uint8_t RSTA : 1; /*!< [2] Repeat START */ - uint8_t TXAK : 1; /*!< [3] Transmit Acknowledge Enable */ - uint8_t TX : 1; /*!< [4] Transmit Mode Select */ - uint8_t MST : 1; /*!< [5] Master Mode Select */ - uint8_t IICIE : 1; /*!< [6] I2C Interrupt Enable */ - uint8_t IICEN : 1; /*!< [7] I2C Enable */ - } B; -} hw_i2c_c1_t; - -/*! - * @name Constants and macros for entire I2C_C1 register - */ -/*@{*/ -#define HW_I2C_C1_ADDR(x) ((x) + 0x2U) - -#define HW_I2C_C1(x) (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x)) -#define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U) -#define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v)) -#define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) | (v))) -#define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v))) -#define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_C1 bitfields - */ - -/*! - * @name Register I2C_C1, field DMAEN[0] (RW) - * - * Enables or disables the DMA function. - * - * Values: - * - 0 - All DMA signalling disabled. - * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions - * trigger the DMA request: a data byte is received, and either address or - * data is transmitted. (ACK/NACK is automatic) the first byte received matches - * the A1 register or is a general call address. If any address matching - * occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known - * from master to slave, then it is not required to check S[SRW]. With this - * assumption, DMA can also be used in this case. In other cases, if the master - * reads data from the slave, then it is required to rewrite the C1 register - * operation. With this assumption, DMA cannot be used. When FACK = 1, an - * address or a data byte is transmitted. - */ -/*@{*/ -#define BP_I2C_C1_DMAEN (0U) /*!< Bit position for I2C_C1_DMAEN. */ -#define BM_I2C_C1_DMAEN (0x01U) /*!< Bit mask for I2C_C1_DMAEN. */ -#define BS_I2C_C1_DMAEN (1U) /*!< Bit field size in bits for I2C_C1_DMAEN. */ - -/*! @brief Read current value of the I2C_C1_DMAEN field. */ -#define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN)) - -/*! @brief Format value for bitfield I2C_C1_DMAEN. */ -#define BF_I2C_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_DMAEN) & BM_I2C_C1_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field WUEN[1] (RW) - * - * The I2C module can wake the MCU from low power mode with no peripheral bus - * running when slave address matching occurs. - * - * Values: - * - 0 - Normal operation. No interrupt generated when address matching in low - * power mode. - * - 1 - Enables the wakeup function in low power mode. - */ -/*@{*/ -#define BP_I2C_C1_WUEN (1U) /*!< Bit position for I2C_C1_WUEN. */ -#define BM_I2C_C1_WUEN (0x02U) /*!< Bit mask for I2C_C1_WUEN. */ -#define BS_I2C_C1_WUEN (1U) /*!< Bit field size in bits for I2C_C1_WUEN. */ - -/*! @brief Read current value of the I2C_C1_WUEN field. */ -#define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN)) - -/*! @brief Format value for bitfield I2C_C1_WUEN. */ -#define BF_I2C_C1_WUEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_WUEN) & BM_I2C_C1_WUEN) - -/*! @brief Set the WUEN field to a new value. */ -#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field RSTA[2] (WORZ) - * - * Writing 1 to this bit generates a repeated START condition provided it is the - * current master. This bit will always be read as 0. Attempting a repeat at the - * wrong time results in loss of arbitration. - */ -/*@{*/ -#define BP_I2C_C1_RSTA (2U) /*!< Bit position for I2C_C1_RSTA. */ -#define BM_I2C_C1_RSTA (0x04U) /*!< Bit mask for I2C_C1_RSTA. */ -#define BS_I2C_C1_RSTA (1U) /*!< Bit field size in bits for I2C_C1_RSTA. */ - -/*! @brief Format value for bitfield I2C_C1_RSTA. */ -#define BF_I2C_C1_RSTA(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_RSTA) & BM_I2C_C1_RSTA) - -/*! @brief Set the RSTA field to a new value. */ -#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field TXAK[3] (RW) - * - * Specifies the value driven onto the SDA during data acknowledge cycles for - * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK - * generation. SCL is held low until TXAK is written. - * - * Values: - * - 0 - An acknowledge signal is sent to the bus on the following receiving - * byte (if FACK is cleared) or the current receiving byte (if FACK is set). - * - 1 - No acknowledge signal is sent to the bus on the following receiving - * data byte (if FACK is cleared) or the current receiving data byte (if FACK is - * set). - */ -/*@{*/ -#define BP_I2C_C1_TXAK (3U) /*!< Bit position for I2C_C1_TXAK. */ -#define BM_I2C_C1_TXAK (0x08U) /*!< Bit mask for I2C_C1_TXAK. */ -#define BS_I2C_C1_TXAK (1U) /*!< Bit field size in bits for I2C_C1_TXAK. */ - -/*! @brief Read current value of the I2C_C1_TXAK field. */ -#define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK)) - -/*! @brief Format value for bitfield I2C_C1_TXAK. */ -#define BF_I2C_C1_TXAK(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TXAK) & BM_I2C_C1_TXAK) - -/*! @brief Set the TXAK field to a new value. */ -#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field TX[4] (RW) - * - * Selects the direction of master and slave transfers. In master mode this bit - * must be set according to the type of transfer required. Therefore, for address - * cycles, this bit is always set. When addressed as a slave this bit must be - * set by software according to the SRW bit in the status register. - * - * Values: - * - 0 - Receive - * - 1 - Transmit - */ -/*@{*/ -#define BP_I2C_C1_TX (4U) /*!< Bit position for I2C_C1_TX. */ -#define BM_I2C_C1_TX (0x10U) /*!< Bit mask for I2C_C1_TX. */ -#define BS_I2C_C1_TX (1U) /*!< Bit field size in bits for I2C_C1_TX. */ - -/*! @brief Read current value of the I2C_C1_TX field. */ -#define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX)) - -/*! @brief Format value for bitfield I2C_C1_TX. */ -#define BF_I2C_C1_TX(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TX) & BM_I2C_C1_TX) - -/*! @brief Set the TX field to a new value. */ -#define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field MST[5] (RW) - * - * When MST is changed from 0 to 1, a START signal is generated on the bus and - * master mode is selected. When this bit changes from 1 to 0, a STOP signal is - * generated and the mode of operation changes from master to slave. - * - * Values: - * - 0 - Slave mode - * - 1 - Master mode - */ -/*@{*/ -#define BP_I2C_C1_MST (5U) /*!< Bit position for I2C_C1_MST. */ -#define BM_I2C_C1_MST (0x20U) /*!< Bit mask for I2C_C1_MST. */ -#define BS_I2C_C1_MST (1U) /*!< Bit field size in bits for I2C_C1_MST. */ - -/*! @brief Read current value of the I2C_C1_MST field. */ -#define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST)) - -/*! @brief Format value for bitfield I2C_C1_MST. */ -#define BF_I2C_C1_MST(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_MST) & BM_I2C_C1_MST) - -/*! @brief Set the MST field to a new value. */ -#define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field IICIE[6] (RW) - * - * Enables I2C interrupt requests. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_I2C_C1_IICIE (6U) /*!< Bit position for I2C_C1_IICIE. */ -#define BM_I2C_C1_IICIE (0x40U) /*!< Bit mask for I2C_C1_IICIE. */ -#define BS_I2C_C1_IICIE (1U) /*!< Bit field size in bits for I2C_C1_IICIE. */ - -/*! @brief Read current value of the I2C_C1_IICIE field. */ -#define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE)) - -/*! @brief Format value for bitfield I2C_C1_IICIE. */ -#define BF_I2C_C1_IICIE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICIE) & BM_I2C_C1_IICIE) - -/*! @brief Set the IICIE field to a new value. */ -#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C1, field IICEN[7] (RW) - * - * Enables I2C module operation. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_I2C_C1_IICEN (7U) /*!< Bit position for I2C_C1_IICEN. */ -#define BM_I2C_C1_IICEN (0x80U) /*!< Bit mask for I2C_C1_IICEN. */ -#define BS_I2C_C1_IICEN (1U) /*!< Bit field size in bits for I2C_C1_IICEN. */ - -/*! @brief Read current value of the I2C_C1_IICEN field. */ -#define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN)) - -/*! @brief Format value for bitfield I2C_C1_IICEN. */ -#define BF_I2C_C1_IICEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICEN) & BM_I2C_C1_IICEN) - -/*! @brief Set the IICEN field to a new value. */ -#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_S - I2C Status register - ******************************************************************************/ - -/*! - * @brief HW_I2C_S - I2C Status register (RW) - * - * Reset value: 0x80U - */ -typedef union _hw_i2c_s -{ - uint8_t U; - struct _hw_i2c_s_bitfields - { - uint8_t RXAK : 1; /*!< [0] Receive Acknowledge */ - uint8_t IICIF : 1; /*!< [1] Interrupt Flag */ - uint8_t SRW : 1; /*!< [2] Slave Read/Write */ - uint8_t RAM : 1; /*!< [3] Range Address Match */ - uint8_t ARBL : 1; /*!< [4] Arbitration Lost */ - uint8_t BUSY : 1; /*!< [5] Bus Busy */ - uint8_t IAAS : 1; /*!< [6] Addressed As A Slave */ - uint8_t TCF : 1; /*!< [7] Transfer Complete Flag */ - } B; -} hw_i2c_s_t; - -/*! - * @name Constants and macros for entire I2C_S register - */ -/*@{*/ -#define HW_I2C_S_ADDR(x) ((x) + 0x3U) - -#define HW_I2C_S(x) (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x)) -#define HW_I2C_S_RD(x) (HW_I2C_S(x).U) -#define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v)) -#define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) | (v))) -#define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v))) -#define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_S bitfields - */ - -/*! - * @name Register I2C_S, field RXAK[0] (RO) - * - * Values: - * - 0 - Acknowledge signal was received after the completion of one byte of - * data transmission on the bus - * - 1 - No acknowledge signal detected - */ -/*@{*/ -#define BP_I2C_S_RXAK (0U) /*!< Bit position for I2C_S_RXAK. */ -#define BM_I2C_S_RXAK (0x01U) /*!< Bit mask for I2C_S_RXAK. */ -#define BS_I2C_S_RXAK (1U) /*!< Bit field size in bits for I2C_S_RXAK. */ - -/*! @brief Read current value of the I2C_S_RXAK field. */ -#define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK)) -/*@}*/ - -/*! - * @name Register I2C_S, field IICIF[1] (W1C) - * - * This bit sets when an interrupt is pending. This bit must be cleared by - * software by writing 1 to it, such as in the interrupt routine. One of the following - * events can set this bit: One byte transfer, including ACK/NACK bit, completes - * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK - * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit, - * completes if FACK is 1. Match of slave address to calling address including - * primary slave address, range slave address , alert response address, second - * slave address, or general call address. Arbitration lost In SMBus mode, any - * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the - * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or - * start detection interrupt: In the interrupt service routine, first clear the - * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and - * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is - * asserted again. - * - * Values: - * - 0 - No interrupt pending - * - 1 - Interrupt pending - */ -/*@{*/ -#define BP_I2C_S_IICIF (1U) /*!< Bit position for I2C_S_IICIF. */ -#define BM_I2C_S_IICIF (0x02U) /*!< Bit mask for I2C_S_IICIF. */ -#define BS_I2C_S_IICIF (1U) /*!< Bit field size in bits for I2C_S_IICIF. */ - -/*! @brief Read current value of the I2C_S_IICIF field. */ -#define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF)) - -/*! @brief Format value for bitfield I2C_S_IICIF. */ -#define BF_I2C_S_IICIF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_IICIF) & BM_I2C_S_IICIF) - -/*! @brief Set the IICIF field to a new value. */ -#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field SRW[2] (RO) - * - * When addressed as a slave, SRW indicates the value of the R/W command bit of - * the calling address sent to the master. - * - * Values: - * - 0 - Slave receive, master writing to slave - * - 1 - Slave transmit, master reading from slave - */ -/*@{*/ -#define BP_I2C_S_SRW (2U) /*!< Bit position for I2C_S_SRW. */ -#define BM_I2C_S_SRW (0x04U) /*!< Bit mask for I2C_S_SRW. */ -#define BS_I2C_S_SRW (1U) /*!< Bit field size in bits for I2C_S_SRW. */ - -/*! @brief Read current value of the I2C_S_SRW field. */ -#define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW)) -/*@}*/ - -/*! - * @name Register I2C_S, field RAM[3] (RW) - * - * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1: - * Any nonzero calling address is received that matches the address in the RA - * register. The calling address is within the range of values of the A1 and RA - * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1. - * Writing the C1 register with any value clears this bit to 0. - * - * Values: - * - 0 - Not addressed - * - 1 - Addressed as a slave - */ -/*@{*/ -#define BP_I2C_S_RAM (3U) /*!< Bit position for I2C_S_RAM. */ -#define BM_I2C_S_RAM (0x08U) /*!< Bit mask for I2C_S_RAM. */ -#define BS_I2C_S_RAM (1U) /*!< Bit field size in bits for I2C_S_RAM. */ - -/*! @brief Read current value of the I2C_S_RAM field. */ -#define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM)) - -/*! @brief Format value for bitfield I2C_S_RAM. */ -#define BF_I2C_S_RAM(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_RAM) & BM_I2C_S_RAM) - -/*! @brief Set the RAM field to a new value. */ -#define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field ARBL[4] (W1C) - * - * This bit is set by hardware when the arbitration procedure is lost. The ARBL - * bit must be cleared by software, by writing 1 to it. - * - * Values: - * - 0 - Standard bus operation. - * - 1 - Loss of arbitration. - */ -/*@{*/ -#define BP_I2C_S_ARBL (4U) /*!< Bit position for I2C_S_ARBL. */ -#define BM_I2C_S_ARBL (0x10U) /*!< Bit mask for I2C_S_ARBL. */ -#define BS_I2C_S_ARBL (1U) /*!< Bit field size in bits for I2C_S_ARBL. */ - -/*! @brief Read current value of the I2C_S_ARBL field. */ -#define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL)) - -/*! @brief Format value for bitfield I2C_S_ARBL. */ -#define BF_I2C_S_ARBL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_ARBL) & BM_I2C_S_ARBL) - -/*! @brief Set the ARBL field to a new value. */ -#define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field BUSY[5] (RO) - * - * Indicates the status of the bus regardless of slave or master mode. This bit - * is set when a START signal is detected and cleared when a STOP signal is - * detected. - * - * Values: - * - 0 - Bus is idle - * - 1 - Bus is busy - */ -/*@{*/ -#define BP_I2C_S_BUSY (5U) /*!< Bit position for I2C_S_BUSY. */ -#define BM_I2C_S_BUSY (0x20U) /*!< Bit mask for I2C_S_BUSY. */ -#define BS_I2C_S_BUSY (1U) /*!< Bit field size in bits for I2C_S_BUSY. */ - -/*! @brief Read current value of the I2C_S_BUSY field. */ -#define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY)) -/*@}*/ - -/*! - * @name Register I2C_S, field IAAS[6] (RW) - * - * This bit is set by one of the following conditions: The calling address - * matches the programmed primary slave address in the A1 register, or matches the - * range address in the RA register (which must be set to a nonzero value and under - * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is - * received. SMB[SIICAEN] is set and the calling address matches the second programmed - * slave address. ALERTEN is set and an SMBus alert response address is received - * RMEN is set and an address is received that is within the range between the - * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must - * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any - * value clears this bit. - * - * Values: - * - 0 - Not addressed - * - 1 - Addressed as a slave - */ -/*@{*/ -#define BP_I2C_S_IAAS (6U) /*!< Bit position for I2C_S_IAAS. */ -#define BM_I2C_S_IAAS (0x40U) /*!< Bit mask for I2C_S_IAAS. */ -#define BS_I2C_S_IAAS (1U) /*!< Bit field size in bits for I2C_S_IAAS. */ - -/*! @brief Read current value of the I2C_S_IAAS field. */ -#define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS)) - -/*! @brief Format value for bitfield I2C_S_IAAS. */ -#define BF_I2C_S_IAAS(v) ((uint8_t)((uint8_t)(v) << BP_I2C_S_IAAS) & BM_I2C_S_IAAS) - -/*! @brief Set the IAAS field to a new value. */ -#define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v)) -/*@}*/ - -/*! - * @name Register I2C_S, field TCF[7] (RO) - * - * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer. - * This bit is valid only during or immediately following a transfer to or from - * the I2C module. TCF is cleared by reading the I2C data register in receive mode - * or by writing to the I2C data register in transmit mode. - * - * Values: - * - 0 - Transfer in progress - * - 1 - Transfer complete - */ -/*@{*/ -#define BP_I2C_S_TCF (7U) /*!< Bit position for I2C_S_TCF. */ -#define BM_I2C_S_TCF (0x80U) /*!< Bit mask for I2C_S_TCF. */ -#define BS_I2C_S_TCF (1U) /*!< Bit field size in bits for I2C_S_TCF. */ - -/*! @brief Read current value of the I2C_S_TCF field. */ -#define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_D - I2C Data I/O register - ******************************************************************************/ - -/*! - * @brief HW_I2C_D - I2C Data I/O register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_d -{ - uint8_t U; - struct _hw_i2c_d_bitfields - { - uint8_t DATA : 8; /*!< [7:0] Data */ - } B; -} hw_i2c_d_t; - -/*! - * @name Constants and macros for entire I2C_D register - */ -/*@{*/ -#define HW_I2C_D_ADDR(x) ((x) + 0x4U) - -#define HW_I2C_D(x) (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x)) -#define HW_I2C_D_RD(x) (HW_I2C_D(x).U) -#define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v)) -#define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) | (v))) -#define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v))) -#define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_D bitfields - */ - -/*! - * @name Register I2C_D, field DATA[7:0] (RW) - * - * In master transmit mode, when data is written to this register, a data - * transfer is initiated. The most significant bit is sent first. In master receive - * mode, reading this register initiates receiving of the next byte of data. When - * making the transition out of master receive mode, switch the I2C mode before - * reading the Data register to prevent an inadvertent initiation of a master - * receive data transfer. In slave mode, the same functions are available after an - * address match occurs. The C1[TX] bit must correctly reflect the desired direction - * of transfer in master and slave modes for the transmission to begin. For - * example, if the I2C module is configured for master transmit but a master receive - * is desired, reading the Data register does not initiate the receive. Reading - * the Data register returns the last byte received while the I2C module is - * configured in master receive or slave receive mode. The Data register does not - * reflect every byte that is transmitted on the I2C bus, and neither can software - * verify that a byte has been written to the Data register correctly by reading it - * back. In master transmit mode, the first byte of data written to the Data - * register following assertion of MST (start bit) or assertion of RSTA (repeated - * start bit) is used for the address transfer and must consist of the calling - * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0). - */ -/*@{*/ -#define BP_I2C_D_DATA (0U) /*!< Bit position for I2C_D_DATA. */ -#define BM_I2C_D_DATA (0xFFU) /*!< Bit mask for I2C_D_DATA. */ -#define BS_I2C_D_DATA (8U) /*!< Bit field size in bits for I2C_D_DATA. */ - -/*! @brief Read current value of the I2C_D_DATA field. */ -#define BR_I2C_D_DATA(x) (HW_I2C_D(x).U) - -/*! @brief Format value for bitfield I2C_D_DATA. */ -#define BF_I2C_D_DATA(v) ((uint8_t)((uint8_t)(v) << BP_I2C_D_DATA) & BM_I2C_D_DATA) - -/*! @brief Set the DATA field to a new value. */ -#define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_C2 - I2C Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_I2C_C2 - I2C Control Register 2 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_c2 -{ - uint8_t U; - struct _hw_i2c_c2_bitfields - { - uint8_t AD : 3; /*!< [2:0] Slave Address */ - uint8_t RMEN : 1; /*!< [3] Range Address Matching Enable */ - uint8_t SBRC : 1; /*!< [4] Slave Baud Rate Control */ - uint8_t HDRS : 1; /*!< [5] High Drive Select */ - uint8_t ADEXT : 1; /*!< [6] Address Extension */ - uint8_t GCAEN : 1; /*!< [7] General Call Address Enable */ - } B; -} hw_i2c_c2_t; - -/*! - * @name Constants and macros for entire I2C_C2 register - */ -/*@{*/ -#define HW_I2C_C2_ADDR(x) ((x) + 0x5U) - -#define HW_I2C_C2(x) (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x)) -#define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U) -#define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v)) -#define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) | (v))) -#define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v))) -#define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_C2 bitfields - */ - -/*! - * @name Register I2C_C2, field AD[2:0] (RW) - * - * Contains the upper three bits of the slave address in the 10-bit address - * scheme. This field is valid only while the ADEXT bit is set. - */ -/*@{*/ -#define BP_I2C_C2_AD (0U) /*!< Bit position for I2C_C2_AD. */ -#define BM_I2C_C2_AD (0x07U) /*!< Bit mask for I2C_C2_AD. */ -#define BS_I2C_C2_AD (3U) /*!< Bit field size in bits for I2C_C2_AD. */ - -/*! @brief Read current value of the I2C_C2_AD field. */ -#define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD) - -/*! @brief Format value for bitfield I2C_C2_AD. */ -#define BF_I2C_C2_AD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_AD) & BM_I2C_C2_AD) - -/*! @brief Set the AD field to a new value. */ -#define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v))) -/*@}*/ - -/*! - * @name Register I2C_C2, field RMEN[3] (RW) - * - * This bit controls the slave address matching for addresses between the values - * of the A1 and RA registers. When this bit is set, a slave address matching - * occurs for any address greater than the value of the A1 register and less than - * or equal to the value of the RA register. - * - * Values: - * - 0 - Range mode disabled. No address matching occurs for an address within - * the range of values of the A1 and RA registers. - * - 1 - Range mode enabled. Address matching occurs when a slave receives an - * address within the range of values of the A1 and RA registers. - */ -/*@{*/ -#define BP_I2C_C2_RMEN (3U) /*!< Bit position for I2C_C2_RMEN. */ -#define BM_I2C_C2_RMEN (0x08U) /*!< Bit mask for I2C_C2_RMEN. */ -#define BS_I2C_C2_RMEN (1U) /*!< Bit field size in bits for I2C_C2_RMEN. */ - -/*! @brief Read current value of the I2C_C2_RMEN field. */ -#define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN)) - -/*! @brief Format value for bitfield I2C_C2_RMEN. */ -#define BF_I2C_C2_RMEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_RMEN) & BM_I2C_C2_RMEN) - -/*! @brief Set the RMEN field to a new value. */ -#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field SBRC[4] (RW) - * - * Enables independent slave mode baud rate at maximum frequency, which forces - * clock stretching on SCL in very fast I2C modes. To a slave, an example of a - * "very fast" mode is when the master transfers at 40 kbit/s but the slave can - * capture the master's data at only 10 kbit/s. - * - * Values: - * - 0 - The slave baud rate follows the master baud rate and clock stretching - * may occur - * - 1 - Slave baud rate is independent of the master baud rate - */ -/*@{*/ -#define BP_I2C_C2_SBRC (4U) /*!< Bit position for I2C_C2_SBRC. */ -#define BM_I2C_C2_SBRC (0x10U) /*!< Bit mask for I2C_C2_SBRC. */ -#define BS_I2C_C2_SBRC (1U) /*!< Bit field size in bits for I2C_C2_SBRC. */ - -/*! @brief Read current value of the I2C_C2_SBRC field. */ -#define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC)) - -/*! @brief Format value for bitfield I2C_C2_SBRC. */ -#define BF_I2C_C2_SBRC(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_SBRC) & BM_I2C_C2_SBRC) - -/*! @brief Set the SBRC field to a new value. */ -#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field HDRS[5] (RW) - * - * Controls the drive capability of the I2C pads. - * - * Values: - * - 0 - Normal drive mode - * - 1 - High drive mode - */ -/*@{*/ -#define BP_I2C_C2_HDRS (5U) /*!< Bit position for I2C_C2_HDRS. */ -#define BM_I2C_C2_HDRS (0x20U) /*!< Bit mask for I2C_C2_HDRS. */ -#define BS_I2C_C2_HDRS (1U) /*!< Bit field size in bits for I2C_C2_HDRS. */ - -/*! @brief Read current value of the I2C_C2_HDRS field. */ -#define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS)) - -/*! @brief Format value for bitfield I2C_C2_HDRS. */ -#define BF_I2C_C2_HDRS(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_HDRS) & BM_I2C_C2_HDRS) - -/*! @brief Set the HDRS field to a new value. */ -#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field ADEXT[6] (RW) - * - * Controls the number of bits used for the slave address. - * - * Values: - * - 0 - 7-bit address scheme - * - 1 - 10-bit address scheme - */ -/*@{*/ -#define BP_I2C_C2_ADEXT (6U) /*!< Bit position for I2C_C2_ADEXT. */ -#define BM_I2C_C2_ADEXT (0x40U) /*!< Bit mask for I2C_C2_ADEXT. */ -#define BS_I2C_C2_ADEXT (1U) /*!< Bit field size in bits for I2C_C2_ADEXT. */ - -/*! @brief Read current value of the I2C_C2_ADEXT field. */ -#define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT)) - -/*! @brief Format value for bitfield I2C_C2_ADEXT. */ -#define BF_I2C_C2_ADEXT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_ADEXT) & BM_I2C_C2_ADEXT) - -/*! @brief Set the ADEXT field to a new value. */ -#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v)) -/*@}*/ - -/*! - * @name Register I2C_C2, field GCAEN[7] (RW) - * - * Enables general call address. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_I2C_C2_GCAEN (7U) /*!< Bit position for I2C_C2_GCAEN. */ -#define BM_I2C_C2_GCAEN (0x80U) /*!< Bit mask for I2C_C2_GCAEN. */ -#define BS_I2C_C2_GCAEN (1U) /*!< Bit field size in bits for I2C_C2_GCAEN. */ - -/*! @brief Read current value of the I2C_C2_GCAEN field. */ -#define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN)) - -/*! @brief Format value for bitfield I2C_C2_GCAEN. */ -#define BF_I2C_C2_GCAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_C2_GCAEN) & BM_I2C_C2_GCAEN) - -/*! @brief Set the GCAEN field to a new value. */ -#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_FLT - I2C Programmable Input Glitch Filter register - ******************************************************************************/ - -/*! - * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_flt -{ - uint8_t U; - struct _hw_i2c_flt_bitfields - { - uint8_t FLT : 4; /*!< [3:0] I2C Programmable Filter Factor */ - uint8_t STARTF : 1; /*!< [4] I2C Bus Start Detect Flag */ - uint8_t SSIE : 1; /*!< [5] I2C Bus Stop or Start Interrupt Enable */ - uint8_t STOPF : 1; /*!< [6] I2C Bus Stop Detect Flag */ - uint8_t SHEN : 1; /*!< [7] Stop Hold Enable */ - } B; -} hw_i2c_flt_t; - -/*! - * @name Constants and macros for entire I2C_FLT register - */ -/*@{*/ -#define HW_I2C_FLT_ADDR(x) ((x) + 0x6U) - -#define HW_I2C_FLT(x) (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x)) -#define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U) -#define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v)) -#define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) | (v))) -#define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v))) -#define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_FLT bitfields - */ - -/*! - * @name Register I2C_FLT, field FLT[3:0] (RW) - * - * Controls the width of the glitch, in terms of I2C module clock cycles, that - * the filter must absorb. For any glitch whose size is less than or equal to this - * width setting, the filter does not allow the glitch to pass. - * - * Values: - * - 0 - No filter/bypass - */ -/*@{*/ -#define BP_I2C_FLT_FLT (0U) /*!< Bit position for I2C_FLT_FLT. */ -#define BM_I2C_FLT_FLT (0x0FU) /*!< Bit mask for I2C_FLT_FLT. */ -#define BS_I2C_FLT_FLT (4U) /*!< Bit field size in bits for I2C_FLT_FLT. */ - -/*! @brief Read current value of the I2C_FLT_FLT field. */ -#define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT) - -/*! @brief Format value for bitfield I2C_FLT_FLT. */ -#define BF_I2C_FLT_FLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_FLT) & BM_I2C_FLT_FLT) - -/*! @brief Set the FLT field to a new value. */ -#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v))) -/*@}*/ - -/*! - * @name Register I2C_FLT, field STARTF[4] (W1C) - * - * Hardware sets this bit when the I2C bus's start status is detected. The - * STARTF bit must be cleared by writing 1 to it. - * - * Values: - * - 0 - No start happens on I2C bus - * - 1 - Start detected on I2C bus - */ -/*@{*/ -#define BP_I2C_FLT_STARTF (4U) /*!< Bit position for I2C_FLT_STARTF. */ -#define BM_I2C_FLT_STARTF (0x10U) /*!< Bit mask for I2C_FLT_STARTF. */ -#define BS_I2C_FLT_STARTF (1U) /*!< Bit field size in bits for I2C_FLT_STARTF. */ - -/*! @brief Read current value of the I2C_FLT_STARTF field. */ -#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF)) - -/*! @brief Format value for bitfield I2C_FLT_STARTF. */ -#define BF_I2C_FLT_STARTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STARTF) & BM_I2C_FLT_STARTF) - -/*! @brief Set the STARTF field to a new value. */ -#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_FLT, field SSIE[5] (RW) - * - * This bit enables the interrupt for I2C bus stop or start detection. To clear - * the I2C bus stop or start detection interrupt: In the interrupt service - * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the - * IICIF bit in the status register. If this sequence is reversed, the IICIF bit - * is asserted again. - * - * Values: - * - 0 - Stop or start detection interrupt is disabled - * - 1 - Stop or start detection interrupt is enabled - */ -/*@{*/ -#define BP_I2C_FLT_SSIE (5U) /*!< Bit position for I2C_FLT_SSIE. */ -#define BM_I2C_FLT_SSIE (0x20U) /*!< Bit mask for I2C_FLT_SSIE. */ -#define BS_I2C_FLT_SSIE (1U) /*!< Bit field size in bits for I2C_FLT_SSIE. */ - -/*! @brief Read current value of the I2C_FLT_SSIE field. */ -#define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE)) - -/*! @brief Format value for bitfield I2C_FLT_SSIE. */ -#define BF_I2C_FLT_SSIE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SSIE) & BM_I2C_FLT_SSIE) - -/*! @brief Set the SSIE field to a new value. */ -#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v)) -/*@}*/ - -/*! - * @name Register I2C_FLT, field STOPF[6] (W1C) - * - * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF - * bit must be cleared by writing 1 to it. - * - * Values: - * - 0 - No stop happens on I2C bus - * - 1 - Stop detected on I2C bus - */ -/*@{*/ -#define BP_I2C_FLT_STOPF (6U) /*!< Bit position for I2C_FLT_STOPF. */ -#define BM_I2C_FLT_STOPF (0x40U) /*!< Bit mask for I2C_FLT_STOPF. */ -#define BS_I2C_FLT_STOPF (1U) /*!< Bit field size in bits for I2C_FLT_STOPF. */ - -/*! @brief Read current value of the I2C_FLT_STOPF field. */ -#define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF)) - -/*! @brief Format value for bitfield I2C_FLT_STOPF. */ -#define BF_I2C_FLT_STOPF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STOPF) & BM_I2C_FLT_STOPF) - -/*! @brief Set the STOPF field to a new value. */ -#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_FLT, field SHEN[7] (RW) - * - * Set this bit to hold off entry to stop mode when any data transmission or - * reception is occurring. The following scenario explains the holdoff - * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set - * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The - * byte currently being transferred, including both address and data, completes - * its transfer. The I2C slave or master acknowledges that the in-transfer byte - * completed its transfer and acknowledges the request to enter stop mode. After - * receiving the I2C module's acknowledgment of the request to enter stop mode, - * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit - * is set to 1 and the I2C module is in an idle or disabled state when the MCU - * signals to enter stop mode, the module immediately acknowledges the request to - * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or - * reception that was suspended by stop mode entry was incomplete: To resume the - * overall transmission or reception after the MCU exits stop mode, software must - * reinitialize the transfer by resending the address of the slave. If the I2C - * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, - * system software will receive the interrupt triggered by the I2C Status Register's - * TCF bit after the MCU wakes from the stop mode. - * - * Values: - * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated. - * - 1 - Stop holdoff is enabled. - */ -/*@{*/ -#define BP_I2C_FLT_SHEN (7U) /*!< Bit position for I2C_FLT_SHEN. */ -#define BM_I2C_FLT_SHEN (0x80U) /*!< Bit mask for I2C_FLT_SHEN. */ -#define BS_I2C_FLT_SHEN (1U) /*!< Bit field size in bits for I2C_FLT_SHEN. */ - -/*! @brief Read current value of the I2C_FLT_SHEN field. */ -#define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN)) - -/*! @brief Format value for bitfield I2C_FLT_SHEN. */ -#define BF_I2C_FLT_SHEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SHEN) & BM_I2C_FLT_SHEN) - -/*! @brief Set the SHEN field to a new value. */ -#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_RA - I2C Range Address register - ******************************************************************************/ - -/*! - * @brief HW_I2C_RA - I2C Range Address register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_ra -{ - uint8_t U; - struct _hw_i2c_ra_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t RAD : 7; /*!< [7:1] Range Slave Address */ - } B; -} hw_i2c_ra_t; - -/*! - * @name Constants and macros for entire I2C_RA register - */ -/*@{*/ -#define HW_I2C_RA_ADDR(x) ((x) + 0x7U) - -#define HW_I2C_RA(x) (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x)) -#define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U) -#define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v)) -#define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) | (v))) -#define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v))) -#define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_RA bitfields - */ - -/*! - * @name Register I2C_RA, field RAD[7:1] (RW) - * - * This field contains the slave address to be used by the I2C module. The field - * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero - * value write enables this register. This register value can be considered as a - * maximum boundary in the range matching mode. - */ -/*@{*/ -#define BP_I2C_RA_RAD (1U) /*!< Bit position for I2C_RA_RAD. */ -#define BM_I2C_RA_RAD (0xFEU) /*!< Bit mask for I2C_RA_RAD. */ -#define BS_I2C_RA_RAD (7U) /*!< Bit field size in bits for I2C_RA_RAD. */ - -/*! @brief Read current value of the I2C_RA_RAD field. */ -#define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD) - -/*! @brief Format value for bitfield I2C_RA_RAD. */ -#define BF_I2C_RA_RAD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_RA_RAD) & BM_I2C_RA_RAD) - -/*! @brief Set the RAD field to a new value. */ -#define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_SMB - I2C SMBus Control and Status register - ******************************************************************************/ - -/*! - * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW) - * - * Reset value: 0x00U - * - * When the SCL and SDA signals are held high for a length of time greater than - * the high timeout period, the SHTF1 flag sets. Before reaching this threshold, - * while the system is detecting how long these signals are being held high, a - * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the - * bus transmission process with the idle bus state. When the TCKSEL bit is set, - * there is no need to monitor the SHTF1 bit because the bus speed is too high to - * match the protocol of SMBus. - */ -typedef union _hw_i2c_smb -{ - uint8_t U; - struct _hw_i2c_smb_bitfields - { - uint8_t SHTF2IE : 1; /*!< [0] SHTF2 Interrupt Enable */ - uint8_t SHTF2 : 1; /*!< [1] SCL High Timeout Flag 2 */ - uint8_t SHTF1 : 1; /*!< [2] SCL High Timeout Flag 1 */ - uint8_t SLTF : 1; /*!< [3] SCL Low Timeout Flag */ - uint8_t TCKSEL : 1; /*!< [4] Timeout Counter Clock Select */ - uint8_t SIICAEN : 1; /*!< [5] Second I2C Address Enable */ - uint8_t ALERTEN : 1; /*!< [6] SMBus Alert Response Address Enable */ - uint8_t FACK : 1; /*!< [7] Fast NACK/ACK Enable */ - } B; -} hw_i2c_smb_t; - -/*! - * @name Constants and macros for entire I2C_SMB register - */ -/*@{*/ -#define HW_I2C_SMB_ADDR(x) ((x) + 0x8U) - -#define HW_I2C_SMB(x) (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x)) -#define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U) -#define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v)) -#define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) | (v))) -#define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v))) -#define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_SMB bitfields - */ - -/*! - * @name Register I2C_SMB, field SHTF2IE[0] (RW) - * - * Enables SCL high and SDA low timeout interrupt. - * - * Values: - * - 0 - SHTF2 interrupt is disabled - * - 1 - SHTF2 interrupt is enabled - */ -/*@{*/ -#define BP_I2C_SMB_SHTF2IE (0U) /*!< Bit position for I2C_SMB_SHTF2IE. */ -#define BM_I2C_SMB_SHTF2IE (0x01U) /*!< Bit mask for I2C_SMB_SHTF2IE. */ -#define BS_I2C_SMB_SHTF2IE (1U) /*!< Bit field size in bits for I2C_SMB_SHTF2IE. */ - -/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */ -#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE)) - -/*! @brief Format value for bitfield I2C_SMB_SHTF2IE. */ -#define BF_I2C_SMB_SHTF2IE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2IE) & BM_I2C_SMB_SHTF2IE) - -/*! @brief Set the SHTF2IE field to a new value. */ -#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SHTF2[1] (W1C) - * - * This bit sets when SCL is held high and SDA is held low more than clock * - * LoValue / 512. Software clears this bit by writing 1 to it. - * - * Values: - * - 0 - No SCL high and SDA low timeout occurs - * - 1 - SCL high and SDA low timeout occurs - */ -/*@{*/ -#define BP_I2C_SMB_SHTF2 (1U) /*!< Bit position for I2C_SMB_SHTF2. */ -#define BM_I2C_SMB_SHTF2 (0x02U) /*!< Bit mask for I2C_SMB_SHTF2. */ -#define BS_I2C_SMB_SHTF2 (1U) /*!< Bit field size in bits for I2C_SMB_SHTF2. */ - -/*! @brief Read current value of the I2C_SMB_SHTF2 field. */ -#define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2)) - -/*! @brief Format value for bitfield I2C_SMB_SHTF2. */ -#define BF_I2C_SMB_SHTF2(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2) & BM_I2C_SMB_SHTF2) - -/*! @brief Set the SHTF2 field to a new value. */ -#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SHTF1[2] (RO) - * - * This read-only bit sets when SCL and SDA are held high more than clock * - * LoValue / 512, which indicates the bus is free. This bit is cleared automatically. - * - * Values: - * - 0 - No SCL high and SDA high timeout occurs - * - 1 - SCL high and SDA high timeout occurs - */ -/*@{*/ -#define BP_I2C_SMB_SHTF1 (2U) /*!< Bit position for I2C_SMB_SHTF1. */ -#define BM_I2C_SMB_SHTF1 (0x04U) /*!< Bit mask for I2C_SMB_SHTF1. */ -#define BS_I2C_SMB_SHTF1 (1U) /*!< Bit field size in bits for I2C_SMB_SHTF1. */ - -/*! @brief Read current value of the I2C_SMB_SHTF1 field. */ -#define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SLTF[3] (W1C) - * - * This bit is set when the SLT register (consisting of the SLTH and SLTL - * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs. - * Software clears this bit by writing a logic 1 to it. The low timeout function - * is disabled when the SLT register's value is 0. - * - * Values: - * - 0 - No low timeout occurs - * - 1 - Low timeout occurs - */ -/*@{*/ -#define BP_I2C_SMB_SLTF (3U) /*!< Bit position for I2C_SMB_SLTF. */ -#define BM_I2C_SMB_SLTF (0x08U) /*!< Bit mask for I2C_SMB_SLTF. */ -#define BS_I2C_SMB_SLTF (1U) /*!< Bit field size in bits for I2C_SMB_SLTF. */ - -/*! @brief Read current value of the I2C_SMB_SLTF field. */ -#define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF)) - -/*! @brief Format value for bitfield I2C_SMB_SLTF. */ -#define BF_I2C_SMB_SLTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SLTF) & BM_I2C_SMB_SLTF) - -/*! @brief Set the SLTF field to a new value. */ -#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field TCKSEL[4] (RW) - * - * Selects the clock source of the timeout counter. - * - * Values: - * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64 - * - 1 - Timeout counter counts at the frequency of the I2C module clock - */ -/*@{*/ -#define BP_I2C_SMB_TCKSEL (4U) /*!< Bit position for I2C_SMB_TCKSEL. */ -#define BM_I2C_SMB_TCKSEL (0x10U) /*!< Bit mask for I2C_SMB_TCKSEL. */ -#define BS_I2C_SMB_TCKSEL (1U) /*!< Bit field size in bits for I2C_SMB_TCKSEL. */ - -/*! @brief Read current value of the I2C_SMB_TCKSEL field. */ -#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL)) - -/*! @brief Format value for bitfield I2C_SMB_TCKSEL. */ -#define BF_I2C_SMB_TCKSEL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_TCKSEL) & BM_I2C_SMB_TCKSEL) - -/*! @brief Set the TCKSEL field to a new value. */ -#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field SIICAEN[5] (RW) - * - * Enables or disables SMBus device default address. - * - * Values: - * - 0 - I2C address register 2 matching is disabled - * - 1 - I2C address register 2 matching is enabled - */ -/*@{*/ -#define BP_I2C_SMB_SIICAEN (5U) /*!< Bit position for I2C_SMB_SIICAEN. */ -#define BM_I2C_SMB_SIICAEN (0x20U) /*!< Bit mask for I2C_SMB_SIICAEN. */ -#define BS_I2C_SMB_SIICAEN (1U) /*!< Bit field size in bits for I2C_SMB_SIICAEN. */ - -/*! @brief Read current value of the I2C_SMB_SIICAEN field. */ -#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN)) - -/*! @brief Format value for bitfield I2C_SMB_SIICAEN. */ -#define BF_I2C_SMB_SIICAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SIICAEN) & BM_I2C_SMB_SIICAEN) - -/*! @brief Set the SIICAEN field to a new value. */ -#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field ALERTEN[6] (RW) - * - * Enables or disables SMBus alert response address matching. After the host - * responds to a device that used the alert response address, you must use software - * to put the device's address on the bus. The alert protocol is described in the - * SMBus specification. - * - * Values: - * - 0 - SMBus alert response address matching is disabled - * - 1 - SMBus alert response address matching is enabled - */ -/*@{*/ -#define BP_I2C_SMB_ALERTEN (6U) /*!< Bit position for I2C_SMB_ALERTEN. */ -#define BM_I2C_SMB_ALERTEN (0x40U) /*!< Bit mask for I2C_SMB_ALERTEN. */ -#define BS_I2C_SMB_ALERTEN (1U) /*!< Bit field size in bits for I2C_SMB_ALERTEN. */ - -/*! @brief Read current value of the I2C_SMB_ALERTEN field. */ -#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN)) - -/*! @brief Format value for bitfield I2C_SMB_ALERTEN. */ -#define BF_I2C_SMB_ALERTEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_ALERTEN) & BM_I2C_SMB_ALERTEN) - -/*! @brief Set the ALERTEN field to a new value. */ -#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v)) -/*@}*/ - -/*! - * @name Register I2C_SMB, field FACK[7] (RW) - * - * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK - * according to the result of receiving data byte. - * - * Values: - * - 0 - An ACK or NACK is sent on the following receiving data byte - * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing - * 1 to TXAK after receiving a data byte generates a NACK. - */ -/*@{*/ -#define BP_I2C_SMB_FACK (7U) /*!< Bit position for I2C_SMB_FACK. */ -#define BM_I2C_SMB_FACK (0x80U) /*!< Bit mask for I2C_SMB_FACK. */ -#define BS_I2C_SMB_FACK (1U) /*!< Bit field size in bits for I2C_SMB_FACK. */ - -/*! @brief Read current value of the I2C_SMB_FACK field. */ -#define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK)) - -/*! @brief Format value for bitfield I2C_SMB_FACK. */ -#define BF_I2C_SMB_FACK(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_FACK) & BM_I2C_SMB_FACK) - -/*! @brief Set the FACK field to a new value. */ -#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_A2 - I2C Address Register 2 - ******************************************************************************/ - -/*! - * @brief HW_I2C_A2 - I2C Address Register 2 (RW) - * - * Reset value: 0xC2U - */ -typedef union _hw_i2c_a2 -{ - uint8_t U; - struct _hw_i2c_a2_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t SAD : 7; /*!< [7:1] SMBus Address */ - } B; -} hw_i2c_a2_t; - -/*! - * @name Constants and macros for entire I2C_A2 register - */ -/*@{*/ -#define HW_I2C_A2_ADDR(x) ((x) + 0x9U) - -#define HW_I2C_A2(x) (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x)) -#define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U) -#define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v)) -#define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) | (v))) -#define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v))) -#define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_A2 bitfields - */ - -/*! - * @name Register I2C_A2, field SAD[7:1] (RW) - * - * Contains the slave address used by the SMBus. This field is used on the - * device default address or other related addresses. - */ -/*@{*/ -#define BP_I2C_A2_SAD (1U) /*!< Bit position for I2C_A2_SAD. */ -#define BM_I2C_A2_SAD (0xFEU) /*!< Bit mask for I2C_A2_SAD. */ -#define BS_I2C_A2_SAD (7U) /*!< Bit field size in bits for I2C_A2_SAD. */ - -/*! @brief Read current value of the I2C_A2_SAD field. */ -#define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD) - -/*! @brief Format value for bitfield I2C_A2_SAD. */ -#define BF_I2C_A2_SAD(v) ((uint8_t)((uint8_t)(v) << BP_I2C_A2_SAD) & BM_I2C_A2_SAD) - -/*! @brief Set the SAD field to a new value. */ -#define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2C_SLTH - I2C SCL Low Timeout Register High - ******************************************************************************/ - -/*! - * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_slth -{ - uint8_t U; - struct _hw_i2c_slth_bitfields - { - uint8_t SSLT : 8; /*!< [7:0] */ - } B; -} hw_i2c_slth_t; - -/*! - * @name Constants and macros for entire I2C_SLTH register - */ -/*@{*/ -#define HW_I2C_SLTH_ADDR(x) ((x) + 0xAU) - -#define HW_I2C_SLTH(x) (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x)) -#define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U) -#define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v)) -#define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) | (v))) -#define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v))) -#define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_SLTH bitfields - */ - -/*! - * @name Register I2C_SLTH, field SSLT[7:0] (RW) - * - * Most significant byte of SCL low timeout value that determines the timeout - * period of SCL low. - */ -/*@{*/ -#define BP_I2C_SLTH_SSLT (0U) /*!< Bit position for I2C_SLTH_SSLT. */ -#define BM_I2C_SLTH_SSLT (0xFFU) /*!< Bit mask for I2C_SLTH_SSLT. */ -#define BS_I2C_SLTH_SSLT (8U) /*!< Bit field size in bits for I2C_SLTH_SSLT. */ - -/*! @brief Read current value of the I2C_SLTH_SSLT field. */ -#define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U) - -/*! @brief Format value for bitfield I2C_SLTH_SSLT. */ -#define BF_I2C_SLTH_SSLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SLTH_SSLT) & BM_I2C_SLTH_SSLT) - -/*! @brief Set the SSLT field to a new value. */ -#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2C_SLTL - I2C SCL Low Timeout Register Low - ******************************************************************************/ - -/*! - * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_i2c_sltl -{ - uint8_t U; - struct _hw_i2c_sltl_bitfields - { - uint8_t SSLT : 8; /*!< [7:0] */ - } B; -} hw_i2c_sltl_t; - -/*! - * @name Constants and macros for entire I2C_SLTL register - */ -/*@{*/ -#define HW_I2C_SLTL_ADDR(x) ((x) + 0xBU) - -#define HW_I2C_SLTL(x) (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x)) -#define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U) -#define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v)) -#define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) | (v))) -#define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v))) -#define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2C_SLTL bitfields - */ - -/*! - * @name Register I2C_SLTL, field SSLT[7:0] (RW) - * - * Least significant byte of SCL low timeout value that determines the timeout - * period of SCL low. - */ -/*@{*/ -#define BP_I2C_SLTL_SSLT (0U) /*!< Bit position for I2C_SLTL_SSLT. */ -#define BM_I2C_SLTL_SSLT (0xFFU) /*!< Bit mask for I2C_SLTL_SSLT. */ -#define BS_I2C_SLTL_SSLT (8U) /*!< Bit field size in bits for I2C_SLTL_SSLT. */ - -/*! @brief Read current value of the I2C_SLTL_SSLT field. */ -#define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U) - -/*! @brief Format value for bitfield I2C_SLTL_SSLT. */ -#define BF_I2C_SLTL_SSLT(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SLTL_SSLT) & BM_I2C_SLTL_SSLT) - -/*! @brief Set the SSLT field to a new value. */ -#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * hw_i2c_t - module struct - ******************************************************************************/ -/*! - * @brief All I2C module registers. - */ -#pragma pack(1) -typedef struct _hw_i2c -{ - __IO hw_i2c_a1_t A1; /*!< [0x0] I2C Address Register 1 */ - __IO hw_i2c_f_t F; /*!< [0x1] I2C Frequency Divider register */ - __IO hw_i2c_c1_t C1; /*!< [0x2] I2C Control Register 1 */ - __IO hw_i2c_s_t S; /*!< [0x3] I2C Status register */ - __IO hw_i2c_d_t D; /*!< [0x4] I2C Data I/O register */ - __IO hw_i2c_c2_t C2; /*!< [0x5] I2C Control Register 2 */ - __IO hw_i2c_flt_t FLT; /*!< [0x6] I2C Programmable Input Glitch Filter register */ - __IO hw_i2c_ra_t RA; /*!< [0x7] I2C Range Address register */ - __IO hw_i2c_smb_t SMB; /*!< [0x8] I2C SMBus Control and Status register */ - __IO hw_i2c_a2_t A2; /*!< [0x9] I2C Address Register 2 */ - __IO hw_i2c_slth_t SLTH; /*!< [0xA] I2C SCL Low Timeout Register High */ - __IO hw_i2c_sltl_t SLTL; /*!< [0xB] I2C SCL Low Timeout Register Low */ -} hw_i2c_t; -#pragma pack() - -/*! @brief Macro to access all I2C registers. */ -/*! @param x I2C module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_I2C(I2C0_BASE). */ -#define HW_I2C(x) (*(hw_i2c_t *)(x)) - -#endif /* __HW_I2C_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2s.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2s.h deleted file mode 100644 index 17fda711c40..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2s.h +++ /dev/null @@ -1,3098 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_I2S_REGISTERS_H__ -#define __HW_I2S_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 I2S - * - * Inter-IC Sound / Synchronous Audio Interface - * - * Registers defined in this header file: - * - HW_I2S_TCSR - SAI Transmit Control Register - * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register - * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register - * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register - * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register - * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register - * - HW_I2S_TDRn - SAI Transmit Data Register - * - HW_I2S_TFRn - SAI Transmit FIFO Register - * - HW_I2S_TMR - SAI Transmit Mask Register - * - HW_I2S_RCSR - SAI Receive Control Register - * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register - * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register - * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register - * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register - * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register - * - HW_I2S_RDRn - SAI Receive Data Register - * - HW_I2S_RFRn - SAI Receive FIFO Register - * - HW_I2S_RMR - SAI Receive Mask Register - * - HW_I2S_MCR - SAI MCLK Control Register - * - HW_I2S_MDR - SAI MCLK Divide Register - * - * - hw_i2s_t - Struct containing all module registers. - */ - -#define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */ - -/******************************************************************************* - * HW_I2S_TCSR - SAI Transmit Control Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tcsr -{ - uint32_t U; - struct _hw_i2s_tcsr_bitfields - { - uint32_t FRDE : 1; /*!< [0] FIFO Request DMA Enable */ - uint32_t FWDE : 1; /*!< [1] FIFO Warning DMA Enable */ - uint32_t RESERVED0 : 6; /*!< [7:2] */ - uint32_t FRIE : 1; /*!< [8] FIFO Request Interrupt Enable */ - uint32_t FWIE : 1; /*!< [9] FIFO Warning Interrupt Enable */ - uint32_t FEIE : 1; /*!< [10] FIFO Error Interrupt Enable */ - uint32_t SEIE : 1; /*!< [11] Sync Error Interrupt Enable */ - uint32_t WSIE : 1; /*!< [12] Word Start Interrupt Enable */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t FRF : 1; /*!< [16] FIFO Request Flag */ - uint32_t FWF : 1; /*!< [17] FIFO Warning Flag */ - uint32_t FEF : 1; /*!< [18] FIFO Error Flag */ - uint32_t SEF : 1; /*!< [19] Sync Error Flag */ - uint32_t WSF : 1; /*!< [20] Word Start Flag */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t SR : 1; /*!< [24] Software Reset */ - uint32_t FR : 1; /*!< [25] FIFO Reset */ - uint32_t RESERVED3 : 2; /*!< [27:26] */ - uint32_t BCE : 1; /*!< [28] Bit Clock Enable */ - uint32_t DBGE : 1; /*!< [29] Debug Enable */ - uint32_t STOPE : 1; /*!< [30] Stop Enable */ - uint32_t TE : 1; /*!< [31] Transmitter Enable */ - } B; -} hw_i2s_tcsr_t; - -/*! - * @name Constants and macros for entire I2S_TCSR register - */ -/*@{*/ -#define HW_I2S_TCSR_ADDR(x) ((x) + 0x0U) - -#define HW_I2S_TCSR(x) (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x)) -#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U) -#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v)) -#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) | (v))) -#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v))) -#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCSR bitfields - */ - -/*! - * @name Register I2S_TCSR, field FRDE[0] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_TCSR_FRDE (0U) /*!< Bit position for I2S_TCSR_FRDE. */ -#define BM_I2S_TCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */ -#define BS_I2S_TCSR_FRDE (1U) /*!< Bit field size in bits for I2S_TCSR_FRDE. */ - -/*! @brief Read current value of the I2S_TCSR_FRDE field. */ -#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE)) - -/*! @brief Format value for bitfield I2S_TCSR_FRDE. */ -#define BF_I2S_TCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE) - -/*! @brief Set the FRDE field to a new value. */ -#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FWDE[1] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_TCSR_FWDE (1U) /*!< Bit position for I2S_TCSR_FWDE. */ -#define BM_I2S_TCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */ -#define BS_I2S_TCSR_FWDE (1U) /*!< Bit field size in bits for I2S_TCSR_FWDE. */ - -/*! @brief Read current value of the I2S_TCSR_FWDE field. */ -#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE)) - -/*! @brief Format value for bitfield I2S_TCSR_FWDE. */ -#define BF_I2S_TCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE) - -/*! @brief Set the FWDE field to a new value. */ -#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FRIE[8] (RW) - * - * Enables/disables FIFO request interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_FRIE (8U) /*!< Bit position for I2S_TCSR_FRIE. */ -#define BM_I2S_TCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */ -#define BS_I2S_TCSR_FRIE (1U) /*!< Bit field size in bits for I2S_TCSR_FRIE. */ - -/*! @brief Read current value of the I2S_TCSR_FRIE field. */ -#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE)) - -/*! @brief Format value for bitfield I2S_TCSR_FRIE. */ -#define BF_I2S_TCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE) - -/*! @brief Set the FRIE field to a new value. */ -#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FWIE[9] (RW) - * - * Enables/disables FIFO warning interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_FWIE (9U) /*!< Bit position for I2S_TCSR_FWIE. */ -#define BM_I2S_TCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */ -#define BS_I2S_TCSR_FWIE (1U) /*!< Bit field size in bits for I2S_TCSR_FWIE. */ - -/*! @brief Read current value of the I2S_TCSR_FWIE field. */ -#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE)) - -/*! @brief Format value for bitfield I2S_TCSR_FWIE. */ -#define BF_I2S_TCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE) - -/*! @brief Set the FWIE field to a new value. */ -#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FEIE[10] (RW) - * - * Enables/disables FIFO error interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_FEIE (10U) /*!< Bit position for I2S_TCSR_FEIE. */ -#define BM_I2S_TCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */ -#define BS_I2S_TCSR_FEIE (1U) /*!< Bit field size in bits for I2S_TCSR_FEIE. */ - -/*! @brief Read current value of the I2S_TCSR_FEIE field. */ -#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE)) - -/*! @brief Format value for bitfield I2S_TCSR_FEIE. */ -#define BF_I2S_TCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field SEIE[11] (RW) - * - * Enables/disables sync error interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_SEIE (11U) /*!< Bit position for I2S_TCSR_SEIE. */ -#define BM_I2S_TCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */ -#define BS_I2S_TCSR_SEIE (1U) /*!< Bit field size in bits for I2S_TCSR_SEIE. */ - -/*! @brief Read current value of the I2S_TCSR_SEIE field. */ -#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE)) - -/*! @brief Format value for bitfield I2S_TCSR_SEIE. */ -#define BF_I2S_TCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE) - -/*! @brief Set the SEIE field to a new value. */ -#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field WSIE[12] (RW) - * - * Enables/disables word start interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_TCSR_WSIE (12U) /*!< Bit position for I2S_TCSR_WSIE. */ -#define BM_I2S_TCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */ -#define BS_I2S_TCSR_WSIE (1U) /*!< Bit field size in bits for I2S_TCSR_WSIE. */ - -/*! @brief Read current value of the I2S_TCSR_WSIE field. */ -#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE)) - -/*! @brief Format value for bitfield I2S_TCSR_WSIE. */ -#define BF_I2S_TCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE) - -/*! @brief Set the WSIE field to a new value. */ -#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FRF[16] (RO) - * - * Indicates that the number of words in an enabled transmit channel FIFO is - * less than or equal to the transmit FIFO watermark. - * - * Values: - * - 0 - Transmit FIFO watermark has not been reached. - * - 1 - Transmit FIFO watermark has been reached. - */ -/*@{*/ -#define BP_I2S_TCSR_FRF (16U) /*!< Bit position for I2S_TCSR_FRF. */ -#define BM_I2S_TCSR_FRF (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */ -#define BS_I2S_TCSR_FRF (1U) /*!< Bit field size in bits for I2S_TCSR_FRF. */ - -/*! @brief Read current value of the I2S_TCSR_FRF field. */ -#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FWF[17] (RO) - * - * Indicates that an enabled transmit FIFO is empty. - * - * Values: - * - 0 - No enabled transmit FIFO is empty. - * - 1 - Enabled transmit FIFO is empty. - */ -/*@{*/ -#define BP_I2S_TCSR_FWF (17U) /*!< Bit position for I2S_TCSR_FWF. */ -#define BM_I2S_TCSR_FWF (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */ -#define BS_I2S_TCSR_FWF (1U) /*!< Bit field size in bits for I2S_TCSR_FWF. */ - -/*! @brief Read current value of the I2S_TCSR_FWF field. */ -#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FEF[18] (W1C) - * - * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this - * field to clear this flag. - * - * Values: - * - 0 - Transmit underrun not detected. - * - 1 - Transmit underrun detected. - */ -/*@{*/ -#define BP_I2S_TCSR_FEF (18U) /*!< Bit position for I2S_TCSR_FEF. */ -#define BM_I2S_TCSR_FEF (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */ -#define BS_I2S_TCSR_FEF (1U) /*!< Bit field size in bits for I2S_TCSR_FEF. */ - -/*! @brief Read current value of the I2S_TCSR_FEF field. */ -#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF)) - -/*! @brief Format value for bitfield I2S_TCSR_FEF. */ -#define BF_I2S_TCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF) - -/*! @brief Set the FEF field to a new value. */ -#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field SEF[19] (W1C) - * - * Indicates that an error in the externally-generated frame sync has been - * detected. Write a logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Sync error not detected. - * - 1 - Frame sync error detected. - */ -/*@{*/ -#define BP_I2S_TCSR_SEF (19U) /*!< Bit position for I2S_TCSR_SEF. */ -#define BM_I2S_TCSR_SEF (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */ -#define BS_I2S_TCSR_SEF (1U) /*!< Bit field size in bits for I2S_TCSR_SEF. */ - -/*! @brief Read current value of the I2S_TCSR_SEF field. */ -#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF)) - -/*! @brief Format value for bitfield I2S_TCSR_SEF. */ -#define BF_I2S_TCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF) - -/*! @brief Set the SEF field to a new value. */ -#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field WSF[20] (W1C) - * - * Indicates that the start of the configured word has been detected. Write a - * logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Start of word not detected. - * - 1 - Start of word detected. - */ -/*@{*/ -#define BP_I2S_TCSR_WSF (20U) /*!< Bit position for I2S_TCSR_WSF. */ -#define BM_I2S_TCSR_WSF (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */ -#define BS_I2S_TCSR_WSF (1U) /*!< Bit field size in bits for I2S_TCSR_WSF. */ - -/*! @brief Read current value of the I2S_TCSR_WSF field. */ -#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF)) - -/*! @brief Format value for bitfield I2S_TCSR_WSF. */ -#define BF_I2S_TCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF) - -/*! @brief Set the WSF field to a new value. */ -#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field SR[24] (RW) - * - * When set, resets the internal transmitter logic including the FIFO pointers. - * Software-visible registers are not affected, except for the status registers. - * - * Values: - * - 0 - No effect. - * - 1 - Software reset. - */ -/*@{*/ -#define BP_I2S_TCSR_SR (24U) /*!< Bit position for I2S_TCSR_SR. */ -#define BM_I2S_TCSR_SR (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */ -#define BS_I2S_TCSR_SR (1U) /*!< Bit field size in bits for I2S_TCSR_SR. */ - -/*! @brief Read current value of the I2S_TCSR_SR field. */ -#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR)) - -/*! @brief Format value for bitfield I2S_TCSR_SR. */ -#define BF_I2S_TCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR) - -/*! @brief Set the SR field to a new value. */ -#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field FR[25] (WORZ) - * - * Resets the FIFO pointers. Reading this field will always return zero. FIFO - * pointers should only be reset when the transmitter is disabled or the FIFO error - * flag is set. - * - * Values: - * - 0 - No effect. - * - 1 - FIFO reset. - */ -/*@{*/ -#define BP_I2S_TCSR_FR (25U) /*!< Bit position for I2S_TCSR_FR. */ -#define BM_I2S_TCSR_FR (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */ -#define BS_I2S_TCSR_FR (1U) /*!< Bit field size in bits for I2S_TCSR_FR. */ - -/*! @brief Format value for bitfield I2S_TCSR_FR. */ -#define BF_I2S_TCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR) - -/*! @brief Set the FR field to a new value. */ -#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field BCE[28] (RW) - * - * Enables the transmit bit clock, separately from the TE. This field is - * automatically set whenever TE is set. When software clears this field, the transmit - * bit clock remains enabled, and this bit remains set, until the end of the - * current frame. - * - * Values: - * - 0 - Transmit bit clock is disabled. - * - 1 - Transmit bit clock is enabled. - */ -/*@{*/ -#define BP_I2S_TCSR_BCE (28U) /*!< Bit position for I2S_TCSR_BCE. */ -#define BM_I2S_TCSR_BCE (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */ -#define BS_I2S_TCSR_BCE (1U) /*!< Bit field size in bits for I2S_TCSR_BCE. */ - -/*! @brief Read current value of the I2S_TCSR_BCE field. */ -#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE)) - -/*! @brief Format value for bitfield I2S_TCSR_BCE. */ -#define BF_I2S_TCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE) - -/*! @brief Set the BCE field to a new value. */ -#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field DBGE[29] (RW) - * - * Enables/disables transmitter operation in Debug mode. The transmit bit clock - * is not affected by debug mode. - * - * Values: - * - 0 - Transmitter is disabled in Debug mode, after completing the current - * frame. - * - 1 - Transmitter is enabled in Debug mode. - */ -/*@{*/ -#define BP_I2S_TCSR_DBGE (29U) /*!< Bit position for I2S_TCSR_DBGE. */ -#define BM_I2S_TCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */ -#define BS_I2S_TCSR_DBGE (1U) /*!< Bit field size in bits for I2S_TCSR_DBGE. */ - -/*! @brief Read current value of the I2S_TCSR_DBGE field. */ -#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE)) - -/*! @brief Format value for bitfield I2S_TCSR_DBGE. */ -#define BF_I2S_TCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE) - -/*! @brief Set the DBGE field to a new value. */ -#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field STOPE[30] (RW) - * - * Configures transmitter operation in Stop mode. This field is ignored and the - * transmitter is disabled in all low-leakage stop modes. - * - * Values: - * - 0 - Transmitter disabled in Stop mode. - * - 1 - Transmitter enabled in Stop mode. - */ -/*@{*/ -#define BP_I2S_TCSR_STOPE (30U) /*!< Bit position for I2S_TCSR_STOPE. */ -#define BM_I2S_TCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */ -#define BS_I2S_TCSR_STOPE (1U) /*!< Bit field size in bits for I2S_TCSR_STOPE. */ - -/*! @brief Read current value of the I2S_TCSR_STOPE field. */ -#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE)) - -/*! @brief Format value for bitfield I2S_TCSR_STOPE. */ -#define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE) - -/*! @brief Set the STOPE field to a new value. */ -#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCSR, field TE[31] (RW) - * - * Enables/disables the transmitter. When software clears this field, the - * transmitter remains enabled, and this bit remains set, until the end of the current - * frame. - * - * Values: - * - 0 - Transmitter is disabled. - * - 1 - Transmitter is enabled, or transmitter has been disabled and has not - * yet reached end of frame. - */ -/*@{*/ -#define BP_I2S_TCSR_TE (31U) /*!< Bit position for I2S_TCSR_TE. */ -#define BM_I2S_TCSR_TE (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */ -#define BS_I2S_TCSR_TE (1U) /*!< Bit field size in bits for I2S_TCSR_TE. */ - -/*! @brief Read current value of the I2S_TCSR_TE field. */ -#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE)) - -/*! @brief Format value for bitfield I2S_TCSR_TE. */ -#define BF_I2S_TCSR_TE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE) - -/*! @brief Set the TE field to a new value. */ -#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tcr1 -{ - uint32_t U; - struct _hw_i2s_tcr1_bitfields - { - uint32_t TFW : 3; /*!< [2:0] Transmit FIFO Watermark */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_i2s_tcr1_t; - -/*! - * @name Constants and macros for entire I2S_TCR1 register - */ -/*@{*/ -#define HW_I2S_TCR1_ADDR(x) ((x) + 0x4U) - -#define HW_I2S_TCR1(x) (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x)) -#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U) -#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v)) -#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) | (v))) -#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v))) -#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR1 bitfields - */ - -/*! - * @name Register I2S_TCR1, field TFW[2:0] (RW) - * - * Configures the watermark level for all enabled transmit channels. - */ -/*@{*/ -#define BP_I2S_TCR1_TFW (0U) /*!< Bit position for I2S_TCR1_TFW. */ -#define BM_I2S_TCR1_TFW (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */ -#define BS_I2S_TCR1_TFW (3U) /*!< Bit field size in bits for I2S_TCR1_TFW. */ - -/*! @brief Read current value of the I2S_TCR1_TFW field. */ -#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW) - -/*! @brief Format value for bitfield I2S_TCR1_TFW. */ -#define BF_I2S_TCR1_TFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW) - -/*! @brief Set the TFW field to a new value. */ -#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr2 -{ - uint32_t U; - struct _hw_i2s_tcr2_bitfields - { - uint32_t DIV : 8; /*!< [7:0] Bit Clock Divide */ - uint32_t RESERVED0 : 16; /*!< [23:8] */ - uint32_t BCD : 1; /*!< [24] Bit Clock Direction */ - uint32_t BCP : 1; /*!< [25] Bit Clock Polarity */ - uint32_t MSEL : 2; /*!< [27:26] MCLK Select */ - uint32_t BCI : 1; /*!< [28] Bit Clock Input */ - uint32_t BCS : 1; /*!< [29] Bit Clock Swap */ - uint32_t SYNC : 2; /*!< [31:30] Synchronous Mode */ - } B; -} hw_i2s_tcr2_t; - -/*! - * @name Constants and macros for entire I2S_TCR2 register - */ -/*@{*/ -#define HW_I2S_TCR2_ADDR(x) ((x) + 0x8U) - -#define HW_I2S_TCR2(x) (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x)) -#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U) -#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v)) -#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) | (v))) -#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v))) -#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR2 bitfields - */ - -/*! - * @name Register I2S_TCR2, field DIV[7:0] (RW) - * - * Divides down the audio master clock to generate the bit clock when configured - * for an internal bit clock. The division value is (DIV + 1) * 2. - */ -/*@{*/ -#define BP_I2S_TCR2_DIV (0U) /*!< Bit position for I2S_TCR2_DIV. */ -#define BM_I2S_TCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */ -#define BS_I2S_TCR2_DIV (8U) /*!< Bit field size in bits for I2S_TCR2_DIV. */ - -/*! @brief Read current value of the I2S_TCR2_DIV field. */ -#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV) - -/*! @brief Format value for bitfield I2S_TCR2_DIV. */ -#define BF_I2S_TCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV) - -/*! @brief Set the DIV field to a new value. */ -#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCD[24] (RW) - * - * Configures the direction of the bit clock. - * - * Values: - * - 0 - Bit clock is generated externally in Slave mode. - * - 1 - Bit clock is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_TCR2_BCD (24U) /*!< Bit position for I2S_TCR2_BCD. */ -#define BM_I2S_TCR2_BCD (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */ -#define BS_I2S_TCR2_BCD (1U) /*!< Bit field size in bits for I2S_TCR2_BCD. */ - -/*! @brief Read current value of the I2S_TCR2_BCD field. */ -#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD)) - -/*! @brief Format value for bitfield I2S_TCR2_BCD. */ -#define BF_I2S_TCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD) - -/*! @brief Set the BCD field to a new value. */ -#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCP[25] (RW) - * - * Configures the polarity of the bit clock. - * - * Values: - * - 0 - Bit clock is active high with drive outputs on rising edge and sample - * inputs on falling edge. - * - 1 - Bit clock is active low with drive outputs on falling edge and sample - * inputs on rising edge. - */ -/*@{*/ -#define BP_I2S_TCR2_BCP (25U) /*!< Bit position for I2S_TCR2_BCP. */ -#define BM_I2S_TCR2_BCP (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */ -#define BS_I2S_TCR2_BCP (1U) /*!< Bit field size in bits for I2S_TCR2_BCP. */ - -/*! @brief Read current value of the I2S_TCR2_BCP field. */ -#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP)) - -/*! @brief Format value for bitfield I2S_TCR2_BCP. */ -#define BF_I2S_TCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP) - -/*! @brief Set the BCP field to a new value. */ -#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field MSEL[27:26] (RW) - * - * Selects the audio Master Clock option used to generate an internally - * generated bit clock. This field has no effect when configured for an externally - * generated bit clock. Depending on the device, some Master Clock options might not be - * available. See the chip configuration details for the availability and - * chip-specific meaning of each option. - * - * Values: - * - 00 - Bus Clock selected. - * - 01 - Master Clock (MCLK) 1 option selected. - * - 10 - Master Clock (MCLK) 2 option selected. - * - 11 - Master Clock (MCLK) 3 option selected. - */ -/*@{*/ -#define BP_I2S_TCR2_MSEL (26U) /*!< Bit position for I2S_TCR2_MSEL. */ -#define BM_I2S_TCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */ -#define BS_I2S_TCR2_MSEL (2U) /*!< Bit field size in bits for I2S_TCR2_MSEL. */ - -/*! @brief Read current value of the I2S_TCR2_MSEL field. */ -#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL) - -/*! @brief Format value for bitfield I2S_TCR2_MSEL. */ -#define BF_I2S_TCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL) - -/*! @brief Set the MSEL field to a new value. */ -#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCI[28] (RW) - * - * When this field is set and using an internally generated bit clock in either - * synchronous or asynchronous mode, the bit clock actually used by the - * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad - * input as if the clock was externally generated). This has the effect of - * decreasing the data input setup time, but increasing the data output valid time. The - * slave mode timing from the datasheet should be used for the transmitter when - * this bit is set. In synchronous mode, this bit allows the transmitter to use - * the slave mode timing from the datasheet, while the receiver uses the master - * mode timing. This field has no effect when configured for an externally generated - * bit clock or when synchronous to another SAI peripheral . - * - * Values: - * - 0 - No effect. - * - 1 - Internal logic is clocked as if bit clock was externally generated. - */ -/*@{*/ -#define BP_I2S_TCR2_BCI (28U) /*!< Bit position for I2S_TCR2_BCI. */ -#define BM_I2S_TCR2_BCI (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */ -#define BS_I2S_TCR2_BCI (1U) /*!< Bit field size in bits for I2S_TCR2_BCI. */ - -/*! @brief Read current value of the I2S_TCR2_BCI field. */ -#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI)) - -/*! @brief Format value for bitfield I2S_TCR2_BCI. */ -#define BF_I2S_TCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI) - -/*! @brief Set the BCI field to a new value. */ -#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field BCS[29] (RW) - * - * This field swaps the bit clock used by the transmitter. When the transmitter - * is configured in asynchronous mode and this bit is set, the transmitter is - * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and - * receiver to share the same bit clock, but the transmitter continues to use the - * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in - * synchronous mode, the transmitter BCS field and receiver BCS field must be set to - * the same value. When both are set, the transmitter and receiver are both - * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync - * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI - * peripheral. - * - * Values: - * - 0 - Use the normal bit clock source. - * - 1 - Swap the bit clock source. - */ -/*@{*/ -#define BP_I2S_TCR2_BCS (29U) /*!< Bit position for I2S_TCR2_BCS. */ -#define BM_I2S_TCR2_BCS (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */ -#define BS_I2S_TCR2_BCS (1U) /*!< Bit field size in bits for I2S_TCR2_BCS. */ - -/*! @brief Read current value of the I2S_TCR2_BCS field. */ -#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS)) - -/*! @brief Format value for bitfield I2S_TCR2_BCS. */ -#define BF_I2S_TCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS) - -/*! @brief Set the BCS field to a new value. */ -#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR2, field SYNC[31:30] (RW) - * - * Configures between asynchronous and synchronous modes of operation. When - * configured for a synchronous mode of operation, the receiver or other SAI - * peripheral must be configured for asynchronous operation. - * - * Values: - * - 00 - Asynchronous mode. - * - 01 - Synchronous with receiver. - * - 10 - Synchronous with another SAI transmitter. - * - 11 - Synchronous with another SAI receiver. - */ -/*@{*/ -#define BP_I2S_TCR2_SYNC (30U) /*!< Bit position for I2S_TCR2_SYNC. */ -#define BM_I2S_TCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */ -#define BS_I2S_TCR2_SYNC (2U) /*!< Bit field size in bits for I2S_TCR2_SYNC. */ - -/*! @brief Read current value of the I2S_TCR2_SYNC field. */ -#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC) - -/*! @brief Format value for bitfield I2S_TCR2_SYNC. */ -#define BF_I2S_TCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC) - -/*! @brief Set the SYNC field to a new value. */ -#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr3 -{ - uint32_t U; - struct _hw_i2s_tcr3_bitfields - { - uint32_t WDFL : 5; /*!< [4:0] Word Flag Configuration */ - uint32_t RESERVED0 : 11; /*!< [15:5] */ - uint32_t TCE : 2; /*!< [17:16] Transmit Channel Enable */ - uint32_t RESERVED1 : 14; /*!< [31:18] */ - } B; -} hw_i2s_tcr3_t; - -/*! - * @name Constants and macros for entire I2S_TCR3 register - */ -/*@{*/ -#define HW_I2S_TCR3_ADDR(x) ((x) + 0xCU) - -#define HW_I2S_TCR3(x) (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x)) -#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U) -#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v)) -#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) | (v))) -#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v))) -#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR3 bitfields - */ - -/*! - * @name Register I2S_TCR3, field WDFL[4:0] (RW) - * - * Configures which word sets the start of word flag. The value written must be - * one less than the word number. For example, writing 0 configures the first - * word in the frame. When configured to a value greater than TCR4[FRSZ], then the - * start of word flag is never set. - */ -/*@{*/ -#define BP_I2S_TCR3_WDFL (0U) /*!< Bit position for I2S_TCR3_WDFL. */ -#define BM_I2S_TCR3_WDFL (0x0000001FU) /*!< Bit mask for I2S_TCR3_WDFL. */ -#define BS_I2S_TCR3_WDFL (5U) /*!< Bit field size in bits for I2S_TCR3_WDFL. */ - -/*! @brief Read current value of the I2S_TCR3_WDFL field. */ -#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL) - -/*! @brief Format value for bitfield I2S_TCR3_WDFL. */ -#define BF_I2S_TCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL) - -/*! @brief Set the WDFL field to a new value. */ -#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR3, field TCE[17:16] (RW) - * - * Enables the corresponding data channel for transmit operation. A channel must - * be enabled before its FIFO is accessed. - * - * Values: - * - 0 - Transmit data channel N is disabled. - * - 1 - Transmit data channel N is enabled. - */ -/*@{*/ -#define BP_I2S_TCR3_TCE (16U) /*!< Bit position for I2S_TCR3_TCE. */ -#define BM_I2S_TCR3_TCE (0x00030000U) /*!< Bit mask for I2S_TCR3_TCE. */ -#define BS_I2S_TCR3_TCE (2U) /*!< Bit field size in bits for I2S_TCR3_TCE. */ - -/*! @brief Read current value of the I2S_TCR3_TCE field. */ -#define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE) - -/*! @brief Format value for bitfield I2S_TCR3_TCE. */ -#define BF_I2S_TCR3_TCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE) - -/*! @brief Set the TCE field to a new value. */ -#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr4 -{ - uint32_t U; - struct _hw_i2s_tcr4_bitfields - { - uint32_t FSD : 1; /*!< [0] Frame Sync Direction */ - uint32_t FSP : 1; /*!< [1] Frame Sync Polarity */ - uint32_t RESERVED0 : 1; /*!< [2] */ - uint32_t FSE : 1; /*!< [3] Frame Sync Early */ - uint32_t MF : 1; /*!< [4] MSB First */ - uint32_t RESERVED1 : 3; /*!< [7:5] */ - uint32_t SYWD : 5; /*!< [12:8] Sync Width */ - uint32_t RESERVED2 : 3; /*!< [15:13] */ - uint32_t FRSZ : 5; /*!< [20:16] Frame size */ - uint32_t RESERVED3 : 11; /*!< [31:21] */ - } B; -} hw_i2s_tcr4_t; - -/*! - * @name Constants and macros for entire I2S_TCR4 register - */ -/*@{*/ -#define HW_I2S_TCR4_ADDR(x) ((x) + 0x10U) - -#define HW_I2S_TCR4(x) (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x)) -#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U) -#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v)) -#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) | (v))) -#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v))) -#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR4 bitfields - */ - -/*! - * @name Register I2S_TCR4, field FSD[0] (RW) - * - * Configures the direction of the frame sync. - * - * Values: - * - 0 - Frame sync is generated externally in Slave mode. - * - 1 - Frame sync is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_TCR4_FSD (0U) /*!< Bit position for I2S_TCR4_FSD. */ -#define BM_I2S_TCR4_FSD (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */ -#define BS_I2S_TCR4_FSD (1U) /*!< Bit field size in bits for I2S_TCR4_FSD. */ - -/*! @brief Read current value of the I2S_TCR4_FSD field. */ -#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD)) - -/*! @brief Format value for bitfield I2S_TCR4_FSD. */ -#define BF_I2S_TCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD) - -/*! @brief Set the FSD field to a new value. */ -#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FSP[1] (RW) - * - * Configures the polarity of the frame sync. - * - * Values: - * - 0 - Frame sync is active high. - * - 1 - Frame sync is active low. - */ -/*@{*/ -#define BP_I2S_TCR4_FSP (1U) /*!< Bit position for I2S_TCR4_FSP. */ -#define BM_I2S_TCR4_FSP (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */ -#define BS_I2S_TCR4_FSP (1U) /*!< Bit field size in bits for I2S_TCR4_FSP. */ - -/*! @brief Read current value of the I2S_TCR4_FSP field. */ -#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP)) - -/*! @brief Format value for bitfield I2S_TCR4_FSP. */ -#define BF_I2S_TCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP) - -/*! @brief Set the FSP field to a new value. */ -#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FSE[3] (RW) - * - * Values: - * - 0 - Frame sync asserts with the first bit of the frame. - * - 1 - Frame sync asserts one bit before the first bit of the frame. - */ -/*@{*/ -#define BP_I2S_TCR4_FSE (3U) /*!< Bit position for I2S_TCR4_FSE. */ -#define BM_I2S_TCR4_FSE (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */ -#define BS_I2S_TCR4_FSE (1U) /*!< Bit field size in bits for I2S_TCR4_FSE. */ - -/*! @brief Read current value of the I2S_TCR4_FSE field. */ -#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE)) - -/*! @brief Format value for bitfield I2S_TCR4_FSE. */ -#define BF_I2S_TCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE) - -/*! @brief Set the FSE field to a new value. */ -#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field MF[4] (RW) - * - * Configures whether the LSB or the MSB is transmitted first. - * - * Values: - * - 0 - LSB is transmitted first. - * - 1 - MSB is transmitted first. - */ -/*@{*/ -#define BP_I2S_TCR4_MF (4U) /*!< Bit position for I2S_TCR4_MF. */ -#define BM_I2S_TCR4_MF (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */ -#define BS_I2S_TCR4_MF (1U) /*!< Bit field size in bits for I2S_TCR4_MF. */ - -/*! @brief Read current value of the I2S_TCR4_MF field. */ -#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF)) - -/*! @brief Format value for bitfield I2S_TCR4_MF. */ -#define BF_I2S_TCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF) - -/*! @brief Set the MF field to a new value. */ -#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field SYWD[12:8] (RW) - * - * Configures the length of the frame sync in number of bit clocks. The value - * written must be one less than the number of bit clocks. For example, write 0 for - * the frame sync to assert for one bit clock only. The sync width cannot be - * configured longer than the first word of the frame. - */ -/*@{*/ -#define BP_I2S_TCR4_SYWD (8U) /*!< Bit position for I2S_TCR4_SYWD. */ -#define BM_I2S_TCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */ -#define BS_I2S_TCR4_SYWD (5U) /*!< Bit field size in bits for I2S_TCR4_SYWD. */ - -/*! @brief Read current value of the I2S_TCR4_SYWD field. */ -#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD) - -/*! @brief Format value for bitfield I2S_TCR4_SYWD. */ -#define BF_I2S_TCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD) - -/*! @brief Set the SYWD field to a new value. */ -#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR4, field FRSZ[20:16] (RW) - * - * Configures the number of words in each frame. The value written must be one - * less than the number of words in the frame. For example, write 0 for one word - * per frame. The maximum supported frame size is 32 words. - */ -/*@{*/ -#define BP_I2S_TCR4_FRSZ (16U) /*!< Bit position for I2S_TCR4_FRSZ. */ -#define BM_I2S_TCR4_FRSZ (0x001F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */ -#define BS_I2S_TCR4_FRSZ (5U) /*!< Bit field size in bits for I2S_TCR4_FRSZ. */ - -/*! @brief Read current value of the I2S_TCR4_FRSZ field. */ -#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ) - -/*! @brief Format value for bitfield I2S_TCR4_FRSZ. */ -#define BF_I2S_TCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ) - -/*! @brief Set the FRSZ field to a new value. */ -#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when TCSR[TE] is set. - */ -typedef union _hw_i2s_tcr5 -{ - uint32_t U; - struct _hw_i2s_tcr5_bitfields - { - uint32_t RESERVED0 : 8; /*!< [7:0] */ - uint32_t FBT : 5; /*!< [12:8] First Bit Shifted */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t W0W : 5; /*!< [20:16] Word 0 Width */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t WNW : 5; /*!< [28:24] Word N Width */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_i2s_tcr5_t; - -/*! - * @name Constants and macros for entire I2S_TCR5 register - */ -/*@{*/ -#define HW_I2S_TCR5_ADDR(x) ((x) + 0x14U) - -#define HW_I2S_TCR5(x) (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x)) -#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U) -#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v)) -#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) | (v))) -#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v))) -#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TCR5 bitfields - */ - -/*! - * @name Register I2S_TCR5, field FBT[12:8] (RW) - * - * Configures the bit index for the first bit transmitted for each word in the - * frame. If configured for MSB First, the index of the next bit transmitted is - * one less than the current bit transmitted. If configured for LSB First, the - * index of the next bit transmitted is one more than the current bit transmitted. - * The value written must be greater than or equal to the word width when - * configured for MSB First. The value written must be less than or equal to 31-word width - * when configured for LSB First. - */ -/*@{*/ -#define BP_I2S_TCR5_FBT (8U) /*!< Bit position for I2S_TCR5_FBT. */ -#define BM_I2S_TCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */ -#define BS_I2S_TCR5_FBT (5U) /*!< Bit field size in bits for I2S_TCR5_FBT. */ - -/*! @brief Read current value of the I2S_TCR5_FBT field. */ -#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT) - -/*! @brief Format value for bitfield I2S_TCR5_FBT. */ -#define BF_I2S_TCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT) - -/*! @brief Set the FBT field to a new value. */ -#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR5, field W0W[20:16] (RW) - * - * Configures the number of bits in the first word in each frame. The value - * written must be one less than the number of bits in the first word. Word width of - * less than 8 bits is not supported if there is only one word per frame. - */ -/*@{*/ -#define BP_I2S_TCR5_W0W (16U) /*!< Bit position for I2S_TCR5_W0W. */ -#define BM_I2S_TCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */ -#define BS_I2S_TCR5_W0W (5U) /*!< Bit field size in bits for I2S_TCR5_W0W. */ - -/*! @brief Read current value of the I2S_TCR5_W0W field. */ -#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W) - -/*! @brief Format value for bitfield I2S_TCR5_W0W. */ -#define BF_I2S_TCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W) - -/*! @brief Set the W0W field to a new value. */ -#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v))) -/*@}*/ - -/*! - * @name Register I2S_TCR5, field WNW[28:24] (RW) - * - * Configures the number of bits in each word, for each word except the first in - * the frame. The value written must be one less than the number of bits per - * word. Word width of less than 8 bits is not supported. - */ -/*@{*/ -#define BP_I2S_TCR5_WNW (24U) /*!< Bit position for I2S_TCR5_WNW. */ -#define BM_I2S_TCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */ -#define BS_I2S_TCR5_WNW (5U) /*!< Bit field size in bits for I2S_TCR5_WNW. */ - -/*! @brief Read current value of the I2S_TCR5_WNW field. */ -#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW) - -/*! @brief Format value for bitfield I2S_TCR5_WNW. */ -#define BF_I2S_TCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW) - -/*! @brief Set the WNW field to a new value. */ -#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TDRn - SAI Transmit Data Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_tdrn -{ - uint32_t U; - struct _hw_i2s_tdrn_bitfields - { - uint32_t TDR : 32; /*!< [31:0] Transmit Data Register */ - } B; -} hw_i2s_tdrn_t; - -/*! - * @name Constants and macros for entire I2S_TDRn register - */ -/*@{*/ -#define HW_I2S_TDRn_COUNT (2U) - -#define HW_I2S_TDRn_ADDR(x, n) ((x) + 0x20U + (0x4U * (n))) - -#define HW_I2S_TDRn(x, n) (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n)) -#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U) -#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual I2S_TDRn bitfields - */ - -/*! - * @name Register I2S_TDRn, field TDR[31:0] (WORZ) - * - * The corresponding TCR3[TCE] bit must be set before accessing the channel's - * transmit data register. Writes to this register when the transmit FIFO is not - * full will push the data written into the transmit data FIFO. Writes to this - * register when the transmit FIFO is full are ignored. - */ -/*@{*/ -#define BP_I2S_TDRn_TDR (0U) /*!< Bit position for I2S_TDRn_TDR. */ -#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */ -#define BS_I2S_TDRn_TDR (32U) /*!< Bit field size in bits for I2S_TDRn_TDR. */ - -/*! @brief Format value for bitfield I2S_TDRn_TDR. */ -#define BF_I2S_TDRn_TDR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR) - -/*! @brief Set the TDR field to a new value. */ -#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TFRn - SAI Transmit FIFO Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO) - * - * Reset value: 0x00000000U - * - * The MSB of the read and write pointers is used to distinguish between FIFO - * full and empty conditions. If the read and write pointers are identical, then - * the FIFO is empty. If the read and write pointers are identical except for the - * MSB, then the FIFO is full. - */ -typedef union _hw_i2s_tfrn -{ - uint32_t U; - struct _hw_i2s_tfrn_bitfields - { - uint32_t RFP : 4; /*!< [3:0] Read FIFO Pointer */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t WFP : 4; /*!< [19:16] Write FIFO Pointer */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_i2s_tfrn_t; - -/*! - * @name Constants and macros for entire I2S_TFRn register - */ -/*@{*/ -#define HW_I2S_TFRn_COUNT (2U) - -#define HW_I2S_TFRn_ADDR(x, n) ((x) + 0x40U + (0x4U * (n))) - -#define HW_I2S_TFRn(x, n) (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n)) -#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual I2S_TFRn bitfields - */ - -/*! - * @name Register I2S_TFRn, field RFP[3:0] (RO) - * - * FIFO read pointer for transmit data channel. - */ -/*@{*/ -#define BP_I2S_TFRn_RFP (0U) /*!< Bit position for I2S_TFRn_RFP. */ -#define BM_I2S_TFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */ -#define BS_I2S_TFRn_RFP (4U) /*!< Bit field size in bits for I2S_TFRn_RFP. */ - -/*! @brief Read current value of the I2S_TFRn_RFP field. */ -#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP) -/*@}*/ - -/*! - * @name Register I2S_TFRn, field WFP[19:16] (RO) - * - * FIFO write pointer for transmit data channel. - */ -/*@{*/ -#define BP_I2S_TFRn_WFP (16U) /*!< Bit position for I2S_TFRn_WFP. */ -#define BM_I2S_TFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */ -#define BS_I2S_TFRn_WFP (4U) /*!< Bit field size in bits for I2S_TFRn_WFP. */ - -/*! @brief Read current value of the I2S_TFRn_WFP field. */ -#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP) -/*@}*/ - -/******************************************************************************* - * HW_I2S_TMR - SAI Transmit Mask Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW) - * - * Reset value: 0x00000000U - * - * This register is double-buffered and updates: When TCSR[TE] is first set At - * the end of each frame. This allows the masked words in each frame to change - * from frame to frame. - */ -typedef union _hw_i2s_tmr -{ - uint32_t U; - struct _hw_i2s_tmr_bitfields - { - uint32_t TWM : 32; /*!< [31:0] Transmit Word Mask */ - } B; -} hw_i2s_tmr_t; - -/*! - * @name Constants and macros for entire I2S_TMR register - */ -/*@{*/ -#define HW_I2S_TMR_ADDR(x) ((x) + 0x60U) - -#define HW_I2S_TMR(x) (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x)) -#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U) -#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v)) -#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) | (v))) -#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v))) -#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_TMR bitfields - */ - -/*! - * @name Register I2S_TMR, field TWM[31:0] (RW) - * - * Configures whether the transmit word is masked (transmit data pin tristated - * and transmit data not read from FIFO) for the corresponding word in the frame. - * - * Values: - * - 0 - Word N is enabled. - * - 1 - Word N is masked. The transmit data pins are tri-stated when masked. - */ -/*@{*/ -#define BP_I2S_TMR_TWM (0U) /*!< Bit position for I2S_TMR_TWM. */ -#define BM_I2S_TMR_TWM (0xFFFFFFFFU) /*!< Bit mask for I2S_TMR_TWM. */ -#define BS_I2S_TMR_TWM (32U) /*!< Bit field size in bits for I2S_TMR_TWM. */ - -/*! @brief Read current value of the I2S_TMR_TWM field. */ -#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U) - -/*! @brief Format value for bitfield I2S_TMR_TWM. */ -#define BF_I2S_TMR_TWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM) - -/*! @brief Set the TWM field to a new value. */ -#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCSR - SAI Receive Control Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCSR - SAI Receive Control Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_rcsr -{ - uint32_t U; - struct _hw_i2s_rcsr_bitfields - { - uint32_t FRDE : 1; /*!< [0] FIFO Request DMA Enable */ - uint32_t FWDE : 1; /*!< [1] FIFO Warning DMA Enable */ - uint32_t RESERVED0 : 6; /*!< [7:2] */ - uint32_t FRIE : 1; /*!< [8] FIFO Request Interrupt Enable */ - uint32_t FWIE : 1; /*!< [9] FIFO Warning Interrupt Enable */ - uint32_t FEIE : 1; /*!< [10] FIFO Error Interrupt Enable */ - uint32_t SEIE : 1; /*!< [11] Sync Error Interrupt Enable */ - uint32_t WSIE : 1; /*!< [12] Word Start Interrupt Enable */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t FRF : 1; /*!< [16] FIFO Request Flag */ - uint32_t FWF : 1; /*!< [17] FIFO Warning Flag */ - uint32_t FEF : 1; /*!< [18] FIFO Error Flag */ - uint32_t SEF : 1; /*!< [19] Sync Error Flag */ - uint32_t WSF : 1; /*!< [20] Word Start Flag */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t SR : 1; /*!< [24] Software Reset */ - uint32_t FR : 1; /*!< [25] FIFO Reset */ - uint32_t RESERVED3 : 2; /*!< [27:26] */ - uint32_t BCE : 1; /*!< [28] Bit Clock Enable */ - uint32_t DBGE : 1; /*!< [29] Debug Enable */ - uint32_t STOPE : 1; /*!< [30] Stop Enable */ - uint32_t RE : 1; /*!< [31] Receiver Enable */ - } B; -} hw_i2s_rcsr_t; - -/*! - * @name Constants and macros for entire I2S_RCSR register - */ -/*@{*/ -#define HW_I2S_RCSR_ADDR(x) ((x) + 0x80U) - -#define HW_I2S_RCSR(x) (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x)) -#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U) -#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v)) -#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) | (v))) -#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v))) -#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCSR bitfields - */ - -/*! - * @name Register I2S_RCSR, field FRDE[0] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_RCSR_FRDE (0U) /*!< Bit position for I2S_RCSR_FRDE. */ -#define BM_I2S_RCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */ -#define BS_I2S_RCSR_FRDE (1U) /*!< Bit field size in bits for I2S_RCSR_FRDE. */ - -/*! @brief Read current value of the I2S_RCSR_FRDE field. */ -#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE)) - -/*! @brief Format value for bitfield I2S_RCSR_FRDE. */ -#define BF_I2S_RCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE) - -/*! @brief Set the FRDE field to a new value. */ -#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FWDE[1] (RW) - * - * Enables/disables DMA requests. - * - * Values: - * - 0 - Disables the DMA request. - * - 1 - Enables the DMA request. - */ -/*@{*/ -#define BP_I2S_RCSR_FWDE (1U) /*!< Bit position for I2S_RCSR_FWDE. */ -#define BM_I2S_RCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */ -#define BS_I2S_RCSR_FWDE (1U) /*!< Bit field size in bits for I2S_RCSR_FWDE. */ - -/*! @brief Read current value of the I2S_RCSR_FWDE field. */ -#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE)) - -/*! @brief Format value for bitfield I2S_RCSR_FWDE. */ -#define BF_I2S_RCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE) - -/*! @brief Set the FWDE field to a new value. */ -#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FRIE[8] (RW) - * - * Enables/disables FIFO request interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_FRIE (8U) /*!< Bit position for I2S_RCSR_FRIE. */ -#define BM_I2S_RCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */ -#define BS_I2S_RCSR_FRIE (1U) /*!< Bit field size in bits for I2S_RCSR_FRIE. */ - -/*! @brief Read current value of the I2S_RCSR_FRIE field. */ -#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE)) - -/*! @brief Format value for bitfield I2S_RCSR_FRIE. */ -#define BF_I2S_RCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE) - -/*! @brief Set the FRIE field to a new value. */ -#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FWIE[9] (RW) - * - * Enables/disables FIFO warning interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_FWIE (9U) /*!< Bit position for I2S_RCSR_FWIE. */ -#define BM_I2S_RCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */ -#define BS_I2S_RCSR_FWIE (1U) /*!< Bit field size in bits for I2S_RCSR_FWIE. */ - -/*! @brief Read current value of the I2S_RCSR_FWIE field. */ -#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE)) - -/*! @brief Format value for bitfield I2S_RCSR_FWIE. */ -#define BF_I2S_RCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE) - -/*! @brief Set the FWIE field to a new value. */ -#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FEIE[10] (RW) - * - * Enables/disables FIFO error interrupts. - * - * Values: - * - 0 - Disables the interrupt. - * - 1 - Enables the interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_FEIE (10U) /*!< Bit position for I2S_RCSR_FEIE. */ -#define BM_I2S_RCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */ -#define BS_I2S_RCSR_FEIE (1U) /*!< Bit field size in bits for I2S_RCSR_FEIE. */ - -/*! @brief Read current value of the I2S_RCSR_FEIE field. */ -#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE)) - -/*! @brief Format value for bitfield I2S_RCSR_FEIE. */ -#define BF_I2S_RCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field SEIE[11] (RW) - * - * Enables/disables sync error interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_SEIE (11U) /*!< Bit position for I2S_RCSR_SEIE. */ -#define BM_I2S_RCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */ -#define BS_I2S_RCSR_SEIE (1U) /*!< Bit field size in bits for I2S_RCSR_SEIE. */ - -/*! @brief Read current value of the I2S_RCSR_SEIE field. */ -#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE)) - -/*! @brief Format value for bitfield I2S_RCSR_SEIE. */ -#define BF_I2S_RCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE) - -/*! @brief Set the SEIE field to a new value. */ -#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field WSIE[12] (RW) - * - * Enables/disables word start interrupts. - * - * Values: - * - 0 - Disables interrupt. - * - 1 - Enables interrupt. - */ -/*@{*/ -#define BP_I2S_RCSR_WSIE (12U) /*!< Bit position for I2S_RCSR_WSIE. */ -#define BM_I2S_RCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */ -#define BS_I2S_RCSR_WSIE (1U) /*!< Bit field size in bits for I2S_RCSR_WSIE. */ - -/*! @brief Read current value of the I2S_RCSR_WSIE field. */ -#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE)) - -/*! @brief Format value for bitfield I2S_RCSR_WSIE. */ -#define BF_I2S_RCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE) - -/*! @brief Set the WSIE field to a new value. */ -#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FRF[16] (RO) - * - * Indicates that the number of words in an enabled receive channel FIFO is - * greater than the receive FIFO watermark. - * - * Values: - * - 0 - Receive FIFO watermark not reached. - * - 1 - Receive FIFO watermark has been reached. - */ -/*@{*/ -#define BP_I2S_RCSR_FRF (16U) /*!< Bit position for I2S_RCSR_FRF. */ -#define BM_I2S_RCSR_FRF (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */ -#define BS_I2S_RCSR_FRF (1U) /*!< Bit field size in bits for I2S_RCSR_FRF. */ - -/*! @brief Read current value of the I2S_RCSR_FRF field. */ -#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FWF[17] (RO) - * - * Indicates that an enabled receive FIFO is full. - * - * Values: - * - 0 - No enabled receive FIFO is full. - * - 1 - Enabled receive FIFO is full. - */ -/*@{*/ -#define BP_I2S_RCSR_FWF (17U) /*!< Bit position for I2S_RCSR_FWF. */ -#define BM_I2S_RCSR_FWF (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */ -#define BS_I2S_RCSR_FWF (1U) /*!< Bit field size in bits for I2S_RCSR_FWF. */ - -/*! @brief Read current value of the I2S_RCSR_FWF field. */ -#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FEF[18] (W1C) - * - * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to - * this field to clear this flag. - * - * Values: - * - 0 - Receive overflow not detected. - * - 1 - Receive overflow detected. - */ -/*@{*/ -#define BP_I2S_RCSR_FEF (18U) /*!< Bit position for I2S_RCSR_FEF. */ -#define BM_I2S_RCSR_FEF (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */ -#define BS_I2S_RCSR_FEF (1U) /*!< Bit field size in bits for I2S_RCSR_FEF. */ - -/*! @brief Read current value of the I2S_RCSR_FEF field. */ -#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF)) - -/*! @brief Format value for bitfield I2S_RCSR_FEF. */ -#define BF_I2S_RCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF) - -/*! @brief Set the FEF field to a new value. */ -#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field SEF[19] (W1C) - * - * Indicates that an error in the externally-generated frame sync has been - * detected. Write a logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Sync error not detected. - * - 1 - Frame sync error detected. - */ -/*@{*/ -#define BP_I2S_RCSR_SEF (19U) /*!< Bit position for I2S_RCSR_SEF. */ -#define BM_I2S_RCSR_SEF (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */ -#define BS_I2S_RCSR_SEF (1U) /*!< Bit field size in bits for I2S_RCSR_SEF. */ - -/*! @brief Read current value of the I2S_RCSR_SEF field. */ -#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF)) - -/*! @brief Format value for bitfield I2S_RCSR_SEF. */ -#define BF_I2S_RCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF) - -/*! @brief Set the SEF field to a new value. */ -#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field WSF[20] (W1C) - * - * Indicates that the start of the configured word has been detected. Write a - * logic 1 to this field to clear this flag. - * - * Values: - * - 0 - Start of word not detected. - * - 1 - Start of word detected. - */ -/*@{*/ -#define BP_I2S_RCSR_WSF (20U) /*!< Bit position for I2S_RCSR_WSF. */ -#define BM_I2S_RCSR_WSF (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */ -#define BS_I2S_RCSR_WSF (1U) /*!< Bit field size in bits for I2S_RCSR_WSF. */ - -/*! @brief Read current value of the I2S_RCSR_WSF field. */ -#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF)) - -/*! @brief Format value for bitfield I2S_RCSR_WSF. */ -#define BF_I2S_RCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF) - -/*! @brief Set the WSF field to a new value. */ -#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field SR[24] (RW) - * - * Resets the internal receiver logic including the FIFO pointers. - * Software-visible registers are not affected, except for the status registers. - * - * Values: - * - 0 - No effect. - * - 1 - Software reset. - */ -/*@{*/ -#define BP_I2S_RCSR_SR (24U) /*!< Bit position for I2S_RCSR_SR. */ -#define BM_I2S_RCSR_SR (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */ -#define BS_I2S_RCSR_SR (1U) /*!< Bit field size in bits for I2S_RCSR_SR. */ - -/*! @brief Read current value of the I2S_RCSR_SR field. */ -#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR)) - -/*! @brief Format value for bitfield I2S_RCSR_SR. */ -#define BF_I2S_RCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR) - -/*! @brief Set the SR field to a new value. */ -#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field FR[25] (WORZ) - * - * Resets the FIFO pointers. Reading this field will always return zero. FIFO - * pointers should only be reset when the receiver is disabled or the FIFO error - * flag is set. - * - * Values: - * - 0 - No effect. - * - 1 - FIFO reset. - */ -/*@{*/ -#define BP_I2S_RCSR_FR (25U) /*!< Bit position for I2S_RCSR_FR. */ -#define BM_I2S_RCSR_FR (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */ -#define BS_I2S_RCSR_FR (1U) /*!< Bit field size in bits for I2S_RCSR_FR. */ - -/*! @brief Format value for bitfield I2S_RCSR_FR. */ -#define BF_I2S_RCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR) - -/*! @brief Set the FR field to a new value. */ -#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field BCE[28] (RW) - * - * Enables the receive bit clock, separately from RE. This field is - * automatically set whenever RE is set. When software clears this field, the receive bit - * clock remains enabled, and this field remains set, until the end of the current - * frame. - * - * Values: - * - 0 - Receive bit clock is disabled. - * - 1 - Receive bit clock is enabled. - */ -/*@{*/ -#define BP_I2S_RCSR_BCE (28U) /*!< Bit position for I2S_RCSR_BCE. */ -#define BM_I2S_RCSR_BCE (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */ -#define BS_I2S_RCSR_BCE (1U) /*!< Bit field size in bits for I2S_RCSR_BCE. */ - -/*! @brief Read current value of the I2S_RCSR_BCE field. */ -#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE)) - -/*! @brief Format value for bitfield I2S_RCSR_BCE. */ -#define BF_I2S_RCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE) - -/*! @brief Set the BCE field to a new value. */ -#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field DBGE[29] (RW) - * - * Enables/disables receiver operation in Debug mode. The receive bit clock is - * not affected by Debug mode. - * - * Values: - * - 0 - Receiver is disabled in Debug mode, after completing the current frame. - * - 1 - Receiver is enabled in Debug mode. - */ -/*@{*/ -#define BP_I2S_RCSR_DBGE (29U) /*!< Bit position for I2S_RCSR_DBGE. */ -#define BM_I2S_RCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */ -#define BS_I2S_RCSR_DBGE (1U) /*!< Bit field size in bits for I2S_RCSR_DBGE. */ - -/*! @brief Read current value of the I2S_RCSR_DBGE field. */ -#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE)) - -/*! @brief Format value for bitfield I2S_RCSR_DBGE. */ -#define BF_I2S_RCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE) - -/*! @brief Set the DBGE field to a new value. */ -#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field STOPE[30] (RW) - * - * Configures receiver operation in Stop mode. This bit is ignored and the - * receiver is disabled in all low-leakage stop modes. - * - * Values: - * - 0 - Receiver disabled in Stop mode. - * - 1 - Receiver enabled in Stop mode. - */ -/*@{*/ -#define BP_I2S_RCSR_STOPE (30U) /*!< Bit position for I2S_RCSR_STOPE. */ -#define BM_I2S_RCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */ -#define BS_I2S_RCSR_STOPE (1U) /*!< Bit field size in bits for I2S_RCSR_STOPE. */ - -/*! @brief Read current value of the I2S_RCSR_STOPE field. */ -#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE)) - -/*! @brief Format value for bitfield I2S_RCSR_STOPE. */ -#define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE) - -/*! @brief Set the STOPE field to a new value. */ -#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCSR, field RE[31] (RW) - * - * Enables/disables the receiver. When software clears this field, the receiver - * remains enabled, and this bit remains set, until the end of the current frame. - * - * Values: - * - 0 - Receiver is disabled. - * - 1 - Receiver is enabled, or receiver has been disabled and has not yet - * reached end of frame. - */ -/*@{*/ -#define BP_I2S_RCSR_RE (31U) /*!< Bit position for I2S_RCSR_RE. */ -#define BM_I2S_RCSR_RE (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */ -#define BS_I2S_RCSR_RE (1U) /*!< Bit field size in bits for I2S_RCSR_RE. */ - -/*! @brief Read current value of the I2S_RCSR_RE field. */ -#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE)) - -/*! @brief Format value for bitfield I2S_RCSR_RE. */ -#define BF_I2S_RCSR_RE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE) - -/*! @brief Set the RE field to a new value. */ -#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR1 - SAI Receive Configuration 1 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_i2s_rcr1 -{ - uint32_t U; - struct _hw_i2s_rcr1_bitfields - { - uint32_t RFW : 3; /*!< [2:0] Receive FIFO Watermark */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_i2s_rcr1_t; - -/*! - * @name Constants and macros for entire I2S_RCR1 register - */ -/*@{*/ -#define HW_I2S_RCR1_ADDR(x) ((x) + 0x84U) - -#define HW_I2S_RCR1(x) (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x)) -#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U) -#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v)) -#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) | (v))) -#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v))) -#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR1 bitfields - */ - -/*! - * @name Register I2S_RCR1, field RFW[2:0] (RW) - * - * Configures the watermark level for all enabled receiver channels. - */ -/*@{*/ -#define BP_I2S_RCR1_RFW (0U) /*!< Bit position for I2S_RCR1_RFW. */ -#define BM_I2S_RCR1_RFW (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */ -#define BS_I2S_RCR1_RFW (3U) /*!< Bit field size in bits for I2S_RCR1_RFW. */ - -/*! @brief Read current value of the I2S_RCR1_RFW field. */ -#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW) - -/*! @brief Format value for bitfield I2S_RCR1_RFW. */ -#define BF_I2S_RCR1_RFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW) - -/*! @brief Set the RFW field to a new value. */ -#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR2 - SAI Receive Configuration 2 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr2 -{ - uint32_t U; - struct _hw_i2s_rcr2_bitfields - { - uint32_t DIV : 8; /*!< [7:0] Bit Clock Divide */ - uint32_t RESERVED0 : 16; /*!< [23:8] */ - uint32_t BCD : 1; /*!< [24] Bit Clock Direction */ - uint32_t BCP : 1; /*!< [25] Bit Clock Polarity */ - uint32_t MSEL : 2; /*!< [27:26] MCLK Select */ - uint32_t BCI : 1; /*!< [28] Bit Clock Input */ - uint32_t BCS : 1; /*!< [29] Bit Clock Swap */ - uint32_t SYNC : 2; /*!< [31:30] Synchronous Mode */ - } B; -} hw_i2s_rcr2_t; - -/*! - * @name Constants and macros for entire I2S_RCR2 register - */ -/*@{*/ -#define HW_I2S_RCR2_ADDR(x) ((x) + 0x88U) - -#define HW_I2S_RCR2(x) (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x)) -#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U) -#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v)) -#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) | (v))) -#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v))) -#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR2 bitfields - */ - -/*! - * @name Register I2S_RCR2, field DIV[7:0] (RW) - * - * Divides down the audio master clock to generate the bit clock when configured - * for an internal bit clock. The division value is (DIV + 1) * 2. - */ -/*@{*/ -#define BP_I2S_RCR2_DIV (0U) /*!< Bit position for I2S_RCR2_DIV. */ -#define BM_I2S_RCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */ -#define BS_I2S_RCR2_DIV (8U) /*!< Bit field size in bits for I2S_RCR2_DIV. */ - -/*! @brief Read current value of the I2S_RCR2_DIV field. */ -#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV) - -/*! @brief Format value for bitfield I2S_RCR2_DIV. */ -#define BF_I2S_RCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV) - -/*! @brief Set the DIV field to a new value. */ -#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCD[24] (RW) - * - * Configures the direction of the bit clock. - * - * Values: - * - 0 - Bit clock is generated externally in Slave mode. - * - 1 - Bit clock is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_RCR2_BCD (24U) /*!< Bit position for I2S_RCR2_BCD. */ -#define BM_I2S_RCR2_BCD (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */ -#define BS_I2S_RCR2_BCD (1U) /*!< Bit field size in bits for I2S_RCR2_BCD. */ - -/*! @brief Read current value of the I2S_RCR2_BCD field. */ -#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD)) - -/*! @brief Format value for bitfield I2S_RCR2_BCD. */ -#define BF_I2S_RCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD) - -/*! @brief Set the BCD field to a new value. */ -#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCP[25] (RW) - * - * Configures the polarity of the bit clock. - * - * Values: - * - 0 - Bit Clock is active high with drive outputs on rising edge and sample - * inputs on falling edge. - * - 1 - Bit Clock is active low with drive outputs on falling edge and sample - * inputs on rising edge. - */ -/*@{*/ -#define BP_I2S_RCR2_BCP (25U) /*!< Bit position for I2S_RCR2_BCP. */ -#define BM_I2S_RCR2_BCP (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */ -#define BS_I2S_RCR2_BCP (1U) /*!< Bit field size in bits for I2S_RCR2_BCP. */ - -/*! @brief Read current value of the I2S_RCR2_BCP field. */ -#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP)) - -/*! @brief Format value for bitfield I2S_RCR2_BCP. */ -#define BF_I2S_RCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP) - -/*! @brief Set the BCP field to a new value. */ -#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field MSEL[27:26] (RW) - * - * Selects the audio Master Clock option used to generate an internally - * generated bit clock. This field has no effect when configured for an externally - * generated bit clock. Depending on the device, some Master Clock options might not be - * available. See the chip configuration details for the availability and - * chip-specific meaning of each option. - * - * Values: - * - 00 - Bus Clock selected. - * - 01 - Master Clock (MCLK) 1 option selected. - * - 10 - Master Clock (MCLK) 2 option selected. - * - 11 - Master Clock (MCLK) 3 option selected. - */ -/*@{*/ -#define BP_I2S_RCR2_MSEL (26U) /*!< Bit position for I2S_RCR2_MSEL. */ -#define BM_I2S_RCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */ -#define BS_I2S_RCR2_MSEL (2U) /*!< Bit field size in bits for I2S_RCR2_MSEL. */ - -/*! @brief Read current value of the I2S_RCR2_MSEL field. */ -#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL) - -/*! @brief Format value for bitfield I2S_RCR2_MSEL. */ -#define BF_I2S_RCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL) - -/*! @brief Set the MSEL field to a new value. */ -#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCI[28] (RW) - * - * When this field is set and using an internally generated bit clock in either - * synchronous or asynchronous mode, the bit clock actually used by the receiver - * is delayed by the pad output delay (the receiver is clocked by the pad input - * as if the clock was externally generated). This has the effect of decreasing - * the data input setup time, but increasing the data output valid time. The slave - * mode timing from the datasheet should be used for the receiver when this bit - * is set. In synchronous mode, this bit allows the receiver to use the slave mode - * timing from the datasheet, while the transmitter uses the master mode timing. - * This field has no effect when configured for an externally generated bit - * clock or when synchronous to another SAI peripheral . - * - * Values: - * - 0 - No effect. - * - 1 - Internal logic is clocked as if bit clock was externally generated. - */ -/*@{*/ -#define BP_I2S_RCR2_BCI (28U) /*!< Bit position for I2S_RCR2_BCI. */ -#define BM_I2S_RCR2_BCI (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */ -#define BS_I2S_RCR2_BCI (1U) /*!< Bit field size in bits for I2S_RCR2_BCI. */ - -/*! @brief Read current value of the I2S_RCR2_BCI field. */ -#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI)) - -/*! @brief Format value for bitfield I2S_RCR2_BCI. */ -#define BF_I2S_RCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI) - -/*! @brief Set the BCI field to a new value. */ -#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field BCS[29] (RW) - * - * This field swaps the bit clock used by the receiver. When the receiver is - * configured in asynchronous mode and this bit is set, the receiver is clocked by - * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and - * receiver to share the same bit clock, but the receiver continues to use the receiver - * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous - * mode, the transmitter BCS field and receiver BCS field must be set to the same - * value. When both are set, the transmitter and receiver are both clocked by the - * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync - * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral. - * - * Values: - * - 0 - Use the normal bit clock source. - * - 1 - Swap the bit clock source. - */ -/*@{*/ -#define BP_I2S_RCR2_BCS (29U) /*!< Bit position for I2S_RCR2_BCS. */ -#define BM_I2S_RCR2_BCS (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */ -#define BS_I2S_RCR2_BCS (1U) /*!< Bit field size in bits for I2S_RCR2_BCS. */ - -/*! @brief Read current value of the I2S_RCR2_BCS field. */ -#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS)) - -/*! @brief Format value for bitfield I2S_RCR2_BCS. */ -#define BF_I2S_RCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS) - -/*! @brief Set the BCS field to a new value. */ -#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR2, field SYNC[31:30] (RW) - * - * Configures between asynchronous and synchronous modes of operation. When - * configured for a synchronous mode of operation, the transmitter or other SAI - * peripheral must be configured for asynchronous operation. - * - * Values: - * - 00 - Asynchronous mode. - * - 01 - Synchronous with transmitter. - * - 10 - Synchronous with another SAI receiver. - * - 11 - Synchronous with another SAI transmitter. - */ -/*@{*/ -#define BP_I2S_RCR2_SYNC (30U) /*!< Bit position for I2S_RCR2_SYNC. */ -#define BM_I2S_RCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */ -#define BS_I2S_RCR2_SYNC (2U) /*!< Bit field size in bits for I2S_RCR2_SYNC. */ - -/*! @brief Read current value of the I2S_RCR2_SYNC field. */ -#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC) - -/*! @brief Format value for bitfield I2S_RCR2_SYNC. */ -#define BF_I2S_RCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC) - -/*! @brief Set the SYNC field to a new value. */ -#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR3 - SAI Receive Configuration 3 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr3 -{ - uint32_t U; - struct _hw_i2s_rcr3_bitfields - { - uint32_t WDFL : 5; /*!< [4:0] Word Flag Configuration */ - uint32_t RESERVED0 : 11; /*!< [15:5] */ - uint32_t RCE : 2; /*!< [17:16] Receive Channel Enable */ - uint32_t RESERVED1 : 14; /*!< [31:18] */ - } B; -} hw_i2s_rcr3_t; - -/*! - * @name Constants and macros for entire I2S_RCR3 register - */ -/*@{*/ -#define HW_I2S_RCR3_ADDR(x) ((x) + 0x8CU) - -#define HW_I2S_RCR3(x) (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x)) -#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U) -#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v)) -#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) | (v))) -#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v))) -#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR3 bitfields - */ - -/*! - * @name Register I2S_RCR3, field WDFL[4:0] (RW) - * - * Configures which word the start of word flag is set. The value written should - * be one less than the word number (for example, write zero to configure for - * the first word in the frame). When configured to a value greater than the Frame - * Size field, then the start of word flag is never set. - */ -/*@{*/ -#define BP_I2S_RCR3_WDFL (0U) /*!< Bit position for I2S_RCR3_WDFL. */ -#define BM_I2S_RCR3_WDFL (0x0000001FU) /*!< Bit mask for I2S_RCR3_WDFL. */ -#define BS_I2S_RCR3_WDFL (5U) /*!< Bit field size in bits for I2S_RCR3_WDFL. */ - -/*! @brief Read current value of the I2S_RCR3_WDFL field. */ -#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL) - -/*! @brief Format value for bitfield I2S_RCR3_WDFL. */ -#define BF_I2S_RCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL) - -/*! @brief Set the WDFL field to a new value. */ -#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR3, field RCE[17:16] (RW) - * - * Enables the corresponding data channel for receive operation. A channel must - * be enabled before its FIFO is accessed. - * - * Values: - * - 0 - Receive data channel N is disabled. - * - 1 - Receive data channel N is enabled. - */ -/*@{*/ -#define BP_I2S_RCR3_RCE (16U) /*!< Bit position for I2S_RCR3_RCE. */ -#define BM_I2S_RCR3_RCE (0x00030000U) /*!< Bit mask for I2S_RCR3_RCE. */ -#define BS_I2S_RCR3_RCE (2U) /*!< Bit field size in bits for I2S_RCR3_RCE. */ - -/*! @brief Read current value of the I2S_RCR3_RCE field. */ -#define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE) - -/*! @brief Format value for bitfield I2S_RCR3_RCE. */ -#define BF_I2S_RCR3_RCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE) - -/*! @brief Set the RCE field to a new value. */ -#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR4 - SAI Receive Configuration 4 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr4 -{ - uint32_t U; - struct _hw_i2s_rcr4_bitfields - { - uint32_t FSD : 1; /*!< [0] Frame Sync Direction */ - uint32_t FSP : 1; /*!< [1] Frame Sync Polarity */ - uint32_t RESERVED0 : 1; /*!< [2] */ - uint32_t FSE : 1; /*!< [3] Frame Sync Early */ - uint32_t MF : 1; /*!< [4] MSB First */ - uint32_t RESERVED1 : 3; /*!< [7:5] */ - uint32_t SYWD : 5; /*!< [12:8] Sync Width */ - uint32_t RESERVED2 : 3; /*!< [15:13] */ - uint32_t FRSZ : 5; /*!< [20:16] Frame Size */ - uint32_t RESERVED3 : 11; /*!< [31:21] */ - } B; -} hw_i2s_rcr4_t; - -/*! - * @name Constants and macros for entire I2S_RCR4 register - */ -/*@{*/ -#define HW_I2S_RCR4_ADDR(x) ((x) + 0x90U) - -#define HW_I2S_RCR4(x) (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x)) -#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U) -#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v)) -#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) | (v))) -#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v))) -#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR4 bitfields - */ - -/*! - * @name Register I2S_RCR4, field FSD[0] (RW) - * - * Configures the direction of the frame sync. - * - * Values: - * - 0 - Frame Sync is generated externally in Slave mode. - * - 1 - Frame Sync is generated internally in Master mode. - */ -/*@{*/ -#define BP_I2S_RCR4_FSD (0U) /*!< Bit position for I2S_RCR4_FSD. */ -#define BM_I2S_RCR4_FSD (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */ -#define BS_I2S_RCR4_FSD (1U) /*!< Bit field size in bits for I2S_RCR4_FSD. */ - -/*! @brief Read current value of the I2S_RCR4_FSD field. */ -#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD)) - -/*! @brief Format value for bitfield I2S_RCR4_FSD. */ -#define BF_I2S_RCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD) - -/*! @brief Set the FSD field to a new value. */ -#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FSP[1] (RW) - * - * Configures the polarity of the frame sync. - * - * Values: - * - 0 - Frame sync is active high. - * - 1 - Frame sync is active low. - */ -/*@{*/ -#define BP_I2S_RCR4_FSP (1U) /*!< Bit position for I2S_RCR4_FSP. */ -#define BM_I2S_RCR4_FSP (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */ -#define BS_I2S_RCR4_FSP (1U) /*!< Bit field size in bits for I2S_RCR4_FSP. */ - -/*! @brief Read current value of the I2S_RCR4_FSP field. */ -#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP)) - -/*! @brief Format value for bitfield I2S_RCR4_FSP. */ -#define BF_I2S_RCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP) - -/*! @brief Set the FSP field to a new value. */ -#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FSE[3] (RW) - * - * Values: - * - 0 - Frame sync asserts with the first bit of the frame. - * - 1 - Frame sync asserts one bit before the first bit of the frame. - */ -/*@{*/ -#define BP_I2S_RCR4_FSE (3U) /*!< Bit position for I2S_RCR4_FSE. */ -#define BM_I2S_RCR4_FSE (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */ -#define BS_I2S_RCR4_FSE (1U) /*!< Bit field size in bits for I2S_RCR4_FSE. */ - -/*! @brief Read current value of the I2S_RCR4_FSE field. */ -#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE)) - -/*! @brief Format value for bitfield I2S_RCR4_FSE. */ -#define BF_I2S_RCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE) - -/*! @brief Set the FSE field to a new value. */ -#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field MF[4] (RW) - * - * Configures whether the LSB or the MSB is received first. - * - * Values: - * - 0 - LSB is received first. - * - 1 - MSB is received first. - */ -/*@{*/ -#define BP_I2S_RCR4_MF (4U) /*!< Bit position for I2S_RCR4_MF. */ -#define BM_I2S_RCR4_MF (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */ -#define BS_I2S_RCR4_MF (1U) /*!< Bit field size in bits for I2S_RCR4_MF. */ - -/*! @brief Read current value of the I2S_RCR4_MF field. */ -#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF)) - -/*! @brief Format value for bitfield I2S_RCR4_MF. */ -#define BF_I2S_RCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF) - -/*! @brief Set the MF field to a new value. */ -#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v)) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field SYWD[12:8] (RW) - * - * Configures the length of the frame sync in number of bit clocks. The value - * written must be one less than the number of bit clocks. For example, write 0 for - * the frame sync to assert for one bit clock only. The sync width cannot be - * configured longer than the first word of the frame. - */ -/*@{*/ -#define BP_I2S_RCR4_SYWD (8U) /*!< Bit position for I2S_RCR4_SYWD. */ -#define BM_I2S_RCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */ -#define BS_I2S_RCR4_SYWD (5U) /*!< Bit field size in bits for I2S_RCR4_SYWD. */ - -/*! @brief Read current value of the I2S_RCR4_SYWD field. */ -#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD) - -/*! @brief Format value for bitfield I2S_RCR4_SYWD. */ -#define BF_I2S_RCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD) - -/*! @brief Set the SYWD field to a new value. */ -#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR4, field FRSZ[20:16] (RW) - * - * Configures the number of words in each frame. The value written must be one - * less than the number of words in the frame. For example, write 0 for one word - * per frame. The maximum supported frame size is 32 words. - */ -/*@{*/ -#define BP_I2S_RCR4_FRSZ (16U) /*!< Bit position for I2S_RCR4_FRSZ. */ -#define BM_I2S_RCR4_FRSZ (0x001F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */ -#define BS_I2S_RCR4_FRSZ (5U) /*!< Bit field size in bits for I2S_RCR4_FRSZ. */ - -/*! @brief Read current value of the I2S_RCR4_FRSZ field. */ -#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ) - -/*! @brief Format value for bitfield I2S_RCR4_FRSZ. */ -#define BF_I2S_RCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ) - -/*! @brief Set the FRSZ field to a new value. */ -#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RCR5 - SAI Receive Configuration 5 Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW) - * - * Reset value: 0x00000000U - * - * This register must not be altered when RCSR[RE] is set. - */ -typedef union _hw_i2s_rcr5 -{ - uint32_t U; - struct _hw_i2s_rcr5_bitfields - { - uint32_t RESERVED0 : 8; /*!< [7:0] */ - uint32_t FBT : 5; /*!< [12:8] First Bit Shifted */ - uint32_t RESERVED1 : 3; /*!< [15:13] */ - uint32_t W0W : 5; /*!< [20:16] Word 0 Width */ - uint32_t RESERVED2 : 3; /*!< [23:21] */ - uint32_t WNW : 5; /*!< [28:24] Word N Width */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_i2s_rcr5_t; - -/*! - * @name Constants and macros for entire I2S_RCR5 register - */ -/*@{*/ -#define HW_I2S_RCR5_ADDR(x) ((x) + 0x94U) - -#define HW_I2S_RCR5(x) (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x)) -#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U) -#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v)) -#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) | (v))) -#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v))) -#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RCR5 bitfields - */ - -/*! - * @name Register I2S_RCR5, field FBT[12:8] (RW) - * - * Configures the bit index for the first bit received for each word in the - * frame. If configured for MSB First, the index of the next bit received is one less - * than the current bit received. If configured for LSB First, the index of the - * next bit received is one more than the current bit received. The value written - * must be greater than or equal to the word width when configured for MSB - * First. The value written must be less than or equal to 31-word width when - * configured for LSB First. - */ -/*@{*/ -#define BP_I2S_RCR5_FBT (8U) /*!< Bit position for I2S_RCR5_FBT. */ -#define BM_I2S_RCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */ -#define BS_I2S_RCR5_FBT (5U) /*!< Bit field size in bits for I2S_RCR5_FBT. */ - -/*! @brief Read current value of the I2S_RCR5_FBT field. */ -#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT) - -/*! @brief Format value for bitfield I2S_RCR5_FBT. */ -#define BF_I2S_RCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT) - -/*! @brief Set the FBT field to a new value. */ -#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR5, field W0W[20:16] (RW) - * - * Configures the number of bits in the first word in each frame. The value - * written must be one less than the number of bits in the first word. Word width of - * less than 8 bits is not supported if there is only one word per frame. - */ -/*@{*/ -#define BP_I2S_RCR5_W0W (16U) /*!< Bit position for I2S_RCR5_W0W. */ -#define BM_I2S_RCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */ -#define BS_I2S_RCR5_W0W (5U) /*!< Bit field size in bits for I2S_RCR5_W0W. */ - -/*! @brief Read current value of the I2S_RCR5_W0W field. */ -#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W) - -/*! @brief Format value for bitfield I2S_RCR5_W0W. */ -#define BF_I2S_RCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W) - -/*! @brief Set the W0W field to a new value. */ -#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v))) -/*@}*/ - -/*! - * @name Register I2S_RCR5, field WNW[28:24] (RW) - * - * Configures the number of bits in each word, for each word except the first in - * the frame. The value written must be one less than the number of bits per - * word. Word width of less than 8 bits is not supported. - */ -/*@{*/ -#define BP_I2S_RCR5_WNW (24U) /*!< Bit position for I2S_RCR5_WNW. */ -#define BM_I2S_RCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */ -#define BS_I2S_RCR5_WNW (5U) /*!< Bit field size in bits for I2S_RCR5_WNW. */ - -/*! @brief Read current value of the I2S_RCR5_WNW field. */ -#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW) - -/*! @brief Format value for bitfield I2S_RCR5_WNW. */ -#define BF_I2S_RCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW) - -/*! @brief Set the WNW field to a new value. */ -#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v))) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RDRn - SAI Receive Data Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RDRn - SAI Receive Data Register (RO) - * - * Reset value: 0x00000000U - * - * Reading this register introduces one additional peripheral clock wait state - * on each read. - */ -typedef union _hw_i2s_rdrn -{ - uint32_t U; - struct _hw_i2s_rdrn_bitfields - { - uint32_t RDR : 32; /*!< [31:0] Receive Data Register */ - } B; -} hw_i2s_rdrn_t; - -/*! - * @name Constants and macros for entire I2S_RDRn register - */ -/*@{*/ -#define HW_I2S_RDRn_COUNT (2U) - -#define HW_I2S_RDRn_ADDR(x, n) ((x) + 0xA0U + (0x4U * (n))) - -#define HW_I2S_RDRn(x, n) (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n)) -#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual I2S_RDRn bitfields - */ - -/*! - * @name Register I2S_RDRn, field RDR[31:0] (RO) - * - * The corresponding RCR3[RCE] bit must be set before accessing the channel's - * receive data register. Reads from this register when the receive FIFO is not - * empty will return the data from the top of the receive FIFO. Reads from this - * register when the receive FIFO is empty are ignored. - */ -/*@{*/ -#define BP_I2S_RDRn_RDR (0U) /*!< Bit position for I2S_RDRn_RDR. */ -#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */ -#define BS_I2S_RDRn_RDR (32U) /*!< Bit field size in bits for I2S_RDRn_RDR. */ - -/*! @brief Read current value of the I2S_RDRn_RDR field. */ -#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RFRn - SAI Receive FIFO Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO) - * - * Reset value: 0x00000000U - * - * The MSB of the read and write pointers is used to distinguish between FIFO - * full and empty conditions. If the read and write pointers are identical, then - * the FIFO is empty. If the read and write pointers are identical except for the - * MSB, then the FIFO is full. - */ -typedef union _hw_i2s_rfrn -{ - uint32_t U; - struct _hw_i2s_rfrn_bitfields - { - uint32_t RFP : 4; /*!< [3:0] Read FIFO Pointer */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t WFP : 4; /*!< [19:16] Write FIFO Pointer */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_i2s_rfrn_t; - -/*! - * @name Constants and macros for entire I2S_RFRn register - */ -/*@{*/ -#define HW_I2S_RFRn_COUNT (2U) - -#define HW_I2S_RFRn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n))) - -#define HW_I2S_RFRn(x, n) (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n)) -#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual I2S_RFRn bitfields - */ - -/*! - * @name Register I2S_RFRn, field RFP[3:0] (RO) - * - * FIFO read pointer for receive data channel. - */ -/*@{*/ -#define BP_I2S_RFRn_RFP (0U) /*!< Bit position for I2S_RFRn_RFP. */ -#define BM_I2S_RFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */ -#define BS_I2S_RFRn_RFP (4U) /*!< Bit field size in bits for I2S_RFRn_RFP. */ - -/*! @brief Read current value of the I2S_RFRn_RFP field. */ -#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP) -/*@}*/ - -/*! - * @name Register I2S_RFRn, field WFP[19:16] (RO) - * - * FIFO write pointer for receive data channel. - */ -/*@{*/ -#define BP_I2S_RFRn_WFP (16U) /*!< Bit position for I2S_RFRn_WFP. */ -#define BM_I2S_RFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */ -#define BS_I2S_RFRn_WFP (4U) /*!< Bit field size in bits for I2S_RFRn_WFP. */ - -/*! @brief Read current value of the I2S_RFRn_WFP field. */ -#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP) -/*@}*/ - -/******************************************************************************* - * HW_I2S_RMR - SAI Receive Mask Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_RMR - SAI Receive Mask Register (RW) - * - * Reset value: 0x00000000U - * - * This register is double-buffered and updates: When RCSR[RE] is first set At - * the end of each frame This allows the masked words in each frame to change from - * frame to frame. - */ -typedef union _hw_i2s_rmr -{ - uint32_t U; - struct _hw_i2s_rmr_bitfields - { - uint32_t RWM : 32; /*!< [31:0] Receive Word Mask */ - } B; -} hw_i2s_rmr_t; - -/*! - * @name Constants and macros for entire I2S_RMR register - */ -/*@{*/ -#define HW_I2S_RMR_ADDR(x) ((x) + 0xE0U) - -#define HW_I2S_RMR(x) (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x)) -#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U) -#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v)) -#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) | (v))) -#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v))) -#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_RMR bitfields - */ - -/*! - * @name Register I2S_RMR, field RWM[31:0] (RW) - * - * Configures whether the receive word is masked (received data ignored and not - * written to receive FIFO) for the corresponding word in the frame. - * - * Values: - * - 0 - Word N is enabled. - * - 1 - Word N is masked. - */ -/*@{*/ -#define BP_I2S_RMR_RWM (0U) /*!< Bit position for I2S_RMR_RWM. */ -#define BM_I2S_RMR_RWM (0xFFFFFFFFU) /*!< Bit mask for I2S_RMR_RWM. */ -#define BS_I2S_RMR_RWM (32U) /*!< Bit field size in bits for I2S_RMR_RWM. */ - -/*! @brief Read current value of the I2S_RMR_RWM field. */ -#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U) - -/*! @brief Format value for bitfield I2S_RMR_RWM. */ -#define BF_I2S_RMR_RWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM) - -/*! @brief Set the RWM field to a new value. */ -#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_MCR - SAI MCLK Control Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_MCR - SAI MCLK Control Register (RW) - * - * Reset value: 0x00000000U - * - * The MCLK Control Register (MCR) controls the clock source and direction of - * the audio master clock. - */ -typedef union _hw_i2s_mcr -{ - uint32_t U; - struct _hw_i2s_mcr_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t MICS : 2; /*!< [25:24] MCLK Input Clock Select */ - uint32_t RESERVED1 : 4; /*!< [29:26] */ - uint32_t MOE : 1; /*!< [30] MCLK Output Enable */ - uint32_t DUF : 1; /*!< [31] Divider Update Flag */ - } B; -} hw_i2s_mcr_t; - -/*! - * @name Constants and macros for entire I2S_MCR register - */ -/*@{*/ -#define HW_I2S_MCR_ADDR(x) ((x) + 0x100U) - -#define HW_I2S_MCR(x) (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x)) -#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U) -#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v)) -#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) | (v))) -#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v))) -#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_MCR bitfields - */ - -/*! - * @name Register I2S_MCR, field MICS[25:24] (RW) - * - * Selects the clock input to the MCLK divider. This field cannot be changed - * while the MCLK divider is enabled. See the chip configuration details for - * information about the connections to these inputs. - * - * Values: - * - 00 - MCLK divider input clock 0 selected. - * - 01 - MCLK divider input clock 1 selected. - * - 10 - MCLK divider input clock 2 selected. - * - 11 - MCLK divider input clock 3 selected. - */ -/*@{*/ -#define BP_I2S_MCR_MICS (24U) /*!< Bit position for I2S_MCR_MICS. */ -#define BM_I2S_MCR_MICS (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */ -#define BS_I2S_MCR_MICS (2U) /*!< Bit field size in bits for I2S_MCR_MICS. */ - -/*! @brief Read current value of the I2S_MCR_MICS field. */ -#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS) - -/*! @brief Format value for bitfield I2S_MCR_MICS. */ -#define BF_I2S_MCR_MICS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS) - -/*! @brief Set the MICS field to a new value. */ -#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v))) -/*@}*/ - -/*! - * @name Register I2S_MCR, field MOE[30] (RW) - * - * Enables the MCLK divider and configures the MCLK signal pin as an output. - * When software clears this field, it remains set until the MCLK divider is fully - * disabled. - * - * Values: - * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK - * divider. - * - 1 - MCLK signal pin is configured as an output from the MCLK divider and - * the MCLK divider is enabled. - */ -/*@{*/ -#define BP_I2S_MCR_MOE (30U) /*!< Bit position for I2S_MCR_MOE. */ -#define BM_I2S_MCR_MOE (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */ -#define BS_I2S_MCR_MOE (1U) /*!< Bit field size in bits for I2S_MCR_MOE. */ - -/*! @brief Read current value of the I2S_MCR_MOE field. */ -#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE)) - -/*! @brief Format value for bitfield I2S_MCR_MOE. */ -#define BF_I2S_MCR_MOE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE) - -/*! @brief Set the MOE field to a new value. */ -#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v)) -/*@}*/ - -/*! - * @name Register I2S_MCR, field DUF[31] (RO) - * - * Provides the status of on-the-fly updates to the MCLK divider ratio. - * - * Values: - * - 0 - MCLK divider ratio is not being updated currently. - * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK - * divider ratio are blocked while this flag remains set. - */ -/*@{*/ -#define BP_I2S_MCR_DUF (31U) /*!< Bit position for I2S_MCR_DUF. */ -#define BM_I2S_MCR_DUF (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */ -#define BS_I2S_MCR_DUF (1U) /*!< Bit field size in bits for I2S_MCR_DUF. */ - -/*! @brief Read current value of the I2S_MCR_DUF field. */ -#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF)) -/*@}*/ - -/******************************************************************************* - * HW_I2S_MDR - SAI MCLK Divide Register - ******************************************************************************/ - -/*! - * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW) - * - * Reset value: 0x00000000U - * - * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the - * MDR can be changed when the MCLK divider clock is enabled, additional writes - * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK - * divided clock is disabled do not set MCR[DUF]. - */ -typedef union _hw_i2s_mdr -{ - uint32_t U; - struct _hw_i2s_mdr_bitfields - { - uint32_t DIVIDE : 12; /*!< [11:0] MCLK Divide */ - uint32_t FRACT : 8; /*!< [19:12] MCLK Fraction */ - uint32_t RESERVED0 : 12; /*!< [31:20] */ - } B; -} hw_i2s_mdr_t; - -/*! - * @name Constants and macros for entire I2S_MDR register - */ -/*@{*/ -#define HW_I2S_MDR_ADDR(x) ((x) + 0x104U) - -#define HW_I2S_MDR(x) (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x)) -#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U) -#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v)) -#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) | (v))) -#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v))) -#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual I2S_MDR bitfields - */ - -/*! - * @name Register I2S_MDR, field DIVIDE[11:0] (RW) - * - * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + - * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the - * DIVIDE field. - */ -/*@{*/ -#define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */ -#define BM_I2S_MDR_DIVIDE (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */ -#define BS_I2S_MDR_DIVIDE (12U) /*!< Bit field size in bits for I2S_MDR_DIVIDE. */ - -/*! @brief Read current value of the I2S_MDR_DIVIDE field. */ -#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE) - -/*! @brief Format value for bitfield I2S_MDR_DIVIDE. */ -#define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE) - -/*! @brief Set the DIVIDE field to a new value. */ -#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v))) -/*@}*/ - -/*! - * @name Register I2S_MDR, field FRACT[19:12] (RW) - * - * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + - * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the - * DIVIDE field. - */ -/*@{*/ -#define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */ -#define BM_I2S_MDR_FRACT (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */ -#define BS_I2S_MDR_FRACT (8U) /*!< Bit field size in bits for I2S_MDR_FRACT. */ - -/*! @brief Read current value of the I2S_MDR_FRACT field. */ -#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT) - -/*! @brief Format value for bitfield I2S_MDR_FRACT. */ -#define BF_I2S_MDR_FRACT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT) - -/*! @brief Set the FRACT field to a new value. */ -#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v))) -/*@}*/ - -/******************************************************************************* - * hw_i2s_t - module struct - ******************************************************************************/ -/*! - * @brief All I2S module registers. - */ -#pragma pack(1) -typedef struct _hw_i2s -{ - __IO hw_i2s_tcsr_t TCSR; /*!< [0x0] SAI Transmit Control Register */ - __IO hw_i2s_tcr1_t TCR1; /*!< [0x4] SAI Transmit Configuration 1 Register */ - __IO hw_i2s_tcr2_t TCR2; /*!< [0x8] SAI Transmit Configuration 2 Register */ - __IO hw_i2s_tcr3_t TCR3; /*!< [0xC] SAI Transmit Configuration 3 Register */ - __IO hw_i2s_tcr4_t TCR4; /*!< [0x10] SAI Transmit Configuration 4 Register */ - __IO hw_i2s_tcr5_t TCR5; /*!< [0x14] SAI Transmit Configuration 5 Register */ - uint8_t _reserved0[8]; - __O hw_i2s_tdrn_t TDRn[2]; /*!< [0x20] SAI Transmit Data Register */ - uint8_t _reserved1[24]; - __I hw_i2s_tfrn_t TFRn[2]; /*!< [0x40] SAI Transmit FIFO Register */ - uint8_t _reserved2[24]; - __IO hw_i2s_tmr_t TMR; /*!< [0x60] SAI Transmit Mask Register */ - uint8_t _reserved3[28]; - __IO hw_i2s_rcsr_t RCSR; /*!< [0x80] SAI Receive Control Register */ - __IO hw_i2s_rcr1_t RCR1; /*!< [0x84] SAI Receive Configuration 1 Register */ - __IO hw_i2s_rcr2_t RCR2; /*!< [0x88] SAI Receive Configuration 2 Register */ - __IO hw_i2s_rcr3_t RCR3; /*!< [0x8C] SAI Receive Configuration 3 Register */ - __IO hw_i2s_rcr4_t RCR4; /*!< [0x90] SAI Receive Configuration 4 Register */ - __IO hw_i2s_rcr5_t RCR5; /*!< [0x94] SAI Receive Configuration 5 Register */ - uint8_t _reserved4[8]; - __I hw_i2s_rdrn_t RDRn[2]; /*!< [0xA0] SAI Receive Data Register */ - uint8_t _reserved5[24]; - __I hw_i2s_rfrn_t RFRn[2]; /*!< [0xC0] SAI Receive FIFO Register */ - uint8_t _reserved6[24]; - __IO hw_i2s_rmr_t RMR; /*!< [0xE0] SAI Receive Mask Register */ - uint8_t _reserved7[28]; - __IO hw_i2s_mcr_t MCR; /*!< [0x100] SAI MCLK Control Register */ - __IO hw_i2s_mdr_t MDR; /*!< [0x104] SAI MCLK Divide Register */ -} hw_i2s_t; -#pragma pack() - -/*! @brief Macro to access all I2S registers. */ -/*! @param x I2S module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_I2S(I2S0_BASE). */ -#define HW_I2S(x) (*(hw_i2s_t *)(x)) - -#endif /* __HW_I2S_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_llwu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_llwu.h deleted file mode 100644 index e31e26a8470..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_llwu.h +++ /dev/null @@ -1,2052 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_LLWU_REGISTERS_H__ -#define __HW_LLWU_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 LLWU - * - * Low leakage wakeup unit - * - * Registers defined in this header file: - * - HW_LLWU_PE1 - LLWU Pin Enable 1 register - * - HW_LLWU_PE2 - LLWU Pin Enable 2 register - * - HW_LLWU_PE3 - LLWU Pin Enable 3 register - * - HW_LLWU_PE4 - LLWU Pin Enable 4 register - * - HW_LLWU_ME - LLWU Module Enable register - * - HW_LLWU_F1 - LLWU Flag 1 register - * - HW_LLWU_F2 - LLWU Flag 2 register - * - HW_LLWU_F3 - LLWU Flag 3 register - * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register - * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register - * - HW_LLWU_RST - LLWU Reset Enable register - * - * - hw_llwu_t - Struct containing all module registers. - */ - -#define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */ - -/******************************************************************************* - * HW_LLWU_PE1 - LLWU Pin Enable 1 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE1 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module - * (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe1 -{ - uint8_t U; - struct _hw_llwu_pe1_bitfields - { - uint8_t WUPE0 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */ - uint8_t WUPE1 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */ - uint8_t WUPE2 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */ - uint8_t WUPE3 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */ - } B; -} hw_llwu_pe1_t; - -/*! - * @name Constants and macros for entire LLWU_PE1 register - */ -/*@{*/ -#define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U) - -#define HW_LLWU_PE1(x) (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x)) -#define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U) -#define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v)) -#define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) | (v))) -#define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v))) -#define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE1 bitfields - */ - -/*! - * @name Register LLWU_PE1, field WUPE0[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE0 (0U) /*!< Bit position for LLWU_PE1_WUPE0. */ -#define BM_LLWU_PE1_WUPE0 (0x03U) /*!< Bit mask for LLWU_PE1_WUPE0. */ -#define BS_LLWU_PE1_WUPE0 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE0. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */ -#define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE0. */ -#define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0) - -/*! @brief Set the WUPE0 field to a new value. */ -#define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE1, field WUPE1[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE1 (2U) /*!< Bit position for LLWU_PE1_WUPE1. */ -#define BM_LLWU_PE1_WUPE1 (0x0CU) /*!< Bit mask for LLWU_PE1_WUPE1. */ -#define BS_LLWU_PE1_WUPE1 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE1. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */ -#define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE1. */ -#define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1) - -/*! @brief Set the WUPE1 field to a new value. */ -#define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE1, field WUPE2[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE2 (4U) /*!< Bit position for LLWU_PE1_WUPE2. */ -#define BM_LLWU_PE1_WUPE2 (0x30U) /*!< Bit mask for LLWU_PE1_WUPE2. */ -#define BS_LLWU_PE1_WUPE2 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE2. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */ -#define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE2. */ -#define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2) - -/*! @brief Set the WUPE2 field to a new value. */ -#define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE1, field WUPE3[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE1_WUPE3 (6U) /*!< Bit position for LLWU_PE1_WUPE3. */ -#define BM_LLWU_PE1_WUPE3 (0xC0U) /*!< Bit mask for LLWU_PE1_WUPE3. */ -#define BS_LLWU_PE1_WUPE3 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE3. */ - -/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */ -#define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3) - -/*! @brief Format value for bitfield LLWU_PE1_WUPE3. */ -#define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3) - -/*! @brief Set the WUPE3 field to a new value. */ -#define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_PE2 - LLWU Pin Enable 2 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE2 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module - * (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe2 -{ - uint8_t U; - struct _hw_llwu_pe2_bitfields - { - uint8_t WUPE4 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */ - uint8_t WUPE5 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */ - uint8_t WUPE6 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */ - uint8_t WUPE7 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */ - } B; -} hw_llwu_pe2_t; - -/*! - * @name Constants and macros for entire LLWU_PE2 register - */ -/*@{*/ -#define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U) - -#define HW_LLWU_PE2(x) (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x)) -#define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U) -#define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v)) -#define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) | (v))) -#define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v))) -#define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE2 bitfields - */ - -/*! - * @name Register LLWU_PE2, field WUPE4[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE4 (0U) /*!< Bit position for LLWU_PE2_WUPE4. */ -#define BM_LLWU_PE2_WUPE4 (0x03U) /*!< Bit mask for LLWU_PE2_WUPE4. */ -#define BS_LLWU_PE2_WUPE4 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE4. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */ -#define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE4. */ -#define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4) - -/*! @brief Set the WUPE4 field to a new value. */ -#define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE2, field WUPE5[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE5 (2U) /*!< Bit position for LLWU_PE2_WUPE5. */ -#define BM_LLWU_PE2_WUPE5 (0x0CU) /*!< Bit mask for LLWU_PE2_WUPE5. */ -#define BS_LLWU_PE2_WUPE5 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE5. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */ -#define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE5. */ -#define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5) - -/*! @brief Set the WUPE5 field to a new value. */ -#define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE2, field WUPE6[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE6 (4U) /*!< Bit position for LLWU_PE2_WUPE6. */ -#define BM_LLWU_PE2_WUPE6 (0x30U) /*!< Bit mask for LLWU_PE2_WUPE6. */ -#define BS_LLWU_PE2_WUPE6 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE6. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */ -#define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE6. */ -#define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6) - -/*! @brief Set the WUPE6 field to a new value. */ -#define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE2, field WUPE7[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE2_WUPE7 (6U) /*!< Bit position for LLWU_PE2_WUPE7. */ -#define BM_LLWU_PE2_WUPE7 (0xC0U) /*!< Bit mask for LLWU_PE2_WUPE7. */ -#define BS_LLWU_PE2_WUPE7 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE7. */ - -/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */ -#define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7) - -/*! @brief Format value for bitfield LLWU_PE2_WUPE7. */ -#define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7) - -/*! @brief Set the WUPE7 field to a new value. */ -#define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_PE3 - LLWU Pin Enable 3 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE3 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module - * (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe3 -{ - uint8_t U; - struct _hw_llwu_pe3_bitfields - { - uint8_t WUPE8 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */ - uint8_t WUPE9 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */ - uint8_t WUPE10 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */ - uint8_t WUPE11 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */ - } B; -} hw_llwu_pe3_t; - -/*! - * @name Constants and macros for entire LLWU_PE3 register - */ -/*@{*/ -#define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U) - -#define HW_LLWU_PE3(x) (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x)) -#define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U) -#define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v)) -#define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) | (v))) -#define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v))) -#define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE3 bitfields - */ - -/*! - * @name Register LLWU_PE3, field WUPE8[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE8 (0U) /*!< Bit position for LLWU_PE3_WUPE8. */ -#define BM_LLWU_PE3_WUPE8 (0x03U) /*!< Bit mask for LLWU_PE3_WUPE8. */ -#define BS_LLWU_PE3_WUPE8 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE8. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */ -#define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE8. */ -#define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8) - -/*! @brief Set the WUPE8 field to a new value. */ -#define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE3, field WUPE9[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE9 (2U) /*!< Bit position for LLWU_PE3_WUPE9. */ -#define BM_LLWU_PE3_WUPE9 (0x0CU) /*!< Bit mask for LLWU_PE3_WUPE9. */ -#define BS_LLWU_PE3_WUPE9 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE9. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */ -#define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE9. */ -#define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9) - -/*! @brief Set the WUPE9 field to a new value. */ -#define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE3, field WUPE10[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE10 (4U) /*!< Bit position for LLWU_PE3_WUPE10. */ -#define BM_LLWU_PE3_WUPE10 (0x30U) /*!< Bit mask for LLWU_PE3_WUPE10. */ -#define BS_LLWU_PE3_WUPE10 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE10. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */ -#define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE10. */ -#define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10) - -/*! @brief Set the WUPE10 field to a new value. */ -#define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE3, field WUPE11[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE3_WUPE11 (6U) /*!< Bit position for LLWU_PE3_WUPE11. */ -#define BM_LLWU_PE3_WUPE11 (0xC0U) /*!< Bit mask for LLWU_PE3_WUPE11. */ -#define BS_LLWU_PE3_WUPE11 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE11. */ - -/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */ -#define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11) - -/*! @brief Format value for bitfield LLWU_PE3_WUPE11. */ -#define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11) - -/*! @brief Set the WUPE11 field to a new value. */ -#define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_PE4 - LLWU Pin Enable 4 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW) - * - * Reset value: 0x00U - * - * LLWU_PE4 contains the field to enable and select the edge detect type for the - * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_pe4 -{ - uint8_t U; - struct _hw_llwu_pe4_bitfields - { - uint8_t WUPE12 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */ - uint8_t WUPE13 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */ - uint8_t WUPE14 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */ - uint8_t WUPE15 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */ - } B; -} hw_llwu_pe4_t; - -/*! - * @name Constants and macros for entire LLWU_PE4 register - */ -/*@{*/ -#define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U) - -#define HW_LLWU_PE4(x) (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x)) -#define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U) -#define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v)) -#define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) | (v))) -#define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v))) -#define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_PE4 bitfields - */ - -/*! - * @name Register LLWU_PE4, field WUPE12[1:0] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE12 (0U) /*!< Bit position for LLWU_PE4_WUPE12. */ -#define BM_LLWU_PE4_WUPE12 (0x03U) /*!< Bit mask for LLWU_PE4_WUPE12. */ -#define BS_LLWU_PE4_WUPE12 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE12. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */ -#define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE12. */ -#define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12) - -/*! @brief Set the WUPE12 field to a new value. */ -#define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE4, field WUPE13[3:2] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE13 (2U) /*!< Bit position for LLWU_PE4_WUPE13. */ -#define BM_LLWU_PE4_WUPE13 (0x0CU) /*!< Bit mask for LLWU_PE4_WUPE13. */ -#define BS_LLWU_PE4_WUPE13 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE13. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */ -#define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE13. */ -#define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13) - -/*! @brief Set the WUPE13 field to a new value. */ -#define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE4, field WUPE14[5:4] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE14 (4U) /*!< Bit position for LLWU_PE4_WUPE14. */ -#define BM_LLWU_PE4_WUPE14 (0x30U) /*!< Bit mask for LLWU_PE4_WUPE14. */ -#define BS_LLWU_PE4_WUPE14 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE14. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */ -#define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE14. */ -#define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14) - -/*! @brief Set the WUPE14 field to a new value. */ -#define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v))) -/*@}*/ - -/*! - * @name Register LLWU_PE4, field WUPE15[7:6] (RW) - * - * Enables and configures the edge detection for the wakeup pin. - * - * Values: - * - 00 - External input pin disabled as wakeup input - * - 01 - External input pin enabled with rising edge detection - * - 10 - External input pin enabled with falling edge detection - * - 11 - External input pin enabled with any change detection - */ -/*@{*/ -#define BP_LLWU_PE4_WUPE15 (6U) /*!< Bit position for LLWU_PE4_WUPE15. */ -#define BM_LLWU_PE4_WUPE15 (0xC0U) /*!< Bit mask for LLWU_PE4_WUPE15. */ -#define BS_LLWU_PE4_WUPE15 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE15. */ - -/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */ -#define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15) - -/*! @brief Format value for bitfield LLWU_PE4_WUPE15. */ -#define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15) - -/*! @brief Set the WUPE15 field to a new value. */ -#define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v))) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_ME - LLWU Module Enable register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_ME - LLWU Module Enable register (RW) - * - * Reset value: 0x00U - * - * LLWU_ME contains the bits to enable the internal module flag as a wakeup - * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS - * and by reset types that trigger Chip Reset not VLLS. It is unaffected by - * reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The - * RCM implements many of the reset functions for the chip. See the chip's reset - * chapter for more information. details for more information. - */ -typedef union _hw_llwu_me -{ - uint8_t U; - struct _hw_llwu_me_bitfields - { - uint8_t WUME0 : 1; /*!< [0] Wakeup Module Enable For Module 0 */ - uint8_t WUME1 : 1; /*!< [1] Wakeup Module Enable for Module 1 */ - uint8_t WUME2 : 1; /*!< [2] Wakeup Module Enable For Module 2 */ - uint8_t WUME3 : 1; /*!< [3] Wakeup Module Enable For Module 3 */ - uint8_t WUME4 : 1; /*!< [4] Wakeup Module Enable For Module 4 */ - uint8_t WUME5 : 1; /*!< [5] Wakeup Module Enable For Module 5 */ - uint8_t WUME6 : 1; /*!< [6] Wakeup Module Enable For Module 6 */ - uint8_t WUME7 : 1; /*!< [7] Wakeup Module Enable For Module 7 */ - } B; -} hw_llwu_me_t; - -/*! - * @name Constants and macros for entire LLWU_ME register - */ -/*@{*/ -#define HW_LLWU_ME_ADDR(x) ((x) + 0x4U) - -#define HW_LLWU_ME(x) (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x)) -#define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U) -#define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v)) -#define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) | (v))) -#define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v))) -#define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_ME bitfields - */ - -/*! - * @name Register LLWU_ME, field WUME0[0] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME0 (0U) /*!< Bit position for LLWU_ME_WUME0. */ -#define BM_LLWU_ME_WUME0 (0x01U) /*!< Bit mask for LLWU_ME_WUME0. */ -#define BS_LLWU_ME_WUME0 (1U) /*!< Bit field size in bits for LLWU_ME_WUME0. */ - -/*! @brief Read current value of the LLWU_ME_WUME0 field. */ -#define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0)) - -/*! @brief Format value for bitfield LLWU_ME_WUME0. */ -#define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0) - -/*! @brief Set the WUME0 field to a new value. */ -#define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME1[1] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME1 (1U) /*!< Bit position for LLWU_ME_WUME1. */ -#define BM_LLWU_ME_WUME1 (0x02U) /*!< Bit mask for LLWU_ME_WUME1. */ -#define BS_LLWU_ME_WUME1 (1U) /*!< Bit field size in bits for LLWU_ME_WUME1. */ - -/*! @brief Read current value of the LLWU_ME_WUME1 field. */ -#define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1)) - -/*! @brief Format value for bitfield LLWU_ME_WUME1. */ -#define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1) - -/*! @brief Set the WUME1 field to a new value. */ -#define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME2[2] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME2 (2U) /*!< Bit position for LLWU_ME_WUME2. */ -#define BM_LLWU_ME_WUME2 (0x04U) /*!< Bit mask for LLWU_ME_WUME2. */ -#define BS_LLWU_ME_WUME2 (1U) /*!< Bit field size in bits for LLWU_ME_WUME2. */ - -/*! @brief Read current value of the LLWU_ME_WUME2 field. */ -#define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2)) - -/*! @brief Format value for bitfield LLWU_ME_WUME2. */ -#define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2) - -/*! @brief Set the WUME2 field to a new value. */ -#define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME3[3] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME3 (3U) /*!< Bit position for LLWU_ME_WUME3. */ -#define BM_LLWU_ME_WUME3 (0x08U) /*!< Bit mask for LLWU_ME_WUME3. */ -#define BS_LLWU_ME_WUME3 (1U) /*!< Bit field size in bits for LLWU_ME_WUME3. */ - -/*! @brief Read current value of the LLWU_ME_WUME3 field. */ -#define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3)) - -/*! @brief Format value for bitfield LLWU_ME_WUME3. */ -#define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3) - -/*! @brief Set the WUME3 field to a new value. */ -#define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME4[4] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME4 (4U) /*!< Bit position for LLWU_ME_WUME4. */ -#define BM_LLWU_ME_WUME4 (0x10U) /*!< Bit mask for LLWU_ME_WUME4. */ -#define BS_LLWU_ME_WUME4 (1U) /*!< Bit field size in bits for LLWU_ME_WUME4. */ - -/*! @brief Read current value of the LLWU_ME_WUME4 field. */ -#define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4)) - -/*! @brief Format value for bitfield LLWU_ME_WUME4. */ -#define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4) - -/*! @brief Set the WUME4 field to a new value. */ -#define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME5[5] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME5 (5U) /*!< Bit position for LLWU_ME_WUME5. */ -#define BM_LLWU_ME_WUME5 (0x20U) /*!< Bit mask for LLWU_ME_WUME5. */ -#define BS_LLWU_ME_WUME5 (1U) /*!< Bit field size in bits for LLWU_ME_WUME5. */ - -/*! @brief Read current value of the LLWU_ME_WUME5 field. */ -#define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5)) - -/*! @brief Format value for bitfield LLWU_ME_WUME5. */ -#define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5) - -/*! @brief Set the WUME5 field to a new value. */ -#define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME6[6] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME6 (6U) /*!< Bit position for LLWU_ME_WUME6. */ -#define BM_LLWU_ME_WUME6 (0x40U) /*!< Bit mask for LLWU_ME_WUME6. */ -#define BS_LLWU_ME_WUME6 (1U) /*!< Bit field size in bits for LLWU_ME_WUME6. */ - -/*! @brief Read current value of the LLWU_ME_WUME6 field. */ -#define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6)) - -/*! @brief Format value for bitfield LLWU_ME_WUME6. */ -#define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6) - -/*! @brief Set the WUME6 field to a new value. */ -#define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_ME, field WUME7[7] (RW) - * - * Enables an internal module as a wakeup source input. - * - * Values: - * - 0 - Internal module flag not used as wakeup source - * - 1 - Internal module flag used as wakeup source - */ -/*@{*/ -#define BP_LLWU_ME_WUME7 (7U) /*!< Bit position for LLWU_ME_WUME7. */ -#define BM_LLWU_ME_WUME7 (0x80U) /*!< Bit mask for LLWU_ME_WUME7. */ -#define BS_LLWU_ME_WUME7 (1U) /*!< Bit field size in bits for LLWU_ME_WUME7. */ - -/*! @brief Read current value of the LLWU_ME_WUME7 field. */ -#define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7)) - -/*! @brief Format value for bitfield LLWU_ME_WUME7. */ -#define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7) - -/*! @brief Set the WUME7 field to a new value. */ -#define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_F1 - LLWU Flag 1 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C) - * - * Reset value: 0x00U - * - * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the - * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU - * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The - * external wakeup flags are read-only and clearing a flag is accomplished by a write - * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will - * remain set if the associated WUPEx bit is cleared. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_f1 -{ - uint8_t U; - struct _hw_llwu_f1_bitfields - { - uint8_t WUF0 : 1; /*!< [0] Wakeup Flag For LLWU_P0 */ - uint8_t WUF1 : 1; /*!< [1] Wakeup Flag For LLWU_P1 */ - uint8_t WUF2 : 1; /*!< [2] Wakeup Flag For LLWU_P2 */ - uint8_t WUF3 : 1; /*!< [3] Wakeup Flag For LLWU_P3 */ - uint8_t WUF4 : 1; /*!< [4] Wakeup Flag For LLWU_P4 */ - uint8_t WUF5 : 1; /*!< [5] Wakeup Flag For LLWU_P5 */ - uint8_t WUF6 : 1; /*!< [6] Wakeup Flag For LLWU_P6 */ - uint8_t WUF7 : 1; /*!< [7] Wakeup Flag For LLWU_P7 */ - } B; -} hw_llwu_f1_t; - -/*! - * @name Constants and macros for entire LLWU_F1 register - */ -/*@{*/ -#define HW_LLWU_F1_ADDR(x) ((x) + 0x5U) - -#define HW_LLWU_F1(x) (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x)) -#define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U) -#define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v)) -#define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) | (v))) -#define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v))) -#define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_F1 bitfields - */ - -/*! - * @name Register LLWU_F1, field WUF0[0] (W1C) - * - * Indicates that an enabled external wake-up pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF0. - * - * Values: - * - 0 - LLWU_P0 input was not a wakeup source - * - 1 - LLWU_P0 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF0 (0U) /*!< Bit position for LLWU_F1_WUF0. */ -#define BM_LLWU_F1_WUF0 (0x01U) /*!< Bit mask for LLWU_F1_WUF0. */ -#define BS_LLWU_F1_WUF0 (1U) /*!< Bit field size in bits for LLWU_F1_WUF0. */ - -/*! @brief Read current value of the LLWU_F1_WUF0 field. */ -#define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0)) - -/*! @brief Format value for bitfield LLWU_F1_WUF0. */ -#define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0) - -/*! @brief Set the WUF0 field to a new value. */ -#define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF1[1] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF1. - * - * Values: - * - 0 - LLWU_P1 input was not a wakeup source - * - 1 - LLWU_P1 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF1 (1U) /*!< Bit position for LLWU_F1_WUF1. */ -#define BM_LLWU_F1_WUF1 (0x02U) /*!< Bit mask for LLWU_F1_WUF1. */ -#define BS_LLWU_F1_WUF1 (1U) /*!< Bit field size in bits for LLWU_F1_WUF1. */ - -/*! @brief Read current value of the LLWU_F1_WUF1 field. */ -#define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1)) - -/*! @brief Format value for bitfield LLWU_F1_WUF1. */ -#define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1) - -/*! @brief Set the WUF1 field to a new value. */ -#define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF2[2] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF2. - * - * Values: - * - 0 - LLWU_P2 input was not a wakeup source - * - 1 - LLWU_P2 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF2 (2U) /*!< Bit position for LLWU_F1_WUF2. */ -#define BM_LLWU_F1_WUF2 (0x04U) /*!< Bit mask for LLWU_F1_WUF2. */ -#define BS_LLWU_F1_WUF2 (1U) /*!< Bit field size in bits for LLWU_F1_WUF2. */ - -/*! @brief Read current value of the LLWU_F1_WUF2 field. */ -#define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2)) - -/*! @brief Format value for bitfield LLWU_F1_WUF2. */ -#define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2) - -/*! @brief Set the WUF2 field to a new value. */ -#define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF3[3] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF3. - * - * Values: - * - 0 - LLWU_P3 input was not a wake-up source - * - 1 - LLWU_P3 input was a wake-up source - */ -/*@{*/ -#define BP_LLWU_F1_WUF3 (3U) /*!< Bit position for LLWU_F1_WUF3. */ -#define BM_LLWU_F1_WUF3 (0x08U) /*!< Bit mask for LLWU_F1_WUF3. */ -#define BS_LLWU_F1_WUF3 (1U) /*!< Bit field size in bits for LLWU_F1_WUF3. */ - -/*! @brief Read current value of the LLWU_F1_WUF3 field. */ -#define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3)) - -/*! @brief Format value for bitfield LLWU_F1_WUF3. */ -#define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3) - -/*! @brief Set the WUF3 field to a new value. */ -#define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF4[4] (W1C) - * - * Indicates that an enabled external wake-up pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF4. - * - * Values: - * - 0 - LLWU_P4 input was not a wakeup source - * - 1 - LLWU_P4 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF4 (4U) /*!< Bit position for LLWU_F1_WUF4. */ -#define BM_LLWU_F1_WUF4 (0x10U) /*!< Bit mask for LLWU_F1_WUF4. */ -#define BS_LLWU_F1_WUF4 (1U) /*!< Bit field size in bits for LLWU_F1_WUF4. */ - -/*! @brief Read current value of the LLWU_F1_WUF4 field. */ -#define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4)) - -/*! @brief Format value for bitfield LLWU_F1_WUF4. */ -#define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4) - -/*! @brief Set the WUF4 field to a new value. */ -#define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF5[5] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF5. - * - * Values: - * - 0 - LLWU_P5 input was not a wakeup source - * - 1 - LLWU_P5 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF5 (5U) /*!< Bit position for LLWU_F1_WUF5. */ -#define BM_LLWU_F1_WUF5 (0x20U) /*!< Bit mask for LLWU_F1_WUF5. */ -#define BS_LLWU_F1_WUF5 (1U) /*!< Bit field size in bits for LLWU_F1_WUF5. */ - -/*! @brief Read current value of the LLWU_F1_WUF5 field. */ -#define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5)) - -/*! @brief Format value for bitfield LLWU_F1_WUF5. */ -#define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5) - -/*! @brief Set the WUF5 field to a new value. */ -#define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF6[6] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF6. - * - * Values: - * - 0 - LLWU_P6 input was not a wakeup source - * - 1 - LLWU_P6 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF6 (6U) /*!< Bit position for LLWU_F1_WUF6. */ -#define BM_LLWU_F1_WUF6 (0x40U) /*!< Bit mask for LLWU_F1_WUF6. */ -#define BS_LLWU_F1_WUF6 (1U) /*!< Bit field size in bits for LLWU_F1_WUF6. */ - -/*! @brief Read current value of the LLWU_F1_WUF6 field. */ -#define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6)) - -/*! @brief Format value for bitfield LLWU_F1_WUF6. */ -#define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6) - -/*! @brief Set the WUF6 field to a new value. */ -#define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F1, field WUF7[7] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF7. - * - * Values: - * - 0 - LLWU_P7 input was not a wakeup source - * - 1 - LLWU_P7 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F1_WUF7 (7U) /*!< Bit position for LLWU_F1_WUF7. */ -#define BM_LLWU_F1_WUF7 (0x80U) /*!< Bit mask for LLWU_F1_WUF7. */ -#define BS_LLWU_F1_WUF7 (1U) /*!< Bit field size in bits for LLWU_F1_WUF7. */ - -/*! @brief Read current value of the LLWU_F1_WUF7 field. */ -#define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7)) - -/*! @brief Format value for bitfield LLWU_F1_WUF7. */ -#define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7) - -/*! @brief Set the WUF7 field to a new value. */ -#define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_F2 - LLWU Flag 2 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C) - * - * Reset value: 0x00U - * - * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the - * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU - * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The - * external wakeup flags are read-only and clearing a flag is accomplished by a write - * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will - * remain set if the associated WUPEx bit is cleared. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_f2 -{ - uint8_t U; - struct _hw_llwu_f2_bitfields - { - uint8_t WUF8 : 1; /*!< [0] Wakeup Flag For LLWU_P8 */ - uint8_t WUF9 : 1; /*!< [1] Wakeup Flag For LLWU_P9 */ - uint8_t WUF10 : 1; /*!< [2] Wakeup Flag For LLWU_P10 */ - uint8_t WUF11 : 1; /*!< [3] Wakeup Flag For LLWU_P11 */ - uint8_t WUF12 : 1; /*!< [4] Wakeup Flag For LLWU_P12 */ - uint8_t WUF13 : 1; /*!< [5] Wakeup Flag For LLWU_P13 */ - uint8_t WUF14 : 1; /*!< [6] Wakeup Flag For LLWU_P14 */ - uint8_t WUF15 : 1; /*!< [7] Wakeup Flag For LLWU_P15 */ - } B; -} hw_llwu_f2_t; - -/*! - * @name Constants and macros for entire LLWU_F2 register - */ -/*@{*/ -#define HW_LLWU_F2_ADDR(x) ((x) + 0x6U) - -#define HW_LLWU_F2(x) (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x)) -#define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U) -#define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v)) -#define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) | (v))) -#define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v))) -#define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_F2 bitfields - */ - -/*! - * @name Register LLWU_F2, field WUF8[0] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF8. - * - * Values: - * - 0 - LLWU_P8 input was not a wakeup source - * - 1 - LLWU_P8 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF8 (0U) /*!< Bit position for LLWU_F2_WUF8. */ -#define BM_LLWU_F2_WUF8 (0x01U) /*!< Bit mask for LLWU_F2_WUF8. */ -#define BS_LLWU_F2_WUF8 (1U) /*!< Bit field size in bits for LLWU_F2_WUF8. */ - -/*! @brief Read current value of the LLWU_F2_WUF8 field. */ -#define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8)) - -/*! @brief Format value for bitfield LLWU_F2_WUF8. */ -#define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8) - -/*! @brief Set the WUF8 field to a new value. */ -#define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF9[1] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF9. - * - * Values: - * - 0 - LLWU_P9 input was not a wakeup source - * - 1 - LLWU_P9 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF9 (1U) /*!< Bit position for LLWU_F2_WUF9. */ -#define BM_LLWU_F2_WUF9 (0x02U) /*!< Bit mask for LLWU_F2_WUF9. */ -#define BS_LLWU_F2_WUF9 (1U) /*!< Bit field size in bits for LLWU_F2_WUF9. */ - -/*! @brief Read current value of the LLWU_F2_WUF9 field. */ -#define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9)) - -/*! @brief Format value for bitfield LLWU_F2_WUF9. */ -#define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9) - -/*! @brief Set the WUF9 field to a new value. */ -#define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF10[2] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF10. - * - * Values: - * - 0 - LLWU_P10 input was not a wakeup source - * - 1 - LLWU_P10 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF10 (2U) /*!< Bit position for LLWU_F2_WUF10. */ -#define BM_LLWU_F2_WUF10 (0x04U) /*!< Bit mask for LLWU_F2_WUF10. */ -#define BS_LLWU_F2_WUF10 (1U) /*!< Bit field size in bits for LLWU_F2_WUF10. */ - -/*! @brief Read current value of the LLWU_F2_WUF10 field. */ -#define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10)) - -/*! @brief Format value for bitfield LLWU_F2_WUF10. */ -#define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10) - -/*! @brief Set the WUF10 field to a new value. */ -#define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF11[3] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF11. - * - * Values: - * - 0 - LLWU_P11 input was not a wakeup source - * - 1 - LLWU_P11 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF11 (3U) /*!< Bit position for LLWU_F2_WUF11. */ -#define BM_LLWU_F2_WUF11 (0x08U) /*!< Bit mask for LLWU_F2_WUF11. */ -#define BS_LLWU_F2_WUF11 (1U) /*!< Bit field size in bits for LLWU_F2_WUF11. */ - -/*! @brief Read current value of the LLWU_F2_WUF11 field. */ -#define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11)) - -/*! @brief Format value for bitfield LLWU_F2_WUF11. */ -#define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11) - -/*! @brief Set the WUF11 field to a new value. */ -#define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF12[4] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF12. - * - * Values: - * - 0 - LLWU_P12 input was not a wakeup source - * - 1 - LLWU_P12 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF12 (4U) /*!< Bit position for LLWU_F2_WUF12. */ -#define BM_LLWU_F2_WUF12 (0x10U) /*!< Bit mask for LLWU_F2_WUF12. */ -#define BS_LLWU_F2_WUF12 (1U) /*!< Bit field size in bits for LLWU_F2_WUF12. */ - -/*! @brief Read current value of the LLWU_F2_WUF12 field. */ -#define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12)) - -/*! @brief Format value for bitfield LLWU_F2_WUF12. */ -#define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12) - -/*! @brief Set the WUF12 field to a new value. */ -#define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF13[5] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF13. - * - * Values: - * - 0 - LLWU_P13 input was not a wakeup source - * - 1 - LLWU_P13 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF13 (5U) /*!< Bit position for LLWU_F2_WUF13. */ -#define BM_LLWU_F2_WUF13 (0x20U) /*!< Bit mask for LLWU_F2_WUF13. */ -#define BS_LLWU_F2_WUF13 (1U) /*!< Bit field size in bits for LLWU_F2_WUF13. */ - -/*! @brief Read current value of the LLWU_F2_WUF13 field. */ -#define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13)) - -/*! @brief Format value for bitfield LLWU_F2_WUF13. */ -#define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13) - -/*! @brief Set the WUF13 field to a new value. */ -#define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF14[6] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF14. - * - * Values: - * - 0 - LLWU_P14 input was not a wakeup source - * - 1 - LLWU_P14 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF14 (6U) /*!< Bit position for LLWU_F2_WUF14. */ -#define BM_LLWU_F2_WUF14 (0x40U) /*!< Bit mask for LLWU_F2_WUF14. */ -#define BS_LLWU_F2_WUF14 (1U) /*!< Bit field size in bits for LLWU_F2_WUF14. */ - -/*! @brief Read current value of the LLWU_F2_WUF14 field. */ -#define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14)) - -/*! @brief Format value for bitfield LLWU_F2_WUF14. */ -#define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14) - -/*! @brief Set the WUF14 field to a new value. */ -#define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_F2, field WUF15[7] (W1C) - * - * Indicates that an enabled external wakeup pin was a source of exiting a - * low-leakage power mode. To clear the flag, write a 1 to WUF15. - * - * Values: - * - 0 - LLWU_P15 input was not a wakeup source - * - 1 - LLWU_P15 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F2_WUF15 (7U) /*!< Bit position for LLWU_F2_WUF15. */ -#define BM_LLWU_F2_WUF15 (0x80U) /*!< Bit mask for LLWU_F2_WUF15. */ -#define BS_LLWU_F2_WUF15 (1U) /*!< Bit field size in bits for LLWU_F2_WUF15. */ - -/*! @brief Read current value of the LLWU_F2_WUF15 field. */ -#define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15)) - -/*! @brief Format value for bitfield LLWU_F2_WUF15. */ -#define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15) - -/*! @brief Set the WUF15 field to a new value. */ -#define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_F3 - LLWU Flag 3 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO) - * - * Reset value: 0x00U - * - * LLWU_F3 contains the wakeup flags indicating which internal wakeup source - * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the - * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. - * For internal peripherals that are capable of running in a low-leakage power - * mode, such as a real time clock module or CMP module, the flag from the - * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared - * in the peripheral instead of writing a 1 to the MWUFx bit. This register is - * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not - * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See - * the IntroductionInformation found here describes the registers of the Reset - * Control Module (RCM). The RCM implements many of the reset functions for the - * chip. See the chip's reset chapter for more information. details for more - * information. - */ -typedef union _hw_llwu_f3 -{ - uint8_t U; - struct _hw_llwu_f3_bitfields - { - uint8_t MWUF0 : 1; /*!< [0] Wakeup flag For module 0 */ - uint8_t MWUF1 : 1; /*!< [1] Wakeup flag For module 1 */ - uint8_t MWUF2 : 1; /*!< [2] Wakeup flag For module 2 */ - uint8_t MWUF3 : 1; /*!< [3] Wakeup flag For module 3 */ - uint8_t MWUF4 : 1; /*!< [4] Wakeup flag For module 4 */ - uint8_t MWUF5 : 1; /*!< [5] Wakeup flag For module 5 */ - uint8_t MWUF6 : 1; /*!< [6] Wakeup flag For module 6 */ - uint8_t MWUF7 : 1; /*!< [7] Wakeup flag For module 7 */ - } B; -} hw_llwu_f3_t; - -/*! - * @name Constants and macros for entire LLWU_F3 register - */ -/*@{*/ -#define HW_LLWU_F3_ADDR(x) ((x) + 0x7U) - -#define HW_LLWU_F3(x) (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x)) -#define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U) -/*@}*/ - -/* - * Constants & macros for individual LLWU_F3 bitfields - */ - -/*! - * @name Register LLWU_F3, field MWUF0[0] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 0 input was not a wakeup source - * - 1 - Module 0 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF0 (0U) /*!< Bit position for LLWU_F3_MWUF0. */ -#define BM_LLWU_F3_MWUF0 (0x01U) /*!< Bit mask for LLWU_F3_MWUF0. */ -#define BS_LLWU_F3_MWUF0 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF0. */ - -/*! @brief Read current value of the LLWU_F3_MWUF0 field. */ -#define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF1[1] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 1 input was not a wakeup source - * - 1 - Module 1 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF1 (1U) /*!< Bit position for LLWU_F3_MWUF1. */ -#define BM_LLWU_F3_MWUF1 (0x02U) /*!< Bit mask for LLWU_F3_MWUF1. */ -#define BS_LLWU_F3_MWUF1 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF1. */ - -/*! @brief Read current value of the LLWU_F3_MWUF1 field. */ -#define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF2[2] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 2 input was not a wakeup source - * - 1 - Module 2 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF2 (2U) /*!< Bit position for LLWU_F3_MWUF2. */ -#define BM_LLWU_F3_MWUF2 (0x04U) /*!< Bit mask for LLWU_F3_MWUF2. */ -#define BS_LLWU_F3_MWUF2 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF2. */ - -/*! @brief Read current value of the LLWU_F3_MWUF2 field. */ -#define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF3[3] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 3 input was not a wakeup source - * - 1 - Module 3 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF3 (3U) /*!< Bit position for LLWU_F3_MWUF3. */ -#define BM_LLWU_F3_MWUF3 (0x08U) /*!< Bit mask for LLWU_F3_MWUF3. */ -#define BS_LLWU_F3_MWUF3 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF3. */ - -/*! @brief Read current value of the LLWU_F3_MWUF3 field. */ -#define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF4[4] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 4 input was not a wakeup source - * - 1 - Module 4 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF4 (4U) /*!< Bit position for LLWU_F3_MWUF4. */ -#define BM_LLWU_F3_MWUF4 (0x10U) /*!< Bit mask for LLWU_F3_MWUF4. */ -#define BS_LLWU_F3_MWUF4 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF4. */ - -/*! @brief Read current value of the LLWU_F3_MWUF4 field. */ -#define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF5[5] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 5 input was not a wakeup source - * - 1 - Module 5 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF5 (5U) /*!< Bit position for LLWU_F3_MWUF5. */ -#define BM_LLWU_F3_MWUF5 (0x20U) /*!< Bit mask for LLWU_F3_MWUF5. */ -#define BS_LLWU_F3_MWUF5 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF5. */ - -/*! @brief Read current value of the LLWU_F3_MWUF5 field. */ -#define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF6[6] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 6 input was not a wakeup source - * - 1 - Module 6 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF6 (6U) /*!< Bit position for LLWU_F3_MWUF6. */ -#define BM_LLWU_F3_MWUF6 (0x40U) /*!< Bit mask for LLWU_F3_MWUF6. */ -#define BS_LLWU_F3_MWUF6 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF6. */ - -/*! @brief Read current value of the LLWU_F3_MWUF6 field. */ -#define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6)) -/*@}*/ - -/*! - * @name Register LLWU_F3, field MWUF7[7] (RO) - * - * Indicates that an enabled internal peripheral was a source of exiting a - * low-leakage power mode. To clear the flag, follow the internal peripheral flag - * clearing mechanism. - * - * Values: - * - 0 - Module 7 input was not a wakeup source - * - 1 - Module 7 input was a wakeup source - */ -/*@{*/ -#define BP_LLWU_F3_MWUF7 (7U) /*!< Bit position for LLWU_F3_MWUF7. */ -#define BM_LLWU_F3_MWUF7 (0x80U) /*!< Bit mask for LLWU_F3_MWUF7. */ -#define BS_LLWU_F3_MWUF7 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF7. */ - -/*! @brief Read current value of the LLWU_F3_MWUF7 field. */ -#define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_FILT1 - LLWU Pin Filter 1 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW) - * - * Reset value: 0x00U - * - * LLWU_FILT1 is a control and status register that is used to enable/disable - * the digital filter 1 features for an external pin. This register is reset on - * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See - * the chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_filt1 -{ - uint8_t U; - struct _hw_llwu_filt1_bitfields - { - uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */ - uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */ - } B; -} hw_llwu_filt1_t; - -/*! - * @name Constants and macros for entire LLWU_FILT1 register - */ -/*@{*/ -#define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U) - -#define HW_LLWU_FILT1(x) (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x)) -#define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U) -#define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v)) -#define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) | (v))) -#define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v))) -#define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_FILT1 bitfields - */ - -/*! - * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW) - * - * Selects 1 out of the 16 wakeup pins to be muxed into the filter. - * - * Values: - * - 0000 - Select LLWU_P0 for filter - * - 1111 - Select LLWU_P15 for filter - */ -/*@{*/ -#define BP_LLWU_FILT1_FILTSEL (0U) /*!< Bit position for LLWU_FILT1_FILTSEL. */ -#define BM_LLWU_FILT1_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT1_FILTSEL. */ -#define BS_LLWU_FILT1_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */ - -/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */ -#define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL) - -/*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */ -#define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL) - -/*! @brief Set the FILTSEL field to a new value. */ -#define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT1, field FILTE[6:5] (RW) - * - * Controls the digital filter options for the external pin detect. - * - * Values: - * - 00 - Filter disabled - * - 01 - Filter posedge detect enabled - * - 10 - Filter negedge detect enabled - * - 11 - Filter any edge detect enabled - */ -/*@{*/ -#define BP_LLWU_FILT1_FILTE (5U) /*!< Bit position for LLWU_FILT1_FILTE. */ -#define BM_LLWU_FILT1_FILTE (0x60U) /*!< Bit mask for LLWU_FILT1_FILTE. */ -#define BS_LLWU_FILT1_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT1_FILTE. */ - -/*! @brief Read current value of the LLWU_FILT1_FILTE field. */ -#define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE) - -/*! @brief Format value for bitfield LLWU_FILT1_FILTE. */ -#define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE) - -/*! @brief Set the FILTE field to a new value. */ -#define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT1, field FILTF[7] (W1C) - * - * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a - * source of exiting a low-leakage power mode. To clear the flag write a one to - * FILTF. - * - * Values: - * - 0 - Pin Filter 1 was not a wakeup source - * - 1 - Pin Filter 1 was a wakeup source - */ -/*@{*/ -#define BP_LLWU_FILT1_FILTF (7U) /*!< Bit position for LLWU_FILT1_FILTF. */ -#define BM_LLWU_FILT1_FILTF (0x80U) /*!< Bit mask for LLWU_FILT1_FILTF. */ -#define BS_LLWU_FILT1_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT1_FILTF. */ - -/*! @brief Read current value of the LLWU_FILT1_FILTF field. */ -#define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF)) - -/*! @brief Format value for bitfield LLWU_FILT1_FILTF. */ -#define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF) - -/*! @brief Set the FILTF field to a new value. */ -#define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_FILT2 - LLWU Pin Filter 2 register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW) - * - * Reset value: 0x00U - * - * LLWU_FILT2 is a control and status register that is used to enable/disable - * the digital filter 2 features for an external pin. This register is reset on - * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See - * the chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_filt2 -{ - uint8_t U; - struct _hw_llwu_filt2_bitfields - { - uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */ - uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */ - } B; -} hw_llwu_filt2_t; - -/*! - * @name Constants and macros for entire LLWU_FILT2 register - */ -/*@{*/ -#define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U) - -#define HW_LLWU_FILT2(x) (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x)) -#define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U) -#define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v)) -#define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) | (v))) -#define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v))) -#define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_FILT2 bitfields - */ - -/*! - * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW) - * - * Selects 1 out of the 16 wakeup pins to be muxed into the filter. - * - * Values: - * - 0000 - Select LLWU_P0 for filter - * - 1111 - Select LLWU_P15 for filter - */ -/*@{*/ -#define BP_LLWU_FILT2_FILTSEL (0U) /*!< Bit position for LLWU_FILT2_FILTSEL. */ -#define BM_LLWU_FILT2_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT2_FILTSEL. */ -#define BS_LLWU_FILT2_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */ - -/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */ -#define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL) - -/*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */ -#define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL) - -/*! @brief Set the FILTSEL field to a new value. */ -#define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT2, field FILTE[6:5] (RW) - * - * Controls the digital filter options for the external pin detect. - * - * Values: - * - 00 - Filter disabled - * - 01 - Filter posedge detect enabled - * - 10 - Filter negedge detect enabled - * - 11 - Filter any edge detect enabled - */ -/*@{*/ -#define BP_LLWU_FILT2_FILTE (5U) /*!< Bit position for LLWU_FILT2_FILTE. */ -#define BM_LLWU_FILT2_FILTE (0x60U) /*!< Bit mask for LLWU_FILT2_FILTE. */ -#define BS_LLWU_FILT2_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT2_FILTE. */ - -/*! @brief Read current value of the LLWU_FILT2_FILTE field. */ -#define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE) - -/*! @brief Format value for bitfield LLWU_FILT2_FILTE. */ -#define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE) - -/*! @brief Set the FILTE field to a new value. */ -#define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v))) -/*@}*/ - -/*! - * @name Register LLWU_FILT2, field FILTF[7] (W1C) - * - * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a - * source of exiting a low-leakage power mode. To clear the flag write a one to - * FILTF. - * - * Values: - * - 0 - Pin Filter 2 was not a wakeup source - * - 1 - Pin Filter 2 was a wakeup source - */ -/*@{*/ -#define BP_LLWU_FILT2_FILTF (7U) /*!< Bit position for LLWU_FILT2_FILTF. */ -#define BM_LLWU_FILT2_FILTF (0x80U) /*!< Bit mask for LLWU_FILT2_FILTF. */ -#define BS_LLWU_FILT2_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT2_FILTF. */ - -/*! @brief Read current value of the LLWU_FILT2_FILTF field. */ -#define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF)) - -/*! @brief Format value for bitfield LLWU_FILT2_FILTF. */ -#define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF) - -/*! @brief Set the FILTF field to a new value. */ -#define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LLWU_RST - LLWU Reset Enable register - ******************************************************************************/ - -/*! - * @brief HW_LLWU_RST - LLWU Reset Enable register (RW) - * - * Reset value: 0x02U - * - * LLWU_RST is a control register that is used to enable/disable the digital - * filter for the external pin detect and RESET pin. This register is reset on Chip - * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is - * unaffected by reset types that do not trigger Chip Reset not VLLS. See the - * IntroductionInformation found here describes the registers of the Reset Control - * Module (RCM). The RCM implements many of the reset functions for the chip. See the - * chip's reset chapter for more information. details for more information. - */ -typedef union _hw_llwu_rst -{ - uint8_t U; - struct _hw_llwu_rst_bitfields - { - uint8_t RSTFILT : 1; /*!< [0] Digital Filter On RESET Pin */ - uint8_t LLRSTE : 1; /*!< [1] Low-Leakage Mode RESET Enable */ - uint8_t RESERVED0 : 6; /*!< [7:2] */ - } B; -} hw_llwu_rst_t; - -/*! - * @name Constants and macros for entire LLWU_RST register - */ -/*@{*/ -#define HW_LLWU_RST_ADDR(x) ((x) + 0xAU) - -#define HW_LLWU_RST(x) (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR(x)) -#define HW_LLWU_RST_RD(x) (HW_LLWU_RST(x).U) -#define HW_LLWU_RST_WR(x, v) (HW_LLWU_RST(x).U = (v)) -#define HW_LLWU_RST_SET(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) | (v))) -#define HW_LLWU_RST_CLR(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) & ~(v))) -#define HW_LLWU_RST_TOG(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LLWU_RST bitfields - */ - -/*! - * @name Register LLWU_RST, field RSTFILT[0] (RW) - * - * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or - * VLLS1 modes. - * - * Values: - * - 0 - Filter not enabled - * - 1 - Filter enabled - */ -/*@{*/ -#define BP_LLWU_RST_RSTFILT (0U) /*!< Bit position for LLWU_RST_RSTFILT. */ -#define BM_LLWU_RST_RSTFILT (0x01U) /*!< Bit mask for LLWU_RST_RSTFILT. */ -#define BS_LLWU_RST_RSTFILT (1U) /*!< Bit field size in bits for LLWU_RST_RSTFILT. */ - -/*! @brief Read current value of the LLWU_RST_RSTFILT field. */ -#define BR_LLWU_RST_RSTFILT(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT)) - -/*! @brief Format value for bitfield LLWU_RST_RSTFILT. */ -#define BF_LLWU_RST_RSTFILT(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_RSTFILT) & BM_LLWU_RST_RSTFILT) - -/*! @brief Set the RSTFILT field to a new value. */ -#define BW_LLWU_RST_RSTFILT(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT) = (v)) -/*@}*/ - -/*! - * @name Register LLWU_RST, field LLRSTE[1] (RW) - * - * This bit must be set to allow the device to be reset while in a low-leakage - * power mode. On devices where Reset is not a dedicated pin, the RESET pin must - * also be enabled in the explicit port mux control. - * - * Values: - * - 0 - RESET pin not enabled as a leakage mode exit source - * - 1 - RESET pin enabled as a low leakage mode exit source - */ -/*@{*/ -#define BP_LLWU_RST_LLRSTE (1U) /*!< Bit position for LLWU_RST_LLRSTE. */ -#define BM_LLWU_RST_LLRSTE (0x02U) /*!< Bit mask for LLWU_RST_LLRSTE. */ -#define BS_LLWU_RST_LLRSTE (1U) /*!< Bit field size in bits for LLWU_RST_LLRSTE. */ - -/*! @brief Read current value of the LLWU_RST_LLRSTE field. */ -#define BR_LLWU_RST_LLRSTE(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE)) - -/*! @brief Format value for bitfield LLWU_RST_LLRSTE. */ -#define BF_LLWU_RST_LLRSTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_LLRSTE) & BM_LLWU_RST_LLRSTE) - -/*! @brief Set the LLRSTE field to a new value. */ -#define BW_LLWU_RST_LLRSTE(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_llwu_t - module struct - ******************************************************************************/ -/*! - * @brief All LLWU module registers. - */ -#pragma pack(1) -typedef struct _hw_llwu -{ - __IO hw_llwu_pe1_t PE1; /*!< [0x0] LLWU Pin Enable 1 register */ - __IO hw_llwu_pe2_t PE2; /*!< [0x1] LLWU Pin Enable 2 register */ - __IO hw_llwu_pe3_t PE3; /*!< [0x2] LLWU Pin Enable 3 register */ - __IO hw_llwu_pe4_t PE4; /*!< [0x3] LLWU Pin Enable 4 register */ - __IO hw_llwu_me_t ME; /*!< [0x4] LLWU Module Enable register */ - __IO hw_llwu_f1_t F1; /*!< [0x5] LLWU Flag 1 register */ - __IO hw_llwu_f2_t F2; /*!< [0x6] LLWU Flag 2 register */ - __I hw_llwu_f3_t F3; /*!< [0x7] LLWU Flag 3 register */ - __IO hw_llwu_filt1_t FILT1; /*!< [0x8] LLWU Pin Filter 1 register */ - __IO hw_llwu_filt2_t FILT2; /*!< [0x9] LLWU Pin Filter 2 register */ - __IO hw_llwu_rst_t RST; /*!< [0xA] LLWU Reset Enable register */ -} hw_llwu_t; -#pragma pack() - -/*! @brief Macro to access all LLWU registers. */ -/*! @param x LLWU module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_LLWU(LLWU_BASE). */ -#define HW_LLWU(x) (*(hw_llwu_t *)(x)) - -#endif /* __HW_LLWU_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_lptmr.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_lptmr.h deleted file mode 100644 index 6cffedb7cb7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_lptmr.h +++ /dev/null @@ -1,617 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_LPTMR_REGISTERS_H__ -#define __HW_LPTMR_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 LPTMR - * - * Low Power Timer - * - * Registers defined in this header file: - * - HW_LPTMR_CSR - Low Power Timer Control Status Register - * - HW_LPTMR_PSR - Low Power Timer Prescale Register - * - HW_LPTMR_CMR - Low Power Timer Compare Register - * - HW_LPTMR_CNR - Low Power Timer Counter Register - * - * - hw_lptmr_t - Struct containing all module registers. - */ - -#define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */ - -/******************************************************************************* - * HW_LPTMR_CSR - Low Power Timer Control Status Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_csr -{ - uint32_t U; - struct _hw_lptmr_csr_bitfields - { - uint32_t TEN : 1; /*!< [0] Timer Enable */ - uint32_t TMS : 1; /*!< [1] Timer Mode Select */ - uint32_t TFC : 1; /*!< [2] Timer Free-Running Counter */ - uint32_t TPP : 1; /*!< [3] Timer Pin Polarity */ - uint32_t TPS : 2; /*!< [5:4] Timer Pin Select */ - uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */ - uint32_t TCF : 1; /*!< [7] Timer Compare Flag */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_lptmr_csr_t; - -/*! - * @name Constants and macros for entire LPTMR_CSR register - */ -/*@{*/ -#define HW_LPTMR_CSR_ADDR(x) ((x) + 0x0U) - -#define HW_LPTMR_CSR(x) (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x)) -#define HW_LPTMR_CSR_RD(x) (HW_LPTMR_CSR(x).U) -#define HW_LPTMR_CSR_WR(x, v) (HW_LPTMR_CSR(x).U = (v)) -#define HW_LPTMR_CSR_SET(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) | (v))) -#define HW_LPTMR_CSR_CLR(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v))) -#define HW_LPTMR_CSR_TOG(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_CSR bitfields - */ - -/*! - * @name Register LPTMR_CSR, field TEN[0] (RW) - * - * When TEN is clear, it resets the LPTMR internal logic, including the CNR and - * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field, - * CSR[5:1] must not be altered. - * - * Values: - * - 0 - LPTMR is disabled and internal logic is reset. - * - 1 - LPTMR is enabled. - */ -/*@{*/ -#define BP_LPTMR_CSR_TEN (0U) /*!< Bit position for LPTMR_CSR_TEN. */ -#define BM_LPTMR_CSR_TEN (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */ -#define BS_LPTMR_CSR_TEN (1U) /*!< Bit field size in bits for LPTMR_CSR_TEN. */ - -/*! @brief Read current value of the LPTMR_CSR_TEN field. */ -#define BR_LPTMR_CSR_TEN(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN)) - -/*! @brief Format value for bitfield LPTMR_CSR_TEN. */ -#define BF_LPTMR_CSR_TEN(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN) - -/*! @brief Set the TEN field to a new value. */ -#define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TMS[1] (RW) - * - * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is - * disabled. - * - * Values: - * - 0 - Time Counter mode. - * - 1 - Pulse Counter mode. - */ -/*@{*/ -#define BP_LPTMR_CSR_TMS (1U) /*!< Bit position for LPTMR_CSR_TMS. */ -#define BM_LPTMR_CSR_TMS (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */ -#define BS_LPTMR_CSR_TMS (1U) /*!< Bit field size in bits for LPTMR_CSR_TMS. */ - -/*! @brief Read current value of the LPTMR_CSR_TMS field. */ -#define BR_LPTMR_CSR_TMS(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS)) - -/*! @brief Format value for bitfield LPTMR_CSR_TMS. */ -#define BF_LPTMR_CSR_TMS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS) - -/*! @brief Set the TMS field to a new value. */ -#define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TFC[2] (RW) - * - * When clear, TFC configures the CNR to reset whenever TCF is set. When set, - * TFC configures the CNR to reset on overflow. TFC must be altered only when the - * LPTMR is disabled. - * - * Values: - * - 0 - CNR is reset whenever TCF is set. - * - 1 - CNR is reset on overflow. - */ -/*@{*/ -#define BP_LPTMR_CSR_TFC (2U) /*!< Bit position for LPTMR_CSR_TFC. */ -#define BM_LPTMR_CSR_TFC (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */ -#define BS_LPTMR_CSR_TFC (1U) /*!< Bit field size in bits for LPTMR_CSR_TFC. */ - -/*! @brief Read current value of the LPTMR_CSR_TFC field. */ -#define BR_LPTMR_CSR_TFC(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC)) - -/*! @brief Format value for bitfield LPTMR_CSR_TFC. */ -#define BF_LPTMR_CSR_TFC(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC) - -/*! @brief Set the TFC field to a new value. */ -#define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TPP[3] (RW) - * - * Configures the polarity of the input source in Pulse Counter mode. TPP must - * be changed only when the LPTMR is disabled. - * - * Values: - * - 0 - Pulse Counter input source is active-high, and the CNR will increment - * on the rising-edge. - * - 1 - Pulse Counter input source is active-low, and the CNR will increment on - * the falling-edge. - */ -/*@{*/ -#define BP_LPTMR_CSR_TPP (3U) /*!< Bit position for LPTMR_CSR_TPP. */ -#define BM_LPTMR_CSR_TPP (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */ -#define BS_LPTMR_CSR_TPP (1U) /*!< Bit field size in bits for LPTMR_CSR_TPP. */ - -/*! @brief Read current value of the LPTMR_CSR_TPP field. */ -#define BR_LPTMR_CSR_TPP(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP)) - -/*! @brief Format value for bitfield LPTMR_CSR_TPP. */ -#define BF_LPTMR_CSR_TPP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP) - -/*! @brief Set the TPP field to a new value. */ -#define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TPS[5:4] (RW) - * - * Configures the input source to be used in Pulse Counter mode. TPS must be - * altered only when the LPTMR is disabled. The input connections vary by device. - * See the chip configuration details for information on the connections to these - * inputs. - * - * Values: - * - 00 - Pulse counter input 0 is selected. - * - 01 - Pulse counter input 1 is selected. - * - 10 - Pulse counter input 2 is selected. - * - 11 - Pulse counter input 3 is selected. - */ -/*@{*/ -#define BP_LPTMR_CSR_TPS (4U) /*!< Bit position for LPTMR_CSR_TPS. */ -#define BM_LPTMR_CSR_TPS (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */ -#define BS_LPTMR_CSR_TPS (2U) /*!< Bit field size in bits for LPTMR_CSR_TPS. */ - -/*! @brief Read current value of the LPTMR_CSR_TPS field. */ -#define BR_LPTMR_CSR_TPS(x) (HW_LPTMR_CSR(x).B.TPS) - -/*! @brief Format value for bitfield LPTMR_CSR_TPS. */ -#define BF_LPTMR_CSR_TPS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS) - -/*! @brief Set the TPS field to a new value. */ -#define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v))) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TIE[6] (RW) - * - * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set. - * - * Values: - * - 0 - Timer interrupt disabled. - * - 1 - Timer interrupt enabled. - */ -/*@{*/ -#define BP_LPTMR_CSR_TIE (6U) /*!< Bit position for LPTMR_CSR_TIE. */ -#define BM_LPTMR_CSR_TIE (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */ -#define BS_LPTMR_CSR_TIE (1U) /*!< Bit field size in bits for LPTMR_CSR_TIE. */ - -/*! @brief Read current value of the LPTMR_CSR_TIE field. */ -#define BR_LPTMR_CSR_TIE(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE)) - -/*! @brief Format value for bitfield LPTMR_CSR_TIE. */ -#define BF_LPTMR_CSR_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_CSR, field TCF[7] (W1C) - * - * TCF is set when the LPTMR is enabled and the CNR equals the CMR and - * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it. - * - * Values: - * - 0 - The value of CNR is not equal to CMR and increments. - * - 1 - The value of CNR is equal to CMR and increments. - */ -/*@{*/ -#define BP_LPTMR_CSR_TCF (7U) /*!< Bit position for LPTMR_CSR_TCF. */ -#define BM_LPTMR_CSR_TCF (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */ -#define BS_LPTMR_CSR_TCF (1U) /*!< Bit field size in bits for LPTMR_CSR_TCF. */ - -/*! @brief Read current value of the LPTMR_CSR_TCF field. */ -#define BR_LPTMR_CSR_TCF(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF)) - -/*! @brief Format value for bitfield LPTMR_CSR_TCF. */ -#define BF_LPTMR_CSR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF) - -/*! @brief Set the TCF field to a new value. */ -#define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_LPTMR_PSR - Low Power Timer Prescale Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_psr -{ - uint32_t U; - struct _hw_lptmr_psr_bitfields - { - uint32_t PCS : 2; /*!< [1:0] Prescaler Clock Select */ - uint32_t PBYP : 1; /*!< [2] Prescaler Bypass */ - uint32_t PRESCALE : 4; /*!< [6:3] Prescale Value */ - uint32_t RESERVED0 : 25; /*!< [31:7] */ - } B; -} hw_lptmr_psr_t; - -/*! - * @name Constants and macros for entire LPTMR_PSR register - */ -/*@{*/ -#define HW_LPTMR_PSR_ADDR(x) ((x) + 0x4U) - -#define HW_LPTMR_PSR(x) (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x)) -#define HW_LPTMR_PSR_RD(x) (HW_LPTMR_PSR(x).U) -#define HW_LPTMR_PSR_WR(x, v) (HW_LPTMR_PSR(x).U = (v)) -#define HW_LPTMR_PSR_SET(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) | (v))) -#define HW_LPTMR_PSR_CLR(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v))) -#define HW_LPTMR_PSR_TOG(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_PSR bitfields - */ - -/*! - * @name Register LPTMR_PSR, field PCS[1:0] (RW) - * - * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must - * be altered only when the LPTMR is disabled. The clock connections vary by - * device. See the chip configuration details for information on the connections to - * these inputs. - * - * Values: - * - 00 - Prescaler/glitch filter clock 0 selected. - * - 01 - Prescaler/glitch filter clock 1 selected. - * - 10 - Prescaler/glitch filter clock 2 selected. - * - 11 - Prescaler/glitch filter clock 3 selected. - */ -/*@{*/ -#define BP_LPTMR_PSR_PCS (0U) /*!< Bit position for LPTMR_PSR_PCS. */ -#define BM_LPTMR_PSR_PCS (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */ -#define BS_LPTMR_PSR_PCS (2U) /*!< Bit field size in bits for LPTMR_PSR_PCS. */ - -/*! @brief Read current value of the LPTMR_PSR_PCS field. */ -#define BR_LPTMR_PSR_PCS(x) (HW_LPTMR_PSR(x).B.PCS) - -/*! @brief Format value for bitfield LPTMR_PSR_PCS. */ -#define BF_LPTMR_PSR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS) - -/*! @brief Set the PCS field to a new value. */ -#define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v))) -/*@}*/ - -/*! - * @name Register LPTMR_PSR, field PBYP[2] (RW) - * - * When PBYP is set, the selected prescaler clock in Time Counter mode or - * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is - * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP - * must be altered only when the LPTMR is disabled. - * - * Values: - * - 0 - Prescaler/glitch filter is enabled. - * - 1 - Prescaler/glitch filter is bypassed. - */ -/*@{*/ -#define BP_LPTMR_PSR_PBYP (2U) /*!< Bit position for LPTMR_PSR_PBYP. */ -#define BM_LPTMR_PSR_PBYP (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */ -#define BS_LPTMR_PSR_PBYP (1U) /*!< Bit field size in bits for LPTMR_PSR_PBYP. */ - -/*! @brief Read current value of the LPTMR_PSR_PBYP field. */ -#define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP)) - -/*! @brief Format value for bitfield LPTMR_PSR_PBYP. */ -#define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP) - -/*! @brief Set the PBYP field to a new value. */ -#define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v)) -/*@}*/ - -/*! - * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW) - * - * Configures the size of the Prescaler in Time Counter mode or width of the - * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR - * is disabled. - * - * Values: - * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not - * support this configuration. - * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes - * change on input pin after 2 rising clock edges. - * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes - * change on input pin after 4 rising clock edges. - * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter - * recognizes change on input pin after 8 rising clock edges. - * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter - * recognizes change on input pin after 16 rising clock edges. - * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter - * recognizes change on input pin after 32 rising clock edges. - * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter - * recognizes change on input pin after 64 rising clock edges. - * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter - * recognizes change on input pin after 128 rising clock edges. - * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter - * recognizes change on input pin after 256 rising clock edges. - * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter - * recognizes change on input pin after 512 rising clock edges. - * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter - * recognizes change on input pin after 1024 rising clock edges. - * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter - * recognizes change on input pin after 2048 rising clock edges. - * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter - * recognizes change on input pin after 4096 rising clock edges. - * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter - * recognizes change on input pin after 8192 rising clock edges. - * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter - * recognizes change on input pin after 16,384 rising clock edges. - * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter - * recognizes change on input pin after 32,768 rising clock edges. - */ -/*@{*/ -#define BP_LPTMR_PSR_PRESCALE (3U) /*!< Bit position for LPTMR_PSR_PRESCALE. */ -#define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */ -#define BS_LPTMR_PSR_PRESCALE (4U) /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */ - -/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */ -#define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE) - -/*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */ -#define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE) - -/*! @brief Set the PRESCALE field to a new value. */ -#define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v))) -/*@}*/ - -/******************************************************************************* - * HW_LPTMR_CMR - Low Power Timer Compare Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_cmr -{ - uint32_t U; - struct _hw_lptmr_cmr_bitfields - { - uint32_t COMPARE : 16; /*!< [15:0] Compare Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_lptmr_cmr_t; - -/*! - * @name Constants and macros for entire LPTMR_CMR register - */ -/*@{*/ -#define HW_LPTMR_CMR_ADDR(x) ((x) + 0x8U) - -#define HW_LPTMR_CMR(x) (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x)) -#define HW_LPTMR_CMR_RD(x) (HW_LPTMR_CMR(x).U) -#define HW_LPTMR_CMR_WR(x, v) (HW_LPTMR_CMR(x).U = (v)) -#define HW_LPTMR_CMR_SET(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) | (v))) -#define HW_LPTMR_CMR_CLR(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v))) -#define HW_LPTMR_CMR_TOG(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_CMR bitfields - */ - -/*! - * @name Register LPTMR_CMR, field COMPARE[15:0] (RW) - * - * When the LPTMR is enabled and the CNR equals the value in the CMR and - * increments, TCF is set and the hardware trigger asserts until the next time the CNR - * increments. If the CMR is 0, the hardware trigger will remain asserted until - * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only - * when TCF is set. - */ -/*@{*/ -#define BP_LPTMR_CMR_COMPARE (0U) /*!< Bit position for LPTMR_CMR_COMPARE. */ -#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */ -#define BS_LPTMR_CMR_COMPARE (16U) /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */ - -/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */ -#define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE) - -/*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */ -#define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE) - -/*! @brief Set the COMPARE field to a new value. */ -#define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v))) -/*@}*/ - -/******************************************************************************* - * HW_LPTMR_CNR - Low Power Timer Counter Register - ******************************************************************************/ - -/*! - * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_lptmr_cnr -{ - uint32_t U; - struct _hw_lptmr_cnr_bitfields - { - uint32_t COUNTER : 16; /*!< [15:0] Counter Value */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_lptmr_cnr_t; - -/*! - * @name Constants and macros for entire LPTMR_CNR register - */ -/*@{*/ -#define HW_LPTMR_CNR_ADDR(x) ((x) + 0xCU) - -#define HW_LPTMR_CNR(x) (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x)) -#define HW_LPTMR_CNR_RD(x) (HW_LPTMR_CNR(x).U) -#define HW_LPTMR_CNR_WR(x, v) (HW_LPTMR_CNR(x).U = (v)) -#define HW_LPTMR_CNR_SET(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) | (v))) -#define HW_LPTMR_CNR_CLR(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v))) -#define HW_LPTMR_CNR_TOG(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual LPTMR_CNR bitfields - */ - -/*! - * @name Register LPTMR_CNR, field COUNTER[15:0] (RW) - */ -/*@{*/ -#define BP_LPTMR_CNR_COUNTER (0U) /*!< Bit position for LPTMR_CNR_COUNTER. */ -#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */ -#define BS_LPTMR_CNR_COUNTER (16U) /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */ - -/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */ -#define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER) - -/*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */ -#define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER) - -/*! @brief Set the COUNTER field to a new value. */ -#define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v))) -/*@}*/ - -/******************************************************************************* - * hw_lptmr_t - module struct - ******************************************************************************/ -/*! - * @brief All LPTMR module registers. - */ -#pragma pack(1) -typedef struct _hw_lptmr -{ - __IO hw_lptmr_csr_t CSR; /*!< [0x0] Low Power Timer Control Status Register */ - __IO hw_lptmr_psr_t PSR; /*!< [0x4] Low Power Timer Prescale Register */ - __IO hw_lptmr_cmr_t CMR; /*!< [0x8] Low Power Timer Compare Register */ - __IO hw_lptmr_cnr_t CNR; /*!< [0xC] Low Power Timer Counter Register */ -} hw_lptmr_t; -#pragma pack() - -/*! @brief Macro to access all LPTMR registers. */ -/*! @param x LPTMR module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_LPTMR(LPTMR0_BASE). */ -#define HW_LPTMR(x) (*(hw_lptmr_t *)(x)) - -#endif /* __HW_LPTMR_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcg.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcg.h deleted file mode 100644 index b120912b4c9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcg.h +++ /dev/null @@ -1,1782 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_MCG_REGISTERS_H__ -#define __HW_MCG_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 MCG - * - * Multipurpose Clock Generator module - * - * Registers defined in this header file: - * - HW_MCG_C1 - MCG Control 1 Register - * - HW_MCG_C2 - MCG Control 2 Register - * - HW_MCG_C3 - MCG Control 3 Register - * - HW_MCG_C4 - MCG Control 4 Register - * - HW_MCG_C5 - MCG Control 5 Register - * - HW_MCG_C6 - MCG Control 6 Register - * - HW_MCG_S - MCG Status Register - * - HW_MCG_SC - MCG Status and Control Register - * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register - * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register - * - HW_MCG_C7 - MCG Control 7 Register - * - HW_MCG_C8 - MCG Control 8 Register - * - * - hw_mcg_t - Struct containing all module registers. - */ - -#define HW_MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */ - -/******************************************************************************* - * HW_MCG_C1 - MCG Control 1 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C1 - MCG Control 1 Register (RW) - * - * Reset value: 0x04U - */ -typedef union _hw_mcg_c1 -{ - uint8_t U; - struct _hw_mcg_c1_bitfields - { - uint8_t IREFSTEN : 1; /*!< [0] Internal Reference Stop Enable */ - uint8_t IRCLKEN : 1; /*!< [1] Internal Reference Clock Enable */ - uint8_t IREFS : 1; /*!< [2] Internal Reference Select */ - uint8_t FRDIV : 3; /*!< [5:3] FLL External Reference Divider */ - uint8_t CLKS : 2; /*!< [7:6] Clock Source Select */ - } B; -} hw_mcg_c1_t; - -/*! - * @name Constants and macros for entire MCG_C1 register - */ -/*@{*/ -#define HW_MCG_C1_ADDR(x) ((x) + 0x0U) - -#define HW_MCG_C1(x) (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR(x)) -#define HW_MCG_C1_RD(x) (HW_MCG_C1(x).U) -#define HW_MCG_C1_WR(x, v) (HW_MCG_C1(x).U = (v)) -#define HW_MCG_C1_SET(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) | (v))) -#define HW_MCG_C1_CLR(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) & ~(v))) -#define HW_MCG_C1_TOG(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C1 bitfields - */ - -/*! - * @name Register MCG_C1, field IREFSTEN[0] (RW) - * - * Controls whether or not the internal reference clock remains enabled when the - * MCG enters Stop mode. - * - * Values: - * - 0 - Internal reference clock is disabled in Stop mode. - * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or - * if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. - */ -/*@{*/ -#define BP_MCG_C1_IREFSTEN (0U) /*!< Bit position for MCG_C1_IREFSTEN. */ -#define BM_MCG_C1_IREFSTEN (0x01U) /*!< Bit mask for MCG_C1_IREFSTEN. */ -#define BS_MCG_C1_IREFSTEN (1U) /*!< Bit field size in bits for MCG_C1_IREFSTEN. */ - -/*! @brief Read current value of the MCG_C1_IREFSTEN field. */ -#define BR_MCG_C1_IREFSTEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN)) - -/*! @brief Format value for bitfield MCG_C1_IREFSTEN. */ -#define BF_MCG_C1_IREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFSTEN) & BM_MCG_C1_IREFSTEN) - -/*! @brief Set the IREFSTEN field to a new value. */ -#define BW_MCG_C1_IREFSTEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C1, field IRCLKEN[1] (RW) - * - * Enables the internal reference clock for use as MCGIRCLK. - * - * Values: - * - 0 - MCGIRCLK inactive. - * - 1 - MCGIRCLK active. - */ -/*@{*/ -#define BP_MCG_C1_IRCLKEN (1U) /*!< Bit position for MCG_C1_IRCLKEN. */ -#define BM_MCG_C1_IRCLKEN (0x02U) /*!< Bit mask for MCG_C1_IRCLKEN. */ -#define BS_MCG_C1_IRCLKEN (1U) /*!< Bit field size in bits for MCG_C1_IRCLKEN. */ - -/*! @brief Read current value of the MCG_C1_IRCLKEN field. */ -#define BR_MCG_C1_IRCLKEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN)) - -/*! @brief Format value for bitfield MCG_C1_IRCLKEN. */ -#define BF_MCG_C1_IRCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IRCLKEN) & BM_MCG_C1_IRCLKEN) - -/*! @brief Set the IRCLKEN field to a new value. */ -#define BW_MCG_C1_IRCLKEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C1, field IREFS[2] (RW) - * - * Selects the reference clock source for the FLL. - * - * Values: - * - 0 - External reference clock is selected. - * - 1 - The slow internal reference clock is selected. - */ -/*@{*/ -#define BP_MCG_C1_IREFS (2U) /*!< Bit position for MCG_C1_IREFS. */ -#define BM_MCG_C1_IREFS (0x04U) /*!< Bit mask for MCG_C1_IREFS. */ -#define BS_MCG_C1_IREFS (1U) /*!< Bit field size in bits for MCG_C1_IREFS. */ - -/*! @brief Read current value of the MCG_C1_IREFS field. */ -#define BR_MCG_C1_IREFS(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS)) - -/*! @brief Format value for bitfield MCG_C1_IREFS. */ -#define BF_MCG_C1_IREFS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFS) & BM_MCG_C1_IREFS) - -/*! @brief Set the IREFS field to a new value. */ -#define BW_MCG_C1_IREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C1, field FRDIV[5:3] (RW) - * - * Selects the amount to divide down the external reference clock for the FLL. - * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is - * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is - * not required to meet this range, but it is recommended in the cases when trying - * to enter a FLL mode from FBE). - * - * Values: - * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE - * values, Divide Factor is 32. - * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE - * values, Divide Factor is 64. - * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE - * values, Divide Factor is 128. - * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE - * values, Divide Factor is 256. - * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE - * values, Divide Factor is 512. - * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE - * values, Divide Factor is 1024. - * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE - * values, Divide Factor is 1280 . - * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE - * values, Divide Factor is 1536 . - */ -/*@{*/ -#define BP_MCG_C1_FRDIV (3U) /*!< Bit position for MCG_C1_FRDIV. */ -#define BM_MCG_C1_FRDIV (0x38U) /*!< Bit mask for MCG_C1_FRDIV. */ -#define BS_MCG_C1_FRDIV (3U) /*!< Bit field size in bits for MCG_C1_FRDIV. */ - -/*! @brief Read current value of the MCG_C1_FRDIV field. */ -#define BR_MCG_C1_FRDIV(x) (HW_MCG_C1(x).B.FRDIV) - -/*! @brief Format value for bitfield MCG_C1_FRDIV. */ -#define BF_MCG_C1_FRDIV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_FRDIV) & BM_MCG_C1_FRDIV) - -/*! @brief Set the FRDIV field to a new value. */ -#define BW_MCG_C1_FRDIV(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v))) -/*@}*/ - -/*! - * @name Register MCG_C1, field CLKS[7:6] (RW) - * - * Selects the clock source for MCGOUTCLK . - * - * Values: - * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control - * bit). - * - 01 - Encoding 1 - Internal reference clock is selected. - * - 10 - Encoding 2 - External reference clock is selected. - * - 11 - Encoding 3 - Reserved. - */ -/*@{*/ -#define BP_MCG_C1_CLKS (6U) /*!< Bit position for MCG_C1_CLKS. */ -#define BM_MCG_C1_CLKS (0xC0U) /*!< Bit mask for MCG_C1_CLKS. */ -#define BS_MCG_C1_CLKS (2U) /*!< Bit field size in bits for MCG_C1_CLKS. */ - -/*! @brief Read current value of the MCG_C1_CLKS field. */ -#define BR_MCG_C1_CLKS(x) (HW_MCG_C1(x).B.CLKS) - -/*! @brief Format value for bitfield MCG_C1_CLKS. */ -#define BF_MCG_C1_CLKS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_CLKS) & BM_MCG_C1_CLKS) - -/*! @brief Set the CLKS field to a new value. */ -#define BW_MCG_C1_CLKS(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C2 - MCG Control 2 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C2 - MCG Control 2 Register (RW) - * - * Reset value: 0x80U - */ -typedef union _hw_mcg_c2 -{ - uint8_t U; - struct _hw_mcg_c2_bitfields - { - uint8_t IRCS : 1; /*!< [0] Internal Reference Clock Select */ - uint8_t LP : 1; /*!< [1] Low Power Select */ - uint8_t EREFS : 1; /*!< [2] External Reference Select */ - uint8_t HGO : 1; /*!< [3] High Gain Oscillator Select */ - uint8_t RANGE : 2; /*!< [5:4] Frequency Range Select */ - uint8_t FCFTRIM : 1; /*!< [6] Fast Internal Reference Clock Fine Trim - * */ - uint8_t LOCRE0 : 1; /*!< [7] Loss of Clock Reset Enable */ - } B; -} hw_mcg_c2_t; - -/*! - * @name Constants and macros for entire MCG_C2 register - */ -/*@{*/ -#define HW_MCG_C2_ADDR(x) ((x) + 0x1U) - -#define HW_MCG_C2(x) (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR(x)) -#define HW_MCG_C2_RD(x) (HW_MCG_C2(x).U) -#define HW_MCG_C2_WR(x, v) (HW_MCG_C2(x).U = (v)) -#define HW_MCG_C2_SET(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) | (v))) -#define HW_MCG_C2_CLR(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) & ~(v))) -#define HW_MCG_C2_TOG(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C2 bitfields - */ - -/*! - * @name Register MCG_C2, field IRCS[0] (RW) - * - * Selects between the fast or slow internal reference clock source. - * - * Values: - * - 0 - Slow internal reference clock selected. - * - 1 - Fast internal reference clock selected. - */ -/*@{*/ -#define BP_MCG_C2_IRCS (0U) /*!< Bit position for MCG_C2_IRCS. */ -#define BM_MCG_C2_IRCS (0x01U) /*!< Bit mask for MCG_C2_IRCS. */ -#define BS_MCG_C2_IRCS (1U) /*!< Bit field size in bits for MCG_C2_IRCS. */ - -/*! @brief Read current value of the MCG_C2_IRCS field. */ -#define BR_MCG_C2_IRCS(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS)) - -/*! @brief Format value for bitfield MCG_C2_IRCS. */ -#define BF_MCG_C2_IRCS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_IRCS) & BM_MCG_C2_IRCS) - -/*! @brief Set the IRCS field to a new value. */ -#define BW_MCG_C2_IRCS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field LP[1] (RW) - * - * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or - * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in - * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any - * other MCG mode, LP bit has no affect. - * - * Values: - * - 0 - FLL or PLL is not disabled in bypass modes. - * - 1 - FLL or PLL is disabled in bypass modes (lower power) - */ -/*@{*/ -#define BP_MCG_C2_LP (1U) /*!< Bit position for MCG_C2_LP. */ -#define BM_MCG_C2_LP (0x02U) /*!< Bit mask for MCG_C2_LP. */ -#define BS_MCG_C2_LP (1U) /*!< Bit field size in bits for MCG_C2_LP. */ - -/*! @brief Read current value of the MCG_C2_LP field. */ -#define BR_MCG_C2_LP(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP)) - -/*! @brief Format value for bitfield MCG_C2_LP. */ -#define BF_MCG_C2_LP(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LP) & BM_MCG_C2_LP) - -/*! @brief Set the LP field to a new value. */ -#define BW_MCG_C2_LP(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field EREFS[2] (RW) - * - * Selects the source for the external reference clock. See the Oscillator (OSC) - * chapter for more details. - * - * Values: - * - 0 - External reference clock requested. - * - 1 - Oscillator requested. - */ -/*@{*/ -#define BP_MCG_C2_EREFS (2U) /*!< Bit position for MCG_C2_EREFS. */ -#define BM_MCG_C2_EREFS (0x04U) /*!< Bit mask for MCG_C2_EREFS. */ -#define BS_MCG_C2_EREFS (1U) /*!< Bit field size in bits for MCG_C2_EREFS. */ - -/*! @brief Read current value of the MCG_C2_EREFS field. */ -#define BR_MCG_C2_EREFS(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS)) - -/*! @brief Format value for bitfield MCG_C2_EREFS. */ -#define BF_MCG_C2_EREFS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_EREFS) & BM_MCG_C2_EREFS) - -/*! @brief Set the EREFS field to a new value. */ -#define BW_MCG_C2_EREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field HGO[3] (RW) - * - * Controls the crystal oscillator mode of operation. See the Oscillator (OSC) - * chapter for more details. - * - * Values: - * - 0 - Configure crystal oscillator for low-power operation. - * - 1 - Configure crystal oscillator for high-gain operation. - */ -/*@{*/ -#define BP_MCG_C2_HGO (3U) /*!< Bit position for MCG_C2_HGO. */ -#define BM_MCG_C2_HGO (0x08U) /*!< Bit mask for MCG_C2_HGO. */ -#define BS_MCG_C2_HGO (1U) /*!< Bit field size in bits for MCG_C2_HGO. */ - -/*! @brief Read current value of the MCG_C2_HGO field. */ -#define BR_MCG_C2_HGO(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO)) - -/*! @brief Format value for bitfield MCG_C2_HGO. */ -#define BF_MCG_C2_HGO(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_HGO) & BM_MCG_C2_HGO) - -/*! @brief Set the HGO field to a new value. */ -#define BW_MCG_C2_HGO(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field RANGE[5:4] (RW) - * - * Selects the frequency range for the crystal oscillator or external clock - * source. See the Oscillator (OSC) chapter for more details and the device data - * sheet for the frequency ranges used. - * - * Values: - * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator . - * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator . - */ -/*@{*/ -#define BP_MCG_C2_RANGE (4U) /*!< Bit position for MCG_C2_RANGE. */ -#define BM_MCG_C2_RANGE (0x30U) /*!< Bit mask for MCG_C2_RANGE. */ -#define BS_MCG_C2_RANGE (2U) /*!< Bit field size in bits for MCG_C2_RANGE. */ - -/*! @brief Read current value of the MCG_C2_RANGE field. */ -#define BR_MCG_C2_RANGE(x) (HW_MCG_C2(x).B.RANGE) - -/*! @brief Format value for bitfield MCG_C2_RANGE. */ -#define BF_MCG_C2_RANGE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_RANGE) & BM_MCG_C2_RANGE) - -/*! @brief Set the RANGE field to a new value. */ -#define BW_MCG_C2_RANGE(x, v) (HW_MCG_C2_WR(x, (HW_MCG_C2_RD(x) & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v))) -/*@}*/ - -/*! - * @name Register MCG_C2, field FCFTRIM[6] (RW) - * - * FCFTRIM controls the smallest adjustment of the fast internal reference clock - * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM - * decreases the period by the smallest amount possible. If an FCFTRIM value stored in - * nonvolatile memory is to be used, it is your responsibility to copy that value - * from the nonvolatile memory location to this bit. - */ -/*@{*/ -#define BP_MCG_C2_FCFTRIM (6U) /*!< Bit position for MCG_C2_FCFTRIM. */ -#define BM_MCG_C2_FCFTRIM (0x40U) /*!< Bit mask for MCG_C2_FCFTRIM. */ -#define BS_MCG_C2_FCFTRIM (1U) /*!< Bit field size in bits for MCG_C2_FCFTRIM. */ - -/*! @brief Read current value of the MCG_C2_FCFTRIM field. */ -#define BR_MCG_C2_FCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM)) - -/*! @brief Format value for bitfield MCG_C2_FCFTRIM. */ -#define BF_MCG_C2_FCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_FCFTRIM) & BM_MCG_C2_FCFTRIM) - -/*! @brief Set the FCFTRIM field to a new value. */ -#define BW_MCG_C2_FCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C2, field LOCRE0[7] (RW) - * - * Determines whether an interrupt or a reset request is made following a loss - * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is - * set. - * - * Values: - * - 0 - Interrupt request is generated on a loss of OSC0 external reference - * clock. - * - 1 - Generate a reset request on a loss of OSC0 external reference clock. - */ -/*@{*/ -#define BP_MCG_C2_LOCRE0 (7U) /*!< Bit position for MCG_C2_LOCRE0. */ -#define BM_MCG_C2_LOCRE0 (0x80U) /*!< Bit mask for MCG_C2_LOCRE0. */ -#define BS_MCG_C2_LOCRE0 (1U) /*!< Bit field size in bits for MCG_C2_LOCRE0. */ - -/*! @brief Read current value of the MCG_C2_LOCRE0 field. */ -#define BR_MCG_C2_LOCRE0(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0)) - -/*! @brief Format value for bitfield MCG_C2_LOCRE0. */ -#define BF_MCG_C2_LOCRE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LOCRE0) & BM_MCG_C2_LOCRE0) - -/*! @brief Set the LOCRE0 field to a new value. */ -#define BW_MCG_C2_LOCRE0(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C3 - MCG Control 3 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C3 - MCG Control 3 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c3 -{ - uint8_t U; - struct _hw_mcg_c3_bitfields - { - uint8_t SCTRIM : 8; /*!< [7:0] Slow Internal Reference Clock Trim - * Setting */ - } B; -} hw_mcg_c3_t; - -/*! - * @name Constants and macros for entire MCG_C3 register - */ -/*@{*/ -#define HW_MCG_C3_ADDR(x) ((x) + 0x2U) - -#define HW_MCG_C3(x) (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR(x)) -#define HW_MCG_C3_RD(x) (HW_MCG_C3(x).U) -#define HW_MCG_C3_WR(x, v) (HW_MCG_C3(x).U = (v)) -#define HW_MCG_C3_SET(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) | (v))) -#define HW_MCG_C3_CLR(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) & ~(v))) -#define HW_MCG_C3_TOG(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C3 bitfields - */ - -/*! - * @name Register MCG_C3, field SCTRIM[7:0] (RW) - * - * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed - * location. controls the slow internal reference clock frequency by controlling - * the slow internal reference clock period. The SCTRIM bits are binary weighted, - * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value - * increases the period, and decreasing the value decreases the period. An additional - * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, - * this value is loaded with a factory trim value. If an SCTRIM value stored in - * nonvolatile memory is to be used, it is your responsibility to copy that value - * from the nonvolatile memory location to this register. - */ -/*@{*/ -#define BP_MCG_C3_SCTRIM (0U) /*!< Bit position for MCG_C3_SCTRIM. */ -#define BM_MCG_C3_SCTRIM (0xFFU) /*!< Bit mask for MCG_C3_SCTRIM. */ -#define BS_MCG_C3_SCTRIM (8U) /*!< Bit field size in bits for MCG_C3_SCTRIM. */ - -/*! @brief Read current value of the MCG_C3_SCTRIM field. */ -#define BR_MCG_C3_SCTRIM(x) (HW_MCG_C3(x).U) - -/*! @brief Format value for bitfield MCG_C3_SCTRIM. */ -#define BF_MCG_C3_SCTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C3_SCTRIM) & BM_MCG_C3_SCTRIM) - -/*! @brief Set the SCTRIM field to a new value. */ -#define BW_MCG_C3_SCTRIM(x, v) (HW_MCG_C3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C4 - MCG Control 4 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C4 - MCG Control 4 Register (RW) - * - * Reset value: 0x00U - * - * Reset values for DRST and DMX32 bits are 0. - */ -typedef union _hw_mcg_c4 -{ - uint8_t U; - struct _hw_mcg_c4_bitfields - { - uint8_t SCFTRIM : 1; /*!< [0] Slow Internal Reference Clock Fine Trim - * */ - uint8_t FCTRIM : 4; /*!< [4:1] Fast Internal Reference Clock Trim - * Setting */ - uint8_t DRST_DRS : 2; /*!< [6:5] DCO Range Select */ - uint8_t DMX32 : 1; /*!< [7] DCO Maximum Frequency with 32.768 kHz - * Reference */ - } B; -} hw_mcg_c4_t; - -/*! - * @name Constants and macros for entire MCG_C4 register - */ -/*@{*/ -#define HW_MCG_C4_ADDR(x) ((x) + 0x3U) - -#define HW_MCG_C4(x) (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR(x)) -#define HW_MCG_C4_RD(x) (HW_MCG_C4(x).U) -#define HW_MCG_C4_WR(x, v) (HW_MCG_C4(x).U = (v)) -#define HW_MCG_C4_SET(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) | (v))) -#define HW_MCG_C4_CLR(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) & ~(v))) -#define HW_MCG_C4_TOG(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C4 bitfields - */ - -/*! - * @name Register MCG_C4, field SCFTRIM[0] (RW) - * - * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed - * location . controls the smallest adjustment of the slow internal reference - * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM - * decreases the period by the smallest amount possible. If an SCFTRIM value stored in - * nonvolatile memory is to be used, it is your responsibility to copy that value - * from the nonvolatile memory location to this bit. - */ -/*@{*/ -#define BP_MCG_C4_SCFTRIM (0U) /*!< Bit position for MCG_C4_SCFTRIM. */ -#define BM_MCG_C4_SCFTRIM (0x01U) /*!< Bit mask for MCG_C4_SCFTRIM. */ -#define BS_MCG_C4_SCFTRIM (1U) /*!< Bit field size in bits for MCG_C4_SCFTRIM. */ - -/*! @brief Read current value of the MCG_C4_SCFTRIM field. */ -#define BR_MCG_C4_SCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM)) - -/*! @brief Format value for bitfield MCG_C4_SCFTRIM. */ -#define BF_MCG_C4_SCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_SCFTRIM) & BM_MCG_C4_SCFTRIM) - -/*! @brief Set the SCFTRIM field to a new value. */ -#define BW_MCG_C4_SCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C4, field FCTRIM[4:1] (RW) - * - * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed - * location. controls the fast internal reference clock frequency by controlling - * the fast internal reference clock period. The FCTRIM bits are binary weighted, - * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value - * increases the period, and decreasing the value decreases the period. If an - * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your - * responsibility to copy that value from the nonvolatile memory location to this register. - */ -/*@{*/ -#define BP_MCG_C4_FCTRIM (1U) /*!< Bit position for MCG_C4_FCTRIM. */ -#define BM_MCG_C4_FCTRIM (0x1EU) /*!< Bit mask for MCG_C4_FCTRIM. */ -#define BS_MCG_C4_FCTRIM (4U) /*!< Bit field size in bits for MCG_C4_FCTRIM. */ - -/*! @brief Read current value of the MCG_C4_FCTRIM field. */ -#define BR_MCG_C4_FCTRIM(x) (HW_MCG_C4(x).B.FCTRIM) - -/*! @brief Format value for bitfield MCG_C4_FCTRIM. */ -#define BF_MCG_C4_FCTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_FCTRIM) & BM_MCG_C4_FCTRIM) - -/*! @brief Set the FCTRIM field to a new value. */ -#define BW_MCG_C4_FCTRIM(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v))) -/*@}*/ - -/*! - * @name Register MCG_C4, field DRST_DRS[6:5] (RW) - * - * The DRS bits select the frequency range for the FLL output, DCOOUT. When the - * LP bit is set, writes to the DRS bits are ignored. The DRST read field - * indicates the current frequency range for DCOOUT. The DRST field does not update - * immediately after a write to the DRS field due to internal synchronization between - * clock domains. See the DCO Frequency Range table for more details. - * - * Values: - * - 00 - Encoding 0 - Low range (reset default). - * - 01 - Encoding 1 - Mid range. - * - 10 - Encoding 2 - Mid-high range. - * - 11 - Encoding 3 - High range. - */ -/*@{*/ -#define BP_MCG_C4_DRST_DRS (5U) /*!< Bit position for MCG_C4_DRST_DRS. */ -#define BM_MCG_C4_DRST_DRS (0x60U) /*!< Bit mask for MCG_C4_DRST_DRS. */ -#define BS_MCG_C4_DRST_DRS (2U) /*!< Bit field size in bits for MCG_C4_DRST_DRS. */ - -/*! @brief Read current value of the MCG_C4_DRST_DRS field. */ -#define BR_MCG_C4_DRST_DRS(x) (HW_MCG_C4(x).B.DRST_DRS) - -/*! @brief Format value for bitfield MCG_C4_DRST_DRS. */ -#define BF_MCG_C4_DRST_DRS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DRST_DRS) & BM_MCG_C4_DRST_DRS) - -/*! @brief Set the DRST_DRS field to a new value. */ -#define BW_MCG_C4_DRST_DRS(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v))) -/*@}*/ - -/*! - * @name Register MCG_C4, field DMX32[7] (RW) - * - * The DMX32 bit controls whether the DCO frequency range is narrowed to its - * maximum frequency with a 32.768 kHz reference. The following table identifies - * settings for the DCO frequency range. The system clocks derived from this source - * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL - * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz - * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0 - * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560 - * 80-100 MHz 1 32.768 kHz 2929 96 MHz - * - * Values: - * - 0 - DCO has a default range of 25%. - * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference. - */ -/*@{*/ -#define BP_MCG_C4_DMX32 (7U) /*!< Bit position for MCG_C4_DMX32. */ -#define BM_MCG_C4_DMX32 (0x80U) /*!< Bit mask for MCG_C4_DMX32. */ -#define BS_MCG_C4_DMX32 (1U) /*!< Bit field size in bits for MCG_C4_DMX32. */ - -/*! @brief Read current value of the MCG_C4_DMX32 field. */ -#define BR_MCG_C4_DMX32(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32)) - -/*! @brief Format value for bitfield MCG_C4_DMX32. */ -#define BF_MCG_C4_DMX32(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DMX32) & BM_MCG_C4_DMX32) - -/*! @brief Set the DMX32 field to a new value. */ -#define BW_MCG_C4_DMX32(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C5 - MCG Control 5 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C5 - MCG Control 5 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c5 -{ - uint8_t U; - struct _hw_mcg_c5_bitfields - { - uint8_t PRDIV0 : 5; /*!< [4:0] PLL External Reference Divider */ - uint8_t PLLSTEN0 : 1; /*!< [5] PLL Stop Enable */ - uint8_t PLLCLKEN0 : 1; /*!< [6] PLL Clock Enable */ - uint8_t RESERVED0 : 1; /*!< [7] */ - } B; -} hw_mcg_c5_t; - -/*! - * @name Constants and macros for entire MCG_C5 register - */ -/*@{*/ -#define HW_MCG_C5_ADDR(x) ((x) + 0x4U) - -#define HW_MCG_C5(x) (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x)) -#define HW_MCG_C5_RD(x) (HW_MCG_C5(x).U) -#define HW_MCG_C5_WR(x, v) (HW_MCG_C5(x).U = (v)) -#define HW_MCG_C5_SET(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) | (v))) -#define HW_MCG_C5_CLR(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v))) -#define HW_MCG_C5_TOG(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C5 bitfields - */ - -/*! - * @name Register MCG_C5, field PRDIV0[4:0] (RW) - * - * Selects the amount to divide down the external reference clock for the PLL. - * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL - * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not - * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0 - * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor - * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved - * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved - * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101 - * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111 - * Reserved - */ -/*@{*/ -#define BP_MCG_C5_PRDIV0 (0U) /*!< Bit position for MCG_C5_PRDIV0. */ -#define BM_MCG_C5_PRDIV0 (0x1FU) /*!< Bit mask for MCG_C5_PRDIV0. */ -#define BS_MCG_C5_PRDIV0 (5U) /*!< Bit field size in bits for MCG_C5_PRDIV0. */ - -/*! @brief Read current value of the MCG_C5_PRDIV0 field. */ -#define BR_MCG_C5_PRDIV0(x) (HW_MCG_C5(x).B.PRDIV0) - -/*! @brief Format value for bitfield MCG_C5_PRDIV0. */ -#define BF_MCG_C5_PRDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0) - -/*! @brief Set the PRDIV0 field to a new value. */ -#define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v))) -/*@}*/ - -/*! - * @name Register MCG_C5, field PLLSTEN0[5] (RW) - * - * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL - * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit - * has no affect and does not enable the PLL Clock to run if it is written to 1. - * - * Values: - * - 0 - MCGPLLCLK is disabled in any of the Stop modes. - * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode. - */ -/*@{*/ -#define BP_MCG_C5_PLLSTEN0 (5U) /*!< Bit position for MCG_C5_PLLSTEN0. */ -#define BM_MCG_C5_PLLSTEN0 (0x20U) /*!< Bit mask for MCG_C5_PLLSTEN0. */ -#define BS_MCG_C5_PLLSTEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */ - -/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */ -#define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0)) - -/*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */ -#define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0) - -/*! @brief Set the PLLSTEN0 field to a new value. */ -#define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C5, field PLLCLKEN0[6] (RW) - * - * Enables the PLL independent of PLLS and enables the PLL clock for use as - * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a - * PLL reference clock in the range of 2 - 4 MHz range prior to setting the - * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not - * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, - * and the external oscillator is being used as the reference clock, the OSCINIT 0 - * bit should be checked to make sure it is set. - * - * Values: - * - 0 - MCGPLLCLK is inactive. - * - 1 - MCGPLLCLK is active. - */ -/*@{*/ -#define BP_MCG_C5_PLLCLKEN0 (6U) /*!< Bit position for MCG_C5_PLLCLKEN0. */ -#define BM_MCG_C5_PLLCLKEN0 (0x40U) /*!< Bit mask for MCG_C5_PLLCLKEN0. */ -#define BS_MCG_C5_PLLCLKEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */ - -/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */ -#define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0)) - -/*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */ -#define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0) - -/*! @brief Set the PLLCLKEN0 field to a new value. */ -#define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C6 - MCG Control 6 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C6 - MCG Control 6 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c6 -{ - uint8_t U; - struct _hw_mcg_c6_bitfields - { - uint8_t VDIV0 : 5; /*!< [4:0] VCO 0 Divider */ - uint8_t CME0 : 1; /*!< [5] Clock Monitor Enable */ - uint8_t PLLS : 1; /*!< [6] PLL Select */ - uint8_t LOLIE0 : 1; /*!< [7] Loss of Lock Interrrupt Enable */ - } B; -} hw_mcg_c6_t; - -/*! - * @name Constants and macros for entire MCG_C6 register - */ -/*@{*/ -#define HW_MCG_C6_ADDR(x) ((x) + 0x5U) - -#define HW_MCG_C6(x) (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR(x)) -#define HW_MCG_C6_RD(x) (HW_MCG_C6(x).U) -#define HW_MCG_C6_WR(x, v) (HW_MCG_C6(x).U = (v)) -#define HW_MCG_C6_SET(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) | (v))) -#define HW_MCG_C6_CLR(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) & ~(v))) -#define HW_MCG_C6_TOG(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C6 bitfields - */ - -/*! - * @name Register MCG_C6, field VDIV0[4:0] (RW) - * - * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits - * establish the multiplication factor (M) applied to the reference clock frequency. - * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0 - * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0 - * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply - * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49 - * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 - * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 - * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 - */ -/*@{*/ -#define BP_MCG_C6_VDIV0 (0U) /*!< Bit position for MCG_C6_VDIV0. */ -#define BM_MCG_C6_VDIV0 (0x1FU) /*!< Bit mask for MCG_C6_VDIV0. */ -#define BS_MCG_C6_VDIV0 (5U) /*!< Bit field size in bits for MCG_C6_VDIV0. */ - -/*! @brief Read current value of the MCG_C6_VDIV0 field. */ -#define BR_MCG_C6_VDIV0(x) (HW_MCG_C6(x).B.VDIV0) - -/*! @brief Format value for bitfield MCG_C6_VDIV0. */ -#define BF_MCG_C6_VDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0) - -/*! @brief Set the VDIV0 field to a new value. */ -#define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v))) -/*@}*/ - -/*! - * @name Register MCG_C6, field CME0[5] (RW) - * - * Enables the loss of clock monitoring circuit for the OSC0 external reference - * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is - * generated following a loss of OSC0 indication. The CME0 bit must only be set - * to a logic 1 when the MCG is in an operational mode that uses the external - * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, - * the value of the RANGE0 bits in the C2 register should not be changed. CME0 - * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a - * reset request may occur while in Stop mode. CME0 should also be set to a - * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. - * - * Values: - * - 0 - External clock monitor is disabled for OSC0. - * - 1 - External clock monitor is enabled for OSC0. - */ -/*@{*/ -#define BP_MCG_C6_CME0 (5U) /*!< Bit position for MCG_C6_CME0. */ -#define BM_MCG_C6_CME0 (0x20U) /*!< Bit mask for MCG_C6_CME0. */ -#define BS_MCG_C6_CME0 (1U) /*!< Bit field size in bits for MCG_C6_CME0. */ - -/*! @brief Read current value of the MCG_C6_CME0 field. */ -#define BR_MCG_C6_CME0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0)) - -/*! @brief Format value for bitfield MCG_C6_CME0. */ -#define BF_MCG_C6_CME0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0) - -/*! @brief Set the CME0 field to a new value. */ -#define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C6, field PLLS[6] (RW) - * - * Controls whether the PLL or FLL output is selected as the MCG source when - * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is - * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. - * - * Values: - * - 0 - FLL is selected. - * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider - * to generate a PLL reference clock in the range of 2-4 MHz prior to setting - * the PLLS bit). - */ -/*@{*/ -#define BP_MCG_C6_PLLS (6U) /*!< Bit position for MCG_C6_PLLS. */ -#define BM_MCG_C6_PLLS (0x40U) /*!< Bit mask for MCG_C6_PLLS. */ -#define BS_MCG_C6_PLLS (1U) /*!< Bit field size in bits for MCG_C6_PLLS. */ - -/*! @brief Read current value of the MCG_C6_PLLS field. */ -#define BR_MCG_C6_PLLS(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS)) - -/*! @brief Format value for bitfield MCG_C6_PLLS. */ -#define BF_MCG_C6_PLLS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS) - -/*! @brief Set the PLLS field to a new value. */ -#define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C6, field LOLIE0[7] (RW) - * - * Determines if an interrupt request is made following a loss of lock - * indication. This bit only has an effect when LOLS 0 is set. - * - * Values: - * - 0 - No interrupt request is generated on loss of lock. - * - 1 - Generate an interrupt request on loss of lock. - */ -/*@{*/ -#define BP_MCG_C6_LOLIE0 (7U) /*!< Bit position for MCG_C6_LOLIE0. */ -#define BM_MCG_C6_LOLIE0 (0x80U) /*!< Bit mask for MCG_C6_LOLIE0. */ -#define BS_MCG_C6_LOLIE0 (1U) /*!< Bit field size in bits for MCG_C6_LOLIE0. */ - -/*! @brief Read current value of the MCG_C6_LOLIE0 field. */ -#define BR_MCG_C6_LOLIE0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0)) - -/*! @brief Format value for bitfield MCG_C6_LOLIE0. */ -#define BF_MCG_C6_LOLIE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0) - -/*! @brief Set the LOLIE0 field to a new value. */ -#define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_S - MCG Status Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_S - MCG Status Register (RW) - * - * Reset value: 0x10U - */ -typedef union _hw_mcg_s -{ - uint8_t U; - struct _hw_mcg_s_bitfields - { - uint8_t IRCST : 1; /*!< [0] Internal Reference Clock Status */ - uint8_t OSCINIT0 : 1; /*!< [1] OSC Initialization */ - uint8_t CLKST : 2; /*!< [3:2] Clock Mode Status */ - uint8_t IREFST : 1; /*!< [4] Internal Reference Status */ - uint8_t PLLST : 1; /*!< [5] PLL Select Status */ - uint8_t LOCK0 : 1; /*!< [6] Lock Status */ - uint8_t LOLS0 : 1; /*!< [7] Loss of Lock Status */ - } B; -} hw_mcg_s_t; - -/*! - * @name Constants and macros for entire MCG_S register - */ -/*@{*/ -#define HW_MCG_S_ADDR(x) ((x) + 0x6U) - -#define HW_MCG_S(x) (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x)) -#define HW_MCG_S_RD(x) (HW_MCG_S(x).U) -#define HW_MCG_S_WR(x, v) (HW_MCG_S(x).U = (v)) -#define HW_MCG_S_SET(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) | (v))) -#define HW_MCG_S_CLR(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v))) -#define HW_MCG_S_TOG(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_S bitfields - */ - -/*! - * @name Register MCG_S, field IRCST[0] (RO) - * - * The IRCST bit indicates the current source for the internal reference clock - * select clock (IRCSCLK). The IRCST bit does not update immediately after a write - * to the IRCS bit due to internal synchronization between clock domains. The - * IRCST bit will only be updated if the internal reference clock is enabled, - * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] - * bit . - * - * Values: - * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC). - * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC). - */ -/*@{*/ -#define BP_MCG_S_IRCST (0U) /*!< Bit position for MCG_S_IRCST. */ -#define BM_MCG_S_IRCST (0x01U) /*!< Bit mask for MCG_S_IRCST. */ -#define BS_MCG_S_IRCST (1U) /*!< Bit field size in bits for MCG_S_IRCST. */ - -/*! @brief Read current value of the MCG_S_IRCST field. */ -#define BR_MCG_S_IRCST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IRCST)) -/*@}*/ - -/*! - * @name Register MCG_S, field OSCINIT0[1] (RO) - * - * This bit, which resets to 0, is set to 1 after the initialization cycles of - * the crystal oscillator clock have completed. After being set, the bit is - * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed - * description for more information. - */ -/*@{*/ -#define BP_MCG_S_OSCINIT0 (1U) /*!< Bit position for MCG_S_OSCINIT0. */ -#define BM_MCG_S_OSCINIT0 (0x02U) /*!< Bit mask for MCG_S_OSCINIT0. */ -#define BS_MCG_S_OSCINIT0 (1U) /*!< Bit field size in bits for MCG_S_OSCINIT0. */ - -/*! @brief Read current value of the MCG_S_OSCINIT0 field. */ -#define BR_MCG_S_OSCINIT0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_OSCINIT0)) -/*@}*/ - -/*! - * @name Register MCG_S, field CLKST[3:2] (RO) - * - * These bits indicate the current clock mode. The CLKST bits do not update - * immediately after a write to the CLKS bits due to internal synchronization between - * clock domains. - * - * Values: - * - 00 - Encoding 0 - Output of the FLL is selected (reset default). - * - 01 - Encoding 1 - Internal reference clock is selected. - * - 10 - Encoding 2 - External reference clock is selected. - * - 11 - Encoding 3 - Output of the PLL is selected. - */ -/*@{*/ -#define BP_MCG_S_CLKST (2U) /*!< Bit position for MCG_S_CLKST. */ -#define BM_MCG_S_CLKST (0x0CU) /*!< Bit mask for MCG_S_CLKST. */ -#define BS_MCG_S_CLKST (2U) /*!< Bit field size in bits for MCG_S_CLKST. */ - -/*! @brief Read current value of the MCG_S_CLKST field. */ -#define BR_MCG_S_CLKST(x) (HW_MCG_S(x).B.CLKST) -/*@}*/ - -/*! - * @name Register MCG_S, field IREFST[4] (RO) - * - * This bit indicates the current source for the FLL reference clock. The IREFST - * bit does not update immediately after a write to the IREFS bit due to - * internal synchronization between clock domains. - * - * Values: - * - 0 - Source of FLL reference clock is the external reference clock. - * - 1 - Source of FLL reference clock is the internal reference clock. - */ -/*@{*/ -#define BP_MCG_S_IREFST (4U) /*!< Bit position for MCG_S_IREFST. */ -#define BM_MCG_S_IREFST (0x10U) /*!< Bit mask for MCG_S_IREFST. */ -#define BS_MCG_S_IREFST (1U) /*!< Bit field size in bits for MCG_S_IREFST. */ - -/*! @brief Read current value of the MCG_S_IREFST field. */ -#define BR_MCG_S_IREFST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST)) -/*@}*/ - -/*! - * @name Register MCG_S, field PLLST[5] (RO) - * - * This bit indicates the clock source selected by PLLS . The PLLST bit does not - * update immediately after a write to the PLLS bit due to internal - * synchronization between clock domains. - * - * Values: - * - 0 - Source of PLLS clock is FLL clock. - * - 1 - Source of PLLS clock is PLL output clock. - */ -/*@{*/ -#define BP_MCG_S_PLLST (5U) /*!< Bit position for MCG_S_PLLST. */ -#define BM_MCG_S_PLLST (0x20U) /*!< Bit mask for MCG_S_PLLST. */ -#define BS_MCG_S_PLLST (1U) /*!< Bit field size in bits for MCG_S_PLLST. */ - -/*! @brief Read current value of the MCG_S_PLLST field. */ -#define BR_MCG_S_PLLST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST)) -/*@}*/ - -/*! - * @name Register MCG_S, field LOCK0[6] (RO) - * - * This bit indicates whether the PLL has acquired lock. Lock detection is only - * enabled when the PLL is enabled (either through clock mode selection or - * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the - * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. - * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in - * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock - * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL - * reference clock will also cause the LOCK0 bit to clear until the PLL has - * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes - * the lock status bit to clear and stay cleared until the Stop mode is exited - * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit - * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted - * again. - * - * Values: - * - 0 - PLL is currently unlocked. - * - 1 - PLL is currently locked. - */ -/*@{*/ -#define BP_MCG_S_LOCK0 (6U) /*!< Bit position for MCG_S_LOCK0. */ -#define BM_MCG_S_LOCK0 (0x40U) /*!< Bit mask for MCG_S_LOCK0. */ -#define BS_MCG_S_LOCK0 (1U) /*!< Bit field size in bits for MCG_S_LOCK0. */ - -/*! @brief Read current value of the MCG_S_LOCK0 field. */ -#define BR_MCG_S_LOCK0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0)) -/*@}*/ - -/*! - * @name Register MCG_S, field LOLS0[7] (W1C) - * - * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set - * if after acquiring lock, the PLL output frequency has fallen outside the lock - * exit frequency tolerance, D unl . LOLIE determines whether an interrupt - * request is made when LOLS is set. LOLRE determines whether a reset request is made - * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it - * when set. Writing a logic 0 to this bit has no effect. - * - * Values: - * - 0 - PLL has not lost lock since LOLS 0 was last cleared. - * - 1 - PLL has lost lock since LOLS 0 was last cleared. - */ -/*@{*/ -#define BP_MCG_S_LOLS0 (7U) /*!< Bit position for MCG_S_LOLS0. */ -#define BM_MCG_S_LOLS0 (0x80U) /*!< Bit mask for MCG_S_LOLS0. */ -#define BS_MCG_S_LOLS0 (1U) /*!< Bit field size in bits for MCG_S_LOLS0. */ - -/*! @brief Read current value of the MCG_S_LOLS0 field. */ -#define BR_MCG_S_LOLS0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0)) - -/*! @brief Format value for bitfield MCG_S_LOLS0. */ -#define BF_MCG_S_LOLS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0) - -/*! @brief Set the LOLS0 field to a new value. */ -#define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_SC - MCG Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_SC - MCG Status and Control Register (RW) - * - * Reset value: 0x02U - */ -typedef union _hw_mcg_sc -{ - uint8_t U; - struct _hw_mcg_sc_bitfields - { - uint8_t LOCS0 : 1; /*!< [0] OSC0 Loss of Clock Status */ - uint8_t FCRDIV : 3; /*!< [3:1] Fast Clock Internal Reference Divider - * */ - uint8_t FLTPRSRV : 1; /*!< [4] FLL Filter Preserve Enable */ - uint8_t ATMF : 1; /*!< [5] Automatic Trim Machine Fail Flag */ - uint8_t ATMS : 1; /*!< [6] Automatic Trim Machine Select */ - uint8_t ATME : 1; /*!< [7] Automatic Trim Machine Enable */ - } B; -} hw_mcg_sc_t; - -/*! - * @name Constants and macros for entire MCG_SC register - */ -/*@{*/ -#define HW_MCG_SC_ADDR(x) ((x) + 0x8U) - -#define HW_MCG_SC(x) (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR(x)) -#define HW_MCG_SC_RD(x) (HW_MCG_SC(x).U) -#define HW_MCG_SC_WR(x, v) (HW_MCG_SC(x).U = (v)) -#define HW_MCG_SC_SET(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) | (v))) -#define HW_MCG_SC_CLR(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) & ~(v))) -#define HW_MCG_SC_TOG(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_SC bitfields - */ - -/*! - * @name Register MCG_SC, field LOCS0[0] (W1C) - * - * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The - * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a - * logic 1 to it when set. - * - * Values: - * - 0 - Loss of OSC0 has not occurred. - * - 1 - Loss of OSC0 has occurred. - */ -/*@{*/ -#define BP_MCG_SC_LOCS0 (0U) /*!< Bit position for MCG_SC_LOCS0. */ -#define BM_MCG_SC_LOCS0 (0x01U) /*!< Bit mask for MCG_SC_LOCS0. */ -#define BS_MCG_SC_LOCS0 (1U) /*!< Bit field size in bits for MCG_SC_LOCS0. */ - -/*! @brief Read current value of the MCG_SC_LOCS0 field. */ -#define BR_MCG_SC_LOCS0(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0)) - -/*! @brief Format value for bitfield MCG_SC_LOCS0. */ -#define BF_MCG_SC_LOCS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_LOCS0) & BM_MCG_SC_LOCS0) - -/*! @brief Set the LOCS0 field to a new value. */ -#define BW_MCG_SC_LOCS0(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field FCRDIV[3:1] (RW) - * - * Selects the amount to divide down the fast internal reference clock. The - * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the - * divider when the Fast IRC is enabled is not supported). - * - * Values: - * - 000 - Divide Factor is 1 - * - 001 - Divide Factor is 2. - * - 010 - Divide Factor is 4. - * - 011 - Divide Factor is 8. - * - 100 - Divide Factor is 16 - * - 101 - Divide Factor is 32 - * - 110 - Divide Factor is 64 - * - 111 - Divide Factor is 128. - */ -/*@{*/ -#define BP_MCG_SC_FCRDIV (1U) /*!< Bit position for MCG_SC_FCRDIV. */ -#define BM_MCG_SC_FCRDIV (0x0EU) /*!< Bit mask for MCG_SC_FCRDIV. */ -#define BS_MCG_SC_FCRDIV (3U) /*!< Bit field size in bits for MCG_SC_FCRDIV. */ - -/*! @brief Read current value of the MCG_SC_FCRDIV field. */ -#define BR_MCG_SC_FCRDIV(x) (HW_MCG_SC(x).B.FCRDIV) - -/*! @brief Format value for bitfield MCG_SC_FCRDIV. */ -#define BF_MCG_SC_FCRDIV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FCRDIV) & BM_MCG_SC_FCRDIV) - -/*! @brief Set the FCRDIV field to a new value. */ -#define BW_MCG_SC_FCRDIV(x, v) (HW_MCG_SC_WR(x, (HW_MCG_SC_RD(x) & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v))) -/*@}*/ - -/*! - * @name Register MCG_SC, field FLTPRSRV[4] (RW) - * - * This bit will prevent the FLL filter values from resetting allowing the FLL - * output frequency to remain the same during clock mode changes where the FLL/DCO - * output is still valid. (Note: This requires that the FLL reference frequency - * to remain the same as what it was prior to the new clock mode switch. - * Otherwise FLL filter and frequency values will change.) - * - * Values: - * - 0 - FLL filter and FLL frequency will reset on changes to currect clock - * mode. - * - 1 - Fll filter and FLL frequency retain their previous values during new - * clock mode change. - */ -/*@{*/ -#define BP_MCG_SC_FLTPRSRV (4U) /*!< Bit position for MCG_SC_FLTPRSRV. */ -#define BM_MCG_SC_FLTPRSRV (0x10U) /*!< Bit mask for MCG_SC_FLTPRSRV. */ -#define BS_MCG_SC_FLTPRSRV (1U) /*!< Bit field size in bits for MCG_SC_FLTPRSRV. */ - -/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */ -#define BR_MCG_SC_FLTPRSRV(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV)) - -/*! @brief Format value for bitfield MCG_SC_FLTPRSRV. */ -#define BF_MCG_SC_FLTPRSRV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FLTPRSRV) & BM_MCG_SC_FLTPRSRV) - -/*! @brief Set the FLTPRSRV field to a new value. */ -#define BW_MCG_SC_FLTPRSRV(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field ATMF[5] (RW) - * - * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the - * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC - * registers is detected or the MCG enters into any Stop mode. A write to ATMF - * clears the flag. - * - * Values: - * - 0 - Automatic Trim Machine completed normally. - * - 1 - Automatic Trim Machine failed. - */ -/*@{*/ -#define BP_MCG_SC_ATMF (5U) /*!< Bit position for MCG_SC_ATMF. */ -#define BM_MCG_SC_ATMF (0x20U) /*!< Bit mask for MCG_SC_ATMF. */ -#define BS_MCG_SC_ATMF (1U) /*!< Bit field size in bits for MCG_SC_ATMF. */ - -/*! @brief Read current value of the MCG_SC_ATMF field. */ -#define BR_MCG_SC_ATMF(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF)) - -/*! @brief Format value for bitfield MCG_SC_ATMF. */ -#define BF_MCG_SC_ATMF(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMF) & BM_MCG_SC_ATMF) - -/*! @brief Set the ATMF field to a new value. */ -#define BW_MCG_SC_ATMF(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field ATMS[6] (RW) - * - * Selects the IRCS clock for Auto Trim Test. - * - * Values: - * - 0 - 32 kHz Internal Reference Clock selected. - * - 1 - 4 MHz Internal Reference Clock selected. - */ -/*@{*/ -#define BP_MCG_SC_ATMS (6U) /*!< Bit position for MCG_SC_ATMS. */ -#define BM_MCG_SC_ATMS (0x40U) /*!< Bit mask for MCG_SC_ATMS. */ -#define BS_MCG_SC_ATMS (1U) /*!< Bit field size in bits for MCG_SC_ATMS. */ - -/*! @brief Read current value of the MCG_SC_ATMS field. */ -#define BR_MCG_SC_ATMS(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS)) - -/*! @brief Format value for bitfield MCG_SC_ATMS. */ -#define BF_MCG_SC_ATMS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMS) & BM_MCG_SC_ATMS) - -/*! @brief Set the ATMS field to a new value. */ -#define BW_MCG_SC_ATMS(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS) = (v)) -/*@}*/ - -/*! - * @name Register MCG_SC, field ATME[7] (RW) - * - * Enables the Auto Trim Machine to start automatically trimming the selected - * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has - * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing - * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim - * operation and clears this bit. - * - * Values: - * - 0 - Auto Trim Machine disabled. - * - 1 - Auto Trim Machine enabled. - */ -/*@{*/ -#define BP_MCG_SC_ATME (7U) /*!< Bit position for MCG_SC_ATME. */ -#define BM_MCG_SC_ATME (0x80U) /*!< Bit mask for MCG_SC_ATME. */ -#define BS_MCG_SC_ATME (1U) /*!< Bit field size in bits for MCG_SC_ATME. */ - -/*! @brief Read current value of the MCG_SC_ATME field. */ -#define BR_MCG_SC_ATME(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME)) - -/*! @brief Format value for bitfield MCG_SC_ATME. */ -#define BF_MCG_SC_ATME(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATME) & BM_MCG_SC_ATME) - -/*! @brief Set the ATME field to a new value. */ -#define BW_MCG_SC_ATME(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_atcvh -{ - uint8_t U; - struct _hw_mcg_atcvh_bitfields - { - uint8_t ATCVH : 8; /*!< [7:0] ATM Compare Value High */ - } B; -} hw_mcg_atcvh_t; - -/*! - * @name Constants and macros for entire MCG_ATCVH register - */ -/*@{*/ -#define HW_MCG_ATCVH_ADDR(x) ((x) + 0xAU) - -#define HW_MCG_ATCVH(x) (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR(x)) -#define HW_MCG_ATCVH_RD(x) (HW_MCG_ATCVH(x).U) -#define HW_MCG_ATCVH_WR(x, v) (HW_MCG_ATCVH(x).U = (v)) -#define HW_MCG_ATCVH_SET(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) | (v))) -#define HW_MCG_ATCVH_CLR(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) & ~(v))) -#define HW_MCG_ATCVH_TOG(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_ATCVH bitfields - */ - -/*! - * @name Register MCG_ATCVH, field ATCVH[7:0] (RW) - * - * Values are used by Auto Trim Machine to compare and adjust Internal Reference - * trim values during ATM SAR conversion. - */ -/*@{*/ -#define BP_MCG_ATCVH_ATCVH (0U) /*!< Bit position for MCG_ATCVH_ATCVH. */ -#define BM_MCG_ATCVH_ATCVH (0xFFU) /*!< Bit mask for MCG_ATCVH_ATCVH. */ -#define BS_MCG_ATCVH_ATCVH (8U) /*!< Bit field size in bits for MCG_ATCVH_ATCVH. */ - -/*! @brief Read current value of the MCG_ATCVH_ATCVH field. */ -#define BR_MCG_ATCVH_ATCVH(x) (HW_MCG_ATCVH(x).U) - -/*! @brief Format value for bitfield MCG_ATCVH_ATCVH. */ -#define BF_MCG_ATCVH_ATCVH(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVH_ATCVH) & BM_MCG_ATCVH_ATCVH) - -/*! @brief Set the ATCVH field to a new value. */ -#define BW_MCG_ATCVH_ATCVH(x, v) (HW_MCG_ATCVH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_atcvl -{ - uint8_t U; - struct _hw_mcg_atcvl_bitfields - { - uint8_t ATCVL : 8; /*!< [7:0] ATM Compare Value Low */ - } B; -} hw_mcg_atcvl_t; - -/*! - * @name Constants and macros for entire MCG_ATCVL register - */ -/*@{*/ -#define HW_MCG_ATCVL_ADDR(x) ((x) + 0xBU) - -#define HW_MCG_ATCVL(x) (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR(x)) -#define HW_MCG_ATCVL_RD(x) (HW_MCG_ATCVL(x).U) -#define HW_MCG_ATCVL_WR(x, v) (HW_MCG_ATCVL(x).U = (v)) -#define HW_MCG_ATCVL_SET(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) | (v))) -#define HW_MCG_ATCVL_CLR(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) & ~(v))) -#define HW_MCG_ATCVL_TOG(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_ATCVL bitfields - */ - -/*! - * @name Register MCG_ATCVL, field ATCVL[7:0] (RW) - * - * Values are used by Auto Trim Machine to compare and adjust Internal Reference - * trim values during ATM SAR conversion. - */ -/*@{*/ -#define BP_MCG_ATCVL_ATCVL (0U) /*!< Bit position for MCG_ATCVL_ATCVL. */ -#define BM_MCG_ATCVL_ATCVL (0xFFU) /*!< Bit mask for MCG_ATCVL_ATCVL. */ -#define BS_MCG_ATCVL_ATCVL (8U) /*!< Bit field size in bits for MCG_ATCVL_ATCVL. */ - -/*! @brief Read current value of the MCG_ATCVL_ATCVL field. */ -#define BR_MCG_ATCVL_ATCVL(x) (HW_MCG_ATCVL(x).U) - -/*! @brief Format value for bitfield MCG_ATCVL_ATCVL. */ -#define BF_MCG_ATCVL_ATCVL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVL_ATCVL) & BM_MCG_ATCVL_ATCVL) - -/*! @brief Set the ATCVL field to a new value. */ -#define BW_MCG_ATCVL_ATCVL(x, v) (HW_MCG_ATCVL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C7 - MCG Control 7 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C7 - MCG Control 7 Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_mcg_c7 -{ - uint8_t U; - struct _hw_mcg_c7_bitfields - { - uint8_t OSCSEL : 2; /*!< [1:0] MCG OSC Clock Select */ - uint8_t RESERVED0 : 6; /*!< [7:2] */ - } B; -} hw_mcg_c7_t; - -/*! - * @name Constants and macros for entire MCG_C7 register - */ -/*@{*/ -#define HW_MCG_C7_ADDR(x) ((x) + 0xCU) - -#define HW_MCG_C7(x) (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR(x)) -#define HW_MCG_C7_RD(x) (HW_MCG_C7(x).U) -#define HW_MCG_C7_WR(x, v) (HW_MCG_C7(x).U = (v)) -#define HW_MCG_C7_SET(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) | (v))) -#define HW_MCG_C7_CLR(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) & ~(v))) -#define HW_MCG_C7_TOG(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C7 bitfields - */ - -/*! - * @name Register MCG_C7, field OSCSEL[1:0] (RW) - * - * Selects the MCG FLL external reference clock - * - * Values: - * - 00 - Selects Oscillator (OSCCLK0). - * - 01 - Selects 32 kHz RTC Oscillator. - * - 10 - Selects Oscillator (OSCCLK1). - * - 11 - RESERVED - */ -/*@{*/ -#define BP_MCG_C7_OSCSEL (0U) /*!< Bit position for MCG_C7_OSCSEL. */ -#define BM_MCG_C7_OSCSEL (0x03U) /*!< Bit mask for MCG_C7_OSCSEL. */ -#define BS_MCG_C7_OSCSEL (2U) /*!< Bit field size in bits for MCG_C7_OSCSEL. */ - -/*! @brief Read current value of the MCG_C7_OSCSEL field. */ -#define BR_MCG_C7_OSCSEL(x) (HW_MCG_C7(x).B.OSCSEL) - -/*! @brief Format value for bitfield MCG_C7_OSCSEL. */ -#define BF_MCG_C7_OSCSEL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C7_OSCSEL) & BM_MCG_C7_OSCSEL) - -/*! @brief Set the OSCSEL field to a new value. */ -#define BW_MCG_C7_OSCSEL(x, v) (HW_MCG_C7_WR(x, (HW_MCG_C7_RD(x) & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCG_C8 - MCG Control 8 Register - ******************************************************************************/ - -/*! - * @brief HW_MCG_C8 - MCG Control 8 Register (RW) - * - * Reset value: 0x80U - */ -typedef union _hw_mcg_c8 -{ - uint8_t U; - struct _hw_mcg_c8_bitfields - { - uint8_t LOCS1 : 1; /*!< [0] RTC Loss of Clock Status */ - uint8_t RESERVED0 : 4; /*!< [4:1] */ - uint8_t CME1 : 1; /*!< [5] Clock Monitor Enable1 */ - uint8_t LOLRE : 1; /*!< [6] PLL Loss of Lock Reset Enable */ - uint8_t LOCRE1 : 1; /*!< [7] Loss of Clock Reset Enable */ - } B; -} hw_mcg_c8_t; - -/*! - * @name Constants and macros for entire MCG_C8 register - */ -/*@{*/ -#define HW_MCG_C8_ADDR(x) ((x) + 0xDU) - -#define HW_MCG_C8(x) (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR(x)) -#define HW_MCG_C8_RD(x) (HW_MCG_C8(x).U) -#define HW_MCG_C8_WR(x, v) (HW_MCG_C8(x).U = (v)) -#define HW_MCG_C8_SET(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) | (v))) -#define HW_MCG_C8_CLR(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) & ~(v))) -#define HW_MCG_C8_TOG(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCG_C8 bitfields - */ - -/*! - * @name Register MCG_C8, field LOCS1[0] (W1C) - * - * This bit indicates when a loss of clock has occurred. This bit is cleared by - * writing a logic 1 to it when set. - * - * Values: - * - 0 - Loss of RTC has not occur. - * - 1 - Loss of RTC has occur - */ -/*@{*/ -#define BP_MCG_C8_LOCS1 (0U) /*!< Bit position for MCG_C8_LOCS1. */ -#define BM_MCG_C8_LOCS1 (0x01U) /*!< Bit mask for MCG_C8_LOCS1. */ -#define BS_MCG_C8_LOCS1 (1U) /*!< Bit field size in bits for MCG_C8_LOCS1. */ - -/*! @brief Read current value of the MCG_C8_LOCS1 field. */ -#define BR_MCG_C8_LOCS1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1)) - -/*! @brief Format value for bitfield MCG_C8_LOCS1. */ -#define BF_MCG_C8_LOCS1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCS1) & BM_MCG_C8_LOCS1) - -/*! @brief Set the LOCS1 field to a new value. */ -#define BW_MCG_C8_LOCS1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C8, field CME1[5] (RW) - * - * Enables the loss of clock monitoring circuit for the output of the RTC - * external reference clock. The LOCRE1 bit will determine whether an interrupt or a - * reset request is generated following a loss of RTC clock indication. The CME1 - * bit should be set to a logic 1 when the MCG is in an operational mode that uses - * the RTC as its external reference clock or if the RTC is operational. CME1 bit - * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a - * reset request may occur when in Stop mode. CME1 should also be set to a logic 0 - * before entering VLPR or VLPW power modes. - * - * Values: - * - 0 - External clock monitor is disabled for RTC clock. - * - 1 - External clock monitor is enabled for RTC clock. - */ -/*@{*/ -#define BP_MCG_C8_CME1 (5U) /*!< Bit position for MCG_C8_CME1. */ -#define BM_MCG_C8_CME1 (0x20U) /*!< Bit mask for MCG_C8_CME1. */ -#define BS_MCG_C8_CME1 (1U) /*!< Bit field size in bits for MCG_C8_CME1. */ - -/*! @brief Read current value of the MCG_C8_CME1 field. */ -#define BR_MCG_C8_CME1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1)) - -/*! @brief Format value for bitfield MCG_C8_CME1. */ -#define BF_MCG_C8_CME1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_CME1) & BM_MCG_C8_CME1) - -/*! @brief Set the CME1 field to a new value. */ -#define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C8, field LOLRE[6] (RW) - * - * Determines if an interrupt or a reset request is made following a PLL loss of - * lock. - * - * Values: - * - 0 - Interrupt request is generated on a PLL loss of lock indication. The - * PLL loss of lock interrupt enable bit must also be set to generate the - * interrupt request. - * - 1 - Generate a reset request on a PLL loss of lock indication. - */ -/*@{*/ -#define BP_MCG_C8_LOLRE (6U) /*!< Bit position for MCG_C8_LOLRE. */ -#define BM_MCG_C8_LOLRE (0x40U) /*!< Bit mask for MCG_C8_LOLRE. */ -#define BS_MCG_C8_LOLRE (1U) /*!< Bit field size in bits for MCG_C8_LOLRE. */ - -/*! @brief Read current value of the MCG_C8_LOLRE field. */ -#define BR_MCG_C8_LOLRE(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE)) - -/*! @brief Format value for bitfield MCG_C8_LOLRE. */ -#define BF_MCG_C8_LOLRE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE) - -/*! @brief Set the LOLRE field to a new value. */ -#define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v)) -/*@}*/ - -/*! - * @name Register MCG_C8, field LOCRE1[7] (RW) - * - * Determines if a interrupt or a reset request is made following a loss of RTC - * external reference clock. The LOCRE1 only has an affect when CME1 is set. - * - * Values: - * - 0 - Interrupt request is generated on a loss of RTC external reference - * clock. - * - 1 - Generate a reset request on a loss of RTC external reference clock - */ -/*@{*/ -#define BP_MCG_C8_LOCRE1 (7U) /*!< Bit position for MCG_C8_LOCRE1. */ -#define BM_MCG_C8_LOCRE1 (0x80U) /*!< Bit mask for MCG_C8_LOCRE1. */ -#define BS_MCG_C8_LOCRE1 (1U) /*!< Bit field size in bits for MCG_C8_LOCRE1. */ - -/*! @brief Read current value of the MCG_C8_LOCRE1 field. */ -#define BR_MCG_C8_LOCRE1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1)) - -/*! @brief Format value for bitfield MCG_C8_LOCRE1. */ -#define BF_MCG_C8_LOCRE1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCRE1) & BM_MCG_C8_LOCRE1) - -/*! @brief Set the LOCRE1 field to a new value. */ -#define BW_MCG_C8_LOCRE1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_mcg_t - module struct - ******************************************************************************/ -/*! - * @brief All MCG module registers. - */ -#pragma pack(1) -typedef struct _hw_mcg -{ - __IO hw_mcg_c1_t C1; /*!< [0x0] MCG Control 1 Register */ - __IO hw_mcg_c2_t C2; /*!< [0x1] MCG Control 2 Register */ - __IO hw_mcg_c3_t C3; /*!< [0x2] MCG Control 3 Register */ - __IO hw_mcg_c4_t C4; /*!< [0x3] MCG Control 4 Register */ - __IO hw_mcg_c5_t C5; /*!< [0x4] MCG Control 5 Register */ - __IO hw_mcg_c6_t C6; /*!< [0x5] MCG Control 6 Register */ - __IO hw_mcg_s_t S; /*!< [0x6] MCG Status Register */ - uint8_t _reserved0[1]; - __IO hw_mcg_sc_t SC; /*!< [0x8] MCG Status and Control Register */ - uint8_t _reserved1[1]; - __IO hw_mcg_atcvh_t ATCVH; /*!< [0xA] MCG Auto Trim Compare Value High Register */ - __IO hw_mcg_atcvl_t ATCVL; /*!< [0xB] MCG Auto Trim Compare Value Low Register */ - __IO hw_mcg_c7_t C7; /*!< [0xC] MCG Control 7 Register */ - __IO hw_mcg_c8_t C8; /*!< [0xD] MCG Control 8 Register */ -} hw_mcg_t; -#pragma pack() - -/*! @brief Macro to access all MCG registers. */ -/*! @param x MCG module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_MCG(MCG_BASE). */ -#define HW_MCG(x) (*(hw_mcg_t *)(x)) - -#endif /* __HW_MCG_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcm.h deleted file mode 100644 index c807c35c20e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcm.h +++ /dev/null @@ -1,1089 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_MCM_REGISTERS_H__ -#define __HW_MCM_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 MCM - * - * Core Platform Miscellaneous Control Module - * - * Registers defined in this header file: - * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration - * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration - * - HW_MCM_CR - Control Register - * - HW_MCM_ISCR - Interrupt Status Register - * - HW_MCM_ETBCC - ETB Counter Control register - * - HW_MCM_ETBRL - ETB Reload register - * - HW_MCM_ETBCNT - ETB Counter Value register - * - HW_MCM_PID - Process ID register - * - * - hw_mcm_t - Struct containing all module registers. - */ - -#define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */ - -/******************************************************************************* - * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration - ******************************************************************************/ - -/*! - * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO) - * - * Reset value: 0x001FU - * - * PLASC is a 16-bit read-only register identifying the presence/absence of bus - * slave connections to the device's crossbar switch. - */ -typedef union _hw_mcm_plasc -{ - uint16_t U; - struct _hw_mcm_plasc_bitfields - { - uint16_t ASC : 8; /*!< [7:0] Each bit in the ASC field indicates - * whether there is a corresponding connection to the crossbar switch's slave - * input port. */ - uint16_t RESERVED0 : 8; /*!< [15:8] */ - } B; -} hw_mcm_plasc_t; - -/*! - * @name Constants and macros for entire MCM_PLASC register - */ -/*@{*/ -#define HW_MCM_PLASC_ADDR(x) ((x) + 0x8U) - -#define HW_MCM_PLASC(x) (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x)) -#define HW_MCM_PLASC_RD(x) (HW_MCM_PLASC(x).U) -/*@}*/ - -/* - * Constants & macros for individual MCM_PLASC bitfields - */ - -/*! - * @name Register MCM_PLASC, field ASC[7:0] (RO) - * - * Values: - * - 0 - A bus slave connection to AXBS input port n is absent - * - 1 - A bus slave connection to AXBS input port n is present - */ -/*@{*/ -#define BP_MCM_PLASC_ASC (0U) /*!< Bit position for MCM_PLASC_ASC. */ -#define BM_MCM_PLASC_ASC (0x00FFU) /*!< Bit mask for MCM_PLASC_ASC. */ -#define BS_MCM_PLASC_ASC (8U) /*!< Bit field size in bits for MCM_PLASC_ASC. */ - -/*! @brief Read current value of the MCM_PLASC_ASC field. */ -#define BR_MCM_PLASC_ASC(x) (HW_MCM_PLASC(x).B.ASC) -/*@}*/ - -/******************************************************************************* - * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration - ******************************************************************************/ - -/*! - * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO) - * - * Reset value: 0x0037U - * - * PLAMC is a 16-bit read-only register identifying the presence/absence of bus - * master connections to the device's crossbar switch. - */ -typedef union _hw_mcm_plamc -{ - uint16_t U; - struct _hw_mcm_plamc_bitfields - { - uint16_t AMC : 8; /*!< [7:0] Each bit in the AMC field indicates - * whether there is a corresponding connection to the AXBS master input port. */ - uint16_t RESERVED0 : 8; /*!< [15:8] */ - } B; -} hw_mcm_plamc_t; - -/*! - * @name Constants and macros for entire MCM_PLAMC register - */ -/*@{*/ -#define HW_MCM_PLAMC_ADDR(x) ((x) + 0xAU) - -#define HW_MCM_PLAMC(x) (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x)) -#define HW_MCM_PLAMC_RD(x) (HW_MCM_PLAMC(x).U) -/*@}*/ - -/* - * Constants & macros for individual MCM_PLAMC bitfields - */ - -/*! - * @name Register MCM_PLAMC, field AMC[7:0] (RO) - * - * Values: - * - 0 - A bus master connection to AXBS input port n is absent - * - 1 - A bus master connection to AXBS input port n is present - */ -/*@{*/ -#define BP_MCM_PLAMC_AMC (0U) /*!< Bit position for MCM_PLAMC_AMC. */ -#define BM_MCM_PLAMC_AMC (0x00FFU) /*!< Bit mask for MCM_PLAMC_AMC. */ -#define BS_MCM_PLAMC_AMC (8U) /*!< Bit field size in bits for MCM_PLAMC_AMC. */ - -/*! @brief Read current value of the MCM_PLAMC_AMC field. */ -#define BR_MCM_PLAMC_AMC(x) (HW_MCM_PLAMC(x).B.AMC) -/*@}*/ - -/******************************************************************************* - * HW_MCM_CR - Control Register - ******************************************************************************/ - -/*! - * @brief HW_MCM_CR - Control Register (RW) - * - * Reset value: 0x00000000U - * - * CR defines the arbitration and protection schemes for the two system RAM - * arrays. - */ -typedef union _hw_mcm_cr -{ - uint32_t U; - struct _hw_mcm_cr_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t SRAMUAP : 2; /*!< [25:24] SRAM_U arbitration priority */ - uint32_t SRAMUWP : 1; /*!< [26] SRAM_U write protect */ - uint32_t RESERVED1 : 1; /*!< [27] */ - uint32_t SRAMLAP : 2; /*!< [29:28] SRAM_L arbitration priority */ - uint32_t SRAMLWP : 1; /*!< [30] SRAM_L Write Protect */ - uint32_t RESERVED2 : 1; /*!< [31] */ - } B; -} hw_mcm_cr_t; - -/*! - * @name Constants and macros for entire MCM_CR register - */ -/*@{*/ -#define HW_MCM_CR_ADDR(x) ((x) + 0xCU) - -#define HW_MCM_CR(x) (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR(x)) -#define HW_MCM_CR_RD(x) (HW_MCM_CR(x).U) -#define HW_MCM_CR_WR(x, v) (HW_MCM_CR(x).U = (v)) -#define HW_MCM_CR_SET(x, v) (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) | (v))) -#define HW_MCM_CR_CLR(x, v) (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) & ~(v))) -#define HW_MCM_CR_TOG(x, v) (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_CR bitfields - */ - -/*! - * @name Register MCM_CR, field SRAMUAP[25:24] (RW) - * - * Defines the arbitration scheme and priority for the processor and SRAM - * backdoor accesses to the SRAM_U array. - * - * Values: - * - 00 - Round robin - * - 01 - Special round robin (favors SRAM backoor accesses over the processor) - * - 10 - Fixed priority. Processor has highest, backdoor has lowest - * - 11 - Fixed priority. Backdoor has highest, processor has lowest - */ -/*@{*/ -#define BP_MCM_CR_SRAMUAP (24U) /*!< Bit position for MCM_CR_SRAMUAP. */ -#define BM_MCM_CR_SRAMUAP (0x03000000U) /*!< Bit mask for MCM_CR_SRAMUAP. */ -#define BS_MCM_CR_SRAMUAP (2U) /*!< Bit field size in bits for MCM_CR_SRAMUAP. */ - -/*! @brief Read current value of the MCM_CR_SRAMUAP field. */ -#define BR_MCM_CR_SRAMUAP(x) (HW_MCM_CR(x).B.SRAMUAP) - -/*! @brief Format value for bitfield MCM_CR_SRAMUAP. */ -#define BF_MCM_CR_SRAMUAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUAP) & BM_MCM_CR_SRAMUAP) - -/*! @brief Set the SRAMUAP field to a new value. */ -#define BW_MCM_CR_SRAMUAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v))) -/*@}*/ - -/*! - * @name Register MCM_CR, field SRAMUWP[26] (RW) - * - * When this bit is set, writes to SRAM_U array generates a bus error. - */ -/*@{*/ -#define BP_MCM_CR_SRAMUWP (26U) /*!< Bit position for MCM_CR_SRAMUWP. */ -#define BM_MCM_CR_SRAMUWP (0x04000000U) /*!< Bit mask for MCM_CR_SRAMUWP. */ -#define BS_MCM_CR_SRAMUWP (1U) /*!< Bit field size in bits for MCM_CR_SRAMUWP. */ - -/*! @brief Read current value of the MCM_CR_SRAMUWP field. */ -#define BR_MCM_CR_SRAMUWP(x) (HW_MCM_CR(x).B.SRAMUWP) - -/*! @brief Format value for bitfield MCM_CR_SRAMUWP. */ -#define BF_MCM_CR_SRAMUWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUWP) & BM_MCM_CR_SRAMUWP) - -/*! @brief Set the SRAMUWP field to a new value. */ -#define BW_MCM_CR_SRAMUWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUWP) | BF_MCM_CR_SRAMUWP(v))) -/*@}*/ - -/*! - * @name Register MCM_CR, field SRAMLAP[29:28] (RW) - * - * Defines the arbitration scheme and priority for the processor and SRAM - * backdoor accesses to the SRAM_L array. - * - * Values: - * - 00 - Round robin - * - 01 - Special round robin (favors SRAM backoor accesses over the processor) - * - 10 - Fixed priority. Processor has highest, backdoor has lowest - * - 11 - Fixed priority. Backdoor has highest, processor has lowest - */ -/*@{*/ -#define BP_MCM_CR_SRAMLAP (28U) /*!< Bit position for MCM_CR_SRAMLAP. */ -#define BM_MCM_CR_SRAMLAP (0x30000000U) /*!< Bit mask for MCM_CR_SRAMLAP. */ -#define BS_MCM_CR_SRAMLAP (2U) /*!< Bit field size in bits for MCM_CR_SRAMLAP. */ - -/*! @brief Read current value of the MCM_CR_SRAMLAP field. */ -#define BR_MCM_CR_SRAMLAP(x) (HW_MCM_CR(x).B.SRAMLAP) - -/*! @brief Format value for bitfield MCM_CR_SRAMLAP. */ -#define BF_MCM_CR_SRAMLAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLAP) & BM_MCM_CR_SRAMLAP) - -/*! @brief Set the SRAMLAP field to a new value. */ -#define BW_MCM_CR_SRAMLAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v))) -/*@}*/ - -/*! - * @name Register MCM_CR, field SRAMLWP[30] (RW) - * - * When this bit is set, writes to SRAM_L array generates a bus error. - */ -/*@{*/ -#define BP_MCM_CR_SRAMLWP (30U) /*!< Bit position for MCM_CR_SRAMLWP. */ -#define BM_MCM_CR_SRAMLWP (0x40000000U) /*!< Bit mask for MCM_CR_SRAMLWP. */ -#define BS_MCM_CR_SRAMLWP (1U) /*!< Bit field size in bits for MCM_CR_SRAMLWP. */ - -/*! @brief Read current value of the MCM_CR_SRAMLWP field. */ -#define BR_MCM_CR_SRAMLWP(x) (HW_MCM_CR(x).B.SRAMLWP) - -/*! @brief Format value for bitfield MCM_CR_SRAMLWP. */ -#define BF_MCM_CR_SRAMLWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLWP) & BM_MCM_CR_SRAMLWP) - -/*! @brief Set the SRAMLWP field to a new value. */ -#define BW_MCM_CR_SRAMLWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLWP) | BF_MCM_CR_SRAMLWP(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCM_ISCR - Interrupt Status Register - ******************************************************************************/ - -/*! - * @brief HW_MCM_ISCR - Interrupt Status Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_mcm_iscr -{ - uint32_t U; - struct _hw_mcm_iscr_bitfields - { - uint32_t RESERVED0 : 1; /*!< [0] */ - uint32_t IRQ : 1; /*!< [1] Normal Interrupt Pending */ - uint32_t NMI : 1; /*!< [2] Non-maskable Interrupt Pending */ - uint32_t DHREQ : 1; /*!< [3] Debug Halt Request Indicator */ - uint32_t RESERVED1 : 4; /*!< [7:4] */ - uint32_t FIOC : 1; /*!< [8] FPU invalid operation interrupt status */ - uint32_t FDZC : 1; /*!< [9] FPU divide-by-zero interrupt status */ - uint32_t FOFC : 1; /*!< [10] FPU overflow interrupt status */ - uint32_t FUFC : 1; /*!< [11] FPU underflow interrupt status */ - uint32_t FIXC : 1; /*!< [12] FPU inexact interrupt status */ - uint32_t RESERVED2 : 2; /*!< [14:13] */ - uint32_t FIDC : 1; /*!< [15] FPU input denormal interrupt status */ - uint32_t RESERVED3 : 8; /*!< [23:16] */ - uint32_t FIOCE : 1; /*!< [24] FPU invalid operation interrupt enable - * */ - uint32_t FDZCE : 1; /*!< [25] FPU divide-by-zero interrupt enable */ - uint32_t FOFCE : 1; /*!< [26] FPU overflow interrupt enable */ - uint32_t FUFCE : 1; /*!< [27] FPU underflow interrupt enable */ - uint32_t FIXCE : 1; /*!< [28] FPU inexact interrupt enable */ - uint32_t RESERVED4 : 2; /*!< [30:29] */ - uint32_t FIDCE : 1; /*!< [31] FPU input denormal interrupt enable */ - } B; -} hw_mcm_iscr_t; - -/*! - * @name Constants and macros for entire MCM_ISCR register - */ -/*@{*/ -#define HW_MCM_ISCR_ADDR(x) ((x) + 0x10U) - -#define HW_MCM_ISCR(x) (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x)) -#define HW_MCM_ISCR_RD(x) (HW_MCM_ISCR(x).U) -#define HW_MCM_ISCR_WR(x, v) (HW_MCM_ISCR(x).U = (v)) -#define HW_MCM_ISCR_SET(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) | (v))) -#define HW_MCM_ISCR_CLR(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v))) -#define HW_MCM_ISCR_TOG(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_ISCR bitfields - */ - -/*! - * @name Register MCM_ISCR, field IRQ[1] (W1C) - * - * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires. - * - * Values: - * - 0 - No pending interrupt - * - 1 - Due to the ETB counter expiring, a normal interrupt is pending - */ -/*@{*/ -#define BP_MCM_ISCR_IRQ (1U) /*!< Bit position for MCM_ISCR_IRQ. */ -#define BM_MCM_ISCR_IRQ (0x00000002U) /*!< Bit mask for MCM_ISCR_IRQ. */ -#define BS_MCM_ISCR_IRQ (1U) /*!< Bit field size in bits for MCM_ISCR_IRQ. */ - -/*! @brief Read current value of the MCM_ISCR_IRQ field. */ -#define BR_MCM_ISCR_IRQ(x) (HW_MCM_ISCR(x).B.IRQ) - -/*! @brief Format value for bitfield MCM_ISCR_IRQ. */ -#define BF_MCM_ISCR_IRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_IRQ) & BM_MCM_ISCR_IRQ) - -/*! @brief Set the IRQ field to a new value. */ -#define BW_MCM_ISCR_IRQ(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_IRQ) | BF_MCM_ISCR_IRQ(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field NMI[2] (W1C) - * - * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires. - * - * Values: - * - 0 - No pending NMI - * - 1 - Due to the ETB counter expiring, an NMI is pending - */ -/*@{*/ -#define BP_MCM_ISCR_NMI (2U) /*!< Bit position for MCM_ISCR_NMI. */ -#define BM_MCM_ISCR_NMI (0x00000004U) /*!< Bit mask for MCM_ISCR_NMI. */ -#define BS_MCM_ISCR_NMI (1U) /*!< Bit field size in bits for MCM_ISCR_NMI. */ - -/*! @brief Read current value of the MCM_ISCR_NMI field. */ -#define BR_MCM_ISCR_NMI(x) (HW_MCM_ISCR(x).B.NMI) - -/*! @brief Format value for bitfield MCM_ISCR_NMI. */ -#define BF_MCM_ISCR_NMI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_NMI) & BM_MCM_ISCR_NMI) - -/*! @brief Set the NMI field to a new value. */ -#define BW_MCM_ISCR_NMI(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_NMI) | BF_MCM_ISCR_NMI(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field DHREQ[3] (RO) - * - * Indicates that a debug halt request is initiated due to a ETB counter - * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the - * counter is disabled or when the ETB counter is reloaded. - * - * Values: - * - 0 - No debug halt request - * - 1 - Debug halt request initiated - */ -/*@{*/ -#define BP_MCM_ISCR_DHREQ (3U) /*!< Bit position for MCM_ISCR_DHREQ. */ -#define BM_MCM_ISCR_DHREQ (0x00000008U) /*!< Bit mask for MCM_ISCR_DHREQ. */ -#define BS_MCM_ISCR_DHREQ (1U) /*!< Bit field size in bits for MCM_ISCR_DHREQ. */ - -/*! @brief Read current value of the MCM_ISCR_DHREQ field. */ -#define BR_MCM_ISCR_DHREQ(x) (HW_MCM_ISCR(x).B.DHREQ) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIOC[8] (RO) - * - * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an - * illegal operation has been detected in the processor's FPU. Once set, this bit - * remains set until software clears the FPSCR[IOC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FIOC (8U) /*!< Bit position for MCM_ISCR_FIOC. */ -#define BM_MCM_ISCR_FIOC (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */ -#define BS_MCM_ISCR_FIOC (1U) /*!< Bit field size in bits for MCM_ISCR_FIOC. */ - -/*! @brief Read current value of the MCM_ISCR_FIOC field. */ -#define BR_MCM_ISCR_FIOC(x) (HW_MCM_ISCR(x).B.FIOC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FDZC[9] (RO) - * - * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a - * divide by zero has been detected in the processor's FPU. Once set, this bit remains - * set until software clears the FPSCR[DZC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FDZC (9U) /*!< Bit position for MCM_ISCR_FDZC. */ -#define BM_MCM_ISCR_FDZC (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */ -#define BS_MCM_ISCR_FDZC (1U) /*!< Bit field size in bits for MCM_ISCR_FDZC. */ - -/*! @brief Read current value of the MCM_ISCR_FDZC field. */ -#define BR_MCM_ISCR_FDZC(x) (HW_MCM_ISCR(x).B.FDZC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FOFC[10] (RO) - * - * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an - * overflow has been detected in the processor's FPU. Once set, this bit remains set - * until software clears the FPSCR[OFC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FOFC (10U) /*!< Bit position for MCM_ISCR_FOFC. */ -#define BM_MCM_ISCR_FOFC (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */ -#define BS_MCM_ISCR_FOFC (1U) /*!< Bit field size in bits for MCM_ISCR_FOFC. */ - -/*! @brief Read current value of the MCM_ISCR_FOFC field. */ -#define BR_MCM_ISCR_FOFC(x) (HW_MCM_ISCR(x).B.FOFC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FUFC[11] (RO) - * - * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an - * underflow has been detected in the processor's FPU. Once set, this bit remains set - * until software clears the FPSCR[UFC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FUFC (11U) /*!< Bit position for MCM_ISCR_FUFC. */ -#define BM_MCM_ISCR_FUFC (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */ -#define BS_MCM_ISCR_FUFC (1U) /*!< Bit field size in bits for MCM_ISCR_FUFC. */ - -/*! @brief Read current value of the MCM_ISCR_FUFC field. */ -#define BR_MCM_ISCR_FUFC(x) (HW_MCM_ISCR(x).B.FUFC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIXC[12] (RO) - * - * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an - * inexact number has been detected in the processor's FPU. Once set, this bit - * remains set until software clears the FPSCR[IXC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FIXC (12U) /*!< Bit position for MCM_ISCR_FIXC. */ -#define BM_MCM_ISCR_FIXC (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */ -#define BS_MCM_ISCR_FIXC (1U) /*!< Bit field size in bits for MCM_ISCR_FIXC. */ - -/*! @brief Read current value of the MCM_ISCR_FIXC field. */ -#define BR_MCM_ISCR_FIXC(x) (HW_MCM_ISCR(x).B.FIXC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIDC[15] (RO) - * - * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input - * denormalized number has been detected in the processor's FPU. Once set, this - * bit remains set until software clears the FPSCR[IDC] bit. - * - * Values: - * - 0 - No interrupt - * - 1 - Interrupt occurred - */ -/*@{*/ -#define BP_MCM_ISCR_FIDC (15U) /*!< Bit position for MCM_ISCR_FIDC. */ -#define BM_MCM_ISCR_FIDC (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */ -#define BS_MCM_ISCR_FIDC (1U) /*!< Bit field size in bits for MCM_ISCR_FIDC. */ - -/*! @brief Read current value of the MCM_ISCR_FIDC field. */ -#define BR_MCM_ISCR_FIDC(x) (HW_MCM_ISCR(x).B.FIDC) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIOCE[24] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FIOCE (24U) /*!< Bit position for MCM_ISCR_FIOCE. */ -#define BM_MCM_ISCR_FIOCE (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */ -#define BS_MCM_ISCR_FIOCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIOCE. */ - -/*! @brief Read current value of the MCM_ISCR_FIOCE field. */ -#define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE) - -/*! @brief Format value for bitfield MCM_ISCR_FIOCE. */ -#define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE) - -/*! @brief Set the FIOCE field to a new value. */ -#define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FDZCE[25] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FDZCE (25U) /*!< Bit position for MCM_ISCR_FDZCE. */ -#define BM_MCM_ISCR_FDZCE (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */ -#define BS_MCM_ISCR_FDZCE (1U) /*!< Bit field size in bits for MCM_ISCR_FDZCE. */ - -/*! @brief Read current value of the MCM_ISCR_FDZCE field. */ -#define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE) - -/*! @brief Format value for bitfield MCM_ISCR_FDZCE. */ -#define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE) - -/*! @brief Set the FDZCE field to a new value. */ -#define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FOFCE[26] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FOFCE (26U) /*!< Bit position for MCM_ISCR_FOFCE. */ -#define BM_MCM_ISCR_FOFCE (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */ -#define BS_MCM_ISCR_FOFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FOFCE. */ - -/*! @brief Read current value of the MCM_ISCR_FOFCE field. */ -#define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE) - -/*! @brief Format value for bitfield MCM_ISCR_FOFCE. */ -#define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE) - -/*! @brief Set the FOFCE field to a new value. */ -#define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FUFCE[27] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FUFCE (27U) /*!< Bit position for MCM_ISCR_FUFCE. */ -#define BM_MCM_ISCR_FUFCE (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */ -#define BS_MCM_ISCR_FUFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FUFCE. */ - -/*! @brief Read current value of the MCM_ISCR_FUFCE field. */ -#define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE) - -/*! @brief Format value for bitfield MCM_ISCR_FUFCE. */ -#define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE) - -/*! @brief Set the FUFCE field to a new value. */ -#define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIXCE[28] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FIXCE (28U) /*!< Bit position for MCM_ISCR_FIXCE. */ -#define BM_MCM_ISCR_FIXCE (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */ -#define BS_MCM_ISCR_FIXCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIXCE. */ - -/*! @brief Read current value of the MCM_ISCR_FIXCE field. */ -#define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE) - -/*! @brief Format value for bitfield MCM_ISCR_FIXCE. */ -#define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE) - -/*! @brief Set the FIXCE field to a new value. */ -#define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v))) -/*@}*/ - -/*! - * @name Register MCM_ISCR, field FIDCE[31] (RW) - * - * Values: - * - 0 - Disable interrupt - * - 1 - Enable interrupt - */ -/*@{*/ -#define BP_MCM_ISCR_FIDCE (31U) /*!< Bit position for MCM_ISCR_FIDCE. */ -#define BM_MCM_ISCR_FIDCE (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */ -#define BS_MCM_ISCR_FIDCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIDCE. */ - -/*! @brief Read current value of the MCM_ISCR_FIDCE field. */ -#define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE) - -/*! @brief Format value for bitfield MCM_ISCR_FIDCE. */ -#define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE) - -/*! @brief Set the FIDCE field to a new value. */ -#define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCM_ETBCC - ETB Counter Control register - ******************************************************************************/ - -/*! - * @brief HW_MCM_ETBCC - ETB Counter Control register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_mcm_etbcc -{ - uint32_t U; - struct _hw_mcm_etbcc_bitfields - { - uint32_t CNTEN : 1; /*!< [0] Counter Enable */ - uint32_t RSPT : 2; /*!< [2:1] Response Type */ - uint32_t RLRQ : 1; /*!< [3] Reload Request */ - uint32_t ETDIS : 1; /*!< [4] ETM-To-TPIU Disable */ - uint32_t ITDIS : 1; /*!< [5] ITM-To-TPIU Disable */ - uint32_t RESERVED0 : 26; /*!< [31:6] */ - } B; -} hw_mcm_etbcc_t; - -/*! - * @name Constants and macros for entire MCM_ETBCC register - */ -/*@{*/ -#define HW_MCM_ETBCC_ADDR(x) ((x) + 0x14U) - -#define HW_MCM_ETBCC(x) (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR(x)) -#define HW_MCM_ETBCC_RD(x) (HW_MCM_ETBCC(x).U) -#define HW_MCM_ETBCC_WR(x, v) (HW_MCM_ETBCC(x).U = (v)) -#define HW_MCM_ETBCC_SET(x, v) (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) | (v))) -#define HW_MCM_ETBCC_CLR(x, v) (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) & ~(v))) -#define HW_MCM_ETBCC_TOG(x, v) (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_ETBCC bitfields - */ - -/*! - * @name Register MCM_ETBCC, field CNTEN[0] (RW) - * - * Enables the ETB counter. - * - * Values: - * - 0 - ETB counter disabled - * - 1 - ETB counter enabled - */ -/*@{*/ -#define BP_MCM_ETBCC_CNTEN (0U) /*!< Bit position for MCM_ETBCC_CNTEN. */ -#define BM_MCM_ETBCC_CNTEN (0x00000001U) /*!< Bit mask for MCM_ETBCC_CNTEN. */ -#define BS_MCM_ETBCC_CNTEN (1U) /*!< Bit field size in bits for MCM_ETBCC_CNTEN. */ - -/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */ -#define BR_MCM_ETBCC_CNTEN(x) (HW_MCM_ETBCC(x).B.CNTEN) - -/*! @brief Format value for bitfield MCM_ETBCC_CNTEN. */ -#define BF_MCM_ETBCC_CNTEN(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_CNTEN) & BM_MCM_ETBCC_CNTEN) - -/*! @brief Set the CNTEN field to a new value. */ -#define BW_MCM_ETBCC_CNTEN(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_CNTEN) | BF_MCM_ETBCC_CNTEN(v))) -/*@}*/ - -/*! - * @name Register MCM_ETBCC, field RSPT[2:1] (RW) - * - * Values: - * - 00 - No response when the ETB count expires - * - 01 - Generate a normal interrupt when the ETB count expires - * - 10 - Generate an NMI when the ETB count expires - * - 11 - Generate a debug halt when the ETB count expires - */ -/*@{*/ -#define BP_MCM_ETBCC_RSPT (1U) /*!< Bit position for MCM_ETBCC_RSPT. */ -#define BM_MCM_ETBCC_RSPT (0x00000006U) /*!< Bit mask for MCM_ETBCC_RSPT. */ -#define BS_MCM_ETBCC_RSPT (2U) /*!< Bit field size in bits for MCM_ETBCC_RSPT. */ - -/*! @brief Read current value of the MCM_ETBCC_RSPT field. */ -#define BR_MCM_ETBCC_RSPT(x) (HW_MCM_ETBCC(x).B.RSPT) - -/*! @brief Format value for bitfield MCM_ETBCC_RSPT. */ -#define BF_MCM_ETBCC_RSPT(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RSPT) & BM_MCM_ETBCC_RSPT) - -/*! @brief Set the RSPT field to a new value. */ -#define BW_MCM_ETBCC_RSPT(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v))) -/*@}*/ - -/*! - * @name Register MCM_ETBCC, field RLRQ[3] (RW) - * - * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI - * interrupts were enabled and an NMI or IRQ interrupt was generated on counter - * expiration, setting this bit clears the pending NMI or IRQ interrupt request. - * If debug halt was enabled and a debug halt request was asserted on counter - * expiration, setting this bit clears the debug halt request. - * - * Values: - * - 0 - No effect - * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests - */ -/*@{*/ -#define BP_MCM_ETBCC_RLRQ (3U) /*!< Bit position for MCM_ETBCC_RLRQ. */ -#define BM_MCM_ETBCC_RLRQ (0x00000008U) /*!< Bit mask for MCM_ETBCC_RLRQ. */ -#define BS_MCM_ETBCC_RLRQ (1U) /*!< Bit field size in bits for MCM_ETBCC_RLRQ. */ - -/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */ -#define BR_MCM_ETBCC_RLRQ(x) (HW_MCM_ETBCC(x).B.RLRQ) - -/*! @brief Format value for bitfield MCM_ETBCC_RLRQ. */ -#define BF_MCM_ETBCC_RLRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RLRQ) & BM_MCM_ETBCC_RLRQ) - -/*! @brief Set the RLRQ field to a new value. */ -#define BW_MCM_ETBCC_RLRQ(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RLRQ) | BF_MCM_ETBCC_RLRQ(v))) -/*@}*/ - -/*! - * @name Register MCM_ETBCC, field ETDIS[4] (RW) - * - * Disables the trace path from ETM to TPIU. - * - * Values: - * - 0 - ETM-to-TPIU trace path enabled - * - 1 - ETM-to-TPIU trace path disabled - */ -/*@{*/ -#define BP_MCM_ETBCC_ETDIS (4U) /*!< Bit position for MCM_ETBCC_ETDIS. */ -#define BM_MCM_ETBCC_ETDIS (0x00000010U) /*!< Bit mask for MCM_ETBCC_ETDIS. */ -#define BS_MCM_ETBCC_ETDIS (1U) /*!< Bit field size in bits for MCM_ETBCC_ETDIS. */ - -/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */ -#define BR_MCM_ETBCC_ETDIS(x) (HW_MCM_ETBCC(x).B.ETDIS) - -/*! @brief Format value for bitfield MCM_ETBCC_ETDIS. */ -#define BF_MCM_ETBCC_ETDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ETDIS) & BM_MCM_ETBCC_ETDIS) - -/*! @brief Set the ETDIS field to a new value. */ -#define BW_MCM_ETBCC_ETDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ETDIS) | BF_MCM_ETBCC_ETDIS(v))) -/*@}*/ - -/*! - * @name Register MCM_ETBCC, field ITDIS[5] (RW) - * - * Disables the trace path from ITM to TPIU. - * - * Values: - * - 0 - ITM-to-TPIU trace path enabled - * - 1 - ITM-to-TPIU trace path disabled - */ -/*@{*/ -#define BP_MCM_ETBCC_ITDIS (5U) /*!< Bit position for MCM_ETBCC_ITDIS. */ -#define BM_MCM_ETBCC_ITDIS (0x00000020U) /*!< Bit mask for MCM_ETBCC_ITDIS. */ -#define BS_MCM_ETBCC_ITDIS (1U) /*!< Bit field size in bits for MCM_ETBCC_ITDIS. */ - -/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */ -#define BR_MCM_ETBCC_ITDIS(x) (HW_MCM_ETBCC(x).B.ITDIS) - -/*! @brief Format value for bitfield MCM_ETBCC_ITDIS. */ -#define BF_MCM_ETBCC_ITDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ITDIS) & BM_MCM_ETBCC_ITDIS) - -/*! @brief Set the ITDIS field to a new value. */ -#define BW_MCM_ETBCC_ITDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ITDIS) | BF_MCM_ETBCC_ITDIS(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCM_ETBRL - ETB Reload register - ******************************************************************************/ - -/*! - * @brief HW_MCM_ETBRL - ETB Reload register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_mcm_etbrl -{ - uint32_t U; - struct _hw_mcm_etbrl_bitfields - { - uint32_t RELOAD : 11; /*!< [10:0] Byte Count Reload Value */ - uint32_t RESERVED0 : 21; /*!< [31:11] */ - } B; -} hw_mcm_etbrl_t; - -/*! - * @name Constants and macros for entire MCM_ETBRL register - */ -/*@{*/ -#define HW_MCM_ETBRL_ADDR(x) ((x) + 0x18U) - -#define HW_MCM_ETBRL(x) (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR(x)) -#define HW_MCM_ETBRL_RD(x) (HW_MCM_ETBRL(x).U) -#define HW_MCM_ETBRL_WR(x, v) (HW_MCM_ETBRL(x).U = (v)) -#define HW_MCM_ETBRL_SET(x, v) (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) | (v))) -#define HW_MCM_ETBRL_CLR(x, v) (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) & ~(v))) -#define HW_MCM_ETBRL_TOG(x, v) (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_ETBRL bitfields - */ - -/*! - * @name Register MCM_ETBRL, field RELOAD[10:0] (RW) - * - * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4 - * value to this field results in a bus error. - */ -/*@{*/ -#define BP_MCM_ETBRL_RELOAD (0U) /*!< Bit position for MCM_ETBRL_RELOAD. */ -#define BM_MCM_ETBRL_RELOAD (0x000007FFU) /*!< Bit mask for MCM_ETBRL_RELOAD. */ -#define BS_MCM_ETBRL_RELOAD (11U) /*!< Bit field size in bits for MCM_ETBRL_RELOAD. */ - -/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */ -#define BR_MCM_ETBRL_RELOAD(x) (HW_MCM_ETBRL(x).B.RELOAD) - -/*! @brief Format value for bitfield MCM_ETBRL_RELOAD. */ -#define BF_MCM_ETBRL_RELOAD(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBRL_RELOAD) & BM_MCM_ETBRL_RELOAD) - -/*! @brief Set the RELOAD field to a new value. */ -#define BW_MCM_ETBRL_RELOAD(x, v) (HW_MCM_ETBRL_WR(x, (HW_MCM_ETBRL_RD(x) & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v))) -/*@}*/ - -/******************************************************************************* - * HW_MCM_ETBCNT - ETB Counter Value register - ******************************************************************************/ - -/*! - * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_mcm_etbcnt -{ - uint32_t U; - struct _hw_mcm_etbcnt_bitfields - { - uint32_t COUNTER : 11; /*!< [10:0] Byte Count Counter Value */ - uint32_t RESERVED0 : 21; /*!< [31:11] */ - } B; -} hw_mcm_etbcnt_t; - -/*! - * @name Constants and macros for entire MCM_ETBCNT register - */ -/*@{*/ -#define HW_MCM_ETBCNT_ADDR(x) ((x) + 0x1CU) - -#define HW_MCM_ETBCNT(x) (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR(x)) -#define HW_MCM_ETBCNT_RD(x) (HW_MCM_ETBCNT(x).U) -/*@}*/ - -/* - * Constants & macros for individual MCM_ETBCNT bitfields - */ - -/*! - * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO) - * - * Indicates the current 0-mod-4 value of the counter. - */ -/*@{*/ -#define BP_MCM_ETBCNT_COUNTER (0U) /*!< Bit position for MCM_ETBCNT_COUNTER. */ -#define BM_MCM_ETBCNT_COUNTER (0x000007FFU) /*!< Bit mask for MCM_ETBCNT_COUNTER. */ -#define BS_MCM_ETBCNT_COUNTER (11U) /*!< Bit field size in bits for MCM_ETBCNT_COUNTER. */ - -/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */ -#define BR_MCM_ETBCNT_COUNTER(x) (HW_MCM_ETBCNT(x).B.COUNTER) -/*@}*/ - -/******************************************************************************* - * HW_MCM_PID - Process ID register - ******************************************************************************/ - -/*! - * @brief HW_MCM_PID - Process ID register (RW) - * - * Reset value: 0x00000000U - * - * This register drives the M0_PID and M1_PID values in the Memory Protection - * Unit(MPU). System software loads this register before passing control to a given - * user mode process. If the PID of the process does not match the value in this - * register, a bus error occurs. See the MPU chapter for more details. - */ -typedef union _hw_mcm_pid -{ - uint32_t U; - struct _hw_mcm_pid_bitfields - { - uint32_t PID : 8; /*!< [7:0] M0_PID And M1_PID For MPU */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_mcm_pid_t; - -/*! - * @name Constants and macros for entire MCM_PID register - */ -/*@{*/ -#define HW_MCM_PID_ADDR(x) ((x) + 0x30U) - -#define HW_MCM_PID(x) (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR(x)) -#define HW_MCM_PID_RD(x) (HW_MCM_PID(x).U) -#define HW_MCM_PID_WR(x, v) (HW_MCM_PID(x).U = (v)) -#define HW_MCM_PID_SET(x, v) (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) | (v))) -#define HW_MCM_PID_CLR(x, v) (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) & ~(v))) -#define HW_MCM_PID_TOG(x, v) (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MCM_PID bitfields - */ - -/*! - * @name Register MCM_PID, field PID[7:0] (RW) - * - * Drives the M0_PID and M1_PID values in the MPU. - */ -/*@{*/ -#define BP_MCM_PID_PID (0U) /*!< Bit position for MCM_PID_PID. */ -#define BM_MCM_PID_PID (0x000000FFU) /*!< Bit mask for MCM_PID_PID. */ -#define BS_MCM_PID_PID (8U) /*!< Bit field size in bits for MCM_PID_PID. */ - -/*! @brief Read current value of the MCM_PID_PID field. */ -#define BR_MCM_PID_PID(x) (HW_MCM_PID(x).B.PID) - -/*! @brief Format value for bitfield MCM_PID_PID. */ -#define BF_MCM_PID_PID(v) ((uint32_t)((uint32_t)(v) << BP_MCM_PID_PID) & BM_MCM_PID_PID) - -/*! @brief Set the PID field to a new value. */ -#define BW_MCM_PID_PID(x, v) (HW_MCM_PID_WR(x, (HW_MCM_PID_RD(x) & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v))) -/*@}*/ - -/******************************************************************************* - * hw_mcm_t - module struct - ******************************************************************************/ -/*! - * @brief All MCM module registers. - */ -#pragma pack(1) -typedef struct _hw_mcm -{ - uint8_t _reserved0[8]; - __I hw_mcm_plasc_t PLASC; /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */ - __I hw_mcm_plamc_t PLAMC; /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */ - __IO hw_mcm_cr_t CR; /*!< [0xC] Control Register */ - __IO hw_mcm_iscr_t ISCR; /*!< [0x10] Interrupt Status Register */ - __IO hw_mcm_etbcc_t ETBCC; /*!< [0x14] ETB Counter Control register */ - __IO hw_mcm_etbrl_t ETBRL; /*!< [0x18] ETB Reload register */ - __I hw_mcm_etbcnt_t ETBCNT; /*!< [0x1C] ETB Counter Value register */ - uint8_t _reserved1[16]; - __IO hw_mcm_pid_t PID; /*!< [0x30] Process ID register */ -} hw_mcm_t; -#pragma pack() - -/*! @brief Macro to access all MCM registers. */ -/*! @param x MCM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_MCM(MCM_BASE). */ -#define HW_MCM(x) (*(hw_mcm_t *)(x)) - -#endif /* __HW_MCM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mpu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mpu.h deleted file mode 100644 index 15691ba17ba..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mpu.h +++ /dev/null @@ -1,1741 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_MPU_REGISTERS_H__ -#define __HW_MPU_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 MPU - * - * Memory protection unit - * - * Registers defined in this header file: - * - HW_MPU_CESR - Control/Error Status Register - * - HW_MPU_EARn - Error Address Register, slave port n - * - HW_MPU_EDRn - Error Detail Register, slave port n - * - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 - * - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 - * - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 - * - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 - * - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n - * - * - hw_mpu_t - Struct containing all module registers. - */ - -#define HW_MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */ - -/******************************************************************************* - * HW_MPU_CESR - Control/Error Status Register - ******************************************************************************/ - -/*! - * @brief HW_MPU_CESR - Control/Error Status Register (RW) - * - * Reset value: 0x00815101U - */ -typedef union _hw_mpu_cesr -{ - uint32_t U; - struct _hw_mpu_cesr_bitfields - { - uint32_t VLD : 1; /*!< [0] Valid */ - uint32_t RESERVED0 : 7; /*!< [7:1] */ - uint32_t NRGD : 4; /*!< [11:8] Number Of Region Descriptors */ - uint32_t NSP : 4; /*!< [15:12] Number Of Slave Ports */ - uint32_t HRL : 4; /*!< [19:16] Hardware Revision Level */ - uint32_t RESERVED1 : 7; /*!< [26:20] */ - uint32_t SPERR : 5; /*!< [31:27] Slave Port n Error */ - } B; -} hw_mpu_cesr_t; - -/*! - * @name Constants and macros for entire MPU_CESR register - */ -/*@{*/ -#define HW_MPU_CESR_ADDR(x) ((x) + 0x0U) - -#define HW_MPU_CESR(x) (*(__IO hw_mpu_cesr_t *) HW_MPU_CESR_ADDR(x)) -#define HW_MPU_CESR_RD(x) (HW_MPU_CESR(x).U) -#define HW_MPU_CESR_WR(x, v) (HW_MPU_CESR(x).U = (v)) -#define HW_MPU_CESR_SET(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) | (v))) -#define HW_MPU_CESR_CLR(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) & ~(v))) -#define HW_MPU_CESR_TOG(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MPU_CESR bitfields - */ - -/*! - * @name Register MPU_CESR, field VLD[0] (RW) - * - * Global enable/disable for the MPU. - * - * Values: - * - 0 - MPU is disabled. All accesses from all bus masters are allowed. - * - 1 - MPU is enabled - */ -/*@{*/ -#define BP_MPU_CESR_VLD (0U) /*!< Bit position for MPU_CESR_VLD. */ -#define BM_MPU_CESR_VLD (0x00000001U) /*!< Bit mask for MPU_CESR_VLD. */ -#define BS_MPU_CESR_VLD (1U) /*!< Bit field size in bits for MPU_CESR_VLD. */ - -/*! @brief Read current value of the MPU_CESR_VLD field. */ -#define BR_MPU_CESR_VLD(x) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD)) - -/*! @brief Format value for bitfield MPU_CESR_VLD. */ -#define BF_MPU_CESR_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_VLD) & BM_MPU_CESR_VLD) - -/*! @brief Set the VLD field to a new value. */ -#define BW_MPU_CESR_VLD(x, v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD) = (v)) -/*@}*/ - -/*! - * @name Register MPU_CESR, field NRGD[11:8] (RO) - * - * Indicates the number of region descriptors implemented in the MPU. - * - * Values: - * - 0000 - 8 region descriptors - * - 0001 - 12 region descriptors - * - 0010 - 16 region descriptors - */ -/*@{*/ -#define BP_MPU_CESR_NRGD (8U) /*!< Bit position for MPU_CESR_NRGD. */ -#define BM_MPU_CESR_NRGD (0x00000F00U) /*!< Bit mask for MPU_CESR_NRGD. */ -#define BS_MPU_CESR_NRGD (4U) /*!< Bit field size in bits for MPU_CESR_NRGD. */ - -/*! @brief Read current value of the MPU_CESR_NRGD field. */ -#define BR_MPU_CESR_NRGD(x) (HW_MPU_CESR(x).B.NRGD) -/*@}*/ - -/*! - * @name Register MPU_CESR, field NSP[15:12] (RO) - * - * Specifies the number of slave ports connected to the MPU. - */ -/*@{*/ -#define BP_MPU_CESR_NSP (12U) /*!< Bit position for MPU_CESR_NSP. */ -#define BM_MPU_CESR_NSP (0x0000F000U) /*!< Bit mask for MPU_CESR_NSP. */ -#define BS_MPU_CESR_NSP (4U) /*!< Bit field size in bits for MPU_CESR_NSP. */ - -/*! @brief Read current value of the MPU_CESR_NSP field. */ -#define BR_MPU_CESR_NSP(x) (HW_MPU_CESR(x).B.NSP) -/*@}*/ - -/*! - * @name Register MPU_CESR, field HRL[19:16] (RO) - * - * Specifies the MPU's hardware and definition revision level. It can be read by - * software to determine the functional definition of the module. - */ -/*@{*/ -#define BP_MPU_CESR_HRL (16U) /*!< Bit position for MPU_CESR_HRL. */ -#define BM_MPU_CESR_HRL (0x000F0000U) /*!< Bit mask for MPU_CESR_HRL. */ -#define BS_MPU_CESR_HRL (4U) /*!< Bit field size in bits for MPU_CESR_HRL. */ - -/*! @brief Read current value of the MPU_CESR_HRL field. */ -#define BR_MPU_CESR_HRL(x) (HW_MPU_CESR(x).B.HRL) -/*@}*/ - -/*! - * @name Register MPU_CESR, field SPERR[31:27] (W1C) - * - * Indicates a captured error in EARn and EDRn. This bit is set when the - * hardware detects an error and records the faulting address and attributes. It is - * cleared by writing one to it. If another error is captured at the exact same cycle - * as the write, the flag remains set. A find-first-one instruction or - * equivalent can detect the presence of a captured error. The following shows the - * correspondence between the bit number and slave port number: Bit 31 corresponds to - * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave - * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4. - * - * Values: - * - 0 - No error has occurred for slave port n. - * - 1 - An error has occurred for slave port n. - */ -/*@{*/ -#define BP_MPU_CESR_SPERR (27U) /*!< Bit position for MPU_CESR_SPERR. */ -#define BM_MPU_CESR_SPERR (0xF8000000U) /*!< Bit mask for MPU_CESR_SPERR. */ -#define BS_MPU_CESR_SPERR (5U) /*!< Bit field size in bits for MPU_CESR_SPERR. */ - -/*! @brief Read current value of the MPU_CESR_SPERR field. */ -#define BR_MPU_CESR_SPERR(x) (HW_MPU_CESR(x).B.SPERR) - -/*! @brief Format value for bitfield MPU_CESR_SPERR. */ -#define BF_MPU_CESR_SPERR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_SPERR) & BM_MPU_CESR_SPERR) - -/*! @brief Set the SPERR field to a new value. */ -#define BW_MPU_CESR_SPERR(x, v) (HW_MPU_CESR_WR(x, (HW_MPU_CESR_RD(x) & ~BM_MPU_CESR_SPERR) | BF_MPU_CESR_SPERR(v))) -/*@}*/ - -/******************************************************************************* - * HW_MPU_EARn - Error Address Register, slave port n - ******************************************************************************/ - -/*! - * @brief HW_MPU_EARn - Error Address Register, slave port n (RO) - * - * Reset value: 0x00000000U - * - * When the MPU detects an access error on slave port n, the 32-bit reference - * address is captured in this read-only register and the corresponding bit in - * CESR[SPERR] set. Additional information about the faulting access is captured in - * the corresponding EDRn at the same time. This register and the corresponding - * EDRn contain the most recent access error; there are no hardware interlocks with - * CESR[SPERR], as the error registers are always loaded upon the occurrence of - * each protection violation. - */ -typedef union _hw_mpu_earn -{ - uint32_t U; - struct _hw_mpu_earn_bitfields - { - uint32_t EADDR : 32; /*!< [31:0] Error Address */ - } B; -} hw_mpu_earn_t; - -/*! - * @name Constants and macros for entire MPU_EARn register - */ -/*@{*/ -#define HW_MPU_EARn_COUNT (5U) - -#define HW_MPU_EARn_ADDR(x, n) ((x) + 0x10U + (0x8U * (n))) - -#define HW_MPU_EARn(x, n) (*(__I hw_mpu_earn_t *) HW_MPU_EARn_ADDR(x, n)) -#define HW_MPU_EARn_RD(x, n) (HW_MPU_EARn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual MPU_EARn bitfields - */ - -/*! - * @name Register MPU_EARn, field EADDR[31:0] (RO) - * - * Indicates the reference address from slave port n that generated the access - * error - */ -/*@{*/ -#define BP_MPU_EARn_EADDR (0U) /*!< Bit position for MPU_EARn_EADDR. */ -#define BM_MPU_EARn_EADDR (0xFFFFFFFFU) /*!< Bit mask for MPU_EARn_EADDR. */ -#define BS_MPU_EARn_EADDR (32U) /*!< Bit field size in bits for MPU_EARn_EADDR. */ - -/*! @brief Read current value of the MPU_EARn_EADDR field. */ -#define BR_MPU_EARn_EADDR(x, n) (HW_MPU_EARn(x, n).U) -/*@}*/ -/******************************************************************************* - * HW_MPU_EDRn - Error Detail Register, slave port n - ******************************************************************************/ - -/*! - * @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO) - * - * Reset value: 0x00000000U - * - * When the MPU detects an access error on slave port n, 32 bits of error detail - * are captured in this read-only register and the corresponding bit in - * CESR[SPERR] is set. Information on the faulting address is captured in the - * corresponding EARn register at the same time. This register and the corresponding EARn - * register contain the most recent access error; there are no hardware interlocks - * with CESR[SPERR] as the error registers are always loaded upon the occurrence - * of each protection violation. - */ -typedef union _hw_mpu_edrn -{ - uint32_t U; - struct _hw_mpu_edrn_bitfields - { - uint32_t ERW : 1; /*!< [0] Error Read/Write */ - uint32_t EATTR : 3; /*!< [3:1] Error Attributes */ - uint32_t EMN : 4; /*!< [7:4] Error Master Number */ - uint32_t EPID : 8; /*!< [15:8] Error Process Identification */ - uint32_t EACD : 16; /*!< [31:16] Error Access Control Detail */ - } B; -} hw_mpu_edrn_t; - -/*! - * @name Constants and macros for entire MPU_EDRn register - */ -/*@{*/ -#define HW_MPU_EDRn_COUNT (5U) - -#define HW_MPU_EDRn_ADDR(x, n) ((x) + 0x14U + (0x8U * (n))) - -#define HW_MPU_EDRn(x, n) (*(__I hw_mpu_edrn_t *) HW_MPU_EDRn_ADDR(x, n)) -#define HW_MPU_EDRn_RD(x, n) (HW_MPU_EDRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual MPU_EDRn bitfields - */ - -/*! - * @name Register MPU_EDRn, field ERW[0] (RO) - * - * Indicates the access type of the faulting reference. - * - * Values: - * - 0 - Read - * - 1 - Write - */ -/*@{*/ -#define BP_MPU_EDRn_ERW (0U) /*!< Bit position for MPU_EDRn_ERW. */ -#define BM_MPU_EDRn_ERW (0x00000001U) /*!< Bit mask for MPU_EDRn_ERW. */ -#define BS_MPU_EDRn_ERW (1U) /*!< Bit field size in bits for MPU_EDRn_ERW. */ - -/*! @brief Read current value of the MPU_EDRn_ERW field. */ -#define BR_MPU_EDRn_ERW(x, n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(x, n), BP_MPU_EDRn_ERW)) -/*@}*/ - -/*! - * @name Register MPU_EDRn, field EATTR[3:1] (RO) - * - * Indicates attribute information about the faulting reference. All other - * encodings are reserved. - * - * Values: - * - 000 - User mode, instruction access - * - 001 - User mode, data access - * - 010 - Supervisor mode, instruction access - * - 011 - Supervisor mode, data access - */ -/*@{*/ -#define BP_MPU_EDRn_EATTR (1U) /*!< Bit position for MPU_EDRn_EATTR. */ -#define BM_MPU_EDRn_EATTR (0x0000000EU) /*!< Bit mask for MPU_EDRn_EATTR. */ -#define BS_MPU_EDRn_EATTR (3U) /*!< Bit field size in bits for MPU_EDRn_EATTR. */ - -/*! @brief Read current value of the MPU_EDRn_EATTR field. */ -#define BR_MPU_EDRn_EATTR(x, n) (HW_MPU_EDRn(x, n).B.EATTR) -/*@}*/ - -/*! - * @name Register MPU_EDRn, field EMN[7:4] (RO) - * - * Indicates the bus master that generated the access error. - */ -/*@{*/ -#define BP_MPU_EDRn_EMN (4U) /*!< Bit position for MPU_EDRn_EMN. */ -#define BM_MPU_EDRn_EMN (0x000000F0U) /*!< Bit mask for MPU_EDRn_EMN. */ -#define BS_MPU_EDRn_EMN (4U) /*!< Bit field size in bits for MPU_EDRn_EMN. */ - -/*! @brief Read current value of the MPU_EDRn_EMN field. */ -#define BR_MPU_EDRn_EMN(x, n) (HW_MPU_EDRn(x, n).B.EMN) -/*@}*/ - -/*! - * @name Register MPU_EDRn, field EPID[15:8] (RO) - * - * Records the process identifier of the faulting reference. The process - * identifier is typically driven only by processor cores; for other bus masters, this - * field is cleared. - */ -/*@{*/ -#define BP_MPU_EDRn_EPID (8U) /*!< Bit position for MPU_EDRn_EPID. */ -#define BM_MPU_EDRn_EPID (0x0000FF00U) /*!< Bit mask for MPU_EDRn_EPID. */ -#define BS_MPU_EDRn_EPID (8U) /*!< Bit field size in bits for MPU_EDRn_EPID. */ - -/*! @brief Read current value of the MPU_EDRn_EPID field. */ -#define BR_MPU_EDRn_EPID(x, n) (HW_MPU_EDRn(x, n).B.EPID) -/*@}*/ - -/*! - * @name Register MPU_EDRn, field EACD[31:16] (RO) - * - * Indicates the region descriptor with the access error. If EDRn contains a - * captured error and EACD is cleared, an access did not hit in any region - * descriptor. If only a single EACD bit is set, the protection error was caused by a - * single non-overlapping region descriptor. If two or more EACD bits are set, the - * protection error was caused by an overlapping set of region descriptors. - */ -/*@{*/ -#define BP_MPU_EDRn_EACD (16U) /*!< Bit position for MPU_EDRn_EACD. */ -#define BM_MPU_EDRn_EACD (0xFFFF0000U) /*!< Bit mask for MPU_EDRn_EACD. */ -#define BS_MPU_EDRn_EACD (16U) /*!< Bit field size in bits for MPU_EDRn_EACD. */ - -/*! @brief Read current value of the MPU_EDRn_EACD field. */ -#define BR_MPU_EDRn_EACD(x, n) (HW_MPU_EDRn(x, n).B.EACD) -/*@}*/ - -/******************************************************************************* - * HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 - ******************************************************************************/ - -/*! - * @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW) - * - * Reset value: 0x00000000U - * - * The first word of the region descriptor defines the 0-modulo-32 byte start - * address of the memory region. Writes to this register clear the region - * descriptor's valid bit (RGDn_WORD3[VLD]). - */ -typedef union _hw_mpu_rgdn_word0 -{ - uint32_t U; - struct _hw_mpu_rgdn_word0_bitfields - { - uint32_t RESERVED0 : 5; /*!< [4:0] */ - uint32_t SRTADDR : 27; /*!< [31:5] Start Address */ - } B; -} hw_mpu_rgdn_word0_t; - -/*! - * @name Constants and macros for entire MPU_RGDn_WORD0 register - */ -/*@{*/ -#define HW_MPU_RGDn_WORD0_COUNT (12U) - -#define HW_MPU_RGDn_WORD0_ADDR(x, n) ((x) + 0x400U + (0x10U * (n))) - -#define HW_MPU_RGDn_WORD0(x, n) (*(__IO hw_mpu_rgdn_word0_t *) HW_MPU_RGDn_WORD0_ADDR(x, n)) -#define HW_MPU_RGDn_WORD0_RD(x, n) (HW_MPU_RGDn_WORD0(x, n).U) -#define HW_MPU_RGDn_WORD0_WR(x, n, v) (HW_MPU_RGDn_WORD0(x, n).U = (v)) -#define HW_MPU_RGDn_WORD0_SET(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) | (v))) -#define HW_MPU_RGDn_WORD0_CLR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) & ~(v))) -#define HW_MPU_RGDn_WORD0_TOG(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MPU_RGDn_WORD0 bitfields - */ - -/*! - * @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW) - * - * Defines the most significant bits of the 0-modulo-32 byte start address of - * the memory region. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD0_SRTADDR (5U) /*!< Bit position for MPU_RGDn_WORD0_SRTADDR. */ -#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) /*!< Bit mask for MPU_RGDn_WORD0_SRTADDR. */ -#define BS_MPU_RGDn_WORD0_SRTADDR (27U) /*!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR. */ - -/*! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field. */ -#define BR_MPU_RGDn_WORD0_SRTADDR(x, n) (HW_MPU_RGDn_WORD0(x, n).B.SRTADDR) - -/*! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR. */ -#define BF_MPU_RGDn_WORD0_SRTADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD0_SRTADDR) & BM_MPU_RGDn_WORD0_SRTADDR) - -/*! @brief Set the SRTADDR field to a new value. */ -#define BW_MPU_RGDn_WORD0_SRTADDR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, (HW_MPU_RGDn_WORD0_RD(x, n) & ~BM_MPU_RGDn_WORD0_SRTADDR) | BF_MPU_RGDn_WORD0_SRTADDR(v))) -/*@}*/ -/******************************************************************************* - * HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 - ******************************************************************************/ - -/*! - * @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW) - * - * Reset value: 0xFFFFFFFFU - * - * The second word of the region descriptor defines the 31-modulo-32 byte end - * address of the memory region. Writes to this register clear the region - * descriptor's valid bit (RGDn_WORD3[VLD]). - */ -typedef union _hw_mpu_rgdn_word1 -{ - uint32_t U; - struct _hw_mpu_rgdn_word1_bitfields - { - uint32_t RESERVED0 : 5; /*!< [4:0] */ - uint32_t ENDADDR : 27; /*!< [31:5] End Address */ - } B; -} hw_mpu_rgdn_word1_t; - -/*! - * @name Constants and macros for entire MPU_RGDn_WORD1 register - */ -/*@{*/ -#define HW_MPU_RGDn_WORD1_COUNT (12U) - -#define HW_MPU_RGDn_WORD1_ADDR(x, n) ((x) + 0x404U + (0x10U * (n))) - -#define HW_MPU_RGDn_WORD1(x, n) (*(__IO hw_mpu_rgdn_word1_t *) HW_MPU_RGDn_WORD1_ADDR(x, n)) -#define HW_MPU_RGDn_WORD1_RD(x, n) (HW_MPU_RGDn_WORD1(x, n).U) -#define HW_MPU_RGDn_WORD1_WR(x, n, v) (HW_MPU_RGDn_WORD1(x, n).U = (v)) -#define HW_MPU_RGDn_WORD1_SET(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) | (v))) -#define HW_MPU_RGDn_WORD1_CLR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) & ~(v))) -#define HW_MPU_RGDn_WORD1_TOG(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MPU_RGDn_WORD1 bitfields - */ - -/*! - * @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW) - * - * Defines the most significant bits of the 31-modulo-32 byte end address of the - * memory region. The MPU does not verify that ENDADDR >= SRTADDR. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD1_ENDADDR (5U) /*!< Bit position for MPU_RGDn_WORD1_ENDADDR. */ -#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) /*!< Bit mask for MPU_RGDn_WORD1_ENDADDR. */ -#define BS_MPU_RGDn_WORD1_ENDADDR (27U) /*!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR. */ - -/*! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field. */ -#define BR_MPU_RGDn_WORD1_ENDADDR(x, n) (HW_MPU_RGDn_WORD1(x, n).B.ENDADDR) - -/*! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR. */ -#define BF_MPU_RGDn_WORD1_ENDADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD1_ENDADDR) & BM_MPU_RGDn_WORD1_ENDADDR) - -/*! @brief Set the ENDADDR field to a new value. */ -#define BW_MPU_RGDn_WORD1_ENDADDR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, (HW_MPU_RGDn_WORD1_RD(x, n) & ~BM_MPU_RGDn_WORD1_ENDADDR) | BF_MPU_RGDn_WORD1_ENDADDR(v))) -/*@}*/ -/******************************************************************************* - * HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 - ******************************************************************************/ - -/*! - * @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW) - * - * Reset value: 0x0061F7DFU - * - * The third word of the region descriptor defines the access control rights of - * the memory region. The access control privileges depend on two broad - * classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate - * privilege rights for user and supervisor mode accesses, as well as the optional - * inclusion of a process identification field within the definition. Bus masters - * 4-7 are limited to separate read and write permissions. For the privilege - * rights of bus masters 0-3, there are three flags associated with this function: - * Read (r) refers to accessing the referenced memory address using an operand - * (data) fetch Write (w) refers to updating the referenced memory address using a - * store (data) instruction Execute (x) refers to reading the referenced memory - * address using an instruction fetch Writes to RGDn_WORD2 clear the region - * descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write - * to RGDAACn instead because stores to these locations do not affect the - * descriptor's valid bit. - */ -typedef union _hw_mpu_rgdn_word2 -{ - uint32_t U; - struct _hw_mpu_rgdn_word2_bitfields - { - uint32_t M0UM : 3; /*!< [2:0] Bus Master 0 User Mode Access Control */ - uint32_t M0SM : 2; /*!< [4:3] Bus Master 0 Supervisor Mode Access - * Control */ - uint32_t M0PE : 1; /*!< [5] Bus Master 0 Process Identifier enable */ - uint32_t M1UM : 3; /*!< [8:6] Bus Master 1 User Mode Access Control */ - uint32_t M1SM : 2; /*!< [10:9] Bus Master 1 Supervisor Mode Access - * Control */ - uint32_t M1PE : 1; /*!< [11] Bus Master 1 Process Identifier enable */ - uint32_t M2UM : 3; /*!< [14:12] Bus Master 2 User Mode Access control - * */ - uint32_t M2SM : 2; /*!< [16:15] Bus Master 2 Supervisor Mode Access - * Control */ - uint32_t M2PE : 1; /*!< [17] Bus Master 2 Process Identifier Enable */ - uint32_t M3UM : 3; /*!< [20:18] Bus Master 3 User Mode Access Control - * */ - uint32_t M3SM : 2; /*!< [22:21] Bus Master 3 Supervisor Mode Access - * Control */ - uint32_t M3PE : 1; /*!< [23] Bus Master 3 Process Identifier Enable */ - uint32_t M4WE : 1; /*!< [24] Bus Master 4 Write Enable */ - uint32_t M4RE : 1; /*!< [25] Bus Master 4 Read Enable */ - uint32_t M5WE : 1; /*!< [26] Bus Master 5 Write Enable */ - uint32_t M5RE : 1; /*!< [27] Bus Master 5 Read Enable */ - uint32_t M6WE : 1; /*!< [28] Bus Master 6 Write Enable */ - uint32_t M6RE : 1; /*!< [29] Bus Master 6 Read Enable */ - uint32_t M7WE : 1; /*!< [30] Bus Master 7 Write Enable */ - uint32_t M7RE : 1; /*!< [31] Bus Master 7 Read Enable */ - } B; -} hw_mpu_rgdn_word2_t; - -/*! - * @name Constants and macros for entire MPU_RGDn_WORD2 register - */ -/*@{*/ -#define HW_MPU_RGDn_WORD2_COUNT (12U) - -#define HW_MPU_RGDn_WORD2_ADDR(x, n) ((x) + 0x408U + (0x10U * (n))) - -#define HW_MPU_RGDn_WORD2(x, n) (*(__IO hw_mpu_rgdn_word2_t *) HW_MPU_RGDn_WORD2_ADDR(x, n)) -#define HW_MPU_RGDn_WORD2_RD(x, n) (HW_MPU_RGDn_WORD2(x, n).U) -#define HW_MPU_RGDn_WORD2_WR(x, n, v) (HW_MPU_RGDn_WORD2(x, n).U = (v)) -#define HW_MPU_RGDn_WORD2_SET(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) | (v))) -#define HW_MPU_RGDn_WORD2_CLR(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) & ~(v))) -#define HW_MPU_RGDn_WORD2_TOG(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MPU_RGDn_WORD2 bitfields - */ - -/*! - * @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW) - * - * See M3UM description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M0UM (0U) /*!< Bit position for MPU_RGDn_WORD2_M0UM. */ -#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) /*!< Bit mask for MPU_RGDn_WORD2_M0UM. */ -#define BS_MPU_RGDn_WORD2_M0UM (3U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M0UM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M0UM field. */ -#define BR_MPU_RGDn_WORD2_M0UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M0UM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM. */ -#define BF_MPU_RGDn_WORD2_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0UM) & BM_MPU_RGDn_WORD2_M0UM) - -/*! @brief Set the M0UM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M0UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0UM) | BF_MPU_RGDn_WORD2_M0UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW) - * - * See M3SM description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M0SM (3U) /*!< Bit position for MPU_RGDn_WORD2_M0SM. */ -#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) /*!< Bit mask for MPU_RGDn_WORD2_M0SM. */ -#define BS_MPU_RGDn_WORD2_M0SM (2U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M0SM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M0SM field. */ -#define BR_MPU_RGDn_WORD2_M0SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M0SM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM. */ -#define BF_MPU_RGDn_WORD2_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0SM) & BM_MPU_RGDn_WORD2_M0SM) - -/*! @brief Set the M0SM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M0SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0SM) | BF_MPU_RGDn_WORD2_M0SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M0PE[5] (RW) - * - * See M0PE description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M0PE (5U) /*!< Bit position for MPU_RGDn_WORD2_M0PE. */ -#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) /*!< Bit mask for MPU_RGDn_WORD2_M0PE. */ -#define BS_MPU_RGDn_WORD2_M0PE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M0PE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M0PE field. */ -#define BR_MPU_RGDn_WORD2_M0PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE. */ -#define BF_MPU_RGDn_WORD2_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0PE) & BM_MPU_RGDn_WORD2_M0PE) - -/*! @brief Set the M0PE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M0PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW) - * - * See M3UM description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M1UM (6U) /*!< Bit position for MPU_RGDn_WORD2_M1UM. */ -#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) /*!< Bit mask for MPU_RGDn_WORD2_M1UM. */ -#define BS_MPU_RGDn_WORD2_M1UM (3U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M1UM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M1UM field. */ -#define BR_MPU_RGDn_WORD2_M1UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M1UM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM. */ -#define BF_MPU_RGDn_WORD2_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1UM) & BM_MPU_RGDn_WORD2_M1UM) - -/*! @brief Set the M1UM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M1UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1UM) | BF_MPU_RGDn_WORD2_M1UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW) - * - * See M3SM description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M1SM (9U) /*!< Bit position for MPU_RGDn_WORD2_M1SM. */ -#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) /*!< Bit mask for MPU_RGDn_WORD2_M1SM. */ -#define BS_MPU_RGDn_WORD2_M1SM (2U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M1SM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M1SM field. */ -#define BR_MPU_RGDn_WORD2_M1SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M1SM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM. */ -#define BF_MPU_RGDn_WORD2_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1SM) & BM_MPU_RGDn_WORD2_M1SM) - -/*! @brief Set the M1SM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M1SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1SM) | BF_MPU_RGDn_WORD2_M1SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M1PE[11] (RW) - * - * See M3PE description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M1PE (11U) /*!< Bit position for MPU_RGDn_WORD2_M1PE. */ -#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) /*!< Bit mask for MPU_RGDn_WORD2_M1PE. */ -#define BS_MPU_RGDn_WORD2_M1PE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M1PE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M1PE field. */ -#define BR_MPU_RGDn_WORD2_M1PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE. */ -#define BF_MPU_RGDn_WORD2_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1PE) & BM_MPU_RGDn_WORD2_M1PE) - -/*! @brief Set the M1PE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M1PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW) - * - * See M3UM description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M2UM (12U) /*!< Bit position for MPU_RGDn_WORD2_M2UM. */ -#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) /*!< Bit mask for MPU_RGDn_WORD2_M2UM. */ -#define BS_MPU_RGDn_WORD2_M2UM (3U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M2UM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M2UM field. */ -#define BR_MPU_RGDn_WORD2_M2UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M2UM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM. */ -#define BF_MPU_RGDn_WORD2_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2UM) & BM_MPU_RGDn_WORD2_M2UM) - -/*! @brief Set the M2UM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M2UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2UM) | BF_MPU_RGDn_WORD2_M2UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW) - * - * See M3SM description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M2SM (15U) /*!< Bit position for MPU_RGDn_WORD2_M2SM. */ -#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) /*!< Bit mask for MPU_RGDn_WORD2_M2SM. */ -#define BS_MPU_RGDn_WORD2_M2SM (2U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M2SM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M2SM field. */ -#define BR_MPU_RGDn_WORD2_M2SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M2SM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM. */ -#define BF_MPU_RGDn_WORD2_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2SM) & BM_MPU_RGDn_WORD2_M2SM) - -/*! @brief Set the M2SM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M2SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2SM) | BF_MPU_RGDn_WORD2_M2SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M2PE[17] (RW) - * - * See M3PE description. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M2PE (17U) /*!< Bit position for MPU_RGDn_WORD2_M2PE. */ -#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) /*!< Bit mask for MPU_RGDn_WORD2_M2PE. */ -#define BS_MPU_RGDn_WORD2_M2PE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M2PE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M2PE field. */ -#define BR_MPU_RGDn_WORD2_M2PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE. */ -#define BF_MPU_RGDn_WORD2_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2PE) & BM_MPU_RGDn_WORD2_M2PE) - -/*! @brief Set the M2PE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M2PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW) - * - * Defines the access controls for bus master 3 in User mode. M3UM consists of - * three independent bits, enabling read (r), write (w), and execute (x) - * permissions. - * - * Values: - * - 0 - An attempted access of that mode may be terminated with an access error - * (if not allowed by another descriptor) and the access not performed. - * - 1 - Allows the given access type to occur - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M3UM (18U) /*!< Bit position for MPU_RGDn_WORD2_M3UM. */ -#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) /*!< Bit mask for MPU_RGDn_WORD2_M3UM. */ -#define BS_MPU_RGDn_WORD2_M3UM (3U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M3UM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M3UM field. */ -#define BR_MPU_RGDn_WORD2_M3UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M3UM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM. */ -#define BF_MPU_RGDn_WORD2_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3UM) & BM_MPU_RGDn_WORD2_M3UM) - -/*! @brief Set the M3UM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M3UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3UM) | BF_MPU_RGDn_WORD2_M3UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW) - * - * Defines the access controls for bus master 3 in Supervisor mode. - * - * Values: - * - 00 - r/w/x; read, write and execute allowed - * - 01 - r/x; read and execute allowed, but no write - * - 10 - r/w; read and write allowed, but no execute - * - 11 - Same as User mode defined in M3UM - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M3SM (21U) /*!< Bit position for MPU_RGDn_WORD2_M3SM. */ -#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) /*!< Bit mask for MPU_RGDn_WORD2_M3SM. */ -#define BS_MPU_RGDn_WORD2_M3SM (2U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M3SM. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M3SM field. */ -#define BR_MPU_RGDn_WORD2_M3SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M3SM) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM. */ -#define BF_MPU_RGDn_WORD2_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3SM) & BM_MPU_RGDn_WORD2_M3SM) - -/*! @brief Set the M3SM field to a new value. */ -#define BW_MPU_RGDn_WORD2_M3SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3SM) | BF_MPU_RGDn_WORD2_M3SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M3PE[23] (RW) - * - * Values: - * - 0 - Do not include the process identifier in the evaluation - * - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit - * evaluation - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M3PE (23U) /*!< Bit position for MPU_RGDn_WORD2_M3PE. */ -#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) /*!< Bit mask for MPU_RGDn_WORD2_M3PE. */ -#define BS_MPU_RGDn_WORD2_M3PE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M3PE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M3PE field. */ -#define BR_MPU_RGDn_WORD2_M3PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE. */ -#define BF_MPU_RGDn_WORD2_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3PE) & BM_MPU_RGDn_WORD2_M3PE) - -/*! @brief Set the M3PE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M3PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M4WE[24] (RW) - * - * Values: - * - 0 - Bus master 4 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 4 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M4WE (24U) /*!< Bit position for MPU_RGDn_WORD2_M4WE. */ -#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) /*!< Bit mask for MPU_RGDn_WORD2_M4WE. */ -#define BS_MPU_RGDn_WORD2_M4WE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M4WE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M4WE field. */ -#define BR_MPU_RGDn_WORD2_M4WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE. */ -#define BF_MPU_RGDn_WORD2_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4WE) & BM_MPU_RGDn_WORD2_M4WE) - -/*! @brief Set the M4WE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M4WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M4RE[25] (RW) - * - * Values: - * - 0 - Bus master 4 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 4 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M4RE (25U) /*!< Bit position for MPU_RGDn_WORD2_M4RE. */ -#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) /*!< Bit mask for MPU_RGDn_WORD2_M4RE. */ -#define BS_MPU_RGDn_WORD2_M4RE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M4RE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M4RE field. */ -#define BR_MPU_RGDn_WORD2_M4RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE. */ -#define BF_MPU_RGDn_WORD2_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4RE) & BM_MPU_RGDn_WORD2_M4RE) - -/*! @brief Set the M4RE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M4RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M5WE[26] (RW) - * - * Values: - * - 0 - Bus master 5 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 5 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M5WE (26U) /*!< Bit position for MPU_RGDn_WORD2_M5WE. */ -#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) /*!< Bit mask for MPU_RGDn_WORD2_M5WE. */ -#define BS_MPU_RGDn_WORD2_M5WE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M5WE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M5WE field. */ -#define BR_MPU_RGDn_WORD2_M5WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE. */ -#define BF_MPU_RGDn_WORD2_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5WE) & BM_MPU_RGDn_WORD2_M5WE) - -/*! @brief Set the M5WE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M5WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M5RE[27] (RW) - * - * Values: - * - 0 - Bus master 5 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 5 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M5RE (27U) /*!< Bit position for MPU_RGDn_WORD2_M5RE. */ -#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) /*!< Bit mask for MPU_RGDn_WORD2_M5RE. */ -#define BS_MPU_RGDn_WORD2_M5RE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M5RE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M5RE field. */ -#define BR_MPU_RGDn_WORD2_M5RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE. */ -#define BF_MPU_RGDn_WORD2_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5RE) & BM_MPU_RGDn_WORD2_M5RE) - -/*! @brief Set the M5RE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M5RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M6WE[28] (RW) - * - * Values: - * - 0 - Bus master 6 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 6 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M6WE (28U) /*!< Bit position for MPU_RGDn_WORD2_M6WE. */ -#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) /*!< Bit mask for MPU_RGDn_WORD2_M6WE. */ -#define BS_MPU_RGDn_WORD2_M6WE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M6WE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M6WE field. */ -#define BR_MPU_RGDn_WORD2_M6WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE. */ -#define BF_MPU_RGDn_WORD2_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6WE) & BM_MPU_RGDn_WORD2_M6WE) - -/*! @brief Set the M6WE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M6WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M6RE[29] (RW) - * - * Values: - * - 0 - Bus master 6 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 6 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M6RE (29U) /*!< Bit position for MPU_RGDn_WORD2_M6RE. */ -#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) /*!< Bit mask for MPU_RGDn_WORD2_M6RE. */ -#define BS_MPU_RGDn_WORD2_M6RE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M6RE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M6RE field. */ -#define BR_MPU_RGDn_WORD2_M6RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE. */ -#define BF_MPU_RGDn_WORD2_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6RE) & BM_MPU_RGDn_WORD2_M6RE) - -/*! @brief Set the M6RE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M6RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M7WE[30] (RW) - * - * Values: - * - 0 - Bus master 7 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 7 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M7WE (30U) /*!< Bit position for MPU_RGDn_WORD2_M7WE. */ -#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) /*!< Bit mask for MPU_RGDn_WORD2_M7WE. */ -#define BS_MPU_RGDn_WORD2_M7WE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M7WE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M7WE field. */ -#define BR_MPU_RGDn_WORD2_M7WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE. */ -#define BF_MPU_RGDn_WORD2_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7WE) & BM_MPU_RGDn_WORD2_M7WE) - -/*! @brief Set the M7WE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M7WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD2, field M7RE[31] (RW) - * - * Values: - * - 0 - Bus master 7 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 7 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDn_WORD2_M7RE (31U) /*!< Bit position for MPU_RGDn_WORD2_M7RE. */ -#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) /*!< Bit mask for MPU_RGDn_WORD2_M7RE. */ -#define BS_MPU_RGDn_WORD2_M7RE (1U) /*!< Bit field size in bits for MPU_RGDn_WORD2_M7RE. */ - -/*! @brief Read current value of the MPU_RGDn_WORD2_M7RE field. */ -#define BR_MPU_RGDn_WORD2_M7RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE. */ -#define BF_MPU_RGDn_WORD2_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7RE) & BM_MPU_RGDn_WORD2_M7RE) - -/*! @brief Set the M7RE field to a new value. */ -#define BW_MPU_RGDn_WORD2_M7RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE) = (v)) -/*@}*/ -/******************************************************************************* - * HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 - ******************************************************************************/ - -/*! - * @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW) - * - * Reset value: 0x00000001U - * - * The fourth word of the region descriptor contains the optional process - * identifier and mask, plus the region descriptor's valid bit. - */ -typedef union _hw_mpu_rgdn_word3 -{ - uint32_t U; - struct _hw_mpu_rgdn_word3_bitfields - { - uint32_t VLD : 1; /*!< [0] Valid */ - uint32_t RESERVED0 : 15; /*!< [15:1] */ - uint32_t PIDMASK : 8; /*!< [23:16] Process Identifier Mask */ - uint32_t PID : 8; /*!< [31:24] Process Identifier */ - } B; -} hw_mpu_rgdn_word3_t; - -/*! - * @name Constants and macros for entire MPU_RGDn_WORD3 register - */ -/*@{*/ -#define HW_MPU_RGDn_WORD3_COUNT (12U) - -#define HW_MPU_RGDn_WORD3_ADDR(x, n) ((x) + 0x40CU + (0x10U * (n))) - -#define HW_MPU_RGDn_WORD3(x, n) (*(__IO hw_mpu_rgdn_word3_t *) HW_MPU_RGDn_WORD3_ADDR(x, n)) -#define HW_MPU_RGDn_WORD3_RD(x, n) (HW_MPU_RGDn_WORD3(x, n).U) -#define HW_MPU_RGDn_WORD3_WR(x, n, v) (HW_MPU_RGDn_WORD3(x, n).U = (v)) -#define HW_MPU_RGDn_WORD3_SET(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) | (v))) -#define HW_MPU_RGDn_WORD3_CLR(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) & ~(v))) -#define HW_MPU_RGDn_WORD3_TOG(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MPU_RGDn_WORD3 bitfields - */ - -/*! - * @name Register MPU_RGDn_WORD3, field VLD[0] (RW) - * - * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this - * bit. - * - * Values: - * - 0 - Region descriptor is invalid - * - 1 - Region descriptor is valid - */ -/*@{*/ -#define BP_MPU_RGDn_WORD3_VLD (0U) /*!< Bit position for MPU_RGDn_WORD3_VLD. */ -#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) /*!< Bit mask for MPU_RGDn_WORD3_VLD. */ -#define BS_MPU_RGDn_WORD3_VLD (1U) /*!< Bit field size in bits for MPU_RGDn_WORD3_VLD. */ - -/*! @brief Read current value of the MPU_RGDn_WORD3_VLD field. */ -#define BR_MPU_RGDn_WORD3_VLD(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD)) - -/*! @brief Format value for bitfield MPU_RGDn_WORD3_VLD. */ -#define BF_MPU_RGDn_WORD3_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_VLD) & BM_MPU_RGDn_WORD3_VLD) - -/*! @brief Set the VLD field to a new value. */ -#define BW_MPU_RGDn_WORD3_VLD(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW) - * - * Provides a masking capability so that multiple process identifiers can be - * included as part of the region hit determination. If a bit in PIDMASK is set, - * then the corresponding PID bit is ignored in the comparison. This field and PID - * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For - * more information on the handling of the PID and PIDMASK, see "Access Evaluation - * - Hit Determination." - */ -/*@{*/ -#define BP_MPU_RGDn_WORD3_PIDMASK (16U) /*!< Bit position for MPU_RGDn_WORD3_PIDMASK. */ -#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) /*!< Bit mask for MPU_RGDn_WORD3_PIDMASK. */ -#define BS_MPU_RGDn_WORD3_PIDMASK (8U) /*!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK. */ - -/*! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field. */ -#define BR_MPU_RGDn_WORD3_PIDMASK(x, n) (HW_MPU_RGDn_WORD3(x, n).B.PIDMASK) - -/*! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK. */ -#define BF_MPU_RGDn_WORD3_PIDMASK(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PIDMASK) & BM_MPU_RGDn_WORD3_PIDMASK) - -/*! @brief Set the PIDMASK field to a new value. */ -#define BW_MPU_RGDn_WORD3_PIDMASK(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PIDMASK) | BF_MPU_RGDn_WORD3_PIDMASK(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDn_WORD3, field PID[31:24] (RW) - * - * Specifies the process identifier that is included in the region hit - * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this - * field. - */ -/*@{*/ -#define BP_MPU_RGDn_WORD3_PID (24U) /*!< Bit position for MPU_RGDn_WORD3_PID. */ -#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) /*!< Bit mask for MPU_RGDn_WORD3_PID. */ -#define BS_MPU_RGDn_WORD3_PID (8U) /*!< Bit field size in bits for MPU_RGDn_WORD3_PID. */ - -/*! @brief Read current value of the MPU_RGDn_WORD3_PID field. */ -#define BR_MPU_RGDn_WORD3_PID(x, n) (HW_MPU_RGDn_WORD3(x, n).B.PID) - -/*! @brief Format value for bitfield MPU_RGDn_WORD3_PID. */ -#define BF_MPU_RGDn_WORD3_PID(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PID) & BM_MPU_RGDn_WORD3_PID) - -/*! @brief Set the PID field to a new value. */ -#define BW_MPU_RGDn_WORD3_PID(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PID) | BF_MPU_RGDn_WORD3_PID(v))) -/*@}*/ - -/******************************************************************************* - * HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n - ******************************************************************************/ - -/*! - * @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW) - * - * Reset value: 0x0061F7DFU - * - * Because software may adjust only the access controls within a region - * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of - * this 32-bit entity is available. Writing to this register does not affect the - * descriptor's valid bit. - */ -typedef union _hw_mpu_rgdaacn -{ - uint32_t U; - struct _hw_mpu_rgdaacn_bitfields - { - uint32_t M0UM : 3; /*!< [2:0] Bus Master 0 User Mode Access Control */ - uint32_t M0SM : 2; /*!< [4:3] Bus Master 0 Supervisor Mode Access - * Control */ - uint32_t M0PE : 1; /*!< [5] Bus Master 0 Process Identifier Enable */ - uint32_t M1UM : 3; /*!< [8:6] Bus Master 1 User Mode Access Control */ - uint32_t M1SM : 2; /*!< [10:9] Bus Master 1 Supervisor Mode Access - * Control */ - uint32_t M1PE : 1; /*!< [11] Bus Master 1 Process Identifier Enable */ - uint32_t M2UM : 3; /*!< [14:12] Bus Master 2 User Mode Access Control - * */ - uint32_t M2SM : 2; /*!< [16:15] Bus Master 2 Supervisor Mode Access - * Control */ - uint32_t M2PE : 1; /*!< [17] Bus Master 2 Process Identifier Enable */ - uint32_t M3UM : 3; /*!< [20:18] Bus Master 3 User Mode Access Control - * */ - uint32_t M3SM : 2; /*!< [22:21] Bus Master 3 Supervisor Mode Access - * Control */ - uint32_t M3PE : 1; /*!< [23] Bus Master 3 Process Identifier Enable */ - uint32_t M4WE : 1; /*!< [24] Bus Master 4 Write Enable */ - uint32_t M4RE : 1; /*!< [25] Bus Master 4 Read Enable */ - uint32_t M5WE : 1; /*!< [26] Bus Master 5 Write Enable */ - uint32_t M5RE : 1; /*!< [27] Bus Master 5 Read Enable */ - uint32_t M6WE : 1; /*!< [28] Bus Master 6 Write Enable */ - uint32_t M6RE : 1; /*!< [29] Bus Master 6 Read Enable */ - uint32_t M7WE : 1; /*!< [30] Bus Master 7 Write Enable */ - uint32_t M7RE : 1; /*!< [31] Bus Master 7 Read Enable */ - } B; -} hw_mpu_rgdaacn_t; - -/*! - * @name Constants and macros for entire MPU_RGDAACn register - */ -/*@{*/ -#define HW_MPU_RGDAACn_COUNT (12U) - -#define HW_MPU_RGDAACn_ADDR(x, n) ((x) + 0x800U + (0x4U * (n))) - -#define HW_MPU_RGDAACn(x, n) (*(__IO hw_mpu_rgdaacn_t *) HW_MPU_RGDAACn_ADDR(x, n)) -#define HW_MPU_RGDAACn_RD(x, n) (HW_MPU_RGDAACn(x, n).U) -#define HW_MPU_RGDAACn_WR(x, n, v) (HW_MPU_RGDAACn(x, n).U = (v)) -#define HW_MPU_RGDAACn_SET(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) | (v))) -#define HW_MPU_RGDAACn_CLR(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) & ~(v))) -#define HW_MPU_RGDAACn_TOG(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual MPU_RGDAACn bitfields - */ - -/*! - * @name Register MPU_RGDAACn, field M0UM[2:0] (RW) - * - * See M3UM description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M0UM (0U) /*!< Bit position for MPU_RGDAACn_M0UM. */ -#define BM_MPU_RGDAACn_M0UM (0x00000007U) /*!< Bit mask for MPU_RGDAACn_M0UM. */ -#define BS_MPU_RGDAACn_M0UM (3U) /*!< Bit field size in bits for MPU_RGDAACn_M0UM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M0UM field. */ -#define BR_MPU_RGDAACn_M0UM(x, n) (HW_MPU_RGDAACn(x, n).B.M0UM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M0UM. */ -#define BF_MPU_RGDAACn_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0UM) & BM_MPU_RGDAACn_M0UM) - -/*! @brief Set the M0UM field to a new value. */ -#define BW_MPU_RGDAACn_M0UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0UM) | BF_MPU_RGDAACn_M0UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M0SM[4:3] (RW) - * - * See M3SM description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M0SM (3U) /*!< Bit position for MPU_RGDAACn_M0SM. */ -#define BM_MPU_RGDAACn_M0SM (0x00000018U) /*!< Bit mask for MPU_RGDAACn_M0SM. */ -#define BS_MPU_RGDAACn_M0SM (2U) /*!< Bit field size in bits for MPU_RGDAACn_M0SM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M0SM field. */ -#define BR_MPU_RGDAACn_M0SM(x, n) (HW_MPU_RGDAACn(x, n).B.M0SM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M0SM. */ -#define BF_MPU_RGDAACn_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0SM) & BM_MPU_RGDAACn_M0SM) - -/*! @brief Set the M0SM field to a new value. */ -#define BW_MPU_RGDAACn_M0SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0SM) | BF_MPU_RGDAACn_M0SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M0PE[5] (RW) - * - * See M3PE description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M0PE (5U) /*!< Bit position for MPU_RGDAACn_M0PE. */ -#define BM_MPU_RGDAACn_M0PE (0x00000020U) /*!< Bit mask for MPU_RGDAACn_M0PE. */ -#define BS_MPU_RGDAACn_M0PE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M0PE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M0PE field. */ -#define BR_MPU_RGDAACn_M0PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M0PE. */ -#define BF_MPU_RGDAACn_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0PE) & BM_MPU_RGDAACn_M0PE) - -/*! @brief Set the M0PE field to a new value. */ -#define BW_MPU_RGDAACn_M0PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M1UM[8:6] (RW) - * - * See M3UM description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M1UM (6U) /*!< Bit position for MPU_RGDAACn_M1UM. */ -#define BM_MPU_RGDAACn_M1UM (0x000001C0U) /*!< Bit mask for MPU_RGDAACn_M1UM. */ -#define BS_MPU_RGDAACn_M1UM (3U) /*!< Bit field size in bits for MPU_RGDAACn_M1UM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M1UM field. */ -#define BR_MPU_RGDAACn_M1UM(x, n) (HW_MPU_RGDAACn(x, n).B.M1UM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M1UM. */ -#define BF_MPU_RGDAACn_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1UM) & BM_MPU_RGDAACn_M1UM) - -/*! @brief Set the M1UM field to a new value. */ -#define BW_MPU_RGDAACn_M1UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1UM) | BF_MPU_RGDAACn_M1UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M1SM[10:9] (RW) - * - * See M3SM description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M1SM (9U) /*!< Bit position for MPU_RGDAACn_M1SM. */ -#define BM_MPU_RGDAACn_M1SM (0x00000600U) /*!< Bit mask for MPU_RGDAACn_M1SM. */ -#define BS_MPU_RGDAACn_M1SM (2U) /*!< Bit field size in bits for MPU_RGDAACn_M1SM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M1SM field. */ -#define BR_MPU_RGDAACn_M1SM(x, n) (HW_MPU_RGDAACn(x, n).B.M1SM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M1SM. */ -#define BF_MPU_RGDAACn_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1SM) & BM_MPU_RGDAACn_M1SM) - -/*! @brief Set the M1SM field to a new value. */ -#define BW_MPU_RGDAACn_M1SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1SM) | BF_MPU_RGDAACn_M1SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M1PE[11] (RW) - * - * See M3PE description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M1PE (11U) /*!< Bit position for MPU_RGDAACn_M1PE. */ -#define BM_MPU_RGDAACn_M1PE (0x00000800U) /*!< Bit mask for MPU_RGDAACn_M1PE. */ -#define BS_MPU_RGDAACn_M1PE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M1PE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M1PE field. */ -#define BR_MPU_RGDAACn_M1PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M1PE. */ -#define BF_MPU_RGDAACn_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1PE) & BM_MPU_RGDAACn_M1PE) - -/*! @brief Set the M1PE field to a new value. */ -#define BW_MPU_RGDAACn_M1PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M2UM[14:12] (RW) - * - * See M3UM description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M2UM (12U) /*!< Bit position for MPU_RGDAACn_M2UM. */ -#define BM_MPU_RGDAACn_M2UM (0x00007000U) /*!< Bit mask for MPU_RGDAACn_M2UM. */ -#define BS_MPU_RGDAACn_M2UM (3U) /*!< Bit field size in bits for MPU_RGDAACn_M2UM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M2UM field. */ -#define BR_MPU_RGDAACn_M2UM(x, n) (HW_MPU_RGDAACn(x, n).B.M2UM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M2UM. */ -#define BF_MPU_RGDAACn_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2UM) & BM_MPU_RGDAACn_M2UM) - -/*! @brief Set the M2UM field to a new value. */ -#define BW_MPU_RGDAACn_M2UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2UM) | BF_MPU_RGDAACn_M2UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M2SM[16:15] (RW) - * - * See M3SM description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M2SM (15U) /*!< Bit position for MPU_RGDAACn_M2SM. */ -#define BM_MPU_RGDAACn_M2SM (0x00018000U) /*!< Bit mask for MPU_RGDAACn_M2SM. */ -#define BS_MPU_RGDAACn_M2SM (2U) /*!< Bit field size in bits for MPU_RGDAACn_M2SM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M2SM field. */ -#define BR_MPU_RGDAACn_M2SM(x, n) (HW_MPU_RGDAACn(x, n).B.M2SM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M2SM. */ -#define BF_MPU_RGDAACn_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2SM) & BM_MPU_RGDAACn_M2SM) - -/*! @brief Set the M2SM field to a new value. */ -#define BW_MPU_RGDAACn_M2SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2SM) | BF_MPU_RGDAACn_M2SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M2PE[17] (RW) - * - * See M3PE description. - */ -/*@{*/ -#define BP_MPU_RGDAACn_M2PE (17U) /*!< Bit position for MPU_RGDAACn_M2PE. */ -#define BM_MPU_RGDAACn_M2PE (0x00020000U) /*!< Bit mask for MPU_RGDAACn_M2PE. */ -#define BS_MPU_RGDAACn_M2PE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M2PE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M2PE field. */ -#define BR_MPU_RGDAACn_M2PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M2PE. */ -#define BF_MPU_RGDAACn_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2PE) & BM_MPU_RGDAACn_M2PE) - -/*! @brief Set the M2PE field to a new value. */ -#define BW_MPU_RGDAACn_M2PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M3UM[20:18] (RW) - * - * Defines the access controls for bus master 3 in user mode. M3UM consists of - * three independent bits, enabling read (r), write (w), and execute (x) - * permissions. - * - * Values: - * - 0 - An attempted access of that mode may be terminated with an access error - * (if not allowed by another descriptor) and the access not performed. - * - 1 - Allows the given access type to occur - */ -/*@{*/ -#define BP_MPU_RGDAACn_M3UM (18U) /*!< Bit position for MPU_RGDAACn_M3UM. */ -#define BM_MPU_RGDAACn_M3UM (0x001C0000U) /*!< Bit mask for MPU_RGDAACn_M3UM. */ -#define BS_MPU_RGDAACn_M3UM (3U) /*!< Bit field size in bits for MPU_RGDAACn_M3UM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M3UM field. */ -#define BR_MPU_RGDAACn_M3UM(x, n) (HW_MPU_RGDAACn(x, n).B.M3UM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M3UM. */ -#define BF_MPU_RGDAACn_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3UM) & BM_MPU_RGDAACn_M3UM) - -/*! @brief Set the M3UM field to a new value. */ -#define BW_MPU_RGDAACn_M3UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3UM) | BF_MPU_RGDAACn_M3UM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M3SM[22:21] (RW) - * - * Defines the access controls for bus master 3 in Supervisor mode. - * - * Values: - * - 00 - r/w/x; read, write and execute allowed - * - 01 - r/x; read and execute allowed, but no write - * - 10 - r/w; read and write allowed, but no execute - * - 11 - Same as User mode defined in M3UM - */ -/*@{*/ -#define BP_MPU_RGDAACn_M3SM (21U) /*!< Bit position for MPU_RGDAACn_M3SM. */ -#define BM_MPU_RGDAACn_M3SM (0x00600000U) /*!< Bit mask for MPU_RGDAACn_M3SM. */ -#define BS_MPU_RGDAACn_M3SM (2U) /*!< Bit field size in bits for MPU_RGDAACn_M3SM. */ - -/*! @brief Read current value of the MPU_RGDAACn_M3SM field. */ -#define BR_MPU_RGDAACn_M3SM(x, n) (HW_MPU_RGDAACn(x, n).B.M3SM) - -/*! @brief Format value for bitfield MPU_RGDAACn_M3SM. */ -#define BF_MPU_RGDAACn_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3SM) & BM_MPU_RGDAACn_M3SM) - -/*! @brief Set the M3SM field to a new value. */ -#define BW_MPU_RGDAACn_M3SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3SM) | BF_MPU_RGDAACn_M3SM(v))) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M3PE[23] (RW) - * - * Values: - * - 0 - Do not include the process identifier in the evaluation - * - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit - * evaluation - */ -/*@{*/ -#define BP_MPU_RGDAACn_M3PE (23U) /*!< Bit position for MPU_RGDAACn_M3PE. */ -#define BM_MPU_RGDAACn_M3PE (0x00800000U) /*!< Bit mask for MPU_RGDAACn_M3PE. */ -#define BS_MPU_RGDAACn_M3PE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M3PE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M3PE field. */ -#define BR_MPU_RGDAACn_M3PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M3PE. */ -#define BF_MPU_RGDAACn_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3PE) & BM_MPU_RGDAACn_M3PE) - -/*! @brief Set the M3PE field to a new value. */ -#define BW_MPU_RGDAACn_M3PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M4WE[24] (RW) - * - * Values: - * - 0 - Bus master 4 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 4 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M4WE (24U) /*!< Bit position for MPU_RGDAACn_M4WE. */ -#define BM_MPU_RGDAACn_M4WE (0x01000000U) /*!< Bit mask for MPU_RGDAACn_M4WE. */ -#define BS_MPU_RGDAACn_M4WE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M4WE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M4WE field. */ -#define BR_MPU_RGDAACn_M4WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M4WE. */ -#define BF_MPU_RGDAACn_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4WE) & BM_MPU_RGDAACn_M4WE) - -/*! @brief Set the M4WE field to a new value. */ -#define BW_MPU_RGDAACn_M4WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M4RE[25] (RW) - * - * Values: - * - 0 - Bus master 4 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 4 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M4RE (25U) /*!< Bit position for MPU_RGDAACn_M4RE. */ -#define BM_MPU_RGDAACn_M4RE (0x02000000U) /*!< Bit mask for MPU_RGDAACn_M4RE. */ -#define BS_MPU_RGDAACn_M4RE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M4RE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M4RE field. */ -#define BR_MPU_RGDAACn_M4RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M4RE. */ -#define BF_MPU_RGDAACn_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4RE) & BM_MPU_RGDAACn_M4RE) - -/*! @brief Set the M4RE field to a new value. */ -#define BW_MPU_RGDAACn_M4RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M5WE[26] (RW) - * - * Values: - * - 0 - Bus master 5 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 5 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M5WE (26U) /*!< Bit position for MPU_RGDAACn_M5WE. */ -#define BM_MPU_RGDAACn_M5WE (0x04000000U) /*!< Bit mask for MPU_RGDAACn_M5WE. */ -#define BS_MPU_RGDAACn_M5WE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M5WE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M5WE field. */ -#define BR_MPU_RGDAACn_M5WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M5WE. */ -#define BF_MPU_RGDAACn_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5WE) & BM_MPU_RGDAACn_M5WE) - -/*! @brief Set the M5WE field to a new value. */ -#define BW_MPU_RGDAACn_M5WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M5RE[27] (RW) - * - * Values: - * - 0 - Bus master 5 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 5 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M5RE (27U) /*!< Bit position for MPU_RGDAACn_M5RE. */ -#define BM_MPU_RGDAACn_M5RE (0x08000000U) /*!< Bit mask for MPU_RGDAACn_M5RE. */ -#define BS_MPU_RGDAACn_M5RE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M5RE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M5RE field. */ -#define BR_MPU_RGDAACn_M5RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M5RE. */ -#define BF_MPU_RGDAACn_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5RE) & BM_MPU_RGDAACn_M5RE) - -/*! @brief Set the M5RE field to a new value. */ -#define BW_MPU_RGDAACn_M5RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M6WE[28] (RW) - * - * Values: - * - 0 - Bus master 6 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 6 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M6WE (28U) /*!< Bit position for MPU_RGDAACn_M6WE. */ -#define BM_MPU_RGDAACn_M6WE (0x10000000U) /*!< Bit mask for MPU_RGDAACn_M6WE. */ -#define BS_MPU_RGDAACn_M6WE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M6WE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M6WE field. */ -#define BR_MPU_RGDAACn_M6WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M6WE. */ -#define BF_MPU_RGDAACn_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6WE) & BM_MPU_RGDAACn_M6WE) - -/*! @brief Set the M6WE field to a new value. */ -#define BW_MPU_RGDAACn_M6WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M6RE[29] (RW) - * - * Values: - * - 0 - Bus master 6 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 6 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M6RE (29U) /*!< Bit position for MPU_RGDAACn_M6RE. */ -#define BM_MPU_RGDAACn_M6RE (0x20000000U) /*!< Bit mask for MPU_RGDAACn_M6RE. */ -#define BS_MPU_RGDAACn_M6RE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M6RE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M6RE field. */ -#define BR_MPU_RGDAACn_M6RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M6RE. */ -#define BF_MPU_RGDAACn_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6RE) & BM_MPU_RGDAACn_M6RE) - -/*! @brief Set the M6RE field to a new value. */ -#define BW_MPU_RGDAACn_M6RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M7WE[30] (RW) - * - * Values: - * - 0 - Bus master 7 writes terminate with an access error and the write is not - * performed - * - 1 - Bus master 7 writes allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M7WE (30U) /*!< Bit position for MPU_RGDAACn_M7WE. */ -#define BM_MPU_RGDAACn_M7WE (0x40000000U) /*!< Bit mask for MPU_RGDAACn_M7WE. */ -#define BS_MPU_RGDAACn_M7WE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M7WE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M7WE field. */ -#define BR_MPU_RGDAACn_M7WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M7WE. */ -#define BF_MPU_RGDAACn_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7WE) & BM_MPU_RGDAACn_M7WE) - -/*! @brief Set the M7WE field to a new value. */ -#define BW_MPU_RGDAACn_M7WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE) = (v)) -/*@}*/ - -/*! - * @name Register MPU_RGDAACn, field M7RE[31] (RW) - * - * Values: - * - 0 - Bus master 7 reads terminate with an access error and the read is not - * performed - * - 1 - Bus master 7 reads allowed - */ -/*@{*/ -#define BP_MPU_RGDAACn_M7RE (31U) /*!< Bit position for MPU_RGDAACn_M7RE. */ -#define BM_MPU_RGDAACn_M7RE (0x80000000U) /*!< Bit mask for MPU_RGDAACn_M7RE. */ -#define BS_MPU_RGDAACn_M7RE (1U) /*!< Bit field size in bits for MPU_RGDAACn_M7RE. */ - -/*! @brief Read current value of the MPU_RGDAACn_M7RE field. */ -#define BR_MPU_RGDAACn_M7RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE)) - -/*! @brief Format value for bitfield MPU_RGDAACn_M7RE. */ -#define BF_MPU_RGDAACn_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7RE) & BM_MPU_RGDAACn_M7RE) - -/*! @brief Set the M7RE field to a new value. */ -#define BW_MPU_RGDAACn_M7RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_mpu_t - module struct - ******************************************************************************/ -/*! - * @brief All MPU module registers. - */ -#pragma pack(1) -typedef struct _hw_mpu -{ - __IO hw_mpu_cesr_t CESR; /*!< [0x0] Control/Error Status Register */ - uint8_t _reserved0[12]; - struct { - __I hw_mpu_earn_t EARn; /*!< [0x10] Error Address Register, slave port n */ - __I hw_mpu_edrn_t EDRn; /*!< [0x14] Error Detail Register, slave port n */ - } SP[5]; - uint8_t _reserved1[968]; - struct { - __IO hw_mpu_rgdn_word0_t RGDn_WORD0; /*!< [0x400] Region Descriptor n, Word 0 */ - __IO hw_mpu_rgdn_word1_t RGDn_WORD1; /*!< [0x404] Region Descriptor n, Word 1 */ - __IO hw_mpu_rgdn_word2_t RGDn_WORD2; /*!< [0x408] Region Descriptor n, Word 2 */ - __IO hw_mpu_rgdn_word3_t RGDn_WORD3; /*!< [0x40C] Region Descriptor n, Word 3 */ - } RGD[12]; - uint8_t _reserved2[832]; - __IO hw_mpu_rgdaacn_t RGDAACn[12]; /*!< [0x800] Region Descriptor Alternate Access Control n */ -} hw_mpu_t; -#pragma pack() - -/*! @brief Macro to access all MPU registers. */ -/*! @param x MPU module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_MPU(MPU_BASE). */ -#define HW_MPU(x) (*(hw_mpu_t *)(x)) - -#endif /* __HW_MPU_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_nv.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_nv.h deleted file mode 100644 index 400dc73044b..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_nv.h +++ /dev/null @@ -1,929 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_NV_REGISTERS_H__ -#define __HW_NV_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 NV - * - * Flash configuration field - * - * Registers defined in this header file: - * - HW_NV_BACKKEY3 - Backdoor Comparison Key 3. - * - HW_NV_BACKKEY2 - Backdoor Comparison Key 2. - * - HW_NV_BACKKEY1 - Backdoor Comparison Key 1. - * - HW_NV_BACKKEY0 - Backdoor Comparison Key 0. - * - HW_NV_BACKKEY7 - Backdoor Comparison Key 7. - * - HW_NV_BACKKEY6 - Backdoor Comparison Key 6. - * - HW_NV_BACKKEY5 - Backdoor Comparison Key 5. - * - HW_NV_BACKKEY4 - Backdoor Comparison Key 4. - * - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register - * - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register - * - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register - * - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register - * - HW_NV_FSEC - Non-volatile Flash Security Register - * - HW_NV_FOPT - Non-volatile Flash Option Register - * - HW_NV_FEPROT - Non-volatile EERAM Protection Register - * - HW_NV_FDPROT - Non-volatile D-Flash Protection Register - * - * - hw_nv_t - Struct containing all module registers. - */ - -#define HW_NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */ - -/******************************************************************************* - * HW_NV_BACKKEY3 - Backdoor Comparison Key 3. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey3 -{ - uint8_t U; - struct _hw_nv_backkey3_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey3_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY3 register - */ -/*@{*/ -#define HW_NV_BACKKEY3_ADDR(x) ((x) + 0x0U) - -#define HW_NV_BACKKEY3(x) (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR(x)) -#define HW_NV_BACKKEY3_RD(x) (HW_NV_BACKKEY3(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY3 bitfields - */ - -/*! - * @name Register NV_BACKKEY3, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY3_KEY (0U) /*!< Bit position for NV_BACKKEY3_KEY. */ -#define BM_NV_BACKKEY3_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY3_KEY. */ -#define BS_NV_BACKKEY3_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY3_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY3_KEY field. */ -#define BR_NV_BACKKEY3_KEY(x) (HW_NV_BACKKEY3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY2 - Backdoor Comparison Key 2. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey2 -{ - uint8_t U; - struct _hw_nv_backkey2_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey2_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY2 register - */ -/*@{*/ -#define HW_NV_BACKKEY2_ADDR(x) ((x) + 0x1U) - -#define HW_NV_BACKKEY2(x) (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR(x)) -#define HW_NV_BACKKEY2_RD(x) (HW_NV_BACKKEY2(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY2 bitfields - */ - -/*! - * @name Register NV_BACKKEY2, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY2_KEY (0U) /*!< Bit position for NV_BACKKEY2_KEY. */ -#define BM_NV_BACKKEY2_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY2_KEY. */ -#define BS_NV_BACKKEY2_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY2_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY2_KEY field. */ -#define BR_NV_BACKKEY2_KEY(x) (HW_NV_BACKKEY2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY1 - Backdoor Comparison Key 1. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey1 -{ - uint8_t U; - struct _hw_nv_backkey1_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey1_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY1 register - */ -/*@{*/ -#define HW_NV_BACKKEY1_ADDR(x) ((x) + 0x2U) - -#define HW_NV_BACKKEY1(x) (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR(x)) -#define HW_NV_BACKKEY1_RD(x) (HW_NV_BACKKEY1(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY1 bitfields - */ - -/*! - * @name Register NV_BACKKEY1, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY1_KEY (0U) /*!< Bit position for NV_BACKKEY1_KEY. */ -#define BM_NV_BACKKEY1_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY1_KEY. */ -#define BS_NV_BACKKEY1_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY1_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY1_KEY field. */ -#define BR_NV_BACKKEY1_KEY(x) (HW_NV_BACKKEY1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY0 - Backdoor Comparison Key 0. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey0 -{ - uint8_t U; - struct _hw_nv_backkey0_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey0_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY0 register - */ -/*@{*/ -#define HW_NV_BACKKEY0_ADDR(x) ((x) + 0x3U) - -#define HW_NV_BACKKEY0(x) (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR(x)) -#define HW_NV_BACKKEY0_RD(x) (HW_NV_BACKKEY0(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY0 bitfields - */ - -/*! - * @name Register NV_BACKKEY0, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY0_KEY (0U) /*!< Bit position for NV_BACKKEY0_KEY. */ -#define BM_NV_BACKKEY0_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY0_KEY. */ -#define BS_NV_BACKKEY0_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY0_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY0_KEY field. */ -#define BR_NV_BACKKEY0_KEY(x) (HW_NV_BACKKEY0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY7 - Backdoor Comparison Key 7. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey7 -{ - uint8_t U; - struct _hw_nv_backkey7_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey7_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY7 register - */ -/*@{*/ -#define HW_NV_BACKKEY7_ADDR(x) ((x) + 0x4U) - -#define HW_NV_BACKKEY7(x) (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR(x)) -#define HW_NV_BACKKEY7_RD(x) (HW_NV_BACKKEY7(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY7 bitfields - */ - -/*! - * @name Register NV_BACKKEY7, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY7_KEY (0U) /*!< Bit position for NV_BACKKEY7_KEY. */ -#define BM_NV_BACKKEY7_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY7_KEY. */ -#define BS_NV_BACKKEY7_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY7_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY7_KEY field. */ -#define BR_NV_BACKKEY7_KEY(x) (HW_NV_BACKKEY7(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY6 - Backdoor Comparison Key 6. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey6 -{ - uint8_t U; - struct _hw_nv_backkey6_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey6_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY6 register - */ -/*@{*/ -#define HW_NV_BACKKEY6_ADDR(x) ((x) + 0x5U) - -#define HW_NV_BACKKEY6(x) (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR(x)) -#define HW_NV_BACKKEY6_RD(x) (HW_NV_BACKKEY6(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY6 bitfields - */ - -/*! - * @name Register NV_BACKKEY6, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY6_KEY (0U) /*!< Bit position for NV_BACKKEY6_KEY. */ -#define BM_NV_BACKKEY6_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY6_KEY. */ -#define BS_NV_BACKKEY6_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY6_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY6_KEY field. */ -#define BR_NV_BACKKEY6_KEY(x) (HW_NV_BACKKEY6(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY5 - Backdoor Comparison Key 5. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey5 -{ - uint8_t U; - struct _hw_nv_backkey5_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey5_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY5 register - */ -/*@{*/ -#define HW_NV_BACKKEY5_ADDR(x) ((x) + 0x6U) - -#define HW_NV_BACKKEY5(x) (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR(x)) -#define HW_NV_BACKKEY5_RD(x) (HW_NV_BACKKEY5(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY5 bitfields - */ - -/*! - * @name Register NV_BACKKEY5, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY5_KEY (0U) /*!< Bit position for NV_BACKKEY5_KEY. */ -#define BM_NV_BACKKEY5_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY5_KEY. */ -#define BS_NV_BACKKEY5_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY5_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY5_KEY field. */ -#define BR_NV_BACKKEY5_KEY(x) (HW_NV_BACKKEY5(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_BACKKEY4 - Backdoor Comparison Key 4. - ******************************************************************************/ - -/*! - * @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_backkey4 -{ - uint8_t U; - struct _hw_nv_backkey4_bitfields - { - uint8_t KEY : 8; /*!< [7:0] Backdoor Comparison Key. */ - } B; -} hw_nv_backkey4_t; - -/*! - * @name Constants and macros for entire NV_BACKKEY4 register - */ -/*@{*/ -#define HW_NV_BACKKEY4_ADDR(x) ((x) + 0x7U) - -#define HW_NV_BACKKEY4(x) (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR(x)) -#define HW_NV_BACKKEY4_RD(x) (HW_NV_BACKKEY4(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_BACKKEY4 bitfields - */ - -/*! - * @name Register NV_BACKKEY4, field KEY[7:0] (RO) - */ -/*@{*/ -#define BP_NV_BACKKEY4_KEY (0U) /*!< Bit position for NV_BACKKEY4_KEY. */ -#define BM_NV_BACKKEY4_KEY (0xFFU) /*!< Bit mask for NV_BACKKEY4_KEY. */ -#define BS_NV_BACKKEY4_KEY (8U) /*!< Bit field size in bits for NV_BACKKEY4_KEY. */ - -/*! @brief Read current value of the NV_BACKKEY4_KEY field. */ -#define BR_NV_BACKKEY4_KEY(x) (HW_NV_BACKKEY4(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot3 -{ - uint8_t U; - struct _hw_nv_fprot3_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot3_t; - -/*! - * @name Constants and macros for entire NV_FPROT3 register - */ -/*@{*/ -#define HW_NV_FPROT3_ADDR(x) ((x) + 0x8U) - -#define HW_NV_FPROT3(x) (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR(x)) -#define HW_NV_FPROT3_RD(x) (HW_NV_FPROT3(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT3 bitfields - */ - -/*! - * @name Register NV_FPROT3, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT3_PROT (0U) /*!< Bit position for NV_FPROT3_PROT. */ -#define BM_NV_FPROT3_PROT (0xFFU) /*!< Bit mask for NV_FPROT3_PROT. */ -#define BS_NV_FPROT3_PROT (8U) /*!< Bit field size in bits for NV_FPROT3_PROT. */ - -/*! @brief Read current value of the NV_FPROT3_PROT field. */ -#define BR_NV_FPROT3_PROT(x) (HW_NV_FPROT3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot2 -{ - uint8_t U; - struct _hw_nv_fprot2_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot2_t; - -/*! - * @name Constants and macros for entire NV_FPROT2 register - */ -/*@{*/ -#define HW_NV_FPROT2_ADDR(x) ((x) + 0x9U) - -#define HW_NV_FPROT2(x) (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR(x)) -#define HW_NV_FPROT2_RD(x) (HW_NV_FPROT2(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT2 bitfields - */ - -/*! - * @name Register NV_FPROT2, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT2_PROT (0U) /*!< Bit position for NV_FPROT2_PROT. */ -#define BM_NV_FPROT2_PROT (0xFFU) /*!< Bit mask for NV_FPROT2_PROT. */ -#define BS_NV_FPROT2_PROT (8U) /*!< Bit field size in bits for NV_FPROT2_PROT. */ - -/*! @brief Read current value of the NV_FPROT2_PROT field. */ -#define BR_NV_FPROT2_PROT(x) (HW_NV_FPROT2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot1 -{ - uint8_t U; - struct _hw_nv_fprot1_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot1_t; - -/*! - * @name Constants and macros for entire NV_FPROT1 register - */ -/*@{*/ -#define HW_NV_FPROT1_ADDR(x) ((x) + 0xAU) - -#define HW_NV_FPROT1(x) (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR(x)) -#define HW_NV_FPROT1_RD(x) (HW_NV_FPROT1(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT1 bitfields - */ - -/*! - * @name Register NV_FPROT1, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT1_PROT (0U) /*!< Bit position for NV_FPROT1_PROT. */ -#define BM_NV_FPROT1_PROT (0xFFU) /*!< Bit mask for NV_FPROT1_PROT. */ -#define BS_NV_FPROT1_PROT (8U) /*!< Bit field size in bits for NV_FPROT1_PROT. */ - -/*! @brief Read current value of the NV_FPROT1_PROT field. */ -#define BR_NV_FPROT1_PROT(x) (HW_NV_FPROT1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fprot0 -{ - uint8_t U; - struct _hw_nv_fprot0_bitfields - { - uint8_t PROT : 8; /*!< [7:0] P-Flash Region Protect */ - } B; -} hw_nv_fprot0_t; - -/*! - * @name Constants and macros for entire NV_FPROT0 register - */ -/*@{*/ -#define HW_NV_FPROT0_ADDR(x) ((x) + 0xBU) - -#define HW_NV_FPROT0(x) (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR(x)) -#define HW_NV_FPROT0_RD(x) (HW_NV_FPROT0(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FPROT0 bitfields - */ - -/*! - * @name Register NV_FPROT0, field PROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FPROT0_PROT (0U) /*!< Bit position for NV_FPROT0_PROT. */ -#define BM_NV_FPROT0_PROT (0xFFU) /*!< Bit mask for NV_FPROT0_PROT. */ -#define BS_NV_FPROT0_PROT (8U) /*!< Bit field size in bits for NV_FPROT0_PROT. */ - -/*! @brief Read current value of the NV_FPROT0_PROT field. */ -#define BR_NV_FPROT0_PROT(x) (HW_NV_FPROT0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FSEC - Non-volatile Flash Security Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO) - * - * Reset value: 0xFFU - * - * Allows the user to customize the operation of the MCU at boot time - */ -typedef union _hw_nv_fsec -{ - uint8_t U; - struct _hw_nv_fsec_bitfields - { - uint8_t SEC : 2; /*!< [1:0] Flash Security */ - uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code - * */ - uint8_t MEEN : 2; /*!< [5:4] */ - uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */ - } B; -} hw_nv_fsec_t; - -/*! - * @name Constants and macros for entire NV_FSEC register - */ -/*@{*/ -#define HW_NV_FSEC_ADDR(x) ((x) + 0xCU) - -#define HW_NV_FSEC(x) (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR(x)) -#define HW_NV_FSEC_RD(x) (HW_NV_FSEC(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FSEC bitfields - */ - -/*! - * @name Register NV_FSEC, field SEC[1:0] (RO) - * - * Values: - * - 10 - MCU security status is unsecure - * - 11 - MCU security status is secure - */ -/*@{*/ -#define BP_NV_FSEC_SEC (0U) /*!< Bit position for NV_FSEC_SEC. */ -#define BM_NV_FSEC_SEC (0x03U) /*!< Bit mask for NV_FSEC_SEC. */ -#define BS_NV_FSEC_SEC (2U) /*!< Bit field size in bits for NV_FSEC_SEC. */ - -/*! @brief Read current value of the NV_FSEC_SEC field. */ -#define BR_NV_FSEC_SEC(x) (HW_NV_FSEC(x).B.SEC) -/*@}*/ - -/*! - * @name Register NV_FSEC, field FSLACC[3:2] (RO) - * - * Values: - * - 10 - Freescale factory access denied - * - 11 - Freescale factory access granted - */ -/*@{*/ -#define BP_NV_FSEC_FSLACC (2U) /*!< Bit position for NV_FSEC_FSLACC. */ -#define BM_NV_FSEC_FSLACC (0x0CU) /*!< Bit mask for NV_FSEC_FSLACC. */ -#define BS_NV_FSEC_FSLACC (2U) /*!< Bit field size in bits for NV_FSEC_FSLACC. */ - -/*! @brief Read current value of the NV_FSEC_FSLACC field. */ -#define BR_NV_FSEC_FSLACC(x) (HW_NV_FSEC(x).B.FSLACC) -/*@}*/ - -/*! - * @name Register NV_FSEC, field MEEN[5:4] (RO) - * - * Values: - * - 10 - Mass erase is disabled - * - 11 - Mass erase is enabled - */ -/*@{*/ -#define BP_NV_FSEC_MEEN (4U) /*!< Bit position for NV_FSEC_MEEN. */ -#define BM_NV_FSEC_MEEN (0x30U) /*!< Bit mask for NV_FSEC_MEEN. */ -#define BS_NV_FSEC_MEEN (2U) /*!< Bit field size in bits for NV_FSEC_MEEN. */ - -/*! @brief Read current value of the NV_FSEC_MEEN field. */ -#define BR_NV_FSEC_MEEN(x) (HW_NV_FSEC(x).B.MEEN) -/*@}*/ - -/*! - * @name Register NV_FSEC, field KEYEN[7:6] (RO) - * - * Values: - * - 10 - Backdoor key access enabled - * - 11 - Backdoor key access disabled - */ -/*@{*/ -#define BP_NV_FSEC_KEYEN (6U) /*!< Bit position for NV_FSEC_KEYEN. */ -#define BM_NV_FSEC_KEYEN (0xC0U) /*!< Bit mask for NV_FSEC_KEYEN. */ -#define BS_NV_FSEC_KEYEN (2U) /*!< Bit field size in bits for NV_FSEC_KEYEN. */ - -/*! @brief Read current value of the NV_FSEC_KEYEN field. */ -#define BR_NV_FSEC_KEYEN(x) (HW_NV_FSEC(x).B.KEYEN) -/*@}*/ - -/******************************************************************************* - * HW_NV_FOPT - Non-volatile Flash Option Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fopt -{ - uint8_t U; - struct _hw_nv_fopt_bitfields - { - uint8_t LPBOOT : 1; /*!< [0] */ - uint8_t EZPORT_DIS : 1; /*!< [1] */ - uint8_t RESERVED0 : 6; /*!< [7:2] */ - } B; -} hw_nv_fopt_t; - -/*! - * @name Constants and macros for entire NV_FOPT register - */ -/*@{*/ -#define HW_NV_FOPT_ADDR(x) ((x) + 0xDU) - -#define HW_NV_FOPT(x) (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR(x)) -#define HW_NV_FOPT_RD(x) (HW_NV_FOPT(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FOPT bitfields - */ - -/*! - * @name Register NV_FOPT, field LPBOOT[0] (RO) - * - * Values: - * - 00 - Low-power boot - * - 01 - Normal boot - */ -/*@{*/ -#define BP_NV_FOPT_LPBOOT (0U) /*!< Bit position for NV_FOPT_LPBOOT. */ -#define BM_NV_FOPT_LPBOOT (0x01U) /*!< Bit mask for NV_FOPT_LPBOOT. */ -#define BS_NV_FOPT_LPBOOT (1U) /*!< Bit field size in bits for NV_FOPT_LPBOOT. */ - -/*! @brief Read current value of the NV_FOPT_LPBOOT field. */ -#define BR_NV_FOPT_LPBOOT(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_LPBOOT)) -/*@}*/ - -/*! - * @name Register NV_FOPT, field EZPORT_DIS[1] (RO) - */ -/*@{*/ -#define BP_NV_FOPT_EZPORT_DIS (1U) /*!< Bit position for NV_FOPT_EZPORT_DIS. */ -#define BM_NV_FOPT_EZPORT_DIS (0x02U) /*!< Bit mask for NV_FOPT_EZPORT_DIS. */ -#define BS_NV_FOPT_EZPORT_DIS (1U) /*!< Bit field size in bits for NV_FOPT_EZPORT_DIS. */ - -/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */ -#define BR_NV_FOPT_EZPORT_DIS(x) (BITBAND_ACCESS8(HW_NV_FOPT_ADDR(x), BP_NV_FOPT_EZPORT_DIS)) -/*@}*/ - -/******************************************************************************* - * HW_NV_FEPROT - Non-volatile EERAM Protection Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FEPROT - Non-volatile EERAM Protection Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_feprot -{ - uint8_t U; - struct _hw_nv_feprot_bitfields - { - uint8_t EPROT : 8; /*!< [7:0] */ - } B; -} hw_nv_feprot_t; - -/*! - * @name Constants and macros for entire NV_FEPROT register - */ -/*@{*/ -#define HW_NV_FEPROT_ADDR(x) ((x) + 0xEU) - -#define HW_NV_FEPROT(x) (*(__I hw_nv_feprot_t *) HW_NV_FEPROT_ADDR(x)) -#define HW_NV_FEPROT_RD(x) (HW_NV_FEPROT(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FEPROT bitfields - */ - -/*! - * @name Register NV_FEPROT, field EPROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FEPROT_EPROT (0U) /*!< Bit position for NV_FEPROT_EPROT. */ -#define BM_NV_FEPROT_EPROT (0xFFU) /*!< Bit mask for NV_FEPROT_EPROT. */ -#define BS_NV_FEPROT_EPROT (8U) /*!< Bit field size in bits for NV_FEPROT_EPROT. */ - -/*! @brief Read current value of the NV_FEPROT_EPROT field. */ -#define BR_NV_FEPROT_EPROT(x) (HW_NV_FEPROT(x).U) -/*@}*/ - -/******************************************************************************* - * HW_NV_FDPROT - Non-volatile D-Flash Protection Register - ******************************************************************************/ - -/*! - * @brief HW_NV_FDPROT - Non-volatile D-Flash Protection Register (RO) - * - * Reset value: 0xFFU - */ -typedef union _hw_nv_fdprot -{ - uint8_t U; - struct _hw_nv_fdprot_bitfields - { - uint8_t DPROT : 8; /*!< [7:0] D-Flash Region Protect */ - } B; -} hw_nv_fdprot_t; - -/*! - * @name Constants and macros for entire NV_FDPROT register - */ -/*@{*/ -#define HW_NV_FDPROT_ADDR(x) ((x) + 0xFU) - -#define HW_NV_FDPROT(x) (*(__I hw_nv_fdprot_t *) HW_NV_FDPROT_ADDR(x)) -#define HW_NV_FDPROT_RD(x) (HW_NV_FDPROT(x).U) -/*@}*/ - -/* - * Constants & macros for individual NV_FDPROT bitfields - */ - -/*! - * @name Register NV_FDPROT, field DPROT[7:0] (RO) - */ -/*@{*/ -#define BP_NV_FDPROT_DPROT (0U) /*!< Bit position for NV_FDPROT_DPROT. */ -#define BM_NV_FDPROT_DPROT (0xFFU) /*!< Bit mask for NV_FDPROT_DPROT. */ -#define BS_NV_FDPROT_DPROT (8U) /*!< Bit field size in bits for NV_FDPROT_DPROT. */ - -/*! @brief Read current value of the NV_FDPROT_DPROT field. */ -#define BR_NV_FDPROT_DPROT(x) (HW_NV_FDPROT(x).U) -/*@}*/ - -/******************************************************************************* - * hw_nv_t - module struct - ******************************************************************************/ -/*! - * @brief All NV module registers. - */ -#pragma pack(1) -typedef struct _hw_nv -{ - __I hw_nv_backkey3_t BACKKEY3; /*!< [0x0] Backdoor Comparison Key 3. */ - __I hw_nv_backkey2_t BACKKEY2; /*!< [0x1] Backdoor Comparison Key 2. */ - __I hw_nv_backkey1_t BACKKEY1; /*!< [0x2] Backdoor Comparison Key 1. */ - __I hw_nv_backkey0_t BACKKEY0; /*!< [0x3] Backdoor Comparison Key 0. */ - __I hw_nv_backkey7_t BACKKEY7; /*!< [0x4] Backdoor Comparison Key 7. */ - __I hw_nv_backkey6_t BACKKEY6; /*!< [0x5] Backdoor Comparison Key 6. */ - __I hw_nv_backkey5_t BACKKEY5; /*!< [0x6] Backdoor Comparison Key 5. */ - __I hw_nv_backkey4_t BACKKEY4; /*!< [0x7] Backdoor Comparison Key 4. */ - __I hw_nv_fprot3_t FPROT3; /*!< [0x8] Non-volatile P-Flash Protection 1 - Low Register */ - __I hw_nv_fprot2_t FPROT2; /*!< [0x9] Non-volatile P-Flash Protection 1 - High Register */ - __I hw_nv_fprot1_t FPROT1; /*!< [0xA] Non-volatile P-Flash Protection 0 - Low Register */ - __I hw_nv_fprot0_t FPROT0; /*!< [0xB] Non-volatile P-Flash Protection 0 - High Register */ - __I hw_nv_fsec_t FSEC; /*!< [0xC] Non-volatile Flash Security Register */ - __I hw_nv_fopt_t FOPT; /*!< [0xD] Non-volatile Flash Option Register */ - __I hw_nv_feprot_t FEPROT; /*!< [0xE] Non-volatile EERAM Protection Register */ - __I hw_nv_fdprot_t FDPROT; /*!< [0xF] Non-volatile D-Flash Protection Register */ -} hw_nv_t; -#pragma pack() - -/*! @brief Macro to access all NV registers. */ -/*! @param x NV module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_NV(FTFE_FlashConfig_BASE). */ -#define HW_NV(x) (*(hw_nv_t *)(x)) - -#endif /* __HW_NV_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_osc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_osc.h deleted file mode 100644 index 3866489e443..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_osc.h +++ /dev/null @@ -1,312 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_OSC_REGISTERS_H__ -#define __HW_OSC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 OSC - * - * Oscillator - * - * Registers defined in this header file: - * - HW_OSC_CR - OSC Control Register - * - * - hw_osc_t - Struct containing all module registers. - */ - -#define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */ - -/******************************************************************************* - * HW_OSC_CR - OSC Control Register - ******************************************************************************/ - -/*! - * @brief HW_OSC_CR - OSC Control Register (RW) - * - * Reset value: 0x00U - * - * After OSC is enabled and starts generating the clocks, the configurations - * such as low power and frequency range, must not be changed. - */ -typedef union _hw_osc_cr -{ - uint8_t U; - struct _hw_osc_cr_bitfields - { - uint8_t SC16P : 1; /*!< [0] Oscillator 16 pF Capacitor Load Configure - * */ - uint8_t SC8P : 1; /*!< [1] Oscillator 8 pF Capacitor Load Configure */ - uint8_t SC4P : 1; /*!< [2] Oscillator 4 pF Capacitor Load Configure */ - uint8_t SC2P : 1; /*!< [3] Oscillator 2 pF Capacitor Load Configure */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t EREFSTEN : 1; /*!< [5] External Reference Stop Enable */ - uint8_t RESERVED1 : 1; /*!< [6] */ - uint8_t ERCLKEN : 1; /*!< [7] External Reference Enable */ - } B; -} hw_osc_cr_t; - -/*! - * @name Constants and macros for entire OSC_CR register - */ -/*@{*/ -#define HW_OSC_CR_ADDR(x) ((x) + 0x0U) - -#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x)) -#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U) -#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v)) -#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v))) -#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v))) -#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual OSC_CR bitfields - */ - -/*! - * @name Register OSC_CR, field SC16P[0] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 16 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC16P (0U) /*!< Bit position for OSC_CR_SC16P. */ -#define BM_OSC_CR_SC16P (0x01U) /*!< Bit mask for OSC_CR_SC16P. */ -#define BS_OSC_CR_SC16P (1U) /*!< Bit field size in bits for OSC_CR_SC16P. */ - -/*! @brief Read current value of the OSC_CR_SC16P field. */ -#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P)) - -/*! @brief Format value for bitfield OSC_CR_SC16P. */ -#define BF_OSC_CR_SC16P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P) - -/*! @brief Set the SC16P field to a new value. */ -#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field SC8P[1] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 8 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC8P (1U) /*!< Bit position for OSC_CR_SC8P. */ -#define BM_OSC_CR_SC8P (0x02U) /*!< Bit mask for OSC_CR_SC8P. */ -#define BS_OSC_CR_SC8P (1U) /*!< Bit field size in bits for OSC_CR_SC8P. */ - -/*! @brief Read current value of the OSC_CR_SC8P field. */ -#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P)) - -/*! @brief Format value for bitfield OSC_CR_SC8P. */ -#define BF_OSC_CR_SC8P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P) - -/*! @brief Set the SC8P field to a new value. */ -#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field SC4P[2] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 4 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC4P (2U) /*!< Bit position for OSC_CR_SC4P. */ -#define BM_OSC_CR_SC4P (0x04U) /*!< Bit mask for OSC_CR_SC4P. */ -#define BS_OSC_CR_SC4P (1U) /*!< Bit field size in bits for OSC_CR_SC4P. */ - -/*! @brief Read current value of the OSC_CR_SC4P field. */ -#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P)) - -/*! @brief Format value for bitfield OSC_CR_SC4P. */ -#define BF_OSC_CR_SC4P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P) - -/*! @brief Set the SC4P field to a new value. */ -#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field SC2P[3] (RW) - * - * Configures the oscillator load. - * - * Values: - * - 0 - Disable the selection. - * - 1 - Add 2 pF capacitor to the oscillator load. - */ -/*@{*/ -#define BP_OSC_CR_SC2P (3U) /*!< Bit position for OSC_CR_SC2P. */ -#define BM_OSC_CR_SC2P (0x08U) /*!< Bit mask for OSC_CR_SC2P. */ -#define BS_OSC_CR_SC2P (1U) /*!< Bit field size in bits for OSC_CR_SC2P. */ - -/*! @brief Read current value of the OSC_CR_SC2P field. */ -#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P)) - -/*! @brief Format value for bitfield OSC_CR_SC2P. */ -#define BF_OSC_CR_SC2P(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P) - -/*! @brief Set the SC2P field to a new value. */ -#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field EREFSTEN[5] (RW) - * - * Controls whether or not the external reference clock (OSCERCLK) remains - * enabled when MCU enters Stop mode. - * - * Values: - * - 0 - External reference clock is disabled in Stop mode. - * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set - * before entering Stop mode. - */ -/*@{*/ -#define BP_OSC_CR_EREFSTEN (5U) /*!< Bit position for OSC_CR_EREFSTEN. */ -#define BM_OSC_CR_EREFSTEN (0x20U) /*!< Bit mask for OSC_CR_EREFSTEN. */ -#define BS_OSC_CR_EREFSTEN (1U) /*!< Bit field size in bits for OSC_CR_EREFSTEN. */ - -/*! @brief Read current value of the OSC_CR_EREFSTEN field. */ -#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN)) - -/*! @brief Format value for bitfield OSC_CR_EREFSTEN. */ -#define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN) - -/*! @brief Set the EREFSTEN field to a new value. */ -#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v)) -/*@}*/ - -/*! - * @name Register OSC_CR, field ERCLKEN[7] (RW) - * - * Enables external reference clock (OSCERCLK). - * - * Values: - * - 0 - External reference clock is inactive. - * - 1 - External reference clock is enabled. - */ -/*@{*/ -#define BP_OSC_CR_ERCLKEN (7U) /*!< Bit position for OSC_CR_ERCLKEN. */ -#define BM_OSC_CR_ERCLKEN (0x80U) /*!< Bit mask for OSC_CR_ERCLKEN. */ -#define BS_OSC_CR_ERCLKEN (1U) /*!< Bit field size in bits for OSC_CR_ERCLKEN. */ - -/*! @brief Read current value of the OSC_CR_ERCLKEN field. */ -#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN)) - -/*! @brief Format value for bitfield OSC_CR_ERCLKEN. */ -#define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN) - -/*! @brief Set the ERCLKEN field to a new value. */ -#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_osc_t - module struct - ******************************************************************************/ -/*! - * @brief All OSC module registers. - */ -#pragma pack(1) -typedef struct _hw_osc -{ - __IO hw_osc_cr_t CR; /*!< [0x0] OSC Control Register */ -} hw_osc_t; -#pragma pack() - -/*! @brief Macro to access all OSC registers. */ -/*! @param x OSC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_OSC(OSC_BASE). */ -#define HW_OSC(x) (*(hw_osc_t *)(x)) - -#endif /* __HW_OSC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pdb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pdb.h deleted file mode 100644 index e66764ff113..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pdb.h +++ /dev/null @@ -1,1329 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PDB_REGISTERS_H__ -#define __HW_PDB_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 PDB - * - * Programmable Delay Block - * - * Registers defined in this header file: - * - HW_PDB_SC - Status and Control register - * - HW_PDB_MOD - Modulus register - * - HW_PDB_CNT - Counter register - * - HW_PDB_IDLY - Interrupt Delay register - * - HW_PDB_CHnC1 - Channel n Control register 1 - * - HW_PDB_CHnS - Channel n Status register - * - HW_PDB_CHnDLY0 - Channel n Delay 0 register - * - HW_PDB_CHnDLY1 - Channel n Delay 1 register - * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register - * - HW_PDB_DACINTn - DAC Interval n register - * - HW_PDB_POEN - Pulse-Out n Enable register - * - HW_PDB_POnDLY - Pulse-Out n Delay register - * - * - hw_pdb_t - Struct containing all module registers. - */ - -#define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */ - -/******************************************************************************* - * HW_PDB_SC - Status and Control register - ******************************************************************************/ - -/*! - * @brief HW_PDB_SC - Status and Control register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_sc -{ - uint32_t U; - struct _hw_pdb_sc_bitfields - { - uint32_t LDOK : 1; /*!< [0] Load OK */ - uint32_t CONT : 1; /*!< [1] Continuous Mode Enable */ - uint32_t MULT : 2; /*!< [3:2] Multiplication Factor Select for - * Prescaler */ - uint32_t RESERVED0 : 1; /*!< [4] */ - uint32_t PDBIE : 1; /*!< [5] PDB Interrupt Enable */ - uint32_t PDBIF : 1; /*!< [6] PDB Interrupt Flag */ - uint32_t PDBEN : 1; /*!< [7] PDB Enable */ - uint32_t TRGSEL : 4; /*!< [11:8] Trigger Input Source Select */ - uint32_t PRESCALER : 3; /*!< [14:12] Prescaler Divider Select */ - uint32_t DMAEN : 1; /*!< [15] DMA Enable */ - uint32_t SWTRIG : 1; /*!< [16] Software Trigger */ - uint32_t PDBEIE : 1; /*!< [17] PDB Sequence Error Interrupt Enable */ - uint32_t LDMOD : 2; /*!< [19:18] Load Mode Select */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ - } B; -} hw_pdb_sc_t; - -/*! - * @name Constants and macros for entire PDB_SC register - */ -/*@{*/ -#define HW_PDB_SC_ADDR(x) ((x) + 0x0U) - -#define HW_PDB_SC(x) (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x)) -#define HW_PDB_SC_RD(x) (HW_PDB_SC(x).U) -#define HW_PDB_SC_WR(x, v) (HW_PDB_SC(x).U = (v)) -#define HW_PDB_SC_SET(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) | (v))) -#define HW_PDB_SC_CLR(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v))) -#define HW_PDB_SC_TOG(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_SC bitfields - */ - -/*! - * @name Register PDB_SC, field LDOK[0] (RW) - * - * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm, - * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY, - * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is - * written to the LDOK field, the values in the buffers of above registers are - * not effective and the buffers cannot be written until the values in buffers are - * loaded into their internal registers. LDOK can be written only when PDBEN is - * set or it can be written at the same time with PDBEN being written to 1. It is - * automatically cleared when the values in buffers are loaded into the internal - * registers or the PDBEN is cleared. Writing 0 to it has no effect. - */ -/*@{*/ -#define BP_PDB_SC_LDOK (0U) /*!< Bit position for PDB_SC_LDOK. */ -#define BM_PDB_SC_LDOK (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */ -#define BS_PDB_SC_LDOK (1U) /*!< Bit field size in bits for PDB_SC_LDOK. */ - -/*! @brief Read current value of the PDB_SC_LDOK field. */ -#define BR_PDB_SC_LDOK(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK)) - -/*! @brief Format value for bitfield PDB_SC_LDOK. */ -#define BF_PDB_SC_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK) - -/*! @brief Set the LDOK field to a new value. */ -#define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field CONT[1] (RW) - * - * Enables the PDB operation in Continuous mode. - * - * Values: - * - 0 - PDB operation in One-Shot mode - * - 1 - PDB operation in Continuous mode - */ -/*@{*/ -#define BP_PDB_SC_CONT (1U) /*!< Bit position for PDB_SC_CONT. */ -#define BM_PDB_SC_CONT (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */ -#define BS_PDB_SC_CONT (1U) /*!< Bit field size in bits for PDB_SC_CONT. */ - -/*! @brief Read current value of the PDB_SC_CONT field. */ -#define BR_PDB_SC_CONT(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT)) - -/*! @brief Format value for bitfield PDB_SC_CONT. */ -#define BF_PDB_SC_CONT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT) - -/*! @brief Set the CONT field to a new value. */ -#define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field MULT[3:2] (RW) - * - * Selects the multiplication factor of the prescaler divider for the counter - * clock. - * - * Values: - * - 00 - Multiplication factor is 1. - * - 01 - Multiplication factor is 10. - * - 10 - Multiplication factor is 20. - * - 11 - Multiplication factor is 40. - */ -/*@{*/ -#define BP_PDB_SC_MULT (2U) /*!< Bit position for PDB_SC_MULT. */ -#define BM_PDB_SC_MULT (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */ -#define BS_PDB_SC_MULT (2U) /*!< Bit field size in bits for PDB_SC_MULT. */ - -/*! @brief Read current value of the PDB_SC_MULT field. */ -#define BR_PDB_SC_MULT(x) (HW_PDB_SC(x).B.MULT) - -/*! @brief Format value for bitfield PDB_SC_MULT. */ -#define BF_PDB_SC_MULT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT) - -/*! @brief Set the MULT field to a new value. */ -#define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v))) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBIE[5] (RW) - * - * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF - * generates a PDB interrupt. - * - * Values: - * - 0 - PDB interrupt disabled. - * - 1 - PDB interrupt enabled. - */ -/*@{*/ -#define BP_PDB_SC_PDBIE (5U) /*!< Bit position for PDB_SC_PDBIE. */ -#define BM_PDB_SC_PDBIE (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */ -#define BS_PDB_SC_PDBIE (1U) /*!< Bit field size in bits for PDB_SC_PDBIE. */ - -/*! @brief Read current value of the PDB_SC_PDBIE field. */ -#define BR_PDB_SC_PDBIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE)) - -/*! @brief Format value for bitfield PDB_SC_PDBIE. */ -#define BF_PDB_SC_PDBIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE) - -/*! @brief Set the PDBIE field to a new value. */ -#define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBIF[6] (RW) - * - * This field is set when the counter value is equal to the IDLY register. - * Writing zero clears this field. - */ -/*@{*/ -#define BP_PDB_SC_PDBIF (6U) /*!< Bit position for PDB_SC_PDBIF. */ -#define BM_PDB_SC_PDBIF (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */ -#define BS_PDB_SC_PDBIF (1U) /*!< Bit field size in bits for PDB_SC_PDBIF. */ - -/*! @brief Read current value of the PDB_SC_PDBIF field. */ -#define BR_PDB_SC_PDBIF(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF)) - -/*! @brief Format value for bitfield PDB_SC_PDBIF. */ -#define BF_PDB_SC_PDBIF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF) - -/*! @brief Set the PDBIF field to a new value. */ -#define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBEN[7] (RW) - * - * Values: - * - 0 - PDB disabled. Counter is off. - * - 1 - PDB enabled. - */ -/*@{*/ -#define BP_PDB_SC_PDBEN (7U) /*!< Bit position for PDB_SC_PDBEN. */ -#define BM_PDB_SC_PDBEN (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */ -#define BS_PDB_SC_PDBEN (1U) /*!< Bit field size in bits for PDB_SC_PDBEN. */ - -/*! @brief Read current value of the PDB_SC_PDBEN field. */ -#define BR_PDB_SC_PDBEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN)) - -/*! @brief Format value for bitfield PDB_SC_PDBEN. */ -#define BF_PDB_SC_PDBEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN) - -/*! @brief Set the PDBEN field to a new value. */ -#define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field TRGSEL[11:8] (RW) - * - * Selects the trigger input source for the PDB. The trigger input source can be - * internal or external (EXTRG pin), or the software trigger. Refer to chip - * configuration details for the actual PDB input trigger connections. - * - * Values: - * - 0000 - Trigger-In 0 is selected. - * - 0001 - Trigger-In 1 is selected. - * - 0010 - Trigger-In 2 is selected. - * - 0011 - Trigger-In 3 is selected. - * - 0100 - Trigger-In 4 is selected. - * - 0101 - Trigger-In 5 is selected. - * - 0110 - Trigger-In 6 is selected. - * - 0111 - Trigger-In 7 is selected. - * - 1000 - Trigger-In 8 is selected. - * - 1001 - Trigger-In 9 is selected. - * - 1010 - Trigger-In 10 is selected. - * - 1011 - Trigger-In 11 is selected. - * - 1100 - Trigger-In 12 is selected. - * - 1101 - Trigger-In 13 is selected. - * - 1110 - Trigger-In 14 is selected. - * - 1111 - Software trigger is selected. - */ -/*@{*/ -#define BP_PDB_SC_TRGSEL (8U) /*!< Bit position for PDB_SC_TRGSEL. */ -#define BM_PDB_SC_TRGSEL (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */ -#define BS_PDB_SC_TRGSEL (4U) /*!< Bit field size in bits for PDB_SC_TRGSEL. */ - -/*! @brief Read current value of the PDB_SC_TRGSEL field. */ -#define BR_PDB_SC_TRGSEL(x) (HW_PDB_SC(x).B.TRGSEL) - -/*! @brief Format value for bitfield PDB_SC_TRGSEL. */ -#define BF_PDB_SC_TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL) - -/*! @brief Set the TRGSEL field to a new value. */ -#define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v))) -/*@}*/ - -/*! - * @name Register PDB_SC, field PRESCALER[14:12] (RW) - * - * Values: - * - 000 - Counting uses the peripheral clock divided by multiplication factor - * selected by MULT. - * - 001 - Counting uses the peripheral clock divided by twice of the - * multiplication factor selected by MULT. - * - 010 - Counting uses the peripheral clock divided by four times of the - * multiplication factor selected by MULT. - * - 011 - Counting uses the peripheral clock divided by eight times of the - * multiplication factor selected by MULT. - * - 100 - Counting uses the peripheral clock divided by 16 times of the - * multiplication factor selected by MULT. - * - 101 - Counting uses the peripheral clock divided by 32 times of the - * multiplication factor selected by MULT. - * - 110 - Counting uses the peripheral clock divided by 64 times of the - * multiplication factor selected by MULT. - * - 111 - Counting uses the peripheral clock divided by 128 times of the - * multiplication factor selected by MULT. - */ -/*@{*/ -#define BP_PDB_SC_PRESCALER (12U) /*!< Bit position for PDB_SC_PRESCALER. */ -#define BM_PDB_SC_PRESCALER (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */ -#define BS_PDB_SC_PRESCALER (3U) /*!< Bit field size in bits for PDB_SC_PRESCALER. */ - -/*! @brief Read current value of the PDB_SC_PRESCALER field. */ -#define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER) - -/*! @brief Format value for bitfield PDB_SC_PRESCALER. */ -#define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER) - -/*! @brief Set the PRESCALER field to a new value. */ -#define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v))) -/*@}*/ - -/*! - * @name Register PDB_SC, field DMAEN[15] (RW) - * - * When DMA is enabled, the PDBIF flag generates a DMA request instead of an - * interrupt. - * - * Values: - * - 0 - DMA disabled. - * - 1 - DMA enabled. - */ -/*@{*/ -#define BP_PDB_SC_DMAEN (15U) /*!< Bit position for PDB_SC_DMAEN. */ -#define BM_PDB_SC_DMAEN (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */ -#define BS_PDB_SC_DMAEN (1U) /*!< Bit field size in bits for PDB_SC_DMAEN. */ - -/*! @brief Read current value of the PDB_SC_DMAEN field. */ -#define BR_PDB_SC_DMAEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN)) - -/*! @brief Format value for bitfield PDB_SC_DMAEN. */ -#define BF_PDB_SC_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field SWTRIG[16] (WORZ) - * - * When PDB is enabled and the software trigger is selected as the trigger input - * source, writing 1 to this field resets and restarts the counter. Writing 0 to - * this field has no effect. Reading this field results 0. - */ -/*@{*/ -#define BP_PDB_SC_SWTRIG (16U) /*!< Bit position for PDB_SC_SWTRIG. */ -#define BM_PDB_SC_SWTRIG (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */ -#define BS_PDB_SC_SWTRIG (1U) /*!< Bit field size in bits for PDB_SC_SWTRIG. */ - -/*! @brief Format value for bitfield PDB_SC_SWTRIG. */ -#define BF_PDB_SC_SWTRIG(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG) - -/*! @brief Set the SWTRIG field to a new value. */ -#define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field PDBEIE[17] (RW) - * - * Enables the PDB sequence error interrupt. When this field is set, any of the - * PDB channel sequence error flags generates a PDB sequence error interrupt. - * - * Values: - * - 0 - PDB sequence error interrupt disabled. - * - 1 - PDB sequence error interrupt enabled. - */ -/*@{*/ -#define BP_PDB_SC_PDBEIE (17U) /*!< Bit position for PDB_SC_PDBEIE. */ -#define BM_PDB_SC_PDBEIE (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */ -#define BS_PDB_SC_PDBEIE (1U) /*!< Bit field size in bits for PDB_SC_PDBEIE. */ - -/*! @brief Read current value of the PDB_SC_PDBEIE field. */ -#define BR_PDB_SC_PDBEIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE)) - -/*! @brief Format value for bitfield PDB_SC_PDBEIE. */ -#define BF_PDB_SC_PDBEIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE) - -/*! @brief Set the PDBEIE field to a new value. */ -#define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v)) -/*@}*/ - -/*! - * @name Register PDB_SC, field LDMOD[19:18] (RW) - * - * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, - * after 1 is written to LDOK. - * - * Values: - * - 00 - The internal registers are loaded with the values from their buffers - * immediately after 1 is written to LDOK. - * - 01 - The internal registers are loaded with the values from their buffers - * when the PDB counter reaches the MOD register value after 1 is written to - * LDOK. - * - 10 - The internal registers are loaded with the values from their buffers - * when a trigger input event is detected after 1 is written to LDOK. - * - 11 - The internal registers are loaded with the values from their buffers - * when either the PDB counter reaches the MOD register value or a trigger - * input event is detected, after 1 is written to LDOK. - */ -/*@{*/ -#define BP_PDB_SC_LDMOD (18U) /*!< Bit position for PDB_SC_LDMOD. */ -#define BM_PDB_SC_LDMOD (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */ -#define BS_PDB_SC_LDMOD (2U) /*!< Bit field size in bits for PDB_SC_LDMOD. */ - -/*! @brief Read current value of the PDB_SC_LDMOD field. */ -#define BR_PDB_SC_LDMOD(x) (HW_PDB_SC(x).B.LDMOD) - -/*! @brief Format value for bitfield PDB_SC_LDMOD. */ -#define BF_PDB_SC_LDMOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD) - -/*! @brief Set the LDMOD field to a new value. */ -#define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_MOD - Modulus register - ******************************************************************************/ - -/*! - * @brief HW_PDB_MOD - Modulus register (RW) - * - * Reset value: 0x0000FFFFU - */ -typedef union _hw_pdb_mod -{ - uint32_t U; - struct _hw_pdb_mod_bitfields - { - uint32_t MOD : 16; /*!< [15:0] PDB Modulus */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_mod_t; - -/*! - * @name Constants and macros for entire PDB_MOD register - */ -/*@{*/ -#define HW_PDB_MOD_ADDR(x) ((x) + 0x4U) - -#define HW_PDB_MOD(x) (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x)) -#define HW_PDB_MOD_RD(x) (HW_PDB_MOD(x).U) -#define HW_PDB_MOD_WR(x, v) (HW_PDB_MOD(x).U = (v)) -#define HW_PDB_MOD_SET(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) | (v))) -#define HW_PDB_MOD_CLR(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v))) -#define HW_PDB_MOD_TOG(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_MOD bitfields - */ - -/*! - * @name Register PDB_MOD, field MOD[15:0] (RW) - * - * Specifies the period of the counter. When the counter reaches this value, it - * will be reset back to zero. If the PDB is in Continuous mode, the count begins - * anew. Reading this field returns the value of the internal register that is - * effective for the current cycle of PDB. - */ -/*@{*/ -#define BP_PDB_MOD_MOD (0U) /*!< Bit position for PDB_MOD_MOD. */ -#define BM_PDB_MOD_MOD (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */ -#define BS_PDB_MOD_MOD (16U) /*!< Bit field size in bits for PDB_MOD_MOD. */ - -/*! @brief Read current value of the PDB_MOD_MOD field. */ -#define BR_PDB_MOD_MOD(x) (HW_PDB_MOD(x).B.MOD) - -/*! @brief Format value for bitfield PDB_MOD_MOD. */ -#define BF_PDB_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD) - -/*! @brief Set the MOD field to a new value. */ -#define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_CNT - Counter register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CNT - Counter register (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_cnt -{ - uint32_t U; - struct _hw_pdb_cnt_bitfields - { - uint32_t CNT : 16; /*!< [15:0] PDB Counter */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_cnt_t; - -/*! - * @name Constants and macros for entire PDB_CNT register - */ -/*@{*/ -#define HW_PDB_CNT_ADDR(x) ((x) + 0x8U) - -#define HW_PDB_CNT(x) (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x)) -#define HW_PDB_CNT_RD(x) (HW_PDB_CNT(x).U) -/*@}*/ - -/* - * Constants & macros for individual PDB_CNT bitfields - */ - -/*! - * @name Register PDB_CNT, field CNT[15:0] (RO) - * - * Contains the current value of the counter. - */ -/*@{*/ -#define BP_PDB_CNT_CNT (0U) /*!< Bit position for PDB_CNT_CNT. */ -#define BM_PDB_CNT_CNT (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */ -#define BS_PDB_CNT_CNT (16U) /*!< Bit field size in bits for PDB_CNT_CNT. */ - -/*! @brief Read current value of the PDB_CNT_CNT field. */ -#define BR_PDB_CNT_CNT(x) (HW_PDB_CNT(x).B.CNT) -/*@}*/ - -/******************************************************************************* - * HW_PDB_IDLY - Interrupt Delay register - ******************************************************************************/ - -/*! - * @brief HW_PDB_IDLY - Interrupt Delay register (RW) - * - * Reset value: 0x0000FFFFU - */ -typedef union _hw_pdb_idly -{ - uint32_t U; - struct _hw_pdb_idly_bitfields - { - uint32_t IDLY : 16; /*!< [15:0] PDB Interrupt Delay */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_idly_t; - -/*! - * @name Constants and macros for entire PDB_IDLY register - */ -/*@{*/ -#define HW_PDB_IDLY_ADDR(x) ((x) + 0xCU) - -#define HW_PDB_IDLY(x) (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x)) -#define HW_PDB_IDLY_RD(x) (HW_PDB_IDLY(x).U) -#define HW_PDB_IDLY_WR(x, v) (HW_PDB_IDLY(x).U = (v)) -#define HW_PDB_IDLY_SET(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) | (v))) -#define HW_PDB_IDLY_CLR(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v))) -#define HW_PDB_IDLY_TOG(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_IDLY bitfields - */ - -/*! - * @name Register PDB_IDLY, field IDLY[15:0] (RW) - * - * Specifies the delay value to schedule the PDB interrupt. It can be used to - * schedule an independent interrupt at some point in the PDB cycle. If enabled, a - * PDB interrupt is generated, when the counter is equal to the IDLY. Reading - * this field returns the value of internal register that is effective for the - * current cycle of the PDB. - */ -/*@{*/ -#define BP_PDB_IDLY_IDLY (0U) /*!< Bit position for PDB_IDLY_IDLY. */ -#define BM_PDB_IDLY_IDLY (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */ -#define BS_PDB_IDLY_IDLY (16U) /*!< Bit field size in bits for PDB_IDLY_IDLY. */ - -/*! @brief Read current value of the PDB_IDLY_IDLY field. */ -#define BR_PDB_IDLY_IDLY(x) (HW_PDB_IDLY(x).B.IDLY) - -/*! @brief Format value for bitfield PDB_IDLY_IDLY. */ -#define BF_PDB_IDLY_IDLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY) - -/*! @brief Set the IDLY field to a new value. */ -#define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_CHnC1 - Channel n Control register 1 - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW) - * - * Reset value: 0x00000000U - * - * Each PDB channel has one control register, CHnC1. The bits in this register - * control the functionality of each PDB channel operation. - */ -typedef union _hw_pdb_chnc1 -{ - uint32_t U; - struct _hw_pdb_chnc1_bitfields - { - uint32_t EN : 8; /*!< [7:0] PDB Channel Pre-Trigger Enable */ - uint32_t TOS : 8; /*!< [15:8] PDB Channel Pre-Trigger Output Select */ - uint32_t BB : 8; /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back - * Operation Enable */ - uint32_t RESERVED0 : 8; /*!< [31:24] */ - } B; -} hw_pdb_chnc1_t; - -/*! - * @name Constants and macros for entire PDB_CHnC1 register - */ -/*@{*/ -#define HW_PDB_CHnC1_COUNT (2U) - -#define HW_PDB_CHnC1_ADDR(x, n) ((x) + 0x10U + (0x28U * (n))) - -#define HW_PDB_CHnC1(x, n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n)) -#define HW_PDB_CHnC1_RD(x, n) (HW_PDB_CHnC1(x, n).U) -#define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v)) -#define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) | (v))) -#define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v))) -#define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnC1 bitfields - */ - -/*! - * @name Register PDB_CHnC1, field EN[7:0] (RW) - * - * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger - * bits are implemented in this MCU. - * - * Values: - * - 0 - PDB channel's corresponding pre-trigger disabled. - * - 1 - PDB channel's corresponding pre-trigger enabled. - */ -/*@{*/ -#define BP_PDB_CHnC1_EN (0U) /*!< Bit position for PDB_CHnC1_EN. */ -#define BM_PDB_CHnC1_EN (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */ -#define BS_PDB_CHnC1_EN (8U) /*!< Bit field size in bits for PDB_CHnC1_EN. */ - -/*! @brief Read current value of the PDB_CHnC1_EN field. */ -#define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN) - -/*! @brief Format value for bitfield PDB_CHnC1_EN. */ -#define BF_PDB_CHnC1_EN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN) - -/*! @brief Set the EN field to a new value. */ -#define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v))) -/*@}*/ - -/*! - * @name Register PDB_CHnC1, field TOS[15:8] (RW) - * - * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are - * implemented in this MCU. - * - * Values: - * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The - * pre-trigger asserts one peripheral clock cycle after a rising edge is detected - * on selected trigger input source or software trigger is selected and SWTRIG - * is written with 1. - * - 1 - PDB channel's corresponding pre-trigger asserts when the counter - * reaches the channel delay register and one peripheral clock cycle after a rising - * edge is detected on selected trigger input source or software trigger is - * selected and SETRIG is written with 1. - */ -/*@{*/ -#define BP_PDB_CHnC1_TOS (8U) /*!< Bit position for PDB_CHnC1_TOS. */ -#define BM_PDB_CHnC1_TOS (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */ -#define BS_PDB_CHnC1_TOS (8U) /*!< Bit field size in bits for PDB_CHnC1_TOS. */ - -/*! @brief Read current value of the PDB_CHnC1_TOS field. */ -#define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS) - -/*! @brief Format value for bitfield PDB_CHnC1_TOS. */ -#define BF_PDB_CHnC1_TOS(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS) - -/*! @brief Set the TOS field to a new value. */ -#define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v))) -/*@}*/ - -/*! - * @name Register PDB_CHnC1, field BB[23:16] (RW) - * - * These bits enable the PDB ADC pre-trigger operation as back-to-back mode. - * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation - * enables the ADC conversions complete to trigger the next PDB channel - * pre-trigger and trigger output, so that the ADC conversions can be triggered on next - * set of configuration and results registers. Application code must only enable - * the back-to-back operation of the PDB pre-triggers at the leading of the - * back-to-back connection chain. - * - * Values: - * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled. - * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled. - */ -/*@{*/ -#define BP_PDB_CHnC1_BB (16U) /*!< Bit position for PDB_CHnC1_BB. */ -#define BM_PDB_CHnC1_BB (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */ -#define BS_PDB_CHnC1_BB (8U) /*!< Bit field size in bits for PDB_CHnC1_BB. */ - -/*! @brief Read current value of the PDB_CHnC1_BB field. */ -#define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB) - -/*! @brief Format value for bitfield PDB_CHnC1_BB. */ -#define BF_PDB_CHnC1_BB(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB) - -/*! @brief Set the BB field to a new value. */ -#define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v))) -/*@}*/ -/******************************************************************************* - * HW_PDB_CHnS - Channel n Status register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnS - Channel n Status register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_chns -{ - uint32_t U; - struct _hw_pdb_chns_bitfields - { - uint32_t ERR : 8; /*!< [7:0] PDB Channel Sequence Error Flags */ - uint32_t RESERVED0 : 8; /*!< [15:8] */ - uint32_t CF : 8; /*!< [23:16] PDB Channel Flags */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ - } B; -} hw_pdb_chns_t; - -/*! - * @name Constants and macros for entire PDB_CHnS register - */ -/*@{*/ -#define HW_PDB_CHnS_COUNT (2U) - -#define HW_PDB_CHnS_ADDR(x, n) ((x) + 0x14U + (0x28U * (n))) - -#define HW_PDB_CHnS(x, n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n)) -#define HW_PDB_CHnS_RD(x, n) (HW_PDB_CHnS(x, n).U) -#define HW_PDB_CHnS_WR(x, n, v) (HW_PDB_CHnS(x, n).U = (v)) -#define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) | (v))) -#define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v))) -#define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnS bitfields - */ - -/*! - * @name Register PDB_CHnS, field ERR[7:0] (RW) - * - * Only the lower M bits are implemented in this MCU. - * - * Values: - * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger. - * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger. - * ADCn block can be triggered for a conversion by one pre-trigger from PDB - * channel n. When one conversion, which is triggered by one of the pre-triggers - * from PDB channel n, is in progress, new trigger from PDB channel's - * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. - * Writing 0's to clear the sequence error flags. - */ -/*@{*/ -#define BP_PDB_CHnS_ERR (0U) /*!< Bit position for PDB_CHnS_ERR. */ -#define BM_PDB_CHnS_ERR (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */ -#define BS_PDB_CHnS_ERR (8U) /*!< Bit field size in bits for PDB_CHnS_ERR. */ - -/*! @brief Read current value of the PDB_CHnS_ERR field. */ -#define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR) - -/*! @brief Format value for bitfield PDB_CHnS_ERR. */ -#define BF_PDB_CHnS_ERR(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR) - -/*! @brief Set the ERR field to a new value. */ -#define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v))) -/*@}*/ - -/*! - * @name Register PDB_CHnS, field CF[23:16] (RW) - * - * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to - * clear these bits. - */ -/*@{*/ -#define BP_PDB_CHnS_CF (16U) /*!< Bit position for PDB_CHnS_CF. */ -#define BM_PDB_CHnS_CF (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */ -#define BS_PDB_CHnS_CF (8U) /*!< Bit field size in bits for PDB_CHnS_CF. */ - -/*! @brief Read current value of the PDB_CHnS_CF field. */ -#define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF) - -/*! @brief Format value for bitfield PDB_CHnS_CF. */ -#define BF_PDB_CHnS_CF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF) - -/*! @brief Set the CF field to a new value. */ -#define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v))) -/*@}*/ -/******************************************************************************* - * HW_PDB_CHnDLY0 - Channel n Delay 0 register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_chndly0 -{ - uint32_t U; - struct _hw_pdb_chndly0_bitfields - { - uint32_t DLY : 16; /*!< [15:0] PDB Channel Delay */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_chndly0_t; - -/*! - * @name Constants and macros for entire PDB_CHnDLY0 register - */ -/*@{*/ -#define HW_PDB_CHnDLY0_COUNT (2U) - -#define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n))) - -#define HW_PDB_CHnDLY0(x, n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n)) -#define HW_PDB_CHnDLY0_RD(x, n) (HW_PDB_CHnDLY0(x, n).U) -#define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v)) -#define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) | (v))) -#define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v))) -#define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnDLY0 bitfields - */ - -/*! - * @name Register PDB_CHnDLY0, field DLY[15:0] (RW) - * - * Specifies the delay value for the channel's corresponding pre-trigger. The - * pre-trigger asserts when the counter is equal to DLY. Reading this field returns - * the value of internal register that is effective for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_CHnDLY0_DLY (0U) /*!< Bit position for PDB_CHnDLY0_DLY. */ -#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */ -#define BS_PDB_CHnDLY0_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */ - -/*! @brief Read current value of the PDB_CHnDLY0_DLY field. */ -#define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY) - -/*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */ -#define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY) - -/*! @brief Set the DLY field to a new value. */ -#define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v))) -/*@}*/ -/******************************************************************************* - * HW_PDB_CHnDLY1 - Channel n Delay 1 register - ******************************************************************************/ - -/*! - * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_chndly1 -{ - uint32_t U; - struct _hw_pdb_chndly1_bitfields - { - uint32_t DLY : 16; /*!< [15:0] PDB Channel Delay */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_chndly1_t; - -/*! - * @name Constants and macros for entire PDB_CHnDLY1 register - */ -/*@{*/ -#define HW_PDB_CHnDLY1_COUNT (2U) - -#define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n))) - -#define HW_PDB_CHnDLY1(x, n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n)) -#define HW_PDB_CHnDLY1_RD(x, n) (HW_PDB_CHnDLY1(x, n).U) -#define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v)) -#define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) | (v))) -#define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v))) -#define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_CHnDLY1 bitfields - */ - -/*! - * @name Register PDB_CHnDLY1, field DLY[15:0] (RW) - * - * These bits specify the delay value for the channel's corresponding - * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these - * bits returns the value of internal register that is effective for the current PDB - * cycle. - */ -/*@{*/ -#define BP_PDB_CHnDLY1_DLY (0U) /*!< Bit position for PDB_CHnDLY1_DLY. */ -#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */ -#define BS_PDB_CHnDLY1_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */ - -/*! @brief Read current value of the PDB_CHnDLY1_DLY field. */ -#define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY) - -/*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */ -#define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY) - -/*! @brief Set the DLY field to a new value. */ -#define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_DACINTCn - DAC Interval Trigger n Control register - ******************************************************************************/ - -/*! - * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_dacintcn -{ - uint32_t U; - struct _hw_pdb_dacintcn_bitfields - { - uint32_t TOE : 1; /*!< [0] DAC Interval Trigger Enable */ - uint32_t EXT : 1; /*!< [1] DAC External Trigger Input Enable */ - uint32_t RESERVED0 : 30; /*!< [31:2] */ - } B; -} hw_pdb_dacintcn_t; - -/*! - * @name Constants and macros for entire PDB_DACINTCn register - */ -/*@{*/ -#define HW_PDB_DACINTCn_COUNT (2U) - -#define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n))) - -#define HW_PDB_DACINTCn(x, n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n)) -#define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U) -#define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v)) -#define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) | (v))) -#define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v))) -#define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_DACINTCn bitfields - */ - -/*! - * @name Register PDB_DACINTCn, field TOE[0] (RW) - * - * This bit enables the DAC interval trigger. - * - * Values: - * - 0 - DAC interval trigger disabled. - * - 1 - DAC interval trigger enabled. - */ -/*@{*/ -#define BP_PDB_DACINTCn_TOE (0U) /*!< Bit position for PDB_DACINTCn_TOE. */ -#define BM_PDB_DACINTCn_TOE (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */ -#define BS_PDB_DACINTCn_TOE (1U) /*!< Bit field size in bits for PDB_DACINTCn_TOE. */ - -/*! @brief Read current value of the PDB_DACINTCn_TOE field. */ -#define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE)) - -/*! @brief Format value for bitfield PDB_DACINTCn_TOE. */ -#define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE) - -/*! @brief Set the TOE field to a new value. */ -#define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v)) -/*@}*/ - -/*! - * @name Register PDB_DACINTCn, field EXT[1] (RW) - * - * Enables the external trigger for DAC interval counter. - * - * Values: - * - 0 - DAC external trigger input disabled. DAC interval counter is reset and - * counting starts when a rising edge is detected on selected trigger input - * source or software trigger is selected and SWTRIG is written with 1. - * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed - * and DAC external trigger input triggers the DAC interval trigger. - */ -/*@{*/ -#define BP_PDB_DACINTCn_EXT (1U) /*!< Bit position for PDB_DACINTCn_EXT. */ -#define BM_PDB_DACINTCn_EXT (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */ -#define BS_PDB_DACINTCn_EXT (1U) /*!< Bit field size in bits for PDB_DACINTCn_EXT. */ - -/*! @brief Read current value of the PDB_DACINTCn_EXT field. */ -#define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT)) - -/*! @brief Format value for bitfield PDB_DACINTCn_EXT. */ -#define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT) - -/*! @brief Set the EXT field to a new value. */ -#define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v)) -/*@}*/ -/******************************************************************************* - * HW_PDB_DACINTn - DAC Interval n register - ******************************************************************************/ - -/*! - * @brief HW_PDB_DACINTn - DAC Interval n register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_dacintn -{ - uint32_t U; - struct _hw_pdb_dacintn_bitfields - { - uint32_t INT : 16; /*!< [15:0] DAC Interval */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_pdb_dacintn_t; - -/*! - * @name Constants and macros for entire PDB_DACINTn register - */ -/*@{*/ -#define HW_PDB_DACINTn_COUNT (2U) - -#define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n))) - -#define HW_PDB_DACINTn(x, n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n)) -#define HW_PDB_DACINTn_RD(x, n) (HW_PDB_DACINTn(x, n).U) -#define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v)) -#define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) | (v))) -#define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v))) -#define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_DACINTn bitfields - */ - -/*! - * @name Register PDB_DACINTn, field INT[15:0] (RW) - * - * Specifies the interval value for DAC interval trigger. DAC interval trigger - * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. - * Reading this field returns the value of internal register that is effective - * for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */ -#define BM_PDB_DACINTn_INT (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */ -#define BS_PDB_DACINTn_INT (16U) /*!< Bit field size in bits for PDB_DACINTn_INT. */ - -/*! @brief Read current value of the PDB_DACINTn_INT field. */ -#define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT) - -/*! @brief Format value for bitfield PDB_DACINTn_INT. */ -#define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT) - -/*! @brief Set the INT field to a new value. */ -#define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_POEN - Pulse-Out n Enable register - ******************************************************************************/ - -/*! - * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_poen -{ - uint32_t U; - struct _hw_pdb_poen_bitfields - { - uint32_t POEN : 8; /*!< [7:0] PDB Pulse-Out Enable */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_pdb_poen_t; - -/*! - * @name Constants and macros for entire PDB_POEN register - */ -/*@{*/ -#define HW_PDB_POEN_ADDR(x) ((x) + 0x190U) - -#define HW_PDB_POEN(x) (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x)) -#define HW_PDB_POEN_RD(x) (HW_PDB_POEN(x).U) -#define HW_PDB_POEN_WR(x, v) (HW_PDB_POEN(x).U = (v)) -#define HW_PDB_POEN_SET(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) | (v))) -#define HW_PDB_POEN_CLR(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v))) -#define HW_PDB_POEN_TOG(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_POEN bitfields - */ - -/*! - * @name Register PDB_POEN, field POEN[7:0] (RW) - * - * Enables the pulse output. Only lower Y bits are implemented in this MCU. - * - * Values: - * - 0 - PDB Pulse-Out disabled - * - 1 - PDB Pulse-Out enabled - */ -/*@{*/ -#define BP_PDB_POEN_POEN (0U) /*!< Bit position for PDB_POEN_POEN. */ -#define BM_PDB_POEN_POEN (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */ -#define BS_PDB_POEN_POEN (8U) /*!< Bit field size in bits for PDB_POEN_POEN. */ - -/*! @brief Read current value of the PDB_POEN_POEN field. */ -#define BR_PDB_POEN_POEN(x) (HW_PDB_POEN(x).B.POEN) - -/*! @brief Format value for bitfield PDB_POEN_POEN. */ -#define BF_PDB_POEN_POEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN) - -/*! @brief Set the POEN field to a new value. */ -#define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v))) -/*@}*/ - -/******************************************************************************* - * HW_PDB_POnDLY - Pulse-Out n Delay register - ******************************************************************************/ - -/*! - * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_pdb_pondly -{ - uint32_t U; - struct _hw_pdb_pondly_bitfields - { - uint32_t DLY2 : 16; /*!< [15:0] PDB Pulse-Out Delay 2 */ - uint32_t DLY1 : 16; /*!< [31:16] PDB Pulse-Out Delay 1 */ - } B; -} hw_pdb_pondly_t; - -/*! - * @name Constants and macros for entire PDB_POnDLY register - */ -/*@{*/ -#define HW_PDB_POnDLY_COUNT (3U) - -#define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n))) - -#define HW_PDB_POnDLY(x, n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n)) -#define HW_PDB_POnDLY_RD(x, n) (HW_PDB_POnDLY(x, n).U) -#define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v)) -#define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) | (v))) -#define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v))) -#define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PDB_POnDLY bitfields - */ - -/*! - * @name Register PDB_POnDLY, field DLY2[15:0] (RW) - * - * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes - * low when the PDB counter is equal to the DLY2. Reading these bits returns the - * value of internal register that is effective for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_POnDLY_DLY2 (0U) /*!< Bit position for PDB_POnDLY_DLY2. */ -#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */ -#define BS_PDB_POnDLY_DLY2 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY2. */ - -/*! @brief Read current value of the PDB_POnDLY_DLY2 field. */ -#define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2) - -/*! @brief Format value for bitfield PDB_POnDLY_DLY2. */ -#define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2) - -/*! @brief Set the DLY2 field to a new value. */ -#define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v))) -/*@}*/ - -/*! - * @name Register PDB_POnDLY, field DLY1[31:16] (RW) - * - * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes - * high when the PDB counter is equal to the DLY1. Reading these bits returns the - * value of internal register that is effective for the current PDB cycle. - */ -/*@{*/ -#define BP_PDB_POnDLY_DLY1 (16U) /*!< Bit position for PDB_POnDLY_DLY1. */ -#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */ -#define BS_PDB_POnDLY_DLY1 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY1. */ - -/*! @brief Read current value of the PDB_POnDLY_DLY1 field. */ -#define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1) - -/*! @brief Format value for bitfield PDB_POnDLY_DLY1. */ -#define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1) - -/*! @brief Set the DLY1 field to a new value. */ -#define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v))) -/*@}*/ - -/******************************************************************************* - * hw_pdb_t - module struct - ******************************************************************************/ -/*! - * @brief All PDB module registers. - */ -#pragma pack(1) -typedef struct _hw_pdb -{ - __IO hw_pdb_sc_t SC; /*!< [0x0] Status and Control register */ - __IO hw_pdb_mod_t MOD; /*!< [0x4] Modulus register */ - __I hw_pdb_cnt_t CNT; /*!< [0x8] Counter register */ - __IO hw_pdb_idly_t IDLY; /*!< [0xC] Interrupt Delay register */ - struct { - __IO hw_pdb_chnc1_t CHnC1; /*!< [0x10] Channel n Control register 1 */ - __IO hw_pdb_chns_t CHnS; /*!< [0x14] Channel n Status register */ - __IO hw_pdb_chndly0_t CHnDLY0; /*!< [0x18] Channel n Delay 0 register */ - __IO hw_pdb_chndly1_t CHnDLY1; /*!< [0x1C] Channel n Delay 1 register */ - uint8_t _reserved0[24]; - } CH[2]; - uint8_t _reserved0[240]; - struct { - __IO hw_pdb_dacintcn_t DACINTCn; /*!< [0x150] DAC Interval Trigger n Control register */ - __IO hw_pdb_dacintn_t DACINTn; /*!< [0x154] DAC Interval n register */ - } DAC[2]; - uint8_t _reserved1[48]; - __IO hw_pdb_poen_t POEN; /*!< [0x190] Pulse-Out n Enable register */ - __IO hw_pdb_pondly_t POnDLY[3]; /*!< [0x194] Pulse-Out n Delay register */ -} hw_pdb_t; -#pragma pack() - -/*! @brief Macro to access all PDB registers. */ -/*! @param x PDB module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PDB(PDB0_BASE). */ -#define HW_PDB(x) (*(hw_pdb_t *)(x)) - -#endif /* __HW_PDB_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pit.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pit.h deleted file mode 100644 index f671bec5faf..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pit.h +++ /dev/null @@ -1,519 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PIT_REGISTERS_H__ -#define __HW_PIT_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 PIT - * - * Periodic Interrupt Timer - * - * Registers defined in this header file: - * - HW_PIT_MCR - PIT Module Control Register - * - HW_PIT_LDVALn - Timer Load Value Register - * - HW_PIT_CVALn - Current Timer Value Register - * - HW_PIT_TCTRLn - Timer Control Register - * - HW_PIT_TFLGn - Timer Flag Register - * - * - hw_pit_t - Struct containing all module registers. - */ - -#define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */ - -/******************************************************************************* - * HW_PIT_MCR - PIT Module Control Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_MCR - PIT Module Control Register (RW) - * - * Reset value: 0x00000006U - * - * This register enables or disables the PIT timer clocks and controls the - * timers when the PIT enters the Debug mode. - */ -typedef union _hw_pit_mcr -{ - uint32_t U; - struct _hw_pit_mcr_bitfields - { - uint32_t FRZ : 1; /*!< [0] Freeze */ - uint32_t MDIS : 1; /*!< [1] Module Disable - (PIT section) */ - uint32_t RESERVED0 : 30; /*!< [31:2] */ - } B; -} hw_pit_mcr_t; - -/*! - * @name Constants and macros for entire PIT_MCR register - */ -/*@{*/ -#define HW_PIT_MCR_ADDR(x) ((x) + 0x0U) - -#define HW_PIT_MCR(x) (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x)) -#define HW_PIT_MCR_RD(x) (HW_PIT_MCR(x).U) -#define HW_PIT_MCR_WR(x, v) (HW_PIT_MCR(x).U = (v)) -#define HW_PIT_MCR_SET(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) | (v))) -#define HW_PIT_MCR_CLR(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v))) -#define HW_PIT_MCR_TOG(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_MCR bitfields - */ - -/*! - * @name Register PIT_MCR, field FRZ[0] (RW) - * - * Allows the timers to be stopped when the device enters the Debug mode. - * - * Values: - * - 0 - Timers continue to run in Debug mode. - * - 1 - Timers are stopped in Debug mode. - */ -/*@{*/ -#define BP_PIT_MCR_FRZ (0U) /*!< Bit position for PIT_MCR_FRZ. */ -#define BM_PIT_MCR_FRZ (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */ -#define BS_PIT_MCR_FRZ (1U) /*!< Bit field size in bits for PIT_MCR_FRZ. */ - -/*! @brief Read current value of the PIT_MCR_FRZ field. */ -#define BR_PIT_MCR_FRZ(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ)) - -/*! @brief Format value for bitfield PIT_MCR_FRZ. */ -#define BF_PIT_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ) - -/*! @brief Set the FRZ field to a new value. */ -#define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v)) -/*@}*/ - -/*! - * @name Register PIT_MCR, field MDIS[1] (RW) - * - * Disables the standard timers. This field must be enabled before any other - * setup is done. - * - * Values: - * - 0 - Clock for standard PIT timers is enabled. - * - 1 - Clock for standard PIT timers is disabled. - */ -/*@{*/ -#define BP_PIT_MCR_MDIS (1U) /*!< Bit position for PIT_MCR_MDIS. */ -#define BM_PIT_MCR_MDIS (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */ -#define BS_PIT_MCR_MDIS (1U) /*!< Bit field size in bits for PIT_MCR_MDIS. */ - -/*! @brief Read current value of the PIT_MCR_MDIS field. */ -#define BR_PIT_MCR_MDIS(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS)) - -/*! @brief Format value for bitfield PIT_MCR_MDIS. */ -#define BF_PIT_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS) - -/*! @brief Set the MDIS field to a new value. */ -#define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_PIT_LDVALn - Timer Load Value Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_LDVALn - Timer Load Value Register (RW) - * - * Reset value: 0x00000000U - * - * These registers select the timeout period for the timer interrupts. - */ -typedef union _hw_pit_ldvaln -{ - uint32_t U; - struct _hw_pit_ldvaln_bitfields - { - uint32_t TSV : 32; /*!< [31:0] Timer Start Value */ - } B; -} hw_pit_ldvaln_t; - -/*! - * @name Constants and macros for entire PIT_LDVALn register - */ -/*@{*/ -#define HW_PIT_LDVALn_COUNT (4U) - -#define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n))) - -#define HW_PIT_LDVALn(x, n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n)) -#define HW_PIT_LDVALn_RD(x, n) (HW_PIT_LDVALn(x, n).U) -#define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v)) -#define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) | (v))) -#define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v))) -#define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_LDVALn bitfields - */ - -/*! - * @name Register PIT_LDVALn, field TSV[31:0] (RW) - * - * Sets the timer start value. The timer will count down until it reaches 0, - * then it will generate an interrupt and load this register value again. Writing a - * new value to this register will not restart the timer; instead the value will - * be loaded after the timer expires. To abort the current cycle and start a - * timer period with the new value, the timer must be disabled and enabled again. - */ -/*@{*/ -#define BP_PIT_LDVALn_TSV (0U) /*!< Bit position for PIT_LDVALn_TSV. */ -#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */ -#define BS_PIT_LDVALn_TSV (32U) /*!< Bit field size in bits for PIT_LDVALn_TSV. */ - -/*! @brief Read current value of the PIT_LDVALn_TSV field. */ -#define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U) - -/*! @brief Format value for bitfield PIT_LDVALn_TSV. */ -#define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV) - -/*! @brief Set the TSV field to a new value. */ -#define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v)) -/*@}*/ -/******************************************************************************* - * HW_PIT_CVALn - Current Timer Value Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_CVALn - Current Timer Value Register (RO) - * - * Reset value: 0x00000000U - * - * These registers indicate the current timer position. - */ -typedef union _hw_pit_cvaln -{ - uint32_t U; - struct _hw_pit_cvaln_bitfields - { - uint32_t TVL : 32; /*!< [31:0] Current Timer Value */ - } B; -} hw_pit_cvaln_t; - -/*! - * @name Constants and macros for entire PIT_CVALn register - */ -/*@{*/ -#define HW_PIT_CVALn_COUNT (4U) - -#define HW_PIT_CVALn_ADDR(x, n) ((x) + 0x104U + (0x10U * (n))) - -#define HW_PIT_CVALn(x, n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n)) -#define HW_PIT_CVALn_RD(x, n) (HW_PIT_CVALn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual PIT_CVALn bitfields - */ - -/*! - * @name Register PIT_CVALn, field TVL[31:0] (RO) - * - * Represents the current timer value, if the timer is enabled. If the timer is - * disabled, do not use this field as its value is unreliable. The timer uses a - * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. - */ -/*@{*/ -#define BP_PIT_CVALn_TVL (0U) /*!< Bit position for PIT_CVALn_TVL. */ -#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */ -#define BS_PIT_CVALn_TVL (32U) /*!< Bit field size in bits for PIT_CVALn_TVL. */ - -/*! @brief Read current value of the PIT_CVALn_TVL field. */ -#define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U) -/*@}*/ -/******************************************************************************* - * HW_PIT_TCTRLn - Timer Control Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_TCTRLn - Timer Control Register (RW) - * - * Reset value: 0x00000000U - * - * These registers contain the control bits for each timer. - */ -typedef union _hw_pit_tctrln -{ - uint32_t U; - struct _hw_pit_tctrln_bitfields - { - uint32_t TEN : 1; /*!< [0] Timer Enable */ - uint32_t TIE : 1; /*!< [1] Timer Interrupt Enable */ - uint32_t CHN : 1; /*!< [2] Chain Mode */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_pit_tctrln_t; - -/*! - * @name Constants and macros for entire PIT_TCTRLn register - */ -/*@{*/ -#define HW_PIT_TCTRLn_COUNT (4U) - -#define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n))) - -#define HW_PIT_TCTRLn(x, n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n)) -#define HW_PIT_TCTRLn_RD(x, n) (HW_PIT_TCTRLn(x, n).U) -#define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v)) -#define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) | (v))) -#define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v))) -#define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_TCTRLn bitfields - */ - -/*! - * @name Register PIT_TCTRLn, field TEN[0] (RW) - * - * Enables or disables the timer. - * - * Values: - * - 0 - Timer n is disabled. - * - 1 - Timer n is enabled. - */ -/*@{*/ -#define BP_PIT_TCTRLn_TEN (0U) /*!< Bit position for PIT_TCTRLn_TEN. */ -#define BM_PIT_TCTRLn_TEN (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */ -#define BS_PIT_TCTRLn_TEN (1U) /*!< Bit field size in bits for PIT_TCTRLn_TEN. */ - -/*! @brief Read current value of the PIT_TCTRLn_TEN field. */ -#define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN)) - -/*! @brief Format value for bitfield PIT_TCTRLn_TEN. */ -#define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN) - -/*! @brief Set the TEN field to a new value. */ -#define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v)) -/*@}*/ - -/*! - * @name Register PIT_TCTRLn, field TIE[1] (RW) - * - * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt - * will immediately cause an interrupt event. To avoid this, the associated - * TFLGn[TIF] must be cleared first. - * - * Values: - * - 0 - Interrupt requests from Timer n are disabled. - * - 1 - Interrupt will be requested whenever TIF is set. - */ -/*@{*/ -#define BP_PIT_TCTRLn_TIE (1U) /*!< Bit position for PIT_TCTRLn_TIE. */ -#define BM_PIT_TCTRLn_TIE (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */ -#define BS_PIT_TCTRLn_TIE (1U) /*!< Bit field size in bits for PIT_TCTRLn_TIE. */ - -/*! @brief Read current value of the PIT_TCTRLn_TIE field. */ -#define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE)) - -/*! @brief Format value for bitfield PIT_TCTRLn_TIE. */ -#define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v)) -/*@}*/ - -/*! - * @name Register PIT_TCTRLn, field CHN[2] (RW) - * - * When activated, Timer n-1 needs to expire before timer n can decrement by 1. - * Timer 0 cannot be chained. - * - * Values: - * - 0 - Timer is not chained. - * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this - * field is set, Timer 2 is chained to Timer 1. - */ -/*@{*/ -#define BP_PIT_TCTRLn_CHN (2U) /*!< Bit position for PIT_TCTRLn_CHN. */ -#define BM_PIT_TCTRLn_CHN (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */ -#define BS_PIT_TCTRLn_CHN (1U) /*!< Bit field size in bits for PIT_TCTRLn_CHN. */ - -/*! @brief Read current value of the PIT_TCTRLn_CHN field. */ -#define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN)) - -/*! @brief Format value for bitfield PIT_TCTRLn_CHN. */ -#define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN) - -/*! @brief Set the CHN field to a new value. */ -#define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v)) -/*@}*/ -/******************************************************************************* - * HW_PIT_TFLGn - Timer Flag Register - ******************************************************************************/ - -/*! - * @brief HW_PIT_TFLGn - Timer Flag Register (RW) - * - * Reset value: 0x00000000U - * - * These registers hold the PIT interrupt flags. - */ -typedef union _hw_pit_tflgn -{ - uint32_t U; - struct _hw_pit_tflgn_bitfields - { - uint32_t TIF : 1; /*!< [0] Timer Interrupt Flag */ - uint32_t RESERVED0 : 31; /*!< [31:1] */ - } B; -} hw_pit_tflgn_t; - -/*! - * @name Constants and macros for entire PIT_TFLGn register - */ -/*@{*/ -#define HW_PIT_TFLGn_COUNT (4U) - -#define HW_PIT_TFLGn_ADDR(x, n) ((x) + 0x10CU + (0x10U * (n))) - -#define HW_PIT_TFLGn(x, n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n)) -#define HW_PIT_TFLGn_RD(x, n) (HW_PIT_TFLGn(x, n).U) -#define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v)) -#define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) | (v))) -#define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v))) -#define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PIT_TFLGn bitfields - */ - -/*! - * @name Register PIT_TFLGn, field TIF[0] (W1C) - * - * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. - * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an - * interrupt request. - * - * Values: - * - 0 - Timeout has not yet occurred. - * - 1 - Timeout has occurred. - */ -/*@{*/ -#define BP_PIT_TFLGn_TIF (0U) /*!< Bit position for PIT_TFLGn_TIF. */ -#define BM_PIT_TFLGn_TIF (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */ -#define BS_PIT_TFLGn_TIF (1U) /*!< Bit field size in bits for PIT_TFLGn_TIF. */ - -/*! @brief Read current value of the PIT_TFLGn_TIF field. */ -#define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF)) - -/*! @brief Format value for bitfield PIT_TFLGn_TIF. */ -#define BF_PIT_TFLGn_TIF(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF) - -/*! @brief Set the TIF field to a new value. */ -#define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_pit_t - module struct - ******************************************************************************/ -/*! - * @brief All PIT module registers. - */ -#pragma pack(1) -typedef struct _hw_pit -{ - __IO hw_pit_mcr_t MCR; /*!< [0x0] PIT Module Control Register */ - uint8_t _reserved0[252]; - struct { - __IO hw_pit_ldvaln_t LDVALn; /*!< [0x100] Timer Load Value Register */ - __I hw_pit_cvaln_t CVALn; /*!< [0x104] Current Timer Value Register */ - __IO hw_pit_tctrln_t TCTRLn; /*!< [0x108] Timer Control Register */ - __IO hw_pit_tflgn_t TFLGn; /*!< [0x10C] Timer Flag Register */ - } CHANNEL[4]; -} hw_pit_t; -#pragma pack() - -/*! @brief Macro to access all PIT registers. */ -/*! @param x PIT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PIT(PIT_BASE). */ -#define HW_PIT(x) (*(hw_pit_t *)(x)) - -#endif /* __HW_PIT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h deleted file mode 100644 index 90d6e2ef556..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h +++ /dev/null @@ -1,575 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PMC_REGISTERS_H__ -#define __HW_PMC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 PMC - * - * Power Management Controller - * - * Registers defined in this header file: - * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register - * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register - * - HW_PMC_REGSC - Regulator Status And Control register - * - * - hw_pmc_t - Struct containing all module registers. - */ - -#define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */ - -/******************************************************************************* - * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register - ******************************************************************************/ - -/*! - * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW) - * - * Reset value: 0x10U - * - * This register contains status and control bits to support the low voltage - * detect function. This register should be written during the reset initialization - * program to set the desired controls even if the desired settings are the same - * as the reset settings. While the device is in the very low power or low - * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect - * systems that must have LVD always on, configure the Power Mode Protection - * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or - * low leakage modes from being enabled. See the device's data sheet for the - * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The - * register's other bits are reset on Chip Reset Not VLLS. For more information - * about these reset types, refer to the Reset section details. - */ -typedef union _hw_pmc_lvdsc1 -{ - uint8_t U; - struct _hw_pmc_lvdsc1_bitfields - { - uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */ - uint8_t RESERVED0 : 2; /*!< [3:2] */ - uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */ - uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */ - uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */ - uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */ - } B; -} hw_pmc_lvdsc1_t; - -/*! - * @name Constants and macros for entire PMC_LVDSC1 register - */ -/*@{*/ -#define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U) - -#define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x)) -#define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U) -#define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v)) -#define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v))) -#define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v))) -#define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PMC_LVDSC1 bitfields - */ - -/*! - * @name Register PMC_LVDSC1, field LVDV[1:0] (RW) - * - * Selects the LVD trip point voltage (V LVD ). - * - * Values: - * - 00 - Low trip point selected (V LVD = V LVDL ) - * - 01 - High trip point selected (V LVD = V LVDH ) - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */ -#define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */ -#define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */ -#define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV) - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */ -#define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV) - -/*! @brief Set the LVDV field to a new value. */ -#define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v))) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDRE[4] (RW) - * - * This write-once bit enables LVDF events to generate a hardware reset. - * Additional writes are ignored. - * - * Values: - * - 0 - LVDF does not generate hardware resets - * - 1 - Force an MCU reset when LVDF = 1 - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */ -#define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */ -#define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */ -#define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE)) - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */ -#define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE) - -/*! @brief Set the LVDRE field to a new value. */ -#define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDIE[5] (RW) - * - * Enables hardware interrupt requests for LVDF. - * - * Values: - * - 0 - Hardware interrupt disabled (use polling) - * - 1 - Request a hardware interrupt when LVDF = 1 - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */ -#define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */ -#define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */ -#define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE)) - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */ -#define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE) - -/*! @brief Set the LVDIE field to a new value. */ -#define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ) - * - * This write-only field is used to acknowledge low voltage detection errors. - * Write 1 to clear LVDF. Reads always return 0. - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */ -#define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */ -#define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */ - -/*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */ -#define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK) - -/*! @brief Set the LVDACK field to a new value. */ -#define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC1, field LVDF[7] (RO) - * - * This read-only status field indicates a low-voltage detect event. - * - * Values: - * - 0 - Low-voltage event not detected - * - 1 - Low-voltage event detected - */ -/*@{*/ -#define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */ -#define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */ -#define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */ - -/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */ -#define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF)) -/*@}*/ - -/******************************************************************************* - * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register - ******************************************************************************/ - -/*! - * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW) - * - * Reset value: 0x00U - * - * This register contains status and control bits to support the low voltage - * warning function. While the device is in the very low power or low leakage modes, - * the LVD system is disabled regardless of LVDSC2 settings. See the device's - * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV - * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the - * register are reset on Chip Reset Not VLLS. For more information about these - * reset types, refer to the Reset section details. - */ -typedef union _hw_pmc_lvdsc2 -{ - uint8_t U; - struct _hw_pmc_lvdsc2_bitfields - { - uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */ - uint8_t RESERVED0 : 3; /*!< [4:2] */ - uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */ - uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */ - uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */ - } B; -} hw_pmc_lvdsc2_t; - -/*! - * @name Constants and macros for entire PMC_LVDSC2 register - */ -/*@{*/ -#define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U) - -#define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x)) -#define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U) -#define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v)) -#define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v))) -#define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v))) -#define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PMC_LVDSC2 bitfields - */ - -/*! - * @name Register PMC_LVDSC2, field LVWV[1:0] (RW) - * - * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning - * depends on LVDSC1[LVDV]. - * - * Values: - * - 00 - Low trip point selected (VLVW = VLVW1) - * - 01 - Mid 1 trip point selected (VLVW = VLVW2) - * - 10 - Mid 2 trip point selected (VLVW = VLVW3) - * - 11 - High trip point selected (VLVW = VLVW4) - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */ -#define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */ -#define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */ - -/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */ -#define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV) - -/*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */ -#define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV) - -/*! @brief Set the LVWV field to a new value. */ -#define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v))) -/*@}*/ - -/*! - * @name Register PMC_LVDSC2, field LVWIE[5] (RW) - * - * Enables hardware interrupt requests for LVWF. - * - * Values: - * - 0 - Hardware interrupt disabled (use polling) - * - 1 - Request a hardware interrupt when LVWF = 1 - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */ -#define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */ -#define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */ - -/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */ -#define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE)) - -/*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */ -#define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE) - -/*! @brief Set the LVWIE field to a new value. */ -#define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ) - * - * This write-only field is used to acknowledge low voltage warning errors. - * Write 1 to clear LVWF. Reads always return 0. - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */ -#define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */ -#define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */ - -/*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */ -#define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK) - -/*! @brief Set the LVWACK field to a new value. */ -#define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v)) -/*@}*/ - -/*! - * @name Register PMC_LVDSC2, field LVWF[7] (RO) - * - * This read-only status field indicates a low-voltage warning event. LVWF is - * set when VSupply transitions below the trip point, or after reset and VSupply is - * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW - * interrupt function, before enabling LVWIE, LVWF must be cleared by writing - * LVWACK first. - * - * Values: - * - 0 - Low-voltage warning event not detected - * - 1 - Low-voltage warning event detected - */ -/*@{*/ -#define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */ -#define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */ -#define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */ - -/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */ -#define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF)) -/*@}*/ - -/******************************************************************************* - * HW_PMC_REGSC - Regulator Status And Control register - ******************************************************************************/ - -/*! - * @brief HW_PMC_REGSC - Regulator Status And Control register (RW) - * - * Reset value: 0x04U - * - * The PMC contains an internal voltage regulator. The voltage regulator design - * uses a bandgap reference that is also available through a buffer as input to - * certain internal peripherals, such as the CMP and ADC. The internal regulator - * provides a status bit (REGONS) indicating the regulator is in run regulation. - * This register is reset on Chip Reset Not VLLS and by reset types that trigger - * Chip Reset not VLLS. See the Reset section details for more information. - */ -typedef union _hw_pmc_regsc -{ - uint8_t U; - struct _hw_pmc_regsc_bitfields - { - uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */ - uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */ - uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_pmc_regsc_t; - -/*! - * @name Constants and macros for entire PMC_REGSC register - */ -/*@{*/ -#define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U) - -#define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x)) -#define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U) -#define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v)) -#define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v))) -#define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v))) -#define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PMC_REGSC bitfields - */ - -/*! - * @name Register PMC_REGSC, field BGBE[0] (RW) - * - * Enables the bandgap buffer. - * - * Values: - * - 0 - Bandgap buffer not enabled - * - 1 - Bandgap buffer enabled - */ -/*@{*/ -#define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */ -#define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */ -#define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */ - -/*! @brief Read current value of the PMC_REGSC_BGBE field. */ -#define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE)) - -/*! @brief Format value for bitfield PMC_REGSC_BGBE. */ -#define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE) - -/*! @brief Set the BGBE field to a new value. */ -#define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v)) -/*@}*/ - -/*! - * @name Register PMC_REGSC, field REGONS[2] (RO) - * - * This read-only field provides the current status of the internal voltage - * regulator. - * - * Values: - * - 0 - Regulator is in stop regulation or in transition to/from it - * - 1 - Regulator is in run regulation - */ -/*@{*/ -#define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */ -#define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */ -#define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */ - -/*! @brief Read current value of the PMC_REGSC_REGONS field. */ -#define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS)) -/*@}*/ - -/*! - * @name Register PMC_REGSC, field ACKISO[3] (W1C) - * - * Reading this field indicates whether certain peripherals and the I/O pads are - * in a latched state as a result of having been in a VLLS mode. Writing 1 to - * this field when it is set releases the I/O pads and certain peripherals to their - * normal run mode state. After recovering from a VLLS mode, user should restore - * chip configuration before clearing ACKISO. In particular, pin configuration - * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from - * being falsely set when ACKISO is cleared. - * - * Values: - * - 0 - Peripherals and I/O pads are in normal run state. - * - 1 - Certain peripherals and I/O pads are in an isolated and latched state. - */ -/*@{*/ -#define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */ -#define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */ -#define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */ - -/*! @brief Read current value of the PMC_REGSC_ACKISO field. */ -#define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO)) - -/*! @brief Format value for bitfield PMC_REGSC_ACKISO. */ -#define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO) - -/*! @brief Set the ACKISO field to a new value. */ -#define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v)) -/*@}*/ - -/*! - * @name Register PMC_REGSC, field BGEN[4] (RW) - * - * BGEN controls whether the bandgap is enabled in lower power modes of - * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage - * reference in low power modes of operation, set BGEN to continue to enable the - * bandgap operation. When the bandgap voltage reference is not needed in low - * power modes, clear BGEN to avoid excess power consumption. - * - * Values: - * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. - * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. - */ -/*@{*/ -#define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */ -#define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */ -#define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */ - -/*! @brief Read current value of the PMC_REGSC_BGEN field. */ -#define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN)) - -/*! @brief Format value for bitfield PMC_REGSC_BGEN. */ -#define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN) - -/*! @brief Set the BGEN field to a new value. */ -#define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_pmc_t - module struct - ******************************************************************************/ -/*! - * @brief All PMC module registers. - */ -#pragma pack(1) -typedef struct _hw_pmc -{ - __IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */ - __IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */ - __IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */ -} hw_pmc_t; -#pragma pack() - -/*! @brief Macro to access all PMC registers. */ -/*! @param x PMC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PMC(PMC_BASE). */ -#define HW_PMC(x) (*(hw_pmc_t *)(x)) - -#endif /* __HW_PMC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_port.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_port.h deleted file mode 100644 index 16a7015df72..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_port.h +++ /dev/null @@ -1,895 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_PORT_REGISTERS_H__ -#define __HW_PORT_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 PORT - * - * Pin Control and Interrupts - * - * Registers defined in this header file: - * - HW_PORT_PCRn - Pin Control Register n - * - HW_PORT_GPCLR - Global Pin Control Low Register - * - HW_PORT_GPCHR - Global Pin Control High Register - * - HW_PORT_ISFR - Interrupt Status Flag Register - * - HW_PORT_DFER - Digital Filter Enable Register - * - HW_PORT_DFCR - Digital Filter Clock Register - * - HW_PORT_DFWR - Digital Filter Width Register - * - * - hw_port_t - Struct containing all module registers. - */ - -#define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */ -#define HW_PORTA (0U) /*!< Instance number for PORTA. */ -#define HW_PORTB (1U) /*!< Instance number for PORTB. */ -#define HW_PORTC (2U) /*!< Instance number for PORTC. */ -#define HW_PORTD (3U) /*!< Instance number for PORTD. */ -#define HW_PORTE (4U) /*!< Instance number for PORTE. */ - -/******************************************************************************* - * HW_PORT_PCRn - Pin Control Register n - ******************************************************************************/ - -/*! - * @brief HW_PORT_PCRn - Pin Control Register n (RW) - * - * Reset value: 0x00000742U - * - * See the Signal Multiplexing and Pin Assignment chapter for the reset value of - * this device. See the GPIO Configuration section for details on the available - * functions for each pin. Do not modify pin configuration registers associated - * with pins not available in your selected package. All unbonded pins not - * available in your package will default to DISABLE state for lowest power consumption. - */ -typedef union _hw_port_pcrn -{ - uint32_t U; - struct _hw_port_pcrn_bitfields - { - uint32_t PS : 1; /*!< [0] Pull Select */ - uint32_t PE : 1; /*!< [1] Pull Enable */ - uint32_t SRE : 1; /*!< [2] Slew Rate Enable */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t PFE : 1; /*!< [4] Passive Filter Enable */ - uint32_t ODE : 1; /*!< [5] Open Drain Enable */ - uint32_t DSE : 1; /*!< [6] Drive Strength Enable */ - uint32_t RESERVED1 : 1; /*!< [7] */ - uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */ - uint32_t RESERVED2 : 4; /*!< [14:11] */ - uint32_t LK : 1; /*!< [15] Lock Register */ - uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */ - uint32_t RESERVED3 : 4; /*!< [23:20] */ - uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */ - uint32_t RESERVED4 : 7; /*!< [31:25] */ - } B; -} hw_port_pcrn_t; - -/*! - * @name Constants and macros for entire PORT_PCRn register - */ -/*@{*/ -#define HW_PORT_PCRn_COUNT (32U) - -#define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n))) - -#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n)) -#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U) -#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v)) -#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v))) -#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v))) -#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_PCRn bitfields - */ - -/*! - * @name Register PORT_PCRn, field PS[0] (RW) - * - * Pull configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the - * corresponding PE field is set. - * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the - * corresponding PE field is set. - */ -/*@{*/ -#define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */ -#define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */ -#define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */ - -/*! @brief Read current value of the PORT_PCRn_PS field. */ -#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS)) - -/*! @brief Format value for bitfield PORT_PCRn_PS. */ -#define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS) - -/*! @brief Set the PS field to a new value. */ -#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field PE[1] (RW) - * - * Pull configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Internal pullup or pulldown resistor is not enabled on the - * corresponding pin. - * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding - * pin, if the pin is configured as a digital input. - */ -/*@{*/ -#define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */ -#define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */ -#define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */ - -/*! @brief Read current value of the PORT_PCRn_PE field. */ -#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE)) - -/*! @brief Format value for bitfield PORT_PCRn_PE. */ -#define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE) - -/*! @brief Set the PE field to a new value. */ -#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field SRE[2] (RW) - * - * Slew rate configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is - * configured as a digital output. - * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is - * configured as a digital output. - */ -/*@{*/ -#define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */ -#define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */ -#define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */ - -/*! @brief Read current value of the PORT_PCRn_SRE field. */ -#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE)) - -/*! @brief Format value for bitfield PORT_PCRn_SRE. */ -#define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE) - -/*! @brief Set the SRE field to a new value. */ -#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field PFE[4] (RW) - * - * Passive filter configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Passive input filter is disabled on the corresponding pin. - * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is - * configured as a digital input. Refer to the device data sheet for filter - * characteristics. - */ -/*@{*/ -#define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */ -#define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */ -#define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */ - -/*! @brief Read current value of the PORT_PCRn_PFE field. */ -#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE)) - -/*! @brief Format value for bitfield PORT_PCRn_PFE. */ -#define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE) - -/*! @brief Set the PFE field to a new value. */ -#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field ODE[5] (RW) - * - * Open drain configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Open drain output is disabled on the corresponding pin. - * - 1 - Open drain output is enabled on the corresponding pin, if the pin is - * configured as a digital output. - */ -/*@{*/ -#define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */ -#define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */ -#define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */ - -/*! @brief Read current value of the PORT_PCRn_ODE field. */ -#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE)) - -/*! @brief Format value for bitfield PORT_PCRn_ODE. */ -#define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE) - -/*! @brief Set the ODE field to a new value. */ -#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field DSE[6] (RW) - * - * Drive strength configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Low drive strength is configured on the corresponding pin, if pin is - * configured as a digital output. - * - 1 - High drive strength is configured on the corresponding pin, if pin is - * configured as a digital output. - */ -/*@{*/ -#define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */ -#define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */ -#define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */ - -/*! @brief Read current value of the PORT_PCRn_DSE field. */ -#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE)) - -/*! @brief Format value for bitfield PORT_PCRn_DSE. */ -#define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE) - -/*! @brief Set the DSE field to a new value. */ -#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field MUX[10:8] (RW) - * - * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are - * reserved and may result in configuring the pin for a different pin muxing - * slot. The corresponding pin is configured in the following pin muxing slot as - * follows: - * - * Values: - * - 000 - Pin disabled (analog). - * - 001 - Alternative 1 (GPIO). - * - 010 - Alternative 2 (chip-specific). - * - 011 - Alternative 3 (chip-specific). - * - 100 - Alternative 4 (chip-specific). - * - 101 - Alternative 5 (chip-specific). - * - 110 - Alternative 6 (chip-specific). - * - 111 - Alternative 7 (chip-specific). - */ -/*@{*/ -#define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */ -#define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */ -#define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */ - -/*! @brief Read current value of the PORT_PCRn_MUX field. */ -#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX) - -/*! @brief Format value for bitfield PORT_PCRn_MUX. */ -#define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX) - -/*! @brief Set the MUX field to a new value. */ -#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v))) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field LK[15] (RW) - * - * Values: - * - 0 - Pin Control Register fields [15:0] are not locked. - * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated - * until the next system reset. - */ -/*@{*/ -#define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */ -#define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */ -#define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */ - -/*! @brief Read current value of the PORT_PCRn_LK field. */ -#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK)) - -/*! @brief Format value for bitfield PORT_PCRn_LK. */ -#define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK) - -/*! @brief Set the LK field to a new value. */ -#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v)) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field IRQC[19:16] (RW) - * - * The pin interrupt configuration is valid in all digital pin muxing modes. The - * corresponding pin is configured to generate interrupt/DMA request as follows: - * - * Values: - * - 0000 - Interrupt/DMA request disabled. - * - 0001 - DMA request on rising edge. - * - 0010 - DMA request on falling edge. - * - 0011 - DMA request on either edge. - * - 1000 - Interrupt when logic 0. - * - 1001 - Interrupt on rising-edge. - * - 1010 - Interrupt on falling-edge. - * - 1011 - Interrupt on either edge. - * - 1100 - Interrupt when logic 1. - */ -/*@{*/ -#define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */ -#define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */ -#define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */ - -/*! @brief Read current value of the PORT_PCRn_IRQC field. */ -#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC) - -/*! @brief Format value for bitfield PORT_PCRn_IRQC. */ -#define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC) - -/*! @brief Set the IRQC field to a new value. */ -#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v))) -/*@}*/ - -/*! - * @name Register PORT_PCRn, field ISF[24] (W1C) - * - * The pin interrupt configuration is valid in all digital pin muxing modes. - * - * Values: - * - 0 - Configured interrupt is not detected. - * - 1 - Configured interrupt is detected. If the pin is configured to generate - * a DMA request, then the corresponding flag will be cleared automatically - * at the completion of the requested DMA transfer. Otherwise, the flag - * remains set until a logic 1 is written to the flag. If the pin is configured for - * a level sensitive interrupt and the pin remains asserted, then the flag - * is set again immediately after it is cleared. - */ -/*@{*/ -#define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */ -#define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */ -#define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */ - -/*! @brief Read current value of the PORT_PCRn_ISF field. */ -#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF)) - -/*! @brief Format value for bitfield PORT_PCRn_ISF. */ -#define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF) - -/*! @brief Set the ISF field to a new value. */ -#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_GPCLR - Global Pin Control Low Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ) - * - * Reset value: 0x00000000U - * - * Only 32-bit writes are supported to this register. - */ -typedef union _hw_port_gpclr -{ - uint32_t U; - struct _hw_port_gpclr_bitfields - { - uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */ - uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */ - } B; -} hw_port_gpclr_t; - -/*! - * @name Constants and macros for entire PORT_GPCLR register - */ -/*@{*/ -#define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U) - -#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x)) -#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U) -#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual PORT_GPCLR bitfields - */ - -/*! - * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ) - * - * Write value that is written to all Pin Control Registers bits [15:0] that are - * selected by GPWE. - */ -/*@{*/ -#define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */ -#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */ -#define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */ - -/*! @brief Format value for bitfield PORT_GPCLR_GPWD. */ -#define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD) - -/*! @brief Set the GPWD field to a new value. */ -#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v))) -/*@}*/ - -/*! - * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ) - * - * Selects which Pin Control Registers (15 through 0) bits [15:0] update with - * the value in GPWD. If a selected Pin Control Register is locked then the write - * to that register is ignored. - * - * Values: - * - 0 - Corresponding Pin Control Register is not updated with the value in - * GPWD. - * - 1 - Corresponding Pin Control Register is updated with the value in GPWD. - */ -/*@{*/ -#define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */ -#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */ -#define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */ - -/*! @brief Format value for bitfield PORT_GPCLR_GPWE. */ -#define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE) - -/*! @brief Set the GPWE field to a new value. */ -#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v))) -/*@}*/ - -/******************************************************************************* - * HW_PORT_GPCHR - Global Pin Control High Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ) - * - * Reset value: 0x00000000U - * - * Only 32-bit writes are supported to this register. - */ -typedef union _hw_port_gpchr -{ - uint32_t U; - struct _hw_port_gpchr_bitfields - { - uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */ - uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */ - } B; -} hw_port_gpchr_t; - -/*! - * @name Constants and macros for entire PORT_GPCHR register - */ -/*@{*/ -#define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U) - -#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x)) -#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U) -#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual PORT_GPCHR bitfields - */ - -/*! - * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ) - * - * Write value that is written to all Pin Control Registers bits [15:0] that are - * selected by GPWE. - */ -/*@{*/ -#define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */ -#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */ -#define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */ - -/*! @brief Format value for bitfield PORT_GPCHR_GPWD. */ -#define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD) - -/*! @brief Set the GPWD field to a new value. */ -#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v))) -/*@}*/ - -/*! - * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ) - * - * Selects which Pin Control Registers (31 through 16) bits [15:0] update with - * the value in GPWD. If a selected Pin Control Register is locked then the write - * to that register is ignored. - * - * Values: - * - 0 - Corresponding Pin Control Register is not updated with the value in - * GPWD. - * - 1 - Corresponding Pin Control Register is updated with the value in GPWD. - */ -/*@{*/ -#define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */ -#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */ -#define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */ - -/*! @brief Format value for bitfield PORT_GPCHR_GPWE. */ -#define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE) - -/*! @brief Set the GPWE field to a new value. */ -#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v))) -/*@}*/ - -/******************************************************************************* - * HW_PORT_ISFR - Interrupt Status Flag Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C) - * - * Reset value: 0x00000000U - * - * The pin interrupt configuration is valid in all digital pin muxing modes. The - * Interrupt Status Flag for each pin is also visible in the corresponding Pin - * Control Register, and each flag can be cleared in either location. - */ -typedef union _hw_port_isfr -{ - uint32_t U; - struct _hw_port_isfr_bitfields - { - uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */ - } B; -} hw_port_isfr_t; - -/*! - * @name Constants and macros for entire PORT_ISFR register - */ -/*@{*/ -#define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U) - -#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x)) -#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U) -#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v)) -#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v))) -#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v))) -#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_ISFR bitfields - */ - -/*! - * @name Register PORT_ISFR, field ISF[31:0] (W1C) - * - * Each bit in the field indicates the detection of the configured interrupt of - * the same number as the field. - * - * Values: - * - 0 - Configured interrupt is not detected. - * - 1 - Configured interrupt is detected. If the pin is configured to generate - * a DMA request, then the corresponding flag will be cleared automatically - * at the completion of the requested DMA transfer. Otherwise, the flag - * remains set until a logic 1 is written to the flag. If the pin is configured for - * a level sensitive interrupt and the pin remains asserted, then the flag - * is set again immediately after it is cleared. - */ -/*@{*/ -#define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */ -#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */ -#define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */ - -/*! @brief Read current value of the PORT_ISFR_ISF field. */ -#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U) - -/*! @brief Format value for bitfield PORT_ISFR_ISF. */ -#define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF) - -/*! @brief Set the ISF field to a new value. */ -#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_DFER - Digital Filter Enable Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_DFER - Digital Filter Enable Register (RW) - * - * Reset value: 0x00000000U - * - * The corresponding bit is read only for pins that do not support a digital - * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for - * the pins that support digital filter. The digital filter configuration is valid - * in all digital pin muxing modes. - */ -typedef union _hw_port_dfer -{ - uint32_t U; - struct _hw_port_dfer_bitfields - { - uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */ - } B; -} hw_port_dfer_t; - -/*! - * @name Constants and macros for entire PORT_DFER register - */ -/*@{*/ -#define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U) - -#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x)) -#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U) -#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v)) -#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v))) -#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v))) -#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_DFER bitfields - */ - -/*! - * @name Register PORT_DFER, field DFE[31:0] (RW) - * - * The digital filter configuration is valid in all digital pin muxing modes. - * The output of each digital filter is reset to zero at system reset and whenever - * the digital filter is disabled. Each bit in the field enables the digital - * filter of the same number as the field. - * - * Values: - * - 0 - Digital filter is disabled on the corresponding pin and output of the - * digital filter is reset to zero. - * - 1 - Digital filter is enabled on the corresponding pin, if the pin is - * configured as a digital input. - */ -/*@{*/ -#define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */ -#define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */ -#define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */ - -/*! @brief Read current value of the PORT_DFER_DFE field. */ -#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U) - -/*! @brief Format value for bitfield PORT_DFER_DFE. */ -#define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE) - -/*! @brief Set the DFE field to a new value. */ -#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_DFCR - Digital Filter Clock Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW) - * - * Reset value: 0x00000000U - * - * This register is read only for ports that do not support a digital filter. - * The digital filter configuration is valid in all digital pin muxing modes. - */ -typedef union _hw_port_dfcr -{ - uint32_t U; - struct _hw_port_dfcr_bitfields - { - uint32_t CS : 1; /*!< [0] Clock Source */ - uint32_t RESERVED0 : 31; /*!< [31:1] */ - } B; -} hw_port_dfcr_t; - -/*! - * @name Constants and macros for entire PORT_DFCR register - */ -/*@{*/ -#define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U) - -#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x)) -#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U) -#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v)) -#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v))) -#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v))) -#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_DFCR bitfields - */ - -/*! - * @name Register PORT_DFCR, field CS[0] (RW) - * - * The digital filter configuration is valid in all digital pin muxing modes. - * Configures the clock source for the digital input filters. Changing the filter - * clock source must be done only when all digital filters are disabled. - * - * Values: - * - 0 - Digital filters are clocked by the bus clock. - * - 1 - Digital filters are clocked by the 1 kHz LPO clock. - */ -/*@{*/ -#define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */ -#define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */ -#define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */ - -/*! @brief Read current value of the PORT_DFCR_CS field. */ -#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS)) - -/*! @brief Format value for bitfield PORT_DFCR_CS. */ -#define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS) - -/*! @brief Set the CS field to a new value. */ -#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_PORT_DFWR - Digital Filter Width Register - ******************************************************************************/ - -/*! - * @brief HW_PORT_DFWR - Digital Filter Width Register (RW) - * - * Reset value: 0x00000000U - * - * This register is read only for ports that do not support a digital filter. - * The digital filter configuration is valid in all digital pin muxing modes. - */ -typedef union _hw_port_dfwr -{ - uint32_t U; - struct _hw_port_dfwr_bitfields - { - uint32_t FILT : 5; /*!< [4:0] Filter Length */ - uint32_t RESERVED0 : 27; /*!< [31:5] */ - } B; -} hw_port_dfwr_t; - -/*! - * @name Constants and macros for entire PORT_DFWR register - */ -/*@{*/ -#define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U) - -#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x)) -#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U) -#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v)) -#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v))) -#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v))) -#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual PORT_DFWR bitfields - */ - -/*! - * @name Register PORT_DFWR, field FILT[4:0] (RW) - * - * The digital filter configuration is valid in all digital pin muxing modes. - * Configures the maximum size of the glitches, in clock cycles, that the digital - * filter absorbs for the enabled digital filters. Glitches that are longer than - * this register setting will pass through the digital filter, and glitches that - * are equal to or less than this register setting are filtered. Changing the - * filter length must be done only after all filters are disabled. - */ -/*@{*/ -#define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */ -#define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */ -#define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */ - -/*! @brief Read current value of the PORT_DFWR_FILT field. */ -#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT) - -/*! @brief Format value for bitfield PORT_DFWR_FILT. */ -#define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT) - -/*! @brief Set the FILT field to a new value. */ -#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v))) -/*@}*/ - -/******************************************************************************* - * hw_port_t - module struct - ******************************************************************************/ -/*! - * @brief All PORT module registers. - */ -#pragma pack(1) -typedef struct _hw_port -{ - __IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */ - __O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */ - __O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */ - uint8_t _reserved0[24]; - __IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */ - uint8_t _reserved1[28]; - __IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */ - __IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */ - __IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */ -} hw_port_t; -#pragma pack() - -/*! @brief Macro to access all PORT registers. */ -/*! @param x PORT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_PORT(PORTA_BASE). */ -#define HW_PORT(x) (*(hw_port_t *)(x)) - -#endif /* __HW_PORT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rcm.h deleted file mode 100644 index 23ceaaeb8e7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rcm.h +++ /dev/null @@ -1,722 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RCM_REGISTERS_H__ -#define __HW_RCM_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 RCM - * - * Reset Control Module - * - * Registers defined in this header file: - * - HW_RCM_SRS0 - System Reset Status Register 0 - * - HW_RCM_SRS1 - System Reset Status Register 1 - * - HW_RCM_RPFC - Reset Pin Filter Control register - * - HW_RCM_RPFW - Reset Pin Filter Width register - * - HW_RCM_MR - Mode Register - * - * - hw_rcm_t - Struct containing all module registers. - */ - -#define HW_RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */ - -/******************************************************************************* - * HW_RCM_SRS0 - System Reset Status Register 0 - ******************************************************************************/ - -/*! - * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO) - * - * Reset value: 0x82U - * - * This register includes read-only status flags to indicate the source of the - * most recent reset. The reset state of these bits depends on what caused the MCU - * to reset. The reset value of this register depends on the reset source: POR - * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET - * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other - * reset - a bit is set if its corresponding reset source caused the reset - */ -typedef union _hw_rcm_srs0 -{ - uint8_t U; - struct _hw_rcm_srs0_bitfields - { - uint8_t WAKEUP : 1; /*!< [0] Low Leakage Wakeup Reset */ - uint8_t LVD : 1; /*!< [1] Low-Voltage Detect Reset */ - uint8_t LOC : 1; /*!< [2] Loss-of-Clock Reset */ - uint8_t LOL : 1; /*!< [3] Loss-of-Lock Reset */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t WDOGb : 1; /*!< [5] Watchdog */ - uint8_t PIN : 1; /*!< [6] External Reset Pin */ - uint8_t POR : 1; /*!< [7] Power-On Reset */ - } B; -} hw_rcm_srs0_t; - -/*! - * @name Constants and macros for entire RCM_SRS0 register - */ -/*@{*/ -#define HW_RCM_SRS0_ADDR(x) ((x) + 0x0U) - -#define HW_RCM_SRS0(x) (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR(x)) -#define HW_RCM_SRS0_RD(x) (HW_RCM_SRS0(x).U) -/*@}*/ - -/* - * Constants & macros for individual RCM_SRS0 bitfields - */ - -/*! - * @name Register RCM_SRS0, field WAKEUP[0] (RO) - * - * Indicates a reset has been caused by an enabled LLWU module wakeup source - * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only - * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx - * mode causes a reset. This bit is cleared by any reset except WAKEUP. - * - * Values: - * - 0 - Reset not caused by LLWU module wakeup source - * - 1 - Reset caused by LLWU module wakeup source - */ -/*@{*/ -#define BP_RCM_SRS0_WAKEUP (0U) /*!< Bit position for RCM_SRS0_WAKEUP. */ -#define BM_RCM_SRS0_WAKEUP (0x01U) /*!< Bit mask for RCM_SRS0_WAKEUP. */ -#define BS_RCM_SRS0_WAKEUP (1U) /*!< Bit field size in bits for RCM_SRS0_WAKEUP. */ - -/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */ -#define BR_RCM_SRS0_WAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WAKEUP)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field LVD[1] (RO) - * - * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, - * an LVD reset occurs. This field is also set by POR. - * - * Values: - * - 0 - Reset not caused by LVD trip or POR - * - 1 - Reset caused by LVD trip or POR - */ -/*@{*/ -#define BP_RCM_SRS0_LVD (1U) /*!< Bit position for RCM_SRS0_LVD. */ -#define BM_RCM_SRS0_LVD (0x02U) /*!< Bit mask for RCM_SRS0_LVD. */ -#define BS_RCM_SRS0_LVD (1U) /*!< Bit field size in bits for RCM_SRS0_LVD. */ - -/*! @brief Read current value of the RCM_SRS0_LVD field. */ -#define BR_RCM_SRS0_LVD(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LVD)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field LOC[2] (RO) - * - * Indicates a reset has been caused by a loss of external clock. The MCG clock - * monitor must be enabled for a loss of clock to be detected. Refer to the - * detailed MCG description for information on enabling the clock monitor. - * - * Values: - * - 0 - Reset not caused by a loss of external clock. - * - 1 - Reset caused by a loss of external clock. - */ -/*@{*/ -#define BP_RCM_SRS0_LOC (2U) /*!< Bit position for RCM_SRS0_LOC. */ -#define BM_RCM_SRS0_LOC (0x04U) /*!< Bit mask for RCM_SRS0_LOC. */ -#define BS_RCM_SRS0_LOC (1U) /*!< Bit field size in bits for RCM_SRS0_LOC. */ - -/*! @brief Read current value of the RCM_SRS0_LOC field. */ -#define BR_RCM_SRS0_LOC(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field LOL[3] (RO) - * - * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the - * MCG description for information on the loss-of-clock event. - * - * Values: - * - 0 - Reset not caused by a loss of lock in the PLL - * - 1 - Reset caused by a loss of lock in the PLL - */ -/*@{*/ -#define BP_RCM_SRS0_LOL (3U) /*!< Bit position for RCM_SRS0_LOL. */ -#define BM_RCM_SRS0_LOL (0x08U) /*!< Bit mask for RCM_SRS0_LOL. */ -#define BS_RCM_SRS0_LOL (1U) /*!< Bit field size in bits for RCM_SRS0_LOL. */ - -/*! @brief Read current value of the RCM_SRS0_LOL field. */ -#define BR_RCM_SRS0_LOL(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field WDOG[5] (RO) - * - * Indicates a reset has been caused by the watchdog timer Computer Operating - * Properly (COP) timing out. This reset source can be blocked by disabling the COP - * watchdog: write 00 to SIM_COPCTRL[COPT]. - * - * Values: - * - 0 - Reset not caused by watchdog timeout - * - 1 - Reset caused by watchdog timeout - */ -/*@{*/ -#define BP_RCM_SRS0_WDOG (5U) /*!< Bit position for RCM_SRS0_WDOG. */ -#define BM_RCM_SRS0_WDOG (0x20U) /*!< Bit mask for RCM_SRS0_WDOG. */ -#define BS_RCM_SRS0_WDOG (1U) /*!< Bit field size in bits for RCM_SRS0_WDOG. */ - -/*! @brief Read current value of the RCM_SRS0_WDOG field. */ -#define BR_RCM_SRS0_WDOG(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WDOG)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field PIN[6] (RO) - * - * Indicates a reset has been caused by an active-low level on the external - * RESET pin. - * - * Values: - * - 0 - Reset not caused by external reset pin - * - 1 - Reset caused by external reset pin - */ -/*@{*/ -#define BP_RCM_SRS0_PIN (6U) /*!< Bit position for RCM_SRS0_PIN. */ -#define BM_RCM_SRS0_PIN (0x40U) /*!< Bit mask for RCM_SRS0_PIN. */ -#define BS_RCM_SRS0_PIN (1U) /*!< Bit field size in bits for RCM_SRS0_PIN. */ - -/*! @brief Read current value of the RCM_SRS0_PIN field. */ -#define BR_RCM_SRS0_PIN(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_PIN)) -/*@}*/ - -/*! - * @name Register RCM_SRS0, field POR[7] (RO) - * - * Indicates a reset has been caused by the power-on detection logic. Because - * the internal supply voltage was ramping up at the time, the low-voltage reset - * (LVD) status bit is also set to indicate that the reset occurred while the - * internal supply was below the LVD threshold. - * - * Values: - * - 0 - Reset not caused by POR - * - 1 - Reset caused by POR - */ -/*@{*/ -#define BP_RCM_SRS0_POR (7U) /*!< Bit position for RCM_SRS0_POR. */ -#define BM_RCM_SRS0_POR (0x80U) /*!< Bit mask for RCM_SRS0_POR. */ -#define BS_RCM_SRS0_POR (1U) /*!< Bit field size in bits for RCM_SRS0_POR. */ - -/*! @brief Read current value of the RCM_SRS0_POR field. */ -#define BR_RCM_SRS0_POR(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_POR)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_SRS1 - System Reset Status Register 1 - ******************************************************************************/ - -/*! - * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO) - * - * Reset value: 0x00U - * - * This register includes read-only status flags to indicate the source of the - * most recent reset. The reset state of these bits depends on what caused the MCU - * to reset. The reset value of this register depends on the reset source: POR - * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other - * reset - a bit is set if its corresponding reset source caused the reset - */ -typedef union _hw_rcm_srs1 -{ - uint8_t U; - struct _hw_rcm_srs1_bitfields - { - uint8_t JTAG : 1; /*!< [0] JTAG Generated Reset */ - uint8_t LOCKUP : 1; /*!< [1] Core Lockup */ - uint8_t SW : 1; /*!< [2] Software */ - uint8_t MDM_AP : 1; /*!< [3] MDM-AP System Reset Request */ - uint8_t EZPT : 1; /*!< [4] EzPort Reset */ - uint8_t SACKERR : 1; /*!< [5] Stop Mode Acknowledge Error Reset */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_rcm_srs1_t; - -/*! - * @name Constants and macros for entire RCM_SRS1 register - */ -/*@{*/ -#define HW_RCM_SRS1_ADDR(x) ((x) + 0x1U) - -#define HW_RCM_SRS1(x) (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR(x)) -#define HW_RCM_SRS1_RD(x) (HW_RCM_SRS1(x).U) -/*@}*/ - -/* - * Constants & macros for individual RCM_SRS1 bitfields - */ - -/*! - * @name Register RCM_SRS1, field JTAG[0] (RO) - * - * Indicates a reset has been caused by JTAG selection of certain IR codes: - * EZPORT, EXTEST, HIGHZ, and CLAMP. - * - * Values: - * - 0 - Reset not caused by JTAG - * - 1 - Reset caused by JTAG - */ -/*@{*/ -#define BP_RCM_SRS1_JTAG (0U) /*!< Bit position for RCM_SRS1_JTAG. */ -#define BM_RCM_SRS1_JTAG (0x01U) /*!< Bit mask for RCM_SRS1_JTAG. */ -#define BS_RCM_SRS1_JTAG (1U) /*!< Bit field size in bits for RCM_SRS1_JTAG. */ - -/*! @brief Read current value of the RCM_SRS1_JTAG field. */ -#define BR_RCM_SRS1_JTAG(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_JTAG)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field LOCKUP[1] (RO) - * - * Indicates a reset has been caused by the ARM core indication of a LOCKUP - * event. - * - * Values: - * - 0 - Reset not caused by core LOCKUP event - * - 1 - Reset caused by core LOCKUP event - */ -/*@{*/ -#define BP_RCM_SRS1_LOCKUP (1U) /*!< Bit position for RCM_SRS1_LOCKUP. */ -#define BM_RCM_SRS1_LOCKUP (0x02U) /*!< Bit mask for RCM_SRS1_LOCKUP. */ -#define BS_RCM_SRS1_LOCKUP (1U) /*!< Bit field size in bits for RCM_SRS1_LOCKUP. */ - -/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */ -#define BR_RCM_SRS1_LOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_LOCKUP)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field SW[2] (RO) - * - * Indicates a reset has been caused by software setting of SYSRESETREQ bit in - * Application Interrupt and Reset Control Register in the ARM core. - * - * Values: - * - 0 - Reset not caused by software setting of SYSRESETREQ bit - * - 1 - Reset caused by software setting of SYSRESETREQ bit - */ -/*@{*/ -#define BP_RCM_SRS1_SW (2U) /*!< Bit position for RCM_SRS1_SW. */ -#define BM_RCM_SRS1_SW (0x04U) /*!< Bit mask for RCM_SRS1_SW. */ -#define BS_RCM_SRS1_SW (1U) /*!< Bit field size in bits for RCM_SRS1_SW. */ - -/*! @brief Read current value of the RCM_SRS1_SW field. */ -#define BR_RCM_SRS1_SW(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SW)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field MDM_AP[3] (RO) - * - * Indicates a reset has been caused by the host debugger system setting of the - * System Reset Request bit in the MDM-AP Control Register. - * - * Values: - * - 0 - Reset not caused by host debugger system setting of the System Reset - * Request bit - * - 1 - Reset caused by host debugger system setting of the System Reset - * Request bit - */ -/*@{*/ -#define BP_RCM_SRS1_MDM_AP (3U) /*!< Bit position for RCM_SRS1_MDM_AP. */ -#define BM_RCM_SRS1_MDM_AP (0x08U) /*!< Bit mask for RCM_SRS1_MDM_AP. */ -#define BS_RCM_SRS1_MDM_AP (1U) /*!< Bit field size in bits for RCM_SRS1_MDM_AP. */ - -/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */ -#define BR_RCM_SRS1_MDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_MDM_AP)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field EZPT[4] (RO) - * - * Indicates a reset has been caused by EzPort receiving the RESET command while - * the device is in EzPort mode. - * - * Values: - * - 0 - Reset not caused by EzPort receiving the RESET command while the device - * is in EzPort mode - * - 1 - Reset caused by EzPort receiving the RESET command while the device is - * in EzPort mode - */ -/*@{*/ -#define BP_RCM_SRS1_EZPT (4U) /*!< Bit position for RCM_SRS1_EZPT. */ -#define BM_RCM_SRS1_EZPT (0x10U) /*!< Bit mask for RCM_SRS1_EZPT. */ -#define BS_RCM_SRS1_EZPT (1U) /*!< Bit field size in bits for RCM_SRS1_EZPT. */ - -/*! @brief Read current value of the RCM_SRS1_EZPT field. */ -#define BR_RCM_SRS1_EZPT(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_EZPT)) -/*@}*/ - -/*! - * @name Register RCM_SRS1, field SACKERR[5] (RO) - * - * Indicates that after an attempt to enter Stop mode, a reset has been caused - * by a failure of one or more peripherals to acknowledge within approximately one - * second to enter stop mode. - * - * Values: - * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter - * stop mode - * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop - * mode - */ -/*@{*/ -#define BP_RCM_SRS1_SACKERR (5U) /*!< Bit position for RCM_SRS1_SACKERR. */ -#define BM_RCM_SRS1_SACKERR (0x20U) /*!< Bit mask for RCM_SRS1_SACKERR. */ -#define BS_RCM_SRS1_SACKERR (1U) /*!< Bit field size in bits for RCM_SRS1_SACKERR. */ - -/*! @brief Read current value of the RCM_SRS1_SACKERR field. */ -#define BR_RCM_SRS1_SACKERR(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SACKERR)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_RPFC - Reset Pin Filter Control register - ******************************************************************************/ - -/*! - * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW) - * - * Reset value: 0x00U - * - * The reset values of bits 2-0 are for Chip POR only. They are unaffected by - * other reset types. The bus clock filter is reset when disabled or when entering - * stop mode. The LPO filter is reset when disabled or when entering any low - * leakage stop mode . - */ -typedef union _hw_rcm_rpfc -{ - uint8_t U; - struct _hw_rcm_rpfc_bitfields - { - uint8_t RSTFLTSRW : 2; /*!< [1:0] Reset Pin Filter Select in Run and - * Wait Modes */ - uint8_t RSTFLTSS : 1; /*!< [2] Reset Pin Filter Select in Stop Mode */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_rcm_rpfc_t; - -/*! - * @name Constants and macros for entire RCM_RPFC register - */ -/*@{*/ -#define HW_RCM_RPFC_ADDR(x) ((x) + 0x4U) - -#define HW_RCM_RPFC(x) (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR(x)) -#define HW_RCM_RPFC_RD(x) (HW_RCM_RPFC(x).U) -#define HW_RCM_RPFC_WR(x, v) (HW_RCM_RPFC(x).U = (v)) -#define HW_RCM_RPFC_SET(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) | (v))) -#define HW_RCM_RPFC_CLR(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) & ~(v))) -#define HW_RCM_RPFC_TOG(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RCM_RPFC bitfields - */ - -/*! - * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW) - * - * Selects how the reset pin filter is enabled in run and wait modes. - * - * Values: - * - 00 - All filtering disabled - * - 01 - Bus clock filter enabled for normal operation - * - 10 - LPO clock filter enabled for normal operation - * - 11 - Reserved - */ -/*@{*/ -#define BP_RCM_RPFC_RSTFLTSRW (0U) /*!< Bit position for RCM_RPFC_RSTFLTSRW. */ -#define BM_RCM_RPFC_RSTFLTSRW (0x03U) /*!< Bit mask for RCM_RPFC_RSTFLTSRW. */ -#define BS_RCM_RPFC_RSTFLTSRW (2U) /*!< Bit field size in bits for RCM_RPFC_RSTFLTSRW. */ - -/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */ -#define BR_RCM_RPFC_RSTFLTSRW(x) (HW_RCM_RPFC(x).B.RSTFLTSRW) - -/*! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW. */ -#define BF_RCM_RPFC_RSTFLTSRW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSRW) & BM_RCM_RPFC_RSTFLTSRW) - -/*! @brief Set the RSTFLTSRW field to a new value. */ -#define BW_RCM_RPFC_RSTFLTSRW(x, v) (HW_RCM_RPFC_WR(x, (HW_RCM_RPFC_RD(x) & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v))) -/*@}*/ - -/*! - * @name Register RCM_RPFC, field RSTFLTSS[2] (RW) - * - * Selects how the reset pin filter is enabled in Stop and VLPS modes - * - * Values: - * - 0 - All filtering disabled - * - 1 - LPO clock filter enabled - */ -/*@{*/ -#define BP_RCM_RPFC_RSTFLTSS (2U) /*!< Bit position for RCM_RPFC_RSTFLTSS. */ -#define BM_RCM_RPFC_RSTFLTSS (0x04U) /*!< Bit mask for RCM_RPFC_RSTFLTSS. */ -#define BS_RCM_RPFC_RSTFLTSS (1U) /*!< Bit field size in bits for RCM_RPFC_RSTFLTSS. */ - -/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */ -#define BR_RCM_RPFC_RSTFLTSS(x) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS)) - -/*! @brief Format value for bitfield RCM_RPFC_RSTFLTSS. */ -#define BF_RCM_RPFC_RSTFLTSS(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSS) & BM_RCM_RPFC_RSTFLTSS) - -/*! @brief Set the RSTFLTSS field to a new value. */ -#define BW_RCM_RPFC_RSTFLTSS(x, v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RCM_RPFW - Reset Pin Filter Width register - ******************************************************************************/ - -/*! - * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW) - * - * Reset value: 0x00U - * - * The reset values of the bits in the RSTFLTSEL field are for Chip POR only. - * They are unaffected by other reset types. - */ -typedef union _hw_rcm_rpfw -{ - uint8_t U; - struct _hw_rcm_rpfw_bitfields - { - uint8_t RSTFLTSEL : 5; /*!< [4:0] Reset Pin Filter Bus Clock Select */ - uint8_t RESERVED0 : 3; /*!< [7:5] */ - } B; -} hw_rcm_rpfw_t; - -/*! - * @name Constants and macros for entire RCM_RPFW register - */ -/*@{*/ -#define HW_RCM_RPFW_ADDR(x) ((x) + 0x5U) - -#define HW_RCM_RPFW(x) (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR(x)) -#define HW_RCM_RPFW_RD(x) (HW_RCM_RPFW(x).U) -#define HW_RCM_RPFW_WR(x, v) (HW_RCM_RPFW(x).U = (v)) -#define HW_RCM_RPFW_SET(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) | (v))) -#define HW_RCM_RPFW_CLR(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) & ~(v))) -#define HW_RCM_RPFW_TOG(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RCM_RPFW bitfields - */ - -/*! - * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW) - * - * Selects the reset pin bus clock filter width. - * - * Values: - * - 00000 - Bus clock filter count is 1 - * - 00001 - Bus clock filter count is 2 - * - 00010 - Bus clock filter count is 3 - * - 00011 - Bus clock filter count is 4 - * - 00100 - Bus clock filter count is 5 - * - 00101 - Bus clock filter count is 6 - * - 00110 - Bus clock filter count is 7 - * - 00111 - Bus clock filter count is 8 - * - 01000 - Bus clock filter count is 9 - * - 01001 - Bus clock filter count is 10 - * - 01010 - Bus clock filter count is 11 - * - 01011 - Bus clock filter count is 12 - * - 01100 - Bus clock filter count is 13 - * - 01101 - Bus clock filter count is 14 - * - 01110 - Bus clock filter count is 15 - * - 01111 - Bus clock filter count is 16 - * - 10000 - Bus clock filter count is 17 - * - 10001 - Bus clock filter count is 18 - * - 10010 - Bus clock filter count is 19 - * - 10011 - Bus clock filter count is 20 - * - 10100 - Bus clock filter count is 21 - * - 10101 - Bus clock filter count is 22 - * - 10110 - Bus clock filter count is 23 - * - 10111 - Bus clock filter count is 24 - * - 11000 - Bus clock filter count is 25 - * - 11001 - Bus clock filter count is 26 - * - 11010 - Bus clock filter count is 27 - * - 11011 - Bus clock filter count is 28 - * - 11100 - Bus clock filter count is 29 - * - 11101 - Bus clock filter count is 30 - * - 11110 - Bus clock filter count is 31 - * - 11111 - Bus clock filter count is 32 - */ -/*@{*/ -#define BP_RCM_RPFW_RSTFLTSEL (0U) /*!< Bit position for RCM_RPFW_RSTFLTSEL. */ -#define BM_RCM_RPFW_RSTFLTSEL (0x1FU) /*!< Bit mask for RCM_RPFW_RSTFLTSEL. */ -#define BS_RCM_RPFW_RSTFLTSEL (5U) /*!< Bit field size in bits for RCM_RPFW_RSTFLTSEL. */ - -/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */ -#define BR_RCM_RPFW_RSTFLTSEL(x) (HW_RCM_RPFW(x).B.RSTFLTSEL) - -/*! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL. */ -#define BF_RCM_RPFW_RSTFLTSEL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFW_RSTFLTSEL) & BM_RCM_RPFW_RSTFLTSEL) - -/*! @brief Set the RSTFLTSEL field to a new value. */ -#define BW_RCM_RPFW_RSTFLTSEL(x, v) (HW_RCM_RPFW_WR(x, (HW_RCM_RPFW_RD(x) & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v))) -/*@}*/ - -/******************************************************************************* - * HW_RCM_MR - Mode Register - ******************************************************************************/ - -/*! - * @brief HW_RCM_MR - Mode Register (RO) - * - * Reset value: 0x00U - * - * This register includes read-only status flags to indicate the state of the - * mode pins during the last Chip Reset. - */ -typedef union _hw_rcm_mr -{ - uint8_t U; - struct _hw_rcm_mr_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t EZP_MS : 1; /*!< [1] EZP_MS_B pin state */ - uint8_t RESERVED1 : 6; /*!< [7:2] */ - } B; -} hw_rcm_mr_t; - -/*! - * @name Constants and macros for entire RCM_MR register - */ -/*@{*/ -#define HW_RCM_MR_ADDR(x) ((x) + 0x7U) - -#define HW_RCM_MR(x) (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR(x)) -#define HW_RCM_MR_RD(x) (HW_RCM_MR(x).U) -/*@}*/ - -/* - * Constants & macros for individual RCM_MR bitfields - */ - -/*! - * @name Register RCM_MR, field EZP_MS[1] (RO) - * - * Reflects the state of the EZP_MS pin during the last Chip Reset - * - * Values: - * - 0 - Pin deasserted (logic 1) - * - 1 - Pin asserted (logic 0) - */ -/*@{*/ -#define BP_RCM_MR_EZP_MS (1U) /*!< Bit position for RCM_MR_EZP_MS. */ -#define BM_RCM_MR_EZP_MS (0x02U) /*!< Bit mask for RCM_MR_EZP_MS. */ -#define BS_RCM_MR_EZP_MS (1U) /*!< Bit field size in bits for RCM_MR_EZP_MS. */ - -/*! @brief Read current value of the RCM_MR_EZP_MS field. */ -#define BR_RCM_MR_EZP_MS(x) (BITBAND_ACCESS8(HW_RCM_MR_ADDR(x), BP_RCM_MR_EZP_MS)) -/*@}*/ - -/******************************************************************************* - * hw_rcm_t - module struct - ******************************************************************************/ -/*! - * @brief All RCM module registers. - */ -#pragma pack(1) -typedef struct _hw_rcm -{ - __I hw_rcm_srs0_t SRS0; /*!< [0x0] System Reset Status Register 0 */ - __I hw_rcm_srs1_t SRS1; /*!< [0x1] System Reset Status Register 1 */ - uint8_t _reserved0[2]; - __IO hw_rcm_rpfc_t RPFC; /*!< [0x4] Reset Pin Filter Control register */ - __IO hw_rcm_rpfw_t RPFW; /*!< [0x5] Reset Pin Filter Width register */ - uint8_t _reserved1[1]; - __I hw_rcm_mr_t MR; /*!< [0x7] Mode Register */ -} hw_rcm_t; -#pragma pack() - -/*! @brief Macro to access all RCM registers. */ -/*! @param x RCM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RCM(RCM_BASE). */ -#define HW_RCM(x) (*(hw_rcm_t *)(x)) - -#endif /* __HW_RCM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfsys.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfsys.h deleted file mode 100644 index 9ab7500de15..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfsys.h +++ /dev/null @@ -1,242 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RFSYS_REGISTERS_H__ -#define __HW_RFSYS_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 RFSYS - * - * System register file - * - * Registers defined in this header file: - * - HW_RFSYS_REGn - Register file register - * - * - hw_rfsys_t - Struct containing all module registers. - */ - -#define HW_RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */ - -/******************************************************************************* - * HW_RFSYS_REGn - Register file register - ******************************************************************************/ - -/*! - * @brief HW_RFSYS_REGn - Register file register (RW) - * - * Reset value: 0x00000000U - * - * Each register can be accessed as 8-, 16-, or 32-bits. - */ -typedef union _hw_rfsys_regn -{ - uint32_t U; - struct _hw_rfsys_regn_bitfields - { - uint32_t LL : 8; /*!< [7:0] */ - uint32_t LH : 8; /*!< [15:8] */ - uint32_t HL : 8; /*!< [23:16] */ - uint32_t HH : 8; /*!< [31:24] */ - } B; -} hw_rfsys_regn_t; - -/*! - * @name Constants and macros for entire RFSYS_REGn register - */ -/*@{*/ -#define HW_RFSYS_REGn_COUNT (8U) - -#define HW_RFSYS_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n))) - -#define HW_RFSYS_REGn(x, n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(x, n)) -#define HW_RFSYS_REGn_RD(x, n) (HW_RFSYS_REGn(x, n).U) -#define HW_RFSYS_REGn_WR(x, n, v) (HW_RFSYS_REGn(x, n).U = (v)) -#define HW_RFSYS_REGn_SET(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) | (v))) -#define HW_RFSYS_REGn_CLR(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) & ~(v))) -#define HW_RFSYS_REGn_TOG(x, n, v) (HW_RFSYS_REGn_WR(x, n, HW_RFSYS_REGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RFSYS_REGn bitfields - */ - -/*! - * @name Register RFSYS_REGn, field LL[7:0] (RW) - * - * Low lower byte - */ -/*@{*/ -#define BP_RFSYS_REGn_LL (0U) /*!< Bit position for RFSYS_REGn_LL. */ -#define BM_RFSYS_REGn_LL (0x000000FFU) /*!< Bit mask for RFSYS_REGn_LL. */ -#define BS_RFSYS_REGn_LL (8U) /*!< Bit field size in bits for RFSYS_REGn_LL. */ - -/*! @brief Read current value of the RFSYS_REGn_LL field. */ -#define BR_RFSYS_REGn_LL(x, n) (HW_RFSYS_REGn(x, n).B.LL) - -/*! @brief Format value for bitfield RFSYS_REGn_LL. */ -#define BF_RFSYS_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LL) & BM_RFSYS_REGn_LL) - -/*! @brief Set the LL field to a new value. */ -#define BW_RFSYS_REGn_LL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v))) -/*@}*/ - -/*! - * @name Register RFSYS_REGn, field LH[15:8] (RW) - * - * Low higher byte - */ -/*@{*/ -#define BP_RFSYS_REGn_LH (8U) /*!< Bit position for RFSYS_REGn_LH. */ -#define BM_RFSYS_REGn_LH (0x0000FF00U) /*!< Bit mask for RFSYS_REGn_LH. */ -#define BS_RFSYS_REGn_LH (8U) /*!< Bit field size in bits for RFSYS_REGn_LH. */ - -/*! @brief Read current value of the RFSYS_REGn_LH field. */ -#define BR_RFSYS_REGn_LH(x, n) (HW_RFSYS_REGn(x, n).B.LH) - -/*! @brief Format value for bitfield RFSYS_REGn_LH. */ -#define BF_RFSYS_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_LH) & BM_RFSYS_REGn_LH) - -/*! @brief Set the LH field to a new value. */ -#define BW_RFSYS_REGn_LH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v))) -/*@}*/ - -/*! - * @name Register RFSYS_REGn, field HL[23:16] (RW) - * - * High lower byte - */ -/*@{*/ -#define BP_RFSYS_REGn_HL (16U) /*!< Bit position for RFSYS_REGn_HL. */ -#define BM_RFSYS_REGn_HL (0x00FF0000U) /*!< Bit mask for RFSYS_REGn_HL. */ -#define BS_RFSYS_REGn_HL (8U) /*!< Bit field size in bits for RFSYS_REGn_HL. */ - -/*! @brief Read current value of the RFSYS_REGn_HL field. */ -#define BR_RFSYS_REGn_HL(x, n) (HW_RFSYS_REGn(x, n).B.HL) - -/*! @brief Format value for bitfield RFSYS_REGn_HL. */ -#define BF_RFSYS_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HL) & BM_RFSYS_REGn_HL) - -/*! @brief Set the HL field to a new value. */ -#define BW_RFSYS_REGn_HL(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v))) -/*@}*/ - -/*! - * @name Register RFSYS_REGn, field HH[31:24] (RW) - * - * High higher byte - */ -/*@{*/ -#define BP_RFSYS_REGn_HH (24U) /*!< Bit position for RFSYS_REGn_HH. */ -#define BM_RFSYS_REGn_HH (0xFF000000U) /*!< Bit mask for RFSYS_REGn_HH. */ -#define BS_RFSYS_REGn_HH (8U) /*!< Bit field size in bits for RFSYS_REGn_HH. */ - -/*! @brief Read current value of the RFSYS_REGn_HH field. */ -#define BR_RFSYS_REGn_HH(x, n) (HW_RFSYS_REGn(x, n).B.HH) - -/*! @brief Format value for bitfield RFSYS_REGn_HH. */ -#define BF_RFSYS_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFSYS_REGn_HH) & BM_RFSYS_REGn_HH) - -/*! @brief Set the HH field to a new value. */ -#define BW_RFSYS_REGn_HH(x, n, v) (HW_RFSYS_REGn_WR(x, n, (HW_RFSYS_REGn_RD(x, n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v))) -/*@}*/ - -/******************************************************************************* - * hw_rfsys_t - module struct - ******************************************************************************/ -/*! - * @brief All RFSYS module registers. - */ -#pragma pack(1) -typedef struct _hw_rfsys -{ - __IO hw_rfsys_regn_t REGn[8]; /*!< [0x0] Register file register */ -} hw_rfsys_t; -#pragma pack() - -/*! @brief Macro to access all RFSYS registers. */ -/*! @param x RFSYS module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RFSYS(RFSYS_BASE). */ -#define HW_RFSYS(x) (*(hw_rfsys_t *)(x)) - -#endif /* __HW_RFSYS_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfvbat.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfvbat.h deleted file mode 100644 index da0938bbd27..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfvbat.h +++ /dev/null @@ -1,242 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RFVBAT_REGISTERS_H__ -#define __HW_RFVBAT_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 RFVBAT - * - * VBAT register file - * - * Registers defined in this header file: - * - HW_RFVBAT_REGn - VBAT register file register - * - * - hw_rfvbat_t - Struct containing all module registers. - */ - -#define HW_RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */ - -/******************************************************************************* - * HW_RFVBAT_REGn - VBAT register file register - ******************************************************************************/ - -/*! - * @brief HW_RFVBAT_REGn - VBAT register file register (RW) - * - * Reset value: 0x00000000U - * - * Each register can be accessed as 8-, 16-, or 32-bits. - */ -typedef union _hw_rfvbat_regn -{ - uint32_t U; - struct _hw_rfvbat_regn_bitfields - { - uint32_t LL : 8; /*!< [7:0] */ - uint32_t LH : 8; /*!< [15:8] */ - uint32_t HL : 8; /*!< [23:16] */ - uint32_t HH : 8; /*!< [31:24] */ - } B; -} hw_rfvbat_regn_t; - -/*! - * @name Constants and macros for entire RFVBAT_REGn register - */ -/*@{*/ -#define HW_RFVBAT_REGn_COUNT (8U) - -#define HW_RFVBAT_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n))) - -#define HW_RFVBAT_REGn(x, n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(x, n)) -#define HW_RFVBAT_REGn_RD(x, n) (HW_RFVBAT_REGn(x, n).U) -#define HW_RFVBAT_REGn_WR(x, n, v) (HW_RFVBAT_REGn(x, n).U = (v)) -#define HW_RFVBAT_REGn_SET(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) | (v))) -#define HW_RFVBAT_REGn_CLR(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) & ~(v))) -#define HW_RFVBAT_REGn_TOG(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RFVBAT_REGn bitfields - */ - -/*! - * @name Register RFVBAT_REGn, field LL[7:0] (RW) - * - * Low lower byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_LL (0U) /*!< Bit position for RFVBAT_REGn_LL. */ -#define BM_RFVBAT_REGn_LL (0x000000FFU) /*!< Bit mask for RFVBAT_REGn_LL. */ -#define BS_RFVBAT_REGn_LL (8U) /*!< Bit field size in bits for RFVBAT_REGn_LL. */ - -/*! @brief Read current value of the RFVBAT_REGn_LL field. */ -#define BR_RFVBAT_REGn_LL(x, n) (HW_RFVBAT_REGn(x, n).B.LL) - -/*! @brief Format value for bitfield RFVBAT_REGn_LL. */ -#define BF_RFVBAT_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LL) & BM_RFVBAT_REGn_LL) - -/*! @brief Set the LL field to a new value. */ -#define BW_RFVBAT_REGn_LL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v))) -/*@}*/ - -/*! - * @name Register RFVBAT_REGn, field LH[15:8] (RW) - * - * Low higher byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_LH (8U) /*!< Bit position for RFVBAT_REGn_LH. */ -#define BM_RFVBAT_REGn_LH (0x0000FF00U) /*!< Bit mask for RFVBAT_REGn_LH. */ -#define BS_RFVBAT_REGn_LH (8U) /*!< Bit field size in bits for RFVBAT_REGn_LH. */ - -/*! @brief Read current value of the RFVBAT_REGn_LH field. */ -#define BR_RFVBAT_REGn_LH(x, n) (HW_RFVBAT_REGn(x, n).B.LH) - -/*! @brief Format value for bitfield RFVBAT_REGn_LH. */ -#define BF_RFVBAT_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LH) & BM_RFVBAT_REGn_LH) - -/*! @brief Set the LH field to a new value. */ -#define BW_RFVBAT_REGn_LH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v))) -/*@}*/ - -/*! - * @name Register RFVBAT_REGn, field HL[23:16] (RW) - * - * High lower byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_HL (16U) /*!< Bit position for RFVBAT_REGn_HL. */ -#define BM_RFVBAT_REGn_HL (0x00FF0000U) /*!< Bit mask for RFVBAT_REGn_HL. */ -#define BS_RFVBAT_REGn_HL (8U) /*!< Bit field size in bits for RFVBAT_REGn_HL. */ - -/*! @brief Read current value of the RFVBAT_REGn_HL field. */ -#define BR_RFVBAT_REGn_HL(x, n) (HW_RFVBAT_REGn(x, n).B.HL) - -/*! @brief Format value for bitfield RFVBAT_REGn_HL. */ -#define BF_RFVBAT_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HL) & BM_RFVBAT_REGn_HL) - -/*! @brief Set the HL field to a new value. */ -#define BW_RFVBAT_REGn_HL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v))) -/*@}*/ - -/*! - * @name Register RFVBAT_REGn, field HH[31:24] (RW) - * - * High higher byte - */ -/*@{*/ -#define BP_RFVBAT_REGn_HH (24U) /*!< Bit position for RFVBAT_REGn_HH. */ -#define BM_RFVBAT_REGn_HH (0xFF000000U) /*!< Bit mask for RFVBAT_REGn_HH. */ -#define BS_RFVBAT_REGn_HH (8U) /*!< Bit field size in bits for RFVBAT_REGn_HH. */ - -/*! @brief Read current value of the RFVBAT_REGn_HH field. */ -#define BR_RFVBAT_REGn_HH(x, n) (HW_RFVBAT_REGn(x, n).B.HH) - -/*! @brief Format value for bitfield RFVBAT_REGn_HH. */ -#define BF_RFVBAT_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HH) & BM_RFVBAT_REGn_HH) - -/*! @brief Set the HH field to a new value. */ -#define BW_RFVBAT_REGn_HH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v))) -/*@}*/ - -/******************************************************************************* - * hw_rfvbat_t - module struct - ******************************************************************************/ -/*! - * @brief All RFVBAT module registers. - */ -#pragma pack(1) -typedef struct _hw_rfvbat -{ - __IO hw_rfvbat_regn_t REGn[8]; /*!< [0x0] VBAT register file register */ -} hw_rfvbat_t; -#pragma pack() - -/*! @brief Macro to access all RFVBAT registers. */ -/*! @param x RFVBAT module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RFVBAT(RFVBAT_BASE). */ -#define HW_RFVBAT(x) (*(hw_rfvbat_t *)(x)) - -#endif /* __HW_RFVBAT_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h deleted file mode 100644 index ca0cfc15d15..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h +++ /dev/null @@ -1,590 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RNG_REGISTERS_H__ -#define __HW_RNG_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 RNG - * - * Random Number Generator Accelerator - * - * Registers defined in this header file: - * - HW_RNG_CR - RNGA Control Register - * - HW_RNG_SR - RNGA Status Register - * - HW_RNG_ER - RNGA Entropy Register - * - HW_RNG_OR - RNGA Output Register - * - * - hw_rng_t - Struct containing all module registers. - */ - -#define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */ - -/******************************************************************************* - * HW_RNG_CR - RNGA Control Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_CR - RNGA Control Register (RW) - * - * Reset value: 0x00000000U - * - * Controls the operation of RNGA. - */ -typedef union _hw_rng_cr -{ - uint32_t U; - struct _hw_rng_cr_bitfields - { - uint32_t GO : 1; /*!< [0] Go */ - uint32_t HA : 1; /*!< [1] High Assurance */ - uint32_t INTM : 1; /*!< [2] Interrupt Mask */ - uint32_t CLRI : 1; /*!< [3] Clear Interrupt */ - uint32_t SLP : 1; /*!< [4] Sleep */ - uint32_t RESERVED0 : 27; /*!< [31:5] */ - } B; -} hw_rng_cr_t; - -/*! - * @name Constants and macros for entire RNG_CR register - */ -/*@{*/ -#define HW_RNG_CR_ADDR(x) ((x) + 0x0U) - -#define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x)) -#define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U) -#define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v)) -#define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v))) -#define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v))) -#define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RNG_CR bitfields - */ - -/*! - * @name Register RNG_CR, field GO[0] (RW) - * - * Specifies whether random-data generation and loading (into OR[RANDOUT]) is - * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading - * OR[RANDOUT] with data. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */ -#define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */ -#define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */ - -/*! @brief Read current value of the RNG_CR_GO field. */ -#define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO)) - -/*! @brief Format value for bitfield RNG_CR_GO. */ -#define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO) - -/*! @brief Set the GO field to a new value. */ -#define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field HA[1] (RW) - * - * Enables notification of security violations (via SR[SECV]). A security - * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky. - * After enabling notification of security violations, you must reset RNGA to - * disable them again. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */ -#define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */ -#define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */ - -/*! @brief Read current value of the RNG_CR_HA field. */ -#define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA)) - -/*! @brief Format value for bitfield RNG_CR_HA. */ -#define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA) - -/*! @brief Set the HA field to a new value. */ -#define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field INTM[2] (RW) - * - * Masks the triggering of an error interrupt to the interrupt controller when - * an OR underflow condition occurs. An OR underflow condition occurs when you - * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description. - * - * Values: - * - 0 - Not masked - * - 1 - Masked - */ -/*@{*/ -#define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */ -#define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */ -#define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */ - -/*! @brief Read current value of the RNG_CR_INTM field. */ -#define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM)) - -/*! @brief Format value for bitfield RNG_CR_INTM. */ -#define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM) - -/*! @brief Set the INTM field to a new value. */ -#define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field CLRI[3] (WORZ) - * - * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]). - * - * Values: - * - 0 - Do not clear the interrupt. - * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets - * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0. - */ -/*@{*/ -#define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */ -#define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */ -#define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */ - -/*! @brief Format value for bitfield RNG_CR_CLRI. */ -#define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI) - -/*! @brief Set the CLRI field to a new value. */ -#define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v)) -/*@}*/ - -/*! - * @name Register RNG_CR, field SLP[4] (RW) - * - * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep - * mode by asserting the DOZE signal. - * - * Values: - * - 0 - Normal mode - * - 1 - Sleep (low-power) mode - */ -/*@{*/ -#define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */ -#define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */ -#define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */ - -/*! @brief Read current value of the RNG_CR_SLP field. */ -#define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP)) - -/*! @brief Format value for bitfield RNG_CR_SLP. */ -#define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP) - -/*! @brief Set the SLP field to a new value. */ -#define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RNG_SR - RNGA Status Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_SR - RNGA Status Register (RO) - * - * Reset value: 0x00010000U - * - * Indicates the status of RNGA. This register is read-only. - */ -typedef union _hw_rng_sr -{ - uint32_t U; - struct _hw_rng_sr_bitfields - { - uint32_t SECV : 1; /*!< [0] Security Violation */ - uint32_t LRS : 1; /*!< [1] Last Read Status */ - uint32_t ORU : 1; /*!< [2] Output Register Underflow */ - uint32_t ERRI : 1; /*!< [3] Error Interrupt */ - uint32_t SLP : 1; /*!< [4] Sleep */ - uint32_t RESERVED0 : 3; /*!< [7:5] */ - uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */ - uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ - } B; -} hw_rng_sr_t; - -/*! - * @name Constants and macros for entire RNG_SR register - */ -/*@{*/ -#define HW_RNG_SR_ADDR(x) ((x) + 0x4U) - -#define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x)) -#define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U) -/*@}*/ - -/* - * Constants & macros for individual RNG_SR bitfields - */ - -/*! - * @name Register RNG_SR, field SECV[0] (RO) - * - * Used only when high assurance is enabled (CR[HA]). Indicates that a security - * violation has occurred.This field is sticky. To clear SR[SECV], you must reset - * RNGA. - * - * Values: - * - 0 - No security violation - * - 1 - Security violation - */ -/*@{*/ -#define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */ -#define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */ -#define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */ - -/*! @brief Read current value of the RNG_SR_SECV field. */ -#define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV)) -/*@}*/ - -/*! - * @name Register RNG_SR, field LRS[1] (RO) - * - * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow - * condition, regardless of whether the error interrupt is masked (CR[INTM]). An - * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. - * After you read this register, RNGA writes 0 to this field. - * - * Values: - * - 0 - No underflow - * - 1 - Underflow - */ -/*@{*/ -#define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */ -#define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */ -#define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */ - -/*! @brief Read current value of the RNG_SR_LRS field. */ -#define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS)) -/*@}*/ - -/*! - * @name Register RNG_SR, field ORU[2] (RO) - * - * Indicates whether an OR underflow condition has occurred since you last read - * this register (SR) or RNGA was reset, regardless of whether the error - * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read - * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this - * field. - * - * Values: - * - 0 - No underflow - * - 1 - Underflow - */ -/*@{*/ -#define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */ -#define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */ -#define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */ - -/*! @brief Read current value of the RNG_SR_ORU field. */ -#define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU)) -/*@}*/ - -/*! - * @name Register RNG_SR, field ERRI[3] (RO) - * - * Indicates whether an OR underflow condition has occurred since you last - * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the - * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when - * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt - * indicator (via CR[CLRI]), RNGA writes 0 to this field. - * - * Values: - * - 0 - No underflow - * - 1 - Underflow - */ -/*@{*/ -#define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */ -#define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */ -#define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */ - -/*! @brief Read current value of the RNG_SR_ERRI field. */ -#define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI)) -/*@}*/ - -/*! - * @name Register RNG_SR, field SLP[4] (RO) - * - * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep - * mode by asserting the DOZE signal. - * - * Values: - * - 0 - Normal mode - * - 1 - Sleep (low-power) mode - */ -/*@{*/ -#define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */ -#define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */ -#define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */ - -/*! @brief Read current value of the RNG_SR_SLP field. */ -#define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP)) -/*@}*/ - -/*! - * @name Register RNG_SR, field OREG_LVL[15:8] (RO) - * - * Indicates the number of random-data words that are in OR[RANDOUT], which - * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] - * is not 0, then the contents of a random number contained in OR[RANDOUT] are - * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. - * - * Values: - * - 0 - No words (empty) - * - 1 - One word (valid) - */ -/*@{*/ -#define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */ -#define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */ -#define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */ - -/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ -#define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL) -/*@}*/ - -/*! - * @name Register RNG_SR, field OREG_SIZE[23:16] (RO) - * - * Indicates the size of the Output (OR) register in terms of the number of - * 32-bit random-data words it can hold. - * - * Values: - * - 1 - One word (this value is fixed) - */ -/*@{*/ -#define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */ -#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */ -#define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */ - -/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */ -#define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE) -/*@}*/ - -/******************************************************************************* - * HW_RNG_ER - RNGA Entropy Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_ER - RNGA Entropy Register (WORZ) - * - * Reset value: 0x00000000U - * - * Specifies an entropy value that RNGA uses in addition to its ring oscillators - * to seed its pseudorandom algorithm. This is a write-only register; reads - * return all zeros. - */ -typedef union _hw_rng_er -{ - uint32_t U; - struct _hw_rng_er_bitfields - { - uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */ - } B; -} hw_rng_er_t; - -/*! - * @name Constants and macros for entire RNG_ER register - */ -/*@{*/ -#define HW_RNG_ER_ADDR(x) ((x) + 0x8U) - -#define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x)) -#define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U) -#define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual RNG_ER bitfields - */ - -/*! - * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ) - * - * Specifies an entropy value that RNGA uses in addition to its ring oscillators - * to seed its pseudorandom algorithm.Specifying a value for this field is - * optional but recommended. You can write to this field at any time during operation. - */ -/*@{*/ -#define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */ -#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */ -#define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */ - -/*! @brief Format value for bitfield RNG_ER_EXT_ENT. */ -#define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT) - -/*! @brief Set the EXT_ENT field to a new value. */ -#define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_RNG_OR - RNGA Output Register - ******************************************************************************/ - -/*! - * @brief HW_RNG_OR - RNGA Output Register (RO) - * - * Reset value: 0x00000000U - * - * Stores a random-data word generated by RNGA. - */ -typedef union _hw_rng_or -{ - uint32_t U; - struct _hw_rng_or_bitfields - { - uint32_t RANDOUT : 32; /*!< [31:0] Random Output */ - } B; -} hw_rng_or_t; - -/*! - * @name Constants and macros for entire RNG_OR register - */ -/*@{*/ -#define HW_RNG_OR_ADDR(x) ((x) + 0xCU) - -#define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x)) -#define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U) -/*@}*/ - -/* - * Constants & macros for individual RNG_OR bitfields - */ - -/*! - * @name Register RNG_OR, field RANDOUT[31:0] (RO) - * - * Stores a random-data word generated by RNGA. This is a read-only field.Before - * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). - * - * Values: - * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is - * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error - * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt - * request to the interrupt controller). - */ -/*@{*/ -#define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */ -#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */ -#define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */ - -/*! @brief Read current value of the RNG_OR_RANDOUT field. */ -#define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U) -/*@}*/ - -/******************************************************************************* - * hw_rng_t - module struct - ******************************************************************************/ -/*! - * @brief All RNG module registers. - */ -#pragma pack(1) -typedef struct _hw_rng -{ - __IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */ - __I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */ - __O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */ - __I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */ -} hw_rng_t; -#pragma pack() - -/*! @brief Macro to access all RNG registers. */ -/*! @param x RNG module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RNG(RNG_BASE). */ -#define HW_RNG(x) (*(hw_rng_t *)(x)) - -#endif /* __HW_RNG_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rtc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rtc.h deleted file mode 100644 index 7c156afd08f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rtc.h +++ /dev/null @@ -1,1662 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_RTC_REGISTERS_H__ -#define __HW_RTC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 RTC - * - * Secure Real Time Clock - * - * Registers defined in this header file: - * - HW_RTC_TSR - RTC Time Seconds Register - * - HW_RTC_TPR - RTC Time Prescaler Register - * - HW_RTC_TAR - RTC Time Alarm Register - * - HW_RTC_TCR - RTC Time Compensation Register - * - HW_RTC_CR - RTC Control Register - * - HW_RTC_SR - RTC Status Register - * - HW_RTC_LR - RTC Lock Register - * - HW_RTC_IER - RTC Interrupt Enable Register - * - HW_RTC_WAR - RTC Write Access Register - * - HW_RTC_RAR - RTC Read Access Register - * - * - hw_rtc_t - Struct containing all module registers. - */ - -#define HW_RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */ - -/******************************************************************************* - * HW_RTC_TSR - RTC Time Seconds Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TSR - RTC Time Seconds Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tsr -{ - uint32_t U; - struct _hw_rtc_tsr_bitfields - { - uint32_t TSR : 32; /*!< [31:0] Time Seconds Register */ - } B; -} hw_rtc_tsr_t; - -/*! - * @name Constants and macros for entire RTC_TSR register - */ -/*@{*/ -#define HW_RTC_TSR_ADDR(x) ((x) + 0x0U) - -#define HW_RTC_TSR(x) (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR(x)) -#define HW_RTC_TSR_RD(x) (HW_RTC_TSR(x).U) -#define HW_RTC_TSR_WR(x, v) (HW_RTC_TSR(x).U = (v)) -#define HW_RTC_TSR_SET(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) | (v))) -#define HW_RTC_TSR_CLR(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) & ~(v))) -#define HW_RTC_TSR_TOG(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TSR bitfields - */ - -/*! - * @name Register RTC_TSR, field TSR[31:0] (RW) - * - * When the time counter is enabled, the TSR is read only and increments once a - * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as - * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the - * TSR can be read or written. Writing to the TSR when the time counter is - * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is - * supported, but not recommended because TSR will read as zero when SR[TIF] or - * SR[TOF] are set (indicating the time is invalid). - */ -/*@{*/ -#define BP_RTC_TSR_TSR (0U) /*!< Bit position for RTC_TSR_TSR. */ -#define BM_RTC_TSR_TSR (0xFFFFFFFFU) /*!< Bit mask for RTC_TSR_TSR. */ -#define BS_RTC_TSR_TSR (32U) /*!< Bit field size in bits for RTC_TSR_TSR. */ - -/*! @brief Read current value of the RTC_TSR_TSR field. */ -#define BR_RTC_TSR_TSR(x) (HW_RTC_TSR(x).U) - -/*! @brief Format value for bitfield RTC_TSR_TSR. */ -#define BF_RTC_TSR_TSR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TSR_TSR) & BM_RTC_TSR_TSR) - -/*! @brief Set the TSR field to a new value. */ -#define BW_RTC_TSR_TSR(x, v) (HW_RTC_TSR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_TPR - RTC Time Prescaler Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tpr -{ - uint32_t U; - struct _hw_rtc_tpr_bitfields - { - uint32_t TPR : 16; /*!< [15:0] Time Prescaler Register */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_rtc_tpr_t; - -/*! - * @name Constants and macros for entire RTC_TPR register - */ -/*@{*/ -#define HW_RTC_TPR_ADDR(x) ((x) + 0x4U) - -#define HW_RTC_TPR(x) (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR(x)) -#define HW_RTC_TPR_RD(x) (HW_RTC_TPR(x).U) -#define HW_RTC_TPR_WR(x, v) (HW_RTC_TPR(x).U = (v)) -#define HW_RTC_TPR_SET(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) | (v))) -#define HW_RTC_TPR_CLR(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) & ~(v))) -#define HW_RTC_TPR_TOG(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TPR bitfields - */ - -/*! - * @name Register RTC_TPR, field TPR[15:0] (RW) - * - * When the time counter is enabled, the TPR is read only and increments every - * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or - * SR[TIF] are set. When the time counter is disabled, the TPR can be read or - * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one - * to a logic zero. - */ -/*@{*/ -#define BP_RTC_TPR_TPR (0U) /*!< Bit position for RTC_TPR_TPR. */ -#define BM_RTC_TPR_TPR (0x0000FFFFU) /*!< Bit mask for RTC_TPR_TPR. */ -#define BS_RTC_TPR_TPR (16U) /*!< Bit field size in bits for RTC_TPR_TPR. */ - -/*! @brief Read current value of the RTC_TPR_TPR field. */ -#define BR_RTC_TPR_TPR(x) (HW_RTC_TPR(x).B.TPR) - -/*! @brief Format value for bitfield RTC_TPR_TPR. */ -#define BF_RTC_TPR_TPR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TPR_TPR) & BM_RTC_TPR_TPR) - -/*! @brief Set the TPR field to a new value. */ -#define BW_RTC_TPR_TPR(x, v) (HW_RTC_TPR_WR(x, (HW_RTC_TPR_RD(x) & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v))) -/*@}*/ - -/******************************************************************************* - * HW_RTC_TAR - RTC Time Alarm Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TAR - RTC Time Alarm Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tar -{ - uint32_t U; - struct _hw_rtc_tar_bitfields - { - uint32_t TAR : 32; /*!< [31:0] Time Alarm Register */ - } B; -} hw_rtc_tar_t; - -/*! - * @name Constants and macros for entire RTC_TAR register - */ -/*@{*/ -#define HW_RTC_TAR_ADDR(x) ((x) + 0x8U) - -#define HW_RTC_TAR(x) (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR(x)) -#define HW_RTC_TAR_RD(x) (HW_RTC_TAR(x).U) -#define HW_RTC_TAR_WR(x, v) (HW_RTC_TAR(x).U = (v)) -#define HW_RTC_TAR_SET(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) | (v))) -#define HW_RTC_TAR_CLR(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) & ~(v))) -#define HW_RTC_TAR_TOG(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TAR bitfields - */ - -/*! - * @name Register RTC_TAR, field TAR[31:0] (RW) - * - * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] - * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the - * SR[TAF]. - */ -/*@{*/ -#define BP_RTC_TAR_TAR (0U) /*!< Bit position for RTC_TAR_TAR. */ -#define BM_RTC_TAR_TAR (0xFFFFFFFFU) /*!< Bit mask for RTC_TAR_TAR. */ -#define BS_RTC_TAR_TAR (32U) /*!< Bit field size in bits for RTC_TAR_TAR. */ - -/*! @brief Read current value of the RTC_TAR_TAR field. */ -#define BR_RTC_TAR_TAR(x) (HW_RTC_TAR(x).U) - -/*! @brief Format value for bitfield RTC_TAR_TAR. */ -#define BF_RTC_TAR_TAR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TAR_TAR) & BM_RTC_TAR_TAR) - -/*! @brief Set the TAR field to a new value. */ -#define BW_RTC_TAR_TAR(x, v) (HW_RTC_TAR_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_TCR - RTC Time Compensation Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_TCR - RTC Time Compensation Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_tcr -{ - uint32_t U; - struct _hw_rtc_tcr_bitfields - { - uint32_t TCR : 8; /*!< [7:0] Time Compensation Register */ - uint32_t CIR : 8; /*!< [15:8] Compensation Interval Register */ - uint32_t TCV : 8; /*!< [23:16] Time Compensation Value */ - uint32_t CIC : 8; /*!< [31:24] Compensation Interval Counter */ - } B; -} hw_rtc_tcr_t; - -/*! - * @name Constants and macros for entire RTC_TCR register - */ -/*@{*/ -#define HW_RTC_TCR_ADDR(x) ((x) + 0xCU) - -#define HW_RTC_TCR(x) (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR(x)) -#define HW_RTC_TCR_RD(x) (HW_RTC_TCR(x).U) -#define HW_RTC_TCR_WR(x, v) (HW_RTC_TCR(x).U = (v)) -#define HW_RTC_TCR_SET(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) | (v))) -#define HW_RTC_TCR_CLR(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) & ~(v))) -#define HW_RTC_TCR_TOG(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_TCR bitfields - */ - -/*! - * @name Register RTC_TCR, field TCR[7:0] (RW) - * - * Configures the number of 32.768 kHz clock cycles in each second. This - * register is double buffered and writes do not take affect until the end of the - * current compensation interval. - * - * Values: - * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles. - * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles. - * - 0 - Time Prescaler Register overflows every 32768 clock cycles. - * - 1 - Time Prescaler Register overflows every 32767 clock cycles. - * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles. - */ -/*@{*/ -#define BP_RTC_TCR_TCR (0U) /*!< Bit position for RTC_TCR_TCR. */ -#define BM_RTC_TCR_TCR (0x000000FFU) /*!< Bit mask for RTC_TCR_TCR. */ -#define BS_RTC_TCR_TCR (8U) /*!< Bit field size in bits for RTC_TCR_TCR. */ - -/*! @brief Read current value of the RTC_TCR_TCR field. */ -#define BR_RTC_TCR_TCR(x) (HW_RTC_TCR(x).B.TCR) - -/*! @brief Format value for bitfield RTC_TCR_TCR. */ -#define BF_RTC_TCR_TCR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_TCR) & BM_RTC_TCR_TCR) - -/*! @brief Set the TCR field to a new value. */ -#define BW_RTC_TCR_TCR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v))) -/*@}*/ - -/*! - * @name Register RTC_TCR, field CIR[15:8] (RW) - * - * Configures the compensation interval in seconds from 1 to 256 to control how - * frequently the TCR should adjust the number of 32.768 kHz cycles in each - * second. The value written should be one less than the number of seconds. For - * example, write zero to configure for a compensation interval of one second. This - * register is double buffered and writes do not take affect until the end of the - * current compensation interval. - */ -/*@{*/ -#define BP_RTC_TCR_CIR (8U) /*!< Bit position for RTC_TCR_CIR. */ -#define BM_RTC_TCR_CIR (0x0000FF00U) /*!< Bit mask for RTC_TCR_CIR. */ -#define BS_RTC_TCR_CIR (8U) /*!< Bit field size in bits for RTC_TCR_CIR. */ - -/*! @brief Read current value of the RTC_TCR_CIR field. */ -#define BR_RTC_TCR_CIR(x) (HW_RTC_TCR(x).B.CIR) - -/*! @brief Format value for bitfield RTC_TCR_CIR. */ -#define BF_RTC_TCR_CIR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_CIR) & BM_RTC_TCR_CIR) - -/*! @brief Set the CIR field to a new value. */ -#define BW_RTC_TCR_CIR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v))) -/*@}*/ - -/*! - * @name Register RTC_TCR, field TCV[23:16] (RO) - * - * Current value used by the compensation logic for the present second interval. - * Updated once a second if the CIC equals 0 with the contents of the TCR field. - * If the CIC does not equal zero then it is loaded with zero (compensation is - * not enabled for that second increment). - */ -/*@{*/ -#define BP_RTC_TCR_TCV (16U) /*!< Bit position for RTC_TCR_TCV. */ -#define BM_RTC_TCR_TCV (0x00FF0000U) /*!< Bit mask for RTC_TCR_TCV. */ -#define BS_RTC_TCR_TCV (8U) /*!< Bit field size in bits for RTC_TCR_TCV. */ - -/*! @brief Read current value of the RTC_TCR_TCV field. */ -#define BR_RTC_TCR_TCV(x) (HW_RTC_TCR(x).B.TCV) -/*@}*/ - -/*! - * @name Register RTC_TCR, field CIC[31:24] (RO) - * - * Current value of the compensation interval counter. If the compensation - * interval counter equals zero then it is loaded with the contents of the CIR. If the - * CIC does not equal zero then it is decremented once a second. - */ -/*@{*/ -#define BP_RTC_TCR_CIC (24U) /*!< Bit position for RTC_TCR_CIC. */ -#define BM_RTC_TCR_CIC (0xFF000000U) /*!< Bit mask for RTC_TCR_CIC. */ -#define BS_RTC_TCR_CIC (8U) /*!< Bit field size in bits for RTC_TCR_CIC. */ - -/*! @brief Read current value of the RTC_TCR_CIC field. */ -#define BR_RTC_TCR_CIC(x) (HW_RTC_TCR(x).B.CIC) -/*@}*/ - -/******************************************************************************* - * HW_RTC_CR - RTC Control Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_CR - RTC Control Register (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_rtc_cr -{ - uint32_t U; - struct _hw_rtc_cr_bitfields - { - uint32_t SWR : 1; /*!< [0] Software Reset */ - uint32_t WPE : 1; /*!< [1] Wakeup Pin Enable */ - uint32_t SUP : 1; /*!< [2] Supervisor Access */ - uint32_t UM : 1; /*!< [3] Update Mode */ - uint32_t WPS : 1; /*!< [4] Wakeup Pin Select */ - uint32_t RESERVED0 : 3; /*!< [7:5] */ - uint32_t OSCE : 1; /*!< [8] Oscillator Enable */ - uint32_t CLKO : 1; /*!< [9] Clock Output */ - uint32_t SC16P : 1; /*!< [10] Oscillator 16pF Load Configure */ - uint32_t SC8P : 1; /*!< [11] Oscillator 8pF Load Configure */ - uint32_t SC4P : 1; /*!< [12] Oscillator 4pF Load Configure */ - uint32_t SC2P : 1; /*!< [13] Oscillator 2pF Load Configure */ - uint32_t RESERVED1 : 18; /*!< [31:14] */ - } B; -} hw_rtc_cr_t; - -/*! - * @name Constants and macros for entire RTC_CR register - */ -/*@{*/ -#define HW_RTC_CR_ADDR(x) ((x) + 0x10U) - -#define HW_RTC_CR(x) (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR(x)) -#define HW_RTC_CR_RD(x) (HW_RTC_CR(x).U) -#define HW_RTC_CR_WR(x, v) (HW_RTC_CR(x).U = (v)) -#define HW_RTC_CR_SET(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) | (v))) -#define HW_RTC_CR_CLR(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) & ~(v))) -#define HW_RTC_CR_TOG(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_CR bitfields - */ - -/*! - * @name Register RTC_CR, field SWR[0] (RW) - * - * Values: - * - 0 - No effect. - * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and - * RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software - * explicitly clearing it. - */ -/*@{*/ -#define BP_RTC_CR_SWR (0U) /*!< Bit position for RTC_CR_SWR. */ -#define BM_RTC_CR_SWR (0x00000001U) /*!< Bit mask for RTC_CR_SWR. */ -#define BS_RTC_CR_SWR (1U) /*!< Bit field size in bits for RTC_CR_SWR. */ - -/*! @brief Read current value of the RTC_CR_SWR field. */ -#define BR_RTC_CR_SWR(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR)) - -/*! @brief Format value for bitfield RTC_CR_SWR. */ -#define BF_RTC_CR_SWR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SWR) & BM_RTC_CR_SWR) - -/*! @brief Set the SWR field to a new value. */ -#define BW_RTC_CR_SWR(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field WPE[1] (RW) - * - * The wakeup pin is optional and not available on all devices. - * - * Values: - * - 0 - Wakeup pin is disabled. - * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt - * asserts or the wakeup pin is turned on. - */ -/*@{*/ -#define BP_RTC_CR_WPE (1U) /*!< Bit position for RTC_CR_WPE. */ -#define BM_RTC_CR_WPE (0x00000002U) /*!< Bit mask for RTC_CR_WPE. */ -#define BS_RTC_CR_WPE (1U) /*!< Bit field size in bits for RTC_CR_WPE. */ - -/*! @brief Read current value of the RTC_CR_WPE field. */ -#define BR_RTC_CR_WPE(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE)) - -/*! @brief Format value for bitfield RTC_CR_WPE. */ -#define BF_RTC_CR_WPE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPE) & BM_RTC_CR_WPE) - -/*! @brief Set the WPE field to a new value. */ -#define BW_RTC_CR_WPE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SUP[2] (RW) - * - * Values: - * - 0 - Non-supervisor mode write accesses are not supported and generate a bus - * error. - * - 1 - Non-supervisor mode write accesses are supported. - */ -/*@{*/ -#define BP_RTC_CR_SUP (2U) /*!< Bit position for RTC_CR_SUP. */ -#define BM_RTC_CR_SUP (0x00000004U) /*!< Bit mask for RTC_CR_SUP. */ -#define BS_RTC_CR_SUP (1U) /*!< Bit field size in bits for RTC_CR_SUP. */ - -/*! @brief Read current value of the RTC_CR_SUP field. */ -#define BR_RTC_CR_SUP(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP)) - -/*! @brief Format value for bitfield RTC_CR_SUP. */ -#define BF_RTC_CR_SUP(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SUP) & BM_RTC_CR_SUP) - -/*! @brief Set the SUP field to a new value. */ -#define BW_RTC_CR_SUP(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field UM[3] (RW) - * - * Allows SR[TCE] to be written even when the Status Register is locked. When - * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if - * the SR[TCE] is clear. - * - * Values: - * - 0 - Registers cannot be written when locked. - * - 1 - Registers can be written when locked under limited conditions. - */ -/*@{*/ -#define BP_RTC_CR_UM (3U) /*!< Bit position for RTC_CR_UM. */ -#define BM_RTC_CR_UM (0x00000008U) /*!< Bit mask for RTC_CR_UM. */ -#define BS_RTC_CR_UM (1U) /*!< Bit field size in bits for RTC_CR_UM. */ - -/*! @brief Read current value of the RTC_CR_UM field. */ -#define BR_RTC_CR_UM(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM)) - -/*! @brief Format value for bitfield RTC_CR_UM. */ -#define BF_RTC_CR_UM(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_UM) & BM_RTC_CR_UM) - -/*! @brief Set the UM field to a new value. */ -#define BW_RTC_CR_UM(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field WPS[4] (RW) - * - * The wakeup pin is optional and not available on all devices. - * - * Values: - * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt - * asserts or the wakeup pin is turned on. - * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin - * is turned on and the 32kHz clock is output to other peripherals. - */ -/*@{*/ -#define BP_RTC_CR_WPS (4U) /*!< Bit position for RTC_CR_WPS. */ -#define BM_RTC_CR_WPS (0x00000010U) /*!< Bit mask for RTC_CR_WPS. */ -#define BS_RTC_CR_WPS (1U) /*!< Bit field size in bits for RTC_CR_WPS. */ - -/*! @brief Read current value of the RTC_CR_WPS field. */ -#define BR_RTC_CR_WPS(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS)) - -/*! @brief Format value for bitfield RTC_CR_WPS. */ -#define BF_RTC_CR_WPS(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPS) & BM_RTC_CR_WPS) - -/*! @brief Set the WPS field to a new value. */ -#define BW_RTC_CR_WPS(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field OSCE[8] (RW) - * - * Values: - * - 0 - 32.768 kHz oscillator is disabled. - * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the - * oscillator startup time before enabling the time counter to allow the 32.768 - * kHz clock time to stabilize. - */ -/*@{*/ -#define BP_RTC_CR_OSCE (8U) /*!< Bit position for RTC_CR_OSCE. */ -#define BM_RTC_CR_OSCE (0x00000100U) /*!< Bit mask for RTC_CR_OSCE. */ -#define BS_RTC_CR_OSCE (1U) /*!< Bit field size in bits for RTC_CR_OSCE. */ - -/*! @brief Read current value of the RTC_CR_OSCE field. */ -#define BR_RTC_CR_OSCE(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE)) - -/*! @brief Format value for bitfield RTC_CR_OSCE. */ -#define BF_RTC_CR_OSCE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_OSCE) & BM_RTC_CR_OSCE) - -/*! @brief Set the OSCE field to a new value. */ -#define BW_RTC_CR_OSCE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field CLKO[9] (RW) - * - * Values: - * - 0 - The 32 kHz clock is output to other peripherals. - * - 1 - The 32 kHz clock is not output to other peripherals. - */ -/*@{*/ -#define BP_RTC_CR_CLKO (9U) /*!< Bit position for RTC_CR_CLKO. */ -#define BM_RTC_CR_CLKO (0x00000200U) /*!< Bit mask for RTC_CR_CLKO. */ -#define BS_RTC_CR_CLKO (1U) /*!< Bit field size in bits for RTC_CR_CLKO. */ - -/*! @brief Read current value of the RTC_CR_CLKO field. */ -#define BR_RTC_CR_CLKO(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO)) - -/*! @brief Format value for bitfield RTC_CR_CLKO. */ -#define BF_RTC_CR_CLKO(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_CLKO) & BM_RTC_CR_CLKO) - -/*! @brief Set the CLKO field to a new value. */ -#define BW_RTC_CR_CLKO(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC16P[10] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC16P (10U) /*!< Bit position for RTC_CR_SC16P. */ -#define BM_RTC_CR_SC16P (0x00000400U) /*!< Bit mask for RTC_CR_SC16P. */ -#define BS_RTC_CR_SC16P (1U) /*!< Bit field size in bits for RTC_CR_SC16P. */ - -/*! @brief Read current value of the RTC_CR_SC16P field. */ -#define BR_RTC_CR_SC16P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P)) - -/*! @brief Format value for bitfield RTC_CR_SC16P. */ -#define BF_RTC_CR_SC16P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC16P) & BM_RTC_CR_SC16P) - -/*! @brief Set the SC16P field to a new value. */ -#define BW_RTC_CR_SC16P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC8P[11] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC8P (11U) /*!< Bit position for RTC_CR_SC8P. */ -#define BM_RTC_CR_SC8P (0x00000800U) /*!< Bit mask for RTC_CR_SC8P. */ -#define BS_RTC_CR_SC8P (1U) /*!< Bit field size in bits for RTC_CR_SC8P. */ - -/*! @brief Read current value of the RTC_CR_SC8P field. */ -#define BR_RTC_CR_SC8P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P)) - -/*! @brief Format value for bitfield RTC_CR_SC8P. */ -#define BF_RTC_CR_SC8P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC8P) & BM_RTC_CR_SC8P) - -/*! @brief Set the SC8P field to a new value. */ -#define BW_RTC_CR_SC8P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC4P[12] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC4P (12U) /*!< Bit position for RTC_CR_SC4P. */ -#define BM_RTC_CR_SC4P (0x00001000U) /*!< Bit mask for RTC_CR_SC4P. */ -#define BS_RTC_CR_SC4P (1U) /*!< Bit field size in bits for RTC_CR_SC4P. */ - -/*! @brief Read current value of the RTC_CR_SC4P field. */ -#define BR_RTC_CR_SC4P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P)) - -/*! @brief Format value for bitfield RTC_CR_SC4P. */ -#define BF_RTC_CR_SC4P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC4P) & BM_RTC_CR_SC4P) - -/*! @brief Set the SC4P field to a new value. */ -#define BW_RTC_CR_SC4P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P) = (v)) -/*@}*/ - -/*! - * @name Register RTC_CR, field SC2P[13] (RW) - * - * Values: - * - 0 - Disable the load. - * - 1 - Enable the additional load. - */ -/*@{*/ -#define BP_RTC_CR_SC2P (13U) /*!< Bit position for RTC_CR_SC2P. */ -#define BM_RTC_CR_SC2P (0x00002000U) /*!< Bit mask for RTC_CR_SC2P. */ -#define BS_RTC_CR_SC2P (1U) /*!< Bit field size in bits for RTC_CR_SC2P. */ - -/*! @brief Read current value of the RTC_CR_SC2P field. */ -#define BR_RTC_CR_SC2P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P)) - -/*! @brief Format value for bitfield RTC_CR_SC2P. */ -#define BF_RTC_CR_SC2P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC2P) & BM_RTC_CR_SC2P) - -/*! @brief Set the SC2P field to a new value. */ -#define BW_RTC_CR_SC2P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_SR - RTC Status Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_SR - RTC Status Register (RW) - * - * Reset value: 0x00000001U - */ -typedef union _hw_rtc_sr -{ - uint32_t U; - struct _hw_rtc_sr_bitfields - { - uint32_t TIF : 1; /*!< [0] Time Invalid Flag */ - uint32_t TOF : 1; /*!< [1] Time Overflow Flag */ - uint32_t TAF : 1; /*!< [2] Time Alarm Flag */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TCE : 1; /*!< [4] Time Counter Enable */ - uint32_t RESERVED1 : 27; /*!< [31:5] */ - } B; -} hw_rtc_sr_t; - -/*! - * @name Constants and macros for entire RTC_SR register - */ -/*@{*/ -#define HW_RTC_SR_ADDR(x) ((x) + 0x14U) - -#define HW_RTC_SR(x) (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR(x)) -#define HW_RTC_SR_RD(x) (HW_RTC_SR(x).U) -#define HW_RTC_SR_WR(x, v) (HW_RTC_SR(x).U = (v)) -#define HW_RTC_SR_SET(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) | (v))) -#define HW_RTC_SR_CLR(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) & ~(v))) -#define HW_RTC_SR_TOG(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_SR bitfields - */ - -/*! - * @name Register RTC_SR, field TIF[0] (RO) - * - * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR - * do not increment and read as zero when this bit is set. This bit is cleared by - * writing the TSR register when the time counter is disabled. - * - * Values: - * - 0 - Time is valid. - * - 1 - Time is invalid and time counter is read as zero. - */ -/*@{*/ -#define BP_RTC_SR_TIF (0U) /*!< Bit position for RTC_SR_TIF. */ -#define BM_RTC_SR_TIF (0x00000001U) /*!< Bit mask for RTC_SR_TIF. */ -#define BS_RTC_SR_TIF (1U) /*!< Bit field size in bits for RTC_SR_TIF. */ - -/*! @brief Read current value of the RTC_SR_TIF field. */ -#define BR_RTC_SR_TIF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TIF)) -/*@}*/ - -/*! - * @name Register RTC_SR, field TOF[1] (RO) - * - * Time overflow flag is set when the time counter is enabled and overflows. The - * TSR and TPR do not increment and read as zero when this bit is set. This bit - * is cleared by writing the TSR register when the time counter is disabled. - * - * Values: - * - 0 - Time overflow has not occurred. - * - 1 - Time overflow has occurred and time counter is read as zero. - */ -/*@{*/ -#define BP_RTC_SR_TOF (1U) /*!< Bit position for RTC_SR_TOF. */ -#define BM_RTC_SR_TOF (0x00000002U) /*!< Bit mask for RTC_SR_TOF. */ -#define BS_RTC_SR_TOF (1U) /*!< Bit field size in bits for RTC_SR_TOF. */ - -/*! @brief Read current value of the RTC_SR_TOF field. */ -#define BR_RTC_SR_TOF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TOF)) -/*@}*/ - -/*! - * @name Register RTC_SR, field TAF[2] (RO) - * - * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] - * increments. This bit is cleared by writing the TAR register. - * - * Values: - * - 0 - Time alarm has not occurred. - * - 1 - Time alarm has occurred. - */ -/*@{*/ -#define BP_RTC_SR_TAF (2U) /*!< Bit position for RTC_SR_TAF. */ -#define BM_RTC_SR_TAF (0x00000004U) /*!< Bit mask for RTC_SR_TAF. */ -#define BS_RTC_SR_TAF (1U) /*!< Bit field size in bits for RTC_SR_TAF. */ - -/*! @brief Read current value of the RTC_SR_TAF field. */ -#define BR_RTC_SR_TAF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TAF)) -/*@}*/ - -/*! - * @name Register RTC_SR, field TCE[4] (RW) - * - * When time counter is disabled the TSR register and TPR register are - * writeable, but do not increment. When time counter is enabled the TSR register and TPR - * register are not writeable, but increment. - * - * Values: - * - 0 - Time counter is disabled. - * - 1 - Time counter is enabled. - */ -/*@{*/ -#define BP_RTC_SR_TCE (4U) /*!< Bit position for RTC_SR_TCE. */ -#define BM_RTC_SR_TCE (0x00000010U) /*!< Bit mask for RTC_SR_TCE. */ -#define BS_RTC_SR_TCE (1U) /*!< Bit field size in bits for RTC_SR_TCE. */ - -/*! @brief Read current value of the RTC_SR_TCE field. */ -#define BR_RTC_SR_TCE(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE)) - -/*! @brief Format value for bitfield RTC_SR_TCE. */ -#define BF_RTC_SR_TCE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_SR_TCE) & BM_RTC_SR_TCE) - -/*! @brief Set the TCE field to a new value. */ -#define BW_RTC_SR_TCE(x, v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_LR - RTC Lock Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_LR - RTC Lock Register (RW) - * - * Reset value: 0x000000FFU - */ -typedef union _hw_rtc_lr -{ - uint32_t U; - struct _hw_rtc_lr_bitfields - { - uint32_t RESERVED0 : 3; /*!< [2:0] */ - uint32_t TCL : 1; /*!< [3] Time Compensation Lock */ - uint32_t CRL : 1; /*!< [4] Control Register Lock */ - uint32_t SRL : 1; /*!< [5] Status Register Lock */ - uint32_t LRL : 1; /*!< [6] Lock Register Lock */ - uint32_t RESERVED1 : 25; /*!< [31:7] */ - } B; -} hw_rtc_lr_t; - -/*! - * @name Constants and macros for entire RTC_LR register - */ -/*@{*/ -#define HW_RTC_LR_ADDR(x) ((x) + 0x18U) - -#define HW_RTC_LR(x) (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR(x)) -#define HW_RTC_LR_RD(x) (HW_RTC_LR(x).U) -#define HW_RTC_LR_WR(x, v) (HW_RTC_LR(x).U = (v)) -#define HW_RTC_LR_SET(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) | (v))) -#define HW_RTC_LR_CLR(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) & ~(v))) -#define HW_RTC_LR_TOG(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_LR bitfields - */ - -/*! - * @name Register RTC_LR, field TCL[3] (RW) - * - * After being cleared, this bit can be set only by VBAT POR or software reset. - * - * Values: - * - 0 - Time Compensation Register is locked and writes are ignored. - * - 1 - Time Compensation Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_TCL (3U) /*!< Bit position for RTC_LR_TCL. */ -#define BM_RTC_LR_TCL (0x00000008U) /*!< Bit mask for RTC_LR_TCL. */ -#define BS_RTC_LR_TCL (1U) /*!< Bit field size in bits for RTC_LR_TCL. */ - -/*! @brief Read current value of the RTC_LR_TCL field. */ -#define BR_RTC_LR_TCL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL)) - -/*! @brief Format value for bitfield RTC_LR_TCL. */ -#define BF_RTC_LR_TCL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_TCL) & BM_RTC_LR_TCL) - -/*! @brief Set the TCL field to a new value. */ -#define BW_RTC_LR_TCL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL) = (v)) -/*@}*/ - -/*! - * @name Register RTC_LR, field CRL[4] (RW) - * - * After being cleared, this bit can only be set by VBAT POR. - * - * Values: - * - 0 - Control Register is locked and writes are ignored. - * - 1 - Control Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_CRL (4U) /*!< Bit position for RTC_LR_CRL. */ -#define BM_RTC_LR_CRL (0x00000010U) /*!< Bit mask for RTC_LR_CRL. */ -#define BS_RTC_LR_CRL (1U) /*!< Bit field size in bits for RTC_LR_CRL. */ - -/*! @brief Read current value of the RTC_LR_CRL field. */ -#define BR_RTC_LR_CRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL)) - -/*! @brief Format value for bitfield RTC_LR_CRL. */ -#define BF_RTC_LR_CRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_CRL) & BM_RTC_LR_CRL) - -/*! @brief Set the CRL field to a new value. */ -#define BW_RTC_LR_CRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL) = (v)) -/*@}*/ - -/*! - * @name Register RTC_LR, field SRL[5] (RW) - * - * After being cleared, this bit can be set only by VBAT POR or software reset. - * - * Values: - * - 0 - Status Register is locked and writes are ignored. - * - 1 - Status Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_SRL (5U) /*!< Bit position for RTC_LR_SRL. */ -#define BM_RTC_LR_SRL (0x00000020U) /*!< Bit mask for RTC_LR_SRL. */ -#define BS_RTC_LR_SRL (1U) /*!< Bit field size in bits for RTC_LR_SRL. */ - -/*! @brief Read current value of the RTC_LR_SRL field. */ -#define BR_RTC_LR_SRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL)) - -/*! @brief Format value for bitfield RTC_LR_SRL. */ -#define BF_RTC_LR_SRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_SRL) & BM_RTC_LR_SRL) - -/*! @brief Set the SRL field to a new value. */ -#define BW_RTC_LR_SRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL) = (v)) -/*@}*/ - -/*! - * @name Register RTC_LR, field LRL[6] (RW) - * - * After being cleared, this bit can be set only by VBAT POR or software reset. - * - * Values: - * - 0 - Lock Register is locked and writes are ignored. - * - 1 - Lock Register is not locked and writes complete as normal. - */ -/*@{*/ -#define BP_RTC_LR_LRL (6U) /*!< Bit position for RTC_LR_LRL. */ -#define BM_RTC_LR_LRL (0x00000040U) /*!< Bit mask for RTC_LR_LRL. */ -#define BS_RTC_LR_LRL (1U) /*!< Bit field size in bits for RTC_LR_LRL. */ - -/*! @brief Read current value of the RTC_LR_LRL field. */ -#define BR_RTC_LR_LRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL)) - -/*! @brief Format value for bitfield RTC_LR_LRL. */ -#define BF_RTC_LR_LRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_LRL) & BM_RTC_LR_LRL) - -/*! @brief Set the LRL field to a new value. */ -#define BW_RTC_LR_LRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_IER - RTC Interrupt Enable Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW) - * - * Reset value: 0x00000007U - */ -typedef union _hw_rtc_ier -{ - uint32_t U; - struct _hw_rtc_ier_bitfields - { - uint32_t TIIE : 1; /*!< [0] Time Invalid Interrupt Enable */ - uint32_t TOIE : 1; /*!< [1] Time Overflow Interrupt Enable */ - uint32_t TAIE : 1; /*!< [2] Time Alarm Interrupt Enable */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t TSIE : 1; /*!< [4] Time Seconds Interrupt Enable */ - uint32_t RESERVED1 : 2; /*!< [6:5] */ - uint32_t WPON : 1; /*!< [7] Wakeup Pin On */ - uint32_t RESERVED2 : 24; /*!< [31:8] */ - } B; -} hw_rtc_ier_t; - -/*! - * @name Constants and macros for entire RTC_IER register - */ -/*@{*/ -#define HW_RTC_IER_ADDR(x) ((x) + 0x1CU) - -#define HW_RTC_IER(x) (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR(x)) -#define HW_RTC_IER_RD(x) (HW_RTC_IER(x).U) -#define HW_RTC_IER_WR(x, v) (HW_RTC_IER(x).U = (v)) -#define HW_RTC_IER_SET(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) | (v))) -#define HW_RTC_IER_CLR(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) & ~(v))) -#define HW_RTC_IER_TOG(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_IER bitfields - */ - -/*! - * @name Register RTC_IER, field TIIE[0] (RW) - * - * Values: - * - 0 - Time invalid flag does not generate an interrupt. - * - 1 - Time invalid flag does generate an interrupt. - */ -/*@{*/ -#define BP_RTC_IER_TIIE (0U) /*!< Bit position for RTC_IER_TIIE. */ -#define BM_RTC_IER_TIIE (0x00000001U) /*!< Bit mask for RTC_IER_TIIE. */ -#define BS_RTC_IER_TIIE (1U) /*!< Bit field size in bits for RTC_IER_TIIE. */ - -/*! @brief Read current value of the RTC_IER_TIIE field. */ -#define BR_RTC_IER_TIIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE)) - -/*! @brief Format value for bitfield RTC_IER_TIIE. */ -#define BF_RTC_IER_TIIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TIIE) & BM_RTC_IER_TIIE) - -/*! @brief Set the TIIE field to a new value. */ -#define BW_RTC_IER_TIIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field TOIE[1] (RW) - * - * Values: - * - 0 - Time overflow flag does not generate an interrupt. - * - 1 - Time overflow flag does generate an interrupt. - */ -/*@{*/ -#define BP_RTC_IER_TOIE (1U) /*!< Bit position for RTC_IER_TOIE. */ -#define BM_RTC_IER_TOIE (0x00000002U) /*!< Bit mask for RTC_IER_TOIE. */ -#define BS_RTC_IER_TOIE (1U) /*!< Bit field size in bits for RTC_IER_TOIE. */ - -/*! @brief Read current value of the RTC_IER_TOIE field. */ -#define BR_RTC_IER_TOIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE)) - -/*! @brief Format value for bitfield RTC_IER_TOIE. */ -#define BF_RTC_IER_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TOIE) & BM_RTC_IER_TOIE) - -/*! @brief Set the TOIE field to a new value. */ -#define BW_RTC_IER_TOIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field TAIE[2] (RW) - * - * Values: - * - 0 - Time alarm flag does not generate an interrupt. - * - 1 - Time alarm flag does generate an interrupt. - */ -/*@{*/ -#define BP_RTC_IER_TAIE (2U) /*!< Bit position for RTC_IER_TAIE. */ -#define BM_RTC_IER_TAIE (0x00000004U) /*!< Bit mask for RTC_IER_TAIE. */ -#define BS_RTC_IER_TAIE (1U) /*!< Bit field size in bits for RTC_IER_TAIE. */ - -/*! @brief Read current value of the RTC_IER_TAIE field. */ -#define BR_RTC_IER_TAIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE)) - -/*! @brief Format value for bitfield RTC_IER_TAIE. */ -#define BF_RTC_IER_TAIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TAIE) & BM_RTC_IER_TAIE) - -/*! @brief Set the TAIE field to a new value. */ -#define BW_RTC_IER_TAIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field TSIE[4] (RW) - * - * The seconds interrupt is an edge-sensitive interrupt with a dedicated - * interrupt vector. It is generated once a second and requires no software overhead - * (there is no corresponding status flag to clear). - * - * Values: - * - 0 - Seconds interrupt is disabled. - * - 1 - Seconds interrupt is enabled. - */ -/*@{*/ -#define BP_RTC_IER_TSIE (4U) /*!< Bit position for RTC_IER_TSIE. */ -#define BM_RTC_IER_TSIE (0x00000010U) /*!< Bit mask for RTC_IER_TSIE. */ -#define BS_RTC_IER_TSIE (1U) /*!< Bit field size in bits for RTC_IER_TSIE. */ - -/*! @brief Read current value of the RTC_IER_TSIE field. */ -#define BR_RTC_IER_TSIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE)) - -/*! @brief Format value for bitfield RTC_IER_TSIE. */ -#define BF_RTC_IER_TSIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TSIE) & BM_RTC_IER_TSIE) - -/*! @brief Set the TSIE field to a new value. */ -#define BW_RTC_IER_TSIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE) = (v)) -/*@}*/ - -/*! - * @name Register RTC_IER, field WPON[7] (RW) - * - * The wakeup pin is optional and not available on all devices. Whenever the - * wakeup pin is enabled and this bit is set, the wakeup pin will assert. - * - * Values: - * - 0 - No effect. - * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert. - */ -/*@{*/ -#define BP_RTC_IER_WPON (7U) /*!< Bit position for RTC_IER_WPON. */ -#define BM_RTC_IER_WPON (0x00000080U) /*!< Bit mask for RTC_IER_WPON. */ -#define BS_RTC_IER_WPON (1U) /*!< Bit field size in bits for RTC_IER_WPON. */ - -/*! @brief Read current value of the RTC_IER_WPON field. */ -#define BR_RTC_IER_WPON(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON)) - -/*! @brief Format value for bitfield RTC_IER_WPON. */ -#define BF_RTC_IER_WPON(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_WPON) & BM_RTC_IER_WPON) - -/*! @brief Set the WPON field to a new value. */ -#define BW_RTC_IER_WPON(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_WAR - RTC Write Access Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_WAR - RTC Write Access Register (RW) - * - * Reset value: 0x000000FFU - */ -typedef union _hw_rtc_war -{ - uint32_t U; - struct _hw_rtc_war_bitfields - { - uint32_t TSRW : 1; /*!< [0] Time Seconds Register Write */ - uint32_t TPRW : 1; /*!< [1] Time Prescaler Register Write */ - uint32_t TARW : 1; /*!< [2] Time Alarm Register Write */ - uint32_t TCRW : 1; /*!< [3] Time Compensation Register Write */ - uint32_t CRW : 1; /*!< [4] Control Register Write */ - uint32_t SRW : 1; /*!< [5] Status Register Write */ - uint32_t LRW : 1; /*!< [6] Lock Register Write */ - uint32_t IERW : 1; /*!< [7] Interrupt Enable Register Write */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_rtc_war_t; - -/*! - * @name Constants and macros for entire RTC_WAR register - */ -/*@{*/ -#define HW_RTC_WAR_ADDR(x) ((x) + 0x800U) - -#define HW_RTC_WAR(x) (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR(x)) -#define HW_RTC_WAR_RD(x) (HW_RTC_WAR(x).U) -#define HW_RTC_WAR_WR(x, v) (HW_RTC_WAR(x).U = (v)) -#define HW_RTC_WAR_SET(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) | (v))) -#define HW_RTC_WAR_CLR(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) & ~(v))) -#define HW_RTC_WAR_TOG(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_WAR bitfields - */ - -/*! - * @name Register RTC_WAR, field TSRW[0] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Seconds Register are ignored. - * - 1 - Writes to the Time Seconds Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TSRW (0U) /*!< Bit position for RTC_WAR_TSRW. */ -#define BM_RTC_WAR_TSRW (0x00000001U) /*!< Bit mask for RTC_WAR_TSRW. */ -#define BS_RTC_WAR_TSRW (1U) /*!< Bit field size in bits for RTC_WAR_TSRW. */ - -/*! @brief Read current value of the RTC_WAR_TSRW field. */ -#define BR_RTC_WAR_TSRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW)) - -/*! @brief Format value for bitfield RTC_WAR_TSRW. */ -#define BF_RTC_WAR_TSRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TSRW) & BM_RTC_WAR_TSRW) - -/*! @brief Set the TSRW field to a new value. */ -#define BW_RTC_WAR_TSRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field TPRW[1] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Prescaler Register are ignored. - * - 1 - Writes to the Time Prescaler Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TPRW (1U) /*!< Bit position for RTC_WAR_TPRW. */ -#define BM_RTC_WAR_TPRW (0x00000002U) /*!< Bit mask for RTC_WAR_TPRW. */ -#define BS_RTC_WAR_TPRW (1U) /*!< Bit field size in bits for RTC_WAR_TPRW. */ - -/*! @brief Read current value of the RTC_WAR_TPRW field. */ -#define BR_RTC_WAR_TPRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW)) - -/*! @brief Format value for bitfield RTC_WAR_TPRW. */ -#define BF_RTC_WAR_TPRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TPRW) & BM_RTC_WAR_TPRW) - -/*! @brief Set the TPRW field to a new value. */ -#define BW_RTC_WAR_TPRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field TARW[2] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Alarm Register are ignored. - * - 1 - Writes to the Time Alarm Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TARW (2U) /*!< Bit position for RTC_WAR_TARW. */ -#define BM_RTC_WAR_TARW (0x00000004U) /*!< Bit mask for RTC_WAR_TARW. */ -#define BS_RTC_WAR_TARW (1U) /*!< Bit field size in bits for RTC_WAR_TARW. */ - -/*! @brief Read current value of the RTC_WAR_TARW field. */ -#define BR_RTC_WAR_TARW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW)) - -/*! @brief Format value for bitfield RTC_WAR_TARW. */ -#define BF_RTC_WAR_TARW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TARW) & BM_RTC_WAR_TARW) - -/*! @brief Set the TARW field to a new value. */ -#define BW_RTC_WAR_TARW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field TCRW[3] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Time Compensation Register are ignored. - * - 1 - Writes to the Time Compensation Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_TCRW (3U) /*!< Bit position for RTC_WAR_TCRW. */ -#define BM_RTC_WAR_TCRW (0x00000008U) /*!< Bit mask for RTC_WAR_TCRW. */ -#define BS_RTC_WAR_TCRW (1U) /*!< Bit field size in bits for RTC_WAR_TCRW. */ - -/*! @brief Read current value of the RTC_WAR_TCRW field. */ -#define BR_RTC_WAR_TCRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW)) - -/*! @brief Format value for bitfield RTC_WAR_TCRW. */ -#define BF_RTC_WAR_TCRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TCRW) & BM_RTC_WAR_TCRW) - -/*! @brief Set the TCRW field to a new value. */ -#define BW_RTC_WAR_TCRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field CRW[4] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Control Register are ignored. - * - 1 - Writes to the Control Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_CRW (4U) /*!< Bit position for RTC_WAR_CRW. */ -#define BM_RTC_WAR_CRW (0x00000010U) /*!< Bit mask for RTC_WAR_CRW. */ -#define BS_RTC_WAR_CRW (1U) /*!< Bit field size in bits for RTC_WAR_CRW. */ - -/*! @brief Read current value of the RTC_WAR_CRW field. */ -#define BR_RTC_WAR_CRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW)) - -/*! @brief Format value for bitfield RTC_WAR_CRW. */ -#define BF_RTC_WAR_CRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_CRW) & BM_RTC_WAR_CRW) - -/*! @brief Set the CRW field to a new value. */ -#define BW_RTC_WAR_CRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field SRW[5] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Status Register are ignored. - * - 1 - Writes to the Status Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_SRW (5U) /*!< Bit position for RTC_WAR_SRW. */ -#define BM_RTC_WAR_SRW (0x00000020U) /*!< Bit mask for RTC_WAR_SRW. */ -#define BS_RTC_WAR_SRW (1U) /*!< Bit field size in bits for RTC_WAR_SRW. */ - -/*! @brief Read current value of the RTC_WAR_SRW field. */ -#define BR_RTC_WAR_SRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW)) - -/*! @brief Format value for bitfield RTC_WAR_SRW. */ -#define BF_RTC_WAR_SRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_SRW) & BM_RTC_WAR_SRW) - -/*! @brief Set the SRW field to a new value. */ -#define BW_RTC_WAR_SRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field LRW[6] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Lock Register are ignored. - * - 1 - Writes to the Lock Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_LRW (6U) /*!< Bit position for RTC_WAR_LRW. */ -#define BM_RTC_WAR_LRW (0x00000040U) /*!< Bit mask for RTC_WAR_LRW. */ -#define BS_RTC_WAR_LRW (1U) /*!< Bit field size in bits for RTC_WAR_LRW. */ - -/*! @brief Read current value of the RTC_WAR_LRW field. */ -#define BR_RTC_WAR_LRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW)) - -/*! @brief Format value for bitfield RTC_WAR_LRW. */ -#define BF_RTC_WAR_LRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_LRW) & BM_RTC_WAR_LRW) - -/*! @brief Set the LRW field to a new value. */ -#define BW_RTC_WAR_LRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW) = (v)) -/*@}*/ - -/*! - * @name Register RTC_WAR, field IERW[7] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Writes to the Interupt Enable Register are ignored. - * - 1 - Writes to the Interrupt Enable Register complete as normal. - */ -/*@{*/ -#define BP_RTC_WAR_IERW (7U) /*!< Bit position for RTC_WAR_IERW. */ -#define BM_RTC_WAR_IERW (0x00000080U) /*!< Bit mask for RTC_WAR_IERW. */ -#define BS_RTC_WAR_IERW (1U) /*!< Bit field size in bits for RTC_WAR_IERW. */ - -/*! @brief Read current value of the RTC_WAR_IERW field. */ -#define BR_RTC_WAR_IERW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW)) - -/*! @brief Format value for bitfield RTC_WAR_IERW. */ -#define BF_RTC_WAR_IERW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_IERW) & BM_RTC_WAR_IERW) - -/*! @brief Set the IERW field to a new value. */ -#define BW_RTC_WAR_IERW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_RTC_RAR - RTC Read Access Register - ******************************************************************************/ - -/*! - * @brief HW_RTC_RAR - RTC Read Access Register (RW) - * - * Reset value: 0x000000FFU - */ -typedef union _hw_rtc_rar -{ - uint32_t U; - struct _hw_rtc_rar_bitfields - { - uint32_t TSRR : 1; /*!< [0] Time Seconds Register Read */ - uint32_t TPRR : 1; /*!< [1] Time Prescaler Register Read */ - uint32_t TARR : 1; /*!< [2] Time Alarm Register Read */ - uint32_t TCRR : 1; /*!< [3] Time Compensation Register Read */ - uint32_t CRR : 1; /*!< [4] Control Register Read */ - uint32_t SRR : 1; /*!< [5] Status Register Read */ - uint32_t LRR : 1; /*!< [6] Lock Register Read */ - uint32_t IERR : 1; /*!< [7] Interrupt Enable Register Read */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_rtc_rar_t; - -/*! - * @name Constants and macros for entire RTC_RAR register - */ -/*@{*/ -#define HW_RTC_RAR_ADDR(x) ((x) + 0x804U) - -#define HW_RTC_RAR(x) (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR(x)) -#define HW_RTC_RAR_RD(x) (HW_RTC_RAR(x).U) -#define HW_RTC_RAR_WR(x, v) (HW_RTC_RAR(x).U = (v)) -#define HW_RTC_RAR_SET(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) | (v))) -#define HW_RTC_RAR_CLR(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) & ~(v))) -#define HW_RTC_RAR_TOG(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual RTC_RAR bitfields - */ - -/*! - * @name Register RTC_RAR, field TSRR[0] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Seconds Register are ignored. - * - 1 - Reads to the Time Seconds Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TSRR (0U) /*!< Bit position for RTC_RAR_TSRR. */ -#define BM_RTC_RAR_TSRR (0x00000001U) /*!< Bit mask for RTC_RAR_TSRR. */ -#define BS_RTC_RAR_TSRR (1U) /*!< Bit field size in bits for RTC_RAR_TSRR. */ - -/*! @brief Read current value of the RTC_RAR_TSRR field. */ -#define BR_RTC_RAR_TSRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR)) - -/*! @brief Format value for bitfield RTC_RAR_TSRR. */ -#define BF_RTC_RAR_TSRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TSRR) & BM_RTC_RAR_TSRR) - -/*! @brief Set the TSRR field to a new value. */ -#define BW_RTC_RAR_TSRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field TPRR[1] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Pprescaler Register are ignored. - * - 1 - Reads to the Time Prescaler Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TPRR (1U) /*!< Bit position for RTC_RAR_TPRR. */ -#define BM_RTC_RAR_TPRR (0x00000002U) /*!< Bit mask for RTC_RAR_TPRR. */ -#define BS_RTC_RAR_TPRR (1U) /*!< Bit field size in bits for RTC_RAR_TPRR. */ - -/*! @brief Read current value of the RTC_RAR_TPRR field. */ -#define BR_RTC_RAR_TPRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR)) - -/*! @brief Format value for bitfield RTC_RAR_TPRR. */ -#define BF_RTC_RAR_TPRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TPRR) & BM_RTC_RAR_TPRR) - -/*! @brief Set the TPRR field to a new value. */ -#define BW_RTC_RAR_TPRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field TARR[2] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Alarm Register are ignored. - * - 1 - Reads to the Time Alarm Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TARR (2U) /*!< Bit position for RTC_RAR_TARR. */ -#define BM_RTC_RAR_TARR (0x00000004U) /*!< Bit mask for RTC_RAR_TARR. */ -#define BS_RTC_RAR_TARR (1U) /*!< Bit field size in bits for RTC_RAR_TARR. */ - -/*! @brief Read current value of the RTC_RAR_TARR field. */ -#define BR_RTC_RAR_TARR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR)) - -/*! @brief Format value for bitfield RTC_RAR_TARR. */ -#define BF_RTC_RAR_TARR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TARR) & BM_RTC_RAR_TARR) - -/*! @brief Set the TARR field to a new value. */ -#define BW_RTC_RAR_TARR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field TCRR[3] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Time Compensation Register are ignored. - * - 1 - Reads to the Time Compensation Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_TCRR (3U) /*!< Bit position for RTC_RAR_TCRR. */ -#define BM_RTC_RAR_TCRR (0x00000008U) /*!< Bit mask for RTC_RAR_TCRR. */ -#define BS_RTC_RAR_TCRR (1U) /*!< Bit field size in bits for RTC_RAR_TCRR. */ - -/*! @brief Read current value of the RTC_RAR_TCRR field. */ -#define BR_RTC_RAR_TCRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR)) - -/*! @brief Format value for bitfield RTC_RAR_TCRR. */ -#define BF_RTC_RAR_TCRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TCRR) & BM_RTC_RAR_TCRR) - -/*! @brief Set the TCRR field to a new value. */ -#define BW_RTC_RAR_TCRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field CRR[4] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Control Register are ignored. - * - 1 - Reads to the Control Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_CRR (4U) /*!< Bit position for RTC_RAR_CRR. */ -#define BM_RTC_RAR_CRR (0x00000010U) /*!< Bit mask for RTC_RAR_CRR. */ -#define BS_RTC_RAR_CRR (1U) /*!< Bit field size in bits for RTC_RAR_CRR. */ - -/*! @brief Read current value of the RTC_RAR_CRR field. */ -#define BR_RTC_RAR_CRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR)) - -/*! @brief Format value for bitfield RTC_RAR_CRR. */ -#define BF_RTC_RAR_CRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_CRR) & BM_RTC_RAR_CRR) - -/*! @brief Set the CRR field to a new value. */ -#define BW_RTC_RAR_CRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field SRR[5] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Status Register are ignored. - * - 1 - Reads to the Status Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_SRR (5U) /*!< Bit position for RTC_RAR_SRR. */ -#define BM_RTC_RAR_SRR (0x00000020U) /*!< Bit mask for RTC_RAR_SRR. */ -#define BS_RTC_RAR_SRR (1U) /*!< Bit field size in bits for RTC_RAR_SRR. */ - -/*! @brief Read current value of the RTC_RAR_SRR field. */ -#define BR_RTC_RAR_SRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR)) - -/*! @brief Format value for bitfield RTC_RAR_SRR. */ -#define BF_RTC_RAR_SRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_SRR) & BM_RTC_RAR_SRR) - -/*! @brief Set the SRR field to a new value. */ -#define BW_RTC_RAR_SRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field LRR[6] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Lock Register are ignored. - * - 1 - Reads to the Lock Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_LRR (6U) /*!< Bit position for RTC_RAR_LRR. */ -#define BM_RTC_RAR_LRR (0x00000040U) /*!< Bit mask for RTC_RAR_LRR. */ -#define BS_RTC_RAR_LRR (1U) /*!< Bit field size in bits for RTC_RAR_LRR. */ - -/*! @brief Read current value of the RTC_RAR_LRR field. */ -#define BR_RTC_RAR_LRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR)) - -/*! @brief Format value for bitfield RTC_RAR_LRR. */ -#define BF_RTC_RAR_LRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_LRR) & BM_RTC_RAR_LRR) - -/*! @brief Set the LRR field to a new value. */ -#define BW_RTC_RAR_LRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR) = (v)) -/*@}*/ - -/*! - * @name Register RTC_RAR, field IERR[7] (RW) - * - * After being cleared, this bit is set only by system reset. It is not affected - * by VBAT POR or software reset. - * - * Values: - * - 0 - Reads to the Interrupt Enable Register are ignored. - * - 1 - Reads to the Interrupt Enable Register complete as normal. - */ -/*@{*/ -#define BP_RTC_RAR_IERR (7U) /*!< Bit position for RTC_RAR_IERR. */ -#define BM_RTC_RAR_IERR (0x00000080U) /*!< Bit mask for RTC_RAR_IERR. */ -#define BS_RTC_RAR_IERR (1U) /*!< Bit field size in bits for RTC_RAR_IERR. */ - -/*! @brief Read current value of the RTC_RAR_IERR field. */ -#define BR_RTC_RAR_IERR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR)) - -/*! @brief Format value for bitfield RTC_RAR_IERR. */ -#define BF_RTC_RAR_IERR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_IERR) & BM_RTC_RAR_IERR) - -/*! @brief Set the IERR field to a new value. */ -#define BW_RTC_RAR_IERR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_rtc_t - module struct - ******************************************************************************/ -/*! - * @brief All RTC module registers. - */ -#pragma pack(1) -typedef struct _hw_rtc -{ - __IO hw_rtc_tsr_t TSR; /*!< [0x0] RTC Time Seconds Register */ - __IO hw_rtc_tpr_t TPR; /*!< [0x4] RTC Time Prescaler Register */ - __IO hw_rtc_tar_t TAR; /*!< [0x8] RTC Time Alarm Register */ - __IO hw_rtc_tcr_t TCR; /*!< [0xC] RTC Time Compensation Register */ - __IO hw_rtc_cr_t CR; /*!< [0x10] RTC Control Register */ - __IO hw_rtc_sr_t SR; /*!< [0x14] RTC Status Register */ - __IO hw_rtc_lr_t LR; /*!< [0x18] RTC Lock Register */ - __IO hw_rtc_ier_t IER; /*!< [0x1C] RTC Interrupt Enable Register */ - uint8_t _reserved0[2016]; - __IO hw_rtc_war_t WAR; /*!< [0x800] RTC Write Access Register */ - __IO hw_rtc_rar_t RAR; /*!< [0x804] RTC Read Access Register */ -} hw_rtc_t; -#pragma pack() - -/*! @brief Macro to access all RTC registers. */ -/*! @param x RTC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_RTC(RTC_BASE). */ -#define HW_RTC(x) (*(hw_rtc_t *)(x)) - -#endif /* __HW_RTC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sdhc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sdhc.h deleted file mode 100644 index 2aa434bf961..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sdhc.h +++ /dev/null @@ -1,5200 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SDHC_REGISTERS_H__ -#define __HW_SDHC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 SDHC - * - * Secured Digital Host Controller - * - * Registers defined in this header file: - * - HW_SDHC_DSADDR - DMA System Address register - * - HW_SDHC_BLKATTR - Block Attributes register - * - HW_SDHC_CMDARG - Command Argument register - * - HW_SDHC_XFERTYP - Transfer Type register - * - HW_SDHC_CMDRSP0 - Command Response 0 - * - HW_SDHC_CMDRSP1 - Command Response 1 - * - HW_SDHC_CMDRSP2 - Command Response 2 - * - HW_SDHC_CMDRSP3 - Command Response 3 - * - HW_SDHC_DATPORT - Buffer Data Port register - * - HW_SDHC_PRSSTAT - Present State register - * - HW_SDHC_PROCTL - Protocol Control register - * - HW_SDHC_SYSCTL - System Control register - * - HW_SDHC_IRQSTAT - Interrupt Status register - * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register - * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register - * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register - * - HW_SDHC_HTCAPBLT - Host Controller Capabilities - * - HW_SDHC_WML - Watermark Level Register - * - HW_SDHC_FEVT - Force Event register - * - HW_SDHC_ADMAES - ADMA Error Status register - * - HW_SDHC_ADSADDR - ADMA System Addressregister - * - HW_SDHC_VENDOR - Vendor Specific register - * - HW_SDHC_MMCBOOT - MMC Boot register - * - HW_SDHC_HOSTVER - Host Controller Version - * - * - hw_sdhc_t - Struct containing all module registers. - */ - -#define HW_SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */ - -/******************************************************************************* - * HW_SDHC_DSADDR - DMA System Address register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_DSADDR - DMA System Address register (RW) - * - * Reset value: 0x00000000U - * - * This register contains the physical system memory address used for DMA - * transfers. - */ -typedef union _hw_sdhc_dsaddr -{ - uint32_t U; - struct _hw_sdhc_dsaddr_bitfields - { - uint32_t RESERVED0 : 2; /*!< [1:0] */ - uint32_t DSADDR : 30; /*!< [31:2] DMA System Address */ - } B; -} hw_sdhc_dsaddr_t; - -/*! - * @name Constants and macros for entire SDHC_DSADDR register - */ -/*@{*/ -#define HW_SDHC_DSADDR_ADDR(x) ((x) + 0x0U) - -#define HW_SDHC_DSADDR(x) (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR(x)) -#define HW_SDHC_DSADDR_RD(x) (HW_SDHC_DSADDR(x).U) -#define HW_SDHC_DSADDR_WR(x, v) (HW_SDHC_DSADDR(x).U = (v)) -#define HW_SDHC_DSADDR_SET(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) | (v))) -#define HW_SDHC_DSADDR_CLR(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) & ~(v))) -#define HW_SDHC_DSADDR_TOG(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_DSADDR bitfields - */ - -/*! - * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW) - * - * Contains the 32-bit system memory address for a DMA transfer. Because the - * address must be word (4 bytes) align, the least 2 bits are reserved, always 0. - * When the SDHC stops a DMA transfer, this register points to the system address - * of the next contiguous data position. It can be accessed only when no - * transaction is executing, that is, after a transaction has stopped. Read operation - * during transfers may return an invalid value. The host driver shall initialize - * this register before starting a DMA transaction. After DMA has stopped, the - * system address of the next contiguous data position can be read from this register. - * This register is protected during a data transfer. When data lines are - * active, write to this register is ignored. The host driver shall wait, until - * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does - * not support a virtual memory system. It supports only continuous physical - * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB - * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this - * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it - * automatically alters the value of internal address counter, so SW cannot - * change this register when IRQSTAT[TC] is set. - */ -/*@{*/ -#define BP_SDHC_DSADDR_DSADDR (2U) /*!< Bit position for SDHC_DSADDR_DSADDR. */ -#define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) /*!< Bit mask for SDHC_DSADDR_DSADDR. */ -#define BS_SDHC_DSADDR_DSADDR (30U) /*!< Bit field size in bits for SDHC_DSADDR_DSADDR. */ - -/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */ -#define BR_SDHC_DSADDR_DSADDR(x) (HW_SDHC_DSADDR(x).B.DSADDR) - -/*! @brief Format value for bitfield SDHC_DSADDR_DSADDR. */ -#define BF_SDHC_DSADDR_DSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DSADDR_DSADDR) & BM_SDHC_DSADDR_DSADDR) - -/*! @brief Set the DSADDR field to a new value. */ -#define BW_SDHC_DSADDR_DSADDR(x, v) (HW_SDHC_DSADDR_WR(x, (HW_SDHC_DSADDR_RD(x) & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v))) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_BLKATTR - Block Attributes register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_BLKATTR - Block Attributes register (RW) - * - * Reset value: 0x00000000U - * - * This register is used to configure the number of data blocks and the number - * of bytes in each block. - */ -typedef union _hw_sdhc_blkattr -{ - uint32_t U; - struct _hw_sdhc_blkattr_bitfields - { - uint32_t BLKSIZE : 13; /*!< [12:0] Transfer Block Size */ - uint32_t RESERVED0 : 3; /*!< [15:13] */ - uint32_t BLKCNT : 16; /*!< [31:16] Blocks Count For Current Transfer - * */ - } B; -} hw_sdhc_blkattr_t; - -/*! - * @name Constants and macros for entire SDHC_BLKATTR register - */ -/*@{*/ -#define HW_SDHC_BLKATTR_ADDR(x) ((x) + 0x4U) - -#define HW_SDHC_BLKATTR(x) (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR(x)) -#define HW_SDHC_BLKATTR_RD(x) (HW_SDHC_BLKATTR(x).U) -#define HW_SDHC_BLKATTR_WR(x, v) (HW_SDHC_BLKATTR(x).U = (v)) -#define HW_SDHC_BLKATTR_SET(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) | (v))) -#define HW_SDHC_BLKATTR_CLR(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) & ~(v))) -#define HW_SDHC_BLKATTR_TOG(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_BLKATTR bitfields - */ - -/*! - * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW) - * - * Specifies the block size for block data transfers. Values ranging from 1 byte - * up to the maximum buffer size can be set. It can be accessed only when no - * transaction is executing, that is, after a transaction has stopped. Read - * operations during transfers may return an invalid value, and write operations will be - * ignored. - * - * Values: - * - 0 - No data transfer. - * - 1 - 1 Byte - * - 10 - 2 Bytes - * - 11 - 3 Bytes - * - 100 - 4 Bytes - * - 111111111 - 511 Bytes - * - 1000000000 - 512 Bytes - * - 100000000000 - 2048 Bytes - * - 1000000000000 - 4096 Bytes - */ -/*@{*/ -#define BP_SDHC_BLKATTR_BLKSIZE (0U) /*!< Bit position for SDHC_BLKATTR_BLKSIZE. */ -#define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) /*!< Bit mask for SDHC_BLKATTR_BLKSIZE. */ -#define BS_SDHC_BLKATTR_BLKSIZE (13U) /*!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE. */ - -/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */ -#define BR_SDHC_BLKATTR_BLKSIZE(x) (HW_SDHC_BLKATTR(x).B.BLKSIZE) - -/*! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE. */ -#define BF_SDHC_BLKATTR_BLKSIZE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKSIZE) & BM_SDHC_BLKATTR_BLKSIZE) - -/*! @brief Set the BLKSIZE field to a new value. */ -#define BW_SDHC_BLKATTR_BLKSIZE(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v))) -/*@}*/ - -/*! - * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW) - * - * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for - * multiple block transfers. For single block transfer, this register will - * always read as 1. The host driver shall set this register to a value between 1 and - * the maximum block count. The SDHC decrements the block count after each block - * transfer and stops when the count reaches zero. Setting the block count to 0 - * results in no data blocks being transferred. This register must be accessed - * only when no transaction is executing, that is, after transactions are stopped. - * During data transfer, read operations on this register may return an invalid - * value and write operations are ignored. When saving transfer content as a result - * of a suspend command, the number of blocks yet to be transferred can be - * determined by reading this register. The reading of this register must be applied - * after transfer is paused by stop at block gap operation and before sending the - * command marked as suspend. This is because when suspend command is sent out, - * SDHC will regard the current transfer as aborted and change BLKCNT back to its - * original value instead of keeping the dynamical indicator of remained block - * count. When restoring transfer content prior to issuing a resume command, the - * host driver shall restore the previously saved block count. Although the BLKCNT - * field is 0 after reset, the read of reset value is 0x1. This is because when - * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of - * BLKCNT is always 1. - * - * Values: - * - 0 - Stop count. - * - 1 - 1 block - * - 10 - 2 blocks - * - 1111111111111111 - 65535 blocks - */ -/*@{*/ -#define BP_SDHC_BLKATTR_BLKCNT (16U) /*!< Bit position for SDHC_BLKATTR_BLKCNT. */ -#define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) /*!< Bit mask for SDHC_BLKATTR_BLKCNT. */ -#define BS_SDHC_BLKATTR_BLKCNT (16U) /*!< Bit field size in bits for SDHC_BLKATTR_BLKCNT. */ - -/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */ -#define BR_SDHC_BLKATTR_BLKCNT(x) (HW_SDHC_BLKATTR(x).B.BLKCNT) - -/*! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT. */ -#define BF_SDHC_BLKATTR_BLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKCNT) & BM_SDHC_BLKATTR_BLKCNT) - -/*! @brief Set the BLKCNT field to a new value. */ -#define BW_SDHC_BLKATTR_BLKCNT(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_CMDARG - Command Argument register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_CMDARG - Command Argument register (RW) - * - * Reset value: 0x00000000U - * - * This register contains the SD/MMC command argument. - */ -typedef union _hw_sdhc_cmdarg -{ - uint32_t U; - struct _hw_sdhc_cmdarg_bitfields - { - uint32_t CMDARG : 32; /*!< [31:0] Command Argument */ - } B; -} hw_sdhc_cmdarg_t; - -/*! - * @name Constants and macros for entire SDHC_CMDARG register - */ -/*@{*/ -#define HW_SDHC_CMDARG_ADDR(x) ((x) + 0x8U) - -#define HW_SDHC_CMDARG(x) (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR(x)) -#define HW_SDHC_CMDARG_RD(x) (HW_SDHC_CMDARG(x).U) -#define HW_SDHC_CMDARG_WR(x, v) (HW_SDHC_CMDARG(x).U = (v)) -#define HW_SDHC_CMDARG_SET(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) | (v))) -#define HW_SDHC_CMDARG_CLR(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) & ~(v))) -#define HW_SDHC_CMDARG_TOG(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_CMDARG bitfields - */ - -/*! - * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW) - * - * The SD/MMC command argument is specified as bits 39-8 of the command format - * in the SD or MMC specification. This register is write protected when - * PRSSTAT[CDIHB0] is set. - */ -/*@{*/ -#define BP_SDHC_CMDARG_CMDARG (0U) /*!< Bit position for SDHC_CMDARG_CMDARG. */ -#define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDARG_CMDARG. */ -#define BS_SDHC_CMDARG_CMDARG (32U) /*!< Bit field size in bits for SDHC_CMDARG_CMDARG. */ - -/*! @brief Read current value of the SDHC_CMDARG_CMDARG field. */ -#define BR_SDHC_CMDARG_CMDARG(x) (HW_SDHC_CMDARG(x).U) - -/*! @brief Format value for bitfield SDHC_CMDARG_CMDARG. */ -#define BF_SDHC_CMDARG_CMDARG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_CMDARG_CMDARG) & BM_SDHC_CMDARG_CMDARG) - -/*! @brief Set the CMDARG field to a new value. */ -#define BW_SDHC_CMDARG_CMDARG(x, v) (HW_SDHC_CMDARG_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_XFERTYP - Transfer Type register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_XFERTYP - Transfer Type register (RW) - * - * Reset value: 0x00000000U - * - * This register is used to control the operation of data transfers. The host - * driver shall set this register before issuing a command followed by a data - * transfer, or before issuing a resume command. To prevent data loss, the SDHC - * prevents writing to the bits that are involved in the data transfer of this - * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN, - * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB] - * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to - * send a command with data by writing to this register is ignored; when - * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with - * data transfer involved, it is mandatory that the block size is nonzero. - * Besides, block count must also be nonzero, or indicated as single block transfer - * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of - * this register is 0 when written), otherwise SDHC will ignore the sending of - * this command and do nothing. For write command, with all above restrictions, it - * is also mandatory that the write protect switch is not active (WPSPL bit of - * Present State Register is 1), otherwise SDHC will also ignore the command. If - * the commands with data transfer does not receive the response in 64 clock - * cycles, that is, response time-out, SDHC will regard the external device does not - * accept the command and abort the data transfer. In this scenario, the driver - * must issue the command again to retry the transfer. It is also possible that, - * for some reason, the card responds to the command but SDHC does not receive the - * response, and if it is internal DMA (either simple DMA or ADMA) read - * operation, the external system memory is over-written by the internal DMA with data - * sent back from the card. The following table shows the summary of how register - * settings determine the type of data transfer. Transfer Type register setting for - * various transfer types Multi/Single block select Block count enable Block - * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite - * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The - * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN], - * in regards to XFERTYP[RSPTYP] as well as the name of the response type. - * Relationship between parameters and the name of the response type Response type - * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response - * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In - * the SDIO specification, response type notation for R5b is not defined. R5 - * includes R5b in the SDIO specification. But R5b is defined in this specification - * to specify that the SDHC will check the busy status after receiving a - * response. For example, usually CMD52 is used with R5, but the I/O abort command shall - * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits. - * The CRC check shall be disabled for these response types. - */ -typedef union _hw_sdhc_xfertyp -{ - uint32_t U; - struct _hw_sdhc_xfertyp_bitfields - { - uint32_t DMAEN : 1; /*!< [0] DMA Enable */ - uint32_t BCEN : 1; /*!< [1] Block Count Enable */ - uint32_t AC12EN : 1; /*!< [2] Auto CMD12 Enable */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t DTDSEL : 1; /*!< [4] Data Transfer Direction Select */ - uint32_t MSBSEL : 1; /*!< [5] Multi/Single Block Select */ - uint32_t RESERVED1 : 10; /*!< [15:6] */ - uint32_t RSPTYP : 2; /*!< [17:16] Response Type Select */ - uint32_t RESERVED2 : 1; /*!< [18] */ - uint32_t CCCEN : 1; /*!< [19] Command CRC Check Enable */ - uint32_t CICEN : 1; /*!< [20] Command Index Check Enable */ - uint32_t DPSEL : 1; /*!< [21] Data Present Select */ - uint32_t CMDTYP : 2; /*!< [23:22] Command Type */ - uint32_t CMDINX : 6; /*!< [29:24] Command Index */ - uint32_t RESERVED3 : 2; /*!< [31:30] */ - } B; -} hw_sdhc_xfertyp_t; - -/*! - * @name Constants and macros for entire SDHC_XFERTYP register - */ -/*@{*/ -#define HW_SDHC_XFERTYP_ADDR(x) ((x) + 0xCU) - -#define HW_SDHC_XFERTYP(x) (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR(x)) -#define HW_SDHC_XFERTYP_RD(x) (HW_SDHC_XFERTYP(x).U) -#define HW_SDHC_XFERTYP_WR(x, v) (HW_SDHC_XFERTYP(x).U = (v)) -#define HW_SDHC_XFERTYP_SET(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) | (v))) -#define HW_SDHC_XFERTYP_CLR(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) & ~(v))) -#define HW_SDHC_XFERTYP_TOG(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_XFERTYP bitfields - */ - -/*! - * @name Register SDHC_XFERTYP, field DMAEN[0] (RW) - * - * Enables DMA functionality. If this bit is set to 1, a DMA operation shall - * begin when the host driver sets the DPSEL bit of this register. Whether the - * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS]. - * - * Values: - * - 0 - Disable - * - 1 - Enable - */ -/*@{*/ -#define BP_SDHC_XFERTYP_DMAEN (0U) /*!< Bit position for SDHC_XFERTYP_DMAEN. */ -#define BM_SDHC_XFERTYP_DMAEN (0x00000001U) /*!< Bit mask for SDHC_XFERTYP_DMAEN. */ -#define BS_SDHC_XFERTYP_DMAEN (1U) /*!< Bit field size in bits for SDHC_XFERTYP_DMAEN. */ - -/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */ -#define BR_SDHC_XFERTYP_DMAEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_DMAEN. */ -#define BF_SDHC_XFERTYP_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DMAEN) & BM_SDHC_XFERTYP_DMAEN) - -/*! @brief Set the DMAEN field to a new value. */ -#define BW_SDHC_XFERTYP_DMAEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field BCEN[1] (RW) - * - * Used to enable the Block Count register, which is only relevant for multiple - * block transfers. When this bit is 0, the internal counter for block is - * disabled, which is useful in executing an infinite transfer. - * - * Values: - * - 0 - Disable - * - 1 - Enable - */ -/*@{*/ -#define BP_SDHC_XFERTYP_BCEN (1U) /*!< Bit position for SDHC_XFERTYP_BCEN. */ -#define BM_SDHC_XFERTYP_BCEN (0x00000002U) /*!< Bit mask for SDHC_XFERTYP_BCEN. */ -#define BS_SDHC_XFERTYP_BCEN (1U) /*!< Bit field size in bits for SDHC_XFERTYP_BCEN. */ - -/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */ -#define BR_SDHC_XFERTYP_BCEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_BCEN. */ -#define BF_SDHC_XFERTYP_BCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_BCEN) & BM_SDHC_XFERTYP_BCEN) - -/*! @brief Set the BCEN field to a new value. */ -#define BW_SDHC_XFERTYP_BCEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field AC12EN[2] (RW) - * - * Multiple block transfers for memory require a CMD12 to stop the transaction. - * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the - * last block transfer has completed. The host driver shall not set this bit to - * issue commands that do not require CMD12 to stop a multiple block data - * transfer. In particular, secure commands defined in File Security Specification (see - * reference list) do not require CMD12. In single block transfer, the SDHC will - * ignore this bit whether it is set or not. - * - * Values: - * - 0 - Disable - * - 1 - Enable - */ -/*@{*/ -#define BP_SDHC_XFERTYP_AC12EN (2U) /*!< Bit position for SDHC_XFERTYP_AC12EN. */ -#define BM_SDHC_XFERTYP_AC12EN (0x00000004U) /*!< Bit mask for SDHC_XFERTYP_AC12EN. */ -#define BS_SDHC_XFERTYP_AC12EN (1U) /*!< Bit field size in bits for SDHC_XFERTYP_AC12EN. */ - -/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */ -#define BR_SDHC_XFERTYP_AC12EN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_AC12EN. */ -#define BF_SDHC_XFERTYP_AC12EN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_AC12EN) & BM_SDHC_XFERTYP_AC12EN) - -/*! @brief Set the AC12EN field to a new value. */ -#define BW_SDHC_XFERTYP_AC12EN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW) - * - * Defines the direction of DAT line data transfers. The bit is set to 1 by the - * host driver to transfer data from the SD card to the SDHC and is set to 0 for - * all other commands. - * - * Values: - * - 0 - Write host to card. - * - 1 - Read card to host. - */ -/*@{*/ -#define BP_SDHC_XFERTYP_DTDSEL (4U) /*!< Bit position for SDHC_XFERTYP_DTDSEL. */ -#define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) /*!< Bit mask for SDHC_XFERTYP_DTDSEL. */ -#define BS_SDHC_XFERTYP_DTDSEL (1U) /*!< Bit field size in bits for SDHC_XFERTYP_DTDSEL. */ - -/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */ -#define BR_SDHC_XFERTYP_DTDSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL. */ -#define BF_SDHC_XFERTYP_DTDSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DTDSEL) & BM_SDHC_XFERTYP_DTDSEL) - -/*! @brief Set the DTDSEL field to a new value. */ -#define BW_SDHC_XFERTYP_DTDSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW) - * - * Enables multiple block DAT line data transfers. For any other commands, this - * bit shall be set to 0. If this bit is 0, it is not necessary to set the block - * count register. - * - * Values: - * - 0 - Single block. - * - 1 - Multiple blocks. - */ -/*@{*/ -#define BP_SDHC_XFERTYP_MSBSEL (5U) /*!< Bit position for SDHC_XFERTYP_MSBSEL. */ -#define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) /*!< Bit mask for SDHC_XFERTYP_MSBSEL. */ -#define BS_SDHC_XFERTYP_MSBSEL (1U) /*!< Bit field size in bits for SDHC_XFERTYP_MSBSEL. */ - -/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */ -#define BR_SDHC_XFERTYP_MSBSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL. */ -#define BF_SDHC_XFERTYP_MSBSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_MSBSEL) & BM_SDHC_XFERTYP_MSBSEL) - -/*! @brief Set the MSBSEL field to a new value. */ -#define BW_SDHC_XFERTYP_MSBSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW) - * - * Values: - * - 00 - No response. - * - 01 - Response length 136. - * - 10 - Response length 48. - * - 11 - Response length 48, check busy after response. - */ -/*@{*/ -#define BP_SDHC_XFERTYP_RSPTYP (16U) /*!< Bit position for SDHC_XFERTYP_RSPTYP. */ -#define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) /*!< Bit mask for SDHC_XFERTYP_RSPTYP. */ -#define BS_SDHC_XFERTYP_RSPTYP (2U) /*!< Bit field size in bits for SDHC_XFERTYP_RSPTYP. */ - -/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */ -#define BR_SDHC_XFERTYP_RSPTYP(x) (HW_SDHC_XFERTYP(x).B.RSPTYP) - -/*! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP. */ -#define BF_SDHC_XFERTYP_RSPTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP) - -/*! @brief Set the RSPTYP field to a new value. */ -#define BW_SDHC_XFERTYP_RSPTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v))) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field CCCEN[19] (RW) - * - * If this bit is set to 1, the SDHC shall check the CRC field in the response. - * If an error is detected, it is reported as a Command CRC Error. If this bit is - * set to 0, the CRC field is not checked. The number of bits checked by the CRC - * field value changes according to the length of the response. - * - * Values: - * - 0 - Disable - * - 1 - Enable - */ -/*@{*/ -#define BP_SDHC_XFERTYP_CCCEN (19U) /*!< Bit position for SDHC_XFERTYP_CCCEN. */ -#define BM_SDHC_XFERTYP_CCCEN (0x00080000U) /*!< Bit mask for SDHC_XFERTYP_CCCEN. */ -#define BS_SDHC_XFERTYP_CCCEN (1U) /*!< Bit field size in bits for SDHC_XFERTYP_CCCEN. */ - -/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */ -#define BR_SDHC_XFERTYP_CCCEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_CCCEN. */ -#define BF_SDHC_XFERTYP_CCCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CCCEN) & BM_SDHC_XFERTYP_CCCEN) - -/*! @brief Set the CCCEN field to a new value. */ -#define BW_SDHC_XFERTYP_CCCEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field CICEN[20] (RW) - * - * If this bit is set to 1, the SDHC will check the index field in the response - * to see if it has the same value as the command index. If it is not, it is - * reported as a command index error. If this bit is set to 0, the index field is not - * checked. - * - * Values: - * - 0 - Disable - * - 1 - Enable - */ -/*@{*/ -#define BP_SDHC_XFERTYP_CICEN (20U) /*!< Bit position for SDHC_XFERTYP_CICEN. */ -#define BM_SDHC_XFERTYP_CICEN (0x00100000U) /*!< Bit mask for SDHC_XFERTYP_CICEN. */ -#define BS_SDHC_XFERTYP_CICEN (1U) /*!< Bit field size in bits for SDHC_XFERTYP_CICEN. */ - -/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */ -#define BR_SDHC_XFERTYP_CICEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_CICEN. */ -#define BF_SDHC_XFERTYP_CICEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CICEN) & BM_SDHC_XFERTYP_CICEN) - -/*! @brief Set the CICEN field to a new value. */ -#define BW_SDHC_XFERTYP_CICEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field DPSEL[21] (RW) - * - * This bit is set to 1 to indicate that data is present and shall be - * transferred using the DAT line. It is set to 0 for the following: Commands using only - * the CMD line, for example: CMD52. Commands with no data transfer, but using the - * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command, - * this bit shall be set, and other bits in this register shall be set the same - * as when the transfer was initially launched. When the Write Protect switch is - * on, that is, the WPSPL bit is active as 0, any command with a write operation - * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is - * 0, writes to the register Transfer Type are ignored. - * - * Values: - * - 0 - No data present. - * - 1 - Data present. - */ -/*@{*/ -#define BP_SDHC_XFERTYP_DPSEL (21U) /*!< Bit position for SDHC_XFERTYP_DPSEL. */ -#define BM_SDHC_XFERTYP_DPSEL (0x00200000U) /*!< Bit mask for SDHC_XFERTYP_DPSEL. */ -#define BS_SDHC_XFERTYP_DPSEL (1U) /*!< Bit field size in bits for SDHC_XFERTYP_DPSEL. */ - -/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */ -#define BR_SDHC_XFERTYP_DPSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL)) - -/*! @brief Format value for bitfield SDHC_XFERTYP_DPSEL. */ -#define BF_SDHC_XFERTYP_DPSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DPSEL) & BM_SDHC_XFERTYP_DPSEL) - -/*! @brief Set the DPSEL field to a new value. */ -#define BW_SDHC_XFERTYP_DPSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW) - * - * There are three types of special commands: suspend, resume, and abort. These - * bits shall be set to 00b for all other commands. Suspend command: If the - * suspend command succeeds, the SDHC shall assume that the card bus has been released - * and that it is possible to issue the next command which uses the DAT line. - * Because the SDHC does not monitor the content of command response, it does not - * know if the suspend command succeeded or not. It is the host driver's - * responsibility to check the status of the suspend command and send another command - * marked as suspend to inform the SDHC that a suspend command was successfully - * issued. After the end bit of command is sent, the SDHC deasserts read wait for read - * transactions and stops checking busy for write transactions. In 4-bit mode, - * the interrupt cycle starts. If the suspend command fails, the SDHC will - * maintain its current state, and the host driver shall restart the transfer by setting - * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by - * restoring the registers saved before sending the suspend command and then sends - * the resume command. The SDHC will check for a pending busy state before - * starting write transfers. Abort command: If this command is set when executing a - * read transfer, the SDHC will stop reads to the buffer. If this command is set - * when executing a write transfer, the SDHC will stop driving the DAT line. After - * issuing the abort command, the host driver must issue a software reset (abort - * transaction). - * - * Values: - * - 00 - Normal other commands. - * - 01 - Suspend CMD52 for writing bus suspend in CCCR. - * - 10 - Resume CMD52 for writing function select in CCCR. - * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR. - */ -/*@{*/ -#define BP_SDHC_XFERTYP_CMDTYP (22U) /*!< Bit position for SDHC_XFERTYP_CMDTYP. */ -#define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) /*!< Bit mask for SDHC_XFERTYP_CMDTYP. */ -#define BS_SDHC_XFERTYP_CMDTYP (2U) /*!< Bit field size in bits for SDHC_XFERTYP_CMDTYP. */ - -/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */ -#define BR_SDHC_XFERTYP_CMDTYP(x) (HW_SDHC_XFERTYP(x).B.CMDTYP) - -/*! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP. */ -#define BF_SDHC_XFERTYP_CMDTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDTYP) & BM_SDHC_XFERTYP_CMDTYP) - -/*! @brief Set the CMDTYP field to a new value. */ -#define BW_SDHC_XFERTYP_CMDTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v))) -/*@}*/ - -/*! - * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW) - * - * These bits shall be set to the command number that is specified in bits 45-40 - * of the command-format in the SD Memory Card Physical Layer Specification and - * SDIO Card Specification. - */ -/*@{*/ -#define BP_SDHC_XFERTYP_CMDINX (24U) /*!< Bit position for SDHC_XFERTYP_CMDINX. */ -#define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) /*!< Bit mask for SDHC_XFERTYP_CMDINX. */ -#define BS_SDHC_XFERTYP_CMDINX (6U) /*!< Bit field size in bits for SDHC_XFERTYP_CMDINX. */ - -/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */ -#define BR_SDHC_XFERTYP_CMDINX(x) (HW_SDHC_XFERTYP(x).B.CMDINX) - -/*! @brief Format value for bitfield SDHC_XFERTYP_CMDINX. */ -#define BF_SDHC_XFERTYP_CMDINX(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX) - -/*! @brief Set the CMDINX field to a new value. */ -#define BW_SDHC_XFERTYP_CMDINX(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v))) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_CMDRSP0 - Command Response 0 - ******************************************************************************/ - -/*! - * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO) - * - * Reset value: 0x00000000U - * - * This register is used to store part 0 of the response bits from the card. - */ -typedef union _hw_sdhc_cmdrsp0 -{ - uint32_t U; - struct _hw_sdhc_cmdrsp0_bitfields - { - uint32_t CMDRSP0 : 32; /*!< [31:0] Command Response 0 */ - } B; -} hw_sdhc_cmdrsp0_t; - -/*! - * @name Constants and macros for entire SDHC_CMDRSP0 register - */ -/*@{*/ -#define HW_SDHC_CMDRSP0_ADDR(x) ((x) + 0x10U) - -#define HW_SDHC_CMDRSP0(x) (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR(x)) -#define HW_SDHC_CMDRSP0_RD(x) (HW_SDHC_CMDRSP0(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_CMDRSP0 bitfields - */ - -/*! - * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO) - */ -/*@{*/ -#define BP_SDHC_CMDRSP0_CMDRSP0 (0U) /*!< Bit position for SDHC_CMDRSP0_CMDRSP0. */ -#define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP0_CMDRSP0. */ -#define BS_SDHC_CMDRSP0_CMDRSP0 (32U) /*!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0. */ - -/*! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field. */ -#define BR_SDHC_CMDRSP0_CMDRSP0(x) (HW_SDHC_CMDRSP0(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_CMDRSP1 - Command Response 1 - ******************************************************************************/ - -/*! - * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO) - * - * Reset value: 0x00000000U - * - * This register is used to store part 1 of the response bits from the card. - */ -typedef union _hw_sdhc_cmdrsp1 -{ - uint32_t U; - struct _hw_sdhc_cmdrsp1_bitfields - { - uint32_t CMDRSP1 : 32; /*!< [31:0] Command Response 1 */ - } B; -} hw_sdhc_cmdrsp1_t; - -/*! - * @name Constants and macros for entire SDHC_CMDRSP1 register - */ -/*@{*/ -#define HW_SDHC_CMDRSP1_ADDR(x) ((x) + 0x14U) - -#define HW_SDHC_CMDRSP1(x) (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR(x)) -#define HW_SDHC_CMDRSP1_RD(x) (HW_SDHC_CMDRSP1(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_CMDRSP1 bitfields - */ - -/*! - * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO) - */ -/*@{*/ -#define BP_SDHC_CMDRSP1_CMDRSP1 (0U) /*!< Bit position for SDHC_CMDRSP1_CMDRSP1. */ -#define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP1_CMDRSP1. */ -#define BS_SDHC_CMDRSP1_CMDRSP1 (32U) /*!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1. */ - -/*! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field. */ -#define BR_SDHC_CMDRSP1_CMDRSP1(x) (HW_SDHC_CMDRSP1(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_CMDRSP2 - Command Response 2 - ******************************************************************************/ - -/*! - * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO) - * - * Reset value: 0x00000000U - * - * This register is used to store part 2 of the response bits from the card. - */ -typedef union _hw_sdhc_cmdrsp2 -{ - uint32_t U; - struct _hw_sdhc_cmdrsp2_bitfields - { - uint32_t CMDRSP2 : 32; /*!< [31:0] Command Response 2 */ - } B; -} hw_sdhc_cmdrsp2_t; - -/*! - * @name Constants and macros for entire SDHC_CMDRSP2 register - */ -/*@{*/ -#define HW_SDHC_CMDRSP2_ADDR(x) ((x) + 0x18U) - -#define HW_SDHC_CMDRSP2(x) (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR(x)) -#define HW_SDHC_CMDRSP2_RD(x) (HW_SDHC_CMDRSP2(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_CMDRSP2 bitfields - */ - -/*! - * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO) - */ -/*@{*/ -#define BP_SDHC_CMDRSP2_CMDRSP2 (0U) /*!< Bit position for SDHC_CMDRSP2_CMDRSP2. */ -#define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP2_CMDRSP2. */ -#define BS_SDHC_CMDRSP2_CMDRSP2 (32U) /*!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2. */ - -/*! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field. */ -#define BR_SDHC_CMDRSP2_CMDRSP2(x) (HW_SDHC_CMDRSP2(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_CMDRSP3 - Command Response 3 - ******************************************************************************/ - -/*! - * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO) - * - * Reset value: 0x00000000U - * - * This register is used to store part 3 of the response bits from the card. The - * following table describes the mapping of command responses from the SD bus to - * command response registers for each response type. In the table, R[ ] refers - * to a bit range within the response data as transmitted on the SD bus. Response - * bit definition for each response type Response type Meaning of response - * Response field Response register R1,R1b (normal response) Card status R[39:8] - * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2 - * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2, - * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4 - * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response - * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card - * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48 - * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0 - * register. Responses of type R1b (auto CMD12 responses) have response data bits - * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have - * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3 - * registers. To be able to read the response status efficiently, the SDHC stores - * only a part of the response data in the command response registers. This - * enables the host driver to efficiently read 32-bit of response data in one read - * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC, - * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN], - * and generate an error interrupt if any error is detected. The bit range for the - * CRC check depends on the response length. If the response length is 48, the - * SDHC will check R[47:1], and if the response length is 136 the SDHC will check - * R[119:1]. Because the SDHC may have a multiple block data transfer executing - * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response - * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This - * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT - * and vice versa. When the SDHC modifies part of the command response - * registers, as shown in the table above, it preserves the unmodified bits. - */ -typedef union _hw_sdhc_cmdrsp3 -{ - uint32_t U; - struct _hw_sdhc_cmdrsp3_bitfields - { - uint32_t CMDRSP3 : 32; /*!< [31:0] Command Response 3 */ - } B; -} hw_sdhc_cmdrsp3_t; - -/*! - * @name Constants and macros for entire SDHC_CMDRSP3 register - */ -/*@{*/ -#define HW_SDHC_CMDRSP3_ADDR(x) ((x) + 0x1CU) - -#define HW_SDHC_CMDRSP3(x) (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR(x)) -#define HW_SDHC_CMDRSP3_RD(x) (HW_SDHC_CMDRSP3(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_CMDRSP3 bitfields - */ - -/*! - * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO) - */ -/*@{*/ -#define BP_SDHC_CMDRSP3_CMDRSP3 (0U) /*!< Bit position for SDHC_CMDRSP3_CMDRSP3. */ -#define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP3_CMDRSP3. */ -#define BS_SDHC_CMDRSP3_CMDRSP3 (32U) /*!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3. */ - -/*! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field. */ -#define BR_SDHC_CMDRSP3_CMDRSP3(x) (HW_SDHC_CMDRSP3(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_DATPORT - Buffer Data Port register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW) - * - * Reset value: 0x00000000U - * - * This is a 32-bit data port register used to access the internal buffer and it - * cannot be updated in Idle mode. - */ -typedef union _hw_sdhc_datport -{ - uint32_t U; - struct _hw_sdhc_datport_bitfields - { - uint32_t DATCONT : 32; /*!< [31:0] Data Content */ - } B; -} hw_sdhc_datport_t; - -/*! - * @name Constants and macros for entire SDHC_DATPORT register - */ -/*@{*/ -#define HW_SDHC_DATPORT_ADDR(x) ((x) + 0x20U) - -#define HW_SDHC_DATPORT(x) (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR(x)) -#define HW_SDHC_DATPORT_RD(x) (HW_SDHC_DATPORT(x).U) -#define HW_SDHC_DATPORT_WR(x, v) (HW_SDHC_DATPORT(x).U = (v)) -#define HW_SDHC_DATPORT_SET(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) | (v))) -#define HW_SDHC_DATPORT_CLR(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) & ~(v))) -#define HW_SDHC_DATPORT_TOG(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_DATPORT bitfields - */ - -/*! - * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW) - * - * The Buffer Data Port register is for 32-bit data access by the CPU or the - * external DMA. When the internal DMA is enabled, any write to this register is - * ignored, and any read from this register will always yield 0s. - */ -/*@{*/ -#define BP_SDHC_DATPORT_DATCONT (0U) /*!< Bit position for SDHC_DATPORT_DATCONT. */ -#define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) /*!< Bit mask for SDHC_DATPORT_DATCONT. */ -#define BS_SDHC_DATPORT_DATCONT (32U) /*!< Bit field size in bits for SDHC_DATPORT_DATCONT. */ - -/*! @brief Read current value of the SDHC_DATPORT_DATCONT field. */ -#define BR_SDHC_DATPORT_DATCONT(x) (HW_SDHC_DATPORT(x).U) - -/*! @brief Format value for bitfield SDHC_DATPORT_DATCONT. */ -#define BF_SDHC_DATPORT_DATCONT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DATPORT_DATCONT) & BM_SDHC_DATPORT_DATCONT) - -/*! @brief Set the DATCONT field to a new value. */ -#define BW_SDHC_DATPORT_DATCONT(x, v) (HW_SDHC_DATPORT_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_PRSSTAT - Present State register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_PRSSTAT - Present State register (RO) - * - * Reset value: 0x00000000U - * - * The host driver can get status of the SDHC from this 32-bit read-only - * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for - * SDIO) when the DAT lines are busy during a data transfer. These commands can be - * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be - * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD - * Physical Specification may add other commands to this list in the future. - */ -typedef union _hw_sdhc_prsstat -{ - uint32_t U; - struct _hw_sdhc_prsstat_bitfields - { - uint32_t CIHB : 1; /*!< [0] Command Inhibit (CMD) */ - uint32_t CDIHB : 1; /*!< [1] Command Inhibit (DAT) */ - uint32_t DLA : 1; /*!< [2] Data Line Active */ - uint32_t SDSTB : 1; /*!< [3] SD Clock Stable */ - uint32_t IPGOFF : 1; /*!< [4] Bus Clock Gated Off Internally */ - uint32_t HCKOFF : 1; /*!< [5] System Clock Gated Off Internally */ - uint32_t PEROFF : 1; /*!< [6] SDHC clock Gated Off Internally */ - uint32_t SDOFF : 1; /*!< [7] SD Clock Gated Off Internally */ - uint32_t WTA : 1; /*!< [8] Write Transfer Active */ - uint32_t RTA : 1; /*!< [9] Read Transfer Active */ - uint32_t BWEN : 1; /*!< [10] Buffer Write Enable */ - uint32_t BREN : 1; /*!< [11] Buffer Read Enable */ - uint32_t RESERVED0 : 4; /*!< [15:12] */ - uint32_t CINS : 1; /*!< [16] Card Inserted */ - uint32_t RESERVED1 : 6; /*!< [22:17] */ - uint32_t CLSL : 1; /*!< [23] CMD Line Signal Level */ - uint32_t DLSL : 8; /*!< [31:24] DAT Line Signal Level */ - } B; -} hw_sdhc_prsstat_t; - -/*! - * @name Constants and macros for entire SDHC_PRSSTAT register - */ -/*@{*/ -#define HW_SDHC_PRSSTAT_ADDR(x) ((x) + 0x24U) - -#define HW_SDHC_PRSSTAT(x) (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR(x)) -#define HW_SDHC_PRSSTAT_RD(x) (HW_SDHC_PRSSTAT(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_PRSSTAT bitfields - */ - -/*! - * @name Register SDHC_PRSSTAT, field CIHB[0] (RO) - * - * If this status bit is 0, it indicates that the CMD line is not in use and the - * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also - * immediately after the Transfer Type register is written. This bit is cleared when - * the command response is received. Even if the CDIHB bit is set to 1, Commands - * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 - * generates a command complete interrupt in the interrupt status register. If the - * SDHC cannot issue the command because of a command conflict error (see - * command CRC error) or because of a command not issued by auto CMD12 error, this bit - * will remain 1 and the command complete is not set. The status of issuing an - * auto CMD12 does not show on this bit. - * - * Values: - * - 0 - Can issue command using only CMD line. - * - 1 - Cannot issue command. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_CIHB (0U) /*!< Bit position for SDHC_PRSSTAT_CIHB. */ -#define BM_SDHC_PRSSTAT_CIHB (0x00000001U) /*!< Bit mask for SDHC_PRSSTAT_CIHB. */ -#define BS_SDHC_PRSSTAT_CIHB (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_CIHB. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */ -#define BR_SDHC_PRSSTAT_CIHB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CIHB)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO) - * - * This status bit is generated if either the DLA or the RTA is set to 1. If - * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command. - * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in - * the case when the command busy is finished, changing from 1 to 0 generates a - * transfer complete interrupt in the Interrupt Status register. The SD host - * driver can save registers for a suspend transaction after this bit has changed - * from 1 to 0. - * - * Values: - * - 0 - Can issue command which uses the DAT line. - * - 1 - Cannot issue command which uses the DAT line. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_CDIHB (1U) /*!< Bit position for SDHC_PRSSTAT_CDIHB. */ -#define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) /*!< Bit mask for SDHC_PRSSTAT_CDIHB. */ -#define BS_SDHC_PRSSTAT_CDIHB (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_CDIHB. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */ -#define BR_SDHC_PRSSTAT_CDIHB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CDIHB)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field DLA[2] (RO) - * - * Indicates whether one of the DAT lines on the SD bus is in use. In the case - * of read transactions: This status indicates whether a read transfer is - * executing on the SD bus. Changes in this value from 1 to 0, between data blocks, - * generates a block gap event interrupt in the Interrupt Status register. This bit - * will be set in either of the following cases: After the end bit of the read - * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit - * will be cleared in either of the following cases: When the end bit of the last - * data block is sent from the SD bus to the SDHC. When the read wait state is - * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at - * the next block gap by driving read wait at the start of the interrupt cycle. - * If the read wait signal is already driven (data buffer cannot receive data), - * the SDHC can wait for a current block gap by continuing to drive the read wait - * signal. It is necessary to support read wait to use the suspend / resume - * function. This bit will remain 1 during read wait. In the case of write - * transactions: This status indicates that a write transfer is executing on the SD bus. - * Changes in this value from 1 to 0 generate a transfer complete interrupt in the - * interrupt status register. This bit will be set in either of the following - * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to - * continue a write transfer. This bit will be cleared in either of the - * following cases: When the SD card releases write busy of the last data block, the SDHC - * will also detect if the output is not busy. If the SD card does not drive the - * busy signal after the CRC status is received, the SDHC shall assume the card - * drive "Not busy". When the SD card releases write busy, prior to waiting for - * write transfer, and as a result of a stop at block gap request. In the case of - * command with busy pending: This status indicates that a busy state follows the - * command and the data line is in use. This bit will be cleared when the DAT0 - * line is released. - * - * Values: - * - 0 - DAT line inactive. - * - 1 - DAT line active. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_DLA (2U) /*!< Bit position for SDHC_PRSSTAT_DLA. */ -#define BM_SDHC_PRSSTAT_DLA (0x00000004U) /*!< Bit mask for SDHC_PRSSTAT_DLA. */ -#define BS_SDHC_PRSSTAT_DLA (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_DLA. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */ -#define BR_SDHC_PRSSTAT_DLA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_DLA)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO) - * - * Indicates that the internal card clock is stable. This bit is for the host - * driver to poll clock status when changing the clock frequency. It is recommended - * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the - * frequency is changing. - * - * Values: - * - 0 - Clock is changing frequency and not stable. - * - 1 - Clock is stable. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_SDSTB (3U) /*!< Bit position for SDHC_PRSSTAT_SDSTB. */ -#define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) /*!< Bit mask for SDHC_PRSSTAT_SDSTB. */ -#define BS_SDHC_PRSSTAT_SDSTB (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_SDSTB. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */ -#define BR_SDHC_PRSSTAT_SDSTB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDSTB)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO) - * - * Indicates that the bus clock is internally gated off. This bit is for the - * host driver to debug. - * - * Values: - * - 0 - Bus clock is active. - * - 1 - Bus clock is gated off. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_IPGOFF (4U) /*!< Bit position for SDHC_PRSSTAT_IPGOFF. */ -#define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) /*!< Bit mask for SDHC_PRSSTAT_IPGOFF. */ -#define BS_SDHC_PRSSTAT_IPGOFF (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */ -#define BR_SDHC_PRSSTAT_IPGOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_IPGOFF)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO) - * - * Indicates that the system clock is internally gated off. This bit is for the - * host driver to debug during a data transfer. - * - * Values: - * - 0 - System clock is active. - * - 1 - System clock is gated off. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_HCKOFF (5U) /*!< Bit position for SDHC_PRSSTAT_HCKOFF. */ -#define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) /*!< Bit mask for SDHC_PRSSTAT_HCKOFF. */ -#define BS_SDHC_PRSSTAT_HCKOFF (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */ -#define BR_SDHC_PRSSTAT_HCKOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_HCKOFF)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO) - * - * Indicates that the is internally gated off. This bit is for the host driver - * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80 - * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock, - * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC - * clock SDHC clock bus clock - * - * Values: - * - 0 - SDHC clock is active. - * - 1 - SDHC clock is gated off. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_PEROFF (6U) /*!< Bit position for SDHC_PRSSTAT_PEROFF. */ -#define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) /*!< Bit mask for SDHC_PRSSTAT_PEROFF. */ -#define BS_SDHC_PRSSTAT_PEROFF (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_PEROFF. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */ -#define BR_SDHC_PRSSTAT_PEROFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_PEROFF)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO) - * - * Indicates that the SD clock is internally gated off, because of buffer - * over/under-run or read pause without read wait assertion, or the driver has cleared - * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug - * data transaction on the SD bus. - * - * Values: - * - 0 - SD clock is active. - * - 1 - SD clock is gated off. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_SDOFF (7U) /*!< Bit position for SDHC_PRSSTAT_SDOFF. */ -#define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) /*!< Bit mask for SDHC_PRSSTAT_SDOFF. */ -#define BS_SDHC_PRSSTAT_SDOFF (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_SDOFF. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */ -#define BR_SDHC_PRSSTAT_SDOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDOFF)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field WTA[8] (RO) - * - * Indicates that a write transfer is active. If this bit is 0, it means no - * valid write data exists in the SDHC. This bit is set in either of the following - * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to - * restart a write transfer. This bit is cleared in either of the following - * cases: After getting the CRC status of the last data block as specified by the - * transfer count (single and multiple). After getting the CRC status of any block - * where data transmission is about to be stopped by a stop at block gap request. - * During a write transaction, a block gap event interrupt is generated when this - * bit is changed to 0, as result of the stop at block gap request being set. - * This status is useful for the host driver in determining when to issue commands - * during write busy state. - * - * Values: - * - 0 - No valid data. - * - 1 - Transferring data. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_WTA (8U) /*!< Bit position for SDHC_PRSSTAT_WTA. */ -#define BM_SDHC_PRSSTAT_WTA (0x00000100U) /*!< Bit mask for SDHC_PRSSTAT_WTA. */ -#define BS_SDHC_PRSSTAT_WTA (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_WTA. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */ -#define BR_SDHC_PRSSTAT_WTA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_WTA)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field RTA[9] (RO) - * - * Used for detecting completion of a read transfer. This bit is set for either - * of the following conditions: After the end bit of the read command. When - * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete - * interrupt is generated when this bit changes to 0. This bit is cleared for either of - * the following conditions: When the last data block as specified by block - * length is transferred to the system, that is, all data are read away from SDHC - * internal buffer. When all valid data blocks have been transferred from SDHC - * internal buffer to the system and no current block transfers are being sent as a - * result of the stop at block gap request being set to 1. - * - * Values: - * - 0 - No valid data. - * - 1 - Transferring data. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_RTA (9U) /*!< Bit position for SDHC_PRSSTAT_RTA. */ -#define BM_SDHC_PRSSTAT_RTA (0x00000200U) /*!< Bit mask for SDHC_PRSSTAT_RTA. */ -#define BS_SDHC_PRSSTAT_RTA (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_RTA. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */ -#define BR_SDHC_PRSSTAT_RTA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_RTA)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field BWEN[10] (RO) - * - * Used for non-DMA write transfers. The SDHC can implement multiple buffers to - * transfer data efficiently. This read-only flag indicates whether space is - * available for write data. If this bit is 1, valid data greater than the watermark - * level can be written to the buffer. This read-only flag indicates whether - * space is available for write data. - * - * Values: - * - 0 - Write disable, the buffer can hold valid data less than the write - * watermark level. - * - 1 - Write enable, the buffer can hold valid data greater than the write - * watermark level. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_BWEN (10U) /*!< Bit position for SDHC_PRSSTAT_BWEN. */ -#define BM_SDHC_PRSSTAT_BWEN (0x00000400U) /*!< Bit mask for SDHC_PRSSTAT_BWEN. */ -#define BS_SDHC_PRSSTAT_BWEN (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_BWEN. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */ -#define BR_SDHC_PRSSTAT_BWEN(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BWEN)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field BREN[11] (RO) - * - * Used for non-DMA read transfers. The SDHC may implement multiple buffers to - * transfer data efficiently. This read-only flag indicates that valid data exists - * in the host side buffer. If this bit is high, valid data greater than the - * watermark level exist in the buffer. This read-only flag indicates that valid - * data exists in the host side buffer. - * - * Values: - * - 0 - Read disable, valid data less than the watermark level exist in the - * buffer. - * - 1 - Read enable, valid data greater than the watermark level exist in the - * buffer. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_BREN (11U) /*!< Bit position for SDHC_PRSSTAT_BREN. */ -#define BM_SDHC_PRSSTAT_BREN (0x00000800U) /*!< Bit mask for SDHC_PRSSTAT_BREN. */ -#define BS_SDHC_PRSSTAT_BREN (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_BREN. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */ -#define BR_SDHC_PRSSTAT_BREN(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BREN)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field CINS[16] (RO) - * - * Indicates whether a card has been inserted. The SDHC debounces this signal so - * that the host driver will not need to wait for it to stabilize. Changing from - * a 0 to 1 generates a card insertion interrupt in the Interrupt Status - * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt - * Status register. A write to the force event register does not effect this bit. - * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this - * bit. - * - * Values: - * - 0 - Power on reset or no card. - * - 1 - Card inserted. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_CINS (16U) /*!< Bit position for SDHC_PRSSTAT_CINS. */ -#define BM_SDHC_PRSSTAT_CINS (0x00010000U) /*!< Bit mask for SDHC_PRSSTAT_CINS. */ -#define BS_SDHC_PRSSTAT_CINS (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_CINS. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */ -#define BR_SDHC_PRSSTAT_CINS(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CINS)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field CLSL[23] (RO) - * - * Used to check the CMD line level to recover from errors, and for debugging. - * The reset value is effected by the external pullup/pulldown resistor, by - * default, the read value of this bit after reset is 1b, when the command line is - * pulled up. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_CLSL (23U) /*!< Bit position for SDHC_PRSSTAT_CLSL. */ -#define BM_SDHC_PRSSTAT_CLSL (0x00800000U) /*!< Bit mask for SDHC_PRSSTAT_CLSL. */ -#define BS_SDHC_PRSSTAT_CLSL (1U) /*!< Bit field size in bits for SDHC_PRSSTAT_CLSL. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */ -#define BR_SDHC_PRSSTAT_CLSL(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CLSL)) -/*@}*/ - -/*! - * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO) - * - * Used to check the DAT line level to recover from errors, and for debugging. - * This is especially useful in detecting the busy signal level from DAT[0]. The - * reset value is effected by the external pullup/pulldown resistors. By default, - * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled - * down and the other lines are pulled up. - */ -/*@{*/ -#define BP_SDHC_PRSSTAT_DLSL (24U) /*!< Bit position for SDHC_PRSSTAT_DLSL. */ -#define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) /*!< Bit mask for SDHC_PRSSTAT_DLSL. */ -#define BS_SDHC_PRSSTAT_DLSL (8U) /*!< Bit field size in bits for SDHC_PRSSTAT_DLSL. */ - -/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */ -#define BR_SDHC_PRSSTAT_DLSL(x) (HW_SDHC_PRSSTAT(x).B.DLSL) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_PROCTL - Protocol Control register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_PROCTL - Protocol Control register (RW) - * - * Reset value: 0x00000020U - * - * There are three cases to restart the transfer after stop at the block gap. - * Which case is appropriate depends on whether the SDHC issues a suspend command - * or the SD card accepts the suspend command: If the host driver does not issue a - * suspend command, the continue request shall be used to restart the transfer. - * If the host driver issues a suspend command and the SD card accepts it, a - * resume command shall be used to restart the transfer. If the host driver issues a - * suspend command and the SD card does not accept it, the continue request shall - * be used to restart the transfer. Any time stop at block gap request stops the - * data transfer, the host driver shall wait for a transfer complete (in the - * interrupt status register), before attempting to restart the transfer. When - * restarting the data transfer by continue request, the host driver shall clear the - * stop at block gap request before or simultaneously. - */ -typedef union _hw_sdhc_proctl -{ - uint32_t U; - struct _hw_sdhc_proctl_bitfields - { - uint32_t LCTL : 1; /*!< [0] LED Control */ - uint32_t DTW : 2; /*!< [2:1] Data Transfer Width */ - uint32_t D3CD : 1; /*!< [3] DAT3 As Card Detection Pin */ - uint32_t EMODE : 2; /*!< [5:4] Endian Mode */ - uint32_t CDTL : 1; /*!< [6] Card Detect Test Level */ - uint32_t CDSS : 1; /*!< [7] Card Detect Signal Selection */ - uint32_t DMAS : 2; /*!< [9:8] DMA Select */ - uint32_t RESERVED0 : 6; /*!< [15:10] */ - uint32_t SABGREQ : 1; /*!< [16] Stop At Block Gap Request */ - uint32_t CREQ : 1; /*!< [17] Continue Request */ - uint32_t RWCTL : 1; /*!< [18] Read Wait Control */ - uint32_t IABG : 1; /*!< [19] Interrupt At Block Gap */ - uint32_t RESERVED1 : 4; /*!< [23:20] */ - uint32_t WECINT : 1; /*!< [24] Wakeup Event Enable On Card Interrupt - * */ - uint32_t WECINS : 1; /*!< [25] Wakeup Event Enable On SD Card - * Insertion */ - uint32_t WECRM : 1; /*!< [26] Wakeup Event Enable On SD Card Removal - * */ - uint32_t RESERVED2 : 5; /*!< [31:27] */ - } B; -} hw_sdhc_proctl_t; - -/*! - * @name Constants and macros for entire SDHC_PROCTL register - */ -/*@{*/ -#define HW_SDHC_PROCTL_ADDR(x) ((x) + 0x28U) - -#define HW_SDHC_PROCTL(x) (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR(x)) -#define HW_SDHC_PROCTL_RD(x) (HW_SDHC_PROCTL(x).U) -#define HW_SDHC_PROCTL_WR(x, v) (HW_SDHC_PROCTL(x).U = (v)) -#define HW_SDHC_PROCTL_SET(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) | (v))) -#define HW_SDHC_PROCTL_CLR(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) & ~(v))) -#define HW_SDHC_PROCTL_TOG(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_PROCTL bitfields - */ - -/*! - * @name Register SDHC_PROCTL, field LCTL[0] (RW) - * - * This bit, fully controlled by the host driver, is used to caution the user - * not to remove the card while the card is being accessed. If the software is - * going to issue multiple SD commands, this bit can be set during all these - * transactions. It is not necessary to change for each transaction. When the software - * issues multiple SD commands, setting the bit once before the first command is - * sufficient: it is not necessary to reset the bit between commands. - * - * Values: - * - 0 - LED off. - * - 1 - LED on. - */ -/*@{*/ -#define BP_SDHC_PROCTL_LCTL (0U) /*!< Bit position for SDHC_PROCTL_LCTL. */ -#define BM_SDHC_PROCTL_LCTL (0x00000001U) /*!< Bit mask for SDHC_PROCTL_LCTL. */ -#define BS_SDHC_PROCTL_LCTL (1U) /*!< Bit field size in bits for SDHC_PROCTL_LCTL. */ - -/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */ -#define BR_SDHC_PROCTL_LCTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL)) - -/*! @brief Format value for bitfield SDHC_PROCTL_LCTL. */ -#define BF_SDHC_PROCTL_LCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_LCTL) & BM_SDHC_PROCTL_LCTL) - -/*! @brief Set the LCTL field to a new value. */ -#define BW_SDHC_PROCTL_LCTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field DTW[2:1] (RW) - * - * Selects the data width of the SD bus for a data transfer. The host driver - * shall set it to match the data width of the card. Possible data transfer width is - * 1-bit, 4-bits or 8-bits. - * - * Values: - * - 00 - 1-bit mode - * - 01 - 4-bit mode - * - 10 - 8-bit mode - * - 11 - Reserved - */ -/*@{*/ -#define BP_SDHC_PROCTL_DTW (1U) /*!< Bit position for SDHC_PROCTL_DTW. */ -#define BM_SDHC_PROCTL_DTW (0x00000006U) /*!< Bit mask for SDHC_PROCTL_DTW. */ -#define BS_SDHC_PROCTL_DTW (2U) /*!< Bit field size in bits for SDHC_PROCTL_DTW. */ - -/*! @brief Read current value of the SDHC_PROCTL_DTW field. */ -#define BR_SDHC_PROCTL_DTW(x) (HW_SDHC_PROCTL(x).B.DTW) - -/*! @brief Format value for bitfield SDHC_PROCTL_DTW. */ -#define BF_SDHC_PROCTL_DTW(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DTW) & BM_SDHC_PROCTL_DTW) - -/*! @brief Set the DTW field to a new value. */ -#define BW_SDHC_PROCTL_DTW(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v))) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field D3CD[3] (RW) - * - * If this bit is set, DAT3 should be pulled down to act as a card detection - * pin. Be cautious when using this feature, because DAT3 is also a chip-select for - * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI - * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt - * is used. - * - * Values: - * - 0 - DAT3 does not monitor card Insertion. - * - 1 - DAT3 as card detection pin. - */ -/*@{*/ -#define BP_SDHC_PROCTL_D3CD (3U) /*!< Bit position for SDHC_PROCTL_D3CD. */ -#define BM_SDHC_PROCTL_D3CD (0x00000008U) /*!< Bit mask for SDHC_PROCTL_D3CD. */ -#define BS_SDHC_PROCTL_D3CD (1U) /*!< Bit field size in bits for SDHC_PROCTL_D3CD. */ - -/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */ -#define BR_SDHC_PROCTL_D3CD(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD)) - -/*! @brief Format value for bitfield SDHC_PROCTL_D3CD. */ -#define BF_SDHC_PROCTL_D3CD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_D3CD) & BM_SDHC_PROCTL_D3CD) - -/*! @brief Set the D3CD field to a new value. */ -#define BW_SDHC_PROCTL_D3CD(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field EMODE[5:4] (RW) - * - * The SDHC supports all four endian modes in data transfer. - * - * Values: - * - 00 - Big endian mode - * - 01 - Half word big endian mode - * - 10 - Little endian mode - * - 11 - Reserved - */ -/*@{*/ -#define BP_SDHC_PROCTL_EMODE (4U) /*!< Bit position for SDHC_PROCTL_EMODE. */ -#define BM_SDHC_PROCTL_EMODE (0x00000030U) /*!< Bit mask for SDHC_PROCTL_EMODE. */ -#define BS_SDHC_PROCTL_EMODE (2U) /*!< Bit field size in bits for SDHC_PROCTL_EMODE. */ - -/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */ -#define BR_SDHC_PROCTL_EMODE(x) (HW_SDHC_PROCTL(x).B.EMODE) - -/*! @brief Format value for bitfield SDHC_PROCTL_EMODE. */ -#define BF_SDHC_PROCTL_EMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_EMODE) & BM_SDHC_PROCTL_EMODE) - -/*! @brief Set the EMODE field to a new value. */ -#define BW_SDHC_PROCTL_EMODE(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v))) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field CDTL[6] (RW) - * - * Enabled while the CDSS is set to 1 and it indicates card insertion. - * - * Values: - * - 0 - Card detect test level is 0, no card inserted. - * - 1 - Card detect test level is 1, card inserted. - */ -/*@{*/ -#define BP_SDHC_PROCTL_CDTL (6U) /*!< Bit position for SDHC_PROCTL_CDTL. */ -#define BM_SDHC_PROCTL_CDTL (0x00000040U) /*!< Bit mask for SDHC_PROCTL_CDTL. */ -#define BS_SDHC_PROCTL_CDTL (1U) /*!< Bit field size in bits for SDHC_PROCTL_CDTL. */ - -/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */ -#define BR_SDHC_PROCTL_CDTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL)) - -/*! @brief Format value for bitfield SDHC_PROCTL_CDTL. */ -#define BF_SDHC_PROCTL_CDTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDTL) & BM_SDHC_PROCTL_CDTL) - -/*! @brief Set the CDTL field to a new value. */ -#define BW_SDHC_PROCTL_CDTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field CDSS[7] (RW) - * - * Selects the source for the card detection. - * - * Values: - * - 0 - Card detection level is selected for normal purpose. - * - 1 - Card detection test level is selected for test purpose. - */ -/*@{*/ -#define BP_SDHC_PROCTL_CDSS (7U) /*!< Bit position for SDHC_PROCTL_CDSS. */ -#define BM_SDHC_PROCTL_CDSS (0x00000080U) /*!< Bit mask for SDHC_PROCTL_CDSS. */ -#define BS_SDHC_PROCTL_CDSS (1U) /*!< Bit field size in bits for SDHC_PROCTL_CDSS. */ - -/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */ -#define BR_SDHC_PROCTL_CDSS(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS)) - -/*! @brief Format value for bitfield SDHC_PROCTL_CDSS. */ -#define BF_SDHC_PROCTL_CDSS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDSS) & BM_SDHC_PROCTL_CDSS) - -/*! @brief Set the CDSS field to a new value. */ -#define BW_SDHC_PROCTL_CDSS(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field DMAS[9:8] (RW) - * - * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA - * operation. - * - * Values: - * - 00 - No DMA or simple DMA is selected. - * - 01 - ADMA1 is selected. - * - 10 - ADMA2 is selected. - * - 11 - Reserved - */ -/*@{*/ -#define BP_SDHC_PROCTL_DMAS (8U) /*!< Bit position for SDHC_PROCTL_DMAS. */ -#define BM_SDHC_PROCTL_DMAS (0x00000300U) /*!< Bit mask for SDHC_PROCTL_DMAS. */ -#define BS_SDHC_PROCTL_DMAS (2U) /*!< Bit field size in bits for SDHC_PROCTL_DMAS. */ - -/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */ -#define BR_SDHC_PROCTL_DMAS(x) (HW_SDHC_PROCTL(x).B.DMAS) - -/*! @brief Format value for bitfield SDHC_PROCTL_DMAS. */ -#define BF_SDHC_PROCTL_DMAS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DMAS) & BM_SDHC_PROCTL_DMAS) - -/*! @brief Set the DMAS field to a new value. */ -#define BW_SDHC_PROCTL_DMAS(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v))) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field SABGREQ[16] (RW) - * - * Used to stop executing a transaction at the next block gap for both DMA and - * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a - * transfer completion, the host driver shall leave this bit set to 1. Clearing both - * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read - * Wait is used to stop the read transaction at the block gap. The SDHC will - * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires - * that SDIO card support read wait. Therefore, the host driver shall not set - * this bit during read transfers unless the SDIO card supports read wait and has - * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause - * the read operation during block gap. In the case of write transfers in which - * the host driver writes data to the data port register, the host driver shall set - * this bit after all block data is written. If this bit is set to 1, the host - * driver shall not write data to the Data Port register after a block is sent. - * Once this bit is set, the host driver shall not clear this bit before - * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects - * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB]. - * - * Values: - * - 0 - Transfer - * - 1 - Stop - */ -/*@{*/ -#define BP_SDHC_PROCTL_SABGREQ (16U) /*!< Bit position for SDHC_PROCTL_SABGREQ. */ -#define BM_SDHC_PROCTL_SABGREQ (0x00010000U) /*!< Bit mask for SDHC_PROCTL_SABGREQ. */ -#define BS_SDHC_PROCTL_SABGREQ (1U) /*!< Bit field size in bits for SDHC_PROCTL_SABGREQ. */ - -/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */ -#define BR_SDHC_PROCTL_SABGREQ(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ)) - -/*! @brief Format value for bitfield SDHC_PROCTL_SABGREQ. */ -#define BF_SDHC_PROCTL_SABGREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_SABGREQ) & BM_SDHC_PROCTL_SABGREQ) - -/*! @brief Set the SABGREQ field to a new value. */ -#define BW_SDHC_PROCTL_SABGREQ(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field CREQ[17] (RW) - * - * Used to restart a transaction which was stopped using the PROCTL[SABGREQ]. - * When a suspend operation is not accepted by the card, it is also by setting this - * bit to restart the paused transfer. To cancel stop at the block gap, set - * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC - * automatically clears this bit, therefore it is not necessary for the host driver to - * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue - * request is ignored. - * - * Values: - * - 0 - No effect. - * - 1 - Restart - */ -/*@{*/ -#define BP_SDHC_PROCTL_CREQ (17U) /*!< Bit position for SDHC_PROCTL_CREQ. */ -#define BM_SDHC_PROCTL_CREQ (0x00020000U) /*!< Bit mask for SDHC_PROCTL_CREQ. */ -#define BS_SDHC_PROCTL_CREQ (1U) /*!< Bit field size in bits for SDHC_PROCTL_CREQ. */ - -/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */ -#define BR_SDHC_PROCTL_CREQ(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ)) - -/*! @brief Format value for bitfield SDHC_PROCTL_CREQ. */ -#define BF_SDHC_PROCTL_CREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CREQ) & BM_SDHC_PROCTL_CREQ) - -/*! @brief Set the CREQ field to a new value. */ -#define BW_SDHC_PROCTL_CREQ(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field RWCTL[18] (RW) - * - * The read wait function is optional for SDIO cards. If the card supports read - * wait, set this bit to enable use of the read wait protocol to stop read data - * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold - * read data, which restricts commands generation. When the host driver detects an - * SDIO card insertion, it shall set this bit according to the CCCR of the card. - * If the card does not support read wait, this bit shall never be set to 1, - * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap - * during read operation is also supported, but the SDHC will stop the SD Clock - * to pause reading operation. - * - * Values: - * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ - * is set. - * - 1 - Enable read wait control, and assert read wait without stopping SD - * clock at block gap when SABGREQ bit is set. - */ -/*@{*/ -#define BP_SDHC_PROCTL_RWCTL (18U) /*!< Bit position for SDHC_PROCTL_RWCTL. */ -#define BM_SDHC_PROCTL_RWCTL (0x00040000U) /*!< Bit mask for SDHC_PROCTL_RWCTL. */ -#define BS_SDHC_PROCTL_RWCTL (1U) /*!< Bit field size in bits for SDHC_PROCTL_RWCTL. */ - -/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */ -#define BR_SDHC_PROCTL_RWCTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL)) - -/*! @brief Format value for bitfield SDHC_PROCTL_RWCTL. */ -#define BF_SDHC_PROCTL_RWCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_RWCTL) & BM_SDHC_PROCTL_RWCTL) - -/*! @brief Set the RWCTL field to a new value. */ -#define BW_SDHC_PROCTL_RWCTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field IABG[19] (RW) - * - * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the - * interrupt cycle. Setting to 1 enables interrupt detection at the block gap - * for a multiple block transfer. Setting to 0 disables interrupt detection during - * a multiple block transfer. If the SDIO card can't signal an interrupt during a - * multiple block transfer, this bit must be set to 0 to avoid an inadvertent - * interrupt. When the host driver detects an SDIO card insertion, it shall set - * this bit according to the CCCR of the card. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_PROCTL_IABG (19U) /*!< Bit position for SDHC_PROCTL_IABG. */ -#define BM_SDHC_PROCTL_IABG (0x00080000U) /*!< Bit mask for SDHC_PROCTL_IABG. */ -#define BS_SDHC_PROCTL_IABG (1U) /*!< Bit field size in bits for SDHC_PROCTL_IABG. */ - -/*! @brief Read current value of the SDHC_PROCTL_IABG field. */ -#define BR_SDHC_PROCTL_IABG(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG)) - -/*! @brief Format value for bitfield SDHC_PROCTL_IABG. */ -#define BF_SDHC_PROCTL_IABG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_IABG) & BM_SDHC_PROCTL_IABG) - -/*! @brief Set the IABG field to a new value. */ -#define BW_SDHC_PROCTL_IABG(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field WECINT[24] (RW) - * - * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS - * (Wake Up Support) in CIS is set to 1. When this bit is set, the card - * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When - * the wakeup feature is not enabled, the SD_CLK must be active to assert the - * card interrupt status and the SDHC interrupt. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_PROCTL_WECINT (24U) /*!< Bit position for SDHC_PROCTL_WECINT. */ -#define BM_SDHC_PROCTL_WECINT (0x01000000U) /*!< Bit mask for SDHC_PROCTL_WECINT. */ -#define BS_SDHC_PROCTL_WECINT (1U) /*!< Bit field size in bits for SDHC_PROCTL_WECINT. */ - -/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */ -#define BR_SDHC_PROCTL_WECINT(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT)) - -/*! @brief Format value for bitfield SDHC_PROCTL_WECINT. */ -#define BF_SDHC_PROCTL_WECINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINT) & BM_SDHC_PROCTL_WECINT) - -/*! @brief Set the WECINT field to a new value. */ -#define BW_SDHC_PROCTL_WECINT(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field WECINS[25] (RW) - * - * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS - * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC - * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is - * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC - * interrupt. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_PROCTL_WECINS (25U) /*!< Bit position for SDHC_PROCTL_WECINS. */ -#define BM_SDHC_PROCTL_WECINS (0x02000000U) /*!< Bit mask for SDHC_PROCTL_WECINS. */ -#define BS_SDHC_PROCTL_WECINS (1U) /*!< Bit field size in bits for SDHC_PROCTL_WECINS. */ - -/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */ -#define BR_SDHC_PROCTL_WECINS(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS)) - -/*! @brief Format value for bitfield SDHC_PROCTL_WECINS. */ -#define BF_SDHC_PROCTL_WECINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINS) & BM_SDHC_PROCTL_WECINS) - -/*! @brief Set the WECINS field to a new value. */ -#define BW_SDHC_PROCTL_WECINS(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_PROCTL, field WECRM[26] (RW) - * - * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS - * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC - * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not - * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_PROCTL_WECRM (26U) /*!< Bit position for SDHC_PROCTL_WECRM. */ -#define BM_SDHC_PROCTL_WECRM (0x04000000U) /*!< Bit mask for SDHC_PROCTL_WECRM. */ -#define BS_SDHC_PROCTL_WECRM (1U) /*!< Bit field size in bits for SDHC_PROCTL_WECRM. */ - -/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */ -#define BR_SDHC_PROCTL_WECRM(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM)) - -/*! @brief Format value for bitfield SDHC_PROCTL_WECRM. */ -#define BF_SDHC_PROCTL_WECRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECRM) & BM_SDHC_PROCTL_WECRM) - -/*! @brief Set the WECRM field to a new value. */ -#define BW_SDHC_PROCTL_WECRM(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_SYSCTL - System Control register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_SYSCTL - System Control register (RW) - * - * Reset value: 0x00008008U - */ -typedef union _hw_sdhc_sysctl -{ - uint32_t U; - struct _hw_sdhc_sysctl_bitfields - { - uint32_t IPGEN : 1; /*!< [0] IPG Clock Enable */ - uint32_t HCKEN : 1; /*!< [1] System Clock Enable */ - uint32_t PEREN : 1; /*!< [2] Peripheral Clock Enable */ - uint32_t SDCLKEN : 1; /*!< [3] SD Clock Enable */ - uint32_t DVS : 4; /*!< [7:4] Divisor */ - uint32_t SDCLKFS : 8; /*!< [15:8] SDCLK Frequency Select */ - uint32_t DTOCV : 4; /*!< [19:16] Data Timeout Counter Value */ - uint32_t RESERVED0 : 4; /*!< [23:20] */ - uint32_t RSTA : 1; /*!< [24] Software Reset For ALL */ - uint32_t RSTC : 1; /*!< [25] Software Reset For CMD Line */ - uint32_t RSTD : 1; /*!< [26] Software Reset For DAT Line */ - uint32_t INITA : 1; /*!< [27] Initialization Active */ - uint32_t RESERVED1 : 4; /*!< [31:28] */ - } B; -} hw_sdhc_sysctl_t; - -/*! - * @name Constants and macros for entire SDHC_SYSCTL register - */ -/*@{*/ -#define HW_SDHC_SYSCTL_ADDR(x) ((x) + 0x2CU) - -#define HW_SDHC_SYSCTL(x) (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR(x)) -#define HW_SDHC_SYSCTL_RD(x) (HW_SDHC_SYSCTL(x).U) -#define HW_SDHC_SYSCTL_WR(x, v) (HW_SDHC_SYSCTL(x).U = (v)) -#define HW_SDHC_SYSCTL_SET(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) | (v))) -#define HW_SDHC_SYSCTL_CLR(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) & ~(v))) -#define HW_SDHC_SYSCTL_TOG(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_SYSCTL bitfields - */ - -/*! - * @name Register SDHC_SYSCTL, field IPGEN[0] (RW) - * - * If this bit is set, bus clock will always be active and no automatic gating - * is applied. The bus clock will be internally gated off, if none of the - * following factors are met: The cmd part is reset, or Data part is reset, or Soft - * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue - * request is just set, or This bit is set, or Card insertion is detected, or Card - * removal is detected, or Card external interrupt is detected, or The SDHC - * clock is not gated off The bus clock will not be auto gated off if the SDHC clock - * is not gated off. So clearing only this bit has no effect unless the PEREN bit - * is also cleared. - * - * Values: - * - 0 - Bus clock will be internally gated off. - * - 1 - Bus clock will not be automatically gated off. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_IPGEN (0U) /*!< Bit position for SDHC_SYSCTL_IPGEN. */ -#define BM_SDHC_SYSCTL_IPGEN (0x00000001U) /*!< Bit mask for SDHC_SYSCTL_IPGEN. */ -#define BS_SDHC_SYSCTL_IPGEN (1U) /*!< Bit field size in bits for SDHC_SYSCTL_IPGEN. */ - -/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */ -#define BR_SDHC_SYSCTL_IPGEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN)) - -/*! @brief Format value for bitfield SDHC_SYSCTL_IPGEN. */ -#define BF_SDHC_SYSCTL_IPGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_IPGEN) & BM_SDHC_SYSCTL_IPGEN) - -/*! @brief Set the IPGEN field to a new value. */ -#define BW_SDHC_SYSCTL_IPGEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field HCKEN[1] (RW) - * - * If this bit is set, system clock will always be active and no automatic - * gating is applied. When this bit is cleared, system clock will be automatically off - * when no data transfer is on the SD bus. - * - * Values: - * - 0 - System clock will be internally gated off. - * - 1 - System clock will not be automatically gated off. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_HCKEN (1U) /*!< Bit position for SDHC_SYSCTL_HCKEN. */ -#define BM_SDHC_SYSCTL_HCKEN (0x00000002U) /*!< Bit mask for SDHC_SYSCTL_HCKEN. */ -#define BS_SDHC_SYSCTL_HCKEN (1U) /*!< Bit field size in bits for SDHC_SYSCTL_HCKEN. */ - -/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */ -#define BR_SDHC_SYSCTL_HCKEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN)) - -/*! @brief Format value for bitfield SDHC_SYSCTL_HCKEN. */ -#define BF_SDHC_SYSCTL_HCKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_HCKEN) & BM_SDHC_SYSCTL_HCKEN) - -/*! @brief Set the HCKEN field to a new value. */ -#define BW_SDHC_SYSCTL_HCKEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field PEREN[2] (RW) - * - * If this bit is set, SDHC clock will always be active and no automatic gating - * is applied. Thus the SDCLK is active except for when auto gating-off during - * buffer danger (buffer about to over-run or under-run). When this bit is cleared, - * the SDHC clock will be automatically off whenever there is no transaction on - * the SD bus. Because this bit is only a feature enabling bit, clearing this bit - * does not stop SDCLK immediately. The SDHC clock will be internally gated off, - * if none of the following factors are met: The cmd part is reset, or Data part - * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is - * just updated, or Continue request is just set, or This bit is set, or Card - * insertion is detected, or Card removal is detected, or Card external interrupt is - * detected, or 80 clocks for initialization phase is ongoing - * - * Values: - * - 0 - SDHC clock will be internally gated off. - * - 1 - SDHC clock will not be automatically gated off. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_PEREN (2U) /*!< Bit position for SDHC_SYSCTL_PEREN. */ -#define BM_SDHC_SYSCTL_PEREN (0x00000004U) /*!< Bit mask for SDHC_SYSCTL_PEREN. */ -#define BS_SDHC_SYSCTL_PEREN (1U) /*!< Bit field size in bits for SDHC_SYSCTL_PEREN. */ - -/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */ -#define BR_SDHC_SYSCTL_PEREN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN)) - -/*! @brief Format value for bitfield SDHC_SYSCTL_PEREN. */ -#define BF_SDHC_SYSCTL_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_PEREN) & BM_SDHC_SYSCTL_PEREN) - -/*! @brief Set the PEREN field to a new value. */ -#define BW_SDHC_SYSCTL_PEREN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW) - * - * The host controller shall stop SDCLK when writing this bit to 0. SDCLK - * frequency can be changed when this bit is 0. Then, the host controller shall - * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the - * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save - * power. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_SDCLKEN (3U) /*!< Bit position for SDHC_SYSCTL_SDCLKEN. */ -#define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) /*!< Bit mask for SDHC_SYSCTL_SDCLKEN. */ -#define BS_SDHC_SYSCTL_SDCLKEN (1U) /*!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN. */ - -/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */ -#define BR_SDHC_SYSCTL_SDCLKEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN)) - -/*! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN. */ -#define BF_SDHC_SYSCTL_SDCLKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKEN) & BM_SDHC_SYSCTL_SDCLKEN) - -/*! @brief Set the SDCLKEN field to a new value. */ -#define BW_SDHC_SYSCTL_SDCLKEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field DVS[7:4] (RW) - * - * Used to provide a more exact divisor to generate the desired SD clock - * frequency. Note the divider can even support odd divisor without deterioration of - * duty cycle. The setting are as following: - * - * Values: - * - 0 - Divisor by 1. - * - 1 - Divisor by 2. - * - 1110 - Divisor by 15. - * - 1111 - Divisor by 16. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_DVS (4U) /*!< Bit position for SDHC_SYSCTL_DVS. */ -#define BM_SDHC_SYSCTL_DVS (0x000000F0U) /*!< Bit mask for SDHC_SYSCTL_DVS. */ -#define BS_SDHC_SYSCTL_DVS (4U) /*!< Bit field size in bits for SDHC_SYSCTL_DVS. */ - -/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */ -#define BR_SDHC_SYSCTL_DVS(x) (HW_SDHC_SYSCTL(x).B.DVS) - -/*! @brief Format value for bitfield SDHC_SYSCTL_DVS. */ -#define BF_SDHC_SYSCTL_DVS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DVS) & BM_SDHC_SYSCTL_DVS) - -/*! @brief Set the DVS field to a new value. */ -#define BW_SDHC_SYSCTL_DVS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v))) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW) - * - * Used to select the frequency of the SDCLK pin. The frequency is not - * programmed directly. Rather this register holds the prescaler (this register) and - * divisor (next register) of the base clock frequency register. Setting 00h bypasses - * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the - * behavior of this prescaler is undefined. The two default divider values can - * be calculated by the frequency of SDHC clock and the following divisor bits. - * The frequency of SDCLK is set by the following formula: Clock frequency = (Base - * clock) / (prescaler x divisor) For example, if the base clock frequency is 96 - * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of - * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency - * less than or equal to the target. Similarly, to approach a clock value of 400 - * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock - * value of 400 kHz. The reset value of this field is 80h, so if the input base - * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375 - * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card - * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall - * never exceed this limit. Only the following settings are allowed: - * - * Values: - * - 1 - Base clock divided by 2. - * - 10 - Base clock divided by 4. - * - 100 - Base clock divided by 8. - * - 1000 - Base clock divided by 16. - * - 10000 - Base clock divided by 32. - * - 100000 - Base clock divided by 64. - * - 1000000 - Base clock divided by 128. - * - 10000000 - Base clock divided by 256. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_SDCLKFS (8U) /*!< Bit position for SDHC_SYSCTL_SDCLKFS. */ -#define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) /*!< Bit mask for SDHC_SYSCTL_SDCLKFS. */ -#define BS_SDHC_SYSCTL_SDCLKFS (8U) /*!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS. */ - -/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */ -#define BR_SDHC_SYSCTL_SDCLKFS(x) (HW_SDHC_SYSCTL(x).B.SDCLKFS) - -/*! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS. */ -#define BF_SDHC_SYSCTL_SDCLKFS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKFS) & BM_SDHC_SYSCTL_SDCLKFS) - -/*! @brief Set the SDCLKFS field to a new value. */ -#define BW_SDHC_SYSCTL_SDCLKFS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v))) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW) - * - * Determines the interval by which DAT line timeouts are detected. See - * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out - * clock frequency will be generated by dividing the base clock SDCLK value by this - * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent - * time-out events. - * - * Values: - * - 0000 - SDCLK x 2 13 - * - 0001 - SDCLK x 2 14 - * - 1110 - SDCLK x 2 27 - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SDHC_SYSCTL_DTOCV (16U) /*!< Bit position for SDHC_SYSCTL_DTOCV. */ -#define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) /*!< Bit mask for SDHC_SYSCTL_DTOCV. */ -#define BS_SDHC_SYSCTL_DTOCV (4U) /*!< Bit field size in bits for SDHC_SYSCTL_DTOCV. */ - -/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */ -#define BR_SDHC_SYSCTL_DTOCV(x) (HW_SDHC_SYSCTL(x).B.DTOCV) - -/*! @brief Format value for bitfield SDHC_SYSCTL_DTOCV. */ -#define BF_SDHC_SYSCTL_DTOCV(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DTOCV) & BM_SDHC_SYSCTL_DTOCV) - -/*! @brief Set the DTOCV field to a new value. */ -#define BW_SDHC_SYSCTL_DTOCV(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v))) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ) - * - * Effects the entire host controller except for the card detection circuit. - * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization, - * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall - * reset this bit to 0 when the capabilities registers are valid and the host driver - * can read them. Additional use of software reset for all does not affect the - * value of the capabilities registers. After this bit is set, it is recommended - * that the host driver reset the external card and reinitialize it. - * - * Values: - * - 0 - No reset. - * - 1 - Reset. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_RSTA (24U) /*!< Bit position for SDHC_SYSCTL_RSTA. */ -#define BM_SDHC_SYSCTL_RSTA (0x01000000U) /*!< Bit mask for SDHC_SYSCTL_RSTA. */ -#define BS_SDHC_SYSCTL_RSTA (1U) /*!< Bit field size in bits for SDHC_SYSCTL_RSTA. */ - -/*! @brief Format value for bitfield SDHC_SYSCTL_RSTA. */ -#define BF_SDHC_SYSCTL_RSTA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTA) & BM_SDHC_SYSCTL_RSTA) - -/*! @brief Set the RSTA field to a new value. */ -#define BW_SDHC_SYSCTL_RSTA(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTA) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ) - * - * Only part of the command circuit is reset. The following registers and bits - * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC] - * - * Values: - * - 0 - No reset. - * - 1 - Reset. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_RSTC (25U) /*!< Bit position for SDHC_SYSCTL_RSTC. */ -#define BM_SDHC_SYSCTL_RSTC (0x02000000U) /*!< Bit mask for SDHC_SYSCTL_RSTC. */ -#define BS_SDHC_SYSCTL_RSTC (1U) /*!< Bit field size in bits for SDHC_SYSCTL_RSTC. */ - -/*! @brief Format value for bitfield SDHC_SYSCTL_RSTC. */ -#define BF_SDHC_SYSCTL_RSTC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTC) & BM_SDHC_SYSCTL_RSTC) - -/*! @brief Set the RSTC field to a new value. */ -#define BW_SDHC_SYSCTL_RSTC(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTC) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ) - * - * Only part of the data circuit is reset. DMA circuit is also reset. The - * following registers and bits are cleared by this bit: Data Port register Buffer Is - * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write - * Enable Read Transfer Active Write Transfer Active DAT Line Active Command - * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request - * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt - * Block Gap Event Transfer Complete - * - * Values: - * - 0 - No reset. - * - 1 - Reset. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_RSTD (26U) /*!< Bit position for SDHC_SYSCTL_RSTD. */ -#define BM_SDHC_SYSCTL_RSTD (0x04000000U) /*!< Bit mask for SDHC_SYSCTL_RSTD. */ -#define BS_SDHC_SYSCTL_RSTD (1U) /*!< Bit field size in bits for SDHC_SYSCTL_RSTD. */ - -/*! @brief Format value for bitfield SDHC_SYSCTL_RSTD. */ -#define BF_SDHC_SYSCTL_RSTD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTD) & BM_SDHC_SYSCTL_RSTD) - -/*! @brief Set the RSTD field to a new value. */ -#define BW_SDHC_SYSCTL_RSTD(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTD) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_SYSCTL, field INITA[27] (RW) - * - * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks - * are sent, this bit is self-cleared. This bit is very useful during the card - * power-up period when 74 SD-clocks are needed and the clock auto gating feature - * is enabled. Writing 1 to this bit when this bit is already 1 has no effect. - * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB] - * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is, - * when command line or data lines are active, write to this bit is not allowed. - * On the otherhand, when this bit is set, that is, during intialization active - * period, it is allowed to issue command, and the command bit stream will appear - * on the CMD pad after all 80 clock cycles are done. So when this command ends, - * the driver can make sure the 80 clock cycles are sent out. This is very useful - * when the driver needs send 80 cycles to the card and does not want to wait - * till this bit is self-cleared. - */ -/*@{*/ -#define BP_SDHC_SYSCTL_INITA (27U) /*!< Bit position for SDHC_SYSCTL_INITA. */ -#define BM_SDHC_SYSCTL_INITA (0x08000000U) /*!< Bit mask for SDHC_SYSCTL_INITA. */ -#define BS_SDHC_SYSCTL_INITA (1U) /*!< Bit field size in bits for SDHC_SYSCTL_INITA. */ - -/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */ -#define BR_SDHC_SYSCTL_INITA(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA)) - -/*! @brief Format value for bitfield SDHC_SYSCTL_INITA. */ -#define BF_SDHC_SYSCTL_INITA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_INITA) & BM_SDHC_SYSCTL_INITA) - -/*! @brief Set the INITA field to a new value. */ -#define BW_SDHC_SYSCTL_INITA(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_IRQSTAT - Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW) - * - * Reset value: 0x00000000U - * - * An interrupt is generated when the Normal Interrupt Signal Enable is enabled - * and at least one of the status bits is set to 1. For all bits, writing 1 to a - * bit clears it; writing to 0 keeps the bit unchanged. More than one status can - * be cleared with a single register write. For Card Interrupt, before writing 1 - * to clear, it is required that the card stops asserting the interrupt, meaning - * that when the Card Driver services the interrupt condition, otherwise the CINT - * bit will be asserted again. The table below shows the relationship between - * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command - * complete Command timeout error Meaning of the status 0 0 X X 1 Response not - * received within 64 SDCLK cycles 1 0 Response received The table below shows the - * relationship between the Transfer Complete and the Data Timeout Error. SDHC status - * for data timeout error/transfer complete bit combinations Transfer complete - * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during - * transfer 1 X Data transfer complete The table below shows the relationship between - * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for - * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of - * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1 - * CMD line conflict - */ -typedef union _hw_sdhc_irqstat -{ - uint32_t U; - struct _hw_sdhc_irqstat_bitfields - { - uint32_t CC : 1; /*!< [0] Command Complete */ - uint32_t TC : 1; /*!< [1] Transfer Complete */ - uint32_t BGE : 1; /*!< [2] Block Gap Event */ - uint32_t DINT : 1; /*!< [3] DMA Interrupt */ - uint32_t BWR : 1; /*!< [4] Buffer Write Ready */ - uint32_t BRR : 1; /*!< [5] Buffer Read Ready */ - uint32_t CINS : 1; /*!< [6] Card Insertion */ - uint32_t CRM : 1; /*!< [7] Card Removal */ - uint32_t CINT : 1; /*!< [8] Card Interrupt */ - uint32_t RESERVED0 : 7; /*!< [15:9] */ - uint32_t CTOE : 1; /*!< [16] Command Timeout Error */ - uint32_t CCE : 1; /*!< [17] Command CRC Error */ - uint32_t CEBE : 1; /*!< [18] Command End Bit Error */ - uint32_t CIE : 1; /*!< [19] Command Index Error */ - uint32_t DTOE : 1; /*!< [20] Data Timeout Error */ - uint32_t DCE : 1; /*!< [21] Data CRC Error */ - uint32_t DEBE : 1; /*!< [22] Data End Bit Error */ - uint32_t RESERVED1 : 1; /*!< [23] */ - uint32_t AC12E : 1; /*!< [24] Auto CMD12 Error */ - uint32_t RESERVED2 : 3; /*!< [27:25] */ - uint32_t DMAE : 1; /*!< [28] DMA Error */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_sdhc_irqstat_t; - -/*! - * @name Constants and macros for entire SDHC_IRQSTAT register - */ -/*@{*/ -#define HW_SDHC_IRQSTAT_ADDR(x) ((x) + 0x30U) - -#define HW_SDHC_IRQSTAT(x) (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR(x)) -#define HW_SDHC_IRQSTAT_RD(x) (HW_SDHC_IRQSTAT(x).U) -#define HW_SDHC_IRQSTAT_WR(x, v) (HW_SDHC_IRQSTAT(x).U = (v)) -#define HW_SDHC_IRQSTAT_SET(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) | (v))) -#define HW_SDHC_IRQSTAT_CLR(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) & ~(v))) -#define HW_SDHC_IRQSTAT_TOG(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_IRQSTAT bitfields - */ - -/*! - * @name Register SDHC_IRQSTAT, field CC[0] (W1C) - * - * This bit is set when you receive the end bit of the command response, except - * Auto CMD12. See PRSSTAT[CIHB]. - * - * Values: - * - 0 - Command not complete. - * - 1 - Command complete. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CC (0U) /*!< Bit position for SDHC_IRQSTAT_CC. */ -#define BM_SDHC_IRQSTAT_CC (0x00000001U) /*!< Bit mask for SDHC_IRQSTAT_CC. */ -#define BS_SDHC_IRQSTAT_CC (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CC. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */ -#define BR_SDHC_IRQSTAT_CC(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CC. */ -#define BF_SDHC_IRQSTAT_CC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CC) & BM_SDHC_IRQSTAT_CC) - -/*! @brief Set the CC field to a new value. */ -#define BW_SDHC_IRQSTAT_CC(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field TC[1] (W1C) - * - * This bit is set when a read or write transfer is completed. In the case of a - * read transaction: This bit is set at the falling edge of the read transfer - * active status. There are two cases in which this interrupt is generated. The - * first is when a data transfer is completed as specified by the data length, after - * the last data has been read to the host system. The second is when data has - * stopped at the block gap and completed the data transfer by setting - * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write - * transaction: This bit is set at the falling edge of the DAT line active - * status. There are two cases in which this interrupt is generated. The first is when - * the last data is written to the SD card as specified by the data length and - * the busy signal is released. The second is when data transfers are stopped at - * the block gap, by setting PROCTL[SABGREQ], and the data transfers are - * completed,after valid data is written to the SD card and the busy signal released. - * - * Values: - * - 0 - Transfer not complete. - * - 1 - Transfer complete. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_TC (1U) /*!< Bit position for SDHC_IRQSTAT_TC. */ -#define BM_SDHC_IRQSTAT_TC (0x00000002U) /*!< Bit mask for SDHC_IRQSTAT_TC. */ -#define BS_SDHC_IRQSTAT_TC (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_TC. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */ -#define BR_SDHC_IRQSTAT_TC(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_TC. */ -#define BF_SDHC_IRQSTAT_TC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_TC) & BM_SDHC_IRQSTAT_TC) - -/*! @brief Set the TC field to a new value. */ -#define BW_SDHC_IRQSTAT_TC(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field BGE[2] (W1C) - * - * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction - * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not - * set to 1. In the case of a read transaction: This bit is set at the falling - * edge of the DAT line active status, when the transaction is stopped at SD Bus - * timing. The read wait must be supported in order to use this function. In the - * case of write transaction: This bit is set at the falling edge of write transfer - * active status, after getting CRC status at SD bus timing. - * - * Values: - * - 0 - No block gap event. - * - 1 - Transaction stopped at block gap. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_BGE (2U) /*!< Bit position for SDHC_IRQSTAT_BGE. */ -#define BM_SDHC_IRQSTAT_BGE (0x00000004U) /*!< Bit mask for SDHC_IRQSTAT_BGE. */ -#define BS_SDHC_IRQSTAT_BGE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_BGE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */ -#define BR_SDHC_IRQSTAT_BGE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_BGE. */ -#define BF_SDHC_IRQSTAT_BGE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BGE) & BM_SDHC_IRQSTAT_BGE) - -/*! @brief Set the BGE field to a new value. */ -#define BW_SDHC_IRQSTAT_BGE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field DINT[3] (W1C) - * - * Occurs only when the internal DMA finishes the data transfer successfully. - * Whenever errors occur during data transfer, this bit will not be set. Instead, - * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring, - * this bit will be set. - * - * Values: - * - 0 - No DMA Interrupt. - * - 1 - DMA Interrupt is generated. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_DINT (3U) /*!< Bit position for SDHC_IRQSTAT_DINT. */ -#define BM_SDHC_IRQSTAT_DINT (0x00000008U) /*!< Bit mask for SDHC_IRQSTAT_DINT. */ -#define BS_SDHC_IRQSTAT_DINT (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_DINT. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */ -#define BR_SDHC_IRQSTAT_DINT(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_DINT. */ -#define BF_SDHC_IRQSTAT_DINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DINT) & BM_SDHC_IRQSTAT_DINT) - -/*! @brief Set the DINT field to a new value. */ -#define BW_SDHC_IRQSTAT_DINT(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field BWR[4] (W1C) - * - * This status bit is set if the Buffer Write Enable bit, in the Present State - * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present - * State register for additional information. - * - * Values: - * - 0 - Not ready to write buffer. - * - 1 - Ready to write buffer. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_BWR (4U) /*!< Bit position for SDHC_IRQSTAT_BWR. */ -#define BM_SDHC_IRQSTAT_BWR (0x00000010U) /*!< Bit mask for SDHC_IRQSTAT_BWR. */ -#define BS_SDHC_IRQSTAT_BWR (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_BWR. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */ -#define BR_SDHC_IRQSTAT_BWR(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_BWR. */ -#define BF_SDHC_IRQSTAT_BWR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BWR) & BM_SDHC_IRQSTAT_BWR) - -/*! @brief Set the BWR field to a new value. */ -#define BW_SDHC_IRQSTAT_BWR(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field BRR[5] (W1C) - * - * This status bit is set if the Buffer Read Enable bit, in the Present State - * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present - * State register for additional information. - * - * Values: - * - 0 - Not ready to read buffer. - * - 1 - Ready to read buffer. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_BRR (5U) /*!< Bit position for SDHC_IRQSTAT_BRR. */ -#define BM_SDHC_IRQSTAT_BRR (0x00000020U) /*!< Bit mask for SDHC_IRQSTAT_BRR. */ -#define BS_SDHC_IRQSTAT_BRR (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_BRR. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */ -#define BR_SDHC_IRQSTAT_BRR(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_BRR. */ -#define BF_SDHC_IRQSTAT_BRR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BRR) & BM_SDHC_IRQSTAT_BRR) - -/*! @brief Set the BRR field to a new value. */ -#define BW_SDHC_IRQSTAT_BRR(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CINS[6] (W1C) - * - * This status bit is set if the Card Inserted bit in the Present State register - * changes from 0 to 1. When the host driver writes this bit to 1 to clear this - * status, the status of the Card Inserted in the Present State register must be - * confirmed. Because the card state may possibly be changed when the host driver - * clears this bit and the interrupt event may not be generated. When this bit - * is cleared, it will be set again if a card is inserted. To leave it cleared, - * clear the Card Inserted Status Enable bit in Interrupt Status Enable register. - * - * Values: - * - 0 - Card state unstable or removed. - * - 1 - Card inserted. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CINS (6U) /*!< Bit position for SDHC_IRQSTAT_CINS. */ -#define BM_SDHC_IRQSTAT_CINS (0x00000040U) /*!< Bit mask for SDHC_IRQSTAT_CINS. */ -#define BS_SDHC_IRQSTAT_CINS (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CINS. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */ -#define BR_SDHC_IRQSTAT_CINS(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CINS. */ -#define BF_SDHC_IRQSTAT_CINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINS) & BM_SDHC_IRQSTAT_CINS) - -/*! @brief Set the CINS field to a new value. */ -#define BW_SDHC_IRQSTAT_CINS(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CRM[7] (W1C) - * - * This status bit is set if the Card Inserted bit in the Present State register - * changes from 1 to 0. When the host driver writes this bit to 1 to clear this - * status, the status of the Card Inserted in the Present State register must be - * confirmed. Because the card state may possibly be changed when the host driver - * clears this bit and the interrupt event may not be generated. When this bit - * is cleared, it will be set again if no card is inserted. To leave it cleared, - * clear the Card Removal Status Enable bit in Interrupt Status Enable register. - * - * Values: - * - 0 - Card state unstable or inserted. - * - 1 - Card removed. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CRM (7U) /*!< Bit position for SDHC_IRQSTAT_CRM. */ -#define BM_SDHC_IRQSTAT_CRM (0x00000080U) /*!< Bit mask for SDHC_IRQSTAT_CRM. */ -#define BS_SDHC_IRQSTAT_CRM (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CRM. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */ -#define BR_SDHC_IRQSTAT_CRM(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CRM. */ -#define BF_SDHC_IRQSTAT_CRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CRM) & BM_SDHC_IRQSTAT_CRM) - -/*! @brief Set the CRM field to a new value. */ -#define BW_SDHC_IRQSTAT_CRM(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CINT[8] (W1C) - * - * This status bit is set when an interrupt signal is detected from the external - * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD - * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled - * during the interrupt cycle, so the interrupt from card can only be sampled - * during interrupt cycle, introducing some delay between the interrupt signal from - * the SDIO card and the interrupt to the host system. Writing this bit to 1 can - * clear this bit, but as the interrupt factor from the SDIO card does not clear, - * this bit is set again. To clear this bit, it is required to reset the interrupt - * factor from the external card followed by a writing 1 to this bit. When this - * status has been set, and the host driver needs to service this interrupt, the - * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be - * 0 to stop driving the interrupt signal to the host system. After completion - * of the card interrupt service (it must reset the interrupt factors in the SDIO - * card and the interrupt signal may not be asserted), write 1 to clear this bit, - * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt - * signal again. - * - * Values: - * - 0 - No Card Interrupt. - * - 1 - Generate Card Interrupt. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CINT (8U) /*!< Bit position for SDHC_IRQSTAT_CINT. */ -#define BM_SDHC_IRQSTAT_CINT (0x00000100U) /*!< Bit mask for SDHC_IRQSTAT_CINT. */ -#define BS_SDHC_IRQSTAT_CINT (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CINT. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */ -#define BR_SDHC_IRQSTAT_CINT(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CINT. */ -#define BF_SDHC_IRQSTAT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINT) & BM_SDHC_IRQSTAT_CINT) - -/*! @brief Set the CINT field to a new value. */ -#define BW_SDHC_IRQSTAT_CINT(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C) - * - * Occurs only if no response is returned within 64 SDCLK cycles from the end - * bit of the command. If the SDHC detects a CMD line conflict, in which case a - * Command CRC Error shall also be set, this bit shall be set without waiting for 64 - * SDCLK cycles. This is because the command will be aborted by the SDHC. - * - * Values: - * - 0 - No error. - * - 1 - Time out. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CTOE (16U) /*!< Bit position for SDHC_IRQSTAT_CTOE. */ -#define BM_SDHC_IRQSTAT_CTOE (0x00010000U) /*!< Bit mask for SDHC_IRQSTAT_CTOE. */ -#define BS_SDHC_IRQSTAT_CTOE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CTOE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */ -#define BR_SDHC_IRQSTAT_CTOE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CTOE. */ -#define BF_SDHC_IRQSTAT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CTOE) & BM_SDHC_IRQSTAT_CTOE) - -/*! @brief Set the CTOE field to a new value. */ -#define BW_SDHC_IRQSTAT_CTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CCE[17] (W1C) - * - * Command CRC Error is generated in two cases. If a response is returned and - * the Command Timeout Error is set to 0, indicating no time-out, this bit is set - * when detecting a CRC error in the command response. The SDHC detects a CMD line - * conflict by monitoring the CMD line when a command is issued. If the SDHC - * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge, - * then the SDHC shall abort the command (Stop driving CMD line) and set this bit - * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line - * conflict. - * - * Values: - * - 0 - No error. - * - 1 - CRC Error generated. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CCE (17U) /*!< Bit position for SDHC_IRQSTAT_CCE. */ -#define BM_SDHC_IRQSTAT_CCE (0x00020000U) /*!< Bit mask for SDHC_IRQSTAT_CCE. */ -#define BS_SDHC_IRQSTAT_CCE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CCE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */ -#define BR_SDHC_IRQSTAT_CCE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CCE. */ -#define BF_SDHC_IRQSTAT_CCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CCE) & BM_SDHC_IRQSTAT_CCE) - -/*! @brief Set the CCE field to a new value. */ -#define BW_SDHC_IRQSTAT_CCE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C) - * - * Occurs when detecting that the end bit of a command response is 0. - * - * Values: - * - 0 - No error. - * - 1 - End Bit Error generated. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CEBE (18U) /*!< Bit position for SDHC_IRQSTAT_CEBE. */ -#define BM_SDHC_IRQSTAT_CEBE (0x00040000U) /*!< Bit mask for SDHC_IRQSTAT_CEBE. */ -#define BS_SDHC_IRQSTAT_CEBE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CEBE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */ -#define BR_SDHC_IRQSTAT_CEBE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CEBE. */ -#define BF_SDHC_IRQSTAT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CEBE) & BM_SDHC_IRQSTAT_CEBE) - -/*! @brief Set the CEBE field to a new value. */ -#define BW_SDHC_IRQSTAT_CEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field CIE[19] (W1C) - * - * Occurs if a Command Index error occurs in the command response. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_CIE (19U) /*!< Bit position for SDHC_IRQSTAT_CIE. */ -#define BM_SDHC_IRQSTAT_CIE (0x00080000U) /*!< Bit mask for SDHC_IRQSTAT_CIE. */ -#define BS_SDHC_IRQSTAT_CIE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_CIE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */ -#define BR_SDHC_IRQSTAT_CIE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_CIE. */ -#define BF_SDHC_IRQSTAT_CIE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CIE) & BM_SDHC_IRQSTAT_CIE) - -/*! @brief Set the CIE field to a new value. */ -#define BW_SDHC_IRQSTAT_CIE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C) - * - * Occurs when detecting one of following time-out conditions. Busy time-out for - * R1b,R5b type Busy time-out after Write CRC status Read Data time-out - * - * Values: - * - 0 - No error. - * - 1 - Time out. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_DTOE (20U) /*!< Bit position for SDHC_IRQSTAT_DTOE. */ -#define BM_SDHC_IRQSTAT_DTOE (0x00100000U) /*!< Bit mask for SDHC_IRQSTAT_DTOE. */ -#define BS_SDHC_IRQSTAT_DTOE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_DTOE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */ -#define BR_SDHC_IRQSTAT_DTOE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_DTOE. */ -#define BF_SDHC_IRQSTAT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DTOE) & BM_SDHC_IRQSTAT_DTOE) - -/*! @brief Set the DTOE field to a new value. */ -#define BW_SDHC_IRQSTAT_DTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field DCE[21] (W1C) - * - * Occurs when detecting a CRC error when transferring read data, which uses the - * DAT line, or when detecting the Write CRC status having a value other than - * 010. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_DCE (21U) /*!< Bit position for SDHC_IRQSTAT_DCE. */ -#define BM_SDHC_IRQSTAT_DCE (0x00200000U) /*!< Bit mask for SDHC_IRQSTAT_DCE. */ -#define BS_SDHC_IRQSTAT_DCE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_DCE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */ -#define BR_SDHC_IRQSTAT_DCE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_DCE. */ -#define BF_SDHC_IRQSTAT_DCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DCE) & BM_SDHC_IRQSTAT_DCE) - -/*! @brief Set the DCE field to a new value. */ -#define BW_SDHC_IRQSTAT_DCE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C) - * - * Occurs either when detecting 0 at the end bit position of read data, which - * uses the DAT line, or at the end bit position of the CRC. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_DEBE (22U) /*!< Bit position for SDHC_IRQSTAT_DEBE. */ -#define BM_SDHC_IRQSTAT_DEBE (0x00400000U) /*!< Bit mask for SDHC_IRQSTAT_DEBE. */ -#define BS_SDHC_IRQSTAT_DEBE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_DEBE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */ -#define BR_SDHC_IRQSTAT_DEBE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_DEBE. */ -#define BF_SDHC_IRQSTAT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DEBE) & BM_SDHC_IRQSTAT_DEBE) - -/*! @brief Set the DEBE field to a new value. */ -#define BW_SDHC_IRQSTAT_DEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C) - * - * Occurs when detecting that one of the bits in the Auto CMD12 Error Status - * register has changed from 0 to 1. This bit is set to 1, not only when the errors - * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the - * previous command error. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_AC12E (24U) /*!< Bit position for SDHC_IRQSTAT_AC12E. */ -#define BM_SDHC_IRQSTAT_AC12E (0x01000000U) /*!< Bit mask for SDHC_IRQSTAT_AC12E. */ -#define BS_SDHC_IRQSTAT_AC12E (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_AC12E. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */ -#define BR_SDHC_IRQSTAT_AC12E(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_AC12E. */ -#define BF_SDHC_IRQSTAT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_AC12E) & BM_SDHC_IRQSTAT_AC12E) - -/*! @brief Set the AC12E field to a new value. */ -#define BW_SDHC_IRQSTAT_AC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C) - * - * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when - * some error occurs in the data transfer. This error can be caused by either - * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System - * Address register is the next fetch address where the error occurs. Because any - * error corrupts the whole data block, the host driver shall restart the transfer - * from the corrupted block boundary. The address of the block boundary can be - * calculated either from the current DSADDR value or from the remaining number of - * blocks and the block size. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_IRQSTAT_DMAE (28U) /*!< Bit position for SDHC_IRQSTAT_DMAE. */ -#define BM_SDHC_IRQSTAT_DMAE (0x10000000U) /*!< Bit mask for SDHC_IRQSTAT_DMAE. */ -#define BS_SDHC_IRQSTAT_DMAE (1U) /*!< Bit field size in bits for SDHC_IRQSTAT_DMAE. */ - -/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */ -#define BR_SDHC_IRQSTAT_DMAE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE)) - -/*! @brief Format value for bitfield SDHC_IRQSTAT_DMAE. */ -#define BF_SDHC_IRQSTAT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DMAE) & BM_SDHC_IRQSTAT_DMAE) - -/*! @brief Set the DMAE field to a new value. */ -#define BW_SDHC_IRQSTAT_DMAE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_IRQSTATEN - Interrupt Status Enable register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW) - * - * Reset value: 0x117F013FU - * - * Setting the bits in this register to 1 enables the corresponding interrupt - * status to be set by the specified event. If any bit is cleared, the - * corresponding interrupt status bit is also cleared, that is, when the bit in this register - * is cleared, the corresponding bit in interrupt status register is always 0. - * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the - * card interrupt signal during the interrupt period and hold its value in the - * flip-flop. There will be some delays on the card interrupt, asserted from the card, - * to the time the host system is informed. To detect a CMD line conflict, the - * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1. - */ -typedef union _hw_sdhc_irqstaten -{ - uint32_t U; - struct _hw_sdhc_irqstaten_bitfields - { - uint32_t CCSEN : 1; /*!< [0] Command Complete Status Enable */ - uint32_t TCSEN : 1; /*!< [1] Transfer Complete Status Enable */ - uint32_t BGESEN : 1; /*!< [2] Block Gap Event Status Enable */ - uint32_t DINTSEN : 1; /*!< [3] DMA Interrupt Status Enable */ - uint32_t BWRSEN : 1; /*!< [4] Buffer Write Ready Status Enable */ - uint32_t BRRSEN : 1; /*!< [5] Buffer Read Ready Status Enable */ - uint32_t CINSEN : 1; /*!< [6] Card Insertion Status Enable */ - uint32_t CRMSEN : 1; /*!< [7] Card Removal Status Enable */ - uint32_t CINTSEN : 1; /*!< [8] Card Interrupt Status Enable */ - uint32_t RESERVED0 : 7; /*!< [15:9] */ - uint32_t CTOESEN : 1; /*!< [16] Command Timeout Error Status Enable */ - uint32_t CCESEN : 1; /*!< [17] Command CRC Error Status Enable */ - uint32_t CEBESEN : 1; /*!< [18] Command End Bit Error Status Enable */ - uint32_t CIESEN : 1; /*!< [19] Command Index Error Status Enable */ - uint32_t DTOESEN : 1; /*!< [20] Data Timeout Error Status Enable */ - uint32_t DCESEN : 1; /*!< [21] Data CRC Error Status Enable */ - uint32_t DEBESEN : 1; /*!< [22] Data End Bit Error Status Enable */ - uint32_t RESERVED1 : 1; /*!< [23] */ - uint32_t AC12ESEN : 1; /*!< [24] Auto CMD12 Error Status Enable */ - uint32_t RESERVED2 : 3; /*!< [27:25] */ - uint32_t DMAESEN : 1; /*!< [28] DMA Error Status Enable */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_sdhc_irqstaten_t; - -/*! - * @name Constants and macros for entire SDHC_IRQSTATEN register - */ -/*@{*/ -#define HW_SDHC_IRQSTATEN_ADDR(x) ((x) + 0x34U) - -#define HW_SDHC_IRQSTATEN(x) (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR(x)) -#define HW_SDHC_IRQSTATEN_RD(x) (HW_SDHC_IRQSTATEN(x).U) -#define HW_SDHC_IRQSTATEN_WR(x, v) (HW_SDHC_IRQSTATEN(x).U = (v)) -#define HW_SDHC_IRQSTATEN_SET(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) | (v))) -#define HW_SDHC_IRQSTATEN_CLR(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) & ~(v))) -#define HW_SDHC_IRQSTATEN_TOG(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_IRQSTATEN bitfields - */ - -/*! - * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CCSEN (0U) /*!< Bit position for SDHC_IRQSTATEN_CCSEN. */ -#define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) /*!< Bit mask for SDHC_IRQSTATEN_CCSEN. */ -#define BS_SDHC_IRQSTATEN_CCSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */ -#define BR_SDHC_IRQSTATEN_CCSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN. */ -#define BF_SDHC_IRQSTATEN_CCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCSEN) & BM_SDHC_IRQSTATEN_CCSEN) - -/*! @brief Set the CCSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CCSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_TCSEN (1U) /*!< Bit position for SDHC_IRQSTATEN_TCSEN. */ -#define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) /*!< Bit mask for SDHC_IRQSTATEN_TCSEN. */ -#define BS_SDHC_IRQSTATEN_TCSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */ -#define BR_SDHC_IRQSTATEN_TCSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN. */ -#define BF_SDHC_IRQSTATEN_TCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_TCSEN) & BM_SDHC_IRQSTATEN_TCSEN) - -/*! @brief Set the TCSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_TCSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_BGESEN (2U) /*!< Bit position for SDHC_IRQSTATEN_BGESEN. */ -#define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) /*!< Bit mask for SDHC_IRQSTATEN_BGESEN. */ -#define BS_SDHC_IRQSTATEN_BGESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */ -#define BR_SDHC_IRQSTATEN_BGESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN. */ -#define BF_SDHC_IRQSTATEN_BGESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BGESEN) & BM_SDHC_IRQSTATEN_BGESEN) - -/*! @brief Set the BGESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_BGESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_DINTSEN (3U) /*!< Bit position for SDHC_IRQSTATEN_DINTSEN. */ -#define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) /*!< Bit mask for SDHC_IRQSTATEN_DINTSEN. */ -#define BS_SDHC_IRQSTATEN_DINTSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */ -#define BR_SDHC_IRQSTATEN_DINTSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN. */ -#define BF_SDHC_IRQSTATEN_DINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DINTSEN) & BM_SDHC_IRQSTATEN_DINTSEN) - -/*! @brief Set the DINTSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_DINTSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_BWRSEN (4U) /*!< Bit position for SDHC_IRQSTATEN_BWRSEN. */ -#define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) /*!< Bit mask for SDHC_IRQSTATEN_BWRSEN. */ -#define BS_SDHC_IRQSTATEN_BWRSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */ -#define BR_SDHC_IRQSTATEN_BWRSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN. */ -#define BF_SDHC_IRQSTATEN_BWRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BWRSEN) & BM_SDHC_IRQSTATEN_BWRSEN) - -/*! @brief Set the BWRSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_BWRSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_BRRSEN (5U) /*!< Bit position for SDHC_IRQSTATEN_BRRSEN. */ -#define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) /*!< Bit mask for SDHC_IRQSTATEN_BRRSEN. */ -#define BS_SDHC_IRQSTATEN_BRRSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */ -#define BR_SDHC_IRQSTATEN_BRRSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN. */ -#define BF_SDHC_IRQSTATEN_BRRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BRRSEN) & BM_SDHC_IRQSTATEN_BRRSEN) - -/*! @brief Set the BRRSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_BRRSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CINSEN (6U) /*!< Bit position for SDHC_IRQSTATEN_CINSEN. */ -#define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) /*!< Bit mask for SDHC_IRQSTATEN_CINSEN. */ -#define BS_SDHC_IRQSTATEN_CINSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */ -#define BR_SDHC_IRQSTATEN_CINSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN. */ -#define BF_SDHC_IRQSTATEN_CINSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINSEN) & BM_SDHC_IRQSTATEN_CINSEN) - -/*! @brief Set the CINSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CINSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CRMSEN (7U) /*!< Bit position for SDHC_IRQSTATEN_CRMSEN. */ -#define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) /*!< Bit mask for SDHC_IRQSTATEN_CRMSEN. */ -#define BS_SDHC_IRQSTATEN_CRMSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */ -#define BR_SDHC_IRQSTATEN_CRMSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN. */ -#define BF_SDHC_IRQSTATEN_CRMSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CRMSEN) & BM_SDHC_IRQSTATEN_CRMSEN) - -/*! @brief Set the CRMSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CRMSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW) - * - * If this bit is set to 0, the SDHC will clear the interrupt request to the - * system. The card interrupt detection is stopped when this bit is cleared and - * restarted when this bit is set to 1. The host driver must clear the this bit - * before servicing the card interrupt and must set this bit again after all interrupt - * requests from the card are cleared to prevent inadvertent interrupts. - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CINTSEN (8U) /*!< Bit position for SDHC_IRQSTATEN_CINTSEN. */ -#define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) /*!< Bit mask for SDHC_IRQSTATEN_CINTSEN. */ -#define BS_SDHC_IRQSTATEN_CINTSEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */ -#define BR_SDHC_IRQSTATEN_CINTSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN. */ -#define BF_SDHC_IRQSTATEN_CINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINTSEN) & BM_SDHC_IRQSTATEN_CINTSEN) - -/*! @brief Set the CINTSEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CINTSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CTOESEN (16U) /*!< Bit position for SDHC_IRQSTATEN_CTOESEN. */ -#define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) /*!< Bit mask for SDHC_IRQSTATEN_CTOESEN. */ -#define BS_SDHC_IRQSTATEN_CTOESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */ -#define BR_SDHC_IRQSTATEN_CTOESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN. */ -#define BF_SDHC_IRQSTATEN_CTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CTOESEN) & BM_SDHC_IRQSTATEN_CTOESEN) - -/*! @brief Set the CTOESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CTOESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CCESEN (17U) /*!< Bit position for SDHC_IRQSTATEN_CCESEN. */ -#define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) /*!< Bit mask for SDHC_IRQSTATEN_CCESEN. */ -#define BS_SDHC_IRQSTATEN_CCESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */ -#define BR_SDHC_IRQSTATEN_CCESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN. */ -#define BF_SDHC_IRQSTATEN_CCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCESEN) & BM_SDHC_IRQSTATEN_CCESEN) - -/*! @brief Set the CCESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CCESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CEBESEN (18U) /*!< Bit position for SDHC_IRQSTATEN_CEBESEN. */ -#define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) /*!< Bit mask for SDHC_IRQSTATEN_CEBESEN. */ -#define BS_SDHC_IRQSTATEN_CEBESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */ -#define BR_SDHC_IRQSTATEN_CEBESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN. */ -#define BF_SDHC_IRQSTATEN_CEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CEBESEN) & BM_SDHC_IRQSTATEN_CEBESEN) - -/*! @brief Set the CEBESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CEBESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_CIESEN (19U) /*!< Bit position for SDHC_IRQSTATEN_CIESEN. */ -#define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) /*!< Bit mask for SDHC_IRQSTATEN_CIESEN. */ -#define BS_SDHC_IRQSTATEN_CIESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */ -#define BR_SDHC_IRQSTATEN_CIESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN. */ -#define BF_SDHC_IRQSTATEN_CIESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CIESEN) & BM_SDHC_IRQSTATEN_CIESEN) - -/*! @brief Set the CIESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_CIESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_DTOESEN (20U) /*!< Bit position for SDHC_IRQSTATEN_DTOESEN. */ -#define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) /*!< Bit mask for SDHC_IRQSTATEN_DTOESEN. */ -#define BS_SDHC_IRQSTATEN_DTOESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */ -#define BR_SDHC_IRQSTATEN_DTOESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN. */ -#define BF_SDHC_IRQSTATEN_DTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DTOESEN) & BM_SDHC_IRQSTATEN_DTOESEN) - -/*! @brief Set the DTOESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_DTOESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_DCESEN (21U) /*!< Bit position for SDHC_IRQSTATEN_DCESEN. */ -#define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) /*!< Bit mask for SDHC_IRQSTATEN_DCESEN. */ -#define BS_SDHC_IRQSTATEN_DCESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */ -#define BR_SDHC_IRQSTATEN_DCESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN. */ -#define BF_SDHC_IRQSTATEN_DCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DCESEN) & BM_SDHC_IRQSTATEN_DCESEN) - -/*! @brief Set the DCESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_DCESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_DEBESEN (22U) /*!< Bit position for SDHC_IRQSTATEN_DEBESEN. */ -#define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) /*!< Bit mask for SDHC_IRQSTATEN_DEBESEN. */ -#define BS_SDHC_IRQSTATEN_DEBESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */ -#define BR_SDHC_IRQSTATEN_DEBESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN. */ -#define BF_SDHC_IRQSTATEN_DEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DEBESEN) & BM_SDHC_IRQSTATEN_DEBESEN) - -/*! @brief Set the DEBESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_DEBESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_AC12ESEN (24U) /*!< Bit position for SDHC_IRQSTATEN_AC12ESEN. */ -#define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) /*!< Bit mask for SDHC_IRQSTATEN_AC12ESEN. */ -#define BS_SDHC_IRQSTATEN_AC12ESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */ -#define BR_SDHC_IRQSTATEN_AC12ESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN. */ -#define BF_SDHC_IRQSTATEN_AC12ESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_AC12ESEN) & BM_SDHC_IRQSTATEN_AC12ESEN) - -/*! @brief Set the AC12ESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_AC12ESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSTATEN_DMAESEN (28U) /*!< Bit position for SDHC_IRQSTATEN_DMAESEN. */ -#define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) /*!< Bit mask for SDHC_IRQSTATEN_DMAESEN. */ -#define BS_SDHC_IRQSTATEN_DMAESEN (1U) /*!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN. */ - -/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */ -#define BR_SDHC_IRQSTATEN_DMAESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN)) - -/*! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN. */ -#define BF_SDHC_IRQSTATEN_DMAESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DMAESEN) & BM_SDHC_IRQSTATEN_DMAESEN) - -/*! @brief Set the DMAESEN field to a new value. */ -#define BW_SDHC_IRQSTATEN_DMAESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_IRQSIGEN - Interrupt Signal Enable register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW) - * - * Reset value: 0x00000000U - * - * This register is used to select which interrupt status is indicated to the - * host system as the interrupt. All of these status bits share the same interrupt - * line. Setting any of these bits to 1 enables interrupt generation. The - * corresponding status register bit will generate an interrupt when the corresponding - * interrupt signal enable bit is set. - */ -typedef union _hw_sdhc_irqsigen -{ - uint32_t U; - struct _hw_sdhc_irqsigen_bitfields - { - uint32_t CCIEN : 1; /*!< [0] Command Complete Interrupt Enable */ - uint32_t TCIEN : 1; /*!< [1] Transfer Complete Interrupt Enable */ - uint32_t BGEIEN : 1; /*!< [2] Block Gap Event Interrupt Enable */ - uint32_t DINTIEN : 1; /*!< [3] DMA Interrupt Enable */ - uint32_t BWRIEN : 1; /*!< [4] Buffer Write Ready Interrupt Enable */ - uint32_t BRRIEN : 1; /*!< [5] Buffer Read Ready Interrupt Enable */ - uint32_t CINSIEN : 1; /*!< [6] Card Insertion Interrupt Enable */ - uint32_t CRMIEN : 1; /*!< [7] Card Removal Interrupt Enable */ - uint32_t CINTIEN : 1; /*!< [8] Card Interrupt Enable */ - uint32_t RESERVED0 : 7; /*!< [15:9] */ - uint32_t CTOEIEN : 1; /*!< [16] Command Timeout Error Interrupt - * Enable */ - uint32_t CCEIEN : 1; /*!< [17] Command CRC Error Interrupt Enable */ - uint32_t CEBEIEN : 1; /*!< [18] Command End Bit Error Interrupt - * Enable */ - uint32_t CIEIEN : 1; /*!< [19] Command Index Error Interrupt Enable */ - uint32_t DTOEIEN : 1; /*!< [20] Data Timeout Error Interrupt Enable */ - uint32_t DCEIEN : 1; /*!< [21] Data CRC Error Interrupt Enable */ - uint32_t DEBEIEN : 1; /*!< [22] Data End Bit Error Interrupt Enable */ - uint32_t RESERVED1 : 1; /*!< [23] */ - uint32_t AC12EIEN : 1; /*!< [24] Auto CMD12 Error Interrupt Enable */ - uint32_t RESERVED2 : 3; /*!< [27:25] */ - uint32_t DMAEIEN : 1; /*!< [28] DMA Error Interrupt Enable */ - uint32_t RESERVED3 : 3; /*!< [31:29] */ - } B; -} hw_sdhc_irqsigen_t; - -/*! - * @name Constants and macros for entire SDHC_IRQSIGEN register - */ -/*@{*/ -#define HW_SDHC_IRQSIGEN_ADDR(x) ((x) + 0x38U) - -#define HW_SDHC_IRQSIGEN(x) (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR(x)) -#define HW_SDHC_IRQSIGEN_RD(x) (HW_SDHC_IRQSIGEN(x).U) -#define HW_SDHC_IRQSIGEN_WR(x, v) (HW_SDHC_IRQSIGEN(x).U = (v)) -#define HW_SDHC_IRQSIGEN_SET(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) | (v))) -#define HW_SDHC_IRQSIGEN_CLR(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) & ~(v))) -#define HW_SDHC_IRQSIGEN_TOG(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_IRQSIGEN bitfields - */ - -/*! - * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CCIEN (0U) /*!< Bit position for SDHC_IRQSIGEN_CCIEN. */ -#define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) /*!< Bit mask for SDHC_IRQSIGEN_CCIEN. */ -#define BS_SDHC_IRQSIGEN_CCIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */ -#define BR_SDHC_IRQSIGEN_CCIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN. */ -#define BF_SDHC_IRQSIGEN_CCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCIEN) & BM_SDHC_IRQSIGEN_CCIEN) - -/*! @brief Set the CCIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CCIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_TCIEN (1U) /*!< Bit position for SDHC_IRQSIGEN_TCIEN. */ -#define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) /*!< Bit mask for SDHC_IRQSIGEN_TCIEN. */ -#define BS_SDHC_IRQSIGEN_TCIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */ -#define BR_SDHC_IRQSIGEN_TCIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN. */ -#define BF_SDHC_IRQSIGEN_TCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_TCIEN) & BM_SDHC_IRQSIGEN_TCIEN) - -/*! @brief Set the TCIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_TCIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_BGEIEN (2U) /*!< Bit position for SDHC_IRQSIGEN_BGEIEN. */ -#define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) /*!< Bit mask for SDHC_IRQSIGEN_BGEIEN. */ -#define BS_SDHC_IRQSIGEN_BGEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */ -#define BR_SDHC_IRQSIGEN_BGEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN. */ -#define BF_SDHC_IRQSIGEN_BGEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BGEIEN) & BM_SDHC_IRQSIGEN_BGEIEN) - -/*! @brief Set the BGEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_BGEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_DINTIEN (3U) /*!< Bit position for SDHC_IRQSIGEN_DINTIEN. */ -#define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) /*!< Bit mask for SDHC_IRQSIGEN_DINTIEN. */ -#define BS_SDHC_IRQSIGEN_DINTIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */ -#define BR_SDHC_IRQSIGEN_DINTIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN. */ -#define BF_SDHC_IRQSIGEN_DINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DINTIEN) & BM_SDHC_IRQSIGEN_DINTIEN) - -/*! @brief Set the DINTIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_DINTIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_BWRIEN (4U) /*!< Bit position for SDHC_IRQSIGEN_BWRIEN. */ -#define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) /*!< Bit mask for SDHC_IRQSIGEN_BWRIEN. */ -#define BS_SDHC_IRQSIGEN_BWRIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */ -#define BR_SDHC_IRQSIGEN_BWRIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN. */ -#define BF_SDHC_IRQSIGEN_BWRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BWRIEN) & BM_SDHC_IRQSIGEN_BWRIEN) - -/*! @brief Set the BWRIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_BWRIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_BRRIEN (5U) /*!< Bit position for SDHC_IRQSIGEN_BRRIEN. */ -#define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) /*!< Bit mask for SDHC_IRQSIGEN_BRRIEN. */ -#define BS_SDHC_IRQSIGEN_BRRIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */ -#define BR_SDHC_IRQSIGEN_BRRIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN. */ -#define BF_SDHC_IRQSIGEN_BRRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BRRIEN) & BM_SDHC_IRQSIGEN_BRRIEN) - -/*! @brief Set the BRRIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_BRRIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CINSIEN (6U) /*!< Bit position for SDHC_IRQSIGEN_CINSIEN. */ -#define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) /*!< Bit mask for SDHC_IRQSIGEN_CINSIEN. */ -#define BS_SDHC_IRQSIGEN_CINSIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */ -#define BR_SDHC_IRQSIGEN_CINSIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN. */ -#define BF_SDHC_IRQSIGEN_CINSIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINSIEN) & BM_SDHC_IRQSIGEN_CINSIEN) - -/*! @brief Set the CINSIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CINSIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CRMIEN (7U) /*!< Bit position for SDHC_IRQSIGEN_CRMIEN. */ -#define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) /*!< Bit mask for SDHC_IRQSIGEN_CRMIEN. */ -#define BS_SDHC_IRQSIGEN_CRMIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */ -#define BR_SDHC_IRQSIGEN_CRMIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN. */ -#define BF_SDHC_IRQSIGEN_CRMIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CRMIEN) & BM_SDHC_IRQSIGEN_CRMIEN) - -/*! @brief Set the CRMIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CRMIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CINTIEN (8U) /*!< Bit position for SDHC_IRQSIGEN_CINTIEN. */ -#define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) /*!< Bit mask for SDHC_IRQSIGEN_CINTIEN. */ -#define BS_SDHC_IRQSIGEN_CINTIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */ -#define BR_SDHC_IRQSIGEN_CINTIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN. */ -#define BF_SDHC_IRQSIGEN_CINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINTIEN) & BM_SDHC_IRQSIGEN_CINTIEN) - -/*! @brief Set the CINTIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CINTIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CTOEIEN (16U) /*!< Bit position for SDHC_IRQSIGEN_CTOEIEN. */ -#define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) /*!< Bit mask for SDHC_IRQSIGEN_CTOEIEN. */ -#define BS_SDHC_IRQSIGEN_CTOEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */ -#define BR_SDHC_IRQSIGEN_CTOEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN. */ -#define BF_SDHC_IRQSIGEN_CTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CTOEIEN) & BM_SDHC_IRQSIGEN_CTOEIEN) - -/*! @brief Set the CTOEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CTOEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CCEIEN (17U) /*!< Bit position for SDHC_IRQSIGEN_CCEIEN. */ -#define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) /*!< Bit mask for SDHC_IRQSIGEN_CCEIEN. */ -#define BS_SDHC_IRQSIGEN_CCEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */ -#define BR_SDHC_IRQSIGEN_CCEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN. */ -#define BF_SDHC_IRQSIGEN_CCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCEIEN) & BM_SDHC_IRQSIGEN_CCEIEN) - -/*! @brief Set the CCEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CCEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CEBEIEN (18U) /*!< Bit position for SDHC_IRQSIGEN_CEBEIEN. */ -#define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) /*!< Bit mask for SDHC_IRQSIGEN_CEBEIEN. */ -#define BS_SDHC_IRQSIGEN_CEBEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */ -#define BR_SDHC_IRQSIGEN_CEBEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN. */ -#define BF_SDHC_IRQSIGEN_CEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CEBEIEN) & BM_SDHC_IRQSIGEN_CEBEIEN) - -/*! @brief Set the CEBEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CEBEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_CIEIEN (19U) /*!< Bit position for SDHC_IRQSIGEN_CIEIEN. */ -#define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) /*!< Bit mask for SDHC_IRQSIGEN_CIEIEN. */ -#define BS_SDHC_IRQSIGEN_CIEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */ -#define BR_SDHC_IRQSIGEN_CIEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN. */ -#define BF_SDHC_IRQSIGEN_CIEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CIEIEN) & BM_SDHC_IRQSIGEN_CIEIEN) - -/*! @brief Set the CIEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_CIEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_DTOEIEN (20U) /*!< Bit position for SDHC_IRQSIGEN_DTOEIEN. */ -#define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) /*!< Bit mask for SDHC_IRQSIGEN_DTOEIEN. */ -#define BS_SDHC_IRQSIGEN_DTOEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */ -#define BR_SDHC_IRQSIGEN_DTOEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN. */ -#define BF_SDHC_IRQSIGEN_DTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DTOEIEN) & BM_SDHC_IRQSIGEN_DTOEIEN) - -/*! @brief Set the DTOEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_DTOEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_DCEIEN (21U) /*!< Bit position for SDHC_IRQSIGEN_DCEIEN. */ -#define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) /*!< Bit mask for SDHC_IRQSIGEN_DCEIEN. */ -#define BS_SDHC_IRQSIGEN_DCEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */ -#define BR_SDHC_IRQSIGEN_DCEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN. */ -#define BF_SDHC_IRQSIGEN_DCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DCEIEN) & BM_SDHC_IRQSIGEN_DCEIEN) - -/*! @brief Set the DCEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_DCEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_DEBEIEN (22U) /*!< Bit position for SDHC_IRQSIGEN_DEBEIEN. */ -#define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) /*!< Bit mask for SDHC_IRQSIGEN_DEBEIEN. */ -#define BS_SDHC_IRQSIGEN_DEBEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */ -#define BR_SDHC_IRQSIGEN_DEBEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN. */ -#define BF_SDHC_IRQSIGEN_DEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DEBEIEN) & BM_SDHC_IRQSIGEN_DEBEIEN) - -/*! @brief Set the DEBEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_DEBEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_AC12EIEN (24U) /*!< Bit position for SDHC_IRQSIGEN_AC12EIEN. */ -#define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) /*!< Bit mask for SDHC_IRQSIGEN_AC12EIEN. */ -#define BS_SDHC_IRQSIGEN_AC12EIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */ -#define BR_SDHC_IRQSIGEN_AC12EIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN. */ -#define BF_SDHC_IRQSIGEN_AC12EIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_AC12EIEN) & BM_SDHC_IRQSIGEN_AC12EIEN) - -/*! @brief Set the AC12EIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_AC12EIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW) - * - * Values: - * - 0 - Masked - * - 1 - Enabled - */ -/*@{*/ -#define BP_SDHC_IRQSIGEN_DMAEIEN (28U) /*!< Bit position for SDHC_IRQSIGEN_DMAEIEN. */ -#define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) /*!< Bit mask for SDHC_IRQSIGEN_DMAEIEN. */ -#define BS_SDHC_IRQSIGEN_DMAEIEN (1U) /*!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN. */ - -/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */ -#define BR_SDHC_IRQSIGEN_DMAEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN)) - -/*! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN. */ -#define BF_SDHC_IRQSIGEN_DMAEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DMAEIEN) & BM_SDHC_IRQSIGEN_DMAEIEN) - -/*! @brief Set the DMAEIEN field to a new value. */ -#define BW_SDHC_IRQSIGEN_DMAEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_AC12ERR - Auto CMD12 Error Status Register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO) - * - * Reset value: 0x00000000U - * - * When the AC12ESEN bit in the Status register is set, the host driver shall - * check this register to identify what kind of error the Auto CMD12 indicated. - * This register is valid only when the Auto CMD12 Error status bit is set. The - * following table shows the relationship between the Auto CMGD12 CRC error and the - * Auto CMD12 command timeout error. Relationship between Command CRC Error and - * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout - * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC - * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be - * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set - * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous - * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto - * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4 - * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors. - * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a - * command that can't be issued. Clear bit 7 if there is no command to issue. The - * timing for generating the auto CMD12 error and writing to the command register - * are asynchronous. After that, bit 7 shall be sampled when the driver is not - * writing to the command register. So it is suggested to read this register only - * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one - * of the error bits (0-4) is set to 1. The command not issued by auto CMD12 - * error does not generate an interrupt. - */ -typedef union _hw_sdhc_ac12err -{ - uint32_t U; - struct _hw_sdhc_ac12err_bitfields - { - uint32_t AC12NE : 1; /*!< [0] Auto CMD12 Not Executed */ - uint32_t AC12TOE : 1; /*!< [1] Auto CMD12 Timeout Error */ - uint32_t AC12EBE : 1; /*!< [2] Auto CMD12 End Bit Error */ - uint32_t AC12CE : 1; /*!< [3] Auto CMD12 CRC Error */ - uint32_t AC12IE : 1; /*!< [4] Auto CMD12 Index Error */ - uint32_t RESERVED0 : 2; /*!< [6:5] */ - uint32_t CNIBAC12E : 1; /*!< [7] Command Not Issued By Auto CMD12 - * Error */ - uint32_t RESERVED1 : 24; /*!< [31:8] */ - } B; -} hw_sdhc_ac12err_t; - -/*! - * @name Constants and macros for entire SDHC_AC12ERR register - */ -/*@{*/ -#define HW_SDHC_AC12ERR_ADDR(x) ((x) + 0x3CU) - -#define HW_SDHC_AC12ERR(x) (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR(x)) -#define HW_SDHC_AC12ERR_RD(x) (HW_SDHC_AC12ERR(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_AC12ERR bitfields - */ - -/*! - * @name Register SDHC_AC12ERR, field AC12NE[0] (RO) - * - * If memory multiple block data transfer is not started, due to a command - * error, this bit is not set because it is not necessary to issue an auto CMD12. - * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory - * multiple block data transfer due to some error. If this bit is set to 1, other - * error status bits (1-4) have no meaning. - * - * Values: - * - 0 - Executed. - * - 1 - Not executed. - */ -/*@{*/ -#define BP_SDHC_AC12ERR_AC12NE (0U) /*!< Bit position for SDHC_AC12ERR_AC12NE. */ -#define BM_SDHC_AC12ERR_AC12NE (0x00000001U) /*!< Bit mask for SDHC_AC12ERR_AC12NE. */ -#define BS_SDHC_AC12ERR_AC12NE (1U) /*!< Bit field size in bits for SDHC_AC12ERR_AC12NE. */ - -/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */ -#define BR_SDHC_AC12ERR_AC12NE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12NE)) -/*@}*/ - -/*! - * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO) - * - * Occurs if no response is returned within 64 SDCLK cycles from the end bit of - * the command. If this bit is set to 1, the other error status bits (2-4) have - * no meaning. - * - * Values: - * - 0 - No error. - * - 1 - Time out. - */ -/*@{*/ -#define BP_SDHC_AC12ERR_AC12TOE (1U) /*!< Bit position for SDHC_AC12ERR_AC12TOE. */ -#define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) /*!< Bit mask for SDHC_AC12ERR_AC12TOE. */ -#define BS_SDHC_AC12ERR_AC12TOE (1U) /*!< Bit field size in bits for SDHC_AC12ERR_AC12TOE. */ - -/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */ -#define BR_SDHC_AC12ERR_AC12TOE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12TOE)) -/*@}*/ - -/*! - * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO) - * - * Occurs when detecting that the end bit of command response is 0 which must be - * 1. - * - * Values: - * - 0 - No error. - * - 1 - End bit error generated. - */ -/*@{*/ -#define BP_SDHC_AC12ERR_AC12EBE (2U) /*!< Bit position for SDHC_AC12ERR_AC12EBE. */ -#define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) /*!< Bit mask for SDHC_AC12ERR_AC12EBE. */ -#define BS_SDHC_AC12ERR_AC12EBE (1U) /*!< Bit field size in bits for SDHC_AC12ERR_AC12EBE. */ - -/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */ -#define BR_SDHC_AC12ERR_AC12EBE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12EBE)) -/*@}*/ - -/*! - * @name Register SDHC_AC12ERR, field AC12CE[3] (RO) - * - * Occurs when detecting a CRC error in the command response. - * - * Values: - * - 0 - No CRC error. - * - 1 - CRC error met in Auto CMD12 response. - */ -/*@{*/ -#define BP_SDHC_AC12ERR_AC12CE (3U) /*!< Bit position for SDHC_AC12ERR_AC12CE. */ -#define BM_SDHC_AC12ERR_AC12CE (0x00000008U) /*!< Bit mask for SDHC_AC12ERR_AC12CE. */ -#define BS_SDHC_AC12ERR_AC12CE (1U) /*!< Bit field size in bits for SDHC_AC12ERR_AC12CE. */ - -/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */ -#define BR_SDHC_AC12ERR_AC12CE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12CE)) -/*@}*/ - -/*! - * @name Register SDHC_AC12ERR, field AC12IE[4] (RO) - * - * Occurs if the command index error occurs in response to a command. - * - * Values: - * - 0 - No error. - * - 1 - Error, the CMD index in response is not CMD12. - */ -/*@{*/ -#define BP_SDHC_AC12ERR_AC12IE (4U) /*!< Bit position for SDHC_AC12ERR_AC12IE. */ -#define BM_SDHC_AC12ERR_AC12IE (0x00000010U) /*!< Bit mask for SDHC_AC12ERR_AC12IE. */ -#define BS_SDHC_AC12ERR_AC12IE (1U) /*!< Bit field size in bits for SDHC_AC12ERR_AC12IE. */ - -/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */ -#define BR_SDHC_AC12ERR_AC12IE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12IE)) -/*@}*/ - -/*! - * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO) - * - * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12 - * error (D04-D01) in this register. - * - * Values: - * - 0 - No error. - * - 1 - Not issued. - */ -/*@{*/ -#define BP_SDHC_AC12ERR_CNIBAC12E (7U) /*!< Bit position for SDHC_AC12ERR_CNIBAC12E. */ -#define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) /*!< Bit mask for SDHC_AC12ERR_CNIBAC12E. */ -#define BS_SDHC_AC12ERR_CNIBAC12E (1U) /*!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E. */ - -/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */ -#define BR_SDHC_AC12ERR_CNIBAC12E(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_CNIBAC12E)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_HTCAPBLT - Host Controller Capabilities - ******************************************************************************/ - -/*! - * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO) - * - * Reset value: 0x07F30000U - * - * This register provides the host driver with information specific to the SDHC - * implementation. The value in this register is the power-on-reset value, and - * does not change with a software reset. Any write to this register is ignored. - */ -typedef union _hw_sdhc_htcapblt -{ - uint32_t U; - struct _hw_sdhc_htcapblt_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t MBL : 3; /*!< [18:16] Max Block Length */ - uint32_t RESERVED1 : 1; /*!< [19] */ - uint32_t ADMAS : 1; /*!< [20] ADMA Support */ - uint32_t HSS : 1; /*!< [21] High Speed Support */ - uint32_t DMAS : 1; /*!< [22] DMA Support */ - uint32_t SRS : 1; /*!< [23] Suspend/Resume Support */ - uint32_t VS33 : 1; /*!< [24] Voltage Support 3.3 V */ - uint32_t RESERVED2 : 7; /*!< [31:25] */ - } B; -} hw_sdhc_htcapblt_t; - -/*! - * @name Constants and macros for entire SDHC_HTCAPBLT register - */ -/*@{*/ -#define HW_SDHC_HTCAPBLT_ADDR(x) ((x) + 0x40U) - -#define HW_SDHC_HTCAPBLT(x) (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR(x)) -#define HW_SDHC_HTCAPBLT_RD(x) (HW_SDHC_HTCAPBLT(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_HTCAPBLT bitfields - */ - -/*! - * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO) - * - * This value indicates the maximum block size that the host driver can read and - * write to the buffer in the SDHC. The buffer shall transfer block size without - * wait cycles. - * - * Values: - * - 000 - 512 bytes - * - 001 - 1024 bytes - * - 010 - 2048 bytes - * - 011 - 4096 bytes - */ -/*@{*/ -#define BP_SDHC_HTCAPBLT_MBL (16U) /*!< Bit position for SDHC_HTCAPBLT_MBL. */ -#define BM_SDHC_HTCAPBLT_MBL (0x00070000U) /*!< Bit mask for SDHC_HTCAPBLT_MBL. */ -#define BS_SDHC_HTCAPBLT_MBL (3U) /*!< Bit field size in bits for SDHC_HTCAPBLT_MBL. */ - -/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */ -#define BR_SDHC_HTCAPBLT_MBL(x) (HW_SDHC_HTCAPBLT(x).B.MBL) -/*@}*/ - -/*! - * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO) - * - * This bit indicates whether the SDHC supports the ADMA feature. - * - * Values: - * - 0 - Advanced DMA not supported. - * - 1 - Advanced DMA supported. - */ -/*@{*/ -#define BP_SDHC_HTCAPBLT_ADMAS (20U) /*!< Bit position for SDHC_HTCAPBLT_ADMAS. */ -#define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) /*!< Bit mask for SDHC_HTCAPBLT_ADMAS. */ -#define BS_SDHC_HTCAPBLT_ADMAS (1U) /*!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS. */ - -/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */ -#define BR_SDHC_HTCAPBLT_ADMAS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_ADMAS)) -/*@}*/ - -/*! - * @name Register SDHC_HTCAPBLT, field HSS[21] (RO) - * - * This bit indicates whether the SDHC supports high speed mode and the host - * system can supply a SD Clock frequency from 25 MHz to 50 MHz. - * - * Values: - * - 0 - High speed not supported. - * - 1 - High speed supported. - */ -/*@{*/ -#define BP_SDHC_HTCAPBLT_HSS (21U) /*!< Bit position for SDHC_HTCAPBLT_HSS. */ -#define BM_SDHC_HTCAPBLT_HSS (0x00200000U) /*!< Bit mask for SDHC_HTCAPBLT_HSS. */ -#define BS_SDHC_HTCAPBLT_HSS (1U) /*!< Bit field size in bits for SDHC_HTCAPBLT_HSS. */ - -/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */ -#define BR_SDHC_HTCAPBLT_HSS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_HSS)) -/*@}*/ - -/*! - * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO) - * - * This bit indicates whether the SDHC is capable of using the internal DMA to - * transfer data between system memory and the data buffer directly. - * - * Values: - * - 0 - DMA not supported. - * - 1 - DMA supported. - */ -/*@{*/ -#define BP_SDHC_HTCAPBLT_DMAS (22U) /*!< Bit position for SDHC_HTCAPBLT_DMAS. */ -#define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) /*!< Bit mask for SDHC_HTCAPBLT_DMAS. */ -#define BS_SDHC_HTCAPBLT_DMAS (1U) /*!< Bit field size in bits for SDHC_HTCAPBLT_DMAS. */ - -/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */ -#define BR_SDHC_HTCAPBLT_DMAS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_DMAS)) -/*@}*/ - -/*! - * @name Register SDHC_HTCAPBLT, field SRS[23] (RO) - * - * This bit indicates whether the SDHC supports suspend / resume functionality. - * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait, - * are not supported, and the host driver shall not issue either suspend or - * resume commands. - * - * Values: - * - 0 - Not supported. - * - 1 - Supported. - */ -/*@{*/ -#define BP_SDHC_HTCAPBLT_SRS (23U) /*!< Bit position for SDHC_HTCAPBLT_SRS. */ -#define BM_SDHC_HTCAPBLT_SRS (0x00800000U) /*!< Bit mask for SDHC_HTCAPBLT_SRS. */ -#define BS_SDHC_HTCAPBLT_SRS (1U) /*!< Bit field size in bits for SDHC_HTCAPBLT_SRS. */ - -/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */ -#define BR_SDHC_HTCAPBLT_SRS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_SRS)) -/*@}*/ - -/*! - * @name Register SDHC_HTCAPBLT, field VS33[24] (RO) - * - * This bit shall depend on the host system ability. - * - * Values: - * - 0 - 3.3 V not supported. - * - 1 - 3.3 V supported. - */ -/*@{*/ -#define BP_SDHC_HTCAPBLT_VS33 (24U) /*!< Bit position for SDHC_HTCAPBLT_VS33. */ -#define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) /*!< Bit mask for SDHC_HTCAPBLT_VS33. */ -#define BS_SDHC_HTCAPBLT_VS33 (1U) /*!< Bit field size in bits for SDHC_HTCAPBLT_VS33. */ - -/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */ -#define BR_SDHC_HTCAPBLT_VS33(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_VS33)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_WML - Watermark Level Register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_WML - Watermark Level Register (RW) - * - * Reset value: 0x00100010U - * - * Both write and read watermark levels (FIFO threshold) are configurable. There - * value can range from 1 to 128 words. Both write and read burst lengths are - * also configurable. There value can range from 1 to 31 words. - */ -typedef union _hw_sdhc_wml -{ - uint32_t U; - struct _hw_sdhc_wml_bitfields - { - uint32_t RDWML : 8; /*!< [7:0] Read Watermark Level */ - uint32_t RESERVED0 : 8; /*!< [15:8] */ - uint32_t WRWML : 8; /*!< [23:16] Write Watermark Level */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ - } B; -} hw_sdhc_wml_t; - -/*! - * @name Constants and macros for entire SDHC_WML register - */ -/*@{*/ -#define HW_SDHC_WML_ADDR(x) ((x) + 0x44U) - -#define HW_SDHC_WML(x) (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR(x)) -#define HW_SDHC_WML_RD(x) (HW_SDHC_WML(x).U) -#define HW_SDHC_WML_WR(x, v) (HW_SDHC_WML(x).U = (v)) -#define HW_SDHC_WML_SET(x, v) (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) | (v))) -#define HW_SDHC_WML_CLR(x, v) (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) & ~(v))) -#define HW_SDHC_WML_TOG(x, v) (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_WML bitfields - */ - -/*! - * @name Register SDHC_WML, field RDWML[7:0] (RW) - * - * The number of words used as the watermark level (FIFO threshold) in a DMA - * read operation. Also the number of words as a sequence of read bursts in - * back-to-back mode. The maximum legal value for the read water mark level is 128. - */ -/*@{*/ -#define BP_SDHC_WML_RDWML (0U) /*!< Bit position for SDHC_WML_RDWML. */ -#define BM_SDHC_WML_RDWML (0x000000FFU) /*!< Bit mask for SDHC_WML_RDWML. */ -#define BS_SDHC_WML_RDWML (8U) /*!< Bit field size in bits for SDHC_WML_RDWML. */ - -/*! @brief Read current value of the SDHC_WML_RDWML field. */ -#define BR_SDHC_WML_RDWML(x) (HW_SDHC_WML(x).B.RDWML) - -/*! @brief Format value for bitfield SDHC_WML_RDWML. */ -#define BF_SDHC_WML_RDWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_RDWML) & BM_SDHC_WML_RDWML) - -/*! @brief Set the RDWML field to a new value. */ -#define BW_SDHC_WML_RDWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v))) -/*@}*/ - -/*! - * @name Register SDHC_WML, field WRWML[23:16] (RW) - * - * The number of words used as the watermark level (FIFO threshold) in a DMA - * write operation. Also the number of words as a sequence of write bursts in - * back-to-back mode. The maximum legal value for the write watermark level is 128. - */ -/*@{*/ -#define BP_SDHC_WML_WRWML (16U) /*!< Bit position for SDHC_WML_WRWML. */ -#define BM_SDHC_WML_WRWML (0x00FF0000U) /*!< Bit mask for SDHC_WML_WRWML. */ -#define BS_SDHC_WML_WRWML (8U) /*!< Bit field size in bits for SDHC_WML_WRWML. */ - -/*! @brief Read current value of the SDHC_WML_WRWML field. */ -#define BR_SDHC_WML_WRWML(x) (HW_SDHC_WML(x).B.WRWML) - -/*! @brief Format value for bitfield SDHC_WML_WRWML. */ -#define BF_SDHC_WML_WRWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_WRWML) & BM_SDHC_WML_WRWML) - -/*! @brief Set the WRWML field to a new value. */ -#define BW_SDHC_WML_WRWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v))) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_FEVT - Force Event register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_FEVT - Force Event register (WO) - * - * Reset value: 0x00000000U - * - * The Force Event (FEVT) register is not a physically implemented register. - * Rather, it is an address at which the Interrupt Status register can be written if - * the corresponding bit of the Interrupt Status Enable register is set. This - * register is a write only register and writing 0 to it has no effect. Writing 1 - * to this register actually sets the corresponding bit of Interrupt Status - * register. A read from this register always results in 0's. To change the - * corresponding status bits in the interrupt status register, make sure to set - * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a - * short pulse on the DAT[1] line, and the driver may treat this interrupt as a - * normal interrupt. The interrupt service routine may skip polling the card - * interrupt factor as the interrupt is selfcleared. - */ -typedef union _hw_sdhc_fevt -{ - uint32_t U; - struct _hw_sdhc_fevt_bitfields - { - uint32_t AC12NE : 1; /*!< [0] Force Event Auto Command 12 Not - * Executed */ - uint32_t AC12TOE : 1; /*!< [1] Force Event Auto Command 12 Time Out - * Error */ - uint32_t AC12CE : 1; /*!< [2] Force Event Auto Command 12 CRC Error */ - uint32_t AC12EBE : 1; /*!< [3] Force Event Auto Command 12 End Bit - * Error */ - uint32_t AC12IE : 1; /*!< [4] Force Event Auto Command 12 Index Error - * */ - uint32_t RESERVED0 : 2; /*!< [6:5] */ - uint32_t CNIBAC12E : 1; /*!< [7] Force Event Command Not Executed By - * Auto Command 12 Error */ - uint32_t RESERVED1 : 8; /*!< [15:8] */ - uint32_t CTOE : 1; /*!< [16] Force Event Command Time Out Error */ - uint32_t CCE : 1; /*!< [17] Force Event Command CRC Error */ - uint32_t CEBE : 1; /*!< [18] Force Event Command End Bit Error */ - uint32_t CIE : 1; /*!< [19] Force Event Command Index Error */ - uint32_t DTOE : 1; /*!< [20] Force Event Data Time Out Error */ - uint32_t DCE : 1; /*!< [21] Force Event Data CRC Error */ - uint32_t DEBE : 1; /*!< [22] Force Event Data End Bit Error */ - uint32_t RESERVED2 : 1; /*!< [23] */ - uint32_t AC12E : 1; /*!< [24] Force Event Auto Command 12 Error */ - uint32_t RESERVED3 : 3; /*!< [27:25] */ - uint32_t DMAE : 1; /*!< [28] Force Event DMA Error */ - uint32_t RESERVED4 : 2; /*!< [30:29] */ - uint32_t CINT : 1; /*!< [31] Force Event Card Interrupt */ - } B; -} hw_sdhc_fevt_t; - -/*! - * @name Constants and macros for entire SDHC_FEVT register - */ -/*@{*/ -#define HW_SDHC_FEVT_ADDR(x) ((x) + 0x50U) - -#define HW_SDHC_FEVT(x) (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR(x)) -#define HW_SDHC_FEVT_RD(x) (HW_SDHC_FEVT(x).U) -#define HW_SDHC_FEVT_WR(x, v) (HW_SDHC_FEVT(x).U = (v)) -/*@}*/ - -/* - * Constants & macros for individual SDHC_FEVT bitfields - */ - -/*! - * @name Register SDHC_FEVT, field AC12NE[0] (WORZ) - * - * Forces AC12ERR[AC12NE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_AC12NE (0U) /*!< Bit position for SDHC_FEVT_AC12NE. */ -#define BM_SDHC_FEVT_AC12NE (0x00000001U) /*!< Bit mask for SDHC_FEVT_AC12NE. */ -#define BS_SDHC_FEVT_AC12NE (1U) /*!< Bit field size in bits for SDHC_FEVT_AC12NE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_AC12NE. */ -#define BF_SDHC_FEVT_AC12NE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12NE) & BM_SDHC_FEVT_AC12NE) - -/*! @brief Set the AC12NE field to a new value. */ -#define BW_SDHC_FEVT_AC12NE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12NE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ) - * - * Forces AC12ERR[AC12TOE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_AC12TOE (1U) /*!< Bit position for SDHC_FEVT_AC12TOE. */ -#define BM_SDHC_FEVT_AC12TOE (0x00000002U) /*!< Bit mask for SDHC_FEVT_AC12TOE. */ -#define BS_SDHC_FEVT_AC12TOE (1U) /*!< Bit field size in bits for SDHC_FEVT_AC12TOE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_AC12TOE. */ -#define BF_SDHC_FEVT_AC12TOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12TOE) & BM_SDHC_FEVT_AC12TOE) - -/*! @brief Set the AC12TOE field to a new value. */ -#define BW_SDHC_FEVT_AC12TOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12TOE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field AC12CE[2] (WORZ) - * - * Forces AC12ERR[AC12CE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_AC12CE (2U) /*!< Bit position for SDHC_FEVT_AC12CE. */ -#define BM_SDHC_FEVT_AC12CE (0x00000004U) /*!< Bit mask for SDHC_FEVT_AC12CE. */ -#define BS_SDHC_FEVT_AC12CE (1U) /*!< Bit field size in bits for SDHC_FEVT_AC12CE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_AC12CE. */ -#define BF_SDHC_FEVT_AC12CE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12CE) & BM_SDHC_FEVT_AC12CE) - -/*! @brief Set the AC12CE field to a new value. */ -#define BW_SDHC_FEVT_AC12CE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12CE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ) - * - * Forces AC12ERR[AC12EBE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_AC12EBE (3U) /*!< Bit position for SDHC_FEVT_AC12EBE. */ -#define BM_SDHC_FEVT_AC12EBE (0x00000008U) /*!< Bit mask for SDHC_FEVT_AC12EBE. */ -#define BS_SDHC_FEVT_AC12EBE (1U) /*!< Bit field size in bits for SDHC_FEVT_AC12EBE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_AC12EBE. */ -#define BF_SDHC_FEVT_AC12EBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12EBE) & BM_SDHC_FEVT_AC12EBE) - -/*! @brief Set the AC12EBE field to a new value. */ -#define BW_SDHC_FEVT_AC12EBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12EBE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field AC12IE[4] (WORZ) - * - * Forces AC12ERR[AC12IE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_AC12IE (4U) /*!< Bit position for SDHC_FEVT_AC12IE. */ -#define BM_SDHC_FEVT_AC12IE (0x00000010U) /*!< Bit mask for SDHC_FEVT_AC12IE. */ -#define BS_SDHC_FEVT_AC12IE (1U) /*!< Bit field size in bits for SDHC_FEVT_AC12IE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_AC12IE. */ -#define BF_SDHC_FEVT_AC12IE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12IE) & BM_SDHC_FEVT_AC12IE) - -/*! @brief Set the AC12IE field to a new value. */ -#define BW_SDHC_FEVT_AC12IE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12IE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ) - * - * Forces AC12ERR[CNIBAC12E] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_CNIBAC12E (7U) /*!< Bit position for SDHC_FEVT_CNIBAC12E. */ -#define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) /*!< Bit mask for SDHC_FEVT_CNIBAC12E. */ -#define BS_SDHC_FEVT_CNIBAC12E (1U) /*!< Bit field size in bits for SDHC_FEVT_CNIBAC12E. */ - -/*! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E. */ -#define BF_SDHC_FEVT_CNIBAC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CNIBAC12E) & BM_SDHC_FEVT_CNIBAC12E) - -/*! @brief Set the CNIBAC12E field to a new value. */ -#define BW_SDHC_FEVT_CNIBAC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CNIBAC12E) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field CTOE[16] (WORZ) - * - * Forces IRQSTAT[CTOE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_CTOE (16U) /*!< Bit position for SDHC_FEVT_CTOE. */ -#define BM_SDHC_FEVT_CTOE (0x00010000U) /*!< Bit mask for SDHC_FEVT_CTOE. */ -#define BS_SDHC_FEVT_CTOE (1U) /*!< Bit field size in bits for SDHC_FEVT_CTOE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_CTOE. */ -#define BF_SDHC_FEVT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CTOE) & BM_SDHC_FEVT_CTOE) - -/*! @brief Set the CTOE field to a new value. */ -#define BW_SDHC_FEVT_CTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CTOE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field CCE[17] (WORZ) - * - * Forces IRQSTAT[CCE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_CCE (17U) /*!< Bit position for SDHC_FEVT_CCE. */ -#define BM_SDHC_FEVT_CCE (0x00020000U) /*!< Bit mask for SDHC_FEVT_CCE. */ -#define BS_SDHC_FEVT_CCE (1U) /*!< Bit field size in bits for SDHC_FEVT_CCE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_CCE. */ -#define BF_SDHC_FEVT_CCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CCE) & BM_SDHC_FEVT_CCE) - -/*! @brief Set the CCE field to a new value. */ -#define BW_SDHC_FEVT_CCE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CCE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field CEBE[18] (WORZ) - * - * Forces IRQSTAT[CEBE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_CEBE (18U) /*!< Bit position for SDHC_FEVT_CEBE. */ -#define BM_SDHC_FEVT_CEBE (0x00040000U) /*!< Bit mask for SDHC_FEVT_CEBE. */ -#define BS_SDHC_FEVT_CEBE (1U) /*!< Bit field size in bits for SDHC_FEVT_CEBE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_CEBE. */ -#define BF_SDHC_FEVT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CEBE) & BM_SDHC_FEVT_CEBE) - -/*! @brief Set the CEBE field to a new value. */ -#define BW_SDHC_FEVT_CEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CEBE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field CIE[19] (WORZ) - * - * Forces IRQSTAT[CCE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_CIE (19U) /*!< Bit position for SDHC_FEVT_CIE. */ -#define BM_SDHC_FEVT_CIE (0x00080000U) /*!< Bit mask for SDHC_FEVT_CIE. */ -#define BS_SDHC_FEVT_CIE (1U) /*!< Bit field size in bits for SDHC_FEVT_CIE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_CIE. */ -#define BF_SDHC_FEVT_CIE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CIE) & BM_SDHC_FEVT_CIE) - -/*! @brief Set the CIE field to a new value. */ -#define BW_SDHC_FEVT_CIE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CIE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field DTOE[20] (WORZ) - * - * Forces IRQSTAT[DTOE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_DTOE (20U) /*!< Bit position for SDHC_FEVT_DTOE. */ -#define BM_SDHC_FEVT_DTOE (0x00100000U) /*!< Bit mask for SDHC_FEVT_DTOE. */ -#define BS_SDHC_FEVT_DTOE (1U) /*!< Bit field size in bits for SDHC_FEVT_DTOE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_DTOE. */ -#define BF_SDHC_FEVT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DTOE) & BM_SDHC_FEVT_DTOE) - -/*! @brief Set the DTOE field to a new value. */ -#define BW_SDHC_FEVT_DTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DTOE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field DCE[21] (WORZ) - * - * Forces IRQSTAT[DCE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_DCE (21U) /*!< Bit position for SDHC_FEVT_DCE. */ -#define BM_SDHC_FEVT_DCE (0x00200000U) /*!< Bit mask for SDHC_FEVT_DCE. */ -#define BS_SDHC_FEVT_DCE (1U) /*!< Bit field size in bits for SDHC_FEVT_DCE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_DCE. */ -#define BF_SDHC_FEVT_DCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DCE) & BM_SDHC_FEVT_DCE) - -/*! @brief Set the DCE field to a new value. */ -#define BW_SDHC_FEVT_DCE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DCE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field DEBE[22] (WORZ) - * - * Forces IRQSTAT[DEBE] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_DEBE (22U) /*!< Bit position for SDHC_FEVT_DEBE. */ -#define BM_SDHC_FEVT_DEBE (0x00400000U) /*!< Bit mask for SDHC_FEVT_DEBE. */ -#define BS_SDHC_FEVT_DEBE (1U) /*!< Bit field size in bits for SDHC_FEVT_DEBE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_DEBE. */ -#define BF_SDHC_FEVT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DEBE) & BM_SDHC_FEVT_DEBE) - -/*! @brief Set the DEBE field to a new value. */ -#define BW_SDHC_FEVT_DEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DEBE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field AC12E[24] (WORZ) - * - * Forces IRQSTAT[AC12E] to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_AC12E (24U) /*!< Bit position for SDHC_FEVT_AC12E. */ -#define BM_SDHC_FEVT_AC12E (0x01000000U) /*!< Bit mask for SDHC_FEVT_AC12E. */ -#define BS_SDHC_FEVT_AC12E (1U) /*!< Bit field size in bits for SDHC_FEVT_AC12E. */ - -/*! @brief Format value for bitfield SDHC_FEVT_AC12E. */ -#define BF_SDHC_FEVT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12E) & BM_SDHC_FEVT_AC12E) - -/*! @brief Set the AC12E field to a new value. */ -#define BW_SDHC_FEVT_AC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12E) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field DMAE[28] (WORZ) - * - * Forces the DMAE bit of Interrupt Status Register to be set. - */ -/*@{*/ -#define BP_SDHC_FEVT_DMAE (28U) /*!< Bit position for SDHC_FEVT_DMAE. */ -#define BM_SDHC_FEVT_DMAE (0x10000000U) /*!< Bit mask for SDHC_FEVT_DMAE. */ -#define BS_SDHC_FEVT_DMAE (1U) /*!< Bit field size in bits for SDHC_FEVT_DMAE. */ - -/*! @brief Format value for bitfield SDHC_FEVT_DMAE. */ -#define BF_SDHC_FEVT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DMAE) & BM_SDHC_FEVT_DMAE) - -/*! @brief Set the DMAE field to a new value. */ -#define BW_SDHC_FEVT_DMAE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DMAE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_FEVT, field CINT[31] (WORZ) - * - * Writing 1 to this bit generates a short low-level pulse on the internal - * DAT[1] line, as if a self-clearing interrupt was received from the external card. - * If enabled, the CINT bit will be set and the interrupt service routine may - * treat this interrupt as a normal interrupt from the external card. - */ -/*@{*/ -#define BP_SDHC_FEVT_CINT (31U) /*!< Bit position for SDHC_FEVT_CINT. */ -#define BM_SDHC_FEVT_CINT (0x80000000U) /*!< Bit mask for SDHC_FEVT_CINT. */ -#define BS_SDHC_FEVT_CINT (1U) /*!< Bit field size in bits for SDHC_FEVT_CINT. */ - -/*! @brief Format value for bitfield SDHC_FEVT_CINT. */ -#define BF_SDHC_FEVT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CINT) & BM_SDHC_FEVT_CINT) - -/*! @brief Set the CINT field to a new value. */ -#define BW_SDHC_FEVT_CINT(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CINT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_ADMAES - ADMA Error Status register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO) - * - * Reset value: 0x00000000U - * - * When an ADMA error interrupt has occurred, the ADMA Error States field in - * this register holds the ADMA state and the ADMA System Address register holds the - * address around the error descriptor. For recovering from this error, the host - * driver requires the ADMA state to identify the error descriptor address as - * follows: ST_STOP: Previous location set in the ADMA System Address register is - * the error descriptor address. ST_FDS: Current location set in the ADMA System - * Address register is the error descriptor address. ST_CADR: This state is never - * set because it only increments the descriptor pointer and doesn't generate an - * ADMA error. ST_TFR: Previous location set in the ADMA System Address register - * is the error descriptor address. In case of a write operation, the host driver - * must use the ACMD22 to get the number of the written block, rather than using - * this information, because unwritten data may exist in the host controller. - * The host controller generates the ADMA error interrupt when it detects invalid - * descriptor data (valid = 0) in the ST_FDS state. The host driver can - * distinguish this error by reading the valid bit of the error descriptor. ADMA Error - * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA - * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next - * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid - * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR - * (Transfer Data) Holds the address of the next executable descriptor command - */ -typedef union _hw_sdhc_admaes -{ - uint32_t U; - struct _hw_sdhc_admaes_bitfields - { - uint32_t ADMAES : 2; /*!< [1:0] ADMA Error State (When ADMA Error Is - * Occurred.) */ - uint32_t ADMALME : 1; /*!< [2] ADMA Length Mismatch Error */ - uint32_t ADMADCE : 1; /*!< [3] ADMA Descriptor Error */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_sdhc_admaes_t; - -/*! - * @name Constants and macros for entire SDHC_ADMAES register - */ -/*@{*/ -#define HW_SDHC_ADMAES_ADDR(x) ((x) + 0x54U) - -#define HW_SDHC_ADMAES(x) (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR(x)) -#define HW_SDHC_ADMAES_RD(x) (HW_SDHC_ADMAES(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_ADMAES bitfields - */ - -/*! - * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO) - * - * Indicates the state of the ADMA when an error has occurred during an ADMA - * data transfer. - */ -/*@{*/ -#define BP_SDHC_ADMAES_ADMAES (0U) /*!< Bit position for SDHC_ADMAES_ADMAES. */ -#define BM_SDHC_ADMAES_ADMAES (0x00000003U) /*!< Bit mask for SDHC_ADMAES_ADMAES. */ -#define BS_SDHC_ADMAES_ADMAES (2U) /*!< Bit field size in bits for SDHC_ADMAES_ADMAES. */ - -/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */ -#define BR_SDHC_ADMAES_ADMAES(x) (HW_SDHC_ADMAES(x).B.ADMAES) -/*@}*/ - -/*! - * @name Register SDHC_ADMAES, field ADMALME[2] (RO) - * - * This error occurs in the following 2 cases: While the block count enable is - * being set, the total data length specified by the descriptor table is different - * from that specified by the block count and block length. Total data length - * can not be divided by the block length. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_ADMAES_ADMALME (2U) /*!< Bit position for SDHC_ADMAES_ADMALME. */ -#define BM_SDHC_ADMAES_ADMALME (0x00000004U) /*!< Bit mask for SDHC_ADMAES_ADMALME. */ -#define BS_SDHC_ADMAES_ADMALME (1U) /*!< Bit field size in bits for SDHC_ADMAES_ADMALME. */ - -/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */ -#define BR_SDHC_ADMAES_ADMALME(x) (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMALME)) -/*@}*/ - -/*! - * @name Register SDHC_ADMAES, field ADMADCE[3] (RO) - * - * This error occurs when an invalid descriptor is fetched by ADMA. - * - * Values: - * - 0 - No error. - * - 1 - Error. - */ -/*@{*/ -#define BP_SDHC_ADMAES_ADMADCE (3U) /*!< Bit position for SDHC_ADMAES_ADMADCE. */ -#define BM_SDHC_ADMAES_ADMADCE (0x00000008U) /*!< Bit mask for SDHC_ADMAES_ADMADCE. */ -#define BS_SDHC_ADMAES_ADMADCE (1U) /*!< Bit field size in bits for SDHC_ADMAES_ADMADCE. */ - -/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */ -#define BR_SDHC_ADMAES_ADMADCE(x) (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMADCE)) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_ADSADDR - ADMA System Addressregister - ******************************************************************************/ - -/*! - * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW) - * - * Reset value: 0x00000000U - * - * This register contains the physical system memory address used for ADMA - * transfers. - */ -typedef union _hw_sdhc_adsaddr -{ - uint32_t U; - struct _hw_sdhc_adsaddr_bitfields - { - uint32_t RESERVED0 : 2; /*!< [1:0] */ - uint32_t ADSADDR : 30; /*!< [31:2] ADMA System Address */ - } B; -} hw_sdhc_adsaddr_t; - -/*! - * @name Constants and macros for entire SDHC_ADSADDR register - */ -/*@{*/ -#define HW_SDHC_ADSADDR_ADDR(x) ((x) + 0x58U) - -#define HW_SDHC_ADSADDR(x) (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR(x)) -#define HW_SDHC_ADSADDR_RD(x) (HW_SDHC_ADSADDR(x).U) -#define HW_SDHC_ADSADDR_WR(x, v) (HW_SDHC_ADSADDR(x).U = (v)) -#define HW_SDHC_ADSADDR_SET(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) | (v))) -#define HW_SDHC_ADSADDR_CLR(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) & ~(v))) -#define HW_SDHC_ADSADDR_TOG(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_ADSADDR bitfields - */ - -/*! - * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW) - * - * Holds the word address of the executing command in the descriptor table. At - * the start of ADMA, the host driver shall set the start address of the - * Descriptor table. The ADMA engine increments this register address whenever fetching a - * descriptor command. When the ADMA is stopped at the block gap, this register - * indicates the address of the next executable descriptor command. When the ADMA - * error interrupt is generated, this register shall hold the valid descriptor - * address depending on the ADMA state. The lower 2 bits of this register is tied - * to '0' so the ADMA address is always word-aligned. Because this register - * supports dynamic address reflecting, when TC bit is set, it automatically alters the - * value of internal address counter, so SW cannot change this register when TC - * bit is set. - */ -/*@{*/ -#define BP_SDHC_ADSADDR_ADSADDR (2U) /*!< Bit position for SDHC_ADSADDR_ADSADDR. */ -#define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) /*!< Bit mask for SDHC_ADSADDR_ADSADDR. */ -#define BS_SDHC_ADSADDR_ADSADDR (30U) /*!< Bit field size in bits for SDHC_ADSADDR_ADSADDR. */ - -/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */ -#define BR_SDHC_ADSADDR_ADSADDR(x) (HW_SDHC_ADSADDR(x).B.ADSADDR) - -/*! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR. */ -#define BF_SDHC_ADSADDR_ADSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_ADSADDR_ADSADDR) & BM_SDHC_ADSADDR_ADSADDR) - -/*! @brief Set the ADSADDR field to a new value. */ -#define BW_SDHC_ADSADDR_ADSADDR(x, v) (HW_SDHC_ADSADDR_WR(x, (HW_SDHC_ADSADDR_RD(x) & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v))) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_VENDOR - Vendor Specific register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_VENDOR - Vendor Specific register (RW) - * - * Reset value: 0x00000001U - * - * This register contains the vendor-specific control/status register. - */ -typedef union _hw_sdhc_vendor -{ - uint32_t U; - struct _hw_sdhc_vendor_bitfields - { - uint32_t EXTDMAEN : 1; /*!< [0] External DMA Request Enable */ - uint32_t EXBLKNU : 1; /*!< [1] Exact Block Number Block Read Enable - * For SDIO CMD53 */ - uint32_t RESERVED0 : 14; /*!< [15:2] */ - uint32_t INTSTVAL : 8; /*!< [23:16] Internal State Value */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ - } B; -} hw_sdhc_vendor_t; - -/*! - * @name Constants and macros for entire SDHC_VENDOR register - */ -/*@{*/ -#define HW_SDHC_VENDOR_ADDR(x) ((x) + 0xC0U) - -#define HW_SDHC_VENDOR(x) (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR(x)) -#define HW_SDHC_VENDOR_RD(x) (HW_SDHC_VENDOR(x).U) -#define HW_SDHC_VENDOR_WR(x, v) (HW_SDHC_VENDOR(x).U = (v)) -#define HW_SDHC_VENDOR_SET(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) | (v))) -#define HW_SDHC_VENDOR_CLR(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) & ~(v))) -#define HW_SDHC_VENDOR_TOG(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_VENDOR bitfields - */ - -/*! - * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW) - * - * Enables the request to external DMA. When the internal DMA (either simple DMA - * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA - * request when the internal buffer is ready. This bit is particularly useful when - * transferring data by CPU polling mode, and it is not allowed to send out the - * external DMA request. By default, this bit is set. - * - * Values: - * - 0 - In any scenario, SDHC does not send out the external DMA request. - * - 1 - When internal DMA is not active, the external DMA request will be sent - * out. - */ -/*@{*/ -#define BP_SDHC_VENDOR_EXTDMAEN (0U) /*!< Bit position for SDHC_VENDOR_EXTDMAEN. */ -#define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) /*!< Bit mask for SDHC_VENDOR_EXTDMAEN. */ -#define BS_SDHC_VENDOR_EXTDMAEN (1U) /*!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN. */ - -/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */ -#define BR_SDHC_VENDOR_EXTDMAEN(x) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN)) - -/*! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN. */ -#define BF_SDHC_VENDOR_EXTDMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXTDMAEN) & BM_SDHC_VENDOR_EXTDMAEN) - -/*! @brief Set the EXTDMAEN field to a new value. */ -#define BW_SDHC_VENDOR_EXTDMAEN(x, v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW) - * - * This bit must be set before S/W issues CMD53 multi-block read with exact - * block number. This bit must not be set if the CMD53 multi-block read is not exact - * block number. - * - * Values: - * - 0 - None exact block read. - * - 1 - Exact block read for SDIO CMD53. - */ -/*@{*/ -#define BP_SDHC_VENDOR_EXBLKNU (1U) /*!< Bit position for SDHC_VENDOR_EXBLKNU. */ -#define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) /*!< Bit mask for SDHC_VENDOR_EXBLKNU. */ -#define BS_SDHC_VENDOR_EXBLKNU (1U) /*!< Bit field size in bits for SDHC_VENDOR_EXBLKNU. */ - -/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */ -#define BR_SDHC_VENDOR_EXBLKNU(x) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU)) - -/*! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU. */ -#define BF_SDHC_VENDOR_EXBLKNU(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXBLKNU) & BM_SDHC_VENDOR_EXBLKNU) - -/*! @brief Set the EXBLKNU field to a new value. */ -#define BW_SDHC_VENDOR_EXBLKNU(x, v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO) - * - * Internal state value, reflecting the corresponding state value selected by - * Debug Select field. This field is read-only and write to this field does not - * have effect. - */ -/*@{*/ -#define BP_SDHC_VENDOR_INTSTVAL (16U) /*!< Bit position for SDHC_VENDOR_INTSTVAL. */ -#define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) /*!< Bit mask for SDHC_VENDOR_INTSTVAL. */ -#define BS_SDHC_VENDOR_INTSTVAL (8U) /*!< Bit field size in bits for SDHC_VENDOR_INTSTVAL. */ - -/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */ -#define BR_SDHC_VENDOR_INTSTVAL(x) (HW_SDHC_VENDOR(x).B.INTSTVAL) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_MMCBOOT - MMC Boot register - ******************************************************************************/ - -/*! - * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW) - * - * Reset value: 0x00000000U - * - * This register contains the MMC fast boot control register. - */ -typedef union _hw_sdhc_mmcboot -{ - uint32_t U; - struct _hw_sdhc_mmcboot_bitfields - { - uint32_t DTOCVACK : 4; /*!< [3:0] Boot ACK Time Out Counter Value */ - uint32_t BOOTACK : 1; /*!< [4] Boot Ack Mode Select */ - uint32_t BOOTMODE : 1; /*!< [5] Boot Mode Select */ - uint32_t BOOTEN : 1; /*!< [6] Boot Mode Enable */ - uint32_t AUTOSABGEN : 1; /*!< [7] */ - uint32_t RESERVED0 : 8; /*!< [15:8] */ - uint32_t BOOTBLKCNT : 16; /*!< [31:16] */ - } B; -} hw_sdhc_mmcboot_t; - -/*! - * @name Constants and macros for entire SDHC_MMCBOOT register - */ -/*@{*/ -#define HW_SDHC_MMCBOOT_ADDR(x) ((x) + 0xC4U) - -#define HW_SDHC_MMCBOOT(x) (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR(x)) -#define HW_SDHC_MMCBOOT_RD(x) (HW_SDHC_MMCBOOT(x).U) -#define HW_SDHC_MMCBOOT_WR(x, v) (HW_SDHC_MMCBOOT(x).U = (v)) -#define HW_SDHC_MMCBOOT_SET(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) | (v))) -#define HW_SDHC_MMCBOOT_CLR(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) & ~(v))) -#define HW_SDHC_MMCBOOT_TOG(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SDHC_MMCBOOT bitfields - */ - -/*! - * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW) - * - * Values: - * - 0000 - SDCLK x 2^8 - * - 0001 - SDCLK x 2^9 - * - 0010 - SDCLK x 2^10 - * - 0011 - SDCLK x 2^11 - * - 0100 - SDCLK x 2^12 - * - 0101 - SDCLK x 2^13 - * - 0110 - SDCLK x 2^14 - * - 0111 - SDCLK x 2^15 - * - 1110 - SDCLK x 2^22 - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SDHC_MMCBOOT_DTOCVACK (0U) /*!< Bit position for SDHC_MMCBOOT_DTOCVACK. */ -#define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) /*!< Bit mask for SDHC_MMCBOOT_DTOCVACK. */ -#define BS_SDHC_MMCBOOT_DTOCVACK (4U) /*!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK. */ - -/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */ -#define BR_SDHC_MMCBOOT_DTOCVACK(x) (HW_SDHC_MMCBOOT(x).B.DTOCVACK) - -/*! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK. */ -#define BF_SDHC_MMCBOOT_DTOCVACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_DTOCVACK) & BM_SDHC_MMCBOOT_DTOCVACK) - -/*! @brief Set the DTOCVACK field to a new value. */ -#define BW_SDHC_MMCBOOT_DTOCVACK(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v))) -/*@}*/ - -/*! - * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW) - * - * Values: - * - 0 - No ack. - * - 1 - Ack. - */ -/*@{*/ -#define BP_SDHC_MMCBOOT_BOOTACK (4U) /*!< Bit position for SDHC_MMCBOOT_BOOTACK. */ -#define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) /*!< Bit mask for SDHC_MMCBOOT_BOOTACK. */ -#define BS_SDHC_MMCBOOT_BOOTACK (1U) /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK. */ - -/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */ -#define BR_SDHC_MMCBOOT_BOOTACK(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK)) - -/*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK. */ -#define BF_SDHC_MMCBOOT_BOOTACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTACK) & BM_SDHC_MMCBOOT_BOOTACK) - -/*! @brief Set the BOOTACK field to a new value. */ -#define BW_SDHC_MMCBOOT_BOOTACK(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW) - * - * Values: - * - 0 - Normal boot. - * - 1 - Alternative boot. - */ -/*@{*/ -#define BP_SDHC_MMCBOOT_BOOTMODE (5U) /*!< Bit position for SDHC_MMCBOOT_BOOTMODE. */ -#define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) /*!< Bit mask for SDHC_MMCBOOT_BOOTMODE. */ -#define BS_SDHC_MMCBOOT_BOOTMODE (1U) /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE. */ - -/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */ -#define BR_SDHC_MMCBOOT_BOOTMODE(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE)) - -/*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE. */ -#define BF_SDHC_MMCBOOT_BOOTMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTMODE) & BM_SDHC_MMCBOOT_BOOTMODE) - -/*! @brief Set the BOOTMODE field to a new value. */ -#define BW_SDHC_MMCBOOT_BOOTMODE(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW) - * - * Values: - * - 0 - Fast boot disable. - * - 1 - Fast boot enable. - */ -/*@{*/ -#define BP_SDHC_MMCBOOT_BOOTEN (6U) /*!< Bit position for SDHC_MMCBOOT_BOOTEN. */ -#define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) /*!< Bit mask for SDHC_MMCBOOT_BOOTEN. */ -#define BS_SDHC_MMCBOOT_BOOTEN (1U) /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN. */ - -/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */ -#define BR_SDHC_MMCBOOT_BOOTEN(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN)) - -/*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN. */ -#define BF_SDHC_MMCBOOT_BOOTEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTEN) & BM_SDHC_MMCBOOT_BOOTEN) - -/*! @brief Set the BOOTEN field to a new value. */ -#define BW_SDHC_MMCBOOT_BOOTEN(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW) - * - * When boot, enable auto stop at block gap function. This function will be - * triggered, and host will stop at block gap when received card block cnt is equal - * to BOOTBLKCNT. - */ -/*@{*/ -#define BP_SDHC_MMCBOOT_AUTOSABGEN (7U) /*!< Bit position for SDHC_MMCBOOT_AUTOSABGEN. */ -#define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) /*!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN. */ -#define BS_SDHC_MMCBOOT_AUTOSABGEN (1U) /*!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN. */ - -/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */ -#define BR_SDHC_MMCBOOT_AUTOSABGEN(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN)) - -/*! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN. */ -#define BF_SDHC_MMCBOOT_AUTOSABGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_AUTOSABGEN) & BM_SDHC_MMCBOOT_AUTOSABGEN) - -/*! @brief Set the AUTOSABGEN field to a new value. */ -#define BW_SDHC_MMCBOOT_AUTOSABGEN(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN) = (v)) -/*@}*/ - -/*! - * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW) - * - * Defines the stop at block gap value of automatic mode. When received card - * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap. - */ -/*@{*/ -#define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U) /*!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT. */ -#define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) /*!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT. */ -#define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U) /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT. */ - -/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */ -#define BR_SDHC_MMCBOOT_BOOTBLKCNT(x) (HW_SDHC_MMCBOOT(x).B.BOOTBLKCNT) - -/*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT. */ -#define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTBLKCNT) & BM_SDHC_MMCBOOT_BOOTBLKCNT) - -/*! @brief Set the BOOTBLKCNT field to a new value. */ -#define BW_SDHC_MMCBOOT_BOOTBLKCNT(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_SDHC_HOSTVER - Host Controller Version - ******************************************************************************/ - -/*! - * @brief HW_SDHC_HOSTVER - Host Controller Version (RO) - * - * Reset value: 0x00001201U - * - * This register contains the vendor host controller version information. All - * bits are read only and will read the same as the power-reset value. - */ -typedef union _hw_sdhc_hostver -{ - uint32_t U; - struct _hw_sdhc_hostver_bitfields - { - uint32_t SVN : 8; /*!< [7:0] Specification Version Number */ - uint32_t VVN : 8; /*!< [15:8] Vendor Version Number */ - uint32_t RESERVED0 : 16; /*!< [31:16] */ - } B; -} hw_sdhc_hostver_t; - -/*! - * @name Constants and macros for entire SDHC_HOSTVER register - */ -/*@{*/ -#define HW_SDHC_HOSTVER_ADDR(x) ((x) + 0xFCU) - -#define HW_SDHC_HOSTVER(x) (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR(x)) -#define HW_SDHC_HOSTVER_RD(x) (HW_SDHC_HOSTVER(x).U) -/*@}*/ - -/* - * Constants & macros for individual SDHC_HOSTVER bitfields - */ - -/*! - * @name Register SDHC_HOSTVER, field SVN[7:0] (RO) - * - * These status bits indicate the host controller specification version. - * - * Values: - * - 1 - SD host specification version 2.0, supports test event register and - * ADMA. - */ -/*@{*/ -#define BP_SDHC_HOSTVER_SVN (0U) /*!< Bit position for SDHC_HOSTVER_SVN. */ -#define BM_SDHC_HOSTVER_SVN (0x000000FFU) /*!< Bit mask for SDHC_HOSTVER_SVN. */ -#define BS_SDHC_HOSTVER_SVN (8U) /*!< Bit field size in bits for SDHC_HOSTVER_SVN. */ - -/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */ -#define BR_SDHC_HOSTVER_SVN(x) (HW_SDHC_HOSTVER(x).B.SVN) -/*@}*/ - -/*! - * @name Register SDHC_HOSTVER, field VVN[15:8] (RO) - * - * These status bits are reserved for the vendor version number. The host driver - * shall not use this status. - * - * Values: - * - 0 - Freescale SDHC version 1.0 - * - 10000 - Freescale SDHC version 2.0 - * - 10001 - Freescale SDHC version 2.1 - * - 10010 - Freescale SDHC version 2.2 - */ -/*@{*/ -#define BP_SDHC_HOSTVER_VVN (8U) /*!< Bit position for SDHC_HOSTVER_VVN. */ -#define BM_SDHC_HOSTVER_VVN (0x0000FF00U) /*!< Bit mask for SDHC_HOSTVER_VVN. */ -#define BS_SDHC_HOSTVER_VVN (8U) /*!< Bit field size in bits for SDHC_HOSTVER_VVN. */ - -/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */ -#define BR_SDHC_HOSTVER_VVN(x) (HW_SDHC_HOSTVER(x).B.VVN) -/*@}*/ - -/******************************************************************************* - * hw_sdhc_t - module struct - ******************************************************************************/ -/*! - * @brief All SDHC module registers. - */ -#pragma pack(1) -typedef struct _hw_sdhc -{ - __IO hw_sdhc_dsaddr_t DSADDR; /*!< [0x0] DMA System Address register */ - __IO hw_sdhc_blkattr_t BLKATTR; /*!< [0x4] Block Attributes register */ - __IO hw_sdhc_cmdarg_t CMDARG; /*!< [0x8] Command Argument register */ - __IO hw_sdhc_xfertyp_t XFERTYP; /*!< [0xC] Transfer Type register */ - __I hw_sdhc_cmdrsp0_t CMDRSP0; /*!< [0x10] Command Response 0 */ - __I hw_sdhc_cmdrsp1_t CMDRSP1; /*!< [0x14] Command Response 1 */ - __I hw_sdhc_cmdrsp2_t CMDRSP2; /*!< [0x18] Command Response 2 */ - __I hw_sdhc_cmdrsp3_t CMDRSP3; /*!< [0x1C] Command Response 3 */ - __IO hw_sdhc_datport_t DATPORT; /*!< [0x20] Buffer Data Port register */ - __I hw_sdhc_prsstat_t PRSSTAT; /*!< [0x24] Present State register */ - __IO hw_sdhc_proctl_t PROCTL; /*!< [0x28] Protocol Control register */ - __IO hw_sdhc_sysctl_t SYSCTL; /*!< [0x2C] System Control register */ - __IO hw_sdhc_irqstat_t IRQSTAT; /*!< [0x30] Interrupt Status register */ - __IO hw_sdhc_irqstaten_t IRQSTATEN; /*!< [0x34] Interrupt Status Enable register */ - __IO hw_sdhc_irqsigen_t IRQSIGEN; /*!< [0x38] Interrupt Signal Enable register */ - __I hw_sdhc_ac12err_t AC12ERR; /*!< [0x3C] Auto CMD12 Error Status Register */ - __I hw_sdhc_htcapblt_t HTCAPBLT; /*!< [0x40] Host Controller Capabilities */ - __IO hw_sdhc_wml_t WML; /*!< [0x44] Watermark Level Register */ - uint8_t _reserved0[8]; - __O hw_sdhc_fevt_t FEVT; /*!< [0x50] Force Event register */ - __I hw_sdhc_admaes_t ADMAES; /*!< [0x54] ADMA Error Status register */ - __IO hw_sdhc_adsaddr_t ADSADDR; /*!< [0x58] ADMA System Addressregister */ - uint8_t _reserved1[100]; - __IO hw_sdhc_vendor_t VENDOR; /*!< [0xC0] Vendor Specific register */ - __IO hw_sdhc_mmcboot_t MMCBOOT; /*!< [0xC4] MMC Boot register */ - uint8_t _reserved2[52]; - __I hw_sdhc_hostver_t HOSTVER; /*!< [0xFC] Host Controller Version */ -} hw_sdhc_t; -#pragma pack() - -/*! @brief Macro to access all SDHC registers. */ -/*! @param x SDHC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SDHC(SDHC_BASE). */ -#define HW_SDHC(x) (*(hw_sdhc_t *)(x)) - -#endif /* __HW_SDHC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sim.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sim.h deleted file mode 100644 index 4f7ea7973e2..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sim.h +++ /dev/null @@ -1,4084 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SIM_REGISTERS_H__ -#define __HW_SIM_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 SIM - * - * System Integration Module - * - * Registers defined in this header file: - * - HW_SIM_SOPT1 - System Options Register 1 - * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register - * - HW_SIM_SOPT2 - System Options Register 2 - * - HW_SIM_SOPT4 - System Options Register 4 - * - HW_SIM_SOPT5 - System Options Register 5 - * - HW_SIM_SOPT7 - System Options Register 7 - * - HW_SIM_SDID - System Device Identification Register - * - HW_SIM_SCGC1 - System Clock Gating Control Register 1 - * - HW_SIM_SCGC2 - System Clock Gating Control Register 2 - * - HW_SIM_SCGC3 - System Clock Gating Control Register 3 - * - HW_SIM_SCGC4 - System Clock Gating Control Register 4 - * - HW_SIM_SCGC5 - System Clock Gating Control Register 5 - * - HW_SIM_SCGC6 - System Clock Gating Control Register 6 - * - HW_SIM_SCGC7 - System Clock Gating Control Register 7 - * - HW_SIM_CLKDIV1 - System Clock Divider Register 1 - * - HW_SIM_CLKDIV2 - System Clock Divider Register 2 - * - HW_SIM_FCFG1 - Flash Configuration Register 1 - * - HW_SIM_FCFG2 - Flash Configuration Register 2 - * - HW_SIM_UIDH - Unique Identification Register High - * - HW_SIM_UIDMH - Unique Identification Register Mid-High - * - HW_SIM_UIDML - Unique Identification Register Mid Low - * - HW_SIM_UIDL - Unique Identification Register Low - * - * - hw_sim_t - Struct containing all module registers. - */ - -#define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */ - -/******************************************************************************* - * HW_SIM_SOPT1 - System Options Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT1 - System Options Register 1 (RW) - * - * Reset value: 0x80000000U - * - * The SOPT1 register is only reset on POR or LVD. - */ -typedef union _hw_sim_sopt1 -{ - uint32_t U; - struct _hw_sim_sopt1_bitfields - { - uint32_t RESERVED0 : 12; /*!< [11:0] */ - uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */ - uint32_t RESERVED1 : 2; /*!< [17:16] */ - uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */ - uint32_t RESERVED2 : 9; /*!< [28:20] */ - uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby - * mode during VLPR and VLPW modes */ - uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby - * mode during Stop, VLPS, LLS and VLLS modes. */ - uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */ - } B; -} hw_sim_sopt1_t; - -/*! - * @name Constants and macros for entire SIM_SOPT1 register - */ -/*@{*/ -#define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U) - -#define HW_SIM_SOPT1(x) (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x)) -#define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U) -#define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v)) -#define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) | (v))) -#define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v))) -#define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT1 bitfields - */ - -/*! - * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO) - * - * This field specifies the amount of system RAM available on the device. - * - * Values: - * - 0001 - 8 KB - * - 0011 - 16 KB - * - 0100 - 24 KB - * - 0101 - 32 KB - * - 0110 - 48 KB - * - 0111 - 64 KB - * - 1000 - 96 KB - * - 1001 - 128 KB - * - 1011 - 256 KB - */ -/*@{*/ -#define BP_SIM_SOPT1_RAMSIZE (12U) /*!< Bit position for SIM_SOPT1_RAMSIZE. */ -#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */ -#define BS_SIM_SOPT1_RAMSIZE (4U) /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */ - -/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */ -#define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW) - * - * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset - * only on POR/LVD. - * - * Values: - * - 00 - System oscillator (OSC32KCLK) - * - 01 - Reserved - * - 10 - RTC 32.768kHz oscillator - * - 11 - LPO 1 kHz - */ -/*@{*/ -#define BP_SIM_SOPT1_OSC32KSEL (18U) /*!< Bit position for SIM_SOPT1_OSC32KSEL. */ -#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */ -#define BS_SIM_SOPT1_OSC32KSEL (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */ - -/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */ -#define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL) - -/*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */ -#define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL) - -/*! @brief Set the OSC32KSEL field to a new value. */ -#define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field USBVSTBY[29] (RW) - * - * Controls whether the USB voltage regulator is placed in standby mode during - * VLPR and VLPW modes. - * - * Values: - * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes. - * - 1 - USB voltage regulator in standby during VLPR and VLPW modes. - */ -/*@{*/ -#define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */ -#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */ -#define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */ - -/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */ -#define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY)) - -/*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */ -#define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY) - -/*! @brief Set the USBVSTBY field to a new value. */ -#define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field USBSSTBY[30] (RW) - * - * Controls whether the USB voltage regulator is placed in standby mode during - * Stop, VLPS, LLS and VLLS modes. - * - * Values: - * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS - * modes. - * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. - */ -/*@{*/ -#define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */ -#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */ -#define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */ - -/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */ -#define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY)) - -/*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */ -#define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY) - -/*! @brief Set the USBSSTBY field to a new value. */ -#define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1, field USBREGEN[31] (RW) - * - * Controls whether the USB voltage regulator is enabled. - * - * Values: - * - 0 - USB voltage regulator is disabled. - * - 1 - USB voltage regulator is enabled. - */ -/*@{*/ -#define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */ -#define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */ -#define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */ - -/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */ -#define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN)) - -/*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */ -#define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN) - -/*! @brief Set the USBREGEN field to a new value. */ -#define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT1CFG - SOPT1 Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW) - * - * Reset value: 0x00000000U - * - * The SOPT1CFG register is reset on System Reset not VLLS. - */ -typedef union _hw_sim_sopt1cfg -{ - uint32_t U; - struct _hw_sim_sopt1cfg_bitfields - { - uint32_t RESERVED0 : 24; /*!< [23:0] */ - uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write - * enable */ - uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write - * enable */ - uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby - * write enable */ - uint32_t RESERVED1 : 5; /*!< [31:27] */ - } B; -} hw_sim_sopt1cfg_t; - -/*! - * @name Constants and macros for entire SIM_SOPT1CFG register - */ -/*@{*/ -#define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U) - -#define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x)) -#define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U) -#define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v)) -#define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v))) -#define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v))) -#define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT1CFG bitfields - */ - -/*! - * @name Register SIM_SOPT1CFG, field URWE[24] (RW) - * - * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This - * register bit clears after a write to USBREGEN. - * - * Values: - * - 0 - SOPT1 USBREGEN cannot be written. - * - 1 - SOPT1 USBREGEN can be written. - */ -/*@{*/ -#define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */ -#define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */ -#define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */ - -/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */ -#define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE)) - -/*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */ -#define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE) - -/*! @brief Set the URWE field to a new value. */ -#define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW) - * - * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. - * This register bit clears after a write to USBVSTBY. - * - * Values: - * - 0 - SOPT1 USBVSTBY cannot be written. - * - 1 - SOPT1 USBVSTBY can be written. - */ -/*@{*/ -#define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */ -#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */ -#define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */ - -/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */ -#define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE)) - -/*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */ -#define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE) - -/*! @brief Set the UVSWE field to a new value. */ -#define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT1CFG, field USSWE[26] (RW) - * - * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. - * This register bit clears after a write to USBSSTBY. - * - * Values: - * - 0 - SOPT1 USBSSTBY cannot be written. - * - 1 - SOPT1 USBSSTBY can be written. - */ -/*@{*/ -#define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */ -#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */ -#define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */ - -/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */ -#define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE)) - -/*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */ -#define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE) - -/*! @brief Set the USSWE field to a new value. */ -#define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT2 - System Options Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT2 - System Options Register 2 (RW) - * - * Reset value: 0x00001000U - * - * SOPT2 contains the controls for selecting many of the module clock source - * options on this device. See the Clock Distribution chapter for more information - * including clocking diagrams and definitions of device clocks. - */ -typedef union _hw_sim_sopt2 -{ - uint32_t U; - struct _hw_sim_sopt2_bitfields - { - uint32_t RESERVED0 : 4; /*!< [3:0] */ - uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */ - uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */ - uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */ - uint32_t RESERVED1 : 1; /*!< [10] */ - uint32_t PTD7PAD : 1; /*!< [11] PTD7 pad drive strength */ - uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */ - uint32_t RESERVED2 : 3; /*!< [15:13] */ - uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */ - uint32_t USBSRC : 1; /*!< [18] USB clock source select */ - uint32_t RMIISRC : 1; /*!< [19] RMII clock source select */ - uint32_t TIMESRC : 2; /*!< [21:20] IEEE 1588 timestamp clock source - * select */ - uint32_t RESERVED3 : 6; /*!< [27:22] */ - uint32_t SDHCSRC : 2; /*!< [29:28] SDHC clock source select */ - uint32_t RESERVED4 : 2; /*!< [31:30] */ - } B; -} hw_sim_sopt2_t; - -/*! - * @name Constants and macros for entire SIM_SOPT2 register - */ -/*@{*/ -#define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U) - -#define HW_SIM_SOPT2(x) (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x)) -#define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U) -#define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v)) -#define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) | (v))) -#define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v))) -#define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT2 bitfields - */ - -/*! - * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW) - * - * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the - * RTC_CLKOUT pin. - * - * Values: - * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin. - * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin. - */ -/*@{*/ -#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */ -#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */ -#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */ -#define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL)) - -/*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */ -#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL) - -/*! @brief Set the RTCCLKOUTSEL field to a new value. */ -#define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW) - * - * Selects the clock to output on the CLKOUT pin. - * - * Values: - * - 000 - FlexBus CLKOUT - * - 001 - Reserved - * - 010 - Flash clock - * - 011 - LPO clock (1 kHz) - * - 100 - MCGIRCLK - * - 101 - RTC 32.768kHz clock - * - 110 - OSCERCLK0 - * - 111 - IRC 48 MHz clock - */ -/*@{*/ -#define BP_SIM_SOPT2_CLKOUTSEL (5U) /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */ -#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */ -#define BS_SIM_SOPT2_CLKOUTSEL (3U) /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */ -#define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL) - -/*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */ -#define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL) - -/*! @brief Set the CLKOUTSEL field to a new value. */ -#define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field FBSL[9:8] (RW) - * - * If flash security is enabled, then this field affects what CPU operations can - * access off-chip via the FlexBus interface. This field has no effect if flash - * security is not enabled. - * - * Values: - * - 00 - All off-chip accesses (instruction and data) via the FlexBus are - * disallowed. - * - 01 - All off-chip accesses (instruction and data) via the FlexBus are - * disallowed. - * - 10 - Off-chip instruction accesses are disallowed. Data accesses are - * allowed. - * - 11 - Off-chip instruction accesses and data accesses are allowed. - */ -/*@{*/ -#define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */ -#define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */ -#define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */ - -/*! @brief Read current value of the SIM_SOPT2_FBSL field. */ -#define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL) - -/*! @brief Format value for bitfield SIM_SOPT2_FBSL. */ -#define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL) - -/*! @brief Set the FBSL field to a new value. */ -#define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field PTD7PAD[11] (RW) - * - * Controls the output drive strength of the PTD7 pin by selecting either one or - * two pads to drive it. - * - * Values: - * - 0 - Single-pad drive strength for PTD7. - * - 1 - Double pad drive strength for PTD7. - */ -/*@{*/ -#define BP_SIM_SOPT2_PTD7PAD (11U) /*!< Bit position for SIM_SOPT2_PTD7PAD. */ -#define BM_SIM_SOPT2_PTD7PAD (0x00000800U) /*!< Bit mask for SIM_SOPT2_PTD7PAD. */ -#define BS_SIM_SOPT2_PTD7PAD (1U) /*!< Bit field size in bits for SIM_SOPT2_PTD7PAD. */ - -/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */ -#define BR_SIM_SOPT2_PTD7PAD(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD)) - -/*! @brief Format value for bitfield SIM_SOPT2_PTD7PAD. */ -#define BF_SIM_SOPT2_PTD7PAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PTD7PAD) & BM_SIM_SOPT2_PTD7PAD) - -/*! @brief Set the PTD7PAD field to a new value. */ -#define BW_SIM_SOPT2_PTD7PAD(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW) - * - * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace - * clock source. - * - * Values: - * - 0 - MCGOUTCLK - * - 1 - Core/system clock - */ -/*@{*/ -#define BP_SIM_SOPT2_TRACECLKSEL (12U) /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */ -#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */ -#define BS_SIM_SOPT2_TRACECLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */ -#define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */ -#define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL) - -/*! @brief Set the TRACECLKSEL field to a new value. */ -#define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW) - * - * Selects the high frequency clock for various peripheral clocking options. - * - * Values: - * - 00 - MCGFLLCLK clock - * - 01 - MCGPLLCLK clock - * - 10 - Reserved - * - 11 - IRC48 MHz clock - */ -/*@{*/ -#define BP_SIM_SOPT2_PLLFLLSEL (16U) /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */ -#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */ -#define BS_SIM_SOPT2_PLLFLLSEL (2U) /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */ - -/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */ -#define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL) - -/*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */ -#define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL) - -/*! @brief Set the PLLFLLSEL field to a new value. */ -#define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field USBSRC[18] (RW) - * - * Selects the clock source for the USB 48 MHz clock. - * - * Values: - * - 0 - External bypass clock (USB_CLKIN). - * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by - * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by - * SIM_CLKDIV2[USBFRAC, USBDIV]. - */ -/*@{*/ -#define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */ -#define BM_SIM_SOPT2_USBSRC (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBSRC. */ -#define BS_SIM_SOPT2_USBSRC (1U) /*!< Bit field size in bits for SIM_SOPT2_USBSRC. */ - -/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */ -#define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC)) - -/*! @brief Format value for bitfield SIM_SOPT2_USBSRC. */ -#define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC) - -/*! @brief Set the USBSRC field to a new value. */ -#define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field RMIISRC[19] (RW) - * - * Selects the clock source for the Ethernet RMII interface - * - * Values: - * - 0 - EXTAL clock - * - 1 - External bypass clock (ENET_1588_CLKIN). - */ -/*@{*/ -#define BP_SIM_SOPT2_RMIISRC (19U) /*!< Bit position for SIM_SOPT2_RMIISRC. */ -#define BM_SIM_SOPT2_RMIISRC (0x00080000U) /*!< Bit mask for SIM_SOPT2_RMIISRC. */ -#define BS_SIM_SOPT2_RMIISRC (1U) /*!< Bit field size in bits for SIM_SOPT2_RMIISRC. */ - -/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */ -#define BR_SIM_SOPT2_RMIISRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC)) - -/*! @brief Format value for bitfield SIM_SOPT2_RMIISRC. */ -#define BF_SIM_SOPT2_RMIISRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RMIISRC) & BM_SIM_SOPT2_RMIISRC) - -/*! @brief Set the RMIISRC field to a new value. */ -#define BW_SIM_SOPT2_RMIISRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW) - * - * Selects the clock source for the Ethernet timestamp clock. - * - * Values: - * - 00 - Core/system clock. - * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by - * SOPT2[PLLFLLSEL]. - * - 10 - OSCERCLK clock - * - 11 - External bypass clock (ENET_1588_CLKIN). - */ -/*@{*/ -#define BP_SIM_SOPT2_TIMESRC (20U) /*!< Bit position for SIM_SOPT2_TIMESRC. */ -#define BM_SIM_SOPT2_TIMESRC (0x00300000U) /*!< Bit mask for SIM_SOPT2_TIMESRC. */ -#define BS_SIM_SOPT2_TIMESRC (2U) /*!< Bit field size in bits for SIM_SOPT2_TIMESRC. */ - -/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */ -#define BR_SIM_SOPT2_TIMESRC(x) (HW_SIM_SOPT2(x).B.TIMESRC) - -/*! @brief Format value for bitfield SIM_SOPT2_TIMESRC. */ -#define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC) - -/*! @brief Set the TIMESRC field to a new value. */ -#define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW) - * - * Selects the clock source for the SDHC clock . - * - * Values: - * - 00 - Core/system clock. - * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by - * SOPT2[PLLFLLSEL]. - * - 10 - OSCERCLK clock - * - 11 - External bypass clock (SDHC0_CLKIN) - */ -/*@{*/ -#define BP_SIM_SOPT2_SDHCSRC (28U) /*!< Bit position for SIM_SOPT2_SDHCSRC. */ -#define BM_SIM_SOPT2_SDHCSRC (0x30000000U) /*!< Bit mask for SIM_SOPT2_SDHCSRC. */ -#define BS_SIM_SOPT2_SDHCSRC (2U) /*!< Bit field size in bits for SIM_SOPT2_SDHCSRC. */ - -/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */ -#define BR_SIM_SOPT2_SDHCSRC(x) (HW_SIM_SOPT2(x).B.SDHCSRC) - -/*! @brief Format value for bitfield SIM_SOPT2_SDHCSRC. */ -#define BF_SIM_SOPT2_SDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_SDHCSRC) & BM_SIM_SOPT2_SDHCSRC) - -/*! @brief Set the SDHCSRC field to a new value. */ -#define BW_SIM_SOPT2_SDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT4 - System Options Register 4 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT4 - System Options Register 4 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt4 -{ - uint32_t U; - struct _hw_sim_sopt4_bitfields - { - uint32_t FTM0FLT0 : 1; /*!< [0] FTM0 Fault 0 Select */ - uint32_t FTM0FLT1 : 1; /*!< [1] FTM0 Fault 1 Select */ - uint32_t FTM0FLT2 : 1; /*!< [2] FTM0 Fault 2 Select */ - uint32_t RESERVED0 : 1; /*!< [3] */ - uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */ - uint32_t RESERVED1 : 3; /*!< [7:5] */ - uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */ - uint32_t RESERVED2 : 3; /*!< [11:9] */ - uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */ - uint32_t RESERVED3 : 5; /*!< [17:13] */ - uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture - * source select */ - uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture - * source select */ - uint32_t RESERVED4 : 2; /*!< [23:22] */ - uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin - * Select */ - uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */ - uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin - * Select */ - uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin - * Select */ - uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0 - * Source Select */ - uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1 - * Source Select */ - uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0 - * Source Select */ - uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1 - * Source Select */ - } B; -} hw_sim_sopt4_t; - -/*! - * @name Constants and macros for entire SIM_SOPT4 register - */ -/*@{*/ -#define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU) - -#define HW_SIM_SOPT4(x) (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x)) -#define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U) -#define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v)) -#define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) | (v))) -#define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v))) -#define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT4 bitfields - */ - -/*! - * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW) - * - * Selects the source of FTM0 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM0_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0FLT0 (0U) /*!< Bit position for SIM_SOPT4_FTM0FLT0. */ -#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */ -#define BS_SIM_SOPT4_FTM0FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */ -#define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */ -#define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0) - -/*! @brief Set the FTM0FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW) - * - * Selects the source of FTM0 fault 1. The pin source for fault 1 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM0_FLT1 pin - * - 1 - CMP1 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit position for SIM_SOPT4_FTM0FLT1. */ -#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */ -#define BS_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */ -#define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */ -#define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1) - -/*! @brief Set the FTM0FLT1 field to a new value. */ -#define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW) - * - * Selects the source of FTM0 fault 2. The pin source for fault 2 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM0_FLT2 pin - * - 1 - CMP2 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0FLT2 (2U) /*!< Bit position for SIM_SOPT4_FTM0FLT2. */ -#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /*!< Bit mask for SIM_SOPT4_FTM0FLT2. */ -#define BS_SIM_SOPT4_FTM0FLT2 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */ -#define BR_SIM_SOPT4_FTM0FLT2(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. */ -#define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2) - -/*! @brief Set the FTM0FLT2 field to a new value. */ -#define BW_SIM_SOPT4_FTM0FLT2(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW) - * - * Selects the source of FTM1 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate pin control - * register in the port control module. - * - * Values: - * - 0 - FTM1_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM1FLT0 (4U) /*!< Bit position for SIM_SOPT4_FTM1FLT0. */ -#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */ -#define BS_SIM_SOPT4_FTM1FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */ -#define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */ -#define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0) - -/*! @brief Set the FTM1FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW) - * - * Selects the source of FTM2 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate PORTx pin - * control register. - * - * Values: - * - 0 - FTM2_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2FLT0 (8U) /*!< Bit position for SIM_SOPT4_FTM2FLT0. */ -#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */ -#define BS_SIM_SOPT4_FTM2FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */ -#define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */ -#define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0) - -/*! @brief Set the FTM2FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW) - * - * Selects the source of FTM3 fault 0. The pin source for fault 0 must be - * configured for the FTM module fault function through the appropriate PORTx pin - * control register. - * - * Values: - * - 0 - FTM3_FLT0 pin - * - 1 - CMP0 out - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */ -#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */ -#define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */ -#define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */ -#define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0) - -/*! @brief Set the FTM3FLT0 field to a new value. */ -#define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW) - * - * Selects the source for FTM1 channel 0 input capture. When the FTM is not in - * input capture mode, clear this field. - * - * Values: - * - 00 - FTM1_CH0 signal - * - 01 - CMP0 output - * - 10 - CMP1 output - * - 11 - USB start of frame pulse - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM1CH0SRC (18U) /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */ -#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */ -#define BS_SIM_SOPT4_FTM1CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */ -#define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */ -#define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC) - -/*! @brief Set the FTM1CH0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW) - * - * Selects the source for FTM2 channel 0 input capture. When the FTM is not in - * input capture mode, clear this field. - * - * Values: - * - 00 - FTM2_CH0 signal - * - 01 - CMP0 output - * - 10 - CMP1 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2CH0SRC (20U) /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */ -#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */ -#define BS_SIM_SOPT4_FTM2CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */ -#define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */ -#define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC) - -/*! @brief Set the FTM2CH0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW) - * - * Selects the external pin used to drive the clock to the FTM0 module. The - * selected pin must also be configured for the FTM external clock function through - * the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM_CLK0 pin - * - 1 - FTM_CLK1 pin - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0CLKSEL (24U) /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */ -#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */ -#define BS_SIM_SOPT4_FTM0CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */ -#define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */ -#define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL) - -/*! @brief Set the FTM0CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW) - * - * Selects the external pin used to drive the clock to the FTM1 module. The - * selected pin must also be configured for the FTM external clock function through - * the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM_CLK0 pin - * - 1 - FTM_CLK1 pin - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM1CLKSEL (25U) /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */ -#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */ -#define BS_SIM_SOPT4_FTM1CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */ -#define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */ -#define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL) - -/*! @brief Set the FTM1CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW) - * - * Selects the external pin used to drive the clock to the FTM2 module. The - * selected pin must also be configured for the FTM2 module external clock function - * through the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM2 external clock driven by FTM_CLK0 pin. - * - 1 - FTM2 external clock driven by FTM_CLK1 pin. - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM2CLKSEL (26U) /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */ -#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */ -#define BS_SIM_SOPT4_FTM2CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */ -#define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */ -#define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL) - -/*! @brief Set the FTM2CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW) - * - * Selects the external pin used to drive the clock to the FTM3 module. The - * selected pin must also be configured for the FTM3 module external clock function - * through the appropriate pin control register in the port control module. - * - * Values: - * - 0 - FTM3 external clock driven by FTM_CLK0 pin. - * - 1 - FTM3 external clock driven by FTM_CLK1 pin. - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */ -#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */ -#define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */ -#define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */ -#define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL) - -/*! @brief Set the FTM3CLKSEL field to a new value. */ -#define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW) - * - * Selects the source of FTM0 hardware trigger 0. - * - * Values: - * - 0 - HSCMP0 output drives FTM0 hardware trigger 0 - * - 1 - FTM1 channel match drives FTM0 hardware trigger 0 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */ -#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */ -#define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */ -#define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */ -#define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC) - -/*! @brief Set the FTM0TRG0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW) - * - * Selects the source of FTM0 hardware trigger 1. - * - * Values: - * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1 - * - 1 - FTM2 channel match drives FTM0 hardware trigger 1 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */ -#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */ -#define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */ -#define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */ -#define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC) - -/*! @brief Set the FTM0TRG1SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW) - * - * Selects the source of FTM3 hardware trigger 0. - * - * Values: - * - 0 - Reserved - * - 1 - FTM1 channel match drives FTM3 hardware trigger 0 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */ -#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */ -#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */ -#define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */ -#define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC) - -/*! @brief Set the FTM3TRG0SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW) - * - * Selects the source of FTM3 hardware trigger 1. - * - * Values: - * - 0 - Reserved - * - 1 - FTM2 channel match drives FTM3 hardware trigger 1 - */ -/*@{*/ -#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */ -#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */ -#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */ - -/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */ -#define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC)) - -/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */ -#define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC) - -/*! @brief Set the FTM3TRG1SRC field to a new value. */ -#define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT5 - System Options Register 5 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT5 - System Options Register 5 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt5 -{ - uint32_t U; - struct _hw_sim_sopt5_bitfields - { - uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source - * select */ - uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select - * */ - uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source - * select */ - uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select - * */ - uint32_t RESERVED0 : 24; /*!< [31:8] */ - } B; -} hw_sim_sopt5_t; - -/*! - * @name Constants and macros for entire SIM_SOPT5 register - */ -/*@{*/ -#define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U) - -#define HW_SIM_SOPT5(x) (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x)) -#define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U) -#define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v)) -#define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) | (v))) -#define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v))) -#define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT5 bitfields - */ - -/*! - * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW) - * - * Selects the source for the UART 0 transmit data. - * - * Values: - * - 00 - UART0_TX pin - * - 01 - UART0_TX pin modulated with FTM1 channel 0 output - * - 10 - UART0_TX pin modulated with FTM2 channel 0 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART0TXSRC (0U) /*!< Bit position for SIM_SOPT5_UART0TXSRC. */ -#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */ -#define BS_SIM_SOPT5_UART0TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */ -#define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */ -#define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC) - -/*! @brief Set the UART0TXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW) - * - * Selects the source for the UART 0 receive data. - * - * Values: - * - 00 - UART0_RX pin - * - 01 - CMP0 - * - 10 - CMP1 - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit position for SIM_SOPT5_UART0RXSRC. */ -#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */ -#define BS_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */ -#define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */ -#define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC) - -/*! @brief Set the UART0RXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW) - * - * Selects the source for the UART 1 transmit data. - * - * Values: - * - 00 - UART1_TX pin - * - 01 - UART1_TX pin modulated with FTM1 channel 0 output - * - 10 - UART1_TX pin modulated with FTM2 channel 0 output - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART1TXSRC (4U) /*!< Bit position for SIM_SOPT5_UART1TXSRC. */ -#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */ -#define BS_SIM_SOPT5_UART1TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */ -#define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */ -#define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC) - -/*! @brief Set the UART1TXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW) - * - * Selects the source for the UART 1 receive data. - * - * Values: - * - 00 - UART1_RX pin - * - 01 - CMP0 - * - 10 - CMP1 - * - 11 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT5_UART1RXSRC (6U) /*!< Bit position for SIM_SOPT5_UART1RXSRC. */ -#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */ -#define BS_SIM_SOPT5_UART1RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */ - -/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */ -#define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC) - -/*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */ -#define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC) - -/*! @brief Set the UART1RXSRC field to a new value. */ -#define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SOPT7 - System Options Register 7 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SOPT7 - System Options Register 7 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_sopt7 -{ - uint32_t U; - struct _hw_sim_sopt7_bitfields - { - uint32_t ADC0TRGSEL : 4; /*!< [3:0] ADC0 trigger select */ - uint32_t ADC0PRETRGSEL : 1; /*!< [4] ADC0 pretrigger select */ - uint32_t RESERVED0 : 2; /*!< [6:5] */ - uint32_t ADC0ALTTRGEN : 1; /*!< [7] ADC0 alternate trigger enable */ - uint32_t ADC1TRGSEL : 4; /*!< [11:8] ADC1 trigger select */ - uint32_t ADC1PRETRGSEL : 1; /*!< [12] ADC1 pre-trigger select */ - uint32_t RESERVED1 : 2; /*!< [14:13] */ - uint32_t ADC1ALTTRGEN : 1; /*!< [15] ADC1 alternate trigger enable */ - uint32_t RESERVED2 : 16; /*!< [31:16] */ - } B; -} hw_sim_sopt7_t; - -/*! - * @name Constants and macros for entire SIM_SOPT7 register - */ -/*@{*/ -#define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U) - -#define HW_SIM_SOPT7(x) (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x)) -#define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U) -#define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v)) -#define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) | (v))) -#define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v))) -#define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SOPT7 bitfields - */ - -/*! - * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW) - * - * Selects the ADC0 trigger source when alternative triggers are functional in - * stop and VLPS modes. . - * - * Values: - * - 0000 - PDB external trigger pin input (PDB0_EXTRG) - * - 0001 - High speed comparator 0 output - * - 0010 - High speed comparator 1 output - * - 0011 - High speed comparator 2 output - * - 0100 - PIT trigger 0 - * - 0101 - PIT trigger 1 - * - 0110 - PIT trigger 2 - * - 0111 - PIT trigger 3 - * - 1000 - FTM0 trigger - * - 1001 - FTM1 trigger - * - 1010 - FTM2 trigger - * - 1011 - FTM3 trigger - * - 1100 - RTC alarm - * - 1101 - RTC seconds - * - 1110 - Low-power timer (LPTMR) trigger - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC0TRGSEL (0U) /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */ -#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */ -#define BS_SIM_SOPT7_ADC0TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */ -#define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */ -#define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL) - -/*! @brief Set the ADC0TRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW) - * - * Selects the ADC0 pre-trigger source when alternative triggers are enabled - * through ADC0ALTTRGEN. - * - * Values: - * - 0 - Pre-trigger A - * - 1 - Pre-trigger B - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */ -#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */ -#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */ -#define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */ -#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL) - -/*! @brief Set the ADC0PRETRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW) - * - * Enable alternative conversion triggers for ADC0. - * - * Values: - * - 0 - PDB trigger selected for ADC0. - * - 1 - Alternate trigger selected for ADC0. - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */ -#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */ -#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */ -#define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */ -#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN) - -/*! @brief Set the ADC0ALTTRGEN field to a new value. */ -#define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW) - * - * Selects the ADC1 trigger source when alternative triggers are functional in - * stop and VLPS modes. - * - * Values: - * - 0000 - PDB external trigger pin input (PDB0_EXTRG) - * - 0001 - High speed comparator 0 output - * - 0010 - High speed comparator 1 output - * - 0011 - High speed comparator 2 output - * - 0100 - PIT trigger 0 - * - 0101 - PIT trigger 1 - * - 0110 - PIT trigger 2 - * - 0111 - PIT trigger 3 - * - 1000 - FTM0 trigger - * - 1001 - FTM1 trigger - * - 1010 - FTM2 trigger - * - 1011 - FTM3 trigger - * - 1100 - RTC alarm - * - 1101 - RTC seconds - * - 1110 - Low-power timer (LPTMR) trigger - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC1TRGSEL (8U) /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */ -#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */ -#define BS_SIM_SOPT7_ADC1TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */ -#define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */ -#define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL) - -/*! @brief Set the ADC1TRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v))) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW) - * - * Selects the ADC1 pre-trigger source when alternative triggers are enabled - * through ADC1ALTTRGEN. - * - * Values: - * - 0 - Pre-trigger A selected for ADC1. - * - 1 - Pre-trigger B selected for ADC1. - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */ -#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */ -#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */ -#define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */ -#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL) - -/*! @brief Set the ADC1PRETRGSEL field to a new value. */ -#define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW) - * - * Enable alternative conversion triggers for ADC1. - * - * Values: - * - 0 - PDB trigger selected for ADC1 - * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. - */ -/*@{*/ -#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */ -#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */ -#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */ - -/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */ -#define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN)) - -/*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */ -#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN) - -/*! @brief Set the ADC1ALTTRGEN field to a new value. */ -#define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SDID - System Device Identification Register - ******************************************************************************/ - -/*! - * @brief HW_SIM_SDID - System Device Identification Register (RO) - * - * Reset value: 0x00000380U - */ -typedef union _hw_sim_sdid -{ - uint32_t U; - struct _hw_sim_sdid_bitfields - { - uint32_t PINID : 4; /*!< [3:0] Pincount identification */ - uint32_t FAMID : 3; /*!< [6:4] Kinetis family identification */ - uint32_t DIEID : 5; /*!< [11:7] Device Die ID */ - uint32_t REVID : 4; /*!< [15:12] Device revision number */ - uint32_t RESERVED0 : 4; /*!< [19:16] */ - uint32_t SERIESID : 4; /*!< [23:20] Kinetis Series ID */ - uint32_t SUBFAMID : 4; /*!< [27:24] Kinetis Sub-Family ID */ - uint32_t FAMILYID : 4; /*!< [31:28] Kinetis Family ID */ - } B; -} hw_sim_sdid_t; - -/*! - * @name Constants and macros for entire SIM_SDID register - */ -/*@{*/ -#define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U) - -#define HW_SIM_SDID(x) (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x)) -#define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_SDID bitfields - */ - -/*! - * @name Register SIM_SDID, field PINID[3:0] (RO) - * - * Specifies the pincount of the device. - * - * Values: - * - 0000 - Reserved - * - 0001 - Reserved - * - 0010 - 32-pin - * - 0011 - Reserved - * - 0100 - 48-pin - * - 0101 - 64-pin - * - 0110 - 80-pin - * - 0111 - 81-pin or 121-pin - * - 1000 - 100-pin - * - 1001 - 121-pin - * - 1010 - 144-pin - * - 1011 - Custom pinout (WLCSP) - * - 1100 - 169-pin - * - 1101 - Reserved - * - 1110 - 256-pin - * - 1111 - Reserved - */ -/*@{*/ -#define BP_SIM_SDID_PINID (0U) /*!< Bit position for SIM_SDID_PINID. */ -#define BM_SIM_SDID_PINID (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */ -#define BS_SIM_SDID_PINID (4U) /*!< Bit field size in bits for SIM_SDID_PINID. */ - -/*! @brief Read current value of the SIM_SDID_PINID field. */ -#define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field FAMID[6:4] (RO) - * - * This field is maintained for compatibility only, but has been superceded by - * the SERIESID, FAMILYID and SUBFAMID fields in this register. - * - * Values: - * - 000 - K1x Family (without tamper) - * - 001 - K2x Family (without tamper) - * - 010 - K3x Family or K1x/K6x Family (with tamper) - * - 011 - K4x Family or K2x Family (with tamper) - * - 100 - K6x Family (without tamper) - * - 101 - K7x Family - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SIM_SDID_FAMID (4U) /*!< Bit position for SIM_SDID_FAMID. */ -#define BM_SIM_SDID_FAMID (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */ -#define BS_SIM_SDID_FAMID (3U) /*!< Bit field size in bits for SIM_SDID_FAMID. */ - -/*! @brief Read current value of the SIM_SDID_FAMID field. */ -#define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field DIEID[11:7] (RO) - * - * Specifies the silicon feature set identication number for the device. - */ -/*@{*/ -#define BP_SIM_SDID_DIEID (7U) /*!< Bit position for SIM_SDID_DIEID. */ -#define BM_SIM_SDID_DIEID (0x00000F80U) /*!< Bit mask for SIM_SDID_DIEID. */ -#define BS_SIM_SDID_DIEID (5U) /*!< Bit field size in bits for SIM_SDID_DIEID. */ - -/*! @brief Read current value of the SIM_SDID_DIEID field. */ -#define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field REVID[15:12] (RO) - * - * Specifies the silicon implementation number for the device. - */ -/*@{*/ -#define BP_SIM_SDID_REVID (12U) /*!< Bit position for SIM_SDID_REVID. */ -#define BM_SIM_SDID_REVID (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */ -#define BS_SIM_SDID_REVID (4U) /*!< Bit field size in bits for SIM_SDID_REVID. */ - -/*! @brief Read current value of the SIM_SDID_REVID field. */ -#define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field SERIESID[23:20] (RO) - * - * Specifies the Kinetis series of the device. - * - * Values: - * - 0000 - Kinetis K series - * - 0001 - Kinetis L series - * - 0101 - Kinetis W series - * - 0110 - Kinetis V series - */ -/*@{*/ -#define BP_SIM_SDID_SERIESID (20U) /*!< Bit position for SIM_SDID_SERIESID. */ -#define BM_SIM_SDID_SERIESID (0x00F00000U) /*!< Bit mask for SIM_SDID_SERIESID. */ -#define BS_SIM_SDID_SERIESID (4U) /*!< Bit field size in bits for SIM_SDID_SERIESID. */ - -/*! @brief Read current value of the SIM_SDID_SERIESID field. */ -#define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field SUBFAMID[27:24] (RO) - * - * Specifies the Kinetis sub-family of the device. - * - * Values: - * - 0000 - Kx0 Subfamily - * - 0001 - Kx1 Subfamily (tamper detect) - * - 0010 - Kx2 Subfamily - * - 0011 - Kx3 Subfamily (tamper detect) - * - 0100 - Kx4 Subfamily - * - 0101 - Kx5 Subfamily (tamper detect) - * - 0110 - Kx6 Subfamily - */ -/*@{*/ -#define BP_SIM_SDID_SUBFAMID (24U) /*!< Bit position for SIM_SDID_SUBFAMID. */ -#define BM_SIM_SDID_SUBFAMID (0x0F000000U) /*!< Bit mask for SIM_SDID_SUBFAMID. */ -#define BS_SIM_SDID_SUBFAMID (4U) /*!< Bit field size in bits for SIM_SDID_SUBFAMID. */ - -/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */ -#define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID) -/*@}*/ - -/*! - * @name Register SIM_SDID, field FAMILYID[31:28] (RO) - * - * Specifies the Kinetis family of the device. - * - * Values: - * - 0001 - K1x Family - * - 0010 - K2x Family - * - 0011 - K3x Family - * - 0100 - K4x Family - * - 0110 - K6x Family - * - 0111 - K7x Family - */ -/*@{*/ -#define BP_SIM_SDID_FAMILYID (28U) /*!< Bit position for SIM_SDID_FAMILYID. */ -#define BM_SIM_SDID_FAMILYID (0xF0000000U) /*!< Bit mask for SIM_SDID_FAMILYID. */ -#define BS_SIM_SDID_FAMILYID (4U) /*!< Bit field size in bits for SIM_SDID_FAMILYID. */ - -/*! @brief Read current value of the SIM_SDID_FAMILYID field. */ -#define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC1 - System Clock Gating Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_scgc1 -{ - uint32_t U; - struct _hw_sim_scgc1_bitfields - { - uint32_t RESERVED0 : 6; /*!< [5:0] */ - uint32_t I2C2b : 1; /*!< [6] I2C2 Clock Gate Control */ - uint32_t RESERVED1 : 3; /*!< [9:7] */ - uint32_t UART4b : 1; /*!< [10] UART4 Clock Gate Control */ - uint32_t UART5b : 1; /*!< [11] UART5 Clock Gate Control */ - uint32_t RESERVED2 : 20; /*!< [31:12] */ - } B; -} hw_sim_scgc1_t; - -/*! - * @name Constants and macros for entire SIM_SCGC1 register - */ -/*@{*/ -#define HW_SIM_SCGC1_ADDR(x) ((x) + 0x1028U) - -#define HW_SIM_SCGC1(x) (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR(x)) -#define HW_SIM_SCGC1_RD(x) (HW_SIM_SCGC1(x).U) -#define HW_SIM_SCGC1_WR(x, v) (HW_SIM_SCGC1(x).U = (v)) -#define HW_SIM_SCGC1_SET(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) | (v))) -#define HW_SIM_SCGC1_CLR(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v))) -#define HW_SIM_SCGC1_TOG(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC1 bitfields - */ - -/*! - * @name Register SIM_SCGC1, field I2C2[6] (RW) - * - * This bit controls the clock gate to the I2C2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC1_I2C2 (6U) /*!< Bit position for SIM_SCGC1_I2C2. */ -#define BM_SIM_SCGC1_I2C2 (0x00000040U) /*!< Bit mask for SIM_SCGC1_I2C2. */ -#define BS_SIM_SCGC1_I2C2 (1U) /*!< Bit field size in bits for SIM_SCGC1_I2C2. */ - -/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */ -#define BR_SIM_SCGC1_I2C2(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2)) - -/*! @brief Format value for bitfield SIM_SCGC1_I2C2. */ -#define BF_SIM_SCGC1_I2C2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_I2C2) & BM_SIM_SCGC1_I2C2) - -/*! @brief Set the I2C2 field to a new value. */ -#define BW_SIM_SCGC1_I2C2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC1, field UART4[10] (RW) - * - * This bit controls the clock gate to the UART4 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC1_UART4 (10U) /*!< Bit position for SIM_SCGC1_UART4. */ -#define BM_SIM_SCGC1_UART4 (0x00000400U) /*!< Bit mask for SIM_SCGC1_UART4. */ -#define BS_SIM_SCGC1_UART4 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART4. */ - -/*! @brief Read current value of the SIM_SCGC1_UART4 field. */ -#define BR_SIM_SCGC1_UART4(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4)) - -/*! @brief Format value for bitfield SIM_SCGC1_UART4. */ -#define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4) - -/*! @brief Set the UART4 field to a new value. */ -#define BW_SIM_SCGC1_UART4(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC1, field UART5[11] (RW) - * - * This bit controls the clock gate to the UART5 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC1_UART5 (11U) /*!< Bit position for SIM_SCGC1_UART5. */ -#define BM_SIM_SCGC1_UART5 (0x00000800U) /*!< Bit mask for SIM_SCGC1_UART5. */ -#define BS_SIM_SCGC1_UART5 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART5. */ - -/*! @brief Read current value of the SIM_SCGC1_UART5 field. */ -#define BR_SIM_SCGC1_UART5(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5)) - -/*! @brief Format value for bitfield SIM_SCGC1_UART5. */ -#define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5) - -/*! @brief Set the UART5 field to a new value. */ -#define BW_SIM_SCGC1_UART5(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC2 - System Clock Gating Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW) - * - * Reset value: 0x00000000U - * - * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through - * AIPS1, define the clock gate control bits in the SCGC2. When accessing through - * AIPS0, define the clock gate control bits in SCGC6. - */ -typedef union _hw_sim_scgc2 -{ - uint32_t U; - struct _hw_sim_scgc2_bitfields - { - uint32_t ENETb : 1; /*!< [0] ENET Clock Gate Control */ - uint32_t RESERVED0 : 11; /*!< [11:1] */ - uint32_t DAC0b : 1; /*!< [12] DAC0 Clock Gate Control */ - uint32_t DAC1b : 1; /*!< [13] DAC1 Clock Gate Control */ - uint32_t RESERVED1 : 18; /*!< [31:14] */ - } B; -} hw_sim_scgc2_t; - -/*! - * @name Constants and macros for entire SIM_SCGC2 register - */ -/*@{*/ -#define HW_SIM_SCGC2_ADDR(x) ((x) + 0x102CU) - -#define HW_SIM_SCGC2(x) (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR(x)) -#define HW_SIM_SCGC2_RD(x) (HW_SIM_SCGC2(x).U) -#define HW_SIM_SCGC2_WR(x, v) (HW_SIM_SCGC2(x).U = (v)) -#define HW_SIM_SCGC2_SET(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) | (v))) -#define HW_SIM_SCGC2_CLR(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v))) -#define HW_SIM_SCGC2_TOG(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC2 bitfields - */ - -/*! - * @name Register SIM_SCGC2, field ENET[0] (RW) - * - * This bit controls the clock gate to the ENET module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC2_ENET (0U) /*!< Bit position for SIM_SCGC2_ENET. */ -#define BM_SIM_SCGC2_ENET (0x00000001U) /*!< Bit mask for SIM_SCGC2_ENET. */ -#define BS_SIM_SCGC2_ENET (1U) /*!< Bit field size in bits for SIM_SCGC2_ENET. */ - -/*! @brief Read current value of the SIM_SCGC2_ENET field. */ -#define BR_SIM_SCGC2_ENET(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET)) - -/*! @brief Format value for bitfield SIM_SCGC2_ENET. */ -#define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET) - -/*! @brief Set the ENET field to a new value. */ -#define BW_SIM_SCGC2_ENET(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC2, field DAC0[12] (RW) - * - * This bit controls the clock gate to the DAC0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC2_DAC0 (12U) /*!< Bit position for SIM_SCGC2_DAC0. */ -#define BM_SIM_SCGC2_DAC0 (0x00001000U) /*!< Bit mask for SIM_SCGC2_DAC0. */ -#define BS_SIM_SCGC2_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC0. */ - -/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */ -#define BR_SIM_SCGC2_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0)) - -/*! @brief Format value for bitfield SIM_SCGC2_DAC0. */ -#define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0) - -/*! @brief Set the DAC0 field to a new value. */ -#define BW_SIM_SCGC2_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC2, field DAC1[13] (RW) - * - * This bit controls the clock gate to the DAC1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC2_DAC1 (13U) /*!< Bit position for SIM_SCGC2_DAC1. */ -#define BM_SIM_SCGC2_DAC1 (0x00002000U) /*!< Bit mask for SIM_SCGC2_DAC1. */ -#define BS_SIM_SCGC2_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC1. */ - -/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */ -#define BR_SIM_SCGC2_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1)) - -/*! @brief Format value for bitfield SIM_SCGC2_DAC1. */ -#define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1) - -/*! @brief Set the DAC1 field to a new value. */ -#define BW_SIM_SCGC2_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC3 - System Clock Gating Control Register 3 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW) - * - * Reset value: 0x00000000U - * - * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing - * through AIPS1, define the clock gate control bits in the SCGC3. When accessing - * through AIPS0, define the clock gate control bits in SCGC6. - */ -typedef union _hw_sim_scgc3 -{ - uint32_t U; - struct _hw_sim_scgc3_bitfields - { - uint32_t RNGA : 1; /*!< [0] RNGA Clock Gate Control */ - uint32_t RESERVED0 : 11; /*!< [11:1] */ - uint32_t SPI2b : 1; /*!< [12] SPI2 Clock Gate Control */ - uint32_t RESERVED1 : 4; /*!< [16:13] */ - uint32_t SDHCb : 1; /*!< [17] SDHC Clock Gate Control */ - uint32_t RESERVED2 : 6; /*!< [23:18] */ - uint32_t FTM2b : 1; /*!< [24] FTM2 Clock Gate Control */ - uint32_t FTM3b : 1; /*!< [25] FTM3 Clock Gate Control */ - uint32_t RESERVED3 : 1; /*!< [26] */ - uint32_t ADC1b : 1; /*!< [27] ADC1 Clock Gate Control */ - uint32_t RESERVED4 : 4; /*!< [31:28] */ - } B; -} hw_sim_scgc3_t; - -/*! - * @name Constants and macros for entire SIM_SCGC3 register - */ -/*@{*/ -#define HW_SIM_SCGC3_ADDR(x) ((x) + 0x1030U) - -#define HW_SIM_SCGC3(x) (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR(x)) -#define HW_SIM_SCGC3_RD(x) (HW_SIM_SCGC3(x).U) -#define HW_SIM_SCGC3_WR(x, v) (HW_SIM_SCGC3(x).U = (v)) -#define HW_SIM_SCGC3_SET(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) | (v))) -#define HW_SIM_SCGC3_CLR(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v))) -#define HW_SIM_SCGC3_TOG(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC3 bitfields - */ - -/*! - * @name Register SIM_SCGC3, field RNGA[0] (RW) - * - * This bit controls the clock gate to the RNGA module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC3_RNGA (0U) /*!< Bit position for SIM_SCGC3_RNGA. */ -#define BM_SIM_SCGC3_RNGA (0x00000001U) /*!< Bit mask for SIM_SCGC3_RNGA. */ -#define BS_SIM_SCGC3_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC3_RNGA. */ - -/*! @brief Read current value of the SIM_SCGC3_RNGA field. */ -#define BR_SIM_SCGC3_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA)) - -/*! @brief Format value for bitfield SIM_SCGC3_RNGA. */ -#define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA) - -/*! @brief Set the RNGA field to a new value. */ -#define BW_SIM_SCGC3_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC3, field SPI2[12] (RW) - * - * This bit controls the clock gate to the SPI2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC3_SPI2 (12U) /*!< Bit position for SIM_SCGC3_SPI2. */ -#define BM_SIM_SCGC3_SPI2 (0x00001000U) /*!< Bit mask for SIM_SCGC3_SPI2. */ -#define BS_SIM_SCGC3_SPI2 (1U) /*!< Bit field size in bits for SIM_SCGC3_SPI2. */ - -/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */ -#define BR_SIM_SCGC3_SPI2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2)) - -/*! @brief Format value for bitfield SIM_SCGC3_SPI2. */ -#define BF_SIM_SCGC3_SPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SPI2) & BM_SIM_SCGC3_SPI2) - -/*! @brief Set the SPI2 field to a new value. */ -#define BW_SIM_SCGC3_SPI2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC3, field SDHC[17] (RW) - * - * This bit controls the clock gate to the SDHC module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC3_SDHC (17U) /*!< Bit position for SIM_SCGC3_SDHC. */ -#define BM_SIM_SCGC3_SDHC (0x00020000U) /*!< Bit mask for SIM_SCGC3_SDHC. */ -#define BS_SIM_SCGC3_SDHC (1U) /*!< Bit field size in bits for SIM_SCGC3_SDHC. */ - -/*! @brief Read current value of the SIM_SCGC3_SDHC field. */ -#define BR_SIM_SCGC3_SDHC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC)) - -/*! @brief Format value for bitfield SIM_SCGC3_SDHC. */ -#define BF_SIM_SCGC3_SDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SDHC) & BM_SIM_SCGC3_SDHC) - -/*! @brief Set the SDHC field to a new value. */ -#define BW_SIM_SCGC3_SDHC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC3, field FTM2[24] (RW) - * - * This bit controls the clock gate to the FTM2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC3_FTM2 (24U) /*!< Bit position for SIM_SCGC3_FTM2. */ -#define BM_SIM_SCGC3_FTM2 (0x01000000U) /*!< Bit mask for SIM_SCGC3_FTM2. */ -#define BS_SIM_SCGC3_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM2. */ - -/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */ -#define BR_SIM_SCGC3_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2)) - -/*! @brief Format value for bitfield SIM_SCGC3_FTM2. */ -#define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2) - -/*! @brief Set the FTM2 field to a new value. */ -#define BW_SIM_SCGC3_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC3, field FTM3[25] (RW) - * - * This bit controls the clock gate to the FTM3 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC3_FTM3 (25U) /*!< Bit position for SIM_SCGC3_FTM3. */ -#define BM_SIM_SCGC3_FTM3 (0x02000000U) /*!< Bit mask for SIM_SCGC3_FTM3. */ -#define BS_SIM_SCGC3_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM3. */ - -/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */ -#define BR_SIM_SCGC3_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3)) - -/*! @brief Format value for bitfield SIM_SCGC3_FTM3. */ -#define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3) - -/*! @brief Set the FTM3 field to a new value. */ -#define BW_SIM_SCGC3_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC3, field ADC1[27] (RW) - * - * This bit controls the clock gate to the ADC1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC3_ADC1 (27U) /*!< Bit position for SIM_SCGC3_ADC1. */ -#define BM_SIM_SCGC3_ADC1 (0x08000000U) /*!< Bit mask for SIM_SCGC3_ADC1. */ -#define BS_SIM_SCGC3_ADC1 (1U) /*!< Bit field size in bits for SIM_SCGC3_ADC1. */ - -/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */ -#define BR_SIM_SCGC3_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1)) - -/*! @brief Format value for bitfield SIM_SCGC3_ADC1. */ -#define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1) - -/*! @brief Set the ADC1 field to a new value. */ -#define BW_SIM_SCGC3_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC4 - System Clock Gating Control Register 4 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW) - * - * Reset value: 0xF0100030U - */ -typedef union _hw_sim_scgc4 -{ - uint32_t U; - struct _hw_sim_scgc4_bitfields - { - uint32_t RESERVED0 : 1; /*!< [0] */ - uint32_t EWMb : 1; /*!< [1] EWM Clock Gate Control */ - uint32_t CMTb : 1; /*!< [2] CMT Clock Gate Control */ - uint32_t RESERVED1 : 3; /*!< [5:3] */ - uint32_t I2C0b : 1; /*!< [6] I2C0 Clock Gate Control */ - uint32_t I2C1b : 1; /*!< [7] I2C1 Clock Gate Control */ - uint32_t RESERVED2 : 2; /*!< [9:8] */ - uint32_t UART0b : 1; /*!< [10] UART0 Clock Gate Control */ - uint32_t UART1b : 1; /*!< [11] UART1 Clock Gate Control */ - uint32_t UART2b : 1; /*!< [12] UART2 Clock Gate Control */ - uint32_t UART3b : 1; /*!< [13] UART3 Clock Gate Control */ - uint32_t RESERVED3 : 4; /*!< [17:14] */ - uint32_t USBOTG : 1; /*!< [18] USB Clock Gate Control */ - uint32_t CMP : 1; /*!< [19] Comparator Clock Gate Control */ - uint32_t VREFb : 1; /*!< [20] VREF Clock Gate Control */ - uint32_t RESERVED4 : 11; /*!< [31:21] */ - } B; -} hw_sim_scgc4_t; - -/*! - * @name Constants and macros for entire SIM_SCGC4 register - */ -/*@{*/ -#define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U) - -#define HW_SIM_SCGC4(x) (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x)) -#define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U) -#define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v)) -#define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) | (v))) -#define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v))) -#define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC4 bitfields - */ - -/*! - * @name Register SIM_SCGC4, field EWM[1] (RW) - * - * This bit controls the clock gate to the EWM module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_EWM (1U) /*!< Bit position for SIM_SCGC4_EWM. */ -#define BM_SIM_SCGC4_EWM (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */ -#define BS_SIM_SCGC4_EWM (1U) /*!< Bit field size in bits for SIM_SCGC4_EWM. */ - -/*! @brief Read current value of the SIM_SCGC4_EWM field. */ -#define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM)) - -/*! @brief Format value for bitfield SIM_SCGC4_EWM. */ -#define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM) - -/*! @brief Set the EWM field to a new value. */ -#define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field CMT[2] (RW) - * - * This bit controls the clock gate to the CMT module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_CMT (2U) /*!< Bit position for SIM_SCGC4_CMT. */ -#define BM_SIM_SCGC4_CMT (0x00000004U) /*!< Bit mask for SIM_SCGC4_CMT. */ -#define BS_SIM_SCGC4_CMT (1U) /*!< Bit field size in bits for SIM_SCGC4_CMT. */ - -/*! @brief Read current value of the SIM_SCGC4_CMT field. */ -#define BR_SIM_SCGC4_CMT(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT)) - -/*! @brief Format value for bitfield SIM_SCGC4_CMT. */ -#define BF_SIM_SCGC4_CMT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT) - -/*! @brief Set the CMT field to a new value. */ -#define BW_SIM_SCGC4_CMT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field I2C0[6] (RW) - * - * This bit controls the clock gate to the I 2 C0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_I2C0 (6U) /*!< Bit position for SIM_SCGC4_I2C0. */ -#define BM_SIM_SCGC4_I2C0 (0x00000040U) /*!< Bit mask for SIM_SCGC4_I2C0. */ -#define BS_SIM_SCGC4_I2C0 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C0. */ - -/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */ -#define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0)) - -/*! @brief Format value for bitfield SIM_SCGC4_I2C0. */ -#define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0) - -/*! @brief Set the I2C0 field to a new value. */ -#define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field I2C1[7] (RW) - * - * This bit controls the clock gate to the I 2 C1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_I2C1 (7U) /*!< Bit position for SIM_SCGC4_I2C1. */ -#define BM_SIM_SCGC4_I2C1 (0x00000080U) /*!< Bit mask for SIM_SCGC4_I2C1. */ -#define BS_SIM_SCGC4_I2C1 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C1. */ - -/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */ -#define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1)) - -/*! @brief Format value for bitfield SIM_SCGC4_I2C1. */ -#define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1) - -/*! @brief Set the I2C1 field to a new value. */ -#define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART0[10] (RW) - * - * This bit controls the clock gate to the UART0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART0 (10U) /*!< Bit position for SIM_SCGC4_UART0. */ -#define BM_SIM_SCGC4_UART0 (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */ -#define BS_SIM_SCGC4_UART0 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART0. */ - -/*! @brief Read current value of the SIM_SCGC4_UART0 field. */ -#define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART0. */ -#define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0) - -/*! @brief Set the UART0 field to a new value. */ -#define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART1[11] (RW) - * - * This bit controls the clock gate to the UART1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART1 (11U) /*!< Bit position for SIM_SCGC4_UART1. */ -#define BM_SIM_SCGC4_UART1 (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */ -#define BS_SIM_SCGC4_UART1 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART1. */ - -/*! @brief Read current value of the SIM_SCGC4_UART1 field. */ -#define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART1. */ -#define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1) - -/*! @brief Set the UART1 field to a new value. */ -#define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART2[12] (RW) - * - * This bit controls the clock gate to the UART2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART2 (12U) /*!< Bit position for SIM_SCGC4_UART2. */ -#define BM_SIM_SCGC4_UART2 (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */ -#define BS_SIM_SCGC4_UART2 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART2. */ - -/*! @brief Read current value of the SIM_SCGC4_UART2 field. */ -#define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART2. */ -#define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2) - -/*! @brief Set the UART2 field to a new value. */ -#define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field UART3[13] (RW) - * - * This bit controls the clock gate to the UART3 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_UART3 (13U) /*!< Bit position for SIM_SCGC4_UART3. */ -#define BM_SIM_SCGC4_UART3 (0x00002000U) /*!< Bit mask for SIM_SCGC4_UART3. */ -#define BS_SIM_SCGC4_UART3 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART3. */ - -/*! @brief Read current value of the SIM_SCGC4_UART3 field. */ -#define BR_SIM_SCGC4_UART3(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3)) - -/*! @brief Format value for bitfield SIM_SCGC4_UART3. */ -#define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3) - -/*! @brief Set the UART3 field to a new value. */ -#define BW_SIM_SCGC4_UART3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field USBOTG[18] (RW) - * - * This bit controls the clock gate to the USB module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_USBOTG (18U) /*!< Bit position for SIM_SCGC4_USBOTG. */ -#define BM_SIM_SCGC4_USBOTG (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBOTG. */ -#define BS_SIM_SCGC4_USBOTG (1U) /*!< Bit field size in bits for SIM_SCGC4_USBOTG. */ - -/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */ -#define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG)) - -/*! @brief Format value for bitfield SIM_SCGC4_USBOTG. */ -#define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG) - -/*! @brief Set the USBOTG field to a new value. */ -#define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field CMP[19] (RW) - * - * This bit controls the clock gate to the comparator module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_CMP (19U) /*!< Bit position for SIM_SCGC4_CMP. */ -#define BM_SIM_SCGC4_CMP (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */ -#define BS_SIM_SCGC4_CMP (1U) /*!< Bit field size in bits for SIM_SCGC4_CMP. */ - -/*! @brief Read current value of the SIM_SCGC4_CMP field. */ -#define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP)) - -/*! @brief Format value for bitfield SIM_SCGC4_CMP. */ -#define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP) - -/*! @brief Set the CMP field to a new value. */ -#define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC4, field VREF[20] (RW) - * - * This bit controls the clock gate to the VREF module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC4_VREF (20U) /*!< Bit position for SIM_SCGC4_VREF. */ -#define BM_SIM_SCGC4_VREF (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */ -#define BS_SIM_SCGC4_VREF (1U) /*!< Bit field size in bits for SIM_SCGC4_VREF. */ - -/*! @brief Read current value of the SIM_SCGC4_VREF field. */ -#define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF)) - -/*! @brief Format value for bitfield SIM_SCGC4_VREF. */ -#define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF) - -/*! @brief Set the VREF field to a new value. */ -#define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC5 - System Clock Gating Control Register 5 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW) - * - * Reset value: 0x00040182U - */ -typedef union _hw_sim_scgc5 -{ - uint32_t U; - struct _hw_sim_scgc5_bitfields - { - uint32_t LPTMR : 1; /*!< [0] Low Power Timer Access Control */ - uint32_t RESERVED0 : 8; /*!< [8:1] */ - uint32_t PORTAb : 1; /*!< [9] Port A Clock Gate Control */ - uint32_t PORTBb : 1; /*!< [10] Port B Clock Gate Control */ - uint32_t PORTCb : 1; /*!< [11] Port C Clock Gate Control */ - uint32_t PORTDb : 1; /*!< [12] Port D Clock Gate Control */ - uint32_t PORTEb : 1; /*!< [13] Port E Clock Gate Control */ - uint32_t RESERVED1 : 18; /*!< [31:14] */ - } B; -} hw_sim_scgc5_t; - -/*! - * @name Constants and macros for entire SIM_SCGC5 register - */ -/*@{*/ -#define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U) - -#define HW_SIM_SCGC5(x) (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x)) -#define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U) -#define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v)) -#define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) | (v))) -#define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v))) -#define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC5 bitfields - */ - -/*! - * @name Register SIM_SCGC5, field LPTMR[0] (RW) - * - * This bit controls software access to the Low Power Timer module. - * - * Values: - * - 0 - Access disabled - * - 1 - Access enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_LPTMR (0U) /*!< Bit position for SIM_SCGC5_LPTMR. */ -#define BM_SIM_SCGC5_LPTMR (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTMR. */ -#define BS_SIM_SCGC5_LPTMR (1U) /*!< Bit field size in bits for SIM_SCGC5_LPTMR. */ - -/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */ -#define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR)) - -/*! @brief Format value for bitfield SIM_SCGC5_LPTMR. */ -#define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR) - -/*! @brief Set the LPTMR field to a new value. */ -#define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTA[9] (RW) - * - * This bit controls the clock gate to the Port A module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTA (9U) /*!< Bit position for SIM_SCGC5_PORTA. */ -#define BM_SIM_SCGC5_PORTA (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */ -#define BS_SIM_SCGC5_PORTA (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTA. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTA field. */ -#define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTA. */ -#define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA) - -/*! @brief Set the PORTA field to a new value. */ -#define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTB[10] (RW) - * - * This bit controls the clock gate to the Port B module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTB (10U) /*!< Bit position for SIM_SCGC5_PORTB. */ -#define BM_SIM_SCGC5_PORTB (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */ -#define BS_SIM_SCGC5_PORTB (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTB. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTB field. */ -#define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTB. */ -#define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB) - -/*! @brief Set the PORTB field to a new value. */ -#define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTC[11] (RW) - * - * This bit controls the clock gate to the Port C module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTC (11U) /*!< Bit position for SIM_SCGC5_PORTC. */ -#define BM_SIM_SCGC5_PORTC (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */ -#define BS_SIM_SCGC5_PORTC (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTC. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTC field. */ -#define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTC. */ -#define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC) - -/*! @brief Set the PORTC field to a new value. */ -#define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTD[12] (RW) - * - * This bit controls the clock gate to the Port D module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTD (12U) /*!< Bit position for SIM_SCGC5_PORTD. */ -#define BM_SIM_SCGC5_PORTD (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */ -#define BS_SIM_SCGC5_PORTD (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTD. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTD field. */ -#define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTD. */ -#define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD) - -/*! @brief Set the PORTD field to a new value. */ -#define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC5, field PORTE[13] (RW) - * - * This bit controls the clock gate to the Port E module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC5_PORTE (13U) /*!< Bit position for SIM_SCGC5_PORTE. */ -#define BM_SIM_SCGC5_PORTE (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */ -#define BS_SIM_SCGC5_PORTE (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTE. */ - -/*! @brief Read current value of the SIM_SCGC5_PORTE field. */ -#define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE)) - -/*! @brief Format value for bitfield SIM_SCGC5_PORTE. */ -#define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE) - -/*! @brief Set the PORTE field to a new value. */ -#define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC6 - System Clock Gating Control Register 6 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW) - * - * Reset value: 0x40000001U - * - * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When - * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3. - * When accessing through AIPS0, define the clock gate control bits in SCGC6. - */ -typedef union _hw_sim_scgc6 -{ - uint32_t U; - struct _hw_sim_scgc6_bitfields - { - uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */ - uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */ - uint32_t RESERVED0 : 2; /*!< [3:2] */ - uint32_t FLEXCAN0 : 1; /*!< [4] FlexCAN0 Clock Gate Control */ - uint32_t RESERVED1 : 4; /*!< [8:5] */ - uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */ - uint32_t RESERVED2 : 2; /*!< [11:10] */ - uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */ - uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */ - uint32_t RESERVED3 : 1; /*!< [14] */ - uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */ - uint32_t RESERVED4 : 2; /*!< [17:16] */ - uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */ - uint32_t RESERVED5 : 2; /*!< [20:19] */ - uint32_t USBDCDb : 1; /*!< [21] USB DCD Clock Gate Control */ - uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */ - uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */ - uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */ - uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */ - uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */ - uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */ - uint32_t RESERVED6 : 1; /*!< [28] */ - uint32_t RTCb : 1; /*!< [29] RTC Access Control */ - uint32_t RESERVED7 : 1; /*!< [30] */ - uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */ - } B; -} hw_sim_scgc6_t; - -/*! - * @name Constants and macros for entire SIM_SCGC6 register - */ -/*@{*/ -#define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU) - -#define HW_SIM_SCGC6(x) (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x)) -#define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U) -#define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v)) -#define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) | (v))) -#define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v))) -#define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC6 bitfields - */ - -/*! - * @name Register SIM_SCGC6, field FTF[0] (RW) - * - * This bit controls the clock gate to the flash memory. Flash reads are still - * supported while the flash memory is clock gated, but entry into low power modes - * is blocked. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTF (0U) /*!< Bit position for SIM_SCGC6_FTF. */ -#define BM_SIM_SCGC6_FTF (0x00000001U) /*!< Bit mask for SIM_SCGC6_FTF. */ -#define BS_SIM_SCGC6_FTF (1U) /*!< Bit field size in bits for SIM_SCGC6_FTF. */ - -/*! @brief Read current value of the SIM_SCGC6_FTF field. */ -#define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTF. */ -#define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF) - -/*! @brief Set the FTF field to a new value. */ -#define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field DMAMUX[1] (RW) - * - * This bit controls the clock gate to the DMA Mux module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_DMAMUX (1U) /*!< Bit position for SIM_SCGC6_DMAMUX. */ -#define BM_SIM_SCGC6_DMAMUX (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX. */ -#define BS_SIM_SCGC6_DMAMUX (1U) /*!< Bit field size in bits for SIM_SCGC6_DMAMUX. */ - -/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */ -#define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX)) - -/*! @brief Format value for bitfield SIM_SCGC6_DMAMUX. */ -#define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX) - -/*! @brief Set the DMAMUX field to a new value. */ -#define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW) - * - * This bit controls the clock gate to the FlexCAN0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FLEXCAN0 (4U) /*!< Bit position for SIM_SCGC6_FLEXCAN0. */ -#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /*!< Bit mask for SIM_SCGC6_FLEXCAN0. */ -#define BS_SIM_SCGC6_FLEXCAN0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. */ - -/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */ -#define BR_SIM_SCGC6_FLEXCAN0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0)) - -/*! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. */ -#define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0) - -/*! @brief Set the FLEXCAN0 field to a new value. */ -#define BW_SIM_SCGC6_FLEXCAN0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field RNGA[9] (RW) - * - * This bit controls the clock gate to the RNGA module. - */ -/*@{*/ -#define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */ -#define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */ -#define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */ - -/*! @brief Read current value of the SIM_SCGC6_RNGA field. */ -#define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA)) - -/*! @brief Format value for bitfield SIM_SCGC6_RNGA. */ -#define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA) - -/*! @brief Set the RNGA field to a new value. */ -#define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field SPI0[12] (RW) - * - * This bit controls the clock gate to the SPI0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_SPI0 (12U) /*!< Bit position for SIM_SCGC6_SPI0. */ -#define BM_SIM_SCGC6_SPI0 (0x00001000U) /*!< Bit mask for SIM_SCGC6_SPI0. */ -#define BS_SIM_SCGC6_SPI0 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI0. */ - -/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */ -#define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0)) - -/*! @brief Format value for bitfield SIM_SCGC6_SPI0. */ -#define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0) - -/*! @brief Set the SPI0 field to a new value. */ -#define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field SPI1[13] (RW) - * - * This bit controls the clock gate to the SPI1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_SPI1 (13U) /*!< Bit position for SIM_SCGC6_SPI1. */ -#define BM_SIM_SCGC6_SPI1 (0x00002000U) /*!< Bit mask for SIM_SCGC6_SPI1. */ -#define BS_SIM_SCGC6_SPI1 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI1. */ - -/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */ -#define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1)) - -/*! @brief Format value for bitfield SIM_SCGC6_SPI1. */ -#define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1) - -/*! @brief Set the SPI1 field to a new value. */ -#define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field I2S[15] (RW) - * - * This bit controls the clock gate to the I 2 S module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_I2S (15U) /*!< Bit position for SIM_SCGC6_I2S. */ -#define BM_SIM_SCGC6_I2S (0x00008000U) /*!< Bit mask for SIM_SCGC6_I2S. */ -#define BS_SIM_SCGC6_I2S (1U) /*!< Bit field size in bits for SIM_SCGC6_I2S. */ - -/*! @brief Read current value of the SIM_SCGC6_I2S field. */ -#define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S)) - -/*! @brief Format value for bitfield SIM_SCGC6_I2S. */ -#define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S) - -/*! @brief Set the I2S field to a new value. */ -#define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field CRC[18] (RW) - * - * This bit controls the clock gate to the CRC module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_CRC (18U) /*!< Bit position for SIM_SCGC6_CRC. */ -#define BM_SIM_SCGC6_CRC (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */ -#define BS_SIM_SCGC6_CRC (1U) /*!< Bit field size in bits for SIM_SCGC6_CRC. */ - -/*! @brief Read current value of the SIM_SCGC6_CRC field. */ -#define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC)) - -/*! @brief Format value for bitfield SIM_SCGC6_CRC. */ -#define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC) - -/*! @brief Set the CRC field to a new value. */ -#define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field USBDCD[21] (RW) - * - * This bit controls the clock gate to the USB DCD module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_USBDCD (21U) /*!< Bit position for SIM_SCGC6_USBDCD. */ -#define BM_SIM_SCGC6_USBDCD (0x00200000U) /*!< Bit mask for SIM_SCGC6_USBDCD. */ -#define BS_SIM_SCGC6_USBDCD (1U) /*!< Bit field size in bits for SIM_SCGC6_USBDCD. */ - -/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */ -#define BR_SIM_SCGC6_USBDCD(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD)) - -/*! @brief Format value for bitfield SIM_SCGC6_USBDCD. */ -#define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD) - -/*! @brief Set the USBDCD field to a new value. */ -#define BW_SIM_SCGC6_USBDCD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field PDB[22] (RW) - * - * This bit controls the clock gate to the PDB module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_PDB (22U) /*!< Bit position for SIM_SCGC6_PDB. */ -#define BM_SIM_SCGC6_PDB (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */ -#define BS_SIM_SCGC6_PDB (1U) /*!< Bit field size in bits for SIM_SCGC6_PDB. */ - -/*! @brief Read current value of the SIM_SCGC6_PDB field. */ -#define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB)) - -/*! @brief Format value for bitfield SIM_SCGC6_PDB. */ -#define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB) - -/*! @brief Set the PDB field to a new value. */ -#define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field PIT[23] (RW) - * - * This bit controls the clock gate to the PIT module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_PIT (23U) /*!< Bit position for SIM_SCGC6_PIT. */ -#define BM_SIM_SCGC6_PIT (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */ -#define BS_SIM_SCGC6_PIT (1U) /*!< Bit field size in bits for SIM_SCGC6_PIT. */ - -/*! @brief Read current value of the SIM_SCGC6_PIT field. */ -#define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT)) - -/*! @brief Format value for bitfield SIM_SCGC6_PIT. */ -#define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT) - -/*! @brief Set the PIT field to a new value. */ -#define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM0[24] (RW) - * - * This bit controls the clock gate to the FTM0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM0 (24U) /*!< Bit position for SIM_SCGC6_FTM0. */ -#define BM_SIM_SCGC6_FTM0 (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */ -#define BS_SIM_SCGC6_FTM0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM0. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */ -#define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM0. */ -#define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0) - -/*! @brief Set the FTM0 field to a new value. */ -#define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM1[25] (RW) - * - * This bit controls the clock gate to the FTM1 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM1 (25U) /*!< Bit position for SIM_SCGC6_FTM1. */ -#define BM_SIM_SCGC6_FTM1 (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */ -#define BS_SIM_SCGC6_FTM1 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM1. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */ -#define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM1. */ -#define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1) - -/*! @brief Set the FTM1 field to a new value. */ -#define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field FTM2[26] (RW) - * - * This bit controls the clock gate to the FTM2 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_FTM2 (26U) /*!< Bit position for SIM_SCGC6_FTM2. */ -#define BM_SIM_SCGC6_FTM2 (0x04000000U) /*!< Bit mask for SIM_SCGC6_FTM2. */ -#define BS_SIM_SCGC6_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM2. */ - -/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */ -#define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2)) - -/*! @brief Format value for bitfield SIM_SCGC6_FTM2. */ -#define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2) - -/*! @brief Set the FTM2 field to a new value. */ -#define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field ADC0[27] (RW) - * - * This bit controls the clock gate to the ADC0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_ADC0 (27U) /*!< Bit position for SIM_SCGC6_ADC0. */ -#define BM_SIM_SCGC6_ADC0 (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */ -#define BS_SIM_SCGC6_ADC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC0. */ - -/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */ -#define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0)) - -/*! @brief Format value for bitfield SIM_SCGC6_ADC0. */ -#define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0) - -/*! @brief Set the ADC0 field to a new value. */ -#define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field RTC[29] (RW) - * - * This bit controls software access and interrupts to the RTC module. - * - * Values: - * - 0 - Access and interrupts disabled - * - 1 - Access and interrupts enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_RTC (29U) /*!< Bit position for SIM_SCGC6_RTC. */ -#define BM_SIM_SCGC6_RTC (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */ -#define BS_SIM_SCGC6_RTC (1U) /*!< Bit field size in bits for SIM_SCGC6_RTC. */ - -/*! @brief Read current value of the SIM_SCGC6_RTC field. */ -#define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC)) - -/*! @brief Format value for bitfield SIM_SCGC6_RTC. */ -#define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC) - -/*! @brief Set the RTC field to a new value. */ -#define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC6, field DAC0[31] (RW) - * - * This bit controls the clock gate to the DAC0 module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC6_DAC0 (31U) /*!< Bit position for SIM_SCGC6_DAC0. */ -#define BM_SIM_SCGC6_DAC0 (0x80000000U) /*!< Bit mask for SIM_SCGC6_DAC0. */ -#define BS_SIM_SCGC6_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC0. */ - -/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */ -#define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0)) - -/*! @brief Format value for bitfield SIM_SCGC6_DAC0. */ -#define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0) - -/*! @brief Set the DAC0 field to a new value. */ -#define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_SCGC7 - System Clock Gating Control Register 7 - ******************************************************************************/ - -/*! - * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW) - * - * Reset value: 0x00000006U - */ -typedef union _hw_sim_scgc7 -{ - uint32_t U; - struct _hw_sim_scgc7_bitfields - { - uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */ - uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */ - uint32_t MPUb : 1; /*!< [2] MPU Clock Gate Control */ - uint32_t RESERVED0 : 29; /*!< [31:3] */ - } B; -} hw_sim_scgc7_t; - -/*! - * @name Constants and macros for entire SIM_SCGC7 register - */ -/*@{*/ -#define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U) - -#define HW_SIM_SCGC7(x) (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x)) -#define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U) -#define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v)) -#define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) | (v))) -#define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v))) -#define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_SCGC7 bitfields - */ - -/*! - * @name Register SIM_SCGC7, field FLEXBUS[0] (RW) - * - * This bit controls the clock gate to the FlexBus module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */ -#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */ -#define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */ - -/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */ -#define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS)) - -/*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */ -#define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS) - -/*! @brief Set the FLEXBUS field to a new value. */ -#define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC7, field DMA[1] (RW) - * - * This bit controls the clock gate to the DMA module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC7_DMA (1U) /*!< Bit position for SIM_SCGC7_DMA. */ -#define BM_SIM_SCGC7_DMA (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */ -#define BS_SIM_SCGC7_DMA (1U) /*!< Bit field size in bits for SIM_SCGC7_DMA. */ - -/*! @brief Read current value of the SIM_SCGC7_DMA field. */ -#define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA)) - -/*! @brief Format value for bitfield SIM_SCGC7_DMA. */ -#define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA) - -/*! @brief Set the DMA field to a new value. */ -#define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v)) -/*@}*/ - -/*! - * @name Register SIM_SCGC7, field MPU[2] (RW) - * - * This bit controls the clock gate to the MPU module. - * - * Values: - * - 0 - Clock disabled - * - 1 - Clock enabled - */ -/*@{*/ -#define BP_SIM_SCGC7_MPU (2U) /*!< Bit position for SIM_SCGC7_MPU. */ -#define BM_SIM_SCGC7_MPU (0x00000004U) /*!< Bit mask for SIM_SCGC7_MPU. */ -#define BS_SIM_SCGC7_MPU (1U) /*!< Bit field size in bits for SIM_SCGC7_MPU. */ - -/*! @brief Read current value of the SIM_SCGC7_MPU field. */ -#define BR_SIM_SCGC7_MPU(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU)) - -/*! @brief Format value for bitfield SIM_SCGC7_MPU. */ -#define BF_SIM_SCGC7_MPU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU) - -/*! @brief Set the MPU field to a new value. */ -#define BW_SIM_SCGC7_MPU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SIM_CLKDIV1 - System Clock Divider Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW) - * - * Reset value: 0x00010000U - * - * When updating CLKDIV1, update all fields using the one write command. - * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the - * write to be ignored. The maximum divide ratio that can be programmed between - * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals - * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide - * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR - * mode. - */ -typedef union _hw_sim_clkdiv1 -{ - uint32_t U; - struct _hw_sim_clkdiv1_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */ - uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */ - uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */ - uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */ - } B; -} hw_sim_clkdiv1_t; - -/*! - * @name Constants and macros for entire SIM_CLKDIV1 register - */ -/*@{*/ -#define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U) - -#define HW_SIM_CLKDIV1(x) (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x)) -#define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U) -#define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v)) -#define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) | (v))) -#define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v))) -#define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_CLKDIV1 bitfields - */ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW) - * - * This field sets the divide value for the flash clock from MCGOUTCLK. At the - * end of reset, it is loaded with either 0001 or 1111 depending on - * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock - * frequency. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV4 (16U) /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */ -#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */ -#define BS_SIM_CLKDIV1_OUTDIV4 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */ -#define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */ -#define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4) - -/*! @brief Set the OUTDIV4 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v))) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW) - * - * This field sets the divide value for the FlexBus clock (external pin FB_CLK) - * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 - * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer - * divide of the system clock frequency. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */ -#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */ -#define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */ -#define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */ -#define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3) - -/*! @brief Set the OUTDIV3 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v))) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW) - * - * This field sets the divide value for the bus clock from MCGOUTCLK. At the end - * of reset, it is loaded with either 0000 or 0111 depending on - * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock - * frequency. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV2 (24U) /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */ -#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */ -#define BS_SIM_CLKDIV1_OUTDIV2 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */ -#define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */ -#define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2) - -/*! @brief Set the OUTDIV2 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v))) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW) - * - * This field sets the divide value for the core/system clock from MCGOUTCLK. At - * the end of reset, it is loaded with either 0000 or 0111 depending on - * FTF_FOPT[LPBOOT]. - * - * Values: - * - 0000 - Divide-by-1. - * - 0001 - Divide-by-2. - * - 0010 - Divide-by-3. - * - 0011 - Divide-by-4. - * - 0100 - Divide-by-5. - * - 0101 - Divide-by-6. - * - 0110 - Divide-by-7. - * - 0111 - Divide-by-8. - * - 1000 - Divide-by-9. - * - 1001 - Divide-by-10. - * - 1010 - Divide-by-11. - * - 1011 - Divide-by-12. - * - 1100 - Divide-by-13. - * - 1101 - Divide-by-14. - * - 1110 - Divide-by-15. - * - 1111 - Divide-by-16. - */ -/*@{*/ -#define BP_SIM_CLKDIV1_OUTDIV1 (28U) /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */ -#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */ -#define BS_SIM_CLKDIV1_OUTDIV1 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */ - -/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */ -#define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1) - -/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */ -#define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1) - -/*! @brief Set the OUTDIV1 field to a new value. */ -#define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_CLKDIV2 - System Clock Divider Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_clkdiv2 -{ - uint32_t U; - struct _hw_sim_clkdiv2_bitfields - { - uint32_t USBFRAC : 1; /*!< [0] USB clock divider fraction */ - uint32_t USBDIV : 3; /*!< [3:1] USB clock divider divisor */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ - } B; -} hw_sim_clkdiv2_t; - -/*! - * @name Constants and macros for entire SIM_CLKDIV2 register - */ -/*@{*/ -#define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U) - -#define HW_SIM_CLKDIV2(x) (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x)) -#define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U) -#define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v)) -#define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) | (v))) -#define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v))) -#define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_CLKDIV2 bitfields - */ - -/*! - * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW) - * - * This field sets the fraction multiply value for the fractional clock divider - * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = - * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] - */ -/*@{*/ -#define BP_SIM_CLKDIV2_USBFRAC (0U) /*!< Bit position for SIM_CLKDIV2_USBFRAC. */ -#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFRAC. */ -#define BS_SIM_CLKDIV2_USBFRAC (1U) /*!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. */ - -/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */ -#define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC)) - -/*! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. */ -#define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC) - -/*! @brief Set the USBFRAC field to a new value. */ -#define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v)) -/*@}*/ - -/*! - * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW) - * - * This field sets the divide value for the fractional clock divider when the - * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider - * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] - */ -/*@{*/ -#define BP_SIM_CLKDIV2_USBDIV (1U) /*!< Bit position for SIM_CLKDIV2_USBDIV. */ -#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBDIV. */ -#define BS_SIM_CLKDIV2_USBDIV (3U) /*!< Bit field size in bits for SIM_CLKDIV2_USBDIV. */ - -/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */ -#define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV) - -/*! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. */ -#define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV) - -/*! @brief Set the USBDIV field to a new value. */ -#define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v))) -/*@}*/ - -/******************************************************************************* - * HW_SIM_FCFG1 - Flash Configuration Register 1 - ******************************************************************************/ - -/*! - * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW) - * - * Reset value: 0xFF0F0F00U - * - * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on - * user programming in user IFR via the PGMPART flash command. For devices with - * program flash only: - */ -typedef union _hw_sim_fcfg1 -{ - uint32_t U; - struct _hw_sim_fcfg1_bitfields - { - uint32_t FLASHDIS : 1; /*!< [0] Flash Disable */ - uint32_t FLASHDOZE : 1; /*!< [1] Flash Doze */ - uint32_t RESERVED0 : 6; /*!< [7:2] */ - uint32_t DEPART : 4; /*!< [11:8] FlexNVM partition */ - uint32_t RESERVED1 : 4; /*!< [15:12] */ - uint32_t EESIZE : 4; /*!< [19:16] EEPROM size */ - uint32_t RESERVED2 : 4; /*!< [23:20] */ - uint32_t PFSIZE : 4; /*!< [27:24] Program flash size */ - uint32_t NVMSIZE : 4; /*!< [31:28] FlexNVM size */ - } B; -} hw_sim_fcfg1_t; - -/*! - * @name Constants and macros for entire SIM_FCFG1 register - */ -/*@{*/ -#define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU) - -#define HW_SIM_FCFG1(x) (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x)) -#define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U) -#define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v)) -#define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) | (v))) -#define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v))) -#define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SIM_FCFG1 bitfields - */ - -/*! - * @name Register SIM_FCFG1, field FLASHDIS[0] (RW) - * - * Flash accesses are disabled (and generate a bus error) and the Flash memory - * is placed in a low power state. This bit should not be changed during VLP - * modes. Relocate the interrupt vectors out of Flash memory before disabling the - * Flash. - * - * Values: - * - 0 - Flash is enabled - * - 1 - Flash is disabled - */ -/*@{*/ -#define BP_SIM_FCFG1_FLASHDIS (0U) /*!< Bit position for SIM_FCFG1_FLASHDIS. */ -#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /*!< Bit mask for SIM_FCFG1_FLASHDIS. */ -#define BS_SIM_FCFG1_FLASHDIS (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDIS. */ - -/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */ -#define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS)) - -/*! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. */ -#define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS) - -/*! @brief Set the FLASHDIS field to a new value. */ -#define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v)) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW) - * - * When set, Flash memory is disabled for the duration of Wait mode. An attempt - * by the DMA or other bus master to access the Flash when the Flash is disabled - * will result in a bus error. This bit should be clear during VLP modes. The - * Flash will be automatically enabled again at the end of Wait mode so interrupt - * vectors do not need to be relocated out of Flash memory. The wakeup time from - * Wait mode is extended when this bit is set. - * - * Values: - * - 0 - Flash remains enabled during Wait mode - * - 1 - Flash is disabled for the duration of Wait mode - */ -/*@{*/ -#define BP_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit position for SIM_FCFG1_FLASHDOZE. */ -#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /*!< Bit mask for SIM_FCFG1_FLASHDOZE. */ -#define BS_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. */ - -/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */ -#define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE)) - -/*! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. */ -#define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE) - -/*! @brief Set the FLASHDOZE field to a new value. */ -#define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v)) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field DEPART[11:8] (RO) - * - * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit - * description in FTFE chapter. For devices without FlexNVM: Reserved - */ -/*@{*/ -#define BP_SIM_FCFG1_DEPART (8U) /*!< Bit position for SIM_FCFG1_DEPART. */ -#define BM_SIM_FCFG1_DEPART (0x00000F00U) /*!< Bit mask for SIM_FCFG1_DEPART. */ -#define BS_SIM_FCFG1_DEPART (4U) /*!< Bit field size in bits for SIM_FCFG1_DEPART. */ - -/*! @brief Read current value of the SIM_FCFG1_DEPART field. */ -#define BR_SIM_FCFG1_DEPART(x) (HW_SIM_FCFG1(x).B.DEPART) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field EESIZE[19:16] (RO) - * - * EEPROM data size . - * - * Values: - * - 0000 - 16 KB - * - 0001 - 8 KB - * - 0010 - 4 KB - * - 0011 - 2 KB - * - 0100 - 1 KB - * - 0101 - 512 Bytes - * - 0110 - 256 Bytes - * - 0111 - 128 Bytes - * - 1000 - 64 Bytes - * - 1001 - 32 Bytes - * - 1111 - 0 Bytes - */ -/*@{*/ -#define BP_SIM_FCFG1_EESIZE (16U) /*!< Bit position for SIM_FCFG1_EESIZE. */ -#define BM_SIM_FCFG1_EESIZE (0x000F0000U) /*!< Bit mask for SIM_FCFG1_EESIZE. */ -#define BS_SIM_FCFG1_EESIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_EESIZE. */ - -/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */ -#define BR_SIM_FCFG1_EESIZE(x) (HW_SIM_FCFG1(x).B.EESIZE) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO) - * - * This field specifies the amount of program flash memory available on the - * device . Undefined values are reserved. - * - * Values: - * - 0011 - 32 KB of program flash memory - * - 0101 - 64 KB of program flash memory - * - 0111 - 128 KB of program flash memory - * - 1001 - 256 KB of program flash memory - * - 1011 - 512 KB of program flash memory - * - 1101 - 1024 KB of program flash memory - * - 1111 - 1024 KB of program flash memory - */ -/*@{*/ -#define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */ -#define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */ -#define BS_SIM_FCFG1_PFSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */ - -/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */ -#define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE) -/*@}*/ - -/*! - * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO) - * - * This field specifies the amount of FlexNVM memory available on the device . - * Undefined values are reserved. - * - * Values: - * - 0000 - 0 KB of FlexNVM - * - 0011 - 32 KB of FlexNVM - * - 0101 - 64 KB of FlexNVM - * - 0111 - 128 KB of FlexNVM - * - 1001 - 256 KB of FlexNVM - * - 1011 - 512 KB of FlexNVM - * - 1111 - 512 KB of FlexNVM - */ -/*@{*/ -#define BP_SIM_FCFG1_NVMSIZE (28U) /*!< Bit position for SIM_FCFG1_NVMSIZE. */ -#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /*!< Bit mask for SIM_FCFG1_NVMSIZE. */ -#define BS_SIM_FCFG1_NVMSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_NVMSIZE. */ - -/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */ -#define BR_SIM_FCFG1_NVMSIZE(x) (HW_SIM_FCFG1(x).B.NVMSIZE) -/*@}*/ - -/******************************************************************************* - * HW_SIM_FCFG2 - Flash Configuration Register 2 - ******************************************************************************/ - -/*! - * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO) - * - * Reset value: 0x7F7F0000U - */ -typedef union _hw_sim_fcfg2 -{ - uint32_t U; - struct _hw_sim_fcfg2_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t MAXADDR1 : 7; /*!< [22:16] Max address block 1 */ - uint32_t PFLSH : 1; /*!< [23] Program flash only */ - uint32_t MAXADDR0 : 7; /*!< [30:24] Max address block 0 */ - uint32_t RESERVED1 : 1; /*!< [31] */ - } B; -} hw_sim_fcfg2_t; - -/*! - * @name Constants and macros for entire SIM_FCFG2 register - */ -/*@{*/ -#define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U) - -#define HW_SIM_FCFG2(x) (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x)) -#define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_FCFG2 bitfields - */ - -/*! - * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO) - * - * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus - * the FlexNVM base address indicates the first invalid address of the FlexNVM - * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of - * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value - * for a device with 256 KB FlexNVM. For devices with program flash only: This - * field equals zero if there is only one program flash block, otherwise it equals - * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20 - * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be - * the MAXADDR1 value for a device with 512 KB program flash memory across two - * flash blocks and no FlexNVM. - */ -/*@{*/ -#define BP_SIM_FCFG2_MAXADDR1 (16U) /*!< Bit position for SIM_FCFG2_MAXADDR1. */ -#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR1. */ -#define BS_SIM_FCFG2_MAXADDR1 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR1. */ - -/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */ -#define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1) -/*@}*/ - -/*! - * @name Register SIM_FCFG2, field PFLSH[23] (RO) - * - * For devices with FlexNVM, this bit is always clear. For devices without - * FlexNVM, this bit is always set. - * - * Values: - * - 0 - Device supports FlexNVM - * - 1 - Program Flash only, device does not support FlexNVM - */ -/*@{*/ -#define BP_SIM_FCFG2_PFLSH (23U) /*!< Bit position for SIM_FCFG2_PFLSH. */ -#define BM_SIM_FCFG2_PFLSH (0x00800000U) /*!< Bit mask for SIM_FCFG2_PFLSH. */ -#define BS_SIM_FCFG2_PFLSH (1U) /*!< Bit field size in bits for SIM_FCFG2_PFLSH. */ - -/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */ -#define BR_SIM_FCFG2_PFLSH(x) (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR(x), BP_SIM_FCFG2_PFLSH)) -/*@}*/ - -/*! - * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO) - * - * This field concatenated with 13 trailing zeros indicates the first invalid - * address of each program flash block. For example, if MAXADDR0 = 0x20 the first - * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 - * value for a device with 256 KB program flash in flash block 0. - */ -/*@{*/ -#define BP_SIM_FCFG2_MAXADDR0 (24U) /*!< Bit position for SIM_FCFG2_MAXADDR0. */ -#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR0. */ -#define BS_SIM_FCFG2_MAXADDR0 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR0. */ - -/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */ -#define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDH - Unique Identification Register High - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDH - Unique Identification Register High (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidh -{ - uint32_t U; - struct _hw_sim_uidh_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidh_t; - -/*! - * @name Constants and macros for entire SIM_UIDH register - */ -/*@{*/ -#define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U) - -#define HW_SIM_UIDH(x) (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x)) -#define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDH bitfields - */ - -/*! - * @name Register SIM_UIDH, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDH_UID (0U) /*!< Bit position for SIM_UIDH_UID. */ -#define BM_SIM_UIDH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */ -#define BS_SIM_UIDH_UID (32U) /*!< Bit field size in bits for SIM_UIDH_UID. */ - -/*! @brief Read current value of the SIM_UIDH_UID field. */ -#define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDMH - Unique Identification Register Mid-High - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidmh -{ - uint32_t U; - struct _hw_sim_uidmh_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidmh_t; - -/*! - * @name Constants and macros for entire SIM_UIDMH register - */ -/*@{*/ -#define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U) - -#define HW_SIM_UIDMH(x) (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x)) -#define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDMH bitfields - */ - -/*! - * @name Register SIM_UIDMH, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDMH_UID (0U) /*!< Bit position for SIM_UIDMH_UID. */ -#define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */ -#define BS_SIM_UIDMH_UID (32U) /*!< Bit field size in bits for SIM_UIDMH_UID. */ - -/*! @brief Read current value of the SIM_UIDMH_UID field. */ -#define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDML - Unique Identification Register Mid Low - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidml -{ - uint32_t U; - struct _hw_sim_uidml_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidml_t; - -/*! - * @name Constants and macros for entire SIM_UIDML register - */ -/*@{*/ -#define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU) - -#define HW_SIM_UIDML(x) (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x)) -#define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDML bitfields - */ - -/*! - * @name Register SIM_UIDML, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDML_UID (0U) /*!< Bit position for SIM_UIDML_UID. */ -#define BM_SIM_UIDML_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */ -#define BS_SIM_UIDML_UID (32U) /*!< Bit field size in bits for SIM_UIDML_UID. */ - -/*! @brief Read current value of the SIM_UIDML_UID field. */ -#define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SIM_UIDL - Unique Identification Register Low - ******************************************************************************/ - -/*! - * @brief HW_SIM_UIDL - Unique Identification Register Low (RO) - * - * Reset value: 0x00000000U - */ -typedef union _hw_sim_uidl -{ - uint32_t U; - struct _hw_sim_uidl_bitfields - { - uint32_t UID : 32; /*!< [31:0] Unique Identification */ - } B; -} hw_sim_uidl_t; - -/*! - * @name Constants and macros for entire SIM_UIDL register - */ -/*@{*/ -#define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U) - -#define HW_SIM_UIDL(x) (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x)) -#define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U) -/*@}*/ - -/* - * Constants & macros for individual SIM_UIDL bitfields - */ - -/*! - * @name Register SIM_UIDL, field UID[31:0] (RO) - * - * Unique identification for the device. - */ -/*@{*/ -#define BP_SIM_UIDL_UID (0U) /*!< Bit position for SIM_UIDL_UID. */ -#define BM_SIM_UIDL_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */ -#define BS_SIM_UIDL_UID (32U) /*!< Bit field size in bits for SIM_UIDL_UID. */ - -/*! @brief Read current value of the SIM_UIDL_UID field. */ -#define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U) -/*@}*/ - -/******************************************************************************* - * hw_sim_t - module struct - ******************************************************************************/ -/*! - * @brief All SIM module registers. - */ -#pragma pack(1) -typedef struct _hw_sim -{ - __IO hw_sim_sopt1_t SOPT1; /*!< [0x0] System Options Register 1 */ - __IO hw_sim_sopt1cfg_t SOPT1CFG; /*!< [0x4] SOPT1 Configuration Register */ - uint8_t _reserved0[4092]; - __IO hw_sim_sopt2_t SOPT2; /*!< [0x1004] System Options Register 2 */ - uint8_t _reserved1[4]; - __IO hw_sim_sopt4_t SOPT4; /*!< [0x100C] System Options Register 4 */ - __IO hw_sim_sopt5_t SOPT5; /*!< [0x1010] System Options Register 5 */ - uint8_t _reserved2[4]; - __IO hw_sim_sopt7_t SOPT7; /*!< [0x1018] System Options Register 7 */ - uint8_t _reserved3[8]; - __I hw_sim_sdid_t SDID; /*!< [0x1024] System Device Identification Register */ - __IO hw_sim_scgc1_t SCGC1; /*!< [0x1028] System Clock Gating Control Register 1 */ - __IO hw_sim_scgc2_t SCGC2; /*!< [0x102C] System Clock Gating Control Register 2 */ - __IO hw_sim_scgc3_t SCGC3; /*!< [0x1030] System Clock Gating Control Register 3 */ - __IO hw_sim_scgc4_t SCGC4; /*!< [0x1034] System Clock Gating Control Register 4 */ - __IO hw_sim_scgc5_t SCGC5; /*!< [0x1038] System Clock Gating Control Register 5 */ - __IO hw_sim_scgc6_t SCGC6; /*!< [0x103C] System Clock Gating Control Register 6 */ - __IO hw_sim_scgc7_t SCGC7; /*!< [0x1040] System Clock Gating Control Register 7 */ - __IO hw_sim_clkdiv1_t CLKDIV1; /*!< [0x1044] System Clock Divider Register 1 */ - __IO hw_sim_clkdiv2_t CLKDIV2; /*!< [0x1048] System Clock Divider Register 2 */ - __IO hw_sim_fcfg1_t FCFG1; /*!< [0x104C] Flash Configuration Register 1 */ - __I hw_sim_fcfg2_t FCFG2; /*!< [0x1050] Flash Configuration Register 2 */ - __I hw_sim_uidh_t UIDH; /*!< [0x1054] Unique Identification Register High */ - __I hw_sim_uidmh_t UIDMH; /*!< [0x1058] Unique Identification Register Mid-High */ - __I hw_sim_uidml_t UIDML; /*!< [0x105C] Unique Identification Register Mid Low */ - __I hw_sim_uidl_t UIDL; /*!< [0x1060] Unique Identification Register Low */ -} hw_sim_t; -#pragma pack() - -/*! @brief Macro to access all SIM registers. */ -/*! @param x SIM module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SIM(SIM_BASE). */ -#define HW_SIM(x) (*(hw_sim_t *)(x)) - -#endif /* __HW_SIM_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_smc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_smc.h deleted file mode 100644 index 05ca69643ca..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_smc.h +++ /dev/null @@ -1,566 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SMC_REGISTERS_H__ -#define __HW_SMC_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 SMC - * - * System Mode Controller - * - * Registers defined in this header file: - * - HW_SMC_PMPROT - Power Mode Protection register - * - HW_SMC_PMCTRL - Power Mode Control register - * - HW_SMC_VLLSCTRL - VLLS Control register - * - HW_SMC_PMSTAT - Power Mode Status register - * - * - hw_smc_t - Struct containing all module registers. - */ - -#define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */ - -/******************************************************************************* - * HW_SMC_PMPROT - Power Mode Protection register - ******************************************************************************/ - -/*! - * @brief HW_SMC_PMPROT - Power Mode Protection register (RW) - * - * Reset value: 0x00U - * - * This register provides protection for entry into any low-power run or stop - * mode. The enabling of the low-power run or stop mode occurs by configuring the - * Power Mode Control register (PMCTRL). The PMPROT register can be written only - * once after any system reset. If the MCU is configured for a disallowed or - * reserved power mode, the MCU remains in its current power mode. For example, if the - * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using - * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is - * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by - * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types - * that do not trigger Chip Reset not VLLS. See the Reset section details for more - * information. - */ -typedef union _hw_smc_pmprot -{ - uint8_t U; - struct _hw_smc_pmprot_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */ - uint8_t RESERVED1 : 1; /*!< [2] */ - uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */ - uint8_t RESERVED2 : 1; /*!< [4] */ - uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */ - uint8_t RESERVED3 : 2; /*!< [7:6] */ - } B; -} hw_smc_pmprot_t; - -/*! - * @name Constants and macros for entire SMC_PMPROT register - */ -/*@{*/ -#define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U) - -#define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x)) -#define HW_SMC_PMPROT_RD(x) (HW_SMC_PMPROT(x).U) -#define HW_SMC_PMPROT_WR(x, v) (HW_SMC_PMPROT(x).U = (v)) -#define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v))) -#define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v))) -#define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SMC_PMPROT bitfields - */ - -/*! - * @name Register SMC_PMPROT, field AVLLS[1] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write once - * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). - * - * Values: - * - 0 - Any VLLSx mode is not allowed - * - 1 - Any VLLSx mode is allowed - */ -/*@{*/ -#define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */ -#define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */ -#define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */ - -/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */ -#define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS)) - -/*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */ -#define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS) - -/*! @brief Set the AVLLS field to a new value. */ -#define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v)) -/*@}*/ - -/*! - * @name Register SMC_PMPROT, field ALLS[3] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write-once - * field allows the MCU to enter any low-leakage stop mode (LLS). - * - * Values: - * - 0 - LLS is not allowed - * - 1 - LLS is allowed - */ -/*@{*/ -#define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */ -#define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */ -#define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */ - -/*! @brief Read current value of the SMC_PMPROT_ALLS field. */ -#define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS)) - -/*! @brief Format value for bitfield SMC_PMPROT_ALLS. */ -#define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS) - -/*! @brief Set the ALLS field to a new value. */ -#define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v)) -/*@}*/ - -/*! - * @name Register SMC_PMPROT, field AVLP[5] (RW) - * - * Provided the appropriate control bits are set up in PMCTRL, this write-once - * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). - * - * Values: - * - 0 - VLPR, VLPW, and VLPS are not allowed. - * - 1 - VLPR, VLPW, and VLPS are allowed. - */ -/*@{*/ -#define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */ -#define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */ -#define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */ - -/*! @brief Read current value of the SMC_PMPROT_AVLP field. */ -#define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP)) - -/*! @brief Format value for bitfield SMC_PMPROT_AVLP. */ -#define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP) - -/*! @brief Set the AVLP field to a new value. */ -#define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SMC_PMCTRL - Power Mode Control register - ******************************************************************************/ - -/*! - * @brief HW_SMC_PMCTRL - Power Mode Control register (RW) - * - * Reset value: 0x00U - * - * The PMCTRL register controls entry into low-power Run and Stop modes, - * provided that the selected power mode is allowed via an appropriate setting of the - * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by - * reset types that trigger Chip POR not VLLS. It is unaffected by reset types - * that do not trigger Chip POR not VLLS. See the Reset section details for more - * information. - */ -typedef union _hw_smc_pmctrl -{ - uint8_t U; - struct _hw_smc_pmctrl_bitfields - { - uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */ - uint8_t STOPA : 1; /*!< [3] Stop Aborted */ - uint8_t RESERVED0 : 1; /*!< [4] */ - uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */ - uint8_t LPWUI : 1; /*!< [7] Low-Power Wake Up On Interrupt */ - } B; -} hw_smc_pmctrl_t; - -/*! - * @name Constants and macros for entire SMC_PMCTRL register - */ -/*@{*/ -#define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U) - -#define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x)) -#define HW_SMC_PMCTRL_RD(x) (HW_SMC_PMCTRL(x).U) -#define HW_SMC_PMCTRL_WR(x, v) (HW_SMC_PMCTRL(x).U = (v)) -#define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v))) -#define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v))) -#define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SMC_PMCTRL bitfields - */ - -/*! - * @name Register SMC_PMCTRL, field STOPM[2:0] (RW) - * - * When written, controls entry into the selected stop mode when Sleep-Now or - * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are - * blocked if the protection level has not been enabled using the PMPROT register. - * After any system reset, this field is cleared by hardware on any successful write - * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL - * register is used to further select the particular VLLS submode which will be - * entered. - * - * Values: - * - 000 - Normal Stop (STOP) - * - 001 - Reserved - * - 010 - Very-Low-Power Stop (VLPS) - * - 011 - Low-Leakage Stop (LLS) - * - 100 - Very-Low-Leakage Stop (VLLSx) - * - 101 - Reserved - * - 110 - Reseved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */ -#define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */ -#define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */ - -/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */ -#define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM) - -/*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */ -#define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM) - -/*! @brief Set the STOPM field to a new value. */ -#define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v))) -/*@}*/ - -/*! - * @name Register SMC_PMCTRL, field STOPA[3] (RO) - * - * When set, this read-only status bit indicates an interrupt or reset occured - * during the previous stop mode entry sequence, preventing the system from - * entering that mode. This field is cleared by hardware at the beginning of any stop - * mode entry sequence and is set if the sequence was aborted. - * - * Values: - * - 0 - The previous stop mode entry was successsful. - * - 1 - The previous stop mode entry was aborted. - */ -/*@{*/ -#define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */ -#define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */ -#define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */ - -/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */ -#define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA)) -/*@}*/ - -/*! - * @name Register SMC_PMCTRL, field RUNM[6:5] (RW) - * - * When written, causes entry into the selected run mode. Writes to this field - * are blocked if the protection level has not been enabled using the PMPROT - * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to - * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. - * - * Values: - * - 00 - Normal Run mode (RUN) - * - 01 - Reserved - * - 10 - Very-Low-Power Run mode (VLPR) - * - 11 - Reserved - */ -/*@{*/ -#define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */ -#define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */ -#define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */ - -/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */ -#define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM) - -/*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */ -#define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM) - -/*! @brief Set the RUNM field to a new value. */ -#define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v))) -/*@}*/ - -/*! - * @name Register SMC_PMCTRL, field LPWUI[7] (RW) - * - * Causes the SMC to exit to normal RUN mode when any active MCU interrupt - * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly - * from RUN mode, the SMC will always exit back to normal RUN mode regardless of - * the LPWUI setting. LPWUI must be modified only while the system is in RUN - * mode, that is, when PMSTAT=RUN. - * - * Values: - * - 0 - The system remains in a VLP mode on an interrupt - * - 1 - The system exits to Normal RUN mode on an interrupt - */ -/*@{*/ -#define BP_SMC_PMCTRL_LPWUI (7U) /*!< Bit position for SMC_PMCTRL_LPWUI. */ -#define BM_SMC_PMCTRL_LPWUI (0x80U) /*!< Bit mask for SMC_PMCTRL_LPWUI. */ -#define BS_SMC_PMCTRL_LPWUI (1U) /*!< Bit field size in bits for SMC_PMCTRL_LPWUI. */ - -/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */ -#define BR_SMC_PMCTRL_LPWUI(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI)) - -/*! @brief Format value for bitfield SMC_PMCTRL_LPWUI. */ -#define BF_SMC_PMCTRL_LPWUI(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_LPWUI) & BM_SMC_PMCTRL_LPWUI) - -/*! @brief Set the LPWUI field to a new value. */ -#define BW_SMC_PMCTRL_LPWUI(x, v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SMC_VLLSCTRL - VLLS Control register - ******************************************************************************/ - -/*! - * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW) - * - * Reset value: 0x03U - * - * The VLLSCTRL register controls features related to VLLS modes. This register - * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not - * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See - * the Reset section details for more information. - */ -typedef union _hw_smc_vllsctrl -{ - uint8_t U; - struct _hw_smc_vllsctrl_bitfields - { - uint8_t VLLSM : 3; /*!< [2:0] VLLS Mode Control */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t PORPO : 1; /*!< [5] POR Power Option */ - uint8_t RESERVED1 : 2; /*!< [7:6] */ - } B; -} hw_smc_vllsctrl_t; - -/*! - * @name Constants and macros for entire SMC_VLLSCTRL register - */ -/*@{*/ -#define HW_SMC_VLLSCTRL_ADDR(x) ((x) + 0x2U) - -#define HW_SMC_VLLSCTRL(x) (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR(x)) -#define HW_SMC_VLLSCTRL_RD(x) (HW_SMC_VLLSCTRL(x).U) -#define HW_SMC_VLLSCTRL_WR(x, v) (HW_SMC_VLLSCTRL(x).U = (v)) -#define HW_SMC_VLLSCTRL_SET(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) | (v))) -#define HW_SMC_VLLSCTRL_CLR(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) & ~(v))) -#define HW_SMC_VLLSCTRL_TOG(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SMC_VLLSCTRL bitfields - */ - -/*! - * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW) - * - * Controls which VLLS sub-mode to enter if STOPM=VLLS. - * - * Values: - * - 000 - VLLS0 - * - 001 - VLLS1 - * - 010 - VLLS2 - * - 011 - VLLS3 - * - 100 - Reserved - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SMC_VLLSCTRL_VLLSM (0U) /*!< Bit position for SMC_VLLSCTRL_VLLSM. */ -#define BM_SMC_VLLSCTRL_VLLSM (0x07U) /*!< Bit mask for SMC_VLLSCTRL_VLLSM. */ -#define BS_SMC_VLLSCTRL_VLLSM (3U) /*!< Bit field size in bits for SMC_VLLSCTRL_VLLSM. */ - -/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */ -#define BR_SMC_VLLSCTRL_VLLSM(x) (HW_SMC_VLLSCTRL(x).B.VLLSM) - -/*! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM. */ -#define BF_SMC_VLLSCTRL_VLLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_VLLSM) & BM_SMC_VLLSCTRL_VLLSM) - -/*! @brief Set the VLLSM field to a new value. */ -#define BW_SMC_VLLSCTRL_VLLSM(x, v) (HW_SMC_VLLSCTRL_WR(x, (HW_SMC_VLLSCTRL_RD(x) & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v))) -/*@}*/ - -/*! - * @name Register SMC_VLLSCTRL, field PORPO[5] (RW) - * - * Controls whether the POR detect circuit (for brown-out detection) is enabled - * in VLLS0 mode. - * - * Values: - * - 0 - POR detect circuit is enabled in VLLS0. - * - 1 - POR detect circuit is disabled in VLLS0. - */ -/*@{*/ -#define BP_SMC_VLLSCTRL_PORPO (5U) /*!< Bit position for SMC_VLLSCTRL_PORPO. */ -#define BM_SMC_VLLSCTRL_PORPO (0x20U) /*!< Bit mask for SMC_VLLSCTRL_PORPO. */ -#define BS_SMC_VLLSCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_VLLSCTRL_PORPO. */ - -/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */ -#define BR_SMC_VLLSCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO)) - -/*! @brief Format value for bitfield SMC_VLLSCTRL_PORPO. */ -#define BF_SMC_VLLSCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_PORPO) & BM_SMC_VLLSCTRL_PORPO) - -/*! @brief Set the PORPO field to a new value. */ -#define BW_SMC_VLLSCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SMC_PMSTAT - Power Mode Status register - ******************************************************************************/ - -/*! - * @brief HW_SMC_PMSTAT - Power Mode Status register (RO) - * - * Reset value: 0x01U - * - * PMSTAT is a read-only, one-hot register which indicates the current power - * mode of the system. This register is reset on Chip POR not VLLS and by reset - * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not - * trigger Chip POR not VLLS. See the Reset section details for more information. - */ -typedef union _hw_smc_pmstat -{ - uint8_t U; - struct _hw_smc_pmstat_bitfields - { - uint8_t PMSTAT : 7; /*!< [6:0] */ - uint8_t RESERVED0 : 1; /*!< [7] */ - } B; -} hw_smc_pmstat_t; - -/*! - * @name Constants and macros for entire SMC_PMSTAT register - */ -/*@{*/ -#define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U) - -#define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x)) -#define HW_SMC_PMSTAT_RD(x) (HW_SMC_PMSTAT(x).U) -/*@}*/ - -/* - * Constants & macros for individual SMC_PMSTAT bitfields - */ - -/*! - * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO) - * - * When debug is enabled, the PMSTAT will not update to STOP or VLPS - */ -/*@{*/ -#define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */ -#define BM_SMC_PMSTAT_PMSTAT (0x7FU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */ -#define BS_SMC_PMSTAT_PMSTAT (7U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */ - -/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */ -#define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).B.PMSTAT) -/*@}*/ - -/******************************************************************************* - * hw_smc_t - module struct - ******************************************************************************/ -/*! - * @brief All SMC module registers. - */ -#pragma pack(1) -typedef struct _hw_smc -{ - __IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */ - __IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */ - __IO hw_smc_vllsctrl_t VLLSCTRL; /*!< [0x2] VLLS Control register */ - __I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */ -} hw_smc_t; -#pragma pack() - -/*! @brief Macro to access all SMC registers. */ -/*! @param x SMC module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SMC(SMC_BASE). */ -#define HW_SMC(x) (*(hw_smc_t *)(x)) - -#endif /* __HW_SMC_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_spi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_spi.h deleted file mode 100644 index ffe2e997104..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_spi.h +++ /dev/null @@ -1,2243 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_SPI_REGISTERS_H__ -#define __HW_SPI_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 SPI - * - * Serial Peripheral Interface - * - * Registers defined in this header file: - * - HW_SPI_MCR - Module Configuration Register - * - HW_SPI_TCR - Transfer Count Register - * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) - * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) - * - HW_SPI_SR - Status Register - * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register - * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode - * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode - * - HW_SPI_POPR - POP RX FIFO Register - * - HW_SPI_TXFRn - Transmit FIFO Registers - * - HW_SPI_RXFRn - Receive FIFO Registers - * - * - hw_spi_t - Struct containing all module registers. - */ - -#define HW_SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */ -#define HW_SPI0 (0U) /*!< Instance number for SPI0. */ -#define HW_SPI1 (1U) /*!< Instance number for SPI1. */ -#define HW_SPI2 (2U) /*!< Instance number for SPI2. */ - -/******************************************************************************* - * HW_SPI_MCR - Module Configuration Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_MCR - Module Configuration Register (RW) - * - * Reset value: 0x00004001U - * - * Contains bits to configure various attributes associated with the module - * operations. The HALT and MDIS bits can be changed at any time, but the effect - * takes place only on the next frame boundary. Only the HALT and MDIS bits in the - * MCR can be changed, while the module is in the Running state. - */ -typedef union _hw_spi_mcr -{ - uint32_t U; - struct _hw_spi_mcr_bitfields - { - uint32_t HALT : 1; /*!< [0] Halt */ - uint32_t RESERVED0 : 7; /*!< [7:1] */ - uint32_t SMPL_PT : 2; /*!< [9:8] Sample Point */ - uint32_t CLR_RXF : 1; /*!< [10] */ - uint32_t CLR_TXF : 1; /*!< [11] Clear TX FIFO */ - uint32_t DIS_RXF : 1; /*!< [12] Disable Receive FIFO */ - uint32_t DIS_TXF : 1; /*!< [13] Disable Transmit FIFO */ - uint32_t MDIS : 1; /*!< [14] Module Disable */ - uint32_t DOZE : 1; /*!< [15] Doze Enable */ - uint32_t PCSIS : 6; /*!< [21:16] Peripheral Chip Select x Inactive - * State */ - uint32_t RESERVED1 : 2; /*!< [23:22] */ - uint32_t ROOE : 1; /*!< [24] Receive FIFO Overflow Overwrite Enable */ - uint32_t PCSSE : 1; /*!< [25] Peripheral Chip Select Strobe Enable */ - uint32_t MTFE : 1; /*!< [26] Modified Timing Format Enable */ - uint32_t FRZ : 1; /*!< [27] Freeze */ - uint32_t DCONF : 2; /*!< [29:28] SPI Configuration. */ - uint32_t CONT_SCKE : 1; /*!< [30] Continuous SCK Enable */ - uint32_t MSTR : 1; /*!< [31] Master/Slave Mode Select */ - } B; -} hw_spi_mcr_t; - -/*! - * @name Constants and macros for entire SPI_MCR register - */ -/*@{*/ -#define HW_SPI_MCR_ADDR(x) ((x) + 0x0U) - -#define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x)) -#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U) -#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v)) -#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v))) -#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v))) -#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_MCR bitfields - */ - -/*! - * @name Register SPI_MCR, field HALT[0] (RW) - * - * The HALT bit starts and stops frame transfers. See Start and Stop of Module - * transfers - * - * Values: - * - 0 - Start transfers. - * - 1 - Stop transfers. - */ -/*@{*/ -#define BP_SPI_MCR_HALT (0U) /*!< Bit position for SPI_MCR_HALT. */ -#define BM_SPI_MCR_HALT (0x00000001U) /*!< Bit mask for SPI_MCR_HALT. */ -#define BS_SPI_MCR_HALT (1U) /*!< Bit field size in bits for SPI_MCR_HALT. */ - -/*! @brief Read current value of the SPI_MCR_HALT field. */ -#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT)) - -/*! @brief Format value for bitfield SPI_MCR_HALT. */ -#define BF_SPI_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT) - -/*! @brief Set the HALT field to a new value. */ -#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field SMPL_PT[9:8] (RW) - * - * Controls when the module master samples SIN in Modified Transfer Format. This - * field is valid only when CPHA bit in CTARn[CPHA] is 0. - * - * Values: - * - 00 - 0 protocol clock cycles between SCK edge and SIN sample - * - 01 - 1 protocol clock cycle between SCK edge and SIN sample - * - 10 - 2 protocol clock cycles between SCK edge and SIN sample - * - 11 - Reserved - */ -/*@{*/ -#define BP_SPI_MCR_SMPL_PT (8U) /*!< Bit position for SPI_MCR_SMPL_PT. */ -#define BM_SPI_MCR_SMPL_PT (0x00000300U) /*!< Bit mask for SPI_MCR_SMPL_PT. */ -#define BS_SPI_MCR_SMPL_PT (2U) /*!< Bit field size in bits for SPI_MCR_SMPL_PT. */ - -/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */ -#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT) - -/*! @brief Format value for bitfield SPI_MCR_SMPL_PT. */ -#define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT) - -/*! @brief Set the SMPL_PT field to a new value. */ -#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v))) -/*@}*/ - -/*! - * @name Register SPI_MCR, field CLR_RXF[10] (WORZ) - * - * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The - * CLR_RXF bit is always read as zero. - * - * Values: - * - 0 - Do not clear the RX FIFO counter. - * - 1 - Clear the RX FIFO counter. - */ -/*@{*/ -#define BP_SPI_MCR_CLR_RXF (10U) /*!< Bit position for SPI_MCR_CLR_RXF. */ -#define BM_SPI_MCR_CLR_RXF (0x00000400U) /*!< Bit mask for SPI_MCR_CLR_RXF. */ -#define BS_SPI_MCR_CLR_RXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_RXF. */ - -/*! @brief Format value for bitfield SPI_MCR_CLR_RXF. */ -#define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF) - -/*! @brief Set the CLR_RXF field to a new value. */ -#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field CLR_TXF[11] (WORZ) - * - * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The - * CLR_TXF bit is always read as zero. - * - * Values: - * - 0 - Do not clear the TX FIFO counter. - * - 1 - Clear the TX FIFO counter. - */ -/*@{*/ -#define BP_SPI_MCR_CLR_TXF (11U) /*!< Bit position for SPI_MCR_CLR_TXF. */ -#define BM_SPI_MCR_CLR_TXF (0x00000800U) /*!< Bit mask for SPI_MCR_CLR_TXF. */ -#define BS_SPI_MCR_CLR_TXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_TXF. */ - -/*! @brief Format value for bitfield SPI_MCR_CLR_TXF. */ -#define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF) - -/*! @brief Set the CLR_TXF field to a new value. */ -#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DIS_RXF[12] (RW) - * - * When the RX FIFO is disabled, the receive part of the module operates as a - * simplified double-buffered SPI. This bit can only be written when the MDIS bit - * is cleared. - * - * Values: - * - 0 - RX FIFO is enabled. - * - 1 - RX FIFO is disabled. - */ -/*@{*/ -#define BP_SPI_MCR_DIS_RXF (12U) /*!< Bit position for SPI_MCR_DIS_RXF. */ -#define BM_SPI_MCR_DIS_RXF (0x00001000U) /*!< Bit mask for SPI_MCR_DIS_RXF. */ -#define BS_SPI_MCR_DIS_RXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_RXF. */ - -/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */ -#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF)) - -/*! @brief Format value for bitfield SPI_MCR_DIS_RXF. */ -#define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF) - -/*! @brief Set the DIS_RXF field to a new value. */ -#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DIS_TXF[13] (RW) - * - * When the TX FIFO is disabled, the transmit part of the module operates as a - * simplified double-buffered SPI. This bit can be written only when the MDIS bit - * is cleared. - * - * Values: - * - 0 - TX FIFO is enabled. - * - 1 - TX FIFO is disabled. - */ -/*@{*/ -#define BP_SPI_MCR_DIS_TXF (13U) /*!< Bit position for SPI_MCR_DIS_TXF. */ -#define BM_SPI_MCR_DIS_TXF (0x00002000U) /*!< Bit mask for SPI_MCR_DIS_TXF. */ -#define BS_SPI_MCR_DIS_TXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_TXF. */ - -/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */ -#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF)) - -/*! @brief Format value for bitfield SPI_MCR_DIS_TXF. */ -#define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF) - -/*! @brief Set the DIS_TXF field to a new value. */ -#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field MDIS[14] (RW) - * - * Allows the clock to be stopped to the non-memory mapped logic in the module - * effectively putting it in a software-controlled power-saving state. The reset - * value of the MDIS bit is parameterized, with a default reset value of 0. When - * the module is used in Slave Mode, we recommend leaving this bit 0, because a - * slave doesn't have control over master transactions. - * - * Values: - * - 0 - Enables the module clocks. - * - 1 - Allows external logic to disable the module clocks. - */ -/*@{*/ -#define BP_SPI_MCR_MDIS (14U) /*!< Bit position for SPI_MCR_MDIS. */ -#define BM_SPI_MCR_MDIS (0x00004000U) /*!< Bit mask for SPI_MCR_MDIS. */ -#define BS_SPI_MCR_MDIS (1U) /*!< Bit field size in bits for SPI_MCR_MDIS. */ - -/*! @brief Read current value of the SPI_MCR_MDIS field. */ -#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS)) - -/*! @brief Format value for bitfield SPI_MCR_MDIS. */ -#define BF_SPI_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS) - -/*! @brief Set the MDIS field to a new value. */ -#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DOZE[15] (RW) - * - * Provides support for an externally controlled Doze mode power-saving - * mechanism. - * - * Values: - * - 0 - Doze mode has no effect on the module. - * - 1 - Doze mode disables the module. - */ -/*@{*/ -#define BP_SPI_MCR_DOZE (15U) /*!< Bit position for SPI_MCR_DOZE. */ -#define BM_SPI_MCR_DOZE (0x00008000U) /*!< Bit mask for SPI_MCR_DOZE. */ -#define BS_SPI_MCR_DOZE (1U) /*!< Bit field size in bits for SPI_MCR_DOZE. */ - -/*! @brief Read current value of the SPI_MCR_DOZE field. */ -#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE)) - -/*! @brief Format value for bitfield SPI_MCR_DOZE. */ -#define BF_SPI_MCR_DOZE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE) - -/*! @brief Set the DOZE field to a new value. */ -#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field PCSIS[21:16] (RW) - * - * Determines the inactive state of PCSx. - * - * Values: - * - 0 - The inactive state of PCSx is low. - * - 1 - The inactive state of PCSx is high. - */ -/*@{*/ -#define BP_SPI_MCR_PCSIS (16U) /*!< Bit position for SPI_MCR_PCSIS. */ -#define BM_SPI_MCR_PCSIS (0x003F0000U) /*!< Bit mask for SPI_MCR_PCSIS. */ -#define BS_SPI_MCR_PCSIS (6U) /*!< Bit field size in bits for SPI_MCR_PCSIS. */ - -/*! @brief Read current value of the SPI_MCR_PCSIS field. */ -#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS) - -/*! @brief Format value for bitfield SPI_MCR_PCSIS. */ -#define BF_SPI_MCR_PCSIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS) - -/*! @brief Set the PCSIS field to a new value. */ -#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v))) -/*@}*/ - -/*! - * @name Register SPI_MCR, field ROOE[24] (RW) - * - * In the RX FIFO overflow condition, configures the module to ignore the - * incoming serial data or overwrite existing data. If the RX FIFO is full and new data - * is received, the data from the transfer, generating the overflow, is ignored - * or shifted into the shift register. - * - * Values: - * - 0 - Incoming data is ignored. - * - 1 - Incoming data is shifted into the shift register. - */ -/*@{*/ -#define BP_SPI_MCR_ROOE (24U) /*!< Bit position for SPI_MCR_ROOE. */ -#define BM_SPI_MCR_ROOE (0x01000000U) /*!< Bit mask for SPI_MCR_ROOE. */ -#define BS_SPI_MCR_ROOE (1U) /*!< Bit field size in bits for SPI_MCR_ROOE. */ - -/*! @brief Read current value of the SPI_MCR_ROOE field. */ -#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE)) - -/*! @brief Format value for bitfield SPI_MCR_ROOE. */ -#define BF_SPI_MCR_ROOE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE) - -/*! @brief Set the ROOE field to a new value. */ -#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field PCSSE[25] (RW) - * - * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal. - * - * Values: - * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. - * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal. - */ -/*@{*/ -#define BP_SPI_MCR_PCSSE (25U) /*!< Bit position for SPI_MCR_PCSSE. */ -#define BM_SPI_MCR_PCSSE (0x02000000U) /*!< Bit mask for SPI_MCR_PCSSE. */ -#define BS_SPI_MCR_PCSSE (1U) /*!< Bit field size in bits for SPI_MCR_PCSSE. */ - -/*! @brief Read current value of the SPI_MCR_PCSSE field. */ -#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE)) - -/*! @brief Format value for bitfield SPI_MCR_PCSSE. */ -#define BF_SPI_MCR_PCSSE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE) - -/*! @brief Set the PCSSE field to a new value. */ -#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field MTFE[26] (RW) - * - * Enables a modified transfer format to be used. - * - * Values: - * - 0 - Modified SPI transfer format disabled. - * - 1 - Modified SPI transfer format enabled. - */ -/*@{*/ -#define BP_SPI_MCR_MTFE (26U) /*!< Bit position for SPI_MCR_MTFE. */ -#define BM_SPI_MCR_MTFE (0x04000000U) /*!< Bit mask for SPI_MCR_MTFE. */ -#define BS_SPI_MCR_MTFE (1U) /*!< Bit field size in bits for SPI_MCR_MTFE. */ - -/*! @brief Read current value of the SPI_MCR_MTFE field. */ -#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE)) - -/*! @brief Format value for bitfield SPI_MCR_MTFE. */ -#define BF_SPI_MCR_MTFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE) - -/*! @brief Set the MTFE field to a new value. */ -#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field FRZ[27] (RW) - * - * Enables transfers to be stopped on the next frame boundary when the device - * enters Debug mode. - * - * Values: - * - 0 - Do not halt serial transfers in Debug mode. - * - 1 - Halt serial transfers in Debug mode. - */ -/*@{*/ -#define BP_SPI_MCR_FRZ (27U) /*!< Bit position for SPI_MCR_FRZ. */ -#define BM_SPI_MCR_FRZ (0x08000000U) /*!< Bit mask for SPI_MCR_FRZ. */ -#define BS_SPI_MCR_FRZ (1U) /*!< Bit field size in bits for SPI_MCR_FRZ. */ - -/*! @brief Read current value of the SPI_MCR_FRZ field. */ -#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ)) - -/*! @brief Format value for bitfield SPI_MCR_FRZ. */ -#define BF_SPI_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ) - -/*! @brief Set the FRZ field to a new value. */ -#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field DCONF[29:28] (RO) - * - * Selects among the different configurations of the module. - * - * Values: - * - 00 - SPI - * - 01 - Reserved - * - 10 - Reserved - * - 11 - Reserved - */ -/*@{*/ -#define BP_SPI_MCR_DCONF (28U) /*!< Bit position for SPI_MCR_DCONF. */ -#define BM_SPI_MCR_DCONF (0x30000000U) /*!< Bit mask for SPI_MCR_DCONF. */ -#define BS_SPI_MCR_DCONF (2U) /*!< Bit field size in bits for SPI_MCR_DCONF. */ - -/*! @brief Read current value of the SPI_MCR_DCONF field. */ -#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF) -/*@}*/ - -/*! - * @name Register SPI_MCR, field CONT_SCKE[30] (RW) - * - * Enables the Serial Communication Clock (SCK) to run continuously. - * - * Values: - * - 0 - Continuous SCK disabled. - * - 1 - Continuous SCK enabled. - */ -/*@{*/ -#define BP_SPI_MCR_CONT_SCKE (30U) /*!< Bit position for SPI_MCR_CONT_SCKE. */ -#define BM_SPI_MCR_CONT_SCKE (0x40000000U) /*!< Bit mask for SPI_MCR_CONT_SCKE. */ -#define BS_SPI_MCR_CONT_SCKE (1U) /*!< Bit field size in bits for SPI_MCR_CONT_SCKE. */ - -/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */ -#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE)) - -/*! @brief Format value for bitfield SPI_MCR_CONT_SCKE. */ -#define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE) - -/*! @brief Set the CONT_SCKE field to a new value. */ -#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_MCR, field MSTR[31] (RW) - * - * Enables either Master mode (if supported) or Slave mode (if supported) - * operation. - * - * Values: - * - 0 - Enables Slave mode - * - 1 - Enables Master mode - */ -/*@{*/ -#define BP_SPI_MCR_MSTR (31U) /*!< Bit position for SPI_MCR_MSTR. */ -#define BM_SPI_MCR_MSTR (0x80000000U) /*!< Bit mask for SPI_MCR_MSTR. */ -#define BS_SPI_MCR_MSTR (1U) /*!< Bit field size in bits for SPI_MCR_MSTR. */ - -/*! @brief Read current value of the SPI_MCR_MSTR field. */ -#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR)) - -/*! @brief Format value for bitfield SPI_MCR_MSTR. */ -#define BF_SPI_MCR_MSTR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR) - -/*! @brief Set the MSTR field to a new value. */ -#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_TCR - Transfer Count Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_TCR - Transfer Count Register (RW) - * - * Reset value: 0x00000000U - * - * TCR contains a counter that indicates the number of SPI transfers made. The - * transfer counter is intended to assist in queue management. Do not write the - * TCR when the module is in the Running state. - */ -typedef union _hw_spi_tcr -{ - uint32_t U; - struct _hw_spi_tcr_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t SPI_TCNT : 16; /*!< [31:16] SPI Transfer Counter */ - } B; -} hw_spi_tcr_t; - -/*! - * @name Constants and macros for entire SPI_TCR register - */ -/*@{*/ -#define HW_SPI_TCR_ADDR(x) ((x) + 0x8U) - -#define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x)) -#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U) -#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v)) -#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v))) -#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v))) -#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_TCR bitfields - */ - -/*! - * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW) - * - * Counts the number of SPI transfers the module makes. The SPI_TCNT field - * increments every time the last bit of an SPI frame is transmitted. A value written - * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at - * the beginning of the frame when the CTCNT field is set in the executing SPI - * command. The Transfer Counter wraps around; incrementing the counter past 65535 - * resets the counter to zero. - */ -/*@{*/ -#define BP_SPI_TCR_SPI_TCNT (16U) /*!< Bit position for SPI_TCR_SPI_TCNT. */ -#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) /*!< Bit mask for SPI_TCR_SPI_TCNT. */ -#define BS_SPI_TCR_SPI_TCNT (16U) /*!< Bit field size in bits for SPI_TCR_SPI_TCNT. */ - -/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */ -#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT) - -/*! @brief Format value for bitfield SPI_TCR_SPI_TCNT. */ -#define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT) - -/*! @brief Set the SPI_TCNT field to a new value. */ -#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v))) -/*@}*/ - -/******************************************************************************* - * HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) - ******************************************************************************/ - -/*! - * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW) - * - * Reset value: 0x78000000U - * - * CTAR registers are used to define different transfer attributes. Do not write - * to the CTAR registers while the module is in the Running state. In Master - * mode, the CTAR registers define combinations of transfer attributes such as frame - * size, clock phase and polarity, data bit ordering, baud rate, and various - * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the - * slave transfer attributes. When the module is configured as an SPI master, the - * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR - * registers is used. When the module is configured as an SPI bus slave, it uses - * the CTAR0 register. - */ -typedef union _hw_spi_ctarn -{ - uint32_t U; - struct _hw_spi_ctarn_bitfields - { - uint32_t BR : 4; /*!< [3:0] Baud Rate Scaler */ - uint32_t DT : 4; /*!< [7:4] Delay After Transfer Scaler */ - uint32_t ASC : 4; /*!< [11:8] After SCK Delay Scaler */ - uint32_t CSSCK : 4; /*!< [15:12] PCS to SCK Delay Scaler */ - uint32_t PBR : 2; /*!< [17:16] Baud Rate Prescaler */ - uint32_t PDT : 2; /*!< [19:18] Delay after Transfer Prescaler */ - uint32_t PASC : 2; /*!< [21:20] After SCK Delay Prescaler */ - uint32_t PCSSCK : 2; /*!< [23:22] PCS to SCK Delay Prescaler */ - uint32_t LSBFE : 1; /*!< [24] LSB First */ - uint32_t CPHA : 1; /*!< [25] Clock Phase */ - uint32_t CPOL : 1; /*!< [26] Clock Polarity */ - uint32_t FMSZ : 4; /*!< [30:27] Frame Size */ - uint32_t DBR : 1; /*!< [31] Double Baud Rate */ - } B; -} hw_spi_ctarn_t; - -/*! - * @name Constants and macros for entire SPI_CTARn register - */ -/*@{*/ -#define HW_SPI_CTARn_COUNT (2U) - -#define HW_SPI_CTARn_ADDR(x, n) ((x) + 0xCU + (0x4U * (n))) - -#define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n)) -#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U) -#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v)) -#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v))) -#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v))) -#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_CTARn bitfields - */ - -/*! - * @name Register SPI_CTARn, field BR[3:0] (RW) - * - * Selects the scaler value for the baud rate. This field is used only in master - * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to - * generate the frequency of the SCK. The baud rate is computed according to the - * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table - * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler - * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 - * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 - */ -/*@{*/ -#define BP_SPI_CTARn_BR (0U) /*!< Bit position for SPI_CTARn_BR. */ -#define BM_SPI_CTARn_BR (0x0000000FU) /*!< Bit mask for SPI_CTARn_BR. */ -#define BS_SPI_CTARn_BR (4U) /*!< Bit field size in bits for SPI_CTARn_BR. */ - -/*! @brief Read current value of the SPI_CTARn_BR field. */ -#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR) - -/*! @brief Format value for bitfield SPI_CTARn_BR. */ -#define BF_SPI_CTARn_BR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR) - -/*! @brief Set the BR field to a new value. */ -#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field DT[7:4] (RW) - * - * Selects the Delay after Transfer Scaler. This field is used only in master - * mode. The Delay after Transfer is the time between the negation of the PCS - * signal at the end of a frame and the assertion of PCS at the beginning of the next - * frame. In the Continuous Serial Communications Clock operation, the DT value - * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the - * protocol clock period, and it is computed according to the following - * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit - * field description for scaler values. - */ -/*@{*/ -#define BP_SPI_CTARn_DT (4U) /*!< Bit position for SPI_CTARn_DT. */ -#define BM_SPI_CTARn_DT (0x000000F0U) /*!< Bit mask for SPI_CTARn_DT. */ -#define BS_SPI_CTARn_DT (4U) /*!< Bit field size in bits for SPI_CTARn_DT. */ - -/*! @brief Read current value of the SPI_CTARn_DT field. */ -#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT) - -/*! @brief Format value for bitfield SPI_CTARn_DT. */ -#define BF_SPI_CTARn_DT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT) - -/*! @brief Set the DT field to a new value. */ -#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field ASC[11:8] (RW) - * - * Selects the scaler value for the After SCK Delay. This field is used only in - * master mode. The After SCK Delay is the delay between the last edge of SCK and - * the negation of PCS. The delay is a multiple of the protocol clock period, - * and it is computed according to the following equation: t ASC = (1/fP) x PASC x - * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for - * scaler values. Refer After SCK Delay (tASC ) for more details. - */ -/*@{*/ -#define BP_SPI_CTARn_ASC (8U) /*!< Bit position for SPI_CTARn_ASC. */ -#define BM_SPI_CTARn_ASC (0x00000F00U) /*!< Bit mask for SPI_CTARn_ASC. */ -#define BS_SPI_CTARn_ASC (4U) /*!< Bit field size in bits for SPI_CTARn_ASC. */ - -/*! @brief Read current value of the SPI_CTARn_ASC field. */ -#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC) - -/*! @brief Format value for bitfield SPI_CTARn_ASC. */ -#define BF_SPI_CTARn_ASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC) - -/*! @brief Set the ASC field to a new value. */ -#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field CSSCK[15:12] (RW) - * - * Selects the scaler value for the PCS to SCK delay. This field is used only in - * master mode. The PCS to SCK Delay is the delay between the assertion of PCS - * and the first edge of the SCK. The delay is a multiple of the protocol clock - * period, and it is computed according to the following equation: t CSC = (1/fP ) - * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay - * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100 - * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192 - * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more - * details. - */ -/*@{*/ -#define BP_SPI_CTARn_CSSCK (12U) /*!< Bit position for SPI_CTARn_CSSCK. */ -#define BM_SPI_CTARn_CSSCK (0x0000F000U) /*!< Bit mask for SPI_CTARn_CSSCK. */ -#define BS_SPI_CTARn_CSSCK (4U) /*!< Bit field size in bits for SPI_CTARn_CSSCK. */ - -/*! @brief Read current value of the SPI_CTARn_CSSCK field. */ -#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK) - -/*! @brief Format value for bitfield SPI_CTARn_CSSCK. */ -#define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK) - -/*! @brief Set the CSSCK field to a new value. */ -#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PBR[17:16] (RW) - * - * Selects the prescaler value for the baud rate. This field is used only in - * master mode. The baud rate is the frequency of the SCK. The protocol clock is - * divided by the prescaler value before the baud rate selection takes place. See - * the BR field description for details on how to compute the baud rate. - * - * Values: - * - 00 - Baud Rate Prescaler value is 2. - * - 01 - Baud Rate Prescaler value is 3. - * - 10 - Baud Rate Prescaler value is 5. - * - 11 - Baud Rate Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PBR (16U) /*!< Bit position for SPI_CTARn_PBR. */ -#define BM_SPI_CTARn_PBR (0x00030000U) /*!< Bit mask for SPI_CTARn_PBR. */ -#define BS_SPI_CTARn_PBR (2U) /*!< Bit field size in bits for SPI_CTARn_PBR. */ - -/*! @brief Read current value of the SPI_CTARn_PBR field. */ -#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR) - -/*! @brief Format value for bitfield SPI_CTARn_PBR. */ -#define BF_SPI_CTARn_PBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR) - -/*! @brief Set the PBR field to a new value. */ -#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PDT[19:18] (RW) - * - * Selects the prescaler value for the delay between the negation of the PCS - * signal at the end of a frame and the assertion of PCS at the beginning of the - * next frame. The PDT field is only used in master mode. See the DT field - * description for details on how to compute the Delay after Transfer. Refer Delay after - * Transfer (tDT ) for more details. - * - * Values: - * - 00 - Delay after Transfer Prescaler value is 1. - * - 01 - Delay after Transfer Prescaler value is 3. - * - 10 - Delay after Transfer Prescaler value is 5. - * - 11 - Delay after Transfer Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PDT (18U) /*!< Bit position for SPI_CTARn_PDT. */ -#define BM_SPI_CTARn_PDT (0x000C0000U) /*!< Bit mask for SPI_CTARn_PDT. */ -#define BS_SPI_CTARn_PDT (2U) /*!< Bit field size in bits for SPI_CTARn_PDT. */ - -/*! @brief Read current value of the SPI_CTARn_PDT field. */ -#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT) - -/*! @brief Format value for bitfield SPI_CTARn_PDT. */ -#define BF_SPI_CTARn_PDT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT) - -/*! @brief Set the PDT field to a new value. */ -#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PASC[21:20] (RW) - * - * Selects the prescaler value for the delay between the last edge of SCK and - * the negation of PCS. See the ASC field description for information on how to - * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details. - * - * Values: - * - 00 - Delay after Transfer Prescaler value is 1. - * - 01 - Delay after Transfer Prescaler value is 3. - * - 10 - Delay after Transfer Prescaler value is 5. - * - 11 - Delay after Transfer Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PASC (20U) /*!< Bit position for SPI_CTARn_PASC. */ -#define BM_SPI_CTARn_PASC (0x00300000U) /*!< Bit mask for SPI_CTARn_PASC. */ -#define BS_SPI_CTARn_PASC (2U) /*!< Bit field size in bits for SPI_CTARn_PASC. */ - -/*! @brief Read current value of the SPI_CTARn_PASC field. */ -#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC) - -/*! @brief Format value for bitfield SPI_CTARn_PASC. */ -#define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC) - -/*! @brief Set the PASC field to a new value. */ -#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field PCSSCK[23:22] (RW) - * - * Selects the prescaler value for the delay between assertion of PCS and the - * first edge of the SCK. See the CSSCK field description for information on how to - * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details. - * - * Values: - * - 00 - PCS to SCK Prescaler value is 1. - * - 01 - PCS to SCK Prescaler value is 3. - * - 10 - PCS to SCK Prescaler value is 5. - * - 11 - PCS to SCK Prescaler value is 7. - */ -/*@{*/ -#define BP_SPI_CTARn_PCSSCK (22U) /*!< Bit position for SPI_CTARn_PCSSCK. */ -#define BM_SPI_CTARn_PCSSCK (0x00C00000U) /*!< Bit mask for SPI_CTARn_PCSSCK. */ -#define BS_SPI_CTARn_PCSSCK (2U) /*!< Bit field size in bits for SPI_CTARn_PCSSCK. */ - -/*! @brief Read current value of the SPI_CTARn_PCSSCK field. */ -#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK) - -/*! @brief Format value for bitfield SPI_CTARn_PCSSCK. */ -#define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK) - -/*! @brief Set the PCSSCK field to a new value. */ -#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field LSBFE[24] (RW) - * - * Specifies whether the LSB or MSB of the frame is transferred first. - * - * Values: - * - 0 - Data is transferred MSB first. - * - 1 - Data is transferred LSB first. - */ -/*@{*/ -#define BP_SPI_CTARn_LSBFE (24U) /*!< Bit position for SPI_CTARn_LSBFE. */ -#define BM_SPI_CTARn_LSBFE (0x01000000U) /*!< Bit mask for SPI_CTARn_LSBFE. */ -#define BS_SPI_CTARn_LSBFE (1U) /*!< Bit field size in bits for SPI_CTARn_LSBFE. */ - -/*! @brief Read current value of the SPI_CTARn_LSBFE field. */ -#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE)) - -/*! @brief Format value for bitfield SPI_CTARn_LSBFE. */ -#define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE) - -/*! @brief Set the LSBFE field to a new value. */ -#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field CPHA[25] (RW) - * - * Selects which edge of SCK causes data to change and which edge causes data to - * be captured. This bit is used in both master and slave mode. For successful - * communication between serial devices, the devices must have identical clock - * phase settings. In Continuous SCK mode, the bit value is ignored and the - * transfers are done as if the CPHA bit is set to 1. - * - * Values: - * - 0 - Data is captured on the leading edge of SCK and changed on the - * following edge. - * - 1 - Data is changed on the leading edge of SCK and captured on the - * following edge. - */ -/*@{*/ -#define BP_SPI_CTARn_CPHA (25U) /*!< Bit position for SPI_CTARn_CPHA. */ -#define BM_SPI_CTARn_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_CPHA. */ -#define BS_SPI_CTARn_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_CPHA. */ - -/*! @brief Read current value of the SPI_CTARn_CPHA field. */ -#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA)) - -/*! @brief Format value for bitfield SPI_CTARn_CPHA. */ -#define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA) - -/*! @brief Set the CPHA field to a new value. */ -#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field CPOL[26] (RW) - * - * Selects the inactive state of the Serial Communications Clock (SCK). This bit - * is used in both master and slave mode. For successful communication between - * serial devices, the devices must have identical clock polarities. When the - * Continuous Selection Format is selected, switching between clock polarities - * without stopping the module can cause errors in the transfer due to the peripheral - * device interpreting the switch of clock polarity as a valid clock edge. In case - * of continous sck mode, when the module goes in low power mode(disabled), - * inactive state of sck is not guaranted. - * - * Values: - * - 0 - The inactive state value of SCK is low. - * - 1 - The inactive state value of SCK is high. - */ -/*@{*/ -#define BP_SPI_CTARn_CPOL (26U) /*!< Bit position for SPI_CTARn_CPOL. */ -#define BM_SPI_CTARn_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_CPOL. */ -#define BS_SPI_CTARn_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_CPOL. */ - -/*! @brief Read current value of the SPI_CTARn_CPOL field. */ -#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL)) - -/*! @brief Format value for bitfield SPI_CTARn_CPOL. */ -#define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL) - -/*! @brief Set the CPOL field to a new value. */ -#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field FMSZ[30:27] (RW) - * - * The number of bits transferred per frame is equal to the FMSZ value plus 1. - * Regardless of the transmission mode, the minimum valid frame size value is 4. - */ -/*@{*/ -#define BP_SPI_CTARn_FMSZ (27U) /*!< Bit position for SPI_CTARn_FMSZ. */ -#define BM_SPI_CTARn_FMSZ (0x78000000U) /*!< Bit mask for SPI_CTARn_FMSZ. */ -#define BS_SPI_CTARn_FMSZ (4U) /*!< Bit field size in bits for SPI_CTARn_FMSZ. */ - -/*! @brief Read current value of the SPI_CTARn_FMSZ field. */ -#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ) - -/*! @brief Format value for bitfield SPI_CTARn_FMSZ. */ -#define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ) - -/*! @brief Set the FMSZ field to a new value. */ -#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v))) -/*@}*/ - -/*! - * @name Register SPI_CTARn, field DBR[31] (RW) - * - * Doubles the effective baud rate of the Serial Communications Clock (SCK). - * This field is used only in master mode. It effectively halves the Baud Rate - * division ratio, supporting faster frequencies, and odd division ratios for the - * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the - * Serial Communications Clock (SCK) depends on the value in the Baud Rate - * Prescaler and the Clock Phase bit as listed in the following table. See the BR field - * description for details on how to compute the baud rate. SPI SCK Duty Cycle - * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 - * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 - * - * Values: - * - 0 - The baud rate is computed normally with a 50/50 duty cycle. - * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate - * Prescaler. - */ -/*@{*/ -#define BP_SPI_CTARn_DBR (31U) /*!< Bit position for SPI_CTARn_DBR. */ -#define BM_SPI_CTARn_DBR (0x80000000U) /*!< Bit mask for SPI_CTARn_DBR. */ -#define BS_SPI_CTARn_DBR (1U) /*!< Bit field size in bits for SPI_CTARn_DBR. */ - -/*! @brief Read current value of the SPI_CTARn_DBR field. */ -#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR)) - -/*! @brief Format value for bitfield SPI_CTARn_DBR. */ -#define BF_SPI_CTARn_DBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR) - -/*! @brief Set the DBR field to a new value. */ -#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v)) -/*@}*/ -/******************************************************************************* - * HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) - ******************************************************************************/ - -/*! - * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW) - * - * Reset value: 0x78000000U - * - * When the module is configured as an SPI bus slave, the CTAR0 register is used. - */ -typedef union _hw_spi_ctarn_slave -{ - uint32_t U; - struct _hw_spi_ctarn_slave_bitfields - { - uint32_t RESERVED0 : 25; /*!< [24:0] */ - uint32_t CPHA : 1; /*!< [25] Clock Phase */ - uint32_t CPOL : 1; /*!< [26] Clock Polarity */ - uint32_t FMSZ : 5; /*!< [31:27] Frame Size */ - } B; -} hw_spi_ctarn_slave_t; - -/*! - * @name Constants and macros for entire SPI_CTARn_SLAVE register - */ -/*@{*/ -#define HW_SPI_CTARn_SLAVE_COUNT (1U) - -#define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n))) - -#define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n)) -#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U) -#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v)) -#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v))) -#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v))) -#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_CTARn_SLAVE bitfields - */ - -/*! - * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW) - * - * Selects which edge of SCK causes data to change and which edge causes data to - * be captured. This bit is used in both master and slave mode. For successful - * communication between serial devices, the devices must have identical clock - * phase settings. In Continuous SCK mode, the bit value is ignored and the - * transfers are done as if the CPHA bit is set to 1. - * - * Values: - * - 0 - Data is captured on the leading edge of SCK and changed on the - * following edge. - * - 1 - Data is changed on the leading edge of SCK and captured on the - * following edge. - */ -/*@{*/ -#define BP_SPI_CTARn_SLAVE_CPHA (25U) /*!< Bit position for SPI_CTARn_SLAVE_CPHA. */ -#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPHA. */ -#define BS_SPI_CTARn_SLAVE_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. */ - -/*! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. */ -#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA)) - -/*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. */ -#define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA) - -/*! @brief Set the CPHA field to a new value. */ -#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW) - * - * Selects the inactive state of the Serial Communications Clock (SCK). In case - * of continous sck mode, when the module goes in low power mode(disabled), - * inactive state of sck is not guaranted. - * - * Values: - * - 0 - The inactive state value of SCK is low. - * - 1 - The inactive state value of SCK is high. - */ -/*@{*/ -#define BP_SPI_CTARn_SLAVE_CPOL (26U) /*!< Bit position for SPI_CTARn_SLAVE_CPOL. */ -#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPOL. */ -#define BS_SPI_CTARn_SLAVE_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. */ - -/*! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. */ -#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL)) - -/*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. */ -#define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL) - -/*! @brief Set the CPOL field to a new value. */ -#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v)) -/*@}*/ - -/*! - * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW) - * - * The number of bits transfered per frame is equal to the FMSZ field value plus - * 1. Note that the minimum valid value of frame size is 4. - */ -/*@{*/ -#define BP_SPI_CTARn_SLAVE_FMSZ (27U) /*!< Bit position for SPI_CTARn_SLAVE_FMSZ. */ -#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /*!< Bit mask for SPI_CTARn_SLAVE_FMSZ. */ -#define BS_SPI_CTARn_SLAVE_FMSZ (5U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. */ - -/*! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. */ -#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ) - -/*! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. */ -#define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ) - -/*! @brief Set the FMSZ field to a new value. */ -#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v))) -/*@}*/ - -/******************************************************************************* - * HW_SPI_SR - Status Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_SR - Status Register (RW) - * - * Reset value: 0x02000000U - * - * SR contains status and flag bits. The bits reflect the status of the module - * and indicate the occurrence of events that can generate interrupt or DMA - * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0 - * to a flag bit has no effect. This register may not be writable in Module - * Disable mode due to the use of power saving mechanisms. - */ -typedef union _hw_spi_sr -{ - uint32_t U; - struct _hw_spi_sr_bitfields - { - uint32_t POPNXTPTR : 4; /*!< [3:0] Pop Next Pointer */ - uint32_t RXCTR : 4; /*!< [7:4] RX FIFO Counter */ - uint32_t TXNXTPTR : 4; /*!< [11:8] Transmit Next Pointer */ - uint32_t TXCTR : 4; /*!< [15:12] TX FIFO Counter */ - uint32_t RESERVED0 : 1; /*!< [16] */ - uint32_t RFDF : 1; /*!< [17] Receive FIFO Drain Flag */ - uint32_t RESERVED1 : 1; /*!< [18] */ - uint32_t RFOF : 1; /*!< [19] Receive FIFO Overflow Flag */ - uint32_t RESERVED2 : 5; /*!< [24:20] */ - uint32_t TFFF : 1; /*!< [25] Transmit FIFO Fill Flag */ - uint32_t RESERVED3 : 1; /*!< [26] */ - uint32_t TFUF : 1; /*!< [27] Transmit FIFO Underflow Flag */ - uint32_t EOQF : 1; /*!< [28] End of Queue Flag */ - uint32_t RESERVED4 : 1; /*!< [29] */ - uint32_t TXRXS : 1; /*!< [30] TX and RX Status */ - uint32_t TCF : 1; /*!< [31] Transfer Complete Flag */ - } B; -} hw_spi_sr_t; - -/*! - * @name Constants and macros for entire SPI_SR register - */ -/*@{*/ -#define HW_SPI_SR_ADDR(x) ((x) + 0x2CU) - -#define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x)) -#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U) -#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v)) -#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v))) -#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v))) -#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_SR bitfields - */ - -/*! - * @name Register SPI_SR, field POPNXTPTR[3:0] (RO) - * - * Contains a pointer to the RX FIFO entry to be returned when the POPR is read. - * The POPNXTPTR is updated when the POPR is read. - */ -/*@{*/ -#define BP_SPI_SR_POPNXTPTR (0U) /*!< Bit position for SPI_SR_POPNXTPTR. */ -#define BM_SPI_SR_POPNXTPTR (0x0000000FU) /*!< Bit mask for SPI_SR_POPNXTPTR. */ -#define BS_SPI_SR_POPNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_POPNXTPTR. */ - -/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */ -#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field RXCTR[7:4] (RO) - * - * Indicates the number of entries in the RX FIFO. The RXCTR is decremented - * every time the POPR is read. The RXCTR is incremented every time data is - * transferred from the shift register to the RX FIFO. - */ -/*@{*/ -#define BP_SPI_SR_RXCTR (4U) /*!< Bit position for SPI_SR_RXCTR. */ -#define BM_SPI_SR_RXCTR (0x000000F0U) /*!< Bit mask for SPI_SR_RXCTR. */ -#define BS_SPI_SR_RXCTR (4U) /*!< Bit field size in bits for SPI_SR_RXCTR. */ - -/*! @brief Read current value of the SPI_SR_RXCTR field. */ -#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field TXNXTPTR[11:8] (RO) - * - * Indicates which TX FIFO entry is transmitted during the next transfer. The - * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to - * the shift register. - */ -/*@{*/ -#define BP_SPI_SR_TXNXTPTR (8U) /*!< Bit position for SPI_SR_TXNXTPTR. */ -#define BM_SPI_SR_TXNXTPTR (0x00000F00U) /*!< Bit mask for SPI_SR_TXNXTPTR. */ -#define BS_SPI_SR_TXNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_TXNXTPTR. */ - -/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */ -#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field TXCTR[15:12] (RO) - * - * Indicates the number of valid entries in the TX FIFO. The TXCTR is - * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI - * command is executed and the SPI data is transferred to the shift register. - */ -/*@{*/ -#define BP_SPI_SR_TXCTR (12U) /*!< Bit position for SPI_SR_TXCTR. */ -#define BM_SPI_SR_TXCTR (0x0000F000U) /*!< Bit mask for SPI_SR_TXCTR. */ -#define BS_SPI_SR_TXCTR (4U) /*!< Bit field size in bits for SPI_SR_TXCTR. */ - -/*! @brief Read current value of the SPI_SR_TXCTR field. */ -#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR) -/*@}*/ - -/*! - * @name Register SPI_SR, field RFDF[17] (W1C) - * - * Provides a method for the module to request that entries be removed from the - * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be - * cleared by writing 1 to it or by acknowledgement from the DMA controller when - * the RX FIFO is empty. - * - * Values: - * - 0 - RX FIFO is empty. - * - 1 - RX FIFO is not empty. - */ -/*@{*/ -#define BP_SPI_SR_RFDF (17U) /*!< Bit position for SPI_SR_RFDF. */ -#define BM_SPI_SR_RFDF (0x00020000U) /*!< Bit mask for SPI_SR_RFDF. */ -#define BS_SPI_SR_RFDF (1U) /*!< Bit field size in bits for SPI_SR_RFDF. */ - -/*! @brief Read current value of the SPI_SR_RFDF field. */ -#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF)) - -/*! @brief Format value for bitfield SPI_SR_RFDF. */ -#define BF_SPI_SR_RFDF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF) - -/*! @brief Set the RFDF field to a new value. */ -#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field RFOF[19] (W1C) - * - * Indicates an overflow condition in the RX FIFO. The field is set when the RX - * FIFO and shift register are full and a transfer is initiated. The bit remains - * set until it is cleared by writing a 1 to it. - * - * Values: - * - 0 - No Rx FIFO overflow. - * - 1 - Rx FIFO overflow has occurred. - */ -/*@{*/ -#define BP_SPI_SR_RFOF (19U) /*!< Bit position for SPI_SR_RFOF. */ -#define BM_SPI_SR_RFOF (0x00080000U) /*!< Bit mask for SPI_SR_RFOF. */ -#define BS_SPI_SR_RFOF (1U) /*!< Bit field size in bits for SPI_SR_RFOF. */ - -/*! @brief Read current value of the SPI_SR_RFOF field. */ -#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF)) - -/*! @brief Format value for bitfield SPI_SR_RFOF. */ -#define BF_SPI_SR_RFOF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF) - -/*! @brief Set the RFOF field to a new value. */ -#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TFFF[25] (W1C) - * - * Provides a method for the module to request more entries to be added to the - * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be - * cleared by writing 1 to it or by acknowledgement from the DMA controller to - * the TX FIFO full request. - * - * Values: - * - 0 - TX FIFO is full. - * - 1 - TX FIFO is not full. - */ -/*@{*/ -#define BP_SPI_SR_TFFF (25U) /*!< Bit position for SPI_SR_TFFF. */ -#define BM_SPI_SR_TFFF (0x02000000U) /*!< Bit mask for SPI_SR_TFFF. */ -#define BS_SPI_SR_TFFF (1U) /*!< Bit field size in bits for SPI_SR_TFFF. */ - -/*! @brief Read current value of the SPI_SR_TFFF field. */ -#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF)) - -/*! @brief Format value for bitfield SPI_SR_TFFF. */ -#define BF_SPI_SR_TFFF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF) - -/*! @brief Set the TFFF field to a new value. */ -#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TFUF[27] (W1C) - * - * Indicates an underflow condition in the TX FIFO. The transmit underflow - * condition is detected only for SPI blocks operating in Slave mode and SPI - * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode - * is empty and an external SPI master initiates a transfer. The TFUF bit remains - * set until cleared by writing 1 to it. - * - * Values: - * - 0 - No TX FIFO underflow. - * - 1 - TX FIFO underflow has occurred. - */ -/*@{*/ -#define BP_SPI_SR_TFUF (27U) /*!< Bit position for SPI_SR_TFUF. */ -#define BM_SPI_SR_TFUF (0x08000000U) /*!< Bit mask for SPI_SR_TFUF. */ -#define BS_SPI_SR_TFUF (1U) /*!< Bit field size in bits for SPI_SR_TFUF. */ - -/*! @brief Read current value of the SPI_SR_TFUF field. */ -#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF)) - -/*! @brief Format value for bitfield SPI_SR_TFUF. */ -#define BF_SPI_SR_TFUF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF) - -/*! @brief Set the TFUF field to a new value. */ -#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field EOQF[28] (W1C) - * - * Indicates that the last entry in a queue has been transmitted when the module - * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit - * set in the command halfword and the end of the transfer is reached. The EOQF - * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set, - * the TXRXS bit is automatically cleared. - * - * Values: - * - 0 - EOQ is not set in the executing command. - * - 1 - EOQ is set in the executing SPI command. - */ -/*@{*/ -#define BP_SPI_SR_EOQF (28U) /*!< Bit position for SPI_SR_EOQF. */ -#define BM_SPI_SR_EOQF (0x10000000U) /*!< Bit mask for SPI_SR_EOQF. */ -#define BS_SPI_SR_EOQF (1U) /*!< Bit field size in bits for SPI_SR_EOQF. */ - -/*! @brief Read current value of the SPI_SR_EOQF field. */ -#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF)) - -/*! @brief Format value for bitfield SPI_SR_EOQF. */ -#define BF_SPI_SR_EOQF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF) - -/*! @brief Set the EOQF field to a new value. */ -#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TXRXS[30] (W1C) - * - * Reflects the run status of the module. - * - * Values: - * - 0 - Transmit and receive operations are disabled (The module is in Stopped - * state). - * - 1 - Transmit and receive operations are enabled (The module is in Running - * state). - */ -/*@{*/ -#define BP_SPI_SR_TXRXS (30U) /*!< Bit position for SPI_SR_TXRXS. */ -#define BM_SPI_SR_TXRXS (0x40000000U) /*!< Bit mask for SPI_SR_TXRXS. */ -#define BS_SPI_SR_TXRXS (1U) /*!< Bit field size in bits for SPI_SR_TXRXS. */ - -/*! @brief Read current value of the SPI_SR_TXRXS field. */ -#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS)) - -/*! @brief Format value for bitfield SPI_SR_TXRXS. */ -#define BF_SPI_SR_TXRXS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS) - -/*! @brief Set the TXRXS field to a new value. */ -#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_SR, field TCF[31] (W1C) - * - * Indicates that all bits in a frame have been shifted out. TCF remains set - * until it is cleared by writing a 1 to it. - * - * Values: - * - 0 - Transfer not complete. - * - 1 - Transfer complete. - */ -/*@{*/ -#define BP_SPI_SR_TCF (31U) /*!< Bit position for SPI_SR_TCF. */ -#define BM_SPI_SR_TCF (0x80000000U) /*!< Bit mask for SPI_SR_TCF. */ -#define BS_SPI_SR_TCF (1U) /*!< Bit field size in bits for SPI_SR_TCF. */ - -/*! @brief Read current value of the SPI_SR_TCF field. */ -#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF)) - -/*! @brief Format value for bitfield SPI_SR_TCF. */ -#define BF_SPI_SR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF) - -/*! @brief Set the TCF field to a new value. */ -#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW) - * - * Reset value: 0x00000000U - * - * RSER controls DMA and interrupt requests. Do not write to the RSER while the - * module is in the Running state. - */ -typedef union _hw_spi_rser -{ - uint32_t U; - struct _hw_spi_rser_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t RFDF_DIRS : 1; /*!< [16] Receive FIFO Drain DMA or Interrupt - * Request Select */ - uint32_t RFDF_RE : 1; /*!< [17] Receive FIFO Drain Request Enable */ - uint32_t RESERVED1 : 1; /*!< [18] */ - uint32_t RFOF_RE : 1; /*!< [19] Receive FIFO Overflow Request Enable - * */ - uint32_t RESERVED2 : 4; /*!< [23:20] */ - uint32_t TFFF_DIRS : 1; /*!< [24] Transmit FIFO Fill DMA or Interrupt - * Request Select */ - uint32_t TFFF_RE : 1; /*!< [25] Transmit FIFO Fill Request Enable */ - uint32_t RESERVED3 : 1; /*!< [26] */ - uint32_t TFUF_RE : 1; /*!< [27] Transmit FIFO Underflow Request - * Enable */ - uint32_t EOQF_RE : 1; /*!< [28] Finished Request Enable */ - uint32_t RESERVED4 : 2; /*!< [30:29] */ - uint32_t TCF_RE : 1; /*!< [31] Transmission Complete Request Enable */ - } B; -} hw_spi_rser_t; - -/*! - * @name Constants and macros for entire SPI_RSER register - */ -/*@{*/ -#define HW_SPI_RSER_ADDR(x) ((x) + 0x30U) - -#define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x)) -#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U) -#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v)) -#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v))) -#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v))) -#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_RSER bitfields - */ - -/*! - * @name Register SPI_RSER, field RFDF_DIRS[16] (RW) - * - * Selects between generating a DMA request or an interrupt request. When the - * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the - * RFDF_DIRS bit selects between generating an interrupt request or a DMA request. - * - * Values: - * - 0 - Interrupt request. - * - 1 - DMA request. - */ -/*@{*/ -#define BP_SPI_RSER_RFDF_DIRS (16U) /*!< Bit position for SPI_RSER_RFDF_DIRS. */ -#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /*!< Bit mask for SPI_RSER_RFDF_DIRS. */ -#define BS_SPI_RSER_RFDF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_DIRS. */ - -/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */ -#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS)) - -/*! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. */ -#define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS) - -/*! @brief Set the RFDF_DIRS field to a new value. */ -#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field RFDF_RE[17] (RW) - * - * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit - * selects between generating an interrupt request or a DMA request. - * - * Values: - * - 0 - RFDF interrupt or DMA requests are disabled. - * - 1 - RFDF interrupt or DMA requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_RFDF_RE (17U) /*!< Bit position for SPI_RSER_RFDF_RE. */ -#define BM_SPI_RSER_RFDF_RE (0x00020000U) /*!< Bit mask for SPI_RSER_RFDF_RE. */ -#define BS_SPI_RSER_RFDF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_RE. */ - -/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */ -#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_RFDF_RE. */ -#define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE) - -/*! @brief Set the RFDF_RE field to a new value. */ -#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field RFOF_RE[19] (RW) - * - * Enables the RFOF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - RFOF interrupt requests are disabled. - * - 1 - RFOF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_RFOF_RE (19U) /*!< Bit position for SPI_RSER_RFOF_RE. */ -#define BM_SPI_RSER_RFOF_RE (0x00080000U) /*!< Bit mask for SPI_RSER_RFOF_RE. */ -#define BS_SPI_RSER_RFOF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFOF_RE. */ - -/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */ -#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_RFOF_RE. */ -#define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE) - -/*! @brief Set the RFOF_RE field to a new value. */ -#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TFFF_DIRS[24] (RW) - * - * Selects between generating a DMA request or an interrupt request. When - * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an - * interrupt request or a DMA request. - * - * Values: - * - 0 - TFFF flag generates interrupt requests. - * - 1 - TFFF flag generates DMA requests. - */ -/*@{*/ -#define BP_SPI_RSER_TFFF_DIRS (24U) /*!< Bit position for SPI_RSER_TFFF_DIRS. */ -#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /*!< Bit mask for SPI_RSER_TFFF_DIRS. */ -#define BS_SPI_RSER_TFFF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_DIRS. */ - -/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */ -#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS)) - -/*! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. */ -#define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS) - -/*! @brief Set the TFFF_DIRS field to a new value. */ -#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TFFF_RE[25] (RW) - * - * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit - * selects between generating an interrupt request or a DMA request. - * - * Values: - * - 0 - TFFF interrupts or DMA requests are disabled. - * - 1 - TFFF interrupts or DMA requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_TFFF_RE (25U) /*!< Bit position for SPI_RSER_TFFF_RE. */ -#define BM_SPI_RSER_TFFF_RE (0x02000000U) /*!< Bit mask for SPI_RSER_TFFF_RE. */ -#define BS_SPI_RSER_TFFF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_RE. */ - -/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */ -#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_TFFF_RE. */ -#define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE) - -/*! @brief Set the TFFF_RE field to a new value. */ -#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TFUF_RE[27] (RW) - * - * Enables the TFUF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - TFUF interrupt requests are disabled. - * - 1 - TFUF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_TFUF_RE (27U) /*!< Bit position for SPI_RSER_TFUF_RE. */ -#define BM_SPI_RSER_TFUF_RE (0x08000000U) /*!< Bit mask for SPI_RSER_TFUF_RE. */ -#define BS_SPI_RSER_TFUF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFUF_RE. */ - -/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */ -#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_TFUF_RE. */ -#define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE) - -/*! @brief Set the TFUF_RE field to a new value. */ -#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field EOQF_RE[28] (RW) - * - * Enables the EOQF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - EOQF interrupt requests are disabled. - * - 1 - EOQF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_EOQF_RE (28U) /*!< Bit position for SPI_RSER_EOQF_RE. */ -#define BM_SPI_RSER_EOQF_RE (0x10000000U) /*!< Bit mask for SPI_RSER_EOQF_RE. */ -#define BS_SPI_RSER_EOQF_RE (1U) /*!< Bit field size in bits for SPI_RSER_EOQF_RE. */ - -/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */ -#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_EOQF_RE. */ -#define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE) - -/*! @brief Set the EOQF_RE field to a new value. */ -#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v)) -/*@}*/ - -/*! - * @name Register SPI_RSER, field TCF_RE[31] (RW) - * - * Enables TCF flag in the SR to generate an interrupt request. - * - * Values: - * - 0 - TCF interrupt requests are disabled. - * - 1 - TCF interrupt requests are enabled. - */ -/*@{*/ -#define BP_SPI_RSER_TCF_RE (31U) /*!< Bit position for SPI_RSER_TCF_RE. */ -#define BM_SPI_RSER_TCF_RE (0x80000000U) /*!< Bit mask for SPI_RSER_TCF_RE. */ -#define BS_SPI_RSER_TCF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TCF_RE. */ - -/*! @brief Read current value of the SPI_RSER_TCF_RE field. */ -#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE)) - -/*! @brief Format value for bitfield SPI_RSER_TCF_RE. */ -#define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE) - -/*! @brief Set the TCF_RE field to a new value. */ -#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode - ******************************************************************************/ - -/*! - * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW) - * - * Reset value: 0x00000000U - * - * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access - * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers - * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits - * can be used as data, supporting up to 32-bit frame operation. A read access - * of PUSHR returns the topmost TX FIFO entry. When the module is disabled, - * writing to this register does not update the FIFO. Therefore, any reads performed - * while the module is disabled return the last PUSHR write performed while the - * module was still enabled. - */ -typedef union _hw_spi_pushr -{ - uint32_t U; - struct _hw_spi_pushr_bitfields - { - uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */ - uint32_t PCS : 6; /*!< [21:16] */ - uint32_t RESERVED0 : 4; /*!< [25:22] */ - uint32_t CTCNT : 1; /*!< [26] Clear Transfer Counter */ - uint32_t EOQ : 1; /*!< [27] End Of Queue */ - uint32_t CTAS : 3; /*!< [30:28] Clock and Transfer Attributes Select - * */ - uint32_t CONT : 1; /*!< [31] Continuous Peripheral Chip Select Enable - * */ - } B; -} hw_spi_pushr_t; - -/*! - * @name Constants and macros for entire SPI_PUSHR register - */ -/*@{*/ -#define HW_SPI_PUSHR_ADDR(x) ((x) + 0x34U) - -#define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x)) -#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U) -#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v)) -#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v))) -#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v))) -#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_PUSHR bitfields - */ - -/*! - * @name Register SPI_PUSHR, field TXDATA[15:0] (RW) - * - * Holds SPI data to be transferred according to the associated SPI command. - */ -/*@{*/ -#define BP_SPI_PUSHR_TXDATA (0U) /*!< Bit position for SPI_PUSHR_TXDATA. */ -#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_PUSHR_TXDATA. */ -#define BS_SPI_PUSHR_TXDATA (16U) /*!< Bit field size in bits for SPI_PUSHR_TXDATA. */ - -/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */ -#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA) - -/*! @brief Format value for bitfield SPI_PUSHR_TXDATA. */ -#define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA) - -/*! @brief Set the TXDATA field to a new value. */ -#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v))) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field PCS[21:16] (RW) - * - * Select which PCS signals are to be asserted for the transfer. Refer to the - * chip configuration details for the number of PCS signals used in this MCU. - * - * Values: - * - 0 - Negate the PCS[x] signal. - * - 1 - Assert the PCS[x] signal. - */ -/*@{*/ -#define BP_SPI_PUSHR_PCS (16U) /*!< Bit position for SPI_PUSHR_PCS. */ -#define BM_SPI_PUSHR_PCS (0x003F0000U) /*!< Bit mask for SPI_PUSHR_PCS. */ -#define BS_SPI_PUSHR_PCS (6U) /*!< Bit field size in bits for SPI_PUSHR_PCS. */ - -/*! @brief Read current value of the SPI_PUSHR_PCS field. */ -#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS) - -/*! @brief Format value for bitfield SPI_PUSHR_PCS. */ -#define BF_SPI_PUSHR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS) - -/*! @brief Set the PCS field to a new value. */ -#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v))) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field CTCNT[26] (RW) - * - * Clears the TCNT field in the TCR register. The TCNT field is cleared before - * the module starts transmitting the current SPI frame. - * - * Values: - * - 0 - Do not clear the TCR[TCNT] field. - * - 1 - Clear the TCR[TCNT] field. - */ -/*@{*/ -#define BP_SPI_PUSHR_CTCNT (26U) /*!< Bit position for SPI_PUSHR_CTCNT. */ -#define BM_SPI_PUSHR_CTCNT (0x04000000U) /*!< Bit mask for SPI_PUSHR_CTCNT. */ -#define BS_SPI_PUSHR_CTCNT (1U) /*!< Bit field size in bits for SPI_PUSHR_CTCNT. */ - -/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */ -#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT)) - -/*! @brief Format value for bitfield SPI_PUSHR_CTCNT. */ -#define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT) - -/*! @brief Set the CTCNT field to a new value. */ -#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v)) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field EOQ[27] (RW) - * - * Host software uses this bit to signal to the module that the current SPI - * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the - * SR is set. - * - * Values: - * - 0 - The SPI data is not the last data to transfer. - * - 1 - The SPI data is the last data to transfer. - */ -/*@{*/ -#define BP_SPI_PUSHR_EOQ (27U) /*!< Bit position for SPI_PUSHR_EOQ. */ -#define BM_SPI_PUSHR_EOQ (0x08000000U) /*!< Bit mask for SPI_PUSHR_EOQ. */ -#define BS_SPI_PUSHR_EOQ (1U) /*!< Bit field size in bits for SPI_PUSHR_EOQ. */ - -/*! @brief Read current value of the SPI_PUSHR_EOQ field. */ -#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ)) - -/*! @brief Format value for bitfield SPI_PUSHR_EOQ. */ -#define BF_SPI_PUSHR_EOQ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ) - -/*! @brief Set the EOQ field to a new value. */ -#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v)) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field CTAS[30:28] (RW) - * - * Selects which CTAR to use in master mode to specify the transfer attributes - * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip - * configuration details to determine how many CTARs this device has. You should - * not program a value in this field for a register that is not present. - * - * Values: - * - 000 - CTAR0 - * - 001 - CTAR1 - * - 010 - Reserved - * - 011 - Reserved - * - 100 - Reserved - * - 101 - Reserved - * - 110 - Reserved - * - 111 - Reserved - */ -/*@{*/ -#define BP_SPI_PUSHR_CTAS (28U) /*!< Bit position for SPI_PUSHR_CTAS. */ -#define BM_SPI_PUSHR_CTAS (0x70000000U) /*!< Bit mask for SPI_PUSHR_CTAS. */ -#define BS_SPI_PUSHR_CTAS (3U) /*!< Bit field size in bits for SPI_PUSHR_CTAS. */ - -/*! @brief Read current value of the SPI_PUSHR_CTAS field. */ -#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS) - -/*! @brief Format value for bitfield SPI_PUSHR_CTAS. */ -#define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS) - -/*! @brief Set the CTAS field to a new value. */ -#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v))) -/*@}*/ - -/*! - * @name Register SPI_PUSHR, field CONT[31] (RW) - * - * Selects a continuous selection format. The bit is used in SPI Master mode. - * The bit enables the selected PCS signals to remain asserted between transfers. - * - * Values: - * - 0 - Return PCSn signals to their inactive state between transfers. - * - 1 - Keep PCSn signals asserted between transfers. - */ -/*@{*/ -#define BP_SPI_PUSHR_CONT (31U) /*!< Bit position for SPI_PUSHR_CONT. */ -#define BM_SPI_PUSHR_CONT (0x80000000U) /*!< Bit mask for SPI_PUSHR_CONT. */ -#define BS_SPI_PUSHR_CONT (1U) /*!< Bit field size in bits for SPI_PUSHR_CONT. */ - -/*! @brief Read current value of the SPI_PUSHR_CONT field. */ -#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT)) - -/*! @brief Format value for bitfield SPI_PUSHR_CONT. */ -#define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT) - -/*! @brief Set the CONT field to a new value. */ -#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v)) -/*@}*/ -/******************************************************************************* - * HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode - ******************************************************************************/ - -/*! - * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW) - * - * Reset value: 0x00000000U - * - * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access - * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register - * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In - * slave mode, all 32 register bits can be used as data, supporting up to 32-bit - * SPI Frame operation. - */ -typedef union _hw_spi_pushr_slave -{ - uint32_t U; - struct _hw_spi_pushr_slave_bitfields - { - uint32_t TXDATA : 32; /*!< [31:0] Transmit Data */ - } B; -} hw_spi_pushr_slave_t; - -/*! - * @name Constants and macros for entire SPI_PUSHR_SLAVE register - */ -/*@{*/ -#define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U) - -#define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x)) -#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U) -#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v)) -#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v))) -#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v))) -#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual SPI_PUSHR_SLAVE bitfields - */ - -/*! - * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW) - * - * Holds SPI data to be transferred according to the associated SPI command. - */ -/*@{*/ -#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) /*!< Bit position for SPI_PUSHR_SLAVE_TXDATA. */ -#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. */ -#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) /*!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. */ - -/*! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. */ -#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U) - -/*! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. */ -#define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA) - -/*! @brief Set the TXDATA field to a new value. */ -#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_SPI_POPR - POP RX FIFO Register - ******************************************************************************/ - -/*! - * @brief HW_SPI_POPR - POP RX FIFO Register (RO) - * - * Reset value: 0x00000000U - * - * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the - * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to - * this register will generate a Transfer Error. - */ -typedef union _hw_spi_popr -{ - uint32_t U; - struct _hw_spi_popr_bitfields - { - uint32_t RXDATA : 32; /*!< [31:0] Received Data */ - } B; -} hw_spi_popr_t; - -/*! - * @name Constants and macros for entire SPI_POPR register - */ -/*@{*/ -#define HW_SPI_POPR_ADDR(x) ((x) + 0x38U) - -#define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x)) -#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U) -/*@}*/ - -/* - * Constants & macros for individual SPI_POPR bitfields - */ - -/*! - * @name Register SPI_POPR, field RXDATA[31:0] (RO) - * - * Contains the SPI data from the RX FIFO entry to which the Pop Next Data - * Pointer points. - */ -/*@{*/ -#define BP_SPI_POPR_RXDATA (0U) /*!< Bit position for SPI_POPR_RXDATA. */ -#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_POPR_RXDATA. */ -#define BS_SPI_POPR_RXDATA (32U) /*!< Bit field size in bits for SPI_POPR_RXDATA. */ - -/*! @brief Read current value of the SPI_POPR_RXDATA field. */ -#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U) -/*@}*/ - -/******************************************************************************* - * HW_SPI_TXFRn - Transmit FIFO Registers - ******************************************************************************/ - -/*! - * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO) - * - * Reset value: 0x00000000U - * - * TXFRn registers provide visibility into the TX FIFO for debugging purposes. - * Each register is an entry in the TX FIFO. The registers are read-only and - * cannot be modified. Reading the TXFRx registers does not alter the state of the TX - * FIFO. - */ -typedef union _hw_spi_txfrn -{ - uint32_t U; - struct _hw_spi_txfrn_bitfields - { - uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */ - uint32_t TXCMD_TXDATA : 16; /*!< [31:16] Transmit Command or Transmit - * Data */ - } B; -} hw_spi_txfrn_t; - -/*! - * @name Constants and macros for entire SPI_TXFRn register - */ -/*@{*/ -#define HW_SPI_TXFRn_COUNT (4U) - -#define HW_SPI_TXFRn_ADDR(x, n) ((x) + 0x3CU + (0x4U * (n))) - -#define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n)) -#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual SPI_TXFRn bitfields - */ - -/*! - * @name Register SPI_TXFRn, field TXDATA[15:0] (RO) - * - * Contains the SPI data to be shifted out. - */ -/*@{*/ -#define BP_SPI_TXFRn_TXDATA (0U) /*!< Bit position for SPI_TXFRn_TXDATA. */ -#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_TXFRn_TXDATA. */ -#define BS_SPI_TXFRn_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXDATA. */ - -/*! @brief Read current value of the SPI_TXFRn_TXDATA field. */ -#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA) -/*@}*/ - -/*! - * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO) - * - * In Master mode the TXCMD field contains the command that sets the transfer - * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of - * the SPI data to be shifted out. - */ -/*@{*/ -#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit position for SPI_TXFRn_TXCMD_TXDATA. */ -#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /*!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. */ -#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. */ - -/*! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. */ -#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA) -/*@}*/ - -/******************************************************************************* - * HW_SPI_RXFRn - Receive FIFO Registers - ******************************************************************************/ - -/*! - * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO) - * - * Reset value: 0x00000000U - * - * RXFRn provide visibility into the RX FIFO for debugging purposes. Each - * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the - * RXFRx registers does not alter the state of the RX FIFO. - */ -typedef union _hw_spi_rxfrn -{ - uint32_t U; - struct _hw_spi_rxfrn_bitfields - { - uint32_t RXDATA : 32; /*!< [31:0] Receive Data */ - } B; -} hw_spi_rxfrn_t; - -/*! - * @name Constants and macros for entire SPI_RXFRn register - */ -/*@{*/ -#define HW_SPI_RXFRn_COUNT (4U) - -#define HW_SPI_RXFRn_ADDR(x, n) ((x) + 0x7CU + (0x4U * (n))) - -#define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n)) -#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U) -/*@}*/ - -/* - * Constants & macros for individual SPI_RXFRn bitfields - */ - -/*! - * @name Register SPI_RXFRn, field RXDATA[31:0] (RO) - * - * Contains the received SPI data. - */ -/*@{*/ -#define BP_SPI_RXFRn_RXDATA (0U) /*!< Bit position for SPI_RXFRn_RXDATA. */ -#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_RXFRn_RXDATA. */ -#define BS_SPI_RXFRn_RXDATA (32U) /*!< Bit field size in bits for SPI_RXFRn_RXDATA. */ - -/*! @brief Read current value of the SPI_RXFRn_RXDATA field. */ -#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_spi_t - module struct - ******************************************************************************/ -/*! - * @brief All SPI module registers. - */ -#pragma pack(1) -typedef struct _hw_spi -{ - __IO hw_spi_mcr_t MCR; /*!< [0x0] Module Configuration Register */ - uint8_t _reserved0[4]; - __IO hw_spi_tcr_t TCR; /*!< [0x8] Transfer Count Register */ - union { - __IO hw_spi_ctarn_t CTARn[2]; /*!< [0xC] Clock and Transfer Attributes Register (In Master Mode) */ - __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; /*!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) */ - }; - uint8_t _reserved1[24]; - __IO hw_spi_sr_t SR; /*!< [0x2C] Status Register */ - __IO hw_spi_rser_t RSER; /*!< [0x30] DMA/Interrupt Request Select and Enable Register */ - union { - __IO hw_spi_pushr_t PUSHR; /*!< [0x34] PUSH TX FIFO Register In Master Mode */ - __IO hw_spi_pushr_slave_t PUSHR_SLAVE; /*!< [0x34] PUSH TX FIFO Register In Slave Mode */ - }; - __I hw_spi_popr_t POPR; /*!< [0x38] POP RX FIFO Register */ - __I hw_spi_txfrn_t TXFRn[4]; /*!< [0x3C] Transmit FIFO Registers */ - uint8_t _reserved2[48]; - __I hw_spi_rxfrn_t RXFRn[4]; /*!< [0x7C] Receive FIFO Registers */ -} hw_spi_t; -#pragma pack() - -/*! @brief Macro to access all SPI registers. */ -/*! @param x SPI module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_SPI(SPI0_BASE). */ -#define HW_SPI(x) (*(hw_spi_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_SPI_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_uart.h deleted file mode 100644 index 5667921db4f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_uart.h +++ /dev/null @@ -1,4474 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_UART_REGISTERS_H__ -#define __HW_UART_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 UART - * - * Serial Communication Interface - * - * Registers defined in this header file: - * - HW_UART_BDH - UART Baud Rate Registers: High - * - HW_UART_BDL - UART Baud Rate Registers: Low - * - HW_UART_C1 - UART Control Register 1 - * - HW_UART_C2 - UART Control Register 2 - * - HW_UART_S1 - UART Status Register 1 - * - HW_UART_S2 - UART Status Register 2 - * - HW_UART_C3 - UART Control Register 3 - * - HW_UART_D - UART Data Register - * - HW_UART_MA1 - UART Match Address Registers 1 - * - HW_UART_MA2 - UART Match Address Registers 2 - * - HW_UART_C4 - UART Control Register 4 - * - HW_UART_C5 - UART Control Register 5 - * - HW_UART_ED - UART Extended Data Register - * - HW_UART_MODEM - UART Modem Register - * - HW_UART_IR - UART Infrared Register - * - HW_UART_PFIFO - UART FIFO Parameters - * - HW_UART_CFIFO - UART FIFO Control Register - * - HW_UART_SFIFO - UART FIFO Status Register - * - HW_UART_TWFIFO - UART FIFO Transmit Watermark - * - HW_UART_TCFIFO - UART FIFO Transmit Count - * - HW_UART_RWFIFO - UART FIFO Receive Watermark - * - HW_UART_RCFIFO - UART FIFO Receive Count - * - HW_UART_C7816 - UART 7816 Control Register - * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register - * - HW_UART_IS7816 - UART 7816 Interrupt Status Register - * - HW_UART_WP7816T0 - UART 7816 Wait Parameter Register - * - HW_UART_WP7816T1 - UART 7816 Wait Parameter Register - * - HW_UART_WN7816 - UART 7816 Wait N Register - * - HW_UART_WF7816 - UART 7816 Wait FD Register - * - HW_UART_ET7816 - UART 7816 Error Threshold Register - * - HW_UART_TL7816 - UART 7816 Transmit Length Register - * - * - hw_uart_t - Struct containing all module registers. - */ - -#define HW_UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */ -#define HW_UART0 (0U) /*!< Instance number for UART0. */ -#define HW_UART1 (1U) /*!< Instance number for UART1. */ -#define HW_UART2 (2U) /*!< Instance number for UART2. */ -#define HW_UART3 (3U) /*!< Instance number for UART3. */ -#define HW_UART4 (4U) /*!< Instance number for UART4. */ -#define HW_UART5 (5U) /*!< Instance number for UART5. */ - -/******************************************************************************* - * HW_UART_BDH - UART Baud Rate Registers: High - ******************************************************************************/ - -/*! - * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW) - * - * Reset value: 0x00U - * - * This register, along with the BDL register, controls the prescale divisor for - * UART baud rate generation. To update the 13-bit baud rate setting - * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write - * to BDL. The working value in BDH does not change until BDL is written. BDL is - * reset to a nonzero value, but after reset, the baud rate generator remains - * disabled until the first time the receiver or transmitter is enabled, that is, - * when C2[RE] or C2[TE] is set. - */ -typedef union _hw_uart_bdh -{ - uint8_t U; - struct _hw_uart_bdh_bitfields - { - uint8_t SBR : 5; /*!< [4:0] UART Baud Rate Bits */ - uint8_t SBNS : 1; /*!< [5] Stop Bit Number Select */ - uint8_t RXEDGIE : 1; /*!< [6] RxD Input Active Edge Interrupt Enable - * */ - uint8_t LBKDIE : 1; /*!< [7] LIN Break Detect Interrupt or DMA - * Request Enable */ - } B; -} hw_uart_bdh_t; - -/*! - * @name Constants and macros for entire UART_BDH register - */ -/*@{*/ -#define HW_UART_BDH_ADDR(x) ((x) + 0x0U) - -#define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x)) -#define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U) -#define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v)) -#define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v))) -#define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v))) -#define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_BDH bitfields - */ - -/*! - * @name Register UART_BDH, field SBR[4:0] (RW) - * - * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate - * generation for details. The baud rate generator is disabled until C2[TE] or - * C2[RE] is set for the first time after reset.The baud rate generator is disabled - * when SBR = 0. Writing to BDH has no effect without writing to BDL, because - * writing to BDH puts the data in a temporary location until BDL is written. - */ -/*@{*/ -#define BP_UART_BDH_SBR (0U) /*!< Bit position for UART_BDH_SBR. */ -#define BM_UART_BDH_SBR (0x1FU) /*!< Bit mask for UART_BDH_SBR. */ -#define BS_UART_BDH_SBR (5U) /*!< Bit field size in bits for UART_BDH_SBR. */ - -/*! @brief Read current value of the UART_BDH_SBR field. */ -#define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR) - -/*! @brief Format value for bitfield UART_BDH_SBR. */ -#define BF_UART_BDH_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR) - -/*! @brief Set the SBR field to a new value. */ -#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v))) -/*@}*/ - -/*! - * @name Register UART_BDH, field SBNS[5] (RW) - * - * SBNS selects the number of stop bits present in a data frame. This field - * valid for all 8, 9 and 10 bit data formats available. This field is not valid when - * C7816[ISO7816E] is enabled. - * - * Values: - * - 0 - Data frame consists of a single stop bit. - * - 1 - Data frame consists of two stop bits. - */ -/*@{*/ -#define BP_UART_BDH_SBNS (5U) /*!< Bit position for UART_BDH_SBNS. */ -#define BM_UART_BDH_SBNS (0x20U) /*!< Bit mask for UART_BDH_SBNS. */ -#define BS_UART_BDH_SBNS (1U) /*!< Bit field size in bits for UART_BDH_SBNS. */ - -/*! @brief Read current value of the UART_BDH_SBNS field. */ -#define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS)) - -/*! @brief Format value for bitfield UART_BDH_SBNS. */ -#define BF_UART_BDH_SBNS(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBNS) & BM_UART_BDH_SBNS) - -/*! @brief Set the SBNS field to a new value. */ -#define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v)) -/*@}*/ - -/*! - * @name Register UART_BDH, field RXEDGIE[6] (RW) - * - * Enables the receive input active edge, RXEDGIF, to generate interrupt - * requests. - * - * Values: - * - 0 - Hardware interrupts from RXEDGIF disabled using polling. - * - 1 - RXEDGIF interrupt request enabled. - */ -/*@{*/ -#define BP_UART_BDH_RXEDGIE (6U) /*!< Bit position for UART_BDH_RXEDGIE. */ -#define BM_UART_BDH_RXEDGIE (0x40U) /*!< Bit mask for UART_BDH_RXEDGIE. */ -#define BS_UART_BDH_RXEDGIE (1U) /*!< Bit field size in bits for UART_BDH_RXEDGIE. */ - -/*! @brief Read current value of the UART_BDH_RXEDGIE field. */ -#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE)) - -/*! @brief Format value for bitfield UART_BDH_RXEDGIE. */ -#define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE) - -/*! @brief Set the RXEDGIE field to a new value. */ -#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_BDH, field LBKDIE[7] (RW) - * - * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests - * based on the state of LBKDDMAS. or DMA transfer requests, - * - * Values: - * - 0 - LBKDIF interrupt and DMA transfer requests disabled. - * - 1 - LBKDIF interrupt or DMA transfer requests enabled. - */ -/*@{*/ -#define BP_UART_BDH_LBKDIE (7U) /*!< Bit position for UART_BDH_LBKDIE. */ -#define BM_UART_BDH_LBKDIE (0x80U) /*!< Bit mask for UART_BDH_LBKDIE. */ -#define BS_UART_BDH_LBKDIE (1U) /*!< Bit field size in bits for UART_BDH_LBKDIE. */ - -/*! @brief Read current value of the UART_BDH_LBKDIE field. */ -#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE)) - -/*! @brief Format value for bitfield UART_BDH_LBKDIE. */ -#define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE) - -/*! @brief Set the LBKDIE field to a new value. */ -#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_BDL - UART Baud Rate Registers: Low - ******************************************************************************/ - -/*! - * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW) - * - * Reset value: 0x04U - * - * This register, along with the BDH register, controls the prescale divisor for - * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0], - * first write to BDH to buffer the high half of the new value and then write to - * BDL. The working value in BDH does not change until BDL is written. BDL is - * reset to a nonzero value, but after reset, the baud rate generator remains - * disabled until the first time the receiver or transmitter is enabled, that is, when - * C2[RE] or C2[TE] is set. - */ -typedef union _hw_uart_bdl -{ - uint8_t U; - struct _hw_uart_bdl_bitfields - { - uint8_t SBR : 8; /*!< [7:0] UART Baud Rate Bits */ - } B; -} hw_uart_bdl_t; - -/*! - * @name Constants and macros for entire UART_BDL register - */ -/*@{*/ -#define HW_UART_BDL_ADDR(x) ((x) + 0x1U) - -#define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x)) -#define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U) -#define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v)) -#define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v))) -#define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v))) -#define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_BDL bitfields - */ - -/*! - * @name Register UART_BDL, field SBR[7:0] (RW) - * - * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate - * generation for details. The baud rate generator is disabled until C2[TE] or - * C2[RE] is set for the first time after reset.The baud rate generator is disabled - * when SBR = 0. Writing to BDH has no effect without writing to BDL, because - * writing to BDH puts the data in a temporary location until BDL is written. When - * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate - * fields must be even, the least significant bit is 0. See MODEM register for more - * details. - */ -/*@{*/ -#define BP_UART_BDL_SBR (0U) /*!< Bit position for UART_BDL_SBR. */ -#define BM_UART_BDL_SBR (0xFFU) /*!< Bit mask for UART_BDL_SBR. */ -#define BS_UART_BDL_SBR (8U) /*!< Bit field size in bits for UART_BDL_SBR. */ - -/*! @brief Read current value of the UART_BDL_SBR field. */ -#define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U) - -/*! @brief Format value for bitfield UART_BDL_SBR. */ -#define BF_UART_BDL_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR) - -/*! @brief Set the SBR field to a new value. */ -#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C1 - UART Control Register 1 - ******************************************************************************/ - -/*! - * @brief HW_UART_C1 - UART Control Register 1 (RW) - * - * Reset value: 0x00U - * - * This read/write register controls various optional features of the UART - * system. - */ -typedef union _hw_uart_c1 -{ - uint8_t U; - struct _hw_uart_c1_bitfields - { - uint8_t PT : 1; /*!< [0] Parity Type */ - uint8_t PE : 1; /*!< [1] Parity Enable */ - uint8_t ILT : 1; /*!< [2] Idle Line Type Select */ - uint8_t WAKE : 1; /*!< [3] Receiver Wakeup Method Select */ - uint8_t M : 1; /*!< [4] 9-bit or 8-bit Mode Select */ - uint8_t RSRC : 1; /*!< [5] Receiver Source Select */ - uint8_t UARTSWAI : 1; /*!< [6] UART Stops in Wait Mode */ - uint8_t LOOPS : 1; /*!< [7] Loop Mode Select */ - } B; -} hw_uart_c1_t; - -/*! - * @name Constants and macros for entire UART_C1 register - */ -/*@{*/ -#define HW_UART_C1_ADDR(x) ((x) + 0x2U) - -#define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x)) -#define HW_UART_C1_RD(x) (HW_UART_C1(x).U) -#define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v)) -#define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v))) -#define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v))) -#define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C1 bitfields - */ - -/*! - * @name Register UART_C1, field PT[0] (RW) - * - * Determines whether the UART generates and checks for even parity or odd - * parity. With even parity, an even number of 1s clears the parity bit and an odd - * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the - * parity bit and an even number of 1s sets the parity bit. This field must be - * cleared when C7816[ISO_7816E] is set/enabled. - * - * Values: - * - 0 - Even parity. - * - 1 - Odd parity. - */ -/*@{*/ -#define BP_UART_C1_PT (0U) /*!< Bit position for UART_C1_PT. */ -#define BM_UART_C1_PT (0x01U) /*!< Bit mask for UART_C1_PT. */ -#define BS_UART_C1_PT (1U) /*!< Bit field size in bits for UART_C1_PT. */ - -/*! @brief Read current value of the UART_C1_PT field. */ -#define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT)) - -/*! @brief Format value for bitfield UART_C1_PT. */ -#define BF_UART_C1_PT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT) - -/*! @brief Set the PT field to a new value. */ -#define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field PE[1] (RW) - * - * Enables the parity function. When parity is enabled, parity function inserts - * a parity bit in the bit position immediately preceding the stop bit. This - * field must be set when C7816[ISO_7816E] is set/enabled. - * - * Values: - * - 0 - Parity function disabled. - * - 1 - Parity function enabled. - */ -/*@{*/ -#define BP_UART_C1_PE (1U) /*!< Bit position for UART_C1_PE. */ -#define BM_UART_C1_PE (0x02U) /*!< Bit mask for UART_C1_PE. */ -#define BS_UART_C1_PE (1U) /*!< Bit field size in bits for UART_C1_PE. */ - -/*! @brief Read current value of the UART_C1_PE field. */ -#define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE)) - -/*! @brief Format value for bitfield UART_C1_PE. */ -#define BF_UART_C1_PE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE) - -/*! @brief Set the PE field to a new value. */ -#define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field ILT[2] (RW) - * - * Determines when the receiver starts counting logic 1s as idle character bits. - * The count begins either after a valid start bit or after the stop bit. If the - * count begins after the start bit, then a string of logic 1s preceding the - * stop bit can cause false recognition of an idle character. Beginning the count - * after the stop bit avoids false idle character recognition, but requires - * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a - * logic of 1'b0 is automatically shifted after a received stop bit, therefore - * resetting the idle count. In case the UART is programmed for IDLE line wakeup - * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting - * logic 1s as idle character bits. In idle line wakeup, an idle character is - * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE, - * and C4[M10] fields. - * - * Values: - * - 0 - Idle character bit count starts after start bit. - * - 1 - Idle character bit count starts after stop bit. - */ -/*@{*/ -#define BP_UART_C1_ILT (2U) /*!< Bit position for UART_C1_ILT. */ -#define BM_UART_C1_ILT (0x04U) /*!< Bit mask for UART_C1_ILT. */ -#define BS_UART_C1_ILT (1U) /*!< Bit field size in bits for UART_C1_ILT. */ - -/*! @brief Read current value of the UART_C1_ILT field. */ -#define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT)) - -/*! @brief Format value for bitfield UART_C1_ILT. */ -#define BF_UART_C1_ILT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT) - -/*! @brief Set the ILT field to a new value. */ -#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field WAKE[3] (RW) - * - * Determines which condition wakes the UART: Address mark in the most - * significant bit position of a received data character, or An idle condition on the - * receive pin input signal. - * - * Values: - * - 0 - Idle line wakeup. - * - 1 - Address mark wakeup. - */ -/*@{*/ -#define BP_UART_C1_WAKE (3U) /*!< Bit position for UART_C1_WAKE. */ -#define BM_UART_C1_WAKE (0x08U) /*!< Bit mask for UART_C1_WAKE. */ -#define BS_UART_C1_WAKE (1U) /*!< Bit field size in bits for UART_C1_WAKE. */ - -/*! @brief Read current value of the UART_C1_WAKE field. */ -#define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE)) - -/*! @brief Format value for bitfield UART_C1_WAKE. */ -#define BF_UART_C1_WAKE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE) - -/*! @brief Set the WAKE field to a new value. */ -#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field M[4] (RW) - * - * This field must be set when C7816[ISO_7816E] is set/enabled. - * - * Values: - * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. - * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. - */ -/*@{*/ -#define BP_UART_C1_M (4U) /*!< Bit position for UART_C1_M. */ -#define BM_UART_C1_M (0x10U) /*!< Bit mask for UART_C1_M. */ -#define BS_UART_C1_M (1U) /*!< Bit field size in bits for UART_C1_M. */ - -/*! @brief Read current value of the UART_C1_M field. */ -#define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M)) - -/*! @brief Format value for bitfield UART_C1_M. */ -#define BF_UART_C1_M(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M) - -/*! @brief Set the M field to a new value. */ -#define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field RSRC[5] (RW) - * - * This field has no meaning or effect unless the LOOPS field is set. When LOOPS - * is set, the RSRC field determines the source for the receiver shift register - * input. - * - * Values: - * - 0 - Selects internal loop back mode. The receiver input is internally - * connected to transmitter output. - * - 1 - Single wire UART mode where the receiver input is connected to the - * transmit pin input signal. - */ -/*@{*/ -#define BP_UART_C1_RSRC (5U) /*!< Bit position for UART_C1_RSRC. */ -#define BM_UART_C1_RSRC (0x20U) /*!< Bit mask for UART_C1_RSRC. */ -#define BS_UART_C1_RSRC (1U) /*!< Bit field size in bits for UART_C1_RSRC. */ - -/*! @brief Read current value of the UART_C1_RSRC field. */ -#define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC)) - -/*! @brief Format value for bitfield UART_C1_RSRC. */ -#define BF_UART_C1_RSRC(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC) - -/*! @brief Set the RSRC field to a new value. */ -#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field UARTSWAI[6] (RW) - * - * Values: - * - 0 - UART clock continues to run in Wait mode. - * - 1 - UART clock freezes while CPU is in Wait mode. - */ -/*@{*/ -#define BP_UART_C1_UARTSWAI (6U) /*!< Bit position for UART_C1_UARTSWAI. */ -#define BM_UART_C1_UARTSWAI (0x40U) /*!< Bit mask for UART_C1_UARTSWAI. */ -#define BS_UART_C1_UARTSWAI (1U) /*!< Bit field size in bits for UART_C1_UARTSWAI. */ - -/*! @brief Read current value of the UART_C1_UARTSWAI field. */ -#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI)) - -/*! @brief Format value for bitfield UART_C1_UARTSWAI. */ -#define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI) - -/*! @brief Set the UARTSWAI field to a new value. */ -#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v)) -/*@}*/ - -/*! - * @name Register UART_C1, field LOOPS[7] (RW) - * - * When LOOPS is set, the RxD pin is disconnected from the UART and the - * transmitter output is internally connected to the receiver input. The transmitter and - * the receiver must be enabled to use the loop function. - * - * Values: - * - 0 - Normal operation. - * - 1 - Loop mode where transmitter output is internally connected to receiver - * input. The receiver input is determined by RSRC. - */ -/*@{*/ -#define BP_UART_C1_LOOPS (7U) /*!< Bit position for UART_C1_LOOPS. */ -#define BM_UART_C1_LOOPS (0x80U) /*!< Bit mask for UART_C1_LOOPS. */ -#define BS_UART_C1_LOOPS (1U) /*!< Bit field size in bits for UART_C1_LOOPS. */ - -/*! @brief Read current value of the UART_C1_LOOPS field. */ -#define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS)) - -/*! @brief Format value for bitfield UART_C1_LOOPS. */ -#define BF_UART_C1_LOOPS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS) - -/*! @brief Set the LOOPS field to a new value. */ -#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C2 - UART Control Register 2 - ******************************************************************************/ - -/*! - * @brief HW_UART_C2 - UART Control Register 2 (RW) - * - * Reset value: 0x00U - * - * This register can be read or written at any time. - */ -typedef union _hw_uart_c2 -{ - uint8_t U; - struct _hw_uart_c2_bitfields - { - uint8_t SBK : 1; /*!< [0] Send Break */ - uint8_t RWU : 1; /*!< [1] Receiver Wakeup Control */ - uint8_t RE : 1; /*!< [2] Receiver Enable */ - uint8_t TE : 1; /*!< [3] Transmitter Enable */ - uint8_t ILIE : 1; /*!< [4] Idle Line Interrupt DMA Transfer Enable */ - uint8_t RIE : 1; /*!< [5] Receiver Full Interrupt or DMA Transfer - * Enable */ - uint8_t TCIE : 1; /*!< [6] Transmission Complete Interrupt or DMA - * Transfer Enable */ - uint8_t TIE : 1; /*!< [7] Transmitter Interrupt or DMA Transfer - * Enable. */ - } B; -} hw_uart_c2_t; - -/*! - * @name Constants and macros for entire UART_C2 register - */ -/*@{*/ -#define HW_UART_C2_ADDR(x) ((x) + 0x3U) - -#define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x)) -#define HW_UART_C2_RD(x) (HW_UART_C2(x).U) -#define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v)) -#define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v))) -#define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v))) -#define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C2 bitfields - */ - -/*! - * @name Register UART_C2, field SBK[0] (RW) - * - * Toggling SBK sends one break character from the following: See Transmitting - * break characters for the number of logic 0s for the different configurations. - * Toggling implies clearing the SBK field before the break character has finished - * transmitting. As long as SBK is set, the transmitter continues to send - * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits). - * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit. - * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13] - * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when - * C7816[ISO_7816E] is set. - * - * Values: - * - 0 - Normal transmitter operation. - * - 1 - Queue break characters to be sent. - */ -/*@{*/ -#define BP_UART_C2_SBK (0U) /*!< Bit position for UART_C2_SBK. */ -#define BM_UART_C2_SBK (0x01U) /*!< Bit mask for UART_C2_SBK. */ -#define BS_UART_C2_SBK (1U) /*!< Bit field size in bits for UART_C2_SBK. */ - -/*! @brief Read current value of the UART_C2_SBK field. */ -#define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK)) - -/*! @brief Format value for bitfield UART_C2_SBK. */ -#define BF_UART_C2_SBK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK) - -/*! @brief Set the SBK field to a new value. */ -#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field RWU[1] (RW) - * - * This field can be set to place the UART receiver in a standby state. RWU - * automatically clears when an RWU event occurs, that is, an IDLE event when - * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be - * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup - * on idle) if the channel is currently not idle. This can be determined by - * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already - * idle, it is possible that the UART will discard data. This is because the data - * must be received or a LIN break detected after an IDLE is detected before IDLE - * is allowed to reasserted. - * - * Values: - * - 0 - Normal operation. - * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt - * requests. Normally, hardware wakes the receiver by automatically clearing - * RWU. - */ -/*@{*/ -#define BP_UART_C2_RWU (1U) /*!< Bit position for UART_C2_RWU. */ -#define BM_UART_C2_RWU (0x02U) /*!< Bit mask for UART_C2_RWU. */ -#define BS_UART_C2_RWU (1U) /*!< Bit field size in bits for UART_C2_RWU. */ - -/*! @brief Read current value of the UART_C2_RWU field. */ -#define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU)) - -/*! @brief Format value for bitfield UART_C2_RWU. */ -#define BF_UART_C2_RWU(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU) - -/*! @brief Set the RWU field to a new value. */ -#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field RE[2] (RW) - * - * Enables the UART receiver. - * - * Values: - * - 0 - Receiver off. - * - 1 - Receiver on. - */ -/*@{*/ -#define BP_UART_C2_RE (2U) /*!< Bit position for UART_C2_RE. */ -#define BM_UART_C2_RE (0x04U) /*!< Bit mask for UART_C2_RE. */ -#define BS_UART_C2_RE (1U) /*!< Bit field size in bits for UART_C2_RE. */ - -/*! @brief Read current value of the UART_C2_RE field. */ -#define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE)) - -/*! @brief Format value for bitfield UART_C2_RE. */ -#define BF_UART_C2_RE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE) - -/*! @brief Set the RE field to a new value. */ -#define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field TE[3] (RW) - * - * Enables the UART transmitter. TE can be used to queue an idle preamble by - * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and - * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been - * transmitted. This condition is detected when TL7816[TLEN] = 0 and four - * additional characters are transmitted. - * - * Values: - * - 0 - Transmitter off. - * - 1 - Transmitter on. - */ -/*@{*/ -#define BP_UART_C2_TE (3U) /*!< Bit position for UART_C2_TE. */ -#define BM_UART_C2_TE (0x08U) /*!< Bit mask for UART_C2_TE. */ -#define BS_UART_C2_TE (1U) /*!< Bit field size in bits for UART_C2_TE. */ - -/*! @brief Read current value of the UART_C2_TE field. */ -#define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE)) - -/*! @brief Format value for bitfield UART_C2_TE. */ -#define BF_UART_C2_TE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE) - -/*! @brief Set the TE field to a new value. */ -#define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field ILIE[4] (RW) - * - * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA - * transfer requests based on the state of C5[ILDMAS]. - * - * Values: - * - 0 - IDLE interrupt requests disabled. and DMA transfer - * - 1 - IDLE interrupt requests enabled. or DMA transfer - */ -/*@{*/ -#define BP_UART_C2_ILIE (4U) /*!< Bit position for UART_C2_ILIE. */ -#define BM_UART_C2_ILIE (0x10U) /*!< Bit mask for UART_C2_ILIE. */ -#define BS_UART_C2_ILIE (1U) /*!< Bit field size in bits for UART_C2_ILIE. */ - -/*! @brief Read current value of the UART_C2_ILIE field. */ -#define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE)) - -/*! @brief Format value for bitfield UART_C2_ILIE. */ -#define BF_UART_C2_ILIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE) - -/*! @brief Set the ILIE field to a new value. */ -#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field RIE[5] (RW) - * - * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, - * based on the state of C5[RDMAS]. - * - * Values: - * - 0 - RDRF interrupt and DMA transfer requests disabled. - * - 1 - RDRF interrupt or DMA transfer requests enabled. - */ -/*@{*/ -#define BP_UART_C2_RIE (5U) /*!< Bit position for UART_C2_RIE. */ -#define BM_UART_C2_RIE (0x20U) /*!< Bit mask for UART_C2_RIE. */ -#define BS_UART_C2_RIE (1U) /*!< Bit field size in bits for UART_C2_RIE. */ - -/*! @brief Read current value of the UART_C2_RIE field. */ -#define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE)) - -/*! @brief Format value for bitfield UART_C2_RIE. */ -#define BF_UART_C2_RIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE) - -/*! @brief Set the RIE field to a new value. */ -#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field TCIE[6] (RW) - * - * Enables the transmission complete flag, S1[TC], to generate interrupt - * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and - * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be - * written unless servicing a DMA request. - * - * Values: - * - 0 - TC interrupt and DMA transfer requests disabled. - * - 1 - TC interrupt or DMA transfer requests enabled. - */ -/*@{*/ -#define BP_UART_C2_TCIE (6U) /*!< Bit position for UART_C2_TCIE. */ -#define BM_UART_C2_TCIE (0x40U) /*!< Bit mask for UART_C2_TCIE. */ -#define BS_UART_C2_TCIE (1U) /*!< Bit field size in bits for UART_C2_TCIE. */ - -/*! @brief Read current value of the UART_C2_TCIE field. */ -#define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE)) - -/*! @brief Format value for bitfield UART_C2_TCIE. */ -#define BF_UART_C2_TCIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE) - -/*! @brief Set the TCIE field to a new value. */ -#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C2, field TIE[7] (RW) - * - * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, - * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE - * must be cleared, and D[D] must not be written unless servicing a DMA request. - * - * Values: - * - 0 - TDRE interrupt and DMA transfer requests disabled. - * - 1 - TDRE interrupt or DMA transfer requests enabled. - */ -/*@{*/ -#define BP_UART_C2_TIE (7U) /*!< Bit position for UART_C2_TIE. */ -#define BM_UART_C2_TIE (0x80U) /*!< Bit mask for UART_C2_TIE. */ -#define BS_UART_C2_TIE (1U) /*!< Bit field size in bits for UART_C2_TIE. */ - -/*! @brief Read current value of the UART_C2_TIE field. */ -#define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE)) - -/*! @brief Format value for bitfield UART_C2_TIE. */ -#define BF_UART_C2_TIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE) - -/*! @brief Set the TIE field to a new value. */ -#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_S1 - UART Status Register 1 - ******************************************************************************/ - -/*! - * @brief HW_UART_S1 - UART Status Register 1 (RO) - * - * Reset value: 0xC0U - * - * The S1 register provides inputs to the MCU for generation of UART interrupts - * or DMA requests. This register can also be polled by the MCU to check the - * status of its fields. To clear a flag, the status register should be read followed - * by a read or write to D register, depending on the interrupt flag type. Other - * instructions can be executed between the two steps as long the handling of - * I/O is not compromised, but the order of operations is important for flag - * clearing. When a flag is configured to trigger a DMA request, assertion of the - * associated DMA done signal from the DMA controller clears the flag. If the - * condition that results in the assertion of the flag, interrupt, or DMA request is not - * resolved prior to clearing the flag, the flag, and interrupt/DMA request, - * reasserts. For example, if the DMA or interrupt service routine fails to write - * sufficient data to the transmit buffer to raise it above the watermark level, the - * flag reasserts and generates another interrupt or DMA request. Reading an - * empty data register to clear one of the flags of the S1 register causes the FIFO - * pointers to become misaligned. A receive FIFO flush reinitializes the - * pointers. A better way to prevent this situation is to always leave one byte in FIFO - * and this byte will be read eventually in clearing the flag bit. - */ -typedef union _hw_uart_s1 -{ - uint8_t U; - struct _hw_uart_s1_bitfields - { - uint8_t PF : 1; /*!< [0] Parity Error Flag */ - uint8_t FE : 1; /*!< [1] Framing Error Flag */ - uint8_t NF : 1; /*!< [2] Noise Flag */ - uint8_t OR : 1; /*!< [3] Receiver Overrun Flag */ - uint8_t IDLE : 1; /*!< [4] Idle Line Flag */ - uint8_t RDRF : 1; /*!< [5] Receive Data Register Full Flag */ - uint8_t TC : 1; /*!< [6] Transmit Complete Flag */ - uint8_t TDRE : 1; /*!< [7] Transmit Data Register Empty Flag */ - } B; -} hw_uart_s1_t; - -/*! - * @name Constants and macros for entire UART_S1 register - */ -/*@{*/ -#define HW_UART_S1_ADDR(x) ((x) + 0x4U) - -#define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x)) -#define HW_UART_S1_RD(x) (HW_UART_S1(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_S1 bitfields - */ - -/*! - * @name Register UART_S1, field PF[0] (RO) - * - * PF is set when PE is set and the parity of the received data does not match - * its parity bit. The PF is not set in the case of an overrun condition. When PF - * is set, it indicates only that a dataword was received with parity error since - * the last time it was cleared. There is no guarantee that the first dataword - * read from the receive buffer has a parity error or that there is only one - * dataword in the buffer that was received with a parity error, unless the receive - * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is - * disabled, Within the receive buffer structure the received dataword is tagged - * if it is received with a parity error. This information is available by reading - * the ED register prior to reading the D register. - * - * Values: - * - 0 - No parity error detected since the last time this flag was cleared. If - * the receive buffer has a depth greater than 1, then there may be data in - * the receive buffer what was received with a parity error. - * - 1 - At least one dataword was received with a parity error since the last - * time this flag was cleared. - */ -/*@{*/ -#define BP_UART_S1_PF (0U) /*!< Bit position for UART_S1_PF. */ -#define BM_UART_S1_PF (0x01U) /*!< Bit mask for UART_S1_PF. */ -#define BS_UART_S1_PF (1U) /*!< Bit field size in bits for UART_S1_PF. */ - -/*! @brief Read current value of the UART_S1_PF field. */ -#define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF)) -/*@}*/ - -/*! - * @name Register UART_S1, field FE[1] (RO) - * - * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set, - * then FE will set when a logic 0 is accepted for either of the two stop bits. - * FE does not set in the case of an overrun or while the LIN break detect feature - * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is - * cleared. To clear FE, read S1 with FE set and then read D. The last data in the - * receive buffer represents the data that was received with the frame error - * enabled. Framing errors are not supported when 7816E is set/enabled. However, if - * this flag is set, data is still not received in 7816 mode. - * - * Values: - * - 0 - No framing error detected. - * - 1 - Framing error. - */ -/*@{*/ -#define BP_UART_S1_FE (1U) /*!< Bit position for UART_S1_FE. */ -#define BM_UART_S1_FE (0x02U) /*!< Bit mask for UART_S1_FE. */ -#define BS_UART_S1_FE (1U) /*!< Bit field size in bits for UART_S1_FE. */ - -/*! @brief Read current value of the UART_S1_FE field. */ -#define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE)) -/*@}*/ - -/*! - * @name Register UART_S1, field NF[2] (RO) - * - * NF is set when the UART detects noise on the receiver input. NF does not - * become set in the case of an overrun or while the LIN break detect feature is - * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has - * been received with noise since the last time it was cleared. There is no - * guarantee that the first dataword read from the receive buffer has noise or that there - * is only one dataword in the buffer that was received with noise unless the - * receive buffer has a depth of one. To clear NF, read S1 and then read D. - * - * Values: - * - 0 - No noise detected since the last time this flag was cleared. If the - * receive buffer has a depth greater than 1 then there may be data in the - * receiver buffer that was received with noise. - * - 1 - At least one dataword was received with noise detected since the last - * time the flag was cleared. - */ -/*@{*/ -#define BP_UART_S1_NF (2U) /*!< Bit position for UART_S1_NF. */ -#define BM_UART_S1_NF (0x04U) /*!< Bit mask for UART_S1_NF. */ -#define BS_UART_S1_NF (1U) /*!< Bit field size in bits for UART_S1_NF. */ - -/*! @brief Read current value of the UART_S1_NF field. */ -#define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF)) -/*@}*/ - -/*! - * @name Register UART_S1, field OR[3] (RO) - * - * OR is set when software fails to prevent the receive data register from - * overflowing with data. The OR bit is set immediately after the stop bit has been - * completely received for the dataword that overflows the buffer and all the other - * error flags (FE, NF, and PF) are prevented from setting. The data in the - * shift register is lost, but the data already in the UART data registers is not - * affected. If the OR flag is set, no data is stored in the data buffer even if - * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE - * flags are blocked from asserting, that is, transition from an inactive to an - * active state. To clear OR, read S1 when OR is set and then read D. See - * functional description for more details regarding the operation of the OR bit.If - * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF] - * is not cleared before the next data character is received. In 7816 mode, it is - * possible to configure a NACK to be returned by programing C7816[ONACK]. - * - * Values: - * - 0 - No overrun has occurred since the last time the flag was cleared. - * - 1 - Overrun has occurred or the overrun flag has not been cleared since the - * last overrun occured. - */ -/*@{*/ -#define BP_UART_S1_OR (3U) /*!< Bit position for UART_S1_OR. */ -#define BM_UART_S1_OR (0x08U) /*!< Bit mask for UART_S1_OR. */ -#define BS_UART_S1_OR (1U) /*!< Bit field size in bits for UART_S1_OR. */ - -/*! @brief Read current value of the UART_S1_OR field. */ -#define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR)) -/*@}*/ - -/*! - * @name Register UART_S1, field IDLE[4] (RO) - * - * After the IDLE flag is cleared, a frame must be received (although not - * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN - * break character must set the S2[LBKDIF] flag before an idle condition can set the - * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D. - * IDLE is set when either of the following appear on the receiver input: 10 - * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10] - * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle - * detection is not supported when 7816E is set/enabled and hence this flag is - * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE - * flag if RWUID is set, else the IDLE flag does not become set. - * - * Values: - * - 0 - Receiver input is either active now or has never become active since - * the IDLE flag was last cleared. - * - 1 - Receiver input has become idle or the flag has not been cleared since - * it last asserted. - */ -/*@{*/ -#define BP_UART_S1_IDLE (4U) /*!< Bit position for UART_S1_IDLE. */ -#define BM_UART_S1_IDLE (0x10U) /*!< Bit mask for UART_S1_IDLE. */ -#define BS_UART_S1_IDLE (1U) /*!< Bit field size in bits for UART_S1_IDLE. */ - -/*! @brief Read current value of the UART_S1_IDLE field. */ -#define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE)) -/*@}*/ - -/*! - * @name Register UART_S1, field RDRF[5] (RO) - * - * RDRF is set when the number of datawords in the receive buffer is equal to or - * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the - * process of being received is not included in the count. To clear RDRF, read S1 - * when RDRF is set and then read D. For more efficient interrupt and DMA - * operation, read all data except the final value from the buffer, using D/C3[T8]/ED. - * Then read S1 and the final data value, resulting in the clearing of the RDRF - * flag. Even if RDRF is set, data will continue to be received until an overrun - * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set. - * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive - * buffer but over-write each other. - * - * Values: - * - 0 - The number of datawords in the receive buffer is less than the number - * indicated by RXWATER. - * - 1 - The number of datawords in the receive buffer is equal to or greater - * than the number indicated by RXWATER at some point in time since this flag - * was last cleared. - */ -/*@{*/ -#define BP_UART_S1_RDRF (5U) /*!< Bit position for UART_S1_RDRF. */ -#define BM_UART_S1_RDRF (0x20U) /*!< Bit mask for UART_S1_RDRF. */ -#define BS_UART_S1_RDRF (1U) /*!< Bit field size in bits for UART_S1_RDRF. */ - -/*! @brief Read current value of the UART_S1_RDRF field. */ -#define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF)) -/*@}*/ - -/*! - * @name Register UART_S1, field TC[6] (RO) - * - * TC is set when the transmit buffer is empty and no data, preamble, or break - * character is being transmitted. When TC is set, the transmit data output signal - * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then - * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is - * set after any NACK signal has been received, but prior to any corresponding - * guard times expiring. Writing to D to transmit new data. Queuing a preamble by - * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK - * in C2. - * - * Values: - * - 0 - Transmitter active (sending data, a preamble, or a break). - * - 1 - Transmitter idle (transmission activity complete). - */ -/*@{*/ -#define BP_UART_S1_TC (6U) /*!< Bit position for UART_S1_TC. */ -#define BM_UART_S1_TC (0x40U) /*!< Bit mask for UART_S1_TC. */ -#define BS_UART_S1_TC (1U) /*!< Bit field size in bits for UART_S1_TC. */ - -/*! @brief Read current value of the UART_S1_TC field. */ -#define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC)) -/*@}*/ - -/*! - * @name Register UART_S1, field TDRE[7] (RO) - * - * TDRE will set when the number of datawords in the transmit buffer (D and - * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A - * character that is in the process of being transmitted is not included in the count. - * To clear TDRE, read S1 when TDRE is set and then write to the UART data - * register (D). For more efficient interrupt servicing, all data except the final value - * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read - * before writing the final data value, resulting in the clearing of the TRDE - * flag. This is more efficient because the TDRE reasserts until the watermark has - * been exceeded. So, attempting to clear the TDRE with every write will be - * ineffective until sufficient data has been written. - * - * Values: - * - 0 - The amount of data in the transmit buffer is greater than the value - * indicated by TWFIFO[TXWATER]. - * - 1 - The amount of data in the transmit buffer is less than or equal to the - * value indicated by TWFIFO[TXWATER] at some point in time since the flag - * has been cleared. - */ -/*@{*/ -#define BP_UART_S1_TDRE (7U) /*!< Bit position for UART_S1_TDRE. */ -#define BM_UART_S1_TDRE (0x80U) /*!< Bit mask for UART_S1_TDRE. */ -#define BS_UART_S1_TDRE (1U) /*!< Bit field size in bits for UART_S1_TDRE. */ - -/*! @brief Read current value of the UART_S1_TDRE field. */ -#define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE)) -/*@}*/ - -/******************************************************************************* - * HW_UART_S2 - UART Status Register 2 - ******************************************************************************/ - -/*! - * @brief HW_UART_S2 - UART Status Register 2 (RW) - * - * Reset value: 0x00U - * - * The S2 register provides inputs to the MCU for generation of UART interrupts - * or DMA requests. Also, this register can be polled by the MCU to check the - * status of these bits. This register can be read or written at any time, with the - * exception of the MSBF and RXINV bits, which should be changed by the user only - * between transmit and receive packets. - */ -typedef union _hw_uart_s2 -{ - uint8_t U; - struct _hw_uart_s2_bitfields - { - uint8_t RAF : 1; /*!< [0] Receiver Active Flag */ - uint8_t LBKDE : 1; /*!< [1] LIN Break Detection Enable */ - uint8_t BRK13 : 1; /*!< [2] Break Transmit Character Length */ - uint8_t RWUID : 1; /*!< [3] Receive Wakeup Idle Detect */ - uint8_t RXINV : 1; /*!< [4] Receive Data Inversion */ - uint8_t MSBF : 1; /*!< [5] Most Significant Bit First */ - uint8_t RXEDGIF : 1; /*!< [6] RxD Pin Active Edge Interrupt Flag */ - uint8_t LBKDIF : 1; /*!< [7] LIN Break Detect Interrupt Flag */ - } B; -} hw_uart_s2_t; - -/*! - * @name Constants and macros for entire UART_S2 register - */ -/*@{*/ -#define HW_UART_S2_ADDR(x) ((x) + 0x5U) - -#define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x)) -#define HW_UART_S2_RD(x) (HW_UART_S2(x).U) -#define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v)) -#define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v))) -#define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v))) -#define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_S2 bitfields - */ - -/*! - * @name Register UART_S2, field RAF[0] (RO) - * - * RAF is set when the UART receiver detects a logic 0 during the RT1 time - * period of the start bit search. RAF is cleared when the receiver detects an idle - * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is - * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] = - * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible - * to configure the guard time to 12. However, if a NACK is required to be - * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a - * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU - * prior to actually being inactive. - * - * Values: - * - 0 - UART receiver idle/inactive waiting for a start bit. - * - 1 - UART receiver active, RxD input not idle. - */ -/*@{*/ -#define BP_UART_S2_RAF (0U) /*!< Bit position for UART_S2_RAF. */ -#define BM_UART_S2_RAF (0x01U) /*!< Bit mask for UART_S2_RAF. */ -#define BS_UART_S2_RAF (1U) /*!< Bit field size in bits for UART_S2_RAF. */ - -/*! @brief Read current value of the UART_S2_RAF field. */ -#define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF)) -/*@}*/ - -/*! - * @name Register UART_S2, field LBKDE[1] (RW) - * - * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF], - * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see . - * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set. - * - * Values: - * - 0 - Break character detection is disabled. - * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or - * 12 bits time if C1[M] = 1. - */ -/*@{*/ -#define BP_UART_S2_LBKDE (1U) /*!< Bit position for UART_S2_LBKDE. */ -#define BM_UART_S2_LBKDE (0x02U) /*!< Bit mask for UART_S2_LBKDE. */ -#define BS_UART_S2_LBKDE (1U) /*!< Bit field size in bits for UART_S2_LBKDE. */ - -/*! @brief Read current value of the UART_S2_LBKDE field. */ -#define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE)) - -/*! @brief Format value for bitfield UART_S2_LBKDE. */ -#define BF_UART_S2_LBKDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE) - -/*! @brief Set the LBKDE field to a new value. */ -#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field BRK13[2] (RW) - * - * Determines whether the transmit break character is 10, 11, or 12 bits long, - * or 13 or 14 bits long. See for the length of the break character for the - * different configurations. The detection of a framing error is not affected by this - * field. Transmitting break characters - * - * Values: - * - 0 - Break character is 10, 11, or 12 bits long. - * - 1 - Break character is 13 or 14 bits long. - */ -/*@{*/ -#define BP_UART_S2_BRK13 (2U) /*!< Bit position for UART_S2_BRK13. */ -#define BM_UART_S2_BRK13 (0x04U) /*!< Bit mask for UART_S2_BRK13. */ -#define BS_UART_S2_BRK13 (1U) /*!< Bit field size in bits for UART_S2_BRK13. */ - -/*! @brief Read current value of the UART_S2_BRK13 field. */ -#define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13)) - -/*! @brief Format value for bitfield UART_S2_BRK13. */ -#define BF_UART_S2_BRK13(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13) - -/*! @brief Set the BRK13 field to a new value. */ -#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field RWUID[3] (RW) - * - * When RWU is set and WAKE is cleared, this field controls whether the idle - * character that wakes the receiver sets S1[IDLE]. This field must be cleared when - * C7816[ISO7816E] is set/enabled. - * - * Values: - * - 0 - S1[IDLE] is not set upon detection of an idle character. - * - 1 - S1[IDLE] is set upon detection of an idle character. - */ -/*@{*/ -#define BP_UART_S2_RWUID (3U) /*!< Bit position for UART_S2_RWUID. */ -#define BM_UART_S2_RWUID (0x08U) /*!< Bit mask for UART_S2_RWUID. */ -#define BS_UART_S2_RWUID (1U) /*!< Bit field size in bits for UART_S2_RWUID. */ - -/*! @brief Read current value of the UART_S2_RWUID field. */ -#define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID)) - -/*! @brief Format value for bitfield UART_S2_RWUID. */ -#define BF_UART_S2_RWUID(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID) - -/*! @brief Set the RWUID field to a new value. */ -#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field RXINV[4] (RW) - * - * Setting this field reverses the polarity of the received data input. In NRZ - * format, a one is represented by a mark and a zero is represented by a space for - * normal polarity, and the opposite for inverted polarity. In IrDA format, a - * zero is represented by short high pulse in the middle of a bit time remaining - * idle low for a one for normal polarity. A zero is represented by a short low - * pulse in the middle of a bit time remaining idle high for a one for inverted - * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are - * enabled and an initial character is detected in T = 0 protocol mode. Setting - * RXINV inverts the RxD input for data bits, start and stop bits, break, and - * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit - * are inverted. - * - * Values: - * - 0 - Receive data is not inverted. - * - 1 - Receive data is inverted. - */ -/*@{*/ -#define BP_UART_S2_RXINV (4U) /*!< Bit position for UART_S2_RXINV. */ -#define BM_UART_S2_RXINV (0x10U) /*!< Bit mask for UART_S2_RXINV. */ -#define BS_UART_S2_RXINV (1U) /*!< Bit field size in bits for UART_S2_RXINV. */ - -/*! @brief Read current value of the UART_S2_RXINV field. */ -#define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV)) - -/*! @brief Format value for bitfield UART_S2_RXINV. */ -#define BF_UART_S2_RXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV) - -/*! @brief Set the RXINV field to a new value. */ -#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field MSBF[5] (RW) - * - * Setting this field reverses the order of the bits that are transmitted and - * received on the wire. This field does not affect the polarity of the bits, the - * location of the parity bit, or the location of the start or stop bits. This - * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and - * an initial character is detected in T = 0 protocol mode. - * - * Values: - * - 0 - LSB (bit0) is the first bit that is transmitted following the start - * bit. Further, the first bit received after the start bit is identified as - * bit0. - * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following - * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the - * first bit received after the start bit is identified as bit8, bit7, or - * bit6, depending on the setting of C1[M] and C1[PE]. - */ -/*@{*/ -#define BP_UART_S2_MSBF (5U) /*!< Bit position for UART_S2_MSBF. */ -#define BM_UART_S2_MSBF (0x20U) /*!< Bit mask for UART_S2_MSBF. */ -#define BS_UART_S2_MSBF (1U) /*!< Bit field size in bits for UART_S2_MSBF. */ - -/*! @brief Read current value of the UART_S2_MSBF field. */ -#define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF)) - -/*! @brief Format value for bitfield UART_S2_MSBF. */ -#define BF_UART_S2_MSBF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF) - -/*! @brief Set the MSBF field to a new value. */ -#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field RXEDGIF[6] (W1C) - * - * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is - * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1 - * to it. See for additional details. RXEDGIF description The active edge is - * detected only in two wire mode and on receiving data coming from the RxD pin. - * - * Values: - * - 0 - No active edge on the receive pin has occurred. - * - 1 - An active edge on the receive pin has occurred. - */ -/*@{*/ -#define BP_UART_S2_RXEDGIF (6U) /*!< Bit position for UART_S2_RXEDGIF. */ -#define BM_UART_S2_RXEDGIF (0x40U) /*!< Bit mask for UART_S2_RXEDGIF. */ -#define BS_UART_S2_RXEDGIF (1U) /*!< Bit field size in bits for UART_S2_RXEDGIF. */ - -/*! @brief Read current value of the UART_S2_RXEDGIF field. */ -#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF)) - -/*! @brief Format value for bitfield UART_S2_RXEDGIF. */ -#define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF) - -/*! @brief Set the RXEDGIF field to a new value. */ -#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v)) -/*@}*/ - -/*! - * @name Register UART_S2, field LBKDIF[7] (W1C) - * - * LBKDIF is set when LBKDE is set and a LIN break character is detected on the - * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M] - * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the - * last LIN break character. LBKDIF is cleared by writing a 1 to it. - * - * Values: - * - 0 - No LIN break character detected. - * - 1 - LIN break character detected. - */ -/*@{*/ -#define BP_UART_S2_LBKDIF (7U) /*!< Bit position for UART_S2_LBKDIF. */ -#define BM_UART_S2_LBKDIF (0x80U) /*!< Bit mask for UART_S2_LBKDIF. */ -#define BS_UART_S2_LBKDIF (1U) /*!< Bit field size in bits for UART_S2_LBKDIF. */ - -/*! @brief Read current value of the UART_S2_LBKDIF field. */ -#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF)) - -/*! @brief Format value for bitfield UART_S2_LBKDIF. */ -#define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF) - -/*! @brief Set the LBKDIF field to a new value. */ -#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C3 - UART Control Register 3 - ******************************************************************************/ - -/*! - * @brief HW_UART_C3 - UART Control Register 3 (RW) - * - * Reset value: 0x00U - * - * Writing R8 does not have any effect. TXDIR and TXINV can be changed only - * between transmit and receive packets. - */ -typedef union _hw_uart_c3 -{ - uint8_t U; - struct _hw_uart_c3_bitfields - { - uint8_t PEIE : 1; /*!< [0] Parity Error Interrupt Enable */ - uint8_t FEIE : 1; /*!< [1] Framing Error Interrupt Enable */ - uint8_t NEIE : 1; /*!< [2] Noise Error Interrupt Enable */ - uint8_t ORIE : 1; /*!< [3] Overrun Error Interrupt Enable */ - uint8_t TXINV : 1; /*!< [4] Transmit Data Inversion. */ - uint8_t TXDIR : 1; /*!< [5] Transmitter Pin Data Direction in - * Single-Wire mode */ - uint8_t T8 : 1; /*!< [6] Transmit Bit 8 */ - uint8_t R8 : 1; /*!< [7] Received Bit 8 */ - } B; -} hw_uart_c3_t; - -/*! - * @name Constants and macros for entire UART_C3 register - */ -/*@{*/ -#define HW_UART_C3_ADDR(x) ((x) + 0x6U) - -#define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x)) -#define HW_UART_C3_RD(x) (HW_UART_C3(x).U) -#define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v)) -#define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v))) -#define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v))) -#define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C3 bitfields - */ - -/*! - * @name Register UART_C3, field PEIE[0] (RW) - * - * Enables the parity error flag, S1[PF], to generate interrupt requests. - * - * Values: - * - 0 - PF interrupt requests are disabled. - * - 1 - PF interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_PEIE (0U) /*!< Bit position for UART_C3_PEIE. */ -#define BM_UART_C3_PEIE (0x01U) /*!< Bit mask for UART_C3_PEIE. */ -#define BS_UART_C3_PEIE (1U) /*!< Bit field size in bits for UART_C3_PEIE. */ - -/*! @brief Read current value of the UART_C3_PEIE field. */ -#define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE)) - -/*! @brief Format value for bitfield UART_C3_PEIE. */ -#define BF_UART_C3_PEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE) - -/*! @brief Set the PEIE field to a new value. */ -#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field FEIE[1] (RW) - * - * Enables the framing error flag, S1[FE], to generate interrupt requests. - * - * Values: - * - 0 - FE interrupt requests are disabled. - * - 1 - FE interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_FEIE (1U) /*!< Bit position for UART_C3_FEIE. */ -#define BM_UART_C3_FEIE (0x02U) /*!< Bit mask for UART_C3_FEIE. */ -#define BS_UART_C3_FEIE (1U) /*!< Bit field size in bits for UART_C3_FEIE. */ - -/*! @brief Read current value of the UART_C3_FEIE field. */ -#define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE)) - -/*! @brief Format value for bitfield UART_C3_FEIE. */ -#define BF_UART_C3_FEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE) - -/*! @brief Set the FEIE field to a new value. */ -#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field NEIE[2] (RW) - * - * Enables the noise flag, S1[NF], to generate interrupt requests. - * - * Values: - * - 0 - NF interrupt requests are disabled. - * - 1 - NF interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_NEIE (2U) /*!< Bit position for UART_C3_NEIE. */ -#define BM_UART_C3_NEIE (0x04U) /*!< Bit mask for UART_C3_NEIE. */ -#define BS_UART_C3_NEIE (1U) /*!< Bit field size in bits for UART_C3_NEIE. */ - -/*! @brief Read current value of the UART_C3_NEIE field. */ -#define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE)) - -/*! @brief Format value for bitfield UART_C3_NEIE. */ -#define BF_UART_C3_NEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE) - -/*! @brief Set the NEIE field to a new value. */ -#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field ORIE[3] (RW) - * - * Enables the overrun error flag, S1[OR], to generate interrupt requests. - * - * Values: - * - 0 - OR interrupts are disabled. - * - 1 - OR interrupt requests are enabled. - */ -/*@{*/ -#define BP_UART_C3_ORIE (3U) /*!< Bit position for UART_C3_ORIE. */ -#define BM_UART_C3_ORIE (0x08U) /*!< Bit mask for UART_C3_ORIE. */ -#define BS_UART_C3_ORIE (1U) /*!< Bit field size in bits for UART_C3_ORIE. */ - -/*! @brief Read current value of the UART_C3_ORIE field. */ -#define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE)) - -/*! @brief Format value for bitfield UART_C3_ORIE. */ -#define BF_UART_C3_ORIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE) - -/*! @brief Set the ORIE field to a new value. */ -#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field TXINV[4] (RW) - * - * Setting this field reverses the polarity of the transmitted data output. In - * NRZ format, a one is represented by a mark and a zero is represented by a space - * for normal polarity, and the opposite for inverted polarity. In IrDA format, - * a zero is represented by short high pulse in the middle of a bit time - * remaining idle low for a one for normal polarity, and a zero is represented by short - * low pulse in the middle of a bit time remaining idle high for a one for - * inverted polarity. This field is automatically set when C7816[INIT] and - * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode. - * Setting TXINV inverts all transmitted values, including idle, break, start, and - * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit - * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only - * the transmitted data bits and parity bit are inverted. - * - * Values: - * - 0 - Transmit data is not inverted. - * - 1 - Transmit data is inverted. - */ -/*@{*/ -#define BP_UART_C3_TXINV (4U) /*!< Bit position for UART_C3_TXINV. */ -#define BM_UART_C3_TXINV (0x10U) /*!< Bit mask for UART_C3_TXINV. */ -#define BS_UART_C3_TXINV (1U) /*!< Bit field size in bits for UART_C3_TXINV. */ - -/*! @brief Read current value of the UART_C3_TXINV field. */ -#define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV)) - -/*! @brief Format value for bitfield UART_C3_TXINV. */ -#define BF_UART_C3_TXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV) - -/*! @brief Set the TXINV field to a new value. */ -#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field TXDIR[5] (RW) - * - * Determines whether the TXD pin is used as an input or output in the - * single-wire mode of operation. This field is relevant only to the single wire mode. - * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is - * automatically cleared after the requested block is transmitted. This condition is - * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted. - * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is - * being transmitted, the hardware automatically overrides this field as needed. In - * this situation, TXDIR does not reflect the temporary state associated with - * the NACK. - * - * Values: - * - 0 - TXD pin is an input in single wire mode. - * - 1 - TXD pin is an output in single wire mode. - */ -/*@{*/ -#define BP_UART_C3_TXDIR (5U) /*!< Bit position for UART_C3_TXDIR. */ -#define BM_UART_C3_TXDIR (0x20U) /*!< Bit mask for UART_C3_TXDIR. */ -#define BS_UART_C3_TXDIR (1U) /*!< Bit field size in bits for UART_C3_TXDIR. */ - -/*! @brief Read current value of the UART_C3_TXDIR field. */ -#define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR)) - -/*! @brief Format value for bitfield UART_C3_TXDIR. */ -#define BF_UART_C3_TXDIR(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR) - -/*! @brief Set the TXDIR field to a new value. */ -#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field T8[6] (RW) - * - * T8 is the ninth data bit transmitted when the UART is configured for 9-bit - * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the - * same as in the previous transmission, T8 does not have to be rewritten. The same - * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit, - * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with - * the remaining data. - */ -/*@{*/ -#define BP_UART_C3_T8 (6U) /*!< Bit position for UART_C3_T8. */ -#define BM_UART_C3_T8 (0x40U) /*!< Bit mask for UART_C3_T8. */ -#define BS_UART_C3_T8 (1U) /*!< Bit field size in bits for UART_C3_T8. */ - -/*! @brief Read current value of the UART_C3_T8 field. */ -#define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8)) - -/*! @brief Format value for bitfield UART_C3_T8. */ -#define BF_UART_C3_T8(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8) - -/*! @brief Set the T8 field to a new value. */ -#define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v)) -/*@}*/ - -/*! - * @name Register UART_C3, field R8[7] (RO) - * - * R8 is the ninth data bit received when the UART is configured for 9-bit data - * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the - * current data value in the UARTx_D register. To read the 9th bit, read the - * value of UARTx_C3[R8], then read the UARTx_D register. - */ -/*@{*/ -#define BP_UART_C3_R8 (7U) /*!< Bit position for UART_C3_R8. */ -#define BM_UART_C3_R8 (0x80U) /*!< Bit mask for UART_C3_R8. */ -#define BS_UART_C3_R8 (1U) /*!< Bit field size in bits for UART_C3_R8. */ - -/*! @brief Read current value of the UART_C3_R8 field. */ -#define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8)) -/*@}*/ - -/******************************************************************************* - * HW_UART_D - UART Data Register - ******************************************************************************/ - -/*! - * @brief HW_UART_D - UART Data Register (RW) - * - * Reset value: 0x00U - * - * This register is actually two separate registers. Reads return the contents - * of the read-only receive data register and writes go to the write-only transmit - * data register. In 8-bit or 9-bit data format, only UART data register (D) - * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is - * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D - * register, only if the ninth bit of data needs to be captured. Similarly, the - * ED register needs to be read, prior to the D register, only if the additional - * flag data for the dataword needs to be captured. In the normal 8-bit mode (M - * bit cleared) if the parity is enabled, you get seven data bits and one parity - * bit. That one parity bit is loaded into the D register. So, for the data bits, - * mask off the parity bit from the value you read out of this register. When - * transmitting in 9-bit data format and using 8-bit write instructions, write first - * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to - * C3[T8] stores the data in a temporary register. If D register is written first, - * and then the new data on data bus is stored in D, the temporary value written by - * the last write to C3[T8] gets stored in the C3[T8] register. - */ -typedef union _hw_uart_d -{ - uint8_t U; - struct _hw_uart_d_bitfields - { - uint8_t RT : 8; /*!< [7:0] */ - } B; -} hw_uart_d_t; - -/*! - * @name Constants and macros for entire UART_D register - */ -/*@{*/ -#define HW_UART_D_ADDR(x) ((x) + 0x7U) - -#define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x)) -#define HW_UART_D_RD(x) (HW_UART_D(x).U) -#define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v)) -#define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v))) -#define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v))) -#define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_D bitfields - */ - -/*! - * @name Register UART_D, field RT[7:0] (RW) - * - * Reads return the contents of the read-only receive data register and writes - * go to the write-only transmit data register. - */ -/*@{*/ -#define BP_UART_D_RT (0U) /*!< Bit position for UART_D_RT. */ -#define BM_UART_D_RT (0xFFU) /*!< Bit mask for UART_D_RT. */ -#define BS_UART_D_RT (8U) /*!< Bit field size in bits for UART_D_RT. */ - -/*! @brief Read current value of the UART_D_RT field. */ -#define BR_UART_D_RT(x) (HW_UART_D(x).U) - -/*! @brief Format value for bitfield UART_D_RT. */ -#define BF_UART_D_RT(v) ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT) - -/*! @brief Set the RT field to a new value. */ -#define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_MA1 - UART Match Address Registers 1 - ******************************************************************************/ - -/*! - * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW) - * - * Reset value: 0x00U - * - * The MA1 and MA2 registers are compared to input data addresses when the most - * significant bit is set and the associated C4[MAEN] field is set. If a match - * occurs, the following data is transferred to the data register. If a match - * fails, the following data is discarded. These registers can be read and written at - * anytime. - */ -typedef union _hw_uart_ma1 -{ - uint8_t U; - struct _hw_uart_ma1_bitfields - { - uint8_t MA : 8; /*!< [7:0] Match Address */ - } B; -} hw_uart_ma1_t; - -/*! - * @name Constants and macros for entire UART_MA1 register - */ -/*@{*/ -#define HW_UART_MA1_ADDR(x) ((x) + 0x8U) - -#define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x)) -#define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U) -#define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v)) -#define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v))) -#define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v))) -#define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_MA1 bitfields - */ - -/*! - * @name Register UART_MA1, field MA[7:0] (RW) - */ -/*@{*/ -#define BP_UART_MA1_MA (0U) /*!< Bit position for UART_MA1_MA. */ -#define BM_UART_MA1_MA (0xFFU) /*!< Bit mask for UART_MA1_MA. */ -#define BS_UART_MA1_MA (8U) /*!< Bit field size in bits for UART_MA1_MA. */ - -/*! @brief Read current value of the UART_MA1_MA field. */ -#define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U) - -/*! @brief Format value for bitfield UART_MA1_MA. */ -#define BF_UART_MA1_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA) - -/*! @brief Set the MA field to a new value. */ -#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_MA2 - UART Match Address Registers 2 - ******************************************************************************/ - -/*! - * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW) - * - * Reset value: 0x00U - * - * These registers can be read and written at anytime. The MA1 and MA2 registers - * are compared to input data addresses when the most significant bit is set and - * the associated C4[MAEN] field is set. If a match occurs, the following data - * is transferred to the data register. If a match fails, the following data is - * discarded. - */ -typedef union _hw_uart_ma2 -{ - uint8_t U; - struct _hw_uart_ma2_bitfields - { - uint8_t MA : 8; /*!< [7:0] Match Address */ - } B; -} hw_uart_ma2_t; - -/*! - * @name Constants and macros for entire UART_MA2 register - */ -/*@{*/ -#define HW_UART_MA2_ADDR(x) ((x) + 0x9U) - -#define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x)) -#define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U) -#define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v)) -#define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v))) -#define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v))) -#define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_MA2 bitfields - */ - -/*! - * @name Register UART_MA2, field MA[7:0] (RW) - */ -/*@{*/ -#define BP_UART_MA2_MA (0U) /*!< Bit position for UART_MA2_MA. */ -#define BM_UART_MA2_MA (0xFFU) /*!< Bit mask for UART_MA2_MA. */ -#define BS_UART_MA2_MA (8U) /*!< Bit field size in bits for UART_MA2_MA. */ - -/*! @brief Read current value of the UART_MA2_MA field. */ -#define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U) - -/*! @brief Format value for bitfield UART_MA2_MA. */ -#define BF_UART_MA2_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA) - -/*! @brief Set the MA field to a new value. */ -#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C4 - UART Control Register 4 - ******************************************************************************/ - -/*! - * @brief HW_UART_C4 - UART Control Register 4 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_uart_c4 -{ - uint8_t U; - struct _hw_uart_c4_bitfields - { - uint8_t BRFA : 5; /*!< [4:0] Baud Rate Fine Adjust */ - uint8_t M10 : 1; /*!< [5] 10-bit Mode select */ - uint8_t MAEN2 : 1; /*!< [6] Match Address Mode Enable 2 */ - uint8_t MAEN1 : 1; /*!< [7] Match Address Mode Enable 1 */ - } B; -} hw_uart_c4_t; - -/*! - * @name Constants and macros for entire UART_C4 register - */ -/*@{*/ -#define HW_UART_C4_ADDR(x) ((x) + 0xAU) - -#define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x)) -#define HW_UART_C4_RD(x) (HW_UART_C4(x).U) -#define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v)) -#define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v))) -#define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v))) -#define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C4 bitfields - */ - -/*! - * @name Register UART_C4, field BRFA[4:0] (RW) - * - * This bit field is used to add more timing resolution to the average baud - * frequency, in increments of 1/32. See Baud rate generation for more information. - */ -/*@{*/ -#define BP_UART_C4_BRFA (0U) /*!< Bit position for UART_C4_BRFA. */ -#define BM_UART_C4_BRFA (0x1FU) /*!< Bit mask for UART_C4_BRFA. */ -#define BS_UART_C4_BRFA (5U) /*!< Bit field size in bits for UART_C4_BRFA. */ - -/*! @brief Read current value of the UART_C4_BRFA field. */ -#define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA) - -/*! @brief Format value for bitfield UART_C4_BRFA. */ -#define BF_UART_C4_BRFA(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA) - -/*! @brief Set the BRFA field to a new value. */ -#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v))) -/*@}*/ - -/*! - * @name Register UART_C4, field M10[5] (RW) - * - * Causes a tenth, non-memory mapped bit to be part of the serial transmission. - * This tenth bit is generated and interpreted as a parity bit. The M10 field - * does not affect the LIN send or detect break behavior. If M10 is set, then both - * C1[M] and C1[PE] must also be set. This field must be cleared when - * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information. - * - * Values: - * - 0 - The parity bit is the ninth bit in the serial transmission. - * - 1 - The parity bit is the tenth bit in the serial transmission. - */ -/*@{*/ -#define BP_UART_C4_M10 (5U) /*!< Bit position for UART_C4_M10. */ -#define BM_UART_C4_M10 (0x20U) /*!< Bit mask for UART_C4_M10. */ -#define BS_UART_C4_M10 (1U) /*!< Bit field size in bits for UART_C4_M10. */ - -/*! @brief Read current value of the UART_C4_M10 field. */ -#define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10)) - -/*! @brief Format value for bitfield UART_C4_M10. */ -#define BF_UART_C4_M10(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10) - -/*! @brief Set the M10 field to a new value. */ -#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v)) -/*@}*/ - -/*! - * @name Register UART_C4, field MAEN2[6] (RW) - * - * See Match address operation for more information. - * - * Values: - * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared. - * - 1 - All data received with the most significant bit cleared, is discarded. - * All data received with the most significant bit set, is compared with - * contents of MA2 register. If no match occurs, the data is discarded. If a - * match occurs, data is transferred to the data buffer. This field must be - * cleared when C7816[ISO7816E] is set/enabled. - */ -/*@{*/ -#define BP_UART_C4_MAEN2 (6U) /*!< Bit position for UART_C4_MAEN2. */ -#define BM_UART_C4_MAEN2 (0x40U) /*!< Bit mask for UART_C4_MAEN2. */ -#define BS_UART_C4_MAEN2 (1U) /*!< Bit field size in bits for UART_C4_MAEN2. */ - -/*! @brief Read current value of the UART_C4_MAEN2 field. */ -#define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2)) - -/*! @brief Format value for bitfield UART_C4_MAEN2. */ -#define BF_UART_C4_MAEN2(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2) - -/*! @brief Set the MAEN2 field to a new value. */ -#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v)) -/*@}*/ - -/*! - * @name Register UART_C4, field MAEN1[7] (RW) - * - * See Match address operation for more information. - * - * Values: - * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared. - * - 1 - All data received with the most significant bit cleared, is discarded. - * All data received with the most significant bit set, is compared with - * contents of MA1 register. If no match occurs, the data is discarded. If match - * occurs, data is transferred to the data buffer. This field must be cleared - * when C7816[ISO7816E] is set/enabled. - */ -/*@{*/ -#define BP_UART_C4_MAEN1 (7U) /*!< Bit position for UART_C4_MAEN1. */ -#define BM_UART_C4_MAEN1 (0x80U) /*!< Bit mask for UART_C4_MAEN1. */ -#define BS_UART_C4_MAEN1 (1U) /*!< Bit field size in bits for UART_C4_MAEN1. */ - -/*! @brief Read current value of the UART_C4_MAEN1 field. */ -#define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1)) - -/*! @brief Format value for bitfield UART_C4_MAEN1. */ -#define BF_UART_C4_MAEN1(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1) - -/*! @brief Set the MAEN1 field to a new value. */ -#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_C5 - UART Control Register 5 - ******************************************************************************/ - -/*! - * @brief HW_UART_C5 - UART Control Register 5 (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_uart_c5 -{ - uint8_t U; - struct _hw_uart_c5_bitfields - { - uint8_t RESERVED0 : 3; /*!< [2:0] */ - uint8_t LBKDDMAS : 1; /*!< [3] LIN Break Detect DMA Select Bit */ - uint8_t ILDMAS : 1; /*!< [4] Idle Line DMA Select */ - uint8_t RDMAS : 1; /*!< [5] Receiver Full DMA Select */ - uint8_t TCDMAS : 1; /*!< [6] Transmission Complete DMA Select */ - uint8_t TDMAS : 1; /*!< [7] Transmitter DMA Select */ - } B; -} hw_uart_c5_t; - -/*! - * @name Constants and macros for entire UART_C5 register - */ -/*@{*/ -#define HW_UART_C5_ADDR(x) ((x) + 0xBU) - -#define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x)) -#define HW_UART_C5_RD(x) (HW_UART_C5(x).U) -#define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v)) -#define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v))) -#define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v))) -#define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C5 bitfields - */ - -/*! - * @name Register UART_C5, field LBKDDMAS[3] (RW) - * - * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or - * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is - * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless - * of the state of LBKDDMAS. - * - * Values: - * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is - * asserted to request an interrupt service. - * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is - * asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_LBKDDMAS (3U) /*!< Bit position for UART_C5_LBKDDMAS. */ -#define BM_UART_C5_LBKDDMAS (0x08U) /*!< Bit mask for UART_C5_LBKDDMAS. */ -#define BS_UART_C5_LBKDDMAS (1U) /*!< Bit field size in bits for UART_C5_LBKDDMAS. */ - -/*! @brief Read current value of the UART_C5_LBKDDMAS field. */ -#define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS)) - -/*! @brief Format value for bitfield UART_C5_LBKDDMAS. */ -#define BF_UART_C5_LBKDDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_LBKDDMAS) & BM_UART_C5_LBKDDMAS) - -/*! @brief Set the LBKDDMAS field to a new value. */ -#define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v)) -/*@}*/ - -/*! - * @name Register UART_C5, field ILDMAS[4] (RW) - * - * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA - * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE - * DMA and IDLE interrupt request signals are not asserted, regardless of the state - * of ILDMAS. - * - * Values: - * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is - * asserted to request an interrupt service. - * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is - * asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_ILDMAS (4U) /*!< Bit position for UART_C5_ILDMAS. */ -#define BM_UART_C5_ILDMAS (0x10U) /*!< Bit mask for UART_C5_ILDMAS. */ -#define BS_UART_C5_ILDMAS (1U) /*!< Bit field size in bits for UART_C5_ILDMAS. */ - -/*! @brief Read current value of the UART_C5_ILDMAS field. */ -#define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS)) - -/*! @brief Format value for bitfield UART_C5_ILDMAS. */ -#define BF_UART_C5_ILDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_ILDMAS) & BM_UART_C5_ILDMAS) - -/*! @brief Set the ILDMAS field to a new value. */ -#define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v)) -/*@}*/ - -/*! - * @name Register UART_C5, field RDMAS[5] (RW) - * - * Configures the receiver data register full flag, S1[RDRF], to generate - * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is - * set, the RDRF DMA and RDFR interrupt request signals are not asserted, - * regardless of the state of RDMAS. - * - * Values: - * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is - * asserted to request an interrupt service. - * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is - * asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_RDMAS (5U) /*!< Bit position for UART_C5_RDMAS. */ -#define BM_UART_C5_RDMAS (0x20U) /*!< Bit mask for UART_C5_RDMAS. */ -#define BS_UART_C5_RDMAS (1U) /*!< Bit field size in bits for UART_C5_RDMAS. */ - -/*! @brief Read current value of the UART_C5_RDMAS field. */ -#define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS)) - -/*! @brief Format value for bitfield UART_C5_RDMAS. */ -#define BF_UART_C5_RDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS) - -/*! @brief Set the RDMAS field to a new value. */ -#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v)) -/*@}*/ - -/*! - * @name Register UART_C5, field TCDMAS[6] (RW) - * - * Configures the transmission complete flag, S1[TC], to generate interrupt or - * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC - * interrupt request signals are not asserted when the S1[TC] flag is set, regardless - * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE] - * must be cleared, and D must not be written unless a DMA request is being serviced. - * - * Values: - * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request - * signal is asserted to request an interrupt service. - * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request - * signal is asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_TCDMAS (6U) /*!< Bit position for UART_C5_TCDMAS. */ -#define BM_UART_C5_TCDMAS (0x40U) /*!< Bit mask for UART_C5_TCDMAS. */ -#define BS_UART_C5_TCDMAS (1U) /*!< Bit field size in bits for UART_C5_TCDMAS. */ - -/*! @brief Read current value of the UART_C5_TCDMAS field. */ -#define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS)) - -/*! @brief Format value for bitfield UART_C5_TCDMAS. */ -#define BF_UART_C5_TCDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TCDMAS) & BM_UART_C5_TCDMAS) - -/*! @brief Set the TCDMAS field to a new value. */ -#define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v)) -/*@}*/ - -/*! - * @name Register UART_C5, field TDMAS[7] (RW) - * - * Configures the transmit data register empty flag, S1[TDRE], to generate - * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and - * TDRE interrupt request signals are not asserted when the TDRE flag is set, - * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE] - * must be cleared, and D must not be written unless a DMA request is being - * serviced. - * - * Values: - * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt - * request signal is asserted to request interrupt service. - * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request - * signal is asserted to request a DMA transfer. - */ -/*@{*/ -#define BP_UART_C5_TDMAS (7U) /*!< Bit position for UART_C5_TDMAS. */ -#define BM_UART_C5_TDMAS (0x80U) /*!< Bit mask for UART_C5_TDMAS. */ -#define BS_UART_C5_TDMAS (1U) /*!< Bit field size in bits for UART_C5_TDMAS. */ - -/*! @brief Read current value of the UART_C5_TDMAS field. */ -#define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS)) - -/*! @brief Format value for bitfield UART_C5_TDMAS. */ -#define BF_UART_C5_TDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS) - -/*! @brief Set the TDMAS field to a new value. */ -#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_ED - UART Extended Data Register - ******************************************************************************/ - -/*! - * @brief HW_UART_ED - UART Extended Data Register (RO) - * - * Reset value: 0x00U - * - * This register contains additional information flags that are stored with a - * received dataword. This register may be read at any time but contains valid data - * only if there is a dataword in the receive FIFO. The data contained in this - * register represents additional information regarding the conditions on which a - * dataword was received. The importance of this data varies with the - * application, and in some cases maybe completely optional. These fields automatically - * update to reflect the conditions of the next dataword whenever D is read. If - * S1[NF] and S1[PF] have not been set since the last time the receive buffer was - * empty, the NOISY and PARITYE fields will be zero. - */ -typedef union _hw_uart_ed -{ - uint8_t U; - struct _hw_uart_ed_bitfields - { - uint8_t RESERVED0 : 6; /*!< [5:0] */ - uint8_t PARITYE : 1; /*!< [6] */ - uint8_t NOISY : 1; /*!< [7] */ - } B; -} hw_uart_ed_t; - -/*! - * @name Constants and macros for entire UART_ED register - */ -/*@{*/ -#define HW_UART_ED_ADDR(x) ((x) + 0xCU) - -#define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x)) -#define HW_UART_ED_RD(x) (HW_UART_ED(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_ED bitfields - */ - -/*! - * @name Register UART_ED, field PARITYE[6] (RO) - * - * The current received dataword contained in D and C3[R8] was received with a - * parity error. - * - * Values: - * - 0 - The dataword was received without a parity error. - * - 1 - The dataword was received with a parity error. - */ -/*@{*/ -#define BP_UART_ED_PARITYE (6U) /*!< Bit position for UART_ED_PARITYE. */ -#define BM_UART_ED_PARITYE (0x40U) /*!< Bit mask for UART_ED_PARITYE. */ -#define BS_UART_ED_PARITYE (1U) /*!< Bit field size in bits for UART_ED_PARITYE. */ - -/*! @brief Read current value of the UART_ED_PARITYE field. */ -#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE)) -/*@}*/ - -/*! - * @name Register UART_ED, field NOISY[7] (RO) - * - * The current received dataword contained in D and C3[R8] was received with - * noise. - * - * Values: - * - 0 - The dataword was received without noise. - * - 1 - The data was received with noise. - */ -/*@{*/ -#define BP_UART_ED_NOISY (7U) /*!< Bit position for UART_ED_NOISY. */ -#define BM_UART_ED_NOISY (0x80U) /*!< Bit mask for UART_ED_NOISY. */ -#define BS_UART_ED_NOISY (1U) /*!< Bit field size in bits for UART_ED_NOISY. */ - -/*! @brief Read current value of the UART_ED_NOISY field. */ -#define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY)) -/*@}*/ - -/******************************************************************************* - * HW_UART_MODEM - UART Modem Register - ******************************************************************************/ - -/*! - * @brief HW_UART_MODEM - UART Modem Register (RW) - * - * Reset value: 0x00U - * - * The MODEM register controls options for setting the modem configuration. - * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is - * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The - * ISO-7816 protocol does not use the RTS and CTS signals. - */ -typedef union _hw_uart_modem -{ - uint8_t U; - struct _hw_uart_modem_bitfields - { - uint8_t TXCTSE : 1; /*!< [0] Transmitter clear-to-send enable */ - uint8_t TXRTSE : 1; /*!< [1] Transmitter request-to-send enable */ - uint8_t TXRTSPOL : 1; /*!< [2] Transmitter request-to-send polarity */ - uint8_t RXRTSE : 1; /*!< [3] Receiver request-to-send enable */ - uint8_t RESERVED0 : 4; /*!< [7:4] */ - } B; -} hw_uart_modem_t; - -/*! - * @name Constants and macros for entire UART_MODEM register - */ -/*@{*/ -#define HW_UART_MODEM_ADDR(x) ((x) + 0xDU) - -#define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x)) -#define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U) -#define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v)) -#define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v))) -#define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v))) -#define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_MODEM bitfields - */ - -/*! - * @name Register UART_MODEM, field TXCTSE[0] (RW) - * - * TXCTSE controls the operation of the transmitter. TXCTSE can be set - * independently from the state of TXRTSE and RXRTSE. - * - * Values: - * - 0 - CTS has no effect on the transmitter. - * - 1 - Enables clear-to-send operation. The transmitter checks the state of - * CTS each time it is ready to send a character. If CTS is asserted, the - * character is sent. If CTS is deasserted, the signal TXD remains in the mark - * state and transmission is delayed until CTS is asserted. Changes in CTS as a - * character is being sent do not affect its transmission. - */ -/*@{*/ -#define BP_UART_MODEM_TXCTSE (0U) /*!< Bit position for UART_MODEM_TXCTSE. */ -#define BM_UART_MODEM_TXCTSE (0x01U) /*!< Bit mask for UART_MODEM_TXCTSE. */ -#define BS_UART_MODEM_TXCTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXCTSE. */ - -/*! @brief Read current value of the UART_MODEM_TXCTSE field. */ -#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE)) - -/*! @brief Format value for bitfield UART_MODEM_TXCTSE. */ -#define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE) - -/*! @brief Set the TXCTSE field to a new value. */ -#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v)) -/*@}*/ - -/*! - * @name Register UART_MODEM, field TXRTSE[1] (RW) - * - * Controls RTS before and after a transmission. - * - * Values: - * - 0 - The transmitter has no effect on RTS. - * - 1 - When a character is placed into an empty transmitter data buffer , RTS - * asserts one bit time before the start bit is transmitted. RTS deasserts - * one bit time after all characters in the transmitter data buffer and shift - * register are completely sent, including the last stop bit. (FIFO) (FIFO) - */ -/*@{*/ -#define BP_UART_MODEM_TXRTSE (1U) /*!< Bit position for UART_MODEM_TXRTSE. */ -#define BM_UART_MODEM_TXRTSE (0x02U) /*!< Bit mask for UART_MODEM_TXRTSE. */ -#define BS_UART_MODEM_TXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSE. */ - -/*! @brief Read current value of the UART_MODEM_TXRTSE field. */ -#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE)) - -/*! @brief Format value for bitfield UART_MODEM_TXRTSE. */ -#define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE) - -/*! @brief Set the TXRTSE field to a new value. */ -#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v)) -/*@}*/ - -/*! - * @name Register UART_MODEM, field TXRTSPOL[2] (RW) - * - * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the - * polarity of the receiver RTS. RTS will remain negated in the active low state - * unless TXRTSE is set. - * - * Values: - * - 0 - Transmitter RTS is active low. - * - 1 - Transmitter RTS is active high. - */ -/*@{*/ -#define BP_UART_MODEM_TXRTSPOL (2U) /*!< Bit position for UART_MODEM_TXRTSPOL. */ -#define BM_UART_MODEM_TXRTSPOL (0x04U) /*!< Bit mask for UART_MODEM_TXRTSPOL. */ -#define BS_UART_MODEM_TXRTSPOL (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSPOL. */ - -/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */ -#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL)) - -/*! @brief Format value for bitfield UART_MODEM_TXRTSPOL. */ -#define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL) - -/*! @brief Set the TXRTSPOL field to a new value. */ -#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v)) -/*@}*/ - -/*! - * @name Register UART_MODEM, field RXRTSE[3] (RW) - * - * Allows the RTS output to control the CTS input of the transmitting device to - * prevent receiver overrun. Do not set both RXRTSE and TXRTSE. - * - * Values: - * - 0 - The receiver has no effect on RTS. - * - 1 - RTS is deasserted if the number of characters in the receiver data - * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted - * when the number of characters in the receiver data register (FIFO) is less - * than RWFIFO[RXWATER]. - */ -/*@{*/ -#define BP_UART_MODEM_RXRTSE (3U) /*!< Bit position for UART_MODEM_RXRTSE. */ -#define BM_UART_MODEM_RXRTSE (0x08U) /*!< Bit mask for UART_MODEM_RXRTSE. */ -#define BS_UART_MODEM_RXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_RXRTSE. */ - -/*! @brief Read current value of the UART_MODEM_RXRTSE field. */ -#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE)) - -/*! @brief Format value for bitfield UART_MODEM_RXRTSE. */ -#define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE) - -/*! @brief Set the RXRTSE field to a new value. */ -#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_IR - UART Infrared Register - ******************************************************************************/ - -/*! - * @brief HW_UART_IR - UART Infrared Register (RW) - * - * Reset value: 0x00U - * - * The IR register controls options for setting the infrared configuration. - */ -typedef union _hw_uart_ir -{ - uint8_t U; - struct _hw_uart_ir_bitfields - { - uint8_t TNP : 2; /*!< [1:0] Transmitter narrow pulse */ - uint8_t IREN : 1; /*!< [2] Infrared enable */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_uart_ir_t; - -/*! - * @name Constants and macros for entire UART_IR register - */ -/*@{*/ -#define HW_UART_IR_ADDR(x) ((x) + 0xEU) - -#define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x)) -#define HW_UART_IR_RD(x) (HW_UART_IR(x).U) -#define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v)) -#define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v))) -#define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v))) -#define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_IR bitfields - */ - -/*! - * @name Register UART_IR, field TNP[1:0] (RW) - * - * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse. - * - * Values: - * - 00 - 3/16. - * - 01 - 1/16. - * - 10 - 1/32. - * - 11 - 1/4. - */ -/*@{*/ -#define BP_UART_IR_TNP (0U) /*!< Bit position for UART_IR_TNP. */ -#define BM_UART_IR_TNP (0x03U) /*!< Bit mask for UART_IR_TNP. */ -#define BS_UART_IR_TNP (2U) /*!< Bit field size in bits for UART_IR_TNP. */ - -/*! @brief Read current value of the UART_IR_TNP field. */ -#define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP) - -/*! @brief Format value for bitfield UART_IR_TNP. */ -#define BF_UART_IR_TNP(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP) - -/*! @brief Set the TNP field to a new value. */ -#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v))) -/*@}*/ - -/*! - * @name Register UART_IR, field IREN[2] (RW) - * - * Enables/disables the infrared modulation/demodulation. - * - * Values: - * - 0 - IR disabled. - * - 1 - IR enabled. - */ -/*@{*/ -#define BP_UART_IR_IREN (2U) /*!< Bit position for UART_IR_IREN. */ -#define BM_UART_IR_IREN (0x04U) /*!< Bit mask for UART_IR_IREN. */ -#define BS_UART_IR_IREN (1U) /*!< Bit field size in bits for UART_IR_IREN. */ - -/*! @brief Read current value of the UART_IR_IREN field. */ -#define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN)) - -/*! @brief Format value for bitfield UART_IR_IREN. */ -#define BF_UART_IR_IREN(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN) - -/*! @brief Set the IREN field to a new value. */ -#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_PFIFO - UART FIFO Parameters - ******************************************************************************/ - -/*! - * @brief HW_UART_PFIFO - UART FIFO Parameters (RW) - * - * Reset value: 0x00U - * - * This register provides the ability for the programmer to turn on and off FIFO - * functionality. It also provides the size of the FIFO that has been - * implemented. This register may be read at any time. This register must be written only - * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is - * empty. - */ -typedef union _hw_uart_pfifo -{ - uint8_t U; - struct _hw_uart_pfifo_bitfields - { - uint8_t RXFIFOSIZE : 3; /*!< [2:0] Receive FIFO. Buffer Depth */ - uint8_t RXFE : 1; /*!< [3] Receive FIFO Enable */ - uint8_t TXFIFOSIZE : 3; /*!< [6:4] Transmit FIFO. Buffer Depth */ - uint8_t TXFE : 1; /*!< [7] Transmit FIFO Enable */ - } B; -} hw_uart_pfifo_t; - -/*! - * @name Constants and macros for entire UART_PFIFO register - */ -/*@{*/ -#define HW_UART_PFIFO_ADDR(x) ((x) + 0x10U) - -#define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x)) -#define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U) -#define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v)) -#define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v))) -#define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v))) -#define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_PFIFO bitfields - */ - -/*! - * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO) - * - * The maximum number of receive datawords that can be stored in the receive - * buffer before an overrun occurs. This field is read only. - * - * Values: - * - 000 - Receive FIFO/Buffer depth = 1 dataword. - * - 001 - Receive FIFO/Buffer depth = 4 datawords. - * - 010 - Receive FIFO/Buffer depth = 8 datawords. - * - 011 - Receive FIFO/Buffer depth = 16 datawords. - * - 100 - Receive FIFO/Buffer depth = 32 datawords. - * - 101 - Receive FIFO/Buffer depth = 64 datawords. - * - 110 - Receive FIFO/Buffer depth = 128 datawords. - * - 111 - Reserved. - */ -/*@{*/ -#define BP_UART_PFIFO_RXFIFOSIZE (0U) /*!< Bit position for UART_PFIFO_RXFIFOSIZE. */ -#define BM_UART_PFIFO_RXFIFOSIZE (0x07U) /*!< Bit mask for UART_PFIFO_RXFIFOSIZE. */ -#define BS_UART_PFIFO_RXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. */ - -/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */ -#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE) -/*@}*/ - -/*! - * @name Register UART_PFIFO, field RXFE[3] (RW) - * - * When this field is set, the built in FIFO structure for the receive buffer is - * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field. - * If this field is not set, the receive buffer operates as a FIFO of depth one - * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be - * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH - * commands must be issued immediately after changing this field. - * - * Values: - * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) - * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. - */ -/*@{*/ -#define BP_UART_PFIFO_RXFE (3U) /*!< Bit position for UART_PFIFO_RXFE. */ -#define BM_UART_PFIFO_RXFE (0x08U) /*!< Bit mask for UART_PFIFO_RXFE. */ -#define BS_UART_PFIFO_RXFE (1U) /*!< Bit field size in bits for UART_PFIFO_RXFE. */ - -/*! @brief Read current value of the UART_PFIFO_RXFE field. */ -#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE)) - -/*! @brief Format value for bitfield UART_PFIFO_RXFE. */ -#define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE) - -/*! @brief Set the RXFE field to a new value. */ -#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO) - * - * The maximum number of transmit datawords that can be stored in the transmit - * buffer. This field is read only. - * - * Values: - * - 000 - Transmit FIFO/Buffer depth = 1 dataword. - * - 001 - Transmit FIFO/Buffer depth = 4 datawords. - * - 010 - Transmit FIFO/Buffer depth = 8 datawords. - * - 011 - Transmit FIFO/Buffer depth = 16 datawords. - * - 100 - Transmit FIFO/Buffer depth = 32 datawords. - * - 101 - Transmit FIFO/Buffer depth = 64 datawords. - * - 110 - Transmit FIFO/Buffer depth = 128 datawords. - * - 111 - Reserved. - */ -/*@{*/ -#define BP_UART_PFIFO_TXFIFOSIZE (4U) /*!< Bit position for UART_PFIFO_TXFIFOSIZE. */ -#define BM_UART_PFIFO_TXFIFOSIZE (0x70U) /*!< Bit mask for UART_PFIFO_TXFIFOSIZE. */ -#define BS_UART_PFIFO_TXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. */ - -/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */ -#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE) -/*@}*/ - -/*! - * @name Register UART_PFIFO, field TXFE[7] (RW) - * - * When this field is set, the built in FIFO structure for the transmit buffer - * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this - * field is not set, the transmit buffer operates as a FIFO of depth one dataword - * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared - * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must - * be issued immediately after changing this field. - * - * Values: - * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). - * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. - */ -/*@{*/ -#define BP_UART_PFIFO_TXFE (7U) /*!< Bit position for UART_PFIFO_TXFE. */ -#define BM_UART_PFIFO_TXFE (0x80U) /*!< Bit mask for UART_PFIFO_TXFE. */ -#define BS_UART_PFIFO_TXFE (1U) /*!< Bit field size in bits for UART_PFIFO_TXFE. */ - -/*! @brief Read current value of the UART_PFIFO_TXFE field. */ -#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE)) - -/*! @brief Format value for bitfield UART_PFIFO_TXFE. */ -#define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE) - -/*! @brief Set the TXFE field to a new value. */ -#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_CFIFO - UART FIFO Control Register - ******************************************************************************/ - -/*! - * @brief HW_UART_CFIFO - UART FIFO Control Register (RW) - * - * Reset value: 0x00U - * - * This register provides the ability to program various control fields for FIFO - * operation. This register may be read or written at any time. Note that - * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action - * to prevent unintended/unpredictable behavior. Therefore, it is recommended that - * TE and RE be cleared prior to flushing the corresponding FIFO. - */ -typedef union _hw_uart_cfifo -{ - uint8_t U; - struct _hw_uart_cfifo_bitfields - { - uint8_t RXUFE : 1; /*!< [0] Receive FIFO Underflow Interrupt Enable */ - uint8_t TXOFE : 1; /*!< [1] Transmit FIFO Overflow Interrupt Enable */ - uint8_t RXOFE : 1; /*!< [2] Receive FIFO Overflow Interrupt Enable */ - uint8_t RESERVED0 : 3; /*!< [5:3] */ - uint8_t RXFLUSH : 1; /*!< [6] Receive FIFO/Buffer Flush */ - uint8_t TXFLUSH : 1; /*!< [7] Transmit FIFO/Buffer Flush */ - } B; -} hw_uart_cfifo_t; - -/*! - * @name Constants and macros for entire UART_CFIFO register - */ -/*@{*/ -#define HW_UART_CFIFO_ADDR(x) ((x) + 0x11U) - -#define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x)) -#define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U) -#define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v)) -#define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v))) -#define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v))) -#define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_CFIFO bitfields - */ - -/*! - * @name Register UART_CFIFO, field RXUFE[0] (RW) - * - * When this field is set, the RXUF flag generates an interrupt to the host. - * - * Values: - * - 0 - RXUF flag does not generate an interrupt to the host. - * - 1 - RXUF flag generates an interrupt to the host. - */ -/*@{*/ -#define BP_UART_CFIFO_RXUFE (0U) /*!< Bit position for UART_CFIFO_RXUFE. */ -#define BM_UART_CFIFO_RXUFE (0x01U) /*!< Bit mask for UART_CFIFO_RXUFE. */ -#define BS_UART_CFIFO_RXUFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXUFE. */ - -/*! @brief Read current value of the UART_CFIFO_RXUFE field. */ -#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE)) - -/*! @brief Format value for bitfield UART_CFIFO_RXUFE. */ -#define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE) - -/*! @brief Set the RXUFE field to a new value. */ -#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field TXOFE[1] (RW) - * - * When this field is set, the TXOF flag generates an interrupt to the host. - * - * Values: - * - 0 - TXOF flag does not generate an interrupt to the host. - * - 1 - TXOF flag generates an interrupt to the host. - */ -/*@{*/ -#define BP_UART_CFIFO_TXOFE (1U) /*!< Bit position for UART_CFIFO_TXOFE. */ -#define BM_UART_CFIFO_TXOFE (0x02U) /*!< Bit mask for UART_CFIFO_TXOFE. */ -#define BS_UART_CFIFO_TXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_TXOFE. */ - -/*! @brief Read current value of the UART_CFIFO_TXOFE field. */ -#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE)) - -/*! @brief Format value for bitfield UART_CFIFO_TXOFE. */ -#define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE) - -/*! @brief Set the TXOFE field to a new value. */ -#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field RXOFE[2] (RW) - * - * When this field is set, the RXOF flag generates an interrupt to the host. - * - * Values: - * - 0 - RXOF flag does not generate an interrupt to the host. - * - 1 - RXOF flag generates an interrupt to the host. - */ -/*@{*/ -#define BP_UART_CFIFO_RXOFE (2U) /*!< Bit position for UART_CFIFO_RXOFE. */ -#define BM_UART_CFIFO_RXOFE (0x04U) /*!< Bit mask for UART_CFIFO_RXOFE. */ -#define BS_UART_CFIFO_RXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXOFE. */ - -/*! @brief Read current value of the UART_CFIFO_RXOFE field. */ -#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE)) - -/*! @brief Format value for bitfield UART_CFIFO_RXOFE. */ -#define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE) - -/*! @brief Set the RXOFE field to a new value. */ -#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ) - * - * Writing to this field causes all data that is stored in the receive - * FIFO/buffer to be flushed. This does not affect data that is in the receive shift - * register. - * - * Values: - * - 0 - No flush operation occurs. - * - 1 - All data in the receive FIFO/buffer is cleared out. - */ -/*@{*/ -#define BP_UART_CFIFO_RXFLUSH (6U) /*!< Bit position for UART_CFIFO_RXFLUSH. */ -#define BM_UART_CFIFO_RXFLUSH (0x40U) /*!< Bit mask for UART_CFIFO_RXFLUSH. */ -#define BS_UART_CFIFO_RXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_RXFLUSH. */ - -/*! @brief Format value for bitfield UART_CFIFO_RXFLUSH. */ -#define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH) - -/*! @brief Set the RXFLUSH field to a new value. */ -#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v)) -/*@}*/ - -/*! - * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ) - * - * Writing to this field causes all data that is stored in the transmit - * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift - * register. - * - * Values: - * - 0 - No flush operation occurs. - * - 1 - All data in the transmit FIFO/Buffer is cleared out. - */ -/*@{*/ -#define BP_UART_CFIFO_TXFLUSH (7U) /*!< Bit position for UART_CFIFO_TXFLUSH. */ -#define BM_UART_CFIFO_TXFLUSH (0x80U) /*!< Bit mask for UART_CFIFO_TXFLUSH. */ -#define BS_UART_CFIFO_TXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_TXFLUSH. */ - -/*! @brief Format value for bitfield UART_CFIFO_TXFLUSH. */ -#define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH) - -/*! @brief Set the TXFLUSH field to a new value. */ -#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_SFIFO - UART FIFO Status Register - ******************************************************************************/ - -/*! - * @brief HW_UART_SFIFO - UART FIFO Status Register (RW) - * - * Reset value: 0xC0U - * - * This register provides status information regarding the transmit and receiver - * buffers/FIFOs, including interrupt information. This register may be written - * to or read at any time. - */ -typedef union _hw_uart_sfifo -{ - uint8_t U; - struct _hw_uart_sfifo_bitfields - { - uint8_t RXUF : 1; /*!< [0] Receiver Buffer Underflow Flag */ - uint8_t TXOF : 1; /*!< [1] Transmitter Buffer Overflow Flag */ - uint8_t RXOF : 1; /*!< [2] Receiver Buffer Overflow Flag */ - uint8_t RESERVED0 : 3; /*!< [5:3] */ - uint8_t RXEMPT : 1; /*!< [6] Receive Buffer/FIFO Empty */ - uint8_t TXEMPT : 1; /*!< [7] Transmit Buffer/FIFO Empty */ - } B; -} hw_uart_sfifo_t; - -/*! - * @name Constants and macros for entire UART_SFIFO register - */ -/*@{*/ -#define HW_UART_SFIFO_ADDR(x) ((x) + 0x12U) - -#define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x)) -#define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U) -#define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v)) -#define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v))) -#define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v))) -#define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_SFIFO bitfields - */ - -/*! - * @name Register UART_SFIFO, field RXUF[0] (W1C) - * - * Indicates that more data has been read from the receive buffer than was - * present. This field will assert regardless of the value of CFIFO[RXUFE]. However, - * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag - * is cleared by writing a 1. - * - * Values: - * - 0 - No receive buffer underflow has occurred since the last time the flag - * was cleared. - * - 1 - At least one receive buffer underflow has occurred since the last time - * the flag was cleared. - */ -/*@{*/ -#define BP_UART_SFIFO_RXUF (0U) /*!< Bit position for UART_SFIFO_RXUF. */ -#define BM_UART_SFIFO_RXUF (0x01U) /*!< Bit mask for UART_SFIFO_RXUF. */ -#define BS_UART_SFIFO_RXUF (1U) /*!< Bit field size in bits for UART_SFIFO_RXUF. */ - -/*! @brief Read current value of the UART_SFIFO_RXUF field. */ -#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF)) - -/*! @brief Format value for bitfield UART_SFIFO_RXUF. */ -#define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF) - -/*! @brief Set the RXUF field to a new value. */ -#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field TXOF[1] (W1C) - * - * Indicates that more data has been written to the transmit buffer than it can - * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However, - * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This - * flag is cleared by writing a 1. - * - * Values: - * - 0 - No transmit buffer overflow has occurred since the last time the flag - * was cleared. - * - 1 - At least one transmit buffer overflow has occurred since the last time - * the flag was cleared. - */ -/*@{*/ -#define BP_UART_SFIFO_TXOF (1U) /*!< Bit position for UART_SFIFO_TXOF. */ -#define BM_UART_SFIFO_TXOF (0x02U) /*!< Bit mask for UART_SFIFO_TXOF. */ -#define BS_UART_SFIFO_TXOF (1U) /*!< Bit field size in bits for UART_SFIFO_TXOF. */ - -/*! @brief Read current value of the UART_SFIFO_TXOF field. */ -#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF)) - -/*! @brief Format value for bitfield UART_SFIFO_TXOF. */ -#define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF) - -/*! @brief Set the TXOF field to a new value. */ -#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field RXOF[2] (W1C) - * - * Indicates that more data has been written to the receive buffer than it can - * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However, - * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag - * is cleared by writing a 1. - * - * Values: - * - 0 - No receive buffer overflow has occurred since the last time the flag - * was cleared. - * - 1 - At least one receive buffer overflow has occurred since the last time - * the flag was cleared. - */ -/*@{*/ -#define BP_UART_SFIFO_RXOF (2U) /*!< Bit position for UART_SFIFO_RXOF. */ -#define BM_UART_SFIFO_RXOF (0x04U) /*!< Bit mask for UART_SFIFO_RXOF. */ -#define BS_UART_SFIFO_RXOF (1U) /*!< Bit field size in bits for UART_SFIFO_RXOF. */ - -/*! @brief Read current value of the UART_SFIFO_RXOF field. */ -#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF)) - -/*! @brief Format value for bitfield UART_SFIFO_RXOF. */ -#define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF) - -/*! @brief Set the RXOF field to a new value. */ -#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field RXEMPT[6] (RO) - * - * Asserts when there is no data in the receive FIFO/Buffer. This field does not - * take into account data that is in the receive shift register. - * - * Values: - * - 0 - Receive buffer is not empty. - * - 1 - Receive buffer is empty. - */ -/*@{*/ -#define BP_UART_SFIFO_RXEMPT (6U) /*!< Bit position for UART_SFIFO_RXEMPT. */ -#define BM_UART_SFIFO_RXEMPT (0x40U) /*!< Bit mask for UART_SFIFO_RXEMPT. */ -#define BS_UART_SFIFO_RXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_RXEMPT. */ - -/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */ -#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT)) -/*@}*/ - -/*! - * @name Register UART_SFIFO, field TXEMPT[7] (RO) - * - * Asserts when there is no data in the Transmit FIFO/buffer. This field does - * not take into account data that is in the transmit shift register. - * - * Values: - * - 0 - Transmit buffer is not empty. - * - 1 - Transmit buffer is empty. - */ -/*@{*/ -#define BP_UART_SFIFO_TXEMPT (7U) /*!< Bit position for UART_SFIFO_TXEMPT. */ -#define BM_UART_SFIFO_TXEMPT (0x80U) /*!< Bit mask for UART_SFIFO_TXEMPT. */ -#define BS_UART_SFIFO_TXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_TXEMPT. */ - -/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */ -#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT)) -/*@}*/ - -/******************************************************************************* - * HW_UART_TWFIFO - UART FIFO Transmit Watermark - ******************************************************************************/ - -/*! - * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW) - * - * Reset value: 0x00U - * - * This register provides the ability to set a programmable threshold for - * notification of needing additional transmit data. This register may be read at any - * time but must be written only when C2[TE] is not set. Changing the value of the - * watermark will not clear the S1[TDRE] flag. - */ -typedef union _hw_uart_twfifo -{ - uint8_t U; - struct _hw_uart_twfifo_bitfields - { - uint8_t TXWATER : 8; /*!< [7:0] Transmit Watermark */ - } B; -} hw_uart_twfifo_t; - -/*! - * @name Constants and macros for entire UART_TWFIFO register - */ -/*@{*/ -#define HW_UART_TWFIFO_ADDR(x) ((x) + 0x13U) - -#define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x)) -#define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U) -#define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v)) -#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v))) -#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v))) -#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_TWFIFO bitfields - */ - -/*! - * @name Register UART_TWFIFO, field TXWATER[7:0] (RW) - * - * When the number of datawords in the transmit FIFO/buffer is equal to or less - * than the value in this register field, an interrupt via S1[TDRE] or a DMA - * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For - * proper operation, the value in TXWATER must be set to be less than the size of - * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE]. - */ -/*@{*/ -#define BP_UART_TWFIFO_TXWATER (0U) /*!< Bit position for UART_TWFIFO_TXWATER. */ -#define BM_UART_TWFIFO_TXWATER (0xFFU) /*!< Bit mask for UART_TWFIFO_TXWATER. */ -#define BS_UART_TWFIFO_TXWATER (8U) /*!< Bit field size in bits for UART_TWFIFO_TXWATER. */ - -/*! @brief Read current value of the UART_TWFIFO_TXWATER field. */ -#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U) - -/*! @brief Format value for bitfield UART_TWFIFO_TXWATER. */ -#define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER) - -/*! @brief Set the TXWATER field to a new value. */ -#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_TCFIFO - UART FIFO Transmit Count - ******************************************************************************/ - -/*! - * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO) - * - * Reset value: 0x00U - * - * This is a read only register that indicates how many datawords are currently - * in the transmit buffer/FIFO. It may be read at any time. - */ -typedef union _hw_uart_tcfifo -{ - uint8_t U; - struct _hw_uart_tcfifo_bitfields - { - uint8_t TXCOUNT : 8; /*!< [7:0] Transmit Counter */ - } B; -} hw_uart_tcfifo_t; - -/*! - * @name Constants and macros for entire UART_TCFIFO register - */ -/*@{*/ -#define HW_UART_TCFIFO_ADDR(x) ((x) + 0x14U) - -#define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x)) -#define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_TCFIFO bitfields - */ - -/*! - * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO) - * - * The value in this register indicates the number of datawords that are in the - * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the - * transmit shift register, it is not included in the count. This value may be used - * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the - * transmit FIFO/buffer. - */ -/*@{*/ -#define BP_UART_TCFIFO_TXCOUNT (0U) /*!< Bit position for UART_TCFIFO_TXCOUNT. */ -#define BM_UART_TCFIFO_TXCOUNT (0xFFU) /*!< Bit mask for UART_TCFIFO_TXCOUNT. */ -#define BS_UART_TCFIFO_TXCOUNT (8U) /*!< Bit field size in bits for UART_TCFIFO_TXCOUNT. */ - -/*! @brief Read current value of the UART_TCFIFO_TXCOUNT field. */ -#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U) -/*@}*/ - -/******************************************************************************* - * HW_UART_RWFIFO - UART FIFO Receive Watermark - ******************************************************************************/ - -/*! - * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW) - * - * Reset value: 0x01U - * - * This register provides the ability to set a programmable threshold for - * notification of the need to remove data from the receiver FIFO/buffer. This register - * may be read at any time but must be written only when C2[RE] is not asserted. - * Changing the value in this register will not clear S1[RDRF]. - */ -typedef union _hw_uart_rwfifo -{ - uint8_t U; - struct _hw_uart_rwfifo_bitfields - { - uint8_t RXWATER : 8; /*!< [7:0] Receive Watermark */ - } B; -} hw_uart_rwfifo_t; - -/*! - * @name Constants and macros for entire UART_RWFIFO register - */ -/*@{*/ -#define HW_UART_RWFIFO_ADDR(x) ((x) + 0x15U) - -#define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x)) -#define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U) -#define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v)) -#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v))) -#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v))) -#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_RWFIFO bitfields - */ - -/*! - * @name Register UART_RWFIFO, field RXWATER[7:0] (RW) - * - * When the number of datawords in the receive FIFO/buffer is equal to or - * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA - * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For - * proper operation, the value in RXWATER must be set to be less than the receive - * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be - * greater than 0. - */ -/*@{*/ -#define BP_UART_RWFIFO_RXWATER (0U) /*!< Bit position for UART_RWFIFO_RXWATER. */ -#define BM_UART_RWFIFO_RXWATER (0xFFU) /*!< Bit mask for UART_RWFIFO_RXWATER. */ -#define BS_UART_RWFIFO_RXWATER (8U) /*!< Bit field size in bits for UART_RWFIFO_RXWATER. */ - -/*! @brief Read current value of the UART_RWFIFO_RXWATER field. */ -#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U) - -/*! @brief Format value for bitfield UART_RWFIFO_RXWATER. */ -#define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER) - -/*! @brief Set the RXWATER field to a new value. */ -#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_RCFIFO - UART FIFO Receive Count - ******************************************************************************/ - -/*! - * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO) - * - * Reset value: 0x00U - * - * This is a read only register that indicates how many datawords are currently - * in the receive FIFO/buffer. It may be read at any time. - */ -typedef union _hw_uart_rcfifo -{ - uint8_t U; - struct _hw_uart_rcfifo_bitfields - { - uint8_t RXCOUNT : 8; /*!< [7:0] Receive Counter */ - } B; -} hw_uart_rcfifo_t; - -/*! - * @name Constants and macros for entire UART_RCFIFO register - */ -/*@{*/ -#define HW_UART_RCFIFO_ADDR(x) ((x) + 0x16U) - -#define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x)) -#define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U) -/*@}*/ - -/* - * Constants & macros for individual UART_RCFIFO bitfields - */ - -/*! - * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO) - * - * The value in this register indicates the number of datawords that are in the - * receive FIFO/buffer. If a dataword is being received, that is, in the receive - * shift register, it is not included in the count. This value may be used in - * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the - * receive FIFO/buffer. - */ -/*@{*/ -#define BP_UART_RCFIFO_RXCOUNT (0U) /*!< Bit position for UART_RCFIFO_RXCOUNT. */ -#define BM_UART_RCFIFO_RXCOUNT (0xFFU) /*!< Bit mask for UART_RCFIFO_RXCOUNT. */ -#define BS_UART_RCFIFO_RXCOUNT (8U) /*!< Bit field size in bits for UART_RCFIFO_RXCOUNT. */ - -/*! @brief Read current value of the UART_RCFIFO_RXCOUNT field. */ -#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U) -/*@}*/ - -/******************************************************************************* - * HW_UART_C7816 - UART 7816 Control Register - ******************************************************************************/ - -/*! - * @brief HW_UART_C7816 - UART 7816 Control Register (RW) - * - * Reset value: 0x00U - * - * The C7816 register is the primary control register for ISO-7816 specific - * functionality. This register is specific to 7816 functionality and the values in - * this register have no effect on UART operation and should be ignored if - * ISO_7816E is not set/enabled. This register may be read at any time but values must - * be changed only when ISO_7816E is not set. - */ -typedef union _hw_uart_c7816 -{ - uint8_t U; - struct _hw_uart_c7816_bitfields - { - uint8_t ISO_7816E : 1; /*!< [0] ISO-7816 Functionality Enabled */ - uint8_t TTYPE : 1; /*!< [1] Transfer Type */ - uint8_t INIT : 1; /*!< [2] Detect Initial Character */ - uint8_t ANACK : 1; /*!< [3] Generate NACK on Error */ - uint8_t ONACK : 1; /*!< [4] Generate NACK on Overflow */ - uint8_t RESERVED0 : 3; /*!< [7:5] */ - } B; -} hw_uart_c7816_t; - -/*! - * @name Constants and macros for entire UART_C7816 register - */ -/*@{*/ -#define HW_UART_C7816_ADDR(x) ((x) + 0x18U) - -#define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x)) -#define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U) -#define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v)) -#define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v))) -#define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v))) -#define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_C7816 bitfields - */ - -/*! - * @name Register UART_C7816, field ISO_7816E[0] (RW) - * - * Indicates that the UART is operating according to the ISO-7816 protocol. This - * field must be modified only when no transmit or receive is occurring. If this - * field is changed during a data transfer, the data being transmitted or - * received may be transferred incorrectly. - * - * Values: - * - 0 - ISO-7816 functionality is turned off/not enabled. - * - 1 - ISO-7816 functionality is turned on/enabled. - */ -/*@{*/ -#define BP_UART_C7816_ISO_7816E (0U) /*!< Bit position for UART_C7816_ISO_7816E. */ -#define BM_UART_C7816_ISO_7816E (0x01U) /*!< Bit mask for UART_C7816_ISO_7816E. */ -#define BS_UART_C7816_ISO_7816E (1U) /*!< Bit field size in bits for UART_C7816_ISO_7816E. */ - -/*! @brief Read current value of the UART_C7816_ISO_7816E field. */ -#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E)) - -/*! @brief Format value for bitfield UART_C7816_ISO_7816E. */ -#define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E) - -/*! @brief Set the ISO_7816E field to a new value. */ -#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field TTYPE[1] (RW) - * - * Indicates the transfer protocol being used. See ISO-7816 / smartcard support - * for more details. - * - * Values: - * - 0 - T = 0 per the ISO-7816 specification. - * - 1 - T = 1 per the ISO-7816 specification. - */ -/*@{*/ -#define BP_UART_C7816_TTYPE (1U) /*!< Bit position for UART_C7816_TTYPE. */ -#define BM_UART_C7816_TTYPE (0x02U) /*!< Bit mask for UART_C7816_TTYPE. */ -#define BS_UART_C7816_TTYPE (1U) /*!< Bit field size in bits for UART_C7816_TTYPE. */ - -/*! @brief Read current value of the UART_C7816_TTYPE field. */ -#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE)) - -/*! @brief Format value for bitfield UART_C7816_TTYPE. */ -#define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE) - -/*! @brief Set the TTYPE field to a new value. */ -#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field INIT[2] (RW) - * - * When this field is set, all received characters are searched for a valid - * initial character. If an invalid initial character is identified, and ANACK is - * set, a NACK is sent. All received data is discarded and error flags blocked - * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV]) - * until a valid initial character is detected. Upon detecting a valid initial - * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are - * automatically updated to reflect the initial character that was received. The - * actual INIT data value is not stored in the receive buffer. Additionally, upon - * detection of a valid initial character, IS7816[INITD] is set and an interrupt - * issued as programmed by IE7816[INITDE]. When a valid initial character is - * detected, INIT is automatically cleared. This Initial Character Detect feature is - * supported only in T = 0 protocol mode. - * - * Values: - * - 0 - Normal operating mode. Receiver does not seek to identify initial - * character. - * - 1 - Receiver searches for initial character. - */ -/*@{*/ -#define BP_UART_C7816_INIT (2U) /*!< Bit position for UART_C7816_INIT. */ -#define BM_UART_C7816_INIT (0x04U) /*!< Bit mask for UART_C7816_INIT. */ -#define BS_UART_C7816_INIT (1U) /*!< Bit field size in bits for UART_C7816_INIT. */ - -/*! @brief Read current value of the UART_C7816_INIT field. */ -#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT)) - -/*! @brief Format value for bitfield UART_C7816_INIT. */ -#define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT) - -/*! @brief Set the INIT field to a new value. */ -#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field ANACK[3] (RW) - * - * When this field is set, the receiver automatically generates a NACK response - * if a parity error occurs or if INIT is set and an invalid initial character is - * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART - * attempts to retransmit the data indefinitely. To stop retransmission attempts, - * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again. - * - * Values: - * - 0 - No NACK is automatically generated. - * - 1 - A NACK is automatically generated if a parity error is detected or if - * an invalid initial character is detected. - */ -/*@{*/ -#define BP_UART_C7816_ANACK (3U) /*!< Bit position for UART_C7816_ANACK. */ -#define BM_UART_C7816_ANACK (0x08U) /*!< Bit mask for UART_C7816_ANACK. */ -#define BS_UART_C7816_ANACK (1U) /*!< Bit field size in bits for UART_C7816_ANACK. */ - -/*! @brief Read current value of the UART_C7816_ANACK field. */ -#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK)) - -/*! @brief Format value for bitfield UART_C7816_ANACK. */ -#define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK) - -/*! @brief Set the ANACK field to a new value. */ -#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v)) -/*@}*/ - -/*! - * @name Register UART_C7816, field ONACK[4] (RW) - * - * When this field is set, the receiver automatically generates a NACK response - * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems, - * this results in the transmitter resending the packet that overflowed until the - * retransmit threshold for that transmitter is reached. A NACK is generated only - * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK - * considerations - * - * Values: - * - 0 - The received data does not generate a NACK when the receipt of the data - * results in an overflow event. - * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a - * received character. - */ -/*@{*/ -#define BP_UART_C7816_ONACK (4U) /*!< Bit position for UART_C7816_ONACK. */ -#define BM_UART_C7816_ONACK (0x10U) /*!< Bit mask for UART_C7816_ONACK. */ -#define BS_UART_C7816_ONACK (1U) /*!< Bit field size in bits for UART_C7816_ONACK. */ - -/*! @brief Read current value of the UART_C7816_ONACK field. */ -#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK)) - -/*! @brief Format value for bitfield UART_C7816_ONACK. */ -#define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK) - -/*! @brief Set the ONACK field to a new value. */ -#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_IE7816 - UART 7816 Interrupt Enable Register - ******************************************************************************/ - -/*! - * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW) - * - * Reset value: 0x00U - * - * The IE7816 register controls which flags result in an interrupt being issued. - * This register is specific to 7816 functionality, the corresponding flags that - * drive the interrupts are not asserted when 7816E is not set/enabled. However, - * these flags may remain set if they are asserted while 7816E was set and not - * subsequently cleared. This register may be read or written to at any time. - */ -typedef union _hw_uart_ie7816 -{ - uint8_t U; - struct _hw_uart_ie7816_bitfields - { - uint8_t RXTE : 1; /*!< [0] Receive Threshold Exceeded Interrupt - * Enable */ - uint8_t TXTE : 1; /*!< [1] Transmit Threshold Exceeded Interrupt - * Enable */ - uint8_t GTVE : 1; /*!< [2] Guard Timer Violated Interrupt Enable */ - uint8_t RESERVED0 : 1; /*!< [3] */ - uint8_t INITDE : 1; /*!< [4] Initial Character Detected Interrupt - * Enable */ - uint8_t BWTE : 1; /*!< [5] Block Wait Timer Interrupt Enable */ - uint8_t CWTE : 1; /*!< [6] Character Wait Timer Interrupt Enable */ - uint8_t WTE : 1; /*!< [7] Wait Timer Interrupt Enable */ - } B; -} hw_uart_ie7816_t; - -/*! - * @name Constants and macros for entire UART_IE7816 register - */ -/*@{*/ -#define HW_UART_IE7816_ADDR(x) ((x) + 0x19U) - -#define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x)) -#define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U) -#define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v)) -#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v))) -#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v))) -#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_IE7816 bitfields - */ - -/*! - * @name Register UART_IE7816, field RXTE[0] (RW) - * - * Values: - * - 0 - The assertion of IS7816[RXT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_RXTE (0U) /*!< Bit position for UART_IE7816_RXTE. */ -#define BM_UART_IE7816_RXTE (0x01U) /*!< Bit mask for UART_IE7816_RXTE. */ -#define BS_UART_IE7816_RXTE (1U) /*!< Bit field size in bits for UART_IE7816_RXTE. */ - -/*! @brief Read current value of the UART_IE7816_RXTE field. */ -#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE)) - -/*! @brief Format value for bitfield UART_IE7816_RXTE. */ -#define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE) - -/*! @brief Set the RXTE field to a new value. */ -#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field TXTE[1] (RW) - * - * Values: - * - 0 - The assertion of IS7816[TXT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_TXTE (1U) /*!< Bit position for UART_IE7816_TXTE. */ -#define BM_UART_IE7816_TXTE (0x02U) /*!< Bit mask for UART_IE7816_TXTE. */ -#define BS_UART_IE7816_TXTE (1U) /*!< Bit field size in bits for UART_IE7816_TXTE. */ - -/*! @brief Read current value of the UART_IE7816_TXTE field. */ -#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE)) - -/*! @brief Format value for bitfield UART_IE7816_TXTE. */ -#define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE) - -/*! @brief Set the TXTE field to a new value. */ -#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field GTVE[2] (RW) - * - * Values: - * - 0 - The assertion of IS7816[GTV] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_GTVE (2U) /*!< Bit position for UART_IE7816_GTVE. */ -#define BM_UART_IE7816_GTVE (0x04U) /*!< Bit mask for UART_IE7816_GTVE. */ -#define BS_UART_IE7816_GTVE (1U) /*!< Bit field size in bits for UART_IE7816_GTVE. */ - -/*! @brief Read current value of the UART_IE7816_GTVE field. */ -#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE)) - -/*! @brief Format value for bitfield UART_IE7816_GTVE. */ -#define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE) - -/*! @brief Set the GTVE field to a new value. */ -#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field INITDE[4] (RW) - * - * Values: - * - 0 - The assertion of IS7816[INITD] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[INITD] results in the generation of an - * interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_INITDE (4U) /*!< Bit position for UART_IE7816_INITDE. */ -#define BM_UART_IE7816_INITDE (0x10U) /*!< Bit mask for UART_IE7816_INITDE. */ -#define BS_UART_IE7816_INITDE (1U) /*!< Bit field size in bits for UART_IE7816_INITDE. */ - -/*! @brief Read current value of the UART_IE7816_INITDE field. */ -#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE)) - -/*! @brief Format value for bitfield UART_IE7816_INITDE. */ -#define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE) - -/*! @brief Set the INITDE field to a new value. */ -#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field BWTE[5] (RW) - * - * Values: - * - 0 - The assertion of IS7816[BWT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_BWTE (5U) /*!< Bit position for UART_IE7816_BWTE. */ -#define BM_UART_IE7816_BWTE (0x20U) /*!< Bit mask for UART_IE7816_BWTE. */ -#define BS_UART_IE7816_BWTE (1U) /*!< Bit field size in bits for UART_IE7816_BWTE. */ - -/*! @brief Read current value of the UART_IE7816_BWTE field. */ -#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE)) - -/*! @brief Format value for bitfield UART_IE7816_BWTE. */ -#define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE) - -/*! @brief Set the BWTE field to a new value. */ -#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field CWTE[6] (RW) - * - * Values: - * - 0 - The assertion of IS7816[CWT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_CWTE (6U) /*!< Bit position for UART_IE7816_CWTE. */ -#define BM_UART_IE7816_CWTE (0x40U) /*!< Bit mask for UART_IE7816_CWTE. */ -#define BS_UART_IE7816_CWTE (1U) /*!< Bit field size in bits for UART_IE7816_CWTE. */ - -/*! @brief Read current value of the UART_IE7816_CWTE field. */ -#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE)) - -/*! @brief Format value for bitfield UART_IE7816_CWTE. */ -#define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE) - -/*! @brief Set the CWTE field to a new value. */ -#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v)) -/*@}*/ - -/*! - * @name Register UART_IE7816, field WTE[7] (RW) - * - * Values: - * - 0 - The assertion of IS7816[WT] does not result in the generation of an - * interrupt. - * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt. - */ -/*@{*/ -#define BP_UART_IE7816_WTE (7U) /*!< Bit position for UART_IE7816_WTE. */ -#define BM_UART_IE7816_WTE (0x80U) /*!< Bit mask for UART_IE7816_WTE. */ -#define BS_UART_IE7816_WTE (1U) /*!< Bit field size in bits for UART_IE7816_WTE. */ - -/*! @brief Read current value of the UART_IE7816_WTE field. */ -#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE)) - -/*! @brief Format value for bitfield UART_IE7816_WTE. */ -#define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE) - -/*! @brief Set the WTE field to a new value. */ -#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_IS7816 - UART 7816 Interrupt Status Register - ******************************************************************************/ - -/*! - * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW) - * - * Reset value: 0x00U - * - * The IS7816 register provides a mechanism to read and clear the interrupt - * flags. All flags/interrupts are cleared by writing a 1 to the field location. - * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only - * the flag condition that occurred since the last time the bit was cleared, not - * that the condition currently exists. The status flags are set regardless of - * whether the corresponding field in the IE7816 is set or cleared. The IE7816 - * controls only if an interrupt is issued to the host processor. This register is - * specific to 7816 functionality and the values in this register have no affect on - * UART operation and should be ignored if 7816E is not set/enabled. This - * register may be read or written at anytime. - */ -typedef union _hw_uart_is7816 -{ - uint8_t U; - struct _hw_uart_is7816_bitfields - { - uint8_t RXT : 1; /*!< [0] Receive Threshold Exceeded Interrupt */ - uint8_t TXT : 1; /*!< [1] Transmit Threshold Exceeded Interrupt */ - uint8_t GTV : 1; /*!< [2] Guard Timer Violated Interrupt */ - uint8_t RESERVED0 : 1; /*!< [3] */ - uint8_t INITD : 1; /*!< [4] Initial Character Detected Interrupt */ - uint8_t BWT : 1; /*!< [5] Block Wait Timer Interrupt */ - uint8_t CWT : 1; /*!< [6] Character Wait Timer Interrupt */ - uint8_t WT : 1; /*!< [7] Wait Timer Interrupt */ - } B; -} hw_uart_is7816_t; - -/*! - * @name Constants and macros for entire UART_IS7816 register - */ -/*@{*/ -#define HW_UART_IS7816_ADDR(x) ((x) + 0x1AU) - -#define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x)) -#define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U) -#define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v)) -#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v))) -#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v))) -#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_IS7816 bitfields - */ - -/*! - * @name Register UART_IS7816, field RXT[0] (W1C) - * - * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS - * generated in response to parity errors on received data. This flag requires ANACK - * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0. - * Clearing this field also resets the counter keeping track of consecutive NACKS. The - * UART will continue to attempt to receive data regardless of whether this flag - * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1, - * or packet is received without needing to issue a NACK, the internal NACK - * detection counter is cleared and the count restarts from zero on the next - * transmitted NACK. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - The number of consecutive NACKS generated as a result of parity errors - * and buffer overruns is less than or equal to the value in - * ET7816[RXTHRESHOLD]. - * - 1 - The number of consecutive NACKS generated as a result of parity errors - * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. - */ -/*@{*/ -#define BP_UART_IS7816_RXT (0U) /*!< Bit position for UART_IS7816_RXT. */ -#define BM_UART_IS7816_RXT (0x01U) /*!< Bit mask for UART_IS7816_RXT. */ -#define BS_UART_IS7816_RXT (1U) /*!< Bit field size in bits for UART_IS7816_RXT. */ - -/*! @brief Read current value of the UART_IS7816_RXT field. */ -#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT)) - -/*! @brief Format value for bitfield UART_IS7816_RXT. */ -#define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT) - -/*! @brief Set the RXT field to a new value. */ -#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field TXT[1] (W1C) - * - * Indicates that the transmit NACK threshold has been exceeded as indicated by - * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART - * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If - * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is - * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the - * internal NACK detection counter is cleared and the count restarts from zero on - * the next received NACK. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - The number of retries and corresponding NACKS does not exceed the value - * in ET7816[TXTHRESHOLD]. - * - 1 - The number of retries and corresponding NACKS exceeds the value in - * ET7816[TXTHRESHOLD]. - */ -/*@{*/ -#define BP_UART_IS7816_TXT (1U) /*!< Bit position for UART_IS7816_TXT. */ -#define BM_UART_IS7816_TXT (0x02U) /*!< Bit mask for UART_IS7816_TXT. */ -#define BS_UART_IS7816_TXT (1U) /*!< Bit field size in bits for UART_IS7816_TXT. */ - -/*! @brief Read current value of the UART_IS7816_TXT field. */ -#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT)) - -/*! @brief Format value for bitfield UART_IS7816_TXT. */ -#define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT) - -/*! @brief Set the TXT field to a new value. */ -#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field GTV[2] (W1C) - * - * Indicates that one or more of the character guard time, block guard time, or - * guard time are violated. This interrupt is cleared by writing 1. - * - * Values: - * - 0 - A guard time (GT, CGT, or BGT) has not been violated. - * - 1 - A guard time (GT, CGT, or BGT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_GTV (2U) /*!< Bit position for UART_IS7816_GTV. */ -#define BM_UART_IS7816_GTV (0x04U) /*!< Bit mask for UART_IS7816_GTV. */ -#define BS_UART_IS7816_GTV (1U) /*!< Bit field size in bits for UART_IS7816_GTV. */ - -/*! @brief Read current value of the UART_IS7816_GTV field. */ -#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV)) - -/*! @brief Format value for bitfield UART_IS7816_GTV. */ -#define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV) - -/*! @brief Set the GTV field to a new value. */ -#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field INITD[4] (W1C) - * - * Indicates that a valid initial character is received. This interrupt is - * cleared by writing 1. - * - * Values: - * - 0 - A valid initial character has not been received. - * - 1 - A valid initial character has been received. - */ -/*@{*/ -#define BP_UART_IS7816_INITD (4U) /*!< Bit position for UART_IS7816_INITD. */ -#define BM_UART_IS7816_INITD (0x10U) /*!< Bit mask for UART_IS7816_INITD. */ -#define BS_UART_IS7816_INITD (1U) /*!< Bit field size in bits for UART_IS7816_INITD. */ - -/*! @brief Read current value of the UART_IS7816_INITD field. */ -#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD)) - -/*! @brief Format value for bitfield UART_IS7816_INITD. */ -#define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD) - -/*! @brief Set the INITD field to a new value. */ -#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field BWT[5] (W1C) - * - * Indicates that the block wait time, the time between the leading edge of - * first received character of a block and the leading edge of the last character the - * previously transmitted block, has exceeded the programmed value. This flag - * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1. - * - * Values: - * - 0 - Block wait time (BWT) has not been violated. - * - 1 - Block wait time (BWT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_BWT (5U) /*!< Bit position for UART_IS7816_BWT. */ -#define BM_UART_IS7816_BWT (0x20U) /*!< Bit mask for UART_IS7816_BWT. */ -#define BS_UART_IS7816_BWT (1U) /*!< Bit field size in bits for UART_IS7816_BWT. */ - -/*! @brief Read current value of the UART_IS7816_BWT field. */ -#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT)) - -/*! @brief Format value for bitfield UART_IS7816_BWT. */ -#define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT) - -/*! @brief Set the BWT field to a new value. */ -#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field CWT[6] (W1C) - * - * Indicates that the character wait time, the time between the leading edges of - * two consecutive characters in a block, has exceeded the programmed value. - * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by - * writing 1. - * - * Values: - * - 0 - Character wait time (CWT) has not been violated. - * - 1 - Character wait time (CWT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_CWT (6U) /*!< Bit position for UART_IS7816_CWT. */ -#define BM_UART_IS7816_CWT (0x40U) /*!< Bit mask for UART_IS7816_CWT. */ -#define BS_UART_IS7816_CWT (1U) /*!< Bit field size in bits for UART_IS7816_CWT. */ - -/*! @brief Read current value of the UART_IS7816_CWT field. */ -#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT)) - -/*! @brief Format value for bitfield UART_IS7816_CWT. */ -#define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT) - -/*! @brief Set the CWT field to a new value. */ -#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v)) -/*@}*/ - -/*! - * @name Register UART_IS7816, field WT[7] (W1C) - * - * Indicates that the wait time, the time between the leading edge of a - * character being transmitted and the leading edge of the next response character, has - * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0. - * This interrupt is cleared by writing 1. - * - * Values: - * - 0 - Wait time (WT) has not been violated. - * - 1 - Wait time (WT) has been violated. - */ -/*@{*/ -#define BP_UART_IS7816_WT (7U) /*!< Bit position for UART_IS7816_WT. */ -#define BM_UART_IS7816_WT (0x80U) /*!< Bit mask for UART_IS7816_WT. */ -#define BS_UART_IS7816_WT (1U) /*!< Bit field size in bits for UART_IS7816_WT. */ - -/*! @brief Read current value of the UART_IS7816_WT field. */ -#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT)) - -/*! @brief Format value for bitfield UART_IS7816_WT. */ -#define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT) - -/*! @brief Set the WT field to a new value. */ -#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WP7816T0 - UART 7816 Wait Parameter Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816T0 - UART 7816 Wait Parameter Register (RW) - * - * Reset value: 0x0AU - * - * The WP7816 register contains constants used in the generation of various wait - * timer counters. To save register space, this register is used differently - * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816t0 -{ - uint8_t U; - struct _hw_uart_wp7816t0_bitfields - { - uint8_t WI : 8; /*!< [7:0] Wait Time Integer (C7816[TTYPE] = 0) */ - } B; -} hw_uart_wp7816t0_t; - -/*! - * @name Constants and macros for entire UART_WP7816T0 register - */ -/*@{*/ -#define HW_UART_WP7816T0_ADDR(x) ((x) + 0x1BU) - -#define HW_UART_WP7816T0(x) (*(__IO hw_uart_wp7816t0_t *) HW_UART_WP7816T0_ADDR(x)) -#define HW_UART_WP7816T0_RD(x) (HW_UART_WP7816T0(x).U) -#define HW_UART_WP7816T0_WR(x, v) (HW_UART_WP7816T0(x).U = (v)) -#define HW_UART_WP7816T0_SET(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) | (v))) -#define HW_UART_WP7816T0_CLR(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) & ~(v))) -#define HW_UART_WP7816T0_TOG(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816T0 bitfields - */ - -/*! - * @name Register UART_WP7816T0, field WI[7:0] (RW) - * - * Used to calculate the value used for the WT counter. It represents a value - * between 1 and 255. The value of zero is not valid. This value is used only when - * C7816[TTYPE] = 0. See Wait time and guard time parameters. - */ -/*@{*/ -#define BP_UART_WP7816T0_WI (0U) /*!< Bit position for UART_WP7816T0_WI. */ -#define BM_UART_WP7816T0_WI (0xFFU) /*!< Bit mask for UART_WP7816T0_WI. */ -#define BS_UART_WP7816T0_WI (8U) /*!< Bit field size in bits for UART_WP7816T0_WI. */ - -/*! @brief Read current value of the UART_WP7816T0_WI field. */ -#define BR_UART_WP7816T0_WI(x) (HW_UART_WP7816T0(x).U) - -/*! @brief Format value for bitfield UART_WP7816T0_WI. */ -#define BF_UART_WP7816T0_WI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T0_WI) & BM_UART_WP7816T0_WI) - -/*! @brief Set the WI field to a new value. */ -#define BW_UART_WP7816T0_WI(x, v) (HW_UART_WP7816T0_WR(x, v)) -/*@}*/ -/******************************************************************************* - * HW_UART_WP7816T1 - UART 7816 Wait Parameter Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WP7816T1 - UART 7816 Wait Parameter Register (RW) - * - * Reset value: 0x0AU - * - * The WP7816 register contains constants used in the generation of various wait - * timer counters. To save register space, this register is used differently - * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wp7816t1 -{ - uint8_t U; - struct _hw_uart_wp7816t1_bitfields - { - uint8_t BWI : 4; /*!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1) - * */ - uint8_t CWI : 4; /*!< [7:4] Character Wait Time Integer (C7816[TTYPE] - * = 1) */ - } B; -} hw_uart_wp7816t1_t; - -/*! - * @name Constants and macros for entire UART_WP7816T1 register - */ -/*@{*/ -#define HW_UART_WP7816T1_ADDR(x) ((x) + 0x1BU) - -#define HW_UART_WP7816T1(x) (*(__IO hw_uart_wp7816t1_t *) HW_UART_WP7816T1_ADDR(x)) -#define HW_UART_WP7816T1_RD(x) (HW_UART_WP7816T1(x).U) -#define HW_UART_WP7816T1_WR(x, v) (HW_UART_WP7816T1(x).U = (v)) -#define HW_UART_WP7816T1_SET(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) | (v))) -#define HW_UART_WP7816T1_CLR(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) & ~(v))) -#define HW_UART_WP7816T1_TOG(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WP7816T1 bitfields - */ - -/*! - * @name Register UART_WP7816T1, field BWI[3:0] (RW) - * - * Used to calculate the value used for the BWT counter. It represent a value - * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time - * and guard time parameters . - */ -/*@{*/ -#define BP_UART_WP7816T1_BWI (0U) /*!< Bit position for UART_WP7816T1_BWI. */ -#define BM_UART_WP7816T1_BWI (0x0FU) /*!< Bit mask for UART_WP7816T1_BWI. */ -#define BS_UART_WP7816T1_BWI (4U) /*!< Bit field size in bits for UART_WP7816T1_BWI. */ - -/*! @brief Read current value of the UART_WP7816T1_BWI field. */ -#define BR_UART_WP7816T1_BWI(x) (HW_UART_WP7816T1(x).B.BWI) - -/*! @brief Format value for bitfield UART_WP7816T1_BWI. */ -#define BF_UART_WP7816T1_BWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_BWI) & BM_UART_WP7816T1_BWI) - -/*! @brief Set the BWI field to a new value. */ -#define BW_UART_WP7816T1_BWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_BWI) | BF_UART_WP7816T1_BWI(v))) -/*@}*/ - -/*! - * @name Register UART_WP7816T1, field CWI[7:4] (RW) - * - * Used to calculate the value used for the CWT counter. It represents a value - * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time - * and guard time parameters . - */ -/*@{*/ -#define BP_UART_WP7816T1_CWI (4U) /*!< Bit position for UART_WP7816T1_CWI. */ -#define BM_UART_WP7816T1_CWI (0xF0U) /*!< Bit mask for UART_WP7816T1_CWI. */ -#define BS_UART_WP7816T1_CWI (4U) /*!< Bit field size in bits for UART_WP7816T1_CWI. */ - -/*! @brief Read current value of the UART_WP7816T1_CWI field. */ -#define BR_UART_WP7816T1_CWI(x) (HW_UART_WP7816T1(x).B.CWI) - -/*! @brief Format value for bitfield UART_WP7816T1_CWI. */ -#define BF_UART_WP7816T1_CWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_CWI) & BM_UART_WP7816T1_CWI) - -/*! @brief Set the CWI field to a new value. */ -#define BW_UART_WP7816T1_CWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_CWI) | BF_UART_WP7816T1_CWI(v))) -/*@}*/ - -/******************************************************************************* - * HW_UART_WN7816 - UART 7816 Wait N Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW) - * - * Reset value: 0x00U - * - * The WN7816 register contains a parameter that is used in the calculation of - * the guard time counter. This register may be read at any time. This register - * must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wn7816 -{ - uint8_t U; - struct _hw_uart_wn7816_bitfields - { - uint8_t GTN : 8; /*!< [7:0] Guard Band N */ - } B; -} hw_uart_wn7816_t; - -/*! - * @name Constants and macros for entire UART_WN7816 register - */ -/*@{*/ -#define HW_UART_WN7816_ADDR(x) ((x) + 0x1CU) - -#define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x)) -#define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U) -#define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v)) -#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v))) -#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v))) -#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WN7816 bitfields - */ - -/*! - * @name Register UART_WN7816, field GTN[7:0] (RW) - * - * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The - * value represents an integer number between 0 and 255. See Wait time and guard - * time parameters . - */ -/*@{*/ -#define BP_UART_WN7816_GTN (0U) /*!< Bit position for UART_WN7816_GTN. */ -#define BM_UART_WN7816_GTN (0xFFU) /*!< Bit mask for UART_WN7816_GTN. */ -#define BS_UART_WN7816_GTN (8U) /*!< Bit field size in bits for UART_WN7816_GTN. */ - -/*! @brief Read current value of the UART_WN7816_GTN field. */ -#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U) - -/*! @brief Format value for bitfield UART_WN7816_GTN. */ -#define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN) - -/*! @brief Set the GTN field to a new value. */ -#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_WF7816 - UART 7816 Wait FD Register - ******************************************************************************/ - -/*! - * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW) - * - * Reset value: 0x01U - * - * The WF7816 contains parameters that are used in the generation of various - * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any - * time. This register must be written to only when C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_wf7816 -{ - uint8_t U; - struct _hw_uart_wf7816_bitfields - { - uint8_t GTFD : 8; /*!< [7:0] FD Multiplier */ - } B; -} hw_uart_wf7816_t; - -/*! - * @name Constants and macros for entire UART_WF7816 register - */ -/*@{*/ -#define HW_UART_WF7816_ADDR(x) ((x) + 0x1DU) - -#define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x)) -#define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U) -#define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v)) -#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v))) -#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v))) -#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_WF7816 bitfields - */ - -/*! - * @name Register UART_WF7816, field GTFD[7:0] (RW) - * - * Used as another multiplier in the calculation of WT and BWT. This value - * represents a number between 1 and 255. The value of 0 is invalid. This value is not - * used in baud rate generation. See Wait time and guard time parameters and - * Baud rate generation . - */ -/*@{*/ -#define BP_UART_WF7816_GTFD (0U) /*!< Bit position for UART_WF7816_GTFD. */ -#define BM_UART_WF7816_GTFD (0xFFU) /*!< Bit mask for UART_WF7816_GTFD. */ -#define BS_UART_WF7816_GTFD (8U) /*!< Bit field size in bits for UART_WF7816_GTFD. */ - -/*! @brief Read current value of the UART_WF7816_GTFD field. */ -#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U) - -/*! @brief Format value for bitfield UART_WF7816_GTFD. */ -#define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD) - -/*! @brief Set the GTFD field to a new value. */ -#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_UART_ET7816 - UART 7816 Error Threshold Register - ******************************************************************************/ - -/*! - * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW) - * - * Reset value: 0x00U - * - * The ET7816 register contains fields that determine the number of NACKs that - * must be received or transmitted before the host processor is notified. This - * register may be read at anytime. This register must be written to only when - * C7816[ISO_7816E] is not set. - */ -typedef union _hw_uart_et7816 -{ - uint8_t U; - struct _hw_uart_et7816_bitfields - { - uint8_t RXTHRESHOLD : 4; /*!< [3:0] Receive NACK Threshold */ - uint8_t TXTHRESHOLD : 4; /*!< [7:4] Transmit NACK Threshold */ - } B; -} hw_uart_et7816_t; - -/*! - * @name Constants and macros for entire UART_ET7816 register - */ -/*@{*/ -#define HW_UART_ET7816_ADDR(x) ((x) + 0x1EU) - -#define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x)) -#define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U) -#define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v)) -#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v))) -#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v))) -#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_ET7816 bitfields - */ - -/*! - * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW) - * - * The value written to this field indicates the maximum number of consecutive - * NACKs generated as a result of a parity error or receiver buffer overruns - * before the host processor is notified. After the counter exceeds that value in the - * field, the IS7816[RXT] is asserted. This field is meaningful only when - * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive - * NACKs that have been transmitted since the last successful reception. This - * counter saturates at 4'hF and does not wrap around. Regardless of the number of - * NACKs sent, the UART continues to receive valid packets indefinitely. For - * additional information, see IS7816[RXT] field description. - */ -/*@{*/ -#define BP_UART_ET7816_RXTHRESHOLD (0U) /*!< Bit position for UART_ET7816_RXTHRESHOLD. */ -#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /*!< Bit mask for UART_ET7816_RXTHRESHOLD. */ -#define BS_UART_ET7816_RXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. */ - -/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */ -#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD) - -/*! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. */ -#define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD) - -/*! @brief Set the RXTHRESHOLD field to a new value. */ -#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v))) -/*@}*/ - -/*! - * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW) - * - * The value written to this field indicates the maximum number of failed - * attempts (NACKs) a transmitted character can have before the host processor is - * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1. - * The value read from this field represents the number of consecutive NACKs - * that have been received since the last successful transmission. This counter - * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are - * received, the UART continues to retransmit indefinitely. This flag only - * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field - * description. - * - * Values: - * - 0 - TXT asserts on the first NACK that is received. - * - 1 - TXT asserts on the second NACK that is received. - */ -/*@{*/ -#define BP_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit position for UART_ET7816_TXTHRESHOLD. */ -#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /*!< Bit mask for UART_ET7816_TXTHRESHOLD. */ -#define BS_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. */ - -/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */ -#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD) - -/*! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. */ -#define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD) - -/*! @brief Set the TXTHRESHOLD field to a new value. */ -#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v))) -/*@}*/ - -/******************************************************************************* - * HW_UART_TL7816 - UART 7816 Transmit Length Register - ******************************************************************************/ - -/*! - * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW) - * - * Reset value: 0x00U - * - * The TL7816 register is used to indicate the number of characters contained in - * the block being transmitted. This register is used only when C7816[TTYPE] = - * 1. This register may be read at anytime. This register must be written only - * when C2[TE] is not enabled. - */ -typedef union _hw_uart_tl7816 -{ - uint8_t U; - struct _hw_uart_tl7816_bitfields - { - uint8_t TLEN : 8; /*!< [7:0] Transmit Length */ - } B; -} hw_uart_tl7816_t; - -/*! - * @name Constants and macros for entire UART_TL7816 register - */ -/*@{*/ -#define HW_UART_TL7816_ADDR(x) ((x) + 0x1FU) - -#define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x)) -#define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U) -#define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v)) -#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v))) -#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v))) -#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual UART_TL7816 bitfields - */ - -/*! - * @name Register UART_TL7816, field TLEN[7:0] (RW) - * - * This value plus four indicates the number of characters contained in the - * block being transmitted. This register is automatically decremented by 1 for each - * character in the information field portion of the block. Additionally, this - * register is automatically decremented by 1 for the first character of a CRC in - * the epilogue field. Therefore, this register must be programmed with the number - * of bytes in the data packet if an LRC is being transmitted, and the number of - * bytes + 1 if a CRC is being transmitted. This register is not decremented for - * characters that are assumed to be part of the Prologue field, that is, the - * first three characters transmitted in a block, or the LRC or last CRC character - * in the Epilogue field, that is, the last character transmitted. This field - * must be programed or adjusted only when C2[TE] is cleared. - */ -/*@{*/ -#define BP_UART_TL7816_TLEN (0U) /*!< Bit position for UART_TL7816_TLEN. */ -#define BM_UART_TL7816_TLEN (0xFFU) /*!< Bit mask for UART_TL7816_TLEN. */ -#define BS_UART_TL7816_TLEN (8U) /*!< Bit field size in bits for UART_TL7816_TLEN. */ - -/*! @brief Read current value of the UART_TL7816_TLEN field. */ -#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U) - -/*! @brief Format value for bitfield UART_TL7816_TLEN. */ -#define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN) - -/*! @brief Set the TLEN field to a new value. */ -#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v)) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_uart_t - module struct - ******************************************************************************/ -/*! - * @brief All UART module registers. - */ -#pragma pack(1) -typedef struct _hw_uart -{ - __IO hw_uart_bdh_t BDH; /*!< [0x0] UART Baud Rate Registers: High */ - __IO hw_uart_bdl_t BDL; /*!< [0x1] UART Baud Rate Registers: Low */ - __IO hw_uart_c1_t C1; /*!< [0x2] UART Control Register 1 */ - __IO hw_uart_c2_t C2; /*!< [0x3] UART Control Register 2 */ - __I hw_uart_s1_t S1; /*!< [0x4] UART Status Register 1 */ - __IO hw_uart_s2_t S2; /*!< [0x5] UART Status Register 2 */ - __IO hw_uart_c3_t C3; /*!< [0x6] UART Control Register 3 */ - __IO hw_uart_d_t D; /*!< [0x7] UART Data Register */ - __IO hw_uart_ma1_t MA1; /*!< [0x8] UART Match Address Registers 1 */ - __IO hw_uart_ma2_t MA2; /*!< [0x9] UART Match Address Registers 2 */ - __IO hw_uart_c4_t C4; /*!< [0xA] UART Control Register 4 */ - __IO hw_uart_c5_t C5; /*!< [0xB] UART Control Register 5 */ - __I hw_uart_ed_t ED; /*!< [0xC] UART Extended Data Register */ - __IO hw_uart_modem_t MODEM; /*!< [0xD] UART Modem Register */ - __IO hw_uart_ir_t IR; /*!< [0xE] UART Infrared Register */ - uint8_t _reserved0[1]; - __IO hw_uart_pfifo_t PFIFO; /*!< [0x10] UART FIFO Parameters */ - __IO hw_uart_cfifo_t CFIFO; /*!< [0x11] UART FIFO Control Register */ - __IO hw_uart_sfifo_t SFIFO; /*!< [0x12] UART FIFO Status Register */ - __IO hw_uart_twfifo_t TWFIFO; /*!< [0x13] UART FIFO Transmit Watermark */ - __I hw_uart_tcfifo_t TCFIFO; /*!< [0x14] UART FIFO Transmit Count */ - __IO hw_uart_rwfifo_t RWFIFO; /*!< [0x15] UART FIFO Receive Watermark */ - __I hw_uart_rcfifo_t RCFIFO; /*!< [0x16] UART FIFO Receive Count */ - uint8_t _reserved1[1]; - __IO hw_uart_c7816_t C7816; /*!< [0x18] UART 7816 Control Register */ - __IO hw_uart_ie7816_t IE7816; /*!< [0x19] UART 7816 Interrupt Enable Register */ - __IO hw_uart_is7816_t IS7816; /*!< [0x1A] UART 7816 Interrupt Status Register */ - union { - __IO hw_uart_wp7816t0_t WP7816T0; /*!< [0x1B] UART 7816 Wait Parameter Register */ - __IO hw_uart_wp7816t1_t WP7816T1; /*!< [0x1B] UART 7816 Wait Parameter Register */ - }; - __IO hw_uart_wn7816_t WN7816; /*!< [0x1C] UART 7816 Wait N Register */ - __IO hw_uart_wf7816_t WF7816; /*!< [0x1D] UART 7816 Wait FD Register */ - __IO hw_uart_et7816_t ET7816; /*!< [0x1E] UART 7816 Error Threshold Register */ - __IO hw_uart_tl7816_t TL7816; /*!< [0x1F] UART 7816 Transmit Length Register */ -} hw_uart_t; -#pragma pack() - -/*! @brief Macro to access all UART registers. */ -/*! @param x UART module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_UART(UART0_BASE). */ -#define HW_UART(x) (*(hw_uart_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_UART_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usb.h deleted file mode 100644 index e001d7b7eb7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usb.h +++ /dev/null @@ -1,3828 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_USB_REGISTERS_H__ -#define __HW_USB_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 USB - * - * Universal Serial Bus, OTG Capable Controller - * - * Registers defined in this header file: - * - HW_USB_PERID - Peripheral ID register - * - HW_USB_IDCOMP - Peripheral ID Complement register - * - HW_USB_REV - Peripheral Revision register - * - HW_USB_ADDINFO - Peripheral Additional Info register - * - HW_USB_OTGISTAT - OTG Interrupt Status register - * - HW_USB_OTGICR - OTG Interrupt Control register - * - HW_USB_OTGSTAT - OTG Status register - * - HW_USB_OTGCTL - OTG Control register - * - HW_USB_ISTAT - Interrupt Status register - * - HW_USB_INTEN - Interrupt Enable register - * - HW_USB_ERRSTAT - Error Interrupt Status register - * - HW_USB_ERREN - Error Interrupt Enable register - * - HW_USB_STAT - Status register - * - HW_USB_CTL - Control register - * - HW_USB_ADDR - Address register - * - HW_USB_BDTPAGE1 - BDT Page register 1 - * - HW_USB_FRMNUML - Frame Number register Low - * - HW_USB_FRMNUMH - Frame Number register High - * - HW_USB_TOKEN - Token register - * - HW_USB_SOFTHLD - SOF Threshold register - * - HW_USB_BDTPAGE2 - BDT Page Register 2 - * - HW_USB_BDTPAGE3 - BDT Page Register 3 - * - HW_USB_ENDPTn - Endpoint Control register - * - HW_USB_USBCTRL - USB Control register - * - HW_USB_OBSERVE - USB OTG Observe register - * - HW_USB_CONTROL - USB OTG Control register - * - HW_USB_USBTRC0 - USB Transceiver Control register 0 - * - HW_USB_USBFRMADJUST - Frame Adjust Register - * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control - * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register - * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status - * - * - hw_usb_t - Struct containing all module registers. - */ - -#define HW_USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */ - -/******************************************************************************* - * HW_USB_PERID - Peripheral ID register - ******************************************************************************/ - -/*! - * @brief HW_USB_PERID - Peripheral ID register (RO) - * - * Reset value: 0x04U - * - * Reads back the value of 0x04. This value is defined for the USB peripheral. - */ -typedef union _hw_usb_perid -{ - uint8_t U; - struct _hw_usb_perid_bitfields - { - uint8_t ID : 6; /*!< [5:0] Peripheral Identification */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_usb_perid_t; - -/*! - * @name Constants and macros for entire USB_PERID register - */ -/*@{*/ -#define HW_USB_PERID_ADDR(x) ((x) + 0x0U) - -#define HW_USB_PERID(x) (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR(x)) -#define HW_USB_PERID_RD(x) (HW_USB_PERID(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_PERID bitfields - */ - -/*! - * @name Register USB_PERID, field ID[5:0] (RO) - * - * This field always reads 0x4h. - */ -/*@{*/ -#define BP_USB_PERID_ID (0U) /*!< Bit position for USB_PERID_ID. */ -#define BM_USB_PERID_ID (0x3FU) /*!< Bit mask for USB_PERID_ID. */ -#define BS_USB_PERID_ID (6U) /*!< Bit field size in bits for USB_PERID_ID. */ - -/*! @brief Read current value of the USB_PERID_ID field. */ -#define BR_USB_PERID_ID(x) (HW_USB_PERID(x).B.ID) -/*@}*/ - -/******************************************************************************* - * HW_USB_IDCOMP - Peripheral ID Complement register - ******************************************************************************/ - -/*! - * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO) - * - * Reset value: 0xFBU - * - * Reads back the complement of the Peripheral ID register. For the USB - * peripheral, the value is 0xFB. - */ -typedef union _hw_usb_idcomp -{ - uint8_t U; - struct _hw_usb_idcomp_bitfields - { - uint8_t NID : 6; /*!< [5:0] */ - uint8_t RESERVED0 : 2; /*!< [7:6] */ - } B; -} hw_usb_idcomp_t; - -/*! - * @name Constants and macros for entire USB_IDCOMP register - */ -/*@{*/ -#define HW_USB_IDCOMP_ADDR(x) ((x) + 0x4U) - -#define HW_USB_IDCOMP(x) (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR(x)) -#define HW_USB_IDCOMP_RD(x) (HW_USB_IDCOMP(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_IDCOMP bitfields - */ - -/*! - * @name Register USB_IDCOMP, field NID[5:0] (RO) - * - * Ones' complement of PERID[ID]. bits. - */ -/*@{*/ -#define BP_USB_IDCOMP_NID (0U) /*!< Bit position for USB_IDCOMP_NID. */ -#define BM_USB_IDCOMP_NID (0x3FU) /*!< Bit mask for USB_IDCOMP_NID. */ -#define BS_USB_IDCOMP_NID (6U) /*!< Bit field size in bits for USB_IDCOMP_NID. */ - -/*! @brief Read current value of the USB_IDCOMP_NID field. */ -#define BR_USB_IDCOMP_NID(x) (HW_USB_IDCOMP(x).B.NID) -/*@}*/ - -/******************************************************************************* - * HW_USB_REV - Peripheral Revision register - ******************************************************************************/ - -/*! - * @brief HW_USB_REV - Peripheral Revision register (RO) - * - * Reset value: 0x33U - * - * Contains the revision number of the USB module. - */ -typedef union _hw_usb_rev -{ - uint8_t U; - struct _hw_usb_rev_bitfields - { - uint8_t REV : 8; /*!< [7:0] Revision */ - } B; -} hw_usb_rev_t; - -/*! - * @name Constants and macros for entire USB_REV register - */ -/*@{*/ -#define HW_USB_REV_ADDR(x) ((x) + 0x8U) - -#define HW_USB_REV(x) (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR(x)) -#define HW_USB_REV_RD(x) (HW_USB_REV(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_REV bitfields - */ - -/*! - * @name Register USB_REV, field REV[7:0] (RO) - * - * Indicates the revision number of the USB Core. - */ -/*@{*/ -#define BP_USB_REV_REV (0U) /*!< Bit position for USB_REV_REV. */ -#define BM_USB_REV_REV (0xFFU) /*!< Bit mask for USB_REV_REV. */ -#define BS_USB_REV_REV (8U) /*!< Bit field size in bits for USB_REV_REV. */ - -/*! @brief Read current value of the USB_REV_REV field. */ -#define BR_USB_REV_REV(x) (HW_USB_REV(x).U) -/*@}*/ - -/******************************************************************************* - * HW_USB_ADDINFO - Peripheral Additional Info register - ******************************************************************************/ - -/*! - * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO) - * - * Reset value: 0x01U - * - * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with - * the Host Enable bit. - */ -typedef union _hw_usb_addinfo -{ - uint8_t U; - struct _hw_usb_addinfo_bitfields - { - uint8_t IEHOST : 1; /*!< [0] */ - uint8_t RESERVED0 : 2; /*!< [2:1] */ - uint8_t IRQNUM : 5; /*!< [7:3] Assigned Interrupt Request Number */ - } B; -} hw_usb_addinfo_t; - -/*! - * @name Constants and macros for entire USB_ADDINFO register - */ -/*@{*/ -#define HW_USB_ADDINFO_ADDR(x) ((x) + 0xCU) - -#define HW_USB_ADDINFO(x) (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR(x)) -#define HW_USB_ADDINFO_RD(x) (HW_USB_ADDINFO(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_ADDINFO bitfields - */ - -/*! - * @name Register USB_ADDINFO, field IEHOST[0] (RO) - * - * This bit is set if host mode is enabled. - */ -/*@{*/ -#define BP_USB_ADDINFO_IEHOST (0U) /*!< Bit position for USB_ADDINFO_IEHOST. */ -#define BM_USB_ADDINFO_IEHOST (0x01U) /*!< Bit mask for USB_ADDINFO_IEHOST. */ -#define BS_USB_ADDINFO_IEHOST (1U) /*!< Bit field size in bits for USB_ADDINFO_IEHOST. */ - -/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */ -#define BR_USB_ADDINFO_IEHOST(x) (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR(x), BP_USB_ADDINFO_IEHOST)) -/*@}*/ - -/*! - * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO) - */ -/*@{*/ -#define BP_USB_ADDINFO_IRQNUM (3U) /*!< Bit position for USB_ADDINFO_IRQNUM. */ -#define BM_USB_ADDINFO_IRQNUM (0xF8U) /*!< Bit mask for USB_ADDINFO_IRQNUM. */ -#define BS_USB_ADDINFO_IRQNUM (5U) /*!< Bit field size in bits for USB_ADDINFO_IRQNUM. */ - -/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */ -#define BR_USB_ADDINFO_IRQNUM(x) (HW_USB_ADDINFO(x).B.IRQNUM) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGISTAT - OTG Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW) - * - * Reset value: 0x00U - * - * Records changes of the ID sense and VBUS signals. Software can read this - * register to determine the event that triggers an interrupt. Only bits that have - * changed since the last software read are set. Writing a one to a bit clears the - * associated interrupt. - */ -typedef union _hw_usb_otgistat -{ - uint8_t U; - struct _hw_usb_otgistat_bitfields - { - uint8_t AVBUSCHG : 1; /*!< [0] */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t B_SESS_CHG : 1; /*!< [2] */ - uint8_t SESSVLDCHG : 1; /*!< [3] */ - uint8_t RESERVED1 : 1; /*!< [4] */ - uint8_t LINE_STATE_CHG : 1; /*!< [5] */ - uint8_t ONEMSEC : 1; /*!< [6] */ - uint8_t IDCHG : 1; /*!< [7] */ - } B; -} hw_usb_otgistat_t; - -/*! - * @name Constants and macros for entire USB_OTGISTAT register - */ -/*@{*/ -#define HW_USB_OTGISTAT_ADDR(x) ((x) + 0x10U) - -#define HW_USB_OTGISTAT(x) (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR(x)) -#define HW_USB_OTGISTAT_RD(x) (HW_USB_OTGISTAT(x).U) -#define HW_USB_OTGISTAT_WR(x, v) (HW_USB_OTGISTAT(x).U = (v)) -#define HW_USB_OTGISTAT_SET(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) | (v))) -#define HW_USB_OTGISTAT_CLR(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) & ~(v))) -#define HW_USB_OTGISTAT_TOG(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGISTAT bitfields - */ - -/*! - * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW) - * - * This bit is set when a change in VBUS is detected on an A device. - */ -/*@{*/ -#define BP_USB_OTGISTAT_AVBUSCHG (0U) /*!< Bit position for USB_OTGISTAT_AVBUSCHG. */ -#define BM_USB_OTGISTAT_AVBUSCHG (0x01U) /*!< Bit mask for USB_OTGISTAT_AVBUSCHG. */ -#define BS_USB_OTGISTAT_AVBUSCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */ -#define BR_USB_OTGISTAT_AVBUSCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG. */ -#define BF_USB_OTGISTAT_AVBUSCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_AVBUSCHG) & BM_USB_OTGISTAT_AVBUSCHG) - -/*! @brief Set the AVBUSCHG field to a new value. */ -#define BW_USB_OTGISTAT_AVBUSCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW) - * - * This bit is set when a change in VBUS is detected on a B device. - */ -/*@{*/ -#define BP_USB_OTGISTAT_B_SESS_CHG (2U) /*!< Bit position for USB_OTGISTAT_B_SESS_CHG. */ -#define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) /*!< Bit mask for USB_OTGISTAT_B_SESS_CHG. */ -#define BS_USB_OTGISTAT_B_SESS_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */ -#define BR_USB_OTGISTAT_B_SESS_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG. */ -#define BF_USB_OTGISTAT_B_SESS_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_B_SESS_CHG) & BM_USB_OTGISTAT_B_SESS_CHG) - -/*! @brief Set the B_SESS_CHG field to a new value. */ -#define BW_USB_OTGISTAT_B_SESS_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW) - * - * This bit is set when a change in VBUS is detected indicating a session valid - * or a session no longer valid. - */ -/*@{*/ -#define BP_USB_OTGISTAT_SESSVLDCHG (3U) /*!< Bit position for USB_OTGISTAT_SESSVLDCHG. */ -#define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) /*!< Bit mask for USB_OTGISTAT_SESSVLDCHG. */ -#define BS_USB_OTGISTAT_SESSVLDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */ -#define BR_USB_OTGISTAT_SESSVLDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG. */ -#define BF_USB_OTGISTAT_SESSVLDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_SESSVLDCHG) & BM_USB_OTGISTAT_SESSVLDCHG) - -/*! @brief Set the SESSVLDCHG field to a new value. */ -#define BW_USB_OTGISTAT_SESSVLDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW) - * - * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) - * are stable without change for 1 millisecond, and the value of the line state - * is different from the last time when the line state was stable. It is set on - * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state. - * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt - * can be used in detecting Reset, Resume, Connect, and Data Line Pulse - * signaling. - */ -/*@{*/ -#define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) /*!< Bit position for USB_OTGISTAT_LINE_STATE_CHG. */ -#define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) /*!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG. */ -#define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */ -#define BR_USB_OTGISTAT_LINE_STATE_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG. */ -#define BF_USB_OTGISTAT_LINE_STATE_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_LINE_STATE_CHG) & BM_USB_OTGISTAT_LINE_STATE_CHG) - -/*! @brief Set the LINE_STATE_CHG field to a new value. */ -#define BW_USB_OTGISTAT_LINE_STATE_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW) - * - * This bit is set when the 1 millisecond timer expires. This bit stays asserted - * until cleared by software. The interrupt must be serviced every millisecond - * to avoid losing 1msec counts. - */ -/*@{*/ -#define BP_USB_OTGISTAT_ONEMSEC (6U) /*!< Bit position for USB_OTGISTAT_ONEMSEC. */ -#define BM_USB_OTGISTAT_ONEMSEC (0x40U) /*!< Bit mask for USB_OTGISTAT_ONEMSEC. */ -#define BS_USB_OTGISTAT_ONEMSEC (1U) /*!< Bit field size in bits for USB_OTGISTAT_ONEMSEC. */ - -/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */ -#define BR_USB_OTGISTAT_ONEMSEC(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC)) - -/*! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC. */ -#define BF_USB_OTGISTAT_ONEMSEC(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_ONEMSEC) & BM_USB_OTGISTAT_ONEMSEC) - -/*! @brief Set the ONEMSEC field to a new value. */ -#define BW_USB_OTGISTAT_ONEMSEC(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGISTAT, field IDCHG[7] (RW) - * - * This bit is set when a change in the ID Signal from the USB connector is - * sensed. - */ -/*@{*/ -#define BP_USB_OTGISTAT_IDCHG (7U) /*!< Bit position for USB_OTGISTAT_IDCHG. */ -#define BM_USB_OTGISTAT_IDCHG (0x80U) /*!< Bit mask for USB_OTGISTAT_IDCHG. */ -#define BS_USB_OTGISTAT_IDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_IDCHG. */ - -/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */ -#define BR_USB_OTGISTAT_IDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG)) - -/*! @brief Format value for bitfield USB_OTGISTAT_IDCHG. */ -#define BF_USB_OTGISTAT_IDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_IDCHG) & BM_USB_OTGISTAT_IDCHG) - -/*! @brief Set the IDCHG field to a new value. */ -#define BW_USB_OTGISTAT_IDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGICR - OTG Interrupt Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW) - * - * Reset value: 0x00U - * - * Enables the corresponding interrupt status bits defined in the OTG Interrupt - * Status Register. - */ -typedef union _hw_usb_otgicr -{ - uint8_t U; - struct _hw_usb_otgicr_bitfields - { - uint8_t AVBUSEN : 1; /*!< [0] A VBUS Valid Interrupt Enable */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t BSESSEN : 1; /*!< [2] B Session END Interrupt Enable */ - uint8_t SESSVLDEN : 1; /*!< [3] Session Valid Interrupt Enable */ - uint8_t RESERVED1 : 1; /*!< [4] */ - uint8_t LINESTATEEN : 1; /*!< [5] Line State Change Interrupt Enable - * */ - uint8_t ONEMSECEN : 1; /*!< [6] One Millisecond Interrupt Enable */ - uint8_t IDEN : 1; /*!< [7] ID Interrupt Enable */ - } B; -} hw_usb_otgicr_t; - -/*! - * @name Constants and macros for entire USB_OTGICR register - */ -/*@{*/ -#define HW_USB_OTGICR_ADDR(x) ((x) + 0x14U) - -#define HW_USB_OTGICR(x) (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR(x)) -#define HW_USB_OTGICR_RD(x) (HW_USB_OTGICR(x).U) -#define HW_USB_OTGICR_WR(x, v) (HW_USB_OTGICR(x).U = (v)) -#define HW_USB_OTGICR_SET(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) | (v))) -#define HW_USB_OTGICR_CLR(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) & ~(v))) -#define HW_USB_OTGICR_TOG(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGICR bitfields - */ - -/*! - * @name Register USB_OTGICR, field AVBUSEN[0] (RW) - * - * Values: - * - 0 - Disables the AVBUSCHG interrupt. - * - 1 - Enables the AVBUSCHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_AVBUSEN (0U) /*!< Bit position for USB_OTGICR_AVBUSEN. */ -#define BM_USB_OTGICR_AVBUSEN (0x01U) /*!< Bit mask for USB_OTGICR_AVBUSEN. */ -#define BS_USB_OTGICR_AVBUSEN (1U) /*!< Bit field size in bits for USB_OTGICR_AVBUSEN. */ - -/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */ -#define BR_USB_OTGICR_AVBUSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN)) - -/*! @brief Format value for bitfield USB_OTGICR_AVBUSEN. */ -#define BF_USB_OTGICR_AVBUSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_AVBUSEN) & BM_USB_OTGICR_AVBUSEN) - -/*! @brief Set the AVBUSEN field to a new value. */ -#define BW_USB_OTGICR_AVBUSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field BSESSEN[2] (RW) - * - * Values: - * - 0 - Disables the B_SESS_CHG interrupt. - * - 1 - Enables the B_SESS_CHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_BSESSEN (2U) /*!< Bit position for USB_OTGICR_BSESSEN. */ -#define BM_USB_OTGICR_BSESSEN (0x04U) /*!< Bit mask for USB_OTGICR_BSESSEN. */ -#define BS_USB_OTGICR_BSESSEN (1U) /*!< Bit field size in bits for USB_OTGICR_BSESSEN. */ - -/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */ -#define BR_USB_OTGICR_BSESSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN)) - -/*! @brief Format value for bitfield USB_OTGICR_BSESSEN. */ -#define BF_USB_OTGICR_BSESSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_BSESSEN) & BM_USB_OTGICR_BSESSEN) - -/*! @brief Set the BSESSEN field to a new value. */ -#define BW_USB_OTGICR_BSESSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field SESSVLDEN[3] (RW) - * - * Values: - * - 0 - Disables the SESSVLDCHG interrupt. - * - 1 - Enables the SESSVLDCHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_SESSVLDEN (3U) /*!< Bit position for USB_OTGICR_SESSVLDEN. */ -#define BM_USB_OTGICR_SESSVLDEN (0x08U) /*!< Bit mask for USB_OTGICR_SESSVLDEN. */ -#define BS_USB_OTGICR_SESSVLDEN (1U) /*!< Bit field size in bits for USB_OTGICR_SESSVLDEN. */ - -/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */ -#define BR_USB_OTGICR_SESSVLDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN)) - -/*! @brief Format value for bitfield USB_OTGICR_SESSVLDEN. */ -#define BF_USB_OTGICR_SESSVLDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_SESSVLDEN) & BM_USB_OTGICR_SESSVLDEN) - -/*! @brief Set the SESSVLDEN field to a new value. */ -#define BW_USB_OTGICR_SESSVLDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field LINESTATEEN[5] (RW) - * - * Values: - * - 0 - Disables the LINE_STAT_CHG interrupt. - * - 1 - Enables the LINE_STAT_CHG interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_LINESTATEEN (5U) /*!< Bit position for USB_OTGICR_LINESTATEEN. */ -#define BM_USB_OTGICR_LINESTATEEN (0x20U) /*!< Bit mask for USB_OTGICR_LINESTATEEN. */ -#define BS_USB_OTGICR_LINESTATEEN (1U) /*!< Bit field size in bits for USB_OTGICR_LINESTATEEN. */ - -/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */ -#define BR_USB_OTGICR_LINESTATEEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN)) - -/*! @brief Format value for bitfield USB_OTGICR_LINESTATEEN. */ -#define BF_USB_OTGICR_LINESTATEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_LINESTATEEN) & BM_USB_OTGICR_LINESTATEEN) - -/*! @brief Set the LINESTATEEN field to a new value. */ -#define BW_USB_OTGICR_LINESTATEEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field ONEMSECEN[6] (RW) - * - * Values: - * - 0 - Diables the 1ms timer interrupt. - * - 1 - Enables the 1ms timer interrupt. - */ -/*@{*/ -#define BP_USB_OTGICR_ONEMSECEN (6U) /*!< Bit position for USB_OTGICR_ONEMSECEN. */ -#define BM_USB_OTGICR_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGICR_ONEMSECEN. */ -#define BS_USB_OTGICR_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGICR_ONEMSECEN. */ - -/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */ -#define BR_USB_OTGICR_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN)) - -/*! @brief Format value for bitfield USB_OTGICR_ONEMSECEN. */ -#define BF_USB_OTGICR_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_ONEMSECEN) & BM_USB_OTGICR_ONEMSECEN) - -/*! @brief Set the ONEMSECEN field to a new value. */ -#define BW_USB_OTGICR_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGICR, field IDEN[7] (RW) - * - * Values: - * - 0 - The ID interrupt is disabled - * - 1 - The ID interrupt is enabled - */ -/*@{*/ -#define BP_USB_OTGICR_IDEN (7U) /*!< Bit position for USB_OTGICR_IDEN. */ -#define BM_USB_OTGICR_IDEN (0x80U) /*!< Bit mask for USB_OTGICR_IDEN. */ -#define BS_USB_OTGICR_IDEN (1U) /*!< Bit field size in bits for USB_OTGICR_IDEN. */ - -/*! @brief Read current value of the USB_OTGICR_IDEN field. */ -#define BR_USB_OTGICR_IDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN)) - -/*! @brief Format value for bitfield USB_OTGICR_IDEN. */ -#define BF_USB_OTGICR_IDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_IDEN) & BM_USB_OTGICR_IDEN) - -/*! @brief Set the IDEN field to a new value. */ -#define BW_USB_OTGICR_IDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGSTAT - OTG Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGSTAT - OTG Status register (RW) - * - * Reset value: 0x00U - * - * Displays the actual value from the external comparator outputs of the ID pin - * and VBUS. - */ -typedef union _hw_usb_otgstat -{ - uint8_t U; - struct _hw_usb_otgstat_bitfields - { - uint8_t AVBUSVLD : 1; /*!< [0] A VBUS Valid */ - uint8_t RESERVED0 : 1; /*!< [1] */ - uint8_t BSESSEND : 1; /*!< [2] B Session End */ - uint8_t SESS_VLD : 1; /*!< [3] Session Valid */ - uint8_t RESERVED1 : 1; /*!< [4] */ - uint8_t LINESTATESTABLE : 1; /*!< [5] */ - uint8_t ONEMSECEN : 1; /*!< [6] */ - uint8_t ID : 1; /*!< [7] */ - } B; -} hw_usb_otgstat_t; - -/*! - * @name Constants and macros for entire USB_OTGSTAT register - */ -/*@{*/ -#define HW_USB_OTGSTAT_ADDR(x) ((x) + 0x18U) - -#define HW_USB_OTGSTAT(x) (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR(x)) -#define HW_USB_OTGSTAT_RD(x) (HW_USB_OTGSTAT(x).U) -#define HW_USB_OTGSTAT_WR(x, v) (HW_USB_OTGSTAT(x).U = (v)) -#define HW_USB_OTGSTAT_SET(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) | (v))) -#define HW_USB_OTGSTAT_CLR(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) & ~(v))) -#define HW_USB_OTGSTAT_TOG(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGSTAT bitfields - */ - -/*! - * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW) - * - * Values: - * - 0 - The VBUS voltage is below the A VBUS Valid threshold. - * - 1 - The VBUS voltage is above the A VBUS Valid threshold. - */ -/*@{*/ -#define BP_USB_OTGSTAT_AVBUSVLD (0U) /*!< Bit position for USB_OTGSTAT_AVBUSVLD. */ -#define BM_USB_OTGSTAT_AVBUSVLD (0x01U) /*!< Bit mask for USB_OTGSTAT_AVBUSVLD. */ -#define BS_USB_OTGSTAT_AVBUSVLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD. */ - -/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */ -#define BR_USB_OTGSTAT_AVBUSVLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD)) - -/*! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD. */ -#define BF_USB_OTGSTAT_AVBUSVLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_AVBUSVLD) & BM_USB_OTGSTAT_AVBUSVLD) - -/*! @brief Set the AVBUSVLD field to a new value. */ -#define BW_USB_OTGSTAT_AVBUSVLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field BSESSEND[2] (RW) - * - * Values: - * - 0 - The VBUS voltage is above the B session end threshold. - * - 1 - The VBUS voltage is below the B session end threshold. - */ -/*@{*/ -#define BP_USB_OTGSTAT_BSESSEND (2U) /*!< Bit position for USB_OTGSTAT_BSESSEND. */ -#define BM_USB_OTGSTAT_BSESSEND (0x04U) /*!< Bit mask for USB_OTGSTAT_BSESSEND. */ -#define BS_USB_OTGSTAT_BSESSEND (1U) /*!< Bit field size in bits for USB_OTGSTAT_BSESSEND. */ - -/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */ -#define BR_USB_OTGSTAT_BSESSEND(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND)) - -/*! @brief Format value for bitfield USB_OTGSTAT_BSESSEND. */ -#define BF_USB_OTGSTAT_BSESSEND(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_BSESSEND) & BM_USB_OTGSTAT_BSESSEND) - -/*! @brief Set the BSESSEND field to a new value. */ -#define BW_USB_OTGSTAT_BSESSEND(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW) - * - * Values: - * - 0 - The VBUS voltage is below the B session valid threshold - * - 1 - The VBUS voltage is above the B session valid threshold. - */ -/*@{*/ -#define BP_USB_OTGSTAT_SESS_VLD (3U) /*!< Bit position for USB_OTGSTAT_SESS_VLD. */ -#define BM_USB_OTGSTAT_SESS_VLD (0x08U) /*!< Bit mask for USB_OTGSTAT_SESS_VLD. */ -#define BS_USB_OTGSTAT_SESS_VLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_SESS_VLD. */ - -/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */ -#define BR_USB_OTGSTAT_SESS_VLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD)) - -/*! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD. */ -#define BF_USB_OTGSTAT_SESS_VLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_SESS_VLD) & BM_USB_OTGSTAT_SESS_VLD) - -/*! @brief Set the SESS_VLD field to a new value. */ -#define BW_USB_OTGSTAT_SESS_VLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW) - * - * Indicates that the internal signals that control the LINE_STATE_CHG field of - * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG - * field and then read this field. If this field reads as 1, then the value of - * LINE_STATE_CHG can be considered stable. - * - * Values: - * - 0 - The LINE_STAT_CHG bit is not yet stable. - * - 1 - The LINE_STAT_CHG bit has been debounced and is stable. - */ -/*@{*/ -#define BP_USB_OTGSTAT_LINESTATESTABLE (5U) /*!< Bit position for USB_OTGSTAT_LINESTATESTABLE. */ -#define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) /*!< Bit mask for USB_OTGSTAT_LINESTATESTABLE. */ -#define BS_USB_OTGSTAT_LINESTATESTABLE (1U) /*!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE. */ - -/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */ -#define BR_USB_OTGSTAT_LINESTATESTABLE(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE)) - -/*! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE. */ -#define BF_USB_OTGSTAT_LINESTATESTABLE(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_LINESTATESTABLE) & BM_USB_OTGSTAT_LINESTATESTABLE) - -/*! @brief Set the LINESTATESTABLE field to a new value. */ -#define BW_USB_OTGSTAT_LINESTATESTABLE(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW) - * - * This bit is reserved for the 1ms count, but it is not useful to software. - */ -/*@{*/ -#define BP_USB_OTGSTAT_ONEMSECEN (6U) /*!< Bit position for USB_OTGSTAT_ONEMSECEN. */ -#define BM_USB_OTGSTAT_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGSTAT_ONEMSECEN. */ -#define BS_USB_OTGSTAT_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN. */ - -/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */ -#define BR_USB_OTGSTAT_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN)) - -/*! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN. */ -#define BF_USB_OTGSTAT_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ONEMSECEN) & BM_USB_OTGSTAT_ONEMSECEN) - -/*! @brief Set the ONEMSECEN field to a new value. */ -#define BW_USB_OTGSTAT_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGSTAT, field ID[7] (RW) - * - * Indicates the current state of the ID pin on the USB connector - * - * Values: - * - 0 - Indicates a Type A cable is plugged into the USB connector. - * - 1 - Indicates no cable is attached or a Type B cable is plugged into the - * USB connector. - */ -/*@{*/ -#define BP_USB_OTGSTAT_ID (7U) /*!< Bit position for USB_OTGSTAT_ID. */ -#define BM_USB_OTGSTAT_ID (0x80U) /*!< Bit mask for USB_OTGSTAT_ID. */ -#define BS_USB_OTGSTAT_ID (1U) /*!< Bit field size in bits for USB_OTGSTAT_ID. */ - -/*! @brief Read current value of the USB_OTGSTAT_ID field. */ -#define BR_USB_OTGSTAT_ID(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID)) - -/*! @brief Format value for bitfield USB_OTGSTAT_ID. */ -#define BF_USB_OTGSTAT_ID(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ID) & BM_USB_OTGSTAT_ID) - -/*! @brief Set the ID field to a new value. */ -#define BW_USB_OTGSTAT_ID(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OTGCTL - OTG Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_OTGCTL - OTG Control register (RW) - * - * Reset value: 0x00U - * - * Controls the operation of VBUS and Data Line termination resistors. - */ -typedef union _hw_usb_otgctl -{ - uint8_t U; - struct _hw_usb_otgctl_bitfields - { - uint8_t RESERVED0 : 2; /*!< [1:0] */ - uint8_t OTGEN : 1; /*!< [2] On-The-Go pullup/pulldown resistor enable - * */ - uint8_t RESERVED1 : 1; /*!< [3] */ - uint8_t DMLOW : 1; /*!< [4] D- Data Line pull-down resistor enable */ - uint8_t DPLOW : 1; /*!< [5] D+ Data Line pull-down resistor enable */ - uint8_t RESERVED2 : 1; /*!< [6] */ - uint8_t DPHIGH : 1; /*!< [7] D+ Data Line pullup resistor enable */ - } B; -} hw_usb_otgctl_t; - -/*! - * @name Constants and macros for entire USB_OTGCTL register - */ -/*@{*/ -#define HW_USB_OTGCTL_ADDR(x) ((x) + 0x1CU) - -#define HW_USB_OTGCTL(x) (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR(x)) -#define HW_USB_OTGCTL_RD(x) (HW_USB_OTGCTL(x).U) -#define HW_USB_OTGCTL_WR(x, v) (HW_USB_OTGCTL(x).U = (v)) -#define HW_USB_OTGCTL_SET(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) | (v))) -#define HW_USB_OTGCTL_CLR(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) & ~(v))) -#define HW_USB_OTGCTL_TOG(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_OTGCTL bitfields - */ - -/*! - * @name Register USB_OTGCTL, field OTGEN[2] (RW) - * - * Values: - * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then - * the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ - * and D- Data Line pull-down resistors are engaged. - * - 1 - The pull-up and pull-down controls in this register are used. - */ -/*@{*/ -#define BP_USB_OTGCTL_OTGEN (2U) /*!< Bit position for USB_OTGCTL_OTGEN. */ -#define BM_USB_OTGCTL_OTGEN (0x04U) /*!< Bit mask for USB_OTGCTL_OTGEN. */ -#define BS_USB_OTGCTL_OTGEN (1U) /*!< Bit field size in bits for USB_OTGCTL_OTGEN. */ - -/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */ -#define BR_USB_OTGCTL_OTGEN(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN)) - -/*! @brief Format value for bitfield USB_OTGCTL_OTGEN. */ -#define BF_USB_OTGCTL_OTGEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_OTGEN) & BM_USB_OTGCTL_OTGEN) - -/*! @brief Set the OTGEN field to a new value. */ -#define BW_USB_OTGCTL_OTGEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGCTL, field DMLOW[4] (RW) - * - * Values: - * - 0 - D- pulldown resistor is not enabled. - * - 1 - D- pulldown resistor is enabled. - */ -/*@{*/ -#define BP_USB_OTGCTL_DMLOW (4U) /*!< Bit position for USB_OTGCTL_DMLOW. */ -#define BM_USB_OTGCTL_DMLOW (0x10U) /*!< Bit mask for USB_OTGCTL_DMLOW. */ -#define BS_USB_OTGCTL_DMLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DMLOW. */ - -/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */ -#define BR_USB_OTGCTL_DMLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW)) - -/*! @brief Format value for bitfield USB_OTGCTL_DMLOW. */ -#define BF_USB_OTGCTL_DMLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DMLOW) & BM_USB_OTGCTL_DMLOW) - -/*! @brief Set the DMLOW field to a new value. */ -#define BW_USB_OTGCTL_DMLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGCTL, field DPLOW[5] (RW) - * - * This bit should always be enabled together with bit 4 (DMLOW) - * - * Values: - * - 0 - D+ pulldown resistor is not enabled. - * - 1 - D+ pulldown resistor is enabled. - */ -/*@{*/ -#define BP_USB_OTGCTL_DPLOW (5U) /*!< Bit position for USB_OTGCTL_DPLOW. */ -#define BM_USB_OTGCTL_DPLOW (0x20U) /*!< Bit mask for USB_OTGCTL_DPLOW. */ -#define BS_USB_OTGCTL_DPLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DPLOW. */ - -/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */ -#define BR_USB_OTGCTL_DPLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW)) - -/*! @brief Format value for bitfield USB_OTGCTL_DPLOW. */ -#define BF_USB_OTGCTL_DPLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPLOW) & BM_USB_OTGCTL_DPLOW) - -/*! @brief Set the DPLOW field to a new value. */ -#define BW_USB_OTGCTL_DPLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW) = (v)) -/*@}*/ - -/*! - * @name Register USB_OTGCTL, field DPHIGH[7] (RW) - * - * Values: - * - 0 - D+ pullup resistor is not enabled - * - 1 - D+ pullup resistor is enabled - */ -/*@{*/ -#define BP_USB_OTGCTL_DPHIGH (7U) /*!< Bit position for USB_OTGCTL_DPHIGH. */ -#define BM_USB_OTGCTL_DPHIGH (0x80U) /*!< Bit mask for USB_OTGCTL_DPHIGH. */ -#define BS_USB_OTGCTL_DPHIGH (1U) /*!< Bit field size in bits for USB_OTGCTL_DPHIGH. */ - -/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */ -#define BR_USB_OTGCTL_DPHIGH(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH)) - -/*! @brief Format value for bitfield USB_OTGCTL_DPHIGH. */ -#define BF_USB_OTGCTL_DPHIGH(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPHIGH) & BM_USB_OTGCTL_DPHIGH) - -/*! @brief Set the DPHIGH field to a new value. */ -#define BW_USB_OTGCTL_DPHIGH(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ISTAT - Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_ISTAT - Interrupt Status register (W1C) - * - * Reset value: 0x00U - * - * Contains fields for each of the interrupt sources within the USB Module. Each - * of these fields are qualified with their respective interrupt enable bits. - * All fields of this register are logically OR'd together along with the OTG - * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the - * processor's interrupt controller. After an interrupt bit has been set it may only - * be cleared by writing a one to the respective interrupt bit. This register - * contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_istat -{ - uint8_t U; - struct _hw_usb_istat_bitfields - { - uint8_t USBRST : 1; /*!< [0] */ - uint8_t ERROR : 1; /*!< [1] */ - uint8_t SOFTOK : 1; /*!< [2] */ - uint8_t TOKDNE : 1; /*!< [3] */ - uint8_t SLEEP : 1; /*!< [4] */ - uint8_t RESUME : 1; /*!< [5] */ - uint8_t ATTACH : 1; /*!< [6] Attach Interrupt */ - uint8_t STALL : 1; /*!< [7] Stall Interrupt */ - } B; -} hw_usb_istat_t; - -/*! - * @name Constants and macros for entire USB_ISTAT register - */ -/*@{*/ -#define HW_USB_ISTAT_ADDR(x) ((x) + 0x80U) - -#define HW_USB_ISTAT(x) (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR(x)) -#define HW_USB_ISTAT_RD(x) (HW_USB_ISTAT(x).U) -#define HW_USB_ISTAT_WR(x, v) (HW_USB_ISTAT(x).U = (v)) -#define HW_USB_ISTAT_SET(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) | (v))) -#define HW_USB_ISTAT_CLR(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) & ~(v))) -#define HW_USB_ISTAT_TOG(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ISTAT bitfields - */ - -/*! - * @name Register USB_ISTAT, field USBRST[0] (W1C) - * - * This bit is set when the USB Module has decoded a valid USB reset. This - * informs the processor that it should write 0x00 into the address register and - * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5 - * microseconds. It is not asserted again until the USB reset condition has been - * removed and then reasserted. - */ -/*@{*/ -#define BP_USB_ISTAT_USBRST (0U) /*!< Bit position for USB_ISTAT_USBRST. */ -#define BM_USB_ISTAT_USBRST (0x01U) /*!< Bit mask for USB_ISTAT_USBRST. */ -#define BS_USB_ISTAT_USBRST (1U) /*!< Bit field size in bits for USB_ISTAT_USBRST. */ - -/*! @brief Read current value of the USB_ISTAT_USBRST field. */ -#define BR_USB_ISTAT_USBRST(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST)) - -/*! @brief Format value for bitfield USB_ISTAT_USBRST. */ -#define BF_USB_ISTAT_USBRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_USBRST) & BM_USB_ISTAT_USBRST) - -/*! @brief Set the USBRST field to a new value. */ -#define BW_USB_ISTAT_USBRST(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field ERROR[1] (W1C) - * - * This bit is set when any of the error conditions within Error Interrupt - * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register - * to determine the source of the error. - */ -/*@{*/ -#define BP_USB_ISTAT_ERROR (1U) /*!< Bit position for USB_ISTAT_ERROR. */ -#define BM_USB_ISTAT_ERROR (0x02U) /*!< Bit mask for USB_ISTAT_ERROR. */ -#define BS_USB_ISTAT_ERROR (1U) /*!< Bit field size in bits for USB_ISTAT_ERROR. */ - -/*! @brief Read current value of the USB_ISTAT_ERROR field. */ -#define BR_USB_ISTAT_ERROR(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR)) - -/*! @brief Format value for bitfield USB_ISTAT_ERROR. */ -#define BF_USB_ISTAT_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ERROR) & BM_USB_ISTAT_ERROR) - -/*! @brief Set the ERROR field to a new value. */ -#define BW_USB_ISTAT_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field SOFTOK[2] (W1C) - * - * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In - * Host mode this field is set when the SOF threshold is reached, so that - * software can prepare for the next SOF. - */ -/*@{*/ -#define BP_USB_ISTAT_SOFTOK (2U) /*!< Bit position for USB_ISTAT_SOFTOK. */ -#define BM_USB_ISTAT_SOFTOK (0x04U) /*!< Bit mask for USB_ISTAT_SOFTOK. */ -#define BS_USB_ISTAT_SOFTOK (1U) /*!< Bit field size in bits for USB_ISTAT_SOFTOK. */ - -/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */ -#define BR_USB_ISTAT_SOFTOK(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK)) - -/*! @brief Format value for bitfield USB_ISTAT_SOFTOK. */ -#define BF_USB_ISTAT_SOFTOK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SOFTOK) & BM_USB_ISTAT_SOFTOK) - -/*! @brief Set the SOFTOK field to a new value. */ -#define BW_USB_ISTAT_SOFTOK(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field TOKDNE[3] (W1C) - * - * This bit is set when the current token being processed has completed. The - * processor must immediately read the STATUS (STAT) register to determine the - * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes - * STAT to be cleared or the STAT holding register to be loaded into the STAT - * register. - */ -/*@{*/ -#define BP_USB_ISTAT_TOKDNE (3U) /*!< Bit position for USB_ISTAT_TOKDNE. */ -#define BM_USB_ISTAT_TOKDNE (0x08U) /*!< Bit mask for USB_ISTAT_TOKDNE. */ -#define BS_USB_ISTAT_TOKDNE (1U) /*!< Bit field size in bits for USB_ISTAT_TOKDNE. */ - -/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */ -#define BR_USB_ISTAT_TOKDNE(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE)) - -/*! @brief Format value for bitfield USB_ISTAT_TOKDNE. */ -#define BF_USB_ISTAT_TOKDNE(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_TOKDNE) & BM_USB_ISTAT_TOKDNE) - -/*! @brief Set the TOKDNE field to a new value. */ -#define BW_USB_ISTAT_TOKDNE(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field SLEEP[4] (W1C) - * - * This bit is set when the USB Module detects a constant idle on the USB bus - * for 3 ms. The sleep timer is reset by activity on the USB bus. - */ -/*@{*/ -#define BP_USB_ISTAT_SLEEP (4U) /*!< Bit position for USB_ISTAT_SLEEP. */ -#define BM_USB_ISTAT_SLEEP (0x10U) /*!< Bit mask for USB_ISTAT_SLEEP. */ -#define BS_USB_ISTAT_SLEEP (1U) /*!< Bit field size in bits for USB_ISTAT_SLEEP. */ - -/*! @brief Read current value of the USB_ISTAT_SLEEP field. */ -#define BR_USB_ISTAT_SLEEP(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP)) - -/*! @brief Format value for bitfield USB_ISTAT_SLEEP. */ -#define BF_USB_ISTAT_SLEEP(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SLEEP) & BM_USB_ISTAT_SLEEP) - -/*! @brief Set the SLEEP field to a new value. */ -#define BW_USB_ISTAT_SLEEP(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field RESUME[5] (W1C) - * - * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us. - * When not in suspend mode this interrupt must be disabled. - */ -/*@{*/ -#define BP_USB_ISTAT_RESUME (5U) /*!< Bit position for USB_ISTAT_RESUME. */ -#define BM_USB_ISTAT_RESUME (0x20U) /*!< Bit mask for USB_ISTAT_RESUME. */ -#define BS_USB_ISTAT_RESUME (1U) /*!< Bit field size in bits for USB_ISTAT_RESUME. */ - -/*! @brief Read current value of the USB_ISTAT_RESUME field. */ -#define BR_USB_ISTAT_RESUME(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME)) - -/*! @brief Format value for bitfield USB_ISTAT_RESUME. */ -#define BF_USB_ISTAT_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_RESUME) & BM_USB_ISTAT_RESUME) - -/*! @brief Set the RESUME field to a new value. */ -#define BW_USB_ISTAT_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field ATTACH[6] (W1C) - * - * This bit is set when the USB Module detects an attach of a USB device. This - * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a - * peripheral is now present and must be configured; it is asserted if there have - * been no transitions on the USB for 2.5 us and the current bus state is not SE0." - */ -/*@{*/ -#define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */ -#define BM_USB_ISTAT_ATTACH (0x40U) /*!< Bit mask for USB_ISTAT_ATTACH. */ -#define BS_USB_ISTAT_ATTACH (1U) /*!< Bit field size in bits for USB_ISTAT_ATTACH. */ - -/*! @brief Read current value of the USB_ISTAT_ATTACH field. */ -#define BR_USB_ISTAT_ATTACH(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH)) - -/*! @brief Format value for bitfield USB_ISTAT_ATTACH. */ -#define BF_USB_ISTAT_ATTACH(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ATTACH) & BM_USB_ISTAT_ATTACH) - -/*! @brief Set the ATTACH field to a new value. */ -#define BW_USB_ISTAT_ATTACH(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH) = (v)) -/*@}*/ - -/*! - * @name Register USB_ISTAT, field STALL[7] (W1C) - * - * In Target mode this bit is asserted when a STALL handshake is sent by the - * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge - * during the handshake phase of a USB transaction.This interrupt can be used to - * determine whether the last USB transaction was completed successfully or - * stalled. - */ -/*@{*/ -#define BP_USB_ISTAT_STALL (7U) /*!< Bit position for USB_ISTAT_STALL. */ -#define BM_USB_ISTAT_STALL (0x80U) /*!< Bit mask for USB_ISTAT_STALL. */ -#define BS_USB_ISTAT_STALL (1U) /*!< Bit field size in bits for USB_ISTAT_STALL. */ - -/*! @brief Read current value of the USB_ISTAT_STALL field. */ -#define BR_USB_ISTAT_STALL(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL)) - -/*! @brief Format value for bitfield USB_ISTAT_STALL. */ -#define BF_USB_ISTAT_STALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_STALL) & BM_USB_ISTAT_STALL) - -/*! @brief Set the STALL field to a new value. */ -#define BW_USB_ISTAT_STALL(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_INTEN - Interrupt Enable register - ******************************************************************************/ - -/*! - * @brief HW_USB_INTEN - Interrupt Enable register (RW) - * - * Reset value: 0x00U - * - * Contains enable fields for each of the interrupt sources within the USB - * Module. Setting any of these bits enables the respective interrupt source in the - * ISTAT register. This register contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_inten -{ - uint8_t U; - struct _hw_usb_inten_bitfields - { - uint8_t USBRSTEN : 1; /*!< [0] USBRST Interrupt Enable */ - uint8_t ERROREN : 1; /*!< [1] ERROR Interrupt Enable */ - uint8_t SOFTOKEN : 1; /*!< [2] SOFTOK Interrupt Enable */ - uint8_t TOKDNEEN : 1; /*!< [3] TOKDNE Interrupt Enable */ - uint8_t SLEEPEN : 1; /*!< [4] SLEEP Interrupt Enable */ - uint8_t RESUMEEN : 1; /*!< [5] RESUME Interrupt Enable */ - uint8_t ATTACHEN : 1; /*!< [6] ATTACH Interrupt Enable */ - uint8_t STALLEN : 1; /*!< [7] STALL Interrupt Enable */ - } B; -} hw_usb_inten_t; - -/*! - * @name Constants and macros for entire USB_INTEN register - */ -/*@{*/ -#define HW_USB_INTEN_ADDR(x) ((x) + 0x84U) - -#define HW_USB_INTEN(x) (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR(x)) -#define HW_USB_INTEN_RD(x) (HW_USB_INTEN(x).U) -#define HW_USB_INTEN_WR(x, v) (HW_USB_INTEN(x).U = (v)) -#define HW_USB_INTEN_SET(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) | (v))) -#define HW_USB_INTEN_CLR(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) & ~(v))) -#define HW_USB_INTEN_TOG(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_INTEN bitfields - */ - -/*! - * @name Register USB_INTEN, field USBRSTEN[0] (RW) - * - * Values: - * - 0 - Disables the USBRST interrupt. - * - 1 - Enables the USBRST interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_USBRSTEN (0U) /*!< Bit position for USB_INTEN_USBRSTEN. */ -#define BM_USB_INTEN_USBRSTEN (0x01U) /*!< Bit mask for USB_INTEN_USBRSTEN. */ -#define BS_USB_INTEN_USBRSTEN (1U) /*!< Bit field size in bits for USB_INTEN_USBRSTEN. */ - -/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */ -#define BR_USB_INTEN_USBRSTEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN)) - -/*! @brief Format value for bitfield USB_INTEN_USBRSTEN. */ -#define BF_USB_INTEN_USBRSTEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_USBRSTEN) & BM_USB_INTEN_USBRSTEN) - -/*! @brief Set the USBRSTEN field to a new value. */ -#define BW_USB_INTEN_USBRSTEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field ERROREN[1] (RW) - * - * Values: - * - 0 - Disables the ERROR interrupt. - * - 1 - Enables the ERROR interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_ERROREN (1U) /*!< Bit position for USB_INTEN_ERROREN. */ -#define BM_USB_INTEN_ERROREN (0x02U) /*!< Bit mask for USB_INTEN_ERROREN. */ -#define BS_USB_INTEN_ERROREN (1U) /*!< Bit field size in bits for USB_INTEN_ERROREN. */ - -/*! @brief Read current value of the USB_INTEN_ERROREN field. */ -#define BR_USB_INTEN_ERROREN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN)) - -/*! @brief Format value for bitfield USB_INTEN_ERROREN. */ -#define BF_USB_INTEN_ERROREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ERROREN) & BM_USB_INTEN_ERROREN) - -/*! @brief Set the ERROREN field to a new value. */ -#define BW_USB_INTEN_ERROREN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field SOFTOKEN[2] (RW) - * - * Values: - * - 0 - Disbles the SOFTOK interrupt. - * - 1 - Enables the SOFTOK interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_SOFTOKEN (2U) /*!< Bit position for USB_INTEN_SOFTOKEN. */ -#define BM_USB_INTEN_SOFTOKEN (0x04U) /*!< Bit mask for USB_INTEN_SOFTOKEN. */ -#define BS_USB_INTEN_SOFTOKEN (1U) /*!< Bit field size in bits for USB_INTEN_SOFTOKEN. */ - -/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */ -#define BR_USB_INTEN_SOFTOKEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN)) - -/*! @brief Format value for bitfield USB_INTEN_SOFTOKEN. */ -#define BF_USB_INTEN_SOFTOKEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SOFTOKEN) & BM_USB_INTEN_SOFTOKEN) - -/*! @brief Set the SOFTOKEN field to a new value. */ -#define BW_USB_INTEN_SOFTOKEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field TOKDNEEN[3] (RW) - * - * Values: - * - 0 - Disables the TOKDNE interrupt. - * - 1 - Enables the TOKDNE interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_TOKDNEEN (3U) /*!< Bit position for USB_INTEN_TOKDNEEN. */ -#define BM_USB_INTEN_TOKDNEEN (0x08U) /*!< Bit mask for USB_INTEN_TOKDNEEN. */ -#define BS_USB_INTEN_TOKDNEEN (1U) /*!< Bit field size in bits for USB_INTEN_TOKDNEEN. */ - -/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */ -#define BR_USB_INTEN_TOKDNEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN)) - -/*! @brief Format value for bitfield USB_INTEN_TOKDNEEN. */ -#define BF_USB_INTEN_TOKDNEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_TOKDNEEN) & BM_USB_INTEN_TOKDNEEN) - -/*! @brief Set the TOKDNEEN field to a new value. */ -#define BW_USB_INTEN_TOKDNEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field SLEEPEN[4] (RW) - * - * Values: - * - 0 - Disables the SLEEP interrupt. - * - 1 - Enables the SLEEP interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_SLEEPEN (4U) /*!< Bit position for USB_INTEN_SLEEPEN. */ -#define BM_USB_INTEN_SLEEPEN (0x10U) /*!< Bit mask for USB_INTEN_SLEEPEN. */ -#define BS_USB_INTEN_SLEEPEN (1U) /*!< Bit field size in bits for USB_INTEN_SLEEPEN. */ - -/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */ -#define BR_USB_INTEN_SLEEPEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN)) - -/*! @brief Format value for bitfield USB_INTEN_SLEEPEN. */ -#define BF_USB_INTEN_SLEEPEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SLEEPEN) & BM_USB_INTEN_SLEEPEN) - -/*! @brief Set the SLEEPEN field to a new value. */ -#define BW_USB_INTEN_SLEEPEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field RESUMEEN[5] (RW) - * - * Values: - * - 0 - Disables the RESUME interrupt. - * - 1 - Enables the RESUME interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_RESUMEEN (5U) /*!< Bit position for USB_INTEN_RESUMEEN. */ -#define BM_USB_INTEN_RESUMEEN (0x20U) /*!< Bit mask for USB_INTEN_RESUMEEN. */ -#define BS_USB_INTEN_RESUMEEN (1U) /*!< Bit field size in bits for USB_INTEN_RESUMEEN. */ - -/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */ -#define BR_USB_INTEN_RESUMEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN)) - -/*! @brief Format value for bitfield USB_INTEN_RESUMEEN. */ -#define BF_USB_INTEN_RESUMEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_RESUMEEN) & BM_USB_INTEN_RESUMEEN) - -/*! @brief Set the RESUMEEN field to a new value. */ -#define BW_USB_INTEN_RESUMEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field ATTACHEN[6] (RW) - * - * Values: - * - 0 - Disables the ATTACH interrupt. - * - 1 - Enables the ATTACH interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_ATTACHEN (6U) /*!< Bit position for USB_INTEN_ATTACHEN. */ -#define BM_USB_INTEN_ATTACHEN (0x40U) /*!< Bit mask for USB_INTEN_ATTACHEN. */ -#define BS_USB_INTEN_ATTACHEN (1U) /*!< Bit field size in bits for USB_INTEN_ATTACHEN. */ - -/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */ -#define BR_USB_INTEN_ATTACHEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN)) - -/*! @brief Format value for bitfield USB_INTEN_ATTACHEN. */ -#define BF_USB_INTEN_ATTACHEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ATTACHEN) & BM_USB_INTEN_ATTACHEN) - -/*! @brief Set the ATTACHEN field to a new value. */ -#define BW_USB_INTEN_ATTACHEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_INTEN, field STALLEN[7] (RW) - * - * Values: - * - 0 - Diasbles the STALL interrupt. - * - 1 - Enables the STALL interrupt. - */ -/*@{*/ -#define BP_USB_INTEN_STALLEN (7U) /*!< Bit position for USB_INTEN_STALLEN. */ -#define BM_USB_INTEN_STALLEN (0x80U) /*!< Bit mask for USB_INTEN_STALLEN. */ -#define BS_USB_INTEN_STALLEN (1U) /*!< Bit field size in bits for USB_INTEN_STALLEN. */ - -/*! @brief Read current value of the USB_INTEN_STALLEN field. */ -#define BR_USB_INTEN_STALLEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN)) - -/*! @brief Format value for bitfield USB_INTEN_STALLEN. */ -#define BF_USB_INTEN_STALLEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_STALLEN) & BM_USB_INTEN_STALLEN) - -/*! @brief Set the STALLEN field to a new value. */ -#define BW_USB_INTEN_STALLEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ERRSTAT - Error Interrupt Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW) - * - * Reset value: 0x00U - * - * Contains enable bits for each of the error sources within the USB Module. - * Each of these bits are qualified with their respective error enable bits. All - * bits of this register are logically OR'd together and the result placed in the - * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only - * be cleared by writing a one to the respective interrupt bit. Each bit is set - * as soon as the error condition is detected. Therefore, the interrupt does not - * typically correspond with the end of a token being processed. This register - * contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_errstat -{ - uint8_t U; - struct _hw_usb_errstat_bitfields - { - uint8_t PIDERR : 1; /*!< [0] */ - uint8_t CRC5EOF : 1; /*!< [1] */ - uint8_t CRC16 : 1; /*!< [2] */ - uint8_t DFN8 : 1; /*!< [3] */ - uint8_t BTOERR : 1; /*!< [4] */ - uint8_t DMAERR : 1; /*!< [5] */ - uint8_t RESERVED0 : 1; /*!< [6] */ - uint8_t BTSERR : 1; /*!< [7] */ - } B; -} hw_usb_errstat_t; - -/*! - * @name Constants and macros for entire USB_ERRSTAT register - */ -/*@{*/ -#define HW_USB_ERRSTAT_ADDR(x) ((x) + 0x88U) - -#define HW_USB_ERRSTAT(x) (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR(x)) -#define HW_USB_ERRSTAT_RD(x) (HW_USB_ERRSTAT(x).U) -#define HW_USB_ERRSTAT_WR(x, v) (HW_USB_ERRSTAT(x).U = (v)) -#define HW_USB_ERRSTAT_SET(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) | (v))) -#define HW_USB_ERRSTAT_CLR(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) & ~(v))) -#define HW_USB_ERRSTAT_TOG(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ERRSTAT bitfields - */ - -/*! - * @name Register USB_ERRSTAT, field PIDERR[0] (W1C) - * - * This bit is set when the PID check field fails. - */ -/*@{*/ -#define BP_USB_ERRSTAT_PIDERR (0U) /*!< Bit position for USB_ERRSTAT_PIDERR. */ -#define BM_USB_ERRSTAT_PIDERR (0x01U) /*!< Bit mask for USB_ERRSTAT_PIDERR. */ -#define BS_USB_ERRSTAT_PIDERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_PIDERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */ -#define BR_USB_ERRSTAT_PIDERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_PIDERR. */ -#define BF_USB_ERRSTAT_PIDERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_PIDERR) & BM_USB_ERRSTAT_PIDERR) - -/*! @brief Set the PIDERR field to a new value. */ -#define BW_USB_ERRSTAT_PIDERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C) - * - * This error interrupt has two functions. When the USB Module is operating in - * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token - * packets generated by the host. If set the token packet was rejected due to a - * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this - * interrupt detects End Of Frame (EOF) error conditions. This occurs when the - * USB Module is transmitting or receiving data and the SOF counter reaches zero. - * This interrupt is useful when developing USB packet scheduling software to - * ensure that no USB transactions cross the start of the next frame. - */ -/*@{*/ -#define BP_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit position for USB_ERRSTAT_CRC5EOF. */ -#define BM_USB_ERRSTAT_CRC5EOF (0x02U) /*!< Bit mask for USB_ERRSTAT_CRC5EOF. */ -#define BS_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC5EOF. */ - -/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */ -#define BR_USB_ERRSTAT_CRC5EOF(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF)) - -/*! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF. */ -#define BF_USB_ERRSTAT_CRC5EOF(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC5EOF) & BM_USB_ERRSTAT_CRC5EOF) - -/*! @brief Set the CRC5EOF field to a new value. */ -#define BW_USB_ERRSTAT_CRC5EOF(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field CRC16[2] (W1C) - * - * This bit is set when a data packet is rejected due to a CRC16 error. - */ -/*@{*/ -#define BP_USB_ERRSTAT_CRC16 (2U) /*!< Bit position for USB_ERRSTAT_CRC16. */ -#define BM_USB_ERRSTAT_CRC16 (0x04U) /*!< Bit mask for USB_ERRSTAT_CRC16. */ -#define BS_USB_ERRSTAT_CRC16 (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC16. */ - -/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */ -#define BR_USB_ERRSTAT_CRC16(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16)) - -/*! @brief Format value for bitfield USB_ERRSTAT_CRC16. */ -#define BF_USB_ERRSTAT_CRC16(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC16) & BM_USB_ERRSTAT_CRC16) - -/*! @brief Set the CRC16 field to a new value. */ -#define BW_USB_ERRSTAT_CRC16(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field DFN8[3] (W1C) - * - * This bit is set if the data field received was not 8 bits in length. USB - * Specification 1.0 requires that data fields be an integral number of bytes. If the - * data field was not an integral number of bytes, this bit is set. - */ -/*@{*/ -#define BP_USB_ERRSTAT_DFN8 (3U) /*!< Bit position for USB_ERRSTAT_DFN8. */ -#define BM_USB_ERRSTAT_DFN8 (0x08U) /*!< Bit mask for USB_ERRSTAT_DFN8. */ -#define BS_USB_ERRSTAT_DFN8 (1U) /*!< Bit field size in bits for USB_ERRSTAT_DFN8. */ - -/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */ -#define BR_USB_ERRSTAT_DFN8(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8)) - -/*! @brief Format value for bitfield USB_ERRSTAT_DFN8. */ -#define BF_USB_ERRSTAT_DFN8(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DFN8) & BM_USB_ERRSTAT_DFN8) - -/*! @brief Set the DFN8 field to a new value. */ -#define BW_USB_ERRSTAT_DFN8(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field BTOERR[4] (W1C) - * - * This bit is set when a bus turnaround timeout error occurs. The USB module - * contains a bus turnaround timer that keeps track of the amount of time elapsed - * between the token and data phases of a SETUP or OUT TOKEN or the data and - * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the - * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs. - */ -/*@{*/ -#define BP_USB_ERRSTAT_BTOERR (4U) /*!< Bit position for USB_ERRSTAT_BTOERR. */ -#define BM_USB_ERRSTAT_BTOERR (0x10U) /*!< Bit mask for USB_ERRSTAT_BTOERR. */ -#define BS_USB_ERRSTAT_BTOERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTOERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */ -#define BR_USB_ERRSTAT_BTOERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_BTOERR. */ -#define BF_USB_ERRSTAT_BTOERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTOERR) & BM_USB_ERRSTAT_BTOERR) - -/*! @brief Set the BTOERR field to a new value. */ -#define BW_USB_ERRSTAT_BTOERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field DMAERR[5] (W1C) - * - * This bit is set if the USB Module has requested a DMA access to read a new - * BDT but has not been given the bus before it needs to receive or transmit data. - * If processing a TX transfer this would cause a transmit data underflow - * condition. If processing a RX transfer this would cause a receive data overflow - * condition. This interrupt is useful when developing device arbitration hardware for - * the microprocessor and the USB module to minimize bus request and bus grant - * latency. This bit is also set if a data packet to or from the host is larger - * than the buffer size allocated in the BDT. In this case the data packet is - * truncated as it is put in buffer memory. - */ -/*@{*/ -#define BP_USB_ERRSTAT_DMAERR (5U) /*!< Bit position for USB_ERRSTAT_DMAERR. */ -#define BM_USB_ERRSTAT_DMAERR (0x20U) /*!< Bit mask for USB_ERRSTAT_DMAERR. */ -#define BS_USB_ERRSTAT_DMAERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_DMAERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */ -#define BR_USB_ERRSTAT_DMAERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_DMAERR. */ -#define BF_USB_ERRSTAT_DMAERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DMAERR) & BM_USB_ERRSTAT_DMAERR) - -/*! @brief Set the DMAERR field to a new value. */ -#define BW_USB_ERRSTAT_DMAERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERRSTAT, field BTSERR[7] (W1C) - * - * This bit is set when a bit stuff error is detected. If set, the corresponding - * packet is rejected due to the error. - */ -/*@{*/ -#define BP_USB_ERRSTAT_BTSERR (7U) /*!< Bit position for USB_ERRSTAT_BTSERR. */ -#define BM_USB_ERRSTAT_BTSERR (0x80U) /*!< Bit mask for USB_ERRSTAT_BTSERR. */ -#define BS_USB_ERRSTAT_BTSERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTSERR. */ - -/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */ -#define BR_USB_ERRSTAT_BTSERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR)) - -/*! @brief Format value for bitfield USB_ERRSTAT_BTSERR. */ -#define BF_USB_ERRSTAT_BTSERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTSERR) & BM_USB_ERRSTAT_BTSERR) - -/*! @brief Set the BTSERR field to a new value. */ -#define BW_USB_ERRSTAT_BTSERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ERREN - Error Interrupt Enable register - ******************************************************************************/ - -/*! - * @brief HW_USB_ERREN - Error Interrupt Enable register (RW) - * - * Reset value: 0x00U - * - * Contains enable bits for each of the error interrupt sources within the USB - * module. Setting any of these bits enables the respective interrupt source in - * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore, - * the interrupt does not typically correspond with the end of a token being - * processed. This register contains the value of 0x00 after a reset. - */ -typedef union _hw_usb_erren -{ - uint8_t U; - struct _hw_usb_erren_bitfields - { - uint8_t PIDERREN : 1; /*!< [0] PIDERR Interrupt Enable */ - uint8_t CRC5EOFEN : 1; /*!< [1] CRC5/EOF Interrupt Enable */ - uint8_t CRC16EN : 1; /*!< [2] CRC16 Interrupt Enable */ - uint8_t DFN8EN : 1; /*!< [3] DFN8 Interrupt Enable */ - uint8_t BTOERREN : 1; /*!< [4] BTOERR Interrupt Enable */ - uint8_t DMAERREN : 1; /*!< [5] DMAERR Interrupt Enable */ - uint8_t RESERVED0 : 1; /*!< [6] */ - uint8_t BTSERREN : 1; /*!< [7] BTSERR Interrupt Enable */ - } B; -} hw_usb_erren_t; - -/*! - * @name Constants and macros for entire USB_ERREN register - */ -/*@{*/ -#define HW_USB_ERREN_ADDR(x) ((x) + 0x8CU) - -#define HW_USB_ERREN(x) (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR(x)) -#define HW_USB_ERREN_RD(x) (HW_USB_ERREN(x).U) -#define HW_USB_ERREN_WR(x, v) (HW_USB_ERREN(x).U = (v)) -#define HW_USB_ERREN_SET(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) | (v))) -#define HW_USB_ERREN_CLR(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) & ~(v))) -#define HW_USB_ERREN_TOG(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ERREN bitfields - */ - -/*! - * @name Register USB_ERREN, field PIDERREN[0] (RW) - * - * Values: - * - 0 - Disables the PIDERR interrupt. - * - 1 - Enters the PIDERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_PIDERREN (0U) /*!< Bit position for USB_ERREN_PIDERREN. */ -#define BM_USB_ERREN_PIDERREN (0x01U) /*!< Bit mask for USB_ERREN_PIDERREN. */ -#define BS_USB_ERREN_PIDERREN (1U) /*!< Bit field size in bits for USB_ERREN_PIDERREN. */ - -/*! @brief Read current value of the USB_ERREN_PIDERREN field. */ -#define BR_USB_ERREN_PIDERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN)) - -/*! @brief Format value for bitfield USB_ERREN_PIDERREN. */ -#define BF_USB_ERREN_PIDERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_PIDERREN) & BM_USB_ERREN_PIDERREN) - -/*! @brief Set the PIDERREN field to a new value. */ -#define BW_USB_ERREN_PIDERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field CRC5EOFEN[1] (RW) - * - * Values: - * - 0 - Disables the CRC5/EOF interrupt. - * - 1 - Enables the CRC5/EOF interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_CRC5EOFEN (1U) /*!< Bit position for USB_ERREN_CRC5EOFEN. */ -#define BM_USB_ERREN_CRC5EOFEN (0x02U) /*!< Bit mask for USB_ERREN_CRC5EOFEN. */ -#define BS_USB_ERREN_CRC5EOFEN (1U) /*!< Bit field size in bits for USB_ERREN_CRC5EOFEN. */ - -/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */ -#define BR_USB_ERREN_CRC5EOFEN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN)) - -/*! @brief Format value for bitfield USB_ERREN_CRC5EOFEN. */ -#define BF_USB_ERREN_CRC5EOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC5EOFEN) & BM_USB_ERREN_CRC5EOFEN) - -/*! @brief Set the CRC5EOFEN field to a new value. */ -#define BW_USB_ERREN_CRC5EOFEN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field CRC16EN[2] (RW) - * - * Values: - * - 0 - Disables the CRC16 interrupt. - * - 1 - Enables the CRC16 interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_CRC16EN (2U) /*!< Bit position for USB_ERREN_CRC16EN. */ -#define BM_USB_ERREN_CRC16EN (0x04U) /*!< Bit mask for USB_ERREN_CRC16EN. */ -#define BS_USB_ERREN_CRC16EN (1U) /*!< Bit field size in bits for USB_ERREN_CRC16EN. */ - -/*! @brief Read current value of the USB_ERREN_CRC16EN field. */ -#define BR_USB_ERREN_CRC16EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN)) - -/*! @brief Format value for bitfield USB_ERREN_CRC16EN. */ -#define BF_USB_ERREN_CRC16EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC16EN) & BM_USB_ERREN_CRC16EN) - -/*! @brief Set the CRC16EN field to a new value. */ -#define BW_USB_ERREN_CRC16EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field DFN8EN[3] (RW) - * - * Values: - * - 0 - Disables the DFN8 interrupt. - * - 1 - Enables the DFN8 interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_DFN8EN (3U) /*!< Bit position for USB_ERREN_DFN8EN. */ -#define BM_USB_ERREN_DFN8EN (0x08U) /*!< Bit mask for USB_ERREN_DFN8EN. */ -#define BS_USB_ERREN_DFN8EN (1U) /*!< Bit field size in bits for USB_ERREN_DFN8EN. */ - -/*! @brief Read current value of the USB_ERREN_DFN8EN field. */ -#define BR_USB_ERREN_DFN8EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN)) - -/*! @brief Format value for bitfield USB_ERREN_DFN8EN. */ -#define BF_USB_ERREN_DFN8EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DFN8EN) & BM_USB_ERREN_DFN8EN) - -/*! @brief Set the DFN8EN field to a new value. */ -#define BW_USB_ERREN_DFN8EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field BTOERREN[4] (RW) - * - * Values: - * - 0 - Disables the BTOERR interrupt. - * - 1 - Enables the BTOERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_BTOERREN (4U) /*!< Bit position for USB_ERREN_BTOERREN. */ -#define BM_USB_ERREN_BTOERREN (0x10U) /*!< Bit mask for USB_ERREN_BTOERREN. */ -#define BS_USB_ERREN_BTOERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTOERREN. */ - -/*! @brief Read current value of the USB_ERREN_BTOERREN field. */ -#define BR_USB_ERREN_BTOERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN)) - -/*! @brief Format value for bitfield USB_ERREN_BTOERREN. */ -#define BF_USB_ERREN_BTOERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTOERREN) & BM_USB_ERREN_BTOERREN) - -/*! @brief Set the BTOERREN field to a new value. */ -#define BW_USB_ERREN_BTOERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field DMAERREN[5] (RW) - * - * Values: - * - 0 - Disables the DMAERR interrupt. - * - 1 - Enables the DMAERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_DMAERREN (5U) /*!< Bit position for USB_ERREN_DMAERREN. */ -#define BM_USB_ERREN_DMAERREN (0x20U) /*!< Bit mask for USB_ERREN_DMAERREN. */ -#define BS_USB_ERREN_DMAERREN (1U) /*!< Bit field size in bits for USB_ERREN_DMAERREN. */ - -/*! @brief Read current value of the USB_ERREN_DMAERREN field. */ -#define BR_USB_ERREN_DMAERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN)) - -/*! @brief Format value for bitfield USB_ERREN_DMAERREN. */ -#define BF_USB_ERREN_DMAERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DMAERREN) & BM_USB_ERREN_DMAERREN) - -/*! @brief Set the DMAERREN field to a new value. */ -#define BW_USB_ERREN_DMAERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ERREN, field BTSERREN[7] (RW) - * - * Values: - * - 0 - Disables the BTSERR interrupt. - * - 1 - Enables the BTSERR interrupt. - */ -/*@{*/ -#define BP_USB_ERREN_BTSERREN (7U) /*!< Bit position for USB_ERREN_BTSERREN. */ -#define BM_USB_ERREN_BTSERREN (0x80U) /*!< Bit mask for USB_ERREN_BTSERREN. */ -#define BS_USB_ERREN_BTSERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTSERREN. */ - -/*! @brief Read current value of the USB_ERREN_BTSERREN field. */ -#define BR_USB_ERREN_BTSERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN)) - -/*! @brief Format value for bitfield USB_ERREN_BTSERREN. */ -#define BF_USB_ERREN_BTSERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTSERREN) & BM_USB_ERREN_BTSERREN) - -/*! @brief Set the BTSERREN field to a new value. */ -#define BW_USB_ERREN_BTSERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_STAT - Status register - ******************************************************************************/ - -/*! - * @brief HW_USB_STAT - Status register (RO) - * - * Reset value: 0x00U - * - * Reports the transaction status within the USB module. When the processor's - * interrupt controller has received a TOKDNE, interrupt the Status Register must - * be read to determine the status of the previous endpoint communication. The - * data in the status register is valid when TOKDNE interrupt is asserted. The - * Status register is actually a read window into a status FIFO maintained by the USB - * module. When the USB module uses a BD, it updates the Status register. If - * another USB transaction is performed before the TOKDNE interrupt is serviced, the - * USB module stores the status of the next transaction in the STAT FIFO. Thus - * STAT is actually a four byte FIFO that allows the processor core to process one - * transaction while the SIE is processing the next transaction. Clearing the - * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents - * of the next STAT value. If the data in the STAT holding register is valid, the - * SIE immediately reasserts to TOKDNE interrupt. - */ -typedef union _hw_usb_stat -{ - uint8_t U; - struct _hw_usb_stat_bitfields - { - uint8_t RESERVED0 : 2; /*!< [1:0] */ - uint8_t ODD : 1; /*!< [2] */ - uint8_t TX : 1; /*!< [3] Transmit Indicator */ - uint8_t ENDP : 4; /*!< [7:4] */ - } B; -} hw_usb_stat_t; - -/*! - * @name Constants and macros for entire USB_STAT register - */ -/*@{*/ -#define HW_USB_STAT_ADDR(x) ((x) + 0x90U) - -#define HW_USB_STAT(x) (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR(x)) -#define HW_USB_STAT_RD(x) (HW_USB_STAT(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_STAT bitfields - */ - -/*! - * @name Register USB_STAT, field ODD[2] (RO) - * - * This bit is set if the last buffer descriptor updated was in the odd bank of - * the BDT. - */ -/*@{*/ -#define BP_USB_STAT_ODD (2U) /*!< Bit position for USB_STAT_ODD. */ -#define BM_USB_STAT_ODD (0x04U) /*!< Bit mask for USB_STAT_ODD. */ -#define BS_USB_STAT_ODD (1U) /*!< Bit field size in bits for USB_STAT_ODD. */ - -/*! @brief Read current value of the USB_STAT_ODD field. */ -#define BR_USB_STAT_ODD(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_ODD)) -/*@}*/ - -/*! - * @name Register USB_STAT, field TX[3] (RO) - * - * Values: - * - 0 - The most recent transaction was a receive operation. - * - 1 - The most recent transaction was a transmit operation. - */ -/*@{*/ -#define BP_USB_STAT_TX (3U) /*!< Bit position for USB_STAT_TX. */ -#define BM_USB_STAT_TX (0x08U) /*!< Bit mask for USB_STAT_TX. */ -#define BS_USB_STAT_TX (1U) /*!< Bit field size in bits for USB_STAT_TX. */ - -/*! @brief Read current value of the USB_STAT_TX field. */ -#define BR_USB_STAT_TX(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_TX)) -/*@}*/ - -/*! - * @name Register USB_STAT, field ENDP[7:4] (RO) - * - * This four-bit field encodes the endpoint address that received or transmitted - * the previous token. This allows the processor core to determine the BDT entry - * that was updated by the last USB transaction. - */ -/*@{*/ -#define BP_USB_STAT_ENDP (4U) /*!< Bit position for USB_STAT_ENDP. */ -#define BM_USB_STAT_ENDP (0xF0U) /*!< Bit mask for USB_STAT_ENDP. */ -#define BS_USB_STAT_ENDP (4U) /*!< Bit field size in bits for USB_STAT_ENDP. */ - -/*! @brief Read current value of the USB_STAT_ENDP field. */ -#define BR_USB_STAT_ENDP(x) (HW_USB_STAT(x).B.ENDP) -/*@}*/ - -/******************************************************************************* - * HW_USB_CTL - Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_CTL - Control register (RW) - * - * Reset value: 0x00U - * - * Provides various control and configuration information for the USB module. - */ -typedef union _hw_usb_ctl -{ - uint8_t U; - struct _hw_usb_ctl_bitfields - { - uint8_t USBENSOFEN : 1; /*!< [0] USB Enable */ - uint8_t ODDRST : 1; /*!< [1] */ - uint8_t RESUME : 1; /*!< [2] */ - uint8_t HOSTMODEEN : 1; /*!< [3] */ - uint8_t RESET : 1; /*!< [4] */ - uint8_t TXSUSPENDTOKENBUSY : 1; /*!< [5] */ - uint8_t SE0 : 1; /*!< [6] Live USB Single Ended Zero signal */ - uint8_t JSTATE : 1; /*!< [7] Live USB differential receiver JSTATE - * signal */ - } B; -} hw_usb_ctl_t; - -/*! - * @name Constants and macros for entire USB_CTL register - */ -/*@{*/ -#define HW_USB_CTL_ADDR(x) ((x) + 0x94U) - -#define HW_USB_CTL(x) (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR(x)) -#define HW_USB_CTL_RD(x) (HW_USB_CTL(x).U) -#define HW_USB_CTL_WR(x, v) (HW_USB_CTL(x).U = (v)) -#define HW_USB_CTL_SET(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) | (v))) -#define HW_USB_CTL_CLR(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) & ~(v))) -#define HW_USB_CTL_TOG(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CTL bitfields - */ - -/*! - * @name Register USB_CTL, field USBENSOFEN[0] (RW) - * - * Setting this bit enables the USB-FS to operate; clearing it disables the - * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs. - * Therefore, setting this bit resets much of the logic in the SIE. When host mode - * is enabled, clearing this bit causes the SIE to stop sending SOF tokens. - * - * Values: - * - 0 - Disables the USB Module. - * - 1 - Enables the USB Module. - */ -/*@{*/ -#define BP_USB_CTL_USBENSOFEN (0U) /*!< Bit position for USB_CTL_USBENSOFEN. */ -#define BM_USB_CTL_USBENSOFEN (0x01U) /*!< Bit mask for USB_CTL_USBENSOFEN. */ -#define BS_USB_CTL_USBENSOFEN (1U) /*!< Bit field size in bits for USB_CTL_USBENSOFEN. */ - -/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */ -#define BR_USB_CTL_USBENSOFEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN)) - -/*! @brief Format value for bitfield USB_CTL_USBENSOFEN. */ -#define BF_USB_CTL_USBENSOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_USBENSOFEN) & BM_USB_CTL_USBENSOFEN) - -/*! @brief Set the USBENSOFEN field to a new value. */ -#define BW_USB_CTL_USBENSOFEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field ODDRST[1] (RW) - * - * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which - * then specifies the EVEN BDT bank. - */ -/*@{*/ -#define BP_USB_CTL_ODDRST (1U) /*!< Bit position for USB_CTL_ODDRST. */ -#define BM_USB_CTL_ODDRST (0x02U) /*!< Bit mask for USB_CTL_ODDRST. */ -#define BS_USB_CTL_ODDRST (1U) /*!< Bit field size in bits for USB_CTL_ODDRST. */ - -/*! @brief Read current value of the USB_CTL_ODDRST field. */ -#define BR_USB_CTL_ODDRST(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST)) - -/*! @brief Format value for bitfield USB_CTL_ODDRST. */ -#define BF_USB_CTL_ODDRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_ODDRST) & BM_USB_CTL_ODDRST) - -/*! @brief Set the ODDRST field to a new value. */ -#define BW_USB_CTL_ODDRST(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field RESUME[2] (RW) - * - * When set to 1 this bit enables the USB Module to execute resume signaling. - * This allows the USB Module to perform remote wake-up. Software must set RESUME - * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN - * bit is set, the USB module appends a Low Speed End of Packet to the Resume - * signaling when the RESUME bit is cleared. For more information on RESUME - * signaling see Section 7.1.4.5 of the USB specification version 1.0. - */ -/*@{*/ -#define BP_USB_CTL_RESUME (2U) /*!< Bit position for USB_CTL_RESUME. */ -#define BM_USB_CTL_RESUME (0x04U) /*!< Bit mask for USB_CTL_RESUME. */ -#define BS_USB_CTL_RESUME (1U) /*!< Bit field size in bits for USB_CTL_RESUME. */ - -/*! @brief Read current value of the USB_CTL_RESUME field. */ -#define BR_USB_CTL_RESUME(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME)) - -/*! @brief Format value for bitfield USB_CTL_RESUME. */ -#define BF_USB_CTL_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESUME) & BM_USB_CTL_RESUME) - -/*! @brief Set the RESUME field to a new value. */ -#define BW_USB_CTL_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field HOSTMODEEN[3] (RW) - * - * When set to 1, this bit enables the USB Module to operate in Host mode. In - * host mode, the USB module performs USB transactions under the programmed control - * of the host processor. - */ -/*@{*/ -#define BP_USB_CTL_HOSTMODEEN (3U) /*!< Bit position for USB_CTL_HOSTMODEEN. */ -#define BM_USB_CTL_HOSTMODEEN (0x08U) /*!< Bit mask for USB_CTL_HOSTMODEEN. */ -#define BS_USB_CTL_HOSTMODEEN (1U) /*!< Bit field size in bits for USB_CTL_HOSTMODEEN. */ - -/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */ -#define BR_USB_CTL_HOSTMODEEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN)) - -/*! @brief Format value for bitfield USB_CTL_HOSTMODEEN. */ -#define BF_USB_CTL_HOSTMODEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_HOSTMODEEN) & BM_USB_CTL_HOSTMODEEN) - -/*! @brief Set the HOSTMODEEN field to a new value. */ -#define BW_USB_CTL_HOSTMODEEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field RESET[4] (RW) - * - * Setting this bit enables the USB Module to generate USB reset signaling. This - * allows the USB Module to reset USB peripherals. This control signal is only - * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the - * required amount of time and then clear it to 0 to end reset signaling. For more - * information on reset signaling see Section 7.1.4.3 of the USB specification version - * 1.0. - */ -/*@{*/ -#define BP_USB_CTL_RESET (4U) /*!< Bit position for USB_CTL_RESET. */ -#define BM_USB_CTL_RESET (0x10U) /*!< Bit mask for USB_CTL_RESET. */ -#define BS_USB_CTL_RESET (1U) /*!< Bit field size in bits for USB_CTL_RESET. */ - -/*! @brief Read current value of the USB_CTL_RESET field. */ -#define BR_USB_CTL_RESET(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET)) - -/*! @brief Format value for bitfield USB_CTL_RESET. */ -#define BF_USB_CTL_RESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESET) & BM_USB_CTL_RESET) - -/*! @brief Set the RESET field to a new value. */ -#define BW_USB_CTL_RESET(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW) - * - * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB - * token. Software must not write more token commands to the Token Register when - * TOKEN_BUSY is set. Software should check this field before writing any tokens - * to the Token Register to ensure that token commands are not lost. In Target - * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and - * reception. Clearing this bit allows the SIE to continue token processing. This bit - * is set by the SIE when a SETUP Token is received allowing software to dequeue - * any pending packet transactions in the BDT before resuming token processing. - */ -/*@{*/ -#define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) /*!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY. */ -#define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) /*!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY. */ -#define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) /*!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY. */ - -/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */ -#define BR_USB_CTL_TXSUSPENDTOKENBUSY(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY)) - -/*! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY. */ -#define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_TXSUSPENDTOKENBUSY) & BM_USB_CTL_TXSUSPENDTOKENBUSY) - -/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */ -#define BW_USB_CTL_TXSUSPENDTOKENBUSY(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field SE0[6] (RW) - */ -/*@{*/ -#define BP_USB_CTL_SE0 (6U) /*!< Bit position for USB_CTL_SE0. */ -#define BM_USB_CTL_SE0 (0x40U) /*!< Bit mask for USB_CTL_SE0. */ -#define BS_USB_CTL_SE0 (1U) /*!< Bit field size in bits for USB_CTL_SE0. */ - -/*! @brief Read current value of the USB_CTL_SE0 field. */ -#define BR_USB_CTL_SE0(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0)) - -/*! @brief Format value for bitfield USB_CTL_SE0. */ -#define BF_USB_CTL_SE0(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_SE0) & BM_USB_CTL_SE0) - -/*! @brief Set the SE0 field to a new value. */ -#define BW_USB_CTL_SE0(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0) = (v)) -/*@}*/ - -/*! - * @name Register USB_CTL, field JSTATE[7] (RW) - * - * The polarity of this signal is affected by the current state of LSEN . - */ -/*@{*/ -#define BP_USB_CTL_JSTATE (7U) /*!< Bit position for USB_CTL_JSTATE. */ -#define BM_USB_CTL_JSTATE (0x80U) /*!< Bit mask for USB_CTL_JSTATE. */ -#define BS_USB_CTL_JSTATE (1U) /*!< Bit field size in bits for USB_CTL_JSTATE. */ - -/*! @brief Read current value of the USB_CTL_JSTATE field. */ -#define BR_USB_CTL_JSTATE(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE)) - -/*! @brief Format value for bitfield USB_CTL_JSTATE. */ -#define BF_USB_CTL_JSTATE(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_JSTATE) & BM_USB_CTL_JSTATE) - -/*! @brief Set the JSTATE field to a new value. */ -#define BW_USB_CTL_JSTATE(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ADDR - Address register - ******************************************************************************/ - -/*! - * @brief HW_USB_ADDR - Address register (RW) - * - * Reset value: 0x00U - * - * Holds the unique USB address that the USB module decodes when in Peripheral - * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module - * transmits this address with a TOKEN packet. This enables the USB module to - * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1. - * The Address register is reset to 0x00 after the reset input becomes active or - * the USB module decodes a USB reset signal. This action initializes the Address - * register to decode address 0x00 as required by the USB specification. - */ -typedef union _hw_usb_addr -{ - uint8_t U; - struct _hw_usb_addr_bitfields - { - uint8_t ADDR : 7; /*!< [6:0] USB Address */ - uint8_t LSEN : 1; /*!< [7] Low Speed Enable bit */ - } B; -} hw_usb_addr_t; - -/*! - * @name Constants and macros for entire USB_ADDR register - */ -/*@{*/ -#define HW_USB_ADDR_ADDR(x) ((x) + 0x98U) - -#define HW_USB_ADDR(x) (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR(x)) -#define HW_USB_ADDR_RD(x) (HW_USB_ADDR(x).U) -#define HW_USB_ADDR_WR(x, v) (HW_USB_ADDR(x).U = (v)) -#define HW_USB_ADDR_SET(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) | (v))) -#define HW_USB_ADDR_CLR(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) & ~(v))) -#define HW_USB_ADDR_TOG(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ADDR bitfields - */ - -/*! - * @name Register USB_ADDR, field ADDR[6:0] (RW) - * - * Defines the USB address that the USB module decodes in peripheral mode, or - * transmits when in host mode. - */ -/*@{*/ -#define BP_USB_ADDR_ADDR (0U) /*!< Bit position for USB_ADDR_ADDR. */ -#define BM_USB_ADDR_ADDR (0x7FU) /*!< Bit mask for USB_ADDR_ADDR. */ -#define BS_USB_ADDR_ADDR (7U) /*!< Bit field size in bits for USB_ADDR_ADDR. */ - -/*! @brief Read current value of the USB_ADDR_ADDR field. */ -#define BR_USB_ADDR_ADDR(x) (HW_USB_ADDR(x).B.ADDR) - -/*! @brief Format value for bitfield USB_ADDR_ADDR. */ -#define BF_USB_ADDR_ADDR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_ADDR) & BM_USB_ADDR_ADDR) - -/*! @brief Set the ADDR field to a new value. */ -#define BW_USB_ADDR_ADDR(x, v) (HW_USB_ADDR_WR(x, (HW_USB_ADDR_RD(x) & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v))) -/*@}*/ - -/*! - * @name Register USB_ADDR, field LSEN[7] (RW) - * - * Informs the USB module that the next token command written to the token - * register must be performed at low speed. This enables the USB module to perform the - * necessary preamble required for low-speed data transmissions. - */ -/*@{*/ -#define BP_USB_ADDR_LSEN (7U) /*!< Bit position for USB_ADDR_LSEN. */ -#define BM_USB_ADDR_LSEN (0x80U) /*!< Bit mask for USB_ADDR_LSEN. */ -#define BS_USB_ADDR_LSEN (1U) /*!< Bit field size in bits for USB_ADDR_LSEN. */ - -/*! @brief Read current value of the USB_ADDR_LSEN field. */ -#define BR_USB_ADDR_LSEN(x) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN)) - -/*! @brief Format value for bitfield USB_ADDR_LSEN. */ -#define BF_USB_ADDR_LSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_LSEN) & BM_USB_ADDR_LSEN) - -/*! @brief Set the LSEN field to a new value. */ -#define BW_USB_ADDR_LSEN(x, v) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_BDTPAGE1 - BDT Page register 1 - ******************************************************************************/ - -/*! - * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW) - * - * Reset value: 0x00U - * - * Provides address bits 15 through 9 of the base address where the current - * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor - * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so - * bits 8 through 0 of the base address are always zero. - */ -typedef union _hw_usb_bdtpage1 -{ - uint8_t U; - struct _hw_usb_bdtpage1_bitfields - { - uint8_t RESERVED0 : 1; /*!< [0] */ - uint8_t BDTBA : 7; /*!< [7:1] */ - } B; -} hw_usb_bdtpage1_t; - -/*! - * @name Constants and macros for entire USB_BDTPAGE1 register - */ -/*@{*/ -#define HW_USB_BDTPAGE1_ADDR(x) ((x) + 0x9CU) - -#define HW_USB_BDTPAGE1(x) (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR(x)) -#define HW_USB_BDTPAGE1_RD(x) (HW_USB_BDTPAGE1(x).U) -#define HW_USB_BDTPAGE1_WR(x, v) (HW_USB_BDTPAGE1(x).U = (v)) -#define HW_USB_BDTPAGE1_SET(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) | (v))) -#define HW_USB_BDTPAGE1_CLR(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) & ~(v))) -#define HW_USB_BDTPAGE1_TOG(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_BDTPAGE1 bitfields - */ - -/*! - * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW) - * - * Provides address bits 15 through 9 of the BDT base address. - */ -/*@{*/ -#define BP_USB_BDTPAGE1_BDTBA (1U) /*!< Bit position for USB_BDTPAGE1_BDTBA. */ -#define BM_USB_BDTPAGE1_BDTBA (0xFEU) /*!< Bit mask for USB_BDTPAGE1_BDTBA. */ -#define BS_USB_BDTPAGE1_BDTBA (7U) /*!< Bit field size in bits for USB_BDTPAGE1_BDTBA. */ - -/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */ -#define BR_USB_BDTPAGE1_BDTBA(x) (HW_USB_BDTPAGE1(x).B.BDTBA) - -/*! @brief Format value for bitfield USB_BDTPAGE1_BDTBA. */ -#define BF_USB_BDTPAGE1_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE1_BDTBA) & BM_USB_BDTPAGE1_BDTBA) - -/*! @brief Set the BDTBA field to a new value. */ -#define BW_USB_BDTPAGE1_BDTBA(x, v) (HW_USB_BDTPAGE1_WR(x, (HW_USB_BDTPAGE1_RD(x) & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v))) -/*@}*/ - -/******************************************************************************* - * HW_USB_FRMNUML - Frame Number register Low - ******************************************************************************/ - -/*! - * @brief HW_USB_FRMNUML - Frame Number register Low (RW) - * - * Reset value: 0x00U - * - * The Frame Number registers (low and high) contain the 11-bit frame number. - * These registers are updated with the current frame number whenever a SOF TOKEN - * is received. - */ -typedef union _hw_usb_frmnuml -{ - uint8_t U; - struct _hw_usb_frmnuml_bitfields - { - uint8_t FRM : 8; /*!< [7:0] */ - } B; -} hw_usb_frmnuml_t; - -/*! - * @name Constants and macros for entire USB_FRMNUML register - */ -/*@{*/ -#define HW_USB_FRMNUML_ADDR(x) ((x) + 0xA0U) - -#define HW_USB_FRMNUML(x) (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR(x)) -#define HW_USB_FRMNUML_RD(x) (HW_USB_FRMNUML(x).U) -#define HW_USB_FRMNUML_WR(x, v) (HW_USB_FRMNUML(x).U = (v)) -#define HW_USB_FRMNUML_SET(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) | (v))) -#define HW_USB_FRMNUML_CLR(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) & ~(v))) -#define HW_USB_FRMNUML_TOG(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_FRMNUML bitfields - */ - -/*! - * @name Register USB_FRMNUML, field FRM[7:0] (RW) - * - * This 8-bit field and the 3-bit field in the Frame Number Register High are - * used to compute the address where the current Buffer Descriptor Table (BDT) - * resides in system memory. - */ -/*@{*/ -#define BP_USB_FRMNUML_FRM (0U) /*!< Bit position for USB_FRMNUML_FRM. */ -#define BM_USB_FRMNUML_FRM (0xFFU) /*!< Bit mask for USB_FRMNUML_FRM. */ -#define BS_USB_FRMNUML_FRM (8U) /*!< Bit field size in bits for USB_FRMNUML_FRM. */ - -/*! @brief Read current value of the USB_FRMNUML_FRM field. */ -#define BR_USB_FRMNUML_FRM(x) (HW_USB_FRMNUML(x).U) - -/*! @brief Format value for bitfield USB_FRMNUML_FRM. */ -#define BF_USB_FRMNUML_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUML_FRM) & BM_USB_FRMNUML_FRM) - -/*! @brief Set the FRM field to a new value. */ -#define BW_USB_FRMNUML_FRM(x, v) (HW_USB_FRMNUML_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_FRMNUMH - Frame Number register High - ******************************************************************************/ - -/*! - * @brief HW_USB_FRMNUMH - Frame Number register High (RW) - * - * Reset value: 0x00U - * - * The Frame Number registers (low and high) contain the 11-bit frame number. - * These registers are updated with the current frame number whenever a SOF TOKEN - * is received. - */ -typedef union _hw_usb_frmnumh -{ - uint8_t U; - struct _hw_usb_frmnumh_bitfields - { - uint8_t FRM : 3; /*!< [2:0] */ - uint8_t RESERVED0 : 5; /*!< [7:3] */ - } B; -} hw_usb_frmnumh_t; - -/*! - * @name Constants and macros for entire USB_FRMNUMH register - */ -/*@{*/ -#define HW_USB_FRMNUMH_ADDR(x) ((x) + 0xA4U) - -#define HW_USB_FRMNUMH(x) (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR(x)) -#define HW_USB_FRMNUMH_RD(x) (HW_USB_FRMNUMH(x).U) -#define HW_USB_FRMNUMH_WR(x, v) (HW_USB_FRMNUMH(x).U = (v)) -#define HW_USB_FRMNUMH_SET(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) | (v))) -#define HW_USB_FRMNUMH_CLR(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) & ~(v))) -#define HW_USB_FRMNUMH_TOG(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_FRMNUMH bitfields - */ - -/*! - * @name Register USB_FRMNUMH, field FRM[2:0] (RW) - * - * This 3-bit field and the 8-bit field in the Frame Number Register Low are - * used to compute the address where the current Buffer Descriptor Table (BDT) - * resides in system memory. - */ -/*@{*/ -#define BP_USB_FRMNUMH_FRM (0U) /*!< Bit position for USB_FRMNUMH_FRM. */ -#define BM_USB_FRMNUMH_FRM (0x07U) /*!< Bit mask for USB_FRMNUMH_FRM. */ -#define BS_USB_FRMNUMH_FRM (3U) /*!< Bit field size in bits for USB_FRMNUMH_FRM. */ - -/*! @brief Read current value of the USB_FRMNUMH_FRM field. */ -#define BR_USB_FRMNUMH_FRM(x) (HW_USB_FRMNUMH(x).B.FRM) - -/*! @brief Format value for bitfield USB_FRMNUMH_FRM. */ -#define BF_USB_FRMNUMH_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUMH_FRM) & BM_USB_FRMNUMH_FRM) - -/*! @brief Set the FRM field to a new value. */ -#define BW_USB_FRMNUMH_FRM(x, v) (HW_USB_FRMNUMH_WR(x, (HW_USB_FRMNUMH_RD(x) & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v))) -/*@}*/ - -/******************************************************************************* - * HW_USB_TOKEN - Token register - ******************************************************************************/ - -/*! - * @brief HW_USB_TOKEN - Token register (RW) - * - * Reset value: 0x00U - * - * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the - * software needs to execute a USB transaction to a peripheral, it writes the - * TOKEN type and endpoint to this register. After this register has been written, - * the USB module begins the specified USB transaction to the address contained in - * the address register. The processor core must always check that the - * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register. - * This ensures that the token commands are not overwritten before they can be - * executed. The address register and endpoint control register 0 are also used when - * performing a token command and therefore must also be written before the - * Token Register. The address register is used to select the USB peripheral address - * transmitted by the token command. The endpoint control register determines the - * handshake and retry policies used during the transfer. - */ -typedef union _hw_usb_token -{ - uint8_t U; - struct _hw_usb_token_bitfields - { - uint8_t TOKENENDPT : 4; /*!< [3:0] */ - uint8_t TOKENPID : 4; /*!< [7:4] */ - } B; -} hw_usb_token_t; - -/*! - * @name Constants and macros for entire USB_TOKEN register - */ -/*@{*/ -#define HW_USB_TOKEN_ADDR(x) ((x) + 0xA8U) - -#define HW_USB_TOKEN(x) (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR(x)) -#define HW_USB_TOKEN_RD(x) (HW_USB_TOKEN(x).U) -#define HW_USB_TOKEN_WR(x, v) (HW_USB_TOKEN(x).U = (v)) -#define HW_USB_TOKEN_SET(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) | (v))) -#define HW_USB_TOKEN_CLR(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) & ~(v))) -#define HW_USB_TOKEN_TOG(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_TOKEN bitfields - */ - -/*! - * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW) - * - * Holds the Endpoint address for the token command. The four bit value written - * must be a valid endpoint. - */ -/*@{*/ -#define BP_USB_TOKEN_TOKENENDPT (0U) /*!< Bit position for USB_TOKEN_TOKENENDPT. */ -#define BM_USB_TOKEN_TOKENENDPT (0x0FU) /*!< Bit mask for USB_TOKEN_TOKENENDPT. */ -#define BS_USB_TOKEN_TOKENENDPT (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENENDPT. */ - -/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */ -#define BR_USB_TOKEN_TOKENENDPT(x) (HW_USB_TOKEN(x).B.TOKENENDPT) - -/*! @brief Format value for bitfield USB_TOKEN_TOKENENDPT. */ -#define BF_USB_TOKEN_TOKENENDPT(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENENDPT) & BM_USB_TOKEN_TOKENENDPT) - -/*! @brief Set the TOKENENDPT field to a new value. */ -#define BW_USB_TOKEN_TOKENENDPT(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v))) -/*@}*/ - -/*! - * @name Register USB_TOKEN, field TOKENPID[7:4] (RW) - * - * Contains the token type executed by the USB module. - * - * Values: - * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction. - * - 1001 - IN Token. USB Module performs an In (RX) transaction. - * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction - */ -/*@{*/ -#define BP_USB_TOKEN_TOKENPID (4U) /*!< Bit position for USB_TOKEN_TOKENPID. */ -#define BM_USB_TOKEN_TOKENPID (0xF0U) /*!< Bit mask for USB_TOKEN_TOKENPID. */ -#define BS_USB_TOKEN_TOKENPID (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENPID. */ - -/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */ -#define BR_USB_TOKEN_TOKENPID(x) (HW_USB_TOKEN(x).B.TOKENPID) - -/*! @brief Format value for bitfield USB_TOKEN_TOKENPID. */ -#define BF_USB_TOKEN_TOKENPID(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENPID) & BM_USB_TOKEN_TOKENPID) - -/*! @brief Set the TOKENPID field to a new value. */ -#define BW_USB_TOKEN_TOKENPID(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v))) -/*@}*/ - -/******************************************************************************* - * HW_USB_SOFTHLD - SOF Threshold register - ******************************************************************************/ - -/*! - * @brief HW_USB_SOFTHLD - SOF Threshold register (RW) - * - * Reset value: 0x00U - * - * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in - * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The - * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with - * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF) - * token is transmitted. The SOF threshold register is used to program the number - * of USB byte times before the SOF to stop initiating token packet transactions. - * This register must be set to a value that ensures that other packets are not - * actively being transmitted when the SOF time counts to zero. When the SOF - * counter reaches the threshold value, no more tokens are transmitted until after the - * SOF has been transmitted. The value programmed into the threshold register - * must reserve enough time to ensure the worst case transaction completes. In - * general the worst case transaction is an IN token followed by a data packet from - * the target followed by the response from the host. The actual time required is - * a function of the maximum packet size on the bus. Typical values for the SOF - * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26; - * 8-byte packets=18. - */ -typedef union _hw_usb_softhld -{ - uint8_t U; - struct _hw_usb_softhld_bitfields - { - uint8_t CNT : 8; /*!< [7:0] */ - } B; -} hw_usb_softhld_t; - -/*! - * @name Constants and macros for entire USB_SOFTHLD register - */ -/*@{*/ -#define HW_USB_SOFTHLD_ADDR(x) ((x) + 0xACU) - -#define HW_USB_SOFTHLD(x) (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR(x)) -#define HW_USB_SOFTHLD_RD(x) (HW_USB_SOFTHLD(x).U) -#define HW_USB_SOFTHLD_WR(x, v) (HW_USB_SOFTHLD(x).U = (v)) -#define HW_USB_SOFTHLD_SET(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) | (v))) -#define HW_USB_SOFTHLD_CLR(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) & ~(v))) -#define HW_USB_SOFTHLD_TOG(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_SOFTHLD bitfields - */ - -/*! - * @name Register USB_SOFTHLD, field CNT[7:0] (RW) - * - * Represents the SOF count threshold in byte times. - */ -/*@{*/ -#define BP_USB_SOFTHLD_CNT (0U) /*!< Bit position for USB_SOFTHLD_CNT. */ -#define BM_USB_SOFTHLD_CNT (0xFFU) /*!< Bit mask for USB_SOFTHLD_CNT. */ -#define BS_USB_SOFTHLD_CNT (8U) /*!< Bit field size in bits for USB_SOFTHLD_CNT. */ - -/*! @brief Read current value of the USB_SOFTHLD_CNT field. */ -#define BR_USB_SOFTHLD_CNT(x) (HW_USB_SOFTHLD(x).U) - -/*! @brief Format value for bitfield USB_SOFTHLD_CNT. */ -#define BF_USB_SOFTHLD_CNT(v) ((uint8_t)((uint8_t)(v) << BP_USB_SOFTHLD_CNT) & BM_USB_SOFTHLD_CNT) - -/*! @brief Set the CNT field to a new value. */ -#define BW_USB_SOFTHLD_CNT(x, v) (HW_USB_SOFTHLD_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_BDTPAGE2 - BDT Page Register 2 - ******************************************************************************/ - -/*! - * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW) - * - * Reset value: 0x00U - * - * Contains an 8-bit value used to compute the address where the current Buffer - * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. - */ -typedef union _hw_usb_bdtpage2 -{ - uint8_t U; - struct _hw_usb_bdtpage2_bitfields - { - uint8_t BDTBA : 8; /*!< [7:0] */ - } B; -} hw_usb_bdtpage2_t; - -/*! - * @name Constants and macros for entire USB_BDTPAGE2 register - */ -/*@{*/ -#define HW_USB_BDTPAGE2_ADDR(x) ((x) + 0xB0U) - -#define HW_USB_BDTPAGE2(x) (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR(x)) -#define HW_USB_BDTPAGE2_RD(x) (HW_USB_BDTPAGE2(x).U) -#define HW_USB_BDTPAGE2_WR(x, v) (HW_USB_BDTPAGE2(x).U = (v)) -#define HW_USB_BDTPAGE2_SET(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) | (v))) -#define HW_USB_BDTPAGE2_CLR(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) & ~(v))) -#define HW_USB_BDTPAGE2_TOG(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_BDTPAGE2 bitfields - */ - -/*! - * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW) - * - * Provides address bits 23 through 16 of the BDT base address that defines the - * location of Buffer Descriptor Table resides in system memory. - */ -/*@{*/ -#define BP_USB_BDTPAGE2_BDTBA (0U) /*!< Bit position for USB_BDTPAGE2_BDTBA. */ -#define BM_USB_BDTPAGE2_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE2_BDTBA. */ -#define BS_USB_BDTPAGE2_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE2_BDTBA. */ - -/*! @brief Read current value of the USB_BDTPAGE2_BDTBA field. */ -#define BR_USB_BDTPAGE2_BDTBA(x) (HW_USB_BDTPAGE2(x).U) - -/*! @brief Format value for bitfield USB_BDTPAGE2_BDTBA. */ -#define BF_USB_BDTPAGE2_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE2_BDTBA) & BM_USB_BDTPAGE2_BDTBA) - -/*! @brief Set the BDTBA field to a new value. */ -#define BW_USB_BDTPAGE2_BDTBA(x, v) (HW_USB_BDTPAGE2_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_BDTPAGE3 - BDT Page Register 3 - ******************************************************************************/ - -/*! - * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW) - * - * Reset value: 0x00U - * - * Contains an 8-bit value used to compute the address where the current Buffer - * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. - */ -typedef union _hw_usb_bdtpage3 -{ - uint8_t U; - struct _hw_usb_bdtpage3_bitfields - { - uint8_t BDTBA : 8; /*!< [7:0] */ - } B; -} hw_usb_bdtpage3_t; - -/*! - * @name Constants and macros for entire USB_BDTPAGE3 register - */ -/*@{*/ -#define HW_USB_BDTPAGE3_ADDR(x) ((x) + 0xB4U) - -#define HW_USB_BDTPAGE3(x) (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR(x)) -#define HW_USB_BDTPAGE3_RD(x) (HW_USB_BDTPAGE3(x).U) -#define HW_USB_BDTPAGE3_WR(x, v) (HW_USB_BDTPAGE3(x).U = (v)) -#define HW_USB_BDTPAGE3_SET(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) | (v))) -#define HW_USB_BDTPAGE3_CLR(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) & ~(v))) -#define HW_USB_BDTPAGE3_TOG(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_BDTPAGE3 bitfields - */ - -/*! - * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW) - * - * Provides address bits 31 through 24 of the BDT base address that defines the - * location of Buffer Descriptor Table resides in system memory. - */ -/*@{*/ -#define BP_USB_BDTPAGE3_BDTBA (0U) /*!< Bit position for USB_BDTPAGE3_BDTBA. */ -#define BM_USB_BDTPAGE3_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE3_BDTBA. */ -#define BS_USB_BDTPAGE3_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE3_BDTBA. */ - -/*! @brief Read current value of the USB_BDTPAGE3_BDTBA field. */ -#define BR_USB_BDTPAGE3_BDTBA(x) (HW_USB_BDTPAGE3(x).U) - -/*! @brief Format value for bitfield USB_BDTPAGE3_BDTBA. */ -#define BF_USB_BDTPAGE3_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE3_BDTBA) & BM_USB_BDTPAGE3_BDTBA) - -/*! @brief Set the BDTBA field to a new value. */ -#define BW_USB_BDTPAGE3_BDTBA(x, v) (HW_USB_BDTPAGE3_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_ENDPTn - Endpoint Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_ENDPTn - Endpoint Control register (RW) - * - * Reset value: 0x00U - * - * Contains the endpoint control bits for each of the 16 endpoints available - * within the USB module for a decoded address. The format for these registers is - * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control - * pipe 0, which is required for all USB functions. Therefore, after a USBRST - * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode - * ENDPT0 is used to determine the handshake, retry and low speed - * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK - * bit should be 1. For Isochronous transfers it should be 0. Common values to - * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, - * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and - * EPTXEN define if an endpoint is enabled and define the direction of the endpoint. - * The endpoint enable/direction control is defined in the following table. - * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint - * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only - * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and - * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP) - * transfers. - */ -typedef union _hw_usb_endptn -{ - uint8_t U; - struct _hw_usb_endptn_bitfields - { - uint8_t EPHSHK : 1; /*!< [0] */ - uint8_t EPSTALL : 1; /*!< [1] */ - uint8_t EPTXEN : 1; /*!< [2] */ - uint8_t EPRXEN : 1; /*!< [3] */ - uint8_t EPCTLDIS : 1; /*!< [4] */ - uint8_t RESERVED0 : 1; /*!< [5] */ - uint8_t RETRYDIS : 1; /*!< [6] */ - uint8_t HOSTWOHUB : 1; /*!< [7] */ - } B; -} hw_usb_endptn_t; - -/*! - * @name Constants and macros for entire USB_ENDPTn register - */ -/*@{*/ -#define HW_USB_ENDPTn_COUNT (16U) - -#define HW_USB_ENDPTn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n))) - -#define HW_USB_ENDPTn(x, n) (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(x, n)) -#define HW_USB_ENDPTn_RD(x, n) (HW_USB_ENDPTn(x, n).U) -#define HW_USB_ENDPTn_WR(x, n, v) (HW_USB_ENDPTn(x, n).U = (v)) -#define HW_USB_ENDPTn_SET(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) | (v))) -#define HW_USB_ENDPTn_CLR(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) & ~(v))) -#define HW_USB_ENDPTn_TOG(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_ENDPTn bitfields - */ - -/*! - * @name Register USB_ENDPTn, field EPHSHK[0] (RW) - * - * When set this bit enables an endpoint to perform handshaking during a - * transaction to this endpoint. This bit is generally 1 unless the endpoint is - * Isochronous. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPHSHK (0U) /*!< Bit position for USB_ENDPTn_EPHSHK. */ -#define BM_USB_ENDPTn_EPHSHK (0x01U) /*!< Bit mask for USB_ENDPTn_EPHSHK. */ -#define BS_USB_ENDPTn_EPHSHK (1U) /*!< Bit field size in bits for USB_ENDPTn_EPHSHK. */ - -/*! @brief Read current value of the USB_ENDPTn_EPHSHK field. */ -#define BR_USB_ENDPTn_EPHSHK(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPHSHK. */ -#define BF_USB_ENDPTn_EPHSHK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPHSHK) & BM_USB_ENDPTn_EPHSHK) - -/*! @brief Set the EPHSHK field to a new value. */ -#define BW_USB_ENDPTn_EPHSHK(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPSTALL[1] (RW) - * - * When set this bit indicates that the endpoint is called. This bit has - * priority over all other control bits in the EndPoint Enable Register, but it is only - * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB - * Module to return a STALL handshake. After an endpoint is stalled it requires - * intervention from the Host Controller. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPSTALL (1U) /*!< Bit position for USB_ENDPTn_EPSTALL. */ -#define BM_USB_ENDPTn_EPSTALL (0x02U) /*!< Bit mask for USB_ENDPTn_EPSTALL. */ -#define BS_USB_ENDPTn_EPSTALL (1U) /*!< Bit field size in bits for USB_ENDPTn_EPSTALL. */ - -/*! @brief Read current value of the USB_ENDPTn_EPSTALL field. */ -#define BR_USB_ENDPTn_EPSTALL(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPSTALL. */ -#define BF_USB_ENDPTn_EPSTALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPSTALL) & BM_USB_ENDPTn_EPSTALL) - -/*! @brief Set the EPSTALL field to a new value. */ -#define BW_USB_ENDPTn_EPSTALL(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPTXEN[2] (RW) - * - * This bit, when set, enables the endpoint for TX transfers. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */ -#define BM_USB_ENDPTn_EPTXEN (0x04U) /*!< Bit mask for USB_ENDPTn_EPTXEN. */ -#define BS_USB_ENDPTn_EPTXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPTXEN. */ - -/*! @brief Read current value of the USB_ENDPTn_EPTXEN field. */ -#define BR_USB_ENDPTn_EPTXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPTXEN. */ -#define BF_USB_ENDPTn_EPTXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPTXEN) & BM_USB_ENDPTn_EPTXEN) - -/*! @brief Set the EPTXEN field to a new value. */ -#define BW_USB_ENDPTn_EPTXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPRXEN[3] (RW) - * - * This bit, when set, enables the endpoint for RX transfers. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */ -#define BM_USB_ENDPTn_EPRXEN (0x08U) /*!< Bit mask for USB_ENDPTn_EPRXEN. */ -#define BS_USB_ENDPTn_EPRXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPRXEN. */ - -/*! @brief Read current value of the USB_ENDPTn_EPRXEN field. */ -#define BR_USB_ENDPTn_EPRXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPRXEN. */ -#define BF_USB_ENDPTn_EPRXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPRXEN) & BM_USB_ENDPTn_EPRXEN) - -/*! @brief Set the EPRXEN field to a new value. */ -#define BW_USB_ENDPTn_EPRXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW) - * - * This bit, when set, disables control (SETUP) transfers. When cleared, control - * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits - * are also set. - */ -/*@{*/ -#define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */ -#define BM_USB_ENDPTn_EPCTLDIS (0x10U) /*!< Bit mask for USB_ENDPTn_EPCTLDIS. */ -#define BS_USB_ENDPTn_EPCTLDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_EPCTLDIS. */ - -/*! @brief Read current value of the USB_ENDPTn_EPCTLDIS field. */ -#define BR_USB_ENDPTn_EPCTLDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS)) - -/*! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS. */ -#define BF_USB_ENDPTn_EPCTLDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPCTLDIS) & BM_USB_ENDPTn_EPCTLDIS) - -/*! @brief Set the EPCTLDIS field to a new value. */ -#define BW_USB_ENDPTn_EPCTLDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field RETRYDIS[6] (RW) - * - * This is a Host mode only bit and is present in the control register for - * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed - * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID - * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When - * this bit is cleared, NAKed transactions are retried in hardware. This bit must - * be set when the host is attempting to poll an interrupt endpoint. - */ -/*@{*/ -#define BP_USB_ENDPTn_RETRYDIS (6U) /*!< Bit position for USB_ENDPTn_RETRYDIS. */ -#define BM_USB_ENDPTn_RETRYDIS (0x40U) /*!< Bit mask for USB_ENDPTn_RETRYDIS. */ -#define BS_USB_ENDPTn_RETRYDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_RETRYDIS. */ - -/*! @brief Read current value of the USB_ENDPTn_RETRYDIS field. */ -#define BR_USB_ENDPTn_RETRYDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS)) - -/*! @brief Format value for bitfield USB_ENDPTn_RETRYDIS. */ -#define BF_USB_ENDPTn_RETRYDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_RETRYDIS) & BM_USB_ENDPTn_RETRYDIS) - -/*! @brief Set the RETRYDIS field to a new value. */ -#define BW_USB_ENDPTn_RETRYDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS) = (v)) -/*@}*/ - -/*! - * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW) - * - * This is a Host mode only field and is present in the control register for - * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a - * directly connected low speed device. When cleared, the host produces the - * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed - * device as required to communicate with a low speed device through a hub. - */ -/*@{*/ -#define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */ -#define BM_USB_ENDPTn_HOSTWOHUB (0x80U) /*!< Bit mask for USB_ENDPTn_HOSTWOHUB. */ -#define BS_USB_ENDPTn_HOSTWOHUB (1U) /*!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB. */ - -/*! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field. */ -#define BR_USB_ENDPTn_HOSTWOHUB(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB)) - -/*! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB. */ -#define BF_USB_ENDPTn_HOSTWOHUB(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_HOSTWOHUB) & BM_USB_ENDPTn_HOSTWOHUB) - -/*! @brief Set the HOSTWOHUB field to a new value. */ -#define BW_USB_ENDPTn_HOSTWOHUB(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_USBCTRL - USB Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_USBCTRL - USB Control register (RW) - * - * Reset value: 0xC0U - */ -typedef union _hw_usb_usbctrl -{ - uint8_t U; - struct _hw_usb_usbctrl_bitfields - { - uint8_t RESERVED0 : 6; /*!< [5:0] */ - uint8_t PDE : 1; /*!< [6] */ - uint8_t SUSP : 1; /*!< [7] */ - } B; -} hw_usb_usbctrl_t; - -/*! - * @name Constants and macros for entire USB_USBCTRL register - */ -/*@{*/ -#define HW_USB_USBCTRL_ADDR(x) ((x) + 0x100U) - -#define HW_USB_USBCTRL(x) (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR(x)) -#define HW_USB_USBCTRL_RD(x) (HW_USB_USBCTRL(x).U) -#define HW_USB_USBCTRL_WR(x, v) (HW_USB_USBCTRL(x).U = (v)) -#define HW_USB_USBCTRL_SET(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) | (v))) -#define HW_USB_USBCTRL_CLR(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) & ~(v))) -#define HW_USB_USBCTRL_TOG(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_USBCTRL bitfields - */ - -/*! - * @name Register USB_USBCTRL, field PDE[6] (RW) - * - * Enables the weak pulldowns on the USB transceiver. - * - * Values: - * - 0 - Weak pulldowns are disabled on D+ and D-. - * - 1 - Weak pulldowns are enabled on D+ and D-. - */ -/*@{*/ -#define BP_USB_USBCTRL_PDE (6U) /*!< Bit position for USB_USBCTRL_PDE. */ -#define BM_USB_USBCTRL_PDE (0x40U) /*!< Bit mask for USB_USBCTRL_PDE. */ -#define BS_USB_USBCTRL_PDE (1U) /*!< Bit field size in bits for USB_USBCTRL_PDE. */ - -/*! @brief Read current value of the USB_USBCTRL_PDE field. */ -#define BR_USB_USBCTRL_PDE(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE)) - -/*! @brief Format value for bitfield USB_USBCTRL_PDE. */ -#define BF_USB_USBCTRL_PDE(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_PDE) & BM_USB_USBCTRL_PDE) - -/*! @brief Set the PDE field to a new value. */ -#define BW_USB_USBCTRL_PDE(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE) = (v)) -/*@}*/ - -/*! - * @name Register USB_USBCTRL, field SUSP[7] (RW) - * - * Places the USB transceiver into the suspend state. - * - * Values: - * - 0 - USB transceiver is not in suspend state. - * - 1 - USB transceiver is in suspend state. - */ -/*@{*/ -#define BP_USB_USBCTRL_SUSP (7U) /*!< Bit position for USB_USBCTRL_SUSP. */ -#define BM_USB_USBCTRL_SUSP (0x80U) /*!< Bit mask for USB_USBCTRL_SUSP. */ -#define BS_USB_USBCTRL_SUSP (1U) /*!< Bit field size in bits for USB_USBCTRL_SUSP. */ - -/*! @brief Read current value of the USB_USBCTRL_SUSP field. */ -#define BR_USB_USBCTRL_SUSP(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP)) - -/*! @brief Format value for bitfield USB_USBCTRL_SUSP. */ -#define BF_USB_USBCTRL_SUSP(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_SUSP) & BM_USB_USBCTRL_SUSP) - -/*! @brief Set the SUSP field to a new value. */ -#define BW_USB_USBCTRL_SUSP(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_OBSERVE - USB OTG Observe register - ******************************************************************************/ - -/*! - * @brief HW_USB_OBSERVE - USB OTG Observe register (RO) - * - * Reset value: 0x50U - * - * Provides visibility on the state of the pull-ups and pull-downs at the - * transceiver. Useful when interfacing to an external OTG control module via a serial - * interface. - */ -typedef union _hw_usb_observe -{ - uint8_t U; - struct _hw_usb_observe_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t DMPD : 1; /*!< [4] */ - uint8_t RESERVED1 : 1; /*!< [5] */ - uint8_t DPPD : 1; /*!< [6] */ - uint8_t DPPU : 1; /*!< [7] */ - } B; -} hw_usb_observe_t; - -/*! - * @name Constants and macros for entire USB_OBSERVE register - */ -/*@{*/ -#define HW_USB_OBSERVE_ADDR(x) ((x) + 0x104U) - -#define HW_USB_OBSERVE(x) (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR(x)) -#define HW_USB_OBSERVE_RD(x) (HW_USB_OBSERVE(x).U) -/*@}*/ - -/* - * Constants & macros for individual USB_OBSERVE bitfields - */ - -/*! - * @name Register USB_OBSERVE, field DMPD[4] (RO) - * - * Provides observability of the D- Pulldown enable at the USB transceiver. - * - * Values: - * - 0 - D- pulldown disabled. - * - 1 - D- pulldown enabled. - */ -/*@{*/ -#define BP_USB_OBSERVE_DMPD (4U) /*!< Bit position for USB_OBSERVE_DMPD. */ -#define BM_USB_OBSERVE_DMPD (0x10U) /*!< Bit mask for USB_OBSERVE_DMPD. */ -#define BS_USB_OBSERVE_DMPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DMPD. */ - -/*! @brief Read current value of the USB_OBSERVE_DMPD field. */ -#define BR_USB_OBSERVE_DMPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DMPD)) -/*@}*/ - -/*! - * @name Register USB_OBSERVE, field DPPD[6] (RO) - * - * Provides observability of the D+ Pulldown enable at the USB transceiver. - * - * Values: - * - 0 - D+ pulldown disabled. - * - 1 - D+ pulldown enabled. - */ -/*@{*/ -#define BP_USB_OBSERVE_DPPD (6U) /*!< Bit position for USB_OBSERVE_DPPD. */ -#define BM_USB_OBSERVE_DPPD (0x40U) /*!< Bit mask for USB_OBSERVE_DPPD. */ -#define BS_USB_OBSERVE_DPPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPD. */ - -/*! @brief Read current value of the USB_OBSERVE_DPPD field. */ -#define BR_USB_OBSERVE_DPPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPD)) -/*@}*/ - -/*! - * @name Register USB_OBSERVE, field DPPU[7] (RO) - * - * Provides observability of the D+ Pullup enable at the USB transceiver. - * - * Values: - * - 0 - D+ pullup disabled. - * - 1 - D+ pullup enabled. - */ -/*@{*/ -#define BP_USB_OBSERVE_DPPU (7U) /*!< Bit position for USB_OBSERVE_DPPU. */ -#define BM_USB_OBSERVE_DPPU (0x80U) /*!< Bit mask for USB_OBSERVE_DPPU. */ -#define BS_USB_OBSERVE_DPPU (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPU. */ - -/*! @brief Read current value of the USB_OBSERVE_DPPU field. */ -#define BR_USB_OBSERVE_DPPU(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPU)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CONTROL - USB OTG Control register - ******************************************************************************/ - -/*! - * @brief HW_USB_CONTROL - USB OTG Control register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_usb_control -{ - uint8_t U; - struct _hw_usb_control_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t DPPULLUPNONOTG : 1; /*!< [4] */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_usb_control_t; - -/*! - * @name Constants and macros for entire USB_CONTROL register - */ -/*@{*/ -#define HW_USB_CONTROL_ADDR(x) ((x) + 0x108U) - -#define HW_USB_CONTROL(x) (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR(x)) -#define HW_USB_CONTROL_RD(x) (HW_USB_CONTROL(x).U) -#define HW_USB_CONTROL_WR(x, v) (HW_USB_CONTROL(x).U = (v)) -#define HW_USB_CONTROL_SET(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) | (v))) -#define HW_USB_CONTROL_CLR(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) & ~(v))) -#define HW_USB_CONTROL_TOG(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CONTROL bitfields - */ - -/*! - * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW) - * - * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG - * device mode. - * - * Values: - * - 0 - DP Pullup in non-OTG device mode is not enabled. - * - 1 - DP Pullup in non-OTG device mode is enabled. - */ -/*@{*/ -#define BP_USB_CONTROL_DPPULLUPNONOTG (4U) /*!< Bit position for USB_CONTROL_DPPULLUPNONOTG. */ -#define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) /*!< Bit mask for USB_CONTROL_DPPULLUPNONOTG. */ -#define BS_USB_CONTROL_DPPULLUPNONOTG (1U) /*!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG. */ - -/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */ -#define BR_USB_CONTROL_DPPULLUPNONOTG(x) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG)) - -/*! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG. */ -#define BF_USB_CONTROL_DPPULLUPNONOTG(v) ((uint8_t)((uint8_t)(v) << BP_USB_CONTROL_DPPULLUPNONOTG) & BM_USB_CONTROL_DPPULLUPNONOTG) - -/*! @brief Set the DPPULLUPNONOTG field to a new value. */ -#define BW_USB_CONTROL_DPPULLUPNONOTG(x, v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_USBTRC0 - USB Transceiver Control register 0 - ******************************************************************************/ - -/*! - * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW) - * - * Reset value: 0x00U - * - * Includes signals for basic operation of the on-chip USB Full Speed - * transceiver and configuration of the USB data connection that are not otherwise included - * in the USB Full Speed controller registers. - */ -typedef union _hw_usb_usbtrc0 -{ - uint8_t U; - struct _hw_usb_usbtrc0_bitfields - { - uint8_t USB_RESUME_INT : 1; /*!< [0] USB Asynchronous Interrupt */ - uint8_t SYNC_DET : 1; /*!< [1] Synchronous USB Interrupt Detect */ - uint8_t USB_CLK_RECOVERY_INT : 1; /*!< [2] Combined USB Clock - * Recovery interrupt status */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t USBRESMEN : 1; /*!< [5] Asynchronous Resume Interrupt Enable - * */ - uint8_t RESERVED1 : 1; /*!< [6] */ - uint8_t USBRESET : 1; /*!< [7] USB Reset */ - } B; -} hw_usb_usbtrc0_t; - -/*! - * @name Constants and macros for entire USB_USBTRC0 register - */ -/*@{*/ -#define HW_USB_USBTRC0_ADDR(x) ((x) + 0x10CU) - -#define HW_USB_USBTRC0(x) (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR(x)) -#define HW_USB_USBTRC0_RD(x) (HW_USB_USBTRC0(x).U) -#define HW_USB_USBTRC0_WR(x, v) (HW_USB_USBTRC0(x).U = (v)) -#define HW_USB_USBTRC0_SET(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) | (v))) -#define HW_USB_USBTRC0_CLR(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) & ~(v))) -#define HW_USB_USBTRC0_TOG(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_USBTRC0 bitfields - */ - -/*! - * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO) - * - * Values: - * - 0 - No interrupt was generated. - * - 1 - Interrupt was generated because of the USB asynchronous interrupt. - */ -/*@{*/ -#define BP_USB_USBTRC0_USB_RESUME_INT (0U) /*!< Bit position for USB_USBTRC0_USB_RESUME_INT. */ -#define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) /*!< Bit mask for USB_USBTRC0_USB_RESUME_INT. */ -#define BS_USB_USBTRC0_USB_RESUME_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT. */ - -/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */ -#define BR_USB_USBTRC0_USB_RESUME_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_RESUME_INT)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field SYNC_DET[1] (RO) - * - * Values: - * - 0 - Synchronous interrupt has not been detected. - * - 1 - Synchronous interrupt has been detected. - */ -/*@{*/ -#define BP_USB_USBTRC0_SYNC_DET (1U) /*!< Bit position for USB_USBTRC0_SYNC_DET. */ -#define BM_USB_USBTRC0_SYNC_DET (0x02U) /*!< Bit mask for USB_USBTRC0_SYNC_DET. */ -#define BS_USB_USBTRC0_SYNC_DET (1U) /*!< Bit field size in bits for USB_USBTRC0_SYNC_DET. */ - -/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */ -#define BR_USB_USBTRC0_SYNC_DET(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_SYNC_DET)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO) - * - * This read-only field will be set to value high at 1'b1 when any of USB clock - * recovery interrupt conditions are detected and those interrupts are unmasked. - * For customer use the only unmasked USB clock recovery interrupt condition - * results from an overflow of the frequency trim setting values indicating that the - * frequency trim calculated is out of the adjustment range of the IRC48M output - * clock. To clear this bit after it has been set, Write 0xFF to register - * USB_CLK_RECOVER_INT_STATUS. - */ -/*@{*/ -#define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) /*!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ -#define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) /*!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ -#define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT. */ - -/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */ -#define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_CLK_RECOVERY_INT)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field USBRESMEN[5] (RW) - * - * This bit, when set, allows the USB module to send an asynchronous wakeup - * event to the MCU upon detection of resume signaling on the USB bus. The MCU then - * re-enables clocks to the USB module. It is used for low-power suspend mode when - * USB module clocks are stopped or the USB transceiver is in Suspend mode. - * Async wakeup only works in device mode. - * - * Values: - * - 0 - USB asynchronous wakeup from suspend mode disabled. - * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous - * resume interrupt differs from the synchronous resume interrupt in that it - * asynchronously detects K-state using the unfiltered state of the D+ and D- - * pins. This interrupt should only be enabled when the Transceiver is - * suspended. - */ -/*@{*/ -#define BP_USB_USBTRC0_USBRESMEN (5U) /*!< Bit position for USB_USBTRC0_USBRESMEN. */ -#define BM_USB_USBTRC0_USBRESMEN (0x20U) /*!< Bit mask for USB_USBTRC0_USBRESMEN. */ -#define BS_USB_USBTRC0_USBRESMEN (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESMEN. */ - -/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */ -#define BR_USB_USBTRC0_USBRESMEN(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN)) - -/*! @brief Format value for bitfield USB_USBTRC0_USBRESMEN. */ -#define BF_USB_USBTRC0_USBRESMEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESMEN) & BM_USB_USBTRC0_USBRESMEN) - -/*! @brief Set the USBRESMEN field to a new value. */ -#define BW_USB_USBTRC0_USBRESMEN(x, v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN) = (v)) -/*@}*/ - -/*! - * @name Register USB_USBTRC0, field USBRESET[7] (WO) - * - * Generates a hard reset to USBOTG. After this bit is set and the reset occurs, - * this bit is automatically cleared. This bit is always read as zero. Wait two - * USB clock cycles after setting this bit. - * - * Values: - * - 0 - Normal USB module operation. - * - 1 - Returns the USB module to its reset state. - */ -/*@{*/ -#define BP_USB_USBTRC0_USBRESET (7U) /*!< Bit position for USB_USBTRC0_USBRESET. */ -#define BM_USB_USBTRC0_USBRESET (0x80U) /*!< Bit mask for USB_USBTRC0_USBRESET. */ -#define BS_USB_USBTRC0_USBRESET (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESET. */ - -/*! @brief Format value for bitfield USB_USBTRC0_USBRESET. */ -#define BF_USB_USBTRC0_USBRESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESET) & BM_USB_USBTRC0_USBRESET) -/*@}*/ - -/******************************************************************************* - * HW_USB_USBFRMADJUST - Frame Adjust Register - ******************************************************************************/ - -/*! - * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW) - * - * Reset value: 0x00U - */ -typedef union _hw_usb_usbfrmadjust -{ - uint8_t U; - struct _hw_usb_usbfrmadjust_bitfields - { - uint8_t ADJ : 8; /*!< [7:0] Frame Adjustment */ - } B; -} hw_usb_usbfrmadjust_t; - -/*! - * @name Constants and macros for entire USB_USBFRMADJUST register - */ -/*@{*/ -#define HW_USB_USBFRMADJUST_ADDR(x) ((x) + 0x114U) - -#define HW_USB_USBFRMADJUST(x) (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR(x)) -#define HW_USB_USBFRMADJUST_RD(x) (HW_USB_USBFRMADJUST(x).U) -#define HW_USB_USBFRMADJUST_WR(x, v) (HW_USB_USBFRMADJUST(x).U = (v)) -#define HW_USB_USBFRMADJUST_SET(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) | (v))) -#define HW_USB_USBFRMADJUST_CLR(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) & ~(v))) -#define HW_USB_USBFRMADJUST_TOG(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_USBFRMADJUST bitfields - */ - -/*! - * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW) - * - * In Host mode, the frame adjustment is a twos complement number that adjusts - * the period of each USB frame in 12-MHz clock periods. A SOF is normally - * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this - * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock. - * Changes to the ADJ bit take effect at the next start of the next frame. - */ -/*@{*/ -#define BP_USB_USBFRMADJUST_ADJ (0U) /*!< Bit position for USB_USBFRMADJUST_ADJ. */ -#define BM_USB_USBFRMADJUST_ADJ (0xFFU) /*!< Bit mask for USB_USBFRMADJUST_ADJ. */ -#define BS_USB_USBFRMADJUST_ADJ (8U) /*!< Bit field size in bits for USB_USBFRMADJUST_ADJ. */ - -/*! @brief Read current value of the USB_USBFRMADJUST_ADJ field. */ -#define BR_USB_USBFRMADJUST_ADJ(x) (HW_USB_USBFRMADJUST(x).U) - -/*! @brief Format value for bitfield USB_USBFRMADJUST_ADJ. */ -#define BF_USB_USBFRMADJUST_ADJ(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBFRMADJUST_ADJ) & BM_USB_USBFRMADJUST_ADJ) - -/*! @brief Set the ADJ field to a new value. */ -#define BW_USB_USBFRMADJUST_ADJ(x, v) (HW_USB_USBFRMADJUST_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW) - * - * Reset value: 0x00U - * - * Signals in this register control the crystal-less USB clock mode in which the - * internal IRC48M oscillator is tuned to match the clock extracted from the - * incoming USB data stream. The IRC48M internal oscillator module must be enabled - * in register USB_CLK_RECOVER_IRC_EN for this mode. - */ -typedef union _hw_usb_clk_recover_ctrl -{ - uint8_t U; - struct _hw_usb_clk_recover_ctrl_bitfields - { - uint8_t RESERVED0 : 5; /*!< [4:0] */ - uint8_t RESTART_IFRTRIM_EN : 1; /*!< [5] Restart from IFR trim value - * */ - uint8_t RESET_RESUME_ROUGH_EN : 1; /*!< [6] Reset/resume to rough - * phase enable */ - uint8_t CLOCK_RECOVER_EN : 1; /*!< [7] Crystal-less USB enable */ - } B; -} hw_usb_clk_recover_ctrl_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_CTRL_ADDR(x) ((x) + 0x140U) - -#define HW_USB_CLK_RECOVER_CTRL(x) (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR(x)) -#define HW_USB_CLK_RECOVER_CTRL_RD(x) (HW_USB_CLK_RECOVER_CTRL(x).U) -#define HW_USB_CLK_RECOVER_CTRL_WR(x, v) (HW_USB_CLK_RECOVER_CTRL(x).U = (v)) -#define HW_USB_CLK_RECOVER_CTRL_SET(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_CTRL_CLR(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_CTRL_TOG(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW) - * - * IRC48 has a default trim fine value whose default value is factory trimmed - * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz - * and keeps updating the trim fine value accordingly - * - * Values: - * - 0 - Trim fine adjustment always works based on the previous updated trim - * fine value (default) - * - 1 - Trim fine restarts from the IFR trim value whenever - * bus_reset/bus_resume is detected or module enable is desasserted - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ -#define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ -#define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */ -#define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */ -#define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) - -/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW) - * - * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock. - * It has two phases after user enables clock_recover_en bit, rough phase and - * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine - * value is different during these two phases. The step in rough phase is larger - * than that in tracking phase. Switch back to rough stage whenever USB bus reset - * or bus resume occurs. - * - * Values: - * - 0 - Always works in tracking phase after the 1st time rough to track - * transition (default) - * - 1 - Go back to rough stage whenever bus reset or bus resume occurs - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ -#define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ -#define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */ -#define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */ -#define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) - -/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW) - * - * This bit must be enabled if user wants to use the crystal-less USB mode for - * the Full Speed USB controller and transceiver. This bit should not be set for - * USB host mode or OTG. - * - * Values: - * - 0 - Disable clock recovery block (default) - * - 1 - Enable clock recovery block - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) /*!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ -#define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ -#define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */ -#define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */ -#define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) - -/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW) - * - * Reset value: 0x01U - * - * Controls basic operation of the on-chip IRC48M module used to produce nominal - * 48MHz clocks for USB crystal-less operation and other functions. See - * additional information about the IRC48M operation in the Clock Distribution chapter. - */ -typedef union _hw_usb_clk_recover_irc_en -{ - uint8_t U; - struct _hw_usb_clk_recover_irc_en_bitfields - { - uint8_t REG_EN : 1; /*!< [0] IRC48M regulator enable */ - uint8_t IRC_EN : 1; /*!< [1] IRC48M enable */ - uint8_t RESERVED0 : 6; /*!< [7:2] */ - } B; -} hw_usb_clk_recover_irc_en_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_IRC_EN_ADDR(x) ((x) + 0x144U) - -#define HW_USB_CLK_RECOVER_IRC_EN(x) (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR(x)) -#define HW_USB_CLK_RECOVER_IRC_EN_RD(x) (HW_USB_CLK_RECOVER_IRC_EN(x).U) -#define HW_USB_CLK_RECOVER_IRC_EN_WR(x, v) (HW_USB_CLK_RECOVER_IRC_EN(x).U = (v)) -#define HW_USB_CLK_RECOVER_IRC_EN_SET(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_IRC_EN_CLR(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_IRC_EN_TOG(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW) - * - * This bit is used to enable the local analog regulator for IRC48Mhz module. - * This bit must be set if user wants to use the crystal-less USB clock - * configuration. - * - * Values: - * - 0 - IRC48M local regulator is disabled - * - 1 - IRC48M local regulator is enabled (default) - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN. */ -#define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN. */ -#define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */ -#define BR_USB_CLK_RECOVER_IRC_EN_REG_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN. */ -#define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN) - -/*! @brief Set the REG_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v)) -/*@}*/ - -/*! - * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW) - * - * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for - * crystal-less USB. It can only be used for FS USB device mode operation. This - * bit must be set before using the crystal-less USB clock configuration. - * - * Values: - * - 0 - Disable the IRC48M module (default) - * - 1 - Enable the IRC48M module - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ -#define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ -#define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */ -#define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN. */ -#define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN) - -/*! @brief Set the IRC_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C) - * - * Reset value: 0x00U - * - * A Write operation with value high at 1'b1 on any combination of individual - * bits will clear those bits. - */ -typedef union _hw_usb_clk_recover_int_status -{ - uint8_t U; - struct _hw_usb_clk_recover_int_status_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t OVF_ERROR : 1; /*!< [4] */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_usb_clk_recover_int_status_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x) ((x) + 0x15CU) - -#define HW_USB_CLK_RECOVER_INT_STATUS(x) (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x)) -#define HW_USB_CLK_RECOVER_INT_STATUS_RD(x) (HW_USB_CLK_RECOVER_INT_STATUS(x).U) -#define HW_USB_CLK_RECOVER_INT_STATUS_WR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS(x).U = (v)) -#define HW_USB_CLK_RECOVER_INT_STATUS_SET(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_INT_STATUS_CLR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_INT_STATUS_TOG(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C) - * - * Indicates that the USB clock recovery algorithm has detected that the - * frequency trim adjustment needed for the IRC48M output clock is outside the available - * TRIM_FINE adjustment range for the IRC48M module. - * - * Values: - * - 0 - No interrupt is reported - * - 1 - Unmasked interrupt has been generated - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) /*!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ -#define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ -#define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */ -#define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */ -#define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) - -/*! @brief Set the OVF_ERROR field to a new value. */ -#define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_usb_t - module struct - ******************************************************************************/ -/*! - * @brief All USB module registers. - */ -#pragma pack(1) -typedef struct _hw_usb -{ - __I hw_usb_perid_t PERID; /*!< [0x0] Peripheral ID register */ - uint8_t _reserved0[3]; - __I hw_usb_idcomp_t IDCOMP; /*!< [0x4] Peripheral ID Complement register */ - uint8_t _reserved1[3]; - __I hw_usb_rev_t REV; /*!< [0x8] Peripheral Revision register */ - uint8_t _reserved2[3]; - __I hw_usb_addinfo_t ADDINFO; /*!< [0xC] Peripheral Additional Info register */ - uint8_t _reserved3[3]; - __IO hw_usb_otgistat_t OTGISTAT; /*!< [0x10] OTG Interrupt Status register */ - uint8_t _reserved4[3]; - __IO hw_usb_otgicr_t OTGICR; /*!< [0x14] OTG Interrupt Control register */ - uint8_t _reserved5[3]; - __IO hw_usb_otgstat_t OTGSTAT; /*!< [0x18] OTG Status register */ - uint8_t _reserved6[3]; - __IO hw_usb_otgctl_t OTGCTL; /*!< [0x1C] OTG Control register */ - uint8_t _reserved7[99]; - __IO hw_usb_istat_t ISTAT; /*!< [0x80] Interrupt Status register */ - uint8_t _reserved8[3]; - __IO hw_usb_inten_t INTEN; /*!< [0x84] Interrupt Enable register */ - uint8_t _reserved9[3]; - __IO hw_usb_errstat_t ERRSTAT; /*!< [0x88] Error Interrupt Status register */ - uint8_t _reserved10[3]; - __IO hw_usb_erren_t ERREN; /*!< [0x8C] Error Interrupt Enable register */ - uint8_t _reserved11[3]; - __I hw_usb_stat_t STAT; /*!< [0x90] Status register */ - uint8_t _reserved12[3]; - __IO hw_usb_ctl_t CTL; /*!< [0x94] Control register */ - uint8_t _reserved13[3]; - __IO hw_usb_addr_t ADDR; /*!< [0x98] Address register */ - uint8_t _reserved14[3]; - __IO hw_usb_bdtpage1_t BDTPAGE1; /*!< [0x9C] BDT Page register 1 */ - uint8_t _reserved15[3]; - __IO hw_usb_frmnuml_t FRMNUML; /*!< [0xA0] Frame Number register Low */ - uint8_t _reserved16[3]; - __IO hw_usb_frmnumh_t FRMNUMH; /*!< [0xA4] Frame Number register High */ - uint8_t _reserved17[3]; - __IO hw_usb_token_t TOKEN; /*!< [0xA8] Token register */ - uint8_t _reserved18[3]; - __IO hw_usb_softhld_t SOFTHLD; /*!< [0xAC] SOF Threshold register */ - uint8_t _reserved19[3]; - __IO hw_usb_bdtpage2_t BDTPAGE2; /*!< [0xB0] BDT Page Register 2 */ - uint8_t _reserved20[3]; - __IO hw_usb_bdtpage3_t BDTPAGE3; /*!< [0xB4] BDT Page Register 3 */ - uint8_t _reserved21[11]; - struct { - __IO hw_usb_endptn_t ENDPTn; /*!< [0xC0] Endpoint Control register */ - uint8_t _reserved0[3]; - } ENDPOINT[16]; - __IO hw_usb_usbctrl_t USBCTRL; /*!< [0x100] USB Control register */ - uint8_t _reserved22[3]; - __I hw_usb_observe_t OBSERVE; /*!< [0x104] USB OTG Observe register */ - uint8_t _reserved23[3]; - __IO hw_usb_control_t CONTROL; /*!< [0x108] USB OTG Control register */ - uint8_t _reserved24[3]; - __IO hw_usb_usbtrc0_t USBTRC0; /*!< [0x10C] USB Transceiver Control register 0 */ - uint8_t _reserved25[7]; - __IO hw_usb_usbfrmadjust_t USBFRMADJUST; /*!< [0x114] Frame Adjust Register */ - uint8_t _reserved26[43]; - __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; /*!< [0x140] USB Clock recovery control */ - uint8_t _reserved27[3]; - __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; /*!< [0x144] IRC48M oscillator enable register */ - uint8_t _reserved28[23]; - __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; /*!< [0x15C] Clock recovery separated interrupt status */ -} hw_usb_t; -#pragma pack() - -/*! @brief Macro to access all USB registers. */ -/*! @param x USB module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_USB(USB0_BASE). */ -#define HW_USB(x) (*(hw_usb_t *)(x)) - -#endif /* __HW_USB_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usbdcd.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usbdcd.h deleted file mode 100644 index f54f659a59e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usbdcd.h +++ /dev/null @@ -1,938 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_USBDCD_REGISTERS_H__ -#define __HW_USBDCD_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 USBDCD - * - * USB Device Charger Detection module - * - * Registers defined in this header file: - * - HW_USBDCD_CONTROL - Control register - * - HW_USBDCD_CLOCK - Clock register - * - HW_USBDCD_STATUS - Status register - * - HW_USBDCD_TIMER0 - TIMER0 register - * - HW_USBDCD_TIMER1 - TIMER1 register - * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register - * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register - * - * - hw_usbdcd_t - Struct containing all module registers. - */ - -#define HW_USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */ - -/******************************************************************************* - * HW_USBDCD_CONTROL - Control register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_CONTROL - Control register (RW) - * - * Reset value: 0x00010000U - * - * Contains the control and interrupt bit fields. - */ -typedef union _hw_usbdcd_control -{ - uint32_t U; - struct _hw_usbdcd_control_bitfields - { - uint32_t IACK : 1; /*!< [0] Interrupt Acknowledge */ - uint32_t RESERVED0 : 7; /*!< [7:1] */ - uint32_t IF : 1; /*!< [8] Interrupt Flag */ - uint32_t RESERVED1 : 7; /*!< [15:9] */ - uint32_t IE : 1; /*!< [16] Interrupt Enable */ - uint32_t BC12 : 1; /*!< [17] */ - uint32_t RESERVED2 : 6; /*!< [23:18] */ - uint32_t START : 1; /*!< [24] Start Change Detection Sequence */ - uint32_t SR : 1; /*!< [25] Software Reset */ - uint32_t RESERVED3 : 6; /*!< [31:26] */ - } B; -} hw_usbdcd_control_t; - -/*! - * @name Constants and macros for entire USBDCD_CONTROL register - */ -/*@{*/ -#define HW_USBDCD_CONTROL_ADDR(x) ((x) + 0x0U) - -#define HW_USBDCD_CONTROL(x) (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x)) -#define HW_USBDCD_CONTROL_RD(x) (HW_USBDCD_CONTROL(x).U) -#define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v)) -#define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) | (v))) -#define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v))) -#define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_CONTROL bitfields - */ - -/*! - * @name Register USBDCD_CONTROL, field IACK[0] (WORZ) - * - * Determines whether the interrupt is cleared. - * - * Values: - * - 0 - Do not clear the interrupt. - * - 1 - Clear the IF bit (interrupt flag). - */ -/*@{*/ -#define BP_USBDCD_CONTROL_IACK (0U) /*!< Bit position for USBDCD_CONTROL_IACK. */ -#define BM_USBDCD_CONTROL_IACK (0x00000001U) /*!< Bit mask for USBDCD_CONTROL_IACK. */ -#define BS_USBDCD_CONTROL_IACK (1U) /*!< Bit field size in bits for USBDCD_CONTROL_IACK. */ - -/*! @brief Format value for bitfield USBDCD_CONTROL_IACK. */ -#define BF_USBDCD_CONTROL_IACK(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_IACK) & BM_USBDCD_CONTROL_IACK) - -/*! @brief Set the IACK field to a new value. */ -#define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v)) -/*@}*/ - -/*! - * @name Register USBDCD_CONTROL, field IF[8] (RO) - * - * Determines whether an interrupt is pending. - * - * Values: - * - 0 - No interrupt is pending. - * - 1 - An interrupt is pending. - */ -/*@{*/ -#define BP_USBDCD_CONTROL_IF (8U) /*!< Bit position for USBDCD_CONTROL_IF. */ -#define BM_USBDCD_CONTROL_IF (0x00000100U) /*!< Bit mask for USBDCD_CONTROL_IF. */ -#define BS_USBDCD_CONTROL_IF (1U) /*!< Bit field size in bits for USBDCD_CONTROL_IF. */ - -/*! @brief Read current value of the USBDCD_CONTROL_IF field. */ -#define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF)) -/*@}*/ - -/*! - * @name Register USBDCD_CONTROL, field IE[16] (RW) - * - * Enables/disables interrupts to the system. - * - * Values: - * - 0 - Disable interrupts to the system. - * - 1 - Enable interrupts to the system. - */ -/*@{*/ -#define BP_USBDCD_CONTROL_IE (16U) /*!< Bit position for USBDCD_CONTROL_IE. */ -#define BM_USBDCD_CONTROL_IE (0x00010000U) /*!< Bit mask for USBDCD_CONTROL_IE. */ -#define BS_USBDCD_CONTROL_IE (1U) /*!< Bit field size in bits for USBDCD_CONTROL_IE. */ - -/*! @brief Read current value of the USBDCD_CONTROL_IE field. */ -#define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE)) - -/*! @brief Format value for bitfield USBDCD_CONTROL_IE. */ -#define BF_USBDCD_CONTROL_IE(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_IE) & BM_USBDCD_CONTROL_IE) - -/*! @brief Set the IE field to a new value. */ -#define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v)) -/*@}*/ - -/*! - * @name Register USBDCD_CONTROL, field BC12[17] (RW) - * - * BC1.2 compatibility. This bit cannot be changed after start detection. - * - * Values: - * - 0 - Compatible with BC1.1 (default) - * - 1 - Compatible with BC1.2 - */ -/*@{*/ -#define BP_USBDCD_CONTROL_BC12 (17U) /*!< Bit position for USBDCD_CONTROL_BC12. */ -#define BM_USBDCD_CONTROL_BC12 (0x00020000U) /*!< Bit mask for USBDCD_CONTROL_BC12. */ -#define BS_USBDCD_CONTROL_BC12 (1U) /*!< Bit field size in bits for USBDCD_CONTROL_BC12. */ - -/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */ -#define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12)) - -/*! @brief Format value for bitfield USBDCD_CONTROL_BC12. */ -#define BF_USBDCD_CONTROL_BC12(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_BC12) & BM_USBDCD_CONTROL_BC12) - -/*! @brief Set the BC12 field to a new value. */ -#define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v)) -/*@}*/ - -/*! - * @name Register USBDCD_CONTROL, field START[24] (WORZ) - * - * Determines whether the charger detection sequence is initiated. - * - * Values: - * - 0 - Do not start the sequence. Writes of this value have no effect. - * - 1 - Initiate the charger detection sequence. If the sequence is already - * running, writes of this value have no effect. - */ -/*@{*/ -#define BP_USBDCD_CONTROL_START (24U) /*!< Bit position for USBDCD_CONTROL_START. */ -#define BM_USBDCD_CONTROL_START (0x01000000U) /*!< Bit mask for USBDCD_CONTROL_START. */ -#define BS_USBDCD_CONTROL_START (1U) /*!< Bit field size in bits for USBDCD_CONTROL_START. */ - -/*! @brief Format value for bitfield USBDCD_CONTROL_START. */ -#define BF_USBDCD_CONTROL_START(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_START) & BM_USBDCD_CONTROL_START) - -/*! @brief Set the START field to a new value. */ -#define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v)) -/*@}*/ - -/*! - * @name Register USBDCD_CONTROL, field SR[25] (WORZ) - * - * Determines whether a software reset is performed. - * - * Values: - * - 0 - Do not perform a software reset. - * - 1 - Perform a software reset. - */ -/*@{*/ -#define BP_USBDCD_CONTROL_SR (25U) /*!< Bit position for USBDCD_CONTROL_SR. */ -#define BM_USBDCD_CONTROL_SR (0x02000000U) /*!< Bit mask for USBDCD_CONTROL_SR. */ -#define BS_USBDCD_CONTROL_SR (1U) /*!< Bit field size in bits for USBDCD_CONTROL_SR. */ - -/*! @brief Format value for bitfield USBDCD_CONTROL_SR. */ -#define BF_USBDCD_CONTROL_SR(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_SR) & BM_USBDCD_CONTROL_SR) - -/*! @brief Set the SR field to a new value. */ -#define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_USBDCD_CLOCK - Clock register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_CLOCK - Clock register (RW) - * - * Reset value: 0x000000C1U - */ -typedef union _hw_usbdcd_clock -{ - uint32_t U; - struct _hw_usbdcd_clock_bitfields - { - uint32_t CLOCK_UNIT : 1; /*!< [0] Unit of Measurement Encoding for - * Clock Speed */ - uint32_t RESERVED0 : 1; /*!< [1] */ - uint32_t CLOCK_SPEED : 10; /*!< [11:2] Numerical Value of Clock Speed - * in Binary */ - uint32_t RESERVED1 : 20; /*!< [31:12] */ - } B; -} hw_usbdcd_clock_t; - -/*! - * @name Constants and macros for entire USBDCD_CLOCK register - */ -/*@{*/ -#define HW_USBDCD_CLOCK_ADDR(x) ((x) + 0x4U) - -#define HW_USBDCD_CLOCK(x) (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x)) -#define HW_USBDCD_CLOCK_RD(x) (HW_USBDCD_CLOCK(x).U) -#define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v)) -#define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) | (v))) -#define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v))) -#define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_CLOCK bitfields - */ - -/*! - * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW) - * - * Specifies the unit of measure for the clock speed. - * - * Values: - * - 0 - kHz Speed (between 1 kHz and 1023 kHz) - * - 1 - MHz Speed (between 1 MHz and 1023 MHz) - */ -/*@{*/ -#define BP_USBDCD_CLOCK_CLOCK_UNIT (0U) /*!< Bit position for USBDCD_CLOCK_CLOCK_UNIT. */ -#define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) /*!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT. */ -#define BS_USBDCD_CLOCK_CLOCK_UNIT (1U) /*!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT. */ - -/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */ -#define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT)) - -/*! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT. */ -#define BF_USBDCD_CLOCK_CLOCK_UNIT(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CLOCK_CLOCK_UNIT) & BM_USBDCD_CLOCK_CLOCK_UNIT) - -/*! @brief Set the CLOCK_UNIT field to a new value. */ -#define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v)) -/*@}*/ - -/*! - * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW) - * - * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to - * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples - * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz: - * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100) - * For 500 kHz: 0b01_1111_0100 (500) - */ -/*@{*/ -#define BP_USBDCD_CLOCK_CLOCK_SPEED (2U) /*!< Bit position for USBDCD_CLOCK_CLOCK_SPEED. */ -#define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) /*!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED. */ -#define BS_USBDCD_CLOCK_CLOCK_SPEED (10U) /*!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED. */ - -/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */ -#define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED) - -/*! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED. */ -#define BF_USBDCD_CLOCK_CLOCK_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CLOCK_CLOCK_SPEED) & BM_USBDCD_CLOCK_CLOCK_SPEED) - -/*! @brief Set the CLOCK_SPEED field to a new value. */ -#define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v))) -/*@}*/ - -/******************************************************************************* - * HW_USBDCD_STATUS - Status register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_STATUS - Status register (RO) - * - * Reset value: 0x00000000U - * - * Provides the current state of the module for system software monitoring. - */ -typedef union _hw_usbdcd_status -{ - uint32_t U; - struct _hw_usbdcd_status_bitfields - { - uint32_t RESERVED0 : 16; /*!< [15:0] */ - uint32_t SEQ_RES : 2; /*!< [17:16] Charger Detection Sequence Results - * */ - uint32_t SEQ_STAT : 2; /*!< [19:18] Charger Detection Sequence Status - * */ - uint32_t ERR : 1; /*!< [20] Error Flag */ - uint32_t TO : 1; /*!< [21] Timeout Flag */ - uint32_t ACTIVE : 1; /*!< [22] Active Status Indicator */ - uint32_t RESERVED1 : 9; /*!< [31:23] */ - } B; -} hw_usbdcd_status_t; - -/*! - * @name Constants and macros for entire USBDCD_STATUS register - */ -/*@{*/ -#define HW_USBDCD_STATUS_ADDR(x) ((x) + 0x8U) - -#define HW_USBDCD_STATUS(x) (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x)) -#define HW_USBDCD_STATUS_RD(x) (HW_USBDCD_STATUS(x).U) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_STATUS bitfields - */ - -/*! - * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO) - * - * Reports how the charger detection is attached. - * - * Values: - * - 00 - No results to report. - * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only - * 2.5 mA (max) until connected. - * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0: - * Attached to either a charging host or a dedicated charger. The charger type - * detection has not completed. 1: Attached to a charging host. The charger - * type detection has completed. - * - 11 - Attached to a dedicated charger. - */ -/*@{*/ -#define BP_USBDCD_STATUS_SEQ_RES (16U) /*!< Bit position for USBDCD_STATUS_SEQ_RES. */ -#define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) /*!< Bit mask for USBDCD_STATUS_SEQ_RES. */ -#define BS_USBDCD_STATUS_SEQ_RES (2U) /*!< Bit field size in bits for USBDCD_STATUS_SEQ_RES. */ - -/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */ -#define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES) -/*@}*/ - -/*! - * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO) - * - * Indicates the status of the charger detection sequence. - * - * Values: - * - 00 - The module is either not enabled, or the module is enabled but the - * data pins have not yet been detected. - * - 01 - Data pin contact detection is complete. - * - 10 - Charging port detection is complete. - * - 11 - Charger type detection is complete. - */ -/*@{*/ -#define BP_USBDCD_STATUS_SEQ_STAT (18U) /*!< Bit position for USBDCD_STATUS_SEQ_STAT. */ -#define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) /*!< Bit mask for USBDCD_STATUS_SEQ_STAT. */ -#define BS_USBDCD_STATUS_SEQ_STAT (2U) /*!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT. */ - -/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */ -#define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT) -/*@}*/ - -/*! - * @name Register USBDCD_STATUS, field ERR[20] (RO) - * - * Indicates whether there is an error in the detection sequence. - * - * Values: - * - 0 - No sequence errors. - * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine - * the phase in which the error occurred. - */ -/*@{*/ -#define BP_USBDCD_STATUS_ERR (20U) /*!< Bit position for USBDCD_STATUS_ERR. */ -#define BM_USBDCD_STATUS_ERR (0x00100000U) /*!< Bit mask for USBDCD_STATUS_ERR. */ -#define BS_USBDCD_STATUS_ERR (1U) /*!< Bit field size in bits for USBDCD_STATUS_ERR. */ - -/*! @brief Read current value of the USBDCD_STATUS_ERR field. */ -#define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR)) -/*@}*/ - -/*! - * @name Register USBDCD_STATUS, field TO[21] (RO) - * - * Indicates whether the detection sequence has passed the timeout threshhold. - * - * Values: - * - 0 - The detection sequence has not been running for over 1 s. - * - 1 - It has been over 1 s since the data pin contact was detected and - * debounced. - */ -/*@{*/ -#define BP_USBDCD_STATUS_TO (21U) /*!< Bit position for USBDCD_STATUS_TO. */ -#define BM_USBDCD_STATUS_TO (0x00200000U) /*!< Bit mask for USBDCD_STATUS_TO. */ -#define BS_USBDCD_STATUS_TO (1U) /*!< Bit field size in bits for USBDCD_STATUS_TO. */ - -/*! @brief Read current value of the USBDCD_STATUS_TO field. */ -#define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO)) -/*@}*/ - -/*! - * @name Register USBDCD_STATUS, field ACTIVE[22] (RO) - * - * Indicates whether the sequence is running. - * - * Values: - * - 0 - The sequence is not running. - * - 1 - The sequence is running. - */ -/*@{*/ -#define BP_USBDCD_STATUS_ACTIVE (22U) /*!< Bit position for USBDCD_STATUS_ACTIVE. */ -#define BM_USBDCD_STATUS_ACTIVE (0x00400000U) /*!< Bit mask for USBDCD_STATUS_ACTIVE. */ -#define BS_USBDCD_STATUS_ACTIVE (1U) /*!< Bit field size in bits for USBDCD_STATUS_ACTIVE. */ - -/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */ -#define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE)) -/*@}*/ - -/******************************************************************************* - * HW_USBDCD_TIMER0 - TIMER0 register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW) - * - * Reset value: 0x00100000U - * - * TIMER0 has an TSEQ_INIT field that represents the system latency in ms. - * Latency is measured from the time when VBUS goes active until the time system - * software initiates charger detection sequence in USBDCD module. When software sets - * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized - * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery - * Charging Specification requires the entire sequence, including TSEQ_INIT, to be - * completed in 1s or less. - */ -typedef union _hw_usbdcd_timer0 -{ - uint32_t U; - struct _hw_usbdcd_timer0_bitfields - { - uint32_t TUNITCON : 12; /*!< [11:0] Unit Connection Timer Elapse (in - * ms) */ - uint32_t RESERVED0 : 4; /*!< [15:12] */ - uint32_t TSEQ_INIT : 10; /*!< [25:16] Sequence Initiation Time */ - uint32_t RESERVED1 : 6; /*!< [31:26] */ - } B; -} hw_usbdcd_timer0_t; - -/*! - * @name Constants and macros for entire USBDCD_TIMER0 register - */ -/*@{*/ -#define HW_USBDCD_TIMER0_ADDR(x) ((x) + 0x10U) - -#define HW_USBDCD_TIMER0(x) (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x)) -#define HW_USBDCD_TIMER0_RD(x) (HW_USBDCD_TIMER0(x).U) -#define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v)) -#define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) | (v))) -#define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v))) -#define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_TIMER0 bitfields - */ - -/*! - * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO) - * - * Displays the amount of elapsed time since the event of setting the START bit - * plus the value of TSEQ_INIT. The timer is automatically initialized with the - * value of TSEQ_INIT before starting to count. This timer enables compliance with - * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging - * Specification. If the timer reaches the one second limit, the module triggers - * an interrupt and sets the error flag STATUS[ERR]. The timer continues - * counting throughout the charger detection sequence, even when control has been passed - * to software. As long as the module is active, the timer continues to count - * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not - * rollover to zero. A software reset clears the timer. - */ -/*@{*/ -#define BP_USBDCD_TIMER0_TUNITCON (0U) /*!< Bit position for USBDCD_TIMER0_TUNITCON. */ -#define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) /*!< Bit mask for USBDCD_TIMER0_TUNITCON. */ -#define BS_USBDCD_TIMER0_TUNITCON (12U) /*!< Bit field size in bits for USBDCD_TIMER0_TUNITCON. */ - -/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */ -#define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON) -/*@}*/ - -/*! - * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW) - * - * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS - * goes active to the time system software initiates the charger detection - * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit - * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid - * values are 0-1023, but the USB Battery Charging Specification requires the - * entire sequence, including TSEQ_INIT, to be completed in 1s or less. - */ -/*@{*/ -#define BP_USBDCD_TIMER0_TSEQ_INIT (16U) /*!< Bit position for USBDCD_TIMER0_TSEQ_INIT. */ -#define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER0_TSEQ_INIT. */ -#define BS_USBDCD_TIMER0_TSEQ_INIT (10U) /*!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT. */ - -/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */ -#define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT) - -/*! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT. */ -#define BF_USBDCD_TIMER0_TSEQ_INIT(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER0_TSEQ_INIT) & BM_USBDCD_TIMER0_TSEQ_INIT) - -/*! @brief Set the TSEQ_INIT field to a new value. */ -#define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v))) -/*@}*/ - -/******************************************************************************* - * HW_USBDCD_TIMER1 - TIMER1 register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW) - * - * Reset value: 0x000A0028U - * - * TIMER1 contains timing parameters. Note that register values can be written - * that are not compliant with the USB Battery Charging Specification, so care - * should be taken when overwriting the default values. - */ -typedef union _hw_usbdcd_timer1 -{ - uint32_t U; - struct _hw_usbdcd_timer1_bitfields - { - uint32_t TVDPSRC_ON : 10; /*!< [9:0] Time Period Comparator Enabled */ - uint32_t RESERVED0 : 6; /*!< [15:10] */ - uint32_t TDCD_DBNC : 10; /*!< [25:16] Time Period to Debounce D+ - * Signal */ - uint32_t RESERVED1 : 6; /*!< [31:26] */ - } B; -} hw_usbdcd_timer1_t; - -/*! - * @name Constants and macros for entire USBDCD_TIMER1 register - */ -/*@{*/ -#define HW_USBDCD_TIMER1_ADDR(x) ((x) + 0x14U) - -#define HW_USBDCD_TIMER1(x) (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x)) -#define HW_USBDCD_TIMER1_RD(x) (HW_USBDCD_TIMER1(x).U) -#define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v)) -#define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) | (v))) -#define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v))) -#define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_TIMER1 bitfields - */ - -/*! - * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW) - * - * This timing parameter is used after detection of the data pin. See "Charging - * Port Detection". Valid values are 1-1023, but the USB Battery Charging - * Specification requires a minimum value of 40 ms. - */ -/*@{*/ -#define BP_USBDCD_TIMER1_TVDPSRC_ON (0U) /*!< Bit position for USBDCD_TIMER1_TVDPSRC_ON. */ -#define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) /*!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON. */ -#define BS_USBDCD_TIMER1_TVDPSRC_ON (10U) /*!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON. */ - -/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */ -#define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON) - -/*! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON. */ -#define BF_USBDCD_TIMER1_TVDPSRC_ON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER1_TVDPSRC_ON) & BM_USBDCD_TIMER1_TVDPSRC_ON) - -/*! @brief Set the TVDPSRC_ON field to a new value. */ -#define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v))) -/*@}*/ - -/*! - * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW) - * - * Sets the time period (ms) to debounce the D+ signal during the data pin - * contact detection phase. See "Debouncing the data pin contact" Valid values are - * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10 - * ms. - */ -/*@{*/ -#define BP_USBDCD_TIMER1_TDCD_DBNC (16U) /*!< Bit position for USBDCD_TIMER1_TDCD_DBNC. */ -#define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER1_TDCD_DBNC. */ -#define BS_USBDCD_TIMER1_TDCD_DBNC (10U) /*!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC. */ - -/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */ -#define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC) - -/*! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC. */ -#define BF_USBDCD_TIMER1_TDCD_DBNC(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER1_TDCD_DBNC) & BM_USBDCD_TIMER1_TDCD_DBNC) - -/*! @brief Set the TDCD_DBNC field to a new value. */ -#define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v))) -/*@}*/ - -/******************************************************************************* - * HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW) - * - * Reset value: 0x00280001U - * - * TIMER2_BC11 contains timing parameters for USB Battery Charging - * Specification, v1.1. Register values can be written that are not compliant with the USB - * Battery Charging Specification, so care should be taken when overwriting the - * default values. - */ -typedef union _hw_usbdcd_timer2_bc11 -{ - uint32_t U; - struct _hw_usbdcd_timer2_bc11_bitfields - { - uint32_t CHECK_DM : 4; /*!< [3:0] Time Before Check of D- Line */ - uint32_t RESERVED0 : 12; /*!< [15:4] */ - uint32_t TVDPSRC_CON : 10; /*!< [25:16] Time Period Before Enabling - * D+ Pullup */ - uint32_t RESERVED1 : 6; /*!< [31:26] */ - } B; -} hw_usbdcd_timer2_bc11_t; - -/*! - * @name Constants and macros for entire USBDCD_TIMER2_BC11 register - */ -/*@{*/ -#define HW_USBDCD_TIMER2_BC11_ADDR(x) ((x) + 0x18U) - -#define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x)) -#define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U) -#define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v)) -#define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) | (v))) -#define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v))) -#define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields - */ - -/*! - * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW) - * - * Sets the amount of time (in ms) that the module waits after the device - * connects to the USB bus until checking the state of the D- line to determine the - * type of charging port. See "Charger Type Detection." Valid values are 1-15ms. - */ -/*@{*/ -#define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) /*!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM. */ -#define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) /*!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM. */ -#define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) /*!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM. */ - -/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */ -#define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM) - -/*! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM. */ -#define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC11_CHECK_DM) & BM_USBDCD_TIMER2_BC11_CHECK_DM) - -/*! @brief Set the CHECK_DM field to a new value. */ -#define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v))) -/*@}*/ - -/*! - * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW) - * - * Sets the time period (ms) that the module waits after charging port detection - * before system software must enable the D+ pullup to connect to the USB host. - * Valid values are 1-1023, but the USB Battery Charging Specification requires a - * minimum value of 40 ms. - */ -/*@{*/ -#define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) /*!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON. */ -#define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON. */ -#define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON. */ - -/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */ -#define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON) - -/*! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON. */ -#define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) - -/*! @brief Set the TVDPSRC_CON field to a new value. */ -#define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v))) -/*@}*/ -/******************************************************************************* - * HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register - ******************************************************************************/ - -/*! - * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW) - * - * Reset value: 0x00010028U - * - * TIMER2_BC12 contains timing parameters for USB Battery Charging - * Specification, v1.2. Register values can be written that are not compliant with the USB - * Battery Charging Specification, so care should be taken when overwriting the - * default values. - */ -typedef union _hw_usbdcd_timer2_bc12 -{ - uint32_t U; - struct _hw_usbdcd_timer2_bc12_bitfields - { - uint32_t TVDMSRC_ON : 10; /*!< [9:0] */ - uint32_t RESERVED0 : 6; /*!< [15:10] */ - uint32_t TWAIT_AFTER_PRD : 10; /*!< [25:16] */ - uint32_t RESERVED1 : 6; /*!< [31:26] */ - } B; -} hw_usbdcd_timer2_bc12_t; - -/*! - * @name Constants and macros for entire USBDCD_TIMER2_BC12 register - */ -/*@{*/ -#define HW_USBDCD_TIMER2_BC12_ADDR(x) ((x) + 0x18U) - -#define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x)) -#define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U) -#define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v)) -#define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) | (v))) -#define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v))) -#define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields - */ - -/*! - * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW) - * - * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid - * values are 0-40ms. - */ -/*@{*/ -#define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) /*!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON. */ -#define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) /*!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON. */ -#define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON. */ - -/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */ -#define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON) - -/*! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON. */ -#define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) - -/*! @brief Set the TVDMSRC_ON field to a new value. */ -#define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v))) -/*@}*/ - -/*! - * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW) - * - * Sets the amount of time (in ms) that the module waits after primary detection - * before start to secondary detection. Valid values are 1-1023ms. Default is - * 1ms. - */ -/*@{*/ -#define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) /*!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */ -#define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */ -#define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */ - -/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */ -#define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD) - -/*! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */ -#define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) - -/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */ -#define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v))) -/*@}*/ - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/******************************************************************************* - * hw_usbdcd_t - module struct - ******************************************************************************/ -/*! - * @brief All USBDCD module registers. - */ -#pragma pack(1) -typedef struct _hw_usbdcd -{ - __IO hw_usbdcd_control_t CONTROL; /*!< [0x0] Control register */ - __IO hw_usbdcd_clock_t CLOCK; /*!< [0x4] Clock register */ - __I hw_usbdcd_status_t STATUS; /*!< [0x8] Status register */ - uint8_t _reserved0[4]; - __IO hw_usbdcd_timer0_t TIMER0; /*!< [0x10] TIMER0 register */ - __IO hw_usbdcd_timer1_t TIMER1; /*!< [0x14] TIMER1 register */ - union { - __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; /*!< [0x18] TIMER2_BC11 register */ - __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; /*!< [0x18] TIMER2_BC12 register */ - }; -} hw_usbdcd_t; -#pragma pack() - -/*! @brief Macro to access all USBDCD registers. */ -/*! @param x USBDCD module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_USBDCD(USBDCD_BASE). */ -#define HW_USBDCD(x) (*(hw_usbdcd_t *)(x)) - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -#endif /* __HW_USBDCD_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_vref.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_vref.h deleted file mode 100644 index d08c8901535..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_vref.h +++ /dev/null @@ -1,387 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_VREF_REGISTERS_H__ -#define __HW_VREF_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 VREF - * - * Voltage Reference - * - * Registers defined in this header file: - * - HW_VREF_TRM - VREF Trim Register - * - HW_VREF_SC - VREF Status and Control Register - * - * - hw_vref_t - Struct containing all module registers. - */ - -#define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */ - -/******************************************************************************* - * HW_VREF_TRM - VREF Trim Register - ******************************************************************************/ - -/*! - * @brief HW_VREF_TRM - VREF Trim Register (RW) - * - * Reset value: 0x00U - * - * This register contains bits that contain the trim data for the Voltage - * Reference. - */ -typedef union _hw_vref_trm -{ - uint8_t U; - struct _hw_vref_trm_bitfields - { - uint8_t TRIM : 6; /*!< [5:0] Trim bits */ - uint8_t CHOPEN : 1; /*!< [6] Chop oscillator enable. When set, - * internal chopping operation is enabled and the internal analog offset will be - * minimized. */ - uint8_t RESERVED0 : 1; /*!< [7] */ - } B; -} hw_vref_trm_t; - -/*! - * @name Constants and macros for entire VREF_TRM register - */ -/*@{*/ -#define HW_VREF_TRM_ADDR(x) ((x) + 0x0U) - -#define HW_VREF_TRM(x) (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x)) -#define HW_VREF_TRM_RD(x) (HW_VREF_TRM(x).U) -#define HW_VREF_TRM_WR(x, v) (HW_VREF_TRM(x).U = (v)) -#define HW_VREF_TRM_SET(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) | (v))) -#define HW_VREF_TRM_CLR(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v))) -#define HW_VREF_TRM_TOG(x, v) (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual VREF_TRM bitfields - */ - -/*! - * @name Register VREF_TRM, field TRIM[5:0] (RW) - * - * These bits change the resulting VREF by approximately +/- 0.5 mV for each - * step. Min = minimum and max = maximum voltage reference output. For minimum and - * maximum voltage reference output values, refer to the Data Sheet for this chip. - * - * Values: - * - 000000 - Min - * - 111111 - Max - */ -/*@{*/ -#define BP_VREF_TRM_TRIM (0U) /*!< Bit position for VREF_TRM_TRIM. */ -#define BM_VREF_TRM_TRIM (0x3FU) /*!< Bit mask for VREF_TRM_TRIM. */ -#define BS_VREF_TRM_TRIM (6U) /*!< Bit field size in bits for VREF_TRM_TRIM. */ - -/*! @brief Read current value of the VREF_TRM_TRIM field. */ -#define BR_VREF_TRM_TRIM(x) (HW_VREF_TRM(x).B.TRIM) - -/*! @brief Format value for bitfield VREF_TRM_TRIM. */ -#define BF_VREF_TRM_TRIM(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM) - -/*! @brief Set the TRIM field to a new value. */ -#define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v))) -/*@}*/ - -/*! - * @name Register VREF_TRM, field CHOPEN[6] (RW) - * - * This bit is set during factory trimming of the VREF voltage. This bit should - * be written to 1 to achieve the performance stated in the data sheet. - * - * Values: - * - 0 - Chop oscillator is disabled. - * - 1 - Chop oscillator is enabled. - */ -/*@{*/ -#define BP_VREF_TRM_CHOPEN (6U) /*!< Bit position for VREF_TRM_CHOPEN. */ -#define BM_VREF_TRM_CHOPEN (0x40U) /*!< Bit mask for VREF_TRM_CHOPEN. */ -#define BS_VREF_TRM_CHOPEN (1U) /*!< Bit field size in bits for VREF_TRM_CHOPEN. */ - -/*! @brief Read current value of the VREF_TRM_CHOPEN field. */ -#define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN)) - -/*! @brief Format value for bitfield VREF_TRM_CHOPEN. */ -#define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN) - -/*! @brief Set the CHOPEN field to a new value. */ -#define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_VREF_SC - VREF Status and Control Register - ******************************************************************************/ - -/*! - * @brief HW_VREF_SC - VREF Status and Control Register (RW) - * - * Reset value: 0x00U - * - * This register contains the control bits used to enable the internal voltage - * reference and to select the buffer mode to be used. - */ -typedef union _hw_vref_sc -{ - uint8_t U; - struct _hw_vref_sc_bitfields - { - uint8_t MODE_LV : 2; /*!< [1:0] Buffer Mode selection */ - uint8_t VREFST : 1; /*!< [2] Internal Voltage Reference stable */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ - uint8_t ICOMPEN : 1; /*!< [5] Second order curvature compensation - * enable */ - uint8_t REGEN : 1; /*!< [6] Regulator enable */ - uint8_t VREFEN : 1; /*!< [7] Internal Voltage Reference enable */ - } B; -} hw_vref_sc_t; - -/*! - * @name Constants and macros for entire VREF_SC register - */ -/*@{*/ -#define HW_VREF_SC_ADDR(x) ((x) + 0x1U) - -#define HW_VREF_SC(x) (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x)) -#define HW_VREF_SC_RD(x) (HW_VREF_SC(x).U) -#define HW_VREF_SC_WR(x, v) (HW_VREF_SC(x).U = (v)) -#define HW_VREF_SC_SET(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) | (v))) -#define HW_VREF_SC_CLR(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v))) -#define HW_VREF_SC_TOG(x, v) (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual VREF_SC bitfields - */ - -/*! - * @name Register VREF_SC, field MODE_LV[1:0] (RW) - * - * These bits select the buffer modes for the Voltage Reference module. - * - * Values: - * - 00 - Bandgap on only, for stabilization and startup - * - 01 - High power buffer mode enabled - * - 10 - Low-power buffer mode enabled - * - 11 - Reserved - */ -/*@{*/ -#define BP_VREF_SC_MODE_LV (0U) /*!< Bit position for VREF_SC_MODE_LV. */ -#define BM_VREF_SC_MODE_LV (0x03U) /*!< Bit mask for VREF_SC_MODE_LV. */ -#define BS_VREF_SC_MODE_LV (2U) /*!< Bit field size in bits for VREF_SC_MODE_LV. */ - -/*! @brief Read current value of the VREF_SC_MODE_LV field. */ -#define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV) - -/*! @brief Format value for bitfield VREF_SC_MODE_LV. */ -#define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV) - -/*! @brief Set the MODE_LV field to a new value. */ -#define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v))) -/*@}*/ - -/*! - * @name Register VREF_SC, field VREFST[2] (RO) - * - * This bit indicates that the bandgap reference within the Voltage Reference - * module has completed its startup and stabilization. - * - * Values: - * - 0 - The module is disabled or not stable. - * - 1 - The module is stable. - */ -/*@{*/ -#define BP_VREF_SC_VREFST (2U) /*!< Bit position for VREF_SC_VREFST. */ -#define BM_VREF_SC_VREFST (0x04U) /*!< Bit mask for VREF_SC_VREFST. */ -#define BS_VREF_SC_VREFST (1U) /*!< Bit field size in bits for VREF_SC_VREFST. */ - -/*! @brief Read current value of the VREF_SC_VREFST field. */ -#define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST)) -/*@}*/ - -/*! - * @name Register VREF_SC, field ICOMPEN[5] (RW) - * - * This bit is set during factory trimming of the VREF voltage. This bit should - * be written to 1 to achieve the performance stated in the data sheet. - * - * Values: - * - 0 - Disabled - * - 1 - Enabled - */ -/*@{*/ -#define BP_VREF_SC_ICOMPEN (5U) /*!< Bit position for VREF_SC_ICOMPEN. */ -#define BM_VREF_SC_ICOMPEN (0x20U) /*!< Bit mask for VREF_SC_ICOMPEN. */ -#define BS_VREF_SC_ICOMPEN (1U) /*!< Bit field size in bits for VREF_SC_ICOMPEN. */ - -/*! @brief Read current value of the VREF_SC_ICOMPEN field. */ -#define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN)) - -/*! @brief Format value for bitfield VREF_SC_ICOMPEN. */ -#define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN) - -/*! @brief Set the ICOMPEN field to a new value. */ -#define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v)) -/*@}*/ - -/*! - * @name Register VREF_SC, field REGEN[6] (RW) - * - * This bit is used to enable the internal 1.75 V regulator to produce a - * constant internal voltage supply in order to reduce the sensitivity to external - * supply noise and variation. If it is desired to keep the regulator enabled in very - * low power modes, refer to the Chip Configuration details for a description on - * how this can be achieved. This bit is set during factory trimming of the VREF - * voltage. This bit should be written to 1 to achieve the performance stated in - * the data sheet. - * - * Values: - * - 0 - Internal 1.75 V regulator is disabled. - * - 1 - Internal 1.75 V regulator is enabled. - */ -/*@{*/ -#define BP_VREF_SC_REGEN (6U) /*!< Bit position for VREF_SC_REGEN. */ -#define BM_VREF_SC_REGEN (0x40U) /*!< Bit mask for VREF_SC_REGEN. */ -#define BS_VREF_SC_REGEN (1U) /*!< Bit field size in bits for VREF_SC_REGEN. */ - -/*! @brief Read current value of the VREF_SC_REGEN field. */ -#define BR_VREF_SC_REGEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN)) - -/*! @brief Format value for bitfield VREF_SC_REGEN. */ -#define BF_VREF_SC_REGEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN) - -/*! @brief Set the REGEN field to a new value. */ -#define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v)) -/*@}*/ - -/*! - * @name Register VREF_SC, field VREFEN[7] (RW) - * - * This bit is used to enable the bandgap reference within the Voltage Reference - * module. After the VREF is enabled, turning off the clock to the VREF module - * via the corresponding clock gate register will not disable the VREF. VREF must - * be disabled via this VREFEN bit. - * - * Values: - * - 0 - The module is disabled. - * - 1 - The module is enabled. - */ -/*@{*/ -#define BP_VREF_SC_VREFEN (7U) /*!< Bit position for VREF_SC_VREFEN. */ -#define BM_VREF_SC_VREFEN (0x80U) /*!< Bit mask for VREF_SC_VREFEN. */ -#define BS_VREF_SC_VREFEN (1U) /*!< Bit field size in bits for VREF_SC_VREFEN. */ - -/*! @brief Read current value of the VREF_SC_VREFEN field. */ -#define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN)) - -/*! @brief Format value for bitfield VREF_SC_VREFEN. */ -#define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN) - -/*! @brief Set the VREFEN field to a new value. */ -#define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v)) -/*@}*/ - -/******************************************************************************* - * hw_vref_t - module struct - ******************************************************************************/ -/*! - * @brief All VREF module registers. - */ -#pragma pack(1) -typedef struct _hw_vref -{ - __IO hw_vref_trm_t TRM; /*!< [0x0] VREF Trim Register */ - __IO hw_vref_sc_t SC; /*!< [0x1] VREF Status and Control Register */ -} hw_vref_t; -#pragma pack() - -/*! @brief Macro to access all VREF registers. */ -/*! @param x VREF module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_VREF(VREF_BASE). */ -#define HW_VREF(x) (*(hw_vref_t *)(x)) - -#endif /* __HW_VREF_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_wdog.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_wdog.h deleted file mode 100644 index c8afba6fedc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_wdog.h +++ /dev/null @@ -1,1156 +0,0 @@ -/* -** ################################################################### -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140604 -** -** Abstract: -** Extension to the CMSIS register access layer header. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/* - * WARNING! DO NOT EDIT THIS FILE DIRECTLY! - * - * This file was generated automatically and any changes may be lost. - */ -#ifndef __HW_WDOG_REGISTERS_H__ -#define __HW_WDOG_REGISTERS_H__ - -#include "MK64F12.h" -#include "fsl_bitaccess.h" - -/* - * MK64F12 WDOG - * - * Generation 2008 Watchdog Timer - * - * Registers defined in this header file: - * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High - * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low - * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High - * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low - * - HW_WDOG_WINH - Watchdog Window Register High - * - HW_WDOG_WINL - Watchdog Window Register Low - * - HW_WDOG_REFRESH - Watchdog Refresh register - * - HW_WDOG_UNLOCK - Watchdog Unlock register - * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High - * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low - * - HW_WDOG_RSTCNT - Watchdog Reset Count register - * - HW_WDOG_PRESC - Watchdog Prescaler register - * - * - hw_wdog_t - Struct containing all module registers. - */ - -#define HW_WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */ - -/******************************************************************************* - * HW_WDOG_STCTRLH - Watchdog Status and Control Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW) - * - * Reset value: 0x01D3U - */ -typedef union _hw_wdog_stctrlh -{ - uint16_t U; - struct _hw_wdog_stctrlh_bitfields - { - uint16_t WDOGEN : 1; /*!< [0] */ - uint16_t CLKSRC : 1; /*!< [1] */ - uint16_t IRQRSTEN : 1; /*!< [2] */ - uint16_t WINEN : 1; /*!< [3] */ - uint16_t ALLOWUPDATE : 1; /*!< [4] */ - uint16_t DBGEN : 1; /*!< [5] */ - uint16_t STOPEN : 1; /*!< [6] */ - uint16_t WAITEN : 1; /*!< [7] */ - uint16_t RESERVED0 : 2; /*!< [9:8] */ - uint16_t TESTWDOG : 1; /*!< [10] */ - uint16_t TESTSEL : 1; /*!< [11] */ - uint16_t BYTESEL : 2; /*!< [13:12] */ - uint16_t DISTESTWDOG : 1; /*!< [14] */ - uint16_t RESERVED1 : 1; /*!< [15] */ - } B; -} hw_wdog_stctrlh_t; - -/*! - * @name Constants and macros for entire WDOG_STCTRLH register - */ -/*@{*/ -#define HW_WDOG_STCTRLH_ADDR(x) ((x) + 0x0U) - -#define HW_WDOG_STCTRLH(x) (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR(x)) -#define HW_WDOG_STCTRLH_RD(x) (HW_WDOG_STCTRLH(x).U) -#define HW_WDOG_STCTRLH_WR(x, v) (HW_WDOG_STCTRLH(x).U = (v)) -#define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) | (v))) -#define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v))) -#define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_STCTRLH bitfields - */ - -/*! - * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW) - * - * Enables or disables the WDOG's operation. In the disabled state, the watchdog - * timer is kept in the reset state, but the other exception conditions can - * still trigger a reset/interrupt. A change in the value of this bit must be held - * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. - * - * Values: - * - 0 - WDOG is disabled. - * - 1 - WDOG is enabled. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_WDOGEN (0U) /*!< Bit position for WDOG_STCTRLH_WDOGEN. */ -#define BM_WDOG_STCTRLH_WDOGEN (0x0001U) /*!< Bit mask for WDOG_STCTRLH_WDOGEN. */ -#define BS_WDOG_STCTRLH_WDOGEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */ -#define BR_WDOG_STCTRLH_WDOGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. */ -#define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN) - -/*! @brief Set the WDOGEN field to a new value. */ -#define BW_WDOG_STCTRLH_WDOGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW) - * - * Selects clock source for the WDOG timer and other internal timing operations. - * - * Values: - * - 0 - WDOG clock sourced from LPO . - * - 1 - WDOG clock sourced from alternate clock source. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_CLKSRC (1U) /*!< Bit position for WDOG_STCTRLH_CLKSRC. */ -#define BM_WDOG_STCTRLH_CLKSRC (0x0002U) /*!< Bit mask for WDOG_STCTRLH_CLKSRC. */ -#define BS_WDOG_STCTRLH_CLKSRC (1U) /*!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. */ - -/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */ -#define BR_WDOG_STCTRLH_CLKSRC(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. */ -#define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC) - -/*! @brief Set the CLKSRC field to a new value. */ -#define BW_WDOG_STCTRLH_CLKSRC(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW) - * - * Used to enable the debug breadcrumbs feature. A change in this bit is updated - * immediately, as opposed to updating after WCT. - * - * Values: - * - 0 - WDOG time-out generates reset only. - * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates - * a reset. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_IRQRSTEN (2U) /*!< Bit position for WDOG_STCTRLH_IRQRSTEN. */ -#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /*!< Bit mask for WDOG_STCTRLH_IRQRSTEN. */ -#define BS_WDOG_STCTRLH_IRQRSTEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */ -#define BR_WDOG_STCTRLH_IRQRSTEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. */ -#define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN) - -/*! @brief Set the IRQRSTEN field to a new value. */ -#define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field WINEN[3] (RW) - * - * Enables Windowing mode. - * - * Values: - * - 0 - Windowing mode is disabled. - * - 1 - Windowing mode is enabled. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_WINEN (3U) /*!< Bit position for WDOG_STCTRLH_WINEN. */ -#define BM_WDOG_STCTRLH_WINEN (0x0008U) /*!< Bit mask for WDOG_STCTRLH_WINEN. */ -#define BS_WDOG_STCTRLH_WINEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WINEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */ -#define BR_WDOG_STCTRLH_WINEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_WINEN. */ -#define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN) - -/*! @brief Set the WINEN field to a new value. */ -#define BW_WDOG_STCTRLH_WINEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW) - * - * Enables updates to watchdog write-once registers, after the reset-triggered - * initial configuration window (WCT) closes, through unlock sequence. - * - * Values: - * - 0 - No further updates allowed to WDOG write-once registers. - * - 1 - WDOG write-once registers can be unlocked for updating. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) /*!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. */ -#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /*!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. */ -#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) /*!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. */ - -/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */ -#define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. */ -#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE) - -/*! @brief Set the ALLOWUPDATE field to a new value. */ -#define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field DBGEN[5] (RW) - * - * Enables or disables WDOG in Debug mode. - * - * Values: - * - 0 - WDOG is disabled in CPU Debug mode. - * - 1 - WDOG is enabled in CPU Debug mode. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_DBGEN (5U) /*!< Bit position for WDOG_STCTRLH_DBGEN. */ -#define BM_WDOG_STCTRLH_DBGEN (0x0020U) /*!< Bit mask for WDOG_STCTRLH_DBGEN. */ -#define BS_WDOG_STCTRLH_DBGEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_DBGEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */ -#define BR_WDOG_STCTRLH_DBGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. */ -#define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN) - -/*! @brief Set the DBGEN field to a new value. */ -#define BW_WDOG_STCTRLH_DBGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field STOPEN[6] (RW) - * - * Enables or disables WDOG in Stop mode. - * - * Values: - * - 0 - WDOG is disabled in CPU Stop mode. - * - 1 - WDOG is enabled in CPU Stop mode. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_STOPEN (6U) /*!< Bit position for WDOG_STCTRLH_STOPEN. */ -#define BM_WDOG_STCTRLH_STOPEN (0x0040U) /*!< Bit mask for WDOG_STCTRLH_STOPEN. */ -#define BS_WDOG_STCTRLH_STOPEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_STOPEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */ -#define BR_WDOG_STCTRLH_STOPEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. */ -#define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN) - -/*! @brief Set the STOPEN field to a new value. */ -#define BW_WDOG_STCTRLH_STOPEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field WAITEN[7] (RW) - * - * Enables or disables WDOG in Wait mode. - * - * Values: - * - 0 - WDOG is disabled in CPU Wait mode. - * - 1 - WDOG is enabled in CPU Wait mode. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_WAITEN (7U) /*!< Bit position for WDOG_STCTRLH_WAITEN. */ -#define BM_WDOG_STCTRLH_WAITEN (0x0080U) /*!< Bit mask for WDOG_STCTRLH_WAITEN. */ -#define BS_WDOG_STCTRLH_WAITEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WAITEN. */ - -/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */ -#define BR_WDOG_STCTRLH_WAITEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. */ -#define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN) - -/*! @brief Set the WAITEN field to a new value. */ -#define BW_WDOG_STCTRLH_WAITEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW) - * - * Puts the watchdog in the functional test mode. In this mode, the watchdog - * timer and the associated compare and reset generation logic is tested for correct - * operation. The clock for the timer is switched from the main watchdog clock - * to the fast clock input for watchdog functional test. The TESTSEL bit selects - * the test to be run. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_TESTWDOG (10U) /*!< Bit position for WDOG_STCTRLH_TESTWDOG. */ -#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /*!< Bit mask for WDOG_STCTRLH_TESTWDOG. */ -#define BS_WDOG_STCTRLH_TESTWDOG (1U) /*!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. */ - -/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */ -#define BR_WDOG_STCTRLH_TESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. */ -#define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG) - -/*! @brief Set the TESTWDOG field to a new value. */ -#define BW_WDOG_STCTRLH_TESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW) - * - * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog - * timer. - * - * Values: - * - 0 - Quick test. The timer runs in normal operation. You can load a small - * time-out value to do a quick test. - * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes - * of the timer are enabled for operation and are compared for time-out - * against the corresponding byte of the programmed time-out value. Select the - * byte through BYTESEL[1:0] for testing. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_TESTSEL (11U) /*!< Bit position for WDOG_STCTRLH_TESTSEL. */ -#define BM_WDOG_STCTRLH_TESTSEL (0x0800U) /*!< Bit mask for WDOG_STCTRLH_TESTSEL. */ -#define BS_WDOG_STCTRLH_TESTSEL (1U) /*!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. */ - -/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */ -#define BR_WDOG_STCTRLH_TESTSEL(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. */ -#define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL) - -/*! @brief Set the TESTSEL field to a new value. */ -#define BW_WDOG_STCTRLH_TESTSEL(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL) = (v)) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW) - * - * This 2-bit field selects the byte to be tested when the watchdog is in the - * byte test mode. - * - * Values: - * - 00 - Byte 0 selected - * - 01 - Byte 1 selected - * - 10 - Byte 2 selected - * - 11 - Byte 3 selected - */ -/*@{*/ -#define BP_WDOG_STCTRLH_BYTESEL (12U) /*!< Bit position for WDOG_STCTRLH_BYTESEL. */ -#define BM_WDOG_STCTRLH_BYTESEL (0x3000U) /*!< Bit mask for WDOG_STCTRLH_BYTESEL. */ -#define BS_WDOG_STCTRLH_BYTESEL (2U) /*!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. */ - -/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */ -#define BR_WDOG_STCTRLH_BYTESEL(x) (HW_WDOG_STCTRLH(x).B.BYTESEL) - -/*! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. */ -#define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL) - -/*! @brief Set the BYTESEL field to a new value. */ -#define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v))) -/*@}*/ - -/*! - * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW) - * - * Allows the WDOG's functional test mode to be disabled permanently. After it - * is set, it can only be cleared by a reset. It cannot be unlocked for editing - * after it is set. - * - * Values: - * - 0 - WDOG functional test mode is not disabled. - * - 1 - WDOG functional test mode is disabled permanently until reset. - */ -/*@{*/ -#define BP_WDOG_STCTRLH_DISTESTWDOG (14U) /*!< Bit position for WDOG_STCTRLH_DISTESTWDOG. */ -#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /*!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. */ -#define BS_WDOG_STCTRLH_DISTESTWDOG (1U) /*!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. */ - -/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */ -#define BR_WDOG_STCTRLH_DISTESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG)) - -/*! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. */ -#define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG) - -/*! @brief Set the DISTESTWDOG field to a new value. */ -#define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_STCTRLL - Watchdog Status and Control Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW) - * - * Reset value: 0x0001U - */ -typedef union _hw_wdog_stctrll -{ - uint16_t U; - struct _hw_wdog_stctrll_bitfields - { - uint16_t RESERVED0 : 15; /*!< [14:0] */ - uint16_t INTFLG : 1; /*!< [15] */ - } B; -} hw_wdog_stctrll_t; - -/*! - * @name Constants and macros for entire WDOG_STCTRLL register - */ -/*@{*/ -#define HW_WDOG_STCTRLL_ADDR(x) ((x) + 0x2U) - -#define HW_WDOG_STCTRLL(x) (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR(x)) -#define HW_WDOG_STCTRLL_RD(x) (HW_WDOG_STCTRLL(x).U) -#define HW_WDOG_STCTRLL_WR(x, v) (HW_WDOG_STCTRLL(x).U = (v)) -#define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) | (v))) -#define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v))) -#define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_STCTRLL bitfields - */ - -/*! - * @name Register WDOG_STCTRLL, field INTFLG[15] (RW) - * - * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a - * precondition to set this flag. INTFLG = 1 results in an interrupt being issued - * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this - * bit. It also gets cleared on a system reset. - */ -/*@{*/ -#define BP_WDOG_STCTRLL_INTFLG (15U) /*!< Bit position for WDOG_STCTRLL_INTFLG. */ -#define BM_WDOG_STCTRLL_INTFLG (0x8000U) /*!< Bit mask for WDOG_STCTRLL_INTFLG. */ -#define BS_WDOG_STCTRLL_INTFLG (1U) /*!< Bit field size in bits for WDOG_STCTRLL_INTFLG. */ - -/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */ -#define BR_WDOG_STCTRLL_INTFLG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG)) - -/*! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. */ -#define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG) - -/*! @brief Set the INTFLG field to a new value. */ -#define BW_WDOG_STCTRLL_INTFLG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG) = (v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TOVALH - Watchdog Time-out Value Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW) - * - * Reset value: 0x004CU - */ -typedef union _hw_wdog_tovalh -{ - uint16_t U; - struct _hw_wdog_tovalh_bitfields - { - uint16_t TOVALHIGH : 16; /*!< [15:0] */ - } B; -} hw_wdog_tovalh_t; - -/*! - * @name Constants and macros for entire WDOG_TOVALH register - */ -/*@{*/ -#define HW_WDOG_TOVALH_ADDR(x) ((x) + 0x4U) - -#define HW_WDOG_TOVALH(x) (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR(x)) -#define HW_WDOG_TOVALH_RD(x) (HW_WDOG_TOVALH(x).U) -#define HW_WDOG_TOVALH_WR(x, v) (HW_WDOG_TOVALH(x).U = (v)) -#define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) | (v))) -#define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v))) -#define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TOVALH bitfields - */ - -/*! - * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW) - * - * Defines the upper 16 bits of the 32-bit time-out value for the watchdog - * timer. It is defined in terms of cycles of the watchdog clock. - */ -/*@{*/ -#define BP_WDOG_TOVALH_TOVALHIGH (0U) /*!< Bit position for WDOG_TOVALH_TOVALHIGH. */ -#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /*!< Bit mask for WDOG_TOVALH_TOVALHIGH. */ -#define BS_WDOG_TOVALH_TOVALHIGH (16U) /*!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. */ - -/*! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. */ -#define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U) - -/*! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. */ -#define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH) - -/*! @brief Set the TOVALHIGH field to a new value. */ -#define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TOVALL - Watchdog Time-out Value Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW) - * - * Reset value: 0x4B4CU - * - * The time-out value of the watchdog must be set to a minimum of four watchdog - * clock cycles. This is to take into account the delay in new settings taking - * effect in the watchdog clock domain. - */ -typedef union _hw_wdog_tovall -{ - uint16_t U; - struct _hw_wdog_tovall_bitfields - { - uint16_t TOVALLOW : 16; /*!< [15:0] */ - } B; -} hw_wdog_tovall_t; - -/*! - * @name Constants and macros for entire WDOG_TOVALL register - */ -/*@{*/ -#define HW_WDOG_TOVALL_ADDR(x) ((x) + 0x6U) - -#define HW_WDOG_TOVALL(x) (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR(x)) -#define HW_WDOG_TOVALL_RD(x) (HW_WDOG_TOVALL(x).U) -#define HW_WDOG_TOVALL_WR(x, v) (HW_WDOG_TOVALL(x).U = (v)) -#define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) | (v))) -#define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v))) -#define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TOVALL bitfields - */ - -/*! - * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW) - * - * Defines the lower 16 bits of the 32-bit time-out value for the watchdog - * timer. It is defined in terms of cycles of the watchdog clock. - */ -/*@{*/ -#define BP_WDOG_TOVALL_TOVALLOW (0U) /*!< Bit position for WDOG_TOVALL_TOVALLOW. */ -#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) /*!< Bit mask for WDOG_TOVALL_TOVALLOW. */ -#define BS_WDOG_TOVALL_TOVALLOW (16U) /*!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. */ - -/*! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. */ -#define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U) - -/*! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. */ -#define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW) - -/*! @brief Set the TOVALLOW field to a new value. */ -#define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_WINH - Watchdog Window Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_WINH - Watchdog Window Register High (RW) - * - * Reset value: 0x0000U - * - * You must set the Window Register value lower than the Time-out Value Register. - */ -typedef union _hw_wdog_winh -{ - uint16_t U; - struct _hw_wdog_winh_bitfields - { - uint16_t WINHIGH : 16; /*!< [15:0] */ - } B; -} hw_wdog_winh_t; - -/*! - * @name Constants and macros for entire WDOG_WINH register - */ -/*@{*/ -#define HW_WDOG_WINH_ADDR(x) ((x) + 0x8U) - -#define HW_WDOG_WINH(x) (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR(x)) -#define HW_WDOG_WINH_RD(x) (HW_WDOG_WINH(x).U) -#define HW_WDOG_WINH_WR(x, v) (HW_WDOG_WINH(x).U = (v)) -#define HW_WDOG_WINH_SET(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) | (v))) -#define HW_WDOG_WINH_CLR(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v))) -#define HW_WDOG_WINH_TOG(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_WINH bitfields - */ - -/*! - * @name Register WDOG_WINH, field WINHIGH[15:0] (RW) - * - * Defines the upper 16 bits of the 32-bit window for the windowed mode of - * operation of the watchdog. It is defined in terms of cycles of the watchdog clock. - * In this mode, the watchdog can be refreshed only when the timer has reached a - * value greater than or equal to this window length. A refresh outside this - * window resets the system or if IRQRSTEN is set, it interrupts and then resets the - * system. - */ -/*@{*/ -#define BP_WDOG_WINH_WINHIGH (0U) /*!< Bit position for WDOG_WINH_WINHIGH. */ -#define BM_WDOG_WINH_WINHIGH (0xFFFFU) /*!< Bit mask for WDOG_WINH_WINHIGH. */ -#define BS_WDOG_WINH_WINHIGH (16U) /*!< Bit field size in bits for WDOG_WINH_WINHIGH. */ - -/*! @brief Read current value of the WDOG_WINH_WINHIGH field. */ -#define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U) - -/*! @brief Format value for bitfield WDOG_WINH_WINHIGH. */ -#define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH) - -/*! @brief Set the WINHIGH field to a new value. */ -#define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_WINL - Watchdog Window Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW) - * - * Reset value: 0x0010U - * - * You must set the Window Register value lower than the Time-out Value Register. - */ -typedef union _hw_wdog_winl -{ - uint16_t U; - struct _hw_wdog_winl_bitfields - { - uint16_t WINLOW : 16; /*!< [15:0] */ - } B; -} hw_wdog_winl_t; - -/*! - * @name Constants and macros for entire WDOG_WINL register - */ -/*@{*/ -#define HW_WDOG_WINL_ADDR(x) ((x) + 0xAU) - -#define HW_WDOG_WINL(x) (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR(x)) -#define HW_WDOG_WINL_RD(x) (HW_WDOG_WINL(x).U) -#define HW_WDOG_WINL_WR(x, v) (HW_WDOG_WINL(x).U = (v)) -#define HW_WDOG_WINL_SET(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) | (v))) -#define HW_WDOG_WINL_CLR(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v))) -#define HW_WDOG_WINL_TOG(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_WINL bitfields - */ - -/*! - * @name Register WDOG_WINL, field WINLOW[15:0] (RW) - * - * Defines the lower 16 bits of the 32-bit window for the windowed mode of - * operation of the watchdog. It is defined in terms of cycles of the pre-scaled - * watchdog clock. In this mode, the watchdog can be refreshed only when the timer - * reaches a value greater than or equal to this window length value. A refresh - * outside of this window resets the system or if IRQRSTEN is set, it interrupts and - * then resets the system. - */ -/*@{*/ -#define BP_WDOG_WINL_WINLOW (0U) /*!< Bit position for WDOG_WINL_WINLOW. */ -#define BM_WDOG_WINL_WINLOW (0xFFFFU) /*!< Bit mask for WDOG_WINL_WINLOW. */ -#define BS_WDOG_WINL_WINLOW (16U) /*!< Bit field size in bits for WDOG_WINL_WINLOW. */ - -/*! @brief Read current value of the WDOG_WINL_WINLOW field. */ -#define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U) - -/*! @brief Format value for bitfield WDOG_WINL_WINLOW. */ -#define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW) - -/*! @brief Set the WINLOW field to a new value. */ -#define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_REFRESH - Watchdog Refresh register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW) - * - * Reset value: 0xB480U - */ -typedef union _hw_wdog_refresh -{ - uint16_t U; - struct _hw_wdog_refresh_bitfields - { - uint16_t WDOGREFRESH : 16; /*!< [15:0] */ - } B; -} hw_wdog_refresh_t; - -/*! - * @name Constants and macros for entire WDOG_REFRESH register - */ -/*@{*/ -#define HW_WDOG_REFRESH_ADDR(x) ((x) + 0xCU) - -#define HW_WDOG_REFRESH(x) (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR(x)) -#define HW_WDOG_REFRESH_RD(x) (HW_WDOG_REFRESH(x).U) -#define HW_WDOG_REFRESH_WR(x, v) (HW_WDOG_REFRESH(x).U = (v)) -#define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) | (v))) -#define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v))) -#define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_REFRESH bitfields - */ - -/*! - * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW) - * - * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 - * bus clock cycles written to this register refreshes the WDOG and prevents it - * from resetting the system. Writing a value other than the above mentioned - * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if - * IRQRSTEN is set, it interrupts and then resets the system. - */ -/*@{*/ -#define BP_WDOG_REFRESH_WDOGREFRESH (0U) /*!< Bit position for WDOG_REFRESH_WDOGREFRESH. */ -#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /*!< Bit mask for WDOG_REFRESH_WDOGREFRESH. */ -#define BS_WDOG_REFRESH_WDOGREFRESH (16U) /*!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. */ - -/*! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. */ -#define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U) - -/*! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. */ -#define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH) - -/*! @brief Set the WDOGREFRESH field to a new value. */ -#define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_UNLOCK - Watchdog Unlock register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW) - * - * Reset value: 0xD928U - */ -typedef union _hw_wdog_unlock -{ - uint16_t U; - struct _hw_wdog_unlock_bitfields - { - uint16_t WDOGUNLOCK : 16; /*!< [15:0] */ - } B; -} hw_wdog_unlock_t; - -/*! - * @name Constants and macros for entire WDOG_UNLOCK register - */ -/*@{*/ -#define HW_WDOG_UNLOCK_ADDR(x) ((x) + 0xEU) - -#define HW_WDOG_UNLOCK(x) (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR(x)) -#define HW_WDOG_UNLOCK_RD(x) (HW_WDOG_UNLOCK(x).U) -#define HW_WDOG_UNLOCK_WR(x, v) (HW_WDOG_UNLOCK(x).U = (v)) -#define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) | (v))) -#define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v))) -#define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_UNLOCK bitfields - */ - -/*! - * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW) - * - * Writing the unlock sequence values to this register to makes the watchdog - * write-once registers writable again. The required unlock sequence is 0xC520 - * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a - * window equal in length to the WCT within which you can update the registers. - * Writing a value other than the above mentioned sequence or if the sequence is - * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts - * and then resets the system. The unlock sequence is effective only if - * ALLOWUPDATE is set. - */ -/*@{*/ -#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) /*!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. */ -#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /*!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. */ -#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) /*!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. */ - -/*! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. */ -#define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U) - -/*! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. */ -#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK) - -/*! @brief Set the WDOGUNLOCK field to a new value. */ -#define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TMROUTH - Watchdog Timer Output Register High - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_wdog_tmrouth -{ - uint16_t U; - struct _hw_wdog_tmrouth_bitfields - { - uint16_t TIMEROUTHIGH : 16; /*!< [15:0] */ - } B; -} hw_wdog_tmrouth_t; - -/*! - * @name Constants and macros for entire WDOG_TMROUTH register - */ -/*@{*/ -#define HW_WDOG_TMROUTH_ADDR(x) ((x) + 0x10U) - -#define HW_WDOG_TMROUTH(x) (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR(x)) -#define HW_WDOG_TMROUTH_RD(x) (HW_WDOG_TMROUTH(x).U) -#define HW_WDOG_TMROUTH_WR(x, v) (HW_WDOG_TMROUTH(x).U = (v)) -#define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) | (v))) -#define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v))) -#define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TMROUTH bitfields - */ - -/*! - * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW) - * - * Shows the value of the upper 16 bits of the watchdog timer. - */ -/*@{*/ -#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) /*!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. */ -#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /*!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. */ -#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /*!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. */ - -/*! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. */ -#define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U) - -/*! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. */ -#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH) - -/*! @brief Set the TIMEROUTHIGH field to a new value. */ -#define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_TMROUTL - Watchdog Timer Output Register Low - ******************************************************************************/ - -/*! - * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW) - * - * Reset value: 0x0000U - * - * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of - * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK - * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following - * the watchdog timer. - */ -typedef union _hw_wdog_tmroutl -{ - uint16_t U; - struct _hw_wdog_tmroutl_bitfields - { - uint16_t TIMEROUTLOW : 16; /*!< [15:0] */ - } B; -} hw_wdog_tmroutl_t; - -/*! - * @name Constants and macros for entire WDOG_TMROUTL register - */ -/*@{*/ -#define HW_WDOG_TMROUTL_ADDR(x) ((x) + 0x12U) - -#define HW_WDOG_TMROUTL(x) (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR(x)) -#define HW_WDOG_TMROUTL_RD(x) (HW_WDOG_TMROUTL(x).U) -#define HW_WDOG_TMROUTL_WR(x, v) (HW_WDOG_TMROUTL(x).U = (v)) -#define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) | (v))) -#define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v))) -#define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_TMROUTL bitfields - */ - -/*! - * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW) - * - * Shows the value of the lower 16 bits of the watchdog timer. - */ -/*@{*/ -#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) /*!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. */ -#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /*!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. */ -#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) /*!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. */ - -/*! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. */ -#define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U) - -/*! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. */ -#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW) - -/*! @brief Set the TIMEROUTLOW field to a new value. */ -#define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_RSTCNT - Watchdog Reset Count register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW) - * - * Reset value: 0x0000U - */ -typedef union _hw_wdog_rstcnt -{ - uint16_t U; - struct _hw_wdog_rstcnt_bitfields - { - uint16_t RSTCNT : 16; /*!< [15:0] */ - } B; -} hw_wdog_rstcnt_t; - -/*! - * @name Constants and macros for entire WDOG_RSTCNT register - */ -/*@{*/ -#define HW_WDOG_RSTCNT_ADDR(x) ((x) + 0x14U) - -#define HW_WDOG_RSTCNT(x) (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR(x)) -#define HW_WDOG_RSTCNT_RD(x) (HW_WDOG_RSTCNT(x).U) -#define HW_WDOG_RSTCNT_WR(x, v) (HW_WDOG_RSTCNT(x).U = (v)) -#define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) | (v))) -#define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v))) -#define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_RSTCNT bitfields - */ - -/*! - * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW) - * - * Counts the number of times the watchdog resets the system. This register is - * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear - * the contents of this register. - */ -/*@{*/ -#define BP_WDOG_RSTCNT_RSTCNT (0U) /*!< Bit position for WDOG_RSTCNT_RSTCNT. */ -#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) /*!< Bit mask for WDOG_RSTCNT_RSTCNT. */ -#define BS_WDOG_RSTCNT_RSTCNT (16U) /*!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. */ - -/*! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. */ -#define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U) - -/*! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. */ -#define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT) - -/*! @brief Set the RSTCNT field to a new value. */ -#define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v)) -/*@}*/ - -/******************************************************************************* - * HW_WDOG_PRESC - Watchdog Prescaler register - ******************************************************************************/ - -/*! - * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW) - * - * Reset value: 0x0400U - */ -typedef union _hw_wdog_presc -{ - uint16_t U; - struct _hw_wdog_presc_bitfields - { - uint16_t RESERVED0 : 8; /*!< [7:0] */ - uint16_t PRESCVAL : 3; /*!< [10:8] */ - uint16_t RESERVED1 : 5; /*!< [15:11] */ - } B; -} hw_wdog_presc_t; - -/*! - * @name Constants and macros for entire WDOG_PRESC register - */ -/*@{*/ -#define HW_WDOG_PRESC_ADDR(x) ((x) + 0x16U) - -#define HW_WDOG_PRESC(x) (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR(x)) -#define HW_WDOG_PRESC_RD(x) (HW_WDOG_PRESC(x).U) -#define HW_WDOG_PRESC_WR(x, v) (HW_WDOG_PRESC(x).U = (v)) -#define HW_WDOG_PRESC_SET(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) | (v))) -#define HW_WDOG_PRESC_CLR(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v))) -#define HW_WDOG_PRESC_TOG(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual WDOG_PRESC bitfields - */ - -/*! - * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW) - * - * 3-bit prescaler for the watchdog clock source. A value of zero indicates no - * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + - * 1) to provide the prescaled WDOG_CLK. - */ -/*@{*/ -#define BP_WDOG_PRESC_PRESCVAL (8U) /*!< Bit position for WDOG_PRESC_PRESCVAL. */ -#define BM_WDOG_PRESC_PRESCVAL (0x0700U) /*!< Bit mask for WDOG_PRESC_PRESCVAL. */ -#define BS_WDOG_PRESC_PRESCVAL (3U) /*!< Bit field size in bits for WDOG_PRESC_PRESCVAL. */ - -/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */ -#define BR_WDOG_PRESC_PRESCVAL(x) (HW_WDOG_PRESC(x).B.PRESCVAL) - -/*! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. */ -#define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL) - -/*! @brief Set the PRESCVAL field to a new value. */ -#define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v))) -/*@}*/ - -/******************************************************************************* - * hw_wdog_t - module struct - ******************************************************************************/ -/*! - * @brief All WDOG module registers. - */ -#pragma pack(1) -typedef struct _hw_wdog -{ - __IO hw_wdog_stctrlh_t STCTRLH; /*!< [0x0] Watchdog Status and Control Register High */ - __IO hw_wdog_stctrll_t STCTRLL; /*!< [0x2] Watchdog Status and Control Register Low */ - __IO hw_wdog_tovalh_t TOVALH; /*!< [0x4] Watchdog Time-out Value Register High */ - __IO hw_wdog_tovall_t TOVALL; /*!< [0x6] Watchdog Time-out Value Register Low */ - __IO hw_wdog_winh_t WINH; /*!< [0x8] Watchdog Window Register High */ - __IO hw_wdog_winl_t WINL; /*!< [0xA] Watchdog Window Register Low */ - __IO hw_wdog_refresh_t REFRESH; /*!< [0xC] Watchdog Refresh register */ - __IO hw_wdog_unlock_t UNLOCK; /*!< [0xE] Watchdog Unlock register */ - __IO hw_wdog_tmrouth_t TMROUTH; /*!< [0x10] Watchdog Timer Output Register High */ - __IO hw_wdog_tmroutl_t TMROUTL; /*!< [0x12] Watchdog Timer Output Register Low */ - __IO hw_wdog_rstcnt_t RSTCNT; /*!< [0x14] Watchdog Reset Count register */ - __IO hw_wdog_presc_t PRESC; /*!< [0x16] Watchdog Prescaler register */ -} hw_wdog_t; -#pragma pack() - -/*! @brief Macro to access all WDOG registers. */ -/*! @param x WDOG module instance base address. */ -/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, - * use the '&' operator, like &HW_WDOG(WDOG_BASE). */ -#define HW_WDOG(x) (*(hw_wdog_t *)(x)) - -#endif /* __HW_WDOG_REGISTERS_H__ */ -/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/fsl_device_registers.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/fsl_device_registers.h deleted file mode 100644 index 02dc670bfa9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/fsl_device_registers.h +++ /dev/null @@ -1,1526 +0,0 @@ -/* - * Copyright (c) 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \ - defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)) - - #define K02F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK02F12810/MK02F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK02F12810/MK02F12810_adc.h" - #include "device/MK02F12810/MK02F12810_cmp.h" - #include "device/MK02F12810/MK02F12810_crc.h" - #include "device/MK02F12810/MK02F12810_dac.h" - #include "device/MK02F12810/MK02F12810_dma.h" - #include "device/MK02F12810/MK02F12810_dmamux.h" - #include "device/MK02F12810/MK02F12810_ewm.h" - #include "device/MK02F12810/MK02F12810_fmc.h" - #include "device/MK02F12810/MK02F12810_ftfa.h" - #include "device/MK02F12810/MK02F12810_ftm.h" - #include "device/MK02F12810/MK02F12810_gpio.h" - #include "device/MK02F12810/MK02F12810_i2c.h" - #include "device/MK02F12810/MK02F12810_llwu.h" - #include "device/MK02F12810/MK02F12810_lptmr.h" - #include "device/MK02F12810/MK02F12810_mcg.h" - #include "device/MK02F12810/MK02F12810_mcm.h" - #include "device/MK02F12810/MK02F12810_nv.h" - #include "device/MK02F12810/MK02F12810_osc.h" - #include "device/MK02F12810/MK02F12810_pdb.h" - #include "device/MK02F12810/MK02F12810_pit.h" - #include "device/MK02F12810/MK02F12810_pmc.h" - #include "device/MK02F12810/MK02F12810_port.h" - #include "device/MK02F12810/MK02F12810_rcm.h" - #include "device/MK02F12810/MK02F12810_sim.h" - #include "device/MK02F12810/MK02F12810_smc.h" - #include "device/MK02F12810/MK02F12810_spi.h" - #include "device/MK02F12810/MK02F12810_uart.h" - #include "device/MK02F12810/MK02F12810_vref.h" - #include "device/MK02F12810/MK02F12810_wdog.h" - -#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \ - defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ - defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \ - defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ - defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \ - defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ - defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \ - defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ - defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \ - defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)) - - #define K20D5_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK20D5/MK20D5.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK20D5/MK20D5_adc.h" - #include "device/MK20D5/MK20D5_cmp.h" - #include "device/MK20D5/MK20D5_cmt.h" - #include "device/MK20D5/MK20D5_crc.h" - #include "device/MK20D5/MK20D5_dma.h" - #include "device/MK20D5/MK20D5_dmamux.h" - #include "device/MK20D5/MK20D5_ewm.h" - #include "device/MK20D5/MK20D5_fmc.h" - #include "device/MK20D5/MK20D5_ftfl.h" - #include "device/MK20D5/MK20D5_ftm.h" - #include "device/MK20D5/MK20D5_gpio.h" - #include "device/MK20D5/MK20D5_i2c.h" - #include "device/MK20D5/MK20D5_i2s.h" - #include "device/MK20D5/MK20D5_llwu.h" - #include "device/MK20D5/MK20D5_lptmr.h" - #include "device/MK20D5/MK20D5_mcg.h" - #include "device/MK20D5/MK20D5_nv.h" - #include "device/MK20D5/MK20D5_osc.h" - #include "device/MK20D5/MK20D5_pdb.h" - #include "device/MK20D5/MK20D5_pit.h" - #include "device/MK20D5/MK20D5_pmc.h" - #include "device/MK20D5/MK20D5_port.h" - #include "device/MK20D5/MK20D5_rcm.h" - #include "device/MK20D5/MK20D5_rfsys.h" - #include "device/MK20D5/MK20D5_rfvbat.h" - #include "device/MK20D5/MK20D5_rtc.h" - #include "device/MK20D5/MK20D5_sim.h" - #include "device/MK20D5/MK20D5_smc.h" - #include "device/MK20D5/MK20D5_spi.h" - #include "device/MK20D5/MK20D5_tsi.h" - #include "device/MK20D5/MK20D5_uart.h" - #include "device/MK20D5/MK20D5_usb.h" - #include "device/MK20D5/MK20D5_usbdcd.h" - #include "device/MK20D5/MK20D5_vref.h" - #include "device/MK20D5/MK20D5_wdog.h" - -#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \ - defined(CPU_MK22FN128VMP10)) - - #define K22F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK22F12810/MK22F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK22F12810/MK22F12810_adc.h" - #include "device/MK22F12810/MK22F12810_cmp.h" - #include "device/MK22F12810/MK22F12810_crc.h" - #include "device/MK22F12810/MK22F12810_dac.h" - #include "device/MK22F12810/MK22F12810_dma.h" - #include "device/MK22F12810/MK22F12810_dmamux.h" - #include "device/MK22F12810/MK22F12810_ewm.h" - #include "device/MK22F12810/MK22F12810_fmc.h" - #include "device/MK22F12810/MK22F12810_ftfa.h" - #include "device/MK22F12810/MK22F12810_ftm.h" - #include "device/MK22F12810/MK22F12810_gpio.h" - #include "device/MK22F12810/MK22F12810_i2c.h" - #include "device/MK22F12810/MK22F12810_i2s.h" - #include "device/MK22F12810/MK22F12810_llwu.h" - #include "device/MK22F12810/MK22F12810_lptmr.h" - #include "device/MK22F12810/MK22F12810_lpuart.h" - #include "device/MK22F12810/MK22F12810_mcg.h" - #include "device/MK22F12810/MK22F12810_mcm.h" - #include "device/MK22F12810/MK22F12810_nv.h" - #include "device/MK22F12810/MK22F12810_osc.h" - #include "device/MK22F12810/MK22F12810_pdb.h" - #include "device/MK22F12810/MK22F12810_pit.h" - #include "device/MK22F12810/MK22F12810_pmc.h" - #include "device/MK22F12810/MK22F12810_port.h" - #include "device/MK22F12810/MK22F12810_rcm.h" - #include "device/MK22F12810/MK22F12810_rfsys.h" - #include "device/MK22F12810/MK22F12810_rfvbat.h" - #include "device/MK22F12810/MK22F12810_rtc.h" - #include "device/MK22F12810/MK22F12810_sim.h" - #include "device/MK22F12810/MK22F12810_smc.h" - #include "device/MK22F12810/MK22F12810_spi.h" - #include "device/MK22F12810/MK22F12810_uart.h" - #include "device/MK22F12810/MK22F12810_usb.h" - #include "device/MK22F12810/MK22F12810_vref.h" - #include "device/MK22F12810/MK22F12810_wdog.h" - -#elif (defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || \ - defined(CPU_MK22FN256VMP12)) - - #define K22F25612_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK22F25612/MK22F25612.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK22F25612/MK22F25612_adc.h" - #include "device/MK22F25612/MK22F25612_cmp.h" - #include "device/MK22F25612/MK22F25612_crc.h" - #include "device/MK22F25612/MK22F25612_dac.h" - #include "device/MK22F25612/MK22F25612_dma.h" - #include "device/MK22F25612/MK22F25612_dmamux.h" - #include "device/MK22F25612/MK22F25612_ewm.h" - #include "device/MK22F25612/MK22F25612_fmc.h" - #include "device/MK22F25612/MK22F25612_ftfa.h" - #include "device/MK22F25612/MK22F25612_ftm.h" - #include "device/MK22F25612/MK22F25612_gpio.h" - #include "device/MK22F25612/MK22F25612_i2c.h" - #include "device/MK22F25612/MK22F25612_i2s.h" - #include "device/MK22F25612/MK22F25612_llwu.h" - #include "device/MK22F25612/MK22F25612_lptmr.h" - #include "device/MK22F25612/MK22F25612_lpuart.h" - #include "device/MK22F25612/MK22F25612_mcg.h" - #include "device/MK22F25612/MK22F25612_mcm.h" - #include "device/MK22F25612/MK22F25612_nv.h" - #include "device/MK22F25612/MK22F25612_osc.h" - #include "device/MK22F25612/MK22F25612_pdb.h" - #include "device/MK22F25612/MK22F25612_pit.h" - #include "device/MK22F25612/MK22F25612_pmc.h" - #include "device/MK22F25612/MK22F25612_port.h" - #include "device/MK22F25612/MK22F25612_rcm.h" - #include "device/MK22F25612/MK22F25612_rfsys.h" - #include "device/MK22F25612/MK22F25612_rfvbat.h" - #include "device/MK22F25612/MK22F25612_rng.h" - #include "device/MK22F25612/MK22F25612_rtc.h" - #include "device/MK22F25612/MK22F25612_sim.h" - #include "device/MK22F25612/MK22F25612_smc.h" - #include "device/MK22F25612/MK22F25612_spi.h" - #include "device/MK22F25612/MK22F25612_uart.h" - #include "device/MK22F25612/MK22F25612_usb.h" - #include "device/MK22F25612/MK22F25612_vref.h" - #include "device/MK22F25612/MK22F25612_wdog.h" - -#elif (defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12)) - - #define K22F51212_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK22F51212/MK22F51212.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK22F51212/MK22F51212_adc.h" - #include "device/MK22F51212/MK22F51212_cmp.h" - #include "device/MK22F51212/MK22F51212_crc.h" - #include "device/MK22F51212/MK22F51212_dac.h" - #include "device/MK22F51212/MK22F51212_dma.h" - #include "device/MK22F51212/MK22F51212_dmamux.h" - #include "device/MK22F51212/MK22F51212_ewm.h" - #include "device/MK22F51212/MK22F51212_fb.h" - #include "device/MK22F51212/MK22F51212_fmc.h" - #include "device/MK22F51212/MK22F51212_ftfa.h" - #include "device/MK22F51212/MK22F51212_ftm.h" - #include "device/MK22F51212/MK22F51212_gpio.h" - #include "device/MK22F51212/MK22F51212_i2c.h" - #include "device/MK22F51212/MK22F51212_i2s.h" - #include "device/MK22F51212/MK22F51212_llwu.h" - #include "device/MK22F51212/MK22F51212_lptmr.h" - #include "device/MK22F51212/MK22F51212_lpuart.h" - #include "device/MK22F51212/MK22F51212_mcg.h" - #include "device/MK22F51212/MK22F51212_mcm.h" - #include "device/MK22F51212/MK22F51212_nv.h" - #include "device/MK22F51212/MK22F51212_osc.h" - #include "device/MK22F51212/MK22F51212_pdb.h" - #include "device/MK22F51212/MK22F51212_pit.h" - #include "device/MK22F51212/MK22F51212_pmc.h" - #include "device/MK22F51212/MK22F51212_port.h" - #include "device/MK22F51212/MK22F51212_rcm.h" - #include "device/MK22F51212/MK22F51212_rfsys.h" - #include "device/MK22F51212/MK22F51212_rfvbat.h" - #include "device/MK22F51212/MK22F51212_rng.h" - #include "device/MK22F51212/MK22F51212_rtc.h" - #include "device/MK22F51212/MK22F51212_sim.h" - #include "device/MK22F51212/MK22F51212_smc.h" - #include "device/MK22F51212/MK22F51212_spi.h" - #include "device/MK22F51212/MK22F51212_uart.h" - #include "device/MK22F51212/MK22F51212_usb.h" - #include "device/MK22F51212/MK22F51212_vref.h" - #include "device/MK22F51212/MK22F51212_wdog.h" - -#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12)) - - #define K24F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK24F12/MK24F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK24F12/MK24F12_adc.h" - #include "device/MK24F12/MK24F12_aips.h" - #include "device/MK24F12/MK24F12_axbs.h" - #include "device/MK24F12/MK24F12_can.h" - #include "device/MK24F12/MK24F12_cau.h" - #include "device/MK24F12/MK24F12_cmp.h" - #include "device/MK24F12/MK24F12_cmt.h" - #include "device/MK24F12/MK24F12_crc.h" - #include "device/MK24F12/MK24F12_dac.h" - #include "device/MK24F12/MK24F12_dma.h" - #include "device/MK24F12/MK24F12_dmamux.h" - #include "device/MK24F12/MK24F12_ewm.h" - #include "device/MK24F12/MK24F12_fb.h" - #include "device/MK24F12/MK24F12_fmc.h" - #include "device/MK24F12/MK24F12_ftfe.h" - #include "device/MK24F12/MK24F12_ftm.h" - #include "device/MK24F12/MK24F12_gpio.h" - #include "device/MK24F12/MK24F12_i2c.h" - #include "device/MK24F12/MK24F12_i2s.h" - #include "device/MK24F12/MK24F12_llwu.h" - #include "device/MK24F12/MK24F12_lptmr.h" - #include "device/MK24F12/MK24F12_mcg.h" - #include "device/MK24F12/MK24F12_mcm.h" - #include "device/MK24F12/MK24F12_mpu.h" - #include "device/MK24F12/MK24F12_nv.h" - #include "device/MK24F12/MK24F12_osc.h" - #include "device/MK24F12/MK24F12_pdb.h" - #include "device/MK24F12/MK24F12_pit.h" - #include "device/MK24F12/MK24F12_pmc.h" - #include "device/MK24F12/MK24F12_port.h" - #include "device/MK24F12/MK24F12_rcm.h" - #include "device/MK24F12/MK24F12_rfsys.h" - #include "device/MK24F12/MK24F12_rfvbat.h" - #include "device/MK24F12/MK24F12_rng.h" - #include "device/MK24F12/MK24F12_rtc.h" - #include "device/MK24F12/MK24F12_sdhc.h" - #include "device/MK24F12/MK24F12_sim.h" - #include "device/MK24F12/MK24F12_smc.h" - #include "device/MK24F12/MK24F12_spi.h" - #include "device/MK24F12/MK24F12_uart.h" - #include "device/MK24F12/MK24F12_usb.h" - #include "device/MK24F12/MK24F12_usbdcd.h" - #include "device/MK24F12/MK24F12_vref.h" - #include "device/MK24F12/MK24F12_wdog.h" - -#elif (defined(CPU_MK24FN256VDC12)) - - #define K24F25612_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK24F25612/MK24F25612.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK24F25612/MK24F25612_adc.h" - #include "device/MK24F25612/MK24F25612_aips.h" - #include "device/MK24F25612/MK24F25612_cmp.h" - #include "device/MK24F25612/MK24F25612_cmt.h" - #include "device/MK24F25612/MK24F25612_crc.h" - #include "device/MK24F25612/MK24F25612_dac.h" - #include "device/MK24F25612/MK24F25612_dma.h" - #include "device/MK24F25612/MK24F25612_dmamux.h" - #include "device/MK24F25612/MK24F25612_ewm.h" - #include "device/MK24F25612/MK24F25612_fmc.h" - #include "device/MK24F25612/MK24F25612_ftfa.h" - #include "device/MK24F25612/MK24F25612_ftm.h" - #include "device/MK24F25612/MK24F25612_gpio.h" - #include "device/MK24F25612/MK24F25612_i2c.h" - #include "device/MK24F25612/MK24F25612_i2s.h" - #include "device/MK24F25612/MK24F25612_llwu.h" - #include "device/MK24F25612/MK24F25612_lptmr.h" - #include "device/MK24F25612/MK24F25612_mcg.h" - #include "device/MK24F25612/MK24F25612_mcm.h" - #include "device/MK24F25612/MK24F25612_osc.h" - #include "device/MK24F25612/MK24F25612_pdb.h" - #include "device/MK24F25612/MK24F25612_pit.h" - #include "device/MK24F25612/MK24F25612_pmc.h" - #include "device/MK24F25612/MK24F25612_port.h" - #include "device/MK24F25612/MK24F25612_rcm.h" - #include "device/MK24F25612/MK24F25612_rfsys.h" - #include "device/MK24F25612/MK24F25612_rfvbat.h" - #include "device/MK24F25612/MK24F25612_rng.h" - #include "device/MK24F25612/MK24F25612_rtc.h" - #include "device/MK24F25612/MK24F25612_sim.h" - #include "device/MK24F25612/MK24F25612_smc.h" - #include "device/MK24F25612/MK24F25612_spi.h" - #include "device/MK24F25612/MK24F25612_uart.h" - #include "device/MK24F25612/MK24F25612_usb.h" - #include "device/MK24F25612/MK24F25612_usbdcd.h" - #include "device/MK24F25612/MK24F25612_vref.h" - #include "device/MK24F25612/MK24F25612_wdog.h" - -#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12)) - - #define K63F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK63F12/MK63F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK63F12/MK63F12_adc.h" - #include "device/MK63F12/MK63F12_aips.h" - #include "device/MK63F12/MK63F12_axbs.h" - #include "device/MK63F12/MK63F12_can.h" - #include "device/MK63F12/MK63F12_cau.h" - #include "device/MK63F12/MK63F12_cmp.h" - #include "device/MK63F12/MK63F12_cmt.h" - #include "device/MK63F12/MK63F12_crc.h" - #include "device/MK63F12/MK63F12_dac.h" - #include "device/MK63F12/MK63F12_dma.h" - #include "device/MK63F12/MK63F12_dmamux.h" - #include "device/MK63F12/MK63F12_enet.h" - #include "device/MK63F12/MK63F12_ewm.h" - #include "device/MK63F12/MK63F12_fb.h" - #include "device/MK63F12/MK63F12_fmc.h" - #include "device/MK63F12/MK63F12_ftfe.h" - #include "device/MK63F12/MK63F12_ftm.h" - #include "device/MK63F12/MK63F12_gpio.h" - #include "device/MK63F12/MK63F12_i2c.h" - #include "device/MK63F12/MK63F12_i2s.h" - #include "device/MK63F12/MK63F12_llwu.h" - #include "device/MK63F12/MK63F12_lptmr.h" - #include "device/MK63F12/MK63F12_mcg.h" - #include "device/MK63F12/MK63F12_mcm.h" - #include "device/MK63F12/MK63F12_mpu.h" - #include "device/MK63F12/MK63F12_nv.h" - #include "device/MK63F12/MK63F12_osc.h" - #include "device/MK63F12/MK63F12_pdb.h" - #include "device/MK63F12/MK63F12_pit.h" - #include "device/MK63F12/MK63F12_pmc.h" - #include "device/MK63F12/MK63F12_port.h" - #include "device/MK63F12/MK63F12_rcm.h" - #include "device/MK63F12/MK63F12_rfsys.h" - #include "device/MK63F12/MK63F12_rfvbat.h" - #include "device/MK63F12/MK63F12_rng.h" - #include "device/MK63F12/MK63F12_rtc.h" - #include "device/MK63F12/MK63F12_sdhc.h" - #include "device/MK63F12/MK63F12_sim.h" - #include "device/MK63F12/MK63F12_smc.h" - #include "device/MK63F12/MK63F12_spi.h" - #include "device/MK63F12/MK63F12_uart.h" - #include "device/MK63F12/MK63F12_usb.h" - #include "device/MK63F12/MK63F12_usbdcd.h" - #include "device/MK63F12/MK63F12_vref.h" - #include "device/MK63F12/MK63F12_wdog.h" - -#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ - defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ - defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)) - - #define K64F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK64F12/MK64F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK64F12/MK64F12_adc.h" - #include "device/MK64F12/MK64F12_aips.h" - #include "device/MK64F12/MK64F12_axbs.h" - #include "device/MK64F12/MK64F12_can.h" - #include "device/MK64F12/MK64F12_cau.h" - #include "device/MK64F12/MK64F12_cmp.h" - #include "device/MK64F12/MK64F12_cmt.h" - #include "device/MK64F12/MK64F12_crc.h" - #include "device/MK64F12/MK64F12_dac.h" - #include "device/MK64F12/MK64F12_dma.h" - #include "device/MK64F12/MK64F12_dmamux.h" - #include "device/MK64F12/MK64F12_enet.h" - #include "device/MK64F12/MK64F12_ewm.h" - #include "device/MK64F12/MK64F12_fb.h" - #include "device/MK64F12/MK64F12_fmc.h" - #include "device/MK64F12/MK64F12_ftfe.h" - #include "device/MK64F12/MK64F12_ftm.h" - #include "device/MK64F12/MK64F12_gpio.h" - #include "device/MK64F12/MK64F12_i2c.h" - #include "device/MK64F12/MK64F12_i2s.h" - #include "device/MK64F12/MK64F12_llwu.h" - #include "device/MK64F12/MK64F12_lptmr.h" - #include "device/MK64F12/MK64F12_mcg.h" - #include "device/MK64F12/MK64F12_mcm.h" - #include "device/MK64F12/MK64F12_mpu.h" - #include "device/MK64F12/MK64F12_nv.h" - #include "device/MK64F12/MK64F12_osc.h" - #include "device/MK64F12/MK64F12_pdb.h" - #include "device/MK64F12/MK64F12_pit.h" - #include "device/MK64F12/MK64F12_pmc.h" - #include "device/MK64F12/MK64F12_port.h" - #include "device/MK64F12/MK64F12_rcm.h" - #include "device/MK64F12/MK64F12_rfsys.h" - #include "device/MK64F12/MK64F12_rfvbat.h" - #include "device/MK64F12/MK64F12_rng.h" - #include "device/MK64F12/MK64F12_rtc.h" - #include "device/MK64F12/MK64F12_sdhc.h" - #include "device/MK64F12/MK64F12_sim.h" - #include "device/MK64F12/MK64F12_smc.h" - #include "device/MK64F12/MK64F12_spi.h" - #include "device/MK64F12/MK64F12_uart.h" - #include "device/MK64F12/MK64F12_usb.h" - #include "device/MK64F12/MK64F12_usbdcd.h" - #include "device/MK64F12/MK64F12_vref.h" - #include "device/MK64F12/MK64F12_wdog.h" - -#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \ - defined(CPU_MK65FX1M0VMI18)) - - #define K65F18_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK65F18/MK65F18.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK65F18/MK65F18_adc.h" - #include "device/MK65F18/MK65F18_aips.h" - #include "device/MK65F18/MK65F18_axbs.h" - #include "device/MK65F18/MK65F18_can.h" - #include "device/MK65F18/MK65F18_cau.h" - #include "device/MK65F18/MK65F18_cmp.h" - #include "device/MK65F18/MK65F18_cmt.h" - #include "device/MK65F18/MK65F18_crc.h" - #include "device/MK65F18/MK65F18_dac.h" - #include "device/MK65F18/MK65F18_dma.h" - #include "device/MK65F18/MK65F18_dmamux.h" - #include "device/MK65F18/MK65F18_enet.h" - #include "device/MK65F18/MK65F18_ewm.h" - #include "device/MK65F18/MK65F18_fb.h" - #include "device/MK65F18/MK65F18_fmc.h" - #include "device/MK65F18/MK65F18_ftfe.h" - #include "device/MK65F18/MK65F18_ftm.h" - #include "device/MK65F18/MK65F18_gpio.h" - #include "device/MK65F18/MK65F18_i2c.h" - #include "device/MK65F18/MK65F18_i2s.h" - #include "device/MK65F18/MK65F18_llwu.h" - #include "device/MK65F18/MK65F18_lmem.h" - #include "device/MK65F18/MK65F18_lptmr.h" - #include "device/MK65F18/MK65F18_lpuart.h" - #include "device/MK65F18/MK65F18_mcg.h" - #include "device/MK65F18/MK65F18_mcm.h" - #include "device/MK65F18/MK65F18_mpu.h" - #include "device/MK65F18/MK65F18_nv.h" - #include "device/MK65F18/MK65F18_osc.h" - #include "device/MK65F18/MK65F18_pdb.h" - #include "device/MK65F18/MK65F18_pit.h" - #include "device/MK65F18/MK65F18_pmc.h" - #include "device/MK65F18/MK65F18_port.h" - #include "device/MK65F18/MK65F18_rcm.h" - #include "device/MK65F18/MK65F18_rfsys.h" - #include "device/MK65F18/MK65F18_rfvbat.h" - #include "device/MK65F18/MK65F18_rng.h" - #include "device/MK65F18/MK65F18_rtc.h" - #include "device/MK65F18/MK65F18_sdhc.h" - #include "device/MK65F18/MK65F18_sdram.h" - #include "device/MK65F18/MK65F18_sim.h" - #include "device/MK65F18/MK65F18_smc.h" - #include "device/MK65F18/MK65F18_spi.h" - #include "device/MK65F18/MK65F18_tpm.h" - #include "device/MK65F18/MK65F18_tsi.h" - #include "device/MK65F18/MK65F18_uart.h" - #include "device/MK65F18/MK65F18_usb.h" - #include "device/MK65F18/MK65F18_usbdcd.h" - #include "device/MK65F18/MK65F18_usbhs.h" - #include "device/MK65F18/MK65F18_usbhsdcd.h" - #include "device/MK65F18/MK65F18_usbphy.h" - #include "device/MK65F18/MK65F18_vref.h" - #include "device/MK65F18/MK65F18_wdog.h" - -#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \ - defined(CPU_MK66FX1M0VMD18)) - - #define K66F18_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK66F18/MK66F18.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK66F18/MK66F18_adc.h" - #include "device/MK66F18/MK66F18_aips.h" - #include "device/MK66F18/MK66F18_axbs.h" - #include "device/MK66F18/MK66F18_can.h" - #include "device/MK66F18/MK66F18_cau.h" - #include "device/MK66F18/MK66F18_cmp.h" - #include "device/MK66F18/MK66F18_cmt.h" - #include "device/MK66F18/MK66F18_crc.h" - #include "device/MK66F18/MK66F18_dac.h" - #include "device/MK66F18/MK66F18_dma.h" - #include "device/MK66F18/MK66F18_dmamux.h" - #include "device/MK66F18/MK66F18_enet.h" - #include "device/MK66F18/MK66F18_ewm.h" - #include "device/MK66F18/MK66F18_fb.h" - #include "device/MK66F18/MK66F18_fmc.h" - #include "device/MK66F18/MK66F18_ftfe.h" - #include "device/MK66F18/MK66F18_ftm.h" - #include "device/MK66F18/MK66F18_gpio.h" - #include "device/MK66F18/MK66F18_i2c.h" - #include "device/MK66F18/MK66F18_i2s.h" - #include "device/MK66F18/MK66F18_llwu.h" - #include "device/MK66F18/MK66F18_lmem.h" - #include "device/MK66F18/MK66F18_lptmr.h" - #include "device/MK66F18/MK66F18_lpuart.h" - #include "device/MK66F18/MK66F18_mcg.h" - #include "device/MK66F18/MK66F18_mcm.h" - #include "device/MK66F18/MK66F18_mpu.h" - #include "device/MK66F18/MK66F18_nv.h" - #include "device/MK66F18/MK66F18_osc.h" - #include "device/MK66F18/MK66F18_pdb.h" - #include "device/MK66F18/MK66F18_pit.h" - #include "device/MK66F18/MK66F18_pmc.h" - #include "device/MK66F18/MK66F18_port.h" - #include "device/MK66F18/MK66F18_rcm.h" - #include "device/MK66F18/MK66F18_rfsys.h" - #include "device/MK66F18/MK66F18_rfvbat.h" - #include "device/MK66F18/MK66F18_rng.h" - #include "device/MK66F18/MK66F18_rtc.h" - #include "device/MK66F18/MK66F18_sdhc.h" - #include "device/MK66F18/MK66F18_sdram.h" - #include "device/MK66F18/MK66F18_sim.h" - #include "device/MK66F18/MK66F18_smc.h" - #include "device/MK66F18/MK66F18_spi.h" - #include "device/MK66F18/MK66F18_tpm.h" - #include "device/MK66F18/MK66F18_tsi.h" - #include "device/MK66F18/MK66F18_uart.h" - #include "device/MK66F18/MK66F18_usb.h" - #include "device/MK66F18/MK66F18_usbdcd.h" - #include "device/MK66F18/MK66F18_usbhs.h" - #include "device/MK66F18/MK66F18_usbhsdcd.h" - #include "device/MK66F18/MK66F18_usbphy.h" - #include "device/MK66F18/MK66F18_vref.h" - #include "device/MK66F18/MK66F18_wdog.h" - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F12_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK70F12/MK70F12.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK70F12/MK70F12_adc.h" - #include "device/MK70F12/MK70F12_aips.h" - #include "device/MK70F12/MK70F12_axbs.h" - #include "device/MK70F12/MK70F12_can.h" - #include "device/MK70F12/MK70F12_cau.h" - #include "device/MK70F12/MK70F12_cmp.h" - #include "device/MK70F12/MK70F12_cmt.h" - #include "device/MK70F12/MK70F12_crc.h" - #include "device/MK70F12/MK70F12_dac.h" - #include "device/MK70F12/MK70F12_ddr.h" - #include "device/MK70F12/MK70F12_dma.h" - #include "device/MK70F12/MK70F12_dmamux.h" - #include "device/MK70F12/MK70F12_enet.h" - #include "device/MK70F12/MK70F12_ewm.h" - #include "device/MK70F12/MK70F12_fb.h" - #include "device/MK70F12/MK70F12_fmc.h" - #include "device/MK70F12/MK70F12_ftfe.h" - #include "device/MK70F12/MK70F12_ftm.h" - #include "device/MK70F12/MK70F12_gpio.h" - #include "device/MK70F12/MK70F12_i2c.h" - #include "device/MK70F12/MK70F12_i2s.h" - #include "device/MK70F12/MK70F12_lcdc.h" - #include "device/MK70F12/MK70F12_llwu.h" - #include "device/MK70F12/MK70F12_lmem.h" - #include "device/MK70F12/MK70F12_lptmr.h" - #include "device/MK70F12/MK70F12_mcg.h" - #include "device/MK70F12/MK70F12_mcm.h" - #include "device/MK70F12/MK70F12_mpu.h" - #include "device/MK70F12/MK70F12_nfc.h" - #include "device/MK70F12/MK70F12_nv.h" - #include "device/MK70F12/MK70F12_osc.h" - #include "device/MK70F12/MK70F12_pdb.h" - #include "device/MK70F12/MK70F12_pit.h" - #include "device/MK70F12/MK70F12_pmc.h" - #include "device/MK70F12/MK70F12_port.h" - #include "device/MK70F12/MK70F12_rcm.h" - #include "device/MK70F12/MK70F12_rfsys.h" - #include "device/MK70F12/MK70F12_rfvbat.h" - #include "device/MK70F12/MK70F12_rng.h" - #include "device/MK70F12/MK70F12_rtc.h" - #include "device/MK70F12/MK70F12_sdhc.h" - #include "device/MK70F12/MK70F12_sim.h" - #include "device/MK70F12/MK70F12_smc.h" - #include "device/MK70F12/MK70F12_spi.h" - #include "device/MK70F12/MK70F12_tsi.h" - #include "device/MK70F12/MK70F12_uart.h" - #include "device/MK70F12/MK70F12_usb.h" - #include "device/MK70F12/MK70F12_usbdcd.h" - #include "device/MK70F12/MK70F12_usbhs.h" - #include "device/MK70F12/MK70F12_vref.h" - #include "device/MK70F12/MK70F12_wdog.h" - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - - #define K70F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MK70F15/MK70F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MK70F15/MK70F15_adc.h" - #include "device/MK70F15/MK70F15_aips.h" - #include "device/MK70F15/MK70F15_axbs.h" - #include "device/MK70F15/MK70F15_can.h" - #include "device/MK70F15/MK70F15_cau.h" - #include "device/MK70F15/MK70F15_cmp.h" - #include "device/MK70F15/MK70F15_cmt.h" - #include "device/MK70F15/MK70F15_crc.h" - #include "device/MK70F15/MK70F15_dac.h" - #include "device/MK70F15/MK70F15_ddr.h" - #include "device/MK70F15/MK70F15_dma.h" - #include "device/MK70F15/MK70F15_dmamux.h" - #include "device/MK70F15/MK70F15_enet.h" - #include "device/MK70F15/MK70F15_ewm.h" - #include "device/MK70F15/MK70F15_fb.h" - #include "device/MK70F15/MK70F15_fmc.h" - #include "device/MK70F15/MK70F15_ftfe.h" - #include "device/MK70F15/MK70F15_ftm.h" - #include "device/MK70F15/MK70F15_gpio.h" - #include "device/MK70F15/MK70F15_i2c.h" - #include "device/MK70F15/MK70F15_i2s.h" - #include "device/MK70F15/MK70F15_lcdc.h" - #include "device/MK70F15/MK70F15_llwu.h" - #include "device/MK70F15/MK70F15_lmem.h" - #include "device/MK70F15/MK70F15_lptmr.h" - #include "device/MK70F15/MK70F15_mcg.h" - #include "device/MK70F15/MK70F15_mcm.h" - #include "device/MK70F15/MK70F15_mpu.h" - #include "device/MK70F15/MK70F15_nfc.h" - #include "device/MK70F15/MK70F15_nv.h" - #include "device/MK70F15/MK70F15_osc.h" - #include "device/MK70F15/MK70F15_pdb.h" - #include "device/MK70F15/MK70F15_pit.h" - #include "device/MK70F15/MK70F15_pmc.h" - #include "device/MK70F15/MK70F15_port.h" - #include "device/MK70F15/MK70F15_rcm.h" - #include "device/MK70F15/MK70F15_rfsys.h" - #include "device/MK70F15/MK70F15_rfvbat.h" - #include "device/MK70F15/MK70F15_rng.h" - #include "device/MK70F15/MK70F15_rtc.h" - #include "device/MK70F15/MK70F15_sdhc.h" - #include "device/MK70F15/MK70F15_sim.h" - #include "device/MK70F15/MK70F15_smc.h" - #include "device/MK70F15/MK70F15_spi.h" - #include "device/MK70F15/MK70F15_tsi.h" - #include "device/MK70F15/MK70F15_uart.h" - #include "device/MK70F15/MK70F15_usb.h" - #include "device/MK70F15/MK70F15_usbdcd.h" - #include "device/MK70F15/MK70F15_usbhs.h" - #include "device/MK70F15/MK70F15_vref.h" - #include "device/MK70F15/MK70F15_wdog.h" - -#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \ - defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \ - defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4)) - - #define KL02Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL02Z4/MKL02Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL02Z4/MKL02Z4_adc.h" - #include "device/MKL02Z4/MKL02Z4_cmp.h" - #include "device/MKL02Z4/MKL02Z4_fgpio.h" - #include "device/MKL02Z4/MKL02Z4_ftfa.h" - #include "device/MKL02Z4/MKL02Z4_gpio.h" - #include "device/MKL02Z4/MKL02Z4_i2c.h" - #include "device/MKL02Z4/MKL02Z4_lptmr.h" - #include "device/MKL02Z4/MKL02Z4_mcg.h" - #include "device/MKL02Z4/MKL02Z4_mcm.h" - #include "device/MKL02Z4/MKL02Z4_mtb.h" - #include "device/MKL02Z4/MKL02Z4_mtbdwt.h" - #include "device/MKL02Z4/MKL02Z4_nv.h" - #include "device/MKL02Z4/MKL02Z4_osc.h" - #include "device/MKL02Z4/MKL02Z4_pmc.h" - #include "device/MKL02Z4/MKL02Z4_port.h" - #include "device/MKL02Z4/MKL02Z4_rcm.h" - #include "device/MKL02Z4/MKL02Z4_rom.h" - #include "device/MKL02Z4/MKL02Z4_sim.h" - #include "device/MKL02Z4/MKL02Z4_smc.h" - #include "device/MKL02Z4/MKL02Z4_spi.h" - #include "device/MKL02Z4/MKL02Z4_tpm.h" - #include "device/MKL02Z4/MKL02Z4_uart0.h" - -#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \ - defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \ - defined(CPU_MKL03Z32VFK4)) - - #define KL03Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL03Z4/MKL03Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL03Z4/MKL03Z4_adc.h" - #include "device/MKL03Z4/MKL03Z4_cmp.h" - #include "device/MKL03Z4/MKL03Z4_fgpio.h" - #include "device/MKL03Z4/MKL03Z4_ftfa.h" - #include "device/MKL03Z4/MKL03Z4_gpio.h" - #include "device/MKL03Z4/MKL03Z4_i2c.h" - #include "device/MKL03Z4/MKL03Z4_llwu.h" - #include "device/MKL03Z4/MKL03Z4_lptmr.h" - #include "device/MKL03Z4/MKL03Z4_lpuart.h" - #include "device/MKL03Z4/MKL03Z4_mcg.h" - #include "device/MKL03Z4/MKL03Z4_mcm.h" - #include "device/MKL03Z4/MKL03Z4_mtb.h" - #include "device/MKL03Z4/MKL03Z4_mtbdwt.h" - #include "device/MKL03Z4/MKL03Z4_nv.h" - #include "device/MKL03Z4/MKL03Z4_osc.h" - #include "device/MKL03Z4/MKL03Z4_pmc.h" - #include "device/MKL03Z4/MKL03Z4_port.h" - #include "device/MKL03Z4/MKL03Z4_rcm.h" - #include "device/MKL03Z4/MKL03Z4_rfsys.h" - #include "device/MKL03Z4/MKL03Z4_rom.h" - #include "device/MKL03Z4/MKL03Z4_rtc.h" - #include "device/MKL03Z4/MKL03Z4_sim.h" - #include "device/MKL03Z4/MKL03Z4_smc.h" - #include "device/MKL03Z4/MKL03Z4_spi.h" - #include "device/MKL03Z4/MKL03Z4_tpm.h" - #include "device/MKL03Z4/MKL03Z4_vref.h" - -#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \ - defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \ - defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ - defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)) - - #define KL05Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL05Z4/MKL05Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL05Z4/MKL05Z4_adc.h" - #include "device/MKL05Z4/MKL05Z4_cmp.h" - #include "device/MKL05Z4/MKL05Z4_dac.h" - #include "device/MKL05Z4/MKL05Z4_dma.h" - #include "device/MKL05Z4/MKL05Z4_dmamux.h" - #include "device/MKL05Z4/MKL05Z4_fgpio.h" - #include "device/MKL05Z4/MKL05Z4_ftfa.h" - #include "device/MKL05Z4/MKL05Z4_gpio.h" - #include "device/MKL05Z4/MKL05Z4_i2c.h" - #include "device/MKL05Z4/MKL05Z4_llwu.h" - #include "device/MKL05Z4/MKL05Z4_lptmr.h" - #include "device/MKL05Z4/MKL05Z4_mcg.h" - #include "device/MKL05Z4/MKL05Z4_mcm.h" - #include "device/MKL05Z4/MKL05Z4_mtb.h" - #include "device/MKL05Z4/MKL05Z4_mtbdwt.h" - #include "device/MKL05Z4/MKL05Z4_nv.h" - #include "device/MKL05Z4/MKL05Z4_osc.h" - #include "device/MKL05Z4/MKL05Z4_pit.h" - #include "device/MKL05Z4/MKL05Z4_pmc.h" - #include "device/MKL05Z4/MKL05Z4_port.h" - #include "device/MKL05Z4/MKL05Z4_rcm.h" - #include "device/MKL05Z4/MKL05Z4_rom.h" - #include "device/MKL05Z4/MKL05Z4_rtc.h" - #include "device/MKL05Z4/MKL05Z4_sim.h" - #include "device/MKL05Z4/MKL05Z4_smc.h" - #include "device/MKL05Z4/MKL05Z4_spi.h" - #include "device/MKL05Z4/MKL05Z4_tpm.h" - #include "device/MKL05Z4/MKL05Z4_tsi.h" - #include "device/MKL05Z4/MKL05Z4_uart0.h" - -#elif (defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \ - defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || \ - defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ - defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4)) - - #define KL13Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL13Z4/MKL13Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL13Z4/MKL13Z4_adc.h" - #include "device/MKL13Z4/MKL13Z4_cmp.h" - #include "device/MKL13Z4/MKL13Z4_dac.h" - #include "device/MKL13Z4/MKL13Z4_dma.h" - #include "device/MKL13Z4/MKL13Z4_dmamux.h" - #include "device/MKL13Z4/MKL13Z4_flexio.h" - #include "device/MKL13Z4/MKL13Z4_ftfa.h" - #include "device/MKL13Z4/MKL13Z4_gpio.h" - #include "device/MKL13Z4/MKL13Z4_i2c.h" - #include "device/MKL13Z4/MKL13Z4_i2s.h" - #include "device/MKL13Z4/MKL13Z4_llwu.h" - #include "device/MKL13Z4/MKL13Z4_lptmr.h" - #include "device/MKL13Z4/MKL13Z4_lpuart.h" - #include "device/MKL13Z4/MKL13Z4_mcg.h" - #include "device/MKL13Z4/MKL13Z4_mcm.h" - #include "device/MKL13Z4/MKL13Z4_mtb.h" - #include "device/MKL13Z4/MKL13Z4_mtbdwt.h" - #include "device/MKL13Z4/MKL13Z4_nv.h" - #include "device/MKL13Z4/MKL13Z4_osc.h" - #include "device/MKL13Z4/MKL13Z4_pit.h" - #include "device/MKL13Z4/MKL13Z4_pmc.h" - #include "device/MKL13Z4/MKL13Z4_port.h" - #include "device/MKL13Z4/MKL13Z4_rcm.h" - #include "device/MKL13Z4/MKL13Z4_rom.h" - #include "device/MKL13Z4/MKL13Z4_rtc.h" - #include "device/MKL13Z4/MKL13Z4_sim.h" - #include "device/MKL13Z4/MKL13Z4_smc.h" - #include "device/MKL13Z4/MKL13Z4_spi.h" - #include "device/MKL13Z4/MKL13Z4_tpm.h" - #include "device/MKL13Z4/MKL13Z4_uart.h" - #include "device/MKL13Z4/MKL13Z4_vref.h" - -#elif (defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \ - defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || \ - defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ - defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4)) - - #define KL23Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL23Z4/MKL23Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL23Z4/MKL23Z4_adc.h" - #include "device/MKL23Z4/MKL23Z4_cmp.h" - #include "device/MKL23Z4/MKL23Z4_dac.h" - #include "device/MKL23Z4/MKL23Z4_dma.h" - #include "device/MKL23Z4/MKL23Z4_dmamux.h" - #include "device/MKL23Z4/MKL23Z4_flexio.h" - #include "device/MKL23Z4/MKL23Z4_ftfa.h" - #include "device/MKL23Z4/MKL23Z4_gpio.h" - #include "device/MKL23Z4/MKL23Z4_i2c.h" - #include "device/MKL23Z4/MKL23Z4_i2s.h" - #include "device/MKL23Z4/MKL23Z4_llwu.h" - #include "device/MKL23Z4/MKL23Z4_lptmr.h" - #include "device/MKL23Z4/MKL23Z4_lpuart.h" - #include "device/MKL23Z4/MKL23Z4_mcg.h" - #include "device/MKL23Z4/MKL23Z4_mcm.h" - #include "device/MKL23Z4/MKL23Z4_mtb.h" - #include "device/MKL23Z4/MKL23Z4_mtbdwt.h" - #include "device/MKL23Z4/MKL23Z4_nv.h" - #include "device/MKL23Z4/MKL23Z4_osc.h" - #include "device/MKL23Z4/MKL23Z4_pit.h" - #include "device/MKL23Z4/MKL23Z4_pmc.h" - #include "device/MKL23Z4/MKL23Z4_port.h" - #include "device/MKL23Z4/MKL23Z4_rcm.h" - #include "device/MKL23Z4/MKL23Z4_rom.h" - #include "device/MKL23Z4/MKL23Z4_rtc.h" - #include "device/MKL23Z4/MKL23Z4_sim.h" - #include "device/MKL23Z4/MKL23Z4_smc.h" - #include "device/MKL23Z4/MKL23Z4_spi.h" - #include "device/MKL23Z4/MKL23Z4_tpm.h" - #include "device/MKL23Z4/MKL23Z4_uart.h" - #include "device/MKL23Z4/MKL23Z4_usb.h" - #include "device/MKL23Z4/MKL23Z4_vref.h" - -#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ - defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)) - - #define KL25Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL25Z4/MKL25Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL25Z4/MKL25Z4_adc.h" - #include "device/MKL25Z4/MKL25Z4_cmp.h" - #include "device/MKL25Z4/MKL25Z4_dac.h" - #include "device/MKL25Z4/MKL25Z4_dma.h" - #include "device/MKL25Z4/MKL25Z4_dmamux.h" - #include "device/MKL25Z4/MKL25Z4_fgpio.h" - #include "device/MKL25Z4/MKL25Z4_ftfa.h" - #include "device/MKL25Z4/MKL25Z4_gpio.h" - #include "device/MKL25Z4/MKL25Z4_i2c.h" - #include "device/MKL25Z4/MKL25Z4_llwu.h" - #include "device/MKL25Z4/MKL25Z4_lptmr.h" - #include "device/MKL25Z4/MKL25Z4_mcg.h" - #include "device/MKL25Z4/MKL25Z4_mcm.h" - #include "device/MKL25Z4/MKL25Z4_mtb.h" - #include "device/MKL25Z4/MKL25Z4_mtbdwt.h" - #include "device/MKL25Z4/MKL25Z4_nv.h" - #include "device/MKL25Z4/MKL25Z4_osc.h" - #include "device/MKL25Z4/MKL25Z4_pit.h" - #include "device/MKL25Z4/MKL25Z4_pmc.h" - #include "device/MKL25Z4/MKL25Z4_port.h" - #include "device/MKL25Z4/MKL25Z4_rcm.h" - #include "device/MKL25Z4/MKL25Z4_rom.h" - #include "device/MKL25Z4/MKL25Z4_rtc.h" - #include "device/MKL25Z4/MKL25Z4_sim.h" - #include "device/MKL25Z4/MKL25Z4_smc.h" - #include "device/MKL25Z4/MKL25Z4_spi.h" - #include "device/MKL25Z4/MKL25Z4_tpm.h" - #include "device/MKL25Z4/MKL25Z4_tsi.h" - #include "device/MKL25Z4/MKL25Z4_uart.h" - #include "device/MKL25Z4/MKL25Z4_uart0.h" - #include "device/MKL25Z4/MKL25Z4_usb.h" - -#elif (defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || \ - defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || \ - defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \ - defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ - defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4)) - - #define KL26Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL26Z4/MKL26Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL26Z4/MKL26Z4_adc.h" - #include "device/MKL26Z4/MKL26Z4_cmp.h" - #include "device/MKL26Z4/MKL26Z4_dac.h" - #include "device/MKL26Z4/MKL26Z4_dma.h" - #include "device/MKL26Z4/MKL26Z4_dmamux.h" - #include "device/MKL26Z4/MKL26Z4_fgpio.h" - #include "device/MKL26Z4/MKL26Z4_ftfa.h" - #include "device/MKL26Z4/MKL26Z4_gpio.h" - #include "device/MKL26Z4/MKL26Z4_i2c.h" - #include "device/MKL26Z4/MKL26Z4_i2s.h" - #include "device/MKL26Z4/MKL26Z4_llwu.h" - #include "device/MKL26Z4/MKL26Z4_lptmr.h" - #include "device/MKL26Z4/MKL26Z4_mcg.h" - #include "device/MKL26Z4/MKL26Z4_mcm.h" - #include "device/MKL26Z4/MKL26Z4_mtb.h" - #include "device/MKL26Z4/MKL26Z4_mtbdwt.h" - #include "device/MKL26Z4/MKL26Z4_nv.h" - #include "device/MKL26Z4/MKL26Z4_osc.h" - #include "device/MKL26Z4/MKL26Z4_pit.h" - #include "device/MKL26Z4/MKL26Z4_pmc.h" - #include "device/MKL26Z4/MKL26Z4_port.h" - #include "device/MKL26Z4/MKL26Z4_rcm.h" - #include "device/MKL26Z4/MKL26Z4_rom.h" - #include "device/MKL26Z4/MKL26Z4_rtc.h" - #include "device/MKL26Z4/MKL26Z4_sim.h" - #include "device/MKL26Z4/MKL26Z4_smc.h" - #include "device/MKL26Z4/MKL26Z4_spi.h" - #include "device/MKL26Z4/MKL26Z4_tpm.h" - #include "device/MKL26Z4/MKL26Z4_tsi.h" - #include "device/MKL26Z4/MKL26Z4_uart.h" - #include "device/MKL26Z4/MKL26Z4_uart0.h" - #include "device/MKL26Z4/MKL26Z4_usb.h" - -#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \ - defined(CPU_MKL33Z256VMP4)) - - #define KL33Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL33Z4/MKL33Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL33Z4/MKL33Z4_adc.h" - #include "device/MKL33Z4/MKL33Z4_cmp.h" - #include "device/MKL33Z4/MKL33Z4_dac.h" - #include "device/MKL33Z4/MKL33Z4_dma.h" - #include "device/MKL33Z4/MKL33Z4_dmamux.h" - #include "device/MKL33Z4/MKL33Z4_flexio.h" - #include "device/MKL33Z4/MKL33Z4_ftfa.h" - #include "device/MKL33Z4/MKL33Z4_gpio.h" - #include "device/MKL33Z4/MKL33Z4_i2c.h" - #include "device/MKL33Z4/MKL33Z4_i2s.h" - #include "device/MKL33Z4/MKL33Z4_lcd.h" - #include "device/MKL33Z4/MKL33Z4_llwu.h" - #include "device/MKL33Z4/MKL33Z4_lptmr.h" - #include "device/MKL33Z4/MKL33Z4_lpuart.h" - #include "device/MKL33Z4/MKL33Z4_mcg.h" - #include "device/MKL33Z4/MKL33Z4_mcm.h" - #include "device/MKL33Z4/MKL33Z4_mtb.h" - #include "device/MKL33Z4/MKL33Z4_mtbdwt.h" - #include "device/MKL33Z4/MKL33Z4_nv.h" - #include "device/MKL33Z4/MKL33Z4_osc.h" - #include "device/MKL33Z4/MKL33Z4_pit.h" - #include "device/MKL33Z4/MKL33Z4_pmc.h" - #include "device/MKL33Z4/MKL33Z4_port.h" - #include "device/MKL33Z4/MKL33Z4_rcm.h" - #include "device/MKL33Z4/MKL33Z4_rom.h" - #include "device/MKL33Z4/MKL33Z4_rtc.h" - #include "device/MKL33Z4/MKL33Z4_sim.h" - #include "device/MKL33Z4/MKL33Z4_smc.h" - #include "device/MKL33Z4/MKL33Z4_spi.h" - #include "device/MKL33Z4/MKL33Z4_tpm.h" - #include "device/MKL33Z4/MKL33Z4_uart.h" - #include "device/MKL33Z4/MKL33Z4_vref.h" - -#elif (defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || \ - defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)) - - #define KL43Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL43Z4/MKL43Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL43Z4/MKL43Z4_adc.h" - #include "device/MKL43Z4/MKL43Z4_cmp.h" - #include "device/MKL43Z4/MKL43Z4_dac.h" - #include "device/MKL43Z4/MKL43Z4_dma.h" - #include "device/MKL43Z4/MKL43Z4_dmamux.h" - #include "device/MKL43Z4/MKL43Z4_flexio.h" - #include "device/MKL43Z4/MKL43Z4_ftfa.h" - #include "device/MKL43Z4/MKL43Z4_gpio.h" - #include "device/MKL43Z4/MKL43Z4_i2c.h" - #include "device/MKL43Z4/MKL43Z4_i2s.h" - #include "device/MKL43Z4/MKL43Z4_lcd.h" - #include "device/MKL43Z4/MKL43Z4_llwu.h" - #include "device/MKL43Z4/MKL43Z4_lptmr.h" - #include "device/MKL43Z4/MKL43Z4_lpuart.h" - #include "device/MKL43Z4/MKL43Z4_mcg.h" - #include "device/MKL43Z4/MKL43Z4_mcm.h" - #include "device/MKL43Z4/MKL43Z4_mtb.h" - #include "device/MKL43Z4/MKL43Z4_mtbdwt.h" - #include "device/MKL43Z4/MKL43Z4_nv.h" - #include "device/MKL43Z4/MKL43Z4_osc.h" - #include "device/MKL43Z4/MKL43Z4_pit.h" - #include "device/MKL43Z4/MKL43Z4_pmc.h" - #include "device/MKL43Z4/MKL43Z4_port.h" - #include "device/MKL43Z4/MKL43Z4_rcm.h" - #include "device/MKL43Z4/MKL43Z4_rom.h" - #include "device/MKL43Z4/MKL43Z4_rtc.h" - #include "device/MKL43Z4/MKL43Z4_sim.h" - #include "device/MKL43Z4/MKL43Z4_smc.h" - #include "device/MKL43Z4/MKL43Z4_spi.h" - #include "device/MKL43Z4/MKL43Z4_tpm.h" - #include "device/MKL43Z4/MKL43Z4_uart.h" - #include "device/MKL43Z4/MKL43Z4_usb.h" - #include "device/MKL43Z4/MKL43Z4_vref.h" - -#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ - defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)) - - #define KL46Z4_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKL46Z4/MKL46Z4.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKL46Z4/MKL46Z4_adc.h" - #include "device/MKL46Z4/MKL46Z4_cmp.h" - #include "device/MKL46Z4/MKL46Z4_dac.h" - #include "device/MKL46Z4/MKL46Z4_dma.h" - #include "device/MKL46Z4/MKL46Z4_dmamux.h" - #include "device/MKL46Z4/MKL46Z4_fgpio.h" - #include "device/MKL46Z4/MKL46Z4_ftfa.h" - #include "device/MKL46Z4/MKL46Z4_gpio.h" - #include "device/MKL46Z4/MKL46Z4_i2c.h" - #include "device/MKL46Z4/MKL46Z4_i2s.h" - #include "device/MKL46Z4/MKL46Z4_lcd.h" - #include "device/MKL46Z4/MKL46Z4_llwu.h" - #include "device/MKL46Z4/MKL46Z4_lptmr.h" - #include "device/MKL46Z4/MKL46Z4_mcg.h" - #include "device/MKL46Z4/MKL46Z4_mcm.h" - #include "device/MKL46Z4/MKL46Z4_mtb.h" - #include "device/MKL46Z4/MKL46Z4_mtbdwt.h" - #include "device/MKL46Z4/MKL46Z4_nv.h" - #include "device/MKL46Z4/MKL46Z4_osc.h" - #include "device/MKL46Z4/MKL46Z4_pit.h" - #include "device/MKL46Z4/MKL46Z4_pmc.h" - #include "device/MKL46Z4/MKL46Z4_port.h" - #include "device/MKL46Z4/MKL46Z4_rcm.h" - #include "device/MKL46Z4/MKL46Z4_rom.h" - #include "device/MKL46Z4/MKL46Z4_rtc.h" - #include "device/MKL46Z4/MKL46Z4_sim.h" - #include "device/MKL46Z4/MKL46Z4_smc.h" - #include "device/MKL46Z4/MKL46Z4_spi.h" - #include "device/MKL46Z4/MKL46Z4_tpm.h" - #include "device/MKL46Z4/MKL46Z4_tsi.h" - #include "device/MKL46Z4/MKL46Z4_uart.h" - #include "device/MKL46Z4/MKL46Z4_uart0.h" - #include "device/MKL46Z4/MKL46Z4_usb.h" - -#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ - defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)) - - #define KV30F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV30F12810/MKV30F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV30F12810/MKV30F12810_adc.h" - #include "device/MKV30F12810/MKV30F12810_cmp.h" - #include "device/MKV30F12810/MKV30F12810_crc.h" - #include "device/MKV30F12810/MKV30F12810_dac.h" - #include "device/MKV30F12810/MKV30F12810_dma.h" - #include "device/MKV30F12810/MKV30F12810_dmamux.h" - #include "device/MKV30F12810/MKV30F12810_ewm.h" - #include "device/MKV30F12810/MKV30F12810_fmc.h" - #include "device/MKV30F12810/MKV30F12810_ftfa.h" - #include "device/MKV30F12810/MKV30F12810_ftm.h" - #include "device/MKV30F12810/MKV30F12810_gpio.h" - #include "device/MKV30F12810/MKV30F12810_i2c.h" - #include "device/MKV30F12810/MKV30F12810_llwu.h" - #include "device/MKV30F12810/MKV30F12810_lptmr.h" - #include "device/MKV30F12810/MKV30F12810_mcg.h" - #include "device/MKV30F12810/MKV30F12810_mcm.h" - #include "device/MKV30F12810/MKV30F12810_nv.h" - #include "device/MKV30F12810/MKV30F12810_osc.h" - #include "device/MKV30F12810/MKV30F12810_pdb.h" - #include "device/MKV30F12810/MKV30F12810_pit.h" - #include "device/MKV30F12810/MKV30F12810_pmc.h" - #include "device/MKV30F12810/MKV30F12810_port.h" - #include "device/MKV30F12810/MKV30F12810_rcm.h" - #include "device/MKV30F12810/MKV30F12810_sim.h" - #include "device/MKV30F12810/MKV30F12810_smc.h" - #include "device/MKV30F12810/MKV30F12810_spi.h" - #include "device/MKV30F12810/MKV30F12810_uart.h" - #include "device/MKV30F12810/MKV30F12810_vref.h" - #include "device/MKV30F12810/MKV30F12810_wdog.h" - -#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)) - - #define KV31F12810_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV31F12810/MKV31F12810.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV31F12810/MKV31F12810_adc.h" - #include "device/MKV31F12810/MKV31F12810_cmp.h" - #include "device/MKV31F12810/MKV31F12810_crc.h" - #include "device/MKV31F12810/MKV31F12810_dac.h" - #include "device/MKV31F12810/MKV31F12810_dma.h" - #include "device/MKV31F12810/MKV31F12810_dmamux.h" - #include "device/MKV31F12810/MKV31F12810_ewm.h" - #include "device/MKV31F12810/MKV31F12810_fmc.h" - #include "device/MKV31F12810/MKV31F12810_ftfa.h" - #include "device/MKV31F12810/MKV31F12810_ftm.h" - #include "device/MKV31F12810/MKV31F12810_gpio.h" - #include "device/MKV31F12810/MKV31F12810_i2c.h" - #include "device/MKV31F12810/MKV31F12810_llwu.h" - #include "device/MKV31F12810/MKV31F12810_lptmr.h" - #include "device/MKV31F12810/MKV31F12810_lpuart.h" - #include "device/MKV31F12810/MKV31F12810_mcg.h" - #include "device/MKV31F12810/MKV31F12810_mcm.h" - #include "device/MKV31F12810/MKV31F12810_nv.h" - #include "device/MKV31F12810/MKV31F12810_osc.h" - #include "device/MKV31F12810/MKV31F12810_pdb.h" - #include "device/MKV31F12810/MKV31F12810_pit.h" - #include "device/MKV31F12810/MKV31F12810_pmc.h" - #include "device/MKV31F12810/MKV31F12810_port.h" - #include "device/MKV31F12810/MKV31F12810_rcm.h" - #include "device/MKV31F12810/MKV31F12810_rfsys.h" - #include "device/MKV31F12810/MKV31F12810_sim.h" - #include "device/MKV31F12810/MKV31F12810_smc.h" - #include "device/MKV31F12810/MKV31F12810_spi.h" - #include "device/MKV31F12810/MKV31F12810_uart.h" - #include "device/MKV31F12810/MKV31F12810_vref.h" - #include "device/MKV31F12810/MKV31F12810_wdog.h" - -#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)) - - #define KV31F25612_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV31F25612/MKV31F25612.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV31F25612/MKV31F25612_adc.h" - #include "device/MKV31F25612/MKV31F25612_cmp.h" - #include "device/MKV31F25612/MKV31F25612_crc.h" - #include "device/MKV31F25612/MKV31F25612_dac.h" - #include "device/MKV31F25612/MKV31F25612_dma.h" - #include "device/MKV31F25612/MKV31F25612_dmamux.h" - #include "device/MKV31F25612/MKV31F25612_ewm.h" - #include "device/MKV31F25612/MKV31F25612_fmc.h" - #include "device/MKV31F25612/MKV31F25612_ftfa.h" - #include "device/MKV31F25612/MKV31F25612_ftm.h" - #include "device/MKV31F25612/MKV31F25612_gpio.h" - #include "device/MKV31F25612/MKV31F25612_i2c.h" - #include "device/MKV31F25612/MKV31F25612_llwu.h" - #include "device/MKV31F25612/MKV31F25612_lptmr.h" - #include "device/MKV31F25612/MKV31F25612_lpuart.h" - #include "device/MKV31F25612/MKV31F25612_mcg.h" - #include "device/MKV31F25612/MKV31F25612_mcm.h" - #include "device/MKV31F25612/MKV31F25612_nv.h" - #include "device/MKV31F25612/MKV31F25612_osc.h" - #include "device/MKV31F25612/MKV31F25612_pdb.h" - #include "device/MKV31F25612/MKV31F25612_pit.h" - #include "device/MKV31F25612/MKV31F25612_pmc.h" - #include "device/MKV31F25612/MKV31F25612_port.h" - #include "device/MKV31F25612/MKV31F25612_rcm.h" - #include "device/MKV31F25612/MKV31F25612_rfsys.h" - #include "device/MKV31F25612/MKV31F25612_rng.h" - #include "device/MKV31F25612/MKV31F25612_sim.h" - #include "device/MKV31F25612/MKV31F25612_smc.h" - #include "device/MKV31F25612/MKV31F25612_spi.h" - #include "device/MKV31F25612/MKV31F25612_uart.h" - #include "device/MKV31F25612/MKV31F25612_vref.h" - #include "device/MKV31F25612/MKV31F25612_wdog.h" - -#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)) - - #define KV31F51212_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV31F51212/MKV31F51212.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV31F51212/MKV31F51212_adc.h" - #include "device/MKV31F51212/MKV31F51212_cmp.h" - #include "device/MKV31F51212/MKV31F51212_crc.h" - #include "device/MKV31F51212/MKV31F51212_dac.h" - #include "device/MKV31F51212/MKV31F51212_dma.h" - #include "device/MKV31F51212/MKV31F51212_dmamux.h" - #include "device/MKV31F51212/MKV31F51212_ewm.h" - #include "device/MKV31F51212/MKV31F51212_fb.h" - #include "device/MKV31F51212/MKV31F51212_fmc.h" - #include "device/MKV31F51212/MKV31F51212_ftfa.h" - #include "device/MKV31F51212/MKV31F51212_ftm.h" - #include "device/MKV31F51212/MKV31F51212_gpio.h" - #include "device/MKV31F51212/MKV31F51212_i2c.h" - #include "device/MKV31F51212/MKV31F51212_llwu.h" - #include "device/MKV31F51212/MKV31F51212_lptmr.h" - #include "device/MKV31F51212/MKV31F51212_lpuart.h" - #include "device/MKV31F51212/MKV31F51212_mcg.h" - #include "device/MKV31F51212/MKV31F51212_mcm.h" - #include "device/MKV31F51212/MKV31F51212_nv.h" - #include "device/MKV31F51212/MKV31F51212_osc.h" - #include "device/MKV31F51212/MKV31F51212_pdb.h" - #include "device/MKV31F51212/MKV31F51212_pit.h" - #include "device/MKV31F51212/MKV31F51212_pmc.h" - #include "device/MKV31F51212/MKV31F51212_port.h" - #include "device/MKV31F51212/MKV31F51212_rcm.h" - #include "device/MKV31F51212/MKV31F51212_rfsys.h" - #include "device/MKV31F51212/MKV31F51212_rng.h" - #include "device/MKV31F51212/MKV31F51212_sim.h" - #include "device/MKV31F51212/MKV31F51212_smc.h" - #include "device/MKV31F51212/MKV31F51212_spi.h" - #include "device/MKV31F51212/MKV31F51212_uart.h" - #include "device/MKV31F51212/MKV31F51212_vref.h" - #include "device/MKV31F51212/MKV31F51212_wdog.h" - -#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \ - defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15)) - - #define KV40F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV40F15/MKV40F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV40F15/MKV40F15_adc.h" - #include "device/MKV40F15/MKV40F15_aoi.h" - #include "device/MKV40F15/MKV40F15_can.h" - #include "device/MKV40F15/MKV40F15_cmp.h" - #include "device/MKV40F15/MKV40F15_crc.h" - #include "device/MKV40F15/MKV40F15_dma.h" - #include "device/MKV40F15/MKV40F15_dmamux.h" - #include "device/MKV40F15/MKV40F15_enc.h" - #include "device/MKV40F15/MKV40F15_ewm.h" - #include "device/MKV40F15/MKV40F15_fmc.h" - #include "device/MKV40F15/MKV40F15_ftfa.h" - #include "device/MKV40F15/MKV40F15_ftm.h" - #include "device/MKV40F15/MKV40F15_gpio.h" - #include "device/MKV40F15/MKV40F15_i2c.h" - #include "device/MKV40F15/MKV40F15_llwu.h" - #include "device/MKV40F15/MKV40F15_lptmr.h" - #include "device/MKV40F15/MKV40F15_mcg.h" - #include "device/MKV40F15/MKV40F15_mcm.h" - #include "device/MKV40F15/MKV40F15_nv.h" - #include "device/MKV40F15/MKV40F15_osc.h" - #include "device/MKV40F15/MKV40F15_pdb.h" - #include "device/MKV40F15/MKV40F15_pit.h" - #include "device/MKV40F15/MKV40F15_pmc.h" - #include "device/MKV40F15/MKV40F15_port.h" - #include "device/MKV40F15/MKV40F15_rcm.h" - #include "device/MKV40F15/MKV40F15_sim.h" - #include "device/MKV40F15/MKV40F15_smc.h" - #include "device/MKV40F15/MKV40F15_spi.h" - #include "device/MKV40F15/MKV40F15_uart.h" - #include "device/MKV40F15/MKV40F15_vref.h" - #include "device/MKV40F15/MKV40F15_wdog.h" - #include "device/MKV40F15/MKV40F15_xbara.h" - #include "device/MKV40F15/MKV40F15_xbarb.h" - -#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15)) - - #define KV43F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV43F15/MKV43F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV43F15/MKV43F15_adc.h" - #include "device/MKV43F15/MKV43F15_aoi.h" - #include "device/MKV43F15/MKV43F15_can.h" - #include "device/MKV43F15/MKV43F15_cmp.h" - #include "device/MKV43F15/MKV43F15_crc.h" - #include "device/MKV43F15/MKV43F15_dma.h" - #include "device/MKV43F15/MKV43F15_dmamux.h" - #include "device/MKV43F15/MKV43F15_enc.h" - #include "device/MKV43F15/MKV43F15_ewm.h" - #include "device/MKV43F15/MKV43F15_fmc.h" - #include "device/MKV43F15/MKV43F15_ftfa.h" - #include "device/MKV43F15/MKV43F15_gpio.h" - #include "device/MKV43F15/MKV43F15_i2c.h" - #include "device/MKV43F15/MKV43F15_llwu.h" - #include "device/MKV43F15/MKV43F15_lptmr.h" - #include "device/MKV43F15/MKV43F15_mcg.h" - #include "device/MKV43F15/MKV43F15_mcm.h" - #include "device/MKV43F15/MKV43F15_nv.h" - #include "device/MKV43F15/MKV43F15_osc.h" - #include "device/MKV43F15/MKV43F15_pdb.h" - #include "device/MKV43F15/MKV43F15_pit.h" - #include "device/MKV43F15/MKV43F15_pmc.h" - #include "device/MKV43F15/MKV43F15_port.h" - #include "device/MKV43F15/MKV43F15_pwm.h" - #include "device/MKV43F15/MKV43F15_rcm.h" - #include "device/MKV43F15/MKV43F15_sim.h" - #include "device/MKV43F15/MKV43F15_smc.h" - #include "device/MKV43F15/MKV43F15_spi.h" - #include "device/MKV43F15/MKV43F15_uart.h" - #include "device/MKV43F15/MKV43F15_vref.h" - #include "device/MKV43F15/MKV43F15_wdog.h" - #include "device/MKV43F15/MKV43F15_xbara.h" - #include "device/MKV43F15/MKV43F15_xbarb.h" - -#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)) - - #define KV44F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV44F15/MKV44F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV44F15/MKV44F15_adc.h" - #include "device/MKV44F15/MKV44F15_aoi.h" - #include "device/MKV44F15/MKV44F15_can.h" - #include "device/MKV44F15/MKV44F15_cmp.h" - #include "device/MKV44F15/MKV44F15_crc.h" - #include "device/MKV44F15/MKV44F15_dac.h" - #include "device/MKV44F15/MKV44F15_dma.h" - #include "device/MKV44F15/MKV44F15_dmamux.h" - #include "device/MKV44F15/MKV44F15_enc.h" - #include "device/MKV44F15/MKV44F15_ewm.h" - #include "device/MKV44F15/MKV44F15_fmc.h" - #include "device/MKV44F15/MKV44F15_ftfa.h" - #include "device/MKV44F15/MKV44F15_gpio.h" - #include "device/MKV44F15/MKV44F15_i2c.h" - #include "device/MKV44F15/MKV44F15_llwu.h" - #include "device/MKV44F15/MKV44F15_lptmr.h" - #include "device/MKV44F15/MKV44F15_mcg.h" - #include "device/MKV44F15/MKV44F15_mcm.h" - #include "device/MKV44F15/MKV44F15_nv.h" - #include "device/MKV44F15/MKV44F15_osc.h" - #include "device/MKV44F15/MKV44F15_pdb.h" - #include "device/MKV44F15/MKV44F15_pit.h" - #include "device/MKV44F15/MKV44F15_pmc.h" - #include "device/MKV44F15/MKV44F15_port.h" - #include "device/MKV44F15/MKV44F15_pwm.h" - #include "device/MKV44F15/MKV44F15_rcm.h" - #include "device/MKV44F15/MKV44F15_sim.h" - #include "device/MKV44F15/MKV44F15_smc.h" - #include "device/MKV44F15/MKV44F15_spi.h" - #include "device/MKV44F15/MKV44F15_uart.h" - #include "device/MKV44F15/MKV44F15_vref.h" - #include "device/MKV44F15/MKV44F15_wdog.h" - #include "device/MKV44F15/MKV44F15_xbara.h" - #include "device/MKV44F15/MKV44F15_xbarb.h" - -#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \ - defined(CPU_MKV45F256VLL15)) - - #define KV45F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV45F15/MKV45F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV45F15/MKV45F15_adc.h" - #include "device/MKV45F15/MKV45F15_aoi.h" - #include "device/MKV45F15/MKV45F15_can.h" - #include "device/MKV45F15/MKV45F15_cmp.h" - #include "device/MKV45F15/MKV45F15_crc.h" - #include "device/MKV45F15/MKV45F15_dma.h" - #include "device/MKV45F15/MKV45F15_dmamux.h" - #include "device/MKV45F15/MKV45F15_enc.h" - #include "device/MKV45F15/MKV45F15_ewm.h" - #include "device/MKV45F15/MKV45F15_fmc.h" - #include "device/MKV45F15/MKV45F15_ftfa.h" - #include "device/MKV45F15/MKV45F15_ftm.h" - #include "device/MKV45F15/MKV45F15_gpio.h" - #include "device/MKV45F15/MKV45F15_i2c.h" - #include "device/MKV45F15/MKV45F15_llwu.h" - #include "device/MKV45F15/MKV45F15_lptmr.h" - #include "device/MKV45F15/MKV45F15_mcg.h" - #include "device/MKV45F15/MKV45F15_mcm.h" - #include "device/MKV45F15/MKV45F15_nv.h" - #include "device/MKV45F15/MKV45F15_osc.h" - #include "device/MKV45F15/MKV45F15_pdb.h" - #include "device/MKV45F15/MKV45F15_pit.h" - #include "device/MKV45F15/MKV45F15_pmc.h" - #include "device/MKV45F15/MKV45F15_port.h" - #include "device/MKV45F15/MKV45F15_pwm.h" - #include "device/MKV45F15/MKV45F15_rcm.h" - #include "device/MKV45F15/MKV45F15_sim.h" - #include "device/MKV45F15/MKV45F15_smc.h" - #include "device/MKV45F15/MKV45F15_spi.h" - #include "device/MKV45F15/MKV45F15_uart.h" - #include "device/MKV45F15/MKV45F15_vref.h" - #include "device/MKV45F15/MKV45F15_wdog.h" - #include "device/MKV45F15/MKV45F15_xbara.h" - #include "device/MKV45F15/MKV45F15_xbarb.h" - -#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \ - defined(CPU_MKV46F256VLL15)) - - #define KV46F15_SERIES - - /* CMSIS-style register definitions */ - #include "device/MKV46F15/MKV46F15.h" - - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.) */ - #include "device/MKV46F15/MKV46F15_adc.h" - #include "device/MKV46F15/MKV46F15_aoi.h" - #include "device/MKV46F15/MKV46F15_can.h" - #include "device/MKV46F15/MKV46F15_cmp.h" - #include "device/MKV46F15/MKV46F15_crc.h" - #include "device/MKV46F15/MKV46F15_dac.h" - #include "device/MKV46F15/MKV46F15_dma.h" - #include "device/MKV46F15/MKV46F15_dmamux.h" - #include "device/MKV46F15/MKV46F15_enc.h" - #include "device/MKV46F15/MKV46F15_ewm.h" - #include "device/MKV46F15/MKV46F15_fmc.h" - #include "device/MKV46F15/MKV46F15_ftfa.h" - #include "device/MKV46F15/MKV46F15_ftm.h" - #include "device/MKV46F15/MKV46F15_gpio.h" - #include "device/MKV46F15/MKV46F15_i2c.h" - #include "device/MKV46F15/MKV46F15_llwu.h" - #include "device/MKV46F15/MKV46F15_lptmr.h" - #include "device/MKV46F15/MKV46F15_mcg.h" - #include "device/MKV46F15/MKV46F15_mcm.h" - #include "device/MKV46F15/MKV46F15_nv.h" - #include "device/MKV46F15/MKV46F15_osc.h" - #include "device/MKV46F15/MKV46F15_pdb.h" - #include "device/MKV46F15/MKV46F15_pit.h" - #include "device/MKV46F15/MKV46F15_pmc.h" - #include "device/MKV46F15/MKV46F15_port.h" - #include "device/MKV46F15/MKV46F15_pwm.h" - #include "device/MKV46F15/MKV46F15_rcm.h" - #include "device/MKV46F15/MKV46F15_sim.h" - #include "device/MKV46F15/MKV46F15_smc.h" - #include "device/MKV46F15/MKV46F15_spi.h" - #include "device/MKV46F15/MKV46F15_uart.h" - #include "device/MKV46F15/MKV46F15_vref.h" - #include "device/MKV46F15/MKV46F15_wdog.h" - #include "device/MKV46F15/MKV46F15_xbara.h" - #include "device/MKV46F15/MKV46F15_xbarb.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogin_api.c deleted file mode 100644 index a8ddedbfe6e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogin_api.c +++ /dev/null @@ -1,80 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralNames.h" -#include "fsl_adc_hal.h" -#include "fsl_clock_manager.h" -#include "PeripheralPins.h" -#include "fsl_device_registers.h" - -#define MAX_FADC 6000000 - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; - uint32_t adc_addrs[] = ADC_BASE_ADDRS; - - CLOCK_SYS_EnableAdcClock(instance); - - uint32_t bus_clock; - CLOCK_SYS_GetFreq(kBusClock, &bus_clock); - uint32_t clkdiv; - for (clkdiv = 0; clkdiv < 4; clkdiv++) { - if ((bus_clock >> clkdiv) <= MAX_FADC) - break; - } - if (clkdiv == 4) { - clkdiv = 0x3; //Set max div - } - /* adc is enabled/triggered when reading. */ - ADC_HAL_Init(adc_addrs[instance]); - ADC_HAL_SetClkSrcMode(adc_addrs[instance], kAdcClkSrcOfBusClk); - ADC_HAL_SetClkDividerMode(adc_addrs[instance], (adc_clk_divider_mode_t)(clkdiv & 0x3)); - ADC_HAL_SetRefVoltSrcMode(adc_addrs[instance], kAdcRefVoltSrcOfVref); - ADC_HAL_SetResolutionMode(adc_addrs[instance], kAdcResolutionBitOfSingleEndAs16); - ADC_HAL_SetContinuousConvCmd(adc_addrs[instance], false); - ADC_HAL_SetHwTriggerCmd(adc_addrs[instance], false); /* sw trigger */ - ADC_HAL_SetHwAverageCmd(adc_addrs[instance], true); - ADC_HAL_SetHwAverageMode(adc_addrs[instance], kAdcHwAverageCountOf4); - ADC_HAL_SetChnMuxMode(adc_addrs[instance], - obj->adc & (1 << ADC_B_CHANNEL_SHIFT) ? kAdcChnMuxOfB : kAdcChnMuxOfA); - - pinmap_pinout(pin, PinMap_ADC); -} - -uint16_t analogin_read_u16(analogin_t *obj) { - uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; - uint32_t adc_addrs[] = ADC_BASE_ADDRS; - /* sw trigger (SC1A) */ - ADC_HAL_ConfigChn(adc_addrs[instance], 0, false, false, obj->adc & 0xF); - while (!ADC_HAL_GetChnConvCompletedCmd(adc_addrs[instance], 0)); - return ADC_HAL_GetChnConvValueRAW(adc_addrs[instance], 0); -} - -float analogin_read(analogin_t *obj) { - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)0xFFFF); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogout_api.c deleted file mode 100644 index 3bbed25800c..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogout_api.c +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" -#include "fsl_clock_manager.h" - -#define RANGE_12BIT 0xFFF - -void analogout_init(dac_t *obj, PinName pin) { - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - if (obj->dac == (DACName)NC) { - error("DAC pin mapping failed"); - } - - SIM_HAL_EnableDacClock(SIM_BASE, 0); - - DAC0->DAT[obj->dac].DATH = 0; - DAC0->DAT[obj->dac].DATL = 0; - - DAC0->C1 = DAC_C1_DACBFMD(2); // One-Time Scan Mode - - DAC0->C0 = DAC_C0_DACEN_MASK // Enable - | DAC_C0_DACSWTRG_MASK // Software Trigger - | DAC_C0_DACRFS_MASK; // VDDA selected - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) {} - -static inline void dac_write(dac_t *obj, int value) { - DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF); - DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF); -} - -static inline int dac_read(dac_t *obj) { - return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL); -} - -void analogout_write(dac_t *obj, float value) { - if (value < 0.0f) { - dac_write(obj, 0); - } else if (value > 1.0f) { - dac_write(obj, RANGE_12BIT); - } else { - dac_write(obj, value * (float)RANGE_12BIT); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) { - dac_write(obj, value >> 4); // 12-bit -} - -float analogout_read(dac_t *obj) { - uint32_t value = dac_read(obj); - return (float)value * (1.0f / (float)RANGE_12BIT); -} - -uint16_t analogout_read_u16(dac_t *obj) { - uint32_t value = dac_read(obj); // 12-bit - return (value << 4) | ((value >> 8) & 0x003F); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c deleted file mode 100644 index cde73ff4fdd..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "fsl_port_hal.h" -#include "fsl_gpio_hal.h" -#include "fsl_sim_hal.h" -#include "fsl_clock_manager.h" - -uint32_t gpio_set(PinName pin) { - MBED_ASSERT(pin != (PinName)NC); - uint32_t pin_num = pin & 0xFF; - - pin_function(pin, (int)kPortMuxAsGpio); - return 1 << pin_num; -} - -void gpio_init(gpio_t *obj, PinName pin) { - obj->pin = pin; - if (pin == (PinName)NC) - return; - - uint32_t port = pin >> GPIO_PORT_SHIFT; - uint32_t port_addrs[] = PORT_BASE_ADDRS; - uint32_t pin_num = pin & 0xFF; - CLOCK_SYS_EnablePortClock(port); - PORT_HAL_SetMuxMode(port_addrs[port], pin_num, kPortMuxAsGpio); -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin != (PinName)NC); - uint32_t port = obj->pin >> GPIO_PORT_SHIFT; - uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; - uint32_t pin_num = obj->pin & 0xFF; - - switch (direction) { - case PIN_INPUT: - GPIO_HAL_SetPinDir(gpio_addrs[port], pin_num, kGpioDigitalInput); - break; - case PIN_OUTPUT: - GPIO_HAL_SetPinDir(gpio_addrs[port], pin_num, kGpioDigitalOutput); - break; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_irq_api.c deleted file mode 100644 index 1e5826e3b5e..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_irq_api.c +++ /dev/null @@ -1,215 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" - -#if DEVICE_INTERRUPTIN - -#include "gpio_api.h" -#include "fsl_gpio_hal.h" -#include "fsl_port_hal.h" -#include "mbed_error.h" - -#define CHANNEL_NUM 160 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -#define IRQ_DISABLED (0) -#define IRQ_RAISING_EDGE (9) -#define IRQ_FALLING_EDGE (10) -#define IRQ_EITHER_EDGE (11) - -static void handle_interrupt_in(PortName port, int ch_base) { - uint32_t i; - uint32_t port_addrs[] = PORT_BASE_ADDRS; - - for (i = 0; i < 32; i++) { - if (PORT_HAL_IsPinIntPending(port_addrs[port], i)) { - uint32_t id = channel_ids[ch_base + i]; - if (id == 0) { - continue; - } - - gpio_irq_event event = IRQ_NONE; - uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; - switch (BR_PORT_PCRn_IRQC(port_addrs[port], i)) { - case IRQ_RAISING_EDGE: - event = IRQ_RISE; - break; - - case IRQ_FALLING_EDGE: - event = IRQ_FALL; - break; - - case IRQ_EITHER_EDGE: - event = (GPIO_HAL_ReadPinInput(gpio_addrs[port], i)) ? (IRQ_RISE) : (IRQ_FALL); - break; - } - if (event != IRQ_NONE) { - irq_handler(id, event); - } - } - } - PORT_HAL_ClearPortIntFlag(port_addrs[port]); -} - -void gpio_irqA(void) {handle_interrupt_in(PortA, 0);} -void gpio_irqB(void) {handle_interrupt_in(PortB, 32);} -void gpio_irqC(void) {handle_interrupt_in(PortC, 64);} -void gpio_irqD(void) {handle_interrupt_in(PortD, 96);} -void gpio_irqE(void) {handle_interrupt_in(PortE, 128);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) { - return -1; - } - - irq_handler = handler; - obj->port = pin >> GPIO_PORT_SHIFT; - obj->pin = pin & 0x7F; - - uint32_t ch_base = 0; - uint32_t vector = (uint32_t)gpio_irqA; - IRQn_Type irq_n = PORTA_IRQn; - switch (obj->port) { - case PortA: - ch_base = 0; - irq_n = PORTA_IRQn; - vector = (uint32_t)gpio_irqA; - break; - case PortB: - ch_base = 32; - irq_n = PORTB_IRQn; - vector = (uint32_t)gpio_irqB; - break; - case PortC: - ch_base = 64; - irq_n = PORTC_IRQn; - vector = (uint32_t)gpio_irqC; - break; - case PortD: - ch_base = 96; - irq_n = PORTD_IRQn; - vector = (uint32_t)gpio_irqD; - break; - case PortE: - ch_base = 128; - irq_n = PORTE_IRQn; - vector = (uint32_t)gpio_irqE; - break; - - default: - error("gpio_irq only supported on port A-E."); - break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - uint32_t port_addrs[] = PORT_BASE_ADDRS; - port_interrupt_config_t irq_settings = kPortIntDisabled; - - switch (BR_PORT_PCRn_IRQC(port_addrs[obj->port], obj->pin)) { - case IRQ_DISABLED: - if (enable) - irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntFallingEdge); - break; - - case IRQ_RAISING_EDGE: - if (enable) { - irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntEitherEdge); - } else { - if (event == IRQ_FALL) - irq_settings = kPortIntRisingEdge; - } - break; - - case IRQ_FALLING_EDGE: - if (enable) { - irq_settings = (event == IRQ_FALL) ? (kPortIntFallingEdge) : (kPortIntEitherEdge); - } else { - if (event == IRQ_RISE) - irq_settings = kPortIntFallingEdge; - } - break; - - case IRQ_EITHER_EDGE: - if (enable) { - irq_settings = kPortIntEitherEdge; - } else { - irq_settings = (event == IRQ_RISE) ? (kPortIntFallingEdge) : (kPortIntRisingEdge); - } - break; - } - - PORT_HAL_SetPinIntMode(port_addrs[obj->port], obj->pin, irq_settings); - PORT_HAL_ClearPinIntFlag(port_addrs[obj->port], obj->pin); -} - -void gpio_irq_enable(gpio_irq_t *obj) { - switch (obj->port) { - case PortA: - NVIC_EnableIRQ(PORTA_IRQn); - break; - case PortB: - NVIC_EnableIRQ(PORTB_IRQn); - break; - case PortC: - NVIC_EnableIRQ(PORTC_IRQn); - break; - case PortD: - NVIC_EnableIRQ(PORTD_IRQn); - break; - case PortE: - NVIC_EnableIRQ(PORTE_IRQn); - break; - } -} - -void gpio_irq_disable(gpio_irq_t *obj) { - switch (obj->port) { - case PortA: - NVIC_DisableIRQ(PORTA_IRQn); - break; - case PortB: - NVIC_DisableIRQ(PORTB_IRQn); - break; - case PortC: - NVIC_DisableIRQ(PORTC_IRQn); - break; - case PortD: - NVIC_DisableIRQ(PORTD_IRQn); - break; - case PortE: - NVIC_DisableIRQ(PORTE_IRQn); - break; - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h deleted file mode 100644 index 7cdf6662baf..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "fsl_gpio_hal.h" -// #include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - uint32_t port = obj->pin >> GPIO_PORT_SHIFT; - uint32_t pin = obj->pin & 0xFF; - uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; - - GPIO_HAL_WritePinOutput(gpio_addrs[port], pin, value); -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - uint32_t port = obj->pin >> GPIO_PORT_SHIFT; - uint32_t pin = obj->pin & 0xFF; - uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; - - return (int)GPIO_HAL_ReadPinInput(gpio_addrs[port], pin); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/i2c_api.c deleted file mode 100644 index ff9cc65d430..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/i2c_api.c +++ /dev/null @@ -1,328 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "fsl_clock_manager.h" -#include "fsl_i2c_hal.h" -#include "fsl_port_hal.h" -#include "fsl_sim_hal.h" -#include "PeripheralPins.h" - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); - uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->instance = pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->instance != NC); - - CLOCK_SYS_EnableI2cClock(obj->instance); - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - I2C_HAL_Init(i2c_addrs[obj->instance]); - I2C_HAL_Enable(i2c_addrs[obj->instance]); - I2C_HAL_SetIntCmd(i2c_addrs[obj->instance], true); - i2c_frequency(obj, 100000); - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - uint32_t port_addrs[] = PORT_BASE_ADDRS; - PORT_HAL_SetOpenDrainCmd(port_addrs[sda >> GPIO_PORT_SHIFT], sda & 0xFF, true); - PORT_HAL_SetOpenDrainCmd(port_addrs[scl >> GPIO_PORT_SHIFT], scl & 0xFF, true); -} - -int i2c_start(i2c_t *obj) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - I2C_HAL_SendStart(i2c_addrs[obj->instance]); - return 0; -} - -int i2c_stop(i2c_t *obj) { - volatile uint32_t n = 0; - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - if (I2C_HAL_IsMaster(i2c_addrs[obj->instance])) - I2C_HAL_SendStop(i2c_addrs[obj->instance]); - - // It seems that there are timing problems - // when there is no waiting time after a STOP. - // This wait is also included on the samples - // code provided with the freedom board - for (n = 0; n < 200; n++) __NOP(); - return 0; -} - -static int timeout_status_poll(i2c_t *obj, i2c_status_flag_t flag) { - uint32_t i, timeout = 100000; - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - - for (i = 0; i < timeout; i++) { - if (I2C_HAL_GetStatusFlag(i2c_addrs[obj->instance], flag)) - return 0; - } - return 1; -} - -// this function waits the end of a tx transfer and return the status of the transaction: -// 0: OK ack received -// 1: OK ack not received -// 2: failure -static int i2c_wait_end_tx_transfer(i2c_t *obj) { - // wait for the interrupt flag - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - - if (timeout_status_poll(obj, kI2CInterruptPending)) { - return 2; - } - I2C_HAL_ClearInt(i2c_addrs[obj->instance]); - - // wait transfer complete - if (timeout_status_poll(obj, kI2CTransferComplete)) { - return 2; - } - - // check if we received the ACK or not - return I2C_HAL_GetStatusFlag(i2c_addrs[obj->instance], kI2CReceivedNak) ? 1 : 0; -} - -// this function waits the end of a rx transfer and return the status of the transaction: -// 0: OK -// 1: failure -static int i2c_wait_end_rx_transfer(i2c_t *obj) { - // wait for the end of the rx transfer - if (timeout_status_poll(obj, kI2CInterruptPending)) { - return 1; - } - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - I2C_HAL_ClearInt(i2c_addrs[obj->instance]); - - return 0; -} - -static int i2c_do_write(i2c_t *obj, int value) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - I2C_HAL_WriteByte(i2c_addrs[obj->instance], value); - - // init and wait the end of the transfer - return i2c_wait_end_tx_transfer(obj); -} - -static int i2c_do_read(i2c_t *obj, char * data, int last) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - if (last) { - I2C_HAL_SendNak(i2c_addrs[obj->instance]); - } else { - I2C_HAL_SendAck(i2c_addrs[obj->instance]); - } - - *data = (I2C_HAL_ReadByte(i2c_addrs[obj->instance]) & 0xFF); - - // start rx transfer and wait the end of the transfer - return i2c_wait_end_rx_transfer(obj); -} - -void i2c_frequency(i2c_t *obj, int hz) { - uint32_t busClock; - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - clock_manager_error_code_t error = CLOCK_SYS_GetFreq(kBusClock, &busClock); - if (error == kClockManagerSuccess) { - I2C_HAL_SetBaudRate(i2c_addrs[obj->instance], busClock, hz / 1000, NULL); - } -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count; - char dummy_read, *ptr; - - if (i2c_start(obj)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - if (i2c_do_write(obj, (address | 0x01))) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // set rx mode - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CReceive); - - // Read in bytes - for (count = 0; count < (length); count++) { - ptr = (count == 0) ? &dummy_read : &data[count - 1]; - uint8_t stop_ = (count == (length - 1)) ? 1 : 0; - if (i2c_do_read(obj, ptr, stop_)) { - i2c_stop(obj); - return count; - } - } - - // If not repeated start, send stop. - if (stop) - i2c_stop(obj); - - // last read - data[count-1] = I2C_HAL_ReadByte(i2c_addrs[obj->instance]); - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i; - - if (i2c_start(obj)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - if (i2c_do_write(obj, (address & 0xFE))) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - for (i = 0; i < length; i++) { - if(i2c_do_write(obj, data[i])) { - i2c_stop(obj); - return i; - } - } - - if (stop) - i2c_stop(obj); - - return length; -} - -void i2c_reset(i2c_t *obj) { - i2c_stop(obj); -} - -int i2c_byte_read(i2c_t *obj, int last) { - char data; - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - // set rx mode - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CReceive); - - // Setup read - i2c_do_read(obj, &data, last); - - // set tx mode - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend); - return I2C_HAL_ReadByte(i2c_addrs[obj->instance]); -} - -int i2c_byte_write(i2c_t *obj, int data) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - // set tx mode - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend); - - return !i2c_do_write(obj, (data & 0xFF)); -} - - -#if DEVICE_I2CSLAVE -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - if (enable_slave) { - // set slave mode - BW_I2C_C1_MST(i2c_addrs[obj->instance], 0); - I2C_HAL_SetIntCmd(i2c_addrs[obj->instance], true); - } else { - // set master mode - BW_I2C_C1_MST(i2c_addrs[obj->instance], 1); - } -} - -int i2c_slave_receive(i2c_t *obj) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - switch(HW_I2C_S_RD(i2c_addrs[obj->instance])) { - // read addressed - case 0xE6: - return 1; - // write addressed - case 0xE2: - return 3; - default: - return 0; - } -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) { - uint8_t dummy_read; - uint8_t *ptr; - int count; - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - // set rx mode - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend); - - // first dummy read - dummy_read = I2C_HAL_ReadByte(i2c_addrs[obj->instance]); - if (i2c_wait_end_rx_transfer(obj)) - return 0; - - // read address - dummy_read = I2C_HAL_ReadByte(i2c_addrs[obj->instance]); - if (i2c_wait_end_rx_transfer(obj)) - return 0; - - // read (length - 1) bytes - for (count = 0; count < (length - 1); count++) { - data[count] = I2C_HAL_ReadByte(i2c_addrs[obj->instance]); - if (i2c_wait_end_rx_transfer(obj)) - return count; - } - - // read last byte - ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count]; - *ptr = I2C_HAL_ReadByte(i2c_addrs[obj->instance]); - - return (length) ? (count + 1) : 0; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int i, count = 0; - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - - // set tx mode - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CSend); - - for (i = 0; i < length; i++) { - if (i2c_do_write(obj, data[count++]) == 2) - return i; - } - - // set rx mode - I2C_HAL_SetDirMode(i2c_addrs[obj->instance], kI2CReceive); - - // dummy rx transfer needed - // otherwise the master cannot generate a stop bit - I2C_HAL_ReadByte(i2c_addrs[obj->instance]); - if (i2c_wait_end_rx_transfer(obj) == 2) - return count; - - return count; -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - uint32_t i2c_addrs[] = I2C_BASE_ADDRS; - I2C_HAL_SetUpperAddress7bit(i2c_addrs[obj->instance], address & 0xfe); -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/objects.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/objects.h deleted file mode 100644 index 68203df3021..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/objects.h +++ /dev/null @@ -1,69 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; -}; - -struct port_s { - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - PWMName pwm_name; -}; - -struct serial_s { - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct i2c_s { - uint32_t instance; -}; - -struct spi_s { - uint32_t instance; -}; - -struct dac_s { - DACName dac; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pinmap.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pinmap.c deleted file mode 100644 index 3b5c38ce8f9..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pinmap.c +++ /dev/null @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "fsl_clock_manager.h" -#include "fsl_port_hal.h" - -void pin_function(PinName pin, int function) { - MBED_ASSERT(pin != (PinName)NC); - CLOCK_SYS_EnablePortClock(pin >> GPIO_PORT_SHIFT); - uint32_t port_addrs[] = PORT_BASE_ADDRS; - PORT_HAL_SetMuxMode(port_addrs[pin >> GPIO_PORT_SHIFT], pin & 0xFF, (port_mux_t)function); -} - -void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != (PinName)NC); - uint32_t instance = pin >> GPIO_PORT_SHIFT; - uint32_t port_addrs[] = PORT_BASE_ADDRS; - uint32_t pinName = pin & 0xFF; - - switch (mode) { - case PullNone: - PORT_HAL_SetPullCmd(port_addrs[instance], pinName, false); - PORT_HAL_SetPullMode(port_addrs[instance], pinName, kPortPullDown); - break; - case PullDown: - PORT_HAL_SetPullCmd(port_addrs[instance], pinName, true); - PORT_HAL_SetPullMode(port_addrs[instance], pinName, kPortPullDown); - break; - case PullUp: - PORT_HAL_SetPullCmd(port_addrs[instance], pinName, true); - PORT_HAL_SetPullMode(port_addrs[instance], pinName, kPortPullUp); - break; - default: - break; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/port_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/port_api.c deleted file mode 100644 index 9e677f664cc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/port_api.c +++ /dev/null @@ -1,77 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -#include "pinmap.h" -#include "gpio_api.h" - -PinName port_pin(PortName port, int pin_n) { - return (PinName)((port << GPIO_PORT_SHIFT) | pin_n); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - // The function is set per pin: reuse gpio logic - for (uint32_t i = 0; i < 32; i++) { - if (obj->mask & (1 << i)) { - gpio_set(port_pin(obj->port, i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - - // The mode is set per pin: reuse pinmap logic - for (uint32_t i = 0; i < 32; i++) { - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - uint32_t port_addrs[] = PORT_BASE_ADDRS; - uint32_t direction = GPIO_HAL_GetPortDir(port_addrs[obj->port]); - switch (dir) { - case PIN_INPUT : - direction &= ~obj->mask; - GPIO_HAL_SetPortDir(port_addrs[obj->port], direction); - break; - case PIN_OUTPUT: - direction |= obj->mask; - GPIO_HAL_SetPortDir(port_addrs[obj->port], direction); - break; - } -} - -void port_write(port_t *obj, int value) { - uint32_t port_addrs[] = PORT_BASE_ADDRS; - uint32_t input = GPIO_HAL_ReadPortInput(port_addrs[obj->port]) & ~obj->mask; - GPIO_HAL_WritePortOutput(port_addrs[obj->port], input | (uint32_t)(value & obj->mask)); -} - -int port_read(port_t *obj) { - uint32_t port_addrs[] = PORT_BASE_ADDRS; - return (int)(GPIO_HAL_ReadPortInput(port_addrs[obj->port]) & obj->mask); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pwmout_api.c deleted file mode 100644 index 647f1fe7cc7..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pwmout_api.c +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "fsl_ftm_hal.h" -#include "fsl_mcg_hal.h" -#include "fsl_clock_manager.h" -#include "PeripheralPins.h" - -static float pwm_clock_mhz; - -void pwmout_init(pwmout_t* obj, PinName pin) { - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - obj->pwm_name = pwm; - - uint32_t pwm_base_clock; - CLOCK_SYS_GetFreq(kBusClock, &pwm_base_clock); - float clkval = (float)pwm_base_clock / 1000000.0f; - uint32_t clkdiv = 0; - while (clkval > 1) { - clkdiv++; - clkval /= 2.0f; - if (clkdiv == 7) { - break; - } - } - - pwm_clock_mhz = clkval; - uint32_t channel = pwm & 0xF; - uint32_t instance = pwm >> TPM_SHIFT; - uint32_t ftm_addrs[] = FTM_BASE_ADDRS; - CLOCK_SYS_EnableFtmClock(instance); - - FTM_HAL_SetTofFreq(ftm_addrs[instance], 3); - FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_SystemClk); - FTM_HAL_SetClockPs(ftm_addrs[instance], (ftm_clock_ps_t)clkdiv); - FTM_HAL_SetCounter(ftm_addrs[instance], 0); - // default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_ms(obj, 20); - pwmout_write (obj, 0); - ftm_pwm_param_t config = { - .mode = kFtmEdgeAlignedPWM, - .edgeMode = kFtmHighTrue - }; - FTM_HAL_EnablePwmMode(ftm_addrs[instance], &config, channel); - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); -} - -void pwmout_free(pwmout_t* obj) { -} - -void pwmout_write(pwmout_t* obj, float value) { - uint32_t instance = obj->pwm_name >> TPM_SHIFT; - if (value < 0.0f) { - value = 0.0f; - } else if (value > 1.0f) { - value = 1.0f; - } - uint32_t ftm_addrs[] = FTM_BASE_ADDRS; - uint16_t mod = FTM_HAL_GetMod(ftm_addrs[instance]); - uint32_t new_count = (uint32_t)((float)(mod) * value); - // Stop FTM clock to ensure instant update of MOD register - FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_None); - FTM_HAL_SetChnCountVal(ftm_addrs[instance], obj->pwm_name & 0xF, new_count); - FTM_HAL_SetCounter(ftm_addrs[instance], 0); - FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_SystemClk); -} - -float pwmout_read(pwmout_t* obj) { - uint32_t ftm_addrs[] = FTM_BASE_ADDRS; - uint16_t count = FTM_HAL_GetChnCountVal(ftm_addrs[obj->pwm_name >> TPM_SHIFT], obj->pwm_name & 0xF, 0); - uint16_t mod = FTM_HAL_GetMod(ftm_addrs[obj->pwm_name >> TPM_SHIFT]); - if (mod == 0) - return 0.0; - float v = (float)(count) / (float)(mod); - return (v > 1.0f) ? (1.0f) : (v); -} - -void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) { - uint32_t instance = obj->pwm_name >> TPM_SHIFT; - uint32_t ftm_addrs[] = FTM_BASE_ADDRS; - float dc = pwmout_read(obj); - // Stop FTM clock to ensure instant update of MOD register - FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_None); - FTM_HAL_SetMod(ftm_addrs[instance], (uint32_t)(pwm_clock_mhz * (float)us) - 1); - pwmout_write(obj, dc); - FTM_HAL_SetClockSource(ftm_addrs[instance], kClock_source_FTM_SystemClk); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - uint32_t ftm_addrs[] = FTM_BASE_ADDRS; - uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us); - FTM_HAL_SetChnCountVal(ftm_addrs[obj->pwm_name >> TPM_SHIFT], obj->pwm_name & 0xF, value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/rtc_api.c deleted file mode 100644 index 9881b4b9e51..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/rtc_api.c +++ /dev/null @@ -1,60 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "pinmap.h" -#include "fsl_rtc_hal.h" -#include "fsl_clock_manager.h" -#include "PeripheralPins.h" - -void rtc_init(void) { - SIM_HAL_EnableRtcClock(SIM_BASE, 0U); - - RTC_HAL_Init(RTC_BASE); - RTC_HAL_Enable(RTC_BASE); - - RTC_HAL_EnableCounter(RTC_BASE, true); -} - -void rtc_free(void) { - // [TODO] -} - -/* - * Little check routine to see if the RTC has been enabled - * 0 = Disabled, 1 = Enabled - */ -int rtc_isenabled(void) { - SIM_HAL_EnableRtcClock(SIM_BASE, 0U); - return (int)RTC_HAL_IsCounterEnabled(RTC_BASE); -} - -time_t rtc_read(void) { - return (time_t)RTC_HAL_GetSecsReg(RTC_BASE); -} - -void rtc_write(time_t t) { - if (t == 0) { - t = 1; - } - RTC_HAL_EnableCounter(RTC_BASE, false); - RTC_HAL_SetSecsReg(RTC_BASE, t); - RTC_HAL_EnableCounter(RTC_BASE, true); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c deleted file mode 100644 index 7f555ec1931..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c +++ /dev/null @@ -1,233 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "serial_api.h" - -#if DEVICE_SERIAL - -// math.h required for floating point operations for baud rate calculation -#include -#include "mbed_assert.h" - -#include - -#include "cmsis.h" -#include "pinmap.h" -#include "fsl_uart_hal.h" -#include "fsl_clock_manager.h" -#include "fsl_uart_features.h" -#include "PeripheralPins.h" - -/* TODO: - putchar/getchar 9 and 10 bits support -*/ -#ifndef UART3_BASE -#define UART_NUM 3 -#else -#define UART_NUM 5 -#endif - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - obj->index = pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)obj->index != NC); - - uint32_t uartSourceClock = CLOCK_SYS_GetUartFreq(obj->index); - - CLOCK_SYS_EnableUartClock(obj->index); - uint32_t uart_addrs[] = UART_BASE_ADDRS; - UART_HAL_Init(uart_addrs[obj->index]); - UART_HAL_SetBaudRate(uart_addrs[obj->index], uartSourceClock, 9600); - UART_HAL_SetParityMode(uart_addrs[obj->index], kUartParityDisabled); - #if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - UART_HAL_SetStopBitCount(uart_addrs[obj->index], kUartOneStopBit); - #endif - UART_HAL_SetBitCountPerChar(uart_addrs[obj->index], kUart8BitsPerChar); - UART_HAL_DisableTransmitter(uart_addrs[obj->index]); - UART_HAL_DisableReceiver(uart_addrs[obj->index]); - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - UART_HAL_FlushTxFifo(uart_addrs[obj->index]); - UART_HAL_EnableTransmitter(uart_addrs[obj->index]); - - pin_mode(tx, PullUp); - } - if (rx != NC) { - UART_HAL_EnableReceiver(uart_addrs[obj->index]); - pin_mode(rx, PullUp); - } - - if (obj->index == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) { - uint32_t uart_addrs[] = UART_BASE_ADDRS; - UART_HAL_SetBaudRate(uart_addrs[obj->index], CLOCK_SYS_GetUartFreq(obj->index), (uint32_t)baudrate); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - uint32_t uart_addrs[] = UART_BASE_ADDRS; - UART_HAL_SetBitCountPerChar(uart_addrs[obj->index], (uart_bit_count_per_char_t)data_bits); - UART_HAL_SetParityMode(uart_addrs[obj->index], (uart_parity_mode_t)parity); - #if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - UART_HAL_SetStopBitCount(uart_addrs[obj->index], (uart_stop_bit_count_t)--stop_bits); - #endif -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) { - if (serial_irq_ids[index] != 0) { - if (transmit_empty) - irq_handler(serial_irq_ids[index], TxIrq); - - if (receive_full) - irq_handler(serial_irq_ids[index], RxIrq); - } -} - -void uart0_irq() { - uart_irq(UART_HAL_IsTxDataRegEmpty(UART0_BASE), UART_HAL_IsRxDataRegFull(UART0_BASE), 0); - if (UART_HAL_GetStatusFlag(UART0_BASE, kUartRxOverrun)) - UART_HAL_ClearStatusFlag(UART0_BASE, kUartRxOverrun); -} -void uart1_irq() { - uart_irq(UART_HAL_IsTxDataRegEmpty(UART1_BASE), UART_HAL_IsRxDataRegFull(UART1_BASE), 1); -} - -void uart2_irq() { - uart_irq(UART_HAL_IsTxDataRegEmpty(UART2_BASE), UART_HAL_IsRxDataRegFull(UART2_BASE), 2); -} - -#if (UART_NUM > 3) - -void uart3_irq() { - uart_irq(UART_HAL_IsTxDataRegEmpty(UART3_BASE), UART_HAL_IsRxDataRegFull(UART3_BASE), 3); -} - -void uart4_irq() { - uart_irq(UART_HAL_IsTxDataRegEmpty(UART4_BASE), UART_HAL_IsRxDataRegFull(UART4_BASE), 4); -} -#endif - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - switch (obj->index) { - case 0: irq_n=UART0_RX_TX_IRQn; vector = (uint32_t)&uart0_irq; break; - case 1: irq_n=UART1_RX_TX_IRQn; vector = (uint32_t)&uart1_irq; break; - case 2: irq_n=UART2_RX_TX_IRQn; vector = (uint32_t)&uart2_irq; break; -#if (UART_NUM > 3) - case 3: irq_n=UART3_RX_TX_IRQn; vector = (uint32_t)&uart3_irq; break; - case 4: irq_n=UART4_RX_TX_IRQn; vector = (uint32_t)&uart4_irq; break; -#endif - } - uint32_t uart_addrs[] = UART_BASE_ADDRS; - if (enable) { - switch (irq) { - case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], true); break; - case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], true); break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - switch (irq) { - case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], false); break; - case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], false); break; - } - switch (other_irq) { - case RxIrq: all_disabled = UART_HAL_GetRxDataRegFullIntCmd(uart_addrs[obj->index]) == 0; break; - case TxIrq: all_disabled = UART_HAL_GetTxDataRegEmptyIntCmd(uart_addrs[obj->index]) == 0; break; - } - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - uint8_t data; - uint32_t uart_addrs[] = UART_BASE_ADDRS; - UART_HAL_Getchar(uart_addrs[obj->index], &data); - - return data; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - uint32_t uart_addrs[] = UART_BASE_ADDRS; - UART_HAL_Putchar(uart_addrs[obj->index], (uint8_t)c); -} - -int serial_readable(serial_t *obj) { - uint32_t uart_address[] = UART_BASE_ADDRS; - if (UART_HAL_GetStatusFlag(uart_address[obj->index], kUartRxOverrun)) - UART_HAL_ClearStatusFlag(uart_address[obj->index], kUartRxOverrun); - return UART_HAL_IsRxDataRegFull(uart_address[obj->index]); -} - -int serial_writable(serial_t *obj) { - uint32_t uart_address[] = UART_BASE_ADDRS; - if (UART_HAL_GetStatusFlag(uart_address[obj->index], kUartRxOverrun)) - UART_HAL_ClearStatusFlag(uart_address[obj->index], kUartRxOverrun); - - return UART_HAL_IsTxDataRegEmpty(uart_address[obj->index]); -} - -void serial_clear(serial_t *obj) { -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - uint32_t uart_address[] = UART_BASE_ADDRS; - UART_HAL_SetBreakCharCmd(uart_address[obj->index], true); -} - -void serial_break_clear(serial_t *obj) { - uint32_t uart_address[] = UART_BASE_ADDRS; - UART_HAL_SetBreakCharCmd(uart_address[obj->index], false); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/sleep.c deleted file mode 100644 index 8b45d4593b1..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/sleep.c +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "fsl_mcg_hal.h" -#include "fsl_smc_hal.h" - -void sleep(void) { - smc_power_mode_protection_config_t sleep_config = {true}; - SMC_HAL_SetProtection(SMC_BASE, &sleep_config); - - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); -} - -void deepsleep(void) { - mcg_clock_select_t mcg_clock = CLOCK_HAL_GetClkSrcMode(MCG_BASE); - - smc_power_mode_protection_config_t sleep_config = {true}; - SMC_HAL_SetProtection(SMC_BASE, &sleep_config); - SMC->PMCTRL = SMC_PMCTRL_STOPM(2); - - //Deep sleep for ARM core: - SCB->SCR = 1 << SCB_SCR_SLEEPDEEP_Pos; - - __WFI(); - - //Switch back to PLL as clock source if needed - //The interrupt that woke up the device will run at reduced speed - if (mcg_clock == kMcgClkSelOut) { - if (CLOCK_HAL_GetPllStatMode(MCG_BASE) == kMcgPllStatPllClkSel) { - while (CLOCK_HAL_GetLock0Mode(MCG_BASE) == kMcgLockUnlocked); - } - CLOCK_HAL_SetClkSrcMode(MCG_BASE, kMcgClkSelOut); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c deleted file mode 100644 index 89e1879d622..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c +++ /dev/null @@ -1,133 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_assert.h" - -#include "spi_api.h" - -#if DEVICE_SPI - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "fsl_clock_manager.h" -#include "fsl_dspi_hal.h" -#include "PeripheralPins.h" - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); - uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); - uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); - uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); - uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); - uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); - - obj->instance = pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->instance != NC); - - CLOCK_SYS_EnableSpiClock(obj->instance); - uint32_t spi_address[] = SPI_BASE_ADDRS; - DSPI_HAL_Init(spi_address[obj->instance]); - DSPI_HAL_Disable(spi_address[obj->instance]); - DSPI_HAL_SetDelay(spi_address[obj->instance], kDspiCtar0, 0, 0, kDspiPcsToSck); - - DSPI_HAL_Enable(spi_address[obj->instance]); - DSPI_HAL_StartTransfer(spi_address[obj->instance]); - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) { - // [TODO] -} -void spi_format(spi_t *obj, int bits, int mode, int slave) { - dspi_data_format_config_t config = {0}; - config.bitsPerFrame = (uint32_t)bits; - config.clkPolarity = (mode & 0x2) ? kDspiClockPolarity_ActiveLow : kDspiClockPolarity_ActiveHigh; - config.clkPhase = (mode & 0x1) ? kDspiClockPhase_SecondEdge : kDspiClockPhase_FirstEdge; - config.direction = kDspiMsbFirst; - uint32_t spi_address[] = SPI_BASE_ADDRS; - dspi_status_t result = DSPI_HAL_SetDataFormat(spi_address[obj->instance], kDspiCtar0, &config); - if (result != kStatus_DSPI_Success) { - error("Failed to configure SPI data format"); - } - - if (slave) { - DSPI_HAL_SetMasterSlaveMode(spi_address[obj->instance], kDspiSlave); - } else { - DSPI_HAL_SetMasterSlaveMode(spi_address[obj->instance], kDspiMaster); - } -} - -void spi_frequency(spi_t *obj, int hz) { - uint32_t busClock; - CLOCK_SYS_GetFreq(kBusClock, &busClock); - uint32_t spi_address[] = SPI_BASE_ADDRS; - DSPI_HAL_SetBaudRate(spi_address[obj->instance], kDspiCtar0, (uint32_t)hz, busClock); - DSPI_HAL_CalculateDelay(spi_address[obj->instance], kDspiCtar0, kDspiLastSckToPcs, busClock, 500000000 / hz); //Half clock period delay after SPI transfer -} - -static inline int spi_writeable(spi_t * obj) { - uint32_t spi_address[] = SPI_BASE_ADDRS; - return DSPI_HAL_GetStatusFlag(spi_address[obj->instance], kDspiTxFifoFillRequest); -} - -static inline int spi_readable(spi_t * obj) { - uint32_t spi_address[] = SPI_BASE_ADDRS; - return DSPI_HAL_GetStatusFlag(spi_address[obj->instance], kDspiRxFifoDrainRequest); -} - -int spi_master_write(spi_t *obj, int value) { - uint32_t spi_address[] = SPI_BASE_ADDRS; - - // wait tx buffer empty - while(!spi_writeable(obj)); - dspi_command_config_t command = {0}; - command.isEndOfQueue = true; - command.isChipSelectContinuous = 0; - DSPI_HAL_WriteDataMastermode(spi_address[obj->instance], &command, (uint16_t)value); - DSPI_HAL_ClearStatusFlag(spi_address[obj->instance], kDspiTxFifoFillRequest); - - // wait rx buffer full - while (!spi_readable(obj)); - DSPI_HAL_ClearStatusFlag(spi_address[obj->instance], kDspiRxFifoDrainRequest); - return DSPI_HAL_ReadData(spi_address[obj->instance]) & 0xff; -} - -int spi_slave_receive(spi_t *obj) { - return spi_readable(obj); -} - -int spi_slave_read(spi_t *obj) { - DSPI_HAL_ClearStatusFlag(obj->instance, kDspiRxFifoDrainRequest); - uint32_t spi_address[] = SPI_BASE_ADDRS; - return DSPI_HAL_ReadData(spi_address[obj->instance]); -} - -void spi_slave_write(spi_t *obj, int value) { - while (!spi_writeable(obj)); - uint32_t spi_address[] = SPI_BASE_ADDRS; - DSPI_HAL_WriteDataSlavemode(spi_address[obj->instance], (uint32_t)value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/us_ticker.c deleted file mode 100644 index 744f7156237..00000000000 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/us_ticker.c +++ /dev/null @@ -1,85 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "fsl_pit_hal.h" -#include "fsl_sim_hal.h" -#include "fsl_clock_manager.h" - -static int us_ticker_inited = 0; - -void us_ticker_init(void) { - if (us_ticker_inited) { - return; - } - us_ticker_inited = 1; - - //Common for ticker/timer - uint32_t busClock; - CLOCK_SYS_EnablePitClock(0); - PIT_HAL_Enable(PIT_BASE); - CLOCK_SYS_GetFreq(kBusClock, &busClock); - - //Timer - PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 0, busClock / 1000000 - 1); - PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 1, 0xFFFFFFFF); - PIT_HAL_SetTimerChainCmd(PIT_BASE, 1, true); - PIT_HAL_StartTimer(PIT_BASE, 0); - PIT_HAL_StartTimer(PIT_BASE, 1); - - //Ticker - PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 2, busClock / 1000000 - 1); - PIT_HAL_SetTimerChainCmd(PIT_BASE, 3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(PIT3_IRQn); -} - - -uint32_t us_ticker_read() { - if (!us_ticker_inited) { - us_ticker_init(); - } - - return ~(PIT_HAL_ReadTimerCount(PIT_BASE, 1)); -} - -void us_ticker_disable_interrupt(void) { - PIT_HAL_SetIntCmd(PIT_BASE, 3, false); -} - -void us_ticker_clear_interrupt(void) { - PIT_HAL_ClearIntFlag(PIT_BASE, 3); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - int delta = (int)(timestamp - us_ticker_read()); - if (delta <= 0) { - // This event was in the past. - // Set the interrupt as pending, but don't process it here. - // This prevents a recurive loop under heavy load - // which can lead to a stack overflow. - NVIC_SetPendingIRQ(PIT3_IRQn); - return; - } - - PIT_HAL_StopTimer(PIT_BASE, 3); - PIT_HAL_StopTimer(PIT_BASE, 2); - PIT_HAL_SetTimerPeriodByCount(PIT_BASE, 3, (uint32_t)delta); - PIT_HAL_SetIntCmd(PIT_BASE, 3, true); - PIT_HAL_StartTimer(PIT_BASE, 3); - PIT_HAL_StartTimer(PIT_BASE, 2); -} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index e413024af1a..ecda1155d7c 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -673,48 +673,6 @@ def binary_hook(t_self, resources, elf, binf): with open(binf.replace(".bin", ".hex"), "w") as f: binh.tofile(f, format='hex') -class K22F(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE'] - self.macros = ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.detect_code = ["0201"] - self.progen = { - "target":"frdm-k22f", - } - -class K64F(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE', 'MCU_K64F', 'FRDM'] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.detect_code = ["0240"] - self.progen = { - "target":"frdm-k64f", - } - -class MTS_GAMBIT(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE', 'MCU_K64F'] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.progen = { - "target":"mts-gambit", - } - ### STMicro ### class NUCLEO_F030R8(Target): @@ -2165,9 +2123,6 @@ def __init__(self): KL46Z(), K20D50M(), TEENSY3_1(), - K22F(), - K64F(), - MTS_GAMBIT(), # FRDM K64F ### STMicro ### B96B_F446VE(), From 2c9c632aad1752e3a72f2b1a53437d16ca0da27e Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh-R9AADQ Date: Fri, 11 Mar 2016 18:44:43 -0600 Subject: [PATCH 04/11] Added Kinetis K64 support Use Kinetis SDK 2.0. Moved this to TARGET_NXP Signed-off-by: Mahadevan Mahesh --- .../cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h | 12718 ++++++++++++++++ .../TARGET_NXP/TARGET_K64F/MK64F12_features.h | 2108 +++ .../TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct | 130 + .../TOOLCHAIN_ARM_STD/startup_MK64F12.S | 1051 ++ .../TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld | 267 + .../TOOLCHAIN_GCC_ARM/startup_MK64F12.S | 993 ++ .../TOOLCHAIN_IAR/MK64FN1M0xxx12.icf | 118 + .../TOOLCHAIN_IAR/startup_MK64F12.S | 870 ++ .../cmsis/TARGET_NXP/TARGET_K64F/cmsis.h | 13 + .../cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c | 42 + .../cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h | 48 + .../TARGET_K64F/fsl_device_registers.h | 58 + .../TARGET_NXP/TARGET_K64F/system_MK64F12.c | 247 + .../TARGET_NXP/TARGET_K64F/system_MK64F12.h | 168 + .../TARGET_K64F/TARGET_FRDM/PeripheralNames.h | 137 + .../TARGET_K64F/TARGET_FRDM/PeripheralPins.c | 208 + .../TARGET_K64F/TARGET_FRDM/PinNames.h | 258 + .../TARGET_K64F/TARGET_FRDM/crc.c | 234 + .../TARGET_K64F/TARGET_FRDM/crc.h | 77 + .../TARGET_K64F/TARGET_FRDM/device.h | 58 + .../TARGET_FRDM/fsl_clock_config.c | 196 + .../TARGET_FRDM/fsl_clock_config.h | 53 + .../TARGET_K64F/TARGET_FRDM/mbed_overrides.c | 79 + .../TARGET_MTS_GAMBIT/PeripheralNames.h | 133 + .../TARGET_MTS_GAMBIT/PeripheralPins.c | 112 + .../TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h | 268 + .../TARGET_K64F/TARGET_MTS_GAMBIT/device.h | 58 + .../TARGET_MTS_GAMBIT/fsl_clock_config.c | 196 + .../TARGET_MTS_GAMBIT/fsl_clock_config.h | 53 + .../TARGET_MTS_GAMBIT/mbed_overrides.c | 29 + .../TARGET_K64F/drivers/fsl_adc16.c | 363 + .../TARGET_K64F/drivers/fsl_adc16.h | 527 + .../TARGET_K64F/drivers/fsl_clock.c | 1760 +++ .../TARGET_K64F/drivers/fsl_clock.h | 1510 ++ .../TARGET_K64F/drivers/fsl_cmp.c | 279 + .../TARGET_K64F/drivers/fsl_cmp.h | 346 + .../TARGET_K64F/drivers/fsl_cmt.c | 260 + .../TARGET_K64F/drivers/fsl_cmt.h | 402 + .../TARGET_K64F/drivers/fsl_common.c | 97 + .../TARGET_K64F/drivers/fsl_common.h | 255 + .../TARGET_K64F/drivers/fsl_crc.c | 270 + .../TARGET_K64F/drivers/fsl_crc.h | 195 + .../TARGET_K64F/drivers/fsl_dac.c | 213 + .../TARGET_K64F/drivers/fsl_dac.h | 379 + .../TARGET_K64F/drivers/fsl_dmamux.c | 87 + .../TARGET_K64F/drivers/fsl_dmamux.h | 176 + .../TARGET_K64F/drivers/fsl_dspi.c | 1659 ++ .../TARGET_K64F/drivers/fsl_dspi.h | 1185 ++ .../TARGET_K64F/drivers/fsl_dspi_edma.c | 1262 ++ .../TARGET_K64F/drivers/fsl_dspi_edma.h | 283 + .../TARGET_K64F/drivers/fsl_edma.c | 1313 ++ .../TARGET_K64F/drivers/fsl_edma.h | 879 ++ .../TARGET_K64F/drivers/fsl_enet.c | 1718 +++ .../TARGET_K64F/drivers/fsl_enet.h | 1160 ++ .../TARGET_K64F/drivers/fsl_ewm.c | 92 + .../TARGET_K64F/drivers/fsl_ewm.h | 242 + .../TARGET_K64F/drivers/fsl_flash.c | 2610 ++++ .../TARGET_K64F/drivers/fsl_flash.h | 1177 ++ .../TARGET_K64F/drivers/fsl_flexbus.c | 196 + .../TARGET_K64F/drivers/fsl_flexbus.h | 266 + .../TARGET_K64F/drivers/fsl_flexcan.c | 1314 ++ .../TARGET_K64F/drivers/fsl_flexcan.h | 1053 ++ .../TARGET_K64F/drivers/fsl_flexcan_edma.c | 176 + .../TARGET_K64F/drivers/fsl_flexcan_edma.h | 128 + .../TARGET_K64F/drivers/fsl_ftm.c | 876 ++ .../TARGET_K64F/drivers/fsl_ftm.h | 862 ++ .../TARGET_K64F/drivers/fsl_gpio.c | 179 + .../TARGET_K64F/drivers/fsl_gpio.h | 390 + .../TARGET_K64F/drivers/fsl_i2c.c | 1536 ++ .../TARGET_K64F/drivers/fsl_i2c.h | 781 + .../TARGET_K64F/drivers/fsl_i2c_edma.c | 526 + .../TARGET_K64F/drivers/fsl_i2c_edma.h | 133 + .../TARGET_K64F/drivers/fsl_llwu.c | 404 + .../TARGET_K64F/drivers/fsl_llwu.h | 321 + .../TARGET_K64F/drivers/fsl_lptmr.c | 117 + .../TARGET_K64F/drivers/fsl_lptmr.h | 351 + .../TARGET_K64F/drivers/fsl_mpu.c | 232 + .../TARGET_K64F/drivers/fsl_mpu.h | 495 + .../TARGET_K64F/drivers/fsl_pdb.c | 135 + .../TARGET_K64F/drivers/fsl_pdb.h | 576 + .../TARGET_K64F/drivers/fsl_pit.c | 119 + .../TARGET_K64F/drivers/fsl_pit.h | 355 + .../TARGET_K64F/drivers/fsl_pmc.c | 93 + .../TARGET_K64F/drivers/fsl_pmc.h | 423 + .../TARGET_K64F/drivers/fsl_port.h | 382 + .../TARGET_K64F/drivers/fsl_rcm.c | 63 + .../TARGET_K64F/drivers/fsl_rcm.h | 432 + .../TARGET_K64F/drivers/fsl_rnga.c | 281 + .../TARGET_K64F/drivers/fsl_rnga.h | 138 + .../TARGET_K64F/drivers/fsl_rtc.c | 370 + .../TARGET_K64F/drivers/fsl_rtc.h | 405 + .../TARGET_K64F/drivers/fsl_sai.c | 1048 ++ .../TARGET_K64F/drivers/fsl_sai.h | 850 ++ .../TARGET_K64F/drivers/fsl_sai_edma.c | 379 + .../TARGET_K64F/drivers/fsl_sai_edma.h | 232 + .../TARGET_K64F/drivers/fsl_sdhc.c | 1294 ++ .../TARGET_K64F/drivers/fsl_sdhc.h | 1082 ++ .../TARGET_K64F/drivers/fsl_sim.c | 53 + .../TARGET_K64F/drivers/fsl_sim.h | 128 + .../TARGET_K64F/drivers/fsl_smc.c | 360 + .../TARGET_K64F/drivers/fsl_smc.h | 419 + .../TARGET_K64F/drivers/fsl_uart.c | 1032 ++ .../TARGET_K64F/drivers/fsl_uart.h | 757 + .../TARGET_K64F/drivers/fsl_uart_edma.c | 362 + .../TARGET_K64F/drivers/fsl_uart_edma.h | 190 + .../TARGET_K64F/drivers/fsl_vref.c | 172 + .../TARGET_K64F/drivers/fsl_vref.h | 228 + .../TARGET_K64F/drivers/fsl_wdog.c | 153 + .../TARGET_K64F/drivers/fsl_wdog.h | 434 + .../TARGET_K64F/peripheral_clock_defines.h | 54 + .../TARGET_K64F/serial_api.c | 276 + .../TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c | 132 + .../TARGET_K64F/us_ticker.c | 87 + .../TARGET_KPSDK2_MCUS/api/PeripheralPins.h | 49 + .../TARGET_KPSDK2_MCUS/api/PortNames.h | 35 + .../TARGET_KPSDK2_MCUS/api/analogin_api.c | 86 + .../TARGET_KPSDK2_MCUS/api/analogout_api.c | 78 + .../TARGET_KPSDK2_MCUS/api/gpio_api.c | 56 + .../TARGET_KPSDK2_MCUS/api/gpio_irq_api.c | 187 + .../TARGET_KPSDK2_MCUS/api/gpio_object.h | 56 + .../TARGET_KPSDK2_MCUS/api/i2c_api.c | 225 + .../TARGET_KPSDK2_MCUS/api/objects.h | 69 + .../TARGET_KPSDK2_MCUS/api/pinmap.c | 60 + .../TARGET_KPSDK2_MCUS/api/port_api.c | 82 + .../TARGET_KPSDK2_MCUS/api/pwmout_api.c | 143 + .../TARGET_KPSDK2_MCUS/api/rtc_api.c | 63 + .../TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c | 47 + workspace_tools/targets.py | 31 + 129 files changed, 66807 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12_features.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/fsl_device_registers.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PeripheralPins.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h new file mode 100644 index 00000000000..4f1375f89c0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h @@ -0,0 +1,12718 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** MK64FX512VDC12 +** MK64FX512VLL12 +** MK64FX512VLQ12 +** MK64FX512VMD12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151218 +** +** Abstract: +** CMSIS Peripheral Access Layer for MK64F12 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** +** ################################################################### +*/ + +/*! + * @file MK64F12.h + * @version 2.8 + * @date 2015-02-19 + * @brief CMSIS Peripheral Access Layer for MK64F12 + * + * CMSIS Peripheral Access Layer for MK64F12 + */ + +#ifndef _MK64F12_H_ +#define _MK64F12_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0008U + +/** + * @brief Macro to calculate address of an aliased word in the peripheral + * bitband area for a peripheral register and bit (bit band region 0x40000000 to + * 0x400FFFFF). + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Address of the aliased word in the peripheral bitband area. + */ +#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 32bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 16bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 8bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ + DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ + DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ + DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ + DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ + DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ + DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ + DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ + DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ + DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ + DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ + DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ + DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ + DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ + DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ + DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ + DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ + MCM_IRQn = 17, /**< Normal Interrupt */ + FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ + Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ + LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ + LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ + WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ + RNG_IRQn = 23, /**< RNG Interrupt */ + I2C0_IRQn = 24, /**< I2C0 interrupt */ + I2C1_IRQn = 25, /**< I2C1 interrupt */ + SPI0_IRQn = 26, /**< SPI0 Interrupt */ + SPI1_IRQn = 27, /**< SPI1 Interrupt */ + I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ + UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ + UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ + UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ + UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ + UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ + UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ + UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ + UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ + UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ + ADC0_IRQn = 39, /**< ADC0 interrupt */ + CMP0_IRQn = 40, /**< CMP0 interrupt */ + CMP1_IRQn = 41, /**< CMP1 interrupt */ + FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ + FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ + CMT_IRQn = 45, /**< CMT interrupt */ + RTC_IRQn = 46, /**< RTC interrupt */ + RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ + PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 52, /**< PDB0 Interrupt */ + USB0_IRQn = 53, /**< USB0 interrupt */ + USBDCD_IRQn = 54, /**< USBDCD Interrupt */ + Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ + DAC0_IRQn = 56, /**< DAC0 interrupt */ + MCG_IRQn = 57, /**< MCG Interrupt */ + LPTMR0_IRQn = 58, /**< LPTimer interrupt */ + PORTA_IRQn = 59, /**< Port A interrupt */ + PORTB_IRQn = 60, /**< Port B interrupt */ + PORTC_IRQn = 61, /**< Port C interrupt */ + PORTD_IRQn = 62, /**< Port D interrupt */ + PORTE_IRQn = 63, /**< Port E interrupt */ + SWI_IRQn = 64, /**< Software interrupt */ + SPI2_IRQn = 65, /**< SPI2 Interrupt */ + UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ + UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ + UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ + UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ + CMP2_IRQn = 70, /**< CMP2 interrupt */ + FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ + DAC1_IRQn = 72, /**< DAC1 interrupt */ + ADC1_IRQn = 73, /**< ADC1 interrupt */ + I2C2_IRQn = 74, /**< I2C2 interrupt */ + CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ + CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ + CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ + CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ + CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ + CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ + SDHC_IRQn = 81, /**< SDHC interrupt */ + ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ + ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ + ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ + ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK64F12.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */ + kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */ + kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */ + kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */ + kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ + kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ + kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ + kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */ + kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ + kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ + kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ + kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ + kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ + kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ + kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ + kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ + kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ + kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ + kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ + kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ + kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ + kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ + kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ + kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ + kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ + kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ + kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ + kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ + kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */ + kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1. */ + kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2. */ + kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */ + kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name SC1 - ADC Status and Control Registers 1 */ +#define ADC_SC1_ADCH_MASK (0x1FU) +#define ADC_SC1_ADCH_SHIFT (0U) +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK (0x20U) +#define ADC_SC1_DIFF_SHIFT (5U) +#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) +#define ADC_SC1_AIEN_MASK (0x40U) +#define ADC_SC1_AIEN_SHIFT (6U) +#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) +#define ADC_SC1_COCO_MASK (0x80U) +#define ADC_SC1_COCO_SHIFT (7U) +#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) + +/* The count of ADC_SC1 */ +#define ADC_SC1_COUNT (2U) + +/*! @name CFG1 - ADC Configuration Register 1 */ +#define ADC_CFG1_ADICLK_MASK (0x3U) +#define ADC_CFG1_ADICLK_SHIFT (0U) +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK (0xCU) +#define ADC_CFG1_MODE_SHIFT (2U) +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK (0x10U) +#define ADC_CFG1_ADLSMP_SHIFT (4U) +#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) +#define ADC_CFG1_ADIV_MASK (0x60U) +#define ADC_CFG1_ADIV_SHIFT (5U) +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK (0x80U) +#define ADC_CFG1_ADLPC_SHIFT (7U) +#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) + +/*! @name CFG2 - ADC Configuration Register 2 */ +#define ADC_CFG2_ADLSTS_MASK (0x3U) +#define ADC_CFG2_ADLSTS_SHIFT (0U) +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK (0x4U) +#define ADC_CFG2_ADHSC_SHIFT (2U) +#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) +#define ADC_CFG2_ADACKEN_MASK (0x8U) +#define ADC_CFG2_ADACKEN_SHIFT (3U) +#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) +#define ADC_CFG2_MUXSEL_MASK (0x10U) +#define ADC_CFG2_MUXSEL_SHIFT (4U) +#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) + +/*! @name R - ADC Data Result Register */ +#define ADC_R_D_MASK (0xFFFFU) +#define ADC_R_D_SHIFT (0U) +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (2U) + +/*! @name CV1 - Compare Value Registers */ +#define ADC_CV1_CV_MASK (0xFFFFU) +#define ADC_CV1_CV_SHIFT (0U) +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) + +/*! @name CV2 - Compare Value Registers */ +#define ADC_CV2_CV_MASK (0xFFFFU) +#define ADC_CV2_CV_SHIFT (0U) +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) + +/*! @name SC2 - Status and Control Register 2 */ +#define ADC_SC2_REFSEL_MASK (0x3U) +#define ADC_SC2_REFSEL_SHIFT (0U) +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK (0x4U) +#define ADC_SC2_DMAEN_SHIFT (2U) +#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) +#define ADC_SC2_ACREN_MASK (0x8U) +#define ADC_SC2_ACREN_SHIFT (3U) +#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) +#define ADC_SC2_ACFGT_MASK (0x10U) +#define ADC_SC2_ACFGT_SHIFT (4U) +#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) +#define ADC_SC2_ACFE_MASK (0x20U) +#define ADC_SC2_ACFE_SHIFT (5U) +#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) +#define ADC_SC2_ADTRG_MASK (0x40U) +#define ADC_SC2_ADTRG_SHIFT (6U) +#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) +#define ADC_SC2_ADACT_MASK (0x80U) +#define ADC_SC2_ADACT_SHIFT (7U) +#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) + +/*! @name SC3 - Status and Control Register 3 */ +#define ADC_SC3_AVGS_MASK (0x3U) +#define ADC_SC3_AVGS_SHIFT (0U) +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK (0x4U) +#define ADC_SC3_AVGE_SHIFT (2U) +#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) +#define ADC_SC3_ADCO_MASK (0x8U) +#define ADC_SC3_ADCO_SHIFT (3U) +#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) +#define ADC_SC3_CALF_MASK (0x40U) +#define ADC_SC3_CALF_SHIFT (6U) +#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) +#define ADC_SC3_CAL_MASK (0x80U) +#define ADC_SC3_CAL_SHIFT (7U) +#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) + +/*! @name OFS - ADC Offset Correction Register */ +#define ADC_OFS_OFS_MASK (0xFFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) + +/*! @name PG - ADC Plus-Side Gain Register */ +#define ADC_PG_PG_MASK (0xFFFFU) +#define ADC_PG_PG_SHIFT (0U) +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) + +/*! @name MG - ADC Minus-Side Gain Register */ +#define ADC_MG_MG_MASK (0xFFFFU) +#define ADC_MG_MG_SHIFT (0U) +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) + +/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPD_CLPD_MASK (0x3FU) +#define ADC_CLPD_CLPD_SHIFT (0U) +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) + +/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPS_CLPS_MASK (0x3FU) +#define ADC_CLPS_CLPS_SHIFT (0U) +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) + +/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP4_CLP4_MASK (0x3FFU) +#define ADC_CLP4_CLP4_SHIFT (0U) +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) + +/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP3_CLP3_MASK (0x1FFU) +#define ADC_CLP3_CLP3_SHIFT (0U) +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) + +/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP2_CLP2_MASK (0xFFU) +#define ADC_CLP2_CLP2_SHIFT (0U) +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) + +/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP1_CLP1_MASK (0x7FU) +#define ADC_CLP1_CLP1_SHIFT (0U) +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) + +/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP0_CLP0_MASK (0x3FU) +#define ADC_CLP0_CLP0_SHIFT (0U) +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) + +/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMD_CLMD_MASK (0x3FU) +#define ADC_CLMD_CLMD_SHIFT (0U) +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) + +/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMS_CLMS_MASK (0x3FU) +#define ADC_CLMS_CLMS_SHIFT (0U) +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) + +/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM4_CLM4_MASK (0x3FFU) +#define ADC_CLM4_CLM4_SHIFT (0U) +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) + +/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM3_CLM3_MASK (0x1FFU) +#define ADC_CLM3_CLM3_SHIFT (0U) +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) + +/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM2_CLM2_MASK (0xFFU) +#define ADC_CLM2_CLM2_SHIFT (0U) +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) + +/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM1_CLM1_MASK (0x7FU) +#define ADC_CLM1_CLM1_SHIFT (0U) +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) + +/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM0_CLM0_MASK (0x3FU) +#define ADC_CLM0_CLM0_SHIFT (0U) +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400BB000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer + * @{ + */ + +/** AIPS - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ + __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ + __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ + __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ + __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ + __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ + __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ + __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ + __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ + __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ + __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ + __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ + __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ + __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ + __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */ +} AIPS_Type; + +/* ---------------------------------------------------------------------------- + -- AIPS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPS_Register_Masks AIPS Register Masks + * @{ + */ + +/*! @name MPRA - Master Privilege Register A */ +#define AIPS_MPRA_MPL5_MASK (0x100U) +#define AIPS_MPRA_MPL5_SHIFT (8U) +#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) +#define AIPS_MPRA_MTW5_MASK (0x200U) +#define AIPS_MPRA_MTW5_SHIFT (9U) +#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) +#define AIPS_MPRA_MTR5_MASK (0x400U) +#define AIPS_MPRA_MTR5_SHIFT (10U) +#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) +#define AIPS_MPRA_MPL4_MASK (0x1000U) +#define AIPS_MPRA_MPL4_SHIFT (12U) +#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) +#define AIPS_MPRA_MTW4_MASK (0x2000U) +#define AIPS_MPRA_MTW4_SHIFT (13U) +#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) +#define AIPS_MPRA_MTR4_MASK (0x4000U) +#define AIPS_MPRA_MTR4_SHIFT (14U) +#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) +#define AIPS_MPRA_MPL3_MASK (0x10000U) +#define AIPS_MPRA_MPL3_SHIFT (16U) +#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) +#define AIPS_MPRA_MTW3_MASK (0x20000U) +#define AIPS_MPRA_MTW3_SHIFT (17U) +#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) +#define AIPS_MPRA_MTR3_MASK (0x40000U) +#define AIPS_MPRA_MTR3_SHIFT (18U) +#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) +#define AIPS_MPRA_MPL2_MASK (0x100000U) +#define AIPS_MPRA_MPL2_SHIFT (20U) +#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) +#define AIPS_MPRA_MTW2_MASK (0x200000U) +#define AIPS_MPRA_MTW2_SHIFT (21U) +#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) +#define AIPS_MPRA_MTR2_MASK (0x400000U) +#define AIPS_MPRA_MTR2_SHIFT (22U) +#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) +#define AIPS_MPRA_MPL1_MASK (0x1000000U) +#define AIPS_MPRA_MPL1_SHIFT (24U) +#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) +#define AIPS_MPRA_MTW1_MASK (0x2000000U) +#define AIPS_MPRA_MTW1_SHIFT (25U) +#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) +#define AIPS_MPRA_MTR1_MASK (0x4000000U) +#define AIPS_MPRA_MTR1_SHIFT (26U) +#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) +#define AIPS_MPRA_MPL0_MASK (0x10000000U) +#define AIPS_MPRA_MPL0_SHIFT (28U) +#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) +#define AIPS_MPRA_MTW0_MASK (0x20000000U) +#define AIPS_MPRA_MTW0_SHIFT (29U) +#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) +#define AIPS_MPRA_MTR0_MASK (0x40000000U) +#define AIPS_MPRA_MTR0_SHIFT (30U) +#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) + +/*! @name PACRA - Peripheral Access Control Register */ +#define AIPS_PACRA_TP7_MASK (0x1U) +#define AIPS_PACRA_TP7_SHIFT (0U) +#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) +#define AIPS_PACRA_WP7_MASK (0x2U) +#define AIPS_PACRA_WP7_SHIFT (1U) +#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) +#define AIPS_PACRA_SP7_MASK (0x4U) +#define AIPS_PACRA_SP7_SHIFT (2U) +#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) +#define AIPS_PACRA_TP6_MASK (0x10U) +#define AIPS_PACRA_TP6_SHIFT (4U) +#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) +#define AIPS_PACRA_WP6_MASK (0x20U) +#define AIPS_PACRA_WP6_SHIFT (5U) +#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) +#define AIPS_PACRA_SP6_MASK (0x40U) +#define AIPS_PACRA_SP6_SHIFT (6U) +#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) +#define AIPS_PACRA_TP5_MASK (0x100U) +#define AIPS_PACRA_TP5_SHIFT (8U) +#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) +#define AIPS_PACRA_WP5_MASK (0x200U) +#define AIPS_PACRA_WP5_SHIFT (9U) +#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) +#define AIPS_PACRA_SP5_MASK (0x400U) +#define AIPS_PACRA_SP5_SHIFT (10U) +#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) +#define AIPS_PACRA_TP4_MASK (0x1000U) +#define AIPS_PACRA_TP4_SHIFT (12U) +#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) +#define AIPS_PACRA_WP4_MASK (0x2000U) +#define AIPS_PACRA_WP4_SHIFT (13U) +#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) +#define AIPS_PACRA_SP4_MASK (0x4000U) +#define AIPS_PACRA_SP4_SHIFT (14U) +#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) +#define AIPS_PACRA_TP3_MASK (0x10000U) +#define AIPS_PACRA_TP3_SHIFT (16U) +#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) +#define AIPS_PACRA_WP3_MASK (0x20000U) +#define AIPS_PACRA_WP3_SHIFT (17U) +#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) +#define AIPS_PACRA_SP3_MASK (0x40000U) +#define AIPS_PACRA_SP3_SHIFT (18U) +#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) +#define AIPS_PACRA_TP2_MASK (0x100000U) +#define AIPS_PACRA_TP2_SHIFT (20U) +#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) +#define AIPS_PACRA_WP2_MASK (0x200000U) +#define AIPS_PACRA_WP2_SHIFT (21U) +#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) +#define AIPS_PACRA_SP2_MASK (0x400000U) +#define AIPS_PACRA_SP2_SHIFT (22U) +#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) +#define AIPS_PACRA_TP1_MASK (0x1000000U) +#define AIPS_PACRA_TP1_SHIFT (24U) +#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) +#define AIPS_PACRA_WP1_MASK (0x2000000U) +#define AIPS_PACRA_WP1_SHIFT (25U) +#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) +#define AIPS_PACRA_SP1_MASK (0x4000000U) +#define AIPS_PACRA_SP1_SHIFT (26U) +#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) +#define AIPS_PACRA_TP0_MASK (0x10000000U) +#define AIPS_PACRA_TP0_SHIFT (28U) +#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) +#define AIPS_PACRA_WP0_MASK (0x20000000U) +#define AIPS_PACRA_WP0_SHIFT (29U) +#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) +#define AIPS_PACRA_SP0_MASK (0x40000000U) +#define AIPS_PACRA_SP0_SHIFT (30U) +#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) + +/*! @name PACRB - Peripheral Access Control Register */ +#define AIPS_PACRB_TP7_MASK (0x1U) +#define AIPS_PACRB_TP7_SHIFT (0U) +#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) +#define AIPS_PACRB_WP7_MASK (0x2U) +#define AIPS_PACRB_WP7_SHIFT (1U) +#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) +#define AIPS_PACRB_SP7_MASK (0x4U) +#define AIPS_PACRB_SP7_SHIFT (2U) +#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) +#define AIPS_PACRB_TP6_MASK (0x10U) +#define AIPS_PACRB_TP6_SHIFT (4U) +#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) +#define AIPS_PACRB_WP6_MASK (0x20U) +#define AIPS_PACRB_WP6_SHIFT (5U) +#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) +#define AIPS_PACRB_SP6_MASK (0x40U) +#define AIPS_PACRB_SP6_SHIFT (6U) +#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) +#define AIPS_PACRB_TP5_MASK (0x100U) +#define AIPS_PACRB_TP5_SHIFT (8U) +#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) +#define AIPS_PACRB_WP5_MASK (0x200U) +#define AIPS_PACRB_WP5_SHIFT (9U) +#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) +#define AIPS_PACRB_SP5_MASK (0x400U) +#define AIPS_PACRB_SP5_SHIFT (10U) +#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) +#define AIPS_PACRB_TP4_MASK (0x1000U) +#define AIPS_PACRB_TP4_SHIFT (12U) +#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) +#define AIPS_PACRB_WP4_MASK (0x2000U) +#define AIPS_PACRB_WP4_SHIFT (13U) +#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) +#define AIPS_PACRB_SP4_MASK (0x4000U) +#define AIPS_PACRB_SP4_SHIFT (14U) +#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) +#define AIPS_PACRB_TP3_MASK (0x10000U) +#define AIPS_PACRB_TP3_SHIFT (16U) +#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) +#define AIPS_PACRB_WP3_MASK (0x20000U) +#define AIPS_PACRB_WP3_SHIFT (17U) +#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) +#define AIPS_PACRB_SP3_MASK (0x40000U) +#define AIPS_PACRB_SP3_SHIFT (18U) +#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) +#define AIPS_PACRB_TP2_MASK (0x100000U) +#define AIPS_PACRB_TP2_SHIFT (20U) +#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) +#define AIPS_PACRB_WP2_MASK (0x200000U) +#define AIPS_PACRB_WP2_SHIFT (21U) +#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) +#define AIPS_PACRB_SP2_MASK (0x400000U) +#define AIPS_PACRB_SP2_SHIFT (22U) +#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) +#define AIPS_PACRB_TP1_MASK (0x1000000U) +#define AIPS_PACRB_TP1_SHIFT (24U) +#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) +#define AIPS_PACRB_WP1_MASK (0x2000000U) +#define AIPS_PACRB_WP1_SHIFT (25U) +#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) +#define AIPS_PACRB_SP1_MASK (0x4000000U) +#define AIPS_PACRB_SP1_SHIFT (26U) +#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) +#define AIPS_PACRB_TP0_MASK (0x10000000U) +#define AIPS_PACRB_TP0_SHIFT (28U) +#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) +#define AIPS_PACRB_WP0_MASK (0x20000000U) +#define AIPS_PACRB_WP0_SHIFT (29U) +#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) +#define AIPS_PACRB_SP0_MASK (0x40000000U) +#define AIPS_PACRB_SP0_SHIFT (30U) +#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) + +/*! @name PACRC - Peripheral Access Control Register */ +#define AIPS_PACRC_TP7_MASK (0x1U) +#define AIPS_PACRC_TP7_SHIFT (0U) +#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) +#define AIPS_PACRC_WP7_MASK (0x2U) +#define AIPS_PACRC_WP7_SHIFT (1U) +#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) +#define AIPS_PACRC_SP7_MASK (0x4U) +#define AIPS_PACRC_SP7_SHIFT (2U) +#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) +#define AIPS_PACRC_TP6_MASK (0x10U) +#define AIPS_PACRC_TP6_SHIFT (4U) +#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) +#define AIPS_PACRC_WP6_MASK (0x20U) +#define AIPS_PACRC_WP6_SHIFT (5U) +#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) +#define AIPS_PACRC_SP6_MASK (0x40U) +#define AIPS_PACRC_SP6_SHIFT (6U) +#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) +#define AIPS_PACRC_TP5_MASK (0x100U) +#define AIPS_PACRC_TP5_SHIFT (8U) +#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) +#define AIPS_PACRC_WP5_MASK (0x200U) +#define AIPS_PACRC_WP5_SHIFT (9U) +#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) +#define AIPS_PACRC_SP5_MASK (0x400U) +#define AIPS_PACRC_SP5_SHIFT (10U) +#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) +#define AIPS_PACRC_TP4_MASK (0x1000U) +#define AIPS_PACRC_TP4_SHIFT (12U) +#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) +#define AIPS_PACRC_WP4_MASK (0x2000U) +#define AIPS_PACRC_WP4_SHIFT (13U) +#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) +#define AIPS_PACRC_SP4_MASK (0x4000U) +#define AIPS_PACRC_SP4_SHIFT (14U) +#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) +#define AIPS_PACRC_TP3_MASK (0x10000U) +#define AIPS_PACRC_TP3_SHIFT (16U) +#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) +#define AIPS_PACRC_WP3_MASK (0x20000U) +#define AIPS_PACRC_WP3_SHIFT (17U) +#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) +#define AIPS_PACRC_SP3_MASK (0x40000U) +#define AIPS_PACRC_SP3_SHIFT (18U) +#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) +#define AIPS_PACRC_TP2_MASK (0x100000U) +#define AIPS_PACRC_TP2_SHIFT (20U) +#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) +#define AIPS_PACRC_WP2_MASK (0x200000U) +#define AIPS_PACRC_WP2_SHIFT (21U) +#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) +#define AIPS_PACRC_SP2_MASK (0x400000U) +#define AIPS_PACRC_SP2_SHIFT (22U) +#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) +#define AIPS_PACRC_TP1_MASK (0x1000000U) +#define AIPS_PACRC_TP1_SHIFT (24U) +#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) +#define AIPS_PACRC_WP1_MASK (0x2000000U) +#define AIPS_PACRC_WP1_SHIFT (25U) +#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) +#define AIPS_PACRC_SP1_MASK (0x4000000U) +#define AIPS_PACRC_SP1_SHIFT (26U) +#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) +#define AIPS_PACRC_TP0_MASK (0x10000000U) +#define AIPS_PACRC_TP0_SHIFT (28U) +#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) +#define AIPS_PACRC_WP0_MASK (0x20000000U) +#define AIPS_PACRC_WP0_SHIFT (29U) +#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) +#define AIPS_PACRC_SP0_MASK (0x40000000U) +#define AIPS_PACRC_SP0_SHIFT (30U) +#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) + +/*! @name PACRD - Peripheral Access Control Register */ +#define AIPS_PACRD_TP7_MASK (0x1U) +#define AIPS_PACRD_TP7_SHIFT (0U) +#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) +#define AIPS_PACRD_WP7_MASK (0x2U) +#define AIPS_PACRD_WP7_SHIFT (1U) +#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) +#define AIPS_PACRD_SP7_MASK (0x4U) +#define AIPS_PACRD_SP7_SHIFT (2U) +#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) +#define AIPS_PACRD_TP6_MASK (0x10U) +#define AIPS_PACRD_TP6_SHIFT (4U) +#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) +#define AIPS_PACRD_WP6_MASK (0x20U) +#define AIPS_PACRD_WP6_SHIFT (5U) +#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) +#define AIPS_PACRD_SP6_MASK (0x40U) +#define AIPS_PACRD_SP6_SHIFT (6U) +#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) +#define AIPS_PACRD_TP5_MASK (0x100U) +#define AIPS_PACRD_TP5_SHIFT (8U) +#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) +#define AIPS_PACRD_WP5_MASK (0x200U) +#define AIPS_PACRD_WP5_SHIFT (9U) +#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) +#define AIPS_PACRD_SP5_MASK (0x400U) +#define AIPS_PACRD_SP5_SHIFT (10U) +#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) +#define AIPS_PACRD_TP4_MASK (0x1000U) +#define AIPS_PACRD_TP4_SHIFT (12U) +#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) +#define AIPS_PACRD_WP4_MASK (0x2000U) +#define AIPS_PACRD_WP4_SHIFT (13U) +#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) +#define AIPS_PACRD_SP4_MASK (0x4000U) +#define AIPS_PACRD_SP4_SHIFT (14U) +#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) +#define AIPS_PACRD_TP3_MASK (0x10000U) +#define AIPS_PACRD_TP3_SHIFT (16U) +#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) +#define AIPS_PACRD_WP3_MASK (0x20000U) +#define AIPS_PACRD_WP3_SHIFT (17U) +#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) +#define AIPS_PACRD_SP3_MASK (0x40000U) +#define AIPS_PACRD_SP3_SHIFT (18U) +#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) +#define AIPS_PACRD_TP2_MASK (0x100000U) +#define AIPS_PACRD_TP2_SHIFT (20U) +#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) +#define AIPS_PACRD_WP2_MASK (0x200000U) +#define AIPS_PACRD_WP2_SHIFT (21U) +#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) +#define AIPS_PACRD_SP2_MASK (0x400000U) +#define AIPS_PACRD_SP2_SHIFT (22U) +#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) +#define AIPS_PACRD_TP1_MASK (0x1000000U) +#define AIPS_PACRD_TP1_SHIFT (24U) +#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) +#define AIPS_PACRD_WP1_MASK (0x2000000U) +#define AIPS_PACRD_WP1_SHIFT (25U) +#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) +#define AIPS_PACRD_SP1_MASK (0x4000000U) +#define AIPS_PACRD_SP1_SHIFT (26U) +#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) +#define AIPS_PACRD_TP0_MASK (0x10000000U) +#define AIPS_PACRD_TP0_SHIFT (28U) +#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) +#define AIPS_PACRD_WP0_MASK (0x20000000U) +#define AIPS_PACRD_WP0_SHIFT (29U) +#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) +#define AIPS_PACRD_SP0_MASK (0x40000000U) +#define AIPS_PACRD_SP0_SHIFT (30U) +#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) + +/*! @name PACRE - Peripheral Access Control Register */ +#define AIPS_PACRE_TP7_MASK (0x1U) +#define AIPS_PACRE_TP7_SHIFT (0U) +#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) +#define AIPS_PACRE_WP7_MASK (0x2U) +#define AIPS_PACRE_WP7_SHIFT (1U) +#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) +#define AIPS_PACRE_SP7_MASK (0x4U) +#define AIPS_PACRE_SP7_SHIFT (2U) +#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) +#define AIPS_PACRE_TP6_MASK (0x10U) +#define AIPS_PACRE_TP6_SHIFT (4U) +#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) +#define AIPS_PACRE_WP6_MASK (0x20U) +#define AIPS_PACRE_WP6_SHIFT (5U) +#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) +#define AIPS_PACRE_SP6_MASK (0x40U) +#define AIPS_PACRE_SP6_SHIFT (6U) +#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) +#define AIPS_PACRE_TP5_MASK (0x100U) +#define AIPS_PACRE_TP5_SHIFT (8U) +#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) +#define AIPS_PACRE_WP5_MASK (0x200U) +#define AIPS_PACRE_WP5_SHIFT (9U) +#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) +#define AIPS_PACRE_SP5_MASK (0x400U) +#define AIPS_PACRE_SP5_SHIFT (10U) +#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) +#define AIPS_PACRE_TP4_MASK (0x1000U) +#define AIPS_PACRE_TP4_SHIFT (12U) +#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) +#define AIPS_PACRE_WP4_MASK (0x2000U) +#define AIPS_PACRE_WP4_SHIFT (13U) +#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) +#define AIPS_PACRE_SP4_MASK (0x4000U) +#define AIPS_PACRE_SP4_SHIFT (14U) +#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) +#define AIPS_PACRE_TP3_MASK (0x10000U) +#define AIPS_PACRE_TP3_SHIFT (16U) +#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) +#define AIPS_PACRE_WP3_MASK (0x20000U) +#define AIPS_PACRE_WP3_SHIFT (17U) +#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) +#define AIPS_PACRE_SP3_MASK (0x40000U) +#define AIPS_PACRE_SP3_SHIFT (18U) +#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) +#define AIPS_PACRE_TP2_MASK (0x100000U) +#define AIPS_PACRE_TP2_SHIFT (20U) +#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) +#define AIPS_PACRE_WP2_MASK (0x200000U) +#define AIPS_PACRE_WP2_SHIFT (21U) +#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) +#define AIPS_PACRE_SP2_MASK (0x400000U) +#define AIPS_PACRE_SP2_SHIFT (22U) +#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) +#define AIPS_PACRE_TP1_MASK (0x1000000U) +#define AIPS_PACRE_TP1_SHIFT (24U) +#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) +#define AIPS_PACRE_WP1_MASK (0x2000000U) +#define AIPS_PACRE_WP1_SHIFT (25U) +#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) +#define AIPS_PACRE_SP1_MASK (0x4000000U) +#define AIPS_PACRE_SP1_SHIFT (26U) +#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) +#define AIPS_PACRE_TP0_MASK (0x10000000U) +#define AIPS_PACRE_TP0_SHIFT (28U) +#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) +#define AIPS_PACRE_WP0_MASK (0x20000000U) +#define AIPS_PACRE_WP0_SHIFT (29U) +#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) +#define AIPS_PACRE_SP0_MASK (0x40000000U) +#define AIPS_PACRE_SP0_SHIFT (30U) +#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) + +/*! @name PACRF - Peripheral Access Control Register */ +#define AIPS_PACRF_TP7_MASK (0x1U) +#define AIPS_PACRF_TP7_SHIFT (0U) +#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) +#define AIPS_PACRF_WP7_MASK (0x2U) +#define AIPS_PACRF_WP7_SHIFT (1U) +#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) +#define AIPS_PACRF_SP7_MASK (0x4U) +#define AIPS_PACRF_SP7_SHIFT (2U) +#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) +#define AIPS_PACRF_TP6_MASK (0x10U) +#define AIPS_PACRF_TP6_SHIFT (4U) +#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) +#define AIPS_PACRF_WP6_MASK (0x20U) +#define AIPS_PACRF_WP6_SHIFT (5U) +#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) +#define AIPS_PACRF_SP6_MASK (0x40U) +#define AIPS_PACRF_SP6_SHIFT (6U) +#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) +#define AIPS_PACRF_TP5_MASK (0x100U) +#define AIPS_PACRF_TP5_SHIFT (8U) +#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) +#define AIPS_PACRF_WP5_MASK (0x200U) +#define AIPS_PACRF_WP5_SHIFT (9U) +#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) +#define AIPS_PACRF_SP5_MASK (0x400U) +#define AIPS_PACRF_SP5_SHIFT (10U) +#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) +#define AIPS_PACRF_TP4_MASK (0x1000U) +#define AIPS_PACRF_TP4_SHIFT (12U) +#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) +#define AIPS_PACRF_WP4_MASK (0x2000U) +#define AIPS_PACRF_WP4_SHIFT (13U) +#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) +#define AIPS_PACRF_SP4_MASK (0x4000U) +#define AIPS_PACRF_SP4_SHIFT (14U) +#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) +#define AIPS_PACRF_TP3_MASK (0x10000U) +#define AIPS_PACRF_TP3_SHIFT (16U) +#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) +#define AIPS_PACRF_WP3_MASK (0x20000U) +#define AIPS_PACRF_WP3_SHIFT (17U) +#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) +#define AIPS_PACRF_SP3_MASK (0x40000U) +#define AIPS_PACRF_SP3_SHIFT (18U) +#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) +#define AIPS_PACRF_TP2_MASK (0x100000U) +#define AIPS_PACRF_TP2_SHIFT (20U) +#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) +#define AIPS_PACRF_WP2_MASK (0x200000U) +#define AIPS_PACRF_WP2_SHIFT (21U) +#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) +#define AIPS_PACRF_SP2_MASK (0x400000U) +#define AIPS_PACRF_SP2_SHIFT (22U) +#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) +#define AIPS_PACRF_TP1_MASK (0x1000000U) +#define AIPS_PACRF_TP1_SHIFT (24U) +#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) +#define AIPS_PACRF_WP1_MASK (0x2000000U) +#define AIPS_PACRF_WP1_SHIFT (25U) +#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) +#define AIPS_PACRF_SP1_MASK (0x4000000U) +#define AIPS_PACRF_SP1_SHIFT (26U) +#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) +#define AIPS_PACRF_TP0_MASK (0x10000000U) +#define AIPS_PACRF_TP0_SHIFT (28U) +#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) +#define AIPS_PACRF_WP0_MASK (0x20000000U) +#define AIPS_PACRF_WP0_SHIFT (29U) +#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) +#define AIPS_PACRF_SP0_MASK (0x40000000U) +#define AIPS_PACRF_SP0_SHIFT (30U) +#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) + +/*! @name PACRG - Peripheral Access Control Register */ +#define AIPS_PACRG_TP7_MASK (0x1U) +#define AIPS_PACRG_TP7_SHIFT (0U) +#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) +#define AIPS_PACRG_WP7_MASK (0x2U) +#define AIPS_PACRG_WP7_SHIFT (1U) +#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) +#define AIPS_PACRG_SP7_MASK (0x4U) +#define AIPS_PACRG_SP7_SHIFT (2U) +#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) +#define AIPS_PACRG_TP6_MASK (0x10U) +#define AIPS_PACRG_TP6_SHIFT (4U) +#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) +#define AIPS_PACRG_WP6_MASK (0x20U) +#define AIPS_PACRG_WP6_SHIFT (5U) +#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) +#define AIPS_PACRG_SP6_MASK (0x40U) +#define AIPS_PACRG_SP6_SHIFT (6U) +#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) +#define AIPS_PACRG_TP5_MASK (0x100U) +#define AIPS_PACRG_TP5_SHIFT (8U) +#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) +#define AIPS_PACRG_WP5_MASK (0x200U) +#define AIPS_PACRG_WP5_SHIFT (9U) +#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) +#define AIPS_PACRG_SP5_MASK (0x400U) +#define AIPS_PACRG_SP5_SHIFT (10U) +#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) +#define AIPS_PACRG_TP4_MASK (0x1000U) +#define AIPS_PACRG_TP4_SHIFT (12U) +#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) +#define AIPS_PACRG_WP4_MASK (0x2000U) +#define AIPS_PACRG_WP4_SHIFT (13U) +#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) +#define AIPS_PACRG_SP4_MASK (0x4000U) +#define AIPS_PACRG_SP4_SHIFT (14U) +#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) +#define AIPS_PACRG_TP3_MASK (0x10000U) +#define AIPS_PACRG_TP3_SHIFT (16U) +#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) +#define AIPS_PACRG_WP3_MASK (0x20000U) +#define AIPS_PACRG_WP3_SHIFT (17U) +#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) +#define AIPS_PACRG_SP3_MASK (0x40000U) +#define AIPS_PACRG_SP3_SHIFT (18U) +#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) +#define AIPS_PACRG_TP2_MASK (0x100000U) +#define AIPS_PACRG_TP2_SHIFT (20U) +#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) +#define AIPS_PACRG_WP2_MASK (0x200000U) +#define AIPS_PACRG_WP2_SHIFT (21U) +#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) +#define AIPS_PACRG_SP2_MASK (0x400000U) +#define AIPS_PACRG_SP2_SHIFT (22U) +#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) +#define AIPS_PACRG_TP1_MASK (0x1000000U) +#define AIPS_PACRG_TP1_SHIFT (24U) +#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) +#define AIPS_PACRG_WP1_MASK (0x2000000U) +#define AIPS_PACRG_WP1_SHIFT (25U) +#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) +#define AIPS_PACRG_SP1_MASK (0x4000000U) +#define AIPS_PACRG_SP1_SHIFT (26U) +#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) +#define AIPS_PACRG_TP0_MASK (0x10000000U) +#define AIPS_PACRG_TP0_SHIFT (28U) +#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) +#define AIPS_PACRG_WP0_MASK (0x20000000U) +#define AIPS_PACRG_WP0_SHIFT (29U) +#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) +#define AIPS_PACRG_SP0_MASK (0x40000000U) +#define AIPS_PACRG_SP0_SHIFT (30U) +#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) + +/*! @name PACRH - Peripheral Access Control Register */ +#define AIPS_PACRH_TP7_MASK (0x1U) +#define AIPS_PACRH_TP7_SHIFT (0U) +#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) +#define AIPS_PACRH_WP7_MASK (0x2U) +#define AIPS_PACRH_WP7_SHIFT (1U) +#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) +#define AIPS_PACRH_SP7_MASK (0x4U) +#define AIPS_PACRH_SP7_SHIFT (2U) +#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) +#define AIPS_PACRH_TP6_MASK (0x10U) +#define AIPS_PACRH_TP6_SHIFT (4U) +#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) +#define AIPS_PACRH_WP6_MASK (0x20U) +#define AIPS_PACRH_WP6_SHIFT (5U) +#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) +#define AIPS_PACRH_SP6_MASK (0x40U) +#define AIPS_PACRH_SP6_SHIFT (6U) +#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) +#define AIPS_PACRH_TP5_MASK (0x100U) +#define AIPS_PACRH_TP5_SHIFT (8U) +#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) +#define AIPS_PACRH_WP5_MASK (0x200U) +#define AIPS_PACRH_WP5_SHIFT (9U) +#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) +#define AIPS_PACRH_SP5_MASK (0x400U) +#define AIPS_PACRH_SP5_SHIFT (10U) +#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) +#define AIPS_PACRH_TP4_MASK (0x1000U) +#define AIPS_PACRH_TP4_SHIFT (12U) +#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) +#define AIPS_PACRH_WP4_MASK (0x2000U) +#define AIPS_PACRH_WP4_SHIFT (13U) +#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) +#define AIPS_PACRH_SP4_MASK (0x4000U) +#define AIPS_PACRH_SP4_SHIFT (14U) +#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) +#define AIPS_PACRH_TP3_MASK (0x10000U) +#define AIPS_PACRH_TP3_SHIFT (16U) +#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) +#define AIPS_PACRH_WP3_MASK (0x20000U) +#define AIPS_PACRH_WP3_SHIFT (17U) +#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) +#define AIPS_PACRH_SP3_MASK (0x40000U) +#define AIPS_PACRH_SP3_SHIFT (18U) +#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) +#define AIPS_PACRH_TP2_MASK (0x100000U) +#define AIPS_PACRH_TP2_SHIFT (20U) +#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) +#define AIPS_PACRH_WP2_MASK (0x200000U) +#define AIPS_PACRH_WP2_SHIFT (21U) +#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) +#define AIPS_PACRH_SP2_MASK (0x400000U) +#define AIPS_PACRH_SP2_SHIFT (22U) +#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) +#define AIPS_PACRH_TP1_MASK (0x1000000U) +#define AIPS_PACRH_TP1_SHIFT (24U) +#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) +#define AIPS_PACRH_WP1_MASK (0x2000000U) +#define AIPS_PACRH_WP1_SHIFT (25U) +#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) +#define AIPS_PACRH_SP1_MASK (0x4000000U) +#define AIPS_PACRH_SP1_SHIFT (26U) +#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) +#define AIPS_PACRH_TP0_MASK (0x10000000U) +#define AIPS_PACRH_TP0_SHIFT (28U) +#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) +#define AIPS_PACRH_WP0_MASK (0x20000000U) +#define AIPS_PACRH_WP0_SHIFT (29U) +#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) +#define AIPS_PACRH_SP0_MASK (0x40000000U) +#define AIPS_PACRH_SP0_SHIFT (30U) +#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) + +/*! @name PACRI - Peripheral Access Control Register */ +#define AIPS_PACRI_TP7_MASK (0x1U) +#define AIPS_PACRI_TP7_SHIFT (0U) +#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) +#define AIPS_PACRI_WP7_MASK (0x2U) +#define AIPS_PACRI_WP7_SHIFT (1U) +#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) +#define AIPS_PACRI_SP7_MASK (0x4U) +#define AIPS_PACRI_SP7_SHIFT (2U) +#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) +#define AIPS_PACRI_TP6_MASK (0x10U) +#define AIPS_PACRI_TP6_SHIFT (4U) +#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) +#define AIPS_PACRI_WP6_MASK (0x20U) +#define AIPS_PACRI_WP6_SHIFT (5U) +#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) +#define AIPS_PACRI_SP6_MASK (0x40U) +#define AIPS_PACRI_SP6_SHIFT (6U) +#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) +#define AIPS_PACRI_TP5_MASK (0x100U) +#define AIPS_PACRI_TP5_SHIFT (8U) +#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) +#define AIPS_PACRI_WP5_MASK (0x200U) +#define AIPS_PACRI_WP5_SHIFT (9U) +#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) +#define AIPS_PACRI_SP5_MASK (0x400U) +#define AIPS_PACRI_SP5_SHIFT (10U) +#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) +#define AIPS_PACRI_TP4_MASK (0x1000U) +#define AIPS_PACRI_TP4_SHIFT (12U) +#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) +#define AIPS_PACRI_WP4_MASK (0x2000U) +#define AIPS_PACRI_WP4_SHIFT (13U) +#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) +#define AIPS_PACRI_SP4_MASK (0x4000U) +#define AIPS_PACRI_SP4_SHIFT (14U) +#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) +#define AIPS_PACRI_TP3_MASK (0x10000U) +#define AIPS_PACRI_TP3_SHIFT (16U) +#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) +#define AIPS_PACRI_WP3_MASK (0x20000U) +#define AIPS_PACRI_WP3_SHIFT (17U) +#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) +#define AIPS_PACRI_SP3_MASK (0x40000U) +#define AIPS_PACRI_SP3_SHIFT (18U) +#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) +#define AIPS_PACRI_TP2_MASK (0x100000U) +#define AIPS_PACRI_TP2_SHIFT (20U) +#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) +#define AIPS_PACRI_WP2_MASK (0x200000U) +#define AIPS_PACRI_WP2_SHIFT (21U) +#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) +#define AIPS_PACRI_SP2_MASK (0x400000U) +#define AIPS_PACRI_SP2_SHIFT (22U) +#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) +#define AIPS_PACRI_TP1_MASK (0x1000000U) +#define AIPS_PACRI_TP1_SHIFT (24U) +#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) +#define AIPS_PACRI_WP1_MASK (0x2000000U) +#define AIPS_PACRI_WP1_SHIFT (25U) +#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) +#define AIPS_PACRI_SP1_MASK (0x4000000U) +#define AIPS_PACRI_SP1_SHIFT (26U) +#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) +#define AIPS_PACRI_TP0_MASK (0x10000000U) +#define AIPS_PACRI_TP0_SHIFT (28U) +#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) +#define AIPS_PACRI_WP0_MASK (0x20000000U) +#define AIPS_PACRI_WP0_SHIFT (29U) +#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) +#define AIPS_PACRI_SP0_MASK (0x40000000U) +#define AIPS_PACRI_SP0_SHIFT (30U) +#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) + +/*! @name PACRJ - Peripheral Access Control Register */ +#define AIPS_PACRJ_TP7_MASK (0x1U) +#define AIPS_PACRJ_TP7_SHIFT (0U) +#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) +#define AIPS_PACRJ_WP7_MASK (0x2U) +#define AIPS_PACRJ_WP7_SHIFT (1U) +#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) +#define AIPS_PACRJ_SP7_MASK (0x4U) +#define AIPS_PACRJ_SP7_SHIFT (2U) +#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) +#define AIPS_PACRJ_TP6_MASK (0x10U) +#define AIPS_PACRJ_TP6_SHIFT (4U) +#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) +#define AIPS_PACRJ_WP6_MASK (0x20U) +#define AIPS_PACRJ_WP6_SHIFT (5U) +#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) +#define AIPS_PACRJ_SP6_MASK (0x40U) +#define AIPS_PACRJ_SP6_SHIFT (6U) +#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) +#define AIPS_PACRJ_TP5_MASK (0x100U) +#define AIPS_PACRJ_TP5_SHIFT (8U) +#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) +#define AIPS_PACRJ_WP5_MASK (0x200U) +#define AIPS_PACRJ_WP5_SHIFT (9U) +#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) +#define AIPS_PACRJ_SP5_MASK (0x400U) +#define AIPS_PACRJ_SP5_SHIFT (10U) +#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) +#define AIPS_PACRJ_TP4_MASK (0x1000U) +#define AIPS_PACRJ_TP4_SHIFT (12U) +#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) +#define AIPS_PACRJ_WP4_MASK (0x2000U) +#define AIPS_PACRJ_WP4_SHIFT (13U) +#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) +#define AIPS_PACRJ_SP4_MASK (0x4000U) +#define AIPS_PACRJ_SP4_SHIFT (14U) +#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) +#define AIPS_PACRJ_TP3_MASK (0x10000U) +#define AIPS_PACRJ_TP3_SHIFT (16U) +#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) +#define AIPS_PACRJ_WP3_MASK (0x20000U) +#define AIPS_PACRJ_WP3_SHIFT (17U) +#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) +#define AIPS_PACRJ_SP3_MASK (0x40000U) +#define AIPS_PACRJ_SP3_SHIFT (18U) +#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) +#define AIPS_PACRJ_TP2_MASK (0x100000U) +#define AIPS_PACRJ_TP2_SHIFT (20U) +#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) +#define AIPS_PACRJ_WP2_MASK (0x200000U) +#define AIPS_PACRJ_WP2_SHIFT (21U) +#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) +#define AIPS_PACRJ_SP2_MASK (0x400000U) +#define AIPS_PACRJ_SP2_SHIFT (22U) +#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) +#define AIPS_PACRJ_TP1_MASK (0x1000000U) +#define AIPS_PACRJ_TP1_SHIFT (24U) +#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) +#define AIPS_PACRJ_WP1_MASK (0x2000000U) +#define AIPS_PACRJ_WP1_SHIFT (25U) +#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) +#define AIPS_PACRJ_SP1_MASK (0x4000000U) +#define AIPS_PACRJ_SP1_SHIFT (26U) +#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) +#define AIPS_PACRJ_TP0_MASK (0x10000000U) +#define AIPS_PACRJ_TP0_SHIFT (28U) +#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) +#define AIPS_PACRJ_WP0_MASK (0x20000000U) +#define AIPS_PACRJ_WP0_SHIFT (29U) +#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) +#define AIPS_PACRJ_SP0_MASK (0x40000000U) +#define AIPS_PACRJ_SP0_SHIFT (30U) +#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) + +/*! @name PACRK - Peripheral Access Control Register */ +#define AIPS_PACRK_TP7_MASK (0x1U) +#define AIPS_PACRK_TP7_SHIFT (0U) +#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) +#define AIPS_PACRK_WP7_MASK (0x2U) +#define AIPS_PACRK_WP7_SHIFT (1U) +#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) +#define AIPS_PACRK_SP7_MASK (0x4U) +#define AIPS_PACRK_SP7_SHIFT (2U) +#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) +#define AIPS_PACRK_TP6_MASK (0x10U) +#define AIPS_PACRK_TP6_SHIFT (4U) +#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) +#define AIPS_PACRK_WP6_MASK (0x20U) +#define AIPS_PACRK_WP6_SHIFT (5U) +#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) +#define AIPS_PACRK_SP6_MASK (0x40U) +#define AIPS_PACRK_SP6_SHIFT (6U) +#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) +#define AIPS_PACRK_TP5_MASK (0x100U) +#define AIPS_PACRK_TP5_SHIFT (8U) +#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) +#define AIPS_PACRK_WP5_MASK (0x200U) +#define AIPS_PACRK_WP5_SHIFT (9U) +#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) +#define AIPS_PACRK_SP5_MASK (0x400U) +#define AIPS_PACRK_SP5_SHIFT (10U) +#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) +#define AIPS_PACRK_TP4_MASK (0x1000U) +#define AIPS_PACRK_TP4_SHIFT (12U) +#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) +#define AIPS_PACRK_WP4_MASK (0x2000U) +#define AIPS_PACRK_WP4_SHIFT (13U) +#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) +#define AIPS_PACRK_SP4_MASK (0x4000U) +#define AIPS_PACRK_SP4_SHIFT (14U) +#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) +#define AIPS_PACRK_TP3_MASK (0x10000U) +#define AIPS_PACRK_TP3_SHIFT (16U) +#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) +#define AIPS_PACRK_WP3_MASK (0x20000U) +#define AIPS_PACRK_WP3_SHIFT (17U) +#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) +#define AIPS_PACRK_SP3_MASK (0x40000U) +#define AIPS_PACRK_SP3_SHIFT (18U) +#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) +#define AIPS_PACRK_TP2_MASK (0x100000U) +#define AIPS_PACRK_TP2_SHIFT (20U) +#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) +#define AIPS_PACRK_WP2_MASK (0x200000U) +#define AIPS_PACRK_WP2_SHIFT (21U) +#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) +#define AIPS_PACRK_SP2_MASK (0x400000U) +#define AIPS_PACRK_SP2_SHIFT (22U) +#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) +#define AIPS_PACRK_TP1_MASK (0x1000000U) +#define AIPS_PACRK_TP1_SHIFT (24U) +#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) +#define AIPS_PACRK_WP1_MASK (0x2000000U) +#define AIPS_PACRK_WP1_SHIFT (25U) +#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) +#define AIPS_PACRK_SP1_MASK (0x4000000U) +#define AIPS_PACRK_SP1_SHIFT (26U) +#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) +#define AIPS_PACRK_TP0_MASK (0x10000000U) +#define AIPS_PACRK_TP0_SHIFT (28U) +#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) +#define AIPS_PACRK_WP0_MASK (0x20000000U) +#define AIPS_PACRK_WP0_SHIFT (29U) +#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) +#define AIPS_PACRK_SP0_MASK (0x40000000U) +#define AIPS_PACRK_SP0_SHIFT (30U) +#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) + +/*! @name PACRL - Peripheral Access Control Register */ +#define AIPS_PACRL_TP7_MASK (0x1U) +#define AIPS_PACRL_TP7_SHIFT (0U) +#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) +#define AIPS_PACRL_WP7_MASK (0x2U) +#define AIPS_PACRL_WP7_SHIFT (1U) +#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) +#define AIPS_PACRL_SP7_MASK (0x4U) +#define AIPS_PACRL_SP7_SHIFT (2U) +#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) +#define AIPS_PACRL_TP6_MASK (0x10U) +#define AIPS_PACRL_TP6_SHIFT (4U) +#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) +#define AIPS_PACRL_WP6_MASK (0x20U) +#define AIPS_PACRL_WP6_SHIFT (5U) +#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) +#define AIPS_PACRL_SP6_MASK (0x40U) +#define AIPS_PACRL_SP6_SHIFT (6U) +#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) +#define AIPS_PACRL_TP5_MASK (0x100U) +#define AIPS_PACRL_TP5_SHIFT (8U) +#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) +#define AIPS_PACRL_WP5_MASK (0x200U) +#define AIPS_PACRL_WP5_SHIFT (9U) +#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) +#define AIPS_PACRL_SP5_MASK (0x400U) +#define AIPS_PACRL_SP5_SHIFT (10U) +#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) +#define AIPS_PACRL_TP4_MASK (0x1000U) +#define AIPS_PACRL_TP4_SHIFT (12U) +#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) +#define AIPS_PACRL_WP4_MASK (0x2000U) +#define AIPS_PACRL_WP4_SHIFT (13U) +#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) +#define AIPS_PACRL_SP4_MASK (0x4000U) +#define AIPS_PACRL_SP4_SHIFT (14U) +#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) +#define AIPS_PACRL_TP3_MASK (0x10000U) +#define AIPS_PACRL_TP3_SHIFT (16U) +#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) +#define AIPS_PACRL_WP3_MASK (0x20000U) +#define AIPS_PACRL_WP3_SHIFT (17U) +#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) +#define AIPS_PACRL_SP3_MASK (0x40000U) +#define AIPS_PACRL_SP3_SHIFT (18U) +#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) +#define AIPS_PACRL_TP2_MASK (0x100000U) +#define AIPS_PACRL_TP2_SHIFT (20U) +#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) +#define AIPS_PACRL_WP2_MASK (0x200000U) +#define AIPS_PACRL_WP2_SHIFT (21U) +#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) +#define AIPS_PACRL_SP2_MASK (0x400000U) +#define AIPS_PACRL_SP2_SHIFT (22U) +#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) +#define AIPS_PACRL_TP1_MASK (0x1000000U) +#define AIPS_PACRL_TP1_SHIFT (24U) +#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) +#define AIPS_PACRL_WP1_MASK (0x2000000U) +#define AIPS_PACRL_WP1_SHIFT (25U) +#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) +#define AIPS_PACRL_SP1_MASK (0x4000000U) +#define AIPS_PACRL_SP1_SHIFT (26U) +#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) +#define AIPS_PACRL_TP0_MASK (0x10000000U) +#define AIPS_PACRL_TP0_SHIFT (28U) +#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) +#define AIPS_PACRL_WP0_MASK (0x20000000U) +#define AIPS_PACRL_WP0_SHIFT (29U) +#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) +#define AIPS_PACRL_SP0_MASK (0x40000000U) +#define AIPS_PACRL_SP0_SHIFT (30U) +#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) + +/*! @name PACRM - Peripheral Access Control Register */ +#define AIPS_PACRM_TP7_MASK (0x1U) +#define AIPS_PACRM_TP7_SHIFT (0U) +#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) +#define AIPS_PACRM_WP7_MASK (0x2U) +#define AIPS_PACRM_WP7_SHIFT (1U) +#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) +#define AIPS_PACRM_SP7_MASK (0x4U) +#define AIPS_PACRM_SP7_SHIFT (2U) +#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) +#define AIPS_PACRM_TP6_MASK (0x10U) +#define AIPS_PACRM_TP6_SHIFT (4U) +#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) +#define AIPS_PACRM_WP6_MASK (0x20U) +#define AIPS_PACRM_WP6_SHIFT (5U) +#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) +#define AIPS_PACRM_SP6_MASK (0x40U) +#define AIPS_PACRM_SP6_SHIFT (6U) +#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) +#define AIPS_PACRM_TP5_MASK (0x100U) +#define AIPS_PACRM_TP5_SHIFT (8U) +#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) +#define AIPS_PACRM_WP5_MASK (0x200U) +#define AIPS_PACRM_WP5_SHIFT (9U) +#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) +#define AIPS_PACRM_SP5_MASK (0x400U) +#define AIPS_PACRM_SP5_SHIFT (10U) +#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) +#define AIPS_PACRM_TP4_MASK (0x1000U) +#define AIPS_PACRM_TP4_SHIFT (12U) +#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) +#define AIPS_PACRM_WP4_MASK (0x2000U) +#define AIPS_PACRM_WP4_SHIFT (13U) +#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) +#define AIPS_PACRM_SP4_MASK (0x4000U) +#define AIPS_PACRM_SP4_SHIFT (14U) +#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) +#define AIPS_PACRM_TP3_MASK (0x10000U) +#define AIPS_PACRM_TP3_SHIFT (16U) +#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) +#define AIPS_PACRM_WP3_MASK (0x20000U) +#define AIPS_PACRM_WP3_SHIFT (17U) +#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) +#define AIPS_PACRM_SP3_MASK (0x40000U) +#define AIPS_PACRM_SP3_SHIFT (18U) +#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) +#define AIPS_PACRM_TP2_MASK (0x100000U) +#define AIPS_PACRM_TP2_SHIFT (20U) +#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) +#define AIPS_PACRM_WP2_MASK (0x200000U) +#define AIPS_PACRM_WP2_SHIFT (21U) +#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) +#define AIPS_PACRM_SP2_MASK (0x400000U) +#define AIPS_PACRM_SP2_SHIFT (22U) +#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) +#define AIPS_PACRM_TP1_MASK (0x1000000U) +#define AIPS_PACRM_TP1_SHIFT (24U) +#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) +#define AIPS_PACRM_WP1_MASK (0x2000000U) +#define AIPS_PACRM_WP1_SHIFT (25U) +#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) +#define AIPS_PACRM_SP1_MASK (0x4000000U) +#define AIPS_PACRM_SP1_SHIFT (26U) +#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) +#define AIPS_PACRM_TP0_MASK (0x10000000U) +#define AIPS_PACRM_TP0_SHIFT (28U) +#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) +#define AIPS_PACRM_WP0_MASK (0x20000000U) +#define AIPS_PACRM_WP0_SHIFT (29U) +#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) +#define AIPS_PACRM_SP0_MASK (0x40000000U) +#define AIPS_PACRM_SP0_SHIFT (30U) +#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) + +/*! @name PACRN - Peripheral Access Control Register */ +#define AIPS_PACRN_TP7_MASK (0x1U) +#define AIPS_PACRN_TP7_SHIFT (0U) +#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) +#define AIPS_PACRN_WP7_MASK (0x2U) +#define AIPS_PACRN_WP7_SHIFT (1U) +#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) +#define AIPS_PACRN_SP7_MASK (0x4U) +#define AIPS_PACRN_SP7_SHIFT (2U) +#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) +#define AIPS_PACRN_TP6_MASK (0x10U) +#define AIPS_PACRN_TP6_SHIFT (4U) +#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) +#define AIPS_PACRN_WP6_MASK (0x20U) +#define AIPS_PACRN_WP6_SHIFT (5U) +#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) +#define AIPS_PACRN_SP6_MASK (0x40U) +#define AIPS_PACRN_SP6_SHIFT (6U) +#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) +#define AIPS_PACRN_TP5_MASK (0x100U) +#define AIPS_PACRN_TP5_SHIFT (8U) +#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) +#define AIPS_PACRN_WP5_MASK (0x200U) +#define AIPS_PACRN_WP5_SHIFT (9U) +#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) +#define AIPS_PACRN_SP5_MASK (0x400U) +#define AIPS_PACRN_SP5_SHIFT (10U) +#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) +#define AIPS_PACRN_TP4_MASK (0x1000U) +#define AIPS_PACRN_TP4_SHIFT (12U) +#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) +#define AIPS_PACRN_WP4_MASK (0x2000U) +#define AIPS_PACRN_WP4_SHIFT (13U) +#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) +#define AIPS_PACRN_SP4_MASK (0x4000U) +#define AIPS_PACRN_SP4_SHIFT (14U) +#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) +#define AIPS_PACRN_TP3_MASK (0x10000U) +#define AIPS_PACRN_TP3_SHIFT (16U) +#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) +#define AIPS_PACRN_WP3_MASK (0x20000U) +#define AIPS_PACRN_WP3_SHIFT (17U) +#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) +#define AIPS_PACRN_SP3_MASK (0x40000U) +#define AIPS_PACRN_SP3_SHIFT (18U) +#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) +#define AIPS_PACRN_TP2_MASK (0x100000U) +#define AIPS_PACRN_TP2_SHIFT (20U) +#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) +#define AIPS_PACRN_WP2_MASK (0x200000U) +#define AIPS_PACRN_WP2_SHIFT (21U) +#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) +#define AIPS_PACRN_SP2_MASK (0x400000U) +#define AIPS_PACRN_SP2_SHIFT (22U) +#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) +#define AIPS_PACRN_TP1_MASK (0x1000000U) +#define AIPS_PACRN_TP1_SHIFT (24U) +#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) +#define AIPS_PACRN_WP1_MASK (0x2000000U) +#define AIPS_PACRN_WP1_SHIFT (25U) +#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) +#define AIPS_PACRN_SP1_MASK (0x4000000U) +#define AIPS_PACRN_SP1_SHIFT (26U) +#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) +#define AIPS_PACRN_TP0_MASK (0x10000000U) +#define AIPS_PACRN_TP0_SHIFT (28U) +#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) +#define AIPS_PACRN_WP0_MASK (0x20000000U) +#define AIPS_PACRN_WP0_SHIFT (29U) +#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) +#define AIPS_PACRN_SP0_MASK (0x40000000U) +#define AIPS_PACRN_SP0_SHIFT (30U) +#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) + +/*! @name PACRO - Peripheral Access Control Register */ +#define AIPS_PACRO_TP7_MASK (0x1U) +#define AIPS_PACRO_TP7_SHIFT (0U) +#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) +#define AIPS_PACRO_WP7_MASK (0x2U) +#define AIPS_PACRO_WP7_SHIFT (1U) +#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) +#define AIPS_PACRO_SP7_MASK (0x4U) +#define AIPS_PACRO_SP7_SHIFT (2U) +#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) +#define AIPS_PACRO_TP6_MASK (0x10U) +#define AIPS_PACRO_TP6_SHIFT (4U) +#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) +#define AIPS_PACRO_WP6_MASK (0x20U) +#define AIPS_PACRO_WP6_SHIFT (5U) +#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) +#define AIPS_PACRO_SP6_MASK (0x40U) +#define AIPS_PACRO_SP6_SHIFT (6U) +#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) +#define AIPS_PACRO_TP5_MASK (0x100U) +#define AIPS_PACRO_TP5_SHIFT (8U) +#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) +#define AIPS_PACRO_WP5_MASK (0x200U) +#define AIPS_PACRO_WP5_SHIFT (9U) +#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) +#define AIPS_PACRO_SP5_MASK (0x400U) +#define AIPS_PACRO_SP5_SHIFT (10U) +#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) +#define AIPS_PACRO_TP4_MASK (0x1000U) +#define AIPS_PACRO_TP4_SHIFT (12U) +#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) +#define AIPS_PACRO_WP4_MASK (0x2000U) +#define AIPS_PACRO_WP4_SHIFT (13U) +#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) +#define AIPS_PACRO_SP4_MASK (0x4000U) +#define AIPS_PACRO_SP4_SHIFT (14U) +#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) +#define AIPS_PACRO_TP3_MASK (0x10000U) +#define AIPS_PACRO_TP3_SHIFT (16U) +#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) +#define AIPS_PACRO_WP3_MASK (0x20000U) +#define AIPS_PACRO_WP3_SHIFT (17U) +#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) +#define AIPS_PACRO_SP3_MASK (0x40000U) +#define AIPS_PACRO_SP3_SHIFT (18U) +#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) +#define AIPS_PACRO_TP2_MASK (0x100000U) +#define AIPS_PACRO_TP2_SHIFT (20U) +#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) +#define AIPS_PACRO_WP2_MASK (0x200000U) +#define AIPS_PACRO_WP2_SHIFT (21U) +#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) +#define AIPS_PACRO_SP2_MASK (0x400000U) +#define AIPS_PACRO_SP2_SHIFT (22U) +#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) +#define AIPS_PACRO_TP1_MASK (0x1000000U) +#define AIPS_PACRO_TP1_SHIFT (24U) +#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) +#define AIPS_PACRO_WP1_MASK (0x2000000U) +#define AIPS_PACRO_WP1_SHIFT (25U) +#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) +#define AIPS_PACRO_SP1_MASK (0x4000000U) +#define AIPS_PACRO_SP1_SHIFT (26U) +#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) +#define AIPS_PACRO_TP0_MASK (0x10000000U) +#define AIPS_PACRO_TP0_SHIFT (28U) +#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) +#define AIPS_PACRO_WP0_MASK (0x20000000U) +#define AIPS_PACRO_WP0_SHIFT (29U) +#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) +#define AIPS_PACRO_SP0_MASK (0x40000000U) +#define AIPS_PACRO_SP0_SHIFT (30U) +#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) + +/*! @name PACRP - Peripheral Access Control Register */ +#define AIPS_PACRP_TP7_MASK (0x1U) +#define AIPS_PACRP_TP7_SHIFT (0U) +#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) +#define AIPS_PACRP_WP7_MASK (0x2U) +#define AIPS_PACRP_WP7_SHIFT (1U) +#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) +#define AIPS_PACRP_SP7_MASK (0x4U) +#define AIPS_PACRP_SP7_SHIFT (2U) +#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) +#define AIPS_PACRP_TP6_MASK (0x10U) +#define AIPS_PACRP_TP6_SHIFT (4U) +#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) +#define AIPS_PACRP_WP6_MASK (0x20U) +#define AIPS_PACRP_WP6_SHIFT (5U) +#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) +#define AIPS_PACRP_SP6_MASK (0x40U) +#define AIPS_PACRP_SP6_SHIFT (6U) +#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) +#define AIPS_PACRP_TP5_MASK (0x100U) +#define AIPS_PACRP_TP5_SHIFT (8U) +#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) +#define AIPS_PACRP_WP5_MASK (0x200U) +#define AIPS_PACRP_WP5_SHIFT (9U) +#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) +#define AIPS_PACRP_SP5_MASK (0x400U) +#define AIPS_PACRP_SP5_SHIFT (10U) +#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) +#define AIPS_PACRP_TP4_MASK (0x1000U) +#define AIPS_PACRP_TP4_SHIFT (12U) +#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) +#define AIPS_PACRP_WP4_MASK (0x2000U) +#define AIPS_PACRP_WP4_SHIFT (13U) +#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) +#define AIPS_PACRP_SP4_MASK (0x4000U) +#define AIPS_PACRP_SP4_SHIFT (14U) +#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) +#define AIPS_PACRP_TP3_MASK (0x10000U) +#define AIPS_PACRP_TP3_SHIFT (16U) +#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) +#define AIPS_PACRP_WP3_MASK (0x20000U) +#define AIPS_PACRP_WP3_SHIFT (17U) +#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) +#define AIPS_PACRP_SP3_MASK (0x40000U) +#define AIPS_PACRP_SP3_SHIFT (18U) +#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) +#define AIPS_PACRP_TP2_MASK (0x100000U) +#define AIPS_PACRP_TP2_SHIFT (20U) +#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) +#define AIPS_PACRP_WP2_MASK (0x200000U) +#define AIPS_PACRP_WP2_SHIFT (21U) +#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) +#define AIPS_PACRP_SP2_MASK (0x400000U) +#define AIPS_PACRP_SP2_SHIFT (22U) +#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) +#define AIPS_PACRP_TP1_MASK (0x1000000U) +#define AIPS_PACRP_TP1_SHIFT (24U) +#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) +#define AIPS_PACRP_WP1_MASK (0x2000000U) +#define AIPS_PACRP_WP1_SHIFT (25U) +#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) +#define AIPS_PACRP_SP1_MASK (0x4000000U) +#define AIPS_PACRP_SP1_SHIFT (26U) +#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) +#define AIPS_PACRP_TP0_MASK (0x10000000U) +#define AIPS_PACRP_TP0_SHIFT (28U) +#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) +#define AIPS_PACRP_WP0_MASK (0x20000000U) +#define AIPS_PACRP_WP0_SHIFT (29U) +#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) +#define AIPS_PACRP_SP0_MASK (0x40000000U) +#define AIPS_PACRP_SP0_SHIFT (30U) +#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) + +/*! @name PACRU - Peripheral Access Control Register */ +#define AIPS_PACRU_TP1_MASK (0x1000000U) +#define AIPS_PACRU_TP1_SHIFT (24U) +#define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK) +#define AIPS_PACRU_WP1_MASK (0x2000000U) +#define AIPS_PACRU_WP1_SHIFT (25U) +#define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK) +#define AIPS_PACRU_SP1_MASK (0x4000000U) +#define AIPS_PACRU_SP1_SHIFT (26U) +#define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK) +#define AIPS_PACRU_TP0_MASK (0x10000000U) +#define AIPS_PACRU_TP0_SHIFT (28U) +#define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK) +#define AIPS_PACRU_WP0_MASK (0x20000000U) +#define AIPS_PACRU_WP0_SHIFT (29U) +#define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK) +#define AIPS_PACRU_SP0_MASK (0x40000000U) +#define AIPS_PACRU_SP0_SHIFT (30U) +#define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK) + + +/*! + * @} + */ /* end of group AIPS_Register_Masks */ + + +/* AIPS - Peripheral instance base addresses */ +/** Peripheral AIPS0 base address */ +#define AIPS0_BASE (0x40000000u) +/** Peripheral AIPS0 base pointer */ +#define AIPS0 ((AIPS_Type *)AIPS0_BASE) +/** Peripheral AIPS1 base address */ +#define AIPS1_BASE (0x40080000u) +/** Peripheral AIPS1 base pointer */ +#define AIPS1 ((AIPS_Type *)AIPS1_BASE) +/** Array initializer of AIPS peripheral base addresses */ +#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } +/** Array initializer of AIPS peripheral base pointers */ +#define AIPS_BASE_PTRS { AIPS0, AIPS1 } + +/*! + * @} + */ /* end of group AIPS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer + * @{ + */ + +/** AXBS - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_1[236]; + } SLAVE[5]; + uint8_t RESERVED_0[768]; + __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8_t RESERVED_1[252]; + __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8_t RESERVED_2[252]; + __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8_t RESERVED_3[252]; + __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ + uint8_t RESERVED_4[252]; + __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8_t RESERVED_5[252]; + __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ +} AXBS_Type; + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/*! @name PRS - Priority Registers Slave */ +#define AXBS_PRS_M0_MASK (0x7U) +#define AXBS_PRS_M0_SHIFT (0U) +#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) +#define AXBS_PRS_M1_MASK (0x70U) +#define AXBS_PRS_M1_SHIFT (4U) +#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) +#define AXBS_PRS_M2_MASK (0x700U) +#define AXBS_PRS_M2_SHIFT (8U) +#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) +#define AXBS_PRS_M3_MASK (0x7000U) +#define AXBS_PRS_M3_SHIFT (12U) +#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) +#define AXBS_PRS_M4_MASK (0x70000U) +#define AXBS_PRS_M4_SHIFT (16U) +#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) +#define AXBS_PRS_M5_MASK (0x700000U) +#define AXBS_PRS_M5_SHIFT (20U) +#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) + +/* The count of AXBS_PRS */ +#define AXBS_PRS_COUNT (5U) + +/*! @name CRS - Control Register */ +#define AXBS_CRS_PARK_MASK (0x7U) +#define AXBS_CRS_PARK_SHIFT (0U) +#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) +#define AXBS_CRS_PCTL_MASK (0x30U) +#define AXBS_CRS_PCTL_SHIFT (4U) +#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) +#define AXBS_CRS_ARB_MASK (0x300U) +#define AXBS_CRS_ARB_SHIFT (8U) +#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) +#define AXBS_CRS_HLP_MASK (0x40000000U) +#define AXBS_CRS_HLP_SHIFT (30U) +#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) +#define AXBS_CRS_RO_MASK (0x80000000U) +#define AXBS_CRS_RO_SHIFT (31U) +#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) + +/* The count of AXBS_CRS */ +#define AXBS_CRS_COUNT (5U) + +/*! @name MGPCR0 - Master General Purpose Control Register */ +#define AXBS_MGPCR0_AULB_MASK (0x7U) +#define AXBS_MGPCR0_AULB_SHIFT (0U) +#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) + +/*! @name MGPCR1 - Master General Purpose Control Register */ +#define AXBS_MGPCR1_AULB_MASK (0x7U) +#define AXBS_MGPCR1_AULB_SHIFT (0U) +#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) + +/*! @name MGPCR2 - Master General Purpose Control Register */ +#define AXBS_MGPCR2_AULB_MASK (0x7U) +#define AXBS_MGPCR2_AULB_SHIFT (0U) +#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) + +/*! @name MGPCR3 - Master General Purpose Control Register */ +#define AXBS_MGPCR3_AULB_MASK (0x7U) +#define AXBS_MGPCR3_AULB_SHIFT (0U) +#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) + +/*! @name MGPCR4 - Master General Purpose Control Register */ +#define AXBS_MGPCR4_AULB_MASK (0x7U) +#define AXBS_MGPCR4_AULB_SHIFT (0U) +#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) + +/*! @name MGPCR5 - Master General Purpose Control Register */ +#define AXBS_MGPCR5_AULB_MASK (0x7U) +#define AXBS_MGPCR5_AULB_SHIFT (0U) +#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) + + +/*! + * @} + */ /* end of group AXBS_Register_Masks */ + + +/* AXBS - Peripheral instance base addresses */ +/** Peripheral AXBS base address */ +#define AXBS_BASE (0x40004000u) +/** Peripheral AXBS base pointer */ +#define AXBS ((AXBS_Type *)AXBS_BASE) +/** Array initializer of AXBS peripheral base addresses */ +#define AXBS_BASE_ADDRS { AXBS_BASE } +/** Array initializer of AXBS peripheral base pointers */ +#define AXBS_BASE_PTRS { AXBS } + +/*! + * @} + */ /* end of group AXBS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_4[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[16]; + uint8_t RESERVED_5[1792]; + __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) + +/*! @name CTRL1 - Control 1 register */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_CLKSRC_MASK (0x2000U) +#define CAN_CTRL1_CLKSRC_SHIFT (13U) +#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/*! @name TIMER - Free Running Timer */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) + +/*! @name RX14MASK - Rx 14 Mask register */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) + +/*! @name RX15MASK - Rx 15 Mask register */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) + +/*! @name ECR - Error Counter */ +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +/*! @name ESR1 - Error and Status 1 register */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +/*! @name IMASK1 - Interrupt Masks 1 register */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) + +/*! @name IFLAG1 - Interrupt Flags 1 register */ +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) + +/*! @name CTRL2 - Control 2 register */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +/*! @name ESR2 - Error and Status 2 register */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) + +/*! @name CRCR - CRC Register */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) + +/*! @name RXFGMASK - Rx FIFO Global Mask register */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) + +/*! @name RXFIR - Rx FIFO Information Register */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (16U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (16U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (16U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (16U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (16U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x40024000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn } +#define CAN_Error_IRQS { CAN0_Error_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer + * @{ + */ + +/** CAU - Register Layout Typedef */ +typedef struct { + __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[2048]; + __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ + __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ + __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ + uint8_t RESERVED_1[20]; + __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ + __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ + __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ + uint8_t RESERVED_2[20]; + __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ + __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ + __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ + uint8_t RESERVED_3[20]; + __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ + __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ + __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ + uint8_t RESERVED_4[84]; + __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ + __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ + __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ + __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ + __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ + uint8_t RESERVED_6[276]; + __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ + __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ + __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ + uint8_t RESERVED_7[20]; + __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ + __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ + __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ +} CAU_Type; + +/* ---------------------------------------------------------------------------- + -- CAU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAU_Register_Masks CAU Register Masks + * @{ + */ + +/*! @name DIRECT - Direct access register 0..Direct access register 15 */ +#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) +#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) +#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) +#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) +#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) +#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) +#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) +#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) +#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) +#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) +#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) +#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) +#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) +#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) +#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) +#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) + +/* The count of CAU_DIRECT */ +#define CAU_DIRECT_COUNT (16U) + +/*! @name LDR_CASR - Status register - Load Register command */ +#define CAU_LDR_CASR_IC_MASK (0x1U) +#define CAU_LDR_CASR_IC_SHIFT (0U) +#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) +#define CAU_LDR_CASR_DPE_MASK (0x2U) +#define CAU_LDR_CASR_DPE_SHIFT (1U) +#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) +#define CAU_LDR_CASR_VER_MASK (0xF0000000U) +#define CAU_LDR_CASR_VER_SHIFT (28U) +#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) + +/*! @name LDR_CAA - Accumulator register - Load Register command */ +#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_LDR_CAA_ACC_SHIFT (0U) +#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) + +/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ +#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA0_SHIFT (0U) +#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) +#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA1_SHIFT (0U) +#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) +#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA2_SHIFT (0U) +#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) +#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA3_SHIFT (0U) +#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) +#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA4_SHIFT (0U) +#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) +#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA5_SHIFT (0U) +#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) +#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA6_SHIFT (0U) +#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) +#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA7_SHIFT (0U) +#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) +#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA8_SHIFT (0U) +#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) + +/* The count of CAU_LDR_CA */ +#define CAU_LDR_CA_COUNT (9U) + +/*! @name STR_CASR - Status register - Store Register command */ +#define CAU_STR_CASR_IC_MASK (0x1U) +#define CAU_STR_CASR_IC_SHIFT (0U) +#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) +#define CAU_STR_CASR_DPE_MASK (0x2U) +#define CAU_STR_CASR_DPE_SHIFT (1U) +#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) +#define CAU_STR_CASR_VER_MASK (0xF0000000U) +#define CAU_STR_CASR_VER_SHIFT (28U) +#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) + +/*! @name STR_CAA - Accumulator register - Store Register command */ +#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_STR_CAA_ACC_SHIFT (0U) +#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) + +/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ +#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA0_SHIFT (0U) +#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) +#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA1_SHIFT (0U) +#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) +#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA2_SHIFT (0U) +#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) +#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA3_SHIFT (0U) +#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) +#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA4_SHIFT (0U) +#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) +#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA5_SHIFT (0U) +#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) +#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA6_SHIFT (0U) +#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) +#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA7_SHIFT (0U) +#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) +#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA8_SHIFT (0U) +#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) + +/* The count of CAU_STR_CA */ +#define CAU_STR_CA_COUNT (9U) + +/*! @name ADR_CASR - Status register - Add Register command */ +#define CAU_ADR_CASR_IC_MASK (0x1U) +#define CAU_ADR_CASR_IC_SHIFT (0U) +#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) +#define CAU_ADR_CASR_DPE_MASK (0x2U) +#define CAU_ADR_CASR_DPE_SHIFT (1U) +#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) +#define CAU_ADR_CASR_VER_MASK (0xF0000000U) +#define CAU_ADR_CASR_VER_SHIFT (28U) +#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) + +/*! @name ADR_CAA - Accumulator register - Add to register command */ +#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_ADR_CAA_ACC_SHIFT (0U) +#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) + +/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ +#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA0_SHIFT (0U) +#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) +#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA1_SHIFT (0U) +#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) +#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA2_SHIFT (0U) +#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) +#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA3_SHIFT (0U) +#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) +#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA4_SHIFT (0U) +#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) +#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA5_SHIFT (0U) +#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) +#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA6_SHIFT (0U) +#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) +#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA7_SHIFT (0U) +#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) +#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA8_SHIFT (0U) +#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) + +/* The count of CAU_ADR_CA */ +#define CAU_ADR_CA_COUNT (9U) + +/*! @name RADR_CASR - Status register - Reverse and Add to Register command */ +#define CAU_RADR_CASR_IC_MASK (0x1U) +#define CAU_RADR_CASR_IC_SHIFT (0U) +#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) +#define CAU_RADR_CASR_DPE_MASK (0x2U) +#define CAU_RADR_CASR_DPE_SHIFT (1U) +#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) +#define CAU_RADR_CASR_VER_MASK (0xF0000000U) +#define CAU_RADR_CASR_VER_SHIFT (28U) +#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) + +/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ +#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_RADR_CAA_ACC_SHIFT (0U) +#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) + +/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ +#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA0_SHIFT (0U) +#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) +#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA1_SHIFT (0U) +#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) +#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA2_SHIFT (0U) +#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) +#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA3_SHIFT (0U) +#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) +#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA4_SHIFT (0U) +#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) +#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA5_SHIFT (0U) +#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) +#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA6_SHIFT (0U) +#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) +#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA7_SHIFT (0U) +#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) +#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA8_SHIFT (0U) +#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) + +/* The count of CAU_RADR_CA */ +#define CAU_RADR_CA_COUNT (9U) + +/*! @name XOR_CASR - Status register - Exclusive Or command */ +#define CAU_XOR_CASR_IC_MASK (0x1U) +#define CAU_XOR_CASR_IC_SHIFT (0U) +#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) +#define CAU_XOR_CASR_DPE_MASK (0x2U) +#define CAU_XOR_CASR_DPE_SHIFT (1U) +#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) +#define CAU_XOR_CASR_VER_MASK (0xF0000000U) +#define CAU_XOR_CASR_VER_SHIFT (28U) +#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) + +/*! @name XOR_CAA - Accumulator register - Exclusive Or command */ +#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_XOR_CAA_ACC_SHIFT (0U) +#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) + +/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ +#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA0_SHIFT (0U) +#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) +#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA1_SHIFT (0U) +#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) +#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA2_SHIFT (0U) +#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) +#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA3_SHIFT (0U) +#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) +#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA4_SHIFT (0U) +#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) +#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA5_SHIFT (0U) +#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) +#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA6_SHIFT (0U) +#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) +#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA7_SHIFT (0U) +#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) +#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA8_SHIFT (0U) +#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) + +/* The count of CAU_XOR_CA */ +#define CAU_XOR_CA_COUNT (9U) + +/*! @name ROTL_CASR - Status register - Rotate Left command */ +#define CAU_ROTL_CASR_IC_MASK (0x1U) +#define CAU_ROTL_CASR_IC_SHIFT (0U) +#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) +#define CAU_ROTL_CASR_DPE_MASK (0x2U) +#define CAU_ROTL_CASR_DPE_SHIFT (1U) +#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) +#define CAU_ROTL_CASR_VER_MASK (0xF0000000U) +#define CAU_ROTL_CASR_VER_SHIFT (28U) +#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) + +/*! @name ROTL_CAA - Accumulator register - Rotate Left command */ +#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CAA_ACC_SHIFT (0U) +#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) + +/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ +#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA0_SHIFT (0U) +#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) +#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA1_SHIFT (0U) +#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) +#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA2_SHIFT (0U) +#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) +#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA3_SHIFT (0U) +#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) +#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA4_SHIFT (0U) +#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) +#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA5_SHIFT (0U) +#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) +#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA6_SHIFT (0U) +#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) +#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA7_SHIFT (0U) +#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) +#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA8_SHIFT (0U) +#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) + +/* The count of CAU_ROTL_CA */ +#define CAU_ROTL_CA_COUNT (9U) + +/*! @name AESC_CASR - Status register - AES Column Operation command */ +#define CAU_AESC_CASR_IC_MASK (0x1U) +#define CAU_AESC_CASR_IC_SHIFT (0U) +#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) +#define CAU_AESC_CASR_DPE_MASK (0x2U) +#define CAU_AESC_CASR_DPE_SHIFT (1U) +#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) +#define CAU_AESC_CASR_VER_MASK (0xF0000000U) +#define CAU_AESC_CASR_VER_SHIFT (28U) +#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) + +/*! @name AESC_CAA - Accumulator register - AES Column Operation command */ +#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_AESC_CAA_ACC_SHIFT (0U) +#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) + +/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ +#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA0_SHIFT (0U) +#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) +#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA1_SHIFT (0U) +#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) +#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA2_SHIFT (0U) +#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) +#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA3_SHIFT (0U) +#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) +#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA4_SHIFT (0U) +#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) +#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA5_SHIFT (0U) +#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) +#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA6_SHIFT (0U) +#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) +#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA7_SHIFT (0U) +#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) +#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA8_SHIFT (0U) +#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) + +/* The count of CAU_AESC_CA */ +#define CAU_AESC_CA_COUNT (9U) + +/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ +#define CAU_AESIC_CASR_IC_MASK (0x1U) +#define CAU_AESIC_CASR_IC_SHIFT (0U) +#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) +#define CAU_AESIC_CASR_DPE_MASK (0x2U) +#define CAU_AESIC_CASR_DPE_SHIFT (1U) +#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) +#define CAU_AESIC_CASR_VER_MASK (0xF0000000U) +#define CAU_AESIC_CASR_VER_SHIFT (28U) +#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) + +/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ +#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CAA_ACC_SHIFT (0U) +#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) + +/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ +#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA0_SHIFT (0U) +#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) +#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA1_SHIFT (0U) +#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) +#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA2_SHIFT (0U) +#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) +#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA3_SHIFT (0U) +#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) +#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA4_SHIFT (0U) +#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) +#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA5_SHIFT (0U) +#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) +#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA6_SHIFT (0U) +#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) +#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA7_SHIFT (0U) +#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) +#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA8_SHIFT (0U) +#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) + +/* The count of CAU_AESIC_CA */ +#define CAU_AESIC_CA_COUNT (9U) + + +/*! + * @} + */ /* end of group CAU_Register_Masks */ + + +/* CAU - Peripheral instance base addresses */ +/** Peripheral CAU base address */ +#define CAU_BASE (0xE0081000u) +/** Peripheral CAU base pointer */ +#define CAU ((CAU_Type *)CAU_BASE) +/** Array initializer of CAU peripheral base addresses */ +#define CAU_BASE_ADDRS { CAU_BASE } +/** Array initializer of CAU peripheral base pointers */ +#define CAU_BASE_PTRS { CAU } + +/*! + * @} + */ /* end of group CAU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) + +/*! @name CR1 - CMP Control Register 1 */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) + +/*! @name FPR - CMP Filter Period Register */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) + +/*! @name SCR - CMP Status and Control Register */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) + +/*! @name DACCR - DAC Control Register */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) + +/*! @name MUXCR - MUX Control Register */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +#define CMP_MUXCR_PSTM_MASK (0x80U) +#define CMP_MUXCR_PSTM_SHIFT (7U) +#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40073008u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x40073010u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { CMP0, CMP1, CMP2 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer + * @{ + */ + +/** CMT - Register Layout Typedef */ +typedef struct { + __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ + __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ + __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ + __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ + __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ + __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ + __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ + __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ + __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ + __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ + __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ + __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ +} CMT_Type; + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ +#define CMT_CGH1_PH_MASK (0xFFU) +#define CMT_CGH1_PH_SHIFT (0U) +#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) + +/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ +#define CMT_CGL1_PL_MASK (0xFFU) +#define CMT_CGL1_PL_SHIFT (0U) +#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) + +/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ +#define CMT_CGH2_SH_MASK (0xFFU) +#define CMT_CGH2_SH_SHIFT (0U) +#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) + +/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ +#define CMT_CGL2_SL_MASK (0xFFU) +#define CMT_CGL2_SL_SHIFT (0U) +#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) + +/*! @name OC - CMT Output Control Register */ +#define CMT_OC_IROPEN_MASK (0x20U) +#define CMT_OC_IROPEN_SHIFT (5U) +#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) +#define CMT_OC_CMTPOL_MASK (0x40U) +#define CMT_OC_CMTPOL_SHIFT (6U) +#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) +#define CMT_OC_IROL_MASK (0x80U) +#define CMT_OC_IROL_SHIFT (7U) +#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) + +/*! @name MSC - CMT Modulator Status and Control Register */ +#define CMT_MSC_MCGEN_MASK (0x1U) +#define CMT_MSC_MCGEN_SHIFT (0U) +#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) +#define CMT_MSC_EOCIE_MASK (0x2U) +#define CMT_MSC_EOCIE_SHIFT (1U) +#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) +#define CMT_MSC_FSK_MASK (0x4U) +#define CMT_MSC_FSK_SHIFT (2U) +#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) +#define CMT_MSC_BASE_MASK (0x8U) +#define CMT_MSC_BASE_SHIFT (3U) +#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) +#define CMT_MSC_EXSPC_MASK (0x10U) +#define CMT_MSC_EXSPC_SHIFT (4U) +#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) +#define CMT_MSC_CMTDIV_MASK (0x60U) +#define CMT_MSC_CMTDIV_SHIFT (5U) +#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) +#define CMT_MSC_EOCF_MASK (0x80U) +#define CMT_MSC_EOCF_SHIFT (7U) +#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) + +/*! @name CMD1 - CMT Modulator Data Register Mark High */ +#define CMT_CMD1_MB_MASK (0xFFU) +#define CMT_CMD1_MB_SHIFT (0U) +#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) + +/*! @name CMD2 - CMT Modulator Data Register Mark Low */ +#define CMT_CMD2_MB_MASK (0xFFU) +#define CMT_CMD2_MB_SHIFT (0U) +#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) + +/*! @name CMD3 - CMT Modulator Data Register Space High */ +#define CMT_CMD3_SB_MASK (0xFFU) +#define CMT_CMD3_SB_SHIFT (0U) +#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) + +/*! @name CMD4 - CMT Modulator Data Register Space Low */ +#define CMT_CMD4_SB_MASK (0xFFU) +#define CMT_CMD4_SB_SHIFT (0U) +#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) + +/*! @name PPS - CMT Primary Prescaler Register */ +#define CMT_PPS_PPSDIV_MASK (0xFU) +#define CMT_PPS_PPSDIV_SHIFT (0U) +#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) + +/*! @name DMA - CMT Direct Memory Access Register */ +#define CMT_DMA_DMA_MASK (0x1U) +#define CMT_DMA_DMA_SHIFT (0U) +#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) + + +/*! + * @} + */ /* end of group CMT_Register_Masks */ + + +/* CMT - Peripheral instance base addresses */ +/** Peripheral CMT base address */ +#define CMT_BASE (0x40062000u) +/** Peripheral CMT base pointer */ +#define CMT ((CMT_Type *)CMT_BASE) +/** Array initializer of CMT peripheral base addresses */ +#define CMT_BASE_ADDRS { CMT_BASE } +/** Array initializer of CMT peripheral base pointers */ +#define CMT_BASE_PTRS { CMT } +/** Interrupt vectors for the CMT peripheral type */ +#define CMT_IRQS { CMT_IRQn } + +/*! + * @} + */ /* end of group CMT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ + } ACCESS8BIT; + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ + } GPOLY_ACCESS8BIT; + }; + union { /* offset: 0x8 */ + __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ + } CTRL_ACCESS8BIT; + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATAL - CRC_DATAL register. */ +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) + +/*! @name DATAH - CRC_DATAH register. */ +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) + +/*! @name DATA - CRC Data register */ +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) + +/*! @name DATALL - CRC_DATALL register. */ +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) + +/*! @name DATALU - CRC_DATALU register. */ +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) + +/*! @name DATAHL - CRC_DATAHL register. */ +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) + +/*! @name DATAHU - CRC_DATAHU register. */ +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) + +/*! @name GPOLYL - CRC_GPOLYL register. */ +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) + +/*! @name GPOLYH - CRC_GPOLYH register. */ +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) + +/*! @name GPOLY - CRC Polynomial register */ +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) + +/*! @name GPOLYLL - CRC_GPOLYLL register. */ +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) + +/*! @name GPOLYLU - CRC_GPOLYLU register. */ +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) + +/*! @name GPOLYHL - CRC_GPOLYHL register. */ +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) + +/*! @name GPOLYHU - CRC_GPOLYHU register. */ +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) + +/*! @name CTRL - CRC Control register */ +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) + +/*! @name CTRLHU - CRC_CTRLHU register. */ +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC base address */ +#define CRC_BASE (0x40032000u) +/** Peripheral CRC base pointer */ +#define CRC0 ((CRC_Type *)CRC_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/** DAC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x2 */ + __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[16]; + __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ + __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ + __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ + __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ +} DAC_Type; + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/*! @name DATL - DAC Data Low Register */ +#define DAC_DATL_DATA0_MASK (0xFFU) +#define DAC_DATL_DATA0_SHIFT (0U) +#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) + +/* The count of DAC_DATL */ +#define DAC_DATL_COUNT (16U) + +/*! @name DATH - DAC Data High Register */ +#define DAC_DATH_DATA1_MASK (0xFU) +#define DAC_DATH_DATA1_SHIFT (0U) +#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) + +/* The count of DAC_DATH */ +#define DAC_DATH_COUNT (16U) + +/*! @name SR - DAC Status Register */ +#define DAC_SR_DACBFRPBF_MASK (0x1U) +#define DAC_SR_DACBFRPBF_SHIFT (0U) +#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) +#define DAC_SR_DACBFRPTF_MASK (0x2U) +#define DAC_SR_DACBFRPTF_SHIFT (1U) +#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) +#define DAC_SR_DACBFWMF_MASK (0x4U) +#define DAC_SR_DACBFWMF_SHIFT (2U) +#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) + +/*! @name C0 - DAC Control Register */ +#define DAC_C0_DACBBIEN_MASK (0x1U) +#define DAC_C0_DACBBIEN_SHIFT (0U) +#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) +#define DAC_C0_DACBTIEN_MASK (0x2U) +#define DAC_C0_DACBTIEN_SHIFT (1U) +#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) +#define DAC_C0_DACBWIEN_MASK (0x4U) +#define DAC_C0_DACBWIEN_SHIFT (2U) +#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) +#define DAC_C0_LPEN_MASK (0x8U) +#define DAC_C0_LPEN_SHIFT (3U) +#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) +#define DAC_C0_DACSWTRG_MASK (0x10U) +#define DAC_C0_DACSWTRG_SHIFT (4U) +#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) +#define DAC_C0_DACTRGSEL_MASK (0x20U) +#define DAC_C0_DACTRGSEL_SHIFT (5U) +#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) +#define DAC_C0_DACRFS_MASK (0x40U) +#define DAC_C0_DACRFS_SHIFT (6U) +#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) +#define DAC_C0_DACEN_MASK (0x80U) +#define DAC_C0_DACEN_SHIFT (7U) +#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) + +/*! @name C1 - DAC Control Register 1 */ +#define DAC_C1_DACBFEN_MASK (0x1U) +#define DAC_C1_DACBFEN_SHIFT (0U) +#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) +#define DAC_C1_DACBFMD_MASK (0x6U) +#define DAC_C1_DACBFMD_SHIFT (1U) +#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) +#define DAC_C1_DACBFWM_MASK (0x18U) +#define DAC_C1_DACBFWM_SHIFT (3U) +#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) +#define DAC_C1_DMAEN_MASK (0x80U) +#define DAC_C1_DMAEN_SHIFT (7U) +#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) + +/*! @name C2 - DAC Control Register 2 */ +#define DAC_C2_DACBFUP_MASK (0xFU) +#define DAC_C2_DACBFUP_SHIFT (0U) +#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) +#define DAC_C2_DACBFRP_MASK (0xF0U) +#define DAC_C2_DACBFRP_SHIFT (4U) +#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) + + +/*! + * @} + */ /* end of group DAC_Register_Masks */ + + +/* DAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400CC000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((DAC_Type *)DAC0_BASE) +/** Peripheral DAC1 base address */ +#define DAC1_BASE (0x400CD000u) +/** Peripheral DAC1 base pointer */ +#define DAC1 ((DAC_Type *)DAC1_BASE) +/** Array initializer of DAC peripheral base addresses */ +#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } +/** Array initializer of DAC peripheral base pointers */ +#define DAC_BASE_PTRS { DAC0, DAC1 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/*! + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[200]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + uint8_t RESERVED_6[3824]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[16]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) + +/*! @name ES - Error Status Register */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0xF00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) + +/*! @name ERQ - Enable Request Register */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) + +/*! @name EEI - Enable Error Interrupt Register */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +#define DMA_CEEI_CEEI_MASK (0xFU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) + +/*! @name SEEI - Set Enable Error Interrupt Register */ +#define DMA_SEEI_SEEI_MASK (0xFU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) + +/*! @name CERQ - Clear Enable Request Register */ +#define DMA_CERQ_CERQ_MASK (0xFU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) + +/*! @name SERQ - Set Enable Request Register */ +#define DMA_SERQ_SERQ_MASK (0xFU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) + +/*! @name CDNE - Clear DONE Status Bit Register */ +#define DMA_CDNE_CDNE_MASK (0xFU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) + +/*! @name SSRT - Set START Bit Register */ +#define DMA_SSRT_SSRT_MASK (0xFU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) + +/*! @name CERR - Clear Error Register */ +#define DMA_CERR_CERR_MASK (0xFU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) + +/*! @name CINT - Clear Interrupt Request Register */ +#define DMA_CINT_CINT_MASK (0xFU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) + +/*! @name INT - Interrupt Request Register */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) + +/*! @name ERR - Error Register */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) + +/*! @name HRS - Hardware Request Status Register */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) + +/*! @name DCHPRI3 - Channel n Priority Register */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) + +/*! @name DCHPRI2 - Channel n Priority Register */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) + +/*! @name DCHPRI1 - Channel n Priority Register */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) + +/*! @name DCHPRI0 - Channel n Priority Register */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) + +/*! @name DCHPRI7 - Channel n Priority Register */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) + +/*! @name DCHPRI6 - Channel n Priority Register */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) + +/*! @name DCHPRI5 - Channel n Priority Register */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) + +/*! @name DCHPRI4 - Channel n Priority Register */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) + +/*! @name DCHPRI11 - Channel n Priority Register */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) + +/*! @name DCHPRI10 - Channel n Priority Register */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) + +/*! @name DCHPRI9 - Channel n Priority Register */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) + +/*! @name DCHPRI8 - Channel n Priority Register */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) + +/*! @name DCHPRI15 - Channel n Priority Register */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) + +/*! @name DCHPRI14 - Channel n Priority Register */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) + +/*! @name DCHPRI13 - Channel n Priority Register */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) + +/*! @name DCHPRI12 - Channel n Priority Register */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) + +/*! @name SADDR - TCD Source Address */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (16U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (16U) + +/*! @name ATTR - TCD Transfer Attributes */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (16U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (16U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (16U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (16U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (16U) + +/*! @name DADDR - TCD Destination Address */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (16U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (16U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (16U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (16U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (16U) + +/*! @name CSR - TCD Control and Status */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0xF00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (16U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (16U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (16U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base address */ +#define DMA_BASE (0x40008000u) +/** Peripheral DMA base pointer */ +#define DMA0 ((DMA_Type *)DMA_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } +#define DMA_ERROR_IRQS { DMA_Error_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel Configuration register */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40U) +#define DMAMUX_CHCFG_TRIG_SHIFT (6U) +#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80U) +#define DMAMUX_CHCFG_ENBL_SHIFT (7U) +#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (16U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x40021000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + uint8_t RESERVED_8[40]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_9[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_10[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_11[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_13[60]; + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint8_t RESERVED_14[4]; + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + uint8_t RESERVED_15[4]; + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_16[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint8_t RESERVED_17[4]; + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_18[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_19[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) + +/*! @name EIMR - Interrupt Mask Register */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) + +/*! @name RDAR - Receive Descriptor Active Register */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) + +/*! @name TDAR - Transmit Descriptor Active Register */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) + +/*! @name ECR - Ethernet Control Register */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_STOPEN_MASK (0x80U) +#define ENET_ECR_STOPEN_SHIFT (7U) +#define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +/*! @name MMFR - MII Management Frame Register */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) + +/*! @name MSCR - MII Speed Control Register */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) + +/*! @name MIBC - MIB Control Register */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) + +/*! @name RCR - Receive Control Register */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) + +/*! @name PALR - Physical Address Lower Register */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) + +/*! @name PAUR - Physical Address Upper Register */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) + +/*! @name OPD - Opcode/Pause Duration Register */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) + +/*! @name IALR - Descriptor Individual Lower Address Register */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) + +/*! @name GAUR - Descriptor Group Upper Address Register */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) + +/*! @name GALR - Descriptor Group Lower Address Register */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) + +/*! @name TFWR - Transmit FIFO Watermark Register */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) + +/*! @name TIPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) + +/*! @name FTRL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) + +/*! @name TACC - Transmit Accelerator Function Configuration */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) + +/*! @name RACC - Receive Accelerator Function Configuration */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Adjustable Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x400C0000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_Transmit_IRQn } +#define ENET_Receive_IRQS { ENET_Receive_IRQn } +#define ENET_Error_IRQS { ENET_Error_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) + +/*! @name SERV - Service Register */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) + +/*! @name CMPL - Compare Low Register */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) + +/*! @name CMPH - Compare High Register */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x40061000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { WDOG_EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer + * @{ + */ + +/** FB - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0xC */ + __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ + __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ + __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ + } CS[6]; + uint8_t RESERVED_0[24]; + __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */ +} FB_Type; + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/*! @name CSAR - Chip Select Address Register */ +#define FB_CSAR_BA_MASK (0xFFFF0000U) +#define FB_CSAR_BA_SHIFT (16U) +#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) + +/* The count of FB_CSAR */ +#define FB_CSAR_COUNT (6U) + +/*! @name CSMR - Chip Select Mask Register */ +#define FB_CSMR_V_MASK (0x1U) +#define FB_CSMR_V_SHIFT (0U) +#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) +#define FB_CSMR_WP_MASK (0x100U) +#define FB_CSMR_WP_SHIFT (8U) +#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) +#define FB_CSMR_BAM_MASK (0xFFFF0000U) +#define FB_CSMR_BAM_SHIFT (16U) +#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) + +/* The count of FB_CSMR */ +#define FB_CSMR_COUNT (6U) + +/*! @name CSCR - Chip Select Control Register */ +#define FB_CSCR_BSTW_MASK (0x8U) +#define FB_CSCR_BSTW_SHIFT (3U) +#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) +#define FB_CSCR_BSTR_MASK (0x10U) +#define FB_CSCR_BSTR_SHIFT (4U) +#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) +#define FB_CSCR_BEM_MASK (0x20U) +#define FB_CSCR_BEM_SHIFT (5U) +#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) +#define FB_CSCR_PS_MASK (0xC0U) +#define FB_CSCR_PS_SHIFT (6U) +#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) +#define FB_CSCR_AA_MASK (0x100U) +#define FB_CSCR_AA_SHIFT (8U) +#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) +#define FB_CSCR_BLS_MASK (0x200U) +#define FB_CSCR_BLS_SHIFT (9U) +#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) +#define FB_CSCR_WS_MASK (0xFC00U) +#define FB_CSCR_WS_SHIFT (10U) +#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) +#define FB_CSCR_WRAH_MASK (0x30000U) +#define FB_CSCR_WRAH_SHIFT (16U) +#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) +#define FB_CSCR_RDAH_MASK (0xC0000U) +#define FB_CSCR_RDAH_SHIFT (18U) +#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) +#define FB_CSCR_ASET_MASK (0x300000U) +#define FB_CSCR_ASET_SHIFT (20U) +#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) +#define FB_CSCR_EXTS_MASK (0x400000U) +#define FB_CSCR_EXTS_SHIFT (22U) +#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) +#define FB_CSCR_SWSEN_MASK (0x800000U) +#define FB_CSCR_SWSEN_SHIFT (23U) +#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) +#define FB_CSCR_SWS_MASK (0xFC000000U) +#define FB_CSCR_SWS_SHIFT (26U) +#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) + +/* The count of FB_CSCR */ +#define FB_CSCR_COUNT (6U) + +/*! @name CSPMCR - Chip Select port Multiplexing Control Register */ +#define FB_CSPMCR_GROUP5_MASK (0xF000U) +#define FB_CSPMCR_GROUP5_SHIFT (12U) +#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) +#define FB_CSPMCR_GROUP4_MASK (0xF0000U) +#define FB_CSPMCR_GROUP4_SHIFT (16U) +#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) +#define FB_CSPMCR_GROUP3_MASK (0xF00000U) +#define FB_CSPMCR_GROUP3_SHIFT (20U) +#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) +#define FB_CSPMCR_GROUP2_MASK (0xF000000U) +#define FB_CSPMCR_GROUP2_SHIFT (24U) +#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) +#define FB_CSPMCR_GROUP1_MASK (0xF0000000U) +#define FB_CSPMCR_GROUP1_SHIFT (28U) +#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) + + +/*! + * @} + */ /* end of group FB_Register_Masks */ + + +/* FB - Peripheral instance base addresses */ +/** Peripheral FB base address */ +#define FB_BASE (0x4000C000u) +/** Peripheral FB base pointer */ +#define FB ((FB_Type *)FB_BASE) +/** Array initializer of FB peripheral base addresses */ +#define FB_BASE_ADDRS { FB_BASE } +/** Array initializer of FB peripheral base pointers */ +#define FB_BASE_PTRS { FB } + +/*! + * @} + */ /* end of group FB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ + __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ + __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */ + uint8_t RESERVED_0[244]; + __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */ + __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */ + __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */ + __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */ + uint8_t RESERVED_1[192]; + struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */ + __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */ + __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */ + } SET[4][4]; +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name PFAPR - Flash Access Protection Register */ +#define FMC_PFAPR_M0AP_MASK (0x3U) +#define FMC_PFAPR_M0AP_SHIFT (0U) +#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) +#define FMC_PFAPR_M1AP_MASK (0xCU) +#define FMC_PFAPR_M1AP_SHIFT (2U) +#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) +#define FMC_PFAPR_M2AP_MASK (0x30U) +#define FMC_PFAPR_M2AP_SHIFT (4U) +#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) +#define FMC_PFAPR_M3AP_MASK (0xC0U) +#define FMC_PFAPR_M3AP_SHIFT (6U) +#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) +#define FMC_PFAPR_M4AP_MASK (0x300U) +#define FMC_PFAPR_M4AP_SHIFT (8U) +#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) +#define FMC_PFAPR_M5AP_MASK (0xC00U) +#define FMC_PFAPR_M5AP_SHIFT (10U) +#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK) +#define FMC_PFAPR_M6AP_MASK (0x3000U) +#define FMC_PFAPR_M6AP_SHIFT (12U) +#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK) +#define FMC_PFAPR_M7AP_MASK (0xC000U) +#define FMC_PFAPR_M7AP_SHIFT (14U) +#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK) +#define FMC_PFAPR_M0PFD_MASK (0x10000U) +#define FMC_PFAPR_M0PFD_SHIFT (16U) +#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) +#define FMC_PFAPR_M1PFD_MASK (0x20000U) +#define FMC_PFAPR_M1PFD_SHIFT (17U) +#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) +#define FMC_PFAPR_M2PFD_MASK (0x40000U) +#define FMC_PFAPR_M2PFD_SHIFT (18U) +#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) +#define FMC_PFAPR_M3PFD_MASK (0x80000U) +#define FMC_PFAPR_M3PFD_SHIFT (19U) +#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) +#define FMC_PFAPR_M4PFD_MASK (0x100000U) +#define FMC_PFAPR_M4PFD_SHIFT (20U) +#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) +#define FMC_PFAPR_M5PFD_MASK (0x200000U) +#define FMC_PFAPR_M5PFD_SHIFT (21U) +#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK) +#define FMC_PFAPR_M6PFD_MASK (0x400000U) +#define FMC_PFAPR_M6PFD_SHIFT (22U) +#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK) +#define FMC_PFAPR_M7PFD_MASK (0x800000U) +#define FMC_PFAPR_M7PFD_SHIFT (23U) +#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK) + +/*! @name PFB0CR - Flash Bank 0 Control Register */ +#define FMC_PFB0CR_B0SEBE_MASK (0x1U) +#define FMC_PFB0CR_B0SEBE_SHIFT (0U) +#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) +#define FMC_PFB0CR_B0IPE_MASK (0x2U) +#define FMC_PFB0CR_B0IPE_SHIFT (1U) +#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) +#define FMC_PFB0CR_B0DPE_MASK (0x4U) +#define FMC_PFB0CR_B0DPE_SHIFT (2U) +#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) +#define FMC_PFB0CR_B0ICE_MASK (0x8U) +#define FMC_PFB0CR_B0ICE_SHIFT (3U) +#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) +#define FMC_PFB0CR_B0DCE_MASK (0x10U) +#define FMC_PFB0CR_B0DCE_SHIFT (4U) +#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) +#define FMC_PFB0CR_CRC_MASK (0xE0U) +#define FMC_PFB0CR_CRC_SHIFT (5U) +#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) +#define FMC_PFB0CR_B0MW_MASK (0x60000U) +#define FMC_PFB0CR_B0MW_SHIFT (17U) +#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) +#define FMC_PFB0CR_S_B_INV_MASK (0x80000U) +#define FMC_PFB0CR_S_B_INV_SHIFT (19U) +#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) +#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) +#define FMC_PFB0CR_CINV_WAY_SHIFT (20U) +#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) +#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) +#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) +#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) +#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) +#define FMC_PFB0CR_B0RWSC_SHIFT (28U) +#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) + +/*! @name PFB1CR - Flash Bank 1 Control Register */ +#define FMC_PFB1CR_B1SEBE_MASK (0x1U) +#define FMC_PFB1CR_B1SEBE_SHIFT (0U) +#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK) +#define FMC_PFB1CR_B1IPE_MASK (0x2U) +#define FMC_PFB1CR_B1IPE_SHIFT (1U) +#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK) +#define FMC_PFB1CR_B1DPE_MASK (0x4U) +#define FMC_PFB1CR_B1DPE_SHIFT (2U) +#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK) +#define FMC_PFB1CR_B1ICE_MASK (0x8U) +#define FMC_PFB1CR_B1ICE_SHIFT (3U) +#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK) +#define FMC_PFB1CR_B1DCE_MASK (0x10U) +#define FMC_PFB1CR_B1DCE_SHIFT (4U) +#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK) +#define FMC_PFB1CR_B1MW_MASK (0x60000U) +#define FMC_PFB1CR_B1MW_SHIFT (17U) +#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK) +#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U) +#define FMC_PFB1CR_B1RWSC_SHIFT (28U) +#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK) + +/*! @name TAGVDW0S - Cache Tag Storage */ +#define FMC_TAGVDW0S_valid_MASK (0x1U) +#define FMC_TAGVDW0S_valid_SHIFT (0U) +#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK) +#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW0S_tag_SHIFT (5U) +#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK) + +/* The count of FMC_TAGVDW0S */ +#define FMC_TAGVDW0S_COUNT (4U) + +/*! @name TAGVDW1S - Cache Tag Storage */ +#define FMC_TAGVDW1S_valid_MASK (0x1U) +#define FMC_TAGVDW1S_valid_SHIFT (0U) +#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK) +#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW1S_tag_SHIFT (5U) +#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK) + +/* The count of FMC_TAGVDW1S */ +#define FMC_TAGVDW1S_COUNT (4U) + +/*! @name TAGVDW2S - Cache Tag Storage */ +#define FMC_TAGVDW2S_valid_MASK (0x1U) +#define FMC_TAGVDW2S_valid_SHIFT (0U) +#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK) +#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW2S_tag_SHIFT (5U) +#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK) + +/* The count of FMC_TAGVDW2S */ +#define FMC_TAGVDW2S_COUNT (4U) + +/*! @name TAGVDW3S - Cache Tag Storage */ +#define FMC_TAGVDW3S_valid_MASK (0x1U) +#define FMC_TAGVDW3S_valid_SHIFT (0U) +#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK) +#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW3S_tag_SHIFT (5U) +#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK) + +/* The count of FMC_TAGVDW3S */ +#define FMC_TAGVDW3S_COUNT (4U) + +/*! @name DATA_U - Cache Data Storage (upper word) */ +#define FMC_DATA_U_data_MASK (0xFFFFFFFFU) +#define FMC_DATA_U_data_SHIFT (0U) +#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK) + +/* The count of FMC_DATA_U */ +#define FMC_DATA_U_COUNT (4U) + +/* The count of FMC_DATA_U */ +#define FMC_DATA_U_COUNT2 (4U) + +/*! @name DATA_L - Cache Data Storage (lower word) */ +#define FMC_DATA_L_data_MASK (0xFFFFFFFFU) +#define FMC_DATA_L_data_SHIFT (0U) +#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK) + +/* The count of FMC_DATA_L */ +#define FMC_DATA_L_COUNT (4U) + +/* The count of FMC_DATA_L */ +#define FMC_DATA_L_COUNT2 (4U) + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x4001F000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC } + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTFE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer + * @{ + */ + +/** FTFE - Register Layout Typedef */ +typedef struct { + __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ + __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ + __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ + uint8_t RESERVED_0[2]; + __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ + __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ +} FTFE_Type; + +/* ---------------------------------------------------------------------------- + -- FTFE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFE_Register_Masks FTFE Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +#define FTFE_FSTAT_MGSTAT0_MASK (0x1U) +#define FTFE_FSTAT_MGSTAT0_SHIFT (0U) +#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) +#define FTFE_FSTAT_FPVIOL_MASK (0x10U) +#define FTFE_FSTAT_FPVIOL_SHIFT (4U) +#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) +#define FTFE_FSTAT_ACCERR_MASK (0x20U) +#define FTFE_FSTAT_ACCERR_SHIFT (5U) +#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) +#define FTFE_FSTAT_RDCOLERR_MASK (0x40U) +#define FTFE_FSTAT_RDCOLERR_SHIFT (6U) +#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) +#define FTFE_FSTAT_CCIF_MASK (0x80U) +#define FTFE_FSTAT_CCIF_SHIFT (7U) +#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) + +/*! @name FCNFG - Flash Configuration Register */ +#define FTFE_FCNFG_EEERDY_MASK (0x1U) +#define FTFE_FCNFG_EEERDY_SHIFT (0U) +#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK) +#define FTFE_FCNFG_RAMRDY_MASK (0x2U) +#define FTFE_FCNFG_RAMRDY_SHIFT (1U) +#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) +#define FTFE_FCNFG_PFLSH_MASK (0x4U) +#define FTFE_FCNFG_PFLSH_SHIFT (2U) +#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK) +#define FTFE_FCNFG_SWAP_MASK (0x8U) +#define FTFE_FCNFG_SWAP_SHIFT (3U) +#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK) +#define FTFE_FCNFG_ERSSUSP_MASK (0x10U) +#define FTFE_FCNFG_ERSSUSP_SHIFT (4U) +#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) +#define FTFE_FCNFG_ERSAREQ_MASK (0x20U) +#define FTFE_FCNFG_ERSAREQ_SHIFT (5U) +#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) +#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) +#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) +#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) +#define FTFE_FCNFG_CCIE_MASK (0x80U) +#define FTFE_FCNFG_CCIE_SHIFT (7U) +#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) + +/*! @name FSEC - Flash Security Register */ +#define FTFE_FSEC_SEC_MASK (0x3U) +#define FTFE_FSEC_SEC_SHIFT (0U) +#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) +#define FTFE_FSEC_FSLACC_MASK (0xCU) +#define FTFE_FSEC_FSLACC_SHIFT (2U) +#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) +#define FTFE_FSEC_MEEN_MASK (0x30U) +#define FTFE_FSEC_MEEN_SHIFT (4U) +#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) +#define FTFE_FSEC_KEYEN_MASK (0xC0U) +#define FTFE_FSEC_KEYEN_SHIFT (6U) +#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) + +/*! @name FOPT - Flash Option Register */ +#define FTFE_FOPT_OPT_MASK (0xFFU) +#define FTFE_FOPT_OPT_SHIFT (0U) +#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK) + +/*! @name FCCOB3 - Flash Common Command Object Registers */ +#define FTFE_FCCOB3_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB3_CCOBn_SHIFT (0U) +#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) + +/*! @name FCCOB2 - Flash Common Command Object Registers */ +#define FTFE_FCCOB2_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB2_CCOBn_SHIFT (0U) +#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) + +/*! @name FCCOB1 - Flash Common Command Object Registers */ +#define FTFE_FCCOB1_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB1_CCOBn_SHIFT (0U) +#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) + +/*! @name FCCOB0 - Flash Common Command Object Registers */ +#define FTFE_FCCOB0_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB0_CCOBn_SHIFT (0U) +#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) + +/*! @name FCCOB7 - Flash Common Command Object Registers */ +#define FTFE_FCCOB7_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB7_CCOBn_SHIFT (0U) +#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) + +/*! @name FCCOB6 - Flash Common Command Object Registers */ +#define FTFE_FCCOB6_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB6_CCOBn_SHIFT (0U) +#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) + +/*! @name FCCOB5 - Flash Common Command Object Registers */ +#define FTFE_FCCOB5_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB5_CCOBn_SHIFT (0U) +#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) + +/*! @name FCCOB4 - Flash Common Command Object Registers */ +#define FTFE_FCCOB4_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB4_CCOBn_SHIFT (0U) +#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) + +/*! @name FCCOBB - Flash Common Command Object Registers */ +#define FTFE_FCCOBB_CCOBn_MASK (0xFFU) +#define FTFE_FCCOBB_CCOBn_SHIFT (0U) +#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) + +/*! @name FCCOBA - Flash Common Command Object Registers */ +#define FTFE_FCCOBA_CCOBn_MASK (0xFFU) +#define FTFE_FCCOBA_CCOBn_SHIFT (0U) +#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) + +/*! @name FCCOB9 - Flash Common Command Object Registers */ +#define FTFE_FCCOB9_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB9_CCOBn_SHIFT (0U) +#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) + +/*! @name FCCOB8 - Flash Common Command Object Registers */ +#define FTFE_FCCOB8_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB8_CCOBn_SHIFT (0U) +#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) + +/*! @name FPROT3 - Program Flash Protection Registers */ +#define FTFE_FPROT3_PROT_MASK (0xFFU) +#define FTFE_FPROT3_PROT_SHIFT (0U) +#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Program Flash Protection Registers */ +#define FTFE_FPROT2_PROT_MASK (0xFFU) +#define FTFE_FPROT2_PROT_SHIFT (0U) +#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Program Flash Protection Registers */ +#define FTFE_FPROT1_PROT_MASK (0xFFU) +#define FTFE_FPROT1_PROT_SHIFT (0U) +#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Program Flash Protection Registers */ +#define FTFE_FPROT0_PROT_MASK (0xFFU) +#define FTFE_FPROT0_PROT_SHIFT (0U) +#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK) + +/*! @name FEPROT - EEPROM Protection Register */ +#define FTFE_FEPROT_EPROT_MASK (0xFFU) +#define FTFE_FEPROT_EPROT_SHIFT (0U) +#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK) + +/*! @name FDPROT - Data Flash Protection Register */ +#define FTFE_FDPROT_DPROT_MASK (0xFFU) +#define FTFE_FDPROT_DPROT_SHIFT (0U) +#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK) + + +/*! + * @} + */ /* end of group FTFE_Register_Masks */ + + +/* FTFE - Peripheral instance base addresses */ +/** Peripheral FTFE base address */ +#define FTFE_BASE (0x40020000u) +/** Peripheral FTFE base pointer */ +#define FTFE ((FTFE_Type *)FTFE_BASE) +/** Array initializer of FTFE peripheral base addresses */ +#define FTFE_BASE_ADDRS { FTFE_BASE } +/** Array initializer of FTFE peripheral base pointers */ +#define FTFE_BASE_PTRS { FTFE } +/** Interrupt vectors for the FTFE peripheral type */ +#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn } +#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn } + +/*! + * @} + */ /* end of group FTFE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/** FTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } CONTROLS[8]; + __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ + __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ + __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ + __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ + __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ + __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ + __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ + __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ + __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ + __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ + __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ + __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ + __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ + __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ + __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ +} FTM_Type; + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/*! @name SC - Status And Control */ +#define FTM_SC_PS_MASK (0x7U) +#define FTM_SC_PS_SHIFT (0U) +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK (0x18U) +#define FTM_SC_CLKS_SHIFT (3U) +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS_MASK (0x20U) +#define FTM_SC_CPWMS_SHIFT (5U) +#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) +#define FTM_SC_TOIE_MASK (0x40U) +#define FTM_SC_TOIE_SHIFT (6U) +#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) +#define FTM_SC_TOF_MASK (0x80U) +#define FTM_SC_TOF_SHIFT (7U) +#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) + +/*! @name CNT - Counter */ +#define FTM_CNT_COUNT_MASK (0xFFFFU) +#define FTM_CNT_COUNT_SHIFT (0U) +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) + +/*! @name MOD - Modulo */ +#define FTM_MOD_MOD_MASK (0xFFFFU) +#define FTM_MOD_MOD_SHIFT (0U) +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) + +/*! @name CnSC - Channel (n) Status And Control */ +#define FTM_CnSC_DMA_MASK (0x1U) +#define FTM_CnSC_DMA_SHIFT (0U) +#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) +#define FTM_CnSC_ELSA_MASK (0x4U) +#define FTM_CnSC_ELSA_SHIFT (2U) +#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) +#define FTM_CnSC_ELSB_MASK (0x8U) +#define FTM_CnSC_ELSB_SHIFT (3U) +#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) +#define FTM_CnSC_MSA_MASK (0x10U) +#define FTM_CnSC_MSA_SHIFT (4U) +#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) +#define FTM_CnSC_MSB_MASK (0x20U) +#define FTM_CnSC_MSB_SHIFT (5U) +#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) +#define FTM_CnSC_CHIE_MASK (0x40U) +#define FTM_CnSC_CHIE_SHIFT (6U) +#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) +#define FTM_CnSC_CHF_MASK (0x80U) +#define FTM_CnSC_CHF_SHIFT (7U) +#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) + +/* The count of FTM_CnSC */ +#define FTM_CnSC_COUNT (8U) + +/*! @name CnV - Channel (n) Value */ +#define FTM_CnV_VAL_MASK (0xFFFFU) +#define FTM_CnV_VAL_SHIFT (0U) +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) + +/* The count of FTM_CnV */ +#define FTM_CnV_COUNT (8U) + +/*! @name CNTIN - Counter Initial Value */ +#define FTM_CNTIN_INIT_MASK (0xFFFFU) +#define FTM_CNTIN_INIT_SHIFT (0U) +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) + +/*! @name STATUS - Capture And Compare Status */ +#define FTM_STATUS_CH0F_MASK (0x1U) +#define FTM_STATUS_CH0F_SHIFT (0U) +#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) +#define FTM_STATUS_CH1F_MASK (0x2U) +#define FTM_STATUS_CH1F_SHIFT (1U) +#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) +#define FTM_STATUS_CH2F_MASK (0x4U) +#define FTM_STATUS_CH2F_SHIFT (2U) +#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) +#define FTM_STATUS_CH3F_MASK (0x8U) +#define FTM_STATUS_CH3F_SHIFT (3U) +#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) +#define FTM_STATUS_CH4F_MASK (0x10U) +#define FTM_STATUS_CH4F_SHIFT (4U) +#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) +#define FTM_STATUS_CH5F_MASK (0x20U) +#define FTM_STATUS_CH5F_SHIFT (5U) +#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) +#define FTM_STATUS_CH6F_MASK (0x40U) +#define FTM_STATUS_CH6F_SHIFT (6U) +#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) +#define FTM_STATUS_CH7F_MASK (0x80U) +#define FTM_STATUS_CH7F_SHIFT (7U) +#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) + +/*! @name MODE - Features Mode Selection */ +#define FTM_MODE_FTMEN_MASK (0x1U) +#define FTM_MODE_FTMEN_SHIFT (0U) +#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) +#define FTM_MODE_INIT_MASK (0x2U) +#define FTM_MODE_INIT_SHIFT (1U) +#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) +#define FTM_MODE_WPDIS_MASK (0x4U) +#define FTM_MODE_WPDIS_SHIFT (2U) +#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) +#define FTM_MODE_PWMSYNC_MASK (0x8U) +#define FTM_MODE_PWMSYNC_SHIFT (3U) +#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) +#define FTM_MODE_CAPTEST_MASK (0x10U) +#define FTM_MODE_CAPTEST_SHIFT (4U) +#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) +#define FTM_MODE_FAULTM_MASK (0x60U) +#define FTM_MODE_FAULTM_SHIFT (5U) +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK (0x80U) +#define FTM_MODE_FAULTIE_SHIFT (7U) +#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) + +/*! @name SYNC - Synchronization */ +#define FTM_SYNC_CNTMIN_MASK (0x1U) +#define FTM_SYNC_CNTMIN_SHIFT (0U) +#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) +#define FTM_SYNC_CNTMAX_MASK (0x2U) +#define FTM_SYNC_CNTMAX_SHIFT (1U) +#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) +#define FTM_SYNC_REINIT_MASK (0x4U) +#define FTM_SYNC_REINIT_SHIFT (2U) +#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) +#define FTM_SYNC_SYNCHOM_MASK (0x8U) +#define FTM_SYNC_SYNCHOM_SHIFT (3U) +#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) +#define FTM_SYNC_TRIG0_MASK (0x10U) +#define FTM_SYNC_TRIG0_SHIFT (4U) +#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) +#define FTM_SYNC_TRIG1_MASK (0x20U) +#define FTM_SYNC_TRIG1_SHIFT (5U) +#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) +#define FTM_SYNC_TRIG2_MASK (0x40U) +#define FTM_SYNC_TRIG2_SHIFT (6U) +#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) +#define FTM_SYNC_SWSYNC_MASK (0x80U) +#define FTM_SYNC_SWSYNC_SHIFT (7U) +#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) + +/*! @name OUTINIT - Initial State For Channels Output */ +#define FTM_OUTINIT_CH0OI_MASK (0x1U) +#define FTM_OUTINIT_CH0OI_SHIFT (0U) +#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) +#define FTM_OUTINIT_CH1OI_MASK (0x2U) +#define FTM_OUTINIT_CH1OI_SHIFT (1U) +#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) +#define FTM_OUTINIT_CH2OI_MASK (0x4U) +#define FTM_OUTINIT_CH2OI_SHIFT (2U) +#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) +#define FTM_OUTINIT_CH3OI_MASK (0x8U) +#define FTM_OUTINIT_CH3OI_SHIFT (3U) +#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) +#define FTM_OUTINIT_CH4OI_MASK (0x10U) +#define FTM_OUTINIT_CH4OI_SHIFT (4U) +#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) +#define FTM_OUTINIT_CH5OI_MASK (0x20U) +#define FTM_OUTINIT_CH5OI_SHIFT (5U) +#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) +#define FTM_OUTINIT_CH6OI_MASK (0x40U) +#define FTM_OUTINIT_CH6OI_SHIFT (6U) +#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) +#define FTM_OUTINIT_CH7OI_MASK (0x80U) +#define FTM_OUTINIT_CH7OI_SHIFT (7U) +#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) + +/*! @name OUTMASK - Output Mask */ +#define FTM_OUTMASK_CH0OM_MASK (0x1U) +#define FTM_OUTMASK_CH0OM_SHIFT (0U) +#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) +#define FTM_OUTMASK_CH1OM_MASK (0x2U) +#define FTM_OUTMASK_CH1OM_SHIFT (1U) +#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) +#define FTM_OUTMASK_CH2OM_MASK (0x4U) +#define FTM_OUTMASK_CH2OM_SHIFT (2U) +#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) +#define FTM_OUTMASK_CH3OM_MASK (0x8U) +#define FTM_OUTMASK_CH3OM_SHIFT (3U) +#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) +#define FTM_OUTMASK_CH4OM_MASK (0x10U) +#define FTM_OUTMASK_CH4OM_SHIFT (4U) +#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) +#define FTM_OUTMASK_CH5OM_MASK (0x20U) +#define FTM_OUTMASK_CH5OM_SHIFT (5U) +#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) +#define FTM_OUTMASK_CH6OM_MASK (0x40U) +#define FTM_OUTMASK_CH6OM_SHIFT (6U) +#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) +#define FTM_OUTMASK_CH7OM_MASK (0x80U) +#define FTM_OUTMASK_CH7OM_SHIFT (7U) +#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) + +/*! @name COMBINE - Function For Linked Channels */ +#define FTM_COMBINE_COMBINE0_MASK (0x1U) +#define FTM_COMBINE_COMBINE0_SHIFT (0U) +#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) +#define FTM_COMBINE_COMP0_MASK (0x2U) +#define FTM_COMBINE_COMP0_SHIFT (1U) +#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) +#define FTM_COMBINE_DECAPEN0_MASK (0x4U) +#define FTM_COMBINE_DECAPEN0_SHIFT (2U) +#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) +#define FTM_COMBINE_DECAP0_MASK (0x8U) +#define FTM_COMBINE_DECAP0_SHIFT (3U) +#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) +#define FTM_COMBINE_DTEN0_MASK (0x10U) +#define FTM_COMBINE_DTEN0_SHIFT (4U) +#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) +#define FTM_COMBINE_SYNCEN0_MASK (0x20U) +#define FTM_COMBINE_SYNCEN0_SHIFT (5U) +#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) +#define FTM_COMBINE_FAULTEN0_MASK (0x40U) +#define FTM_COMBINE_FAULTEN0_SHIFT (6U) +#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) +#define FTM_COMBINE_COMBINE1_MASK (0x100U) +#define FTM_COMBINE_COMBINE1_SHIFT (8U) +#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) +#define FTM_COMBINE_COMP1_MASK (0x200U) +#define FTM_COMBINE_COMP1_SHIFT (9U) +#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) +#define FTM_COMBINE_DECAPEN1_MASK (0x400U) +#define FTM_COMBINE_DECAPEN1_SHIFT (10U) +#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) +#define FTM_COMBINE_DECAP1_MASK (0x800U) +#define FTM_COMBINE_DECAP1_SHIFT (11U) +#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) +#define FTM_COMBINE_DTEN1_MASK (0x1000U) +#define FTM_COMBINE_DTEN1_SHIFT (12U) +#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) +#define FTM_COMBINE_SYNCEN1_MASK (0x2000U) +#define FTM_COMBINE_SYNCEN1_SHIFT (13U) +#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) +#define FTM_COMBINE_FAULTEN1_MASK (0x4000U) +#define FTM_COMBINE_FAULTEN1_SHIFT (14U) +#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) +#define FTM_COMBINE_COMBINE2_MASK (0x10000U) +#define FTM_COMBINE_COMBINE2_SHIFT (16U) +#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) +#define FTM_COMBINE_COMP2_MASK (0x20000U) +#define FTM_COMBINE_COMP2_SHIFT (17U) +#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) +#define FTM_COMBINE_DECAPEN2_MASK (0x40000U) +#define FTM_COMBINE_DECAPEN2_SHIFT (18U) +#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) +#define FTM_COMBINE_DECAP2_MASK (0x80000U) +#define FTM_COMBINE_DECAP2_SHIFT (19U) +#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) +#define FTM_COMBINE_DTEN2_MASK (0x100000U) +#define FTM_COMBINE_DTEN2_SHIFT (20U) +#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) +#define FTM_COMBINE_SYNCEN2_MASK (0x200000U) +#define FTM_COMBINE_SYNCEN2_SHIFT (21U) +#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) +#define FTM_COMBINE_FAULTEN2_MASK (0x400000U) +#define FTM_COMBINE_FAULTEN2_SHIFT (22U) +#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) +#define FTM_COMBINE_COMBINE3_MASK (0x1000000U) +#define FTM_COMBINE_COMBINE3_SHIFT (24U) +#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) +#define FTM_COMBINE_COMP3_MASK (0x2000000U) +#define FTM_COMBINE_COMP3_SHIFT (25U) +#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) +#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) +#define FTM_COMBINE_DECAPEN3_SHIFT (26U) +#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) +#define FTM_COMBINE_DECAP3_MASK (0x8000000U) +#define FTM_COMBINE_DECAP3_SHIFT (27U) +#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) +#define FTM_COMBINE_DTEN3_MASK (0x10000000U) +#define FTM_COMBINE_DTEN3_SHIFT (28U) +#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) +#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) +#define FTM_COMBINE_SYNCEN3_SHIFT (29U) +#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) +#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) +#define FTM_COMBINE_FAULTEN3_SHIFT (30U) +#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) + +/*! @name DEADTIME - Deadtime Insertion Control */ +#define FTM_DEADTIME_DTVAL_MASK (0x3FU) +#define FTM_DEADTIME_DTVAL_SHIFT (0U) +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK (0xC0U) +#define FTM_DEADTIME_DTPS_SHIFT (6U) +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) + +/*! @name EXTTRIG - FTM External Trigger */ +#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) +#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) +#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) +#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) +#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) +#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) +#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) +#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) +#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) +#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) +#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) +#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) +#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) +#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) +#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) +#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) +#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) +#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) +#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) +#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) +#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) +#define FTM_EXTTRIG_TRIGF_MASK (0x80U) +#define FTM_EXTTRIG_TRIGF_SHIFT (7U) +#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) + +/*! @name POL - Channels Polarity */ +#define FTM_POL_POL0_MASK (0x1U) +#define FTM_POL_POL0_SHIFT (0U) +#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) +#define FTM_POL_POL1_MASK (0x2U) +#define FTM_POL_POL1_SHIFT (1U) +#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) +#define FTM_POL_POL2_MASK (0x4U) +#define FTM_POL_POL2_SHIFT (2U) +#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) +#define FTM_POL_POL3_MASK (0x8U) +#define FTM_POL_POL3_SHIFT (3U) +#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) +#define FTM_POL_POL4_MASK (0x10U) +#define FTM_POL_POL4_SHIFT (4U) +#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) +#define FTM_POL_POL5_MASK (0x20U) +#define FTM_POL_POL5_SHIFT (5U) +#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) +#define FTM_POL_POL6_MASK (0x40U) +#define FTM_POL_POL6_SHIFT (6U) +#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) +#define FTM_POL_POL7_MASK (0x80U) +#define FTM_POL_POL7_SHIFT (7U) +#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) + +/*! @name FMS - Fault Mode Status */ +#define FTM_FMS_FAULTF0_MASK (0x1U) +#define FTM_FMS_FAULTF0_SHIFT (0U) +#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) +#define FTM_FMS_FAULTF1_MASK (0x2U) +#define FTM_FMS_FAULTF1_SHIFT (1U) +#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) +#define FTM_FMS_FAULTF2_MASK (0x4U) +#define FTM_FMS_FAULTF2_SHIFT (2U) +#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) +#define FTM_FMS_FAULTF3_MASK (0x8U) +#define FTM_FMS_FAULTF3_SHIFT (3U) +#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) +#define FTM_FMS_FAULTIN_MASK (0x20U) +#define FTM_FMS_FAULTIN_SHIFT (5U) +#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) +#define FTM_FMS_WPEN_MASK (0x40U) +#define FTM_FMS_WPEN_SHIFT (6U) +#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) +#define FTM_FMS_FAULTF_MASK (0x80U) +#define FTM_FMS_FAULTF_SHIFT (7U) +#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) + +/*! @name FILTER - Input Capture Filter Control */ +#define FTM_FILTER_CH0FVAL_MASK (0xFU) +#define FTM_FILTER_CH0FVAL_SHIFT (0U) +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK (0xF0U) +#define FTM_FILTER_CH1FVAL_SHIFT (4U) +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK (0xF00U) +#define FTM_FILTER_CH2FVAL_SHIFT (8U) +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK (0xF000U) +#define FTM_FILTER_CH3FVAL_SHIFT (12U) +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) + +/*! @name FLTCTRL - Fault Control */ +#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) +#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) +#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) +#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) +#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) +#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) +#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) +#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) +#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) +#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) +#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) +#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) +#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) +#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) +#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) +#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) +#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) +#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) +#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) +#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) +#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) +#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) +#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) +#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) +#define FTM_FLTCTRL_FFVAL_MASK (0xF00U) +#define FTM_FLTCTRL_FFVAL_SHIFT (8U) +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) + +/*! @name QDCTRL - Quadrature Decoder Control And Status */ +#define FTM_QDCTRL_QUADEN_MASK (0x1U) +#define FTM_QDCTRL_QUADEN_SHIFT (0U) +#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) +#define FTM_QDCTRL_TOFDIR_MASK (0x2U) +#define FTM_QDCTRL_TOFDIR_SHIFT (1U) +#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) +#define FTM_QDCTRL_QUADIR_MASK (0x4U) +#define FTM_QDCTRL_QUADIR_SHIFT (2U) +#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) +#define FTM_QDCTRL_QUADMODE_MASK (0x8U) +#define FTM_QDCTRL_QUADMODE_SHIFT (3U) +#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) +#define FTM_QDCTRL_PHBPOL_MASK (0x10U) +#define FTM_QDCTRL_PHBPOL_SHIFT (4U) +#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) +#define FTM_QDCTRL_PHAPOL_MASK (0x20U) +#define FTM_QDCTRL_PHAPOL_SHIFT (5U) +#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) +#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) +#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) +#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) +#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) +#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) +#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) + +/*! @name CONF - Configuration */ +#define FTM_CONF_NUMTOF_MASK (0x1FU) +#define FTM_CONF_NUMTOF_SHIFT (0U) +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK (0xC0U) +#define FTM_CONF_BDMMODE_SHIFT (6U) +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK (0x200U) +#define FTM_CONF_GTBEEN_SHIFT (9U) +#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) +#define FTM_CONF_GTBEOUT_MASK (0x400U) +#define FTM_CONF_GTBEOUT_SHIFT (10U) +#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) + +/*! @name FLTPOL - FTM Fault Input Polarity */ +#define FTM_FLTPOL_FLT0POL_MASK (0x1U) +#define FTM_FLTPOL_FLT0POL_SHIFT (0U) +#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) +#define FTM_FLTPOL_FLT1POL_MASK (0x2U) +#define FTM_FLTPOL_FLT1POL_SHIFT (1U) +#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) +#define FTM_FLTPOL_FLT2POL_MASK (0x4U) +#define FTM_FLTPOL_FLT2POL_SHIFT (2U) +#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) +#define FTM_FLTPOL_FLT3POL_MASK (0x8U) +#define FTM_FLTPOL_FLT3POL_SHIFT (3U) +#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) + +/*! @name SYNCONF - Synchronization Configuration */ +#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) +#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) +#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) +#define FTM_SYNCONF_CNTINC_MASK (0x4U) +#define FTM_SYNCONF_CNTINC_SHIFT (2U) +#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) +#define FTM_SYNCONF_INVC_MASK (0x10U) +#define FTM_SYNCONF_INVC_SHIFT (4U) +#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) +#define FTM_SYNCONF_SWOC_MASK (0x20U) +#define FTM_SYNCONF_SWOC_SHIFT (5U) +#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) +#define FTM_SYNCONF_SYNCMODE_MASK (0x80U) +#define FTM_SYNCONF_SYNCMODE_SHIFT (7U) +#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) +#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) +#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) +#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) +#define FTM_SYNCONF_SWWRBUF_MASK (0x200U) +#define FTM_SYNCONF_SWWRBUF_SHIFT (9U) +#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) +#define FTM_SYNCONF_SWOM_MASK (0x400U) +#define FTM_SYNCONF_SWOM_SHIFT (10U) +#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) +#define FTM_SYNCONF_SWINVC_MASK (0x800U) +#define FTM_SYNCONF_SWINVC_SHIFT (11U) +#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) +#define FTM_SYNCONF_SWSOC_MASK (0x1000U) +#define FTM_SYNCONF_SWSOC_SHIFT (12U) +#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) +#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) +#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) +#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) +#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) +#define FTM_SYNCONF_HWWRBUF_SHIFT (17U) +#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) +#define FTM_SYNCONF_HWOM_MASK (0x40000U) +#define FTM_SYNCONF_HWOM_SHIFT (18U) +#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) +#define FTM_SYNCONF_HWINVC_MASK (0x80000U) +#define FTM_SYNCONF_HWINVC_SHIFT (19U) +#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) +#define FTM_SYNCONF_HWSOC_MASK (0x100000U) +#define FTM_SYNCONF_HWSOC_SHIFT (20U) +#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) + +/*! @name INVCTRL - FTM Inverting Control */ +#define FTM_INVCTRL_INV0EN_MASK (0x1U) +#define FTM_INVCTRL_INV0EN_SHIFT (0U) +#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) +#define FTM_INVCTRL_INV1EN_MASK (0x2U) +#define FTM_INVCTRL_INV1EN_SHIFT (1U) +#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) +#define FTM_INVCTRL_INV2EN_MASK (0x4U) +#define FTM_INVCTRL_INV2EN_SHIFT (2U) +#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) +#define FTM_INVCTRL_INV3EN_MASK (0x8U) +#define FTM_INVCTRL_INV3EN_SHIFT (3U) +#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) + +/*! @name SWOCTRL - FTM Software Output Control */ +#define FTM_SWOCTRL_CH0OC_MASK (0x1U) +#define FTM_SWOCTRL_CH0OC_SHIFT (0U) +#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) +#define FTM_SWOCTRL_CH1OC_MASK (0x2U) +#define FTM_SWOCTRL_CH1OC_SHIFT (1U) +#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) +#define FTM_SWOCTRL_CH2OC_MASK (0x4U) +#define FTM_SWOCTRL_CH2OC_SHIFT (2U) +#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) +#define FTM_SWOCTRL_CH3OC_MASK (0x8U) +#define FTM_SWOCTRL_CH3OC_SHIFT (3U) +#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) +#define FTM_SWOCTRL_CH4OC_MASK (0x10U) +#define FTM_SWOCTRL_CH4OC_SHIFT (4U) +#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) +#define FTM_SWOCTRL_CH5OC_MASK (0x20U) +#define FTM_SWOCTRL_CH5OC_SHIFT (5U) +#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) +#define FTM_SWOCTRL_CH6OC_MASK (0x40U) +#define FTM_SWOCTRL_CH6OC_SHIFT (6U) +#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) +#define FTM_SWOCTRL_CH7OC_MASK (0x80U) +#define FTM_SWOCTRL_CH7OC_SHIFT (7U) +#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) +#define FTM_SWOCTRL_CH0OCV_MASK (0x100U) +#define FTM_SWOCTRL_CH0OCV_SHIFT (8U) +#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) +#define FTM_SWOCTRL_CH1OCV_MASK (0x200U) +#define FTM_SWOCTRL_CH1OCV_SHIFT (9U) +#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) +#define FTM_SWOCTRL_CH2OCV_MASK (0x400U) +#define FTM_SWOCTRL_CH2OCV_SHIFT (10U) +#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) +#define FTM_SWOCTRL_CH3OCV_MASK (0x800U) +#define FTM_SWOCTRL_CH3OCV_SHIFT (11U) +#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) +#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) +#define FTM_SWOCTRL_CH4OCV_SHIFT (12U) +#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) +#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) +#define FTM_SWOCTRL_CH5OCV_SHIFT (13U) +#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) +#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) +#define FTM_SWOCTRL_CH6OCV_SHIFT (14U) +#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) +#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) +#define FTM_SWOCTRL_CH7OCV_SHIFT (15U) +#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) + +/*! @name PWMLOAD - FTM PWM Load */ +#define FTM_PWMLOAD_CH0SEL_MASK (0x1U) +#define FTM_PWMLOAD_CH0SEL_SHIFT (0U) +#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) +#define FTM_PWMLOAD_CH1SEL_MASK (0x2U) +#define FTM_PWMLOAD_CH1SEL_SHIFT (1U) +#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) +#define FTM_PWMLOAD_CH2SEL_MASK (0x4U) +#define FTM_PWMLOAD_CH2SEL_SHIFT (2U) +#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) +#define FTM_PWMLOAD_CH3SEL_MASK (0x8U) +#define FTM_PWMLOAD_CH3SEL_SHIFT (3U) +#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) +#define FTM_PWMLOAD_CH4SEL_MASK (0x10U) +#define FTM_PWMLOAD_CH4SEL_SHIFT (4U) +#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) +#define FTM_PWMLOAD_CH5SEL_MASK (0x20U) +#define FTM_PWMLOAD_CH5SEL_SHIFT (5U) +#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) +#define FTM_PWMLOAD_CH6SEL_MASK (0x40U) +#define FTM_PWMLOAD_CH6SEL_SHIFT (6U) +#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) +#define FTM_PWMLOAD_CH7SEL_MASK (0x80U) +#define FTM_PWMLOAD_CH7SEL_SHIFT (7U) +#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) +#define FTM_PWMLOAD_LDOK_MASK (0x200U) +#define FTM_PWMLOAD_LDOK_SHIFT (9U) +#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) + + +/*! + * @} + */ /* end of group FTM_Register_Masks */ + + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM0 base address */ +#define FTM0_BASE (0x40038000u) +/** Peripheral FTM0 base pointer */ +#define FTM0 ((FTM_Type *)FTM0_BASE) +/** Peripheral FTM1 base address */ +#define FTM1_BASE (0x40039000u) +/** Peripheral FTM1 base pointer */ +#define FTM1 ((FTM_Type *)FTM1_BASE) +/** Peripheral FTM2 base address */ +#define FTM2_BASE (0x4003A000u) +/** Peripheral FTM2 base pointer */ +#define FTM2 ((FTM_Type *)FTM2_BASE) +/** Peripheral FTM3 base address */ +#define FTM3_BASE (0x400B9000u) +/** Peripheral FTM3 base pointer */ +#define FTM3 ((FTM_Type *)FTM3_BASE) +/** Array initializer of FTM peripheral base addresses */ +#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE } +/** Array initializer of FTM peripheral base pointers */ +#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 } +/** Interrupt vectors for the FTM peripheral type */ +#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn } + +/*! + * @} + */ /* end of group FTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name PDOR - Port Data Output Register */ +#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) +#define GPIO_PDOR_PDO_SHIFT (0U) +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) + +/*! @name PSOR - Port Set Output Register */ +#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define GPIO_PSOR_PTSO_SHIFT (0U) +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) + +/*! @name PCOR - Port Clear Output Register */ +#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define GPIO_PCOR_PTCO_SHIFT (0U) +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) + +/*! @name PTOR - Port Toggle Output Register */ +#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define GPIO_PTOR_PTTO_SHIFT (0U) +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) + +/*! @name PDIR - Port Data Input Register */ +#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define GPIO_PDIR_PDI_SHIFT (0U) +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) + +/*! @name PDDR - Port Data Direction Register */ +#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define GPIO_PDDR_PDD_SHIFT (0U) +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral PTA base address */ +#define PTA_BASE (0x400FF000u) +/** Peripheral PTA base pointer */ +#define PTA ((GPIO_Type *)PTA_BASE) +/** Peripheral PTB base address */ +#define PTB_BASE (0x400FF040u) +/** Peripheral PTB base pointer */ +#define PTB ((GPIO_Type *)PTB_BASE) +/** Peripheral PTC base address */ +#define PTC_BASE (0x400FF080u) +/** Peripheral PTC base pointer */ +#define PTC ((GPIO_Type *)PTC_BASE) +/** Peripheral PTD base address */ +#define PTD_BASE (0x400FF0C0u) +/** Peripheral PTD base pointer */ +#define PTD ((GPIO_Type *)PTD_BASE) +/** Peripheral PTE base address */ +#define PTE_BASE (0x400FF100u) +/** Peripheral PTE base pointer */ +#define PTE ((GPIO_Type *)PTE_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ + __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ + __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ + __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ + __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ + __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ + __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ + __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ + __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ + __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ + __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ + __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name A1 - I2C Address Register 1 */ +#define I2C_A1_AD_MASK (0xFEU) +#define I2C_A1_AD_SHIFT (1U) +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) + +/*! @name F - I2C Frequency Divider register */ +#define I2C_F_ICR_MASK (0x3FU) +#define I2C_F_ICR_SHIFT (0U) +#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) +#define I2C_F_MULT_MASK (0xC0U) +#define I2C_F_MULT_SHIFT (6U) +#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) + +/*! @name C1 - I2C Control Register 1 */ +#define I2C_C1_DMAEN_MASK (0x1U) +#define I2C_C1_DMAEN_SHIFT (0U) +#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) +#define I2C_C1_WUEN_MASK (0x2U) +#define I2C_C1_WUEN_SHIFT (1U) +#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) +#define I2C_C1_RSTA_MASK (0x4U) +#define I2C_C1_RSTA_SHIFT (2U) +#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) +#define I2C_C1_TXAK_MASK (0x8U) +#define I2C_C1_TXAK_SHIFT (3U) +#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) +#define I2C_C1_TX_MASK (0x10U) +#define I2C_C1_TX_SHIFT (4U) +#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) +#define I2C_C1_MST_MASK (0x20U) +#define I2C_C1_MST_SHIFT (5U) +#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) +#define I2C_C1_IICIE_MASK (0x40U) +#define I2C_C1_IICIE_SHIFT (6U) +#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) +#define I2C_C1_IICEN_MASK (0x80U) +#define I2C_C1_IICEN_SHIFT (7U) +#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) + +/*! @name S - I2C Status register */ +#define I2C_S_RXAK_MASK (0x1U) +#define I2C_S_RXAK_SHIFT (0U) +#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) +#define I2C_S_IICIF_MASK (0x2U) +#define I2C_S_IICIF_SHIFT (1U) +#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) +#define I2C_S_SRW_MASK (0x4U) +#define I2C_S_SRW_SHIFT (2U) +#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) +#define I2C_S_RAM_MASK (0x8U) +#define I2C_S_RAM_SHIFT (3U) +#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) +#define I2C_S_ARBL_MASK (0x10U) +#define I2C_S_ARBL_SHIFT (4U) +#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) +#define I2C_S_BUSY_MASK (0x20U) +#define I2C_S_BUSY_SHIFT (5U) +#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) +#define I2C_S_IAAS_MASK (0x40U) +#define I2C_S_IAAS_SHIFT (6U) +#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) +#define I2C_S_TCF_MASK (0x80U) +#define I2C_S_TCF_SHIFT (7U) +#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) + +/*! @name D - I2C Data I/O register */ +#define I2C_D_DATA_MASK (0xFFU) +#define I2C_D_DATA_SHIFT (0U) +#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) + +/*! @name C2 - I2C Control Register 2 */ +#define I2C_C2_AD_MASK (0x7U) +#define I2C_C2_AD_SHIFT (0U) +#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) +#define I2C_C2_RMEN_MASK (0x8U) +#define I2C_C2_RMEN_SHIFT (3U) +#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) +#define I2C_C2_SBRC_MASK (0x10U) +#define I2C_C2_SBRC_SHIFT (4U) +#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) +#define I2C_C2_HDRS_MASK (0x20U) +#define I2C_C2_HDRS_SHIFT (5U) +#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) +#define I2C_C2_ADEXT_MASK (0x40U) +#define I2C_C2_ADEXT_SHIFT (6U) +#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) +#define I2C_C2_GCAEN_MASK (0x80U) +#define I2C_C2_GCAEN_SHIFT (7U) +#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) + +/*! @name FLT - I2C Programmable Input Glitch Filter register */ +#define I2C_FLT_FLT_MASK (0xFU) +#define I2C_FLT_FLT_SHIFT (0U) +#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) +#define I2C_FLT_STARTF_MASK (0x10U) +#define I2C_FLT_STARTF_SHIFT (4U) +#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) +#define I2C_FLT_SSIE_MASK (0x20U) +#define I2C_FLT_SSIE_SHIFT (5U) +#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) +#define I2C_FLT_STOPF_MASK (0x40U) +#define I2C_FLT_STOPF_SHIFT (6U) +#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) +#define I2C_FLT_SHEN_MASK (0x80U) +#define I2C_FLT_SHEN_SHIFT (7U) +#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) + +/*! @name RA - I2C Range Address register */ +#define I2C_RA_RAD_MASK (0xFEU) +#define I2C_RA_RAD_SHIFT (1U) +#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) + +/*! @name SMB - I2C SMBus Control and Status register */ +#define I2C_SMB_SHTF2IE_MASK (0x1U) +#define I2C_SMB_SHTF2IE_SHIFT (0U) +#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) +#define I2C_SMB_SHTF2_MASK (0x2U) +#define I2C_SMB_SHTF2_SHIFT (1U) +#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) +#define I2C_SMB_SHTF1_MASK (0x4U) +#define I2C_SMB_SHTF1_SHIFT (2U) +#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) +#define I2C_SMB_SLTF_MASK (0x8U) +#define I2C_SMB_SLTF_SHIFT (3U) +#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) +#define I2C_SMB_TCKSEL_MASK (0x10U) +#define I2C_SMB_TCKSEL_SHIFT (4U) +#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) +#define I2C_SMB_SIICAEN_MASK (0x20U) +#define I2C_SMB_SIICAEN_SHIFT (5U) +#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) +#define I2C_SMB_ALERTEN_MASK (0x40U) +#define I2C_SMB_ALERTEN_SHIFT (6U) +#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) +#define I2C_SMB_FACK_MASK (0x80U) +#define I2C_SMB_FACK_SHIFT (7U) +#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) + +/*! @name A2 - I2C Address Register 2 */ +#define I2C_A2_SAD_MASK (0xFEU) +#define I2C_A2_SAD_SHIFT (1U) +#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) + +/*! @name SLTH - I2C SCL Low Timeout Register High */ +#define I2C_SLTH_SSLT_MASK (0xFFU) +#define I2C_SLTH_SSLT_SHIFT (0U) +#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) + +/*! @name SLTL - I2C SCL Low Timeout Register Low */ +#define I2C_SLTL_SSLT_MASK (0xFFU) +#define I2C_SLTL_SSLT_SHIFT (0U) +#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40066000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40067000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x400E6000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1, I2C2 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[24]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ + __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x7U) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x30000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0xFU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0xF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x7U) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x30000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0xFU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0xF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + +/*! @name MCR - SAI MCLK Control Register */ +#define I2S_MCR_MICS_MASK (0x3000000U) +#define I2S_MCR_MICS_SHIFT (24U) +#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +#define I2S_MCR_DUF_MASK (0x80000000U) +#define I2S_MCR_DUF_SHIFT (31U) +#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) + +/*! @name MDR - SAI MCLK Divide Register */ +#define I2S_MDR_DIVIDE_MASK (0xFFFU) +#define I2S_MDR_DIVIDE_SHIFT (0U) +#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) +#define I2S_MDR_FRACT_MASK (0xFF000U) +#define I2S_MDR_FRACT_SHIFT (12U) +#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x4002F000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { I2S0_Rx_IRQn } +#define I2S_TX_IRQS { I2S0_Tx_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer + * @{ + */ + +/** LLWU - Register Layout Typedef */ +typedef struct { + __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ + __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ + __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ + __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ + __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ + __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ + __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ + __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ + __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ + __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ + __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */ +} LLWU_Type; + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/*! @name PE1 - LLWU Pin Enable 1 register */ +#define LLWU_PE1_WUPE0_MASK (0x3U) +#define LLWU_PE1_WUPE0_SHIFT (0U) +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) +#define LLWU_PE1_WUPE1_MASK (0xCU) +#define LLWU_PE1_WUPE1_SHIFT (2U) +#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) +#define LLWU_PE1_WUPE2_MASK (0x30U) +#define LLWU_PE1_WUPE2_SHIFT (4U) +#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) +#define LLWU_PE1_WUPE3_MASK (0xC0U) +#define LLWU_PE1_WUPE3_SHIFT (6U) +#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) + +/*! @name PE2 - LLWU Pin Enable 2 register */ +#define LLWU_PE2_WUPE4_MASK (0x3U) +#define LLWU_PE2_WUPE4_SHIFT (0U) +#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) +#define LLWU_PE2_WUPE5_MASK (0xCU) +#define LLWU_PE2_WUPE5_SHIFT (2U) +#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) +#define LLWU_PE2_WUPE6_MASK (0x30U) +#define LLWU_PE2_WUPE6_SHIFT (4U) +#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) +#define LLWU_PE2_WUPE7_MASK (0xC0U) +#define LLWU_PE2_WUPE7_SHIFT (6U) +#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) + +/*! @name PE3 - LLWU Pin Enable 3 register */ +#define LLWU_PE3_WUPE8_MASK (0x3U) +#define LLWU_PE3_WUPE8_SHIFT (0U) +#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) +#define LLWU_PE3_WUPE9_MASK (0xCU) +#define LLWU_PE3_WUPE9_SHIFT (2U) +#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) +#define LLWU_PE3_WUPE10_MASK (0x30U) +#define LLWU_PE3_WUPE10_SHIFT (4U) +#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) +#define LLWU_PE3_WUPE11_MASK (0xC0U) +#define LLWU_PE3_WUPE11_SHIFT (6U) +#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) + +/*! @name PE4 - LLWU Pin Enable 4 register */ +#define LLWU_PE4_WUPE12_MASK (0x3U) +#define LLWU_PE4_WUPE12_SHIFT (0U) +#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) +#define LLWU_PE4_WUPE13_MASK (0xCU) +#define LLWU_PE4_WUPE13_SHIFT (2U) +#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) +#define LLWU_PE4_WUPE14_MASK (0x30U) +#define LLWU_PE4_WUPE14_SHIFT (4U) +#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) +#define LLWU_PE4_WUPE15_MASK (0xC0U) +#define LLWU_PE4_WUPE15_SHIFT (6U) +#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) + +/*! @name ME - LLWU Module Enable register */ +#define LLWU_ME_WUME0_MASK (0x1U) +#define LLWU_ME_WUME0_SHIFT (0U) +#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) +#define LLWU_ME_WUME1_MASK (0x2U) +#define LLWU_ME_WUME1_SHIFT (1U) +#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) +#define LLWU_ME_WUME2_MASK (0x4U) +#define LLWU_ME_WUME2_SHIFT (2U) +#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) +#define LLWU_ME_WUME3_MASK (0x8U) +#define LLWU_ME_WUME3_SHIFT (3U) +#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) +#define LLWU_ME_WUME4_MASK (0x10U) +#define LLWU_ME_WUME4_SHIFT (4U) +#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) +#define LLWU_ME_WUME5_MASK (0x20U) +#define LLWU_ME_WUME5_SHIFT (5U) +#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) +#define LLWU_ME_WUME6_MASK (0x40U) +#define LLWU_ME_WUME6_SHIFT (6U) +#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) +#define LLWU_ME_WUME7_MASK (0x80U) +#define LLWU_ME_WUME7_SHIFT (7U) +#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) + +/*! @name F1 - LLWU Flag 1 register */ +#define LLWU_F1_WUF0_MASK (0x1U) +#define LLWU_F1_WUF0_SHIFT (0U) +#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) +#define LLWU_F1_WUF1_MASK (0x2U) +#define LLWU_F1_WUF1_SHIFT (1U) +#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) +#define LLWU_F1_WUF2_MASK (0x4U) +#define LLWU_F1_WUF2_SHIFT (2U) +#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) +#define LLWU_F1_WUF3_MASK (0x8U) +#define LLWU_F1_WUF3_SHIFT (3U) +#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) +#define LLWU_F1_WUF4_MASK (0x10U) +#define LLWU_F1_WUF4_SHIFT (4U) +#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) +#define LLWU_F1_WUF5_MASK (0x20U) +#define LLWU_F1_WUF5_SHIFT (5U) +#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) +#define LLWU_F1_WUF6_MASK (0x40U) +#define LLWU_F1_WUF6_SHIFT (6U) +#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) +#define LLWU_F1_WUF7_MASK (0x80U) +#define LLWU_F1_WUF7_SHIFT (7U) +#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) + +/*! @name F2 - LLWU Flag 2 register */ +#define LLWU_F2_WUF8_MASK (0x1U) +#define LLWU_F2_WUF8_SHIFT (0U) +#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) +#define LLWU_F2_WUF9_MASK (0x2U) +#define LLWU_F2_WUF9_SHIFT (1U) +#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) +#define LLWU_F2_WUF10_MASK (0x4U) +#define LLWU_F2_WUF10_SHIFT (2U) +#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) +#define LLWU_F2_WUF11_MASK (0x8U) +#define LLWU_F2_WUF11_SHIFT (3U) +#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) +#define LLWU_F2_WUF12_MASK (0x10U) +#define LLWU_F2_WUF12_SHIFT (4U) +#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) +#define LLWU_F2_WUF13_MASK (0x20U) +#define LLWU_F2_WUF13_SHIFT (5U) +#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) +#define LLWU_F2_WUF14_MASK (0x40U) +#define LLWU_F2_WUF14_SHIFT (6U) +#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) +#define LLWU_F2_WUF15_MASK (0x80U) +#define LLWU_F2_WUF15_SHIFT (7U) +#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) + +/*! @name F3 - LLWU Flag 3 register */ +#define LLWU_F3_MWUF0_MASK (0x1U) +#define LLWU_F3_MWUF0_SHIFT (0U) +#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) +#define LLWU_F3_MWUF1_MASK (0x2U) +#define LLWU_F3_MWUF1_SHIFT (1U) +#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) +#define LLWU_F3_MWUF2_MASK (0x4U) +#define LLWU_F3_MWUF2_SHIFT (2U) +#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) +#define LLWU_F3_MWUF3_MASK (0x8U) +#define LLWU_F3_MWUF3_SHIFT (3U) +#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) +#define LLWU_F3_MWUF4_MASK (0x10U) +#define LLWU_F3_MWUF4_SHIFT (4U) +#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) +#define LLWU_F3_MWUF5_MASK (0x20U) +#define LLWU_F3_MWUF5_SHIFT (5U) +#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) +#define LLWU_F3_MWUF6_MASK (0x40U) +#define LLWU_F3_MWUF6_SHIFT (6U) +#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) +#define LLWU_F3_MWUF7_MASK (0x80U) +#define LLWU_F3_MWUF7_SHIFT (7U) +#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) + +/*! @name FILT1 - LLWU Pin Filter 1 register */ +#define LLWU_FILT1_FILTSEL_MASK (0xFU) +#define LLWU_FILT1_FILTSEL_SHIFT (0U) +#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) +#define LLWU_FILT1_FILTE_MASK (0x60U) +#define LLWU_FILT1_FILTE_SHIFT (5U) +#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) +#define LLWU_FILT1_FILTF_MASK (0x80U) +#define LLWU_FILT1_FILTF_SHIFT (7U) +#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) + +/*! @name FILT2 - LLWU Pin Filter 2 register */ +#define LLWU_FILT2_FILTSEL_MASK (0xFU) +#define LLWU_FILT2_FILTSEL_SHIFT (0U) +#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) +#define LLWU_FILT2_FILTE_MASK (0x60U) +#define LLWU_FILT2_FILTE_SHIFT (5U) +#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) +#define LLWU_FILT2_FILTF_MASK (0x80U) +#define LLWU_FILT2_FILTF_SHIFT (7U) +#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) + +/*! @name RST - LLWU Reset Enable register */ +#define LLWU_RST_RSTFILT_MASK (0x1U) +#define LLWU_RST_RSTFILT_SHIFT (0U) +#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK) +#define LLWU_RST_LLRSTE_MASK (0x2U) +#define LLWU_RST_LLRSTE_SHIFT (1U) +#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK) + + +/*! + * @} + */ /* end of group LLWU_Register_Masks */ + + +/* LLWU - Peripheral instance base addresses */ +/** Peripheral LLWU base address */ +#define LLWU_BASE (0x4007C000u) +/** Peripheral LLWU base pointer */ +#define LLWU ((LLWU_Type *)LLWU_BASE) +/** Array initializer of LLWU peripheral base addresses */ +#define LLWU_BASE_ADDRS { LLWU_BASE } +/** Array initializer of LLWU peripheral base pointers */ +#define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } + +/*! + * @} + */ /* end of group LLWU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ + __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ + __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ + __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Low Power Timer Control Status Register */ +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +/*! @name PSR - Low Power Timer Prescale Register */ +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) + +/*! @name CMR - Low Power Timer Compare Register */ +#define LPTMR_CMR_COMPARE_MASK (0xFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) + +/*! @name CNR - Low Power Timer Counter Register */ +#define LPTMR_CNR_COUNTER_MASK (0xFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x40040000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer + * @{ + */ + +/** MCG - Register Layout Typedef */ +typedef struct { + __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ + __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ + __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ + __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ + __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ + __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ + __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ + uint8_t RESERVED_0[1]; + __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ + uint8_t RESERVED_1[1]; + __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ + __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ + __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ + __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ +} MCG_Type; + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/*! @name C1 - MCG Control 1 Register */ +#define MCG_C1_IREFSTEN_MASK (0x1U) +#define MCG_C1_IREFSTEN_SHIFT (0U) +#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) +#define MCG_C1_IRCLKEN_MASK (0x2U) +#define MCG_C1_IRCLKEN_SHIFT (1U) +#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) +#define MCG_C1_IREFS_MASK (0x4U) +#define MCG_C1_IREFS_SHIFT (2U) +#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) +#define MCG_C1_FRDIV_MASK (0x38U) +#define MCG_C1_FRDIV_SHIFT (3U) +#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) +#define MCG_C1_CLKS_MASK (0xC0U) +#define MCG_C1_CLKS_SHIFT (6U) +#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) + +/*! @name C2 - MCG Control 2 Register */ +#define MCG_C2_IRCS_MASK (0x1U) +#define MCG_C2_IRCS_SHIFT (0U) +#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) +#define MCG_C2_LP_MASK (0x2U) +#define MCG_C2_LP_SHIFT (1U) +#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) +#define MCG_C2_EREFS_MASK (0x4U) +#define MCG_C2_EREFS_SHIFT (2U) +#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) +#define MCG_C2_HGO_MASK (0x8U) +#define MCG_C2_HGO_SHIFT (3U) +#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) +#define MCG_C2_RANGE_MASK (0x30U) +#define MCG_C2_RANGE_SHIFT (4U) +#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) +#define MCG_C2_FCFTRIM_MASK (0x40U) +#define MCG_C2_FCFTRIM_SHIFT (6U) +#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) +#define MCG_C2_LOCRE0_MASK (0x80U) +#define MCG_C2_LOCRE0_SHIFT (7U) +#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) + +/*! @name C3 - MCG Control 3 Register */ +#define MCG_C3_SCTRIM_MASK (0xFFU) +#define MCG_C3_SCTRIM_SHIFT (0U) +#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) + +/*! @name C4 - MCG Control 4 Register */ +#define MCG_C4_SCFTRIM_MASK (0x1U) +#define MCG_C4_SCFTRIM_SHIFT (0U) +#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) +#define MCG_C4_FCTRIM_MASK (0x1EU) +#define MCG_C4_FCTRIM_SHIFT (1U) +#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) +#define MCG_C4_DRST_DRS_MASK (0x60U) +#define MCG_C4_DRST_DRS_SHIFT (5U) +#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) +#define MCG_C4_DMX32_MASK (0x80U) +#define MCG_C4_DMX32_SHIFT (7U) +#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) + +/*! @name C5 - MCG Control 5 Register */ +#define MCG_C5_PRDIV0_MASK (0x1FU) +#define MCG_C5_PRDIV0_SHIFT (0U) +#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) +#define MCG_C5_PLLSTEN0_MASK (0x20U) +#define MCG_C5_PLLSTEN0_SHIFT (5U) +#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) +#define MCG_C5_PLLCLKEN0_MASK (0x40U) +#define MCG_C5_PLLCLKEN0_SHIFT (6U) +#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) + +/*! @name C6 - MCG Control 6 Register */ +#define MCG_C6_VDIV0_MASK (0x1FU) +#define MCG_C6_VDIV0_SHIFT (0U) +#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) +#define MCG_C6_CME0_MASK (0x20U) +#define MCG_C6_CME0_SHIFT (5U) +#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) +#define MCG_C6_PLLS_MASK (0x40U) +#define MCG_C6_PLLS_SHIFT (6U) +#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) +#define MCG_C6_LOLIE0_MASK (0x80U) +#define MCG_C6_LOLIE0_SHIFT (7U) +#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) + +/*! @name S - MCG Status Register */ +#define MCG_S_IRCST_MASK (0x1U) +#define MCG_S_IRCST_SHIFT (0U) +#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) +#define MCG_S_OSCINIT0_MASK (0x2U) +#define MCG_S_OSCINIT0_SHIFT (1U) +#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) +#define MCG_S_CLKST_MASK (0xCU) +#define MCG_S_CLKST_SHIFT (2U) +#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) +#define MCG_S_IREFST_MASK (0x10U) +#define MCG_S_IREFST_SHIFT (4U) +#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) +#define MCG_S_PLLST_MASK (0x20U) +#define MCG_S_PLLST_SHIFT (5U) +#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) +#define MCG_S_LOCK0_MASK (0x40U) +#define MCG_S_LOCK0_SHIFT (6U) +#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) +#define MCG_S_LOLS0_MASK (0x80U) +#define MCG_S_LOLS0_SHIFT (7U) +#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) + +/*! @name SC - MCG Status and Control Register */ +#define MCG_SC_LOCS0_MASK (0x1U) +#define MCG_SC_LOCS0_SHIFT (0U) +#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) +#define MCG_SC_FCRDIV_MASK (0xEU) +#define MCG_SC_FCRDIV_SHIFT (1U) +#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) +#define MCG_SC_FLTPRSRV_MASK (0x10U) +#define MCG_SC_FLTPRSRV_SHIFT (4U) +#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) +#define MCG_SC_ATMF_MASK (0x20U) +#define MCG_SC_ATMF_SHIFT (5U) +#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) +#define MCG_SC_ATMS_MASK (0x40U) +#define MCG_SC_ATMS_SHIFT (6U) +#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) +#define MCG_SC_ATME_MASK (0x80U) +#define MCG_SC_ATME_SHIFT (7U) +#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) + +/*! @name ATCVH - MCG Auto Trim Compare Value High Register */ +#define MCG_ATCVH_ATCVH_MASK (0xFFU) +#define MCG_ATCVH_ATCVH_SHIFT (0U) +#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) + +/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ +#define MCG_ATCVL_ATCVL_MASK (0xFFU) +#define MCG_ATCVL_ATCVL_SHIFT (0U) +#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) + +/*! @name C7 - MCG Control 7 Register */ +#define MCG_C7_OSCSEL_MASK (0x3U) +#define MCG_C7_OSCSEL_SHIFT (0U) +#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) + +/*! @name C8 - MCG Control 8 Register */ +#define MCG_C8_LOCS1_MASK (0x1U) +#define MCG_C8_LOCS1_SHIFT (0U) +#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) +#define MCG_C8_CME1_MASK (0x20U) +#define MCG_C8_CME1_SHIFT (5U) +#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) +#define MCG_C8_LOLRE_MASK (0x40U) +#define MCG_C8_LOLRE_SHIFT (6U) +#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) +#define MCG_C8_LOCRE1_MASK (0x80U) +#define MCG_C8_LOCRE1_SHIFT (7U) +#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) + + +/*! + * @} + */ /* end of group MCG_Register_Masks */ + + +/* MCG - Peripheral instance base addresses */ +/** Peripheral MCG base address */ +#define MCG_BASE (0x40064000u) +/** Peripheral MCG base pointer */ +#define MCG ((MCG_Type *)MCG_BASE) +/** Array initializer of MCG peripheral base addresses */ +#define MCG_BASE_ADDRS { MCG_BASE } +/** Array initializer of MCG peripheral base pointers */ +#define MCG_BASE_PTRS { MCG } + +/*! + * @} + */ /* end of group MCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + __IO uint32_t CR; /**< Control Register, offset: 0xC */ + __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */ + __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */ + __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ +} MCM_Type; + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +#define MCM_PLASC_ASC_MASK (0xFFU) +#define MCM_PLASC_ASC_SHIFT (0U) +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) + +/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +#define MCM_PLAMC_AMC_MASK (0xFFU) +#define MCM_PLAMC_AMC_SHIFT (0U) +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) + +/*! @name CR - Control Register */ +#define MCM_CR_SRAMUAP_MASK (0x3000000U) +#define MCM_CR_SRAMUAP_SHIFT (24U) +#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK) +#define MCM_CR_SRAMUWP_MASK (0x4000000U) +#define MCM_CR_SRAMUWP_SHIFT (26U) +#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK) +#define MCM_CR_SRAMLAP_MASK (0x30000000U) +#define MCM_CR_SRAMLAP_SHIFT (28U) +#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK) +#define MCM_CR_SRAMLWP_MASK (0x40000000U) +#define MCM_CR_SRAMLWP_SHIFT (30U) +#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK) + +/*! @name ISCR - Interrupt Status Register */ +#define MCM_ISCR_IRQ_MASK (0x2U) +#define MCM_ISCR_IRQ_SHIFT (1U) +#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK) +#define MCM_ISCR_NMI_MASK (0x4U) +#define MCM_ISCR_NMI_SHIFT (2U) +#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK) +#define MCM_ISCR_DHREQ_MASK (0x8U) +#define MCM_ISCR_DHREQ_SHIFT (3U) +#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK) +#define MCM_ISCR_FIOC_MASK (0x100U) +#define MCM_ISCR_FIOC_SHIFT (8U) +#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) +#define MCM_ISCR_FDZC_MASK (0x200U) +#define MCM_ISCR_FDZC_SHIFT (9U) +#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) +#define MCM_ISCR_FOFC_MASK (0x400U) +#define MCM_ISCR_FOFC_SHIFT (10U) +#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) +#define MCM_ISCR_FUFC_MASK (0x800U) +#define MCM_ISCR_FUFC_SHIFT (11U) +#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) +#define MCM_ISCR_FIXC_MASK (0x1000U) +#define MCM_ISCR_FIXC_SHIFT (12U) +#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) +#define MCM_ISCR_FIDC_MASK (0x8000U) +#define MCM_ISCR_FIDC_SHIFT (15U) +#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) +#define MCM_ISCR_FIOCE_MASK (0x1000000U) +#define MCM_ISCR_FIOCE_SHIFT (24U) +#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) +#define MCM_ISCR_FDZCE_MASK (0x2000000U) +#define MCM_ISCR_FDZCE_SHIFT (25U) +#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) +#define MCM_ISCR_FOFCE_MASK (0x4000000U) +#define MCM_ISCR_FOFCE_SHIFT (26U) +#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) +#define MCM_ISCR_FUFCE_MASK (0x8000000U) +#define MCM_ISCR_FUFCE_SHIFT (27U) +#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) +#define MCM_ISCR_FIXCE_MASK (0x10000000U) +#define MCM_ISCR_FIXCE_SHIFT (28U) +#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) +#define MCM_ISCR_FIDCE_MASK (0x80000000U) +#define MCM_ISCR_FIDCE_SHIFT (31U) +#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) + +/*! @name ETBCC - ETB Counter Control register */ +#define MCM_ETBCC_CNTEN_MASK (0x1U) +#define MCM_ETBCC_CNTEN_SHIFT (0U) +#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK) +#define MCM_ETBCC_RSPT_MASK (0x6U) +#define MCM_ETBCC_RSPT_SHIFT (1U) +#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK) +#define MCM_ETBCC_RLRQ_MASK (0x8U) +#define MCM_ETBCC_RLRQ_SHIFT (3U) +#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK) +#define MCM_ETBCC_ETDIS_MASK (0x10U) +#define MCM_ETBCC_ETDIS_SHIFT (4U) +#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK) +#define MCM_ETBCC_ITDIS_MASK (0x20U) +#define MCM_ETBCC_ITDIS_SHIFT (5U) +#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK) + +/*! @name ETBRL - ETB Reload register */ +#define MCM_ETBRL_RELOAD_MASK (0x7FFU) +#define MCM_ETBRL_RELOAD_SHIFT (0U) +#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK) + +/*! @name ETBCNT - ETB Counter Value register */ +#define MCM_ETBCNT_COUNTER_MASK (0x7FFU) +#define MCM_ETBCNT_COUNTER_SHIFT (0U) +#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK) + +/*! @name PID - Process ID register */ +#define MCM_PID_PID_MASK (0xFFU) +#define MCM_PID_PID_SHIFT (0U) +#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) + + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base address */ +#define MCM_BASE (0xE0080000u) +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +/** Array initializer of MCM peripheral base addresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } +/** Interrupt vectors for the MCM peripheral type */ +#define MCM_IRQS { MCM_IRQn } + +/*! + * @} + */ /* end of group MCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MPU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer + * @{ + */ + +/** MPU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + struct { /* offset: 0x10, array step: 0x8 */ + __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ + __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ + } SP[5]; + uint8_t RESERVED_1[968]; + __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ + uint8_t RESERVED_2[832]; + __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ +} MPU_Type; + +/* ---------------------------------------------------------------------------- + -- MPU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MPU_Register_Masks MPU Register Masks + * @{ + */ + +/*! @name CESR - Control/Error Status Register */ +#define MPU_CESR_VLD_MASK (0x1U) +#define MPU_CESR_VLD_SHIFT (0U) +#define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK) +#define MPU_CESR_NRGD_MASK (0xF00U) +#define MPU_CESR_NRGD_SHIFT (8U) +#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK) +#define MPU_CESR_NSP_MASK (0xF000U) +#define MPU_CESR_NSP_SHIFT (12U) +#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK) +#define MPU_CESR_HRL_MASK (0xF0000U) +#define MPU_CESR_HRL_SHIFT (16U) +#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK) +#define MPU_CESR_SPERR_MASK (0xF8000000U) +#define MPU_CESR_SPERR_SHIFT (27U) +#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK) + +/*! @name EAR - Error Address Register, slave port n */ +#define MPU_EAR_EADDR_MASK (0xFFFFFFFFU) +#define MPU_EAR_EADDR_SHIFT (0U) +#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK) + +/* The count of MPU_EAR */ +#define MPU_EAR_COUNT (5U) + +/*! @name EDR - Error Detail Register, slave port n */ +#define MPU_EDR_ERW_MASK (0x1U) +#define MPU_EDR_ERW_SHIFT (0U) +#define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK) +#define MPU_EDR_EATTR_MASK (0xEU) +#define MPU_EDR_EATTR_SHIFT (1U) +#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK) +#define MPU_EDR_EMN_MASK (0xF0U) +#define MPU_EDR_EMN_SHIFT (4U) +#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK) +#define MPU_EDR_EPID_MASK (0xFF00U) +#define MPU_EDR_EPID_SHIFT (8U) +#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK) +#define MPU_EDR_EACD_MASK (0xFFFF0000U) +#define MPU_EDR_EACD_SHIFT (16U) +#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK) + +/* The count of MPU_EDR */ +#define MPU_EDR_COUNT (5U) + +/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ +#define MPU_WORD_VLD_MASK (0x1U) +#define MPU_WORD_VLD_SHIFT (0U) +#define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK) +#define MPU_WORD_M0UM_MASK (0x7U) +#define MPU_WORD_M0UM_SHIFT (0U) +#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK) +#define MPU_WORD_M0SM_MASK (0x18U) +#define MPU_WORD_M0SM_SHIFT (3U) +#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK) +#define MPU_WORD_M0PE_MASK (0x20U) +#define MPU_WORD_M0PE_SHIFT (5U) +#define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK) +#define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) +#define MPU_WORD_ENDADDR_SHIFT (5U) +#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK) +#define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) +#define MPU_WORD_SRTADDR_SHIFT (5U) +#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK) +#define MPU_WORD_M1UM_MASK (0x1C0U) +#define MPU_WORD_M1UM_SHIFT (6U) +#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK) +#define MPU_WORD_M1SM_MASK (0x600U) +#define MPU_WORD_M1SM_SHIFT (9U) +#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK) +#define MPU_WORD_M1PE_MASK (0x800U) +#define MPU_WORD_M1PE_SHIFT (11U) +#define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK) +#define MPU_WORD_M2UM_MASK (0x7000U) +#define MPU_WORD_M2UM_SHIFT (12U) +#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK) +#define MPU_WORD_M2SM_MASK (0x18000U) +#define MPU_WORD_M2SM_SHIFT (15U) +#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK) +#define MPU_WORD_PIDMASK_MASK (0xFF0000U) +#define MPU_WORD_PIDMASK_SHIFT (16U) +#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK) +#define MPU_WORD_M2PE_MASK (0x20000U) +#define MPU_WORD_M2PE_SHIFT (17U) +#define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK) +#define MPU_WORD_M3UM_MASK (0x1C0000U) +#define MPU_WORD_M3UM_SHIFT (18U) +#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK) +#define MPU_WORD_M3SM_MASK (0x600000U) +#define MPU_WORD_M3SM_SHIFT (21U) +#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK) +#define MPU_WORD_M3PE_MASK (0x800000U) +#define MPU_WORD_M3PE_SHIFT (23U) +#define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK) +#define MPU_WORD_PID_MASK (0xFF000000U) +#define MPU_WORD_PID_SHIFT (24U) +#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK) +#define MPU_WORD_M4WE_MASK (0x1000000U) +#define MPU_WORD_M4WE_SHIFT (24U) +#define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK) +#define MPU_WORD_M4RE_MASK (0x2000000U) +#define MPU_WORD_M4RE_SHIFT (25U) +#define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK) +#define MPU_WORD_M5WE_MASK (0x4000000U) +#define MPU_WORD_M5WE_SHIFT (26U) +#define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK) +#define MPU_WORD_M5RE_MASK (0x8000000U) +#define MPU_WORD_M5RE_SHIFT (27U) +#define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK) +#define MPU_WORD_M6WE_MASK (0x10000000U) +#define MPU_WORD_M6WE_SHIFT (28U) +#define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK) +#define MPU_WORD_M6RE_MASK (0x20000000U) +#define MPU_WORD_M6RE_SHIFT (29U) +#define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK) +#define MPU_WORD_M7WE_MASK (0x40000000U) +#define MPU_WORD_M7WE_SHIFT (30U) +#define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK) +#define MPU_WORD_M7RE_MASK (0x80000000U) +#define MPU_WORD_M7RE_SHIFT (31U) +#define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK) + +/* The count of MPU_WORD */ +#define MPU_WORD_COUNT (12U) + +/* The count of MPU_WORD */ +#define MPU_WORD_COUNT2 (4U) + +/*! @name RGDAAC - Region Descriptor Alternate Access Control n */ +#define MPU_RGDAAC_M0UM_MASK (0x7U) +#define MPU_RGDAAC_M0UM_SHIFT (0U) +#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK) +#define MPU_RGDAAC_M0SM_MASK (0x18U) +#define MPU_RGDAAC_M0SM_SHIFT (3U) +#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK) +#define MPU_RGDAAC_M0PE_MASK (0x20U) +#define MPU_RGDAAC_M0PE_SHIFT (5U) +#define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK) +#define MPU_RGDAAC_M1UM_MASK (0x1C0U) +#define MPU_RGDAAC_M1UM_SHIFT (6U) +#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK) +#define MPU_RGDAAC_M1SM_MASK (0x600U) +#define MPU_RGDAAC_M1SM_SHIFT (9U) +#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK) +#define MPU_RGDAAC_M1PE_MASK (0x800U) +#define MPU_RGDAAC_M1PE_SHIFT (11U) +#define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK) +#define MPU_RGDAAC_M2UM_MASK (0x7000U) +#define MPU_RGDAAC_M2UM_SHIFT (12U) +#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK) +#define MPU_RGDAAC_M2SM_MASK (0x18000U) +#define MPU_RGDAAC_M2SM_SHIFT (15U) +#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK) +#define MPU_RGDAAC_M2PE_MASK (0x20000U) +#define MPU_RGDAAC_M2PE_SHIFT (17U) +#define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK) +#define MPU_RGDAAC_M3UM_MASK (0x1C0000U) +#define MPU_RGDAAC_M3UM_SHIFT (18U) +#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK) +#define MPU_RGDAAC_M3SM_MASK (0x600000U) +#define MPU_RGDAAC_M3SM_SHIFT (21U) +#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK) +#define MPU_RGDAAC_M3PE_MASK (0x800000U) +#define MPU_RGDAAC_M3PE_SHIFT (23U) +#define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK) +#define MPU_RGDAAC_M4WE_MASK (0x1000000U) +#define MPU_RGDAAC_M4WE_SHIFT (24U) +#define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK) +#define MPU_RGDAAC_M4RE_MASK (0x2000000U) +#define MPU_RGDAAC_M4RE_SHIFT (25U) +#define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK) +#define MPU_RGDAAC_M5WE_MASK (0x4000000U) +#define MPU_RGDAAC_M5WE_SHIFT (26U) +#define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK) +#define MPU_RGDAAC_M5RE_MASK (0x8000000U) +#define MPU_RGDAAC_M5RE_SHIFT (27U) +#define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK) +#define MPU_RGDAAC_M6WE_MASK (0x10000000U) +#define MPU_RGDAAC_M6WE_SHIFT (28U) +#define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK) +#define MPU_RGDAAC_M6RE_MASK (0x20000000U) +#define MPU_RGDAAC_M6RE_SHIFT (29U) +#define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK) +#define MPU_RGDAAC_M7WE_MASK (0x40000000U) +#define MPU_RGDAAC_M7WE_SHIFT (30U) +#define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK) +#define MPU_RGDAAC_M7RE_MASK (0x80000000U) +#define MPU_RGDAAC_M7RE_SHIFT (31U) +#define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK) + +/* The count of MPU_RGDAAC */ +#define MPU_RGDAAC_COUNT (12U) + + +/*! + * @} + */ /* end of group MPU_Register_Masks */ + + +/* MPU - Peripheral instance base addresses */ +/** Peripheral MPU base address */ +#define MPU_BASE (0x4000D000u) +/** Peripheral MPU base pointer */ +#define MPU ((MPU_Type *)MPU_BASE) +/** Array initializer of MPU peripheral base addresses */ +#define MPU_BASE_ADDRS { MPU_BASE } +/** Array initializer of MPU peripheral base pointers */ +#define MPU_BASE_PTRS { MPU } + +/*! + * @} + */ /* end of group MPU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer + * @{ + */ + +/** NV - Register Layout Typedef */ +typedef struct { + __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ + __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ + __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ + __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ + __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ + __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ + __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ + __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ + __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ + __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ + __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ + __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ + __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ + __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ + __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ + __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ +} NV_Type; + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/*! @name BACKKEY3 - Backdoor Comparison Key 3. */ +#define NV_BACKKEY3_KEY_MASK (0xFFU) +#define NV_BACKKEY3_KEY_SHIFT (0U) +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) + +/*! @name BACKKEY2 - Backdoor Comparison Key 2. */ +#define NV_BACKKEY2_KEY_MASK (0xFFU) +#define NV_BACKKEY2_KEY_SHIFT (0U) +#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) + +/*! @name BACKKEY1 - Backdoor Comparison Key 1. */ +#define NV_BACKKEY1_KEY_MASK (0xFFU) +#define NV_BACKKEY1_KEY_SHIFT (0U) +#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) + +/*! @name BACKKEY0 - Backdoor Comparison Key 0. */ +#define NV_BACKKEY0_KEY_MASK (0xFFU) +#define NV_BACKKEY0_KEY_SHIFT (0U) +#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) + +/*! @name BACKKEY7 - Backdoor Comparison Key 7. */ +#define NV_BACKKEY7_KEY_MASK (0xFFU) +#define NV_BACKKEY7_KEY_SHIFT (0U) +#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) + +/*! @name BACKKEY6 - Backdoor Comparison Key 6. */ +#define NV_BACKKEY6_KEY_MASK (0xFFU) +#define NV_BACKKEY6_KEY_SHIFT (0U) +#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) + +/*! @name BACKKEY5 - Backdoor Comparison Key 5. */ +#define NV_BACKKEY5_KEY_MASK (0xFFU) +#define NV_BACKKEY5_KEY_SHIFT (0U) +#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) + +/*! @name BACKKEY4 - Backdoor Comparison Key 4. */ +#define NV_BACKKEY4_KEY_MASK (0xFFU) +#define NV_BACKKEY4_KEY_SHIFT (0U) +#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) + +/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ +#define NV_FPROT3_PROT_MASK (0xFFU) +#define NV_FPROT3_PROT_SHIFT (0U) +#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ +#define NV_FPROT2_PROT_MASK (0xFFU) +#define NV_FPROT2_PROT_SHIFT (0U) +#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ +#define NV_FPROT1_PROT_MASK (0xFFU) +#define NV_FPROT1_PROT_SHIFT (0U) +#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ +#define NV_FPROT0_PROT_MASK (0xFFU) +#define NV_FPROT0_PROT_SHIFT (0U) +#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) + +/*! @name FSEC - Non-volatile Flash Security Register */ +#define NV_FSEC_SEC_MASK (0x3U) +#define NV_FSEC_SEC_SHIFT (0U) +#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) +#define NV_FSEC_FSLACC_MASK (0xCU) +#define NV_FSEC_FSLACC_SHIFT (2U) +#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) +#define NV_FSEC_MEEN_MASK (0x30U) +#define NV_FSEC_MEEN_SHIFT (4U) +#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) +#define NV_FSEC_KEYEN_MASK (0xC0U) +#define NV_FSEC_KEYEN_SHIFT (6U) +#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) + +/*! @name FOPT - Non-volatile Flash Option Register */ +#define NV_FOPT_LPBOOT_MASK (0x1U) +#define NV_FOPT_LPBOOT_SHIFT (0U) +#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) +#define NV_FOPT_EZPORT_DIS_MASK (0x2U) +#define NV_FOPT_EZPORT_DIS_SHIFT (1U) +#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) + +/*! @name FEPROT - Non-volatile EERAM Protection Register */ +#define NV_FEPROT_EPROT_MASK (0xFFU) +#define NV_FEPROT_EPROT_SHIFT (0U) +#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) + +/*! @name FDPROT - Non-volatile D-Flash Protection Register */ +#define NV_FDPROT_DPROT_MASK (0xFFU) +#define NV_FDPROT_DPROT_SHIFT (0U) +#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) + + +/*! + * @} + */ /* end of group NV_Register_Masks */ + + +/* NV - Peripheral instance base addresses */ +/** Peripheral FTFE_FlashConfig base address */ +#define FTFE_FlashConfig_BASE (0x400u) +/** Peripheral FTFE_FlashConfig base pointer */ +#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE) +/** Array initializer of NV peripheral base addresses */ +#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE } +/** Array initializer of NV peripheral base pointers */ +#define NV_BASE_PTRS { FTFE_FlashConfig } + +/*! + * @} + */ /* end of group NV_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer + * @{ + */ + +/** OSC - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ +} OSC_Type; + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/*! @name CR - OSC Control Register */ +#define OSC_CR_SC16P_MASK (0x1U) +#define OSC_CR_SC16P_SHIFT (0U) +#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) +#define OSC_CR_SC8P_MASK (0x2U) +#define OSC_CR_SC8P_SHIFT (1U) +#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) +#define OSC_CR_SC4P_MASK (0x4U) +#define OSC_CR_SC4P_SHIFT (2U) +#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) +#define OSC_CR_SC2P_MASK (0x8U) +#define OSC_CR_SC2P_SHIFT (3U) +#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) +#define OSC_CR_EREFSTEN_MASK (0x20U) +#define OSC_CR_EREFSTEN_SHIFT (5U) +#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) +#define OSC_CR_ERCLKEN_MASK (0x80U) +#define OSC_CR_ERCLKEN_SHIFT (7U) +#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) + + +/*! + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC base address */ +#define OSC_BASE (0x40065000u) +/** Peripheral OSC base pointer */ +#define OSC ((OSC_Type *)OSC_BASE) +/** Array initializer of OSC peripheral base addresses */ +#define OSC_BASE_ADDRS { OSC_BASE } +/** Array initializer of OSC peripheral base pointers */ +#define OSC_BASE_PTRS { OSC } + +/*! + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer + * @{ + */ + +/** PDB - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ + __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ + __I uint32_t CNT; /**< Counter register, offset: 0x8 */ + __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ + __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ + uint8_t RESERVED_0[24]; + } CH[2]; + uint8_t RESERVED_0[240]; + struct { /* offset: 0x150, array step: 0x8 */ + __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ + __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ + } DAC[2]; + uint8_t RESERVED_1[48]; + __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ + __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ +} PDB_Type; + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/*! @name SC - Status and Control register */ +#define PDB_SC_LDOK_MASK (0x1U) +#define PDB_SC_LDOK_SHIFT (0U) +#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) +#define PDB_SC_CONT_MASK (0x2U) +#define PDB_SC_CONT_SHIFT (1U) +#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) +#define PDB_SC_MULT_MASK (0xCU) +#define PDB_SC_MULT_SHIFT (2U) +#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) +#define PDB_SC_PDBIE_MASK (0x20U) +#define PDB_SC_PDBIE_SHIFT (5U) +#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) +#define PDB_SC_PDBIF_MASK (0x40U) +#define PDB_SC_PDBIF_SHIFT (6U) +#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) +#define PDB_SC_PDBEN_MASK (0x80U) +#define PDB_SC_PDBEN_SHIFT (7U) +#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) +#define PDB_SC_TRGSEL_MASK (0xF00U) +#define PDB_SC_TRGSEL_SHIFT (8U) +#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) +#define PDB_SC_PRESCALER_MASK (0x7000U) +#define PDB_SC_PRESCALER_SHIFT (12U) +#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) +#define PDB_SC_DMAEN_MASK (0x8000U) +#define PDB_SC_DMAEN_SHIFT (15U) +#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) +#define PDB_SC_SWTRIG_MASK (0x10000U) +#define PDB_SC_SWTRIG_SHIFT (16U) +#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) +#define PDB_SC_PDBEIE_MASK (0x20000U) +#define PDB_SC_PDBEIE_SHIFT (17U) +#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) +#define PDB_SC_LDMOD_MASK (0xC0000U) +#define PDB_SC_LDMOD_SHIFT (18U) +#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) + +/*! @name MOD - Modulus register */ +#define PDB_MOD_MOD_MASK (0xFFFFU) +#define PDB_MOD_MOD_SHIFT (0U) +#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) + +/*! @name CNT - Counter register */ +#define PDB_CNT_CNT_MASK (0xFFFFU) +#define PDB_CNT_CNT_SHIFT (0U) +#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) + +/*! @name IDLY - Interrupt Delay register */ +#define PDB_IDLY_IDLY_MASK (0xFFFFU) +#define PDB_IDLY_IDLY_SHIFT (0U) +#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) + +/*! @name C1 - Channel n Control register 1 */ +#define PDB_C1_EN_MASK (0xFFU) +#define PDB_C1_EN_SHIFT (0U) +#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) +#define PDB_C1_TOS_MASK (0xFF00U) +#define PDB_C1_TOS_SHIFT (8U) +#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) +#define PDB_C1_BB_MASK (0xFF0000U) +#define PDB_C1_BB_SHIFT (16U) +#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) + +/* The count of PDB_C1 */ +#define PDB_C1_COUNT (2U) + +/*! @name S - Channel n Status register */ +#define PDB_S_ERR_MASK (0xFFU) +#define PDB_S_ERR_SHIFT (0U) +#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) +#define PDB_S_CF_MASK (0xFF0000U) +#define PDB_S_CF_SHIFT (16U) +#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) + +/* The count of PDB_S */ +#define PDB_S_COUNT (2U) + +/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ +#define PDB_DLY_DLY_MASK (0xFFFFU) +#define PDB_DLY_DLY_SHIFT (0U) +#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) + +/* The count of PDB_DLY */ +#define PDB_DLY_COUNT (2U) + +/* The count of PDB_DLY */ +#define PDB_DLY_COUNT2 (2U) + +/*! @name INTC - DAC Interval Trigger n Control register */ +#define PDB_INTC_TOE_MASK (0x1U) +#define PDB_INTC_TOE_SHIFT (0U) +#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) +#define PDB_INTC_EXT_MASK (0x2U) +#define PDB_INTC_EXT_SHIFT (1U) +#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) + +/* The count of PDB_INTC */ +#define PDB_INTC_COUNT (2U) + +/*! @name INT - DAC Interval n register */ +#define PDB_INT_INT_MASK (0xFFFFU) +#define PDB_INT_INT_SHIFT (0U) +#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) + +/* The count of PDB_INT */ +#define PDB_INT_COUNT (2U) + +/*! @name POEN - Pulse-Out n Enable register */ +#define PDB_POEN_POEN_MASK (0xFFU) +#define PDB_POEN_POEN_SHIFT (0U) +#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) + +/*! @name PODLY - Pulse-Out n Delay register */ +#define PDB_PODLY_DLY2_MASK (0xFFFFU) +#define PDB_PODLY_DLY2_SHIFT (0U) +#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) +#define PDB_PODLY_DLY1_MASK (0xFFFF0000U) +#define PDB_PODLY_DLY1_SHIFT (16U) +#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) + +/* The count of PDB_PODLY */ +#define PDB_PODLY_COUNT (3U) + + +/*! + * @} + */ /* end of group PDB_Register_Masks */ + + +/* PDB - Peripheral instance base addresses */ +/** Peripheral PDB0 base address */ +#define PDB0_BASE (0x40036000u) +/** Peripheral PDB0 base pointer */ +#define PDB0 ((PDB_Type *)PDB0_BASE) +/** Array initializer of PDB peripheral base addresses */ +#define PDB_BASE_ADDRS { PDB0_BASE } +/** Array initializer of PDB peripheral base pointers */ +#define PDB_BASE_PTRS { PDB0 } +/** Interrupt vectors for the PDB peripheral type */ +#define PDB_IRQS { PDB0_IRQn } + +/*! + * @} + */ /* end of group PDB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[252]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) + +/*! @name LDVAL - Timer Load Value Register */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40037000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ + __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ + __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ +#define PMC_LVDSC1_LVDV_MASK (0x3U) +#define PMC_LVDSC1_LVDV_SHIFT (0U) +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) +#define PMC_LVDSC1_LVDRE_MASK (0x10U) +#define PMC_LVDSC1_LVDRE_SHIFT (4U) +#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) +#define PMC_LVDSC1_LVDIE_MASK (0x20U) +#define PMC_LVDSC1_LVDIE_SHIFT (5U) +#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) +#define PMC_LVDSC1_LVDACK_MASK (0x40U) +#define PMC_LVDSC1_LVDACK_SHIFT (6U) +#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) +#define PMC_LVDSC1_LVDF_MASK (0x80U) +#define PMC_LVDSC1_LVDF_SHIFT (7U) +#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) + +/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ +#define PMC_LVDSC2_LVWV_MASK (0x3U) +#define PMC_LVDSC2_LVWV_SHIFT (0U) +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) +#define PMC_LVDSC2_LVWIE_MASK (0x20U) +#define PMC_LVDSC2_LVWIE_SHIFT (5U) +#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) +#define PMC_LVDSC2_LVWACK_MASK (0x40U) +#define PMC_LVDSC2_LVWACK_SHIFT (6U) +#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) +#define PMC_LVDSC2_LVWF_MASK (0x80U) +#define PMC_LVDSC2_LVWF_SHIFT (7U) +#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) + +/*! @name REGSC - Regulator Status And Control register */ +#define PMC_REGSC_BGBE_MASK (0x1U) +#define PMC_REGSC_BGBE_SHIFT (0U) +#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) +#define PMC_REGSC_REGONS_MASK (0x4U) +#define PMC_REGSC_REGONS_SHIFT (2U) +#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) +#define PMC_REGSC_ACKISO_MASK (0x8U) +#define PMC_REGSC_ACKISO_SHIFT (3U) +#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) +#define PMC_REGSC_BGEN_MASK (0x10U) +#define PMC_REGSC_BGEN_SHIFT (4U) +#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +/** Peripheral PMC base address */ +#define PMC_BASE (0x4007D000u) +/** Peripheral PMC base pointer */ +#define PMC ((PMC_Type *)PMC_BASE) +/** Array initializer of PMC peripheral base addresses */ +#define PMC_BASE_ADDRS { PMC_BASE } +/** Array initializer of PMC peripheral base pointers */ +#define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { LVD_LVW_IRQn } + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ + __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ + __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ + uint8_t RESERVED_1[28]; + __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ + __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ + __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name PCR - Pin Control Register n */ +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) +#define PORT_PCR_SRE_MASK (0x4U) +#define PORT_PCR_SRE_SHIFT (2U) +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) +#define PORT_PCR_MUX_MASK (0x700U) +#define PORT_PCR_MUX_SHIFT (8U) +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +#define PORT_PCR_IRQC_MASK (0xF0000U) +#define PORT_PCR_IRQC_SHIFT (16U) +#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) +#define PORT_PCR_ISF_MASK (0x1000000U) +#define PORT_PCR_ISF_SHIFT (24U) +#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + +/*! @name GPCLR - Global Pin Control Low Register */ +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) +#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCLR_GPWE_SHIFT (16U) +#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) + +/*! @name GPCHR - Global Pin Control High Register */ +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) +#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCHR_GPWE_SHIFT (16U) +#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) + +/*! @name ISFR - Interrupt Status Flag Register */ +#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) +#define PORT_ISFR_ISF_SHIFT (0U) +#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) + +/*! @name DFER - Digital Filter Enable Register */ +#define PORT_DFER_DFE_MASK (0xFFFFFFFFU) +#define PORT_DFER_DFE_SHIFT (0U) +#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) + +/*! @name DFCR - Digital Filter Clock Register */ +#define PORT_DFCR_CS_MASK (0x1U) +#define PORT_DFCR_CS_SHIFT (0U) +#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) + +/*! @name DFWR - Digital Filter Width Register */ +#define PORT_DFWR_FILT_MASK (0x1FU) +#define PORT_DFWR_FILT_SHIFT (0U) +#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORTA base address */ +#define PORTA_BASE (0x40049000u) +/** Peripheral PORTA base pointer */ +#define PORTA ((PORT_Type *)PORTA_BASE) +/** Peripheral PORTB base address */ +#define PORTB_BASE (0x4004A000u) +/** Peripheral PORTB base pointer */ +#define PORTB ((PORT_Type *)PORTB_BASE) +/** Peripheral PORTC base address */ +#define PORTC_BASE (0x4004B000u) +/** Peripheral PORTC base pointer */ +#define PORTC ((PORT_Type *)PORTC_BASE) +/** Peripheral PORTD base address */ +#define PORTD_BASE (0x4004C000u) +/** Peripheral PORTD base pointer */ +#define PORTD ((PORT_Type *)PORTD_BASE) +/** Peripheral PORTE base address */ +#define PORTE_BASE (0x4004D000u) +/** Peripheral PORTE base pointer */ +#define PORTE ((PORT_Type *)PORTE_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer + * @{ + */ + +/** RCM - Register Layout Typedef */ +typedef struct { + __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ + __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ + uint8_t RESERVED_0[2]; + __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ + __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ + uint8_t RESERVED_1[1]; + __I uint8_t MR; /**< Mode Register, offset: 0x7 */ +} RCM_Type; + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/*! @name SRS0 - System Reset Status Register 0 */ +#define RCM_SRS0_WAKEUP_MASK (0x1U) +#define RCM_SRS0_WAKEUP_SHIFT (0U) +#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) +#define RCM_SRS0_LVD_MASK (0x2U) +#define RCM_SRS0_LVD_SHIFT (1U) +#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) +#define RCM_SRS0_LOC_MASK (0x4U) +#define RCM_SRS0_LOC_SHIFT (2U) +#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) +#define RCM_SRS0_LOL_MASK (0x8U) +#define RCM_SRS0_LOL_SHIFT (3U) +#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) +#define RCM_SRS0_WDOG_MASK (0x20U) +#define RCM_SRS0_WDOG_SHIFT (5U) +#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) +#define RCM_SRS0_PIN_MASK (0x40U) +#define RCM_SRS0_PIN_SHIFT (6U) +#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) +#define RCM_SRS0_POR_MASK (0x80U) +#define RCM_SRS0_POR_SHIFT (7U) +#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) + +/*! @name SRS1 - System Reset Status Register 1 */ +#define RCM_SRS1_JTAG_MASK (0x1U) +#define RCM_SRS1_JTAG_SHIFT (0U) +#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) +#define RCM_SRS1_LOCKUP_MASK (0x2U) +#define RCM_SRS1_LOCKUP_SHIFT (1U) +#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) +#define RCM_SRS1_SW_MASK (0x4U) +#define RCM_SRS1_SW_SHIFT (2U) +#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) +#define RCM_SRS1_MDM_AP_MASK (0x8U) +#define RCM_SRS1_MDM_AP_SHIFT (3U) +#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) +#define RCM_SRS1_EZPT_MASK (0x10U) +#define RCM_SRS1_EZPT_SHIFT (4U) +#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) +#define RCM_SRS1_SACKERR_MASK (0x20U) +#define RCM_SRS1_SACKERR_SHIFT (5U) +#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) + +/*! @name RPFC - Reset Pin Filter Control register */ +#define RCM_RPFC_RSTFLTSRW_MASK (0x3U) +#define RCM_RPFC_RSTFLTSRW_SHIFT (0U) +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) +#define RCM_RPFC_RSTFLTSS_MASK (0x4U) +#define RCM_RPFC_RSTFLTSS_SHIFT (2U) +#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) + +/*! @name RPFW - Reset Pin Filter Width register */ +#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) +#define RCM_RPFW_RSTFLTSEL_SHIFT (0U) +#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) + +/*! @name MR - Mode Register */ +#define RCM_MR_EZP_MS_MASK (0x2U) +#define RCM_MR_EZP_MS_SHIFT (1U) +#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) + + +/*! + * @} + */ /* end of group RCM_Register_Masks */ + + +/* RCM - Peripheral instance base addresses */ +/** Peripheral RCM base address */ +#define RCM_BASE (0x4007F000u) +/** Peripheral RCM base pointer */ +#define RCM ((RCM_Type *)RCM_BASE) +/** Array initializer of RCM peripheral base addresses */ +#define RCM_BASE_ADDRS { RCM_BASE } +/** Array initializer of RCM peripheral base pointers */ +#define RCM_BASE_PTRS { RCM } + +/*! + * @} + */ /* end of group RCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer + * @{ + */ + +/** RFSYS - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ +} RFSYS_Type; + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/*! @name REG - Register file register */ +#define RFSYS_REG_LL_MASK (0xFFU) +#define RFSYS_REG_LL_SHIFT (0U) +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) +#define RFSYS_REG_LH_MASK (0xFF00U) +#define RFSYS_REG_LH_SHIFT (8U) +#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) +#define RFSYS_REG_HL_MASK (0xFF0000U) +#define RFSYS_REG_HL_SHIFT (16U) +#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) +#define RFSYS_REG_HH_MASK (0xFF000000U) +#define RFSYS_REG_HH_SHIFT (24U) +#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) + +/* The count of RFSYS_REG */ +#define RFSYS_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFSYS_Register_Masks */ + + +/* RFSYS - Peripheral instance base addresses */ +/** Peripheral RFSYS base address */ +#define RFSYS_BASE (0x40041000u) +/** Peripheral RFSYS base pointer */ +#define RFSYS ((RFSYS_Type *)RFSYS_BASE) +/** Array initializer of RFSYS peripheral base addresses */ +#define RFSYS_BASE_ADDRS { RFSYS_BASE } +/** Array initializer of RFSYS peripheral base pointers */ +#define RFSYS_BASE_PTRS { RFSYS } + +/*! + * @} + */ /* end of group RFSYS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer + * @{ + */ + +/** RFVBAT - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ +} RFVBAT_Type; + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/*! @name REG - VBAT register file register */ +#define RFVBAT_REG_LL_MASK (0xFFU) +#define RFVBAT_REG_LL_SHIFT (0U) +#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) +#define RFVBAT_REG_LH_MASK (0xFF00U) +#define RFVBAT_REG_LH_SHIFT (8U) +#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) +#define RFVBAT_REG_HL_MASK (0xFF0000U) +#define RFVBAT_REG_HL_SHIFT (16U) +#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) +#define RFVBAT_REG_HH_MASK (0xFF000000U) +#define RFVBAT_REG_HH_SHIFT (24U) +#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) + +/* The count of RFVBAT_REG */ +#define RFVBAT_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFVBAT_Register_Masks */ + + +/* RFVBAT - Peripheral instance base addresses */ +/** Peripheral RFVBAT base address */ +#define RFVBAT_BASE (0x4003E000u) +/** Peripheral RFVBAT base pointer */ +#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) +/** Array initializer of RFVBAT peripheral base addresses */ +#define RFVBAT_BASE_ADDRS { RFVBAT_BASE } +/** Array initializer of RFVBAT peripheral base pointers */ +#define RFVBAT_BASE_PTRS { RFVBAT } + +/*! + * @} + */ /* end of group RFVBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ + __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ + __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ + __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name CR - RNGA Control Register */ +#define RNG_CR_GO_MASK (0x1U) +#define RNG_CR_GO_SHIFT (0U) +#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) +#define RNG_CR_HA_MASK (0x2U) +#define RNG_CR_HA_SHIFT (1U) +#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) +#define RNG_CR_INTM_MASK (0x4U) +#define RNG_CR_INTM_SHIFT (2U) +#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) +#define RNG_CR_CLRI_MASK (0x8U) +#define RNG_CR_CLRI_SHIFT (3U) +#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) +#define RNG_CR_SLP_MASK (0x10U) +#define RNG_CR_SLP_SHIFT (4U) +#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) + +/*! @name SR - RNGA Status Register */ +#define RNG_SR_SECV_MASK (0x1U) +#define RNG_SR_SECV_SHIFT (0U) +#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) +#define RNG_SR_LRS_MASK (0x2U) +#define RNG_SR_LRS_SHIFT (1U) +#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) +#define RNG_SR_ORU_MASK (0x4U) +#define RNG_SR_ORU_SHIFT (2U) +#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) +#define RNG_SR_ERRI_MASK (0x8U) +#define RNG_SR_ERRI_SHIFT (3U) +#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) +#define RNG_SR_SLP_MASK (0x10U) +#define RNG_SR_SLP_SHIFT (4U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_OREG_LVL_MASK (0xFF00U) +#define RNG_SR_OREG_LVL_SHIFT (8U) +#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) +#define RNG_SR_OREG_SIZE_MASK (0xFF0000U) +#define RNG_SR_OREG_SIZE_SHIFT (16U) +#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) + +/*! @name ER - RNGA Entropy Register */ +#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) +#define RNG_ER_EXT_ENT_SHIFT (0U) +#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) + +/*! @name OR - RNGA Output Register */ +#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OR_RANDOUT_SHIFT (0U) +#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x40029000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } +/** Interrupt vectors for the RNG peripheral type */ +#define RNG_IRQS { RNG_IRQn } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ + uint8_t RESERVED_0[2016]; + __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ + __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name TSR - RTC Time Seconds Register */ +#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) +#define RTC_TSR_TSR_SHIFT (0U) +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) + +/*! @name TPR - RTC Time Prescaler Register */ +#define RTC_TPR_TPR_MASK (0xFFFFU) +#define RTC_TPR_TPR_SHIFT (0U) +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) + +/*! @name TAR - RTC Time Alarm Register */ +#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) +#define RTC_TAR_TAR_SHIFT (0U) +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) + +/*! @name TCR - RTC Time Compensation Register */ +#define RTC_TCR_TCR_MASK (0xFFU) +#define RTC_TCR_TCR_SHIFT (0U) +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) +#define RTC_TCR_CIR_MASK (0xFF00U) +#define RTC_TCR_CIR_SHIFT (8U) +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) +#define RTC_TCR_TCV_MASK (0xFF0000U) +#define RTC_TCR_TCV_SHIFT (16U) +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) +#define RTC_TCR_CIC_MASK (0xFF000000U) +#define RTC_TCR_CIC_SHIFT (24U) +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) + +/*! @name CR - RTC Control Register */ +#define RTC_CR_SWR_MASK (0x1U) +#define RTC_CR_SWR_SHIFT (0U) +#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) +#define RTC_CR_WPE_MASK (0x2U) +#define RTC_CR_WPE_SHIFT (1U) +#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) +#define RTC_CR_SUP_MASK (0x4U) +#define RTC_CR_SUP_SHIFT (2U) +#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) +#define RTC_CR_UM_MASK (0x8U) +#define RTC_CR_UM_SHIFT (3U) +#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) +#define RTC_CR_WPS_MASK (0x10U) +#define RTC_CR_WPS_SHIFT (4U) +#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) +#define RTC_CR_OSCE_MASK (0x100U) +#define RTC_CR_OSCE_SHIFT (8U) +#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) +#define RTC_CR_CLKO_MASK (0x200U) +#define RTC_CR_CLKO_SHIFT (9U) +#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) +#define RTC_CR_SC16P_MASK (0x400U) +#define RTC_CR_SC16P_SHIFT (10U) +#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) +#define RTC_CR_SC8P_MASK (0x800U) +#define RTC_CR_SC8P_SHIFT (11U) +#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) +#define RTC_CR_SC4P_MASK (0x1000U) +#define RTC_CR_SC4P_SHIFT (12U) +#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) +#define RTC_CR_SC2P_MASK (0x2000U) +#define RTC_CR_SC2P_SHIFT (13U) +#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) + +/*! @name SR - RTC Status Register */ +#define RTC_SR_TIF_MASK (0x1U) +#define RTC_SR_TIF_SHIFT (0U) +#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) +#define RTC_SR_TOF_MASK (0x2U) +#define RTC_SR_TOF_SHIFT (1U) +#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) +#define RTC_SR_TAF_MASK (0x4U) +#define RTC_SR_TAF_SHIFT (2U) +#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) +#define RTC_SR_TCE_MASK (0x10U) +#define RTC_SR_TCE_SHIFT (4U) +#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) + +/*! @name LR - RTC Lock Register */ +#define RTC_LR_TCL_MASK (0x8U) +#define RTC_LR_TCL_SHIFT (3U) +#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) +#define RTC_LR_CRL_MASK (0x10U) +#define RTC_LR_CRL_SHIFT (4U) +#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) +#define RTC_LR_SRL_MASK (0x20U) +#define RTC_LR_SRL_SHIFT (5U) +#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) +#define RTC_LR_LRL_MASK (0x40U) +#define RTC_LR_LRL_SHIFT (6U) +#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) + +/*! @name IER - RTC Interrupt Enable Register */ +#define RTC_IER_TIIE_MASK (0x1U) +#define RTC_IER_TIIE_SHIFT (0U) +#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) +#define RTC_IER_TOIE_MASK (0x2U) +#define RTC_IER_TOIE_SHIFT (1U) +#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) +#define RTC_IER_TAIE_MASK (0x4U) +#define RTC_IER_TAIE_SHIFT (2U) +#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) +#define RTC_IER_TSIE_MASK (0x10U) +#define RTC_IER_TSIE_SHIFT (4U) +#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) +#define RTC_IER_WPON_MASK (0x80U) +#define RTC_IER_WPON_SHIFT (7U) +#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) + +/*! @name WAR - RTC Write Access Register */ +#define RTC_WAR_TSRW_MASK (0x1U) +#define RTC_WAR_TSRW_SHIFT (0U) +#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) +#define RTC_WAR_TPRW_MASK (0x2U) +#define RTC_WAR_TPRW_SHIFT (1U) +#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) +#define RTC_WAR_TARW_MASK (0x4U) +#define RTC_WAR_TARW_SHIFT (2U) +#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) +#define RTC_WAR_TCRW_MASK (0x8U) +#define RTC_WAR_TCRW_SHIFT (3U) +#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) +#define RTC_WAR_CRW_MASK (0x10U) +#define RTC_WAR_CRW_SHIFT (4U) +#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) +#define RTC_WAR_SRW_MASK (0x20U) +#define RTC_WAR_SRW_SHIFT (5U) +#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) +#define RTC_WAR_LRW_MASK (0x40U) +#define RTC_WAR_LRW_SHIFT (6U) +#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) +#define RTC_WAR_IERW_MASK (0x80U) +#define RTC_WAR_IERW_SHIFT (7U) +#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) + +/*! @name RAR - RTC Read Access Register */ +#define RTC_RAR_TSRR_MASK (0x1U) +#define RTC_RAR_TSRR_SHIFT (0U) +#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) +#define RTC_RAR_TPRR_MASK (0x2U) +#define RTC_RAR_TPRR_SHIFT (1U) +#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) +#define RTC_RAR_TARR_MASK (0x4U) +#define RTC_RAR_TARR_SHIFT (2U) +#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) +#define RTC_RAR_TCRR_MASK (0x8U) +#define RTC_RAR_TCRR_SHIFT (3U) +#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) +#define RTC_RAR_CRR_MASK (0x10U) +#define RTC_RAR_CRR_SHIFT (4U) +#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) +#define RTC_RAR_SRR_MASK (0x20U) +#define RTC_RAR_SRR_SHIFT (5U) +#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) +#define RTC_RAR_LRR_MASK (0x40U) +#define RTC_RAR_LRR_SHIFT (6U) +#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) +#define RTC_RAR_IERR_MASK (0x80U) +#define RTC_RAR_IERR_SHIFT (7U) +#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4003D000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer + * @{ + */ + +/** SDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */ + __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */ + __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */ + __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */ + __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */ + __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */ + __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */ + __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */ + __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */ + __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */ + __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */ + __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */ + __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */ + uint8_t RESERVED_0[8]; + __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */ + __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */ + __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */ + uint8_t RESERVED_1[100]; + __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */ + __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */ + uint8_t RESERVED_2[52]; + __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */ +} SDHC_Type; + +/* ---------------------------------------------------------------------------- + -- SDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDHC_Register_Masks SDHC Register Masks + * @{ + */ + +/*! @name DSADDR - DMA System Address register */ +#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU) +#define SDHC_DSADDR_DSADDR_SHIFT (2U) +#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK) + +/*! @name BLKATTR - Block Attributes register */ +#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU) +#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U) +#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK) +#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U) +#define SDHC_BLKATTR_BLKCNT_SHIFT (16U) +#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK) + +/*! @name CMDARG - Command Argument register */ +#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU) +#define SDHC_CMDARG_CMDARG_SHIFT (0U) +#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK) + +/*! @name XFERTYP - Transfer Type register */ +#define SDHC_XFERTYP_DMAEN_MASK (0x1U) +#define SDHC_XFERTYP_DMAEN_SHIFT (0U) +#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK) +#define SDHC_XFERTYP_BCEN_MASK (0x2U) +#define SDHC_XFERTYP_BCEN_SHIFT (1U) +#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK) +#define SDHC_XFERTYP_AC12EN_MASK (0x4U) +#define SDHC_XFERTYP_AC12EN_SHIFT (2U) +#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK) +#define SDHC_XFERTYP_DTDSEL_MASK (0x10U) +#define SDHC_XFERTYP_DTDSEL_SHIFT (4U) +#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK) +#define SDHC_XFERTYP_MSBSEL_MASK (0x20U) +#define SDHC_XFERTYP_MSBSEL_SHIFT (5U) +#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK) +#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U) +#define SDHC_XFERTYP_RSPTYP_SHIFT (16U) +#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK) +#define SDHC_XFERTYP_CCCEN_MASK (0x80000U) +#define SDHC_XFERTYP_CCCEN_SHIFT (19U) +#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK) +#define SDHC_XFERTYP_CICEN_MASK (0x100000U) +#define SDHC_XFERTYP_CICEN_SHIFT (20U) +#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK) +#define SDHC_XFERTYP_DPSEL_MASK (0x200000U) +#define SDHC_XFERTYP_DPSEL_SHIFT (21U) +#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK) +#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U) +#define SDHC_XFERTYP_CMDTYP_SHIFT (22U) +#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK) +#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U) +#define SDHC_XFERTYP_CMDINX_SHIFT (24U) +#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK) + +/*! @name CMDRSP - Command Response 0..Command Response 3 */ +#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK) +#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK) +#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK) +#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK) + +/* The count of SDHC_CMDRSP */ +#define SDHC_CMDRSP_COUNT (4U) + +/*! @name DATPORT - Buffer Data Port register */ +#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU) +#define SDHC_DATPORT_DATCONT_SHIFT (0U) +#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK) + +/*! @name PRSSTAT - Present State register */ +#define SDHC_PRSSTAT_CIHB_MASK (0x1U) +#define SDHC_PRSSTAT_CIHB_SHIFT (0U) +#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK) +#define SDHC_PRSSTAT_CDIHB_MASK (0x2U) +#define SDHC_PRSSTAT_CDIHB_SHIFT (1U) +#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK) +#define SDHC_PRSSTAT_DLA_MASK (0x4U) +#define SDHC_PRSSTAT_DLA_SHIFT (2U) +#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK) +#define SDHC_PRSSTAT_SDSTB_MASK (0x8U) +#define SDHC_PRSSTAT_SDSTB_SHIFT (3U) +#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK) +#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U) +#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U) +#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK) +#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U) +#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U) +#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK) +#define SDHC_PRSSTAT_PEROFF_MASK (0x40U) +#define SDHC_PRSSTAT_PEROFF_SHIFT (6U) +#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK) +#define SDHC_PRSSTAT_SDOFF_MASK (0x80U) +#define SDHC_PRSSTAT_SDOFF_SHIFT (7U) +#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK) +#define SDHC_PRSSTAT_WTA_MASK (0x100U) +#define SDHC_PRSSTAT_WTA_SHIFT (8U) +#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK) +#define SDHC_PRSSTAT_RTA_MASK (0x200U) +#define SDHC_PRSSTAT_RTA_SHIFT (9U) +#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK) +#define SDHC_PRSSTAT_BWEN_MASK (0x400U) +#define SDHC_PRSSTAT_BWEN_SHIFT (10U) +#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK) +#define SDHC_PRSSTAT_BREN_MASK (0x800U) +#define SDHC_PRSSTAT_BREN_SHIFT (11U) +#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK) +#define SDHC_PRSSTAT_CINS_MASK (0x10000U) +#define SDHC_PRSSTAT_CINS_SHIFT (16U) +#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK) +#define SDHC_PRSSTAT_CLSL_MASK (0x800000U) +#define SDHC_PRSSTAT_CLSL_SHIFT (23U) +#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK) +#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U) +#define SDHC_PRSSTAT_DLSL_SHIFT (24U) +#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK) + +/*! @name PROCTL - Protocol Control register */ +#define SDHC_PROCTL_LCTL_MASK (0x1U) +#define SDHC_PROCTL_LCTL_SHIFT (0U) +#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK) +#define SDHC_PROCTL_DTW_MASK (0x6U) +#define SDHC_PROCTL_DTW_SHIFT (1U) +#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK) +#define SDHC_PROCTL_D3CD_MASK (0x8U) +#define SDHC_PROCTL_D3CD_SHIFT (3U) +#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK) +#define SDHC_PROCTL_EMODE_MASK (0x30U) +#define SDHC_PROCTL_EMODE_SHIFT (4U) +#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK) +#define SDHC_PROCTL_CDTL_MASK (0x40U) +#define SDHC_PROCTL_CDTL_SHIFT (6U) +#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK) +#define SDHC_PROCTL_CDSS_MASK (0x80U) +#define SDHC_PROCTL_CDSS_SHIFT (7U) +#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK) +#define SDHC_PROCTL_DMAS_MASK (0x300U) +#define SDHC_PROCTL_DMAS_SHIFT (8U) +#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK) +#define SDHC_PROCTL_SABGREQ_MASK (0x10000U) +#define SDHC_PROCTL_SABGREQ_SHIFT (16U) +#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK) +#define SDHC_PROCTL_CREQ_MASK (0x20000U) +#define SDHC_PROCTL_CREQ_SHIFT (17U) +#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK) +#define SDHC_PROCTL_RWCTL_MASK (0x40000U) +#define SDHC_PROCTL_RWCTL_SHIFT (18U) +#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK) +#define SDHC_PROCTL_IABG_MASK (0x80000U) +#define SDHC_PROCTL_IABG_SHIFT (19U) +#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK) +#define SDHC_PROCTL_WECINT_MASK (0x1000000U) +#define SDHC_PROCTL_WECINT_SHIFT (24U) +#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK) +#define SDHC_PROCTL_WECINS_MASK (0x2000000U) +#define SDHC_PROCTL_WECINS_SHIFT (25U) +#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK) +#define SDHC_PROCTL_WECRM_MASK (0x4000000U) +#define SDHC_PROCTL_WECRM_SHIFT (26U) +#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK) + +/*! @name SYSCTL - System Control register */ +#define SDHC_SYSCTL_IPGEN_MASK (0x1U) +#define SDHC_SYSCTL_IPGEN_SHIFT (0U) +#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK) +#define SDHC_SYSCTL_HCKEN_MASK (0x2U) +#define SDHC_SYSCTL_HCKEN_SHIFT (1U) +#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK) +#define SDHC_SYSCTL_PEREN_MASK (0x4U) +#define SDHC_SYSCTL_PEREN_SHIFT (2U) +#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK) +#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U) +#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U) +#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK) +#define SDHC_SYSCTL_DVS_MASK (0xF0U) +#define SDHC_SYSCTL_DVS_SHIFT (4U) +#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK) +#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U) +#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U) +#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK) +#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U) +#define SDHC_SYSCTL_DTOCV_SHIFT (16U) +#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK) +#define SDHC_SYSCTL_RSTA_MASK (0x1000000U) +#define SDHC_SYSCTL_RSTA_SHIFT (24U) +#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK) +#define SDHC_SYSCTL_RSTC_MASK (0x2000000U) +#define SDHC_SYSCTL_RSTC_SHIFT (25U) +#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK) +#define SDHC_SYSCTL_RSTD_MASK (0x4000000U) +#define SDHC_SYSCTL_RSTD_SHIFT (26U) +#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK) +#define SDHC_SYSCTL_INITA_MASK (0x8000000U) +#define SDHC_SYSCTL_INITA_SHIFT (27U) +#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK) + +/*! @name IRQSTAT - Interrupt Status register */ +#define SDHC_IRQSTAT_CC_MASK (0x1U) +#define SDHC_IRQSTAT_CC_SHIFT (0U) +#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK) +#define SDHC_IRQSTAT_TC_MASK (0x2U) +#define SDHC_IRQSTAT_TC_SHIFT (1U) +#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK) +#define SDHC_IRQSTAT_BGE_MASK (0x4U) +#define SDHC_IRQSTAT_BGE_SHIFT (2U) +#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK) +#define SDHC_IRQSTAT_DINT_MASK (0x8U) +#define SDHC_IRQSTAT_DINT_SHIFT (3U) +#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK) +#define SDHC_IRQSTAT_BWR_MASK (0x10U) +#define SDHC_IRQSTAT_BWR_SHIFT (4U) +#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK) +#define SDHC_IRQSTAT_BRR_MASK (0x20U) +#define SDHC_IRQSTAT_BRR_SHIFT (5U) +#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK) +#define SDHC_IRQSTAT_CINS_MASK (0x40U) +#define SDHC_IRQSTAT_CINS_SHIFT (6U) +#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK) +#define SDHC_IRQSTAT_CRM_MASK (0x80U) +#define SDHC_IRQSTAT_CRM_SHIFT (7U) +#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK) +#define SDHC_IRQSTAT_CINT_MASK (0x100U) +#define SDHC_IRQSTAT_CINT_SHIFT (8U) +#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK) +#define SDHC_IRQSTAT_CTOE_MASK (0x10000U) +#define SDHC_IRQSTAT_CTOE_SHIFT (16U) +#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK) +#define SDHC_IRQSTAT_CCE_MASK (0x20000U) +#define SDHC_IRQSTAT_CCE_SHIFT (17U) +#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK) +#define SDHC_IRQSTAT_CEBE_MASK (0x40000U) +#define SDHC_IRQSTAT_CEBE_SHIFT (18U) +#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK) +#define SDHC_IRQSTAT_CIE_MASK (0x80000U) +#define SDHC_IRQSTAT_CIE_SHIFT (19U) +#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK) +#define SDHC_IRQSTAT_DTOE_MASK (0x100000U) +#define SDHC_IRQSTAT_DTOE_SHIFT (20U) +#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK) +#define SDHC_IRQSTAT_DCE_MASK (0x200000U) +#define SDHC_IRQSTAT_DCE_SHIFT (21U) +#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK) +#define SDHC_IRQSTAT_DEBE_MASK (0x400000U) +#define SDHC_IRQSTAT_DEBE_SHIFT (22U) +#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK) +#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U) +#define SDHC_IRQSTAT_AC12E_SHIFT (24U) +#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK) +#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U) +#define SDHC_IRQSTAT_DMAE_SHIFT (28U) +#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK) + +/*! @name IRQSTATEN - Interrupt Status Enable register */ +#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U) +#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U) +#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK) +#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U) +#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U) +#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK) +#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U) +#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U) +#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK) +#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U) +#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U) +#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK) +#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U) +#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U) +#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK) +#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U) +#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U) +#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK) +#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U) +#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U) +#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK) +#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U) +#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U) +#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK) +#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U) +#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U) +#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK) +#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U) +#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U) +#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK) +#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U) +#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U) +#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK) +#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U) +#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U) +#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK) +#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U) +#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U) +#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK) +#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U) +#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U) +#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK) +#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U) +#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U) +#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK) +#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U) +#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U) +#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK) +#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U) +#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U) +#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK) +#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U) +#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U) +#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK) + +/*! @name IRQSIGEN - Interrupt Signal Enable register */ +#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U) +#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U) +#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK) +#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U) +#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U) +#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK) +#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U) +#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U) +#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK) +#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U) +#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U) +#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK) +#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U) +#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U) +#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK) +#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U) +#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U) +#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK) +#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U) +#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U) +#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK) +#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U) +#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U) +#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK) +#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U) +#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U) +#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK) +#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U) +#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U) +#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK) +#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U) +#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U) +#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK) +#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U) +#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U) +#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK) +#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U) +#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U) +#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK) +#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U) +#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U) +#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK) +#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U) +#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U) +#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK) +#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U) +#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U) +#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK) +#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U) +#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U) +#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK) +#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U) +#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U) +#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK) + +/*! @name AC12ERR - Auto CMD12 Error Status Register */ +#define SDHC_AC12ERR_AC12NE_MASK (0x1U) +#define SDHC_AC12ERR_AC12NE_SHIFT (0U) +#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK) +#define SDHC_AC12ERR_AC12TOE_MASK (0x2U) +#define SDHC_AC12ERR_AC12TOE_SHIFT (1U) +#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK) +#define SDHC_AC12ERR_AC12EBE_MASK (0x4U) +#define SDHC_AC12ERR_AC12EBE_SHIFT (2U) +#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK) +#define SDHC_AC12ERR_AC12CE_MASK (0x8U) +#define SDHC_AC12ERR_AC12CE_SHIFT (3U) +#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK) +#define SDHC_AC12ERR_AC12IE_MASK (0x10U) +#define SDHC_AC12ERR_AC12IE_SHIFT (4U) +#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK) +#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U) +#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U) +#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK) + +/*! @name HTCAPBLT - Host Controller Capabilities */ +#define SDHC_HTCAPBLT_MBL_MASK (0x70000U) +#define SDHC_HTCAPBLT_MBL_SHIFT (16U) +#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK) +#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U) +#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U) +#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK) +#define SDHC_HTCAPBLT_HSS_MASK (0x200000U) +#define SDHC_HTCAPBLT_HSS_SHIFT (21U) +#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK) +#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U) +#define SDHC_HTCAPBLT_DMAS_SHIFT (22U) +#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK) +#define SDHC_HTCAPBLT_SRS_MASK (0x800000U) +#define SDHC_HTCAPBLT_SRS_SHIFT (23U) +#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK) +#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U) +#define SDHC_HTCAPBLT_VS33_SHIFT (24U) +#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK) + +/*! @name WML - Watermark Level Register */ +#define SDHC_WML_RDWML_MASK (0xFFU) +#define SDHC_WML_RDWML_SHIFT (0U) +#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK) +#define SDHC_WML_WRWML_MASK (0xFF0000U) +#define SDHC_WML_WRWML_SHIFT (16U) +#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK) + +/*! @name FEVT - Force Event register */ +#define SDHC_FEVT_AC12NE_MASK (0x1U) +#define SDHC_FEVT_AC12NE_SHIFT (0U) +#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK) +#define SDHC_FEVT_AC12TOE_MASK (0x2U) +#define SDHC_FEVT_AC12TOE_SHIFT (1U) +#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK) +#define SDHC_FEVT_AC12CE_MASK (0x4U) +#define SDHC_FEVT_AC12CE_SHIFT (2U) +#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK) +#define SDHC_FEVT_AC12EBE_MASK (0x8U) +#define SDHC_FEVT_AC12EBE_SHIFT (3U) +#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK) +#define SDHC_FEVT_AC12IE_MASK (0x10U) +#define SDHC_FEVT_AC12IE_SHIFT (4U) +#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK) +#define SDHC_FEVT_CNIBAC12E_MASK (0x80U) +#define SDHC_FEVT_CNIBAC12E_SHIFT (7U) +#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK) +#define SDHC_FEVT_CTOE_MASK (0x10000U) +#define SDHC_FEVT_CTOE_SHIFT (16U) +#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK) +#define SDHC_FEVT_CCE_MASK (0x20000U) +#define SDHC_FEVT_CCE_SHIFT (17U) +#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK) +#define SDHC_FEVT_CEBE_MASK (0x40000U) +#define SDHC_FEVT_CEBE_SHIFT (18U) +#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK) +#define SDHC_FEVT_CIE_MASK (0x80000U) +#define SDHC_FEVT_CIE_SHIFT (19U) +#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK) +#define SDHC_FEVT_DTOE_MASK (0x100000U) +#define SDHC_FEVT_DTOE_SHIFT (20U) +#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK) +#define SDHC_FEVT_DCE_MASK (0x200000U) +#define SDHC_FEVT_DCE_SHIFT (21U) +#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK) +#define SDHC_FEVT_DEBE_MASK (0x400000U) +#define SDHC_FEVT_DEBE_SHIFT (22U) +#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK) +#define SDHC_FEVT_AC12E_MASK (0x1000000U) +#define SDHC_FEVT_AC12E_SHIFT (24U) +#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK) +#define SDHC_FEVT_DMAE_MASK (0x10000000U) +#define SDHC_FEVT_DMAE_SHIFT (28U) +#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK) +#define SDHC_FEVT_CINT_MASK (0x80000000U) +#define SDHC_FEVT_CINT_SHIFT (31U) +#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK) + +/*! @name ADMAES - ADMA Error Status register */ +#define SDHC_ADMAES_ADMAES_MASK (0x3U) +#define SDHC_ADMAES_ADMAES_SHIFT (0U) +#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK) +#define SDHC_ADMAES_ADMALME_MASK (0x4U) +#define SDHC_ADMAES_ADMALME_SHIFT (2U) +#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK) +#define SDHC_ADMAES_ADMADCE_MASK (0x8U) +#define SDHC_ADMAES_ADMADCE_SHIFT (3U) +#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK) + +/*! @name ADSADDR - ADMA System Addressregister */ +#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU) +#define SDHC_ADSADDR_ADSADDR_SHIFT (2U) +#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK) + +/*! @name VENDOR - Vendor Specific register */ +#define SDHC_VENDOR_EXTDMAEN_MASK (0x1U) +#define SDHC_VENDOR_EXTDMAEN_SHIFT (0U) +#define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK) +#define SDHC_VENDOR_EXBLKNU_MASK (0x2U) +#define SDHC_VENDOR_EXBLKNU_SHIFT (1U) +#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK) +#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U) +#define SDHC_VENDOR_INTSTVAL_SHIFT (16U) +#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK) + +/*! @name MMCBOOT - MMC Boot register */ +#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU) +#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U) +#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK) +#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U) +#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U) +#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK) +#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U) +#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U) +#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK) +#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U) +#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U) +#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK) +#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U) +#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U) +#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK) +#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U) +#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U) +#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) + +/*! @name HOSTVER - Host Controller Version */ +#define SDHC_HOSTVER_SVN_MASK (0xFFU) +#define SDHC_HOSTVER_SVN_SHIFT (0U) +#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK) +#define SDHC_HOSTVER_VVN_MASK (0xFF00U) +#define SDHC_HOSTVER_VVN_SHIFT (8U) +#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK) + + +/*! + * @} + */ /* end of group SDHC_Register_Masks */ + + +/* SDHC - Peripheral instance base addresses */ +/** Peripheral SDHC base address */ +#define SDHC_BASE (0x400B1000u) +/** Peripheral SDHC base pointer */ +#define SDHC ((SDHC_Type *)SDHC_BASE) +/** Array initializer of SDHC peripheral base addresses */ +#define SDHC_BASE_ADDRS { SDHC_BASE } +/** Array initializer of SDHC peripheral base pointers */ +#define SDHC_BASE_PTRS { SDHC } +/** Interrupt vectors for the SDHC peripheral type */ +#define SDHC_IRQS { SDHC_IRQn } + +/*! + * @} + */ /* end of group SDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ + __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ + uint8_t RESERVED_0[4092]; + __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ + __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ + uint8_t RESERVED_3[8]; + __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ + __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */ + __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */ + __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */ + __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ + __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ + __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ + __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ + __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ + __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ + __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ + __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ + __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ + __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ + __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ + __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ +} SIM_Type; + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/*! @name SOPT1 - System Options Register 1 */ +#define SIM_SOPT1_RAMSIZE_MASK (0xF000U) +#define SIM_SOPT1_RAMSIZE_SHIFT (12U) +#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) +#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) +#define SIM_SOPT1_OSC32KSEL_SHIFT (18U) +#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) +#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) +#define SIM_SOPT1_USBVSTBY_SHIFT (29U) +#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) +#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) +#define SIM_SOPT1_USBSSTBY_SHIFT (30U) +#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) +#define SIM_SOPT1_USBREGEN_MASK (0x80000000U) +#define SIM_SOPT1_USBREGEN_SHIFT (31U) +#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) + +/*! @name SOPT1CFG - SOPT1 Configuration Register */ +#define SIM_SOPT1CFG_URWE_MASK (0x1000000U) +#define SIM_SOPT1CFG_URWE_SHIFT (24U) +#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) +#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) +#define SIM_SOPT1CFG_UVSWE_SHIFT (25U) +#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) +#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) +#define SIM_SOPT1CFG_USSWE_SHIFT (26U) +#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) + +/*! @name SOPT2 - System Options Register 2 */ +#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) +#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) +#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) +#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) +#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) +#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) +#define SIM_SOPT2_FBSL_MASK (0x300U) +#define SIM_SOPT2_FBSL_SHIFT (8U) +#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK) +#define SIM_SOPT2_PTD7PAD_MASK (0x800U) +#define SIM_SOPT2_PTD7PAD_SHIFT (11U) +#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK) +#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) +#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) +#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) +#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) +#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) +#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) +#define SIM_SOPT2_USBSRC_MASK (0x40000U) +#define SIM_SOPT2_USBSRC_SHIFT (18U) +#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) +#define SIM_SOPT2_RMIISRC_MASK (0x80000U) +#define SIM_SOPT2_RMIISRC_SHIFT (19U) +#define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK) +#define SIM_SOPT2_TIMESRC_MASK (0x300000U) +#define SIM_SOPT2_TIMESRC_SHIFT (20U) +#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK) +#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U) +#define SIM_SOPT2_SDHCSRC_SHIFT (28U) +#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK) + +/*! @name SOPT4 - System Options Register 4 */ +#define SIM_SOPT4_FTM0FLT0_MASK (0x1U) +#define SIM_SOPT4_FTM0FLT0_SHIFT (0U) +#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) +#define SIM_SOPT4_FTM0FLT1_MASK (0x2U) +#define SIM_SOPT4_FTM0FLT1_SHIFT (1U) +#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) +#define SIM_SOPT4_FTM0FLT2_MASK (0x4U) +#define SIM_SOPT4_FTM0FLT2_SHIFT (2U) +#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK) +#define SIM_SOPT4_FTM1FLT0_MASK (0x10U) +#define SIM_SOPT4_FTM1FLT0_SHIFT (4U) +#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) +#define SIM_SOPT4_FTM2FLT0_MASK (0x100U) +#define SIM_SOPT4_FTM2FLT0_SHIFT (8U) +#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) +#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U) +#define SIM_SOPT4_FTM3FLT0_SHIFT (12U) +#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK) +#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) +#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) +#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) +#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) +#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) +#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) +#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) +#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) +#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) +#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) +#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) +#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) +#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) +#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) +#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) +#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U) +#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U) +#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK) +#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) +#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) +#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) +#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) +#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) +#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) +#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U) +#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U) +#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK) +#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U) +#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U) +#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK) + +/*! @name SOPT5 - System Options Register 5 */ +#define SIM_SOPT5_UART0TXSRC_MASK (0x3U) +#define SIM_SOPT5_UART0TXSRC_SHIFT (0U) +#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) +#define SIM_SOPT5_UART0RXSRC_MASK (0xCU) +#define SIM_SOPT5_UART0RXSRC_SHIFT (2U) +#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) +#define SIM_SOPT5_UART1TXSRC_MASK (0x30U) +#define SIM_SOPT5_UART1TXSRC_SHIFT (4U) +#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) +#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) +#define SIM_SOPT5_UART1RXSRC_SHIFT (6U) +#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) + +/*! @name SOPT7 - System Options Register 7 */ +#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) +#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) +#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) +#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) +#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) +#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) +#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) +#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) +#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) +#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U) +#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U) +#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK) +#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U) +#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U) +#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK) +#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U) +#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U) +#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK) + +/*! @name SDID - System Device Identification Register */ +#define SIM_SDID_PINID_MASK (0xFU) +#define SIM_SDID_PINID_SHIFT (0U) +#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) +#define SIM_SDID_FAMID_MASK (0x70U) +#define SIM_SDID_FAMID_SHIFT (4U) +#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) +#define SIM_SDID_DIEID_MASK (0xF80U) +#define SIM_SDID_DIEID_SHIFT (7U) +#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) +#define SIM_SDID_REVID_MASK (0xF000U) +#define SIM_SDID_REVID_SHIFT (12U) +#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) +#define SIM_SDID_SERIESID_MASK (0xF00000U) +#define SIM_SDID_SERIESID_SHIFT (20U) +#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) +#define SIM_SDID_SUBFAMID_MASK (0xF000000U) +#define SIM_SDID_SUBFAMID_SHIFT (24U) +#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) +#define SIM_SDID_FAMILYID_MASK (0xF0000000U) +#define SIM_SDID_FAMILYID_SHIFT (28U) +#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) + +/*! @name SCGC1 - System Clock Gating Control Register 1 */ +#define SIM_SCGC1_I2C2_MASK (0x40U) +#define SIM_SCGC1_I2C2_SHIFT (6U) +#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK) +#define SIM_SCGC1_UART4_MASK (0x400U) +#define SIM_SCGC1_UART4_SHIFT (10U) +#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK) +#define SIM_SCGC1_UART5_MASK (0x800U) +#define SIM_SCGC1_UART5_SHIFT (11U) +#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK) + +/*! @name SCGC2 - System Clock Gating Control Register 2 */ +#define SIM_SCGC2_ENET_MASK (0x1U) +#define SIM_SCGC2_ENET_SHIFT (0U) +#define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK) +#define SIM_SCGC2_DAC0_MASK (0x1000U) +#define SIM_SCGC2_DAC0_SHIFT (12U) +#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK) +#define SIM_SCGC2_DAC1_MASK (0x2000U) +#define SIM_SCGC2_DAC1_SHIFT (13U) +#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK) + +/*! @name SCGC3 - System Clock Gating Control Register 3 */ +#define SIM_SCGC3_RNGA_MASK (0x1U) +#define SIM_SCGC3_RNGA_SHIFT (0U) +#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK) +#define SIM_SCGC3_SPI2_MASK (0x1000U) +#define SIM_SCGC3_SPI2_SHIFT (12U) +#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK) +#define SIM_SCGC3_SDHC_MASK (0x20000U) +#define SIM_SCGC3_SDHC_SHIFT (17U) +#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK) +#define SIM_SCGC3_FTM2_MASK (0x1000000U) +#define SIM_SCGC3_FTM2_SHIFT (24U) +#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK) +#define SIM_SCGC3_FTM3_MASK (0x2000000U) +#define SIM_SCGC3_FTM3_SHIFT (25U) +#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK) +#define SIM_SCGC3_ADC1_MASK (0x8000000U) +#define SIM_SCGC3_ADC1_SHIFT (27U) +#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK) + +/*! @name SCGC4 - System Clock Gating Control Register 4 */ +#define SIM_SCGC4_EWM_MASK (0x2U) +#define SIM_SCGC4_EWM_SHIFT (1U) +#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) +#define SIM_SCGC4_CMT_MASK (0x4U) +#define SIM_SCGC4_CMT_SHIFT (2U) +#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) +#define SIM_SCGC4_I2C0_MASK (0x40U) +#define SIM_SCGC4_I2C0_SHIFT (6U) +#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) +#define SIM_SCGC4_I2C1_MASK (0x80U) +#define SIM_SCGC4_I2C1_SHIFT (7U) +#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) +#define SIM_SCGC4_UART0_MASK (0x400U) +#define SIM_SCGC4_UART0_SHIFT (10U) +#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) +#define SIM_SCGC4_UART1_MASK (0x800U) +#define SIM_SCGC4_UART1_SHIFT (11U) +#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) +#define SIM_SCGC4_UART2_MASK (0x1000U) +#define SIM_SCGC4_UART2_SHIFT (12U) +#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) +#define SIM_SCGC4_UART3_MASK (0x2000U) +#define SIM_SCGC4_UART3_SHIFT (13U) +#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK) +#define SIM_SCGC4_USBOTG_MASK (0x40000U) +#define SIM_SCGC4_USBOTG_SHIFT (18U) +#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) +#define SIM_SCGC4_CMP_MASK (0x80000U) +#define SIM_SCGC4_CMP_SHIFT (19U) +#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) +#define SIM_SCGC4_VREF_MASK (0x100000U) +#define SIM_SCGC4_VREF_SHIFT (20U) +#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) + +/*! @name SCGC5 - System Clock Gating Control Register 5 */ +#define SIM_SCGC5_LPTMR_MASK (0x1U) +#define SIM_SCGC5_LPTMR_SHIFT (0U) +#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) +#define SIM_SCGC5_PORTA_MASK (0x200U) +#define SIM_SCGC5_PORTA_SHIFT (9U) +#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) +#define SIM_SCGC5_PORTB_MASK (0x400U) +#define SIM_SCGC5_PORTB_SHIFT (10U) +#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) +#define SIM_SCGC5_PORTC_MASK (0x800U) +#define SIM_SCGC5_PORTC_SHIFT (11U) +#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) +#define SIM_SCGC5_PORTD_MASK (0x1000U) +#define SIM_SCGC5_PORTD_SHIFT (12U) +#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) +#define SIM_SCGC5_PORTE_MASK (0x2000U) +#define SIM_SCGC5_PORTE_SHIFT (13U) +#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) + +/*! @name SCGC6 - System Clock Gating Control Register 6 */ +#define SIM_SCGC6_FTF_MASK (0x1U) +#define SIM_SCGC6_FTF_SHIFT (0U) +#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) +#define SIM_SCGC6_DMAMUX_MASK (0x2U) +#define SIM_SCGC6_DMAMUX_SHIFT (1U) +#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) +#define SIM_SCGC6_FLEXCAN0_MASK (0x10U) +#define SIM_SCGC6_FLEXCAN0_SHIFT (4U) +#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK) +#define SIM_SCGC6_RNGA_MASK (0x200U) +#define SIM_SCGC6_RNGA_SHIFT (9U) +#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) +#define SIM_SCGC6_SPI0_MASK (0x1000U) +#define SIM_SCGC6_SPI0_SHIFT (12U) +#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) +#define SIM_SCGC6_SPI1_MASK (0x2000U) +#define SIM_SCGC6_SPI1_SHIFT (13U) +#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) +#define SIM_SCGC6_I2S_MASK (0x8000U) +#define SIM_SCGC6_I2S_SHIFT (15U) +#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) +#define SIM_SCGC6_CRC_MASK (0x40000U) +#define SIM_SCGC6_CRC_SHIFT (18U) +#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) +#define SIM_SCGC6_USBDCD_MASK (0x200000U) +#define SIM_SCGC6_USBDCD_SHIFT (21U) +#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) +#define SIM_SCGC6_PDB_MASK (0x400000U) +#define SIM_SCGC6_PDB_SHIFT (22U) +#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) +#define SIM_SCGC6_PIT_MASK (0x800000U) +#define SIM_SCGC6_PIT_SHIFT (23U) +#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) +#define SIM_SCGC6_FTM0_MASK (0x1000000U) +#define SIM_SCGC6_FTM0_SHIFT (24U) +#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) +#define SIM_SCGC6_FTM1_MASK (0x2000000U) +#define SIM_SCGC6_FTM1_SHIFT (25U) +#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) +#define SIM_SCGC6_FTM2_MASK (0x4000000U) +#define SIM_SCGC6_FTM2_SHIFT (26U) +#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) +#define SIM_SCGC6_ADC0_MASK (0x8000000U) +#define SIM_SCGC6_ADC0_SHIFT (27U) +#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) +#define SIM_SCGC6_RTC_MASK (0x20000000U) +#define SIM_SCGC6_RTC_SHIFT (29U) +#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) +#define SIM_SCGC6_DAC0_MASK (0x80000000U) +#define SIM_SCGC6_DAC0_SHIFT (31U) +#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) + +/*! @name SCGC7 - System Clock Gating Control Register 7 */ +#define SIM_SCGC7_FLEXBUS_MASK (0x1U) +#define SIM_SCGC7_FLEXBUS_SHIFT (0U) +#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK) +#define SIM_SCGC7_DMA_MASK (0x2U) +#define SIM_SCGC7_DMA_SHIFT (1U) +#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) +#define SIM_SCGC7_MPU_MASK (0x4U) +#define SIM_SCGC7_MPU_SHIFT (2U) +#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) + +/*! @name CLKDIV1 - System Clock Divider Register 1 */ +#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) +#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) +#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) +#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U) +#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U) +#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK) +#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) +#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) +#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) +#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) +#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) +#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) + +/*! @name CLKDIV2 - System Clock Divider Register 2 */ +#define SIM_CLKDIV2_USBFRAC_MASK (0x1U) +#define SIM_CLKDIV2_USBFRAC_SHIFT (0U) +#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) +#define SIM_CLKDIV2_USBDIV_MASK (0xEU) +#define SIM_CLKDIV2_USBDIV_SHIFT (1U) +#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) + +/*! @name FCFG1 - Flash Configuration Register 1 */ +#define SIM_FCFG1_FLASHDIS_MASK (0x1U) +#define SIM_FCFG1_FLASHDIS_SHIFT (0U) +#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) +#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) +#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) +#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) +#define SIM_FCFG1_DEPART_MASK (0xF00U) +#define SIM_FCFG1_DEPART_SHIFT (8U) +#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) +#define SIM_FCFG1_EESIZE_MASK (0xF0000U) +#define SIM_FCFG1_EESIZE_SHIFT (16U) +#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK) +#define SIM_FCFG1_PFSIZE_MASK (0xF000000U) +#define SIM_FCFG1_PFSIZE_SHIFT (24U) +#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) +#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) +#define SIM_FCFG1_NVMSIZE_SHIFT (28U) +#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) + +/*! @name FCFG2 - Flash Configuration Register 2 */ +#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) +#define SIM_FCFG2_MAXADDR1_SHIFT (16U) +#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) +#define SIM_FCFG2_PFLSH_MASK (0x800000U) +#define SIM_FCFG2_PFLSH_SHIFT (23U) +#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK) +#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) +#define SIM_FCFG2_MAXADDR0_SHIFT (24U) +#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) + +/*! @name UIDH - Unique Identification Register High */ +#define SIM_UIDH_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDH_UID_SHIFT (0U) +#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) + +/*! @name UIDMH - Unique Identification Register Mid-High */ +#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDMH_UID_SHIFT (0U) +#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) + +/*! @name UIDML - Unique Identification Register Mid Low */ +#define SIM_UIDML_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDML_UID_SHIFT (0U) +#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) + +/*! @name UIDL - Unique Identification Register Low */ +#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDL_UID_SHIFT (0U) +#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) + + +/*! + * @} + */ /* end of group SIM_Register_Masks */ + + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM base address */ +#define SIM_BASE (0x40047000u) +/** Peripheral SIM base pointer */ +#define SIM ((SIM_Type *)SIM_BASE) +/** Array initializer of SIM peripheral base addresses */ +#define SIM_BASE_ADDRS { SIM_BASE } +/** Array initializer of SIM peripheral base pointers */ +#define SIM_BASE_PTRS { SIM } + +/*! + * @} + */ /* end of group SIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer + * @{ + */ + +/** SMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ + __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ + __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */ + __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ +} SMC_Type; + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/*! @name PMPROT - Power Mode Protection register */ +#define SMC_PMPROT_AVLLS_MASK (0x2U) +#define SMC_PMPROT_AVLLS_SHIFT (1U) +#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) +#define SMC_PMPROT_ALLS_MASK (0x8U) +#define SMC_PMPROT_ALLS_SHIFT (3U) +#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) +#define SMC_PMPROT_AVLP_MASK (0x20U) +#define SMC_PMPROT_AVLP_SHIFT (5U) +#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) + +/*! @name PMCTRL - Power Mode Control register */ +#define SMC_PMCTRL_STOPM_MASK (0x7U) +#define SMC_PMCTRL_STOPM_SHIFT (0U) +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) +#define SMC_PMCTRL_STOPA_MASK (0x8U) +#define SMC_PMCTRL_STOPA_SHIFT (3U) +#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) +#define SMC_PMCTRL_RUNM_MASK (0x60U) +#define SMC_PMCTRL_RUNM_SHIFT (5U) +#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) +#define SMC_PMCTRL_LPWUI_MASK (0x80U) +#define SMC_PMCTRL_LPWUI_SHIFT (7U) +#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK) + +/*! @name VLLSCTRL - VLLS Control register */ +#define SMC_VLLSCTRL_VLLSM_MASK (0x7U) +#define SMC_VLLSCTRL_VLLSM_SHIFT (0U) +#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK) +#define SMC_VLLSCTRL_PORPO_MASK (0x20U) +#define SMC_VLLSCTRL_PORPO_SHIFT (5U) +#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK) + +/*! @name PMSTAT - Power Mode Status register */ +#define SMC_PMSTAT_PMSTAT_MASK (0x7FU) +#define SMC_PMSTAT_PMSTAT_SHIFT (0U) +#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) + + +/*! + * @} + */ /* end of group SMC_Register_Masks */ + + +/* SMC - Peripheral instance base addresses */ +/** Peripheral SMC base address */ +#define SMC_BASE (0x4007E000u) +/** Peripheral SMC base pointer */ +#define SMC ((SMC_Type *)SMC_BASE) +/** Array initializer of SMC peripheral base addresses */ +#define SMC_BASE_ADDRS { SMC_BASE } +/** Array initializer of SMC peripheral base pointers */ +#define SMC_BASE_PTRS { SMC } + +/*! + * @} + */ /* end of group SMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint8_t RESERVED_1[24]; + __IO uint32_t SR; /**< Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ + __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ + __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ + __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ + uint8_t RESERVED_2[48]; + __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ + __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ + __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ + __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define SPI_MCR_HALT_MASK (0x1U) +#define SPI_MCR_HALT_SHIFT (0U) +#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) +#define SPI_MCR_SMPL_PT_MASK (0x300U) +#define SPI_MCR_SMPL_PT_SHIFT (8U) +#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) +#define SPI_MCR_CLR_RXF_MASK (0x400U) +#define SPI_MCR_CLR_RXF_SHIFT (10U) +#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) +#define SPI_MCR_CLR_TXF_MASK (0x800U) +#define SPI_MCR_CLR_TXF_SHIFT (11U) +#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) +#define SPI_MCR_DIS_RXF_MASK (0x1000U) +#define SPI_MCR_DIS_RXF_SHIFT (12U) +#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) +#define SPI_MCR_DIS_TXF_MASK (0x2000U) +#define SPI_MCR_DIS_TXF_SHIFT (13U) +#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) +#define SPI_MCR_MDIS_MASK (0x4000U) +#define SPI_MCR_MDIS_SHIFT (14U) +#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) +#define SPI_MCR_DOZE_MASK (0x8000U) +#define SPI_MCR_DOZE_SHIFT (15U) +#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) +#define SPI_MCR_PCSIS_MASK (0x3F0000U) +#define SPI_MCR_PCSIS_SHIFT (16U) +#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) +#define SPI_MCR_ROOE_MASK (0x1000000U) +#define SPI_MCR_ROOE_SHIFT (24U) +#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) +#define SPI_MCR_PCSSE_MASK (0x2000000U) +#define SPI_MCR_PCSSE_SHIFT (25U) +#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) +#define SPI_MCR_MTFE_MASK (0x4000000U) +#define SPI_MCR_MTFE_SHIFT (26U) +#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) +#define SPI_MCR_FRZ_MASK (0x8000000U) +#define SPI_MCR_FRZ_SHIFT (27U) +#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) +#define SPI_MCR_DCONF_MASK (0x30000000U) +#define SPI_MCR_DCONF_SHIFT (28U) +#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) +#define SPI_MCR_CONT_SCKE_MASK (0x40000000U) +#define SPI_MCR_CONT_SCKE_SHIFT (30U) +#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) +#define SPI_MCR_MSTR_MASK (0x80000000U) +#define SPI_MCR_MSTR_SHIFT (31U) +#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) + +/*! @name TCR - Transfer Count Register */ +#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) +#define SPI_TCR_SPI_TCNT_SHIFT (16U) +#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) + +/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ +#define SPI_CTAR_BR_MASK (0xFU) +#define SPI_CTAR_BR_SHIFT (0U) +#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) +#define SPI_CTAR_DT_MASK (0xF0U) +#define SPI_CTAR_DT_SHIFT (4U) +#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) +#define SPI_CTAR_ASC_MASK (0xF00U) +#define SPI_CTAR_ASC_SHIFT (8U) +#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) +#define SPI_CTAR_CSSCK_MASK (0xF000U) +#define SPI_CTAR_CSSCK_SHIFT (12U) +#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) +#define SPI_CTAR_PBR_MASK (0x30000U) +#define SPI_CTAR_PBR_SHIFT (16U) +#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) +#define SPI_CTAR_PDT_MASK (0xC0000U) +#define SPI_CTAR_PDT_SHIFT (18U) +#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) +#define SPI_CTAR_PASC_MASK (0x300000U) +#define SPI_CTAR_PASC_SHIFT (20U) +#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) +#define SPI_CTAR_PCSSCK_MASK (0xC00000U) +#define SPI_CTAR_PCSSCK_SHIFT (22U) +#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) +#define SPI_CTAR_LSBFE_MASK (0x1000000U) +#define SPI_CTAR_LSBFE_SHIFT (24U) +#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) +#define SPI_CTAR_CPHA_MASK (0x2000000U) +#define SPI_CTAR_CPHA_SHIFT (25U) +#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) +#define SPI_CTAR_CPOL_MASK (0x4000000U) +#define SPI_CTAR_CPOL_SHIFT (26U) +#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) +#define SPI_CTAR_FMSZ_MASK (0x78000000U) +#define SPI_CTAR_FMSZ_SHIFT (27U) +#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) +#define SPI_CTAR_DBR_MASK (0x80000000U) +#define SPI_CTAR_DBR_SHIFT (31U) +#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) + +/* The count of SPI_CTAR */ +#define SPI_CTAR_COUNT (2U) + +/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ +#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) +#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) +#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) +#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) +#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) +#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) +#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) +#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) +#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) + +/* The count of SPI_CTAR_SLAVE */ +#define SPI_CTAR_SLAVE_COUNT (1U) + +/*! @name SR - Status Register */ +#define SPI_SR_POPNXTPTR_MASK (0xFU) +#define SPI_SR_POPNXTPTR_SHIFT (0U) +#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) +#define SPI_SR_RXCTR_MASK (0xF0U) +#define SPI_SR_RXCTR_SHIFT (4U) +#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) +#define SPI_SR_TXNXTPTR_MASK (0xF00U) +#define SPI_SR_TXNXTPTR_SHIFT (8U) +#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) +#define SPI_SR_TXCTR_MASK (0xF000U) +#define SPI_SR_TXCTR_SHIFT (12U) +#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) +#define SPI_SR_RFDF_MASK (0x20000U) +#define SPI_SR_RFDF_SHIFT (17U) +#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) +#define SPI_SR_RFOF_MASK (0x80000U) +#define SPI_SR_RFOF_SHIFT (19U) +#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) +#define SPI_SR_TFFF_MASK (0x2000000U) +#define SPI_SR_TFFF_SHIFT (25U) +#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) +#define SPI_SR_TFUF_MASK (0x8000000U) +#define SPI_SR_TFUF_SHIFT (27U) +#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) +#define SPI_SR_EOQF_MASK (0x10000000U) +#define SPI_SR_EOQF_SHIFT (28U) +#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) +#define SPI_SR_TXRXS_MASK (0x40000000U) +#define SPI_SR_TXRXS_SHIFT (30U) +#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) +#define SPI_SR_TCF_MASK (0x80000000U) +#define SPI_SR_TCF_SHIFT (31U) +#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) + +/*! @name RSER - DMA/Interrupt Request Select and Enable Register */ +#define SPI_RSER_RFDF_DIRS_MASK (0x10000U) +#define SPI_RSER_RFDF_DIRS_SHIFT (16U) +#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) +#define SPI_RSER_RFDF_RE_MASK (0x20000U) +#define SPI_RSER_RFDF_RE_SHIFT (17U) +#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) +#define SPI_RSER_RFOF_RE_MASK (0x80000U) +#define SPI_RSER_RFOF_RE_SHIFT (19U) +#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) +#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) +#define SPI_RSER_TFFF_DIRS_SHIFT (24U) +#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) +#define SPI_RSER_TFFF_RE_MASK (0x2000000U) +#define SPI_RSER_TFFF_RE_SHIFT (25U) +#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) +#define SPI_RSER_TFUF_RE_MASK (0x8000000U) +#define SPI_RSER_TFUF_RE_SHIFT (27U) +#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) +#define SPI_RSER_EOQF_RE_MASK (0x10000000U) +#define SPI_RSER_EOQF_RE_SHIFT (28U) +#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) +#define SPI_RSER_TCF_RE_MASK (0x80000000U) +#define SPI_RSER_TCF_RE_SHIFT (31U) +#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) + +/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ +#define SPI_PUSHR_TXDATA_MASK (0xFFFFU) +#define SPI_PUSHR_TXDATA_SHIFT (0U) +#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) +#define SPI_PUSHR_PCS_MASK (0x3F0000U) +#define SPI_PUSHR_PCS_SHIFT (16U) +#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) +#define SPI_PUSHR_CTCNT_MASK (0x4000000U) +#define SPI_PUSHR_CTCNT_SHIFT (26U) +#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) +#define SPI_PUSHR_EOQ_MASK (0x8000000U) +#define SPI_PUSHR_EOQ_SHIFT (27U) +#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) +#define SPI_PUSHR_CTAS_MASK (0x70000000U) +#define SPI_PUSHR_CTAS_SHIFT (28U) +#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) +#define SPI_PUSHR_CONT_MASK (0x80000000U) +#define SPI_PUSHR_CONT_SHIFT (31U) +#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) + +/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ +#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) +#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) +#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) + +/*! @name POPR - POP RX FIFO Register */ +#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_POPR_RXDATA_SHIFT (0U) +#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) + +/*! @name TXFR0 - Transmit FIFO Registers */ +#define SPI_TXFR0_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR0_TXDATA_SHIFT (0U) +#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) +#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) + +/*! @name TXFR1 - Transmit FIFO Registers */ +#define SPI_TXFR1_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR1_TXDATA_SHIFT (0U) +#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) +#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) + +/*! @name TXFR2 - Transmit FIFO Registers */ +#define SPI_TXFR2_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR2_TXDATA_SHIFT (0U) +#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) +#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) + +/*! @name TXFR3 - Transmit FIFO Registers */ +#define SPI_TXFR3_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR3_TXDATA_SHIFT (0U) +#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) +#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) + +/*! @name RXFR0 - Receive FIFO Registers */ +#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR0_RXDATA_SHIFT (0U) +#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) + +/*! @name RXFR1 - Receive FIFO Registers */ +#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR1_RXDATA_SHIFT (0U) +#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) + +/*! @name RXFR2 - Receive FIFO Registers */ +#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR2_RXDATA_SHIFT (0U) +#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) + +/*! @name RXFR3 - Receive FIFO Registers */ +#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR3_RXDATA_SHIFT (0U) +#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x4002C000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x4002D000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Peripheral SPI2 base address */ +#define SPI2_BASE (0x400AC000u) +/** Peripheral SPI2 base pointer */ +#define SPI2 ((SPI_Type *)SPI2_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ + __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ + __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ + __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ + __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ + __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ + __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ + __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ + __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ + __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ + __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ + __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ + __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ + __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ + __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ + uint8_t RESERVED_0[1]; + __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ + __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ + __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ + __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ + __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ + __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ + __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ + uint8_t RESERVED_1[1]; + __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ + __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ + __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ + union { /* offset: 0x1B */ + __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + }; + __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ + __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ + __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ + __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name BDH - UART Baud Rate Registers: High */ +#define UART_BDH_SBR_MASK (0x1FU) +#define UART_BDH_SBR_SHIFT (0U) +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) +#define UART_BDH_SBNS_MASK (0x20U) +#define UART_BDH_SBNS_SHIFT (5U) +#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) +#define UART_BDH_RXEDGIE_MASK (0x40U) +#define UART_BDH_RXEDGIE_SHIFT (6U) +#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) +#define UART_BDH_LBKDIE_MASK (0x80U) +#define UART_BDH_LBKDIE_SHIFT (7U) +#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) + +/*! @name BDL - UART Baud Rate Registers: Low */ +#define UART_BDL_SBR_MASK (0xFFU) +#define UART_BDL_SBR_SHIFT (0U) +#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) + +/*! @name C1 - UART Control Register 1 */ +#define UART_C1_PT_MASK (0x1U) +#define UART_C1_PT_SHIFT (0U) +#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) +#define UART_C1_PE_MASK (0x2U) +#define UART_C1_PE_SHIFT (1U) +#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) +#define UART_C1_ILT_MASK (0x4U) +#define UART_C1_ILT_SHIFT (2U) +#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) +#define UART_C1_WAKE_MASK (0x8U) +#define UART_C1_WAKE_SHIFT (3U) +#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) +#define UART_C1_M_MASK (0x10U) +#define UART_C1_M_SHIFT (4U) +#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) +#define UART_C1_RSRC_MASK (0x20U) +#define UART_C1_RSRC_SHIFT (5U) +#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) +#define UART_C1_UARTSWAI_MASK (0x40U) +#define UART_C1_UARTSWAI_SHIFT (6U) +#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) +#define UART_C1_LOOPS_MASK (0x80U) +#define UART_C1_LOOPS_SHIFT (7U) +#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) + +/*! @name C2 - UART Control Register 2 */ +#define UART_C2_SBK_MASK (0x1U) +#define UART_C2_SBK_SHIFT (0U) +#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) +#define UART_C2_RWU_MASK (0x2U) +#define UART_C2_RWU_SHIFT (1U) +#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) +#define UART_C2_RE_MASK (0x4U) +#define UART_C2_RE_SHIFT (2U) +#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) +#define UART_C2_TE_MASK (0x8U) +#define UART_C2_TE_SHIFT (3U) +#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) +#define UART_C2_ILIE_MASK (0x10U) +#define UART_C2_ILIE_SHIFT (4U) +#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) +#define UART_C2_RIE_MASK (0x20U) +#define UART_C2_RIE_SHIFT (5U) +#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) +#define UART_C2_TCIE_MASK (0x40U) +#define UART_C2_TCIE_SHIFT (6U) +#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) +#define UART_C2_TIE_MASK (0x80U) +#define UART_C2_TIE_SHIFT (7U) +#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) + +/*! @name S1 - UART Status Register 1 */ +#define UART_S1_PF_MASK (0x1U) +#define UART_S1_PF_SHIFT (0U) +#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) +#define UART_S1_FE_MASK (0x2U) +#define UART_S1_FE_SHIFT (1U) +#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) +#define UART_S1_NF_MASK (0x4U) +#define UART_S1_NF_SHIFT (2U) +#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) +#define UART_S1_OR_MASK (0x8U) +#define UART_S1_OR_SHIFT (3U) +#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) +#define UART_S1_IDLE_MASK (0x10U) +#define UART_S1_IDLE_SHIFT (4U) +#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) +#define UART_S1_RDRF_MASK (0x20U) +#define UART_S1_RDRF_SHIFT (5U) +#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) +#define UART_S1_TC_MASK (0x40U) +#define UART_S1_TC_SHIFT (6U) +#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) +#define UART_S1_TDRE_MASK (0x80U) +#define UART_S1_TDRE_SHIFT (7U) +#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) + +/*! @name S2 - UART Status Register 2 */ +#define UART_S2_RAF_MASK (0x1U) +#define UART_S2_RAF_SHIFT (0U) +#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) +#define UART_S2_LBKDE_MASK (0x2U) +#define UART_S2_LBKDE_SHIFT (1U) +#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) +#define UART_S2_BRK13_MASK (0x4U) +#define UART_S2_BRK13_SHIFT (2U) +#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) +#define UART_S2_RWUID_MASK (0x8U) +#define UART_S2_RWUID_SHIFT (3U) +#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) +#define UART_S2_RXINV_MASK (0x10U) +#define UART_S2_RXINV_SHIFT (4U) +#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) +#define UART_S2_MSBF_MASK (0x20U) +#define UART_S2_MSBF_SHIFT (5U) +#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) +#define UART_S2_RXEDGIF_MASK (0x40U) +#define UART_S2_RXEDGIF_SHIFT (6U) +#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) +#define UART_S2_LBKDIF_MASK (0x80U) +#define UART_S2_LBKDIF_SHIFT (7U) +#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) + +/*! @name C3 - UART Control Register 3 */ +#define UART_C3_PEIE_MASK (0x1U) +#define UART_C3_PEIE_SHIFT (0U) +#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) +#define UART_C3_FEIE_MASK (0x2U) +#define UART_C3_FEIE_SHIFT (1U) +#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) +#define UART_C3_NEIE_MASK (0x4U) +#define UART_C3_NEIE_SHIFT (2U) +#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) +#define UART_C3_ORIE_MASK (0x8U) +#define UART_C3_ORIE_SHIFT (3U) +#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) +#define UART_C3_TXINV_MASK (0x10U) +#define UART_C3_TXINV_SHIFT (4U) +#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) +#define UART_C3_TXDIR_MASK (0x20U) +#define UART_C3_TXDIR_SHIFT (5U) +#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) +#define UART_C3_T8_MASK (0x40U) +#define UART_C3_T8_SHIFT (6U) +#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) +#define UART_C3_R8_MASK (0x80U) +#define UART_C3_R8_SHIFT (7U) +#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) + +/*! @name D - UART Data Register */ +#define UART_D_RT_MASK (0xFFU) +#define UART_D_RT_SHIFT (0U) +#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) + +/*! @name MA1 - UART Match Address Registers 1 */ +#define UART_MA1_MA_MASK (0xFFU) +#define UART_MA1_MA_SHIFT (0U) +#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) + +/*! @name MA2 - UART Match Address Registers 2 */ +#define UART_MA2_MA_MASK (0xFFU) +#define UART_MA2_MA_SHIFT (0U) +#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) + +/*! @name C4 - UART Control Register 4 */ +#define UART_C4_BRFA_MASK (0x1FU) +#define UART_C4_BRFA_SHIFT (0U) +#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) +#define UART_C4_M10_MASK (0x20U) +#define UART_C4_M10_SHIFT (5U) +#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) +#define UART_C4_MAEN2_MASK (0x40U) +#define UART_C4_MAEN2_SHIFT (6U) +#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) +#define UART_C4_MAEN1_MASK (0x80U) +#define UART_C4_MAEN1_SHIFT (7U) +#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) + +/*! @name C5 - UART Control Register 5 */ +#define UART_C5_LBKDDMAS_MASK (0x8U) +#define UART_C5_LBKDDMAS_SHIFT (3U) +#define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK) +#define UART_C5_ILDMAS_MASK (0x10U) +#define UART_C5_ILDMAS_SHIFT (4U) +#define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK) +#define UART_C5_RDMAS_MASK (0x20U) +#define UART_C5_RDMAS_SHIFT (5U) +#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) +#define UART_C5_TCDMAS_MASK (0x40U) +#define UART_C5_TCDMAS_SHIFT (6U) +#define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK) +#define UART_C5_TDMAS_MASK (0x80U) +#define UART_C5_TDMAS_SHIFT (7U) +#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) + +/*! @name ED - UART Extended Data Register */ +#define UART_ED_PARITYE_MASK (0x40U) +#define UART_ED_PARITYE_SHIFT (6U) +#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) +#define UART_ED_NOISY_MASK (0x80U) +#define UART_ED_NOISY_SHIFT (7U) +#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) + +/*! @name MODEM - UART Modem Register */ +#define UART_MODEM_TXCTSE_MASK (0x1U) +#define UART_MODEM_TXCTSE_SHIFT (0U) +#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) +#define UART_MODEM_TXRTSE_MASK (0x2U) +#define UART_MODEM_TXRTSE_SHIFT (1U) +#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) +#define UART_MODEM_TXRTSPOL_MASK (0x4U) +#define UART_MODEM_TXRTSPOL_SHIFT (2U) +#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) +#define UART_MODEM_RXRTSE_MASK (0x8U) +#define UART_MODEM_RXRTSE_SHIFT (3U) +#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) + +/*! @name IR - UART Infrared Register */ +#define UART_IR_TNP_MASK (0x3U) +#define UART_IR_TNP_SHIFT (0U) +#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) +#define UART_IR_IREN_MASK (0x4U) +#define UART_IR_IREN_SHIFT (2U) +#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) + +/*! @name PFIFO - UART FIFO Parameters */ +#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) +#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) +#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) +#define UART_PFIFO_RXFE_MASK (0x8U) +#define UART_PFIFO_RXFE_SHIFT (3U) +#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) +#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) +#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) +#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) +#define UART_PFIFO_TXFE_MASK (0x80U) +#define UART_PFIFO_TXFE_SHIFT (7U) +#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) + +/*! @name CFIFO - UART FIFO Control Register */ +#define UART_CFIFO_RXUFE_MASK (0x1U) +#define UART_CFIFO_RXUFE_SHIFT (0U) +#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) +#define UART_CFIFO_TXOFE_MASK (0x2U) +#define UART_CFIFO_TXOFE_SHIFT (1U) +#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) +#define UART_CFIFO_RXOFE_MASK (0x4U) +#define UART_CFIFO_RXOFE_SHIFT (2U) +#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) +#define UART_CFIFO_RXFLUSH_MASK (0x40U) +#define UART_CFIFO_RXFLUSH_SHIFT (6U) +#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) +#define UART_CFIFO_TXFLUSH_MASK (0x80U) +#define UART_CFIFO_TXFLUSH_SHIFT (7U) +#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) + +/*! @name SFIFO - UART FIFO Status Register */ +#define UART_SFIFO_RXUF_MASK (0x1U) +#define UART_SFIFO_RXUF_SHIFT (0U) +#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) +#define UART_SFIFO_TXOF_MASK (0x2U) +#define UART_SFIFO_TXOF_SHIFT (1U) +#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) +#define UART_SFIFO_RXOF_MASK (0x4U) +#define UART_SFIFO_RXOF_SHIFT (2U) +#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) +#define UART_SFIFO_RXEMPT_MASK (0x40U) +#define UART_SFIFO_RXEMPT_SHIFT (6U) +#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) +#define UART_SFIFO_TXEMPT_MASK (0x80U) +#define UART_SFIFO_TXEMPT_SHIFT (7U) +#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) + +/*! @name TWFIFO - UART FIFO Transmit Watermark */ +#define UART_TWFIFO_TXWATER_MASK (0xFFU) +#define UART_TWFIFO_TXWATER_SHIFT (0U) +#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) + +/*! @name TCFIFO - UART FIFO Transmit Count */ +#define UART_TCFIFO_TXCOUNT_MASK (0xFFU) +#define UART_TCFIFO_TXCOUNT_SHIFT (0U) +#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) + +/*! @name RWFIFO - UART FIFO Receive Watermark */ +#define UART_RWFIFO_RXWATER_MASK (0xFFU) +#define UART_RWFIFO_RXWATER_SHIFT (0U) +#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) + +/*! @name RCFIFO - UART FIFO Receive Count */ +#define UART_RCFIFO_RXCOUNT_MASK (0xFFU) +#define UART_RCFIFO_RXCOUNT_SHIFT (0U) +#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) + +/*! @name C7816 - UART 7816 Control Register */ +#define UART_C7816_ISO_7816E_MASK (0x1U) +#define UART_C7816_ISO_7816E_SHIFT (0U) +#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) +#define UART_C7816_TTYPE_MASK (0x2U) +#define UART_C7816_TTYPE_SHIFT (1U) +#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) +#define UART_C7816_INIT_MASK (0x4U) +#define UART_C7816_INIT_SHIFT (2U) +#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) +#define UART_C7816_ANACK_MASK (0x8U) +#define UART_C7816_ANACK_SHIFT (3U) +#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) +#define UART_C7816_ONACK_MASK (0x10U) +#define UART_C7816_ONACK_SHIFT (4U) +#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) + +/*! @name IE7816 - UART 7816 Interrupt Enable Register */ +#define UART_IE7816_RXTE_MASK (0x1U) +#define UART_IE7816_RXTE_SHIFT (0U) +#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) +#define UART_IE7816_TXTE_MASK (0x2U) +#define UART_IE7816_TXTE_SHIFT (1U) +#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) +#define UART_IE7816_GTVE_MASK (0x4U) +#define UART_IE7816_GTVE_SHIFT (2U) +#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) +#define UART_IE7816_INITDE_MASK (0x10U) +#define UART_IE7816_INITDE_SHIFT (4U) +#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) +#define UART_IE7816_BWTE_MASK (0x20U) +#define UART_IE7816_BWTE_SHIFT (5U) +#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) +#define UART_IE7816_CWTE_MASK (0x40U) +#define UART_IE7816_CWTE_SHIFT (6U) +#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) +#define UART_IE7816_WTE_MASK (0x80U) +#define UART_IE7816_WTE_SHIFT (7U) +#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) + +/*! @name IS7816 - UART 7816 Interrupt Status Register */ +#define UART_IS7816_RXT_MASK (0x1U) +#define UART_IS7816_RXT_SHIFT (0U) +#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) +#define UART_IS7816_TXT_MASK (0x2U) +#define UART_IS7816_TXT_SHIFT (1U) +#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) +#define UART_IS7816_GTV_MASK (0x4U) +#define UART_IS7816_GTV_SHIFT (2U) +#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) +#define UART_IS7816_INITD_MASK (0x10U) +#define UART_IS7816_INITD_SHIFT (4U) +#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) +#define UART_IS7816_BWT_MASK (0x20U) +#define UART_IS7816_BWT_SHIFT (5U) +#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) +#define UART_IS7816_CWT_MASK (0x40U) +#define UART_IS7816_CWT_SHIFT (6U) +#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) +#define UART_IS7816_WT_MASK (0x80U) +#define UART_IS7816_WT_SHIFT (7U) +#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) + +/*! @name WP7816T0 - UART 7816 Wait Parameter Register */ +#define UART_WP7816T0_WI_MASK (0xFFU) +#define UART_WP7816T0_WI_SHIFT (0U) +#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) + +/*! @name WP7816T1 - UART 7816 Wait Parameter Register */ +#define UART_WP7816T1_BWI_MASK (0xFU) +#define UART_WP7816T1_BWI_SHIFT (0U) +#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) +#define UART_WP7816T1_CWI_MASK (0xF0U) +#define UART_WP7816T1_CWI_SHIFT (4U) +#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) + +/*! @name WN7816 - UART 7816 Wait N Register */ +#define UART_WN7816_GTN_MASK (0xFFU) +#define UART_WN7816_GTN_SHIFT (0U) +#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) + +/*! @name WF7816 - UART 7816 Wait FD Register */ +#define UART_WF7816_GTFD_MASK (0xFFU) +#define UART_WF7816_GTFD_SHIFT (0U) +#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) + +/*! @name ET7816 - UART 7816 Error Threshold Register */ +#define UART_ET7816_RXTHRESHOLD_MASK (0xFU) +#define UART_ET7816_RXTHRESHOLD_SHIFT (0U) +#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) +#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) +#define UART_ET7816_TXTHRESHOLD_SHIFT (4U) +#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) + +/*! @name TL7816 - UART 7816 Transmit Length Register */ +#define UART_TL7816_TLEN_MASK (0xFFU) +#define UART_TL7816_TLEN_SHIFT (0U) +#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART0 base address */ +#define UART0_BASE (0x4006A000u) +/** Peripheral UART0 base pointer */ +#define UART0 ((UART_Type *)UART0_BASE) +/** Peripheral UART1 base address */ +#define UART1_BASE (0x4006B000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x4006C000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x4006D000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x400EA000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x400EB000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn } +#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn } +#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status register, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control register, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ + uint8_t RESERVED_26[43]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ + uint8_t RESERVED_27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ + uint8_t RESERVED_28[23]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID register */ +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) + +/*! @name IDCOMP - Peripheral ID Complement register */ +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) + +/*! @name REV - Peripheral Revision register */ +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) + +/*! @name ADDINFO - Peripheral Additional Info register */ +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) +#define USB_ADDINFO_IRQNUM_MASK (0xF8U) +#define USB_ADDINFO_IRQNUM_SHIFT (3U) +#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) + +/*! @name OTGISTAT - OTG Interrupt Status register */ +#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) +#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) +#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) +#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) +#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) +#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) +#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) +#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) +#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) +#define USB_OTGISTAT_IDCHG_MASK (0x80U) +#define USB_OTGISTAT_IDCHG_SHIFT (7U) +#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) + +/*! @name OTGICR - OTG Interrupt Control register */ +#define USB_OTGICR_AVBUSEN_MASK (0x1U) +#define USB_OTGICR_AVBUSEN_SHIFT (0U) +#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) +#define USB_OTGICR_BSESSEN_MASK (0x4U) +#define USB_OTGICR_BSESSEN_SHIFT (2U) +#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) +#define USB_OTGICR_SESSVLDEN_MASK (0x8U) +#define USB_OTGICR_SESSVLDEN_SHIFT (3U) +#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) +#define USB_OTGICR_IDEN_MASK (0x80U) +#define USB_OTGICR_IDEN_SHIFT (7U) +#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) + +/*! @name OTGSTAT - OTG Status register */ +#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) +#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) +#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) +#define USB_OTGSTAT_BSESSEND_MASK (0x4U) +#define USB_OTGSTAT_BSESSEND_SHIFT (2U) +#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) +#define USB_OTGSTAT_SESS_VLD_MASK (0x8U) +#define USB_OTGSTAT_SESS_VLD_SHIFT (3U) +#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) +#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) +#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) +#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) +#define USB_OTGSTAT_ID_MASK (0x80U) +#define USB_OTGSTAT_ID_SHIFT (7U) +#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) + +/*! @name OTGCTL - OTG Control register */ +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) + +/*! @name ISTAT - Interrupt Status register */ +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) + +/*! @name INTEN - Interrupt Enable register */ +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) + +/*! @name ERRSTAT - Error Interrupt Status register */ +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) + +/*! @name ERREN - Error Interrupt Enable register */ +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) + +/*! @name STAT - Status register */ +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) + +/*! @name CTL - Control register */ +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) + +/*! @name ADDR - Address register */ +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) + +/*! @name BDTPAGE1 - BDT Page register 1 */ +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) + +/*! @name FRMNUML - Frame Number register Low */ +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) + +/*! @name FRMNUMH - Frame Number register High */ +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) + +/*! @name TOKEN - Token register */ +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) + +/*! @name SOFTHLD - SOF Threshold register */ +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) + +/*! @name BDTPAGE2 - BDT Page Register 2 */ +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) + +/*! @name BDTPAGE3 - BDT Page Register 3 */ +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) + +/*! @name ENDPT - Endpoint Control register */ +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control register */ +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) + +/*! @name OBSERVE - USB OTG Observe register */ +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) + +/*! @name CONTROL - USB OTG Control register */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) + +/*! @name USBTRC0 - USB Transceiver Control register 0 */ +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) + +/*! @name USBFRMADJUST - Frame Adjust Register */ +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) + +/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) + +/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ +#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) + +/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40072000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer + * @{ + */ + +/** USBDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ + __I uint32_t STATUS; /**< Status register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ + __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ + union { /* offset: 0x18 */ + __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ + __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ + }; +} USBDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/*! @name CONTROL - Control register */ +#define USBDCD_CONTROL_IACK_MASK (0x1U) +#define USBDCD_CONTROL_IACK_SHIFT (0U) +#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) +#define USBDCD_CONTROL_IF_MASK (0x100U) +#define USBDCD_CONTROL_IF_SHIFT (8U) +#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) +#define USBDCD_CONTROL_IE_MASK (0x10000U) +#define USBDCD_CONTROL_IE_SHIFT (16U) +#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) +#define USBDCD_CONTROL_BC12_MASK (0x20000U) +#define USBDCD_CONTROL_BC12_SHIFT (17U) +#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) +#define USBDCD_CONTROL_START_MASK (0x1000000U) +#define USBDCD_CONTROL_START_SHIFT (24U) +#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) +#define USBDCD_CONTROL_SR_MASK (0x2000000U) +#define USBDCD_CONTROL_SR_SHIFT (25U) +#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) + +/*! @name CLOCK - Clock register */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) +#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) +#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) + +/*! @name STATUS - Status register */ +#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) +#define USBDCD_STATUS_SEQ_RES_SHIFT (16U) +#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) +#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) +#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) +#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) +#define USBDCD_STATUS_ERR_MASK (0x100000U) +#define USBDCD_STATUS_ERR_SHIFT (20U) +#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) +#define USBDCD_STATUS_TO_MASK (0x200000U) +#define USBDCD_STATUS_TO_SHIFT (21U) +#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) +#define USBDCD_STATUS_ACTIVE_MASK (0x400000U) +#define USBDCD_STATUS_ACTIVE_SHIFT (22U) +#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) + +/*! @name TIMER0 - TIMER0 register */ +#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) +#define USBDCD_TIMER0_TUNITCON_SHIFT (0U) +#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) +#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) +#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) +#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) + +/*! @name TIMER1 - TIMER1 register */ +#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) +#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) +#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) +#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) +#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) +#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) + +/*! @name TIMER2_BC11 - TIMER2_BC11 register */ +#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) +#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) +#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) +#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) +#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) +#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) + +/*! @name TIMER2_BC12 - TIMER2_BC12 register */ +#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) +#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) +#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) +#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) +#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) +#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) + + +/*! + * @} + */ /* end of group USBDCD_Register_Masks */ + + +/* USBDCD - Peripheral instance base addresses */ +/** Peripheral USBDCD base address */ +#define USBDCD_BASE (0x40035000u) +/** Peripheral USBDCD base pointer */ +#define USBDCD ((USBDCD_Type *)USBDCD_BASE) +/** Array initializer of USBDCD peripheral base addresses */ +#define USBDCD_BASE_ADDRS { USBDCD_BASE } +/** Array initializer of USBDCD peripheral base pointers */ +#define USBDCD_BASE_PTRS { USBDCD } +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USBDCD_IRQn } + +/*! + * @} + */ /* end of group USBDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ + __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name TRM - VREF Trim Register */ +#define VREF_TRM_TRIM_MASK (0x3FU) +#define VREF_TRM_TRIM_SHIFT (0U) +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) +#define VREF_TRM_CHOPEN_MASK (0x40U) +#define VREF_TRM_CHOPEN_SHIFT (6U) +#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) + +/*! @name SC - VREF Status and Control Register */ +#define VREF_SC_MODE_LV_MASK (0x3U) +#define VREF_SC_MODE_LV_SHIFT (0U) +#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) +#define VREF_SC_VREFST_MASK (0x4U) +#define VREF_SC_VREFST_SHIFT (2U) +#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) +#define VREF_SC_ICOMPEN_MASK (0x20U) +#define VREF_SC_ICOMPEN_SHIFT (5U) +#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) +#define VREF_SC_REGEN_MASK (0x40U) +#define VREF_SC_REGEN_SHIFT (6U) +#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) +#define VREF_SC_VREFEN_MASK (0x80U) +#define VREF_SC_VREFEN_SHIFT (7U) +#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +/** Peripheral VREF base address */ +#define VREF_BASE (0x40074000u) +/** Peripheral VREF base pointer */ +#define VREF ((VREF_Type *)VREF_BASE) +/** Array initializer of VREF peripheral base addresses */ +#define VREF_BASE_ADDRS { VREF_BASE } +/** Array initializer of VREF peripheral base pointers */ +#define VREF_BASE_PTRS { VREF } + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ + __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ + __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ + __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ + __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ + __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ + __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ + __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ + __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ + __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ + __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ + __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name STCTRLH - Watchdog Status and Control Register High */ +#define WDOG_STCTRLH_WDOGEN_MASK (0x1U) +#define WDOG_STCTRLH_WDOGEN_SHIFT (0U) +#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) +#define WDOG_STCTRLH_CLKSRC_MASK (0x2U) +#define WDOG_STCTRLH_CLKSRC_SHIFT (1U) +#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) +#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) +#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) +#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) +#define WDOG_STCTRLH_WINEN_MASK (0x8U) +#define WDOG_STCTRLH_WINEN_SHIFT (3U) +#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) +#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) +#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) +#define WDOG_STCTRLH_DBGEN_MASK (0x20U) +#define WDOG_STCTRLH_DBGEN_SHIFT (5U) +#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) +#define WDOG_STCTRLH_STOPEN_MASK (0x40U) +#define WDOG_STCTRLH_STOPEN_SHIFT (6U) +#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) +#define WDOG_STCTRLH_WAITEN_MASK (0x80U) +#define WDOG_STCTRLH_WAITEN_SHIFT (7U) +#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) +#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) +#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) +#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) +#define WDOG_STCTRLH_TESTSEL_MASK (0x800U) +#define WDOG_STCTRLH_TESTSEL_SHIFT (11U) +#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) +#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) +#define WDOG_STCTRLH_BYTESEL_SHIFT (12U) +#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) +#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) +#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) +#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) + +/*! @name STCTRLL - Watchdog Status and Control Register Low */ +#define WDOG_STCTRLL_INTFLG_MASK (0x8000U) +#define WDOG_STCTRLL_INTFLG_SHIFT (15U) +#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) + +/*! @name TOVALH - Watchdog Time-out Value Register High */ +#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) +#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) +#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) + +/*! @name TOVALL - Watchdog Time-out Value Register Low */ +#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) +#define WDOG_TOVALL_TOVALLOW_SHIFT (0U) +#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) + +/*! @name WINH - Watchdog Window Register High */ +#define WDOG_WINH_WINHIGH_MASK (0xFFFFU) +#define WDOG_WINH_WINHIGH_SHIFT (0U) +#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) + +/*! @name WINL - Watchdog Window Register Low */ +#define WDOG_WINL_WINLOW_MASK (0xFFFFU) +#define WDOG_WINL_WINLOW_SHIFT (0U) +#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) + +/*! @name REFRESH - Watchdog Refresh register */ +#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) +#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) +#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) + +/*! @name UNLOCK - Watchdog Unlock register */ +#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) +#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) +#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) + +/*! @name TMROUTH - Watchdog Timer Output Register High */ +#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) +#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) +#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) + +/*! @name TMROUTL - Watchdog Timer Output Register Low */ +#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) +#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) +#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) + +/*! @name RSTCNT - Watchdog Reset Count register */ +#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) +#define WDOG_RSTCNT_RSTCNT_SHIFT (0U) +#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) + +/*! @name PRESC - Watchdog Prescaler register */ +#define WDOG_PRESC_PRESCVAL_MASK (0x700U) +#define WDOG_PRESC_PRESCVAL_SHIFT (8U) +#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG base address */ +#define WDOG_BASE (0x40052000u) +/** Peripheral WDOG base pointer */ +#define WDOG ((WDOG_Type *)WDOG_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { WDOG_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG_EWM_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base) +#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base) +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT +#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) +#define MCM_ISR_REG(base) MCM_ISCR_REG(base) +#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK +#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT +#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK +#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT +#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK +#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT +#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK +#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT +#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK +#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT +#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK +#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT +#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK +#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT +#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK +#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT +#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK +#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT +#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK +#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT +#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK +#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT +#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK +#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define DSPI2 SPI2 +#define FLEXCAN0 CAN0 +#define GPIOA_BASE PTA_BASE +#define GPIOA PTA +#define GPIOB_BASE PTB_BASE +#define GPIOB PTB +#define GPIOC_BASE PTC_BASE +#define GPIOC PTC +#define GPIOD_BASE PTD_BASE +#define GPIOD PTD +#define GPIOE_BASE PTE_BASE +#define GPIOE PTE +#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base) +#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base) +#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK +#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT +#define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x) +#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK +#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT +#define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x) +#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK +#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT +#define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x) +#define Watchdog_IRQn WDOG_EWM_IRQn +#define Watchdog_IRQHandler WDOG_EWM_IRQHandler +#define LPTimer_IRQn LPTMR0_IRQn +#define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler +#define DMAMUX0 DMAMUX +#define WDOG0 WDOG +#define MCM0 MCM +#define RTC0 RTC + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MK64F12_H_ */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12_features.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12_features.h new file mode 100644 index 00000000000..2137c500cd3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12_features.h @@ -0,0 +1,2108 @@ +/* +** ################################################################### +** Version: rev. 2.14, 2015-06-08 +** Build: b151217 +** +** Abstract: +** Chip specific module features. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-01-30) +** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** - rev. 2.6 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.7 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.8 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.9 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 2.10 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 2.11 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PDB and PORT. +** - rev. 2.12 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 2.13 (2015-05-27) +** Several USB features added. +** - rev. 2.14 (2015-06-08) +** FTM features BUS_CLOCK and FAST_CLOCK removed. +** +** ################################################################### +*/ + +#ifndef _MK64F12_FEATURES_H_ +#define _MK64F12_FEATURES_H_ + +/* SOC module features */ + +#if defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) + /* @brief ACMP availability on the SoC. */ + #define FSL_FEATURE_SOC_ACMP_COUNT (0) + /* @brief ADC16 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC16_COUNT (2) + /* @brief ADC12 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC12_COUNT (0) + /* @brief AFE availability on the SoC. */ + #define FSL_FEATURE_SOC_AFE_COUNT (0) + /* @brief AIPS availability on the SoC. */ + #define FSL_FEATURE_SOC_AIPS_COUNT (2) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (0) + /* @brief AXBS availability on the SoC. */ + #define FSL_FEATURE_SOC_AXBS_COUNT (1) + /* @brief ASMC availability on the SoC. */ + #define FSL_FEATURE_SOC_ASMC_COUNT (0) + /* @brief CADC availability on the SoC. */ + #define FSL_FEATURE_SOC_CADC_COUNT (0) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief MMCAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMCAU_COUNT (1) + /* @brief CMP availability on the SoC. */ + #define FSL_FEATURE_SOC_CMP_COUNT (3) + /* @brief CMT availability on the SoC. */ + #define FSL_FEATURE_SOC_CMT_COUNT (1) + /* @brief CNC availability on the SoC. */ + #define FSL_FEATURE_SOC_CNC_COUNT (0) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief DAC availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC_COUNT (2) + /* @brief DAC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC32_COUNT (0) + /* @brief DCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_DCDC_COUNT (0) + /* @brief DDR availability on the SoC. */ + #define FSL_FEATURE_SOC_DDR_COUNT (0) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (0) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief DMAMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) + /* @brief DRY availability on the SoC. */ + #define FSL_FEATURE_SOC_DRY_COUNT (0) + /* @brief DSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_DSPI_COUNT (3) + /* @brief EMVSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (0) + /* @brief ENET availability on the SoC. */ + #define FSL_FEATURE_SOC_ENET_COUNT (1) + /* @brief EWM availability on the SoC. */ + #define FSL_FEATURE_SOC_EWM_COUNT (1) + /* @brief FB availability on the SoC. */ + #define FSL_FEATURE_SOC_FB_COUNT (1) + /* @brief FGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FGPIO_COUNT (0) + /* @brief FLEXIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FSKDT availability on the SoC. */ + #define FSL_FEATURE_SOC_FSKDT_COUNT (0) + /* @brief FTFA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFA_COUNT (0) + /* @brief FTFE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFE_COUNT (1) + /* @brief FTFL availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFL_COUNT (0) + /* @brief FTM availability on the SoC. */ + #define FSL_FEATURE_SOC_FTM_COUNT (4) + /* @brief FTMRA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRA_COUNT (0) + /* @brief FTMRE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRE_COUNT (0) + /* @brief FTMRH availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRH_COUNT (0) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief HSADC availability on the SoC. */ + #define FSL_FEATURE_SOC_HSADC_COUNT (0) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (3) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (1) + /* @brief ICS availability on the SoC. */ + #define FSL_FEATURE_SOC_ICS_COUNT (0) + /* @brief INTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INTMUX_COUNT (0) + /* @brief IRQ availability on the SoC. */ + #define FSL_FEATURE_SOC_IRQ_COUNT (0) + /* @brief KBI availability on the SoC. */ + #define FSL_FEATURE_SOC_KBI_COUNT (0) + /* @brief SLCD availability on the SoC. */ + #define FSL_FEATURE_SOC_SLCD_COUNT (0) + /* @brief LCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_LCDC_COUNT (0) + /* @brief LDO availability on the SoC. */ + #define FSL_FEATURE_SOC_LDO_COUNT (0) + /* @brief LLWU availability on the SoC. */ + #define FSL_FEATURE_SOC_LLWU_COUNT (1) + /* @brief LMEM availability on the SoC. */ + #define FSL_FEATURE_SOC_LMEM_COUNT (0) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (0) + /* @brief LPIT availability on the SoC. */ + #define FSL_FEATURE_SOC_LPIT_COUNT (0) + /* @brief LPSCI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSCI_COUNT (0) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (0) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPTPM availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTPM_COUNT (0) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (0) + /* @brief LTC availability on the SoC. */ + #define FSL_FEATURE_SOC_LTC_COUNT (0) + /* @brief MC availability on the SoC. */ + #define FSL_FEATURE_SOC_MC_COUNT (0) + /* @brief MCG availability on the SoC. */ + #define FSL_FEATURE_SOC_MCG_COUNT (1) + /* @brief MCGLITE availability on the SoC. */ + #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) + /* @brief MCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MCM_COUNT (1) + /* @brief MMAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMAU_COUNT (0) + /* @brief MMDVSQ availability on the SoC. */ + #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) + /* @brief MPU availability on the SoC. */ + #define FSL_FEATURE_SOC_MPU_COUNT (1) + /* @brief MSCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCAN_COUNT (0) + /* @brief MSCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCM_COUNT (0) + /* @brief MTB availability on the SoC. */ + #define FSL_FEATURE_SOC_MTB_COUNT (0) + /* @brief MTBDWT availability on the SoC. */ + #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) + /* @brief MU availability on the SoC. */ + #define FSL_FEATURE_SOC_MU_COUNT (0) + /* @brief NFC availability on the SoC. */ + #define FSL_FEATURE_SOC_NFC_COUNT (0) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (0) + /* @brief OSC availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC_COUNT (1) + /* @brief OSC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC32_COUNT (0) + /* @brief OTFAD availability on the SoC. */ + #define FSL_FEATURE_SOC_OTFAD_COUNT (0) + /* @brief PDB availability on the SoC. */ + #define FSL_FEATURE_SOC_PDB_COUNT (1) + /* @brief PCC availability on the SoC. */ + #define FSL_FEATURE_SOC_PCC_COUNT (0) + /* @brief PGA availability on the SoC. */ + #define FSL_FEATURE_SOC_PGA_COUNT (0) + /* @brief PIT availability on the SoC. */ + #define FSL_FEATURE_SOC_PIT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (0) + /* @brief PWT availability on the SoC. */ + #define FSL_FEATURE_SOC_PWT_COUNT (0) + /* @brief QuadSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) + /* @brief RCM availability on the SoC. */ + #define FSL_FEATURE_SOC_RCM_COUNT (1) + /* @brief RFSYS availability on the SoC. */ + #define FSL_FEATURE_SOC_RFSYS_COUNT (1) + /* @brief RFVBAT availability on the SoC. */ + #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) + /* @brief RNG availability on the SoC. */ + #define FSL_FEATURE_SOC_RNG_COUNT (1) + /* @brief RNGB availability on the SoC. */ + #define FSL_FEATURE_SOC_RNGB_COUNT (0) + /* @brief ROM availability on the SoC. */ + #define FSL_FEATURE_SOC_ROM_COUNT (0) + /* @brief RSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_RSIM_COUNT (0) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (0) + /* @brief SCI availability on the SoC. */ + #define FSL_FEATURE_SOC_SCI_COUNT (0) + /* @brief SDHC availability on the SoC. */ + #define FSL_FEATURE_SOC_SDHC_COUNT (1) + /* @brief SDRAM availability on the SoC. */ + #define FSL_FEATURE_SOC_SDRAM_COUNT (0) + /* @brief SEMA42 availability on the SoC. */ + #define FSL_FEATURE_SOC_SEMA42_COUNT (0) + /* @brief SIM availability on the SoC. */ + #define FSL_FEATURE_SOC_SIM_COUNT (1) + /* @brief SMC availability on the SoC. */ + #define FSL_FEATURE_SOC_SMC_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (0) + /* @brief TMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TMR_COUNT (0) + /* @brief TPM availability on the SoC. */ + #define FSL_FEATURE_SOC_TPM_COUNT (0) + /* @brief TRGMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) + /* @brief TRIAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) + /* @brief TRNG availability on the SoC. */ + #define FSL_FEATURE_SOC_TRNG_COUNT (0) + /* @brief TSI availability on the SoC. */ + #define FSL_FEATURE_SOC_TSI_COUNT (0) + /* @brief TSTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TSTMR_COUNT (0) + /* @brief UART availability on the SoC. */ + #define FSL_FEATURE_SOC_UART_COUNT (6) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBDCD_COUNT (1) + /* @brief USBHSDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) + /* @brief USBPHY availability on the SoC. */ + #define FSL_FEATURE_SOC_USBPHY_COUNT (0) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_WDOG_COUNT (1) + /* @brief XBAR availability on the SoC. */ + #define FSL_FEATURE_SOC_XBAR_COUNT (0) + /* @brief XBARA availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARA_COUNT (0) + /* @brief XBARB availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARB_COUNT (0) + /* @brief XCVR availability on the SoC. */ + #define FSL_FEATURE_SOC_XCVR_COUNT (0) + /* @brief XRDC availability on the SoC. */ + #define FSL_FEATURE_SOC_XRDC_COUNT (0) + /* @brief ZLL availability on the SoC. */ + #define FSL_FEATURE_SOC_ZLL_COUNT (0) +#elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) + /* @brief ACMP availability on the SoC. */ + #define FSL_FEATURE_SOC_ACMP_COUNT (0) + /* @brief ADC16 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC16_COUNT (2) + /* @brief ADC12 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC12_COUNT (0) + /* @brief AFE availability on the SoC. */ + #define FSL_FEATURE_SOC_AFE_COUNT (0) + /* @brief AIPS availability on the SoC. */ + #define FSL_FEATURE_SOC_AIPS_COUNT (2) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (0) + /* @brief AXBS availability on the SoC. */ + #define FSL_FEATURE_SOC_AXBS_COUNT (1) + /* @brief ASMC availability on the SoC. */ + #define FSL_FEATURE_SOC_ASMC_COUNT (0) + /* @brief CADC availability on the SoC. */ + #define FSL_FEATURE_SOC_CADC_COUNT (0) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief MMCAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMCAU_COUNT (1) + /* @brief CMP availability on the SoC. */ + #define FSL_FEATURE_SOC_CMP_COUNT (3) + /* @brief CMT availability on the SoC. */ + #define FSL_FEATURE_SOC_CMT_COUNT (1) + /* @brief CNC availability on the SoC. */ + #define FSL_FEATURE_SOC_CNC_COUNT (0) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief DAC availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC_COUNT (1) + /* @brief DAC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC32_COUNT (0) + /* @brief DCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_DCDC_COUNT (0) + /* @brief DDR availability on the SoC. */ + #define FSL_FEATURE_SOC_DDR_COUNT (0) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (0) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief DMAMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) + /* @brief DRY availability on the SoC. */ + #define FSL_FEATURE_SOC_DRY_COUNT (0) + /* @brief DSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_DSPI_COUNT (3) + /* @brief EMVSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (0) + /* @brief ENET availability on the SoC. */ + #define FSL_FEATURE_SOC_ENET_COUNT (1) + /* @brief EWM availability on the SoC. */ + #define FSL_FEATURE_SOC_EWM_COUNT (1) + /* @brief FB availability on the SoC. */ + #define FSL_FEATURE_SOC_FB_COUNT (1) + /* @brief FGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FGPIO_COUNT (0) + /* @brief FLEXIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FSKDT availability on the SoC. */ + #define FSL_FEATURE_SOC_FSKDT_COUNT (0) + /* @brief FTFA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFA_COUNT (0) + /* @brief FTFE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFE_COUNT (1) + /* @brief FTFL availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFL_COUNT (0) + /* @brief FTM availability on the SoC. */ + #define FSL_FEATURE_SOC_FTM_COUNT (4) + /* @brief FTMRA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRA_COUNT (0) + /* @brief FTMRE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRE_COUNT (0) + /* @brief FTMRH availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRH_COUNT (0) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief HSADC availability on the SoC. */ + #define FSL_FEATURE_SOC_HSADC_COUNT (0) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (3) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (1) + /* @brief ICS availability on the SoC. */ + #define FSL_FEATURE_SOC_ICS_COUNT (0) + /* @brief INTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INTMUX_COUNT (0) + /* @brief IRQ availability on the SoC. */ + #define FSL_FEATURE_SOC_IRQ_COUNT (0) + /* @brief KBI availability on the SoC. */ + #define FSL_FEATURE_SOC_KBI_COUNT (0) + /* @brief SLCD availability on the SoC. */ + #define FSL_FEATURE_SOC_SLCD_COUNT (0) + /* @brief LCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_LCDC_COUNT (0) + /* @brief LDO availability on the SoC. */ + #define FSL_FEATURE_SOC_LDO_COUNT (0) + /* @brief LLWU availability on the SoC. */ + #define FSL_FEATURE_SOC_LLWU_COUNT (1) + /* @brief LMEM availability on the SoC. */ + #define FSL_FEATURE_SOC_LMEM_COUNT (0) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (0) + /* @brief LPIT availability on the SoC. */ + #define FSL_FEATURE_SOC_LPIT_COUNT (0) + /* @brief LPSCI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSCI_COUNT (0) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (0) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPTPM availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTPM_COUNT (0) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (0) + /* @brief LTC availability on the SoC. */ + #define FSL_FEATURE_SOC_LTC_COUNT (0) + /* @brief MC availability on the SoC. */ + #define FSL_FEATURE_SOC_MC_COUNT (0) + /* @brief MCG availability on the SoC. */ + #define FSL_FEATURE_SOC_MCG_COUNT (1) + /* @brief MCGLITE availability on the SoC. */ + #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) + /* @brief MCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MCM_COUNT (1) + /* @brief MMAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMAU_COUNT (0) + /* @brief MMDVSQ availability on the SoC. */ + #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) + /* @brief MPU availability on the SoC. */ + #define FSL_FEATURE_SOC_MPU_COUNT (1) + /* @brief MSCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCAN_COUNT (0) + /* @brief MSCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCM_COUNT (0) + /* @brief MTB availability on the SoC. */ + #define FSL_FEATURE_SOC_MTB_COUNT (0) + /* @brief MTBDWT availability on the SoC. */ + #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) + /* @brief MU availability on the SoC. */ + #define FSL_FEATURE_SOC_MU_COUNT (0) + /* @brief NFC availability on the SoC. */ + #define FSL_FEATURE_SOC_NFC_COUNT (0) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (0) + /* @brief OSC availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC_COUNT (1) + /* @brief OSC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC32_COUNT (0) + /* @brief OTFAD availability on the SoC. */ + #define FSL_FEATURE_SOC_OTFAD_COUNT (0) + /* @brief PDB availability on the SoC. */ + #define FSL_FEATURE_SOC_PDB_COUNT (1) + /* @brief PCC availability on the SoC. */ + #define FSL_FEATURE_SOC_PCC_COUNT (0) + /* @brief PGA availability on the SoC. */ + #define FSL_FEATURE_SOC_PGA_COUNT (0) + /* @brief PIT availability on the SoC. */ + #define FSL_FEATURE_SOC_PIT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (0) + /* @brief PWT availability on the SoC. */ + #define FSL_FEATURE_SOC_PWT_COUNT (0) + /* @brief QuadSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) + /* @brief RCM availability on the SoC. */ + #define FSL_FEATURE_SOC_RCM_COUNT (1) + /* @brief RFSYS availability on the SoC. */ + #define FSL_FEATURE_SOC_RFSYS_COUNT (1) + /* @brief RFVBAT availability on the SoC. */ + #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) + /* @brief RNG availability on the SoC. */ + #define FSL_FEATURE_SOC_RNG_COUNT (1) + /* @brief RNGB availability on the SoC. */ + #define FSL_FEATURE_SOC_RNGB_COUNT (0) + /* @brief ROM availability on the SoC. */ + #define FSL_FEATURE_SOC_ROM_COUNT (0) + /* @brief RSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_RSIM_COUNT (0) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (0) + /* @brief SCI availability on the SoC. */ + #define FSL_FEATURE_SOC_SCI_COUNT (0) + /* @brief SDHC availability on the SoC. */ + #define FSL_FEATURE_SOC_SDHC_COUNT (1) + /* @brief SDRAM availability on the SoC. */ + #define FSL_FEATURE_SOC_SDRAM_COUNT (0) + /* @brief SEMA42 availability on the SoC. */ + #define FSL_FEATURE_SOC_SEMA42_COUNT (0) + /* @brief SIM availability on the SoC. */ + #define FSL_FEATURE_SOC_SIM_COUNT (1) + /* @brief SMC availability on the SoC. */ + #define FSL_FEATURE_SOC_SMC_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (0) + /* @brief TMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TMR_COUNT (0) + /* @brief TPM availability on the SoC. */ + #define FSL_FEATURE_SOC_TPM_COUNT (0) + /* @brief TRGMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) + /* @brief TRIAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) + /* @brief TRNG availability on the SoC. */ + #define FSL_FEATURE_SOC_TRNG_COUNT (0) + /* @brief TSI availability on the SoC. */ + #define FSL_FEATURE_SOC_TSI_COUNT (0) + /* @brief TSTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TSTMR_COUNT (0) + /* @brief UART availability on the SoC. */ + #define FSL_FEATURE_SOC_UART_COUNT (6) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBDCD_COUNT (1) + /* @brief USBHSDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) + /* @brief USBPHY availability on the SoC. */ + #define FSL_FEATURE_SOC_USBPHY_COUNT (0) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_WDOG_COUNT (1) + /* @brief XBAR availability on the SoC. */ + #define FSL_FEATURE_SOC_XBAR_COUNT (0) + /* @brief XBARA availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARA_COUNT (0) + /* @brief XBARB availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARB_COUNT (0) + /* @brief XCVR availability on the SoC. */ + #define FSL_FEATURE_SOC_XCVR_COUNT (0) + /* @brief XRDC availability on the SoC. */ + #define FSL_FEATURE_SOC_XRDC_COUNT (0) + /* @brief ZLL availability on the SoC. */ + #define FSL_FEATURE_SOC_ZLL_COUNT (0) +#endif + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ +#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) +/* @brief Has bitfield name BUF31TO0M. */ +#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) +/* @brief Number of interrupt vectors. */ +#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (16) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) +/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* ENET module features */ + +/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */ +#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0) +/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */ +#define FSL_FEATURE_ENET_SUPPORT_PTP (1) +/* @brief Number of associated interrupt vectors. */ +#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) +/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ +#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (0) + +/* FLEXBUS module features */ + +/* No feature definitions */ + +/* FLASH module features */ + +#if defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (1) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#elif defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (1) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#endif /* defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) */ + +/* FTM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == FTM0 ? (8) : \ + ((x) == FTM1 ? (2) : \ + ((x) == FTM2 ? (2) : \ + ((x) == FTM3 ? (8) : (-1))))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Enable pwm output for the module. */ +#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) +/* @brief Has half-cycle reload for the module. */ +#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) +/* @brief Has reload interrupt. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) +/* @brief Has reload initialization trigger. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) +/* @brief Ihe interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (1) + +/* LLWU module features */ + +/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) +/* @brief Has pins 8-15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) +/* @brief Maximum number of internal modules connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) +/* @brief Number of digital filters. */ +#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) +/* @brief Has MF5 register. */ +#define FSL_FEATURE_LLWU_HAS_MF (0) +/* @brief Has PF register. */ +#define FSL_FEATURE_LLWU_HAS_PF (0) +/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ +#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) +/* @brief Has external pin 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) +/* @brief Has external pin 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) +/* @brief Has external pin 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) +/* @brief Has external pin 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) +/* @brief Has external pin 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) +/* @brief Has external pin 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) +/* @brief Has external pin 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) +/* @brief Has external pin 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) +/* @brief Has external pin 8 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) +/* @brief Has external pin 9 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) +/* @brief Has external pin 10 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) +/* @brief Has external pin 11 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) +/* @brief Has external pin 12 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) +/* @brief Has external pin 13 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) +/* @brief Has external pin 14 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) +/* @brief Has external pin 15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) +/* @brief Has external pin 16 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) +/* @brief Has external pin 17 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) +/* @brief Has external pin 18 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) +/* @brief Has external pin 19 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) +/* @brief Has external pin 20 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) +/* @brief Has external pin 21 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) +/* @brief Has external pin 22 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) +/* @brief Has external pin 23 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) +/* @brief Has external pin 24 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) +/* @brief Has external pin 25 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) +/* @brief Has external pin 26 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) +/* @brief Has external pin 27 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) +/* @brief Has external pin 28 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) +/* @brief Has external pin 29 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) +/* @brief Has external pin 30 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) +/* @brief Has external pin 31 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) +/* @brief Has internal module 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) +/* @brief Has internal module 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) +/* @brief Has internal module 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) +/* @brief Has internal module 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) +/* @brief Has internal module 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) +/* @brief Has internal module 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) +/* @brief Has internal module 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) +/* @brief Has internal module 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) +/* @brief Has Version ID Register (LLWU_VERID). */ +#define FSL_FEATURE_LLWU_HAS_VERID (0) +/* @brief Has Parameter Register (LLWU_PARAM). */ +#define FSL_FEATURE_LLWU_HAS_PARAM (0) +/* @brief Width of registers of the LLWU. */ +#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) +/* @brief Has DMA Enable register (LLWU_DE). */ +#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (1) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (1) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL (1) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* MPU module features */ + +/* @brief Specifies number of descriptors available. */ +#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12) +/* @brief Has process identifier support. */ +#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1) +/* @brief Has master 0. */ +#define FSL_FEATURE_MPU_HAS_MASTER0 (1) +/* @brief Has master 1. */ +#define FSL_FEATURE_MPU_HAS_MASTER1 (1) +/* @brief Has master 2. */ +#define FSL_FEATURE_MPU_HAS_MASTER2 (1) +/* @brief Has master 3. */ +#define FSL_FEATURE_MPU_HAS_MASTER3 (1) +/* @brief Has master 4. */ +#define FSL_FEATURE_MPU_HAS_MASTER4 (1) +/* @brief Has master 5. */ +#define FSL_FEATURE_MPU_HAS_MASTER5 (1) +/* @brief Has master 6. */ +#define FSL_FEATURE_MPU_HAS_MASTER6 (0) +/* @brief Has master 7. */ +#define FSL_FEATURE_MPU_HAS_MASTER7 (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (0) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (1) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) + +/* PDB module features */ + +/* @brief Define the count of supporting ADC pre-trigger for each channel. */ +#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) +/* @brief Has DAC support. */ +#define FSL_FEATURE_PDB_HAS_DAC (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (1) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (0) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (1) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (1) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (1) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (1) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +#if defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) + /* @brief Has wakeup pin. */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has wakeup pin selection (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (1) + /* @brief Has RTC_CLKIN available. */ + #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) + /* @brief Has prescaler adjust for LPO. */ + #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) + /* @brief Has Clock Pin Enable field. */ + #define FSL_FEATURE_RTC_HAS_CPE (0) + /* @brief Has Timer Seconds Interrupt Configuration field. */ + #define FSL_FEATURE_RTC_HAS_TSIC (0) + /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ + #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) +#elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) + /* @brief Has wakeup pin. */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has wakeup pin selection (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (0) + /* @brief Has RTC_CLKIN available. */ + #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) + /* @brief Has prescaler adjust for LPO. */ + #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) + /* @brief Has Clock Pin Enable field. */ + #define FSL_FEATURE_RTC_HAS_CPE (0) + /* @brief Has Timer Seconds Interrupt Configuration field. */ + #define FSL_FEATURE_RTC_HAS_TSIC (0) + /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ + #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) +#endif /* defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VDC12) || \ + defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */ + +/* SDHC module features */ + +/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ +#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) +/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ +#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) +/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ +#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (4) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (1) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (0) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (0) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (0) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (1) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == DSPI0 ? (4) : \ + ((x) == DSPI1 ? (1) : \ + ((x) == DSPI2 ? (1) : (-1)))) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == DSPI0 ? (1) : \ + ((x) == DSPI1 ? (0) : \ + ((x) == DSPI2 ? (0) : (-1)))) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* UART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_HAS_FIFO (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) +/* @brief Peripheral type. */ +#define FSL_FEATURE_UART_IS_SCI (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (8) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (1) : \ + ((x) == UART5 ? (1) : (-1))))))) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_UART_HAS_DMA_SELECT (1) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == UART0 ? (1) : \ + ((x) == UART1 ? (1) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (0) : \ + ((x) == UART5 ? (0) : (-1))))))) + +/* USB module features */ + +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief Describes the set of SC[MODE_LV] bitfield values */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief Has Wait mode support. */ +#define FSL_FEATURE_WDOG_HAS_WAITEN (1) + +#endif /* _MK64F12_FEATURES_H_ */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct new file mode 100644 index 00000000000..5409a2e9f1f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct @@ -0,0 +1,130 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151009 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +#define __ram_vector_table__ 1 + +/* Heap 1/4 of ram and stack 1/8 */ +#define __stack_size__ 0x8000 +#define __heap_size__ 0x10000 + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000400 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_flash_config_start 0x00000400 +#define m_flash_config_size 0x00000010 + +#define m_text_start 0x00000410 +#define m_text_size 0x000FFBF0 + +#define m_interrupts_ram_start 0x1FFF0000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x00010000 - m_interrupts_ram_size) + +#define m_data_2_start 0x20000000 +#define m_data_2_size 0x00030000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM1 ((ImageLimit(RW_m_data_2) == m_data_2_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { +#if (!defined(__ram_vector_table__)) + VECTOR_RAM m_interrupts_start EMPTY 0 { + } +#endif + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} + +LR_m_flash_config m_flash_config_start m_flash_config_size { + ER_m_flash_config m_flash_config_start m_flash_config_size { ; load address = execution address + * (FlashConfig) + } +} + +#if (defined(__ram_vector_table__)) +LR_m_interrupts_ram m_interrupts_ram_start m_interrupts_ram_size { + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } +} +#endif + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S new file mode 100644 index 00000000000..debbfe77dcc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S @@ -0,0 +1,1051 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MK64F12.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * MK64F12 +; * @version: 2.8 +; * @date: 2015-2-19 +; * @build: b151210 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20030000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD UART0_LON_IRQHandler ;UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ;UART5 Error interrupt + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD ENET_1588_Timer_IRQHandler ;Ethernet MAC IEEE 1588 Timer Interrupt + DCD ENET_Transmit_IRQHandler ;Ethernet MAC Transmit Interrupt + DCD ENET_Receive_IRQHandler ;Ethernet MAC Receive Interrupt + DCD ENET_Error_IRQHandler ;Ethernet MAC Error and miscelaneous Interrupt + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Data flash protection byte (FDPROT) +; Each bit protects a 1/8 region of the data flash memory. +; (Program flash only devices: Reserved) +; FDPROT.0 +; FDPROT.1 +; FDPROT.2 +; FDPROT.3 +; FDPROT.4 +; FDPROT.5 +; FDPROT.6 +; FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; +; EEPROM protection byte (FEPROT) +; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; (Program flash only devices: Reserved) +; FEPROT.0 +; FEPROT.1 +; FEPROT.2 +; FEPROT.3 +; FEPROT.4 +; FEPROT.5 +; FEPROT.6 +; FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; EZPORT_DIS +; <0=> EzPort operation is disabled +; <1=> EzPort operation is enabled +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , FEPROT , FDPROT + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA8_IRQHandler\ + PROC + EXPORT DMA8_IRQHandler [WEAK] + LDR R0, =DMA8_DriverIRQHandler + BX R0 + ENDP + +DMA9_IRQHandler\ + PROC + EXPORT DMA9_IRQHandler [WEAK] + LDR R0, =DMA9_DriverIRQHandler + BX R0 + ENDP + +DMA10_IRQHandler\ + PROC + EXPORT DMA10_IRQHandler [WEAK] + LDR R0, =DMA10_DriverIRQHandler + BX R0 + ENDP + +DMA11_IRQHandler\ + PROC + EXPORT DMA11_IRQHandler [WEAK] + LDR R0, =DMA11_DriverIRQHandler + BX R0 + ENDP + +DMA12_IRQHandler\ + PROC + EXPORT DMA12_IRQHandler [WEAK] + LDR R0, =DMA12_DriverIRQHandler + BX R0 + ENDP + +DMA13_IRQHandler\ + PROC + EXPORT DMA13_IRQHandler [WEAK] + LDR R0, =DMA13_DriverIRQHandler + BX R0 + ENDP + +DMA14_IRQHandler\ + PROC + EXPORT DMA14_IRQHandler [WEAK] + LDR R0, =DMA14_DriverIRQHandler + BX R0 + ENDP + +DMA15_IRQHandler\ + PROC + EXPORT DMA15_IRQHandler [WEAK] + LDR R0, =DMA15_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +I2S0_Tx_IRQHandler\ + PROC + EXPORT I2S0_Tx_IRQHandler [WEAK] + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + ENDP + +I2S0_Rx_IRQHandler\ + PROC + EXPORT I2S0_Rx_IRQHandler [WEAK] + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + ENDP + +UART0_LON_IRQHandler\ + PROC + EXPORT UART0_LON_IRQHandler [WEAK] + LDR R0, =UART0_LON_DriverIRQHandler + BX R0 + ENDP + +UART0_RX_TX_IRQHandler\ + PROC + EXPORT UART0_RX_TX_IRQHandler [WEAK] + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART0_ERR_IRQHandler\ + PROC + EXPORT UART0_ERR_IRQHandler [WEAK] + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + ENDP + +UART1_RX_TX_IRQHandler\ + PROC + EXPORT UART1_RX_TX_IRQHandler [WEAK] + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART1_ERR_IRQHandler\ + PROC + EXPORT UART1_ERR_IRQHandler [WEAK] + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + ENDP + +UART2_RX_TX_IRQHandler\ + PROC + EXPORT UART2_RX_TX_IRQHandler [WEAK] + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART2_ERR_IRQHandler\ + PROC + EXPORT UART2_ERR_IRQHandler [WEAK] + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + ENDP + +UART3_RX_TX_IRQHandler\ + PROC + EXPORT UART3_RX_TX_IRQHandler [WEAK] + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART3_ERR_IRQHandler\ + PROC + EXPORT UART3_ERR_IRQHandler [WEAK] + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + ENDP + +SPI2_IRQHandler\ + PROC + EXPORT SPI2_IRQHandler [WEAK] + LDR R0, =SPI2_DriverIRQHandler + BX R0 + ENDP + +UART4_RX_TX_IRQHandler\ + PROC + EXPORT UART4_RX_TX_IRQHandler [WEAK] + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART4_ERR_IRQHandler\ + PROC + EXPORT UART4_ERR_IRQHandler [WEAK] + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + ENDP + +UART5_RX_TX_IRQHandler\ + PROC + EXPORT UART5_RX_TX_IRQHandler [WEAK] + LDR R0, =UART5_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART5_ERR_IRQHandler\ + PROC + EXPORT UART5_ERR_IRQHandler [WEAK] + LDR R0, =UART5_ERR_DriverIRQHandler + BX R0 + ENDP + +I2C2_IRQHandler\ + PROC + EXPORT I2C2_IRQHandler [WEAK] + LDR R0, =I2C2_DriverIRQHandler + BX R0 + ENDP + +CAN0_ORed_Message_buffer_IRQHandler\ + PROC + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Bus_Off_IRQHandler\ + PROC + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Error_IRQHandler\ + PROC + EXPORT CAN0_Error_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Tx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Rx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Wake_Up_IRQHandler\ + PROC + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +SDHC_IRQHandler\ + PROC + EXPORT SDHC_IRQHandler [WEAK] + LDR R0, =SDHC_DriverIRQHandler + BX R0 + ENDP + +ENET_1588_Timer_IRQHandler\ + PROC + EXPORT ENET_1588_Timer_IRQHandler [WEAK] + LDR R0, =ENET_1588_Timer_DriverIRQHandler + BX R0 + ENDP + +ENET_Transmit_IRQHandler\ + PROC + EXPORT ENET_Transmit_IRQHandler [WEAK] + LDR R0, =ENET_Transmit_DriverIRQHandler + BX R0 + ENDP + +ENET_Receive_IRQHandler\ + PROC + EXPORT ENET_Receive_IRQHandler [WEAK] + LDR R0, =ENET_Receive_DriverIRQHandler + BX R0 + ENDP + +ENET_Error_IRQHandler\ + PROC + EXPORT ENET_Error_IRQHandler [WEAK] + LDR R0, =ENET_Error_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT DMA8_DriverIRQHandler [WEAK] + EXPORT DMA9_DriverIRQHandler [WEAK] + EXPORT DMA10_DriverIRQHandler [WEAK] + EXPORT DMA11_DriverIRQHandler [WEAK] + EXPORT DMA12_DriverIRQHandler [WEAK] + EXPORT DMA13_DriverIRQHandler [WEAK] + EXPORT DMA14_DriverIRQHandler [WEAK] + EXPORT DMA15_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTFE_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT I2S0_Tx_DriverIRQHandler [WEAK] + EXPORT I2S0_Rx_DriverIRQHandler [WEAK] + EXPORT UART0_LON_DriverIRQHandler [WEAK] + EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART0_ERR_DriverIRQHandler [WEAK] + EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART1_ERR_DriverIRQHandler [WEAK] + EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART2_ERR_DriverIRQHandler [WEAK] + EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART3_ERR_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT SPI2_DriverIRQHandler [WEAK] + EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART4_ERR_DriverIRQHandler [WEAK] + EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART5_ERR_DriverIRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT I2C2_DriverIRQHandler [WEAK] + EXPORT CAN0_DriverIRQHandler [WEAK] + EXPORT SDHC_DriverIRQHandler [WEAK] + EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK] + EXPORT ENET_Transmit_DriverIRQHandler [WEAK] + EXPORT ENET_Receive_DriverIRQHandler [WEAK] + EXPORT ENET_Error_DriverIRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +UART0_LON_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +UART5_RX_TX_DriverIRQHandler +UART5_ERR_DriverIRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +ENET_1588_Timer_DriverIRQHandler +ENET_Transmit_DriverIRQHandler +ENET_Receive_DriverIRQHandler +ENET_Error_DriverIRQHandler +DefaultISR + B DefaultISR + ENDP + ALIGN + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..b129b2c2a5b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld new file mode 100644 index 00000000000..d77d225f64c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld @@ -0,0 +1,267 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: GNU C Compiler +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151217 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +__stack_size__ = 0x8000; +__heap_size__ = 0x10000; + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + . = ALIGN(512); + USB_RAM_START = .; + . += USB_RAM_GAP; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data_2 + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data_2 + + m_usb_bdt USB_RAM_START (NOLOAD) : + { + *(m_usb_bdt) + USB_RAM_BDT_END = .; + } + + m_usb_global USB_RAM_BDT_END (NOLOAD) : + { + *(m_usb_global) + } + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S new file mode 100644 index 00000000000..b91177dc283 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S @@ -0,0 +1,993 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MK64F12.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MK64F12 */ +/* @version: 2.8 */ +/* @date: 2015-2-19 */ +/* @build: b151210 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ + .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ + .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ + .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ + .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/ + .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/ + .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/ + .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/ + .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/ + .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/ + .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/ + .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/ + .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/ + .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/ + .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/ + .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/ + .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ + .long MCM_IRQHandler /* Normal Interrupt*/ + .long FTFE_IRQHandler /* FTFE Command complete interrupt*/ + .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ + .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/ + .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ + .long RNG_IRQHandler /* RNG Interrupt*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 Interrupt*/ + .long SPI1_IRQHandler /* SPI1 Interrupt*/ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ + .long UART0_LON_IRQHandler /* UART0 LON interrupt*/ + .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ + .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ + .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ + .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ + .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ + .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ + .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/ + .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long CMP1_IRQHandler /* CMP1 interrupt*/ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ + .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ + .long CMT_IRQHandler /* CMT interrupt*/ + .long RTC_IRQHandler /* RTC interrupt*/ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ + .long PDB0_IRQHandler /* PDB0 Interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long USBDCD_IRQHandler /* USBDCD Interrupt*/ + .long Reserved71_IRQHandler /* Reserved interrupt 71*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long MCG_IRQHandler /* MCG Interrupt*/ + .long LPTMR0_IRQHandler /* LPTimer interrupt*/ + .long PORTA_IRQHandler /* Port A interrupt*/ + .long PORTB_IRQHandler /* Port B interrupt*/ + .long PORTC_IRQHandler /* Port C interrupt*/ + .long PORTD_IRQHandler /* Port D interrupt*/ + .long PORTE_IRQHandler /* Port E interrupt*/ + .long SWI_IRQHandler /* Software interrupt*/ + .long SPI2_IRQHandler /* SPI2 Interrupt*/ + .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/ + .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/ + .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/ + .long UART5_ERR_IRQHandler /* UART5 Error interrupt*/ + .long CMP2_IRQHandler /* CMP2 interrupt*/ + .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ + .long DAC1_IRQHandler /* DAC1 interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long I2C2_IRQHandler /* I2C2 interrupt*/ + .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/ + .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/ + .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/ + .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/ + .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/ + .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/ + .long SDHC_IRQHandler /* SDHC interrupt*/ + .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/ + .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/ + .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/ + .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/ + .long DefaultISR /* 102*/ + .long DefaultISR /* 103*/ + .long DefaultISR /* 104*/ + .long DefaultISR /* 105*/ + .long DefaultISR /* 106*/ + .long DefaultISR /* 107*/ + .long DefaultISR /* 108*/ + .long DefaultISR /* 109*/ + .long DefaultISR /* 110*/ + .long DefaultISR /* 111*/ + .long DefaultISR /* 112*/ + .long DefaultISR /* 113*/ + .long DefaultISR /* 114*/ + .long DefaultISR /* 115*/ + .long DefaultISR /* 116*/ + .long DefaultISR /* 117*/ + .long DefaultISR /* 118*/ + .long DefaultISR /* 119*/ + .long DefaultISR /* 120*/ + .long DefaultISR /* 121*/ + .long DefaultISR /* 122*/ + .long DefaultISR /* 123*/ + .long DefaultISR /* 124*/ + .long DefaultISR /* 125*/ + .long DefaultISR /* 126*/ + .long DefaultISR /* 127*/ + .long DefaultISR /* 128*/ + .long DefaultISR /* 129*/ + .long DefaultISR /* 130*/ + .long DefaultISR /* 131*/ + .long DefaultISR /* 132*/ + .long DefaultISR /* 133*/ + .long DefaultISR /* 134*/ + .long DefaultISR /* 135*/ + .long DefaultISR /* 136*/ + .long DefaultISR /* 137*/ + .long DefaultISR /* 138*/ + .long DefaultISR /* 139*/ + .long DefaultISR /* 140*/ + .long DefaultISR /* 141*/ + .long DefaultISR /* 142*/ + .long DefaultISR /* 143*/ + .long DefaultISR /* 144*/ + .long DefaultISR /* 145*/ + .long DefaultISR /* 146*/ + .long DefaultISR /* 147*/ + .long DefaultISR /* 148*/ + .long DefaultISR /* 149*/ + .long DefaultISR /* 150*/ + .long DefaultISR /* 151*/ + .long DefaultISR /* 152*/ + .long DefaultISR /* 153*/ + .long DefaultISR /* 154*/ + .long DefaultISR /* 155*/ + .long DefaultISR /* 156*/ + .long DefaultISR /* 157*/ + .long DefaultISR /* 158*/ + .long DefaultISR /* 159*/ + .long DefaultISR /* 160*/ + .long DefaultISR /* 161*/ + .long DefaultISR /* 162*/ + .long DefaultISR /* 163*/ + .long DefaultISR /* 164*/ + .long DefaultISR /* 165*/ + .long DefaultISR /* 166*/ + .long DefaultISR /* 167*/ + .long DefaultISR /* 168*/ + .long DefaultISR /* 169*/ + .long DefaultISR /* 170*/ + .long DefaultISR /* 171*/ + .long DefaultISR /* 172*/ + .long DefaultISR /* 173*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_IRQHandler + .type DMA4_IRQHandler, %function +DMA4_IRQHandler: + ldr r0,=DMA4_DriverIRQHandler + bx r0 + .size DMA4_IRQHandler, . - DMA4_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_IRQHandler + .type DMA5_IRQHandler, %function +DMA5_IRQHandler: + ldr r0,=DMA5_DriverIRQHandler + bx r0 + .size DMA5_IRQHandler, . - DMA5_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_IRQHandler + .type DMA6_IRQHandler, %function +DMA6_IRQHandler: + ldr r0,=DMA6_DriverIRQHandler + bx r0 + .size DMA6_IRQHandler, . - DMA6_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_IRQHandler + .type DMA7_IRQHandler, %function +DMA7_IRQHandler: + ldr r0,=DMA7_DriverIRQHandler + bx r0 + .size DMA7_IRQHandler, . - DMA7_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_IRQHandler + .type DMA8_IRQHandler, %function +DMA8_IRQHandler: + ldr r0,=DMA8_DriverIRQHandler + bx r0 + .size DMA8_IRQHandler, . - DMA8_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_IRQHandler + .type DMA9_IRQHandler, %function +DMA9_IRQHandler: + ldr r0,=DMA9_DriverIRQHandler + bx r0 + .size DMA9_IRQHandler, . - DMA9_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_IRQHandler + .type DMA10_IRQHandler, %function +DMA10_IRQHandler: + ldr r0,=DMA10_DriverIRQHandler + bx r0 + .size DMA10_IRQHandler, . - DMA10_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_IRQHandler + .type DMA11_IRQHandler, %function +DMA11_IRQHandler: + ldr r0,=DMA11_DriverIRQHandler + bx r0 + .size DMA11_IRQHandler, . - DMA11_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_IRQHandler + .type DMA12_IRQHandler, %function +DMA12_IRQHandler: + ldr r0,=DMA12_DriverIRQHandler + bx r0 + .size DMA12_IRQHandler, . - DMA12_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_IRQHandler + .type DMA13_IRQHandler, %function +DMA13_IRQHandler: + ldr r0,=DMA13_DriverIRQHandler + bx r0 + .size DMA13_IRQHandler, . - DMA13_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_IRQHandler + .type DMA14_IRQHandler, %function +DMA14_IRQHandler: + ldr r0,=DMA14_DriverIRQHandler + bx r0 + .size DMA14_IRQHandler, . - DMA14_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_IRQHandler + .type DMA15_IRQHandler, %function +DMA15_IRQHandler: + ldr r0,=DMA15_DriverIRQHandler + bx r0 + .size DMA15_IRQHandler, . - DMA15_IRQHandler + + .align 1 + .thumb_func + .weak DMA_Error_IRQHandler + .type DMA_Error_IRQHandler, %function +DMA_Error_IRQHandler: + ldr r0,=DMA_Error_DriverIRQHandler + bx r0 + .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Tx_IRQHandler + .type I2S0_Tx_IRQHandler, %function +I2S0_Tx_IRQHandler: + ldr r0,=I2S0_Tx_DriverIRQHandler + bx r0 + .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Rx_IRQHandler + .type I2S0_Rx_IRQHandler, %function +I2S0_Rx_IRQHandler: + ldr r0,=I2S0_Rx_DriverIRQHandler + bx r0 + .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler + + .align 1 + .thumb_func + .weak UART0_LON_IRQHandler + .type UART0_LON_IRQHandler, %function +UART0_LON_IRQHandler: + ldr r0,=UART0_LON_DriverIRQHandler + bx r0 + .size UART0_LON_IRQHandler, . - UART0_LON_IRQHandler + + .align 1 + .thumb_func + .weak UART0_RX_TX_IRQHandler + .type UART0_RX_TX_IRQHandler, %function +UART0_RX_TX_IRQHandler: + ldr r0,=UART0_RX_TX_DriverIRQHandler + bx r0 + .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART0_ERR_IRQHandler + .type UART0_ERR_IRQHandler, %function +UART0_ERR_IRQHandler: + ldr r0,=UART0_ERR_DriverIRQHandler + bx r0 + .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART1_RX_TX_IRQHandler + .type UART1_RX_TX_IRQHandler, %function +UART1_RX_TX_IRQHandler: + ldr r0,=UART1_RX_TX_DriverIRQHandler + bx r0 + .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART1_ERR_IRQHandler + .type UART1_ERR_IRQHandler, %function +UART1_ERR_IRQHandler: + ldr r0,=UART1_ERR_DriverIRQHandler + bx r0 + .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART2_RX_TX_IRQHandler + .type UART2_RX_TX_IRQHandler, %function +UART2_RX_TX_IRQHandler: + ldr r0,=UART2_RX_TX_DriverIRQHandler + bx r0 + .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART2_ERR_IRQHandler + .type UART2_ERR_IRQHandler, %function +UART2_ERR_IRQHandler: + ldr r0,=UART2_ERR_DriverIRQHandler + bx r0 + .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART3_RX_TX_IRQHandler + .type UART3_RX_TX_IRQHandler, %function +UART3_RX_TX_IRQHandler: + ldr r0,=UART3_RX_TX_DriverIRQHandler + bx r0 + .size UART3_RX_TX_IRQHandler, . - UART3_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART3_ERR_IRQHandler + .type UART3_ERR_IRQHandler, %function +UART3_ERR_IRQHandler: + ldr r0,=UART3_ERR_DriverIRQHandler + bx r0 + .size UART3_ERR_IRQHandler, . - UART3_ERR_IRQHandler + + .align 1 + .thumb_func + .weak SPI2_IRQHandler + .type SPI2_IRQHandler, %function +SPI2_IRQHandler: + ldr r0,=SPI2_DriverIRQHandler + bx r0 + .size SPI2_IRQHandler, . - SPI2_IRQHandler + + .align 1 + .thumb_func + .weak UART4_RX_TX_IRQHandler + .type UART4_RX_TX_IRQHandler, %function +UART4_RX_TX_IRQHandler: + ldr r0,=UART4_RX_TX_DriverIRQHandler + bx r0 + .size UART4_RX_TX_IRQHandler, . - UART4_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART4_ERR_IRQHandler + .type UART4_ERR_IRQHandler, %function +UART4_ERR_IRQHandler: + ldr r0,=UART4_ERR_DriverIRQHandler + bx r0 + .size UART4_ERR_IRQHandler, . - UART4_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART5_RX_TX_IRQHandler + .type UART5_RX_TX_IRQHandler, %function +UART5_RX_TX_IRQHandler: + ldr r0,=UART5_RX_TX_DriverIRQHandler + bx r0 + .size UART5_RX_TX_IRQHandler, . - UART5_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART5_ERR_IRQHandler + .type UART5_ERR_IRQHandler, %function +UART5_ERR_IRQHandler: + ldr r0,=UART5_ERR_DriverIRQHandler + bx r0 + .size UART5_ERR_IRQHandler, . - UART5_ERR_IRQHandler + + .align 1 + .thumb_func + .weak I2C2_IRQHandler + .type I2C2_IRQHandler, %function +I2C2_IRQHandler: + ldr r0,=I2C2_DriverIRQHandler + bx r0 + .size I2C2_IRQHandler, . - I2C2_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_ORed_Message_buffer_IRQHandler + .type CAN0_ORed_Message_buffer_IRQHandler, %function +CAN0_ORed_Message_buffer_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_ORed_Message_buffer_IRQHandler, . - CAN0_ORed_Message_buffer_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Bus_Off_IRQHandler + .type CAN0_Bus_Off_IRQHandler, %function +CAN0_Bus_Off_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Bus_Off_IRQHandler, . - CAN0_Bus_Off_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Error_IRQHandler + .type CAN0_Error_IRQHandler, %function +CAN0_Error_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Error_IRQHandler, . - CAN0_Error_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Tx_Warning_IRQHandler + .type CAN0_Tx_Warning_IRQHandler, %function +CAN0_Tx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Tx_Warning_IRQHandler, . - CAN0_Tx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Rx_Warning_IRQHandler + .type CAN0_Rx_Warning_IRQHandler, %function +CAN0_Rx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Rx_Warning_IRQHandler, . - CAN0_Rx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Wake_Up_IRQHandler + .type CAN0_Wake_Up_IRQHandler, %function +CAN0_Wake_Up_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Wake_Up_IRQHandler, . - CAN0_Wake_Up_IRQHandler + + .align 1 + .thumb_func + .weak SDHC_IRQHandler + .type SDHC_IRQHandler, %function +SDHC_IRQHandler: + ldr r0,=SDHC_DriverIRQHandler + bx r0 + .size SDHC_IRQHandler, . - SDHC_IRQHandler + + .align 1 + .thumb_func + .weak ENET_1588_Timer_IRQHandler + .type ENET_1588_Timer_IRQHandler, %function +ENET_1588_Timer_IRQHandler: + ldr r0,=ENET_1588_Timer_DriverIRQHandler + bx r0 + .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler + + .align 1 + .thumb_func + .weak ENET_Transmit_IRQHandler + .type ENET_Transmit_IRQHandler, %function +ENET_Transmit_IRQHandler: + ldr r0,=ENET_Transmit_DriverIRQHandler + bx r0 + .size ENET_Transmit_IRQHandler, . - ENET_Transmit_IRQHandler + + .align 1 + .thumb_func + .weak ENET_Receive_IRQHandler + .type ENET_Receive_IRQHandler, %function +ENET_Receive_IRQHandler: + ldr r0,=ENET_Receive_DriverIRQHandler + bx r0 + .size ENET_Receive_IRQHandler, . - ENET_Receive_IRQHandler + + .align 1 + .thumb_func + .weak ENET_Error_IRQHandler + .type ENET_Error_IRQHandler, %function +ENET_Error_IRQHandler: + ldr r0,=ENET_Error_DriverIRQHandler + bx r0 + .size ENET_Error_IRQHandler, . - ENET_Error_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler DMA4_DriverIRQHandler + def_irq_handler DMA5_DriverIRQHandler + def_irq_handler DMA6_DriverIRQHandler + def_irq_handler DMA7_DriverIRQHandler + def_irq_handler DMA8_DriverIRQHandler + def_irq_handler DMA9_DriverIRQHandler + def_irq_handler DMA10_DriverIRQHandler + def_irq_handler DMA11_DriverIRQHandler + def_irq_handler DMA12_DriverIRQHandler + def_irq_handler DMA13_DriverIRQHandler + def_irq_handler DMA14_DriverIRQHandler + def_irq_handler DMA15_DriverIRQHandler + def_irq_handler DMA_Error_DriverIRQHandler + def_irq_handler MCM_IRQHandler + def_irq_handler FTFE_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler WDOG_EWM_IRQHandler + def_irq_handler RNG_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler I2S0_Tx_DriverIRQHandler + def_irq_handler I2S0_Rx_DriverIRQHandler + def_irq_handler UART0_LON_DriverIRQHandler + def_irq_handler UART0_RX_TX_DriverIRQHandler + def_irq_handler UART0_ERR_DriverIRQHandler + def_irq_handler UART1_RX_TX_DriverIRQHandler + def_irq_handler UART1_ERR_DriverIRQHandler + def_irq_handler UART2_RX_TX_DriverIRQHandler + def_irq_handler UART2_ERR_DriverIRQHandler + def_irq_handler UART3_RX_TX_DriverIRQHandler + def_irq_handler UART3_ERR_DriverIRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler FTM2_IRQHandler + def_irq_handler CMT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USBDCD_IRQHandler + def_irq_handler Reserved71_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler SPI2_DriverIRQHandler + def_irq_handler UART4_RX_TX_DriverIRQHandler + def_irq_handler UART4_ERR_DriverIRQHandler + def_irq_handler UART5_RX_TX_DriverIRQHandler + def_irq_handler UART5_ERR_DriverIRQHandler + def_irq_handler CMP2_IRQHandler + def_irq_handler FTM3_IRQHandler + def_irq_handler DAC1_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler I2C2_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler SDHC_DriverIRQHandler + def_irq_handler ENET_1588_Timer_DriverIRQHandler + def_irq_handler ENET_Transmit_DriverIRQHandler + def_irq_handler ENET_Receive_DriverIRQHandler + def_irq_handler ENET_Error_DriverIRQHandler + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf new file mode 100644 index 00000000000..4b753e15d1b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf @@ -0,0 +1,118 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151009 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +define symbol __ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +define symbol __stack_size__=0x8000; +define symbol __heap_size__=0x10000; + +define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x000FFFFF; + +define symbol m_interrupts_ram_start = 0x1FFF0000; +define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x1FFFFFFF; + +define symbol m_data_2_start = 0x20000000; +define symbol m_data_2_end = 0x2002FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end] + | mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S new file mode 100644 index 00000000000..bcc689b9d80 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S @@ -0,0 +1,870 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MK64F12.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; MK64F12 +; @version: 2.8 +; @date: 2015-2-19 +; @build: b151210 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD UART0_LON_IRQHandler ;UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ;UART5 Error interrupt + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD ENET_1588_Timer_IRQHandler ;Ethernet MAC IEEE 1588 Timer Interrupt + DCD ENET_Transmit_IRQHandler ;Ethernet MAC Transmit Interrupt + DCD ENET_Receive_IRQHandler ;Ethernet MAC Receive Interrupt + DCD ENET_Error_IRQHandler ;Ethernet MAC Error and miscelaneous Interrupt + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_IRQHandler + LDR R0, =DMA8_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_IRQHandler + LDR R0, =DMA9_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_IRQHandler + LDR R0, =DMA10_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_IRQHandler + LDR R0, =DMA11_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA12_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_IRQHandler + LDR R0, =DMA12_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA13_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_IRQHandler + LDR R0, =DMA13_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA14_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_IRQHandler + LDR R0, =DMA14_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA15_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_IRQHandler + LDR R0, =DMA15_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK MCM_IRQHandler + PUBWEAK FTFE_IRQHandler + PUBWEAK Read_Collision_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RNG_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Tx_IRQHandler + PUBWEAK I2S0_Tx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Tx_IRQHandler + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Rx_IRQHandler + PUBWEAK I2S0_Rx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Rx_IRQHandler + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + + PUBWEAK UART0_LON_IRQHandler + PUBWEAK UART0_LON_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_LON_IRQHandler + LDR R0, =UART0_LON_DriverIRQHandler + BX R0 + + PUBWEAK UART0_RX_TX_IRQHandler + PUBWEAK UART0_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_RX_TX_IRQHandler + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART0_ERR_IRQHandler + PUBWEAK UART0_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_ERR_IRQHandler + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART1_RX_TX_IRQHandler + PUBWEAK UART1_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_RX_TX_IRQHandler + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART1_ERR_IRQHandler + PUBWEAK UART1_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_ERR_IRQHandler + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART2_RX_TX_IRQHandler + PUBWEAK UART2_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_RX_TX_IRQHandler + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART2_ERR_IRQHandler + PUBWEAK UART2_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_ERR_IRQHandler + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART3_RX_TX_IRQHandler + PUBWEAK UART3_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART3_RX_TX_IRQHandler + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART3_ERR_IRQHandler + PUBWEAK UART3_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART3_ERR_IRQHandler + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK FTM0_IRQHandler + PUBWEAK FTM1_IRQHandler + PUBWEAK FTM2_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK PIT1_IRQHandler + PUBWEAK PIT2_IRQHandler + PUBWEAK PIT3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK USBDCD_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK SPI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI2_IRQHandler + LDR R0, =SPI2_DriverIRQHandler + BX R0 + + PUBWEAK UART4_RX_TX_IRQHandler + PUBWEAK UART4_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART4_RX_TX_IRQHandler + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART4_ERR_IRQHandler + PUBWEAK UART4_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART4_ERR_IRQHandler + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART5_RX_TX_IRQHandler + PUBWEAK UART5_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART5_RX_TX_IRQHandler + LDR R0, =UART5_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART5_ERR_IRQHandler + PUBWEAK UART5_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART5_ERR_IRQHandler + LDR R0, =UART5_ERR_DriverIRQHandler + BX R0 + + PUBWEAK CMP2_IRQHandler + PUBWEAK FTM3_IRQHandler + PUBWEAK DAC1_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK I2C2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C2_IRQHandler + LDR R0, =I2C2_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_ORed_Message_buffer_IRQHandler + PUBWEAK CAN0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_ORed_Message_buffer_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Bus_Off_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Bus_Off_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Error_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Error_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Tx_Warning_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Tx_Warning_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Rx_Warning_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Rx_Warning_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Wake_Up_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Wake_Up_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK SDHC_IRQHandler + PUBWEAK SDHC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDHC_IRQHandler + LDR R0, =SDHC_DriverIRQHandler + BX R0 + + PUBWEAK ENET_1588_Timer_IRQHandler + PUBWEAK ENET_1588_Timer_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_1588_Timer_IRQHandler + LDR R0, =ENET_1588_Timer_DriverIRQHandler + BX R0 + + PUBWEAK ENET_Transmit_IRQHandler + PUBWEAK ENET_Transmit_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_Transmit_IRQHandler + LDR R0, =ENET_Transmit_DriverIRQHandler + BX R0 + + PUBWEAK ENET_Receive_IRQHandler + PUBWEAK ENET_Receive_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_Receive_IRQHandler + LDR R0, =ENET_Receive_DriverIRQHandler + BX R0 + + PUBWEAK ENET_Error_IRQHandler + PUBWEAK ENET_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_Error_IRQHandler + LDR R0, =ENET_Error_DriverIRQHandler + BX R0 + + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +UART0_LON_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +UART5_RX_TX_DriverIRQHandler +UART5_ERR_DriverIRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +ENET_1588_Timer_DriverIRQHandler +ENET_Transmit_DriverIRQHandler +ENET_Receive_DriverIRQHandler +ENET_Error_DriverIRQHandler +DefaultISR + B DefaultISR + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis.h new file mode 100644 index 00000000000..7423a125ba6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "fsl_device_registers.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c new file mode 100644 index 00000000000..59b37502b22 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InstallIRQHandler(IRQn, vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h new file mode 100644 index 00000000000..45141f5e2c8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/fsl_device_registers.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/fsl_device_registers.h new file mode 100644 index 00000000000..383809bbcf5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/fsl_device_registers.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ + defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ + defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)) + +#define K64F12_SERIES + +/* CMSIS-style register definitions */ +#include "MK64F12.h" +/* CPU specific feature definitions */ +#include "MK64F12_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.c new file mode 100644 index 00000000000..c04333ef268 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.c @@ -0,0 +1,247 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** MK64FX512VDC12 +** MK64FX512VLL12 +** MK64FX512VLQ12 +** MK64FX512VMD12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151216 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** +** ################################################################### +*/ + +/*! + * @file MK64F12 + * @version 2.8 + * @date 2015-02-19 + * @brief Device specific configuration file for MK64F12 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +#if (DISABLE_WDOG) + /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ + /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ + /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | + WDOG_STCTRLH_WAITEN_MASK | + WDOG_STCTRLH_STOPEN_MASK | + WDOG_STCTRLH_ALLOWUPDATE_MASK | + WDOG_STCTRLH_CLKSRC_MASK | + 0x0100U; +#endif /* (DISABLE_WDOG) */ + +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x00U: + MCGOUTClock *= 640U; + break; + case 0x20U: + MCGOUTClock *= 1280U; + break; + case 0x40U: + MCGOUTClock *= 1920U; + break; + case 0x60U: + MCGOUTClock *= 2560U; + break; + case 0x80U: + MCGOUTClock *= 732U; + break; + case 0xA0U: + MCGOUTClock *= 1464U; + break; + case 0xC0U: + MCGOUTClock *= 2197U; + break; + case 0xE0U: + MCGOUTClock *= 2929U; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + /* PLL is selected */ + Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.h new file mode 100644 index 00000000000..72bb5aa448b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.h @@ -0,0 +1,168 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** MK64FX512VDC12 +** MK64FX512VLL12 +** MK64FX512VLQ12 +** MK64FX512VMD12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151216 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** +** ################################################################### +*/ + +/*! + * @file MK64F12 + * @version 2.8 + * @date 2015-02-19 + * @brief Device specific configuration file for MK64F12 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MK64F12_H_ +#define _SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ +#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ + +/* RTC oscillator setting */ +/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ +#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ + +/* Low power mode enable */ +/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ + +#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MK64F12_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h new file mode 100644 index 00000000000..65d2b635b81 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, + ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, + ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, + ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, + ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, + ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, + ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, + ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, + ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, + ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, + ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, + ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, + ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, + ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, + ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c new file mode 100644 index 00000000000..92009d72410 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c @@ -0,0 +1,208 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTA17, ADC1_SE17, 0}, + {PTB0 , ADC0_SE8 , 0}, + {PTB1 , ADC0_SE9 , 0}, + {PTB2 , ADC0_SE12, 0}, + {PTB3 , ADC0_SE13, 0}, + {PTB6 , ADC1_SE12, 0}, + {PTB7 , ADC1_SE13, 0}, + {PTB10, ADC1_SE14, 0}, + {PTB11, ADC1_SE15, 0}, + {PTC0 , ADC0_SE14, 0}, + {PTC1 , ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10, ADC1_SE6b, 0}, + {PTC11, ADC1_SE7b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTE0, ADC1_SE4a, 0}, + {PTE1, ADC1_SE5a, 0}, + {PTE2, ADC1_SE6a, 0}, + {PTE3, ADC1_SE7a, 0}, + //{PTE24, ADC0_SE17, 0}, //I2C pull up + //{PTE25, ADC0_SE18, 0}, //I2C pull up + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE25, I2C_0, 5}, + {PTB1 , I2C_0, 2}, + {PTB3 , I2C_0, 2}, + {PTC11, I2C_1, 2}, + {PTA13, I2C_2, 5}, + {PTD3 , I2C_0, 7}, + {PTE0 , I2C_1, 6}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE24, I2C_0, 5}, + {PTB0 , I2C_0, 2}, + {PTB2 , I2C_0, 2}, + {PTC10, I2C_1, 2}, + {PTA12, I2C_2, 5}, + {PTA14, I2C_2, 5}, + {PTD2 , I2C_0, 7}, + {PTE1 , I2C_1, 6}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC17, UART_3, 3}, + {PTD7 , UART_0, 3}, + {PTD3 , UART_2, 3}, + {PTC4 , UART_1, 3}, + {PTC15, UART_4, 3}, + {PTB11, UART_3, 3}, + {PTA14, UART_0, 3}, + {PTE24, UART_4, 3}, + {PTE4 , UART_3, 3}, + {PTE0, UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTE1 , UART_1, 3}, + {PTE5 , UART_3, 3}, + {PTE25, UART_4, 3}, + {PTA15, UART_0, 3}, + {PTC16, UART_3, 3}, + {PTB10, UART_3, 3}, + {PTC3 , UART_1, 3}, + {PTC14, UART_4, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTD1 , SPI_0, 2}, + {PTE2 , SPI_1, 2}, + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTB21, SPI_2, 2}, + {PTC5 , SPI_0, 2}, + {PTD5 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2 , SPI_0, 2}, + {PTE1 , SPI_1, 2}, + {PTE3 , SPI_1, 7}, + {PTA16, SPI_0, 2}, + {PTB16, SPI_1, 2}, + {PTB22, SPI_2, 2}, + {PTC6 , SPI_0, 2}, + {PTD6 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3 , SPI_0, 2}, + {PTE1 , SPI_1, 7}, + {PTE3 , SPI_1, 2}, + {PTA17, SPI_0, 2}, + {PTB17, SPI_1, 2}, + {PTB23, SPI_2, 2}, + {PTC7 , SPI_0, 2}, + {PTD7 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0 , SPI_0, 2}, + {PTE4 , SPI_1, 2}, + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTB20, SPI_2, 2}, + {PTC4 , SPI_0, 2}, + {PTD4 , SPI_1, 7}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0 , PWM_6 , 3}, + {PTA1 , PWM_7 , 3}, + {PTA2 , PWM_8 , 3}, + {PTA3 , PWM_1 , 3}, + {PTA4 , PWM_2 , 3}, + {PTA5 , PWM_3 , 3}, + {PTA6 , PWM_4 , 3}, + {PTA7 , PWM_5 , 3}, + {PTA8 , PWM_9 , 3}, + {PTA9 , PWM_10, 3}, + {PTA10, PWM_17, 3}, + {PTA11, PWM_18, 3}, + {PTA12, PWM_9 , 3}, + {PTA13, PWM_10, 3}, + + {PTB0 , PWM_9 , 3}, + {PTB1 , PWM_10, 3}, + {PTB18, PWM_17, 3}, + {PTB19, PWM_18, 3}, + + {PTC1 , PWM_1 , 4}, + {PTC2 , PWM_2 , 4}, + {PTC3 , PWM_3 , 4}, + {PTC4 , PWM_4 , 4}, + {PTC5 , PWM_3 , 7}, + {PTC8 , PWM_29, 3}, + {PTC9 , PWM_30, 3}, + {PTC10, PWM_31, 3}, + {PTC11, PWM_32, 3}, + + {PTD0 , PWM_25, 4}, + {PTD1 , PWM_26, 4}, + {PTD2 , PWM_27, 4}, + {PTD3 , PWM_28, 4}, + {PTD4 , PWM_5 , 4}, + {PTD5 , PWM_6 , 4}, + {PTD6 , PWM_7 , 4}, + {PTD4 , PWM_5 , 4}, + {PTD7 , PWM_8 , 4}, + + {PTE5 , PWM_25, 6}, + {PTE6 , PWM_26, 6}, + + {NC , NC , 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h new file mode 100644 index 00000000000..92b0f35217f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h @@ -0,0 +1,258 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), + PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), + PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), + PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTA22 = (0 << GPIO_PORT_SHIFT | 22), + PTA23 = (0 << GPIO_PORT_SHIFT | 23), + PTA24 = (0 << GPIO_PORT_SHIFT | 24), + PTA25 = (0 << GPIO_PORT_SHIFT | 25), + PTA26 = (0 << GPIO_PORT_SHIFT | 26), + PTA27 = (0 << GPIO_PORT_SHIFT | 27), + PTA28 = (0 << GPIO_PORT_SHIFT | 28), + PTA29 = (0 << GPIO_PORT_SHIFT | 29), + PTA30 = (0 << GPIO_PORT_SHIFT | 30), + PTA31 = (0 << GPIO_PORT_SHIFT | 31), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), + PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), + PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), + PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), + PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), + PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB12 = (1 << GPIO_PORT_SHIFT | 12), + PTB13 = (1 << GPIO_PORT_SHIFT | 13), + PTB14 = (1 << GPIO_PORT_SHIFT | 14), + PTB15 = (1 << GPIO_PORT_SHIFT | 15), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTB24 = (1 << GPIO_PORT_SHIFT | 24), + PTB25 = (1 << GPIO_PORT_SHIFT | 25), + PTB26 = (1 << GPIO_PORT_SHIFT | 26), + PTB27 = (1 << GPIO_PORT_SHIFT | 27), + PTB28 = (1 << GPIO_PORT_SHIFT | 28), + PTB29 = (1 << GPIO_PORT_SHIFT | 29), + PTB30 = (1 << GPIO_PORT_SHIFT | 30), + PTB31 = (1 << GPIO_PORT_SHIFT | 31), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTC20 = (2 << GPIO_PORT_SHIFT | 20), + PTC21 = (2 << GPIO_PORT_SHIFT | 21), + PTC22 = (2 << GPIO_PORT_SHIFT | 22), + PTC23 = (2 << GPIO_PORT_SHIFT | 23), + PTC24 = (2 << GPIO_PORT_SHIFT | 24), + PTC25 = (2 << GPIO_PORT_SHIFT | 25), + PTC26 = (2 << GPIO_PORT_SHIFT | 26), + PTC27 = (2 << GPIO_PORT_SHIFT | 27), + PTC28 = (2 << GPIO_PORT_SHIFT | 28), + PTC29 = (2 << GPIO_PORT_SHIFT | 29), + PTC30 = (2 << GPIO_PORT_SHIFT | 30), + PTC31 = (2 << GPIO_PORT_SHIFT | 31), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), + PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), + PTD10 = (3 << GPIO_PORT_SHIFT | 10), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTD15 = (3 << GPIO_PORT_SHIFT | 15), + PTD16 = (3 << GPIO_PORT_SHIFT | 16), + PTD17 = (3 << GPIO_PORT_SHIFT | 17), + PTD18 = (3 << GPIO_PORT_SHIFT | 18), + PTD19 = (3 << GPIO_PORT_SHIFT | 19), + PTD20 = (3 << GPIO_PORT_SHIFT | 20), + PTD21 = (3 << GPIO_PORT_SHIFT | 21), + PTD22 = (3 << GPIO_PORT_SHIFT | 22), + PTD23 = (3 << GPIO_PORT_SHIFT | 23), + PTD24 = (3 << GPIO_PORT_SHIFT | 24), + PTD25 = (3 << GPIO_PORT_SHIFT | 25), + PTD26 = (3 << GPIO_PORT_SHIFT | 26), + PTD27 = (3 << GPIO_PORT_SHIFT | 27), + PTD28 = (3 << GPIO_PORT_SHIFT | 28), + PTD29 = (3 << GPIO_PORT_SHIFT | 29), + PTD30 = (3 << GPIO_PORT_SHIFT | 30), + PTD31 = (3 << GPIO_PORT_SHIFT | 31), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), + PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), + PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), + PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), + PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), + PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), + PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), + PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE14 = (4 << GPIO_PORT_SHIFT | 14), + PTE15 = (4 << GPIO_PORT_SHIFT | 15), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE26 = (4 << GPIO_PORT_SHIFT | 26), + PTE27 = (4 << GPIO_PORT_SHIFT | 27), + PTE28 = (4 << GPIO_PORT_SHIFT | 28), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + LED_RED = PTB22, + LED_GREEN = PTE26, + LED_BLUE = PTB21, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + //Push buttons + SW2 = PTC6, + SW3 = PTA4, + + // USB Pins + USBTX = PTB17, + USBRX = PTB16, + + // Arduino Headers + D0 = PTC16, + D1 = PTC17, + D2 = PTB9, + D3 = PTA1, + D4 = PTB23, + D5 = PTA2, + D6 = PTC2, + D7 = PTC3, + D8 = PTA0, + D9 = PTC4, + D10 = PTD0, + D11 = PTD2, + D12 = PTD3, + D13 = PTD1, + D14 = PTE25, + D15 = PTE24, + + I2C_SCL = D15, + I2C_SDA = D14, + + A0 = PTB2, + A1 = PTB3, + A2 = PTB10, + A3 = PTB11, + A4 = PTC11, + A5 = PTC10, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c new file mode 100644 index 00000000000..7e2d7e7c516 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c @@ -0,0 +1,234 @@ +/********************************************************************** + * + * Filename: crc.c + * + * Description: Slow and fast implementations of the CRC standards. + * + * Notes: The parameters for each supported CRC standard are + * defined in the header file crc.h. The implementations + * here should stand up to further additions to that list. + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#include "crc.h" + + +/* + * Derive parameters from the standard-specific parameters in crc.h. + */ +#define WIDTH (8 * sizeof(crc)) +#define TOPBIT (1 << (WIDTH - 1)) + +#if (REFLECT_DATA == TRUE) +#undef REFLECT_DATA +#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8)) +#else +#undef REFLECT_DATA +#define REFLECT_DATA(X) (X) +#endif + +#if (REFLECT_REMAINDER == TRUE) +#undef REFLECT_REMAINDER +#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH)) +#else +#undef REFLECT_REMAINDER +#define REFLECT_REMAINDER(X) (X) +#endif + + +/********************************************************************* + * + * Function: reflect() + * + * Description: Reorder the bits of a binary sequence, by reflecting + * them about the middle position. + * + * Notes: No checking is done that nBits <= 32. + * + * Returns: The reflection of the original data. + * + *********************************************************************/ +static unsigned long +reflect(unsigned long data, unsigned char nBits) +{ + unsigned long reflection = 0x00000000; + unsigned char bit; + + /* + * Reflect the data about the center bit. + */ + for (bit = 0; bit < nBits; ++bit) + { + /* + * If the LSB bit is set, set the reflection of it. + */ + if (data & 0x01) + { + reflection |= (1 << ((nBits - 1) - bit)); + } + + data = (data >> 1); + } + + return (reflection); + +} /* reflect() */ + + +/********************************************************************* + * + * Function: crcSlow() + * + * Description: Compute the CRC of a given message. + * + * Notes: + * + * Returns: The CRC of the message. + * + *********************************************************************/ +crc +crcSlow(unsigned char const message[], int nBytes) +{ + crc remainder = INITIAL_REMAINDER; + int byte; + unsigned char bit; + + + /* + * Perform modulo-2 division, a byte at a time. + */ + for (byte = 0; byte < nBytes; ++byte) + { + /* + * Bring the next byte into the remainder. + */ + remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8)); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) + { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) + { + remainder = (remainder << 1) ^ POLYNOMIAL; + } + else + { + remainder = (remainder << 1); + } + } + } + + /* + * The final remainder is the CRC result. + */ + return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); + +} /* crcSlow() */ + + +crc crcTable[256]; + + +/********************************************************************* + * + * Function: crcInit() + * + * Description: Populate the partial CRC lookup table. + * + * Notes: This function must be rerun any time the CRC standard + * is changed. If desired, it can be run "offline" and + * the table results stored in an embedded system's ROM. + * + * Returns: None defined. + * + *********************************************************************/ +void +crcInit(void) +{ + crc remainder; + int dividend; + unsigned char bit; + + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) + { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (WIDTH - 8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) + { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) + { + remainder = (remainder << 1) ^ POLYNOMIAL; + } + else + { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + crcTable[dividend] = remainder; + } + +} /* crcInit() */ + + +/********************************************************************* + * + * Function: crcFast() + * + * Description: Compute the CRC of a given message. + * + * Notes: crcInit() must be called first. + * + * Returns: The CRC of the message. + * + *********************************************************************/ +crc +crcFast(unsigned char const message[], int nBytes) +{ + crc remainder = INITIAL_REMAINDER; + unsigned char data; + int byte; + + + /* + * Divide the message by the polynomial, a byte at a time. + */ + for (byte = 0; byte < nBytes; ++byte) + { + data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8)); + remainder = crcTable[data] ^ (remainder << 8); + } + + /* + * The final remainder is the CRC. + */ + return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); + +} /* crcFast() */ + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h new file mode 100644 index 00000000000..fae66ae4bcc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h @@ -0,0 +1,77 @@ +/********************************************************************** + * + * Filename: crc.h + * + * Description: A header file describing the various CRC standards. + * + * Notes: + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#ifndef _crc_h +#define _crc_h + + +#define FALSE 0 +#define TRUE !FALSE + +/* + * Select the CRC standard from the list that follows. + */ +#define CRC16 + + +#if defined(CRC_CCITT) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-CCITT" +#define POLYNOMIAL 0x1021 +#define INITIAL_REMAINDER 0xFFFF +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA FALSE +#define REFLECT_REMAINDER FALSE +#define CHECK_VALUE 0x29B1 + +#elif defined(CRC16) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-16" +#define POLYNOMIAL 0x8005 +#define INITIAL_REMAINDER 0x0000 +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xBB3D + +#elif defined(CRC32) + +typedef unsigned long crc; + +#define CRC_NAME "CRC-32" +#define POLYNOMIAL 0x04C11DB7 +#define INITIAL_REMAINDER 0xFFFFFFFF +#define FINAL_XOR_VALUE 0xFFFFFFFF +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xCBF43926 + +#else + +#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." + +#endif + + +void crcInit(void); +crc crcSlow(unsigned char const message[], int nBytes); +crc crcFast(unsigned char const message[], int nBytes); + + +#endif /* _crc_h */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h new file mode 100644 index 00000000000..8f3ef7e1252 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c new file mode 100755 index 00000000000..9ceaef0a1ae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 120MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 7U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 120000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC, false); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h new file mode 100755 index 00000000000..050c3ab79b0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 50000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c new file mode 100644 index 00000000000..f324d8310ee --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" + +#define CRC16 +#include "crc.h" +#include "fsl_clock_config.h" + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} + +// Provide ethernet devices with a semi-unique MAC address from the UUID +void mbed_mac_address(char *mac) +{ + + unsigned int UUID_LOC_BASE = 0x40048054; // First adddress of the 4-word UUID + char uuid[16]; // So we can take a local copy of the UUID + uint32_t MAC[3]; // 3 16 bits words for the MAC + + // copy the UUID to the variable MAC[] + memcpy(uuid,(const void*)UUID_LOC_BASE,sizeof(uuid)); + + // generate three CRC16's using different slices of the UUID + MAC[0] = crcSlow(uuid, 8); // most significant half-word + MAC[1] = crcSlow(uuid, 12); + MAC[2] = crcSlow(uuid, 16); // least significant half word + + // The network stack expects an array of 6 bytes + // so we copy, and shift and copy from the half-word array to the byte array + mac[0] = MAC[0] >> 8; + mac[1] = MAC[0]; + mac[2] = MAC[1] >> 8; + mac[3] = MAC[1]; + mac[4] = MAC[2] >> 8; + mac[5] = MAC[2]; + + // We want to force bits [1:0] of the most significant byte [0] + // to be "10" + // http://en.wikipedia.org/wiki/MAC_address + + mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered" + mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast + +} + + + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h new file mode 100644 index 00000000000..077ca4a5561 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_2 = 2, + UART_3 = 3, + UART_5 = 5, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, +} I2CName; + + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + // could be 4 or could be 3... not sure what register + // this is for... too much abstraction + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + + + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4, + ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5, + ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6, + ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7, + ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, + ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, + ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, + ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, + ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, + ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, + ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, + ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, + ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, +} ADCName; + + + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c new file mode 100644 index 00000000000..dd0721fb5fe --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c @@ -0,0 +1,112 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE25, I2C_0, 5}, + {PTB1 , I2C_0, 2}, + {PTB3 , I2C_0, 2}, + {PTC11, I2C_1, 2}, + {PTD3 , I2C_0, 7}, + {PTE0 , I2C_1, 6}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE24, I2C_0, 5}, + {PTB0 , I2C_0, 2}, + {PTB2 , I2C_0, 2}, + {PTC10, I2C_1, 2}, + {PTD2 , I2C_0, 7}, + {PTE1 , I2C_1, 6}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC17, UART_3, 3}, + {PTD7 , UART_0, 3}, + {PTD3 , UART_2, 3}, + {PTB11, UART_3, 3}, + {PTA14, UART_0, 3}, + {PTE4 , UART_3, 3}, + {PTE8 , UART_5, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTE5 , UART_3, 3}, + {PTA15, UART_0, 3}, + {PTC16, UART_3, 3}, + {PTB10, UART_3, 3}, + {PTD2 , UART_2, 3}, + {PTC6 , UART_0, 3}, + {PTE9 , UART_5, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTD1 , SPI_0, 2}, + {PTE2 , SPI_1, 2}, + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTC5 , SPI_0, 2}, + {PTD5 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2 , SPI_0, 2}, + {PTE1 , SPI_1, 2}, + {PTE3 , SPI_1, 7}, + {PTA16, SPI_0, 2}, + {PTB16, SPI_1, 2}, + {PTC6 , SPI_0, 2}, + {PTD6 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3 , SPI_0, 2}, + {PTE1 , SPI_1, 7}, + {PTE3 , SPI_1, 2}, + {PTA17, SPI_0, 2}, + {PTB17, SPI_1, 2}, + {PTC7 , SPI_0, 2}, + {PTD7 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0 , SPI_0, 2}, + {PTE4 , SPI_1, 2}, + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTC4 , SPI_0, 2}, + {PTD4 , SPI_1, 7}, + {NC , NC , 0} +}; + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h new file mode 100644 index 00000000000..1e3fc8dcd15 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h @@ -0,0 +1,268 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), + PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), + PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), + PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTA22 = (0 << GPIO_PORT_SHIFT | 22), + PTA23 = (0 << GPIO_PORT_SHIFT | 23), + PTA24 = (0 << GPIO_PORT_SHIFT | 24), + PTA25 = (0 << GPIO_PORT_SHIFT | 25), + PTA26 = (0 << GPIO_PORT_SHIFT | 26), + PTA27 = (0 << GPIO_PORT_SHIFT | 27), + PTA28 = (0 << GPIO_PORT_SHIFT | 28), + PTA29 = (0 << GPIO_PORT_SHIFT | 29), + PTA30 = (0 << GPIO_PORT_SHIFT | 30), + PTA31 = (0 << GPIO_PORT_SHIFT | 31), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), + PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), + PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), + PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), + PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), + PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB12 = (1 << GPIO_PORT_SHIFT | 12), + PTB13 = (1 << GPIO_PORT_SHIFT | 13), + PTB14 = (1 << GPIO_PORT_SHIFT | 14), + PTB15 = (1 << GPIO_PORT_SHIFT | 15), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTB24 = (1 << GPIO_PORT_SHIFT | 24), + PTB25 = (1 << GPIO_PORT_SHIFT | 25), + PTB26 = (1 << GPIO_PORT_SHIFT | 26), + PTB27 = (1 << GPIO_PORT_SHIFT | 27), + PTB28 = (1 << GPIO_PORT_SHIFT | 28), + PTB29 = (1 << GPIO_PORT_SHIFT | 29), + PTB30 = (1 << GPIO_PORT_SHIFT | 30), + PTB31 = (1 << GPIO_PORT_SHIFT | 31), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTC20 = (2 << GPIO_PORT_SHIFT | 20), + PTC21 = (2 << GPIO_PORT_SHIFT | 21), + PTC22 = (2 << GPIO_PORT_SHIFT | 22), + PTC23 = (2 << GPIO_PORT_SHIFT | 23), + PTC24 = (2 << GPIO_PORT_SHIFT | 24), + PTC25 = (2 << GPIO_PORT_SHIFT | 25), + PTC26 = (2 << GPIO_PORT_SHIFT | 26), + PTC27 = (2 << GPIO_PORT_SHIFT | 27), + PTC28 = (2 << GPIO_PORT_SHIFT | 28), + PTC29 = (2 << GPIO_PORT_SHIFT | 29), + PTC30 = (2 << GPIO_PORT_SHIFT | 30), + PTC31 = (2 << GPIO_PORT_SHIFT | 31), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), + PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), + PTD10 = (3 << GPIO_PORT_SHIFT | 10), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTD15 = (3 << GPIO_PORT_SHIFT | 15), + PTD16 = (3 << GPIO_PORT_SHIFT | 16), + PTD17 = (3 << GPIO_PORT_SHIFT | 17), + PTD18 = (3 << GPIO_PORT_SHIFT | 18), + PTD19 = (3 << GPIO_PORT_SHIFT | 19), + PTD20 = (3 << GPIO_PORT_SHIFT | 20), + PTD21 = (3 << GPIO_PORT_SHIFT | 21), + PTD22 = (3 << GPIO_PORT_SHIFT | 22), + PTD23 = (3 << GPIO_PORT_SHIFT | 23), + PTD24 = (3 << GPIO_PORT_SHIFT | 24), + PTD25 = (3 << GPIO_PORT_SHIFT | 25), + PTD26 = (3 << GPIO_PORT_SHIFT | 26), + PTD27 = (3 << GPIO_PORT_SHIFT | 27), + PTD28 = (3 << GPIO_PORT_SHIFT | 28), + PTD29 = (3 << GPIO_PORT_SHIFT | 29), + PTD30 = (3 << GPIO_PORT_SHIFT | 30), + PTD31 = (3 << GPIO_PORT_SHIFT | 31), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), + PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), + PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), + PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), + PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), + PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), + PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), + PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE14 = (4 << GPIO_PORT_SHIFT | 14), + PTE15 = (4 << GPIO_PORT_SHIFT | 15), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE26 = (4 << GPIO_PORT_SHIFT | 26), + PTE27 = (4 << GPIO_PORT_SHIFT | 27), + PTE28 = (4 << GPIO_PORT_SHIFT | 28), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + // led color naming + LED_GREEN = PTC0, + + // mbed original LED naming + LED1 = PTD15, + LED2 = PTD14, + LED3 = PTD13, + LED4 = PTD11, + LED5 = PTD12, + STATUS = LED_GREEN, + + // USB Pins + USBTX = PTB17, + USBRX = PTB16, + + // SPI Pins + SPI0_SOUT = PTC6, + SPI0_SIN = PTC7, + SPI0_SCK = PTC5, + + SPI1_SOUT = PTE3, + SPI1_SIN = PTE1, + SPI1_SCK = PTE2, + + // SPI Chip Select Pins + SPI0_NCS0 = PTC4, + SPI0_NCS1 = PTC3, + SPI0_NCS2 = PTC2, + SPI0_NCS3 = PTC1, + + SPI1_NCS0 = PTE4, + SPI1_NCS1 = PTE0, + SPI1_NCS2 = PTE5, + SPI1_NCS3 = PTE6, + + // GPIO's + AP1_GPIO1 = PTB7, + AP1_GPIO2 = PTB6, + AP1_GPIO3 = PTB5, + AP1_GPIO4 = PTB4, + + AP2_GPIO1 = PTA27, + AP2_GPIO2 = PTA26, + AP2_GPIO3 = PTA25, + AP2_GPIO4 = PTA24, + + // Cellular Radio Serial Pins + RADIO_SERIAL_TX = PTE8, + RADIO_SERIAL_RX = PTE9, + RADIO_SERIAL_RTS = PTE11, + RADIO_SERIAL_CTS = PTE10, + RADIO_SERIAL_DTR = PTE26, + RADIO_SERIAL_DSR = PTE25, + RADIO_SERIAL_RI = PTE24, + RADIO_SERIAL_CD = PTE12, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h new file mode 100644 index 00000000000..109924b210c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c new file mode 100755 index 00000000000..9ceaef0a1ae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 120MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 7U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 120000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC, false); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h new file mode 100755 index 00000000000..050c3ab79b0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 50000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c new file mode 100644 index 00000000000..3d28610d0a4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "fsl_clock_config.h" +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c new file mode 100755 index 00000000000..8f1aa77b2ea --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc16.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC16 module. + * + * @param base ADC16 peripheral base address + */ +static uint32_t ADC16_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC16 bases for each instance. */ +static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; + +/*! @brief Pointers to ADC16 clocks for each instance. */ +const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC16_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++) + { + if (s_adc16Bases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_ADC16_COUNT); + + return instance; +} + +void ADC16_Init(ADC_Type *base, const adc16_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Enable the clock. */ + CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); + + /* ADCx_CFG1. */ + tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG1_ADLSMP_MASK; + } + tmp32 |= ADC_CFG1_ADIV(config->clockDivider); + if (config->enableLowPower) + { + tmp32 |= ADC_CFG1_ADLPC_MASK; + } + base->CFG1 = tmp32; + + /* ADCx_CFG2. */ + tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG2_ADHSC_MASK; + } + if (config->enableAsynchronousClock) + { + tmp32 |= ADC_CFG2_ADACKEN_MASK; + } + base->CFG2 = tmp32; + + /* ADCx_SC2. */ + tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); + tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); + base->SC2 = tmp32; + + /* ADCx_SC3. */ + if (config->enableContinuousConversion) + { + base->SC3 |= ADC_SC3_ADCO_MASK; + } + else + { + base->SC3 &= ~ADC_SC3_ADCO_MASK; + } +} + +void ADC16_Deinit(ADC_Type *base) +{ + /* Disable the clock. */ + CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +} + +void ADC16_GetDefaultConfig(adc16_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + config->clockSource = kADC16_ClockSourceAsynchronousClock; + config->enableAsynchronousClock = true; + config->clockDivider = kADC16_ClockDivider8; + config->resolution = kADC16_ResolutionSE12Bit; + config->longSampleMode = kADC16_LongSampleDisabled; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableContinuousConversion = false; +} + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +status_t ADC16_DoAutoCalibration(ADC_Type *base) +{ + bool bHWTrigger = false; + uint32_t tmp32; + status_t status = kStatus_Success; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) + { + bHWTrigger = true; + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } + + /* Clear the CALF and launch the calibration. */ + base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; + while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) + { + /* Check the CALF when the calibration is active. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + break; + } + } + + /* Restore the hardware trigger setting if it was enabled before. */ + if (bHWTrigger) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + /* Check the CALF at the end of calibration. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + } + if (kStatus_Success != status) /* Check if the calibration process is succeed. */ + { + return status; + } + + /* Calculate the calibration values. */ + tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->PG = tmp32; + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->MG = tmp32; +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + + return kStatus_Success; +} +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) +{ + if (kADC16_ChannelMuxA == mode) + { + base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; + } + else /* kADC16_ChannelMuxB. */ + { + base->CFG2 |= ADC_CFG2_MUXSEL_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) +{ + uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); + + if (!config) /* Pass "NULL" to disable the feature. */ + { + base->SC2 = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_SC2_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC16_HardwareCompareMode0: + break; + case kADC16_HardwareCompareMode1: + tmp32 |= ADC_SC2_ACFGT_MASK; + break; + case kADC16_HardwareCompareMode2: + tmp32 |= ADC_SC2_ACREN_MASK; + break; + case kADC16_HardwareCompareMode3: + tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; + break; + default: + break; + } + base->SC2 = tmp32; + + /* Load the compare values. */ + base->CV1 = ADC_CV1_CV(config->value1); + base->CV2 = ADC_CV2_CV(config->value2); +} + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) +{ + uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); + + if (kADC16_HardwareAverageDisabled != mode) + { + tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); + } + base->SC3 = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) +{ + uint32_t tmp32; + + if (!config) /* Passing "NULL" is to disable the feature. */ + { + base->PGA = 0U; + return; + } + + /* Enable the PGA and set the gain value. */ + tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); + + /* Configure the misc features for PGA. */ + if (config->enableRunInNormalMode) + { + tmp32 |= ADC_PGA_PGALPb_MASK; + } +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + if (config->disablePgaChopping) + { + tmp32 |= ADC_PGA_PGACHPb_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + if (config->enableRunInOffsetMeasurement) + { + tmp32 |= ADC_PGA_PGAOFSM_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ + base->PGA = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +uint32_t ADC16_GetStatusFlags(ADC_Type *base) +{ + uint32_t ret = 0; + + if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) + { + ret |= kADC16_ActiveFlag; + } +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) + { + ret |= kADC16_CalibrationFailedFlag; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + return ret; +} + +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (mask & kADC16_CalibrationFailedFlag)) + { + base->SC3 |= ADC_SC3_CALF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +} + +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) +{ + assert(channelGroup < ADC_SC1_COUNT); + assert(NULL != config); + + uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + /* Enable the differential conversion. */ + if (config->enableDifferentialConversion) + { + sc1 |= ADC_SC1_DIFF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + /* Enable the interrupt when the conversion is done. */ + if (config->enableInterruptOnConversionCompleted) + { + sc1 |= ADC_SC1_AIEN_MASK; + } + base->SC1[channelGroup] = sc1; +} + +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_SC1_COUNT); + + uint32_t ret = 0U; + + if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) + { + ret |= kADC16_ChannelConversionDoneFlag; + } + return ret; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h new file mode 100755 index 00000000000..c6b5bc0d1ae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC16_H_ +#define _FSL_ADC16_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc16 + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ADC16 driver version 2.0.0. */ +#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Channel status flags. + */ +enum _adc16_channel_status_flags +{ + kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ +}; + +/*! + * @brief Converter status flags. + */ +enum _adc16_status_flags +{ + kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +}; + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Channel multiplexer mode for each channel. + * + * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b + * are the different channels but share the same channel number. + */ +typedef enum _adc_channel_mux_mode +{ + kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ + kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ +} adc16_channel_mux_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc16_clock_divider +{ + kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc16_clock_divider_t; + +/*! + *@brief Converter's resolution. + */ +typedef enum _adc16_resolution +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ + kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ + kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ + + /* This group of enumeration is for public user. */ + kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ + kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ + kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ + kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ + kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + +#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) + /* 16-bit is supported by default. */ + kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ + kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ +} adc16_resolution_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc16_clock_source +{ + kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ + kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ + kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ + kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ + + /* Chip defined clock source */ + kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ +} adc16_clock_source_t; + +/*! + * @brief Long sample mode. + */ +typedef enum _adc16_long_sample_mode +{ + kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ + kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ + kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ + kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ + kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ +} adc16_long_sample_mode_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc16_reference_voltage_source +{ + kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ + kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ +} adc16_reference_voltage_source_t; + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Hardware average mode. + */ +typedef enum _adc16_hardware_average_mode +{ + kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ +} adc16_hardware_average_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +/*! + * @brief Hardware compare mode. + */ +typedef enum _adc16_hardware_compare_mode +{ + kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ + kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ + kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; + else, value1 > x > value2. */ + kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; + else x >= value1 || x <= value2. */ +} adc16_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief PGA's Gain mode. + */ +typedef enum _adc16_pga_gain +{ + kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ + kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ + kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ + kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ + kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ + kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ + kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ +} adc16_pga_gain_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief ADC16 converter configuration . + */ +typedef struct _adc16_config +{ + adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ + bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ + adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ + adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ + adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable low power. */ + bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ +} adc16_config_t; + +/*! + * @brief ADC16 Hardware compare configuration. + */ +typedef struct _adc16_hardware_compare_config +{ + adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc16_hardware_compare_mode_t". */ + int16_t value1; /*!< Setting value1 for hardware compare mode. */ + int16_t value2; /*!< Setting value2 for hardware compare mode. */ +} adc16_hardware_compare_config_t; + +/*! + * @brief ADC16 channel conversion configuration. + */ +typedef struct _adc16_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + bool enableDifferentialConversion; /*!< Using Differential sample mode. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +} adc16_channel_config_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief ADC16 programmable gain amplifier configuration. + */ +typedef struct _adc16_pga_config +{ + adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ + bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + bool disablePgaChopping; /*!< Disable the PGA chopping function. + The PGA employs chopping to remove/reduce offset and 1/f noise and offers + an offset measurement configuration that aids the offset calibration. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. + When this feature is enabled, the PGA disconnects itself from the external + inputs and auto-configures into offset measurement mode. With this field + set, run the ADC in the recommended settings and enable the maximum hardware + averaging to get the PGA offset number. The output is the + (PGA offset * (64+1)) for the given PGA setting. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ +} adc16_pga_config_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to configuration structure. See "adc16_config_t". + */ +void ADC16_Init(ADC_Type *base, const adc16_config_t *config); + +/*! + * @brief De-initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + */ +void ADC16_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for converter's configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + * config->clockSource = kADC16_ClockSourceAsynchronousClock; + * config->enableAsynchronousClock = true; + * config->clockDivider = kADC16_ClockDivider8; + * config->resolution = kADC16_ResolutionSE12Bit; + * config->longSampleMode = kADC16_LongSampleDisabled; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableContinuousConversion = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void ADC16_GetDefaultConfig(adc16_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation. + * Execute the calibration before using the converter. Note that the hardware trigger should be used + * during calibration. + * + * @param base ADC16 peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration is failed. + */ +status_t ADC16_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION +/*! + * @brief Sets the offset value for the conversion result. + * + * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result + * is subtracted by it. Note, the hardware calibration fills the offset value automatically. + * + * @param base ADC16 peripheral base address. + * @param value Setting offset value. + */ +static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFS = (uint32_t)(value); +} +#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ + +/* @} */ + +/*! + * @name Advanced Feature + * @{ + */ + +#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA +/*! + * @brief Enables generating the DMA trigger when conversion is completed. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of DMA feature. "true" means to enable, "false" means not. + */ +static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_DMAEN_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_DMAEN_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_DMA */ + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not. + */ +static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } +} + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Sets the channel mux mode. + * + * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an + * indicated channel. + * + * @param base ADC16 peripheral base address. + * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". + */ +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result + * in + * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference + * manual document for more detailed information. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature. + */ +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Sets the hardware average mode. + * + * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple + * conversion results are accumulated and averaged internally. This aids reading results. + * + * @param base ADC16 peripheral base address. + * @param mode Setting hardware average mode. See "adc16_hardware_average_mode_t". + */ +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief Configures the PGA for converter's front end. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature. + */ +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief Gets the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". + */ +uint32_t ADC16_GetStatusFlags(ADC_Type *base); + +/*! + * @brief Clears the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * @param mask Mask value for the cleared flags. See "_adc16_status_flags". + */ +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Conversion Channel + * @{ + */ + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one + * group of status and control register, one for each conversion. The channel group parameter indicates which group of + * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware + * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion. + * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to "adc16_channel_config_t" structure for conversion channel. + */ +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". + */ +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_ADC16_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c new file mode 100755 index 00000000000..7e5f05aff36 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c @@ -0,0 +1,1760 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Macro definition remap workaround. */ +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#endif +#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#endif +#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK))) +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#endif +#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK))) +#define MCG_C6_CME0_MASK MCG_C6_CME_MASK +#endif + +/* PLL fixed multiplier when there is not PRDIV and VDIV. */ +#define PLL_FIXED_MULT (375U) +/* Max frequency of the reference clock used for internal clock trim. */ +#define TRIM_REF_CLK_MIN (8000000U) +/* Min frequency of the reference clock used for internal clock trim. */ +#define TRIM_REF_CLK_MAX (16000000U) +/* Max trim value of fast internal reference clock. */ +#define TRIM_FIRC_MAX (5000000U) +/* Min trim value of fast internal reference clock. */ +#define TRIM_FIRC_MIN (3000000U) +/* Max trim value of fast internal reference clock. */ +#define TRIM_SIRC_MAX (39063U) +/* Min trim value of fast internal reference clock. */ +#define TRIM_SIRC_MIN (31250U) + +#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT) +#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) +#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT) +#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) +#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) +#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) +#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) +#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) +#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) +#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) +#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) +#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) +#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) +#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) +#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) +#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) +#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) +#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) +#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) + +#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) + +#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) +#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) +#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT) +#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) +#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) +#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) + +/* MCG_S_CLKST definition. */ +enum _mcg_clkout_stat +{ + kMCG_ClkOutStatFll, /* FLL. */ + kMCG_ClkOutStatInt, /* Internal clock. */ + kMCG_ClkOutStatExt, /* External clock. */ + kMCG_ClkOutStatPll /* PLL. */ +}; + +/* MCG_S_PLLST definition. */ +enum _mcg_pllst +{ + kMCG_PllstFll, /* FLL is used. */ + kMCG_PllstPll /* PLL is used. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Slow internal reference clock frequency. */ +static uint32_t s_slowIrcFreq = 32768U; +/* Fast internal reference clock frequency. */ +static uint32_t s_fastIrcFreq = 4000000U; + +/* External XTAL0 (OSC0) clock frequency. */ +uint32_t g_xtal0Freq; + +/* External XTAL32K clock frequency. */ +uint32_t g_xtal32Freq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the MCG external reference clock frequency. + * + * Get the current MCG external reference clock frequency in Hz. It is + * the frequency select by MCG_C7[OSCSEL]. This is an internal function. + * + * @return MCG external reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetMcgExtClkFreq(void); + +/*! + * @brief Get the MCG FLL external reference clock frequency. + * + * Get the current MCG FLL external reference clock frequency in Hz. It is + * the frequency after by MCG_C1[FRDIV]. This is an internal function. + * + * @return MCG FLL external reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetFllExtRefClkFreq(void); + +/*! + * @brief Get the MCG FLL reference clock frequency. + * + * Get the current MCG FLL reference clock frequency in Hz. It is + * the frequency select by MCG_C1[IREFS]. This is an internal function. + * + * @return MCG FLL reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetFllRefClkFreq(void); + +/*! + * @brief Get the frequency of clock selected by MCG_C2[IRCS]. + * + * This clock's two output: + * 1. MCGOUTCLK when MCG_S[CLKST]=0. + * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1. + * + * @return The frequency in Hz. + */ +static uint32_t CLOCK_GetInternalRefClkSelectFreq(void); + +/*! + * @brief Get the MCG PLL/PLL0 reference clock frequency. + * + * Get the current MCG PLL/PLL0 reference clock frequency in Hz. + * This is an internal function. + * + * @return MCG PLL/PLL0 reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetPll0RefFreq(void); + +/*! + * @brief Calculate the RANGE value base on crystal frequency. + * + * To setup external crystal oscillator, must set the register bits RANGE + * base on the crystal frequency. This function returns the RANGE base on the + * input frequency. This is an internal function. + * + * @param freq Crystal frequency in Hz. + * @return The RANGE value. + */ +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); + +/*! + * @brief Delay function to wait FLL stable. + * + * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least + * 1ms. Every time changes FLL setting, should wait this time for FLL stable. + */ +static void CLOCK_FllStableDelay(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetMcgExtClkFreq(void) +{ + uint32_t freq; + + switch (MCG_C7_OSCSEL_VAL) + { + case 0U: + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + freq = g_xtal0Freq; + break; + case 1U: + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 2U: + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +static uint32_t CLOCK_GetFllExtRefClkFreq(void) +{ + /* FllExtRef = McgExtRef / FllExtRefDiv */ + uint8_t frdiv; + uint8_t range; + uint8_t oscsel; + + uint32_t freq = CLOCK_GetMcgExtClkFreq(); + + if (!freq) + { + return freq; + } + + frdiv = MCG_C1_FRDIV_VAL; + freq >>= frdiv; + + range = MCG_C2_RANGE_VAL; + oscsel = MCG_C7_OSCSEL_VAL; + + /* + When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. + 1. MCG_C7[OSCSEL] selects IRC48M. + 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. + */ + if (((0U != range) && (kMCG_OscselOsc == oscsel)) || (kMCG_OscselIrc == oscsel)) + { + switch (frdiv) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + freq >>= 5u; + break; + case 6: + /* 64*20=1280 */ + freq /= 20u; + break; + case 7: + /* 128*12=1536 */ + freq /= 12u; + break; + default: + freq = 0u; + break; + } + } + + return freq; +} + +static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) +{ + if (kMCG_IrcSlow == MCG_S_IRCST_VAL) + { + /* Slow internal reference clock selected*/ + return s_slowIrcFreq; + } + else + { + /* Fast internal reference clock selected*/ + return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; + } +} + +static uint32_t CLOCK_GetFllRefClkFreq(void) +{ + /* If use external reference clock. */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + return CLOCK_GetFllExtRefClkFreq(); + } + /* If use internal reference clock. */ + else + { + return s_slowIrcFreq; + } +} + +static uint32_t CLOCK_GetPll0RefFreq(void) +{ + /* MCG external reference clock. */ + return CLOCK_GetMcgExtClkFreq(); +} + +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) +{ + uint8_t range; + + if (freq <= 39063U) + { + range = 0U; + } + else if (freq <= 8000000U) + { + range = 1U; + } + else + { + range = 2U; + } + + return range; +} + +static void CLOCK_FllStableDelay(void) +{ + /* + Should wait at least 1ms. Because in these modes, the core clock is 100MHz + at most, so this function could obtain the 1ms delay. + */ + volatile uint32_t i = 30000U; + while (i--) + { + __NOP(); + } +} + +uint32_t CLOCK_GetOsc0ErClkFreq(void) +{ + if (OSC0->CR & OSC_CR_ERCLKEN_MASK) + { + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + return g_xtal0Freq; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetEr32kClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT1_OSC32KSEL_VAL) + { + case 0U: /* OSC 32k clock */ + freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; + break; + case 2U: /* RTC 32k clock */ + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 3U: /* LPO clock */ + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; + } + return freq; +} + +uint32_t CLOCK_GetPllFllSelClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT2_PLLFLLSEL_VAL) + { + case 0U: /* FLL. */ + freq = CLOCK_GetFllFreq(); + break; + case 1U: /* PLL. */ + freq = CLOCK_GetPll0Freq(); + break; + case 3U: /* MCG IRC48M. */ + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +uint32_t CLOCK_GetPlatClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFlashClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); +} + +uint32_t CLOCK_GetFlexBusClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); +} + +uint32_t CLOCK_GetBusClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); +} + +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + case kCLOCK_PlatClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); + break; + case kCLOCK_FlexBusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); + break; + case kCLOCK_FlashClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); + break; + case kCLOCK_PllFllSelClk: + freq = CLOCK_GetPllFllSelClkFreq(); + break; + case kCLOCK_Er32kClk: + freq = CLOCK_GetEr32kClkFreq(); + break; + case kCLOCK_Osc0ErClk: + freq = CLOCK_GetOsc0ErClkFreq(); + break; + case kCLOCK_McgFixedFreqClk: + freq = CLOCK_GetFixedFreqClkFreq(); + break; + case kCLOCK_McgInternalRefClk: + freq = CLOCK_GetInternalRefClkFreq(); + break; + case kCLOCK_McgFllClk: + freq = CLOCK_GetFllFreq(); + break; + case kCLOCK_McgPll0Clk: + freq = CLOCK_GetPll0Freq(); + break; + case kCLOCK_McgIrc48MClk: + freq = MCG_INTERNAL_IRC_48M; + break; + case kCLOCK_LpoClk: + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_SetSimConfig(sim_clock_config_t const *config) +{ + SIM->CLKDIV1 = config->clkdiv1; + CLOCK_SetPllFllSelClock(config->pllFllSel); + CLOCK_SetEr32kClock(config->er32kSrc); +} + +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcExt == src) + { + SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; + } + else + { + switch (freq) + { + case 120000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); + break; + case 96000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); + break; + case 72000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); + break; + case 48000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); + break; + default: + ret = false; + break; + } + + SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); + } + + CLOCK_EnableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcIrc48M == src) + { + USB0->CLK_RECOVER_IRC_EN = 0x03U; + USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; + } + return ret; +} + +uint32_t CLOCK_GetOutClkFreq(void) +{ + uint32_t mcgoutclk; + uint32_t clkst = MCG_S_CLKST_VAL; + + switch (clkst) + { + case kMCG_ClkOutStatPll: + mcgoutclk = CLOCK_GetPll0Freq(); + break; + case kMCG_ClkOutStatFll: + mcgoutclk = CLOCK_GetFllFreq(); + break; + case kMCG_ClkOutStatInt: + mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); + break; + case kMCG_ClkOutStatExt: + mcgoutclk = CLOCK_GetMcgExtClkFreq(); + break; + default: + mcgoutclk = 0U; + break; + } + return mcgoutclk; +} + +uint32_t CLOCK_GetFllFreq(void) +{ + static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; + + uint8_t drs, dmx32; + uint32_t freq; + + /* If FLL is not enabled currently, then return 0U. */ + if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) + { + return 0U; + } + + /* Get FLL reference clock frequency. */ + freq = CLOCK_GetFllRefClkFreq(); + if (!freq) + { + return freq; + } + + drs = MCG_C4_DRST_DRS_VAL; + dmx32 = MCG_C4_DMX32_VAL; + + return freq * fllFactorTable[drs][dmx32]; +} + +uint32_t CLOCK_GetInternalRefClkFreq(void) +{ + /* If MCGIRCLK is gated. */ + if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) + { + return 0U; + } + + return CLOCK_GetInternalRefClkSelectFreq(); +} + +uint32_t CLOCK_GetFixedFreqClkFreq(void) +{ + uint32_t freq = CLOCK_GetFllRefClkFreq(); + + /* MCGFFCLK must be no more than MCGOUTCLK/8. */ + if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U))) + { + return freq; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetPll0Freq(void) +{ + uint32_t mcgpll0clk; + + /* If PLL0 is not enabled, return 0. */ + if (!(MCG->S & MCG_S_LOCK0_MASK)) + { + return 0U; + } + + mcgpll0clk = CLOCK_GetPll0RefFreq(); + + mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); + mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); + + return mcgpll0clk; +} + +status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) +{ + bool needDelay; + uint32_t i; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ + if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) + { + return kStatus_MCG_SourceUsed; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + if (MCG_C7_OSCSEL_VAL != oscsel) + { + /* If change OSCSEL, need to delay, ERR009878. */ + needDelay = true; + } + else + { + needDelay = false; + } + + MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); + if (kMCG_OscselOsc == oscsel) + { + if (MCG->C2 & MCG_C2_EREFS_MASK) + { + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } + } + + if (needDelay) + { + /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ + i = 1500U; + while (i--) + { + __NOP(); + } + } + + return kStatus_Success; +} + +status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) +{ + uint32_t mcgOutClkState = MCG_S_CLKST_VAL; + mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL; + uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + /* If MCGIRCLK is used as system clock source. */ + if (kMCG_ClkOutStatInt == mcgOutClkState) + { + /* If need to change MCGIRCLK source or driver, return error. */ + if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) + { + return kStatus_MCG_SourceUsed; + } + } +#endif + + /* If need to update the FCRDIV. */ + if (fcrdiv != curFcrdiv) + { + /* If fast IRC is in use currently, change to slow IRC. */ + if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK))) + { + MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); + while (MCG_S_IRCST_VAL != kMCG_IrcSlow) + { + } + } + /* Update FCRDIV. */ + MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); + } + + /* Set internal reference clock selection. */ + MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); + MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; + + /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ + if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) + { + while (MCG_S_IRCST_VAL != ircs) + { + } + } + + return kStatus_Success; +} + +uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) +{ + uint8_t ret_prdiv; /* PRDIV to return. */ + uint8_t ret_vdiv; /* VDIV to return. */ + uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */ + uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */ + uint8_t prdiv_cur; /* PRDIV value for iteration. */ + uint8_t vdiv_cur; /* VDIV value for iteration. */ + uint32_t ret_freq = 0U; /* PLL output fequency to return. */ + uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ + uint32_t ref_div; /* Reference frequency after PRDIV. */ + + /* + Steps: + 1. Get allowed prdiv with such rules: + 1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN. + 2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX. + 2. For each allowed prdiv, there are two candidate vdiv values: + 1). (desireFreq / (refFreq / prdiv)). + 2). (desireFreq / (refFreq / prdiv)) + 1. + If could get the precise desired frequency, return current prdiv and + vdiv directly. Otherwise choose the one which is closer to desired + frequency. + */ + + /* Reference frequency is out of range. */ + if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) || + (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) + { + return 0U; + } + + /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */ + prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN; + prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX; + + /* PRDIV traversal. */ + for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) + { + /* Reference frequency after PRDIV. */ + ref_div = refFreq / prdiv_cur; + + vdiv_cur = desireFreq / ref_div; + + if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) + { + /* No VDIV is available with this PRDIV. */ + continue; + } + + ret_freq = vdiv_cur * ref_div; + + if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) + { + if (ret_freq == desireFreq) /* If desire frequency is got. */ + { + *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; + return ret_freq; + } + /* New PRDIV/VDIV is closer. */ + if (diff > desireFreq - ret_freq) + { + diff = desireFreq - ret_freq; + ret_prdiv = prdiv_cur; + ret_vdiv = vdiv_cur; + } + } + vdiv_cur++; + if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) + { + ret_freq += ref_div; + /* New PRDIV/VDIV is closer. */ + if (diff > ret_freq - desireFreq) + { + diff = ret_freq - desireFreq; + ret_prdiv = prdiv_cur; + ret_vdiv = vdiv_cur; + } + } + } + + if (0xFFFFFFFFU != diff) + { + /* PRDIV/VDIV found. */ + *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; + ret_freq = (refFreq / ret_prdiv) * ret_vdiv; + return ret_freq; + } + else + { + /* No proper PRDIV/VDIV found. */ + return 0U; + } +} + +void CLOCK_EnablePll0(mcg_pll_config_t const *config) +{ + assert(config); + + uint8_t mcg_c5 = 0U; + + mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); + MCG->C5 = mcg_c5; /* Disable the PLL first. */ + + MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); + + /* Set enable mode. */ + MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); + + /* Wait for PLL lock. */ + while (!(MCG->S & MCG_S_LOCK0_MASK)) + { + } +} + +void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) +{ + /* Clear the previous flag, MCG_SC[LOCS0]. */ + MCG->SC &= ~MCG_SC_ATMF_MASK; + + if (kMCG_MonitorNone == mode) + { + MCG->C6 &= ~MCG_C6_CME0_MASK; + } + else + { + if (kMCG_MonitorInt == mode) + { + MCG->C2 &= ~MCG_C2_LOCRE0_MASK; + } + else + { + MCG->C2 |= MCG_C2_LOCRE0_MASK; + } + MCG->C6 |= MCG_C6_CME0_MASK; + } +} + +void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) +{ + uint8_t mcg_c8 = MCG->C8; + + mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); + + if (kMCG_MonitorNone != mode) + { + if (kMCG_MonitorReset == mode) + { + mcg_c8 |= MCG_C8_LOCRE1_MASK; + } + mcg_c8 |= MCG_C8_CME1_MASK; + } + MCG->C8 = mcg_c8; +} + +void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) +{ + uint8_t mcg_c8; + + /* Clear previous flag. */ + MCG->S = MCG_S_LOLS0_MASK; + + if (kMCG_MonitorNone == mode) + { + MCG->C6 &= ~MCG_C6_LOLIE0_MASK; + } + else + { + mcg_c8 = MCG->C8; + + mcg_c8 &= ~MCG_C8_LOCS1_MASK; + + if (kMCG_MonitorInt == mode) + { + mcg_c8 &= ~MCG_C8_LOLRE_MASK; + } + else + { + mcg_c8 |= MCG_C8_LOLRE_MASK; + } + MCG->C8 = mcg_c8; + MCG->C6 |= MCG_C6_LOLIE0_MASK; + } +} + +uint32_t CLOCK_GetStatusFlags(void) +{ + uint32_t ret = 0U; + uint8_t mcg_s = MCG->S; + + if (MCG->SC & MCG_SC_LOCS0_MASK) + { + ret |= kMCG_Osc0LostFlag; + } + if (mcg_s & MCG_S_OSCINIT0_MASK) + { + ret |= kMCG_Osc0InitFlag; + } + if (MCG->C8 & MCG_C8_LOCS1_MASK) + { + ret |= kMCG_RtcOscLostFlag; + } + if (mcg_s & MCG_S_LOLS0_MASK) + { + ret |= kMCG_Pll0LostFlag; + } + if (mcg_s & MCG_S_LOCK0_MASK) + { + ret |= kMCG_Pll0LockFlag; + } + return ret; +} + +void CLOCK_ClearStatusFlags(uint32_t mask) +{ + uint8_t reg; + + if (mask & kMCG_Osc0LostFlag) + { + MCG->SC &= ~MCG_SC_ATMF_MASK; + } + if (mask & kMCG_RtcOscLostFlag) + { + reg = MCG->C8; + MCG->C8 = reg; + } + if (mask & kMCG_Pll0LostFlag) + { + MCG->S = MCG_S_LOLS0_MASK; + } +} + +void CLOCK_InitOsc0(osc_config_t const *config) +{ + uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); + + OSC_SetCapLoad(OSC0, config->capLoad); + OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); + + MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); + + if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) + { + /* Wait for stable. */ + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } +} + +void CLOCK_DeinitOsc0(void) +{ + OSC0->CR = 0U; + MCG->C2 &= ~OSC_MODE_MASK; +} + +status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) +{ + uint32_t multi; /* extFreq / desireFreq */ + uint32_t actv; /* Auto trim value. */ + uint8_t mcg_sc; + + static const uint32_t trimRange[2][2] = { + /* Min Max */ + {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */ + {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ + }; + + if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) + { + return kStatus_MCG_AtmBusClockInvalid; + } + + /* Check desired frequency range. */ + if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) + { + return kStatus_MCG_AtmDesiredFreqInvalid; + } + + /* + Make sure internal reference clock is not used to generate bus clock. + Here only need to check (MCG_S_IREFST == 1). + */ + if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) + { + return kStatus_MCG_AtmIrcUsed; + } + + multi = extFreq / desireFreq; + actv = multi * 21U; + + if (kMCG_AtmSel4m == atms) + { + actv *= 128U; + } + + /* Now begin to start trim. */ + MCG->ATCVL = (uint8_t)actv; + MCG->ATCVH = (uint8_t)(actv >> 8U); + + mcg_sc = MCG->SC; + mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); + mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); + MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); + + /* Wait for finished. */ + while (MCG->SC & MCG_SC_ATME_MASK) + { + } + + /* Error occurs? */ + if (MCG->SC & MCG_SC_ATMF_MASK) + { + /* Clear the failed flag. */ + MCG->SC = mcg_sc; + return kStatus_MCG_AtmHardwareFail; + } + + *actualFreq = extFreq / multi; + + if (kMCG_AtmSel4m == atms) + { + s_fastIrcFreq = *actualFreq; + } + else + { + s_slowIrcFreq = *actualFreq; + } + + return kStatus_Success; +} + +mcg_mode_t CLOCK_GetMode(void) +{ + mcg_mode_t mode = kMCG_ModeError; + uint32_t clkst = MCG_S_CLKST_VAL; + uint32_t irefst = MCG_S_IREFST_VAL; + uint32_t lp = MCG_C2_LP_VAL; + uint32_t pllst = MCG_S_PLLST_VAL; + + /*------------------------------------------------------------------ + Mode and Registers + ____________________________________________________________________ + + Mode | CLKST | IREFST | PLLST | LP + ____________________________________________________________________ + + FEI | 00(FLL) | 1(INT) | 0(FLL) | X + ____________________________________________________________________ + + FEE | 00(FLL) | 0(EXT) | 0(FLL) | X + ____________________________________________________________________ + + FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) + ____________________________________________________________________ + + BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) + ____________________________________________________________________ + + PEE | 11(PLL) | 0(EXT) | 1(PLL) | X + ____________________________________________________________________ + + PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) + ____________________________________________________________________ + + PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) + ____________________________________________________________________ + + PEI | 11(PLL) | 1(INT) | 1(PLL) | X + ____________________________________________________________________ + + ----------------------------------------------------------------------*/ + + switch (clkst) + { + case kMCG_ClkOutStatFll: + if (kMCG_FllSrcExternal == irefst) + { + mode = kMCG_ModeFEE; + } + else + { + mode = kMCG_ModeFEI; + } + break; + case kMCG_ClkOutStatInt: + if (lp) + { + mode = kMCG_ModeBLPI; + } + else + { + { + mode = kMCG_ModeFBI; + } + } + break; + case kMCG_ClkOutStatExt: + if (lp) + { + mode = kMCG_ModeBLPE; + } + else + { + if (kMCG_PllstPll == pllst) + { + mode = kMCG_ModePBE; + } + else + { + mode = kMCG_ModeFBE; + } + } + break; + case kMCG_ClkOutStatPll: + { + mode = kMCG_ModePEE; + } + break; + default: + break; + } + + return mode; +} + +status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */ + + /* Wait and check status. */ + while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ + MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs)); + + /* Check MCG_S[CLKST] */ + while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) + { + } + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* Wait and check status. */ + while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* Set DRS and DMX32. */ + mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = mcg_c4; + + /* Wait for DRST_DRS update. */ + while (MCG->C4 != mcg_c4) + { + } + + /* Check MCG_S[CLKST] */ + while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) + { + } + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || + (kMCG_ModeBLPI == mode))) + + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + mcg_c4 = MCG->C4; + + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + + /* Wait and check status. */ + while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) + { + } + + MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs)); + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || + (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Change to FLL mode. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + /* Set LP bit to enable the FLL */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* Wait for Reference clock Status bit to clear */ + while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* Set DRST_DRS and DMX32. */ + mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + + /* Wait for clock status bits to show clock source is ext ref clk */ + while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) + { + } + + /* Wait for fll stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetBlpiMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + return kStatus_MCG_ModeUnreachable; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + /* Set LP. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_SetBlpeMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Set LP bit to enter BLPE mode. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +{ + /* + This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, + but with this workflow, the source mode could be all modes except PEI/PBI. + */ + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + /* Change to use external clock first. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + + /* Wait for CLKST clock status bits to show clock source is ext ref clk */ + while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) + { + } + + /* Disable PLL first, then configure PLL. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + /* Configure the PLL. */ + { + CLOCK_EnablePll0(config); + } + + /* Change to PLL mode. */ + MCG->C6 |= MCG_C6_PLLS_MASK; + while (!(MCG->S & MCG_S_PLLST_MASK)) + { + } + + return kStatus_Success; +} + +status_t CLOCK_SetPeeMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (kMCG_ModePBE != mode) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Change to use PLL/FLL output clock first. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + + /* Wait for clock status bits to update */ + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) + { + } + + return kStatus_Success; +} + +status_t CLOCK_ExternalModeToFbeModeQuick(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG->S & MCG_S_IREFST_MASK) + { + return kStatus_MCG_ModeInvalid; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + /* Disable low power */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + } + + /* Disable PLL. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + return kStatus_Success; +} + +status_t CLOCK_InternalModeToFbiModeQuick(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (!(MCG->S & MCG_S_IREFST_MASK)) + { + return kStatus_MCG_ModeInvalid; + } +#endif + + /* Disable low power */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + } + + return kStatus_Success; +} + +status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + return CLOCK_SetFeiMode(drs, fllStableDelay); +} + +status_t CLOCK_BootToFeeMode( + mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + CLOCK_SetExternalRefClkConfig(oscsel); + + return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); +} + +status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) +{ + /* If reset mode is FEI mode, set MCGIRCLK and always success. */ + CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); + + /* If reset mode is not BLPI, first enter FBI mode. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + } + + /* Enter BLPI mode. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) +{ + CLOCK_SetExternalRefClkConfig(oscsel); + + /* Set to FBE mode. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ + while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) + { + } + + /* In FBE now, start to enter BLPE. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +{ + assert(config); + + CLOCK_SetExternalRefClkConfig(oscsel); + + CLOCK_SetPbeMode(pllcs, config); + + /* Change to use PLL output clock. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) + { + } + + return kStatus_Success; +} + +/* + The transaction matrix. It defines the path for mode switch, the row is for + current mode and the column is target mode. + For example, switch from FEI to PEE: + 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE. + 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE. + 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE. + Thus the MCG mode has changed from FEI to PEE. + */ +static const mcg_mode_t mcgModeMatrix[8][8] = { + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FEI */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FBI */ + {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, + kMCG_ModeFBI}, /* BLPI */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FEE */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePBE}, /* FBE */ + {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePBE}, /* BLPE */ + {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePEE}, /* PBE */ + {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, + kMCG_ModePBE} /* PEE */ + /* FEI FBI BLPI FEE FBE BLPE PBE PEE */ +}; + +status_t CLOCK_SetMcgConfig(const mcg_config_t *config) +{ + mcg_mode_t next_mode; + status_t status = kStatus_Success; + + mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0; + + /* If need to change external clock, MCG_C7[OSCSEL]. */ + if (MCG_C7_OSCSEL_VAL != config->oscsel) + { + /* If external clock is in use, change to FEI first. */ + if (!(MCG->S & MCG_S_IRCST_MASK)) + { + CLOCK_ExternalModeToFbeModeQuick(); + CLOCK_SetFeiMode(config->drs, (void (*)(void))0); + } + + CLOCK_SetExternalRefClkConfig(config->oscsel); + } + + /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ + if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt) + { + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + { + CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay); + } + } + + /* Configure MCGIRCLK. */ + CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv); + + next_mode = CLOCK_GetMode(); + + do + { + next_mode = mcgModeMatrix[next_mode][config->mcgMode]; + + switch (next_mode) + { + case kMCG_ModeFEI: + status = CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFEE: + status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFBI: + status = CLOCK_SetFbiMode(config->drs, (void (*)(void))0); + break; + case kMCG_ModeFBE: + status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0); + break; + case kMCG_ModeBLPI: + status = CLOCK_SetBlpiMode(); + break; + case kMCG_ModeBLPE: + status = CLOCK_SetBlpeMode(); + break; + case kMCG_ModePBE: + /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ + if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) + { + { + status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); + } + } + else + { + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + } + } + break; + case kMCG_ModePEE: + status = CLOCK_SetPeeMode(); + break; + default: + break; + } + if (kStatus_Success != status) + { + return status; + } + } while (next_mode != config->mcgMode); + + if (config->pll0Config.enableMode & kMCG_PllEnableIndependent) + { + CLOCK_EnablePll0(&config->pll0Config); + } + else + { + MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; + } + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h new file mode 100755 index 00000000000..1e75c3b7711 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h @@ -0,0 +1,1510 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! @addtogroup clock */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock driver version. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief External XTAL0 (OSC0) clock frequency. + * + * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example, + * if XTAL0 is 8MHz, + * @code + * CLOCK_InitOsc0(...); // Setup the OSC0 + * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver. + * @endcode + * + * This is important for the multicore platforms, only one core needs to setup + * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq + * to get valid clock frequency. + */ +extern uint32_t g_xtal0Freq; + +/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. + * + * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtal32Freq to set the value in to clock driver. + * + * This is important for the multicore platforms, only one core needs to setup + * the clock, all other cores need to call CLOCK_SetXtal32Freq + * to get valid clock frequency. + */ +extern uint32_t g_xtal32Freq; + +/*! @brief IRC48M clock frequency in Hz. */ +#define MCG_INTERNAL_IRC_48M 48000000U + +#if (defined(OSC) && !(defined(OSC0))) +#define OSC0 OSC +#endif + +/*! @brief Clock ip name array for DMAMUX. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dmamux0 \ + } + +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet0 \ + } + +/*! @brief Clock ip name array for PORT. */ +#define PORT_CLOCKS \ + { \ + kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_Sai0 \ + } + +/*! @brief Clock ip name array for FLEXBUS. */ +#define FLEXBUS_CLOCKS \ + { \ + kCLOCK_Flexbus0 \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit0 \ + } + +/*! @brief Clock ip name array for DSPI. */ +#define DSPI_CLOCKS \ + { \ + kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \ + } + +/*! @brief Clock ip name array for LPTMR. */ +#define LPTMR_CLOCKS \ + { \ + kCLOCK_Lptmr0 \ + } + +/*! @brief Clock ip name array for SDHC. */ +#define SDHC_CLOCKS \ + { \ + kCLOCK_Sdhc0 \ + } + +/*! @brief Clock ip name array for FTM. */ +#define FTM_CLOCKS \ + { \ + kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \ + } + +/*! @brief Clock ip name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_Flexcan0 \ + } + +/*! @brief Clock ip name array for DAC. */ +#define DAC_CLOCKS \ + { \ + kCLOCK_Dac0, kCLOCK_Dac1 \ + } + +/*! @brief Clock ip name array for ADC16. */ +#define ADC16_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } + +/*! @brief Clock ip name array for MMCAU. */ +#define MMCAU_CLOCKS \ + { \ + kCLOCK_Mmcau0 \ + } + +/*! @brief Clock ip name array for MPU. */ +#define MPU_CLOCKS \ + { \ + kCLOCK_Mpu0 \ + } + +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref0 \ + } + +/*! @brief Clock ip name array for CMT. */ +#define CMT_CLOCKS \ + { \ + kCLOCK_Cmt0 \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \ + } + +/*! @brief Clock ip name array for RNGA. */ +#define RNGA_CLOCKS \ + { \ + kCLOCK_Rnga0 \ + } + +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2 \ + } + +/*! @brief Clock ip name array for PDB. */ +#define PDB_CLOCKS \ + { \ + kCLOCK_Pdb0 \ + } + +/*! @brief Clock ip name array for FTF. */ +#define FTF_CLOCKS \ + { \ + kCLOCK_Ftf0 \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \ + } + +/*! + * @brief LPO clock frequency. + */ +#define LPO_CLK_FREQ 1000U + +/*! @brief Peripherals clock source definition. */ +#define SYS_CLK kCLOCK_CoreSysClk +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK +#define I2C1_CLK_SRC BUS_CLK +#define I2C2_CLK_SRC BUS_CLK +#define DSPI0_CLK_SRC BUS_CLK +#define DSPI1_CLK_SRC BUS_CLK +#define DSPI2_CLK_SRC BUS_CLK +#define UART0_CLK_SRC SYS_CLK +#define UART1_CLK_SRC SYS_CLK +#define UART2_CLK_SRC BUS_CLK +#define UART3_CLK_SRC BUS_CLK +#define UART4_CLK_SRC BUS_CLK +#define UART5_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + + /* ----------------------------- System layer clock -------------------------------*/ + kCLOCK_CoreSysClk, /*!< Core/system clock */ + kCLOCK_PlatClk, /*!< Platform clock */ + kCLOCK_BusClk, /*!< Bus clock */ + kCLOCK_FlexBusClk, /*!< FlexBus clock */ + kCLOCK_FlashClk, /*!< Flash clock */ + kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ + kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ + + /* ---------------------------------- OSC clock -----------------------------------*/ + kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ + kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ + kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ + kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ + + /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ + kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ + kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ + kCLOCK_McgFllClk, /*!< MCGFLLCLK */ + kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ + kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ + kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ + kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ + kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ + + /* --------------------------------- Other clock ----------------------------------*/ + kCLOCK_LpoClk, /*!< LPO clock */ + +} clock_name_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ + kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */ + kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ +} clock_usb_src_t; + +/*------------------------------------------------------------------------------ + + clock_gate_t definition: + + 31 16 0 + ----------------------------------------------------------------- + | SIM_SCGC register offset | control bit offset in SCGC | + ----------------------------------------------------------------- + + For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the + SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as + + kCLOCK_GateSdhc0 = (0x1030 << 16) | 17; + +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 16U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U), + kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U), + kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U), + + kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U), + kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U), + kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U), + + kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U), + kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U), + kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U), + kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U), + + kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), + kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), + kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), + kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), + kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U), + kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U), + kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), + kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U), + kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), + kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), + + kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), + kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), + kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), + kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), + kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), + kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), + + kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), + kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), + kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U), + kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U), + kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), + kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), + kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), + kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), + kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U), + kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), + kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), + kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), + kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), + kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), + kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), + kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), + + kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U), + kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), + kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U), +} clock_ip_name_t; + +/*!@brief SIM configuration structure for clock setting. */ +typedef struct _sim_clock_config +{ + uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ + uint8_t er32kSrc; /*!< ERCLK32K source selection. */ + uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ +} sim_clock_config_t; + +/*! @brief OSC work mode. */ +typedef enum _osc_mode +{ + kOSC_ModeExt = 0U, /*!< Use external clock. */ +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) + kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ +#else + kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ +#endif + kOSC_ModeOscHighGain = 0U +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) + | + MCG_C2_EREFS_MASK +#else + | + MCG_C2_EREFS0_MASK +#endif +#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) + | + MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ +#else + | + MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ +#endif +} osc_mode_t; + +/*! @brief Oscillator capacitor load setting.*/ +enum _osc_cap_load +{ + kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ + kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ + kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ + kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ +}; + +/*! @brief OSCERCLK enable mode. */ +enum _oscer_enable_mode +{ + kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ + kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ +}; + +/*! @brief OSC configuration for OSCERCLK. */ +typedef struct _oscer_config +{ + uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ + +} oscer_config_t; + +/*! + * @brief OSC Initialization Configuration Structure + * + * Defines the configuration data structure to initialize the OSC. + * When porting to a new board, please set the following members + * according to board setting: + * 1. freq: The external frequency. + * 2. workMode: The OSC module mode. + */ +typedef struct _osc_config +{ + uint32_t freq; /*!< External clock frequency. */ + uint8_t capLoad; /*!< Capacitor load setting. */ + osc_mode_t workMode; /*!< OSC work mode setting. */ + oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ +} osc_config_t; + +/*! @brief MCG FLL reference clock source select. */ +typedef enum _mcg_fll_src +{ + kMCG_FllSrcExternal, /*!< External reference clock is selected */ + kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ +} mcg_fll_src_t; + +/*! @brief MCG internal reference clock select */ +typedef enum _mcg_irc_mode +{ + kMCG_IrcSlow, /*!< Slow internal reference clock selected */ + kMCG_IrcFast /*!< Fast internal reference clock selected */ +} mcg_irc_mode_t; + +/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ +typedef enum _mcg_dmx32 +{ + kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ + kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ +} mcg_dmx32_t; + +/*! @brief MCG DCO range select */ +typedef enum _mcg_drs +{ + kMCG_DrsLow, /*!< Low frequency range */ + kMCG_DrsMid, /*!< Mid frequency range */ + kMCG_DrsMidHigh, /*!< Mid-High frequency range */ + kMCG_DrsHigh /*!< High frequency range */ +} mcg_drs_t; + +/*! @brief MCG PLL reference clock select */ +typedef enum _mcg_pll_ref_src +{ + kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ + kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ +} mcg_pll_ref_src_t; + +/*! @brief MCGOUT clock source. */ +typedef enum _mcg_clkout_src +{ + kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ + kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ + kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ +} mcg_clkout_src_t; + +/*! @brief MCG Automatic Trim Machine Select */ +typedef enum _mcg_atm_select +{ + kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ + kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ +} mcg_atm_select_t; + +/*! @brief MCG OSC Clock Select */ +typedef enum _mcg_oscsel +{ + kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ + kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ + kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */ +} mcg_oscsel_t; + +/*! @brief MCG PLLCS select */ +typedef enum _mcg_pll_clk_select +{ + kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ + kMCG_PllClkSelPll1 /* PLL1 output clock is selected */ +} mcg_pll_clk_select_t; + +/*! @brief MCG clock monitor mode. */ +typedef enum _mcg_monitor_mode +{ + kMCG_MonitorNone, /*!< Clock monitor is disabled. */ + kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ + kMCG_MonitorReset /*!< System reset when clock lost. */ +} mcg_monitor_mode_t; + +/*! @brief MCG status. */ +enum _mcg_status +{ + kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ + kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific + function. */ + kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ + kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ + kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ + kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ + kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Could not change clock source because + it is used currently. */ +}; + +/*! @brief MCG status flags. */ +enum _mcg_status_flags_t +{ + kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ + kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ + kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ + kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ + kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ +}; + +/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ +enum _mcg_irclk_enable_mode +{ + kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ + kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ +}; + +/*! @brief MCG PLL clock enable mode definition. */ +enum _mcg_pll_enable_mode +{ + kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of + MCG clock mode. Generally, PLL + is disabled in FLL modes + (FEI/FBI/FEE/FBE), set PLL clock + enable independent will enable + PLL in the FLL modes. */ + kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ +}; + +/*! @brief MCG mode definitions */ +typedef enum _mcg_mode +{ + kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ + kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ + kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ + kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ + kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ + kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ + kMCG_ModePBE, /*!< PBE - PLL Bypassed External */ + kMCG_ModePEE, /*!< PEE - PLL Engaged External */ + kMCG_ModeError /*!< Unknown mode */ +} mcg_mode_t; + +/*! @brief MCG PLL configuration. */ +typedef struct _mcg_pll_config +{ + uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ + uint8_t prdiv; /*!< Reference divider PRDIV. */ + uint8_t vdiv; /*!< VCO divider VDIV. */ +} mcg_pll_config_t; + +/*! @brief MCG configure structure for mode change. + * + * When porting to a new board, please set the following members + * according to board setting: + * 1. frdiv: If FLL uses the external reference clock, please set this + * value to make sure external reference clock divided by frdiv is + * in the range 31.25kHz to 39.0625kHz. + * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after + * PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to + * FSL_FEATURE_MCG_PLL_REF_MAX. + */ +typedef struct _mcg_config +{ + mcg_mode_t mcgMode; /*!< MCG mode. */ + + /* ----------------------- MCGIRCCLK settings ------------------------ */ + uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ + mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ + uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ + + /* ------------------------ MCG FLL settings ------------------------- */ + uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ + mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ + mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ + mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ + + /* ------------------------ MCG PLL settings ------------------------- */ + mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */ + +} mcg_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set the XTAL0 frequency based on board setting. + * + * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal0Freq(uint32_t freq) +{ + g_xtal0Freq = freq; +} + +/*! + * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting. + * + * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal32Freq(uint32_t freq) +{ + g_xtal32Freq = freq; +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Set ERCLK32K source. + * + * @param src The value to set ERCLK32K clock source. + */ +static inline void CLOCK_SetEr32kClock(uint32_t src) +{ + SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); +} + +/*! + * @brief Set SDHC0 clock source. + * + * @param src The value to set SDHC0 clock source. + */ +static inline void CLOCK_SetSdhc0Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src)); +} + +/*! + * @brief Set enet timestamp clock source. + * + * @param src The value to set enet timestamp clock source. + */ +static inline void CLOCK_SetEnetTime0Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src)); +} + +/*! + * @brief Set RMII clock source. + * + * @param src The value to set RMII clock source. + */ +static inline void CLOCK_SetRmii0Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src)); +} + +/*! + * @brief Set debug trace clock source. + * + * @param src The value to set debug trace clock source. + */ +static inline void CLOCK_SetTraceClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); +} + +/*! + * @brief Set PLLFLLSEL clock source. + * + * @param src The value to set PLLFLLSEL clock source. + */ +static inline void CLOCK_SetPllFllSelClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); +} + +/*! + * @brief Set CLKOUT source. + * + * @param src The value to set CLKOUT source. + */ +static inline void CLOCK_SetClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); +} + +/*! + * @brief Set RTC_CLKOUT source. + * + * @param src The value to set RTC_CLKOUT source. + */ +static inline void CLOCK_SetRtcClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); +} + +/*! @brief Enable USB FS clock. + * + * @param src USB FS clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB FS clock. + */ +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB FS clock. + * + * Disable USB FS clock. + */ +static inline void CLOCK_DisableUsbfs0Clock(void) +{ + CLOCK_DisableClock(kCLOCK_Usbfs0); +} + +/*! + * @brief System clock divider + * + * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4]. + * + * @param outdiv1 Clock 1 output divider value. + * + * @param outdiv2 Clock 2 output divider value. + * + * @param outdiv3 Clock 3 output divider value. + * + * @param outdiv4 Clock 4 output divider value. + */ +static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) +{ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | + SIM_CLKDIV1_OUTDIV4(outdiv4); +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * The MCG must be properly configured before using this function. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in Hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Get the core clock or system clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! + * @brief Get the platform clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetPlatClkFreq(void); + +/*! + * @brief Get the bus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetBusClkFreq(void); + +/*! + * @brief Get the flexbus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlexBusClkFreq(void); + +/*! + * @brief Get the flash clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlashClkFreq(void); + +/*! + * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetPllFllSelClkFreq(void); + +/*! + * @brief Get the external reference 32K clock frequency (ERCLK32K). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetEr32kClkFreq(void); + +/*! + * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetOsc0ErClkFreq(void); + +/*! + * @brief Set the clock configure in SIM module. + * + * This function sets system layer clock settings in SIM module. + * + * @param config Pointer to the configure structure. + */ +void CLOCK_SetSimConfig(sim_clock_config_t const *config); + +/*! + * @brief Set the system clock dividers in SIM to safe value. + * + * The system level clocks (core clock, bus clock, flexbus clock and flash clock) + * must be in allowed ranges. During MCG clock mode switch, the MCG output clock + * changes then the system level clocks may be out of range. This function could + * be used before MCG mode change, to make sure system level clocks are in allowed + * range. + * + * @param config Pointer to the configure structure. + */ +static inline void CLOCK_SetSimSafeDivs(void) +{ + SIM->CLKDIV1 = 0x01240000U; +} + +/*! @name MCG frequency functions. */ +/*@{*/ + +/*! + * @brief Get the MCG output clock(MCGOUTCLK) frequency. + * + * This function gets the MCG output clock frequency (Hz) based on current MCG + * register value. + * + * @return The frequency of MCGOUTCLK. + */ +uint32_t CLOCK_GetOutClkFreq(void); + +/*! + * @brief Get the MCG FLL clock(MCGFLLCLK) frequency. + * + * This function gets the MCG FLL clock frequency (Hz) based on current MCG + * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other + * modes, FLL is disabled in low power state. + * + * @return The frequency of MCGFLLCLK. + */ +uint32_t CLOCK_GetFllFreq(void); + +/*! + * @brief Get the MCG internal reference clock(MCGIRCLK) frequency. + * + * This function gets the MCG internal reference clock frequency (Hz) based + * on current MCG register value. + * + * @return The frequency of MCGIRCLK. + */ +uint32_t CLOCK_GetInternalRefClkFreq(void); + +/*! + * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency. + * + * This function gets the MCG fixed frequency clock frequency (Hz) based + * on current MCG register value. + * + * @return The frequency of MCGFFCLK. + */ +uint32_t CLOCK_GetFixedFreqClkFreq(void); + +/*! + * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency. + * + * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG + * register value. + * + * @return The frequency of MCGPLL0CLK. + */ +uint32_t CLOCK_GetPll0Freq(void); + +/*@}*/ + +/*! @name MCG clock configuration. */ +/*@{*/ + +/*! + * @brief Enable or disable MCG low power. + * + * Enable MCG low power will disable the PLL and FLL in bypass modes. That is, + * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and + * PBI mode, enable low power will set MCG to BLPI mode. + * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting. + * + * @param enable True to enable MCG low power, false to disable MCG low power. + */ +static inline void CLOCK_SetLowPowerEnable(bool enable) +{ + if (enable) + { + MCG->C2 |= MCG_C2_LP_MASK; + } + else + { + MCG->C2 &= ~MCG_C2_LP_MASK; + } +} + +/*! + * @brief Configure the Internal Reference clock (MCGIRCLK) + * + * This function setups the \c MCGIRCLK base on parameters. It selects the IRC + * source, if fast IRC is used, this function also sets the fast IRC divider. + * This function also sets whether enable \c MCGIRCLK in stop mode. + * Calling this function in FBI/PBI/BLPI modes may change the system clock, so + * it is not allowed to use this in these modes. + * + * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. + * @param ircs MCGIRCLK clock source, choose fast or slow. + * @param fcrdiv Fast IRC divider setting (\c FCRDIV). + * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK. + * @retval kStatus_Success MCGIRCLK configuration finished successfully. + */ +status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); + +/*! + * @brief Select the MCG external reference clock. + * + * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL] + * and wait for the clock source stable. Should not change external reference + * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes. + * + * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. + * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change. + * @retval kStatus_Success External reference clock set successfully. + */ +status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); + +/*! + * @brief Enables the PLL0 in FLL mode. + * + * This function setups the PLL0 in FLL mode, make sure the PLL reference + * clock is enabled before calling this function. This function reconfigures + * the PLL0, make sure the PLL0 is not used as a clock source while calling + * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL + * divider values. + * + * @param config Pointer to the configuration structure. + */ +void CLOCK_EnablePll0(mcg_pll_config_t const *config); + +/*! + * @brief Disables the PLL0 in FLL mode. + * + * This function disables the PLL0 in FLL mode, it should be used together with + * @ref CLOCK_EnablePll0. + */ +static inline void CLOCK_DisablePll0(void) +{ + MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); +} + +/*! + * @brief Calculates the PLL divider setting for desired output frequency. + * + * This function calculates the proper reference clock divider (\c PRDIV) and + * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the + * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are + * returned from parameters. If desired frequency is not valid, this function + * returns 0. + * + * @param refFreq PLL reference clock frequency. + * @param desireFreq Desired PLL output frequency. + * @param prdiv PRDIV value to generate desired PLL frequency. + * @param vdiv VDIV value to generate desired PLL frequency. + * @return Closest frequency PLL could generate. + */ +uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); + +/*@}*/ + +/*! @name MCG clock lock monitor functions. */ +/*@{*/ + +/*! + * @brief Set the OSC0 clock monitor mode. + * + * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details. + * + * @param mode The monitor mode to set. + */ +void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Set the RTC OSC clock monitor mode. + * + * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details. + * + * @param mode The monitor mode to set. + */ +void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Set the PLL0 clock monitor mode. + * + * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details. + * + * @param mode The monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Get the MCG status flags. + * + * This function gets the MCG clock status flags, all the status flags are + * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To + * check specific flags, compare the return value with the flags. + * + * Example: + * @code + // To check the clock lost lock status of OSC0 and PLL0. + uint32_t mcgFlags; + + mcgFlags = CLOCK_GetStatusFlags(); + + if (mcgFlags & kMCG_Osc0LostFlag) + { + // OSC0 clock lock lost. Do something. + } + if (mcgFlags & kMCG_Pll0LostFlag) + { + // PLL0 clock lock lost. Do something. + } + @endcode + * + * @return Logical OR value of the @ref _mcg_status_flags_t. + */ +uint32_t CLOCK_GetStatusFlags(void); + +/*! + * @brief Clears the MCG status flags. + * + * This function clears the MCG clock lock lost status. The parameter is logical + * OR value of the flags to clear, see @ref _mcg_status_flags_t. + * + * Example: + * @code + // To clear the clock lost lock status flags of OSC0 and PLL0. + + CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); + @endcode + * + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration @ref _mcg_status_flags_t. + */ +void CLOCK_ClearStatusFlags(uint32_t mask); + +/*@}*/ + +/*! + * @name OSC configuration + * @{ + */ + +/*! + * @brief Configures the OSC external reference clock (OSCERCLK). + * + * This function configures the OSC external reference clock (OSCERCLK). + * For example, to enable the OSCERCLK in normal mode and stop mode, and also set + * the output divider to 1, as follows: + * + @code + oscer_config_t config = + { + .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, + .erclkDiv = 1U, + }; + + OSC_SetExtRefClkConfig(OSC, &config); + @endcode + * + * @param base OSC peripheral address. + * @param config Pointer to the configuration structure. + */ +static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); + reg |= config->enableMode; + + base->CR = reg; +} + +/*! + * @brief Sets the capacitor load configuration for the oscillator. + * + * This function sets the specified capacitors configuration for the oscillator. + * This should be done in the early system level initialization function call + * based on the system configuration. + * + * @param base OSC peripheral address. + * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. + * + * Example: + @code + // To enable only 2 pF and 8 pF capacitor load, please use like this. + OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); + @endcode + */ +static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Initialize OSC0. + * + * This function initializes OSC0 according to board configuration. + * + * @param config Pointer to the OSC0 configuration structure. + */ +void CLOCK_InitOsc0(osc_config_t const *config); + +/*! + * @brief Deinitialize OSC0. + * + * This function deinitializes OSC0. + */ +void CLOCK_DeinitOsc0(void); + +/* @} */ + +/*! + * @name MCG auto-trim machine. + * @{ + */ + +/*! + * @brief Auto trim the internal reference clock. + * + * This function trims the internal reference clock using external clock. If + * successful, it returns the kStatus_Success and the frequency after + * trimming is received in the parameter @p actualFreq. If an error occurs, + * the error code is returned. + * + * @param extFreq External clock frequency, should be bus clock. + * @param desireFreq Frequency want to trim to. + * @param actualFreq Actual frequency after trim. + * @param atms Trim fast or slow internal reference clock. + * @retval kStatus_Success ATM success. + * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM. + * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. + * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source. + * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim. + */ +status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); +/* @} */ + +/*! @name MCG mode functions. */ +/*@{*/ + +/*! + * @brief Gets the current MCG mode. + * + * This function checks the MCG registers and determine current MCG mode. + * + * @return Current MCG mode or error code, see @ref mcg_mode_t. + */ +mcg_mode_t CLOCK_GetMode(void); + +/*! + * @brief Set MCG to FEI mode. + * + * This function sets MCG to FEI mode. If could not set to FEI mode directly + * from current mode, this function returns error. @ref kMCG_Dmx32Default is used in this + * mode because using kMCG_Dmx32Fine with internal reference clock source + * might damage hardware. + * + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable, if pass + * in NULL, then does not delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FEE mode. + * + * This function sets MCG to FEE mode. If could not set to FEE mode directly + * from current mode, this function returns error. + * + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable, if pass + * in NULL, then does not delay. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FBI mode. + * + * This function sets MCG to FBI mode. If could not set to FBI mode directly + * from current mode, this function returns error. + * + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. If FLL + * is not used in FBI mode, this parameter could be NULL. Pass in + * NULL does not delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FBE mode. + * + * This function sets MCG to FBE mode. If could not set to FBE mode directly + * from current mode, this function returns error. + * + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FBE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. If FLL + * is not used in FBE mode, this parameter could be NULL. Pass in NULL + * does not delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to BLPI mode. + * + * This function sets MCG to BLPI mode. If could not set to BLPI mode directly + * from current mode, this function returns error. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetBlpiMode(void); + +/*! + * @brief Set MCG to BLPE mode. + * + * This function sets MCG to BLPE mode. If could not set to BLPE mode directly + * from current mode, this function returns error. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetBlpeMode(void); + +/*! + * @brief Set MCG to PBE mode. + * + * This function sets MCG to PBE mode. If could not set to PBE mode directly + * from current mode, this function returns error. + * + * @param pllcs The PLL selection, PLLCS. + * @param config Pointer to the PLL configuration. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + * + * @note + * 1. The parameter \c pllcs selects the PLL, for some platforms, there is + * only one PLL, the parameter pllcs is kept for interface compatible. + * 2. The parameter \c config is the PLL configuration structure, on some + * platforms, could choose the external PLL directly. This means that the + * configuration structure is not necessary, pass in NULL for this case. + * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); + */ +status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); + +/*! + * @brief Set MCG to PEE mode. + * + * This function sets MCG to PEE mode. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + * + * @note This function only change CLKS to use PLL/FLL output. If the + * PRDIV/VDIV are different from PBE mode, please setup these + * settings in PBE mode and wait for stable then switch to PEE mode. + */ +status_t CLOCK_SetPeeMode(void); + +/*! + * @brief Switch MCG to FBE mode quickly from external mode. + * + * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly. + * It only changes to use external clock as the system clock souce and disable PLL, but does not + * configure FLL settings. This is a lite function with small code size, it is useful + * during mode switch. For example, to switch from PEE mode to FEI mode: + * + * @code + * CLOCK_ExternalModeToFbeModeQuick(); + * CLOCK_SetFeiMode(...); + * @endcode + * + * @retval kStatus_Success Change successfully. + * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function. + */ +status_t CLOCK_ExternalModeToFbeModeQuick(void); + +/*! + * @brief Switch MCG to FBI mode quickly from internal modes. + * + * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly. + * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not + * configure FLL settings. This is a lite function with small code size, it is useful + * during mode switch. For example, to switch from PEI mode to FEE mode: + * + * @code + * CLOCK_InternalModeToFbiModeQuick(); + * CLOCK_SetFeeMode(...); + * @endcode + * + * @retval kStatus_Success Change successfully. + * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function. + */ +status_t CLOCK_InternalModeToFbiModeQuick(void); + +/*! + * @brief Set MCG to FEI mode during system boot up. + * + * This function sets MCG to FEI mode from reset mode, it could be used to + * set up MCG during system boot up. @ref kMCG_Dmx32Default is used in this + * mode because using kMCG_Dmx32Fine with internal reference clock source + * might damage hardware. + * + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FEE mode during system bootup. + * + * This function sets MCG to FEE mode from reset mode, it could be used to + * set up MCG during system boot up. + * + * @param oscsel OSC clock select, OSCSEL. + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToFeeMode( + mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to BLPI mode during system boot up. + * + * This function sets MCG to BLPI mode from reset mode, it could be used to + * setup MCG during sytem boot up. + * + * @param fcrdiv Fast IRC divider, FCRDIV. + * @param ircs The internal reference clock to select, IRCS. + * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. + * + * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); + +/*! + * @brief Set MCG to BLPE mode during sytem boot up. + * + * This function sets MCG to BLPE mode from reset mode, it could be used to + * setup MCG during sytem boot up. + * + * @param oscsel OSC clock select, MCG_C7[OSCSEL]. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); + +/*! + * @brief Set MCG to PEE mode during system boot up. + * + * This function sets MCG to PEE mode from reset mode, it could be used to + * setup MCG during system boot up. + * + * @param oscsel OSC clock select, MCG_C7[OSCSEL]. + * @param pllcs The PLL selection, PLLCS. + * @param config Pointer to the PLL configuration. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); + +/*! + * @brief Set MCG to some target mode. + * + * This function sets MCG to some target mode defined by the configure + * structure, if cannot switch to target mode directly, this function will + * choose the proper path. + * + * @param config Pointer to the target MCG mode configuration structure. + * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status. + * + * @note If external clock is used in the target mode, please make sure it is + * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before + * this funciton. + */ +status_t CLOCK_SetMcgConfig(mcg_config_t const *config); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c new file mode 100755 index 00000000000..09885e74211 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmp.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for CMP module. + * + * @param base CMP peripheral base address + */ +static uint32_t CMP_GetInstance(CMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CMP bases for each instance. */ +static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; +/*! @brief Pointers to CMP clocks for each instance. */ +const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t CMP_GetInstance(CMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++) + { + if (s_cmpBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_CMP_COUNT); + + return instance; +} + +void CMP_Init(CMP_Type *base, const cmp_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* Enable the clock. */ + CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); + + /* Configure. */ + CMP_Enable(base, false); /* Disable the CMP module during configuring. */ + /* CMPx_CR1. */ + tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); + if (config->enableHighSpeed) + { + tmp8 |= CMP_CR1_PMODE_MASK; + } + if (config->enableInvertOutput) + { + tmp8 |= CMP_CR1_INV_MASK; + } + if (config->useUnfilteredOutput) + { + tmp8 |= CMP_CR1_COS_MASK; + } + if (config->enablePinOut) + { + tmp8 |= CMP_CR1_OPE_MASK; + } +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + if (config->enableTriggerMode) + { + tmp8 |= CMP_CR1_TRIGM_MASK; + } + else + { + tmp8 &= ~CMP_CR1_TRIGM_MASK; + } +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + base->CR1 = tmp8; + + /* CMPx_CR0. */ + tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; + tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); + base->CR0 = tmp8; + + CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ +} + +void CMP_Deinit(CMP_Type *base) +{ + /* Disable the CMP module. */ + CMP_Enable(base, false); + + /* Disable the clock. */ + CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); +} + +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + assert(NULL != config); + + config->enableCmp = true; /* Enable the CMP module after initialization. */ + config->hysteresisMode = kCMP_HysteresisLevel0; + config->enableHighSpeed = false; + config->enableInvertOutput = false; + config->useUnfilteredOutput = false; + config->enablePinOut = false; +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} + +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) +{ + uint8_t tmp8 = base->MUXCR; + + tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); + tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); + base->MUXCR = tmp8; +} + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +void CMP_EnableDMA(CMP_Type *base, bool enable) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (enable) + { + tmp8 |= CMP_SCR_DMAEN_MASK; + } + else + { + tmp8 &= ~CMP_SCR_DMAEN_MASK; + } + base->SCR = tmp8; +} +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + /* Choose the clock source for sampling. */ + if (config->enableSample) + { + base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ + } + else + { + base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ + } +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + /* Set the filter count. */ + tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; + tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); + base->CR0 = tmp8; + /* Set the filter period. It is used as the divider to bus clock. */ + base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); +} + +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) +{ + uint8_t tmp8 = 0U; + + if (NULL == config) + { + /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ + base->DACCR = 0U; + return; + } + /* CMPx_DACCR. */ + tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ + if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) + { + tmp8 |= CMP_DACCR_VRSEL_MASK; + } + tmp8 |= CMP_DACCR_VOSEL(config->DACValue); + + base->DACCR = tmp8; +} + +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +uint32_t CMP_GetStatusFlags(CMP_Type *base) +{ + uint32_t ret32 = 0U; + + if (0U != (CMP_SCR_CFR_MASK & base->SCR)) + { + ret32 |= kCMP_OutputRisingEventFlag; + } + if (0U != (CMP_SCR_CFF_MASK & base->SCR)) + { + ret32 |= kCMP_OutputFallingEventFlag; + } + if (0U != (CMP_SCR_COUT_MASK & base->SCR)) + { + ret32 |= kCMP_OutputAssertEventFlag; + } + return ret32; +} + +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFR_MASK; + } + if (0U != (kCMP_OutputFallingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFF_MASK; + } + base->SCR = tmp8; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h new file mode 100755 index 00000000000..53d84a0f2d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CMP_H_ +#define _FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMP driver version 2.0.0. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! +* @brief Interrupt enable/disable mask. +*/ +enum _cmp_interrupt_enable +{ + kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ + kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ +}; + +/*! + * @brief Status flags' mask. + */ +enum _cmp_status_flags +{ + kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on compare output has occurred. */ + kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */ + kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ +}; + +/*! + * @brief CMP Hysteresis mode. + */ +typedef enum _cmp_hysteresis_mode +{ + kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ + kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ + kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ + kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ +} cmp_hysteresis_mode_t; + +/*! + * @brief CMP Voltage Reference source. + */ +typedef enum _cmp_reference_voltage_source +{ + kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */ + kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */ +} cmp_reference_voltage_source_t; + +/*! + * @brief Configure the comparator. + */ +typedef struct _cmp_config +{ + bool enableCmp; /*!< Enable the CMP module. */ + cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ + bool enableHighSpeed; /*!< Enable High Speed (HS) comparison mode. */ + bool enableInvertOutput; /*!< Enable inverted comparator output. */ + bool useUnfilteredOutput; /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */ + bool enablePinOut; /*!< The comparator output is available on the associated pin. */ +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool enableTriggerMode; /*!< Enable the trigger mode. */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} cmp_config_t; + +/*! + * @brief Configure the filter. + */ +typedef struct _cmp_filter_config +{ +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + bool enableSample; /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */ +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/ + uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */ +} cmp_filter_config_t; + +/*! + * @brief Configure the internal DAC. + */ +typedef struct _cmp_dac_config +{ + cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ + uint8_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-63.*/ +} cmp_dac_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are: + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config); + +/*! + * @brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are: + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * @param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base); + +/*! + * @brief Enables/disables the CMP module. + * + * @param base CMP peripheral base address. + * @param enable Enable the module or not. + */ +static inline void CMP_Enable(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_EN_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_EN_MASK; + } +} + +/*! +* @brief Initializes the CMP user configuration structure. +* +* This function initializes the user configure structure to these default values: +* @code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* @endcode +* @param config Pointer to the configuration structure. +*/ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/*! + * @brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set as same in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * @param base CMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA + * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP + * if the + * DMA is disabled. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable); +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE +/*! + * @brief Enables/disables the window mode. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_WE_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_WE_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ + +#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE +/*! + * @brief Enables/disables the pass through mode. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->MUXCR |= CMP_MUXCR_PSTM_MASK; + } + else + { + base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ + +/*! + * @brief Configures the filter. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); + +/*! + * @brief Configures the internal DAC. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. "NULL" is for disabling the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); + +/*! + * @brief Enables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Results + * @{ + */ + +/*! + * @brief Gets the status flags. + * + * @param base CMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base); + +/*! + * @brief Clears the status flags. + * + * @param base CMP peripheral base address. + * @param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_CMP_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c new file mode 100755 index 00000000000..9e8831f9983 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmt.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The standard intermediate frequency (IF). */ +#define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U) +/* CMT data modulate mask. */ +#define CMT_MODULATE_COUNT_WIDTH (8U) +/* CMT diver 1. */ +#define CMT_CMTDIV_ONE (1) +/* CMT diver 2. */ +#define CMT_CMTDIV_TWO (2) +/* CMT diver 4. */ +#define CMT_CMTDIV_FOUR (4) +/* CMT diver 8. */ +#define CMT_CMTDIV_EIGHT (8) +/* CMT mode bit mask. */ +#define CMT_MODE_BIT_MASK (CMT_MSC_MCGEN_MASK | CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for CMT module. + * + * @param base CMT peripheral base address. + */ +static uint32_t CMT_GetInstance(CMT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to cmt clocks for each instance. */ +const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS; + +/*! @brief Pointers to cmt bases for each instance. */ +static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS; + +/*! @brief Pointers to cmt IRQ number for each instance. */ +const IRQn_Type s_cmtIrqs[] = CMT_IRQS; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t CMT_GetInstance(CMT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_CMT_COUNT; instance++) + { + if (s_cmtBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_CMT_COUNT); + + return instance; +} + +void CMT_GetDefaultConfig(cmt_config_t *config) +{ + assert(config); + + /* Default infrared output is enabled and set with high active, the divider is set to 1. */ + config->isInterruptEnabled = false; + config->isIroEnabled = true; + config->iroPolarity = kCMT_IROActiveHigh; + config->divider = kCMT_SecondClkDiv1; +} + +void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz) +{ + assert(config); + assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ); + + uint8_t divider; + + /* Ungate clock. */ + CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]); + + /* Sets clock divider. The divider set in pps should be set + to make sycClock_Hz/divder = 8MHz */ + base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1); + divider = base->MSC; + divider &= ~CMT_MSC_CMTDIV_MASK; + divider |= CMT_MSC_CMTDIV(config->divider); + base->MSC = divider; + + /* Set the IRO signal. */ + base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled); + + /* Set interrupt. */ + if (config->isInterruptEnabled) + { + CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable); + EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); + } +} + +void CMT_Deinit(CMT_Type *base) +{ + /*Disable the CMT modulator. */ + base->MSC = 0; + + /* Disable the interrupt. */ + CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable); + DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); + + /* Gate the clock. */ + CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]); +} + +void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig) +{ + uint8_t mscReg; + + /* Set the mode. */ + if (mode != kCMT_DirectIROCtl) + { + assert(modulateConfig); + + /* Set carrier generator. */ + CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1); + if (mode == kCMT_FSKMode) + { + CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2); + } + + /* Set carrier modulator. */ + CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount); + } + + /* Set the CMT mode. */ + mscReg = base->MSC; + mscReg &= ~CMT_MODE_BIT_MASK; + mscReg |= mode; + + base->MSC = mscReg; +} + +cmt_mode_t CMT_GetMode(CMT_Type *base) +{ + uint8_t mode = base->MSC; + + if (!(mode & CMT_MSC_MCGEN_MASK)) + { /* Carrier modulator disabled and the IRO signal is in direct software control. */ + return kCMT_DirectIROCtl; + } + else + { + /* Carrier modulator is enabled. */ + if (mode & CMT_MSC_BASE_MASK) + { + /* Base band mode. */ + return kCMT_BasebandMode; + } + else if (mode & CMT_MSC_FSK_MASK) + { + /* FSK mode. */ + return kCMT_FSKMode; + } + else + { + /* Time mode. */ + return kCMT_TimeMode; + } + } +} + +uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz) +{ + uint32_t frequency; + uint32_t divider; + + /* Get intermediate frequency. */ + frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1); + + /* Get the second divider. */ + divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT); + /* Get CMT frequency. */ + switch ((cmt_second_clkdiv_t)divider) + { + case kCMT_SecondClkDiv1: + frequency = frequency / CMT_CMTDIV_ONE; + break; + case kCMT_SecondClkDiv2: + frequency = frequency / CMT_CMTDIV_TWO; + break; + case kCMT_SecondClkDiv4: + frequency = frequency / CMT_CMTDIV_FOUR; + break; + case kCMT_SecondClkDiv8: + frequency = frequency / CMT_CMTDIV_EIGHT; + break; + default: + frequency = frequency / CMT_CMTDIV_ONE; + break; + } + + return frequency; +} + +void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount) +{ + /* Set modulate mark. */ + base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK; + base->CMD2 = (markCount & CMT_CMD2_MB_MASK); + /* Set modulate space. */ + base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK; + base->CMD4 = spaceCount & CMT_CMD4_SB_MASK; +} + +void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state) +{ + uint8_t ocReg = base->OC; + + ocReg &= ~CMT_OC_IROL_MASK; + ocReg |= CMT_OC_IROL(state); + + /* Set the infrared output signal control. */ + base->OC = ocReg; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h new file mode 100755 index 00000000000..df0b2c91066 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CMT_H_ +#define _FSL_CMT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMT driver version 2.0.0. */ +#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief The modes of CMT. + */ +typedef enum _cmt_mode +{ + kCMT_DirectIROCtl = 0x00U, /*!< Carrier modulator is disabled and the IRO signal is directly in software control */ + kCMT_TimeMode = 0x01U, /*!< Carrier modulator is enabled in time mode. */ + kCMT_FSKMode = 0x05U, /*!< Carrier modulator is enabled in FSK mode. */ + kCMT_BasebandMode = 0x09U /*!< Carrier modulator is enabled in baseband mode. */ +} cmt_mode_t; + +/*! + * @brief The CMT clock divide primary prescaler. + * The primary clock divider is used to divider the bus clock to + * get the intermediate frequency to approximately equal to 8 MHZ. + * When the bus clock is 8 MHZ, set primary prescaler to "kCMT_PrimaryClkDiv1". + */ +typedef enum _cmt_primary_clkdiv +{ + kCMT_PrimaryClkDiv1 = 0U, /*!< The intermediate frequency is the bus clock divided by 1. */ + kCMT_PrimaryClkDiv2 = 1U, /*!< The intermediate frequency is the bus clock divided by 2. */ + kCMT_PrimaryClkDiv3 = 2U, /*!< The intermediate frequency is the bus clock divided by 3. */ + kCMT_PrimaryClkDiv4 = 3U, /*!< The intermediate frequency is the bus clock divided by 4. */ + kCMT_PrimaryClkDiv5 = 4U, /*!< The intermediate frequency is the bus clock divided by 5. */ + kCMT_PrimaryClkDiv6 = 5U, /*!< The intermediate frequency is the bus clock divided by 6. */ + kCMT_PrimaryClkDiv7 = 6U, /*!< The intermediate frequency is the bus clock divided by 7. */ + kCMT_PrimaryClkDiv8 = 7U, /*!< The intermediate frequency is the bus clock divided by 8. */ + kCMT_PrimaryClkDiv9 = 8U, /*!< The intermediate frequency is the bus clock divided by 9. */ + kCMT_PrimaryClkDiv10 = 9U, /*!< The intermediate frequency is the bus clock divided by 10. */ + kCMT_PrimaryClkDiv11 = 10U, /*!< The intermediate frequency is the bus clock divided by 11. */ + kCMT_PrimaryClkDiv12 = 11U, /*!< The intermediate frequency is the bus clock divided by 12. */ + kCMT_PrimaryClkDiv13 = 12U, /*!< The intermediate frequency is the bus clock divided by 13. */ + kCMT_PrimaryClkDiv14 = 13U, /*!< The intermediate frequency is the bus clock divided by 14. */ + kCMT_PrimaryClkDiv15 = 14U, /*!< The intermediate frequency is the bus clock divided by 15. */ + kCMT_PrimaryClkDiv16 = 15U /*!< The intermediate frequency is the bus clock divided by 16. */ +} cmt_primary_clkdiv_t; + +/*! + * @brief The CMT clock divide secondary prescaler. + * The second prescaler can be used to divide the 8 MHZ CMT clock + * by 1, 2, 4, or 8 according to the specification. + */ +typedef enum _cmt_second_clkdiv +{ + kCMT_SecondClkDiv1 = 0U, /*!< The CMT clock is the intermediate frequency frequency divided by 1. */ + kCMT_SecondClkDiv2 = 1U, /*!< The CMT clock is the intermediate frequency frequency divided by 2. */ + kCMT_SecondClkDiv4 = 2U, /*!< The CMT clock is the intermediate frequency frequency divided by 4. */ + kCMT_SecondClkDiv8 = 3U /*!< The CMT clock is the intermediate frequency frequency divided by 8. */ +} cmt_second_clkdiv_t; + +/*! + * @brief The CMT infrared output polarity. + */ +typedef enum _cmt_infrared_output_polarity +{ + kCMT_IROActiveLow = 0U, /*!< The CMT infrared output signal polarity is active-low. */ + kCMT_IROActiveHigh = 1U /*!< The CMT infrared output signal polarity is active-high. */ +} cmt_infrared_output_polarity_t; + +/*! + * @brief The CMT infrared output signal state control. + */ +typedef enum _cmt_infrared_output_state +{ + kCMT_IROCtlLow = 0U, /*!< The CMT Infrared output signal state is controlled to low. */ + kCMT_IROCtlHigh = 1U /*!< The CMT Infrared output signal state is controlled to high. */ +} cmt_infrared_output_state_t; + +/*! + * @brief CMT interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the CMT interrupt configurations. + */ +enum _cmt_interrupt_enable +{ + kCMT_EndOfCycleInterruptEnable = CMT_MSC_EOCIE_MASK, /*!< CMT end of cycle interrupt. */ +}; + +/*! + * @brief CMT carrier generator and modulator configure structure + * + */ +typedef struct _cmt_modulate_config +{ + uint8_t highCount1; /*!< The high time for carrier generator first register. */ + uint8_t lowCount1; /*!< The low time for carrier generator first register. */ + uint8_t highCount2; /*!< The high time for carrier generator second register for FSK mode. */ + uint8_t lowCount2; /*!< The low time for carrier generator second register for FSK mode. */ + uint16_t markCount; /*!< The mark time for the modulator gate. */ + uint16_t spaceCount; /*!< The space time for the modulator gate. */ +} cmt_modulate_config_t; + +/*! @brief CMT basic configuration structure. */ +typedef struct _cmt_config +{ + bool isInterruptEnabled; /*!< Timer interrupt 0-disable, 1-enable. */ + bool isIroEnabled; /*!< The IRO output 0-disabled, 1-enabled. */ + cmt_infrared_output_polarity_t iroPolarity; /*!< The IRO polarity. */ + cmt_second_clkdiv_t divider; /*!< The CMT clock divide prescaler. */ +} cmt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Gets the CMT default configuration structure. The purpose + * of this API is to get the default configuration structure for the CMT_Init(). + * Use the initialized structure unchanged in CMT_Init(), or modify + * some fields of the structure before calling the CMT_Init(). + * + * @param config The CMT configuration structure pointer. + */ +void CMT_GetDefaultConfig(cmt_config_t *config); + +/*! + * @brief Initializes the CMT module. + * + * This function ungates the module clock and sets the CMT internal clock, + * interrupt, and infrared output signal for the CMT module. + * + * @param base CMT peripheral base address. + * @param config The CMT basic configuration structure. + * @param busClock_Hz The CMT module input clock - bus clock frequency. + */ +void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz); + +/*! + * @brief Disables the CMT module and gate control. + * + * This function disables CMT modulator, interrupts, and gates the + * CMT clock control. CMT_Init must be called to use the CMT again. + * + * @param base CMT peripheral base address. + */ +void CMT_Deinit(CMT_Type *base); + +/*! @}*/ + +/*! + * @name Basic Control Operations + * @{ + */ + +/*! + * @brief Selects the mode for CMT. + * + * @param base CMT peripheral base address. + * @param mode The CMT feature mode enumeration. See "cmt_mode_t". + * @param modulateConfig The carrier generation and modulator configuration. + */ +void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig); + +/*! + * @brief Gets the mode of the CMT module. + * + * @param base CMT peripheral base address. + * @return The CMT mode. + * kCMT_DirectIROCtl Carrier modulator is disabled, the IRO signal is directly in software control. + * kCMT_TimeMode Carrier modulator is enabled in time mode. + * kCMT_FSKMode Carrier modulator is enabled in FSK mode. + * kCMT_BasebandMode Carrier modulator is enabled in baseband mode. + */ +cmt_mode_t CMT_GetMode(CMT_Type *base); + +/*! + * @brief Gets the actual CMT clock frequency. + * + * @param base CMT peripheral base address. + * @param busClock_Hz CMT module input clock - bus clock frequency. + * @return The CMT clock frequency. + */ +uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz); + +/*! + * @brief Sets the primary data set for the CMT carrier generator counter. + * + * This function sets the high time and low time of the primary data set for the + * CMT carrier generator counter to control the period and the duty cycle of the + * output carrier signal. + * If the CMT clock period is Tcmt, The period of the carrier generator signal equals + * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount). + * + * @param base CMT peripheral base address. + * @param highCount The number of CMT clocks for carrier generator signal high time, + * integer in the range of 1 ~ 0xFF. + * @param lowCount The number of CMT clocks for carrier generator signal low time, + * integer in the range of 1 ~ 0xFF. + */ +static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCount, uint32_t lowCount) +{ + assert(highCount <= CMT_CGH1_PH_MASK); + assert(highCount); + assert(lowCount <= CMT_CGL1_PL_MASK); + assert(lowCount); + + base->CGH1 = highCount; + base->CGL1 = lowCount; +} + +/*! + * @brief Sets the secondary data set for the CMT carrier generator counter. + * + * This function is used for FSK mode setting the high time and low time of the secondary + * data set CMT carrier generator counter to control the period and the duty cycle + * of the output carrier signal. + * If the CMT clock period is Tcmt, The period of the carrier generator signal equals + * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount). + * + * @param base CMT peripheral base address. + * @param highCount The number of CMT clocks for carrier generator signal high time, + * integer in the range of 1 ~ 0xFF. + * @param lowCount The number of CMT clocks for carrier generator signal low time, + * integer in the range of 1 ~ 0xFF. + */ +static inline void CMT_SetCarrirGenerateCountTwo(CMT_Type *base, uint32_t highCount, uint32_t lowCount) +{ + assert(highCount <= CMT_CGH2_SH_MASK); + assert(highCount); + assert(lowCount <= CMT_CGL2_SL_MASK); + assert(lowCount); + + base->CGH2 = highCount; + base->CGL2 = lowCount; +} + +/*! + * @brief Sets the modulation mark and space time period for the CMT modulator. + * + * This function sets the mark time period of the CMT modulator counter + * to control the mark time of the output modulated signal from the carrier generator output signal. + * If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg: + * - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8). + * The space period of the generated signal equals spaceCount / (Fcmt/8). + * - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg. + * The space period of the generated signal equals spaceCount / fcg. + * + * @param base Base address for current CMT instance. + * @param markCount The number of clock period for CMT modulator signal mark period, + * in the range of 0 ~ 0xFFFF. + * @param spaceCount The number of clock period for CMT modulator signal space period, + * in the range of the 0 ~ 0xFFFF. + */ +void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount); + +/*! + * @brief Enables or disables the extended space operation. + * + * This function is used to make the space period longer + * for time, baseband, and FSK modes. + * + * @param base CMT peripheral base address. + * @param enable True enable the extended space, false disable the extended space. + */ +static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable) +{ + if (enable) + { + base->MSC |= CMT_MSC_EXSPC_MASK; + } + else + { + base->MSC &= ~CMT_MSC_EXSPC_MASK; + } +} + +/*! + * @brief Sets IRO - infrared output signal state. + * + * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set + * and the IRO signal is enabled. + * + * @param base CMT peripheral base address. + * @param state The control of the IRO signal. See "cmt_infrared_output_state_t" + */ +void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state); + +/*! + * @brief Enables the CMT interrupt. + * + * This function enables the CMT interrupts according to the provided maskIf enabled. + * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end + * of the modulator cycle. This interrupt provides a means for the user + * to reload the new mark/space values into the CMT modulator data registers + * and verify the modulator mark and space. + * For example, to enable the end of cycle, do the following: + * @code + * CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); + * @endcode + * @param base CMT peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. + */ +static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask) +{ + base->MSC |= mask; +} + +/*! + * @brief Disables the CMT interrupt. + * + * This function disables the CMT interrupts according to the provided maskIf enabled. + * The CMT only has the end of the cycle interrupt. + * For example, to disable the end of cycle, do the following: + * @code + * CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); + * @endcode + * + * @param base CMT peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. + */ +static inline void CMT_DisableInterrupts(CMT_Type *base, uint32_t mask) +{ + base->MSC &= ~mask; +} + +/*! + * @brief Gets the end of the cycle status flag. + * + * The flag is set: + * - When the modulator is not currently active and carrier and modulator + * are set to start the initial CMT transmission. + * - At the end of each modulation cycle when the counter is reloaded and + * the carrier and modulator are enabled. + * @param base CMT peripheral base address. + * @return Current status of the end of cycle status flag + * @arg non-zero: End-of-cycle has occurred. + * @arg zero: End-of-cycle has not yet occurred since the flag last cleared. + */ +static inline uint32_t CMT_GetStatusFlags(CMT_Type *base) +{ + return base->MSC & CMT_MSC_EOCF_MASK; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CMT_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c new file mode 100755 index 00000000000..895bbb04a00 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +/* This is not needed for mbed */ +#if 0 +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __asm("bkpt #0"); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __asm("bkpt #0"); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ +#endif +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + + __disable_irq(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + __enable_irq(); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h new file mode 100755 index 00000000000..105dca049a7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Enable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void EnableIRQ(IRQn_Type interrupt) +{ +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { + NVIC_EnableIRQ(interrupt); + } +} + +/*! + * @brief Disable specific interrupt. + * + * Disable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void DisableIRQ(IRQn_Type interrupt) +{ +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { + NVIC_DisableIRQ(interrupt); + } +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +} + +/*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ + __set_PRIMASK(primask); +} + +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + */ +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c new file mode 100755 index 00000000000..f73647e1c78 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! +* @brief CRC module configuration. +* +* This structure holds the configuration for the CRC module. +*/ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + crc_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + crc_ConfigureAndStart(base, &moduleConfig); +} + +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + crc_SetProtocolConfig(base, config); + } + else + { + crc_SetRawProtocolConfig(base, config); + } +} + +void CRC_GetDefaultConfig(crc_config_t *config) +{ + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((dataSize) && ((uint32_t)data & 3U)) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h new file mode 100755 index 00000000000..ce0b60fbaf9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.0. */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! +* @brief CRC protocol configuration. +* +* This structure holds the configuration for the CRC protocol. +* +*/ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral. + * It also configures the CRC module and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +} + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register (intermediate or final checksum). + * The configured type of transpose and complement are applied. + * + * @param base CRC peripheral address. + * @return intermediate or final 32-bit checksum, after configured transpose and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register (intermediate or final checksum). + * The configured type of transpose and complement are applied. + * + * @param base CRC peripheral address. + * @return intermediate or final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c new file mode 100755 index 00000000000..2f83f5ee9e6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dac.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DAC module. + * + * @param base DAC peripheral base address + */ +static uint32_t DAC_GetInstance(DAC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DAC bases for each instance. */ +static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS; +/*! @brief Pointers to DAC clocks for each instance. */ +const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t DAC_GetInstance(DAC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DAC_COUNT; instance++) + { + if (s_dacBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DAC_COUNT); + + return instance; +} + +void DAC_Init(DAC_Type *base, const dac_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* Enable the clock. */ + CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); + + /* Configure. */ + /* DACx_C0. */ + tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK); + if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource) + { + tmp8 |= DAC_C0_DACRFS_MASK; + } + if (config->enableLowPowerMode) + { + tmp8 |= DAC_C0_LPEN_MASK; + } + base->C0 = tmp8; + + DAC_Enable(base, true); +} + +void DAC_Deinit(DAC_Type *base) +{ + DAC_Enable(base, false); + + /* Disable the clock. */ + CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); +} + +void DAC_GetDefaultConfig(dac_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + config->enableLowPowerMode = false; +} + +void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* DACx_C0. */ + tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK); + if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode) + { + tmp8 |= DAC_C0_DACTRGSEL_MASK; + } + base->C0 = tmp8; + + /* DACx_C1. */ + tmp8 = base->C1 & + ~( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + DAC_C1_DACBFWM_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + DAC_C1_DACBFMD_MASK); +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + tmp8 |= DAC_C1_DACBFWM(config->watermark); +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + tmp8 |= DAC_C1_DACBFMD(config->workMode); + base->C1 = tmp8; + + /* DACx_C2. */ + tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK; + tmp8 |= DAC_C2_DACBFUP(config->upperLimit); + base->C2 = tmp8; +} + +void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config) +{ + assert(NULL != config); + + config->triggerMode = kDAC_BufferTriggerBySoftwareMode; +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + config->watermark = kDAC_BufferWatermark1Word; +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + config->workMode = kDAC_BufferWorkAsNormalMode; + config->upperLimit = DAC_DATL_COUNT - 1U; +} + +void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value) +{ + assert(index < DAC_DATL_COUNT); + + base->DAT[index].DATL = (uint8_t)(0xFFU & value); /* Low 8-bit. */ + base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */ +} + +void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index) +{ + assert(index < DAC_DATL_COUNT); + + uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK; + + tmp8 |= DAC_C2_DACBFRP(index); + base->C2 = tmp8; +} + +void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_C0_DACBWIEN_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); + base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ +} + +void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_C0_DACBWIEN_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); + base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ +} + +uint32_t DAC_GetBufferStatusFlags(DAC_Type *base) +{ + return (uint32_t)(base->SR & ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_SR_DACBFWMF_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK)); +} + +void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_SR_DACBFWMF_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK); + base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */ +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h new file mode 100755 index 00000000000..44e2d048bd9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DAC_H_ +#define _FSL_DAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dac + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DAC driver version 2.0.0. */ +#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief DAC buffer flags. + */ +enum _dac_buffer_status_flags +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK, /*!< DAC Buffer Watermark Flag. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + kDAC_BufferReadPointerTopPositionFlag = DAC_SR_DACBFRPTF_MASK, /*!< DAC Buffer Read Pointer Top Position Flag. */ + kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position + Flag. */ +}; + +/*! + * @brief DAC buffer interrupts. + */ +enum _dac_buffer_interrupt_enable +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK, /*!< DAC Buffer Watermark Interrupt Enable. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK, /*!< DAC Buffer Read Pointer Top Flag Interrupt + Enable. */ + kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag + Interrupt Enable */ +}; + +/*! + * @brief DAC reference voltage source. + */ +typedef enum _dac_reference_voltage_source +{ + kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ + kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ +} dac_reference_voltage_source_t; + +/*! + * @brief DAC buffer trigger mode. + */ +typedef enum _dac_buffer_trigger_mode +{ + kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */ + kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */ +} dac_buffer_trigger_mode_t; + +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION +/*! + * @brief DAC buffer watermark. + */ +typedef enum _dac_buffer_watermark +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD + kDAC_BufferWatermark1Word = 0U, /*!< 1 word away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD + kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD + kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD + kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD */ +} dac_buffer_watermark_t; +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + +/*! + * @brief DAC buffer work mode. + */ +typedef enum _dac_buffer_work_mode +{ + kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */ +#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE + kDAC_BufferWorkAsSwingMode, /*!< Swing mode. */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */ + kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */ +#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE + kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */ +} dac_buffer_work_mode_t; + +/*! + * @brief DAC module configuration. + */ +typedef struct _dac_config +{ + dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */ + bool enableLowPowerMode; /*!< Enable the low power mode. */ +} dac_config_t; + +/*! + * @brief DAC buffer configuration. + */ +typedef struct _dac_buffer_config +{ + dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + dac_buffer_work_mode_t workMode; /*!< Select the buffer's work mode. */ + uint8_t upperLimit; /*!< Set the upper limit for buffer index. + Normally, 0-15 is available for buffer with 16 item. */ +} dac_buffer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the DAC module. + * + * This function initializes the DAC module, including: + * - Enabling the clock for DAC module. + * - Configuring the DAC converter with a user configuration. + * - Enabling the DAC module. + * + * @param base DAC peripheral base address. + * @param config Pointer to the configuration structure. See "dac_config_t". + */ +void DAC_Init(DAC_Type *base, const dac_config_t *config); + +/*! + * @brief De-initializes the DAC module. + * + * This function de-initializes the DAC module, including: + * - Disabling the DAC module. + * - Disabling the clock for the DAC module. + * + * @param base DAC peripheral base address. + */ +void DAC_Deinit(DAC_Type *base); + +/*! + * @brief Initializes the DAC user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are: + * @code + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + * config->enableLowPowerMode = false; + * @endcode + * @param config Pointer to the configuration structure. See "dac_config_t". + */ +void DAC_GetDefaultConfig(dac_config_t *config); + +/*! + * @brief Enables the DAC module. + * + * @param base DAC peripheral base address. + * @param enable Enables the feature or not. + */ +static inline void DAC_Enable(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C0 |= DAC_C0_DACEN_MASK; + } + else + { + base->C0 &= ~DAC_C0_DACEN_MASK; + } +} + +/* @} */ + +/*! + * @name Buffer + * @{ + */ + +/*! + * @brief Enables the DAC buffer. + * + * @param base DAC peripheral base address. + * @param enable Enables the feature or not. + */ +static inline void DAC_EnableBuffer(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= DAC_C1_DACBFEN_MASK; + } + else + { + base->C1 &= ~DAC_C1_DACBFEN_MASK; + } +} + +/*! + * @brief Configures the CMP buffer. + * + * @param base DAC peripheral base address. + * @param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ +void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config); + +/*! + * @brief Initializes the DAC buffer configuration structure. + * + * This function initializes the DAC buffer configuration structure to a default value. The default values are: + * @code + * config->triggerMode = kDAC_BufferTriggerBySoftwareMode; + * config->watermark = kDAC_BufferWatermark1Word; + * config->workMode = kDAC_BufferWorkAsNormalMode; + * config->upperLimit = DAC_DATL_COUNT - 1U; + * @endcode + * @param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ +void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config); + +/*! + * @brief Enables the DMA for DAC buffer. + * + * @param base DAC peripheral base address. + * @param enable Enables the feature or not. + */ +static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= DAC_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~DAC_C1_DMAEN_MASK; + } +} + +/*! + * @brief Sets the value for items in the buffer. + * + * @param base DAC peripheral base address. + * @param index Setting index for items in the buffer. The available index should not exceed the size of the DAC buffer. + * @param value Setting value for items in the buffer. 12-bits are available. + */ +void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value); + +/*! + * @brief Triggers the buffer by software and updates the read pointer of the DAC buffer. + * + * This function triggers the function by software. The read pointer of the DAC buffer is updated with one step + * after this function is called. Changing the read pointer depends on the buffer's work mode. + * + * @param base DAC peripheral base address. + */ +static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base) +{ + base->C0 |= DAC_C0_DACSWTRG_MASK; +} + +/*! + * @brief Gets the current read pointer of the DAC buffer. + * + * This function gets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated + * by software trigger or hardware trigger. + * + * @param base DAC peripheral base address. + * + * @return Current read pointer of DAC buffer. + */ +static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base) +{ + return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT); +} + +/*! + * @brief Sets the current read pointer of the DAC buffer. + * + * This function sets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated by + * software trigger or hardware trigger. After the read pointer changes, the DAC output value also changes. + * + * @param base DAC peripheral base address. + * @param index Setting index value for the pointer. + */ +void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index); + +/*! + * @brief Enables interrupts for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ +void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask); + +/*! + * @brief Disables interrupts for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ +void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask); + +/*! + * @brief Gets the flags of events for the DAC buffer. + * + * @param base DAC peripheral base address. + * + * @return Mask value for the asserted flags. See "_dac_buffer_status_flags". + */ +uint32_t DAC_GetBufferStatusFlags(DAC_Type *base); + +/*! + * @brief Clears the flags of events for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for flags. See "_dac_buffer_status_flags_t". + */ +void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_DAC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c new file mode 100755 index 00000000000..a288b9f22fc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMAMUX. + * + * @param base DMAMUX peripheral base address. + */ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMAMUX instance number to base pointer. */ +static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; + +/*! @brief Array to map DMAMUX instance number to clock name. */ +static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++) + { + if (s_dmamuxBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT); + + return instance; +} + +void DMAMUX_Init(DMAMUX_Type *base) +{ + CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +} + +void DMAMUX_Deinit(DMAMUX_Type *base) +{ + CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h new file mode 100755 index 00000000000..f4294d4dfa8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMAMUX_H_ +#define _FSL_DMAMUX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmamux + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMAMUX driver version 2.0.0. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMAMUX Initialize and De-initialize + * @{ + */ + +/*! + * @brief Initializes DMAMUX peripheral. + * + * This function ungate the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base); + +/*! + * @brief Deinitializes DMAMUX peripheral. + * + * This function gate the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base); + +/* @} */ +/*! + * @name DMAMUX Channel Operation + * @{ + */ + +/*! + * @brief Enable DMAMUX channel. + * + * This function enable DMAMUX channel to work. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Disable DMAMUX channel. + * + * This function disable DMAMUX channel. + * + * @note User must disable DMAMUX channel before configure it. + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Configure DMAMUX channel source. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param source Channel source which is used to trigger DMA transfer. + */ +static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t source) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); +} + +#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U +/*! + * @brief Enable DMAMUX period trigger. + * + * This function enable DMAMUX period trigger feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; +} + +/*! + * @brief Disable DMAMUX period trigger. + * + * This function disable DMAMUX period trigger. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; +} +#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /* _FSL_DMAMUX_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c new file mode 100755 index 00000000000..5654ce7aac6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c @@ -0,0 +1,1659 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_dspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Typedef for master interrupt handler. */ +typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DSPI module. + * + * @param base DSPI peripheral base address. + */ +uint32_t DSPI_GetInstance(SPI_Type *base); + +/*! + * @brief Configures the DSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base DSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type dspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type dspi_pcs_polarity_config_t. + */ +static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Master fill up the TX FIFO with data. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Slave fill up the TX FIFO with data. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief DSPI common interrupt handler. + * + * @param base DSPI peripheral address. + * @param handle pointer to g_dspiHandle which stores the transfer state. + */ +static void DSPI_CommonIRQHandler(SPI_Type *base, void *param); + +/*! + * @brief Master prepare the transfer. + * Basically it set up dspi_master_handle . + * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function. + */ +static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint32_t s_baudratePrescaler[] = {2, 3, 5, 7}; +static const uint32_t s_baudrateScaler[] = {2, 4, 6, 8, 16, 32, 64, 128, + 256, 512, 1024, 2048, 4096, 8192, 16384, 32768}; + +static const uint32_t s_delayPrescaler[] = {1, 3, 5, 7}; +static const uint32_t s_delayScaler[] = {2, 4, 8, 16, 32, 64, 128, 256, + 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536}; + +/*! @brief Pointers to dspi bases for each instance. */ +static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS; + +/*! @brief Pointers to dspi IRQ number for each instance. */ +static IRQn_Type const s_dspiIRQ[] = SPI_IRQS; + +/*! @brief Pointers to dspi clocks for each instance. */ +static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS; + +/*! @brief Pointers to dspi handles for each instance. */ +static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT]; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static dspi_master_isr_t s_dspiMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static dspi_slave_isr_t s_dspiSlaveIsr; + +/********************************************************************************************************************** +* Code +*********************************************************************************************************************/ +uint32_t DSPI_GetInstance(SPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++) + { + if (s_dspiBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DSPI_COUNT); + + return instance; +} + +void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + uint32_t temp; + /* enable DSPI clock */ + CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); + + DSPI_Enable(base, true); + DSPI_StopTransfer(base); + + DSPI_SetMasterSlaveMode(base, kDSPI_Master); + + temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | + SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); + + base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) | + SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) | + SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) | + SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); + + DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + if (0 == DSPI_MasterSetBaudRate(base, masterConfig->whichCtar, masterConfig->ctarConfig.baudRate, srcClock_Hz)) + { + assert(false); + } + + temp = base->CTAR[masterConfig->whichCtar] & + ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); + + base->CTAR[masterConfig->whichCtar] = + temp | SPI_CTAR_FMSZ(masterConfig->ctarConfig.bitsPerFrame - 1) | SPI_CTAR_CPOL(masterConfig->ctarConfig.cpol) | + SPI_CTAR_CPHA(masterConfig->ctarConfig.cpha) | SPI_CTAR_LSBFE(masterConfig->ctarConfig.direction); + + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_PcsToSck, srcClock_Hz, + masterConfig->ctarConfig.pcsToSckDelayInNanoSec); + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_LastSckToPcs, srcClock_Hz, + masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec); + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz, + masterConfig->ctarConfig.betweenTransferDelayInNanoSec); + + DSPI_StartTransfer(base); +} + +void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) +{ + masterConfig->whichCtar = kDSPI_Ctar0; + masterConfig->ctarConfig.baudRate = 500000; + masterConfig->ctarConfig.bitsPerFrame = 8; + masterConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + masterConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + masterConfig->ctarConfig.direction = kDSPI_MsbFirst; + + masterConfig->ctarConfig.pcsToSckDelayInNanoSec = 1000; + masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec = 1000; + masterConfig->ctarConfig.betweenTransferDelayInNanoSec = 1000; + + masterConfig->whichPcs = kDSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kDSPI_PcsActiveLow; + + masterConfig->enableContinuousSCK = false; + masterConfig->enableRxFifoOverWrite = false; + masterConfig->enableModifiedTimingFormat = false; + masterConfig->samplePoint = kDSPI_SckToSin0Clock; +} + +void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) +{ + uint32_t temp = 0; + + /* enable DSPI clock */ + CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); + + DSPI_Enable(base, true); + DSPI_StopTransfer(base); + + DSPI_SetMasterSlaveMode(base, kDSPI_Slave); + + temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | + SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); + + base->MCR = temp | SPI_MCR_CONT_SCKE(slaveConfig->enableContinuousSCK) | + SPI_MCR_MTFE(slaveConfig->enableModifiedTimingFormat) | + SPI_MCR_ROOE(slaveConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(slaveConfig->samplePoint) | + SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); + + DSPI_SetOnePcsPolarity(base, kDSPI_Pcs0, kDSPI_PcsActiveLow); + + temp = base->CTAR[slaveConfig->whichCtar] & + ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); + + base->CTAR[slaveConfig->whichCtar] = temp | SPI_CTAR_SLAVE_FMSZ(slaveConfig->ctarConfig.bitsPerFrame - 1) | + SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) | + SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha); + + DSPI_StartTransfer(base); +} + +void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) +{ + slaveConfig->whichCtar = kDSPI_Ctar0; + slaveConfig->ctarConfig.bitsPerFrame = 8; + slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + + slaveConfig->enableContinuousSCK = false; + slaveConfig->enableRxFifoOverWrite = false; + slaveConfig->enableModifiedTimingFormat = false; + slaveConfig->samplePoint = kDSPI_SckToSin0Clock; +} + +void DSPI_Deinit(SPI_Type *base) +{ + DSPI_StopTransfer(base); + DSPI_Enable(base, false); + + /* disable DSPI clock */ + CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]); +} + +static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t temp; + + temp = base->MCR; + + if (activeLowOrHigh == kDSPI_PcsActiveLow) + { + temp |= SPI_MCR_PCSIS(pcs); + } + else + { + temp &= ~SPI_MCR_PCSIS(pcs); + } + + base->MCR = temp; +} + +uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz) +{ + /* for master mode configuration, if slave mode detected, return 0*/ + if (!DSPI_IsMaster(base)) + { + return 0; + } + uint32_t temp; + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t dbr, bestDbr; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t baudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the requested value */ + min_diff = 0xFFFFFFFFU; + bestPrescaler = 0; + bestScaler = 0; + bestDbr = 1; + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 16) && min_diff; scaler++) + { + for (dbr = 1; (dbr < 3) && min_diff; dbr++) + { + realBaudrate = ((srcClock_Hz * dbr) / (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler]))); + + /* calculate the baud rate difference based on the conditional statement that states that the calculated + * baud rate must not exceed the desired baud rate. + */ + if (baudrate >= realBaudrate) + { + diff = baudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + bestDbr = dbr; + } + } + } + } + } + + /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ + temp = base->CTAR[whichCtar] & ~(SPI_CTAR_DBR_MASK | SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK); + + base->CTAR[whichCtar] = temp | ((bestDbr - 1) << SPI_CTAR_DBR_SHIFT) | (bestPrescaler << SPI_CTAR_PBR_SHIFT) | + (bestScaler << SPI_CTAR_BR_SHIFT); + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +void DSPI_MasterSetDelayScaler( + SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay) +{ + /* these settings are only relevant in master mode */ + if (DSPI_IsMaster(base)) + { + switch (whichDelay) + { + case kDSPI_PcsToSck: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK)) | + SPI_CTAR_PCSSCK(prescaler) | SPI_CTAR_CSSCK(scaler); + break; + case kDSPI_LastSckToPcs: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PASC_MASK) & (~SPI_CTAR_ASC_MASK)) | + SPI_CTAR_PASC(prescaler) | SPI_CTAR_ASC(scaler); + break; + case kDSPI_BetweenTransfer: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PDT_MASK) & (~SPI_CTAR_DT_MASK)) | + SPI_CTAR_PDT(prescaler) | SPI_CTAR_DT(scaler); + break; + default: + break; + } + } +} + +uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, + uint32_t srcClock_Hz, + uint32_t delayTimeInNanoSec) +{ + /* for master mode configuration, if slave mode detected, return 0 */ + if (!DSPI_IsMaster(base)) + { + return 0; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realDelay, bestDelay; + uint32_t diff, min_diff; + uint32_t initialDelayNanoSec; + + /* find combination of prescaler and scaler resulting in the delay closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + /* Initialize prescaler and scaler to their max values to generate the max delay */ + bestPrescaler = 0x3; + bestScaler = 0xF; + bestDelay = (((1000000000U * 4) / srcClock_Hz) * s_delayPrescaler[bestPrescaler] * s_delayScaler[bestScaler]) / 4; + + /* First calculate the initial, default delay */ + initialDelayNanoSec = 1000000000U / srcClock_Hz * 2; + + /* If the initial, default delay is already greater than the desired delay, then + * set the delays to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + DSPI_MasterSetDelayScaler(base, whichCtar, 0, 0, whichDelay); + return initialDelayNanoSec; + } + + /* In all for loops, if min_diff = 0, the exit for loop */ + for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 16) && min_diff; scaler++) + { + realDelay = ((4000000000U / srcClock_Hz) * s_delayPrescaler[prescaler] * s_delayScaler[scaler]) / 4; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = realDelay - delayTimeInNanoSec; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + } + + /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ + DSPI_MasterSetDelayScaler(base, whichCtar, bestPrescaler, bestScaler, whichDelay); + + /* return the actual calculated baud rate */ + return bestDelay; +} + +void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) +{ + command->isPcsContinuous = false; + command->whichCtar = kDSPI_Ctar0; + command->whichPcs = kDSPI_Pcs0; + command->isEndOfQueue = false; + command->clearTransferCount = false; +} + +void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR = data; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR_SLAVE = data; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) +{ + if (mask & SPI_RSER_TFFF_RE_MASK) + { + base->RSER &= ~SPI_RSER_TFFF_DIRS_MASK; + } + if (mask & SPI_RSER_RFDF_RE_MASK) + { + base->RSER &= ~SPI_RSER_RFDF_DIRS_MASK; + } + base->RSER |= mask; +} + +/*Transactional APIs -- Master*/ + +void DSPI_MasterTransferCreateHandle(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + g_dspiHandle[DSPI_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; +} + +status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) +{ + assert(transfer); + + uint16_t wordToSend = 0; + uint16_t wordReceived = 0; + uint8_t dummyData = DSPI_MASTER_DUMMY_DATA; + uint8_t bitsPerFrame; + + uint32_t command; + uint32_t lastCommand; + + uint8_t *txData; + uint8_t *rxData; + uint32_t remainingSendByteCount; + uint32_t remainingReceiveByteCount; + + uint32_t fifoSize; + dspi_command_data_config_t commandStruct; + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + DSPI_StopTransfer(base); + DSPI_DisableInterrupts(base, kDSPI_AllInterruptEnable); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + /*Calculate the command and lastCommand*/ + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + + command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + /*Calculate the bitsPerFrame*/ + bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + txData = transfer->txData; + rxData = transfer->rxData; + remainingSendByteCount = transfer->dataSize; + remainingReceiveByteCount = transfer->dataSize; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + fifoSize = 1; + } + else + { + fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + + DSPI_StartTransfer(base); + + if (bitsPerFrame <= 8) + { + while (remainingSendByteCount > 0) + { + if (remainingSendByteCount == 1) + { + while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + base->PUSHR = (*txData) | (lastCommand); + txData++; + } + else + { + base->PUSHR = (lastCommand) | (dummyData); + } + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + remainingSendByteCount--; + + while (remainingReceiveByteCount > 0) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + /* Read data from POPR*/ + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + else + { + /*Wait until Tx Fifo is not full*/ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + if (txData != NULL) + { + base->PUSHR = command | (uint16_t)(*txData); + txData++; + } + else + { + base->PUSHR = command | dummyData; + } + remainingSendByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + } + else + { + while (remainingSendByteCount > 0) + { + if (remainingSendByteCount <= 2) + { + while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (rxData != NULL) + { + *rxData = wordReceived; + ++rxData; + *rxData = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + wordToSend = *(txData); + ++txData; + + if (remainingSendByteCount > 1) + { + wordToSend |= (unsigned)(*(txData)) << 8U; + ++txData; + } + } + else + { + wordToSend = dummyData; + } + + base->PUSHR = lastCommand | wordToSend; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + remainingSendByteCount = 0; + + while (remainingReceiveByteCount > 0) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (remainingReceiveByteCount != 1) + { + if (rxData != NULL) + { + *(rxData) = wordReceived; + ++rxData; + *(rxData) = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + } + else + { + if (rxData != NULL) + { + *(rxData) = wordReceived; + ++rxData; + } + remainingReceiveByteCount--; + } + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + else + { + /*Wait until Tx Fifo is not full*/ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + wordToSend = *(txData); + ++txData; + wordToSend |= (unsigned)(*(txData)) << 8U; + ++txData; + } + else + { + wordToSend = dummyData; + } + base->PUSHR = command | wordToSend; + remainingSendByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (rxData != NULL) + { + *rxData = wordReceived; + ++rxData; + *rxData = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + } + + return kStatus_Success; +} + +static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) +{ + dspi_command_data_config_t commandStruct; + + DSPI_StopTransfer(base); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + handle->fifoSize = 1; + } + else + { + handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; +} + +status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + handle->state = kDSPI_Busy; + + DSPI_MasterTransferPrepare(base, handle, transfer); + DSPI_StartTransfer(base); + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + + DSPI_MasterTransferFillUpTxFifo(base, handle); + + /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt + * Since SPI is a synchronous interface, we only need to enable the RX interrupt. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ; + + DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + + return kStatus_Success; +} + +status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->remainingReceiveByteCount; + return kStatus_Success; +} + +static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle) +{ + /* Disable interrupt requests*/ + DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); + + status_t status = 0; + if (handle->state == kDSPI_Error) + { + status = kStatus_DSPI_Error; + } + else + { + status = kStatus_Success; + } + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } + + /* The transfer is complete.*/ + handle->state = kDSPI_Idle; +} + +static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle) +{ + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_MASTER_DUMMY_DATA; + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + /* Fill the fifo until it is full or until the send word count is 0 or until the difference + * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. + * The reason for checking the difference is to ensure we only send as much as the + * RX FIFO can receive. + * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the + * send data, hence the difference between the remainingReceiveByteCount and + * remainingSendByteCount must be divided by 2 to convert this difference into a + * 16-bit (2 byte) value. + */ + while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && + ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) / 2 < handle->fifoSize)) + { + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->remainingSendByteCount == 1) + { + wordToSend = *(handle->txData); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = dummyData; + } + handle->remainingSendByteCount = 0; + base->PUSHR = handle->lastCommand | wordToSend; + } + /* For all words except the last word */ + else + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* increment to next data byte */ + } + else + { + wordToSend = dummyData; + } + handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ + base->PUSHR = handle->command | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* exit loop if send count is zero, else update local variables for next loop */ + if (handle->remainingSendByteCount == 0) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + /* Optimized for bits/frame less than or equal to one byte. */ + else + { + /* Fill the fifo until it is full or until the send word count is 0 or until the difference + * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. + * The reason for checking the difference is to ensure we only send as much as the + * RX FIFO can receive. + */ + while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && + ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) < handle->fifoSize)) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + base->PUSHR = handle->lastCommand | wordToSend; + } + else + { + base->PUSHR = handle->command | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + --handle->remainingSendByteCount; + + /* exit loop if send count is zero, else update local variables for next loop */ + if (handle->remainingSendByteCount == 0) + { + break; + } + } + } +} + +void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) +{ + DSPI_StopTransfer(base); + + /* Disable interrupt requests*/ + DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); + + handle->state = kDSPI_Idle; +} + +void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) +{ + /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */ + if (handle->remainingReceiveByteCount) + { + /* Check read buffer.*/ + uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */ + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + /* clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* Store read bytes into rx buffer only if a buffer pointer was provided */ + if (handle->rxData) + { + /* For the last word received, if there is an extra byte due to the odd transfer + * byte count, only save the the last byte and discard the upper byte + */ + if (handle->remainingReceiveByteCount == 1) + { + *handle->rxData = wordReceived; /* Write first data byte */ + --handle->remainingReceiveByteCount; + } + else + { + *handle->rxData = wordReceived; /* Write first data byte */ + ++handle->rxData; /* increment to next data byte */ + *handle->rxData = wordReceived >> 8; /* Write second data byte */ + ++handle->rxData; /* increment to next data byte */ + handle->remainingReceiveByteCount -= 2; + } + } + else + { + if (handle->remainingReceiveByteCount == 1) + { + --handle->remainingReceiveByteCount; + } + else + { + handle->remainingReceiveByteCount -= 2; + } + } + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } /* End of RX FIFO drain while loop */ + } + /* Optimized for bits/frame less than or equal to one byte. */ + else + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + /* clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* Store read bytes into rx buffer only if a buffer pointer was provided */ + if (handle->rxData) + { + *handle->rxData = wordReceived; + ++handle->rxData; + } + + --handle->remainingReceiveByteCount; + + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } /* End of RX FIFO drain while loop */ + } + } + + /* Check write buffer. We always have to send a word in order to keep the transfer + * moving. So if the caller didn't provide a send buffer, we just send a zero. + */ + if (handle->remainingSendByteCount) + { + DSPI_MasterTransferFillUpTxFifo(base, handle); + } + + /* Check if we're done with this transfer.*/ + if ((handle->remainingSendByteCount == 0) && (handle->remainingReceiveByteCount == 0)) + { + /* Complete the transfer and disable the interrupts */ + DSPI_MasterTransferComplete(base, handle); + } +} + +/*Transactional APIs -- Slave*/ +void DSPI_SlaveTransferCreateHandle(SPI_Type *base, + dspi_slave_handle_t *handle, + dspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + g_dspiHandle[DSPI_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; +} + +status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If receive length is zero */ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + handle->state = kDSPI_Busy; + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + + /* Store transfer information */ + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->errorCount = 0; + + uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; + handle->bitsPerFrame = + (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; + + DSPI_StopTransfer(base); + + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + DSPI_StartTransfer(base); + + /* Prepare data to transmit */ + DSPI_SlaveTransferFillUpTxFifo(base, handle); + + s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ; + + /* Enable RX FIFO drain request, the slave only use this interrupt */ + DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + + if (handle->rxData) + { + /* RX FIFO overflow request enable */ + DSPI_EnableInterrupts(base, kDSPI_RxFifoOverflowInterruptEnable); + } + if (handle->txData) + { + /* TX FIFO underflow request enable */ + DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable); + } + + return kStatus_Success; +} + +status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->remainingReceiveByteCount; + return kStatus_Success; +} + +static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle) +{ + uint16_t transmitData = 0; + uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA; + + /* Service the transmitter, if transmit buffer provided, transmit the data, + * else transmit dummy pattern + */ + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + /* Transmit data */ + if (handle->remainingSendByteCount > 0) + { + /* Have data to transmit, update the transmit data and push to FIFO */ + if (handle->bitsPerFrame <= 8) + { + /* bits/frame is 1 byte */ + if (handle->txData) + { + /* Update transmit data and transmit pointer */ + transmitData = *handle->txData; + handle->txData++; + } + else + { + transmitData = dummyPattern; + } + + /* Decrease remaining dataSize */ + --handle->remainingSendByteCount; + } + /* bits/frame is 2 bytes */ + else + { + /* With multibytes per frame transmission, the transmit frame contains data from + * transmit buffer until sent dataSize matches user request. Other bytes will set to + * dummy pattern value. + */ + if (handle->txData) + { + /* Update first byte of transmit data and transmit pointer */ + transmitData = *handle->txData; + handle->txData++; + + if (handle->remainingSendByteCount == 1) + { + /* Decrease remaining dataSize */ + --handle->remainingSendByteCount; + /* Update second byte of transmit data to second byte of dummy pattern */ + transmitData = transmitData | (uint16_t)(((uint16_t)dummyPattern) << 8); + } + else + { + /* Update second byte of transmit data and transmit pointer */ + transmitData = transmitData | (uint16_t)((uint16_t)(*handle->txData) << 8); + handle->txData++; + handle->remainingSendByteCount -= 2; + } + } + else + { + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + } + else + { + handle->remainingSendByteCount -= 2; + } + transmitData = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; + } + } + } + else + { + break; + } + + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = transmitData; + + /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } +} + +static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle) +{ + /* Disable interrupt requests */ + DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | + kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); + + /* The transfer is complete. */ + handle->txData = NULL; + handle->rxData = NULL; + handle->remainingReceiveByteCount = 0; + handle->remainingSendByteCount = 0; + + status_t status = 0; + if (handle->state == kDSPI_Error) + { + status = kStatus_DSPI_Error; + } + else + { + status = kStatus_Success; + } + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } + + handle->state = kDSPI_Idle; +} + +void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) +{ + DSPI_StopTransfer(base); + + /* Disable interrupt requests */ + DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | + kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); + + handle->state = kDSPI_Idle; + handle->remainingSendByteCount = 0; + handle->remainingReceiveByteCount = 0; +} + +void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) +{ + uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA; + uint32_t dataReceived; + uint32_t dataSend = 0; + + /* Because SPI protocol is synchronous, the number of bytes that that slave received from the + * master is the actual number of bytes that the slave transmitted to the master. So we only + * monitor the received dataSize to know when the transfer is complete. + */ + if (handle->remainingReceiveByteCount > 0) + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + /* Have received data in the buffer. */ + dataReceived = base->POPR; + /*Clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* If bits/frame is one byte */ + if (handle->bitsPerFrame <= 8) + { + if (handle->rxData) + { + /* Receive buffer is not null, store data into it */ + *handle->rxData = dataReceived; + ++handle->rxData; + } + /* Descrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + dataSend = *handle->txData; + ++handle->txData; + } + else + { + dataSend = dummyPattern; + } + + --handle->remainingSendByteCount; + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = dataSend; + } + } + else /* If bits/frame is 2 bytes */ + { + /* With multibytes frame receiving, we only receive till the received dataSize + * matches user request. Other bytes will be ignored. + */ + if (handle->rxData) + { + /* Receive buffer is not null, store first byte into it */ + *handle->rxData = dataReceived; + ++handle->rxData; + + if (handle->remainingReceiveByteCount == 1) + { + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + } + else + { + /* Receive buffer is not null, store second byte into it */ + *handle->rxData = dataReceived >> 8; + ++handle->rxData; + handle->remainingReceiveByteCount -= 2; + } + } + /* If no handle->rxData*/ + else + { + if (handle->remainingReceiveByteCount == 1) + { + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + } + else + { + handle->remainingReceiveByteCount -= 2; + } + } + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + dataSend = *handle->txData; + ++handle->txData; + + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + dataSend |= (uint16_t)((uint16_t)(dummyPattern) << 8); + } + else + { + dataSend |= (uint32_t)(*handle->txData) << 8; + ++handle->txData; + handle->remainingSendByteCount -= 2; + } + } + /* If no handle->txData*/ + else + { + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + } + else + { + handle->remainingSendByteCount -= 2; + } + dataSend = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; + } + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = dataSend; + } + } + /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } + } + /* Check if remaining receive byte count matches user request */ + if ((handle->remainingReceiveByteCount == 0) || (handle->state == kDSPI_Error)) + { + /* Other cases, stop the transfer. */ + DSPI_SlaveTransferComplete(base, handle); + return; + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoUnderflowFlag) && (base->RSER & SPI_RSER_TFUF_RE_MASK)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoUnderflowFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kDSPI_Error; + } + handle->errorCount++; + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if ((DSPI_GetStatusFlags(base) & kDSPI_RxFifoOverflowFlag) && (base->RSER & SPI_RSER_RFOF_RE_MASK)) + { + DSPI_ClearStatusFlags(base, kDSPI_RxFifoOverflowFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kDSPI_Error; + } + handle->errorCount++; + } +} + +static void DSPI_CommonIRQHandler(SPI_Type *base, void *param) +{ + if (DSPI_IsMaster(base)) + { + s_dspiMasterIsr(base, (dspi_master_handle_t *)param); + } + else + { + s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param); + } +} + +#if defined(SPI0) +void SPI0_DriverIRQHandler(void) +{ + assert(g_dspiHandle[0]); + DSPI_CommonIRQHandler(SPI0, g_dspiHandle[0]); +} +#endif + +#if defined(SPI1) +void SPI1_DriverIRQHandler(void) +{ + assert(g_dspiHandle[1]); + DSPI_CommonIRQHandler(SPI1, g_dspiHandle[1]); +} +#endif + +#if defined(SPI2) +void SPI2_DriverIRQHandler(void) +{ + assert(g_dspiHandle[2]); + DSPI_CommonIRQHandler(SPI2, g_dspiHandle[2]); +} +#endif + +#if defined(SPI3) +void SPI3_DriverIRQHandler(void) +{ + assert(g_dspiHandle[3]); + DSPI_CommonIRQHandler(SPI3, g_dspiHandle[3]); +} +#endif + +#if defined(SPI4) +void SPI4_DriverIRQHandler(void) +{ + assert(g_dspiHandle[4]); + DSPI_CommonIRQHandler(SPI4, g_dspiHandle[4]); +} +#endif + +#if defined(SPI5) +void SPI5_DriverIRQHandler(void) +{ + assert(g_dspiHandle[5]); + DSPI_CommonIRQHandler(SPI5, g_dspiHandle[5]); +} +#endif + +#if (FSL_FEATURE_SOC_DSPI_COUNT > 6) +#error "Should write the SPIx_DriverIRQHandler function that instance greater than 5 !" +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h new file mode 100755 index 00000000000..93da32fa2f7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h @@ -0,0 +1,1185 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DSPI_H_ +#define _FSL_DSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dspi + * @{ + */ + +/*! @file */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DSPI driver version 2.1.0. */ +#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @name Dummy data */ +/*@{*/ +#define DSPI_MASTER_DUMMY_DATA (0x00U) /*!< Master dummy data used for tx if there is not txData. */ +#define DSPI_SLAVE_DUMMY_DATA (0x00U) /*!< Slave dummy data used for tx if there is not txData. */ +/*@}*/ + +/*! @brief Status for the DSPI driver.*/ +enum _dspi_status +{ + kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/ + kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */ + kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/ + kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out Of range. */ +}; + +/*! @brief DSPI status flags in SPIx_SR register.*/ +enum _dspi_flags +{ + kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ + kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ + kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ + kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ + kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ + kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ + kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ + kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | + SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All status above.*/ +}; + +/*! @brief DSPI interrupt source.*/ +enum _dspi_interrupt_enable +{ + kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ + kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ + kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ + kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ + kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ + kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ + kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | + SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK + /*!< All above interrupts enable.*/ +}; + +/*! @brief DSPI DMA source.*/ +enum _dspi_dma_enable +{ + kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests. + No Tx interrupt request. */ + kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests. + No Rx interrupt request. */ +}; + +/*! @brief DSPI master or slave mode configuration.*/ +typedef enum _dspi_master_slave_mode +{ + kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/ + kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/ +} dspi_master_slave_mode_t; + +/*! + * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid + * only when CPHA bit in CTAR register is 0. + */ +typedef enum _dspi_master_sample_point +{ + kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/ + kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/ + kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/ +} dspi_master_sample_point_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/ +typedef enum _dspi_which_pcs_config +{ + kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */ + kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */ + kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */ + kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */ + kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */ + kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */ +} dspi_which_pcs_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/ +typedef enum _dspi_pcs_polarity_config +{ + kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */ + kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */ +} dspi_pcs_polarity_config_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/ +enum _dspi_pcs_polarity +{ + kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */ + kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */ + kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief DSPI clock polarity configuration for a given CTAR.*/ +typedef enum _dspi_clock_polarity +{ + kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/ + kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/ +} dspi_clock_polarity_t; + +/*! @brief DSPI clock phase configuration for a given CTAR.*/ +typedef enum _dspi_clock_phase +{ + kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} dspi_clock_phase_t; + +/*! @brief DSPI data shifter direction options for a given CTAR.*/ +typedef enum _dspi_shift_direction +{ + kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} dspi_shift_direction_t; + +/*! @brief DSPI delay type selection.*/ +typedef enum _dspi_delay_type +{ + kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */ + kDSPI_LastSckToPcs, /*!< Last SCK edge to Pcs delay. */ + kDSPI_BetweenTransfer /*!< Delay between transfers. */ +} dspi_delay_type_t; + +/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/ +typedef enum _dspi_ctar_selection +{ + kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the + same register address. */ + kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */ + kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. */ + kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. */ + kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. */ + kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. */ + kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. */ + kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. */ +} dspi_ctar_selection_t; + +#define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro , internal used. */ +#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro , internal used. */ +#define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro , internal used. */ +#define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro , internal used. */ +/*! @brief Can use this enumeration for DSPI master transfer configFlags. */ +enum _dspi_transfer_config_flag_for_master +{ + kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ + kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */ + kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */ + kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */ + kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */ + kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */ + kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */ + kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */ + + kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */ + kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */ + kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/ + kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */ + kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ + kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ + + kDSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous. */ + kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/ +}; + +#define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro , internal used. */ +#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro , internal used. */ +/*! @brief Can use this enum for DSPI slave transfer configFlags. */ +enum _dspi_transfer_config_flag_for_slave +{ + kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */ + /*!< DSPI slave can only use PCS0. */ +}; + +/*! @brief DSPI transfer state, which is used for DSPI transactional APIs' state machine. */ +enum _dspi_transfer_state +{ + kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kDSPI_Busy, /*!< Transfer queue is not finished. */ + kDSPI_Error /*!< Transfer error. */ +}; + +/*! @brief DSPI master command date configuration used for SPIx_PUSHR.*/ +typedef struct _dspi_command_data_config +{ + bool isPcsContinuous; /*!< Option to enable the continuous assertion of chip select between transfers.*/ + dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes + Register (CTAR) to use for CTAS.*/ + dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ + bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/ + bool clearTransferCount; /*!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts.*/ +} dspi_command_data_config_t; + +/*! @brief DSPI master ctar configuration structure.*/ +typedef struct _dspi_master_ctar_config +{ + uint32_t baudRate; /*!< Baud Rate for DSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ + dspi_clock_polarity_t cpol; /*!< Clock polarity. */ + dspi_clock_phase_t cpha; /*!< Clock phase. */ + dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum + delay. It sets the boundary value if out of range that can be set.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the + minimum delay.It sets the boundary value if out of range that can be + set.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum + delay.It sets the boundary value if out of range that can be set.*/ +} dspi_master_ctar_config_t; + +/*! @brief DSPI master configuration structure.*/ +typedef struct _dspi_master_config +{ + dspi_ctar_selection_t whichCtar; /*!< Desired CTAR to use. */ + dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ + + dspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs). */ + dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low. */ + + bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only + supported for CPHA = 1.*/ + bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming + data is ignored, the data from the transfer that generated the overflow + is either ignored. ROOE = 1, the incoming data is shifted in to the + shift to the shift register. */ + + bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if it's true.*/ + dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer + Format. It's valid only when CPHA=0. */ +} dspi_master_config_t; + +/*! @brief DSPI slave ctar configuration structure.*/ +typedef struct _dspi_slave_ctar_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ + dspi_clock_polarity_t cpol; /*!< Clock polarity. */ + dspi_clock_phase_t cpha; /*!< Clock phase. */ + /*!< Slave only supports MSB , does not support LSB.*/ +} dspi_slave_ctar_config_t; + +/*! @brief DSPI slave configuration structure.*/ +typedef struct _dspi_slave_config +{ + dspi_ctar_selection_t whichCtar; /*!< Desired CTAR to use. */ + dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ + + bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only + supported for CPHA = 1.*/ + bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming + data is ignored, the data from the transfer that generated the overflow + is either ignored. ROOE = 1, the incoming data is shifted in to the + shift to the shift register. */ + bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if it's true.*/ + dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer + Format. It's valid only when CPHA=0. */ +} dspi_slave_config_t; + +/*! +* @brief Forward declaration of the _dspi_master_handle typedefs. +*/ +typedef struct _dspi_master_handle dspi_master_handle_t; + +/*! +* @brief Forward declaration of the _dspi_slave_handle typedefs. +*/ +typedef struct _dspi_slave_handle dspi_slave_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral address. + * @param handle Pointer to the handle for the DSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base, + dspi_master_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral address. + * @param handle Pointer to the handle for the DSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base, + dspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief DSPI master/slave transfer structure.*/ +typedef struct _dspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t + configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the + transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer + is used for slave.*/ +} dspi_transfer_t; + +/*! @brief DSPI master transfer handle structure used for transactional API. */ +struct _dspi_master_handle +{ + uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */ + volatile uint32_t command; /*!< Desired data command. */ + volatile uint32_t lastCommand; /*!< Desired last data command. */ + + uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/ + volatile bool isThereExtraByte; /*!< Is there extra byte.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ + + dspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief DSPI slave transfer handle structure used for transactional API. */ +struct _dspi_slave_handle +{ + uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */ + volatile bool isThereExtraByte; /*!< Is there extra byte.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< DSPI transfer state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + dspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the DSPI master. + * + * This function initializes the DSPI master configuration. An example use case is as follows: + * @code + * dspi_master_config_t masterConfig; + * masterConfig.whichCtar = kDSPI_Ctar0; + * masterConfig.ctarConfig.baudRate = 500000000; + * masterConfig.ctarConfig.bitsPerFrame = 8; + * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; + * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ; + * masterConfig.whichPcs = kDSPI_Pcs0; + * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; + * masterConfig.enableContinuousSCK = false; + * masterConfig.enableRxFifoOverWrite = false; + * masterConfig.enableModifiedTimingFormat = false; + * masterConfig.samplePoint = kDSPI_SckToSin0Clock; + * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); + * @endcode + * + * @param base DSPI peripheral address. + * @param masterConfig Pointer to structure dspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the dspi_master_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). + * User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure + * before calling DSPI_MasterInit(). + * Example: + * @code + * dspi_master_config_t masterConfig; + * DSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to dspi_master_config_t structure + */ +void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig); + +/*! + * @brief DSPI slave configuration. + * + * This function initializes the DSPI slave configuration. An example use case is as follows: + * @code + * dspi_slave_config_t slaveConfig; + * slaveConfig->whichCtar = kDSPI_Ctar0; + * slaveConfig->ctarConfig.bitsPerFrame = 8; + * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * slaveConfig->enableContinuousSCK = false; + * slaveConfig->enableRxFifoOverWrite = false; + * slaveConfig->enableModifiedTimingFormat = false; + * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; + * DSPI_SlaveInit(base, &slaveConfig); + * @endcode + * + * @param base DSPI peripheral address. + * @param slaveConfig Pointer to structure dspi_master_config_t. + */ +void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the dspi_slave_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). + * User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure + * before calling DSPI_SlaveInit(). + * Example: + * @code + * dspi_slave_config_t slaveConfig; + * DSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to dspi_slave_config_t structure. + */ +void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. + * @param base DSPI peripheral address. + */ +void DSPI_Deinit(SPI_Type *base); + +/*! + * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. + * + * @param base DSPI peripheral address. + * @param enable pass true to enable module, false to disable module. + */ +static inline void DSPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~SPI_MCR_MDIS_MASK; + } + else + { + base->MCR |= SPI_MCR_MDIS_MASK; + } +} + +/*! + *@} +*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the DSPI status flag state. + * @param base DSPI peripheral address. + * @return The DSPI status(in SR register). + */ +static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Clears the DSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The + * function uses these bit positions in its algorithm to clear the desired flag state. + * Example usage: + * @code + * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag); + * @endcode + * + * @param base DSPI peripheral address. + * @param statusFlags The status flag , used from type dspi_flags. + */ +static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} +*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the DSPI interrupts. + * + * This function configures the various interrupt masks of the DSPI. The parameters are base and an interrupt mask. + * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. + * + * @code + * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable. + */ +void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the DSPI interrupts. + * + * @code + * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable. + */ +static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! + *@} +*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask. + * @code + * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask can use the enum dspi_dma_enable. + */ +static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask) +{ + base->RSER |= mask; +} + +/*! + * @brief Disables the DSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask can use the enum dspi_dma_enable. + */ +static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! + * @brief Gets the DSPI master PUSHR data register address for the DMA operation. + * + * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI master PUSHR data register address. + */ +static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->PUSHR); +} + +/*! + * @brief Gets the DSPI slave PUSHR data register address for the DMA operation. + * + * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI slave PUSHR data register address. + */ +static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->PUSHR_SLAVE); +} + +/*! + * @brief Gets the DSPI POPR data register address for the DMA operation. + * + * This function gets the DSPI POPR data register address as this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI POPR data register address. + */ +static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->POPR); +} + +/*! + *@} +*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the DSPI for master or slave. + * + * @param base DSPI peripheral address. + * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. + */ +static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode) +{ + base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode); +} + +/*! + * @brief Returns whether the DSPI module is in master mode. + * + * @param base DSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool DSPI_IsMaster(SPI_Type *base) +{ + return (bool)((base->MCR) & SPI_MCR_MSTR_MASK); +} +/*! + * @brief Starts the DSPI transfers and clears HALT bit in MCR. + * + * This function sets the module to begin data transfer in either master or slave mode. + * + * @param base DSPI peripheral address. + */ +static inline void DSPI_StartTransfer(SPI_Type *base) +{ + base->MCR &= ~SPI_MCR_HALT_MASK; +} +/*! + * @brief Stops (halts) DSPI transfers and sets HALT bit in MCR. + * + * This function stops data transfers in either master or slave mode. + * + * @param base DSPI peripheral address. + */ +static inline void DSPI_StopTransfer(SPI_Type *base) +{ + base->MCR |= SPI_MCR_HALT_MASK; +} + +/*! + * @brief Enables (or disables) the DSPI FIFOs. + * + * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently). + * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration. To enable, + * the caller must pass in a logic 1 (true). + * + * @param base DSPI peripheral address. + * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO + * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO + */ +static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo) +{ + base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) | + SPI_MCR_DIS_RXF(!enableRxFifo); +} + +/*! + * @brief Flushes the DSPI FIFOs. + * + * @param base DSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO + */ +static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) | + SPI_MCR_CLR_RXF(flushRxFifo); +} + +/*! + * @brief Configures the DSPI peripheral chip select polarity simultaneously. + * For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of + * PCSs is specific to the device. + * @code + * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow); + @endcode + * @param base DSPI peripheral address. + * @param mask The PCS polarity mask , can use the enum _dspi_pcs_polarity. + */ +static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask) +{ + base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask); +} + +/*! + * @brief Sets the DSPI baud rate in bits per second. + * + * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without + * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the + * caller also provide the frequency of the module source clock (in Hertz). + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t + * @param baudRate_Bps The desired baud rate in bits per second + * @param srcClock_Hz Module source input clock in Hertz + * @return The actual calculated baud rate + */ +uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz); + +/*! + * @brief Manually configures the delay prescaler and scaler for a particular CTAR. + * + * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar + * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT). + * + * These delay names are available in type dspi_delay_type_t. + * + * The user passes the delay to configure along with the prescaler and scaler value. + * This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply + * wish to manually increment either value. + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). + * @param scaler The scaler delay value (can be any integer between 0 to 15). + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + */ +void DSPI_MasterSetDelayScaler( + SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. + * + * This function calculates the values for: + * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or + * After SCK delay pre-scalar (PASC) and scalar (ASC), or + * Delay after transfer pre-scalar (PDT)and scalar (DT). + * + * These delay names are available in type dspi_delay_type_t. + * + * The user passes which delay they want to configure along with the desired delay value in nanoseconds. The function + * calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact + * delay match may not be possible. In this case, the closest match is calculated without going below the desired + * delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum + * supported delay is returned. The higher level peripheral driver alerts the user of an out of range delay + * input. + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + * @param srcClock_Hz Module source input clock in Hertz + * @param delayTimeInNanoSec The desired delay value in nanoseconds. + * @return The actual calculated delay value. + */ +uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, + uint32_t srcClock_Hz, + uint32_t delayTimeInNanoSec); + +/*! + * @brief Writes data into the data buffer for master mode. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example: + * @code + * dspi_command_data_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs0; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteData(base, &commandConfig, dataWord); + @endcode + * + * @param base DSPI peripheral address. + * @param command Pointer to command structure. + * @param data The data word to be sent. + */ +static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) +{ + base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); +} + +/*! + * @brief Sets the dspi_command_data_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). + * User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure + * before calling DSPI_MasterWrite_xx(). + * Example: + * @code + * dspi_command_data_config_t command; + * DSPI_GetDefaultDataCommandConfig(&command); + * @endcode + * @param command pointer to dspi_command_data_config_t structure. + */ +void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command); + +/*! + * @brief Writes data into the data buffer master mode and waits till complete to return. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example: + * @code + * dspi_command_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs1; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); + * @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, + * receive data is available when transmit completes. + * + * @param base DSPI peripheral address. + * @param command Pointer to command structure. + * @param data The data word to be sent. + */ +void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data); + +/*! + * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. + * + * This function allows the caller to pass in the data command structure and returns the command word formatted + * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the + * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or + * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps + * improve performance in cases where the command structure is constant. For example, the user calls this function + * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR + * this formatted command word with the desired data to transmit. This process increases transmit performance when + * compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a + * data word is to be sent. + * + * @param command Pointer to command structure. + * @return The command word formatted to the PUSHR data register bit field. + */ +static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command) +{ + /* Format the 16-bit command word according to the PUSHR data register bit field*/ + return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount)); +} + +/*! + * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data + * buffer, master mode and waits till complete to return. + * + * In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word + * as the data to send. + * The command portion provides characteristics of the data such as the optional continuous chip select operation +* between + * transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS + * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the + * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for + * appending this command with the data to send. This is an example: + * @code + * dataWord = <16-bit command> | <16-bit data>; + * DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord); + * @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). + * Because the SPI is a synchronous protocol, the receive data is available when transmit completes. + * + * For a blocking polling transfer, see methods below. + * Option 1: +* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); +* uint32_t data0 = command_to_send | data_need_to_send_0; +* uint32_t data1 = command_to_send | data_need_to_send_1; +* uint32_t data2 = command_to_send | data_need_to_send_2; +* +* DSPI_MasterWriteCommandDataBlocking(base,data0); +* DSPI_MasterWriteCommandDataBlocking(base,data1); +* DSPI_MasterWriteCommandDataBlocking(base,data2); +* +* Option 2: +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); +* + * @param base DSPI peripheral address. + * @param data The data word (command and data combined) to be sent + */ +void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data); + +/*! + * @brief Writes data into the data buffer in slave mode. + * + * In slave mode, up to 16-bit words may be written. + * + * @param base DSPI peripheral address. + * @param data The data to send. + */ +static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data) +{ + base->PUSHR_SLAVE = data; +} + +/*! + * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. + * + * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data + * into data register, and finally waits until the data is transmitted. + * + * @param base DSPI peripheral address. + * @param data The data to send. + */ +void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data); + +/*! + * @brief Reads data from the data buffer. + * + * @param base DSPI peripheral address. + * @return The data from the read data buffer. + */ +static inline uint32_t DSPI_ReadData(SPI_Type *base) +{ + return (base->POPR); +} + +/*! + *@} +*/ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the DSPI master handle. + * + * This function initializes the DSPI handle which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * @param base DSPI peripheral base address. + * @param handle DSPI handle pointer to dspi_master_handle_t. + * @param callback dspi callback. + * @param userData callback function parameter. + */ +void DSPI_MasterTransferCreateHandle(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief DSPI master transfer data using polling. + * + * This function transfers data with polling. This is a blocking function, which does not return until all transfers + * have been + * completed. + * + * @param base DSPI peripheral base address. + * @param transfer pointer to dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); + +/*! + * @brief DSPI master transfer data using interrupts. + * + * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all + data + * have been transferred, the callback function is called. + + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count); + +/*! + * @brief DSPI master aborts transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + */ +void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + */ +void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Initializes the DSPI slave handle. + * + * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * @param handle DSPI handle pointer to dspi_slave_handle_t. + * @param base DSPI peripheral base address. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void DSPI_SlaveTransferCreateHandle(SPI_Type *base, + dspi_slave_handle_t *handle, + dspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief DSPI slave transfers data using an interrupt. + * + * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all + * data + * have been transferred, the callback function is called. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief DSPI slave aborts a transfer using an interrupt. + * + * This function aborts transfer using an interrupt. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state. + */ +void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state. + */ +void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + *@} +*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + /*! + *@} + */ + +#endif /*_FSL_DSPI_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c new file mode 100755 index 00000000000..4d9e129ff24 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c @@ -0,0 +1,1262 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_dspi_edma.h" + +/*********************************************************************************************************************** +* Definitons +***********************************************************************************************************************/ + +/*! +* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. +*/ +typedef struct _dspi_master_edma_private_handle +{ + SPI_Type *base; /*!< DSPI peripheral base address. */ + dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ +} dspi_master_edma_private_handle_t; + +/*! +* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. +*/ +typedef struct _dspi_slave_edma_private_handle +{ + SPI_Type *base; /*!< DSPI peripheral base address. */ + dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ +} dspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** +* Prototypes +***********************************************************************************************************************/ +/*! +* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA. +* This is not a public API as it is called from other driver functions. +*/ +static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! +* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA. +* This is not a public API as it is called from other driver functions. +*/ +static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); +/*! +* @brief Get instance number for DSPI module. +* +* This is not a public API and it's extern from fsl_dspi.c. +* +* @param base DSPI peripheral base address +*/ +extern uint32_t DSPI_GetInstance(SPI_Type *base); + +/*********************************************************************************************************************** +* Variables +***********************************************************************************************************************/ + +/*! @brief Pointers to dspi edma handles for each instance. */ +static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; +static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; + +/*********************************************************************************************************************** +* Code +***********************************************************************************************************************/ + +void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, + dspi_master_edma_handle_t *handle, + dspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToIntermediaryHandle, + edma_handle_t *edmaIntermediaryToTxRegHandle) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = DSPI_GetInstance(base); + + s_dspiMasterEdmaPrivateHandle[instance].base = base; + s_dspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle; + handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle; +} + +status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + uint32_t instance = DSPI_GetInstance(base); + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_MASTER_DUMMY_DATA; + uint8_t dataAlreadyFed = 0; + uint8_t dataFedMax = 2; + + uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); + uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base); + + edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); + + edma_transfer_config_t transferConfigA; + edma_transfer_config_t transferConfigB; + edma_transfer_config_t transferConfigC; + + handle->txBuffIfNull = ((uint32_t)DSPI_MASTER_DUMMY_DATA << 8) | DSPI_MASTER_DUMMY_DATA; + + handle->state = kDSPI_Busy; + + dspi_command_data_config_t commandStruct; + DSPI_StopTransfer(base); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + handle->fifoSize = 1; + } + else + { + handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + /* this limits the amount of data we can transfer due to the linked channel. + * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame + */ + if (handle->bitsPerFrame > 8) + { + if (transfer->dataSize > 1022) + { + return kStatus_DSPI_OutOfRange; + } + } + else + { + if (transfer->dataSize > 511) + { + return kStatus_DSPI_OutOfRange; + } + } + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback, + &s_dspiMasterEdmaPrivateHandle[instance]); + + handle->isThereExtraByte = false; + if (handle->bitsPerFrame > 8) + { + if (handle->remainingSendByteCount % 2 == 1) + { + handle->remainingSendByteCount++; + handle->remainingReceiveByteCount--; + handle->isThereExtraByte = true; + } + } + + /*If dspi has separate dma request , prepare the first data in "intermediary" . + else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to + * trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel + */ + + /*Prepare the firt data*/ + if (handle->bitsPerFrame > 8) + { + /* If it's the last word */ + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->isThereExtraByte) + { + wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else /* For all words except the last word , frame > 8bits */ + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* increment to next data byte */ + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->command = (handle->command & 0xffff0000U) | wordToSend; + } + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data word*/ + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else + { + handle->command = (handle->command & 0xffff0000U) | wordToSend; + } + } + } + + else /*dspi has shared dma request*/ + + { + /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->isThereExtraByte) + { + wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + ; + } + handle->remainingSendByteCount = 0; + base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + /* For all words except the last word */ + else + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + ; + } + handle->remainingSendByteCount -= 2; + base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + dataAlreadyFed += 2; + + /* exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else + { + base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + --handle->remainingSendByteCount; + + dataAlreadyFed++; + + /* exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + } + + /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + transferConfigA.srcAddr = (uint32_t)rxAddr; + transferConfigA.srcOffset = 0; + + if (handle->rxData) + { + transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigA.destOffset = 1; + } + else + { + transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigA.destOffset = 0; + } + + transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigA.minorLoopBytes = 1; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; + } + else + { + transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigA.minorLoopBytes = 2; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; + } + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigA, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + + /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should + write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the + SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ + EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + transferConfigB.srcAddr = (uint32_t)(handle->txData); + transferConfigB.srcOffset = 1; + } + else + { + transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigB.srcOffset = 0; + } + + transferConfigB.destAddr = (uint32_t)(&handle->command); + transferConfigB.destOffset = 0; + + transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigB.minorLoopBytes = 1; + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*already prepared the first data in "intermediary" , so minus 1 */ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1; + } + else + { + /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is + majorlink , the majorlink would not trigger the channel_C*/ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1; + } + } + else + { + transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigB.minorLoopBytes = 2; + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*already prepared the first data in "intermediary" , so minus 1 */ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + else + { + /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is + * majorlink*/ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1; + } + } + + EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL); + } + + /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to + handle the last data */ + EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); + + if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || + ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) && + (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) + { + if (handle->txData) + { + uint32_t bufferIndex = 0; + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->bitsPerFrame <= 8) + { + bufferIndex = handle->remainingSendByteCount - 1; + } + else + { + bufferIndex = handle->remainingSendByteCount - 2; + } + } + else + { + bufferIndex = handle->remainingSendByteCount; + } + + if (handle->bitsPerFrame <= 8) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1]; + } + else + { + if (handle->isThereExtraByte) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 2] | + ((uint32_t)dummyData << 8); + } + else + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | + ((uint32_t)handle->txData[bufferIndex - 1] << 8) | + handle->txData[bufferIndex - 2]; + } + } + } + else + { + if (handle->bitsPerFrame <= 8) + { + wordToSend = dummyData; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + } + + if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) || + ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0))) + { + transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand); + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + transferConfigC.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL); + } + + if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) + { + transferConfigC.srcAddr = (uint32_t)(&(handle->command)); + transferConfigC.destAddr = (uint32_t)txAddr; + + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + + if (handle->bitsPerFrame <= 8) + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1; + } + else + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD); + EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, false); + } + else + { + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL); + } + + /*Start the EDMA channel_A , channel_B , channel_C transfer*/ + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle); + EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); + + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel; + uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; + uint8_t t = 0; + if (channelPriorityLow > channelPriorityMid) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityMid; + channelPriorityMid = t; + } + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + if (channelPriorityMid > channelPriorityHigh) + { + t = channelPriorityMid; + channelPriorityMid = channelPriorityHigh; + channelPriorityHigh = t; + } + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityMid; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + } + else + { + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityMid; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + } + + /*Set the channel link. + For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C. + For DSPI instances with separate RX and TX DMA requests: + Rx DMA request -> channel_A + Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary" before the DMA + transfer and then channel_B is used to prepare the next data to "intermediary" ) */ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB + to prepare the next 32bits data (User_send_buffer to handle->command) */ + if (handle->remainingSendByteCount > 1) + { + EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink, + handle->edmaTxDataToIntermediaryHandle->channel); + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + } + else + { + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel); + + if (handle->isThereExtraByte) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorLink, handle->edmaTxDataToIntermediaryHandle->channel); + } + + EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink, + handle->edmaIntermediaryToTxRegHandle->channel); + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable); + } + + DSPI_StartTransfer(base); + + return kStatus_Success; +} + +static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle; + + dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle; + + uint32_t dataReceived; + + DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + if (dspiEdmaPrivateHandle->handle->isThereExtraByte) + { + while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK)) + { + } + dataReceived = (dspiEdmaPrivateHandle->base)->POPR; + if (dspiEdmaPrivateHandle->handle->rxData) + { + (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived; + } + } + + if (dspiEdmaPrivateHandle->handle->callback) + { + dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, + kStatus_Success, dspiEdmaPrivateHandle->handle->userData); + } + + dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; +} + +void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle) +{ + DSPI_StopTransfer(base); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle); + EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle); + + handle->state = kDSPI_Idle; +} + +status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - bytes; + + return kStatus_Success; +} + +void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, + dspi_slave_edma_handle_t *handle, + dspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = DSPI_GetInstance(base); + + s_dspiSlaveEdmaPrivateHandle[instance].base = base; + s_dspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If send/receive length is zero */ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); + + uint32_t instance = DSPI_GetInstance(base); + uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; + handle->bitsPerFrame = + (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; + + /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer + * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame + */ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->bitsPerFrame > 8) + { + if (transfer->dataSize > 1022) + { + return kStatus_DSPI_OutOfRange; + } + } + else + { + if (transfer->dataSize > 511) + { + return kStatus_DSPI_OutOfRange; + } + } + } + + if ((handle->bitsPerFrame > 8) && (transfer->dataSize < 2)) + { + return kStatus_InvalidArgument; + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]); + + handle->state = kDSPI_Busy; + + /* Store transfer information */ + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->errorCount = 0; + + handle->isThereExtraByte = false; + if (handle->bitsPerFrame > 8) + { + if (handle->remainingSendByteCount % 2 == 1) + { + handle->remainingSendByteCount++; + handle->remainingReceiveByteCount--; + handle->isThereExtraByte = true; + } + } + + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_SLAVE_DUMMY_DATA; + uint8_t dataAlreadyFed = 0; + uint8_t dataFedMax = 2; + + uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); + uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base); + + edma_transfer_config_t transferConfigA; + edma_transfer_config_t transferConfigC; + + DSPI_StopTransfer(base); + + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + DSPI_StartTransfer(base); + + /*if dspi has separate dma request , need not prepare data first . + else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to + slaveGetTxRegister if there is no fifo*/ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* Increment to next data byte */ + if ((handle->remainingSendByteCount == 2) && (handle->isThereExtraByte)) + { + wordToSend |= (unsigned)(dummyData) << 8U; + ++handle->txData; /* Increment to next data byte */ + } + else + { + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* Increment to next data byte */ + } + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ + base->PUSHR_SLAVE = wordToSend; + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + dataAlreadyFed += 2; + + /* Exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + /* Increment to next data word*/ + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + base->PUSHR_SLAVE = wordToSend; + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + /* Decrement remainingSendByteCount*/ + --handle->remainingSendByteCount; + + dataAlreadyFed++; + + /* Exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + } + + /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ + if (handle->remainingReceiveByteCount > 0) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + transferConfigA.srcAddr = (uint32_t)rxAddr; + transferConfigA.srcOffset = 0; + + if (handle->rxData) + { + transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigA.destOffset = 1; + } + else + { + transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigA.destOffset = 0; + } + + transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigA.minorLoopBytes = 1; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; + } + else + { + transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigA.minorLoopBytes = 2; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; + } + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigA, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + } + + if (handle->remainingSendByteCount > 0) + { + /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + /*If there is extra byte , it would use the */ + if (handle->isThereExtraByte) + { + if (handle->txData) + { + handle->txLastData = + handle->txData[handle->remainingSendByteCount - 2] | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8); + } + else + { + handle->txLastData = DSPI_SLAVE_DUMMY_DATA | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8); + } + transferConfigC.srcAddr = (uint32_t)(&(handle->txLastData)); + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + transferConfigC.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL); + } + + /*Set another transferConfigC*/ + if ((handle->isThereExtraByte) && (handle->remainingSendByteCount == 2)) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, NULL); + } + else + { + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.destOffset = 0; + + if (handle->txData) + { + transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0])); + transferConfigC.srcOffset = 1; + } + else + { + transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigC.srcOffset = 0; + if (handle->bitsPerFrame <= 8) + { + handle->txBuffIfNull = DSPI_SLAVE_DUMMY_DATA; + } + else + { + handle->txBuffIfNull = (DSPI_SLAVE_DUMMY_DATA << 8) | DSPI_SLAVE_DUMMY_DATA; + } + } + + transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigC.minorLoopBytes = 1; + transferConfigC.majorLoopCounts = handle->remainingSendByteCount; + } + else + { + transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigC.minorLoopBytes = 2; + if (handle->isThereExtraByte) + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + else + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2; + } + } + + if (handle->isThereExtraByte) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, softwareTCD); + EDMA_EnableAutoStopRequest(handle->edmaTxDataToTxRegHandle->base, + handle->edmaTxDataToTxRegHandle->channel, false); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + } + } + + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel; + uint8_t t = 0; + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &preemption_config_t); + } + else + { + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + } + + /*Set the channel link. + For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C. + For DSPI instances with separate RX and TX DMA requests: + Rx DMA request -> channel_A + Tx DMA request -> channel_C */ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel); + } + DSPI_EnableDMA(base, kDSPI_RxDmaEnable); + } + else + { + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + } + + return kStatus_Success; +} + +static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle; + + dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle; + + uint32_t dataReceived; + + DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + if (dspiEdmaPrivateHandle->handle->isThereExtraByte) + { + while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK)) + { + } + dataReceived = (dspiEdmaPrivateHandle->base)->POPR; + if (dspiEdmaPrivateHandle->handle->rxData) + { + (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived; + } + } + + if (dspiEdmaPrivateHandle->handle->callback) + { + dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, + kStatus_Success, dspiEdmaPrivateHandle->handle->userData); + } + + dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; +} + +void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle) +{ + DSPI_StopTransfer(base); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kDSPI_Idle; +} + +status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - bytes; + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h new file mode 100755 index 00000000000..326b7ee442a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DSPI_EDMA_H_ +#define _FSL_DSPI_EDMA_H_ + +#include "fsl_dspi.h" +#include "fsl_edma.h" +/*! + * @addtogroup dspi_edma_driver + * @{ + */ + +/*! @file */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! +* @brief Forward declaration of the DSPI eDMA master handle typedefs. +*/ +typedef struct _dspi_master_edma_handle dspi_master_edma_handle_t; + +/*! +* @brief Forward declaration of the DSPI eDMA slave handle typedefs. +*/ +typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the handle for the DSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base, + dspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the handle for the DSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base, + dspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief DSPI master eDMA transfer handle structure used for transactional API. */ +struct _dspi_master_edma_handle +{ + uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */ + volatile uint32_t command; /*!< Desired data command. */ + volatile uint32_t lastCommand; /*!< Desired last data command. */ + + uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/ + volatile bool isThereExtraByte; /*!< Is there extra byte.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + + volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ + + dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!TCD[channel].SADDR = tcd->SADDR; + base->TCD[channel].SOFF = tcd->SOFF; + base->TCD[channel].ATTR = tcd->ATTR; + base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; + base->TCD[channel].SLAST = tcd->SLAST; + base->TCD[channel].DADDR = tcd->DADDR; + base->TCD[channel].DOFF = tcd->DOFF; + base->TCD[channel].CITER_ELINKNO = tcd->CITER; + base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; + /* Clear DONE bit first, otherwise ESG cannot be set */ + base->TCD[channel].CSR = 0; + base->TCD[channel].CSR = tcd->CSR; + base->TCD[channel].BITER_ELINKNO = tcd->BITER; +} + +void EDMA_Init(DMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + + uint32_t tmpreg; + + /* Ungate EDMA periphral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = base->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); + base->CR = tmpreg; +} + +void EDMA_Deinit(DMA_Type *base) +{ + /* Gate EDMA periphral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +} + +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + config->enableRoundRobinArbitration = false; + config->enableHaltOnError = true; + config->enableContinuousLinkMode = false; + config->enableDebugMode = false; +} + +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); +} + +void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); +} + +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].NBYTES_MLOFFYES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + base->TCD[channel].NBYTES_MLOFFYES = tmpreg; +} + +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); +} + +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Enable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI |= (0x1U << channel); + } + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Disable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI &= ~(0x1U << channel); + } + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(true); + tcd->BITER = 0U; +} + +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + /* source address */ + tcd->SADDR = config->srcAddr; + /* destination address */ + tcd->DADDR = config->destAddr; + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); + /* Source address signed offset */ + tcd->SOFF = config->srcOffset; + /* Destination address signed offset */ + tcd->DOFF = config->destOffset; + /* Minor byte transfer count */ + tcd->NBYTES = config->minorLoopBytes; + /* Current major iteration count */ + tcd->CITER = config->majorLoopCounts; + /* Starting major iteration count */ + tcd->BITER = config->majorLoopCounts; + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = (uint32_t)nextTcd; + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + } +} + +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint32_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set likned channel */ + tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint32_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; + } +} + +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t nbytes = 0; + uint32_t remainingBytes = 0; + + if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) + { + remainingBytes = 0; + } + else + { + /* Calculate the nbytes */ + if (base->TCD[channel].NBYTES_MLOFFYES & (DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK)) + { + nbytes = (base->TCD[channel].NBYTES_MLOFFYES & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> + DMA_NBYTES_MLOFFYES_NBYTES_SHIFT; + } + else + { + nbytes = + (base->TCD[channel].NBYTES_MLOFFNO & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT; + } + /* Calculate the unfinished bytes */ + if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) + { + remainingBytes = ((base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT) * + nbytes; + } + else + { + remainingBytes = + ((base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT) * + nbytes; + } + } + + return remainingBytes; +} + +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + /* Get ERROR bit flag */ + retval |= (((base->ERR >> channel) & 0x1U) << 1U); + /* Get INT bit flag */ + retval |= (((base->INT >> channel) & 0x1U) << 2U); + + return retval; +} + +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Clear DONE bit flag */ + if (mask & kEDMA_DoneFlag) + { + base->CDNE = channel; + } + /* Clear ERROR bit flag */ + if (mask & kEDMA_ErrorFlag) + { + base->CERR = channel; + } + /* Clear INT bit flag */ + if (mask & kEDMA_InterruptFlag) + { + base->CINT = channel; + } +} + +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t edmaInstance; + uint32_t channelIndex; + edma_tcd_t *tcdRegs; + + handle->base = base; + handle->channel = channel; + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; + s_EDMAHandle[channelIndex] = handle; + /* Enable NVIC interrupt */ + EnableIRQ(s_edmaIRQNumber[channelIndex]); + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0); + + /* Initialize tcd queue attibute. */ + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + handle->tcdSize = tcdSize; + handle->flags = 0; + handle->tcdPool = tcdPool; +} + +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); + assert(srcWidth == 1U || srcWidth == 2U || srcWidth == 4U || srcWidth == 16U || srcWidth == 32U); + assert(destWidth == 1U || destWidth == 2U || destWidth == 4U || destWidth == 16U || destWidth == 32U); + assert(transferBytes % bytesEachRequest == 0); + + config->destAddr = (uint32_t)destAddr; + config->srcAddr = (uint32_t)srcAddr; + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + switch (srcWidth) + { + case 1U: + config->srcTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->srcTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->srcTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->srcTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->srcTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (destWidth) + { + case 1U: + config->destTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->destTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->destTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->destTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->destTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (type) + { + case kEDMA_MemoryToMemory: + config->destOffset = destWidth; + config->srcOffset = srcWidth; + break; + case kEDMA_MemoryToPeripheral: + config->destOffset = 0U; + config->srcOffset = srcWidth; + break; + case kEDMA_PeripheralToMemory: + config->destOffset = destWidth; + config->srcOffset = 0U; + break; + default: + break; + } +} + +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + if (handle->tcdPool == NULL) + { + /* + Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because + if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit + this check mechanism, EDMA_CreatHandle will clear CSR register. + */ + if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); + /* Enable auto disable request feature */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint32_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + if (handle->tcdUsed >= handle->tcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1U; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0U; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Enable scatter/gather also in the TCD registers. */ + csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + link succeed. + */ + if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + { + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; + } +} + +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + handle->flags |= EDMA_TRANSFER_ENABLED_MASK; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & (1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +} + +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +} + +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + handle->base->TCD[handle->channel].CSR = 0; + /* Cancel all next TCD transfer. */ + handle->base->TCD[handle->channel].DLAST_SGA = 0; +} + +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Clear EDMA interrupt flag */ + handle->base->CINT = handle->channel; + if (handle->tcdPool == NULL) + { + (handle->callback)(handle, handle->userData, true, 0); + } + else /* Use the TCD queue. */ + { + uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool transfer_done; + + /* Check if transfer is already finished. */ + transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); + /* Get the offset of the current transfer TCD blcoks. */ + sga -= (uint32_t)handle->tcdPool; + /* Get the index of the current transfer TCD blcoks. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD (current one is already finished) */ + new_header = sga_index; + } + else + { + /* New header shall point to this descriptor (not finished yet) */ + new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == handle->header) + { + if (handle->tcdUsed == handle->tcdSize) + { + tcds_done = handle->tcdUsed; + } + else + { + /* Internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = new_header - handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + } + /* Advance header to the point beyond the last finished TCD block. */ + handle->header = new_header; + /* Release TCD blocks. */ + handle->tcdUsed -= tcds_done; + /* Invoke callback function. */ + if (handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + } +} + +/* 8 channels (Shared): kl28 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U + +void DMA0_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +} + +void DMA0_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +} + +void DMA0_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +} + +void DMA0_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +} +#endif /* 8 channels (Shared) */ + +/* 32 channels (Shared): k80 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_DMA16_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } +} + +void DMA1_DMA17_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } +} + +void DMA2_DMA18_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } +} + +void DMA3_DMA19_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } +} + +void DMA4_DMA20_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } +} + +void DMA5_DMA21_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } +} + +void DMA6_DMA22_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } +} + +void DMA7_DMA23_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } +} + +void DMA8_DMA24_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } +} + +void DMA9_DMA25_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } +} + +void DMA10_DMA26_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } +} + +void DMA11_DMA27_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } +} + +void DMA12_DMA28_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +} + +void DMA13_DMA29_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +} + +void DMA14_DMA30_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +} + +void DMA15_DMA31_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +} +#endif /* 32 channels (Shared) */ + +/* 4 channels (No Shared): kv10 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 + +void DMA0_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[0]); +} + +void DMA1_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[1]); +} + +void DMA2_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[2]); +} + +void DMA3_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[3]); +} + +/* 8 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U + +void DMA4_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[4]); +} + +void DMA5_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[5]); +} + +void DMA6_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[6]); +} + +void DMA7_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[7]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ + +/* 16 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U + +void DMA8_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[8]); +} + +void DMA9_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[9]); +} + +void DMA10_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[10]); +} + +void DMA11_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[11]); +} + +void DMA12_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[12]); +} + +void DMA13_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[13]); +} + +void DMA14_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[14]); +} + +void DMA15_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[15]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ + +/* 32 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U + +void DMA16_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[16]); +} + +void DMA17_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[17]); +} + +void DMA18_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[18]); +} + +void DMA19_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[19]); +} + +void DMA20_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[20]); +} + +void DMA21_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[21]); +} + +void DMA22_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[22]); +} + +void DMA23_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[23]); +} + +void DMA24_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[24]); +} + +void DMA25_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[25]); +} + +void DMA26_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[26]); +} + +void DMA27_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[27]); +} + +void DMA28_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[28]); +} + +void DMA29_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[29]); +} + +void DMA30_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[30]); +} + +void DMA31_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[31]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ + +#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h new file mode 100755 index 00000000000..ca9632e247a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h @@ -0,0 +1,879 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _FSL_EDMA_H_ +#define _FSL_EDMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_driver + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) + +/*! @brief Get the pointer of DCHPRIn */ +#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2G bytes. */ +} edma_modulo_t; + +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief eDMA channel status flags. */ +enum _edma_channel_status_flags +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief eDMA channel error status flags. */ +enum _edma_error_status_flags +{ + kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ + kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ + kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 + kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit will be 0, otherwise be 1 */ +}; + +/*! @brief eDMA interrupt source */ +typedef enum _edma_interrupt_enable +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +} edma_interrupt_enable_t; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA transfer status */ +enum _edma_transfer_status +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority + arbitration is used for channel selection */ + bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of + a new channel. Executing channels are allowed to complete. */ +} edma_config_t; + +/*! + * @brief eDMA transfer configuration + * + * This structure configures the source/destination transfer attribute. + * This figure shows the eDMA's transfer model: + * _________________________________________________ + * | Transfer Size | | + * Minor Loop |_______________| Major loop Count 1 | + * Bytes | Transfer Size | | + * ____________|_______________|____________________|--> Minor loop complete + * ____________________________________ + * | | | + * |_______________| Major Loop Count 2 | + * | | | + * |_______________|____________________|--> Minor loop Complete + * + * ---------------------------------------------------------> Transfer complete + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to + form the next-state value as each source read is completed. */ + int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to + form the next-state value as each destination write is completed. */ + uint16_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ + uint32_t majorLoopCounts; /*!< Major loop iteration count. */ +} edma_transfer_config_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for minor loop mapping. */ +} edma_minor_offset_config_t; + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure scatter/gather feature as a next hardware TCD. + */ +typedef struct _edma_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_tcd_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define Callback function for eDMA. */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + DMA_Type *base; /*!< eDMA peripheral base address. */ + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint8_t channel; /*!< eDMA channel number. */ + volatile int8_t header; /*!< The first TCD index. */ + volatile int8_t tail; /*!< The last TCD index. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ + uint8_t flags; /*!< The status of the current channel. */ +} edma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes eDMA peripheral. + * + * This function ungates the eDMA clock and configure eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config Pointer to configuration structure, see "edma_config_t". + * @note This function enable the minor loop map feature. + */ +void EDMA_Init(DMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(DMA_Type *base); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to a default value. + * The default configuration is set to the following value: + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config Pointer to eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +/*! + * @brief Sets all TCD registers to a default value. + * + * This function sets TCD registers for this channel to default value. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is on-going, + * or it will case unpredicated results. + * @note This function will enable auto stop request feature. + */ +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configure the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if user + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature will be enabled. + * And DREQ bit will be cleared in the previous transfer configuration which + * will be set in eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(DMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * Minor offset means signed-extended value added to source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to Minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config Pointer to channel preemption configuration structure. + */ +static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, + uint32_t channel, + const edma_channel_Preemption_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + DMA_DCHPRIn(base, channel) = + (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | + DMA_DCHPRI0_CHPRI(config->channelPriority)); +} + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures minor link or major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid. + */ +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth Bandwidth setting, it can be one of: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); + +/*! + * @brief Sets the source modulo and destination modulo for eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo Source modulo value. + * @param destModulo Destination modulo value. + */ +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command for enable(ture) or disable(false). + */ +static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); +} +#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command for enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. User need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function will enable auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers. + * STCD is used in scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if user + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned, or it will cause eDMA error. + * @note If nextTcd is not NULL, it means scatter gather feature will be enabled. + * And DREQ bit will be cleared in the previous transfer configuration which + * will be set in EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * Minor offset is a signed-extended value added to the source address or destination + * address after each minor loop. + * + * @param tcd Point to the TCD structure. + * @param config Pointer to Minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted. + * + * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd Point to the TCD structure. + * @param bandWidth Bandwidth setting, it can be one of: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +/*! + * @brief Sets the source modulo and destination modulo for eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd Point to the TCD structure. + * @param srcModulo Source modulo value. + * @param destModulo Destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd Point to the TCD structure. + * @param enable The command for enable(ture) or disable(false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. User need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. User need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SERQ = DMA_SERQ_SERQ(channel); +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CERQ = DMA_CERQ_CERQ(channel); +} + +/*! + * @brief Starts the eDMA transfer by software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SSRT = DMA_SSRT_SSRT(channel); +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the Remaining bytes from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the the number of bytes that have not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Bytes have not been transferred yet for the current TCD. + * @note This function can only be used to get unfinished bytes of transfer without + * the next TCD, or it might be inaccuracy. + */ +uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. User need to use the + * _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) +{ + return base->ES; +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. User need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. User need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using transaction API for eDMA. This function + * initializes the internal state of eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. + * + * @param handle eDMA handle pointer. + * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData Parameter for callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief eDMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stop transfer. + * + * This function disables the channel request to pause the transfer. User can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA abort transfer. + * + * This function disables the channel request and clear transfer status bits. + * User can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA IRQ handler for current major loop transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_EDMA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c new file mode 100755 index 00000000000..c999f7714d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c @@ -0,0 +1,1718 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_enet.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U +/*! @brief Ethernet mac address length. */ +#define ENET_FRAME_MACLEN 6U +/*! @brief Ethernet Frame header length. */ +#define ENET_FRAME_HEADERLEN 14U +/*! @brief Ethernet VLAN header length. */ +#define ENET_FRAME_VLAN_HEADERLEN 18U +/*! @brief MDC frequency. */ +#define ENET_MDC_FREQUENCY 2500000U +/*! @brief NanoSecond in one second. */ +#define ENET_NANOSECOND_ONE_SECOND 1000000000U +/*! @brief Define a common clock cycle delays used for time stamp capture. */ +#define ENET_1588TIME_DELAY_COUNT 10U +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); + +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param config ENET Mac configuration. + * @param bufferConfig ENET buffer configuration. + * @param macAddr ENET six-byte mac address. + * @param srcClock_Hz ENET module clock source, normally it's system clock. + */ +static void ENET_SetMacController(ENET_Type *base, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); + +/*! + * @brief Set ENET MAC transmit buffer descriptors. + * + * @param txBdStartAlign The aligned start address of ENET transmit buffer descriptors. + * is recommended to evenly divisible by 16. + * @param txBuffStartAlign The aligned start address of ENET transmit buffers, must be evenly divisible by 16. + * @param txBuffSizeAlign The aligned ENET transmit buffer size, must be evenly divisible by 16. + * @param txBdNumber The number of ENET transmit buffers. + */ +static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartAlign, + uint8_t *txBuffStartAlign, + uint32_t txBuffSizeAlign, + uint32_t txBdNumber); + +/*! + * @brief Set ENET MAC receive buffer descriptors. + * + * @param rxBdStartAlign The aligned start address of ENET receive buffer descriptors. + * is recommended to evenly divisible by 16. + * @param rxBuffStartAlign The aligned start address of ENET receive buffers, must be evenly divisible by 16. + * @param rxBuffSizeAlign The aligned ENET receive buffer size, must be evenly divisible by 16. + * @param rxBdNumber The number of ENET receive buffers. + * @param enableInterrupt Enable/disables to generate the receive byte and frame interrupt. + * It's used for ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enabled case. + */ +static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign, + uint8_t *rxBuffStartAlign, + uint32_t rxBuffSizeAlign, + uint32_t rxBdNumber, + bool enableInterrupt); + +/*! + * @brief Updates the ENET read buffer descriptors. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + */ +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. + * + * @param data The ENET read data for frame parse. + * @param ptpTsData The ENET PTP message and time-stamp data pointer. + * @param isFastEnabled The fast parse flag. + * - true , Fast processing, only check if this is a PTP message. + * - false, Store the PTP message data after check the PTP message. + */ +static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); + +/*! + * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The new PTP 1588 time-stamp data pointer. + */ +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. + */ +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); + +/*! + * @brief Store the transmit time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + */ +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ptpTimeData The PTP 1588 time-stamp data pointer. + */ +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL}; + +/*! @brief Pointers to enet clocks for each instance. */ +const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT] = ENET_CLOCKS; + +/*! @brief Pointers to enet transmit IRQ number for each instance. */ +const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS; +/*! @brief Pointers to enet receive IRQ number for each instance. */ +const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Pointers to enet timestamp IRQ number for each instance. */ +const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! @brief Pointers to enet error IRQ number for each instance. */ +const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS; + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_ENET_COUNT; instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_ENET_COUNT); + + return instance; +} + +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + assert(config); + + /* Initializes the MAC configure structure to zero. */ + memset(config, 0, sizeof(enet_config_t)); + + /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ + config->miiMode = kENET_RmiiMode; + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + /* Sets the maximum receive frame length. */ + config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +} + +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + /* Checks input parameters. */ + assert(handle); + assert(config); + assert(bufferConfig); + assert(bufferConfig->rxBdStartAddrAlign); + assert(bufferConfig->txBdStartAddrAlign); + assert(bufferConfig->rxBufferAlign); + assert(bufferConfig->txBufferAlign); + assert(macAddr); + assert(bufferConfig->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); + + /* Make sure the buffers should be have the capability of process at least one maximum frame. */ + if (config->macSpecialConfig & kENET_ControlVLANTagEnable) + { + assert(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > ENET_FRAME_MAX_VALNFRAMELEN); + } + else + { + assert(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > ENET_FRAME_MAX_FRAMELEN); + assert(bufferConfig->rxBuffSizeAlign * bufferConfig->rxBdNumber > config->rxMaxFrameLen); + } + + uint32_t instance = ENET_GetInstance(base); + + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_enetClock[instance]); + + /* Reset ENET module. */ + ENET_Reset(base); + + /* Initializes the ENET transmit buffer descriptors. */ + ENET_SetTxBufferDescriptors(bufferConfig->txBdStartAddrAlign, bufferConfig->txBufferAlign, + bufferConfig->txBuffSizeAlign, bufferConfig->txBdNumber); + + /* Initializes the ENET receive buffer descriptors. */ + ENET_SetRxBufferDescriptors(bufferConfig->rxBdStartAddrAlign, bufferConfig->rxBufferAlign, + bufferConfig->rxBuffSizeAlign, bufferConfig->rxBdNumber, + !!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxByteInterrupt))); + + /* Initializes the ENET MAC controller. */ + ENET_SetMacController(base, config, bufferConfig, macAddr, srcClock_Hz); + + /* Initialize the handle to zero. */ + memset(handle, 0, sizeof(enet_handle_t)); + + /* Store transfer parameters in handle pointer. */ + handle->rxBdBase = bufferConfig->rxBdStartAddrAlign; + handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign; + handle->rxBdDirty = bufferConfig->rxBdStartAddrAlign; + handle->txBdBase = bufferConfig->txBdStartAddrAlign; + handle->txBdCurrent = bufferConfig->txBdStartAddrAlign; + handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign; + handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign; + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[instance] = handle; +} + +void ENET_Deinit(ENET_Type *base) +{ + /* Disable interrupt. */ + base->EIMR = 0; + + /* Disable ENET. */ + base->ECR &= ~ENET_ECR_ETHEREN_MASK; + + /* Disables the clock source. */ + CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); +} + +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) +{ + assert(handle); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; +} + +static void ENET_SetMacController(ENET_Type *base, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + uint32_t rcr = 0; + uint32_t tcr = 0; + uint32_t ecr = 0; + uint32_t macSpecialConfig = config->macSpecialConfig; + uint32_t instance = ENET_GetInstance(base); + + /* Configures MAC receive controller with user configure structure. */ + rcr = ENET_RCR_NLC(!!(macSpecialConfig & kENET_ControlRxPayloadCheckEnable)) | + ENET_RCR_CFEN(!!(macSpecialConfig & kENET_ControlFlowControlEnable)) | + ENET_RCR_FCE(!!(macSpecialConfig & kENET_ControlFlowControlEnable)) | + ENET_RCR_PADEN(!!(macSpecialConfig & kENET_ControlRxPadRemoveEnable)) | + ENET_RCR_BC_REJ(!!(macSpecialConfig & kENET_ControlRxBroadCastRejectEnable)) | + ENET_RCR_PROM(!!(macSpecialConfig & kENET_ControlPromiscuousEnable)) | ENET_RCR_MII_MODE(1) | + ENET_RCR_RMII_MODE(config->miiMode) | ENET_RCR_RMII_10T(!config->miiSpeed) | + ENET_RCR_MAX_FL(config->rxMaxFrameLen) | ENET_RCR_CRCFWD(1); + /* Receive setting for half duplex. */ + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT(1); + } + /* Sets internal loop only for MII mode. */ + if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode == kENET_MiiMode)) + { + rcr |= ENET_RCR_LOOP(1); + rcr &= ~ENET_RCR_DRT_MASK; + } + base->RCR = rcr; + + /* Configures MAC transmit controller: duplex mode, mac address insertion. */ + tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); + tcr |= ENET_TCR_FDEN(config->miiDuplex) | ENET_TCR_ADDINS(!!(macSpecialConfig & kENET_ControlMacAddrInsert)); + base->TCR = tcr; + + /* Configures receive and transmit accelerator. */ + base->TACC = config->txAccelerConfig; + base->RACC = config->rxAccelerConfig; + + /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ + if (macSpecialConfig & kENET_ControlFlowControlEnable) + { + uint32_t reemReg; + base->OPD = config->pauseDuration; + reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); +#if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + base->RSEM = reemReg; + } + + /* FIFO threshold setting for store and forward enable/disable case. */ + if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) + { + /* Transmit fifo watermark settings. */ + base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; + /* Receive fifo full threshold settings. */ + base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; + } + else + { + /* Transmit fifo watermark settings. */ + base->TFWR = ENET_TFWR_STRFWD_MASK; + base->RSFL = 0; + } + + /* Enable store and forward when accelerator is enabled */ + if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) + { + base->TFWR = ENET_TFWR_STRFWD_MASK; + } + if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) + { + base->RSFL = 0; + } + + /* Initializes transmit buffer descriptor rings start address, two start address should be aligned. */ + base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; + base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; + /* Initializes the maximum buffer size, the buffer size should be aligned. */ + base->MRBR = bufferConfig->rxBuffSizeAlign; + + /* Configures the Mac address. */ + ENET_SetMacAddr(base, macAddr); + + /* Initialize the SMI if uninitialized. */ + if (!ENET_GetSMI(base)) + { + ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); + } + + /* Enables Ethernet interrupt and NVIC. */ + ENET_EnableInterrupts(base, config->interrupt); + if (config->interrupt & (kENET_RxByteInterrupt | kENET_RxFrameInterrupt)) + { + EnableIRQ(s_enetRxIrqId[instance]); + } + if (config->interrupt & (kENET_TxByteInterrupt | kENET_TxFrameInterrupt)) + { + EnableIRQ(s_enetTxIrqId[instance]); + } + if (config->interrupt & (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_GraceStopInterrupt | kENET_MiiInterrupt | + kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | + kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt | kENET_WakeupInterrupt)) + { + EnableIRQ(s_enetErrIrqId[instance]); + } + + /* ENET control register setting. */ + ecr = base->ECR; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Sets the 1588 enhanced feature. */ + ecr |= ENET_ECR_EN1588_MASK; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Enables Ethernet module after all configuration except the buffer descriptor active. */ + ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; + base->ECR = ecr; +} + +static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartAlign, + uint8_t *txBuffStartAlign, + uint32_t txBuffSizeAlign, + uint32_t txBdNumber) +{ + assert(txBdStartAlign); + assert(txBuffStartAlign); + + uint32_t count; + volatile enet_tx_bd_struct_t *curBuffDescrip = txBdStartAlign; + + for (count = 0; count < txBdNumber; count++) + { + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]); + /* Initializes data length. */ + curBuffDescrip->length = 0; + /* Sets the crc. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == txBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Enable transmit interrupt for store the transmit timestamp. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } +} + +static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign, + uint8_t *rxBuffStartAlign, + uint32_t rxBuffSizeAlign, + uint32_t rxBdNumber, + bool enableInterrupt) +{ + assert(rxBdStartAlign); + assert(rxBuffStartAlign); + + volatile enet_rx_bd_struct_t *curBuffDescrip = rxBdStartAlign; + uint32_t count = 0; + + /* Initializes receive buffer descriptors. */ + for (count = 0; count < rxBdNumber; count++) + { + /* Set data buffer and the length. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffStartAlign[count * rxBuffSizeAlign]); + curBuffDescrip->length = 0; + + /* Initializes the buffer descriptors with empty bit. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == rxBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (enableInterrupt) + { + /* Enable receive interrupt. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK; + } + else + { + curBuffDescrip->controlExtend1 = 0; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } +} + +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t rcr; + uint32_t tcr; + + rcr = base->RCR; + tcr = base->TCR; + + /* Sets speed mode. */ + if (kENET_MiiSpeed10M == speed) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } + else + { + rcr &= ~ENET_RCR_RMII_10T_MASK; + } + /* Set duplex mode. */ + if (duplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + tcr &= ~ENET_TCR_FDEN_MASK; + } + else + { + rcr &= ~ENET_RCR_DRT_MASK; + tcr |= ENET_TCR_FDEN_MASK; + } + + base->RCR = rcr; + base->TCR = tcr; +} + +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + uint32_t address; + + /* Set physical address lower register. */ + address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | + (uint32_t)macAddr[3]); + base->PALR = address; + /* Set physical address high register. */ + address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); + base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; +} + +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + assert(macAddr); + + uint32_t address; + + /* Get from physical address lower register. */ + address = base->PALR; + macAddr[0] = 0xFFU & (address >> 24U); + macAddr[1] = 0xFFU & (address >> 16U); + macAddr[2] = 0xFFU & (address >> 8U); + macAddr[3] = 0xFFU & address; + + /* Get from physical address high register. */ + address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; +} + +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) +{ + assert(srcClock_Hz); + + uint32_t clkCycle = 0; + uint32_t speed = 0; + uint32_t mscr = 0; + + /* Calculate the MII speed which controls the frequency of the MDC. */ + speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); + /* Calculate the hold time on the MDIO output. */ + clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; + /* Build the configuration for MDC/MDIO control. */ + mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_DIS_PRE(isPreambleDisabled) | ENET_MSCR_HOLDTIME(clkCycle); + base->MSCR = mscr; +} + +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | + (data & 0xFFFF); + base->MMFR = mmfr; +} + +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) +{ + uint32_t mmfr = 0; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); + base->MMFR = mmfr; +} + +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(handle->rxBdCurrent); + assert(eErrorStatic); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent); +} + +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) +{ + assert(handle); + assert(handle->rxBdCurrent); + assert(length); + + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent; + + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + *length = 0; + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + *length = 0; + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) +{ + assert(handle); + assert(handle->rxBdCurrent); + + uint32_t len = 0; + uint32_t offset = 0; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip; + status_t result = kStatus_Success; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Get the current buffer descriptor. */ + curBuffDescrip = handle->rxBdCurrent; + /* Increase current buffer descriptor to the next one. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent = handle->rxBdBase; + } + else + { + handle->rxBdCurrent++; + } + + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* Find the last buffer descriptor for the frame*/ + break; + } + } while (handle->rxBdCurrent != handle->rxBdDirty); + + /* Update all receive buffer descriptors for the whole frame. */ + ENET_UpdateReadBuffers(base, handle); + + return result; + } + else + { + /* Frame read from the MAC to user buffer and update the buffer descriptors. + Process the frame, a frame on several receive buffers are considered . */ + /* Get the current buffer descriptor. */ + curBuffDescrip = handle->rxBdCurrent; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(curBuffDescrip->buffer, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* Increase current buffer descriptor to the next one. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent = handle->rxBdBase; + } + else + { + handle->rxBdCurrent++; + } + + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, curBuffDescrip->buffer, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ENET_UpdateReadBuffers(base, handle); + return result; + } + } + else + { + /* Store the fragments of a frame on several buffer descriptors. */ + isLastBuff = false; + memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign); + offset += handle->rxBuffSizeAlign; + if (offset >= length) + { + break; + } + } + + /* Get the current buffer descriptor. */ + curBuffDescrip = handle->rxBdCurrent; + } + /* All error happens will break the while loop and arrive here to update receive buffers. */ + ENET_UpdateReadBuffers(base, handle); + } + return kStatus_ENET_RxFrameFail; +} + +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + do + { + /* Clears status. */ + handle->rxBdDirty->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + /* Sets the receive buffer descriptor with the empty flag. */ + handle->rxBdDirty->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Increases the buffer descriptor to the next one. */ + if (handle->rxBdDirty->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdDirty = handle->rxBdBase; + } + else + { + handle->rxBdDirty++; + } + + /* Actives the receive buffer descriptor. */ + base->RDAR = ENET_RDAR_RDAR_MASK; + + } while (handle->rxBdDirty != handle->rxBdCurrent); +} + +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) +{ + assert(handle); + assert(handle->txBdCurrent); + assert(data); + assert(length <= (ENET_FRAME_MAX_VALNFRAMELEN - 4)); + + volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdCurrent; + uint32_t len = 0; + uint32_t sizeleft = 0; + + /* Check if the transmit buffer is ready. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign >= length) + { + /* Copy data to the buffer for uDMA transfer. */ + memcpy(curBuffDescrip->buffer, data, length); + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent = handle->txBdBase; + } + else + { + handle->txBdCurrent++; + } + + /* Active the transmit buffer descriptor. */ + base->TDAR = ENET_TDAR_TDAR_MASK; + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent = handle->txBdBase; + } + else + { + handle->txBdCurrent++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; + if (sizeleft > handle->txBuffSizeAlign) + { + /* Data copy. */ + memcpy(curBuffDescrip->buffer, data + len, handle->txBuffSizeAlign); + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign; + len += handle->txBuffSizeAlign; + /* Sets the control flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + /* Active the transmit buffer descriptor*/ + base->TDAR = ENET_TDAR_TDAR_MASK; + } + else + { + memcpy(curBuffDescrip->buffer, data + len, sizeleft); + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + /* Active the transmit buffer descriptor. */ + base->TDAR = ENET_TDAR_TDAR_MASK; + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent; + + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameFail; + } +} + +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Enable a multicast group address. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR = 1U << ((crc >> 0x1AU) & 0x1FU); + } + else + { + base->GAUR = 1U << ((crc >> 0x1AU) & 0x1FU); + } +} + +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Set the hash table. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } + else + { + base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(eErrorStatic); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic->control; + controlExt = handle->txBdDirtyStatic->controlExtend0; + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic = handle->txBdBase; + } + else + { + handle->txBdDirtyStatic++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic != handle->txBdCurrent); + + return kStatus_ENET_TxFrameFail; +} + +static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) +{ + assert(data); + if (!isFastEnabled) + { + assert(ptpTsData); + } + + bool isPtpMsg = false; + uint8_t *buffer = data; + uint16_t ptpType; + + /* Check for VLAN frame. */ + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) + { + buffer += (ENET_FRAME_VLAN_HEADERLEN - ENET_FRAME_HEADERLEN); + } + + ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); + switch (ENET_HTONS(ptpType)) + { /* Ethernet layer 2. */ + case ENET_ETHERNETL2: + if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType) + { + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a ptpv2 message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), + kENET_PtpSrcPortIdLen); + } + } + break; + /* IPV4. */ + case ENET_IPV4: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV4 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + /* IPV6. */ + case ENET_IPV6: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV6 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + default: + break; + } + return isPtpMsg; +} + +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) +{ + assert(handle); + assert(ptpConfig); + + uint32_t instance = ENET_GetInstance(base); + + /* Start the 1588 timer. */ + ENET_Ptp1588StartTimer(base, ptpConfig->ptp1588ClockSrc_Hz); + + /* Enables the time stamp interrupt for the master clock on a device. */ + ENET_EnableInterrupts(base, kENET_TsTimerInterrupt); + EnableIRQ(s_enetTsIrqId[instance]); + + /* Enables the transmit interrupt to store the transmit frame time-stamp. */ + ENET_EnableInterrupts(base, kENET_TxFrameInterrupt); + EnableIRQ(s_enetTxIrqId[instance]); + + /* Setting the receive and transmit state for transaction. */ + handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData; + handle->rxPtpTsDataRing.size = ptpConfig->ptpTsRxBuffNum; + handle->rxPtpTsDataRing.front = 0; + handle->rxPtpTsDataRing.end = 0; + handle->txPtpTsDataRing.ptpTsData = ptpConfig->txPtpTsData; + handle->txPtpTsDataRing.size = ptpConfig->ptpTsTxBuffNum; + handle->txPtpTsDataRing.front = 0; + handle->txPtpTsDataRing.end = 0; + handle->msTimerSecond = 0; + handle->txBdDirtyTime = handle->txBdBase; + handle->txBdDirtyStatic = handle->txBdBase; +} + +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) +{ + /* Restart PTP 1588 timer, master clock. */ + base->ATCR = ENET_ATCR_RESTART_MASK; + + /* Initializes PTP 1588 timer. */ + base->ATINC = ENET_ATINC_INC(ENET_NANOSECOND_ONE_SECOND / ptpClkSrc); + base->ATPER = ENET_NANOSECOND_ONE_SECOND; + /* Sets periodical event and the event signal output assertion and Actives PTP 1588 timer. */ + base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; +} + +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + uint16_t count = ENET_1588TIME_DELAY_COUNT; + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get the current PTP time. */ + ptpTime->second = handle->msTimerSecond; + /* Get the nanosecond from the master timer. */ + base->ATCR |= ENET_ATCR_CAPTURE_MASK; + /* Add at least six clock cycle delay to get accurate time. + It's the requirement when the 1588 clock source is slower + than the register clock. + */ + while (count--) + { + __NOP(); + } + /* Get the captured time. */ + ptpTime->nanosecond = base->ATVR; + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Sets PTP timer. */ + handle->msTimerSecond = ptpTime->second; + base->ATVR = ptpTime->nanosecond; + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) +{ + /* Set correction for PTP timer increment. */ + base->ATINC = (base->ATINC & ~ENET_ATINC_INC_CORR_MASK) | (corrIncrease << ENET_ATINC_INC_CORR_SHIFT); + /* Set correction for PTP timer period. */ + base->ATCOR = (base->ATCOR & ~ENET_ATCOR_COR_MASK) | (corrPeriod << ENET_ATCOR_COR_SHIFT); +} + +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimeData); + + uint16_t usedBuffer = 0; + + /* Check if the buffers ring is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == ptpTsDataRing->size) + { + return kStatus_ENET_PtpTsRingFull; + } + + /* Copy the new data into the buffer. */ + memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); + + /* Increase the buffer pointer to the next empty one. */ + ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; + + return kStatus_Success; +} + +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimedata); + + uint32_t index; + uint32_t size; + uint16_t usedBuffer = 0; + + /* Check the PTP 1588 timestamp ring. */ + if (ptpTsDataRing->front == ptpTsDataRing->end) + { + return kStatus_ENET_PtpTsRingEmpty; + } + + /* Search the element in the ring buffer */ + index = ptpTsDataRing->front; + size = ptpTsDataRing->size; + while (index != ptpTsDataRing->end) + { + if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && + (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && + ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && + ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) + { + break; + } + + /* Increase the ptp ring index. */ + index = (index + 1) % size; + } + + if (index == ptpTsDataRing->end) + { + /* Check if buffers is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == ptpTsDataRing->size) + { /* Drop one in the front. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; + } + return kStatus_ENET_PtpTsRingFull; + } + + /* Get the right timestamp of the required ptp messag. */ + ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; + ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; + + /* Increase the index. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; + + return kStatus_Success; +} + +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + bool ptpTimerWrap = false; + enet_ptp_time_t ptpTimer; + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimer); + + /* Get PTP timer wrap event. */ + ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt; + + /* Get transmit time stamp second. */ + if ((ptpTimer.nanosecond > ptpTimeData->timeStamp.nanosecond) || + ((ptpTimer.nanosecond < ptpTimeData->timeStamp.nanosecond) && ptpTimerWrap)) + { + ptpTimeData->timeStamp.second = handle->msTimerSecond; + } + else + { + ptpTimeData->timeStamp.second = handle->msTimerSecond - 1; + } + /* Enable the interrupt. */ + EnableGlobalIRQ(primask); + + /* Store the timestamp to the receive time stamp ring. */ + /* Check if the buffers ring is full. */ + return ENET_Ptp1588UpdateTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + uint32_t primask; + bool ptpTimerWrap; + bool isPtpEventMessage = false; + enet_ptp_time_data_t ptpTimeData; + volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdDirtyTime; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + + /* Parse the PTP message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(curBuffDescrip->buffer, &ptpTimeData, false); + if (isPtpEventMessage) + { + do + { + /* Increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime = handle->txBdBase; + } + else + { + handle->txBdDirtyTime++; + } + + /* Do time stamp check on the last buffer descriptor of the frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimeData.timeStamp); + + /* Get PTP timer wrap event. */ + ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt; + + /* Get transmit time stamp second. */ + if ((ptpTimeData.timeStamp.nanosecond > curBuffDescrip->timestamp) || + ((ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp) && ptpTimerWrap)) + { + ptpTimeData.timeStamp.second = handle->msTimerSecond; + } + else + { + ptpTimeData.timeStamp.second = handle->msTimerSecond - 1; + } + + /* Enable the interrupt. */ + EnableGlobalIRQ(primask); + + /* Store the timestamp to the transmit timestamp ring. */ + return ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData); + } + + /* Get the current transmit buffer descriptor. */ + curBuffDescrip = handle->txBdDirtyTime; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + } while (handle->txBdDirtyTime != handle->txBdCurrent); + return kStatus_ENET_TxFrameFail; + } + return kStatus_Success; +} + +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); +} + +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + /* Check if the transmit interrupt happen. */ + if ((kENET_TxByteInterrupt | kENET_TxFrameInterrupt) & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = kENET_TxFrameInterrupt | kENET_TxByteInterrupt; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the transmit timestamp from the buffer descriptor should be done here. */ + ENET_StoreTxFrameTime(base, handle); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_TxEvent, handle->userData); + } + } +} + +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + /* Check if the receive interrupt happen. */ + if ((kENET_RxByteInterrupt | kENET_RxFrameInterrupt) & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = kENET_RxFrameInterrupt | kENET_RxByteInterrupt; + + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_RxEvent, handle->userData); + } + } +} + +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; + + /* Check if the PTP time stamp interrupt happen. */ + if (kENET_WakeupInterrupt & base->EIR) + { + /* Clear the wakeup interrupt. */ + base->EIR = kENET_WakeupInterrupt; + /* wake up and enter the normal mode. */ + ENET_EnableSleepMode(base, false); + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); + } + } + else + { + /* Clear the time stamp interrupt. */ + errMask &= base->EIR; + base->EIR = errMask; + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_ErrEvent, handle->userData); + } + } +} +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + /* Check if the PTP time stamp interrupt happen. */ + if (kENET_TsTimerInterrupt & base->EIR) + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsTimerInterrupt; + + /* Increase timer second counter. */ + handle->msTimerSecond++; + + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_TimeStampEvent, handle->userData); + } + } + else + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsAvailInterrupt; + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_TimeStampAvailEvent, handle->userData); + } + } +} +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +void ENET_Transmit_IRQHandler(void) +{ + ENET_TransmitIRQHandler(ENET, s_ENETHandle[0]); +} + +void ENET_Receive_IRQHandler(void) +{ + ENET_ReceiveIRQHandler(ENET, s_ENETHandle[0]); +} + +void ENET_Error_IRQHandler(void) +{ + ENET_ErrorIRQHandler(ENET, s_ENETHandle[0]); +} + +void ENET_1588_Timer_IRQHandler(void) +{ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h new file mode 100755 index 00000000000..8a53c821e5b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h @@ -0,0 +1,1160 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup enet + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ +#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ +#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ +#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ +/*@}*/ + +/* Extended control regions for enhanced buffer descriptors. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @name First extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ +/*@}*/ + +/*! @name First extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ +/*@}*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive error status flag mask. */ +#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ + ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) +#endif + +/*! @name Defines the maximum Ethernet frame size. */ +/*@{*/ +#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Maximum Ethernet frame size. */ +#define ENET_FRAME_MAX_VALNFRAMELEN 1522U /*!< Maximum VLAN frame size. */ +/*@}*/ + +#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ +#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ +#define ENET_BUFF_ALIGNMENT 16U /*!< Ethernet buffer alignment. */ + +/*! @brief Defines the PHY address scope for the ENET. */ +#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameBusy = + MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Transmit buffer descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U) /*!< Transmit frame fail. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 5U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 6U) /*!< Timestamp ring empty. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode +{ + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode /*!< RMII mode for data interface. */ +} enet_mii_mode_t; + +/*! @brief Defines the 10 Mbps or 100 Mbps speed for the MII data interface. */ +typedef enum _enet_mii_speed +{ + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M /*!< Speed 100 Mbps. */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex +{ + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Defines the write operation for the MII management frame. */ +typedef enum _enet_mii_write +{ + kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ + kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ +} enet_mii_write_t; + +/*! @brief Defines the read operation for the MII management frame. */ +typedef enum _enet_mii_read +{ + kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ + kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ +} enet_mii_read_t; + +/*! @brief Defines a special configuration for ENET MAC controller. + * + * These control flags are provided for special user requirements. + * Normally, these control flags are unused for ENET initialization. + * For special requirements, set the flags to + * macSpecialConfig in the enet_config_t. + * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store + * and forward. FIFO store and forward means that the FIFO read/send is started + * when a complete frame is stored in TX/RX FIFO. If this flag is set, + * configure rxFifoFullThreshold and txFifoWatermark + * in the enet_config_t. + */ +typedef enum _enet_special_control_flag +{ + kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ + kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ + kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ + kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ + kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ + kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ + kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ + kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ + kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ + kENET_ControlVLANTagEnable = 0x0200U /*!< Enable VLAN tag frame. */ +} enet_special_control_flag_t; + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _enet_interrupt_enable +{ + kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ + kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ + kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ + kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ + kENET_TxByteInterrupt = ENET_EIR_TXB_MASK, /*!< TX BYTE interrupt source */ + kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ + kENET_RxByteInterrupt = ENET_EIR_RXB_MASK, /*!< RX BYTE interrupt source */ + kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ + kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ + kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ + kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ + kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ + kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive interrupt source */ + kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK /*!< WAKEUP interrupt source */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ + kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event +{ + kENET_RxEvent, /*!< Receive event. */ + kENET_TxEvent, /*!< Transmit event. */ + kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ + kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + kENET_TimeStampEvent, /*!< Time stamp event. */ + kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_event_t; + +/*! @brief Defines the transmit accelerator configuration. */ +typedef enum _enet_tx_accelerator +{ + kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ + kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ + kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ +} enet_tx_accelerator_t; + +/*! @brief Defines the receive accelerator configuration. */ +typedef enum _enet_rx_accelerator +{ + kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ + kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ + kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ + kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ + kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ +} enet_rx_accelerator_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type +{ + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ +typedef enum _enet_ptp_timer_channel +{ + kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ + kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ + kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ + kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ +} enet_ptp_timer_channel_t; + +/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ +typedef enum _enet_ptp_timer_channel_mode +{ + kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ + kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ + kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ + kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ + kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ + kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ + kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ + kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ + kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ + kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ + kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ + kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ +} enet_ptp_timer_channel_mode_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ +typedef struct _enet_rx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t payloadCheckSum; /*!< Internal payload checksum. */ + uint8_t headerLength; /*!< Header length. */ + uint8_t protocolTyte; /*!< Protocol type. */ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ +typedef struct _enet_tx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t reserved0; + uint16_t reserved1; + uint16_t reserved2; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved3; + uint16_t reserved4; + uint16_t reserved5; + uint16_t reserved6; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_tx_bd_struct_t; + +/*! @brief Defines the ENET data error statistic structure. */ +typedef struct _enet_data_error_stats +{ + uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ + uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ + uint32_t statsRxFcsErr; /*!< Receive CRC error. */ + uint32_t statsRxOverRunErr; /*!< Receive over run. */ + uint32_t statsRxTruncateErr; /*!< Receive truncate. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ + uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ + uint32_t statsRxMacErr; /*!< Receive Mac error. */ + uint32_t statsRxPhyErr; /*!< Receive PHY error. */ + uint32_t statsRxCollisionErr; /*!< Receive collision. */ + uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ + uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ + uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ + uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ + uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ + uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ + uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_data_error_stats_t; + +/*! @brief Defines the receive buffer descriptor configure structure. + * + * Note: For the internal DMA requirements, the buffers have a corresponding alignment requirement: + * 1. The aligned receive and transmit buffer size must be evenly divisible by 16. + * 2. The aligned transmit and receive buffer descriptor start address must be at + * least 64 bit aligned. However, it's recommended to be evenly divisible by 16. + * 3. The aligned transmit and receive buffer start address must be evenly divisible by 16. + * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". + * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". + */ +typedef struct _enet_buffer_config +{ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address. */ + volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ +} enet_buffer_config_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configure structure. */ +typedef struct _enet_ptp_config +{ + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ + enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ + uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ +} enet_ptp_config_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. macSpecialConfig is used for a special control configuration, A logical OR of + * "enet_special_control_flag_t". For a special configuration for MAC, + * set this parameter to 0. + * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: + * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. + * 2 - 128 bytes written to TX FIFO .... + * 3 - 192 bytes written to TX FIFO .... + * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... + * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 + * or for larger bus access latency 3 or larger due to contention for the system bus. + * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. + * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. + * If the end of the frame is stored in FIFO and the frame size if smaller than the + * txWatermark, the frame is still transmitted. The rule is the + * same for rxFifoFullThreshold in the receive direction. + * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure + * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold + * are set for flow control enabled case. + * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure + * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. + * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator + * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are + * recommended to be used to enable the transmit and receive accelerator. + * After the accelerators are enabled, the store and forward feature should be enabled. + * As a result, kENET_ControlStoreAndFwdDisabled should not be set. + */ +typedef struct _enet_config +{ + uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ + uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ + uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, + it makes MAC generate XOFF pause frame. */ +#if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, + independent of size, that can be accept. If the limit is reached, reception + continues and a pause frame is triggered. */ +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify + the MAC receive ready status. */ + uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO + before a frame transmit start. */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + volatile enet_rx_bd_struct_t *rxBdBase; /*!< Receive buffer descriptor base address pointer. */ + volatile enet_rx_bd_struct_t *rxBdCurrent; /*!< The current available receive buffer descriptor pointer. */ + volatile enet_rx_bd_struct_t *rxBdDirty; /*!< The dirty receive buffer descriptor needed to be updated from. */ + volatile enet_tx_bd_struct_t *txBdBase; /*!< Transmit buffer descriptor base address pointer. */ + volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */ + uint32_t rxBuffSizeAlign; /*!< Receive buffer size alignment. */ + uint32_t txBuffSizeAlign; /*!< Transmit buffer size alignment. */ + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + volatile enet_tx_bd_struct_t *txBdDirtyStatic; /*!< The dirty transmit buffer descriptor for error static update. */ + volatile enet_tx_bd_struct_t *txBdDirtyTime; /*!< The dirty transmit buffer descriptor for time stamp update. */ + uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * @param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * @param srcClock_Hz The internal module clock source for MII clock. + * + * @note ENET has two buffer descriptors: legacy buffer descriptors and + * enhanced 1588 buffer descriptors. The legacy descriptor is used by default. To + * use 1588 feature, use the enhanced 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Resets the ENET module. + * + * This function restores the ENET module to reset state. + * Note that this function sets all registers to + * reset state. As a result, the ENET module can't work after calling this function. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Reset(ENET_Type *base) +{ + base->ECR |= ENET_ECR_RESET_MASK; +} + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); + +/*! + * @brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * @param base ENET peripheral base address. + * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * @param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); + +/*! + * @brief Gets the ENET SMI- MII management interface configuration. + * + * This API is used to get the SMI configuration to check if the MII management + * interface has been set. + * + * @param base ENET peripheral base address. + * @return The SMI setup status true or false. + */ +static inline bool ENET_GetSMI(ENET_Type *base) +{ + return (0 != (base->MSCR & 0x7E)); +} + +/*! + * @brief Reads data from the PHY register through SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); +} + +/*! + * @brief Starts an SMI (Serial Management Interface) read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Starts a SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +/* @} */ + +/*! + * @name MAC Address Filter + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Adds the ENET device to a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); + +/*! + * @brief Moves the ENET device from a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); + +/* @} */ + +/*! + * @name Other basic operation + * @{ + */ + +/*! + * @brief Activates ENET read or receive. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveRead(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +/*! + * @brief Enables/disables the MAC to enter sleep mode. + * This function is used to set the MAC enter sleep mode. + * When entering sleep mode, the magic frame wakeup interrupt should be enabled + * to wake up MAC from the sleep mode and reset it to normal mode. + * + * @param base ENET peripheral base address. + * @param enable True enable sleep mode, false disable sleep mode. + */ +static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) +{ + if (enable) + { + /* When this field is set, MAC enters sleep mode. */ + base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; + } + else + { /* MAC exits sleep mode. */ + base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); + } +} + +/*! + * @brief Gets ENET transmit and receive accelerator functions from MAC controller. + * + * @param base ENET peripheral base address. + * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + */ +static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) +{ + assert(txAccelOption); + assert(txAccelOption); + + *txAccelOption = base->TACC; + *rxAccelOption = base->RACC; +} + +/* @} */ + +/*! + * @name Interrupts. + * @{ + */ + +/*! + * @brief Enables the ENET interrupt. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to enable the TX frame interrupt and RX frame interrupt, do this: + * @code + * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR |= mask; +} + +/*! + * @brief Disables the ENET interrupt. + * + * This function disables the ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to disable the TX frame interrupt and RX frame interrupt, do this: + * @code + * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR &= ~mask; +} + +/*! + * @brief Gets the ENET interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_interrupt_enable_t. + */ +static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) +{ + return base->EIR; +} + +/*! + * @brief Clears the ENET interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do this: + * @code + * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) +{ + base->EIR = mask; +} + +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Set the callback function. + * This API is provided for application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * @param handle ENET handler pointer. Should be provided by application. + * @param callback The ENET callback function. + * @param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); + +/*! + * @brief Gets the ENET the error statistics of a received frame. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * For example: + * @code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /*! + * @brief Gets the size of the read frame. + * This function reads a received frame size from the ENET buffer descriptors. + * @note The FCS of the frame is removed by MAC controller and the size is the length without the FCS. + * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". + * + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param length The length of the valid frame received. + * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. + * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data + * and NULL length to update the receive buffers. + * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); + +/*! + * @brief Reads a frame from the ENET device. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * @note The FCS of the frame is removed by MAC controller and is not delivered to the application. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); + +/*! + * @brief Transmits an ENET frame. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmit. + * @retval kStatus_ENET_TxFrameFail Transmit frame fail. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); + +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The error IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/* @} */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @name ENET PTP 1588 function operation + * @{ + */ + +/*! + * @brief Configures the ENET PTP 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Stops the ENET PTP 1588 Timer. + * This function is used to stops the ENET PTP timer. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Ptp1588StopTimer(ENET_Type *base) +{ + /* Disable PTP timer and reset the timer. */ + base->ATCR &= ~ENET_ATCR_EN_MASK; + base->ATCR |= ENET_ATCR_RESTART_MASK; +} + +/*! + * @brief Adjusts the ENET PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); + +/*! + * @brief Sets ENET PTP 1588 timer channel mode. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, + enet_ptp_timer_channel_t channel, + enet_ptp_timer_channel_mode_t mode, + bool intEnable) +{ + uint32_t tcrReg = 0; + + tcrReg = ENET_TCSR_TMODE(mode) | ENET_TCSR_TIE(intEnable); + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} + +/*! + * @brief Sets ENET PTP 1588 timer channel comparison value. + * + * @param base ENET peripheral base address. + * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". + * @param cmpValue The compare value for the compare setting. + */ +static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) +{ + base->CHANNEL[channel].TCCR = cmpValue; +} + +/*! + * @brief Gets the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + * @return True or false, Compare or capture operation status + */ +static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); +} + +/*! + * @brief Clears the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + */ +static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; + base->TGSR = (1U << channel); +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief Sets the ENET PTP 1588 timer to the assigned time. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief The IEEE 1588 PTP time stamp interrupt handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c new file mode 100755 index 00000000000..1a71a07e582 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ewm.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void EWM_Init(EWM_Type *base, const ewm_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + + CLOCK_EnableClock(kCLOCK_Ewm0); + value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | + EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + base->CLKPRESCALER = config->prescaler; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + base->CLKCTRL = config->clockSource; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ + + base->CMPL = config->compareLowValue; + base->CMPH = config->compareHighValue; + base->CTRL = value; +} + +void EWM_Deinit(EWM_Type *base) +{ + EWM_DisableInterrupts(base, kEWM_InterruptEnable); + CLOCK_DisableClock(kCLOCK_Ewm0); +} + +void EWM_GetDefaultConfig(ewm_config_t *config) +{ + assert(config); + + config->enableEwm = true; + config->enableEwmInput = false; + config->setInputAssertLogic = false; + config->enableInterrupt = false; +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + config->clockSource = kEWM_LpoClockSource0; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + config->prescaler = 0U; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + config->compareLowValue = 0U; + config->compareHighValue = 0xFEU; +} + +void EWM_Refresh(EWM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; + EnableGlobalIRQ(primaskValue); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h new file mode 100755 index 00000000000..a5c45b3fe76 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_EWM_H_ +#define _FSL_EWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ewm_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EWM driver version 2.0.1. */ +#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Describes ewm clock source. */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT +typedef enum _ewm_lpo_clock_source +{ + kEWM_LpoClockSource0 = 0U, /*!< ewm clock sourced from lpo_clk[0]*/ + kEWM_LpoClockSource1 = 1U, /*!< ewm clock sourced from lpo_clk[1]*/ + kEWM_LpoClockSource2 = 2U, /*!< ewm clock sourced from lpo_clk[2]*/ + kEWM_LpoClockSource3 = 3U, /*!< ewm clock sourced from lpo_clk[3]*/ +} ewm_lpo_clock_source_t; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ + +/*! +* @brief Data structure for EWM configuration. +* +* This structure is used to configure the EWM. +*/ +typedef struct _ewm_config +{ + bool enableEwm; /*!< Enable EWM module */ + bool enableEwmInput; /*!< Enable EWM_in input */ + bool setInputAssertLogic; /*!< EWM_in signal assertion state */ + bool enableInterrupt; /*!< Enable EWM interrupt */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t prescaler; /*!< Clock prescaler value */ +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + uint8_t compareLowValue; /*!< Compare low register value */ + uint8_t compareHighValue; /*!< Compare high register value */ +} ewm_config_t; + +/*! + * @brief EWM interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the EWM interrupt configurations. + */ +enum _ewm_interrupt_enable_t +{ + kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable EWM to generate an interrupt*/ +}; + +/*! + * @brief EWM status flags. + * + * This structure contains the constants for the EWM status flags for use in the EWM functions. + */ +enum _ewm_status_flags_t +{ + kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when ewm is enabled*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name EWM Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that except for interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * Example: + * @code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * @endcode + * + * @param base EWM peripheral base address + * @param config The configuration of EWM +*/ +void EWM_Init(EWM_Type *base, const ewm_config_t *config); + +/*! + * @brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * @param base EWM peripheral base address +*/ +void EWM_Deinit(EWM_Type *base); + +/*! + * @brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configure structure to default values. The default + * values are: + * @code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * @endcode + * + * @param config Pointer to EWM configuration structure. + * @see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config); + +/* @} */ + +/*! + * @name EWM functional Operation + * @{ + */ + +/*! + * @brief Enables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined: + * @arg kEWM_InterruptEnable + */ +static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL |= mask; +} + +/*! + * @brief Disables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined: + * @arg kEWM_InterruptEnable + */ +static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL &= ~mask; +} + +/*! + * @brief Gets EWM all status flags. + * + * This function gets all status flags. + * + * Example for getting Running Flag: + * @code + * uint32_t status; + * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; + * @endcode + * @param base EWM peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) +{ + return (base->CTRL & EWM_CTRL_EWMEN_MASK); +} + +/*! + * @brief Service EWM. + * + * This function reset EWM counter to zero. + * + * @param base EWM peripheral base address +*/ +void EWM_Refresh(EWM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_EWM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c new file mode 100755 index 00000000000..2add4e96352 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c @@ -0,0 +1,2610 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flash.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Misc utility defines + * @{ + */ +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif +#ifndef ALIGN_UP +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU)) +#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU)) +#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU)) +#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU)) +#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU)) +#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \ + ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU)) +#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \ + ((uint32_t)(w)&0xFFU)) +/*@}*/ + +/*! @brief Data flash IFR map Field*/ +#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U +#endif + +/*! + * @name Reserved FlexNVM size (For a variety of purposes) defines + * @{ + */ +#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU +#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU +/*@}*/ + +/*! + * @name Flash Program Once Field defines + * @{ + */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ + 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ + 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +/* FTFL parts(eg. K20) only support 4-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 +#endif +/*@}*/ + +/*! + * @name Flash security status defines + * @{ + */ +#define FLASH_SECURITY_STATE_KEYEN 0x80U +#define FLASH_SECURITY_STATE_UNSECURED 0x02U +#define FLASH_NOT_SECURE 0x01U +#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U +#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U +/*@}*/ + +/*! + * @name Flash controller command numbers + * @{ + */ +#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ +#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ +#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ +#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ +#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ +#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ +#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ +#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ +#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ +#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ +#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ +#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ +#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ +#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ +#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ +#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ +#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ +#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ +#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ +#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ + /*@}*/ + +/*! + * @name Common flash register info defines + * @{ + */ +#if defined(FTFA) +#define FTFx FTFA +#define FTFx_BASE FTFA_BASE +#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFE) +#define FTFx FTFE +#define FTFx_BASE FTFE_BASE +#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFL) +#define FTFx FTFL +#define FTFx_BASE FTFL_BASE +#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#else +#error "Unknown flash controller" +#endif +/*@}*/ + +/*! + * @brief Enumeration for access segment property. + */ +enum _flash_access_segment_property +{ + kFLASH_accessSegmentBase = 256UL, +}; + +/*! + * @brief Enumeration for acceleration ram property. + */ +enum _flash_acceleration_ram_property +{ + kFLASH_accelerationRamSize = 0x400U +}; + +/*! + * @brief Enumeration for flash config area. + */ +enum _flash_config_area_range +{ + kFLASH_configAreaStart = 0x400U, + kFLASH_configAreaEnd = 0x40FU +}; + +/*! @brief program Flash block base address*/ +#define PFLASH_BLOCK_BASE 0x00U + +/*! @brief Total flash region count*/ +#define FSL_FEATURE_FTFx_REGION_COUNT (32U) + +/*! + * @name Flash register access type defines + * @{ + */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT +#define FTFx_REG_ACCESS_TYPE volatile uint8_t * +#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + /*@}*/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Copy flash_run_command() to RAM*/ +static void copy_flash_run_command(uint8_t *flashRunCommand); +/*! @brief Copy flash_cache_clear_command() to RAM*/ +static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand); +/*! @brief Check whether flash execute-in-ram functions are ready*/ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ +static status_t flash_command_sequence(flash_config_t *config); + +/*! @brief Perform the cache clear to the flash*/ +void flash_cache_clear(flash_config_t *config); + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline); +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info); +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Access to FTFx->FCCOB */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3; +#else +#error "Unknown flash controller" +#endif + +/*! @brief Access to FTFx->FPROT */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3; +#else +#error "Unknown flash controller" +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief A function pointer used to point to relocated flash_run_command() */ +static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat); +/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */ +static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) +/*! @brief A static buffer used to hold flash_run_command() */ +static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize]; +/*! @brief A static buffer used to hold flash_cache_clear_command() */ +static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize]; +/*! @brief Flash execute-in-ram function information */ +static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; +#endif + +/*! + * @brief Table of pflash sizes. + * + * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. + * + * The values in this table have been right shifted 10 bits so that they will all fit within + * an 16-bit integer. To get the actual flash density, you must left shift the looked up value + * by 10 bits. + * + * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is + * reserved. + * + * Code to use the table: + * @code + * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + * @endcode + */ +const uint16_t kPFlashDensities[] = { + 8, /* 0x0 - 8192, 8KB */ + 16, /* 0x1 - 16384, 16KB */ + 24, /* 0x2 - 24576, 24KB */ + 32, /* 0x3 - 32768, 32KB */ + 48, /* 0x4 - 49152, 48KB */ + 64, /* 0x5 - 65536, 64KB */ + 96, /* 0x6 - 98304, 96KB */ + 128, /* 0x7 - 131072, 128KB */ + 192, /* 0x8 - 196608, 192KB */ + 256, /* 0x9 - 262144, 256KB */ + 384, /* 0xa - 393216, 384KB */ + 512, /* 0xb - 524288, 512KB */ + 768, /* 0xc - 786432, 768KB */ + 1024, /* 0xd - 1048576, 1MB */ + 1536, /* 0xe - 1572864, 1.5MB */ + /* 2048, 0xf - 2097152, 2MB */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FLASH_Init(flash_config_t *config) +{ + uint32_t flashDensity; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* calculate the flash density from SIM_FCFG1.PFSIZE */ + uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. + * We just use the pre-defined flash size in feature file here to support pre-production parts */ + if (pfsize == 0xf) + { + flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; + } + else + { + flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + } + + /* fill out a few of the structure members */ + config->PFlashBlockBase = PFLASH_BLOCK_BASE; + config->PFlashTotalSize = flashDensity; + config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + config->PFlashAccessSegmentSize = kFLASH_accessSegmentBase << FTFx->FACSS; + config->PFlashAccessSegmentCount = FTFx->FACSN; +#else + config->PFlashAccessSegmentSize = 0; + config->PFlashAccessSegmentCount = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + config->PFlashCallback = NULL; + +/* copy required flash commands to RAM */ +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) + if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) + { + s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; + s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; + s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand; + config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; + FLASH_PrepareExecuteInRamFunctions(config); + } +#endif + + config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; + config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + { + status_t returnCode; + config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; + returnCode = flash_update_flexnvm_memory_partition_status(config); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + } +#endif + + return kStatus_FLASH_Success; +} + +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + config->PFlashCallback = callback; + + return kStatus_FLASH_Success; +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); + copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand); + flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all flash blocks */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} + +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + uint32_t sectorSize; + flash_operation_config_t flashInfo; + uint32_t endAddress; /* storing end address */ + uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + sectorSize = flashInfo.activeSectorSize; + + /* calculating Flash end address */ + endAddress = start + lengthInBytes - 1; + + /* re-calculate the endAddress and align it to the start of the next sector + * which will be used in the comparison below */ + if (endAddress % sectorSize) + { + numberOfSectors = endAddress / sectorSize + 1; + endAddress = numberOfSectors * sectorSize - 1; + } + + /* the start address will increment to the next sector address + * until it reaches the endAdddress */ + while (start <= endAddress) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* Increment to the next sector */ + start += sectorSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Prepare passing parameter to erase all flash blocks (unsecure). */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all unsecure command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ + +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all execute-only segments + * 1st element for the FCCOB register */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + + while (lengthInBytes > 0) + { + /* preparing passing parameter to program the flash block */ + kFCCOBx[1] = *src++; + if (4 == flashInfo.blockWriteUnitSize) + { + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); + } + else if (8 == flashInfo.blockWriteUnitSize) + { + kFCCOBx[2] = *src++; + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* update start address for next iteration */ + start += flashInfo.blockWriteUnitSize; + + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashInfo.blockWriteUnitSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (src == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); + + kFCCOBx[1] = *src; + +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + kFCCOBx[2] = *(src + 1); + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + uint32_t sectorSize; + flash_operation_config_t flashInfo; +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + bool needSwitchFlexRamMode = false; +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + sectorSize = flashInfo.activeSectorSize; + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsRamError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + while (lengthInBytes > 0) + { + /* Make sure the write operation doesn't span two sectors */ + uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); + uint32_t lengthTobeProgrammedOfCurrentSector; + uint32_t currentOffset = 0; + + if (endAddressOfCurrentSector == start) + { + endAddressOfCurrentSector += sectorSize; + } + + if (lengthInBytes + start > endAddressOfCurrentSector) + { + lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; + } + else + { + lengthTobeProgrammedOfCurrentSector = lengthInBytes; + } + + /* Program Current Sector */ + while (lengthTobeProgrammedOfCurrentSector > 0) + { + /* Make sure the program size doesn't exceeds Acceleration RAM size */ + uint32_t programSizeOfCurrentPass; + uint32_t numberOfPhases; + + if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize) + { + programSizeOfCurrentPass = kFLASH_accelerationRamSize; + } + else + { + programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; + } + + /* Copy data to FlexRAM */ + memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); + /* Set start address of the data to be programmed */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); + /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ + numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment; + + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); + + /* Peform command sequence */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + if (returnCode != kStatus_FLASH_Success) + { + flash_cache_clear(config); + return returnCode; + } + + lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; + currentOffset += programSizeOfCurrentPass; + } + + src += currentOffset / 4; + start += currentOffset; + lengthInBytes -= currentOffset; + } + + flash_cache_clear(config); + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Restore function of FlexRAM if needed. */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsEepromError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + bool needSwitchFlexRamMode = false; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Validates the range of the given address */ + if ((start < config->FlexRAMBlockBase) || + ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) + { + return kStatus_FLASH_AddressError; + } + + returnCode = kStatus_FLASH_Success; + + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsEepromError; + } + } + + /* Write data to FlexRAM when it is used as EEPROM emulator */ + while (lengthInBytes > 0) + { + if ((!(start & 0x3U)) && (lengthInBytes >= 4)) + { + *(uint32_t *)start = *(uint32_t *)src; + start += 4; + src += 4; + lengthInBytes -= 4; + } + else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) + { + *(uint16_t *)start = *(uint16_t *)src; + start += 2; + src += 2; + lengthInBytes -= 2; + } + else + { + *(uint8_t *)start = *src; + start += 1; + src += 1; + lengthInBytes -= 1; + } + /* Wait till EEERDY bit is set */ + while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + } + + /* Check for protection violation error */ + if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + } + + /* Switch function of FlexRAM if needed */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsRamError; + } + } + + return returnCode; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + while (lengthInBytes > 0) + { + /* preparing passing parameter */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); + if (flashInfo.resourceCmdAddressAligment == 4) + { + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else if (flashInfo.resourceCmdAddressAligment == 8) + { + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success != returnCode) + { + break; + } + + /* fetch data */ + *dst++ = kFCCOBx[1]; + if (flashInfo.resourceCmdAddressAligment == 8) + { + *dst++ = kFCCOBx[2]; + } + /* update start address for next iteration */ + start += flashInfo.resourceCmdAddressAligment; + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashInfo.resourceCmdAddressAligment; + } + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success == returnCode) + { + *dst = kFCCOBx[1]; +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + *(dst + 1) = kFCCOBx[2]; + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + } + + return returnCode; +} + +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) +{ + /* store data read from flash register */ + uint8_t registerValue; + + if ((config == NULL) || (state == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* check the status of the flash security bits in the security register */ + if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) + { + /* Flash in unsecured state */ + *state = kFLASH_securityStateNotSecure; + } + else + { + /* Flash in secured state + * check for backdoor key security enable bit */ + if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) + { + /* Backdoor key security enabled */ + *state = kFLASH_securityStateBackdoorEnabled; + } + else + { + /* Backdoor key security disabled */ + *state = kFLASH_securityStateBackdoorDisabled; + } + } + + return (kStatus_FLASH_Success); +} + +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) +{ + uint8_t registerValue; /* registerValue */ + status_t returnCode; /* return code variable */ + + if ((config == NULL) || (backdoorKey == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* set the default return code as kStatus_Success */ + returnCode = kStatus_FLASH_Success; + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* Check to see if flash is in secure state (any state other than 0x2) + * If not, then skip this since flash is not secure */ + if (0x02 != (registerValue & 0x03)) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) +{ + /* Check arguments. */ + uint32_t blockSize; + flash_operation_config_t flashInfo; + uint32_t nextBlockStartAddress; + uint32_t remainingBytes; + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + start = flashInfo.convertedAddress; + blockSize = flashInfo.activeBlockSize; + + nextBlockStartAddress = ALIGN_UP(start, blockSize); + if (nextBlockStartAddress == start) + { + nextBlockStartAddress += blockSize; + } + + remainingBytes = lengthInBytes; + + while (remainingBytes) + { + uint32_t numberOfPhrases; + uint32_t verifyLength = nextBlockStartAddress - start; + if (verifyLength > remainingBytes) + { + verifyLength = remainingBytes; + } + + numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment; + + /* Fill in verify section command parameters. */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + if (returnCode) + { + return returnCode; + } + + remainingBytes -= verifyLength; + start += verifyLength; + nextBlockStartAddress += blockSize; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if (expectedData == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + + while (lengthInBytes) + { + /* preparing passing parameter to program check the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); + kFCCOBx[2] = *expectedData; + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + if (failedAddress) + { + *failedAddress = start; + } + if (failedData) + { + *failedData = 0; + } + break; + } + + lengthInBytes -= flashInfo.checkCmdAddressAligment; + expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData); + start += flashInfo.checkCmdAddressAligment; + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify erase all execute-only segments command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state) +{ + uint32_t endAddress; /* end address for protection check */ + uint32_t protectionRegionSize; /* size of flash protection region */ + uint32_t regionCheckedCounter; /* increments each time the flash address was checked for + * protection status */ + uint32_t regionCounter; /* incrementing variable used to increment through the flash + * protection regions */ + uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ + + uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each + * protection region */ + uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1]; /* array of the start addresses for each flash + * protection region. Note this is REGION_COUNT+1 + * due to requiring the next start address after + * the end of flash for loop-check purposes below */ + status_t returnCode; + + if (protection_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + + /* calculating Flash end address */ + endAddress = start + lengthInBytes; + + /* Calculate the size of the flash protection region + * If the flash density is > 32KB, then protection region is 1/32 of total flash density + * Else if flash density is < 32KB, then flash protection region is set to 1KB */ + if (config->PFlashTotalSize > 32 * 1024) + { + protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT; + } + else + { + protectionRegionSize = 1024; + } + + /* populate the flashRegionAddress array with the start address of each flash region */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + + /* populate up to 33rd element of array, this is the next address after end of flash array */ + while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT) + { + flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter; + regionCounter++; + } + + /* populate flashRegionProtectStatus array with status information + * Protection status for each region is stored in the FPROT[3:0] registers + * Each bit represents one region of flash + * 4 registers * 8-bits-per-register = 32-bits (32-regions) + * The convention is: + * FPROT3[bit 0] is the first protection region (start of flash memory) + * FPROT0[bit 7] is the last protection region (end of flash memory) + * regionCounter is used to determine which FPROT[3:0] register to check for protection status + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT) + { + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u); + } + else if ((regionCounter >= 8) && (regionCounter < 16)) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u); + } + else if ((regionCounter >= 16) && (regionCounter < 24)) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u); + } + else + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u); + } + regionCounter++; + } + + /* loop through the flash regions and check + * desired flash address range for protection status + * loop stops when it is detected that start has exceeded the endAddress */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + regionCheckedCounter = 0; + protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ + while (start < endAddress) + { + /* check to see if the address falls within this protection region + * Note that if the entire flash is to be checked, the last protection + * region checked would consist of the last protection start address and + * the start address following the end of flash */ + if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) + { + /* increment regionCheckedCounter to indicate this region was checked */ + regionCheckedCounter++; + + /* check the protection status of this region + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + if (!flashRegionProtectStatus[regionCounter]) + { + /* increment protectStatusCounter to indicate this region is protected */ + protectStatusCounter++; + } + start += protectionRegionSize; /* increment to an address within the next region */ + } + regionCounter++; /* increment regionCounter to check for the next flash protection region */ + } + + /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ + if (protectStatusCounter == 0) + { + *protection_state = kFLASH_protectionStateUnprotected; + } + /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ + else if (protectStatusCounter == regionCheckedCounter) + { + *protection_state = kFLASH_protectionStateProtected; + } + /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed + * In other words, some regions are protected while others are unprotected */ + else + { + *protection_state = kFLASH_protectionStateMixed; + } + + return (returnCode); +} + +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state) +{ + status_t returnCode; + + if (access_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + { + uint32_t executeOnlySegmentCounter = 0; + + /* calculating end address */ + uint32_t endAddress = start + lengthInBytes; + + /* Aligning start address and end address */ + uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize); + uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize); + + uint32_t segmentIndex = 0; + uint32_t maxSupportedExecuteOnlySegmentCount = + (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize; + + while (start < endAddress) + { + uint32_t xacc; + + segmentIndex = start / config->PFlashAccessSegmentSize; + + if (segmentIndex < 32) + { + xacc = *(const volatile uint32_t *)&FTFx->XACCL3; + } + else if (segmentIndex < config->PFlashAccessSegmentCount) + { + xacc = *(const volatile uint32_t *)&FTFx->XACCH3; + segmentIndex -= 32; + } + else + { + break; + } + + /* Determine if this address range is in a execute-only protection flash segment. */ + if ((~xacc) & (1u << segmentIndex)) + { + executeOnlySegmentCounter++; + } + + start += config->PFlashAccessSegmentSize; + } + + if (executeOnlySegmentCounter < 1u) + { + *access_state = kFLASH_accessStateUnLimited; + } + else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) + { + *access_state = kFLASH_accessStateMixed; + } + else + { + *access_state = kFLASH_accessStateExecuteOnly; + } + } +#else + *access_state = kFLASH_accessStateUnLimited; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + return (returnCode); +} + +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + if ((config == NULL) || (value == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + switch (whichProperty) + { + case kFLASH_propertyPflashSectorSize: + *value = config->PFlashSectorSize; + break; + + case kFLASH_propertyPflashTotalSize: + *value = config->PFlashTotalSize; + break; + + case kFLASH_propertyPflashBlockSize: + *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + break; + + case kFLASH_propertyPflashBlockCount: + *value = config->PFlashBlockCount; + break; + + case kFLASH_propertyPflashBlockBaseAddr: + *value = config->PFlashBlockBase; + break; + + case kFLASH_propertyPflashFacSupport: +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) + *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; +#else + *value = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + break; + + case kFLASH_propertyPflashAccessSegmentSize: + *value = config->PFlashAccessSegmentSize; + break; + + case kFLASH_propertyPflashAccessSegmentCount: + *value = config->PFlashAccessSegmentCount; + break; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + case kFLASH_propertyDflashSectorSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + break; + case kFLASH_propertyDflashTotalSize: + *value = config->DFlashTotalSize; + break; + case kFLASH_propertyDflashBlockSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; + break; + case kFLASH_propertyDflashBlockCount: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + break; + case kFLASH_propertyDflashBlockBaseAddr: + *value = config->DFlashBlockBase; + break; + case kFLASH_propertyEepromTotalSize: + *value = config->EEpromTotalSize; + break; +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + + default: /* catch inputs that are not recognized */ + return kStatus_FLASH_UnknownProperty; + } + + return kStatus_FLASH_Success; +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) +{ + status_t status; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + status = flasn_check_flexram_function_option_range(option); + if (status != kStatus_FLASH_Success) + { + return status; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo) +{ + status_t returnCode; + + if ((config == NULL) || (returnInfo == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) + { + return kStatus_FLASH_AlignmentError; + } + + /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ + if ((address >= (config->PFlashTotalSize / 2)) || + ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd))) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + /* Check the option. */ + returnCode = flash_check_swap_control_option(option); + if (returnCode) + { + return returnCode; + } + + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + + returnCode = flash_command_sequence(config); + + returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5; + returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6; + returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7; + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) +{ + flash_swap_state_config_t returnInfo; + status_t returnCode; + + memset(&returnInfo, 0xFFU, sizeof(returnInfo)); + + do + { + returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + if (kFLASH_swapFunctionOptionDisable == option) + { + if (returnInfo.flashSwapState == kFLASH_swapStateDisabled) + { + return kStatus_FLASH_Success; + } + else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized) + { + /* The swap system changed to the DISABLED state with Program flash block 0 + * located at relative flash address 0x0_0000 */ + returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo); + } + else + { + /* Swap disable should be requested only when swap system is in the uninitialized state */ + return kStatus_FLASH_SwapSystemNotInUninitialized; + } + } + else + { + /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, + * the swap procedure should be Uninitialized -> Update-Erased -> Complete. + * After the first swap has been completed, the flash swap inidicator address cannot be modified + * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> + * Complete. */ + switch (returnInfo.flashSwapState) + { + case kFLASH_swapStateUninitialized: + /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo); + break; + case kFLASH_swapStateReady: + /* Validate whether the address provided to the swap system is matched to + * swap indicator address in the IFR */ + returnCode = flash_validate_swap_indicator_address(config, address); + if (returnCode == kStatus_FLASH_Success) + { + /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo); + } + break; + case kFLASH_swapStateUpdate: + /* If current swap mode is Update, Erase indicator sector in non active block + * to proceed swap system to update-erased state */ + returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), + FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey); + break; + case kFLASH_swapStateUpdateErased: + /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo); + break; + case kFLASH_swapStateComplete: + break; + case kFLASH_swapStateDisabled: + /* When swap system is in disabled state, We need to clear swap system back to uninitialized + * by issuing EraseAllBlocks command */ + returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; + break; + default: + returnCode = kStatus_FLASH_InvalidArgument; + break; + } + } + if (returnCode != kStatus_FLASH_Success) + { + break; + } + } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option))); + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 + * or it will cause access error. */ + /* eepromDataSizeCode &= 0x3FU; */ + /* flexnvmPartitionCode &= 0x0FU; */ + + /* preparing passing parameter to program the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be updated by program partition command during reset sequence, + * so we just set reserved values for partitioned FlexNVM size here */ + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ + +status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + *kFPROT = protectStatus; + + if (protectStatus != *kFPROT) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + *protectStatus = *kFPROT; + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FDPROT = protectStatus; + + if (FTFx->FDPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FDPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FEPROT = protectStatus; + + if (FTFx->FEPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FEPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Run flash command + * + * This function should be copied to RAM for execution to make sure that code works + * properly even flash cache is disabled. + * It is for flash-resident bootloader only, not technically required for ROM or + * flashloader (RAM-resident bootloader). + */ +void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) +{ + /* clear CCIF bit */ + *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) + { + } +} + +/*! + * @brief Be used for determining the size of flash_run_command() + * + * This function must be defined that lexically follows flash_run_command(), + * so we can determine the size of flash_run_command() at runtime and not worry + * about toolchain or code generation differences. + */ +void flash_run_command_end(void) +{ +} + +/*! + * @brief Copy flash_run_command() to RAM + * + * This function copys the memory between flash_run_command() and flash_run_command_end() + * into the buffer which is also means that copying flash_run_command() to RAM. + */ +static void copy_flash_run_command(uint8_t *flashRunCommand) +{ + /* Calculate the valid length of flash_run_command() memory. + * Set max size(64 bytes) as default function size, in case some compiler allocates + * flash_run_command_end ahead of flash_run_command. */ + uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; + uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U); + uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U); + if (flash_run_command_end_addr > flash_run_command_start_addr) + { + funcLength = flash_run_command_end_addr - flash_run_command_start_addr; + + assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); + + /* In case some compiler allocates other function in the middle of flash_run_command + * and flash_run_command_end. */ + if (funcLength > kFLASH_executeInRamFunctionMaxSize) + { + funcLength = kFLASH_executeInRamFunctionMaxSize; + } + } + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why -1 and +1 operation exist. */ + memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength); + callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Command Sequence + * + * This function is used to perform the command write sequence to the flash. + * + * @param driver Pointer to storage for the driver runtime state. + * @return An error code or kStatus_FLASH_Success + */ +static status_t flash_command_sequence(flash_config_t *config) +{ + uint8_t registerValue; + +#if FLASH_DRIVER_IS_FLASH_RESIDENT + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + + /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using + * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() + * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ + callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT)); +#else + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + /* clear CCIF bit */ + FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) + { + } +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + + /* Check error bits */ + /* Get flash status register value */ + registerValue = FTFx->FSTAT; + + /* checking access error */ + if (registerValue & FTFx_FSTAT_ACCERR_MASK) + { + return kStatus_FLASH_AccessError; + } + /* checking protection error */ + else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + /* checking MGSTAT0 non-correctable error */ + else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) + { + return kStatus_FLASH_CommandFailure; + } + else + { + return kStatus_FLASH_Success; + } +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Run flash cache clear command + * + * This function should be copied to RAM for execution to make sure that code works + * properly even flash cache is disabled. + * It is for flash-resident bootloader only, not technically required for ROM or + * flashloader (RAM-resident bootloader). + */ +void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) +{ +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS + *ftfx_reg |= MCM_PLACR_CFCC_MASK; +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + *ftfx_reg |= MSCM_OCMDR_OCMC1(2); + *ftfx_reg |= MSCM_OCMDR_OCMC1(1); +#else +/* #error "Unknown flash cache controller" */ +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +} + +/*! + * @brief Be used for determining the size of flash_cache_clear_command() + * + * This function must be defined that lexically follows flash_cache_clear_command(), + * so we can determine the size of flash_cache_clear_command() at runtime and not worry + * about toolchain or code generation differences. + */ +void flash_cache_clear_command_end(void) +{ +} + +/*! + * @brief Copy flash_cache_clear_command() to RAM + * + * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end() + * into the buffer which is also means that copying flash_cache_clear_command() to RAM. + */ +static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand) +{ + /* Calculate the valid length of flash_cache_clear_command() memory. + * Set max size(64 bytes) as default function size, in case some compiler allocates + * flash_cache_clear_command_end ahead of flash_cache_clear_command. */ + uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; + uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U); + uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U); + if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr) + { + funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr; + + assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); + + /* In case some compiler allocates other function in the middle of flash_cache_clear_command + * and flash_cache_clear_command_end. */ + if (funcLength > kFLASH_executeInRamFunctionMaxSize) + { + funcLength = kFLASH_executeInRamFunctionMaxSize; + } + } + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why -1 and +1 operation exist. */ + memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength); + callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Cache Clear + * + * This function is used to perform the cache clear to the flash. + */ +#if (defined(__GNUC__)) +/* #pragma GCC push_options */ +/* #pragma GCC optimize("O0") */ +void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) +#else +#if (defined(__ICCARM__)) +#pragma optimize = none +#endif +#if (defined(__CC_ARM)) +#pragma push +#pragma O0 +#endif +void flash_cache_clear(flash_config_t *config) +#endif +{ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return; + } + +/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using + * pre-processed MACROs or a global variable in flash_cache_clear_comamnd() + * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */ +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS +#if defined(MCM) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR); +#endif +#if defined(MCM0) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR); +#endif +#if defined(MCM1) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR); +#else + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]); +#else + /* #error "Unknown flash cache controller" */ + /* meaningless code, just a workaround to solve warning*/ + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0); +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + +#else + +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS +#if defined(MCM) + MCM->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#if defined(MCM0) + MCM0->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#if defined(MCM1) + MCM1->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2); + MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1); +#else +/* #error "Unknown flash cache controller" */ +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#if (defined(__CC_ARM)) +#pragma pop +#endif +#if (defined(__GNUC__)) +/* #pragma GCC pop_options */ +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Check whether flash execute-in-ram functions are ready */ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + if ((config->flashExecuteInRamFunctionInfo) && + (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_ExecuteInRamFunctionNotReady; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Verify the start and length are alignmentBaseline aligned. */ + if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + +/* check for valid range of the target addresses */ +#if !FLASH_SSD_IS_FLEXNVM_ENABLED + if ((startAddress < config->PFlashBlockBase) || + ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize))) +#else + if (!(((startAddress >= config->PFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) || + ((startAddress >= config->DFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))))) +#endif + { + return kStatus_FLASH_AddressError; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Clean up info Structure*/ + memset(info, 0, sizeof(flash_operation_config_t)); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) + { + info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; + info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; + } + else +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + { + info->convertedAddress = address; + info->activeSectorSize = config->PFlashSectorSize; + info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key) +{ + /* Validate the user key */ + if (key != kFLASH_apiEraseKey) + { + return kStatus_FLASH_EraseKeyError; + } + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) +{ + struct + { + uint32_t reserved0; + uint8_t FlexNVMPartitionCode; + uint8_t EEPROMDataSetSize; + uint16_t reserved1; + } dataIFRReadOut; + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get FlexNVM memory partition info from data flash IFR */ + returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, + sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_PartitionStatusUpdateFailure; + } + + /* Fill out partitioned EEPROM size */ + dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; + switch (dataIFRReadOut.EEPROMDataSetSize) + { + case 0x00U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; + break; + case 0x01U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; + break; + case 0x02U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; + break; + case 0x03U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; + break; + case 0x04U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; + break; + case 0x05U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; + break; + case 0x06U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; + break; + case 0x07U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; + break; + case 0x08U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; + break; + case 0x09U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; + break; + case 0x0AU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; + break; + case 0x0BU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; + break; + case 0x0CU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; + break; + case 0x0DU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; + break; + case 0x0EU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; + break; + case 0x0FU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; + break; + default: + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + break; + } + + /* Fill out partitioned DFlash size */ + dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; + switch (dataIFRReadOut.FlexNVMPartitionCode) + { + case 0x00U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ + break; + case 0x01U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ + break; + case 0x02U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ + break; + case 0x03U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ + break; + case 0x04U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ + break; + case 0x05U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ + break; + case 0x06U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ + break; + case 0x07U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ + break; + case 0x08U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ + break; + case 0x09U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ + break; + case 0x0AU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ + break; + case 0x0BU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ + break; + case 0x0CU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ + break; + case 0x0DU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ + break; + case 0x0EU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ + break; + case 0x0FU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ + break; + default: + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; + break; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option) +{ + status_t status; + uint32_t maxReadbleAddress; + + if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + + status = kStatus_FLASH_Success; + + maxReadbleAddress = start + lengthInBytes - 1; + if (option == kFLASH_resourceOptionVersionId) + { + if ((start != kFLASH_resourceRangeVersionIdStart) || + ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd)) + { + status = kStatus_FLASH_InvalidArgument; + } + } + else if (option == kFLASH_resourceOptionFlashIfr) + { + if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes) + { + } +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP + else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) && + (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd)) + { + } +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + else if ((start >= kFLASH_resourceRangeDflashIfrStart) && + (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd)) + { + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + + return status; +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option) +{ + if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) || + (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) || + (option == kFLASH_swapControlOptionDisableSystem)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_InvalidArgument; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) +{ + flash_swap_ifr_field_config_t flashSwapIfrField; + uint32_t swapIndicatorAddress; + + status_t returnCode; + returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField, + sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field, + * the low 4 bit value of Swap Indicator Address is always 4'b0000 */ + swapIndicatorAddress = + (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; + if (address != swapIndicatorAddress) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) +{ + if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) && + (option != kFLASH_flexramFunctionOptionAvailableForEeprom)) + { + return kStatus_FLASH_InvalidArgument; + } + + return kStatus_FLASH_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h new file mode 100755 index 00000000000..63463e03cb4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h @@ -0,0 +1,1177 @@ +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLASH_H_ +#define _FSL_FLASH_H_ + +#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) +#include +#include +#include "fsl_device_registers.h" +#include "bootloader_common.h" +#else +#include "fsl_common.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! + * @name Flash version + * @{ + */ +/*! @brief Construct the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief FLASH driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief FLASH driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_driverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_driverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_driverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_driverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Whether to support FlexNVM in flash driver */ +#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) +#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */ +#endif + +/*! @brief Whether the FlexNVM is enabled in flash driver */ +#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) + +/*! @brief Flash driver location. */ +#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) +#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) +#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */ +#else +#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */ +#endif +#endif + +/*! @brief Flash Driver Export option */ +#if !defined(FLASH_DRIVER_IS_EXPORTED) +#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) +#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */ +#else +#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */ +#endif +#endif +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASH) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Construct a status code value from a group and code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< Api is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< Api erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-ram function is not available.*/ + kStatus_FLASH_PartitionStatusUpdateFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ + kStatus_FLASH_SetFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/ + kStatus_FLASH_RecoverFlexramAsRamError = + MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as ram.*/ + kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as ram.*/ + kStatus_FLASH_RecoverFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/ + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash api is not supported.*/ + kStatus_FLASH_SwapSystemNotInUninitialized = + MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/ + kStatus_FLASH_SwapIndicatorAddressError = + MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Construct the four char code for flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_apiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for supported flash margin levels. + */ +typedef enum _flash_margin_value +{ + kFLASH_marginValueNormal, /*!< Use the 'normal' read level for 1s.*/ + kFLASH_marginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ + kFLASH_marginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ + kFLASH_marginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ +} flash_margin_value_t; + +/*! + * @brief Enumeration for the three possible flash security states. + */ +typedef enum _flash_security_state +{ + kFLASH_securityStateNotSecure, /*!< Flash is not secure.*/ + kFLASH_securityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ + kFLASH_securityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ +} flash_security_state_t; + +/*! + * @brief Enumeration for the three possible flash protection levels. + */ +typedef enum _flash_protection_state +{ + kFLASH_protectionStateUnprotected, /*!< Flash region is not protected.*/ + kFLASH_protectionStateProtected, /*!< Flash region is protected.*/ + kFLASH_protectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ +} flash_protection_state_t; + +/*! + * @brief Enumeration for the three possible flash execute access levels. + */ +typedef enum _flash_execute_only_access_state +{ + kFLASH_accessStateUnLimited, /*!< Flash region is unLimited.*/ + kFLASH_accessStateExecuteOnly, /*!< Flash region is execute only.*/ + kFLASH_accessStateMixed /*!< Flash is mixed with unLimited and execute only region.*/ +} flash_execute_only_access_state_t; + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_propertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_propertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_propertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_propertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_propertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + kFLASH_propertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ + kFLASH_propertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ + kFLASH_propertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ + kFLASH_propertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ + kFLASH_propertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ + kFLASH_propertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ + kFLASH_propertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ + kFLASH_propertyDflashBlockSize = 0x12U, /*!< Dflash block count property.*/ + kFLASH_propertyDflashBlockCount = 0x13U, /*!< Dflash block base address property.*/ + kFLASH_propertyDflashBlockBaseAddr = 0x14U, /*!< Eeprom total size property.*/ + kFLASH_propertyEepromTotalSize = 0x15U +} flash_property_tag_t; + +/*! + * @brief Constants for execute-in-ram flash function. + */ +enum _flash_execute_in_ram_function_constants +{ + kFLASH_executeInRamFunctionMaxSize = 64U, /*!< Max size of execute-in-ram function.*/ + kFLASH_executeInRamFunctionTotalNum = 2U /*!< Total number of execute-in-ram functions.*/ +}; + +/*! + * @brief Flash execute-in-ram function information. + */ +typedef struct _flash_execute_in_ram_function_config +{ + uint32_t activeFunctionCount; /*!< Number of available execute-in-ram functions.*/ + uint8_t *flashRunCommand; /*!< execute-in-ram function: flash_run_command.*/ + uint8_t *flashCacheClearCommand; /*!< execute-in-ram function: flash_cache_clear_command.*/ +} flash_execute_in_ram_function_config_t; + +/*! + * @brief Enumeration for the two possible options of flash read resource command. + */ +typedef enum _flash_read_resource_option +{ + kFLASH_resourceOptionFlashIfr = + 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ + kFLASH_resourceOptionVersionId = 0x01U /*!< Select code for Version ID*/ +} flash_read_resource_option_t; + +/*! + * @brief Enumeration for the range of special-purpose flash resource + */ +enum _flash_read_resource_range +{ +#if (FSL_FEATURE_FLASH_IS_FTFE == 1) + kFLASH_resourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ + kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_resourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ + kFLASH_resourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ + kFLASH_resourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ + kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_resourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ + kFLASH_resourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ +#endif + kFLASH_resourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ + kFLASH_resourceRangePflashSwapIfrEnd = 0x403FFU, /*!< Pflash swap IFR end address.*/ + kFLASH_resourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ + kFLASH_resourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ +}; + +/*! + * @brief Enumeration for the two possilbe options of set flexram function command. + */ +typedef enum _flash_flexram_function_option +{ + kFLASH_flexramFunctionOptionAvailableAsRam = 0xFFU, /*!< Option used to make FlexRAM available as RAM */ + kFLASH_flexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */ +} flash_flexram_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap function + */ +typedef enum _flash_swap_function_option +{ + kFLASH_swapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */ + kFLASH_swapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */ +} flash_swap_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap Control commands + */ +typedef enum _flash_swap_control_option +{ + kFLASH_swapControlOptionIntializeSystem = 0x01U, /*!< Option used to Intialize Swap System */ + kFLASH_swapControlOptionSetInUpdateState = 0x02U, /*!< Option used to Set Swap in Update State */ + kFLASH_swapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */ + kFLASH_swapControlOptionReportStatus = 0x08U, /*!< Option used to Report Swap Status */ + kFLASH_swapControlOptionDisableSystem = 0x10U /*!< Option used to Disable Swap Status */ +} flash_swap_control_option_t; + +/*! + * @brief Enumeration for the possible flash swap status. + */ +typedef enum _flash_swap_state +{ + kFLASH_swapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/ + kFLASH_swapStateReady = 0x01U, /*!< Flash swap system is in ready state.*/ + kFLASH_swapStateUpdate = 0x02U, /*!< Flash swap system is in update state.*/ + kFLASH_swapStateUpdateErased = 0x03U, /*!< Flash swap system is in updateErased state.*/ + kFLASH_swapStateComplete = 0x04U, /*!< Flash swap system is in complete state.*/ + kFLASH_swapStateDisabled = 0x05U /*!< Flash swap system is in disabled state.*/ +} flash_swap_state_t; + +/*! + * @breif Enumeration for the possible flash swap block status + */ +typedef enum _flash_swap_block_status +{ + kFLASH_swapBlockStatusLowerHalfProgramBlocksAtZero = + 0x00U, /*!< Swap block status is that lower half program block at zero.*/ + kFLASH_swapBlockStatusUpperHalfProgramBlocksAtZero = + 0x01U, /*!< Swap block status is that upper half program block at zero.*/ +} flash_swap_block_status_t; + +/*! + * @brief Flash Swap information. + */ +typedef struct _flash_swap_state_config +{ + flash_swap_state_t flashSwapState; /*!< Current swap system status.*/ + flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/ + flash_swap_block_status_t nextSwapBlockStatus; /*!< Next swap block status.*/ +} flash_swap_state_config_t; + +/*! + * @brief Flash Swap IFR fileds. + */ +typedef struct _flash_swap_ifr_field_config +{ + uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/ + uint16_t swapEnableWord; /*!< Swap enable word field.*/ + uint8_t reserved0[6]; /*!< Reserved field.*/ + uint16_t swapDisableWord; /*!< Swap disable word field.*/ + uint8_t reserved1[4]; /*!< Reserved field.*/ +} flash_swap_ifr_field_config_t; + +/*! + * @brief Enumeration for FlexRAM load during reset option. + */ +typedef enum _flash_partition_flexram_load_option +{ + kFLASH_partitionFlexramLoadOptionLoadedWithValidEepromData = + 0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/ + kFLASH_partitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/ +} flash_partition_flexram_load_option_t; + +/*! @brief callback type used for pflash block*/ +typedef void (*flash_callback_t)(void); + +/*! + * @brief Active flash information for current operation. + */ +typedef struct _flash_operation_config +{ + uint32_t convertedAddress; /*!< Converted address for current flash type.*/ + uint32_t activeSectorSize; /*!< Sector size of current flash type.*/ + uint32_t activeBlockSize; /*!< Block size of current flash type.*/ + uint32_t blockWriteUnitSize; /*!< write unit size.*/ + uint32_t sectorCmdAddressAligment; /*!< Erase sector command address alignment.*/ + uint32_t sectionCmdAddressAligment; /*!< Program/Verify section command address alignment.*/ + uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/ + uint32_t checkCmdAddressAligment; /*!< Program check command address alignment.*/ +} flash_operation_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< Base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< Size of all combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< Number of PFlash blocks. */ + uint32_t PFlashSectorSize; /*!< Size in bytes of a sector of PFlash. */ + flash_callback_t PFlashCallback; /*!< Callback function for flash API. */ + uint32_t PFlashAccessSegmentSize; /*!< Size in bytes of a access segment of PFlash. */ + uint32_t PFlashAccessSegmentCount; /*!< Number of PFlash access segments. */ + uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-ram function. */ + uint32_t FlexRAMBlockBase; /*!< For FlexNVM device, this is the base address of FlexRAM + For non-FlexNVM device, this is the base address of acceleration RAM memory */ + uint32_t FlexRAMTotalSize; /*!< For FlexNVM device, this is the size of FlexRAM + For non-FlexNVM device, this is the size of acceleration RAM memory */ + uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory); + For non-FlexNVM device, this field is unused */ + uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory; + For non-FlexNVM device, this field is unused */ + uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned + from FlexRAM; + For non-FlexNVM device, this field is unused */ +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes global flash properties structure members + * + * This function checks and initializes Flash module for the other Flash APIs. + * + * @param config Pointer to storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! + * @brief Set the desired flash callback function + * + * @param config Pointer to storage for the driver runtime state. + * @param callback callback function to be stored in driver + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback); + +/*! + * @brief Prepare flash execute-in-ram functions + * + * @param config Pointer to storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config); +#endif + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases entire flash + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status + */ +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key); + +/*! + * @brief Erases flash sectors encompassed by parameters passed into function + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address does not need to be sector aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be word aligned. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! + * @brief Erases entire flash, including protected sectors. + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status + */ +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key); +#endif + +/*! + * @brief Erases all program flash execute-only segments defined by the FXACC registers. + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters + * + * This function programs the flash memory with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); + +/*! + * @brief Programs Program Once Field through parameters + * + * This function programs the Program Once Field with desired data for a given + * flash area as determined by the index and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param index The index indicating which area of Program Once Field to be programmed. + * @param src Pointer to the source buffer of data that is to be programmed + * into the Program Once Field. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes); + +/*! + * @brief Programs flash with data at locations passed in through parameters via Program Section command + * + * This function programs the flash memory with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as ram + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); +#endif + +/*! + * @brief Programs EEPROM with data at locations passed in through parameters + * + * This function programs the Emulated EEPROM with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as ram + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); +#endif + +/*@}*/ + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Read resource with data at locations passed in through parameters + * + * This function reads the flash memory with desired location for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param dst Pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be read. Must be word-aligned. + * @param option The resource option which indicates which area should be read back. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option); +#endif + +/*! + * @brief Read Program Once Field through parameters + * + * This function reads the read once feild with given index and length + * + * @param config Pointer to storage for the driver runtime state. + * @param index The index indicating the area of program once field to be read. + * @param dst Pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Security + * @{ + */ + +/*! + * @brief Returns the security state via the pointer passed into the function + * + * This function retrieves the current Flash security status, including the + * security enabling state and the backdoor key enabling state. + * + * @param config Pointer to storage for the driver runtime state. + * @param state Pointer to the value returned for the current security status code: + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state); + +/*! + * @brief Allows user to bypass security with a backdoor key + * + * If the MCU is in secured state, this function will unsecure the MCU by + * comparing the provided backdoor key with ones in the Flash Configuration + * Field. + * + * @param config Pointer to storage for the driver runtime state. + * @param backdoorKey Pointer to the user buffer containing the backdoor key. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies erasure of entire flash at specified margin level + * + * This function will check to see if the flash have been erased to the + * specified read margin level. + * + * @param config Pointer to storage for the driver runtime state. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin); + +/*! + * @brief Verifies erasure of desired flash area at specified margin level + * + * This function will check the appropriate number of flash sectors based on + * the desired start address and length to see if the flash have been erased + * to the specified read margin level. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be verified. Must be word-aligned. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin); + +/*! + * @brief Verifies programming of desired flash area at specified margin level + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it with expected data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be verified. Must be word-aligned. + * @param expectedData Pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice + * @param failedAddress Pointer to returned failing address. + * @param failedData Pointer to returned failing data. Some derivitives do + * not included failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData); + +/*! + * @brief Verifies if the program flash executeonly segments have been erased to + * the specified read margin level + * + * @param config Pointer to storage for the driver runtime state. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin); + +/*@}*/ + +/*! + * @name Protection + * @{ + */ + +/*! + * @brief Returns the protection state of desired flash area via the pointer passed into the function + * + * This function retrieves the current Flash protect status for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param protection_state Pointer to the value returned for the current + * protection status code for the desired flash area. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + */ +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state); + +/*! + * @brief Returns the access state of desired flash area via the pointer passed into the function + * + * This function retrieves the current Flash access status for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param access_state Pointer to the value returned for the current + * access status code for the desired flash area. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + */ +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config Pointer to storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value Pointer to the value returned for the desired flash property + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty unknown property tag + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +/*! + * @name FlexRAM + * @{ + */ + +/*! + * @brief Set FlexRAM Function command + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set work mode of FlexRAM + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option); +#endif + +/*@}*/ + +/*! + * @name Swap + * @{ + */ + +/*! + * @brief Configure Swap function or Check the swap state of Flash Module + * + * @param config Pointer to storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param option The possible option used to configure Flash Swap function or check the flash swap status + * @param returnInfo Pointer to the data which is used to return the information of flash swap. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo); +#endif + +/*! + * @brief Swap the lower half flash with the higher half flaock + * + * @param config Pointer to storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param option The possible option used to configure Flash Swap function or check the flash swap status + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state + */ +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option); +#endif + +/*! + * @name FlexNVM + * @{ + */ + +/*! + * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the + * FlexRAM. + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set FlexRAM load behavior during reset. + * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems. + * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup + * memory supporting EEPROM functions. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode); +#endif + +/*@}*/ + +/*! +* @name Flash Protection Utilities +* @{ +*/ + +/*! + * @brief Set PFLASH Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is + * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest + * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus); + +/*! + * @brief Get PFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the + * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant + * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus); + +/*! + * @brief Set DFLASH Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is + * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest + * address area of DFlash. The most significant bit is corresponding to the highest address area of DFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus); +#endif + +/*! + * @brief Get DFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of + * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most + * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as + * below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus); +#endif + +/*! + * @brief Set EEPROM Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is + * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest + * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on. + * There are two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus); +#endif + +/*! + * @brief Get DFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of + * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most + * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus); +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLASH_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c new file mode 100755 index 00000000000..009a730fdf6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexbus.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base FLEXBUS peripheral base address + * + * @return The FLEXBUS instance + */ +static uint32_t FLEXBUS_GetInstance(FB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to FLEXBUS bases for each instance. */ +static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS; + +/*! @brief Pointers to FLEXBUS clocks for each instance. */ +static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FLEXBUS_GetInstance(FB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FB_COUNT; instance++) + { + if (s_flexbusBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FB_COUNT); + + return instance; +} + +void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) +{ + assert(config != NULL); + assert(config->chip < FB_CSAR_COUNT); + assert(config->waitStates <= 0x3FU); + + uint32_t chip = 0; + uint32_t reg_value = 0; + + /* Ungate clock for FLEXBUS */ + CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); + + /* Reset all the register to default state */ + for (chip = 0; chip < FB_CSAR_COUNT; chip++) + { + /* Reset CSMR register, all chips not valid (disabled) */ + base->CS[chip].CSMR = 0x0000U; + /* Set default base address */ + base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); + /* Reset FB_CSCRx register */ + base->CS[chip].CSCR = 0x0000U; + } + /* Set FB_CSPMCR register */ + /* FlexBus signal group 1 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT; + /* FlexBus signal group 2 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT; + /* FlexBus signal group 3 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT; + /* FlexBus signal group 4 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT; + /* FlexBus signal group 5 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT; + /* Write to CSPMCR register */ + base->CSPMCR = reg_value; + + /* Update chip value */ + chip = config->chip; + + /* Base address */ + reg_value = config->chipBaseAddress; + /* Write to CSAR register */ + base->CS[chip].CSAR = reg_value; + /* Chip-select validation */ + reg_value = 0x1U << FB_CSMR_V_SHIFT; + /* Write protect */ + reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT; + /* Base address mask */ + reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT; + /* Write to CSMR register */ + base->CS[chip].CSMR = reg_value; + /* Burst write */ + reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT; + /* Burst read */ + reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT; + /* Byte-enable mode */ + reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT; + /* Port size */ + reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT; + /* The internal transfer acknowledge for accesses */ + reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT; + /* Byte-Lane shift */ + reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT; + /* The number of wait states */ + reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT; + /* Write address hold or deselect */ + reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT; + /* Read address hold or deselect */ + reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT; + /* Address setup */ + reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT; + /* Extended transfer start/extended address latch */ + reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT; + /* Secondary wait state */ + reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT; + /* Write to CSCR register */ + base->CS[chip].CSCR = reg_value; + /* FlexBus signal group 1 multiplex control */ + reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT; + /* FlexBus signal group 2 multiplex control */ + reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT; + /* FlexBus signal group 3 multiplex control */ + reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT; + /* FlexBus signal group 4 multiplex control */ + reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT; + /* FlexBus signal group 5 multiplex control */ + reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT; + /* Write to CSPMCR register */ + base->CSPMCR = reg_value; +} + +void FLEXBUS_Deinit(FB_Type *base) +{ + /* Gate clock for FLEXBUS */ + CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); +} + +void FLEXBUS_GetDefaultConfig(flexbus_config_t *config) +{ + config->chip = 0; /* Chip 0 FlexBus for validation */ + config->writeProtect = 0; /* Write accesses are allowed */ + config->burstWrite = 0; /* Burst-Write disable */ + config->burstRead = 0; /* Burst-Read disable */ + config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */ + config->autoAcknowledge = true; /* Auto-Acknowledge enable */ + config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */ + config->secondaryWaitStates = 0; /* Secondary wait state disable */ + config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */ + config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */ + config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */ + config->addressSetup = + kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */ + config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */ + config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */ + config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */ + config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */ + config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */ + config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */ +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h new file mode 100755 index 00000000000..23cde14a569 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXBUS_H_ +#define _FSL_FLEXBUS_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexbus + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! + * @brief Defines port size for FlexBus peripheral. + */ +typedef enum _flexbus_port_size +{ + kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */ + kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */ + kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */ +} flexbus_port_size_t; + +/*! + * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. + */ +typedef enum _flexbus_write_address_hold +{ + kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */ +} flexbus_write_address_hold_t; + +/*! + * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. + */ +typedef enum _flexbus_read_address_hold +{ + kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */ + kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */ + kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */ + kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */ +} flexbus_read_address_hold_t; + +/*! + * @brief Address setup for FlexBus peripheral. + */ +typedef enum _flexbus_address_setup +{ + kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */ + kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */ + kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */ + kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */ +} flexbus_address_setup_t; + +/*! + * @brief Defines byte-lane shift for FlexBus peripheral. + */ +typedef enum _flexbus_bytelane_shift +{ + kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */ + kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */ +} flexbus_bytelane_shift_t; + +/*! + * @brief Defines multiplex group1 valid signals. + */ +typedef enum _flexbus_multiplex_group1_signal +{ + kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */ + kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */ + kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */ +} flexbus_multiplex_group1_t; + +/*! + * @brief Defines multiplex group2 valid signals. + */ +typedef enum _flexbus_multiplex_group2_signal +{ + kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */ + kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */ + kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */ +} flexbus_multiplex_group2_t; + +/*! + * @brief Defines multiplex group3 valid signals. + */ +typedef enum _flexbus_multiplex_group3_signal +{ + kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */ + kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */ + kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */ +} flexbus_multiplex_group3_t; + +/*! + * @brief Defines multiplex group4 valid signals. + */ +typedef enum _flexbus_multiplex_group4_signal +{ + kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */ + kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */ + kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */ +} flexbus_multiplex_group4_t; + +/*! + * @brief Defines multiplex group5 valid signals. + */ +typedef enum _flexbus_multiplex_group5_signal +{ + kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */ + kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */ + kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */ +} flexbus_multiplex_group5_t; + +/*! + * @brief Configuration structure that the user needs to set. + */ +typedef struct _flexbus_config +{ + uint8_t chip; /*!< Chip FlexBus for validation */ + uint8_t waitStates; /*!< Value of wait states */ + uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */ + uint32_t chipBaseAddressMask; /*!< Chip base address mask */ + bool writeProtect; /*!< Write protected */ + bool burstWrite; /*!< Burst-Write enable */ + bool burstRead; /*!< Burst-Read enable */ + bool byteEnableMode; /*!< Byte-enable mode support */ + bool autoAcknowledge; /*!< Auto acknowledge setting */ + bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */ + bool secondaryWaitStates; /*!< Secondary wait states number */ + flexbus_port_size_t portSize; /*!< Port size of transfer */ + flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */ + flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */ + flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option */ + flexbus_address_setup_t addressSetup; /*!< Address setup setting */ + flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control */ + flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control */ + flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control */ + flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control */ + flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control */ +} flexbus_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name FlexBus functional operation + * @{ + */ + +/*! + * @brief Initializes and configures the FlexBus module. + * + * This function enables the clock gate for FlexBus module. + * Only chip 0 is validated and set to known values. Other chips are disabled. + * NOTE: In this function, certain parameters, depending on external memories, must + * be set before using FLEXBUS_Init() function. + * This example shows how to set up the uart_state_t and the + * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing + * in these parameters: + @code + flexbus_config_t flexbusConfig; + FLEXBUS_GetDefaultConfig(&flexbusConfig); + flexbusConfig.waitStates = 2U; + flexbusConfig.chipBaseAddress = 0x60000000U; + flexbusConfig.chipBaseAddressMask = 7U; + FLEXBUS_Init(FB, &flexbusConfig); + @endcode + * + * @param base FlexBus peripheral address. + * @param config Pointer to the configure structure +*/ +void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config); + +/*! + * @brief De-initializes a FlexBus instance. + * + * This function disables the clock gate of the FlexBus module clock. + * + * @param base FlexBus peripheral address. + */ +void FLEXBUS_Deinit(FB_Type *base); + +/*! + * @brief Initializes the FlexBus configuration structure. + * + * This function initializes the FlexBus configuration structure to default value. The default + * values are: + @code + fbConfig->chip = 0; + fbConfig->writeProtect = 0; + fbConfig->burstWrite = 0; + fbConfig->burstRead = 0; + fbConfig->byteEnableMode = 0; + fbConfig->autoAcknowledge = true; + fbConfig->extendTransferAddress = 0; + fbConfig->secondaryWaitStates = 0; + fbConfig->byteLaneShift = kFLEXBUS_NotShifted; + fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle; + fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles; + fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge; + fbConfig->portSize = kFLEXBUS_1Byte; + fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; + fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ; + fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; + fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; + fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; + @endcode + * @param config Pointer to the initialization structure. + * @see FLEXBUS_Init + */ +void FLEXBUS_GetDefaultConfig(flexbus_config_t *config); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_FLEXBUS_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c new file mode 100755 index 00000000000..5a1028ba978 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c @@ -0,0 +1,1314 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexcan.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ + +#define FLEXCAN_TIME_QUANTA_NUM (10) + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ + /*! The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */ + /*! an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Enter FlexCAN Fraze Mode. + * + * This function makes the FlexCAN work under Fraze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_EnterFrazeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Fraze Mode. + * + * This function makes the FlexCAN leave Fraze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_ExitFrazeMode(CAN_Type *base); + +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Check if Message Buffer interrupt is enabled. + * + * This function check if Message Buffer interrupt is enabled. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. +*/ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Set Baud Rate of FlexCAN. + * + * This function set the baud rate of FlexCAN. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRate_Bps Baud Rate in Bps. + */ +static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[FSL_FEATURE_SOC_FLEXCAN_COUNT]; + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FLEXCAN_COUNT; instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FLEXCAN_COUNT); + + return instance; +} + +static void FLEXCAN_EnterFrazeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK; + + /* Wait until the FlexCAN Module enter freeze mode. */ + while (!(base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +static void FLEXCAN_ExitFrazeMode(CAN_Type *base) +{ + /* Clear Freeze, Halt bits. */ + base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK); + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (base->MCR & CAN_MCR_FRZACK_MASK) + { + } +} + +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + + /* Is Rx FIFO enabled? */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Get RFFN value. */ + lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; + + if (mbIdx <= lastOccupiedMb) + { + return true; + } + else + { + return false; + } + } + else + { + return false; + } +} + +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) +{ + /* Assertion. */ + assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)); + +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + if (mbIdx < 32) + { +#endif + if (base->IMASK1 & ((uint32_t)(1 << mbIdx))) + { + return true; + } + else + { + return false; + } +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + } + else + { + if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32)))) + return true; + else + return false; + } +#endif +} + +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(!(base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0) + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (base->MCR & CAN_MCR_LPMACK_MASK) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (base->MCR & CAN_MCR_SOFTRST_MASK) + { + } + +/* Reset MCR rigister. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#else + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#endif + + /* Reset CTRL1 and CTRL2 rigister. */ + base->CTRL1 = CAN_CTRL1_SMP_MASK; + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; + + /* Clean all Message Buffer CS fields. */ + for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->MB[i].CS = 0x0; + } +} + +static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) +{ + flexcan_timing_config_t timingConfig; + uint32_t priDiv = baudRate_Bps * FLEXCAN_TIME_QUANTA_NUM; + + /* Assertion: Desired baud rate is too high. */ + assert(baudRate_Bps <= 1000000U); + /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ + assert(priDiv <= sourceClock_Hz); + + if (0 == priDiv) + { + priDiv = 1; + } + + priDiv = (sourceClock_Hz / priDiv) - 1; + + /* Desired baud rate is too low. */ + if (priDiv > 0xFF) + { + priDiv = 0xFF; + } + + /* FlexCAN timing setting formula: + * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); + */ + timingConfig.preDivider = priDiv; + timingConfig.phaseSeg1 = 3; + timingConfig.phaseSeg2 = 2; + timingConfig.propSeg = 1; + timingConfig.rJumpwidth = 1; + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, &timingConfig); +} + +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) +{ + uint32_t mcrTemp; + + /* Assertion. */ + assert(config); + assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + + /* Enable FlexCAN clock. */ + CLOCK_EnableClock(s_flexcanClock[FLEXCAN_GetInstance(base)]); + + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : + base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; + + /* Enable FlexCAN Module for configuartion. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + + /* Save current MCR value. */ + mcrTemp = base->MCR; + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1); + + /* Enable Loop Back Mode? */ + base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK; + + /* Enable Self Wake Up Mode? */ + mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; + + /* Enable Individual Rx Masking? */ + mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + /* Enable Doze Mode? */ + mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; +#endif + + /* Save MCR Configuation. */ + base->MCR = mcrTemp; + + /* Baud Rate Configuration.*/ + FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate); +} + +void FLEXCAN_Deinit(CAN_Type *base) +{ + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + + /* Disable FlexCAN clock. */ + CLOCK_DisableClock(s_flexcanClock[FLEXCAN_GetInstance(base)]); +} + +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Initialize FlexCAN Module config struct with default value. */ + config->clkSrc = kFLEXCAN_ClkSrcOsc; + config->baudRate = 125000U; + config->maxMbNum = 16; + config->enableLoopBack = false; + config->enableSelfWakeup = false; + config->enableIndividMask = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + config->enableDoze = false; +#endif +} + +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= + (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); +} + +void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); +} + +void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); +} + +void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); +} + +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + if (FLEXCAN_IsMbOccupied(base, mbIdx)) + { + assert(false); + } + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((config) || (false == enable))); + + uint32_t cs_temp = 0; + + if (FLEXCAN_IsMbOccupied(base, mbIdx)) + { + assert(false); + } + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = config->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == config->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == config->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +{ + /* Assertion. */ + assert((config) || (false == enable)); + + volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); + uint8_t setup_mb, i, rffn = 0; + + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + if (enable) + { + assert(config->idFilterNum <= 128); + + /* Get the setup_mb value. */ + setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT; + setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xF; i++) + { + if ((8 * (i + 1)) >= config->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8) - (2 * rffn)) > 0); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + } + else + { + rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; + } + + /* Clean ID filter table occuyied Message Buffer Region. */ + rffn = (rffn + 1) * 8; + for (i = 0; i < rffn; i++) + { + idFilterRegion[i] = 0x0; + } + + if (enable) + { + /* Disable unused Rx FIFO Filter. */ + for (i = config->idFilterNum; i < rffn; i++) + { + idFilterRegion[i] = 0xFFFFFFFFU; + } + + /* Copy ID filter table to Message Buffer Region. */ + for (i = 0; i < config->idFilterNum; i++) + { + idFilterRegion[i] = config->idFilterTable[i]; + } + + /* Setup ID Fitlter Type. */ + switch (config->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK : + base->CTRL2 | CAN_CTRL2_MRP_MASK; + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5. */ + FLEXCAN_SetRxMbConfig(base, 0, NULL, false); + FLEXCAN_SetRxMbConfig(base, 1, NULL, false); + FLEXCAN_SetRxMbConfig(base, 2, NULL, false); + FLEXCAN_SetRxMbConfig(base, 3, NULL, false); + FLEXCAN_SetRxMbConfig(base, 4, NULL, false); + FLEXCAN_SetRxMbConfig(base, 5, NULL, false); + } + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); + } + else + { + /* Enter Fraze Mode. */ + FLEXCAN_EnterFrazeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Fraze Mode. */ + FLEXCAN_ExitFrazeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(txFrame); + assert(txFrame->length <= 8); + + uint32_t cs_temp = 0; + + if (FLEXCAN_IsMbOccupied(base, mbIdx)) + { + assert(false); + } + + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = txFrame->id; + + /* Fill Message Format field. */ + if (kFLEXCAN_FrameFormatExtend == txFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if (kFLEXCAN_FrameTypeRemote == txFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = txFrame->dataWord0; + base->MB[mbIdx].WORD1 = txFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + + return kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + return kStatus_Fail; + } +} + +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(rxFrame); + + uint32_t cs_temp; + uint8_t rx_code; + + if (FLEXCAN_IsMbOccupied(base, mbIdx)) + { + assert(false); + } + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[mbIdx].WORD0; + rxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if (kFLEXCAN_RxMbFull == rx_code) + { + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Fail; + } +} + +status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(rxFrame); + + uint32_t cs_temp; + + /* Check if Rx FIFO is Enabled. */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[0].WORD0; + rxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +{ + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) + { + /* Wait until CAN Message send out. */ + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) + { + } + + /* Clean Tx Message Buffer Flag. */ + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Wait until Rx Message Buffer non-empty. */ + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) + { + } + + /* Clean Rx Message Buffer Flag. */ + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); +} + +status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Rx FIFO non-empty. */ + while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* */ + rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | + kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | + kFLEXCAN_WakeUpInterruptEnable); + } + else + { + FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | + kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | + kFLEXCAN_WakeUpInterruptEnable); + } + + /* Enable interrupts in NVIC. */ + EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) + { + assert(false); + } + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + /* Distinguish transmit type. */ + if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; + + /* Register user Frame buffer to receive remote Frame. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; + } + + if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) + { + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); + + return kStatus_Success; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; + return kStatus_Fail; + } + } + else + { + return kStatus_FLEXCAN_TxBusy; + } +} + +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) + { + assert(false); + } + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxBusy; + } +} + +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = xfer->frame; + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts( + base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxFifoBusy; + } +} + +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + if (FLEXCAN_IsMbOccupied(base, mbIdx)) + { + assert(false); + } + + /* Disable Message Buffer Interrupt. */ + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = 0x0; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + if (FLEXCAN_IsMbOccupied(base, mbIdx)) + { + assert(false); + } + + /* Disable Message Buffer Interrupt. */ + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = 0x0; + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(handle); + + /* Check if Rx FIFO is enabled. */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts( + base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = 0x0; + } + + handle->rxFifoState = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(handle); + + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result; + + /* Store Current FlexCAN Module Error and Status. */ + result = base->ESR1; + + do + { + /* Solve FlexCAN Error and Status Interrupt. */ + if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)) + { + status = kStatus_FLEXCAN_ErrorStatus; + + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | + kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag); + } + /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ + else + { + /* For this implementation, we solve the Message with lowest MB index first. */ + for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { + /* Get the lowest unhandled Message Buffer */ + if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) + { + break; + } + } + + /* Does not find Message to deal with. */ + if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + break; + } + + /* Solve Rx FIFO interrupt. */ + if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag)) + { + switch (1 << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + status = kStatus_FLEXCAN_RxFifoWarning; + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxFifoIdle; + } + FLEXCAN_TransferAbortReceiveFifo(base, handle); + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + else + { + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case kFLEXCAN_StateRxData: + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + FLEXCAN_TransferAbortReceive(base, handle, result); + break; + + /* Solve Rx Remote Frame. */ + case kFLEXCAN_StateRxRemote: + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + FLEXCAN_TransferAbortReceive(base, handle, result); + break; + + /* Solve Tx Data Frame. */ + case kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; + FLEXCAN_TransferAbortSend(base, handle, result); + break; + + /* Solve Tx Remote Frame. */ + case kFLEXCAN_StateTxRemote: + handle->mbState[result] = kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + + /* Clear resolved Message Buffer IRQ. */ + FLEXCAN_ClearMbStatusFlags(base, 1 << result); + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + + /* Reset return status */ + status = kStatus_FLEXCAN_UnHandled; + + /* Store Current FlexCAN Module Error and Status. */ + result = base->ESR1; + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) || + (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); +#else + while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) || + (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); +#endif +} + +#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 0) +void CAN0_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[0]); + + FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]); +} +#endif + +#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 1) +void CAN1_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[1]); + + FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]); +} +#endif + +#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 2) +void CAN2_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[2]); + + FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]); +} +#endif + +#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 3) +void CAN3_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[3]); + + FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]); +} +#endif + +#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 4) +void CAN4_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[4]); + + FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h new file mode 100755 index 00000000000..b0dee77173d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h @@ -0,0 +1,1053 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXCAN_H_ +#define _FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/*! @file*/ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN driver version 2.1.0. */ +#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 16)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_STD(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_STD(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. \ + */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_STD(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_STD(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ + */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ + */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN transfer status. */ +enum _flexcan_status +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */ +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +/*! @brief FlexCAN clock source. */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ +} flexcan_clock_source_t; + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +/*! + * @brief FlexCAN Rx FIFO priority + * + * The matching process starts from the Rx MB(or Rx FIFO) with higher priority. + * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with + * the Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the FlexCAN Module interrupt configurations. + * Note: FlexCAN Message Buffers and Rx FIFO have their own interrupts. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */ +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to + * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = CAN_ESR1_BIT1ERR_MASK | /*!< All FlexCAN Error Status. */ + CAN_ESR1_BIT0ERR_MASK | + CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK, +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Rx FIFO status flags. + * + * The FlexCAN Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum _flexcan_rx_fifo_flags +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t reserve1 : 1; /*!< Reserved for placeholder. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t reserve2 : 3; /*!< Reserved for place holder. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +/*! @brief FlexCAN module configuration structure. */ +typedef struct _flexcan_config +{ + uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif +} flexcan_config_t; + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint8_t preDivider; /*!< Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Phase Segment 1. */ + uint8_t phaseSeg2; /*!< Phase Segment 2. */ + uint8_t propSeg; /*!< Propagation Segment. */ +} flexcan_timing_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +/*! @brief FlexCAN Rx FIFO configure structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The quantity of filter elements. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]; + /*!< The buffer for received data from Message Buffers. */ + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters: + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 125000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz); + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disable the FlexCAN module clock and set all register value + * to reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Get the default configuration structure. + * + * This function initializes the FlexCAN configure structure to default value. The default + * value are: + * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 125000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * + * @param config Pointer to FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config); + +/* @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in FLEXCAN_Init(). + * If Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with same index. What calls for special attention is that only the first 32 + * individual masks can be used as Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/Disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param config Pointer to FlexCAN Message Buffer configuration structure. + * @param enable Enable/Disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); + +/*! + * @brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to FlexCAN Rx FIFO configuration structure. + * @param enable Enable/Disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ +void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} + +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + return ((((uint64_t)base->IFLAG1) & mask) | ((((uint64_t)base->IFLAG2) << 32) & mask)); +#else + return (base->IFLAG1 & mask); +#endif +} + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFF); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to provided mask. + * + * This function enables the FlexCAN interrupts according to provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if (mask & kFLEXCAN_WakeUpInterruptEnable) + { + base->MCR |= CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 |= (mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Disables FlexCAN interrupts according to provided mask. + * + * This function disables the FlexCAN interrupts according to provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if (mask & kFLEXCAN_WakeUpInterruptEnable) + { + base->MCR &= ~CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 &= ~(mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFF); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif +} + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFF)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif +} + +/* @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uint32_t) & (base->MB[0].CS); +} + +/* @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (base->MCR & CAN_MCR_LPMACK_MASK) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (!(base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +/*! + * @brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +/*! + * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c new file mode 100644 index 00000000000..cc3e27cecb1 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexcan_edma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ + +/*base, flexcanPrivateHandle->handle); + + if (flexcanPrivateHandle->handle->callback) + { + flexcanPrivateHandle->handle->callback(flexcanPrivateHandle->base, flexcanPrivateHandle->handle, + kStatus_FLEXCAN_RxFifoIdle, flexcanPrivateHandle->handle->userData); + } + } +} + +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle) +{ + assert(handle); + + uint32_t instance = FLEXCAN_GetInstance(base); + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + memset(handle, 0, sizeof(flexcan_edma_handle_t)); + + handle->rxFifoState = KFLEXCAN_RxFifoIdle; + handle->rxFifoEdmaHandle = rxFifoEdmaHandle; + + /* Register Callback. */ + handle->callback = callback; + handle->userData = userData; + + /* Configure Rx FIFO DMA. */ + EDMA_SetCallback(handle->rxFifoEdmaHandle, FLEXCAN_ReceiveFifoEDMACallback, &s_edmaPrivateHandle[instance]); +} + +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *xfer) +{ + assert(handle->rxFifoEdmaHandle); + + edma_transfer_config_t dmaXferConfig; + status_t status; + + /* If previous Rx FIFO receive not finished. */ + if (KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->rxFifoState = KFLEXCAN_RxFifoBusy; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&dmaXferConfig, (void *)FLEXCAN_GetRxFifoHeadAddr(base), sizeof(flexcan_frame_t), + (void *)xfer->frame, sizeof(uint32_t), sizeof(flexcan_frame_t), sizeof(flexcan_frame_t), + kEDMA_PeripheralToMemory); + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig); + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle) +{ + assert(handle->rxFifoEdmaHandle); + + /* Disable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxFifoEdmaHandle); + + handle->rxFifoState = KFLEXCAN_RxFifoIdle; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h new file mode 100644 index 00000000000..75742a83ed6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXCAN_EDMA_H_ +#define _FSL_FLEXCAN_EDMA_H_ + +#include "fsl_flexcan.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexcan_edma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexcan_edma_handle flexcan_edma_handle_t; + +/*! @brief FlexCAN transfer callback function. */ +typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, + flexcan_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief FlexCAN eDMA handle +*/ +struct _flexcan_edma_handle +{ + flexcan_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA Rx FIFO channel used. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle); + +/*! + * @brief Receives the CAN Message from the Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param xfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the receive process which used eDMA. + * + * This function aborts the receive process which used eDMA. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_EDMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c new file mode 100755 index 00000000000..a9056097574 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c @@ -0,0 +1,876 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ftm.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base FTM peripheral base address + * + * @return The FTM instance + */ +static uint32_t FTM_GetInstance(FTM_Type *base); + +/*! + * @brief Sets the FTM register PWM synchronization method + * + * This function will set the necessary bits for the PWM synchronization mode that + * user wishes to use. + * + * @param base FTM peripheral base address + * @param syncMethod Syncronization methods to use to update buffered registers. This is a logical + * OR of members of the enumeration ::ftm_pwm_sync_method_t + */ +static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod); + +/*! + * @brief Sets the reload points used as loading points for register update + * + * This function will set the necessary bits based on what the user wishes to use as loading + * points for FTM register update. When using this it is not required to use PWM synchnronization. + * + * @param base FTM peripheral base address + * @param reloadPoints FTM reload points. This is a logical OR of members of the + * enumeration ::ftm_reload_point_t + */ +static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to FTM bases for each instance. */ +static FTM_Type *const s_ftmBases[] = FTM_BASE_PTRS; + +/*! @brief Pointers to FTM clocks for each instance. */ +static const clock_ip_name_t s_ftmClocks[] = FTM_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FTM_GetInstance(FTM_Type *base) +{ + uint32_t instance; + uint32_t ftmArrayCount = (sizeof(s_ftmBases) / sizeof(s_ftmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ftmArrayCount; instance++) + { + if (s_ftmBases[instance] == base) + { + break; + } + } + + assert(instance < ftmArrayCount); + + return instance; +} + +static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod) +{ + uint8_t chnlNumber = 0; + uint32_t reg = 0, syncReg = 0; + + syncReg = base->SYNC; + /* Enable PWM synchronization of output mask register */ + syncReg |= FTM_SYNC_SYNCHOM_MASK; + + reg = base->COMBINE; + for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) + { + /* Enable PWM synchronization of registers C(n)V and C(n+1)V */ + reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); + } + base->COMBINE = reg; + + reg = base->SYNCONF; + + /* Use enhanced PWM synchronization method. Use PWM sync to update register values */ + reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_SWOC_MASK); + + if (syncMethod & FTM_SYNC_SWSYNC_MASK) + { + /* Enable needed bits for software trigger to update registers with its buffer value */ + reg |= (FTM_SYNCONF_SWRSTCNT_MASK | FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK | + FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_SWOM_MASK); + } + + if (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) + { + /* Enable needed bits for hardware trigger to update registers with its buffer value */ + reg |= (FTM_SYNCONF_HWRSTCNT_MASK | FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK | + FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_HWOM_MASK); + + /* Enable the appropriate hardware trigger that is used for PWM sync */ + if (syncMethod & FTM_SYNC_TRIG0_MASK) + { + syncReg |= FTM_SYNC_TRIG0_MASK; + } + if (syncMethod & FTM_SYNC_TRIG1_MASK) + { + syncReg |= FTM_SYNC_TRIG1_MASK; + } + if (syncMethod & FTM_SYNC_TRIG2_MASK) + { + syncReg |= FTM_SYNC_TRIG2_MASK; + } + } + + /* Write back values to the SYNC register */ + base->SYNC = syncReg; + + /* Write the PWM synch values to the SYNCONF register */ + base->SYNCONF = reg; +} + +static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints) +{ + uint32_t chnlNumber = 0; + uint32_t reg = 0; + + /* Need CNTINC bit to be 1 for CNTIN register to update with its buffer value on reload */ + base->SYNCONF |= FTM_SYNCONF_CNTINC_MASK; + + reg = base->COMBINE; + for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) + { + /* Need SYNCEN bit to be 1 for CnV reg to update with its buffer value on reload */ + reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); + } + base->COMBINE = reg; + + /* Set the reload points */ + reg = base->PWMLOAD; + + /* Enable the selected channel match reload points */ + reg &= ~((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1); + reg |= (reloadPoints & ((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1)); + +#if defined(FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) && (FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) + /* Enable half cycle match as a reload point */ + if (reloadPoints & kFTM_HalfCycMatch) + { + reg |= FTM_PWMLOAD_HCSEL_MASK; + } + else + { + reg &= ~FTM_PWMLOAD_HCSEL_MASK; + } +#endif /* FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD */ + + base->PWMLOAD = reg; + + /* These reload points are used when counter is in up-down counting mode */ + reg = base->SYNC; + if (reloadPoints & kFTM_CntMax) + { + /* Reload when counter turns from up to down */ + reg |= FTM_SYNC_CNTMAX_MASK; + } + else + { + reg &= ~FTM_SYNC_CNTMAX_MASK; + } + + if (reloadPoints & kFTM_CntMin) + { + /* Reload when counter turns from down to up */ + reg |= FTM_SYNC_CNTMIN_MASK; + } + else + { + reg &= ~FTM_SYNC_CNTMIN_MASK; + } + base->SYNC = reg; +} + +status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) +{ + assert(config); + + uint32_t reg; + + if (!(config->pwmSyncMode & + (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_SWSYNC_MASK))) + { + /* Invalid PWM sync mode */ + return kStatus_Fail; + } + + /* Ungate the FTM clock*/ + CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]); + + /* Configure the fault mode, enable FTM mode and disable write protection */ + base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK; + + /* Configure the update mechanism for buffered registers */ + FTM_SetPwmSync(base, config->pwmSyncMode); + + if (config->reloadPoints) + { + /* Setup intermediate register reload points */ + FTM_SetReloadPoints(base, config->reloadPoints); + } + + /* Set the clock prescale factor */ + base->SC = FTM_SC_PS(config->prescale); + + /* Setup the counter operation */ + base->CONF = (FTM_CONF_BDMMODE(config->bdmMode) | FTM_CONF_GTBEEN(config->useGlobalTimeBase)); + + /* Initial state of channel output */ + base->OUTINIT = config->chnlInitState; + + /* Channel polarity */ + base->POL = config->chnlPolarity; + + /* Set the external trigger sources */ + base->EXTTRIG = config->extTriggers; +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) + if (config->extTriggers & kFTM_ReloadInitTrigger) + { + base->CONF |= FTM_CONF_ITRIGR_MASK; + } + else + { + base->CONF &= ~FTM_CONF_ITRIGR_MASK; + } +#endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */ + + /* FTM deadtime insertion control */ + base->DEADTIME = (FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue)); + + /* FTM fault filter value */ + reg = base->FLTCTRL; + reg &= ~FTM_FLTCTRL_FFVAL_MASK; + reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue); + base->FLTCTRL = reg; + + return kStatus_Success; +} + +void FTM_Deinit(FTM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(FTM_SC_CLKS_MASK); + + /* Gate the FTM clock */ + CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]); +} + +void FTM_GetDefaultConfig(ftm_config_t *config) +{ + assert(config); + + /* Divide FTM clock by 1 */ + config->prescale = kFTM_Prescale_Divide_1; + /* FTM behavior in BDM mode */ + config->bdmMode = kFTM_BdmMode_0; + /* Software trigger will be used to update registers */ + config->pwmSyncMode = kFTM_SoftwareTrigger; + /* No intermediate register load */ + config->reloadPoints = 0; + /* Fault control disabled for all channels */ + config->faultMode = kFTM_Fault_Disable; + /* Disable the fault filter */ + config->faultFilterValue = 0; + /* Divide the system clock by 1 */ + config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + /* No counts are inserted */ + config->deadTimeValue = 0; + /* No external trigger */ + config->extTriggers = 0; + /* Initialization value is 0 for all channels */ + config->chnlInitState = 0; + /* Active high polarity for all channels */ + config->chnlPolarity = 0; + /* Use internal FTM counter as timebase */ + config->useGlobalTimeBase = false; +} + +status_t FTM_SetupPwm(FTM_Type *base, + const ftm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + + uint32_t mod, reg; + uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK))); + uint16_t cnv, cnvFirstEdge; + uint8_t i; + + switch (mode) + { + case kFTM_EdgeAlignedPwm: + case kFTM_CombinedPwm: + base->SC &= ~FTM_SC_CPWMS_MASK; + mod = (ftmClock / pwmFreq_Hz) - 1; + break; + case kFTM_CenterAlignedPwm: + base->SC |= FTM_SC_CPWMS_MASK; + mod = ftmClock / (pwmFreq_Hz * 2); + break; + default: + return kStatus_Fail; + } + + /* Return an error in case we overflow the registers, probably would require changing + * clock source to get the desired frequency */ + if (mod > 65535U) + { + return kStatus_Fail; + } + /* Set the PWM period */ + base->MOD = mod; + + /* Setup each FTM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Return error if requested dutycycle is greater than the max allowed */ + if (chnlParams->dutyCyclePercent > 100) + { + return kStatus_Fail; + } + + if ((mode == kFTM_EdgeAlignedPwm) || (mode == kFTM_CenterAlignedPwm)) + { + /* Clear the current mode and edge level bits */ + reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level */ + reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level)); + + /* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */ + reg |= FTM_CnSC_MSB(1U); + + /* Update the mode and edge level */ + base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; + + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlParams->chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return kStatus_Fail; + } + + /* Return error if requested value is greater than the max allowed */ + if (chnlParams->firstEdgeDelayPercent > 100) + { + return kStatus_Fail; + } + + /* Configure delay of the first edge */ + if (chnlParams->firstEdgeDelayPercent == 0) + { + /* No delay for the first edge */ + cnvFirstEdge = 0; + } + else + { + cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; + } + + /* Configure dutycycle */ + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + cnvFirstEdge = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + /* Clear the current mode and edge level bits for channel n */ + reg = base->CONTROLS[chnlParams->chnlNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n */ + reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level)); + + /* Update the mode and edge level for channel n */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg; + + /* Clear the current mode and edge level bits for channel n + 1 */ + reg = base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n + 1 */ + reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level)); + + /* Update the mode and edge level for channel n + 1*/ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg; + + /* Set the channel pair values */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + + /* Set the combine bit for the channel pair */ + base->COMBINE |= + (1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber))); + } + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true); +#endif + + chnlParams++; + } + + return kStatus_Success; +} + +void FTM_UpdatePwmDutycycle(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent) +{ + uint16_t cnv, cnvFirstEdge = 0, mod; + + mod = base->MOD; + if ((currentPwmMode == kFTM_EdgeAlignedPwm) || (currentPwmMode == kFTM_CenterAlignedPwm)) + { + cnv = (mod * dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[chnlNumber].CnV = cnv; + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return; + } + + cnv = (mod * dutyCyclePercent) / 100; + cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + } +} + +void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level) +{ + uint32_t reg = base->CONTROLS[chnlNumber].CnSC; + + /* Clear the field and write the new level value */ + reg &= ~(FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)level << FTM_CnSC_ELSA_SHIFT) & (FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + base->CONTROLS[chnlNumber].CnSC = reg; +} + +void FTM_SetupInputCapture(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_input_capture_edge_t captureMode, + uint32_t filterValue) +{ + uint32_t reg; + + reg = base->CONTROLS[chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= captureMode; + + /* Set the requested input capture mode */ + base->CONTROLS[chnlNumber].CnSC = reg; + /* Input filter available only for channels 0, 1, 2, 3 */ + if (chnlNumber < kFTM_Chnl_4) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); + reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); + base->FILTER = reg; + } +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to input mode */ + FTM_SetPwmOutputEnable(base, chnlNumber, false); +#endif +} + +void FTM_SetupOutputCompare(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_output_compare_mode_t compareMode, + uint32_t compareValue) +{ + uint32_t reg; + + /* Set output on match to the requested level */ + base->CONTROLS[chnlNumber].CnV = compareValue; + + reg = base->CONTROLS[chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= compareMode; + /* Setup the channel output behaviour when a match occurs with the compare value */ + base->CONTROLS[chnlNumber].CnSC = reg; + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlNumber, true); +#endif +} + +void FTM_SetupDualEdgeCapture(FTM_Type *base, + ftm_chnl_t chnlPairNumber, + const ftm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue) +{ + assert(edgeParam); + + uint32_t reg; + + reg = base->COMBINE; + /* Clear the combine bit for the channel pair */ + reg &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + /* Enable the DECAPEN bit */ + reg |= (1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + reg |= (1U << (FTM_COMBINE_DECAP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + base->COMBINE = reg; + + /* Setup the edge detection from channel n and n + 1 */ + reg = base->CONTROLS[chnlPairNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->currChanEdgeMode); + base->CONTROLS[chnlPairNumber * 2].CnSC = reg; + + reg = base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->nextChanEdgeMode); + base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC = reg; + + /* Input filter available only for channels 0, 1, 2, 3 */ + if (chnlPairNumber < kFTM_Chnl_4) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + base->FILTER = reg; + } + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to input mode */ + FTM_SetPwmOutputEnable(base, chnlPairNumber, false); +#endif +} + +void FTM_SetupQuadDecode(FTM_Type *base, + const ftm_phase_params_t *phaseAParams, + const ftm_phase_params_t *phaseBParams, + ftm_quad_decode_mode_t quadMode) +{ + assert(phaseAParams); + assert(phaseBParams); + + uint32_t reg; + + /* Set Phase A filter value if phase filter is enabled */ + if (phaseAParams->enablePhaseFilter) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK); + reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); + base->FILTER = reg; + } + + /* Set Phase B filter value if phase filter is enabled */ + if (phaseBParams->enablePhaseFilter) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH1FVAL_MASK); + reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); + base->FILTER = reg; + } + + /* Set Quadrature decode properties */ + reg = base->QDCTRL; + reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK | + FTM_QDCTRL_PHBPOL_MASK); + reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) | + FTM_QDCTRL_PHBFLTREN(phaseBParams->enablePhaseFilter) | FTM_QDCTRL_PHAPOL(phaseAParams->phasePolarity) | + FTM_QDCTRL_PHBPOL(phaseBParams->phasePolarity)); + base->QDCTRL = reg; + /* Enable Quad decode */ + base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK; +} + +void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams) +{ + uint32_t reg; + + reg = base->FLTCTRL; + if (faultParams->enableFaultInput) + { + /* Enable the fault input */ + reg |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + else + { + /* Disable the fault input */ + reg &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + + if (faultParams->useFaultFilter) + { + /* Enable the fault filter */ + reg |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + } + else + { + /* Disable the fault filter */ + reg &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + } + base->FLTCTRL = reg; + + if (faultParams->faultLevel) + { + /* Active low polarity for the fault input pin */ + base->FLTPOL |= (1U << faultNumber); + } + else + { + /* Active high polarity for the fault input pin */ + base->FLTPOL &= ~(1U << faultNumber); + } +} + +void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask) +{ + uint32_t chnlInts = (mask & 0xFFU); + uint8_t chnlNumber = 0; + + /* Enable the timer overflow interrupt */ + if (mask & kFTM_TimeOverflowInterruptEnable) + { + base->SC |= FTM_SC_TOIE_MASK; + } + + /* Enable the fault interrupt */ + if (mask & kFTM_FaultInterruptEnable) + { + base->MODE |= FTM_MODE_FAULTIE_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Enable the reload interrupt available only on certain SoC's */ + if (mask & kFTM_ReloadInterruptEnable) + { + base->SC |= FTM_SC_RIE_MASK; + } +#endif + + /* Enable the channel interrupts */ + while (chnlInts) + { + if (chnlInts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInts = chnlInts >> 1U; + } +} + +void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask) +{ + uint32_t chnlInts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Disable the timer overflow interrupt */ + if (mask & kFTM_TimeOverflowInterruptEnable) + { + base->SC &= ~FTM_SC_TOIE_MASK; + } + /* Disable the fault interrupt */ + if (mask & kFTM_FaultInterruptEnable) + { + base->MODE &= ~FTM_MODE_FAULTIE_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Disable the reload interrupt available only on certain SoC's */ + if (mask & kFTM_ReloadInterruptEnable) + { + base->SC &= ~FTM_SC_RIE_MASK; + } +#endif + + /* Disable the channel interrupts */ + while (chnlInts) + { + if (chnlInts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInts = chnlInts >> 1U; + } +} + +uint32_t FTM_GetEnabledInterrupts(FTM_Type *base) +{ + uint32_t enabledInterrupts = 0; + int8_t chnlCount = FSL_FEATURE_FTM_CHANNEL_COUNTn(base); + + /* The CHANNEL_COUNT macro returns -1 if it cannot match the FTM instance */ + assert(chnlCount != -1); + + /* Check if timer overflow interrupt is enabled */ + if (base->SC & FTM_SC_TOIE_MASK) + { + enabledInterrupts |= kFTM_TimeOverflowInterruptEnable; + } + /* Check if fault interrupt is enabled */ + if (base->MODE & FTM_MODE_FAULTIE_MASK) + { + enabledInterrupts |= kFTM_FaultInterruptEnable; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check if the reload interrupt is enabled */ + if (base->SC & FTM_SC_RIE_MASK) + { + enabledInterrupts |= kFTM_ReloadInterruptEnable; + } +#endif + + /* Check if the channel interrupts are enabled */ + while (chnlCount > 0) + { + chnlCount--; + if (base->CONTROLS[chnlCount].CnSC & FTM_CnSC_CHIE_MASK) + { + enabledInterrupts |= (1U << chnlCount); + } + } + + return enabledInterrupts; +} + +uint32_t FTM_GetStatusFlags(FTM_Type *base) +{ + uint32_t statusFlags = 0; + + /* Check the timer flag */ + if (base->SC & FTM_SC_TOF_MASK) + { + statusFlags |= kFTM_TimeOverflowFlag; + } + /* Check fault flag */ + if (base->FMS & FTM_FMS_FAULTF_MASK) + { + statusFlags |= kFTM_FaultFlag; + } + /* Check channel trigger flag */ + if (base->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) + { + statusFlags |= kFTM_ChnlTriggerFlag; + } +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check reload flag */ + if (base->SC & FTM_SC_RF_MASK) + { + statusFlags |= kFTM_ReloadFlag; + } +#endif + + /* Lower 8 bits contain the channel status flags */ + statusFlags |= (base->STATUS & 0xFFU); + + return statusFlags; +} + +void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask) +{ + /* Clear the timer overflow flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_TimeOverflowFlag) + { + base->SC &= ~FTM_SC_TOF_MASK; + } + /* Clear fault flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_FaultFlag) + { + base->FMS &= ~FTM_FMS_FAULTF_MASK; + } + /* Clear channel trigger flag */ + if (mask & kFTM_ChnlTriggerFlag) + { + base->EXTTRIG &= ~FTM_EXTTRIG_TRIGF_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check reload flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_ReloadFlag) + { + base->SC &= ~FTM_SC_RF_MASK; + } +#endif + /* Clear the channel status flags by writing a 0 to the bit */ + base->STATUS &= ~(mask & 0xFFU); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h new file mode 100755 index 00000000000..eb1ebf79f4c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h @@ -0,0 +1,862 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FTM_H_ +#define _FSL_FTM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ftm_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of FTM channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _ftm_chnl +{ + kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/ + kFTM_Chnl_1, /*!< FTM channel number 1 */ + kFTM_Chnl_2, /*!< FTM channel number 2 */ + kFTM_Chnl_3, /*!< FTM channel number 3 */ + kFTM_Chnl_4, /*!< FTM channel number 4 */ + kFTM_Chnl_5, /*!< FTM channel number 5 */ + kFTM_Chnl_6, /*!< FTM channel number 6 */ + kFTM_Chnl_7 /*!< FTM channel number 7 */ +} ftm_chnl_t; + +/*! @brief List of FTM faults */ +typedef enum _ftm_fault_input +{ + kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */ + kFTM_Fault_1, /*!< FTM fault 1 input pin */ + kFTM_Fault_2, /*!< FTM fault 2 input pin */ + kFTM_Fault_3 /*!< FTM fault 3 input pin */ +} ftm_fault_input_t; + +/*! @brief FTM PWM operation modes */ +typedef enum _ftm_pwm_mode +{ + kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */ + kFTM_CombinedPwm /*!< Combined PWM */ +} ftm_pwm_mode_t; + +/*! @brief FTM PWM output pulse mode: high-true, low-true or no output */ +typedef enum _ftm_pwm_level_select +{ + kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */ + kFTM_LowTrue, /*!< Low true pulses */ + kFTM_HighTrue /*!< High true pulses */ +} ftm_pwm_level_select_t; + +/*! @brief Options to configure a FTM channel's PWM signal */ +typedef struct _ftm_chnl_pwm_signal_param +{ + ftm_chnl_t chnlNumber; /*!< The channel/channel pair number. + In combined mode, this represents the channel pair number. */ + ftm_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0 = inactive signal(0% duty cycle)... + 100 = always active signal (100% duty cycle).*/ + uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate an asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure leave as 0; Should be specified as a + percentage of the PWM period */ +} ftm_chnl_pwm_signal_param_t; + +/*! @brief FlexTimer output compare mode */ +typedef enum _ftm_output_compare_mode +{ + kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ + kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ + kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */ + kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */ +} ftm_output_compare_mode_t; + +/*! @brief FlexTimer input capture edge */ +typedef enum _ftm_input_capture_edge +{ + kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/ + kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/ + kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ +} ftm_input_capture_edge_t; + +/*! @brief FlexTimer dual edge capture modes */ +typedef enum _ftm_dual_edge_capture_mode +{ + kFTM_OneShot = 0U, /*!< One-shot capture mode */ + kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */ +} ftm_dual_edge_capture_mode_t; + +/*! @brief FlexTimer dual edge capture parameters */ +typedef struct _ftm_dual_edge_capture_param +{ + ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */ + ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ + ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ +} ftm_dual_edge_capture_param_t; + +/*! @brief FlexTimer quadrature decode modes */ +typedef enum _ftm_quad_decode_mode +{ + kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ + kFTM_QuadCountAndDir /*!< Count and direction encoding mode */ +} ftm_quad_decode_mode_t; + +/*! @brief FlexTimer quadrature phase polarities */ +typedef enum _ftm_phase_polarity +{ + kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ + kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */ +} ftm_phase_polarity_t; + +/*! @brief FlexTimer quadrature decode phase parameters */ +typedef struct _ftm_phase_param +{ + bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */ + uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */ + ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */ +} ftm_phase_params_t; + +/*! @brief Structure is used to hold the parameters to configure a FTM fault */ +typedef struct _ftm_fault_param +{ + bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */ + bool faultLevel; /*!< True: Fault polarity is active low i.e '0' indicates a fault; + False: Fault polarity is active high */ + bool useFaultFilter; /*!< True: Use the filtered fault signal; + False: Use the direct path from fault input */ +} ftm_fault_param_t; + +/*! @brief FlexTimer pre-scaler factor for the dead time insertion*/ +typedef enum _ftm_deadtime_prescale +{ + kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */ + kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */ + kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */ +} ftm_deadtime_prescale_t; + +/*! @brief FlexTimer clock source selection*/ +typedef enum _ftm_clock_source +{ + kFTM_SystemClock = 1U, /*!< System clock selected */ + kFTM_FixedClock, /*!< Fixed frequency clock */ + kFTM_ExternalClock /*!< External clock */ +} ftm_clock_source_t; + +/*! @brief FlexTimer pre-scaler factor selection for the clock source*/ +typedef enum _ftm_clock_prescale +{ + kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ + kFTM_Prescale_Divide_2, /*!< Divide by 2 */ + kFTM_Prescale_Divide_4, /*!< Divide by 4 */ + kFTM_Prescale_Divide_8, /*!< Divide by 8 */ + kFTM_Prescale_Divide_16, /*!< Divide by 16 */ + kFTM_Prescale_Divide_32, /*!< Divide by 32 */ + kFTM_Prescale_Divide_64, /*!< Divide by 64 */ + kFTM_Prescale_Divide_128 /*!< Divide by 128 */ +} ftm_clock_prescale_t; + +/*! @brief Options for the FlexTimer behaviour in BDM Mode */ +typedef enum _ftm_bdm_mode +{ + kFTM_BdmMode_0 = 0U, + /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V + registers bypass the register buffers */ + kFTM_BdmMode_1, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to + MOD,CNTIN and C(n)V registers bypass the register buffers */ + kFTM_BdmMode_2, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, + writes to MOD,CNTIN and C(n)V registers bypass the register buffers */ + kFTM_BdmMode_3 + /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and + C(n)V registers is in fully functional mode */ +} ftm_bdm_mode_t; + +/*! @brief Options for the FTM fault control mode */ +typedef enum _ftm_fault_mode +{ + kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */ + kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */ + kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */ + kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */ +} ftm_fault_mode_t; + +/*! + * @brief FTM external trigger options + * @note Actual available external trigger sources are SoC-specific + */ +typedef enum _ftm_external_trigger +{ + kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */ + kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */ + kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */ + kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */ + kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */ + kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */ + kFTM_Chnl6Trigger = + (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */ + kFTM_Chnl7Trigger = + (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */ + kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */ + kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */ +} ftm_external_trigger_t; + +/*! @brief FlexTimer PWM sync options to update registers with buffer */ +typedef enum _ftm_pwm_sync_method +{ + kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */ + kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */ + kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */ + kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */ +} ftm_pwm_sync_method_t; + +/*! + * @brief FTM options available as loading point for register reload + * @note Actual available reload points are SoC-specific + */ +typedef enum _ftm_reload_point +{ + kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */ + kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */ + kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */ + kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */ + kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */ + kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */ + kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */ + kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */ + kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */ + kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */ + kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */ +} ftm_reload_point_t; + +/*! + * @brief List of FTM interrupts + * @note Actual available interrupts are SoC-specific + */ +typedef enum _ftm_interrupt_enable +{ + kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */ + kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */ + kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */ + kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */ + kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */ + kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */ + kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */ + kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */ + kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */ + kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */ + kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */ +} ftm_interrupt_enable_t; + +/*! + * @brief List of FTM flags + * @note Actual available flags are SoC-specific + */ +typedef enum _ftm_status_flags +{ + kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */ + kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */ + kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */ + kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */ + kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */ + kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */ + kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */ + kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */ + kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */ + kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */ + kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */ + kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */ +} ftm_status_flags_t; + +/*! + * @brief FTM configuration structure + * + * This structure holds the configuration settings for the FTM peripheral. To initialize this + * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ftm_config +{ + ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */ + ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */ + uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple + update modes can be used by providing an OR'ed list of options + available in enumeration ::ftm_pwm_sync_method_t. */ + uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM + synchronization is not required. Multiple reload points can be used by providing + an OR'ed list of options available in + enumeration ::ftm_reload_point_t. */ + ftm_fault_mode_t faultMode; /*!< FTM fault control mode */ + uint8_t faultFilterValue; /*!< Fault input filter value */ + ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */ + uint8_t deadTimeValue; /*!< The dead time value */ + uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be + enabled by providing an OR'ed list of options available in + enumeration ::ftm_external_trigger_t. */ + uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */ + uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */ + bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled; + False: disabled */ +} ftm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FTM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the FTM driver. + * + * @param base FTM peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t FTM_Init(FTM_Type *base, const ftm_config_t *config); + +/*! + * @brief Gates the FTM clock. + * + * @param base FTM peripheral base address + */ +void FTM_Deinit(FTM_Type *base); + +/*! + * @brief Fills in the FTM configuration structure with the default settings. + * + * The default values are: + * @code + * config->prescale = kFTM_Prescale_Divide_1; + * config->bdmMode = kFTM_BdmMode_0; + * config->pwmSyncMode = kFTM_SoftwareTrigger; + * config->reloadPoints = 0; + * config->faultMode = kFTM_Fault_Disable; + * config->faultFilterValue = 0; + * config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + * config->deadTimeValue = 0; + * config->extTriggers = 0; + * config->chnlInitState = 0; + * config->chnlPolarity = 0; + * config->useGlobalTimeBase = false; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void FTM_GetDefaultConfig(ftm_config_t *config); + +/*! @}*/ + +/*! + * @name Channel mode operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this + * function to configure all FTM channels that are used to output a PWM signal. + * + * @param base FTM peripheral base address + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure; This should be the size of the array passed in + * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz FTM counter clock in Hz + * + * @return kStatus_Success if the PWM setup was successful + * kStatus_Error on failure + */ +status_t FTM_SetupPwm(FTM_Type *base, + const ftm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel/channel pair number. In combined mode, this represents + * the channel pair number + * @param currentPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void FTM_UpdatePwmDutycycle(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Updates the edge level selection for a channel. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. + * See the Kinetis SoC reference manual for details about this field. + */ +void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level); + +/*! + * @brief Enables capturing an input signal on the channel using the function parameters. + * + * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is + * captured into the CnV register. The user has to read the CnV register separately to get this + * value. The filter function is disabled if the filterVal argument passed in is 0. The filter + * function is available only for channels 0, 1, 2, 3. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param captureMode Specifies which edge to capture + * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3. + */ +void FTM_SetupInputCapture(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_input_capture_edge_t captureMode, + uint32_t filterValue); + +/*! + * @brief Configures the FTM to generate timed pulses. + * + * When the FTM counter matches the value of compareVal argument (this is written into CnV reg), + * the channel output is changed based on what is specified in the compareMode argument. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param compareMode Action to take on the channel output when the compare condition is met + * @param compareValue Value to be programmed in the CnV register. + */ +void FTM_SetupOutputCompare(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_output_compare_mode_t compareMode, + uint32_t compareValue); + +/*! + * @brief Configures the dual edge capture mode of the FTM. + * + * This function sets up the dual edge capture mode on a channel pair. The capture edge for the + * channel pair and the capture mode (one-shot or continuous) is specified in the parameter + * argument. The filter function is disabled if the filterVal argument passed is zero. The filter + * function is available only on channels 0 and 2. The user has to read the channel CnV registers + * separately to get the capture values. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param edgeParam Sets up the dual edge capture function + * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1. + */ +void FTM_SetupDualEdgeCapture(FTM_Type *base, + ftm_chnl_t chnlPairNumber, + const ftm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue); + +/*! @}*/ + +/*! + * @brief Configures the parameters and activates the quadrature decoder mode. + * + * @param base FTM peripheral base address + * @param phaseAParams Phase A configuration parameters + * @param phaseBParams Phase B configuration parameters + * @param quadMode Selects encoding mode used in quadrature decoder mode + */ +void FTM_SetupQuadDecode(FTM_Type *base, + const ftm_phase_params_t *phaseAParams, + const ftm_phase_params_t *phaseBParams, + ftm_quad_decode_mode_t quadMode); + +/*! + * @brief Sets up the working of the FTM fault protection. + * + * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter. + * + * @param base FTM peripheral base address + * @param faultNumber FTM fault to configure. + * @param faultParams Parameters passed in to set up the fault + */ +void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected FTM interrupts. + * + * @param base FTM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected FTM interrupts. + * + * @param base FTM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled FTM interrupts. + * + * @param base FTM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +uint32_t FTM_GetEnabledInterrupts(FTM_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the FTM status flags. + * + * @param base FTM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ftm_status_flags_t + */ +uint32_t FTM_GetStatusFlags(FTM_Type *base); + +/*! + * @brief Clears the FTM status flags. + * + * @param base FTM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ftm_status_flags_t + */ +void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the FTM counter. + * + * @param base FTM peripheral base address + * @param clockSource FTM clock source; After the clock source is set, the counter starts running. + */ +static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource) +{ + uint32_t reg = base->SC; + + reg &= ~(FTM_SC_CLKS_MASK); + reg |= FTM_SC_CLKS(clockSource); + base->SC = reg; +} + +/*! + * @brief Stops the FTM counter. + * + * @param base FTM peripheral base address + */ +static inline void FTM_StopTimer(FTM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(FTM_SC_CLKS_MASK); +} + +/*! @}*/ + +/*! + * @name Software output control + * @{ + */ + +/*! + * @brief Enables or disables the channel software output control. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be enabled or disabled + * @param value true: channel output is affected by software output control + false: channel output is unaffected by software output control + */ +static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SWOCTRL |= (1U << chnlNumber); + } + else + { + base->SWOCTRL &= ~(1U << chnlNumber); + } +} + +/*! + * @brief Sets the channel software output control value. + * + * @param base FTM peripheral base address. + * @param chnlNumber Channel to be configured + * @param value true to set 1, false to set 0 + */ +static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SWOCTRL |= (1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); + } + else + { + base->SWOCTRL &= ~(1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); + } +} + +/*! @}*/ + +/*! + * @brief Enables or disables the FTM global time base signal generation to other FTMs. + * + * @param base FTM peripheral base address + * @param enable true to enable, false to disable + */ +static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable) +{ + if (enable) + { + base->CONF |= FTM_CONF_GTBEOUT_MASK; + } + else + { + base->CONF &= ~FTM_CONF_GTBEOUT_MASK; + } +} + +/*! + * @brief Sets the FTM peripheral timer channel output mask. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be configured + * @param mask true: masked, channel is forced to its inactive state; false: unmasked + */ +static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask) +{ + if (mask) + { + base->OUTMASK |= (1U << chnlNumber); + } + else + { + base->OUTMASK &= ~(1U << chnlNumber); + } +} + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) +/*! + * @brief Allows user to enable an output on an FTM channel. + * + * To enable the PWM channel output call this function with val=true. For input mode, + * call this function with val=false. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be configured + * @param value true: enable output; false: output is disabled, used in input mode + */ +static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SC |= (1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); + } + else + { + base->SC &= ~(1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); + } +} +#endif + +/*! + * @name Channel pair operations + * @{ + */ + +/*! + * @brief This function enables/disables the fault control in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: Enable fault control for this channel pair; false: No fault control + */ +static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables the dead time insertion in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: Insert dead time in this channel pair; false: No dead time inserted + */ +static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables complementary mode in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: enable complementary mode; false: disable complementary mode + */ +static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables inverting control in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: enable inverting; false: disable inverting + */ +static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->INVCTRL |= (1U << chnlPairNumber); + } + else + { + base->INVCTRL &= ~(1U << chnlPairNumber); + } +} + +/*! @}*/ + +/*! + * @brief Enables or disables the FTM software trigger for PWM synchronization. + * + * @param base FTM peripheral base address + * @param enable true: software trigger is selected, false: software trigger is not selected + */ +static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable) +{ + if (enable) + { + base->SYNC |= FTM_SYNC_SWSYNC_MASK; + } + else + { + base->SYNC &= ~FTM_SYNC_SWSYNC_MASK; + } +} + +/*! + * @brief Enables or disables the FTM write protection. + * + * @param base FTM peripheral base address + * @param enable true: Write-protection is enabled, false: Write-protection is disabled + */ +static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable) +{ + /* Configure write protection */ + if (enable) + { + base->FMS |= FTM_FMS_WPEN_MASK; + } + else + { + base->MODE |= FTM_MODE_WPDIS_MASK; + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FTM_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c new file mode 100755 index 00000000000..8fc068f2d6a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_GPIO_COUNT); + + return instance; +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + GPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! +* @brief Gets the FGPIO instance according to the GPIO base +* +* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval FGPIO instance +*/ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT); + + return instance; +} + +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + FGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h new file mode 100755 index 00000000000..6eaaaa08744 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.1.0. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief GPIO direction definition*/ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused + * Note : In some cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig() + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin's number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low logic level. + * - 1: corresponding pin output high logic level. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin's number + * @retval GPIO port input value + * - 0: corresponding pin input low logic level. + * - 1: corresponding pin input high logic level. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name GPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads whole GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pins' interrupt status flag. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); + +/*@}*/ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduce the FGPIO feature. + * + * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name FGPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO pin's number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low logic level. + * - 1: corresponding pin output high logic level. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name FGPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the whole FGPIO port. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO pin's number + * @retval FGPIO port input value + * - 0: corresponding pin input low logic level. + * - 1: corresponding pin input high logic level. + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name FGPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads the whole FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pins' interrupt status flag. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); + +/*@}*/ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c new file mode 100755 index 00000000000..e77a3832399 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c @@ -0,0 +1,1536 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ +/*! All flags which are cleared by the driver upon starting a transfer. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, +#else + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +#endif + +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; + +/*! @brief SCL clock divider used to calculate baudrate. */ +const uint16_t s_i2cDividerTable[] = {20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, + 48, 56, 68, 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, + 112, 128, 144, 160, 192, 240, 160, 192, 224, 256, 288, 320, 384, + 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768, 896, 1024, + 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +/*! @brief Pointers to i2c clocks for each instance. */ +const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_I2C_COUNT; instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_I2C_COUNT); + + return instance; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + uint16_t timeout = UINT16_MAX; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + else + { + handle->state = kCheckAddressState; + } + + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout)) + { + } + + /* Failed to start the transfer. */ + if (timeout == 0) + { + return kStatus_I2C_Timeout; + } + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->S; + *isDone = false; + volatile uint8_t dummy = 0; + bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + if (result) + { + return result; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == kCheckAddressState) + { + if (statusFlags & kI2C_ReceiveNakFlag) + { + return kStatus_I2C_Nak; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case kSendCommandState: + if (handle->transfer.subaddressSize) + { + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case kReceiveDataBeginState: + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Next state, receive data. */ + handle->state = kReceiveDataState; + break; + + /* Receive I2C data. */ + case kReceiveDataState: + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->D; + handle->transfer.data++; + } + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig && srcClock_Hz); + + /* Temporary register for filter read. */ + uint8_t fltReg; +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + uint8_t c2Reg; +#endif + + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); + + /* Disable I2C prior to configuring it. */ + base->C1 &= ~(I2C_C1_IICEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + /* Configure high drive feature. */ + c2Reg = base->C2; + c2Reg &= ~(I2C_C2_HDRS_MASK); + c2Reg |= I2C_C2_HDRS(masterConfig->enableHighDrive); + base->C2 = c2Reg; +#endif + + /* Read out the FLT register. */ + fltReg = base->FLT; + +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + /* Configure the stop / hold enable. */ + fltReg &= ~(I2C_FLT_SHEN_MASK); + fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); +#endif + + /* Configure the glitch filter value. */ + fltReg &= ~(I2C_FLT_FLT_MASK); + fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); + + /* Write the register value back to the filter register. */ + base->FLT = fltReg; + + /* Enable the I2C peripheral based on the configuration. */ + base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + +/* Default pin high drive is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + masterConfig->enableHighDrive = false; +#endif + +/* Default stop hold enable is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + masterConfig->enableStopHold = false; +#endif + + /* Default glitch filter value is no filter. */ + masterConfig->glitchFilterWidth = 0U; + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 |= I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT |= I2C_FLT_STOPIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT |= I2C_FLT_SSIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 &= ~I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT &= ~I2C_FLT_STOPIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT &= ~I2C_FLT_SSIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t multiplier; + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) + { + multiplier = 1u << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) + { + computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint8_t savedMult; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + uint8_t timeDelay = 6; + + /* Return an error if the bus is already in use, but not by us. */ + if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0)) + { + result = kStatus_I2C_Busy; + } + else + { + savedMult = base->F; + base->F = savedMult & (~I2C_F_MULT_MASK); + + /* We are already in a transfer, so send a repeated start. */ + base->C1 |= I2C_C1_RSTA_MASK; + + /* Restore the multiplier factor. */ + base->F = savedMult; + + /* Add some delay to wait the Re-Start signal. */ + while (timeDelay--) + { + __NOP(); + } + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + /* Issue the STOP command on the bus. */ + base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Wait until data transfer complete. */ + while ((base->S & kI2C_BusBusyFlag) && (--timeout)) + { + } + + if (timeout == 0) + { + result = kStatus_I2C_Timeout; + } + + return result; +} + +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + uint32_t statusFlags = base->S; + +#ifdef I2C_HAS_STOP_DETECT + /* Look up the STOPF bit from the filter register. */ + if (base->FLT & I2C_FLT_STOPF_MASK) + { + statusFlags |= kI2C_StopDetectFlag; + } +#endif + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Look up the STARTF bit from the filter register. */ + if (base->FLT & I2C_FLT_STARTF_MASK) + { + statusFlags |= kI2C_StartDetectFlag; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + return statusFlags; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->C1 |= I2C_C1_TX_MASK; + + while (txSize--) + { + /* Send a byte of data. */ + base->D = *txBuff++; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + statusFlags = base->S; + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (statusFlags & kI2C_ArbitrationLostFlag) + { + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if (statusFlags & kI2C_ReceiveNakFlag) + { + base->S = kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + return result; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = base->D; + + while ((rxSize--)) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0) + { + /* Read the final byte. */ + result = I2C_MasterStop(base); + } + + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = base->D; + } + + return result; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Wait until ready to complete. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + /* Return if error. */ + if (result) + { + return result; + } + + /* Send subaddress. */ + if (xfer->subaddressSize) + { + do + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + xfer->subaddressSize--; + base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); + + } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + + if (xfer->direction == kI2C_Read) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result) + { + return result; + } + } + } + + /* Wait until address + command transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + /* Transmit data. */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize); + + if (((result == kStatus_Success) && (!(xfer->flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + } + + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || result) + { + /* Send stop command if transfer done or received Nak. */ + if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->C1 & I2C_C1_MST_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + uint8_t tmpReg; + + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); + + /* Configure addressing mode. */ + switch (slaveConfig->addressingMode) + { + case kI2C_Address7bit: + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + break; + + case kI2C_RangeMatch: + assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U; + base->C2 |= I2C_C2_RMEN_MASK; + break; + + default: + break; + } + + /* Configure low power wake up feature. */ + tmpReg = base->C1; + tmpReg &= ~I2C_C1_WUEN_MASK; + base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); + + /* Configure general call & baud rate control & high drive feature. */ + tmpReg = base->C2; + tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); + tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + tmpReg &= ~I2C_C2_HDRS_MASK; + tmpReg |= I2C_C2_HDRS(slaveConfig->enableHighDrive); +#endif + base->C2 = tmpReg; +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* By default slave is addressed with 7-bit address. */ + slaveConfig->addressingMode = kI2C_Address7bit; + + /* General call mode is disabled by default. */ + slaveConfig->enableGeneralCall = false; + + /* Slave address match waking up MCU from low power mode is disabled. */ + slaveConfig->enableWakeUp = false; + +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + /* Default pin high drive is disabled. */ + slaveConfig->enableHighDrive = false; +#endif + + /* Independent slave mode baud rate at maximum frequency is disabled. */ + slaveConfig->enableBaudRateCtl = false; + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + return I2C_MasterWriteBlocking(base, txBuff, txSize); +} + +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Wait until the data register is ready for receive. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK); + + while (rxSize--) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->D; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + } +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->isBusy) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, kIrqFlags); + } + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle); + + if (handle->isBusy) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->isBusy = false; + } +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + +#ifdef I2C_HAS_STOP_DETECT + /* Check stop flag. */ + if (status & kI2C_StopDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Call slave callback if this is the STOP of the transfer. */ + if (handle->isBusy) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + return; + } +#endif /* I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + if (status & kI2C_StartDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + xfer->event = kI2C_SlaveRepeatedStartEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (!(status & kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check NAK */ + if (status & kI2C_ReceiveNakFlag) + { + /* Set receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy. */ + dummy = base->D; + + if (handle->transfer.dataSize != 0) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + /* Check address match. */ + else if (status & kI2C_AddressMatchFlag) + { + handle->isBusy = true; + xfer->event = kI2C_SlaveAddressMatchEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + /* Change direction to send data. */ + base->C1 |= I2C_C1_TX_MASK; + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + } + } + /* Check transfer complete flag. */ + else if (status & kI2C_TransferCompleteFlag) + { + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + uint8_t data = base->D; + + if (handle->transfer.dataSize) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + if (!handle->transfer.dataSize) + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed receive complete event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->D; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + if (handle->transfer.dataSize) + { + /* Send data. */ + base->D = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed txdone event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } +} + +void I2C0_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); +} + +#if (FSL_FEATURE_SOC_I2C_COUNT > 1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif /* I2C COUNT > 1 */ + +#if (FSL_FEATURE_SOC_I2C_COUNT > 2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif /* I2C COUNT > 2 */ +#if (FSL_FEATURE_SOC_I2C_COUNT > 3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif /* I2C COUNT > 3 */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h new file mode 100755 index 00000000000..41a9afbdd54 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h @@ -0,0 +1,781 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.0. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ + defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) +#define I2C_HAS_STOP_DETECT +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * - #kI2C_StartDetectFlag + * - #kI2C_StopDetectFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ + kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ +#ifdef I2C_HAS_STOP_DETECT + kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmit to slave. */ + kI2C_Read = 0x1U, /*!< Master receive from slave. */ +} i2c_direction_t; + +/*! @brief Addressing mode. */ +typedef enum _i2c_slave_address_mode +{ + kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ + kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ +} i2c_slave_address_mode_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< Transfer starts without a start signal. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< Transfer ends without a stop signal. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ +#endif + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveRepeatedStartEvent | +#endif + kI2C_SlaveCompletionEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */ +#endif +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + bool enableStopHold; /*!< Controls the stop hold enable. */ +#endif + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ + uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ +} i2c_master_config_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + bool enableGeneralCall; /*!< Enable general call addressing mode. */ + bool enableWakeUp; /*!< Enables/disables waking up MCU from low power mode. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */ +#endif + bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ + uint16_t slaveAddress; /*!< Slave address configuration. */ + uint16_t upperAddress; /*!< Maximum boundary slave address used in range matching mode. */ + i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */ +} i2c_slave_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t *volatile data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t *volatile data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + bool isBusy; /*!< Whether transfer is busy. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application to use + * the I2C driver, or any operation to the I2C module could cause hard fault + * because clock is not enabled. The configuration structure can be filled by user + * from scratch, or be set with default values by I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * Example: + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig pointer to master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initializes the I2C with slave configuration. + * + * @note This API should be called at the beginning of the application to use + * the I2C driver, or any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user. + * Example + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false + * }; + * I2C_SlaveInit(I2C0, &config); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig pointer to slave configuration structure + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of + * the structure before calling I2C_MasterConfigure(). + * Example: + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig Pointer to the master configuration structure. +*/ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * Example: + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig Pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disabless the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_IICEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_IICEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags could get the related status. + */ +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags could get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter could be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ +/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (statusMask & kI2C_StartDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + +#ifdef I2C_HAS_STOP_DETECT + if (statusMask & kI2C_StopDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + + base->S = (uint8_t)statusMask; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter could be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @name DMA Control + * @{ + */ +#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT +/*! + * @brief Enables/disables the I2C DMA interrupt. + * + * @param base I2C base pointer + * @param enable true to enable, false to disable +*/ +static inline void I2C_EnableDMA(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_DMAEN_MASK; + } +} + +#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ + +/*! + * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address + * for I2C DMA transfer configuration. + * + * @param base I2C base pointer + * @return data register address + */ +static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) +{ + return (uint32_t)(&(base->D)); +} + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus without a STOP signal. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus with a STOP signal. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user paramater passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API will return immediately after transfer initiates, user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished, if the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Sucessully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c new file mode 100755 index 00000000000..c8f7c20629f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, false); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) + { + /* Change to send NAK at the last byte. */ + i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; + + /* Wait the last data to be received. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + + /* Read the last data byte. */ + *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = + i2cPrivateHandle->base->D; + } + else + { + /* Wait the last data to be sent. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + } + } + + i2cPrivateHandle->handle->state = kIdleState; + + if (i2cPrivateHandle->handle->completionCallback) + { + i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result, + i2cPrivateHandle->handle->userData); + } +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + i2c_direction_t direction = xfer->direction; + + /* Init the handle member. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + handle->state = kTransferDataState; + + /* Wait until ready to complete. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout)) + { + } + + /* Failed to start the transfer. */ + if (timeout == 0) + { + return kStatus_I2C_Timeout; + } + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + /* Send subaddress. */ + if (handle->transfer.subaddressSize) + { + do + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + return result; + } + + } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success)); + + if (handle->transfer.direction == kI2C_Read) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + } + } + + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + } + + return result; +} + +static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle) +{ + edma_transfer_config_t transfer_config; + + if (handle->transfer.direction == kI2C_Read) + { + transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.destAddr = (uint32_t)(handle->transfer.data); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); + } + else + { + transfer_config.majorLoopCounts = handle->transfer.dataSize; + } + + transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.srcOffset = 0; + transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.destOffset = 1; + transfer_config.minorLoopBytes = 1; + } + else + { + transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1); + transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); + transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.srcOffset = 1; + transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.destOffset = 0; + transfer_config.minorLoopBytes = 1; + } + + EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config); + EDMA_StartTransfer(handle->dmaHandle); +} + +void I2C_MasterCreateEDMAHandle(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaHandle) +{ + assert(handle); + assert(edmaHandle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Set the base for the handle. */ + base = base; + + /* Set the handle for EDMA. */ + handle->dmaHandle = edmaHandle; + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]); +} + +status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result; + uint8_t tmpReg; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable dma xfer. */ + I2C_EnableDMA(base, false); + + /* Send address and command buffer(if there is), until senddata phase or receive data phase. */ + result = I2C_InitTransferStateMachineEDMA(base, handle, xfer); + + if (result) + { + /* Send stop if received Nak. */ + if (result == kStatus_I2C_Nak) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + + /* Reset the state to idle state. */ + handle->state = kIdleState; + + return result; + } + + /* Configure dma transfer. */ + /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read, + need to send stop before reading the last byte, so the dma transfer size should + be (xSize - 1). */ + if (handle->transfer.dataSize > 1) + { + I2C_MasterTransferEDMAConfig(base, handle); + if (handle->transfer.direction == kI2C_Read) + { + /* Change direction for receive. */ + base->C1 &= ~I2C_C1_TX_MASK; + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + } + else + { + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + + /* Send the first data. */ + base->D = *handle->transfer.data; + } + } + else /* If transfer size is 1, use polling method. */ + { + if (handle->transfer.direction == kI2C_Read) + { + tmpReg = base->C1; + + /* Change direction to Rx. */ + tmpReg &= ~I2C_C1_TX_MASK; + + /* Configure send NAK */ + tmpReg |= I2C_C1_TXAK_MASK; + + base->C1 = tmpReg; + + /* Read dummy to release the bus. */ + dummy = base->D; + } + else + { + base->D = *handle->transfer.data; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + + /* Read the last byte of data. */ + if (handle->transfer.direction == kI2C_Read) + { + *handle->transfer.data = base->D; + } + + /* Reset the state to idle. */ + handle->state = kIdleState; + } + + return result; +} + +status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle->dmaHandle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kIdleState != handle->state) + { + *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + else + { + *count = handle->transferSize; + } + + return kStatus_Success; +} + +void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle) +{ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable dma transfer. */ + I2C_EnableDMA(base, false); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h new file mode 100755 index 00000000000..234876d451c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup i2c_edma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief I2C master edma handle typedef. */ +typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t; + +/*! @brief I2C master edma transfer callback typedef. */ +typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base, + i2c_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master edma transfer structure. */ +struct _i2c_master_edma_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< I2C master transfer status. */ + edma_handle_t *dmaHandle; /*!< The eDMA handler used. */ + i2c_master_edma_transfer_callback_t + completionCallback; /*!< Callback function called after edma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block EDMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transcational functions. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + * @param callback pointer to user callback function. + * @param userData user param passed to the callback function. + * @param edmaHandle EDMA handle pointer. + */ +void I2C_MasterCreateEDMAHandle(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaHandle); + +/*! + * @brief Performs a master edma non-blocking transfer on the I2C bus. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + * @param xfer pointer to transfer structure of i2c_master_transfer_t. + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a edma non-blocking transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master edma non-blocking transfer in a early time. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + */ +void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c new file mode 100755 index 00000000000..c27b91e9f04 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_llwu.h" + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + volatile uint32_t *regBase; + uint32_t regOffset; + uint32_t reg; + + switch (pinIndex >> 4U) + { + case 0U: + regBase = &base->PE1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 1U: + regBase = &base->PE2; + break; +#endif + default: + regBase = NULL; + break; + } +#else + volatile uint8_t *regBase; + uint8_t regOffset; + uint8_t reg; + switch (pinIndex >> 2U) + { + case 0U: + regBase = &base->PE1; + break; + case 1U: + regBase = &base->PE2; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 2U: + regBase = &base->PE3; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) + case 3U: + regBase = &base->PE4; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 4U: + regBase = &base->PE5; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) + case 5U: + regBase = &base->PE6; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 6U: + regBase = &base->PE7; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) + case 7U: + regBase = &base->PE8; + break; +#endif + default: + regBase = NULL; + break; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ + + if (regBase) + { + reg = *regBase; +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + regOffset = ((pinIndex & 0x0FU) << 1U); +#else + regOffset = ((pinIndex & 0x03U) << 1U); +#endif + reg &= ~(0x3U << regOffset); + reg |= ((uint32_t)pinMode << regOffset); + *regBase = reg; + } +} + +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->PF & (1U << pinIndex)); +#else + volatile uint8_t *regBase; + + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + return (bool)(*regBase & (1U << pinIndex % 8)); + } + else + { + return false; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + base->PF = (1U << pinIndex); +#else + volatile uint8_t *regBase; + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + if (regBase) + { + *regBase = (1U << pinIndex % 8U); + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); + reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) + /* Clear the Filter Detect Flag */ + | LLWU_FILT_FILTF1_MASK) + << (filterIndex * 8U - 1U)); + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); + reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); + reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); + /* Clear the Filter Detect Flag */ + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); +#else + bool status = false; + + switch (filterIndex) + { + case 1: + status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + break; + } + + return status; +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + switch (filterIndex) + { + case 1: + reg |= LLWU_FILT_FILTF1_MASK; + break; + case 2: + reg |= LLWU_FILT_FILTF2_MASK; + break; + case 3: + reg |= LLWU_FILT_FILTF3_MASK; + break; + case 4: + reg |= LLWU_FILT_FILTF4_MASK; + break; + default: + break; + } + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) +{ + uint8_t reg; + + reg = base->RST; + reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); + reg |= + (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); + base->RST = reg; +} +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h new file mode 100755 index 00000000000..7c11572e806 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LLWU_H_ +#define _FSL_LLWU_H_ + +#include "fsl_common.h" + +/*! @addtogroup llwu */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LLWU driver version 2.0.1. */ +#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief External input pin control modes + */ +typedef enum _llwu_external_pin_mode +{ + kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as wakeup input. */ + kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with rising edge detection. */ + kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/ + kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ +} llwu_external_pin_mode_t; + +/*! + * @brief Digital filter control modes + */ +typedef enum _llwu_pin_filter_mode +{ + kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ + kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ + kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ + kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ +} llwu_pin_filter_mode_t; + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _llwu_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} llwu_version_id_t; +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _llwu_param +{ + uint8_t filters; /*!< Number of pin filter. */ + uint8_t dmas; /*!< Number of wakeup DMA. */ + uint8_t modules; /*!< Number of wakeup module. */ + uint8_t pins; /*!< Number of wake up pin. */ +} llwu_param_t; +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief External input pin filter control structure + */ +typedef struct _llwu_external_pin_filter_mode +{ + uint32_t pinIndex; /*!< Pin number */ + llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ +} llwu_external_pin_filter_mode_t; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Low-Leakage Wakeup Unit Control APIs + * @{ + */ + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief Gets the LLWU version ID. + * + * This function gets the LLWU version ID, including major version number, + * minor version number, and feature specification number. + * + * @param base LLWU peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief Gets the LLWU parameter. + * + * This function gets the LLWU parameter, including wakeup pin number, module + * number, DMA number, and pin filter number. + * + * @param base LLWU peripheral base address. + * @param param Pointer to LLWU param structure. + */ +static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) +{ + *((uint32_t *)param) = base->PARAM; +} +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * @brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index which to be enabled as external wakeup source, start from 1. + * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t + */ +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woke up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index, start from 1. + * @return true if the specific pin is wake up source. + */ +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); + +/*! + * @brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index, start from 1. + */ +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) +/*! + * @brief Enables/disables the internal module source. + * + * This function enables/disables the internal module source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex module index which to be enabled as internal wakeup source, start from 1. + * @param enable enable or disable setting + */ +static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->ME |= 1U << moduleIndex; + } + else + { + base->ME &= ~(1U << moduleIndex); + } +} + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the system is + * woke up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param moduleIndex module index, start from 1. + * @return true if the specific pin is wake up source. + */ +static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->MF & (1U << moduleIndex)); +#else +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->MF5 & (1U << moduleIndex)); +#else + return (bool)(base->F5 & (1U << moduleIndex)); +#endif /* FSL_FEATURE_LLWU_HAS_PF */ +#else +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->PF3 & (1U << moduleIndex)); +#else + return (bool)(base->F3 & (1U << moduleIndex)); +#endif +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ + +#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) +/*! + * @brief Enables/disables the internal module DMA wakeup source. + * + * This function enables/disables the internal DMA that is used as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex Internal module index which used as DMA request source, start from 1. + * @param enable Enable or disable DMA request source + */ +static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->DE |= 1U << moduleIndex; + } + else + { + base->DE &= ~(1U << moduleIndex); + } +} +#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1. + * @param filterMode filter mode configuration + */ +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index, start from 1. + * @return true if the flag is a source of existing a low-leakage power mode. + */ +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +/*! + * @brief Clear the pin filter configuration. + * + * This function clear the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index which to be clear the flag, start from 1. + */ +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +/*! + * @brief Sets the reset pin mode. + * + * This function sets how the reset pin is used as a low leakage mode exit source. + * + * @param pinEnable Enable reset pin filter + * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif /* _FSL_LLWU_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c new file mode 100755 index 00000000000..b3dcc89d55d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lptmr.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base LPTMR peripheral base address + * + * @return The LPTMR instance + */ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPTMR bases for each instance. */ +static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; + +/*! @brief Pointers to LPTMR clocks for each instance. */ +static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++) + { + if (s_lptmrBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT); + + return instance; +} + +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) +{ + assert(config); + + /* Ungate the LPTMR clock*/ + CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); + + /* Configure the timers operation mode and input pin setup */ + base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); + + /* Configure the prescale value and clock source */ + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + LPTMR_PSR_PCS(config->prescalerClockSource)); +} + +void LPTMR_Deinit(LPTMR_Type *base) +{ + /* Disable the LPTMR and reset the internal logic */ + base->CSR &= ~LPTMR_CSR_TEN_MASK; + /* Gate the LPTMR clock*/ + CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); +} + +void LPTMR_GetDefaultConfig(lptmr_config_t *config) +{ + assert(config); + + /* Use time counter mode */ + config->timerMode = kLPTMR_TimerModeTimeCounter; + /* Use input 0 as source in pulse counter mode */ + config->pinSelect = kLPTMR_PinSelectInput_0; + /* Pulse input pin polarity is active-high */ + config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + /* Counter resets whenever TCF flag is set */ + config->enableFreeRunning = false; + /* Bypass the prescaler */ + config->bypassPrescaler = true; + /* LPTMR clock source */ + config->prescalerClockSource = kLPTMR_PrescalerClock_1; + /* Divide the prescaler clock by 2 */ + config->value = kLPTMR_Prescale_Glitch_0; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h new file mode 100755 index 00000000000..fd3cb1ed242 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPTMR_H_ +#define _FSL_LPTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lptmr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief LPTMR pin selection, used in pulse counter mode.*/ +typedef enum _lptmr_pin_select +{ + kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ + kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ + kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ + kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity, used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity +{ + kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ + kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode +{ + kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ + kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler/glitch filter values*/ +typedef enum _lptmr_prescaler_glitch_value +{ + kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ + kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ + kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ + kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ + kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ + kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ + kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ + kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ + kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ + kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ + kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ + kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ + kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ + kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ + kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ + kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ +} lptmr_prescaler_glitch_value_t; + +/*! + * @brief LPTMR prescaler/glitch filter clock select. + * @note Clock connections are SoC-specific + */ +typedef enum _lptmr_prescaler_clock_select +{ + kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ + kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ + kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ + kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +} lptmr_prescaler_clock_select_t; + +/*! @brief List of LPTMR interrupts */ +typedef enum _lptmr_interrupt_enable +{ + kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ +} lptmr_interrupt_enable_t; + +/*! @brief List of LPTMR status flags */ +typedef enum _lptmr_status_flags +{ + kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ +} lptmr_status_flags_t; + +/*! + * @brief LPTMR config structure + * + * This structure holds the configuration settings for the LPTMR peripheral. To initialize this + * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _lptmr_config +{ + lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ + lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ + lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ + bool enableFreeRunning; /*!< true: enable free running, counter is reset on overflow + false: counter is reset when the compare flag is set */ + bool bypassPrescaler; /*!< true: bypass prescaler; false: use clock from prescaler */ + lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ + lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ +} lptmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungate the LPTMR clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the LPTMR driver. + * + * @param base LPTMR peripheral base address + * @param config Pointer to user's LPTMR config structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); + +/*! + * @brief Gate the LPTMR clock + * + * @param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base); + +/*! + * @brief Fill in the LPTMR config struct with the default settings + * + * The default values are: + * @code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * @endcode + * @param config Pointer to user's LPTMR config structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! + * @brief Disables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + base->CSR &= ~mask; +} + +/*! + * @brief Gets the enabled LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPTMR status flags + * + * @param base LPTMR peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TCF_MASK); +} + +/*! + * @brief Clears the LPTMR status flags + * + * @param base LPTMR peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers counts from 0 till it equals the count value set here. The count value is written to + * the CMR register. + * + * @note + * 1. The TCF flag is set with the CNR equals the count provided here and then increments. + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base LPTMR peripheral base address + * @param ticks Timer period in units of ticks + */ +static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks) +{ + base->CMR = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base LPTMR peripheral base address + * + * @return Current counter value in ticks + */ +static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) +{ + /* Must first write any value to the CNR. This will synchronize and register the current value + * of the CNR into a temporary register which can then be read + */ + base->CNR = 0U; + return (uint16_t)base->CNR; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, the timer counts up to the CMR register value. + * Each time the timer reaches CMR value and then increments, it generates a + * trigger pulse and sets the timeout interrupt flag. An interrupt will also be + * triggered if the timer interrupt is enabled. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StartTimer(LPTMR_Type *base) +{ + base->CSR |= LPTMR_CSR_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer counting and resets the timer's counter register + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StopTimer(LPTMR_Type *base) +{ + base->CSR &= ~LPTMR_CSR_TEN_MASK; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPTMR_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c new file mode 100755 index 00000000000..926eff9641f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_mpu.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Defines the register numbers of the region descriptor configure. */ +#define MPU_REGIONDESCRIPTOR_WROD_REGNUM (4U) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const clock_ip_name_t g_mpuClock[FSL_FEATURE_SOC_MPU_COUNT] = MPU_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void MPU_Init(MPU_Type *base, const mpu_config_t *config) +{ + assert(config); + uint8_t count; + + /* Un-gate MPU clock */ + CLOCK_EnableClock(g_mpuClock[0]); + + /* Initializes the regions. */ + for (count = 1; count < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; count++) + { + base->WORD[count][3] = 0; /* VLD/VID+PID. */ + base->WORD[count][0] = 0; /* Start address. */ + base->WORD[count][1] = 0; /* End address. */ + base->WORD[count][2] = 0; /* Access rights. */ + base->RGDAAC[count] = 0; /* Alternate access rights. */ + } + + /* MPU configure. */ + while (config) + { + MPU_SetRegionConfig(base, &(config->regionConfig)); + config = config->next; + } + /* Enable MPU. */ + MPU_Enable(base, true); +} + +void MPU_Deinit(MPU_Type *base) +{ + /* Disable MPU. */ + MPU_Enable(base, false); + + /* Gate the clock. */ + CLOCK_DisableClock(g_mpuClock[0]); +} + +void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform) +{ + assert(hardwareInform); + + uint32_t cesReg = base->CESR; + + hardwareInform->hardwareRevisionLevel = (cesReg & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT; + hardwareInform->slavePortsNumbers = (cesReg & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT; + hardwareInform->regionsNumbers = (mpu_region_total_num_t)((cesReg & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT); +} + +void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig) +{ + assert(regionConfig); + + uint32_t wordReg = 0; + uint8_t count; + uint8_t number = regionConfig->regionNum; + + /* The start and end address of the region descriptor. */ + base->WORD[number][0] = regionConfig->startAddress; + base->WORD[number][1] = regionConfig->endAddress; + + /* The region descriptor access rights control. */ + for (count = 0; count < MPU_REGIONDESCRIPTOR_WROD_REGNUM; count++) + { + wordReg |= MPU_WORD_LOW_MASTER(count, (((uint32_t)regionConfig->accessRights1[count].superAccessRights << 3U) | + (uint8_t)regionConfig->accessRights1[count].userAccessRights)) | + MPU_WORD_HIGH_MASTER(count, ((uint32_t)regionConfig->accessRights2[count].readEnable << 1U | + (uint8_t)regionConfig->accessRights2[count].writeEnable)); + +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + wordReg |= MPU_WORD_MASTER_PE(count, regionConfig->accessRights1[count].processIdentifierEnable); +#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ + } + + /* Set region descriptor access rights. */ + base->WORD[number][2] = wordReg; + + wordReg = MPU_WORD_VLD(1); +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + wordReg |= MPU_WORD_PID(regionConfig->processIdentifier) | MPU_WORD_PIDMASK(regionConfig->processIdMask); +#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ + + base->WORD[number][3] = wordReg; +} + +void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr) +{ + base->WORD[regionNum][0] = startAddr; + base->WORD[regionNum][1] = endAddr; +} + +void MPU_SetRegionLowMasterAccessRights(MPU_Type *base, + mpu_region_num_t regionNum, + mpu_master_t masterNum, + const mpu_low_masters_access_rights_t *accessRights) +{ + assert(accessRights); +#if FSL_FEATURE_MPU_HAS_MASTER4 + assert(masterNum < kMPU_Master4); +#endif + uint32_t mask = MPU_WORD_LOW_MASTER_MASK(masterNum); + uint32_t right = base->RGDAAC[regionNum]; + +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + mask |= MPU_LOW_MASTER_PE_MASK(masterNum); +#endif + + /* Build rights control value. */ + right &= ~mask; + right |= MPU_WORD_LOW_MASTER(masterNum, + ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights)); +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + right |= MPU_WORD_MASTER_PE(masterNum, accessRights->processIdentifierEnable); +#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ + + /* Set low master region access rights. */ + base->RGDAAC[regionNum] = right; +} + +void MPU_SetRegionHighMasterAccessRights(MPU_Type *base, + mpu_region_num_t regionNum, + mpu_master_t masterNum, + const mpu_high_masters_access_rights_t *accessRights) +{ + assert(accessRights); +#if FSL_FEATURE_MPU_HAS_MASTER3 + assert(masterNum > kMPU_Master3); +#endif + uint32_t mask = MPU_WORD_HIGH_MASTER_MASK(masterNum); + uint32_t right = base->RGDAAC[regionNum]; + + /* Build rights control value. */ + right &= ~mask; + right |= MPU_WORD_HIGH_MASTER((masterNum - (uint8_t)kMPU_RegionNum04), + (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable)); + /* Set low master region access rights. */ + base->RGDAAC[regionNum] = right; +} + +bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum) +{ + uint8_t sperr; + + sperr = ((base->CESR & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT) & (0x1U << slaveNum); + + return (sperr != 0) ? true : false; +} + +void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform) +{ + assert(errInform); + + uint16_t value; + + /* Error address. */ + errInform->address = base->SP[slaveNum].EAR; + + /* Error detail information. */ + value = (base->SP[slaveNum].EDR & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT; + if (!value) + { + errInform->accessControl = kMPU_NoRegionHit; + } + else if (!(value & (uint16_t)(value - 1))) + { + errInform->accessControl = kMPU_NoneOverlappRegion; + } + else + { + errInform->accessControl = kMPU_OverlappRegion; + } + + value = base->SP[slaveNum].EDR; + errInform->master = (mpu_master_t)((value & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT); + errInform->attributes = (mpu_err_attributes_t)((value & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT); + errInform->accessType = (mpu_err_access_type_t)((value & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT); +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + errInform->processorIdentification = (uint8_t)((value & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT); +#endif + + /*!< Clears error slave port bit. */ + value = (base->CESR & ~MPU_CESR_SPERR_MASK) | (0x1U << slaveNum); + base->CESR = value; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h new file mode 100755 index 00000000000..acdcfd1be38 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_MPU_H_ +#define _FSL_MPU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mpu + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief MPU driver version 2.0.0. */ +#define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief MPU low master bit shift. */ +#define MPU_WORD_LOW_MASTER_SHIFT(n) (n * 6) + +/*! @brief MPU low master bit mask. */ +#define MPU_WORD_LOW_MASTER_MASK(n) (0x1Fu << MPU_WORD_LOW_MASTER_SHIFT(n)) + +/*! @brief MPU low master bit width. */ +#define MPU_WORD_LOW_MASTER_WIDTH 5 + +/*! @brief MPU low master priority setting. */ +#define MPU_WORD_LOW_MASTER(n, x) \ + (((uint32_t)(((uint32_t)(x)) << MPU_WORD_LOW_MASTER_SHIFT(n))) & MPU_WORD_LOW_MASTER_MASK(n)) + +/*! @brief MPU low master process enable bit shift. */ +#define MPU_LOW_MASTER_PE_SHIFT(n) (n * 6 + 5) + +/*! @brief MPU low master process enable bit mask. */ +#define MPU_LOW_MASTER_PE_MASK(n) (0x1u << MPU_LOW_MASTER_PE_SHIFT(n)) + +/*! @brief MPU low master process enable width. */ +#define MPU_WORD_MASTER_PE_WIDTH 1 + +/*! @brief MPU low master process enable setting. */ +#define MPU_WORD_MASTER_PE(n, x) \ + (((uint32_t)(((uint32_t)(x)) << MPU_LOW_MASTER_PE_SHIFT(n))) & MPU_LOW_MASTER_PE_MASK(n)) + +/*! @brief MPU high master bit shift. */ +#define MPU_WORD_HIGH_MASTER_SHIFT(n) (n * 2 + 24) + +/*! @brief MPU high master bit mask. */ +#define MPU_WORD_HIGH_MASTER_MASK(n) (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n)) + +/*! @brief MPU high master bit width. */ +#define MPU_WORD_HIGH_MASTER_WIDTH 2 + +/*! @brief MPU high master priority setting. */ +#define MPU_WORD_HIGH_MASTER(n, x) \ + (((uint32_t)(((uint32_t)(x)) << MPU_WORD_HIGH_MASTER_SHIFT(n))) & MPU_WORD_HIGH_MASTER_MASK(n)) + +/*! @brief MPU region number. */ +typedef enum _mpu_region_num +{ +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U + kMPU_RegionNum00 = 0U, /*!< MPU region number 0. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U + kMPU_RegionNum01 = 1U, /*!< MPU region number 1. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U + kMPU_RegionNum02 = 2U, /*!< MPU region number 2. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U + kMPU_RegionNum03 = 3U, /*!< MPU region number 3. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U + kMPU_RegionNum04 = 4U, /*!< MPU region number 4. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U + kMPU_RegionNum05 = 5U, /*!< MPU region number 5. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U + kMPU_RegionNum06 = 6U, /*!< MPU region number 6. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U + kMPU_RegionNum07 = 7U, /*!< MPU region number 7. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U + kMPU_RegionNum08 = 8U, /*!< MPU region number 8. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U + kMPU_RegionNum09 = 9U, /*!< MPU region number 9. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U + kMPU_RegionNum10 = 10U, /*!< MPU region number 10. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U + kMPU_RegionNum11 = 11U, /*!< MPU region number 11. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U + kMPU_RegionNum12 = 12U, /*!< MPU region number 12. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U + kMPU_RegionNum13 = 13U, /*!< MPU region number 13. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U + kMPU_RegionNum14 = 14U, /*!< MPU region number 14. */ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U + kMPU_RegionNum15 = 15U, /*!< MPU region number 15. */ +#endif +} mpu_region_num_t; + +/*! @brief MPU master number. */ +typedef enum _mpu_master +{ +#if FSL_FEATURE_MPU_HAS_MASTER0 + kMPU_Master0 = 0U, /*!< MPU master core. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER1 + kMPU_Master1 = 1U, /*!< MPU master defined in SoC. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER2 + kMPU_Master2 = 2U, /*!< MPU master defined in SoC. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER3 + kMPU_Master3 = 3U, /*!< MPU master defined in SoC. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER4 + kMPU_Master4 = 4U, /*!< MPU master defined in SoC. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER5 + kMPU_Master5 = 5U, /*!< MPU master defined in SoC. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER6 + kMPU_Master6 = 6U, /*!< MPU master defined in SoC. */ +#endif +#if FSL_FEATURE_MPU_HAS_MASTER7 + kMPU_Master7 = 7U /*!< MPU master defined in SoC. */ +#endif +} mpu_master_t; + +/*! @brief Describes the number of MPU regions. */ +typedef enum _mpu_region_total_num +{ + kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */ + kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */ + kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */ +} mpu_region_total_num_t; + +/*! @brief MPU slave port number. */ +typedef enum _mpu_slave +{ + kMPU_Slave0 = 4U, /*!< MPU slave port 0. */ + kMPU_Slave1 = 3U, /*!< MPU slave port 1. */ + kMPU_Slave2 = 2U, /*!< MPU slave port 2. */ + kMPU_Slave3 = 1U, /*!< MPU slave port 3. */ + kMPU_Slave4 = 0U /*!< MPU slave port 4. */ +} mpu_slave_t; + +/*! @brief MPU error access control detail. */ +typedef enum _mpu_err_access_control +{ + kMPU_NoRegionHit = 0U, /*!< No region hit error. */ + kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */ + kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */ +} mpu_err_access_control_t; + +/*! @brief MPU error access type. */ +typedef enum _mpu_err_access_type +{ + kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */ + kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */ +} mpu_err_access_type_t; + +/*! @brief MPU access error attributes.*/ +typedef enum _mpu_err_attributes +{ + kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */ + kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */ + kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */ + kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */ +} mpu_err_attributes_t; + +/*! @brief MPU access rights in supervisor mode for master port 0 ~ port 3. */ +typedef enum _mpu_supervisor_access_rights +{ + kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */ + kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */ + kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */ + kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */ +} mpu_supervisor_access_rights_t; + +/*! @brief MPU access rights in user mode for master port 0 ~ port 3. */ +typedef enum _mpu_user_access_rights +{ + kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */ + kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */ + kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */ + kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */ + kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */ + kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */ + kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */ + kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */ +} mpu_user_access_rights_t; + +/*! @brief MPU hardware basic information. */ +typedef struct _mpu_hardware_info +{ + uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */ + uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */ + mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */ +} mpu_hardware_info_t; + +/*! @brief MPU detail error access information. */ +typedef struct _mpu_access_err_info +{ + mpu_master_t master; /*!< Access error master. */ + mpu_err_attributes_t attributes; /*!< Access error attributes. */ + mpu_err_access_type_t accessType; /*!< Access error type. */ + mpu_err_access_control_t accessControl; /*!< Access error control. */ + uint32_t address; /*!< Access error address. */ +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + uint8_t processorIdentification; /*!< Access error processor identification. */ +#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ +} mpu_access_err_info_t; + +/*! @brief MPU access rights for low master master port 0 ~ port 3. */ +typedef struct _mpu_low_masters_access_rights +{ + mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */ + mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */ +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + bool processIdentifierEnable; /*!< Enables or disables process identifier. */ +#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ +} mpu_low_masters_access_rights_t; + +/*! @brief MPU access rights mode for high master port 4 ~ port 7. */ +typedef struct _mpu_high_masters_access_rights +{ + bool writeEnable; /*!< Enables or disables write permission. */ + bool readEnable; /*!< Enables or disables read permission. */ +} mpu_high_masters_access_rights_t; + +/*! + * @brief MPU region configuration structure. + * + * This structure is used to configure the regionNum region. + * The accessRights1[0] ~ accessRights1[3] are used to configure the four low master + * numbers: master 0 ~ master 3. The accessRights2[0] ~ accessRights2[3] are + * used to configure the four high master numbers: master 4 ~ master 7. + * The master port assignment is the chip configuration. Normally, the core is the + * master 0, debugger is the master 1. + * Note: MPU assigns a priority scheme where the debugger is treated as the highest + * priority master followed by the core and then all the remaining masters. + * MPU protection does not allow writes from the core to affect the "regionNum 0" start + * and end address nor the permissions associated with the debugger. It can only write + * the permission fields associated with the other masters. This protection guarantee + * the debugger always has access to the entire address space and those rights can't + * be changed by the core or any other bus master. Prepare + * the region configuration when regionNum is kMPU_RegionNum00. + */ +typedef struct _mpu_region_config +{ + mpu_region_num_t regionNum; /*!< MPU region number. */ + uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual + start address is 0-modulo-32 byte address. */ + uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end + address is 31-modulo-32 byte address. */ + mpu_low_masters_access_rights_t accessRights1[4]; /*!< Low masters access permission. */ + mpu_high_masters_access_rights_t accessRights2[4]; /*!< High masters access permission. */ +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */ + uint8_t + processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */ +#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ +} mpu_region_config_t; + +/*! + * @brief The configuration structure for the MPU initialization. + * + * This structure is used when calling the MPU_Init function. + */ +typedef struct _mpu_config +{ + mpu_region_config_t regionConfig; /*!< region access permission. */ + struct _mpu_config *next; /*!< pointer to the next structure. */ +} mpu_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the MPU with the user configuration structure. + * + * This function configures the MPU module with the user-defined configuration. + * + * @param base MPU peripheral base address. + * @param config The pointer to the configuration structure. + */ +void MPU_Init(MPU_Type *base, const mpu_config_t *config); + +/*! + * @brief Deinitializes the MPU regions. + * + * @param base MPU peripheral base address. + */ +void MPU_Deinit(MPU_Type *base); + +/* @}*/ + +/*! + * @name Basic Control Operations + * @{ + */ + +/*! + * @brief Enables/disables the MPU globally. + * + * Call this API to enable or disable the MPU module. + * + * @param base MPU peripheral base address. + * @param enable True enable MPU, false disable MPU. + */ +static inline void MPU_Enable(MPU_Type *base, bool enable) +{ + if (enable) + { + /* Enable the MPU globally. */ + base->CESR |= MPU_CESR_VLD_MASK; + } + else + { /* Disable the MPU globally. */ + base->CESR &= ~MPU_CESR_VLD_MASK; + } +} + +/*! + * @brief Enables/disables the MPU for a special region. + * + * When MPU is enabled, call this API to disable an unused region + * of an enabled MPU. Call this API to minimize the power dissipation. + * + * @param base MPU peripheral base address. + * @param number MPU region number. + * @param enable True enable the special region MPU, false disable the special region MPU. + */ +static inline void MPU_RegionEnable(MPU_Type *base, mpu_region_num_t number, bool enable) +{ + if (enable) + { + /* Enable the #number region MPU. */ + base->WORD[number][3] |= MPU_WORD_VLD_MASK; + } + else + { /* Disable the #number region MPU. */ + base->WORD[number][3] &= ~MPU_WORD_VLD_MASK; + } +} + +/*! + * @brief Gets the MPU basic hardware information. + * + * @param base MPU peripheral base address. + * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t". + */ +void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform); + +/*! + * @brief Sets the MPU region. + * + * Note: Due to the MPU protection, the kMPU_RegionNum00 does not allow writes from the + * core to affect the start and end address nor the permissions associated with + * the debugger. It can only write the permission fields associated + * with the other masters. + * + * @param base MPU peripheral base address. + * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t". + */ +void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig); + +/*! + * @brief Sets the region start and end address. + * + * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU. + * The actual start address by MPU is 0-modulo-32 byte address. + * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. + * The actual end address used by MPU is 31-modulo-32 byte address. + * Note: Due to the MPU protection, the startAddr and endAddr can't be + * changed by the core when regionNum is "kMPU_RegionNum00". + * + * @param base MPU peripheral base address. + * @param regionNum MPU region number. + * @param startAddr Region start address. + * @param endAddr Region end address. + */ +void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr); + +/*! + * @brief Sets the MPU region access rights for low master port 0 ~ port 3. + * This can be used to change the region access rights for any master port for any region. + * + * @param base MPU peripheral base address. + * @param regionNum MPU region number. + * @param masterNum MPU master number. Should range from kMPU_Master0 ~ kMPU_Master3. + * @param accessRights The pointer to the MPU access rights configuration. See "mpu_low_masters_access_rights_t". + */ +void MPU_SetRegionLowMasterAccessRights(MPU_Type *base, + mpu_region_num_t regionNum, + mpu_master_t masterNum, + const mpu_low_masters_access_rights_t *accessRights); + +/*! + * @brief Sets the MPU region access rights for high master port 4 ~ port 7. + * This can be used to change the region access rights for any master port for any region. + * + * @param base MPU peripheral base address. + * @param regionNum MPU region number. + * @param masterNum MPU master number. Should range from kMPU_Master4 ~ kMPU_Master7. + * @param accessRights The pointer to the MPU access rights configuration. See "mpu_high_masters_access_rights_t". + */ +void MPU_SetRegionHighMasterAccessRights(MPU_Type *base, + mpu_region_num_t regionNum, + mpu_master_t masterNum, + const mpu_high_masters_access_rights_t *accessRights); + +/*! + * @brief Gets the numbers of slave ports where errors occur. + * + * @param base MPU peripheral base address. + * @param slaveNum MPU slave port number. + * @return The slave ports error status. + * true - error happens in this slave port. + * false - error didn't happen in this slave port. + */ +bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum); + +/*! + * @brief Gets the MPU detailed error access information. + * + * @param base MPU peripheral base address. + * @param slaveNum MPU slave port number. + * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t". + */ +void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MPU_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c new file mode 100755 index 00000000000..b5c9b88ec6c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pdb.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for PDB module. + * + * @param base PDB peripheral base address + */ +static uint32_t PDB_GetInstance(PDB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PDB bases for each instance. */ +static PDB_Type *const s_pdbBases[] = PDB_BASE_PTRS; +/*! @brief Pointers to PDB clocks for each instance. */ +const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t PDB_GetInstance(PDB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_PDB_COUNT; instance++) + { + if (s_pdbBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_PDB_COUNT); + + return instance; +} + +void PDB_Init(PDB_Type *base, const pdb_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Enable the clock. */ + CLOCK_EnableClock(s_pdbClocks[PDB_GetInstance(base)]); + + /* Configure. */ + /* PDBx_SC. */ + tmp32 = base->SC & + ~(PDB_SC_LDMOD_MASK | PDB_SC_PRESCALER_MASK | PDB_SC_TRGSEL_MASK | PDB_SC_MULT_MASK | PDB_SC_CONT_MASK); + + tmp32 |= PDB_SC_LDMOD(config->loadValueMode) | PDB_SC_PRESCALER(config->prescalerDivider) | + PDB_SC_TRGSEL(config->triggerInputSource) | PDB_SC_MULT(config->dividerMultiplicationFactor); + if (config->enableContinuousMode) + { + tmp32 |= PDB_SC_CONT_MASK; + } + base->SC = tmp32; + + PDB_Enable(base, true); /* Enable the PDB module. */ +} + +void PDB_Deinit(PDB_Type *base) +{ + PDB_Enable(base, false); /* Disable the PDB module. */ + + /* Disable the clock. */ + CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]); +} + +void PDB_GetDefaultConfig(pdb_config_t *config) +{ + assert(NULL != config); + + config->loadValueMode = kPDB_LoadValueImmediately; + config->prescalerDivider = kPDB_PrescalerDivider1; + config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + config->triggerInputSource = kPDB_TriggerSoftware; + config->enableContinuousMode = false; +} + +#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC +void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config) +{ + assert(channel < PDB_INTC_COUNT); + assert(NULL != config); + + uint32_t tmp32 = 0U; + + /* PDBx_DACINTC. */ + if (config->enableExternalTriggerInput) + { + tmp32 |= PDB_INTC_EXT_MASK; + } + if (config->enableIntervalTrigger) + { + tmp32 |= PDB_INTC_TOE_MASK; + } + base->DAC[channel].INTC = tmp32; +} +#endif /* FSL_FEATURE_PDB_HAS_DAC */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h new file mode 100755 index 00000000000..1f05b61b26b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h @@ -0,0 +1,576 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PDB_H_ +#define _FSL_PDB_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pdb + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PDB driver version 2.0.1. */ +#define FSL_PDB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief PDB flags. + */ +enum _pdb_status_flags +{ + kPDB_LoadOKFlag = PDB_SC_LDOK_MASK, /*!< This flag is automatically cleared when the values in buffers are + loaded into the internal registers after the LDOK bit is set or the + PDBEN is cleared. */ + kPDB_DelayEventFlag = PDB_SC_PDBIF_MASK, /*!< PDB timer delay event flag. */ +}; + +/*! + * @brief PDB ADC PreTrigger channel flags. + */ +enum _pdb_adc_pretrigger_flags +{ + /* PDB PreTrigger channel match flags. */ + kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-Trigger 0 flag. */ + kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-Trigger 1 flag. */ +#if (PDB_DLY_COUNT > 2) + kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-Trigger 2 flag. */ + kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-Trigger 3 flag. */ +#endif /* PDB_DLY_COUNT > 2 */ +#if (PDB_DLY_COUNT > 4) + kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-Trigger 4 flag. */ + kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-Trigger 5 flag. */ + kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-Trigger 6 flag. */ + kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-Trigger 7 flag. */ +#endif /* PDB_DLY_COUNT > 4 */ + + /* PDB PreTrigger channel error flags. */ + kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-Trigger 0 Error. */ + kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-Trigger 1 Error. */ +#if (PDB_DLY_COUNT > 2) + kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-Trigger 2 Error. */ + kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-Trigger 3 Error. */ +#endif /* PDB_DLY_COUNT > 2 */ +#if (PDB_DLY_COUNT > 4) + kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-Trigger 4 Error. */ + kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-Trigger 5 Error. */ + kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-Trigger 6 Error. */ + kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-Trigger 7 Error. */ +#endif /* PDB_DLY_COUNT > 4 */ +}; + +/*! + * @brief PDB buffer interrupts. + */ +enum _pdb_interrupt_enable +{ + kPDB_SequenceErrorInterruptEnable = PDB_SC_PDBEIE_MASK, /*!< PDB sequence error interrupt enable. */ + kPDB_DelayInterruptEnable = PDB_SC_PDBIE_MASK, /*!< PDB delay interrupt enable. */ +}; + +/*! + * @brief PDB load value mode. + * + * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]). + * These values are for: + * - PDB counter (PDBx_MOD, PDBx_IDLY) + * - ADC trigger (PDBx_CHnDLYm) + * - DAC trigger (PDBx_DACINTx) + * - CMP trigger (PDBx_POyDLY) + */ +typedef enum _pdb_load_value_mode +{ + kPDB_LoadValueImmediately = 0U, /*!< Load immediately after 1 is written to LDOK. */ + kPDB_LoadValueOnCounterOverflow = 1U, /*!< Load when the PDB counter overflows (reaches the MOD + register value). */ + kPDB_LoadValueOnTriggerInput = 2U, /*!< Load a trigger input event is detected. */ + kPDB_LoadValueOnCounterOverflowOrTriggerInput = 3U, /*!< Load either when the PDB counter overflows or a trigger + input is detected. */ +} pdb_load_value_mode_t; + +/*! + * @brief Prescaler divider. + * + * Counting uses the peripheral clock divided by multiplication factor selected by times of MULT. + */ +typedef enum _pdb_prescaler_divider +{ + kPDB_PrescalerDivider1 = 0U, /*!< Divider x1. */ + kPDB_PrescalerDivider2 = 1U, /*!< Divider x2. */ + kPDB_PrescalerDivider4 = 2U, /*!< Divider x4. */ + kPDB_PrescalerDivider8 = 3U, /*!< Divider x8. */ + kPDB_PrescalerDivider16 = 4U, /*!< Divider x16. */ + kPDB_PrescalerDivider32 = 5U, /*!< Divider x32. */ + kPDB_PrescalerDivider64 = 6U, /*!< Divider x64. */ + kPDB_PrescalerDivider128 = 7U, /*!< Divider x128. */ +} pdb_prescaler_divider_t; + +/*! + * @brief Multiplication factor select for prescaler. + * + * Selects the multiplication factor of the prescaler divider for the counter clock. + */ +typedef enum _pdb_divider_multiplication_factor +{ + kPDB_DividerMultiplicationFactor1 = 0U, /*!< Multiplication factor is 1. */ + kPDB_DividerMultiplicationFactor10 = 1U, /*!< Multiplication factor is 10. */ + kPDB_DividerMultiplicationFactor20 = 2U, /*!< Multiplication factor is 20. */ + kPDB_DividerMultiplicationFactor40 = 3U, /*!< Multiplication factor is 40. */ +} pdb_divider_multiplication_factor_t; + +/*! + * @brief Trigger input source + * + * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or + * the software trigger. Refer to chip configuration details for the actual PDB input trigger connections. + */ +typedef enum _pdb_trigger_input_source +{ + kPDB_TriggerInput0 = 0U, /*!< Trigger-In 0. */ + kPDB_TriggerInput1 = 1U, /*!< Trigger-In 1. */ + kPDB_TriggerInput2 = 2U, /*!< Trigger-In 2. */ + kPDB_TriggerInput3 = 3U, /*!< Trigger-In 3. */ + kPDB_TriggerInput4 = 4U, /*!< Trigger-In 4. */ + kPDB_TriggerInput5 = 5U, /*!< Trigger-In 5. */ + kPDB_TriggerInput6 = 6U, /*!< Trigger-In 6. */ + kPDB_TriggerInput7 = 7U, /*!< Trigger-In 7. */ + kPDB_TriggerInput8 = 8U, /*!< Trigger-In 8. */ + kPDB_TriggerInput9 = 9U, /*!< Trigger-In 9. */ + kPDB_TriggerInput10 = 10U, /*!< Trigger-In 10. */ + kPDB_TriggerInput11 = 11U, /*!< Trigger-In 11. */ + kPDB_TriggerInput12 = 12U, /*!< Trigger-In 12. */ + kPDB_TriggerInput13 = 13U, /*!< Trigger-In 13. */ + kPDB_TriggerInput14 = 14U, /*!< Trigger-In 14. */ + kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15. */ +} pdb_trigger_input_source_t; + +/*! + * @brief PDB module configuration. + */ +typedef struct _pdb_config +{ + pdb_load_value_mode_t loadValueMode; /*!< Select the load value mode. */ + pdb_prescaler_divider_t prescalerDivider; /*!< Select the prescaler divider. */ + pdb_divider_multiplication_factor_t dividerMultiplicationFactor; /*!< Multiplication factor select for prescaler. */ + pdb_trigger_input_source_t triggerInputSource; /*!< Select the trigger input source. */ + bool enableContinuousMode; /*!< Enable the PDB operation in Continuous mode.*/ +} pdb_config_t; + +/*! + * @brief PDB ADC Pre-Trigger configuration. + */ +typedef struct _pdb_adc_pretrigger_config +{ + uint32_t enablePreTriggerMask; /*!< PDB Channel Pre-Trigger Enable. */ + uint32_t enableOutputMask; /*!< PDB Channel Pre-Trigger Output Select. + PDB channel's corresponding pre-trigger asserts when the counter + reaches the channel delay register. */ + uint32_t enableBackToBackOperationMask; /*!< PDB Channel Pre-Trigger Back-to-Back Operation Enable. + Back-to-back operation enables the ADC conversions complete to trigger + the next PDB channel pre-trigger and trigger output, so that the ADC + conversions can be triggered on next set of configuration and results + registers.*/ +} pdb_adc_pretrigger_config_t; + +/*! + * @brief PDB DAC trigger configuration. + */ +typedef struct _pdb_dac_trigger_config +{ + bool enableExternalTriggerInput; /*!< Enables the external trigger for DAC interval counter. */ + bool enableIntervalTrigger; /*!< Enables the DAC interval trigger. */ +} pdb_dac_trigger_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the PDB module. + * + * This function is to make the initialization for PDB module. The operations includes are: + * - Enable the clock for PDB instance. + * - Configure the PDB module. + * - Enable the PDB module. + * + * @param base PDB peripheral base address. + * @param config Pointer to configuration structure. See "pdb_config_t". + */ +void PDB_Init(PDB_Type *base, const pdb_config_t *config); + +/*! + * @brief De-initializes the PDB module. + * + * @param base PDB peripheral base address. + */ +void PDB_Deinit(PDB_Type *base); + +/*! + * @brief Initializes the PDB user configure structure. + * + * This function initializes the user configure structure to default value. the default value are: + * @code + * config->loadValueMode = kPDB_LoadValueImmediately; + * config->prescalerDivider = kPDB_PrescalerDivider1; + * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + * config->triggerInputSource = kPDB_TriggerSoftware; + * config->enableContinuousMode = false; + * @endcode + * @param config Pointer to configuration structure. See "pdb_config_t". + */ +void PDB_GetDefaultConfig(pdb_config_t *config); + +/*! + * @brief Enables the PDB module. + * + * @param base PDB peripheral base address. + * @param enable Enable the module or not. + */ +static inline void PDB_Enable(PDB_Type *base, bool enable) +{ + if (enable) + { + base->SC |= PDB_SC_PDBEN_MASK; + } + else + { + base->SC &= ~PDB_SC_PDBEN_MASK; + } +} + +/* @} */ + +/*! + * @name Basic Counter + * @{ + */ + +/*! + * @brief Triggers the PDB counter by software. + * + * @param base PDB peripheral base address. + */ +static inline void PDB_DoSoftwareTrigger(PDB_Type *base) +{ + base->SC |= PDB_SC_SWTRIG_MASK; +} + +/*! + * @brief Loads the counter values. + * + * This function is to load the counter values from their internal buffer. + * See "pdb_load_value_mode_t" about PDB's load mode. + * + * @param base PDB peripheral base address. + */ +static inline void PDB_DoLoadValues(PDB_Type *base) +{ + base->SC |= PDB_SC_LDOK_MASK; +} + +/*! + * @brief Enables the DMA for the PDB module. + * + * @param base PDB peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PDB_EnableDMA(PDB_Type *base, bool enable) +{ + if (enable) + { + base->SC |= PDB_SC_DMAEN_MASK; + } + else + { + base->SC &= ~PDB_SC_DMAEN_MASK; + } +} + +/*! + * @brief Enables the interrupts for the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". + */ +static inline void PDB_EnableInterrupts(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); + + base->SC |= mask; +} + +/*! + * @brief Disables the interrupts for the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". + */ +static inline void PDB_DisableInterrupts(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); + + base->SC &= ~mask; +} + +/*! + * @brief Gets the status flags of the PDB module. + * + * @param base PDB peripheral base address. + * + * @return Mask value for asserted flags. See "_pdb_status_flags". + */ +static inline uint32_t PDB_GetStatusFlags(PDB_Type *base) +{ + return base->SC & (PDB_SC_PDBIF_MASK | PDB_SC_LDOK_MASK); +} + +/*! + * @brief Clears the status flags of the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value of flags. See "_pdb_status_flags". + */ +static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~PDB_SC_PDBIF_MASK)); + + base->SC &= ~mask; +} + +/*! + * @brief Specifies the period of the counter. + * + * @param base PDB peripheral base address. + * @param value Setting value for the modulus. 16-bit is available. + */ +static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value) +{ + base->MOD = PDB_MOD_MOD(value); +} + +/*! + * @brief Gets the PDB counter's current value. + * + * @param base PDB peripheral base address. + * + * @return PDB counter's current value. + */ +static inline uint32_t PDB_GetCounterValue(PDB_Type *base) +{ + return base->CNT; +} + +/*! + * @brief Sets the value for PDB counter delay event. + * + * @param base PDB peripheral base address. + * @param value Setting value for PDB counter delay event. 16-bit is available. + */ +static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value) +{ + base->IDLY = PDB_IDLY_IDLY(value); +} +/* @} */ + +/*! + * @name ADC Pre-Trigger + * @{ + */ + +/*! + * @brief Configures the ADC PreTrigger in PDB module. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param config Pointer to configuration structure. See "pdb_adc_pretrigger_config_t". + */ +static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config) +{ + assert(channel < PDB_C1_COUNT); + assert(NULL != config); + + base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) | + PDB_C1_EN(config->enableOutputMask); +} + +/*! + * @brief Sets the value for ADC Pre-Trigger delay event. + * + * This function is to set the value for ADC Pre-Trigger delay event. IT Specifies the delay value for the channel's + * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the setting value here. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param preChannel Channel group index for ADC instance. + * @param value Setting value for ADC Pre-Trigger delay event. 16-bit is available. + */ +static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value) +{ + assert(channel < PDB_C1_COUNT); + assert(preChannel < PDB_DLY_COUNT); + + base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value); +} + +/*! + * @brief Gets the ADC Pre-Trigger's status flags. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * + * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags". + */ +static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel) +{ + assert(channel < PDB_C1_COUNT); + + return base->CH[channel].S; +} + +/*! + * @brief Clears the ADC Pre-Trigger's status flags. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags". + */ +static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < PDB_C1_COUNT); + + base->CH[channel].S &= ~mask; +} + +/* @} */ + +#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC +/*! + * @name DAC Interval Trigger + * @{ + */ + +/*! + * @brief Configures the DAC trigger in PDB module. + * + * @param base PDB peripheral base address. + * @param channel Channel index for DAC instance. + * @param config Pointer to configuration structure. See "pdb_dac_trigger_config_t". + */ +void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config); + +/*! + * @brief Sets the value for the DAC interval event. + * + * This fucntion is to set the value for DAC interval event. DAC interval trigger would trigger the DAC module to update + * buffer when the DAC interval counter is equal to the setting value here. + * + * @param base PDB peripheral base address. + * @param channel Channel index for DAC instance. + * @param value Setting value for the DAC interval event. + */ +static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value) +{ + assert(channel < PDB_INT_COUNT); + + base->DAC[channel].INT = PDB_INT_INT(value); +} + +/* @} */ +#endif /* FSL_FEATURE_PDB_HAS_DAC */ + +/*! + * @name Pulse-Out Trigger + * @{ + */ + +/*! + * @brief Enables the pulse out trigger channels. + * + * @param base PDB peripheral base address. + * @param channelMask Channel mask value for multiple pulse out trigger channel. + * @param enable Enable the feature or not. + */ +static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable) +{ + if (enable) + { + base->POEN |= PDB_POEN_POEN(channelMask); + } + else + { + base->POEN &= ~(PDB_POEN_POEN(channelMask)); + } +} + +/*! + * @brief Sets event values for pulse out trigger. + * + * This function is used to set event values for pulse output trigger. + * These pulse output trigger delay values specify the delay for the PDB Pulse-Out. Pulse-Out goes high when the PDB + * counter is equal to the pulse output high value (value1). Pulse-Out goes low when the PDB counter is equal to the + * pulse output low value (value2). + * + * @param base PDB peripheral base address. + * @param channel Channel index for pulse out trigger channel. + * @param value1 Setting value for pulse out high. + * @param value2 Setting value for pulse out low. + */ +static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2) +{ + assert(channel < PDB_PODLY_COUNT); + + base->PODLY[channel] = PDB_PODLY_DLY1(value1) | PDB_PODLY_DLY2(value2); +} + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_PDB_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c new file mode 100755 index 00000000000..1f2fdfe8b45 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pit.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base PIT peripheral base address + * + * @return The PIT instance + */ +static uint32_t PIT_GetInstance(PIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PIT bases for each instance. */ +static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; + +/*! @brief Pointers to PIT clocks for each instance. */ +static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PIT_GetInstance(PIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++) + { + if (s_pitBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_PIT_COUNT); + + return instance; +} + +void PIT_Init(PIT_Type *base, const pit_config_t *config) +{ + assert(config); + + /* Ungate the PIT clock*/ + CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); + + /* Enable PIT timers */ + base->MCR &= ~PIT_MCR_MDIS_MASK; + + /* Config timer operation when in debug mode */ + if (config->enableRunInDebug) + { + base->MCR &= ~PIT_MCR_FRZ_MASK; + } + else + { + base->MCR |= PIT_MCR_FRZ_MASK; + } +} + +void PIT_Deinit(PIT_Type *base) +{ + /* Disable PIT timers */ + base->MCR |= PIT_MCR_MDIS_MASK; + + /* Gate the PIT clock*/ + CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); +} + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) +{ + uint32_t valueH = 0U; + uint32_t valueL = 0U; + + /* LTMR64H should be read before LTMR64L */ + valueH = base->LTMR64H; + valueL = base->LTMR64L; + + return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); +} + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h new file mode 100755 index 00000000000..61606e7e8bd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PIT_H_ +#define _FSL_PIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pit_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of PIT channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pit_chnl +{ + kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ + kPIT_Chnl_1, /*!< PIT channel number 1 */ + kPIT_Chnl_2, /*!< PIT channel number 2 */ + kPIT_Chnl_3, /*!< PIT channel number 3 */ +} pit_chnl_t; + +/*! @brief List of PIT interrupts */ +typedef enum _pit_interrupt_enable +{ + kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ +} pit_interrupt_enable_t; + +/*! @brief List of PIT status flags */ +typedef enum _pit_status_flags +{ + kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ +} pit_status_flags_t; + +/*! + * @brief PIT config structure + * + * This structure holds the configuration settings for the PIT peripheral. To initialize this + * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ +} pit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PIT driver. + * + * @param base PIT peripheral base address + * @param config Pointer to user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config); + +/*! + * @brief Gate the PIT clock and disable the PIT module + * + * @param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base); + +/*! + * @brief Fill in the PIT config struct with the default settings + * + * The default values are: + * @code + * config->enableRunInDebug = false; + * @endcode + * @param config Pointer to user's PIT config structure. + */ +static inline void PIT_GetDefaultConfig(pit_config_t *config) +{ + assert(config); + + /* Timers are stopped in Debug mode */ + config->enableRunInDebug = false; +} + +#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE + +/*! + * @brief Enables or disables chaining a timer with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. Each timer is 32-bits, this allows the developers + * to chain timers together and form a longer timer (64-bits and larger). The first timer + * (timer 0) cannot be chained to any other timer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number which is chained with the previous timer + * @param enable Enable or disable chain. + * true: Current timer is chained with the previous timer. + * false: Timer doesn't chain with other timers. + */ +static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; + } + else + { + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; + } +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL &= ~mask; +} + +/*! + * @brief Gets the enabled PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PIT status flags + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); +} + +/*! + * @brief Clears the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TFLG = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function until it reaches 0, + * then it will generate an interrupt and load this regiter value again. + * Writing a new value to this register will not restart the timer; instead the value + * will be loaded after the timer expires. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + */ +static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) +{ + base->CHANNEL[channel].LDVAL = count; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, count down to 0 and + * then load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops every timer counting. Timers reload their periods + * respectively after the next time they call the PIT_DRV_StartTimer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * @param base PIT peripheral base address + * + * @return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PIT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c new file mode 100755 index 00000000000..82d7b7ace13 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_pmc.h" + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +void PMC_GetParam(PMC_Type *base, pmc_param_t *param) +{ + uint32_t reg = base->PARAM; + ; + param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); + param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) +{ + base->LVDSC1 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) + /* Clear the Low Voltage Detect Flag with previouse power detect setting */ + | PMC_LVDSC1_LVDACK_MASK); +} + +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) +{ + base->LVDSC2 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) + /* Clear the Low Voltage Warning Flag with previouse power detect setting */ + | PMC_LVDSC2_LVWACK_MASK); +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) +{ + base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | + ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) + /* Clear the High Voltage Detect Flag with previouse power detect setting */ + | PMC_HVDSC1_HVDACK_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) +{ + base->REGSC = (0U +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBE */ +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + ); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h new file mode 100755 index 00000000000..c60c19c01e9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PMC_H_ +#define _FSL_PMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmc */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMC driver version */ +#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) +/*! + * @brief Low-Voltage Detect Voltage Select + */ +typedef enum _pmc_low_volt_detect_volt_select +{ + kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/ + kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/ +} pmc_low_volt_detect_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) +/*! + * @brief Low-Voltage Warning Voltage Select + */ +typedef enum _pmc_low_volt_warning_volt_select +{ + kPMC_LowVoltWarningLowTrip = 0U, /*!< Low trip point selected (VLVW = VLVW1)*/ + kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ + kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ + kPMC_LowVoltWarningHighTrip = 3U /*!< High trip point selected (VLVW = VLVW4)*/ +} pmc_low_volt_warning_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-Voltage Detect Voltage Select + */ +typedef enum _pmc_high_volt_detect_volt_select +{ + kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/ + kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/ +} pmc_high_volt_detect_volt_select_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) +/*! + * @brief Bandgap Buffer Drive Select. + */ +typedef enum _pmc_bandgap_buffer_drive_select +{ + kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive. */ + kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */ +} pmc_bandgap_buffer_drive_select_t; +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + +#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) +/*! + * @brief VLPx Option + */ +typedef enum _pmc_vlp_freq_option +{ + kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ + kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ +} pmc_vlp_freq_mode_t; +#endif /* FSL_FEATURE_PMC_HAS_VLPO */ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + @brief IP version ID definition. + */ +typedef struct _pmc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} pmc_version_id_t; +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! @brief IP parameter definition. */ +typedef struct _pmc_param +{ + bool vlpoEnable; /*!< VLPO enable. */ + bool hvdEnable; /*!< HVD enable. */ +} pmc_param_t; +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +/*! + * @brief Low-Voltage Detect Configuration Structure + */ +typedef struct _pmc_low_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when low voltage detect*/ + bool enableReset; /*!< Enable system reset when low voltage detect*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low voltage detect trip point voltage selection*/ +#endif +} pmc_low_volt_detect_config_t; + +/*! + * @brief Low-Voltage Warning Configuration Structure + */ +typedef struct _pmc_low_volt_warning_config +{ + bool enableInt; /*!< Enable interrupt when low voltage warning*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low voltage warning trip point voltage selection*/ +#endif +} pmc_low_volt_warning_config_t; + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-Voltage Detect Configuration Structure + */ +typedef struct _pmc_high_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when high voltage detect*/ + bool enableReset; /*!< Enable system reset when high voltage detect*/ + pmc_high_volt_detect_volt_select_t voltSelect; /*!< High voltage detect trip point voltage selection*/ +} pmc_high_volt_detect_config_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Bandgap Buffer configuration. + */ +typedef struct _pmc_bandgap_buffer_config +{ +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + bool enable; /*!< Enable bandgap buffer. */ +#endif +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + bool enableInLowPowerMode; /*!< Enable bandgap buffer in low power mode. */ +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ +} pmc_bandgap_buffer_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Power Management Controller Control APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + * @brief Gets the PMC version ID. + * + * This function gets the PMC version ID, including major version number, + * minor version number and feature specification number. + * + * @param base PMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * @brief Gets the PMC parameter. + * + * This function gets the PMC parameter, including VLPO enable and HVD enable. + * + * @param base PMC peripheral base address. + * @param param Pointer to PMC param structure. + */ +void PMC_GetParam(PMC_Type *base, pmc_param_t *param); +#endif + +/*! + * @brief Configure the low voltage detect setting. + * + * This function configures the low voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable system reset or not. + * + * @param base PMC peripheral base address. + * @param config Low-Voltage detect configuration structure. + */ +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); + +/*! + * @brief Get Low-Voltage Detect Flag status + * + * This function reads the current LVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current low voltage detect flag + * - true: Low-Voltage detected + * - false: Low-Voltage not detected + */ +static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK); +} + +/*! + * @brief Acknowledge to clear the Low-Voltage Detect flag + * + * This function acknowledges the low voltage detection errors (write 1 to + * clear LVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) +{ + base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; +} + +/*! + * @brief Configure the low voltage warning setting. + * + * This function configures the low voltage warning setting, including the trip + * point voltage setting and enable interrupt or not. + * + * @param base PMC peripheral base address. + * @param config Low-Voltage warning configuration structure. + */ +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); + +/*! + * @brief Get Low-Voltage Warning Flag status + * + * This function polls the current LVWF status. When 1 is returned, it + * indicates a low-voltage warning event. LVWF is set when V Supply transitions + * below the trip point or after reset and V Supply is already below the V LVW. + * + * @param base PMC peripheral base address. + * @return Current LVWF status + * - true: Low-Voltage Warning Flag is set. + * - false: the Low-Voltage Warning does not happen. + */ +static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK); +} + +/*! + * @brief Acknowledge to Low-Voltage Warning flag + * + * This function acknowledges the low voltage warning errors (write 1 to + * clear LVWF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) +{ + base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief Configure the high voltage detect setting. + * + * This function configures the high voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable system reset or not. + * + * @param base PMC peripheral base address. + * @param config High-Voltage detect configuration structure. + */ +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); + +/*! + * @brief Get High-Voltage Detect Flag status + * + * This function reads the current HVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current high voltage detect flag + * - true: High-Voltage detected + * - false: High-Voltage not detected + */ +static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); +} + +/*! + * @brief Acknowledge to clear the High-Voltage Detect flag + * + * This function acknowledges the high voltage detection errors (write 1 to + * clear HVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) +{ + base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Configure the PMC bandgap + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low power mode. + * + * @param base PMC peripheral base address. + * @param config Pointer to the configuration structure + */ +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) +/*! + * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. + * + * This function reads the Acknowledge Isolation setting that indicates + * whether certain peripherals and the I/O pads are in a latched state as + * a result of having been in the VLLS mode. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return ACK isolation + * 0 - Peripherals and I/O pads are in a normal run state. + * 1 - Certain peripherals and I/O pads are in an isolated and + * latched state. + */ +static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK); +} + +/*! + * @brief Acknowledge to Peripherals and I/O pads isolation flag. + * + * This function clears the ACK Isolation flag. Writing one to this setting + * when it is set releases the I/O pads and certain peripherals to their normal + * run mode state. + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) +{ + base->REGSC |= PMC_REGSC_ACKISO_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ + +#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) +/*! + * @brief Gets the Regulator regulation status. + * + * This function returns the regulator to a run regulation status. It provides + * the current status of the internal voltage regulator. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return Regulation status + * 0 - Regulator is in a stop regulation or in transition to/from the regulation. + * 1 - Regulator is in a run regulation. + * + */ +static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_REGONS */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMC_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h new file mode 100755 index 00000000000..790518ccd3c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PORT_H_ +#define _FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! Version 2.0.1. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */ +}; + +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */ +}; + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Internal resistor pull feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */ + kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */ +}; + +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */ +}; + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ + kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */ + kPORT_MuxAlt2 = 2U, /*!< chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< chip-specific */ +} port_mux_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */ +#endif +} port_interrupt_t; + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*! @brief PORT pin config structure */ +typedef struct _port_pin_config +{ + uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */ + uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */ + uint16_t : 1; + uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */ +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */ + uint16_t : 1; + uint16_t mux : 3; /*!< pin mux Configure */ + uint16_t : 4; +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration: + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configure structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration: + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + * @param config PORT PCR register configure structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)config); + + if (mask & 0xffffU) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (mask >> 16) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will + * be reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use in the case you just need to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*@}*/ + +/*! @name Interrupt */ +/*@{*/ + +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} + +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pins' interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PORT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c new file mode 100755 index 00000000000..538f6872a3a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rcm.h" + +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + uint32_t reg; + + reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); + } + base->RPC = reg; +#else + base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + base->RPFW = config->busClockFilterCount; + } +#endif /* FSL_FEATURE_RCM_REG_WIDTH */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) +{ + uint32_t reg; + + reg = base->FM; + reg &= ~RCM_FM_FORCEROM_MASK; + reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); + base->FM = reg; +} +#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h new file mode 100755 index 00000000000..81e25559eaf --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RCM_H_ +#define _FSL_RCM_H_ + +#include "fsl_common.h" + +/*! @addtogroup rcm */ +/*! @{*/ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RCM driver version 2.0.0. */ +#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief System Reset Source Name definitions + */ +typedef enum _rcm_reset_source +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) +/* RCM register bit width is 32. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ + +#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +/* RCM register bit width is 8. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ + kRCM_SourceAll = 0xffffffffU, +} rcm_reset_source_t; + +/*! + * @brief Reset pin filter select in Run and Wait modes + */ +typedef enum _rcm_run_wait_filter_mode +{ + kRCM_FilterDisable = 0U, /*!< All filtering disabled */ + kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ + kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ +} rcm_run_wait_filter_mode_t; + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Boot from ROM configuration. + */ +typedef enum _rcm_boot_rom_config +{ + kRCM_BootFlash = 0U, /*!< Boot from flash */ + kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ + kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ + kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ +} rcm_boot_rom_config_t; +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Max delay time from interrupt asserts to system reset. + */ +typedef enum _rcm_reset_delay +{ + kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ + kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ + kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ + kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ +} rcm_reset_delay_t; + +/*! + * @brief System reset interrupt enable bit definitions. + */ +typedef enum _rcm_interrupt_enable +{ + kRCM_IntNone = 0U, /*!< No interrupt enabled. */ + kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ + kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ + kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ + kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ + kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ + kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ + kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ + kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ +#endif + kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ + | + RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | + RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + | + RCM_SRIE_CORE1_MASK +#endif +} rcm_interrupt_enable_t; +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _rcm_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} rcm_version_id_t; +#endif + +/*! + * @brief Reset pin filter configuration + */ +typedef struct _rcm_reset_pin_filter_config +{ + bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ + rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ + uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ +} rcm_reset_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Reset Control Module APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief Gets the RCM version ID. + * + * This function gets the RCM version ID including the major version number, + * the minor version number, and the feature specification number. + * + * @param base RCM peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif + +#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) +/*! + * @brief Gets the reset source implemented status. + * + * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. + * Use source masks defined in the rcm_reset_source_t to get the desired source status. + * + * Example: + @code + uint32_t status; + + // To test whether the MCU is reset using Watchdog. + status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source implemented status bit map. + */ +static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) +{ + return base->PARAM; +} +#endif /* FSL_FEATURE_RCM_HAS_PARAM */ + +/*! + * @brief Gets the reset source status which caused a previous reset. + * + * This function gets the current reset source status. Use source masks + * defined in the rcm_reset_source_t to get the desired source status. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SRS; +#else + return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) +/*! + * @brief Gets the sticky reset source status. + * + * This function gets the current reset source status that has not been cleared + * by software for some specific source. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SSRS; +#else + return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +/*! + * @brief Clears the sticky reset source status. + * + * This function clears the sticky system reset flags indicated by source masks. + * + * Example: + @code + // Clears multiple reset sources. + RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @param sourceMasks reset source status bit map + */ +static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + base->SSRS = sourceMasks; +#else + base->SSRS0 = (sourceMasks & 0xffU); + base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} +#endif /* FSL_FEATURE_RCM_HAS_SSRS */ + +/*! + * @brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * @param base RCM peripheral base address. + * @param config Pointer to the configuration structure. + */ +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); + +#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) +/*! + * @brief Gets the EZP_MS_B pin assert status. + * + * This function gets the easy port mode status (EZP_MS_B) pin assert status. + * + * @param base RCM peripheral base address. + * @return status true - asserted, false - reasserted + */ +static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) +{ + return (bool)(base->MR & RCM_MR_EZP_MS_MASK); +} +#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Gets the ROM boot source. + * + * This function gets the ROM boot source during the last chip reset. + * + * @param base RCM peripheral base address. + * @return The ROM boot source. + */ +static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) +{ + return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); +} + +/*! + * @brief Clears the ROM boot source flag. + * + * This function clears the ROM boot source flag. + * + * @param base Register base address of RCM + */ +static inline void RCM_ClearBootRomSource(RCM_Type *base) +{ + base->MR |= RCM_MR_BOOTROM_MASK; +} + +/*! + * @brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * @param base RCM peripheral base address. + * @param config Boot configuration. + */ +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Sets the system reset interrupt configuration. + * + * For graceful shutdown, the RCM supports delaying the assertion of the system + * reset for a period of time when the reset interrupt is generated. This function + * can be used to enable the interrupt and the delay period. The interrupts + * are passed in as bit mask. See rcm_int_t for details. For example, to + * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, + * configure as follows: + * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); + * + * @param base RCM peripheral base address. + * @param intMask Bit mask of the system reset interrupts to enable. See + * rcm_interrupt_enable_t for details. + * @param Delay Bit mask of the system reset interrupts to enable. + */ +static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) +{ + base->SRIE = (intMask | delay); +} +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_RCM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c new file mode 100755 index 00000000000..9be27499efd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rnga.h" + +#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/******************************************************************************* + * RNG_CR - RNGA Control Register + ******************************************************************************/ +/*! + * @brief RNG_CR - RNGA Control Register (RW) + * + * Reset value: 0x00000000U + * + * Controls the operation of RNGA. + */ +/*! + * @name Constants and macros for entire RNG_CR register + */ +/*@{*/ +#define RNG_CR_REG(base) ((base)->CR) +#define RNG_RD_CR(base) (RNG_CR_REG(base)) +#define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value)) +#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register RNG_CR, field GO[0] (RW) + * + * Specifies whether random-data generation and loading (into OR[RANDOUT]) is + * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading + * OR[RANDOUT] with data. + * + * Values: + * - 0b0 - Disabled + * - 0b1 - Enabled + */ +/*@{*/ +/*! @brief Read current value of the RNG_CR_GO field. */ +#define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT) + +/*! @brief Set the GO field to a new value. */ +#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value))) +/*@}*/ + +/*! + * @name Register RNG_CR, field SLP[4] (RW) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0b0 - Normal mode + * - 0b1 - Sleep (low-power) mode + */ +/*@{*/ +/*! @brief Read current value of the RNG_CR_SLP field. */ +#define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT) + +/*! @brief Set the SLP field to a new value. */ +#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value))) +/*@}*/ + +/******************************************************************************* + * RNG_SR - RNGA Status Register + ******************************************************************************/ +#define RNG_SR_REG(base) ((base)->SR) + +/*! + * @name Register RNG_SR, field OREG_LVL[15:8] (RO) + * + * Indicates the number of random-data words that are in OR[RANDOUT], which + * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] + * is not 0, then the contents of a random number contained in OR[RANDOUT] are + * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. + * + * Values: + * - 0b00000000 - No words (empty) + * - 0b00000001 - One word (valid) + */ +/*@{*/ +/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ +#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT) +/*@}*/ + +/*! + * @name Register RNG_SR, field SLP[4] (RO) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0b0 - Normal mode + * - 0b1 - Sleep (low-power) mode + */ +/*@{*/ +/*! @brief Read current value of the RNG_SR_SLP field. */ +#define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT) +/*@}*/ + +/******************************************************************************* + * RNG_OR - RNGA Output Register + ******************************************************************************/ +/*! + * @brief RNG_OR - RNGA Output Register (RO) + * + * Reset value: 0x00000000U + * + * Stores a random-data word generated by RNGA. + */ +/*! + * @name Constants and macros for entire RNG_OR register + */ +/*@{*/ +#define RNG_OR_REG(base) ((base)->OR) +#define RNG_RD_OR(base) (RNG_OR_REG(base)) +/*@}*/ + +/******************************************************************************* + * RNG_ER - RNGA Entropy Register + ******************************************************************************/ +/*! + * @brief RNG_ER - RNGA Entropy Register (WORZ) + * + * Reset value: 0x00000000U + * + * Specifies an entropy value that RNGA uses in addition to its ring oscillators + * to seed its pseudorandom algorithm. This is a write-only register; reads + * return all zeros. + */ +/*! + * @name Constants and macros for entire RNG_ER register + */ +/*@{*/ +#define RNG_ER_REG(base) ((base)->ER) +#define RNG_RD_ER(base) (RNG_ER_REG(base)) +#define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value)) +/*@}*/ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ + +static uint32_t rnga_ReadEntropy(RNG_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +void RNGA_Init(RNG_Type *base) +{ + /* Enable the clock gate. */ + CLOCK_EnableClock(kCLOCK_Rnga0); + CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */ + CLOCK_EnableClock(kCLOCK_Rnga0); + + /* Reset the registers for RNGA module to reset state. */ + RNG_WR_CR(base, 0); + /* Enables the RNGA random data generation and loading.*/ + RNG_WR_CR_GO(base, 1); +} + +void RNGA_Deinit(RNG_Type *base) +{ + /* Disable the clock for RNGA module.*/ + CLOCK_DisableClock(kCLOCK_Rnga0); +} + +/*! + * @brief Get a random data from RNGA. + * + * @param base RNGA base address + */ +static uint32_t rnga_ReadEntropy(RNG_Type *base) +{ + uint32_t data = 0; + if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/ + { + /* Wait for valid random-data.*/ + while (RNG_RD_SR_OREG_LVL(base) == 0) + { + } + data = RNG_RD_OR(base); + } + /* Get random-data word generated by RNGA.*/ + return data; +} + +status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size) +{ + status_t result = kStatus_Success; + uint32_t random_32; + uint8_t *random_p; + uint32_t random_size; + uint8_t *data_p = (uint8_t *)data; + uint32_t i; + + /* Check input parameters.*/ + if (base && data && data_size) + { + do + { + /* Read Entropy.*/ + random_32 = rnga_ReadEntropy(base); + + random_p = (uint8_t *)&random_32; + + if (data_size < sizeof(random_32)) + { + random_size = data_size; + } + else + { + random_size = sizeof(random_32); + } + + for (i = 0; i < random_size; i++) + { + *data_p++ = *random_p++; + } + + data_size -= random_size; + } while (data_size > 0); + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode) +{ + RNG_WR_CR_SLP(base, (uint32_t)mode); +} + +rnga_mode_t RNGA_GetMode(RNG_Type *base) +{ + return (rnga_mode_t)RNG_RD_SR_SLP(base); +} + +void RNGA_Seed(RNG_Type *base, uint32_t seed) +{ + /* Write to RNGA Entropy Register.*/ + RNG_WR_ER(base, seed); +} + +#endif /* FSL_FEATURE_SOC_RNG_COUNT */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h new file mode 100755 index 00000000000..04950a4540c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RNGA_DRIVER_H_ +#define _FSL_RNGA_DRIVER_H_ + +#include "fsl_common.h" + +#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT +/*! + * @addtogroup rnga_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RNGA driver version 2.0.1. */ +#define FSL_RNGA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief RNGA working mode */ +typedef enum _rnga_mode +{ + kRNGA_ModeNormal = 0U, /*!< Normal Mode. The ring-oscillator clocks are active; RNGA generates entropy + (randomness) from the clocks and stores it in shift registers.*/ + kRNGA_ModeSleep = 1U, /*!< Sleep Mode. The ring-oscillator clocks are inactive; RNGA does not generate entropy.*/ +} rnga_mode_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RNGA. + * + * This function initializes the RNGA. + * When called, the RNGA entropy generation starts immediately. + * + * @param base RNGA base address + */ +void RNGA_Init(RNG_Type *base); + +/*! + * @brief Shuts down the RNGA. + * + * This function shuts down the RNGA. + * + * @param base RNGA base address + */ +void RNGA_Deinit(RNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the RNGA. + * + * @param base RNGA base address + * @param data pointer to user buffer to be filled by random data + * @param data_size size of data in bytes + * @return RNGA status + */ +status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size); + +/*! + * @brief Feeds the RNGA module. + * + * This function inputs an entropy value that the RNGA uses to seed its + * pseudo-random algorithm. + * + * @param base RNGA base address + * @param seed input seed value + */ +void RNGA_Seed(RNG_Type *base, uint32_t seed); + +/*! + * @brief Sets the RNGA in normal mode or sleep mode. + * + * This function sets the RNGA in sleep mode or normal mode. + * + * @param base RNGA base address + * @param mode normal mode or sleep mode + */ +void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode); + +/*! + * @brief Gets the RNGA working mode. + * + * This function gets the RNGA working mode. + * + * @param base RNGA base address + * @return normal mode or sleep mode + */ +rnga_mode_t RNGA_GetMode(RNG_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_RNG_COUNT */ +#endif /* _FSL_RNGA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c new file mode 100755 index 00000000000..898a544a467 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if (datetime->day > daysPerMonth[datetime->month]) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +void RTC_Init(RTC_Type *base, const rtc_config_t *config) +{ + assert(config); + + uint32_t reg; + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Issue a software reset if timer is invalid */ + if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) + { + RTC_Reset(RTC); + } + + reg = base->CR; + /* Setup the update mode and supervisor access mode */ + reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); + reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); +#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN + /* Setup the wakeup pin select */ + reg &= ~(RTC_CR_WPS_MASK); + reg |= RTC_CR_WPS(config->wakeupSelect); +#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ + base->CR = reg; + + /* Configure the RTC time compensation register */ + base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); +} + +void RTC_GetDefaultConfig(rtc_config_t *config) +{ + assert(config); + + /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ + config->wakeupSelect = false; + /* Registers cannot be written when locked */ + config->updateMode = false; + /* Non-supervisor mode write accesses are not supported and will generate a bus error */ + config->supervisorAccess = false; + /* Compensation interval used by the crystal compensation logic */ + config->compensationInterval = 0; + /* Compensation time used by the crystal compensation logic */ + config->compensationTime = 0; +} + +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->TSR = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = base->TSR; + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = base->TSR; + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->TAR = alarmSeconds; + + return kStatus_Success; +} + +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->TAR; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + /* The alarm flag is cleared by writing to the TAR register */ + if (mask & kRTC_AlarmFlag) + { + base->TAR = 0U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeOverflowFlag) + { + base->TSR = 1U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeInvalidFlag) + { + base->TSR = 1U; + } +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) +{ + *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); +} + +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) +{ + /* Prepare to initialize the register with the new value written */ + base->MER &= ~RTC_MER_MCE_MASK; + + base->MCHR = (uint32_t)((counter) >> 32); + base->MCLR = (uint32_t)(counter); +} + +status_t RTC_IncrementMonotonicCounter(RTC_Type *base) +{ + if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) + { + return kStatus_Fail; + } + + /* Prepare to switch to increment mode */ + base->MER |= RTC_MER_MCE_MASK; + /* Write anything so the counter increments*/ + base->MCLR = 1U; + + return kStatus_Success; +} + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h new file mode 100755 index 00000000000..063d1d40c34 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ + kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ + kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ + kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ + kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ + kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ +} rtc_status_flags_t; + +/*! @brief List of RTC Oscillator capacitor load settings */ +typedef enum _rtc_osc_cap_load +{ + kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2pF capacitor load */ + kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4pF capacitor load */ + kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8pF capacitor load */ + kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */ +} rtc_osc_cap_load_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/*! + * @brief RTC config structure + * + * This structure holds the configuration settings for the RTC peripheral. To initialize this + * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _rtc_config +{ + bool wakeupSelect; /*!< true: Wakeup pin outputs the 32KHz clock; + false:Wakeup pin used to wakeup the chip */ + bool updateMode; /*!< true: Registers can be written even when locked under certain + conditions, false: No writes allowed when registers are locked */ + bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; + false: Non-supervisor accesses are not supported */ + uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ + uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ +} rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the RTC clock and configures the peripheral for basic operation. + * + * This function will issue a software reset if the timer invalid flag is set. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + * @param config Pointer to user's RTC config structure. + */ +void RTC_Init(RTC_Type *base, const rtc_config_t *config); + +/*! + * @brief Stop the timer and gate the RTC clock + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->SR &= ~RTC_SR_TCE_MASK; + + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +/*! + * @brief Fill in the RTC config struct with the default settings + * + * The default values are: + * @code + * config->wakeupSelect = false; + * config->updateMode = false; + * config->supervisorAccess = false; + * config->compensationInterval = 0; + * config->compensationTime = 0; + * @endcode + * @param config Pointer to user's RTC config structure. + */ +void RTC_GetDefaultConfig(rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the RTC status flags + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); +} + +/*! + * @brief Clears the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->SR |= RTC_SR_TCE_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->SR &= ~RTC_SR_TCE_MASK; +} + +/*! @}*/ + +/*! + * @brief This function sets the specified capacitor configuration for the RTC oscillator. + * + * @param base RTC peripheral base address + * @param capLoad Oscillator loads to enable. This is a logical OR of members of the + * enumeration ::rtc_osc_cap_load_t + */ +static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) +{ + uint32_t reg = base->CR; + + reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR + * registers. The SWR bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CR |= RTC_CR_SWR_MASK; + base->CR &= ~RTC_CR_SWR_MASK; + + /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ + base->TSR = 1U; +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +/*! + * @name Monotonic counter functions + * @{ + */ + +/*! + * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns + * them as a single value. + * + * @param base RTC peripheral base address + * @param counter Pointer to variable where the value is stored. + */ +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); + +/*! + * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing + * the given single value. + * + * @param base RTC peripheral base address + * @param counter Counter value + */ +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); + +/*! + * @brief Increments the Monotonic Counter by one. + * + * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting + * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the + * monotonic counter low that causes it to overflow also increments the monotonic counter high. + * + * @param base RTC peripheral base address + * + * @return kStatus_Success: success + * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found + */ +status_t RTC_IncrementMonotonicCounter(RTC_Type *base); + +/*! @}*/ + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c new file mode 100755 index 00000000000..a45e9e62134 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c @@ -0,0 +1,1048 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _sai_transfer_state +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occured. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ +/*!@brief SAI handle pointer */ +sai_handle_t *s_saiHandle[FSL_FEATURE_SOC_I2S_COUNT][2]; +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + uint32_t freq = mclkSrcClock_Hz; + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /*In order to prevent overflow */ + freq /= 100; + mclk_Hz /= 100; + + /* Compute the max fract number */ + max_fract = mclk_Hz * 4096 / freq + 1; + if (max_fract > 256) + { + max_fract = 256; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = freq * fract; + remaind = mul_freq % mclk_Hz; + divide = mul_freq / mclk_Hz; + + /* Find the exactly frequency */ + if (remaind == 0) + { + current_fract = fract; + current_divide = mul_freq / mclk_Hz; + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2) + { + remaind = mclk_Hz - remaind; + divide += 1; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); + + /* Waiting for the divider updated */ + while (base->MCR & I2S_MCR_DUF_MASK) + { + } +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_I2S_COUNT; instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_I2S_COUNT); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * j)); + buffer++; + } + base->TDR[channel] = data; + data = 0; + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = base->RDR[channel]; + for (j = 0; j < bytesPerWord; j++) + { + *buffer = (data >> (8U * j)) & 0xFF; + buffer++; + } + } +} + +void SAI_TxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Configure Master clock output enable */ + base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); + + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + base->TCR4 |= I2S_TCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; + default: + break; + } +} + +void SAI_RxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + + /* Enable SAI clock first. */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Configure Master clock output enable */ + base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); + + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + base->RCR4 |= I2S_RCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; + default: + break; + } +} + +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); + CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +} + +void SAI_TxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusLeftJustified; + config->syncMode = kSAI_ModeAsync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_RxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusLeftJustified; + config->syncMode = kSAI_ModeSync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + else + { + /* Should not close RE even sync with Rx */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } +} + +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } +} + +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = format->sampleRate_Hz * 32U * 2U; + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->TCR2 & I2S_TCR2_BCD_MASK) + { + base->TCR2 &= ~I2S_TCR2_DIV_MASK; + base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + if (format->protocol == kSAI_BusRightJustified) + { + base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(31U); + } + else + { + base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(format->bitWidth - 1); + } + + /* Set mono or stereo */ + base->TMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->TCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = format->sampleRate_Hz * 32U * 2U; + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->RCR2 & I2S_RCR2_BCD_MASK) + { + base->RCR2 &= ~I2S_RCR2_DIV_MASK; + base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + if (format->protocol == kSAI_BusRightJustified) + { + base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(31U); + } + else + { + base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(format->bitWidth - 1); + } + + /* Set mono or stereo */ + base->RMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->RCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size; i++) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size; i++) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + } +} + +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Enable Tx irq */ + EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Enable Rx irq */ + EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->TCSR & I2S_TCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->TCSR & I2S_TCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->TCSR & I2S_TCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->RCSR & I2S_RCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->RCSR & I2S_RCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->RCSR & I2S_RCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +#if defined(FSL_FEATURE_SAI_INT_SOURCE_NUM) && (FSL_FEATURE_SAI_INT_SOURCE_NUM == 1) +void I2S0_DriverIRQHandler(void) +{ + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) + { + SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + } + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) + { + SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + } +} +#else +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0]); + SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); +} + +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1]); + SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); +} +#endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0]); + SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); +} + +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1]); + SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h new file mode 100755 index 00000000000..72b6efd06bc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SAI_H_ +#define _FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +/*@}*/ + +/*! @brief SAI return status*/ +enum _sai_status_t +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode */ + kSAI_Slave = 0x1U /*!< Slave mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoLeft, /*!< Only left channel have sound. */ + kSAI_MonoRight /*!< Only Right channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +} sai_sync_mode_t; + +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief The SAI interrupt enable flag */ +enum _sai_interrupt_enable_t +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The DMA request sources */ +enum _sai_dma_enable_t +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The SAI status flag */ +enum _sai_flags +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configure structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + sai_mclk_source_t mclkSource; /*!< Master Clock source */ + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ + kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + uint8_t channel; /*!< Data channel used in transfer.*/ + sai_protocol_t protocol; /*!< Which audio protocol used */ +} sai_transfer_format_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32bits */ + uint8_t channel; /*!< Transfer channel */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI Tx peripheral. + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configure structure. +*/ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Initializes the the SAI Rx peripheral. + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configure structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Sets the SAI Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * Example: + @code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Sets the SAI Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * Example: + @code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer +*/ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables SAI Tx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables SAI Rx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following source if defined: + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. +*/ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. +*/ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for SAI Tx transactional APIs. Call + * this function one time to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback pointer to user callback function + * @param userData user parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for SAI Rx transactional APIs. Call + * this function one time to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback pointer to user callback function + * @param userData user parameter passed to the callback function + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal to masterClockHz in format. + * @return Status of this function. Return value is one of status_t. +*/ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @return Status of this function. Return value is one of status_t. +*/ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle pointer to sai_handle_t structure which stores the transfer state + * @param xfer pointer to sai_transfer_t structure + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle pointer to sai_handle_t structure which stores the transfer state + * @param xfer pointer to sai_transfer_t structure + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the the current IRQ receive. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle pointer to sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SAI_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c new file mode 100755 index 00000000000..9b1b2f6c490 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai_edma.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + SAI_TransferAbortSendEDMA(privHandle->base, saiHandle); + } +} + +static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; + sai_edma_handle_t *saiHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + SAI_TransferAbortReceiveEDMA(privHandle->base, saiHandle); + } +} + +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; + + /* Update the data channel SAI used */ + handle->channel = format->channel; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; + + /* Update the data channel SAI used */ + handle->channel = format->channel; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h new file mode 100755 index 00000000000..44506fa039d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SAI_EDMA_H_ +#define _FSL_SAI_EDMA_H_ + +#include "fsl_sai.h" +#include "fsl_edma.h" + +/*! + * @addtogroup sai_edma + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef struct _sai_edma_handle sai_edma_handle_t; + +/*! @brief SAI eDMA transfer callback function for finish and error */ +typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ +struct _sai_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs a non-blocking SAI transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Aborts a SAI transfer using eDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI receive using eDMA. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SAI. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param count Bytes count sent by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SAI. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param count Bytes count received by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c new file mode 100755 index 00000000000..0c5dd2b625d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c @@ -0,0 +1,1294 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sdhc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock setting */ +/* Max SD clock divisor from base clock */ +#define SDHC_MAX_DVS ((SDHC_SYSCTL_DVS_MASK >> SDHC_SYSCTL_DVS_SHIFT) + 1U) +#define SDHC_INITIAL_DVS (1U) /* Initial value of SD clock divisor */ +#define SDHC_INITIAL_CLKFS (2U) /* Initial value of SD clock frequency selector */ +#define SDHC_NEXT_DVS(x) ((x) += 1U) +#define SDHC_PREV_DVS(x) ((x) -= 1U) +#define SDHC_MAX_CLKFS ((SDHC_SYSCTL_SDCLKFS_MASK >> SDHC_SYSCTL_SDCLKFS_SHIFT) + 1U) +#define SDHC_NEXT_CLKFS(x) ((x) <<= 1U) +#define SDHC_PREV_CLKFS(x) ((x) >>= 1U) + +/*! @brief ADMA table configuration */ +typedef struct _sdhc_adma_table_config +{ + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} sdhc_adma_table_config_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base SDHC peripheral base address. + * @return Instance number. + */ +static uint32_t SDHC_GetInstance(SDHC_Type *base); + +/*! + * @brief Set transfer interrupt. + * + * @param base SDHC peripheral base address. + * @param usingInterruptSignal True to use IRQ signal. + */ +static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal); + +/*! + * @brief Start transfer according to current transfer state + * + * @param base SDHC peripheral base address. + * @param command Command to be sent. + * @param data Data to be transferred. + */ +static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data); + +/*! + * @brief Receive command response + * + * @param base SDHC peripheral base address. + * @param command Command to be sent. + */ +static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command); + +/*! + * @brief Read DATAPORT when buffer enable bit is set. + * + * @param base SDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time transaction. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Read data by using DATAPORT polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be read. + * @retval kStatus_Fail Read DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_ReadByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Write DATAPORT when buffer enable bit is set. + * + * @param base SDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t SDHC_WriteDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Write data by using DATAPORT polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Write DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_WriteByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Send command by using polling way. + * + * @param base SDHC peripheral base address. + * @param command Command to be sent. + * @retval kStatus_Fail Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_SendCommandBlocking(SDHC_Type *base, sdhc_command_t *command); + +/*! + * @brief Transfer data by DATAPORT and polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_TransferByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Transfer data by ADMA2 and polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_TransferByAdma2Blocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Transfer data by polling way. + * + * @param dmaMode DMA mode. + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_TransferDataBlocking(sdhc_dma_mode_t dmaMode, SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Handle card detect interrupt. + * + * @param handle SDHC handle. + * @param interruptFlags Card detect related interrupt flags. + */ +static void SDHC_TransferHandleCardDetect(sdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle command interrupt. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + * @param interruptFlags Command related interrupt flags. + */ +static void SDHC_TransferHandleCommand(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle data interrupt. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + * @param interruptFlags Data related interrupt flags. + */ +static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle SDIO card interrupt signal. + * + * @param handle SDHC handle. + */ +static void SDHC_TransferHandleSdioInterrupt(sdhc_handle_t *handle); + +/*! + * @brief Handle SDIO block gap event. + * + * @param handle SDHC handle. + */ +static void SDHC_TransferHandleSdioBlockGap(sdhc_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief SDHC internal handle pointer array */ +static sdhc_handle_t *s_sdhcHandle[FSL_FEATURE_SOC_SDHC_COUNT]; + +/*! @brief SDHC base pointer array */ +static SDHC_Type *const s_sdhcBase[] = SDHC_BASE_PTRS; + +/*! @brief SDHC IRQ name array */ +static const IRQn_Type s_sdhcIRQ[] = SDHC_IRQS; + +/*! @brief SDHC clock array name */ +static const clock_ip_name_t s_sdhcClock[] = SDHC_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SDHC_GetInstance(SDHC_Type *base) +{ + uint8_t instance = 0; + + while ((instance < FSL_FEATURE_SOC_SDHC_COUNT) && (s_sdhcBase[instance] != base)) + { + instance++; + } + + assert(instance < FSL_FEATURE_SOC_SDHC_COUNT); + + return instance; +} + +static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal) +{ + uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ + sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT); + bool cardDetectDat3 = (bool)(base->PROCTL & SDHC_PROCTL_D3CD_MASK); + + /* Disable all interrupts */ + SDHC_DisableInterruptStatus(base, (uint32_t)kSDHC_AllInterruptFlags); + SDHC_DisableInterruptSignal(base, (uint32_t)kSDHC_AllInterruptFlags); + DisableIRQ(s_sdhcIRQ[SDHC_GetInstance(base)]); + + interruptEnabled = + (kSDHC_CommandIndexErrorFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag | + kSDHC_CommandTimeoutFlag | kSDHC_CommandCompleteFlag | kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | + kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag); + if (cardDetectDat3) + { + interruptEnabled |= (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag); + } + switch (dmaMode) + { + case kSDHC_DmaModeAdma1: + case kSDHC_DmaModeAdma2: + interruptEnabled |= (kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag); + break; + case kSDHC_DmaModeNo: + interruptEnabled |= (kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + break; + default: + break; + } + + SDHC_EnableInterruptStatus(base, interruptEnabled); + if (usingInterruptSignal) + { + SDHC_EnableInterruptSignal(base, interruptEnabled); + } +} + +static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data) +{ + assert(command); + + uint32_t flags = 0U; + sdhc_transfer_config_t sdhcTransferConfig; + sdhc_dma_mode_t dmaMode; + + /* Define the flag corresponding to each response type. */ + switch (command->responseType) + { + case kSDHC_ResponseTypeNone: + break; + case kSDHC_ResponseTypeR1: /* Response 1 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kSDHC_ResponseTypeR1b: /* Response 1 with busy */ + flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kSDHC_ResponseTypeR2: /* Response 2 */ + flags |= (kSDHC_ResponseLength136Flag | kSDHC_EnableCrcCheckFlag); + break; + case kSDHC_ResponseTypeR3: /* Response 3 */ + flags |= (kSDHC_ResponseLength48Flag); + break; + case kSDHC_ResponseTypeR4: /* Response 4 */ + flags |= (kSDHC_ResponseLength48Flag); + break; + case kSDHC_ResponseTypeR5: /* Response 5 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag); + break; + case kSDHC_ResponseTypeR5b: /* Response 5 with busy */ + flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kSDHC_ResponseTypeR6: /* Response 6 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kSDHC_ResponseTypeR7: /* Response 7 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + default: + break; + } + if (command->type == kSDHC_CommandTypeAbort) + { + flags |= kSDHC_CommandTypeAbortFlag; + } + + if (data) + { + flags |= kSDHC_DataPresentFlag; + dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT); + if (dmaMode != kSDHC_DmaModeNo) + { + flags |= kSDHC_EnableDmaFlag; + } + if (data->rxData) + { + flags |= kSDHC_DataReadFlag; + } + if (data->blockCount > 1U) + { + flags |= (kSDHC_MultipleBlockFlag | kSDHC_EnableBlockCountFlag); + if (data->enableAutoCommand12) + { + /* Enable Auto command 12. */ + flags |= kSDHC_EnableAutoCommand12Flag; + } + } + if (data->blockCount > SDHC_MAX_BLOCK_COUNT) + { + sdhcTransferConfig.dataBlockSize = data->blockSize; + sdhcTransferConfig.dataBlockCount = SDHC_MAX_BLOCK_COUNT; + + flags &= ~(uint32_t)kSDHC_EnableBlockCountFlag; + } + else + { + sdhcTransferConfig.dataBlockSize = data->blockSize; + sdhcTransferConfig.dataBlockCount = data->blockCount; + } + } + else + { + sdhcTransferConfig.dataBlockSize = 0U; + sdhcTransferConfig.dataBlockCount = 0U; + } + + sdhcTransferConfig.commandArgument = command->argument; + sdhcTransferConfig.commandIndex = command->index; + sdhcTransferConfig.flags = flags; + SDHC_SetTransferConfig(base, &sdhcTransferConfig); +} + +static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command) +{ + assert(command); + + uint32_t i; + + if (command->responseType != kSDHC_ResponseTypeNone) + { + command->response[0U] = SDHC_GetCommandResponse(base, 0U); + if (command->responseType == kSDHC_ResponseTypeR2) + { + command->response[1U] = SDHC_GetCommandResponse(base, 1U); + command->response[2U] = SDHC_GetCommandResponse(base, 2U); + command->response[3U] = SDHC_GetCommandResponse(base, 3U); + + i = 4U; + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + do + { + command->response[i - 1U] <<= 8U; + if (i > 1U) + { + command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); + } + } while (i--); + } + } +} + +static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords) +{ + assert(data); + + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->WML & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT); + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = SDHC_ReadData(base); + i++; + } + + return transferredWords; +} + +static status_t SDHC_ReadByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data) +{ + assert(data); + + uint32_t totalWords; + uint32_t transferredWords = 0U; + status_t error = kStatus_Success; + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag))) + { + } + + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_DataErrorFlag) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + if (error == kStatus_Success) + { + transferredWords = SDHC_ReadDataPort(base, data, transferredWords); + } + + /* Clear buffer enable flag to trigger transfer. Clear data error flag when SDHC encounter error */ + SDHC_ClearInterruptStatusFlags(base, (kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag)); + } + + /* Clear data complete flag after the last read operation. */ + SDHC_ClearInterruptStatusFlags(base, kSDHC_DataCompleteFlag); + + return error; +} + +static uint32_t SDHC_WriteDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords) +{ + assert(data); + + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ + uint32_t writeWatermark = ((base->WML & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT); + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ + if (writeWatermark >= totalWords) + { + wordsCanBeWrote = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrote = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left + words. */ + else + { + wordsCanBeWrote = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrote) + { + SDHC_WriteData(base, data->txData[transferredWords++]); + i++; + } + + return transferredWords; +} + +static status_t SDHC_WriteByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data) +{ + assert(data); + + uint32_t totalWords; + uint32_t transferredWords = 0U; + status_t error = kStatus_Success; + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_BufferWriteReadyFlag | kSDHC_DataErrorFlag))) + { + } + + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_DataErrorFlag) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + if (error == kStatus_Success) + { + transferredWords = SDHC_WriteDataPort(base, data, transferredWords); + } + + /* Clear buffer enable flag to trigger transfer. Clear error flag when SDHC encounter error. */ + SDHC_ClearInterruptStatusFlags(base, (kSDHC_BufferWriteReadyFlag | kSDHC_DataErrorFlag)); + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag))) + { + } + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_DataErrorFlag) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + SDHC_ClearInterruptStatusFlags(base, (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag)); + + return error; +} + +static status_t SDHC_SendCommandBlocking(SDHC_Type *base, sdhc_command_t *command) +{ + assert(command); + + status_t error = kStatus_Success; + + /* Wait command complete or SDHC encounters error. */ + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_CommandCompleteFlag | kSDHC_CommandErrorFlag))) + { + } + + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_CommandErrorFlag) + { + error = kStatus_Fail; + } + /* Receive response when command completes successfully. */ + if (error == kStatus_Success) + { + SDHC_ReceiveCommandResponse(base, command); + } + + SDHC_ClearInterruptStatusFlags(base, (kSDHC_CommandCompleteFlag | kSDHC_CommandErrorFlag)); + + return error; +} + +static status_t SDHC_TransferByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data) +{ + assert(data); + + status_t error = kStatus_Success; + + if (data->rxData) + { + error = SDHC_ReadByDataPortBlocking(base, data); + } + else + { + error = SDHC_WriteByDataPortBlocking(base, data); + } + + return error; +} + +static status_t SDHC_TransferByAdma2Blocking(SDHC_Type *base, sdhc_data_t *data) +{ + status_t error = kStatus_Success; + + /* Wait data complete or SDHC encounters error. */ + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag))) + { + } + if (SDHC_GetInterruptStatusFlags(base) & (kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag)) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + SDHC_ClearInterruptStatusFlags( + base, (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag)); + return error; +} + +#if defined FSL_SDHC_ENABLE_ADMA1 +#define SDHC_TransferByAdma1Blocking(base, data) SDHC_TransferByAdma2Blocking(base, data) +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + +static status_t SDHC_TransferDataBlocking(sdhc_dma_mode_t dmaMode, SDHC_Type *base, sdhc_data_t *data) +{ + status_t error = kStatus_Success; + + switch (dmaMode) + { + case kSDHC_DmaModeNo: + error = SDHC_TransferByDataPortBlocking(base, data); + break; +#if defined FSL_SDHC_ENABLE_ADMA1 + case kSDHC_DmaModeAdma1: + error = SDHC_TransferByAdma1Blocking(base, data); + break; +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + case kSDHC_DmaModeAdma2: + error = SDHC_TransferByAdma2Blocking(base, data); + break; + default: + error = kStatus_InvalidArgument; + break; + } + + return error; +} + +static void SDHC_TransferHandleCardDetect(sdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(interruptFlags & kSDHC_CardDetectFlag); + + if (interruptFlags & kSDHC_CardInsertionFlag) + { + if (handle->callback.CardInserted) + { + handle->callback.CardInserted(); + } + } + else + { + if (handle->callback.CardRemoved) + { + handle->callback.CardRemoved(); + } + } +} + +static void SDHC_TransferHandleCommand(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(interruptFlags & kSDHC_CommandFlag); + + if ((interruptFlags & kSDHC_CommandErrorFlag) && (!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDHC_SendCommandFailed, handle->userData); + } + else + { + /* Receive response */ + SDHC_ReceiveCommandResponse(base, handle->command); + if ((!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } +} + +static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + assert(interruptFlags & kSDHC_DataFlag); + + if ((!(handle->data->enableIgnoreError)) && (interruptFlags & (kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag)) && + (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDHC_TransferDataFailed, handle->userData); + } + else + { + if (interruptFlags & kSDHC_BufferReadReadyFlag) + { + handle->transferredWords = SDHC_ReadDataPort(base, handle->data, handle->transferredWords); + } + else if (interruptFlags & kSDHC_BufferWriteReadyFlag) + { + handle->transferredWords = SDHC_WriteDataPort(base, handle->data, handle->transferredWords); + } + else if ((interruptFlags & kSDHC_DataCompleteFlag) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + /* Do nothing when DMA complete flag is set. Wait until data complete flag is set. */ + } + } +} + +static void SDHC_TransferHandleSdioInterrupt(sdhc_handle_t *handle) +{ + if (handle->callback.SdioInterrupt) + { + handle->callback.SdioInterrupt(); + } +} + +static void SDHC_TransferHandleSdioBlockGap(sdhc_handle_t *handle) +{ + if (handle->callback.SdioBlockGap) + { + handle->callback.SdioBlockGap(); + } +} + +void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config) +{ + assert(config); +#if !defined FSL_SDHC_ENABLE_ADMA1 + assert(config->dmaMode != kSDHC_DmaModeAdma1); +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + + uint32_t proctl; + uint32_t wml; + + /* Enable SDHC clock. */ + CLOCK_EnableClock(s_sdhcClock[SDHC_GetInstance(base)]); + + /* Reset SDHC. */ + SDHC_Reset(base, kSDHC_ResetAll, 100); + + proctl = base->PROCTL; + wml = base->WML; + + proctl &= ~(SDHC_PROCTL_D3CD_MASK | SDHC_PROCTL_EMODE_MASK | SDHC_PROCTL_DMAS_MASK); + /* Set DAT3 as card detection pin */ + if (config->cardDetectDat3) + { + proctl |= SDHC_PROCTL_D3CD_MASK; + } + /* Endian mode and DMA mode */ + proctl |= (SDHC_PROCTL_EMODE(config->endianMode) | SDHC_PROCTL_DMAS(config->dmaMode)); + + /* Watermark level */ + wml &= ~(SDHC_WML_RDWML_MASK | SDHC_WML_WRWML_MASK); + wml |= (SDHC_WML_RDWML(config->readWatermarkLevel) | SDHC_WML_WRWML(config->writeWatermarkLevel)); + + base->WML = wml; + base->PROCTL = proctl; + + /* Disable all clock auto gated off feature because of DAT0 line logic(card buffer full status) can't be updated + correctly when clock auto gated off is enabled. */ + base->SYSCTL |= (SDHC_SYSCTL_PEREN_MASK | SDHC_SYSCTL_HCKEN_MASK | SDHC_SYSCTL_IPGEN_MASK); + + /* Enable interrupt status but doesn't enable interrupt signal. */ + SDHC_SetTransferInterrupt(base, false); +} + +void SDHC_Deinit(SDHC_Type *base) +{ + /* Disable clock. */ + CLOCK_DisableClock(s_sdhcClock[SDHC_GetInstance(base)]); +} + +bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout) +{ + base->SYSCTL |= (mask & (SDHC_SYSCTL_RSTA_MASK | SDHC_SYSCTL_RSTC_MASK | SDHC_SYSCTL_RSTD_MASK)); + /* Delay some time to wait reset success. */ + while ((base->SYSCTL & mask)) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability) +{ + assert(capability); + + uint32_t htCapability; + uint32_t hostVer; + uint32_t maxBlockLength; + + hostVer = base->HOSTVER; + htCapability = base->HTCAPBLT; + + /* Get the capability of SDHC. */ + capability->specVersion = ((hostVer & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT); + capability->vendorVersion = ((hostVer & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT); + maxBlockLength = ((htCapability & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT); + capability->maxBlockLength = (512U << maxBlockLength); + /* Other attributes not in HTCAPBLT register. */ + capability->maxBlockCount = SDHC_MAX_BLOCK_COUNT; + capability->flags = (htCapability & (kSDHC_SupportAdmaFlag | kSDHC_SupportHighSpeedFlag | kSDHC_SupportDmaFlag | + kSDHC_SupportSuspendResumeFlag | kSDHC_SupportV330Flag)); +#if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT + capability->flags |= (htCapability & kSDHC_SupportV300Flag); +#endif +#if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT + capability->flags |= (htCapability & kSDHC_SupportV180Flag); +#endif + /* eSDHC on all kinetis boards will support 4/8 bit data bus width. */ + capability->flags |= (kSDHC_Support4BitFlag | kSDHC_Support8BitFlag); +} + +uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) +{ + assert(busClock_Hz && (busClock_Hz < srcClock_Hz)); + + uint32_t divisor; + uint32_t prescaler; + uint32_t sysctl; + uint32_t nearestFrequency = 0; + + divisor = SDHC_INITIAL_DVS; + prescaler = SDHC_INITIAL_CLKFS; + + /* Disable SD clock. It should be disabled before changing the SD clock frequency.*/ + base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK; + + if (busClock_Hz > 0U) + { + while ((srcClock_Hz / prescaler / SDHC_MAX_DVS > busClock_Hz) && (prescaler < SDHC_MAX_CLKFS)) + { + SDHC_NEXT_CLKFS(prescaler); + } + while ((srcClock_Hz / prescaler / divisor > busClock_Hz) && (divisor < SDHC_MAX_DVS)) + { + SDHC_NEXT_DVS(divisor); + } + nearestFrequency = srcClock_Hz / prescaler / divisor; + SDHC_PREV_CLKFS(prescaler); + SDHC_PREV_DVS(divisor); + + /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ + sysctl = base->SYSCTL; + sysctl &= ~(SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DTOCV_MASK); + sysctl |= (SDHC_SYSCTL_DVS(divisor) | SDHC_SYSCTL_SDCLKFS(prescaler) | SDHC_SYSCTL_DTOCV(0xEU)); + base->SYSCTL = sysctl; + + /* Wait until the SD clock is stable. */ + while (!(base->PRSSTAT & SDHC_PRSSTAT_SDSTB_MASK)) + { + } + /* Enable the SD clock. */ + base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK; + } + + return nearestFrequency; +} + +bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout) +{ + base->SYSCTL |= SDHC_SYSCTL_INITA_MASK; + /* Delay some time to wait card become active state. */ + while (!(base->SYSCTL & SDHC_SYSCTL_INITA_MASK)) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config) +{ + assert(config); + + base->BLKATTR = ((base->BLKATTR & ~(SDHC_BLKATTR_BLKSIZE_MASK | SDHC_BLKATTR_BLKCNT_MASK)) | + (SDHC_BLKATTR_BLKSIZE(config->dataBlockSize) | SDHC_BLKATTR_BLKCNT(config->dataBlockCount))); + base->CMDARG = config->commandArgument; + base->XFERTYP = (((config->commandIndex << SDHC_XFERTYP_CMDINX_SHIFT) & SDHC_XFERTYP_CMDINX_MASK) | + (config->flags & (SDHC_XFERTYP_DMAEN_MASK | SDHC_XFERTYP_MSBSEL_MASK | SDHC_XFERTYP_DPSEL_MASK | + SDHC_XFERTYP_CMDTYP_MASK | SDHC_XFERTYP_BCEN_MASK | SDHC_XFERTYP_CICEN_MASK | + SDHC_XFERTYP_CCCEN_MASK | SDHC_XFERTYP_RSPTYP_MASK | SDHC_XFERTYP_DTDSEL_MASK | + SDHC_XFERTYP_AC12EN_MASK))); +} + +void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable) +{ + uint32_t proctl = base->PROCTL; + uint32_t vendor = base->VENDOR; + + if (enable) + { + if (mask & kSDHC_StopAtBlockGapFlag) + { + proctl |= SDHC_PROCTL_SABGREQ_MASK; + } + if (mask & kSDHC_ReadWaitControlFlag) + { + proctl |= SDHC_PROCTL_RWCTL_MASK; + } + if (mask & kSDHC_InterruptAtBlockGapFlag) + { + proctl |= SDHC_PROCTL_IABG_MASK; + } + if (mask & kSDHC_ExactBlockNumberReadFlag) + { + vendor |= SDHC_VENDOR_EXBLKNU_MASK; + } + } + else + { + if (mask & kSDHC_StopAtBlockGapFlag) + { + proctl &= ~SDHC_PROCTL_SABGREQ_MASK; + } + if (mask & kSDHC_ReadWaitControlFlag) + { + proctl &= ~SDHC_PROCTL_RWCTL_MASK; + } + if (mask & kSDHC_InterruptAtBlockGapFlag) + { + proctl &= ~SDHC_PROCTL_IABG_MASK; + } + if (mask & kSDHC_ExactBlockNumberReadFlag) + { + vendor &= ~SDHC_VENDOR_EXBLKNU_MASK; + } + } + + base->PROCTL = proctl; + base->VENDOR = vendor; +} + +void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config) +{ + assert(config); + + uint32_t mmcboot; + + mmcboot = base->MMCBOOT; + mmcboot |= (SDHC_MMCBOOT_DTOCVACK(config->ackTimeoutCount) | SDHC_MMCBOOT_BOOTMODE(config->bootMode) | + SDHC_MMCBOOT_BOOTBLKCNT(config->blockCount)); + if (config->enableBootAck) + { + mmcboot |= SDHC_MMCBOOT_BOOTACK_MASK; + } + if (config->enableBoot) + { + mmcboot |= SDHC_MMCBOOT_BOOTEN_MASK; + } + if (config->enableAutoStopAtBlockGap) + { + mmcboot |= SDHC_MMCBOOT_AUTOSABGEN_MASK; + } + base->MMCBOOT = mmcboot; +} + +status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, + sdhc_dma_mode_t dmaMode, + uint32_t *table, + uint32_t tableWords, + const uint32_t *data, + uint32_t dataBytes) +{ + status_t error = kStatus_Success; + const uint32_t *startAddress; + uint32_t entries; + uint32_t i; +#if defined FSL_SDHC_ENABLE_ADMA1 + sdhc_adma1_descriptor_t *adma1EntryAddress; +#endif + sdhc_adma2_descriptor_t *adma2EntryAddress; + + if ((((!table) || (!tableWords)) && ((dmaMode == kSDHC_DmaModeAdma1) || (dmaMode == kSDHC_DmaModeAdma2))) || + (!data) || (!dataBytes) +#if !defined FSL_SDHC_ENABLE_ADMA1 + || (dmaMode == kSDHC_DmaModeAdma1) +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + ) + { + error = kStatus_InvalidArgument; + } + else + { + switch (dmaMode) + { + case kSDHC_DmaModeNo: + break; +#if defined FSL_SDHC_ENABLE_ADMA1 + case kSDHC_DmaModeAdma1: + startAddress = data; + /* Check if ADMA descriptor's number is enough. */ + entries = ((dataBytes / SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + /* ADMA1 needs two descriptors to finish a transfer */ + entries <<= 1U; + if (entries > ((tableWords * sizeof(uint32_t)) / sizeof(sdhc_adma1_descriptor_t))) + { + error = kStatus_OutOfRange; + } + else + { + adma1EntryAddress = (sdhc_adma1_descriptor_t *)(table); + for (i = 0U; i < entries; i += 2U) + { + /* Each descriptor for ADMA1 is 32-bit in length */ + if ((dataBytes - sizeof(uint32_t) * (startAddress - data)) <= + SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + /* The last piece of data, setting end flag in descriptor */ + adma1EntryAddress[i] = ((uint32_t)(dataBytes - sizeof(uint32_t) * (startAddress - data)) + << SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = + ((uint32_t)(startAddress) << SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] |= + (SDHC_ADMA1_DESCRIPTOR_TYPE_TRANSFER | SDHC_ADMA1_DESCRIPTOR_END_MASK); + } + else + { + adma1EntryAddress[i] = ((uint32_t)SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY + << SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = + ((uint32_t)(startAddress) << SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] |= kSDHC_Adma1DescriptorTypeTransfer; + startAddress += SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY / sizeof(uint32_t); + } + } + + /* When use ADMA, disable simple DMA */ + base->DSADDR = 0U; + base->ADSADDR = (uint32_t)table; + } + break; +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + case kSDHC_DmaModeAdma2: + startAddress = data; + /* Check if ADMA descriptor's number is enough. */ + entries = ((dataBytes / SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + if (entries > ((tableWords * sizeof(uint32_t)) / sizeof(sdhc_adma2_descriptor_t))) + { + error = kStatus_OutOfRange; + } + else + { + adma2EntryAddress = (sdhc_adma2_descriptor_t *)(table); + for (i = 0U; i < entries; i++) + { + /* Each descriptor for ADMA2 is 64-bit in length */ + if ((dataBytes - sizeof(uint32_t) * (startAddress - data)) <= + SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + /* The last piece of data, setting end flag in descriptor */ + adma2EntryAddress[i].address = startAddress; + adma2EntryAddress[i].attribute = ((dataBytes - sizeof(uint32_t) * (startAddress - data)) + << SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= + (kSDHC_Adma2DescriptorTypeTransfer | kSDHC_Adma2DescriptorEndFlag); + } + else + { + adma2EntryAddress[i].address = startAddress; + adma2EntryAddress[i].attribute = + (((SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY / sizeof(uint32_t)) * sizeof(uint32_t)) + << SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= kSDHC_Adma2DescriptorTypeTransfer; + startAddress += (SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY / sizeof(uint32_t)); + } + } + + /* When use ADMA, disable simple DMA */ + base->DSADDR = 0U; + base->ADSADDR = (uint32_t)table; + } + break; + default: + break; + } + } + + return error; +} + +status_t SDHC_TransferBlocking(SDHC_Type *base, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer) +{ + assert(transfer); + assert(transfer->command); /* Command must not be NULL, data can be NULL. */ + + status_t error = kStatus_Success; + sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT); + sdhc_command_t *command = transfer->command; + sdhc_data_t *data = transfer->data; + + /* DATA-PORT is 32-bit align, ADMA2 4 bytes align, ADMA1 is 4096 bytes align */ + if ((!command) || (data && (data->blockSize % 4U))) + { + error = kStatus_InvalidArgument; + } + else + { + /* Wait until command/data bus out of busy status. */ + while (SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) + { + } + while (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag)) + { + } + + /* Update ADMA descriptor table if data isn't NULL. */ + if (data && (kStatus_Success != SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords, + (data->rxData ? data->rxData : data->txData), + (data->blockCount * data->blockSize)))) + { + error = kStatus_SDHC_PrepareAdmaDescriptorFailed; + } + else + { + SDHC_StartTransfer(base, command, data); + + /* Send command and receive data. */ + if (kStatus_Success != SDHC_SendCommandBlocking(base, command)) + { + error = kStatus_SDHC_SendCommandFailed; + } + else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data))) + { + error = kStatus_SDHC_TransferDataFailed; + } + else + { + } + } + } + + return error; +} + +void SDHC_TransferCreateHandle(SDHC_Type *base, + sdhc_handle_t *handle, + const sdhc_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.CardInserted = callback->CardInserted; + handle->callback.CardRemoved = callback->CardRemoved; + handle->callback.SdioInterrupt = callback->SdioInterrupt; + handle->callback.SdioBlockGap = callback->SdioBlockGap; + handle->callback.TransferComplete = callback->TransferComplete; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_sdhcHandle[SDHC_GetInstance(base)] = handle; + + /* Enable interrupt in NVIC. */ + SDHC_SetTransferInterrupt(base, true); + EnableIRQ(s_sdhcIRQ[SDHC_GetInstance(base)]); +} + +status_t SDHC_TransferNonBlocking( + SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer) +{ + assert(transfer); + + sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT); + status_t error = kStatus_Success; + sdhc_command_t *command = transfer->command; + sdhc_data_t *data = transfer->data; + + /* DATA-PORT is 32-bit align, ADMA2 4 bytes align, ADMA1 is 4096 bytes align */ + if ((!(transfer->command)) || ((transfer->data) && (transfer->data->blockSize % 4U))) + { + error = kStatus_InvalidArgument; + } + else + { + /* Wait until command/data bus out of busy status. */ + if ((SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) || + (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag))) + { + error = kStatus_SDHC_BusyTransferring; + } + else + { + /* Update ADMA descriptor table and reset transferred words if data isn't NULL. */ + if (data && (kStatus_Success != SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords, + (data->rxData ? data->rxData : data->txData), + (data->blockCount * data->blockSize)))) + { + error = kStatus_SDHC_PrepareAdmaDescriptorFailed; + } + else + { + /* Save command and data into handle before transferring. */ + handle->command = command; + handle->data = data; + handle->interruptFlags = 0U; + /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ + handle->transferredWords = 0U; + SDHC_StartTransfer(base, command, data); + } + } + } + + return error; +} + +void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags; + + interruptFlags = SDHC_GetInterruptStatusFlags(base); + handle->interruptFlags = interruptFlags; + + if (interruptFlags & kSDHC_CardDetectFlag) + { + SDHC_TransferHandleCardDetect(handle, (interruptFlags & kSDHC_CardDetectFlag)); + } + if (interruptFlags & kSDHC_CommandFlag) + { + SDHC_TransferHandleCommand(base, handle, (interruptFlags & kSDHC_CommandFlag)); + } + if (interruptFlags & kSDHC_DataFlag) + { + SDHC_TransferHandleData(base, handle, (interruptFlags & kSDHC_DataFlag)); + } + if (interruptFlags & kSDHC_CardInterruptFlag) + { + SDHC_TransferHandleSdioInterrupt(handle); + } + if (interruptFlags & kSDHC_BlockGapEventFlag) + { + SDHC_TransferHandleSdioBlockGap(handle); + } + + SDHC_ClearInterruptStatusFlags(base, interruptFlags); +} + +#if defined(SDHC) +void SDHC_DriverIRQHandler(void) +{ + assert(s_sdhcHandle[0]); + + SDHC_TransferHandleIRQ(SDHC, s_sdhcHandle[0]); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h new file mode 100755 index 00000000000..2272402bb15 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h @@ -0,0 +1,1082 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SDHC_H_ +#define _FSL_SDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sdhc + * @{ + */ + +/*! @file */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define SDHC_MAX_BLOCK_COUNT (SDHC_BLKATTR_BLKCNT_MASK >> SDHC_BLKATTR_BLKCNT_SHIFT) + +/*! @brief SDHC status */ +enum _sdhc_status +{ + kStatus_SDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_SDHC, 0U), /*!< Transfer is on-going */ + kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U), /*!< Send command failed */ + kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U), /*!< Transfer data failed */ +}; + +/*! @brief Host controller capabilities flag mask */ +enum _sdhc_capability_flag +{ + kSDHC_SupportAdmaFlag = SDHC_HTCAPBLT_ADMAS_MASK, /*!< Support ADMA */ + kSDHC_SupportHighSpeedFlag = SDHC_HTCAPBLT_HSS_MASK, /*!< Support high-speed */ + kSDHC_SupportDmaFlag = SDHC_HTCAPBLT_DMAS_MASK, /*!< Support DMA */ + kSDHC_SupportSuspendResumeFlag = SDHC_HTCAPBLT_SRS_MASK, /*!< Support suspend/resume */ + kSDHC_SupportV330Flag = SDHC_HTCAPBLT_VS33_MASK, /*!< Support voltage 3.3V */ +#if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT + kSDHC_SupportV300Flag = SDHC_HTCAPBLT_VS30_MASK, /*!< Support voltage 3.0V */ +#endif +#if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT + kSDHC_SupportV180Flag = SDHC_HTCAPBLT_VS18_MASK, /*!< Support voltage 1.8V */ +#endif + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kSDHC_Support4BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kSDHC_Support8BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ +}; + +/*! @brief Wakeup event mask */ +enum _sdhc_wakeup_event +{ + kSDHC_WakeupEventOnCardInt = SDHC_PROCTL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kSDHC_WakeupEventOnCardInsert = SDHC_PROCTL_WECINS_MASK, /*!< Wakeup on card insertion */ + kSDHC_WakeupEventOnCardRemove = SDHC_PROCTL_WECRM_MASK, /*!< Wakeup on card removal */ + + kSDHC_WakeupEventsAll = (kSDHC_WakeupEventOnCardInt | kSDHC_WakeupEventOnCardInsert | + kSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _sdhc_reset +{ + kSDHC_ResetAll = SDHC_SYSCTL_RSTA_MASK, /*!< Reset all except card detection */ + kSDHC_ResetCommand = SDHC_SYSCTL_RSTC_MASK, /*!< Reset command line */ + kSDHC_ResetData = SDHC_SYSCTL_RSTD_MASK, /*!< Reset data line */ + + kSDHC_ResetsAll = (kSDHC_ResetAll | kSDHC_ResetCommand | kSDHC_ResetData), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _sdhc_transfer_flag +{ + kSDHC_EnableDmaFlag = SDHC_XFERTYP_DMAEN_MASK, /*!< Enable DMA */ + + kSDHC_CommandTypeSuspendFlag = (SDHC_XFERTYP_CMDTYP(1U)), /*!< Suspend command */ + kSDHC_CommandTypeResumeFlag = (SDHC_XFERTYP_CMDTYP(2U)), /*!< Resume command */ + kSDHC_CommandTypeAbortFlag = (SDHC_XFERTYP_CMDTYP(3U)), /*!< Abort command */ + + kSDHC_EnableBlockCountFlag = SDHC_XFERTYP_BCEN_MASK, /*!< Enable block count */ + kSDHC_EnableAutoCommand12Flag = SDHC_XFERTYP_AC12EN_MASK, /*!< Enable auto CMD12 */ + kSDHC_DataReadFlag = SDHC_XFERTYP_DTDSEL_MASK, /*!< Enable data read */ + kSDHC_MultipleBlockFlag = SDHC_XFERTYP_MSBSEL_MASK, /*!< Multiple block data read/write */ + + kSDHC_ResponseLength136Flag = SDHC_XFERTYP_RSPTYP(1U), /*!< 136 bit response length */ + kSDHC_ResponseLength48Flag = SDHC_XFERTYP_RSPTYP(2U), /*!< 48 bit response length */ + kSDHC_ResponseLength48BusyFlag = SDHC_XFERTYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kSDHC_EnableCrcCheckFlag = SDHC_XFERTYP_CCCEN_MASK, /*!< Enable CRC check */ + kSDHC_EnableIndexCheckFlag = SDHC_XFERTYP_CICEN_MASK, /*!< Enable index check */ + kSDHC_DataPresentFlag = SDHC_XFERTYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _sdhc_present_status_flag +{ + kSDHC_CommandInhibitFlag = SDHC_PRSSTAT_CIHB_MASK, /*!< Command inhibit */ + kSDHC_DataInhibitFlag = SDHC_PRSSTAT_CDIHB_MASK, /*!< Data inhibit */ + kSDHC_DataLineActiveFlag = SDHC_PRSSTAT_DLA_MASK, /*!< Data line active */ + kSDHC_SdClockStableFlag = SDHC_PRSSTAT_SDSTB_MASK, /*!< SD bus clock stable */ + kSDHC_WriteTransferActiveFlag = SDHC_PRSSTAT_WTA_MASK, /*!< Write transfer active */ + kSDHC_ReadTransferActiveFlag = SDHC_PRSSTAT_RTA_MASK, /*!< Read transfer active */ + kSDHC_BufferWriteEnableFlag = SDHC_PRSSTAT_BWEN_MASK, /*!< Buffer write enable */ + kSDHC_BufferReadEnableFlag = SDHC_PRSSTAT_BREN_MASK, /*!< Buffer read enable */ + kSDHC_CardInsertedFlag = SDHC_PRSSTAT_CINS_MASK, /*!< Card inserted */ + kSDHC_CommandLineLevelFlag = SDHC_PRSSTAT_CLSL_MASK, /*!< Command line signal level */ + kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */ + kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */ + kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */ + kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */ + kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */ + kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */ + kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */ + kSDHC_Data7LineLevelFlag = (1U << 31U), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _sdhc_interrupt_status_flag +{ + kSDHC_CommandCompleteFlag = SDHC_IRQSTAT_CC_MASK, /*!< Command complete */ + kSDHC_DataCompleteFlag = SDHC_IRQSTAT_TC_MASK, /*!< Data complete */ + kSDHC_BlockGapEventFlag = SDHC_IRQSTAT_BGE_MASK, /*!< Block gap event */ + kSDHC_DmaCompleteFlag = SDHC_IRQSTAT_DINT_MASK, /*!< DMA interrupt */ + kSDHC_BufferWriteReadyFlag = SDHC_IRQSTAT_BWR_MASK, /*!< Buffer write ready */ + kSDHC_BufferReadReadyFlag = SDHC_IRQSTAT_BRR_MASK, /*!< Buffer read ready */ + kSDHC_CardInsertionFlag = SDHC_IRQSTAT_CINS_MASK, /*!< Card inserted */ + kSDHC_CardRemovalFlag = SDHC_IRQSTAT_CRM_MASK, /*!< Card removed */ + kSDHC_CardInterruptFlag = SDHC_IRQSTAT_CINT_MASK, /*!< Card interrupt */ + kSDHC_CommandTimeoutFlag = SDHC_IRQSTAT_CTOE_MASK, /*!< Command timeout error */ + kSDHC_CommandCrcErrorFlag = SDHC_IRQSTAT_CCE_MASK, /*!< Command CRC error */ + kSDHC_CommandEndBitErrorFlag = SDHC_IRQSTAT_CEBE_MASK, /*!< Command end bit error */ + kSDHC_CommandIndexErrorFlag = SDHC_IRQSTAT_CIE_MASK, /*!< Command index error */ + kSDHC_DataTimeoutFlag = SDHC_IRQSTAT_DTOE_MASK, /*!< Data timeout error */ + kSDHC_DataCrcErrorFlag = SDHC_IRQSTAT_DCE_MASK, /*!< Data CRC error */ + kSDHC_DataEndBitErrorFlag = SDHC_IRQSTAT_DEBE_MASK, /*!< Data end bit error */ + kSDHC_AutoCommand12ErrorFlag = SDHC_IRQSTAT_AC12E_MASK, /*!< Auto CMD12 error */ + kSDHC_DmaErrorFlag = SDHC_IRQSTAT_DMAE_MASK, /*!< DMA error */ + + kSDHC_CommandErrorFlag = (kSDHC_CommandTimeoutFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag | + kSDHC_CommandIndexErrorFlag), /*!< Command error */ + kSDHC_DataErrorFlag = (kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | kSDHC_DataEndBitErrorFlag | + kSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kSDHC_ErrorFlag = (kSDHC_CommandErrorFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< All error */ + kSDHC_DataFlag = (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_BufferWriteReadyFlag | + kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< Data interrupts */ + kSDHC_CommandFlag = (kSDHC_CommandErrorFlag | kSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kSDHC_CardDetectFlag = (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + + kSDHC_AllInterruptFlags = (kSDHC_BlockGapEventFlag | kSDHC_CardInterruptFlag | kSDHC_CommandFlag | kSDHC_DataFlag | + kSDHC_ErrorFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _sdhc_auto_command12_error_status_flag +{ + kSDHC_AutoCommand12NotExecutedFlag = SDHC_AC12ERR_AC12NE_MASK, /*!< Not executed error */ + kSDHC_AutoCommand12TimeoutFlag = SDHC_AC12ERR_AC12TOE_MASK, /*!< Timeout error */ + kSDHC_AutoCommand12EndBitErrorFlag = SDHC_AC12ERR_AC12EBE_MASK, /*!< End bit error */ + kSDHC_AutoCommand12CrcErrorFlag = SDHC_AC12ERR_AC12CE_MASK, /*!< CRC error */ + kSDHC_AutoCommand12IndexErrorFlag = SDHC_AC12ERR_AC12IE_MASK, /*!< Index error */ + kSDHC_AutoCommand12NotIssuedFlag = SDHC_AC12ERR_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief ADMA error status flag mask */ +enum _sdhc_adma_error_status_flag +{ + kSDHC_AdmaLenghMismatchFlag = SDHC_ADMAES_ADMALME_MASK, /*!< Length mismatch error */ + kSDHC_AdmaDescriptorErrorFlag = SDHC_ADMAES_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +typedef enum _sdhc_adma_error_state +{ + kSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */ + kSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */ + kSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */ + kSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ +} sdhc_adma_error_state_t; + +/*! @brief Force event mask */ +enum _sdhc_force_event +{ + kSDHC_ForceEventAutoCommand12NotExecuted = SDHC_FEVT_AC12NE_MASK, /*!< Auto CMD12 not executed error */ + kSDHC_ForceEventAutoCommand12Timeout = SDHC_FEVT_AC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kSDHC_ForceEventAutoCommand12CrcError = SDHC_FEVT_AC12CE_MASK, /*!< Auto CMD12 CRC error */ + kSDHC_ForceEventEndBitError = SDHC_FEVT_AC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kSDHC_ForceEventAutoCommand12IndexError = SDHC_FEVT_AC12IE_MASK, /*!< Auto CMD12 index error */ + kSDHC_ForceEventAutoCommand12NotIssued = SDHC_FEVT_CNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kSDHC_ForceEventCommandTimeout = SDHC_FEVT_CTOE_MASK, /*!< Command timeout error */ + kSDHC_ForceEventCommandCrcError = SDHC_FEVT_CCE_MASK, /*!< Command CRC error */ + kSDHC_ForceEventCommandEndBitError = SDHC_FEVT_CEBE_MASK, /*!< Command end bit error */ + kSDHC_ForceEventCommandIndexError = SDHC_FEVT_CIE_MASK, /*!< Command index error */ + kSDHC_ForceEventDataTimeout = SDHC_FEVT_DTOE_MASK, /*!< Data timeout error */ + kSDHC_ForceEventDataCrcError = SDHC_FEVT_DCE_MASK, /*!< Data CRC error */ + kSDHC_ForceEventDataEndBitError = SDHC_FEVT_DEBE_MASK, /*!< Data end bit error */ + kSDHC_ForceEventAutoCommand12Error = SDHC_FEVT_AC12E_MASK, /*!< Auto CMD12 error */ + kSDHC_ForceEventCardInt = SDHC_FEVT_CINT_MASK, /*!< Card interrupt */ + kSDHC_ForceEventDmaError = SDHC_FEVT_DMAE_MASK, /*!< Dma error */ + + kSDHC_ForceEventsAll = + (kSDHC_ForceEventAutoCommand12NotExecuted | kSDHC_ForceEventAutoCommand12Timeout | + kSDHC_ForceEventAutoCommand12CrcError | kSDHC_ForceEventEndBitError | kSDHC_ForceEventAutoCommand12IndexError | + kSDHC_ForceEventAutoCommand12NotIssued | kSDHC_ForceEventCommandTimeout | kSDHC_ForceEventCommandCrcError | + kSDHC_ForceEventCommandEndBitError | kSDHC_ForceEventCommandIndexError | kSDHC_ForceEventDataTimeout | + kSDHC_ForceEventDataCrcError | kSDHC_ForceEventDataEndBitError | kSDHC_ForceEventAutoCommand12Error | + kSDHC_ForceEventCardInt | kSDHC_ForceEventDmaError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _sdhc_data_bus_width +{ + kSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} sdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _sdhc_endian_mode +{ + kSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} sdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _sdhc_dma_mode +{ + kSDHC_DmaModeNo = 0U, /*!< No DMA */ + kSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ +} sdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _sdhc_sdio_control_flag +{ + kSDHC_StopAtBlockGapFlag = 0x01, /*!< Stop at block gap */ + kSDHC_ReadWaitControlFlag = 0x02, /*!< Read wait control */ + kSDHC_InterruptAtBlockGapFlag = 0x04, /*!< Interrupt at block gap */ + kSDHC_ExactBlockNumberReadFlag = 0x08, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _sdhc_boot_mode +{ + kSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} sdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _sdhc_command_type +{ + kSDHC_CommandTypeNormal = 0U, /*!< Normal command */ + kSDHC_CommandTypeSuspend = 1U, /*!< Suspend command */ + kSDHC_CommandTypeResume = 2U, /*!< Resume command */ + kSDHC_CommandTypeAbort = 3U, /*!< Abort command */ +} sdhc_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _sdhc_response_type +{ + kSDHC_ResponseTypeNone = 0U, /*!< Response type: none */ + kSDHC_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kSDHC_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kSDHC_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kSDHC_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kSDHC_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kSDHC_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kSDHC_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kSDHC_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kSDHC_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} sdhc_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define SDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define SDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define SDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define SDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The max value of LENGTH filed in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _sdhc_adma1_descriptor_flag +{ + kSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kSDHC_Adma1DescriptorTypeNop = (kSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kSDHC_Adma1DescriptorTypeTransfer = + (kSDHC_Adma1DescriptorActivity2Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kSDHC_Adma1DescriptorTypeLink = (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorActivity2Flag | + kSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kSDHC_Adma1DescriptorTypeSetLength = + (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The max value of LENGTH field in ADMA2's descriptor */ +#define SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _sdhc_adma2_descriptor_flag +{ + kSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kSDHC_Adma2DescriptorTypeNop = (kSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kSDHC_Adma2DescriptorTypeReserved = + (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kSDHC_Adma2DescriptorTypeTransfer = + (kSDHC_Adma2DescriptorActivity2Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kSDHC_Adma2DescriptorTypeLink = (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorActivity2Flag | + kSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief Define the adma1 descriptor structure. */ +typedef uint32_t sdhc_adma1_descriptor_t; + +/*! @brief Define the ADMA2 descriptor structure. */ +typedef struct _sdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} sdhc_adma2_descriptor_t; + +/*! + * @brief SDHC capability information. + * + * Define structure to save the capability information of SDHC. + */ +typedef struct _sdhc_capability +{ + uint32_t specVersion; /*!< Specification version */ + uint32_t vendorVersion; /*!< Vendor version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_sdhc_capability_flag) */ +} sdhc_capability_t; + +/*! @brief Card transfer configuration. + * + * Define structure to configure the transfer-related command index/argument/flags and data block + * size/data block numbers. This structure needs to be filled each time a command is sent to the card. + */ +typedef struct _sdhc_transfer_config +{ + size_t dataBlockSize; /*!< Data block size */ + uint32_t dataBlockCount; /*!< Data block count */ + uint32_t commandArgument; /*!< Command argument */ + uint32_t commandIndex; /*!< Command index */ + uint32_t flags; /*!< Transfer flags(_sdhc_transfer_flag) */ +} sdhc_transfer_config_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _sdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK */ + sdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableBoot; /*!< Enable or disable fast boot */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} sdhc_boot_config_t; + +/*! @brief Data structure to initialize the SDHC */ +typedef struct _sdhc_config +{ + bool cardDetectDat3; /*!< Enable DAT3 as card detection pin */ + sdhc_endian_mode_t endianMode; /*!< Endian mode */ + sdhc_dma_mode_t dmaMode; /*!< DMA mode */ + uint32_t readWatermarkLevel; /*!< Watermark level for DMA read operation */ + uint32_t writeWatermarkLevel; /*!< Watermark level for DMA write operation */ +} sdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Define structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _sdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} sdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _sdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + sdhc_command_type_t type; /*!< Command type */ + sdhc_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ +} sdhc_command_t; + +/*! @brief Transfer state */ +typedef struct _sdhc_transfer +{ + sdhc_data_t *data; /*!< Data to transfer */ + sdhc_command_t *command; /*!< Command to send */ +} sdhc_transfer_t; + +/*! @brief SDHC handle typedef */ +typedef struct _sdhc_handle sdhc_handle_t; + +/*! @brief SDHC callback functions. */ +typedef struct _sdhc_transfer_callback +{ + void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(void); /*!< Card removed occurs */ + void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */ + void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */ + void (*TransferComplete)(SDHC_Type *base, + sdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} sdhc_transfer_callback_t; + +/*! + * @brief Host descriptor + * + * Define the structure to save the SDHC state information and callback function. The detail interrupt status when + * send command or transfer data can be obtained from interruptFlags field by using mask defined in sdhc_interrupt_flag_t; + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _sdhc_handle +{ + /* Transfer parameter */ + sdhc_data_t *volatile data; /*!< Data to transfer */ + sdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + sdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief SDHC transfer function. */ +typedef status_t (*sdhc_transfer_function_t)(SDHC_Type *base, sdhc_transfer_t *content); + +/*! @brief SDHC host descriptor */ +typedef struct _sdhc_host +{ + SDHC_Type *base; /*!< SDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< SDHC source clock frequency united in Hz */ + sdhc_config_t config; /*!< SDHC configuration */ + sdhc_capability_t capability; /*!< SDHC capability information */ + sdhc_transfer_function_t transfer; /*!< SDHC transfer function */ +} sdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief SDHC module initialization function. + * + * Configure the SDHC according to the user configuration. + * + * Example: + @code + sdhc_config_t config; + config.enableDat3AsCDPin = false; + config.endianMode = kSDHC_EndianModeLittle; + config.dmaMode = kSDHC_DmaModeAdma2; + config.readWatermarkLevel = 512U; + config.writeWatermarkLevel = 512U; + SDHC_Init(SDHC, &config); + @endcode + * + * @param base SDHC peripheral base address. + * @param config SDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config); + +/*! + * @brief Deinitialize the SDHC. + * + * @param base SDHC peripheral base address. + */ +void SDHC_Deinit(SDHC_Type *base); + +/*! + * @brief Reset the SDHC. + * + * @param base SDHC peripheral base address. + * @param mask The reset type mask(_sdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Set ADMA descriptor table configuration. + * + * @param base SDHC peripheral base address. + * @param dmaMode DMA mode. + * @param table ADMA table address. + * @param tableWords ADMA table buffer length united as Words. + * @param data Data buffer address. + * @param dataBytes Data length united as bytes. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, + sdhc_dma_mode_t dmaMode, + uint32_t *table, + uint32_t tableWords, + const uint32_t *data, + uint32_t dataBytes); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupt status + * + * @param base SDHC peripheral base address. + * @param mask Interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_EnableInterruptStatus(SDHC_Type *base, uint32_t mask) +{ + base->IRQSTATEN |= mask; +} + +/*! + * @brief Disable interrupt status. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_DisableInterruptStatus(SDHC_Type *base, uint32_t mask) +{ + base->IRQSTATEN &= ~mask; +} + +/*! + * @brief Enable interrupts signal corresponding to the interrupt status flag. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_EnableInterruptSignal(SDHC_Type *base, uint32_t mask) +{ + base->IRQSIGEN |= mask; +} + +/*! + * @brief Disable interrupts signal corresponding to the interrupt status flag. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_DisableInterruptSignal(SDHC_Type *base, uint32_t mask) +{ + base->IRQSIGEN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get current interrupt status. + * + * @param base SDHC peripheral base address. + * @return Current interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline uint32_t SDHC_GetInterruptStatusFlags(SDHC_Type *base) +{ + return base->IRQSTAT; +} + +/*! + * @brief Clear specified interrupt status. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_ClearInterruptStatusFlags(SDHC_Type *base, uint32_t mask) +{ + base->IRQSTAT = mask; +} + +/*! + * @brief Get the status of auto command 12 error. + * + * @param base SDHC peripheral base address. + * @return Auto command 12 error status flags mask(_sdhc_auto_command12_error_status_flag). + */ +static inline uint32_t SDHC_GetAutoCommand12ErrorStatusFlags(SDHC_Type *base) +{ + return base->AC12ERR; +} + +/*! + * @brief Get the status of ADMA error. + * + * @param base SDHC peripheral base address. + * @return ADMA error status flags mask(_sdhc_adma_error_status_flag). + */ +static inline uint32_t SDHC_GetAdmaErrorStatusFlags(SDHC_Type *base) +{ + return base->ADMAES; +} + +/*! + * @brief Get present status. + * + * This function gets the present SDHC's status except for interrupt status and error status. + * + * @param base SDHC peripheral base address. + * @return Present SDHC's status flags mask(_sdhc_present_status_flag). + */ +static inline uint32_t SDHC_GetPresentStatusFlags(SDHC_Type *base) +{ + return base->PRSSTAT; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the capability information + * + * @param base SDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability); + +/*! + * @brief Enable or disable SD bus clock. + * + * @param base SDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void SDHC_EnableSdClock(SDHC_Type *base, bool enable) +{ + if (enable) + { + base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK; + } + else + { + base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK; + } +} + +/*! + * @brief Set SD bus clock frequency. + * + * @param base SDHC peripheral base address. + * @param srcClock_Hz SDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Send 80 clocks to the card to set it to be active state. + * + * This function must be called after each time the card is inserted to make card can receive command correctly. + * + * @param base SDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout); + +/*! + * @brief Set the data transfer width. + * + * @param base SDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t width) +{ + base->PROCTL = ((base->PROCTL & ~SDHC_PROCTL_DTW_MASK) | SDHC_PROCTL_DTW(width)); +} + +/*! + * @brief Set card transfer-related configuration. + * + * This function fills card transfer-related command argument/transfer flag/data size. Command and data will be sent by + * SDHC after calling this function. + * + * Example: + @code + sdhc_transfer_config_t transferConfig; + transferConfig.dataBlockSize = 512U; + transferConfig.dataBlockCount = 2U; + transferConfig.commandArgument = 0x01AAU; + transferConfig.commandIndex = 8U; + transferConfig.flags |= (kSDHC_EnableDmaFlag | kSDHC_EnableAutoCommand12Flag | kSDHC_MultipleBlockFlag); + SDHC_SetTransferConfig(SDHC, &transferConfig); + @endcode + * + * @param base SDHC peripheral base address. + * @param config Command configuration structure. + */ +void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config); + +/*! + * @brief Get the command response. + * + * @param base SDHC peripheral base address. + * @param index The index of response register, range from 0 to 3. + * @return Response register transfer. + */ +static inline uint32_t SDHC_GetCommandResponse(SDHC_Type *base, uint32_t index) +{ + assert(index < 4U); + + return base->CMDRSP[index]; +} + +/*! + * @brief Fill the the data port. + * + * This function is mainly used to implement the data transfer by Data Port instead of DMA. + * + * @param base SDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void SDHC_WriteData(SDHC_Type *base, uint32_t data) +{ + base->DATPORT = data; +} + +/*! + * @brief Retrieve the data from the data port. + * + * This function is mainly used to implement the data transfer by Data Port instead of DMA. + * + * @param base SDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t SDHC_ReadData(SDHC_Type *base) +{ + return base->DATPORT; +} + +/*! + * @brief Enable or disable wakeup event in low power mode + * + * @param base SDHC peripheral base address. + * @param mask Wakeup events mask(_sdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void SDHC_EnableWakeupEvent(SDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROCTL |= mask; + } + else + { + base->PROCTL &= ~mask; + } +} + +/*! + * @brief Enable or disable card detection level for test. + * + * @param base SDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void SDHC_EnableCardDetectTest(SDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROCTL |= SDHC_PROCTL_CDSS_MASK; + } + else + { + base->PROCTL &= ~SDHC_PROCTL_CDSS_MASK; + } +} + +/*! + * @brief Set card detection test level. + * + * This function set the card detection test level to indicate whether the card is inserted into SDHC when DAT[3]/ + * CD pin is selected as card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is select + * as the card detection pin. + * + * @param base SDHC peripheral base address. + * @param high True to set the card detect level to high. + */ +static inline void SDHC_SetCardDetectTestLevel(SDHC_Type *base, bool high) +{ + if (high) + { + base->PROCTL |= SDHC_PROCTL_CDTL_MASK; + } + else + { + base->PROCTL &= ~SDHC_PROCTL_CDTL_MASK; + } +} + +/*! + * @brief Enable or disable SDIO card control. + * + * @param base SDHC peripheral base address. + * @param mask SDIO card control flags mask(_sdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Restart a transaction which has stopped at the block gap for SDIO card. + * + * @param base SDHC peripheral base address. + */ +static inline void SDHC_SetContinueRequest(SDHC_Type *base) +{ + base->PROCTL |= SDHC_PROCTL_CREQ_MASK; +} + +/*! + * @brief Configure the MMC boot feature. + * + * Example: + @code + sdhc_boot_config_t bootConfig; + bootConfig.ackTimeoutCount = 4; + bootConfig.bootMode = kSDHC_BootModeNormal; + bootConfig.blockCount = 5; + bootConfig.enableBootAck = true; + bootConfig.enableBoot = true; + enableBoot.enableAutoStopAtBlockGap = true; + SDHC_SetMmcBootConfig(SDHC, &bootConfig); + @endcode + * + * @param base SDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config); + +/*! + * @brief Force to generate events according to the given mask. + * + * @param base SDHC peripheral base address. + * @param mask The force events mask(_sdhc_force_event). + */ +static inline void SDHC_SetForceEvent(SDHC_Type *base, uint32_t mask) +{ + base->FEVT = mask; +} + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfer command/data using blocking way. + * + * This function waits until the command response/data is got or SDHC encounters error by polling the status flag. + * Application must not call this API in multiple threads at the same time because of that this API doesn't support + * reentry mechanism. + * + * @note Needn't to call the API 'SDHC_TransferCreateHandle' when calling this API. + * + * @param base SDHC peripheral base address. + * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2. + * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_SDHC_SendCommandFailed Send command failed. + * @retval kStatus_SDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDHC_TransferBlocking(SDHC_Type *base, + uint32_t *admaTable, + uint32_t admaTableWords, + sdhc_transfer_t *transfer); + +/*! + * @brief Create the SDHC handle. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void SDHC_TransferCreateHandle(SDHC_Type *base, + sdhc_handle_t *handle, + const sdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfer command/data using interrupt and asynchronous way. + * + * This function send command and data and return immediately. It doesn't wait the transfer complete or encounter error. + * Application must not call this API in multiple threads at the same time because of that this API doesn't support + * reentry mechanism. + * + * @note Must call the API 'SDHC_TransferCreateHandle' when calling this API. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2. + * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_SDHC_BusyTransferring Busy transferring. + * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDHC_TransferNonBlocking( + SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for SDHC + * + * This function deals with IRQs on the given host controller. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + */ +void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_SDHC_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c new file mode 100755 index 00000000000..3a4b801b7b3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_sim.h" + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) +{ + SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); + + SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; +} +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +void SIM_GetUniqueId(sim_uid_t *uid) +{ +#if defined(SIM_UIDH) + uid->H = SIM->UIDH; +#endif + uid->MH = SIM->UIDMH; + uid->ML = SIM->UIDML; + uid->L = SIM->UIDL; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h new file mode 100755 index 00000000000..a3b69188841 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _FSL_SIM_H_ +#define _FSL_SIM_H_ + +#include "fsl_common.h" + +/*! @addtogroup sim */ +/*! @{*/ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ +/*@}*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*!@brief USB voltage regulator enable setting. */ +enum _sim_usb_volt_reg_enable_mode +{ + kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ + kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ + kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ + kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | + SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ +}; +#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ + +/*!@brief Unique ID. */ +typedef struct _sim_uid +{ +#if defined(SIM_UIDH) + uint32_t H; /*!< UIDH. */ +#endif + uint32_t MH; /*!< UIDMH. */ + uint32_t ML; /*!< UIDML. */ + uint32_t L; /*!< UIDL. */ +} sim_uid_t; + +/*!@brief Flash enable mode. */ +enum _sim_flash_mode +{ + kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ + kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*! + * @brief Sets the USB voltage regulator setting. + * + * This function configures whether the USB voltage regulator is enabled in + * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations + * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable + * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, + * please use: + * + * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); + * + * @param mask USB voltage regulator enable setting. + */ +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +/*! + * @brief Get the unique identification register value. + * + * @param uid Pointer to the structure to save the UID value. + */ +void SIM_GetUniqueId(sim_uid_t *uid); + +/*! + * @brief Set the flash enable mode. + * + * @param mode The mode to set, see \ref _sim_flash_mode for mode details. + */ +static inline void SIM_SetFlashMode(uint8_t mode) +{ + SIM->FCFG1 = mode; +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_SIM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c new file mode 100755 index 00000000000..0018cf7dce2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_smc.h" + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +void SMC_GetParam(SMC_Type *base, smc_param_t *param) +{ + uint32_t reg = base->PARAM; + param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); + param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); + param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); + param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); +} +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +status_t SMC_SetPowerModeRun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure Normal RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +status_t SMC_SetPowerModeHsrun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure High Speed RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +status_t SMC_SetPowerModeWait(SMC_Type *base) +{ + /* configure Normal Wait mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) + /* configure the Partial Stop mode in Noraml Stop mode */ + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_PSTOPO_MASK; + reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); + base->STOPCTRL = reg; +#endif + + /* configure Normal Stop mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter Stop mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +status_t SMC_SetPowerModeVlpr(SMC_Type *base +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + , + bool wakeupMode +#endif + ) +{ + uint8_t reg; + + reg = base->PMCTRL; +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + /* configure whether the system remains in VLP mode on an interrupt */ + if (wakeupMode) + { + /* exits to RUN mode on an interrupt */ + reg |= SMC_PMCTRL_LPWUI_MASK; + } + else + { + /* remains in VLP mode on an interrupt */ + reg &= ~SMC_PMCTRL_LPWUI_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + + /* configure VLPR mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlpw(SMC_Type *base) +{ + /* Power mode transaction to VLPW can only happen in VLPR mode */ + if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base)) + { + return kStatus_Fail; + } + + /* configure VLPW mode */ + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlps(SMC_Type *base) +{ + uint8_t reg; + + /* configure VLPS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter VLPS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeLls(SMC_Type *base +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) + , + const smc_power_mode_lls_config_t *config +#endif + ) +{ + uint8_t reg; + + /* configure to LLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure LLS sub-mode*/ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + if (config->subMode == kSMC_StopSub0) +#endif + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enablePorDetectInVlls0) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; +#endif + } + } +#endif /* FSL_FEATURE_SMC_HAS_PORPO */ + +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + else if (config->subMode == kSMC_StopSub2) + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enableRam2InVlls2) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + } + else + { + } +#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ + + /* configure to VLLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure the VLLS sub-mode */ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + reg = base->VLLSCTRL; + reg &= ~SMC_VLLSCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); + base->VLLSCTRL = reg; +#else +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#else + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ +#endif + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h new file mode 100755 index 00000000000..5149f87e346 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SMC_H_ +#define _FSL_SMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup smc */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMC driver version 2.0.1. */ +#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief Power Modes Protection + */ +typedef enum _smc_power_mode_protection +{ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + kSMC_AllowPowerModeAll = (0U +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_AVLLS_MASK +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_ALLS_MASK +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + | + SMC_PMPROT_AVLP_MASK +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + | + kSMC_AllowPowerModeHsrun +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + ) /*!< Allow all power mode. */ +} smc_power_mode_protection_t; + +/*! + * @brief Power Modes in PMSTAT + */ +typedef enum _smc_power_state +{ + kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ + kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ + kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ + kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ + kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_power_state_t; + +/*! + * @brief Run mode definition + */ +typedef enum _smc_run_mode +{ + kSMC_RunNormal = 0U, /*!< normal RUN mode. */ + kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_run_mode_t; + +/*! + * @brief Stop mode definition + */ +typedef enum _smc_stop_mode +{ + kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ + kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_StopVlls = 4U /*!< Very-Low-Leakage Stop mode. */ +#endif +} smc_stop_mode_t; + +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) +/*! + * @brief VLLS/LLS stop sub mode definition + */ +typedef enum _smc_stop_submode +{ + kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ + kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ + kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ + kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ +} smc_stop_submode_t; +#endif + +/*! + * @brief Partial STOP option + */ +typedef enum _smc_partial_stop_mode +{ + kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ + kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ + kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ +} smc_partial_stop_option_t; + +/*! + * @brief SMC configuration status + */ +enum _smc_status +{ + kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ +}; + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _smc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} smc_version_id_t; +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _smc_param +{ + bool hsrunEnable; /*!< HSRUN mode enable. */ + bool llsEnable; /*!< LLS mode enable. */ + bool lls2Enable; /*!< LLS2 mode enable. */ + bool vlls0Enable; /*!< VLLS0 mode enable. */ +} smc_param_t; +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) +/*! + * @brief SMC Low-Leakage Stop power mode config + */ +typedef struct _smc_power_mode_lls_config +{ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ +#endif +} smc_power_mode_lls_config_t; +#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief SMC Very Low-Leakage Stop power mode config + */ +typedef struct _smc_power_mode_vlls_config +{ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) + bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ +#endif +} smc_power_mode_vlls_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name System mode controller APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief Gets the SMC version ID. + * + * This function gets the SMC version ID, including major version number, + * minor version number and feature specification number. + * + * @param base SMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief Gets the SMC parameter. + * + * This function gets the SMC parameter, including the enabled power mdoes. + * + * @param base SMC peripheral base address. + * @param param Pointer to SMC param structure. + */ +void SMC_GetParam(SMC_Type *base, smc_param_t *param); +#endif + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes in the specified chip family. The available power modes + * are defined in the smc_power_mode_protection_t. This should be done at an early + * system level initialization stage. See the reference manual for details. + * This register can only write once after the power reset. + * + * The allowed modes are passed as bit map, for example, to allow LLS and VLLS, + * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). + * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). + * + * @param base SMC peripheral base address. + * @param allowedModes Bitmap of the allowed power modes. + */ +static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) +{ + base->PMPROT = allowedModes; +} + +/*! + * @brief Gets the current power mode status. + * + * This function returns the current power mode stat. Once application + * switches the power mode, it should always check the stat to check whether it + * runs into the specified mode or not. An application should check + * this mode before switching to a different mode. The system requires that + * only certain modes can switch to other specific modes. See the + * reference manual for details and the smc_power_state_t for information about + * the power stat. + * + * @param base SMC peripheral base address. + * @return Current power mode status. + */ +static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) +{ + return (smc_power_state_t)base->PMSTAT; +} + +/*! + * @brief Configure the system to RUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeRun(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * @brief Configure the system to HSRUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeHsrun(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +/*! + * @brief Configure the system to WAIT power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeWait(SMC_Type *base); + +/*! + * @brief Configure the system to Stop power mode. + * + * @param base SMC peripheral base address. + * @param option Partial Stop mode option. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); + +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) +/*! + * @brief Configure the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); +#else +/*! + * @brief Configure the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + +/*! + * @brief Configure the system to VLPW power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpw(SMC_Type *base); + +/*! + * @brief Configure the system to VLPS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlps(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) +/*! + * @brief Configure the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @param config The LLS power mode configuration structure + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); +#else +/*! + * @brief Configure the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base); +#endif +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief Configure the system to VLLS power mode. + * + * @param base SMC peripheral base address. + * @param config The VLLS power mode configuration structure. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_SMC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c new file mode 100755 index 00000000000..b0b92399db4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c @@ -0,0 +1,1032 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy /* RX busy. */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ +static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS; +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; + +/* UART ISR for transactional APIs. */ +static uart_isr_t s_uartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + + assert(instance < uartArrayCount); + + return instance; +} + +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + uint16_t sbr; + uint8_t temp; + + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (config->baudRate_Bps * 16); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr; + + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + + if (kUART_ParityDisabled != config->parityMode) + { + temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode); + } + + base->C1 = temp; + +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Set tx/rx FIFO watermark */ + base->TWFIFO = config->txFifoWatermark; + base->RWFIFO = config->rxFifoWatermark; + + /* Enable tx/rx FIFO */ + base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK); + + /* Flush FIFO */ + base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); +#endif + + /* Enable TX/RX base on configure structure. */ + temp = base->C2; + + if (config->enableTx) + { + temp |= UART_C2_TE_MASK; + } + + if (config->enableRx) + { + temp |= UART_C2_RE_MASK; + } + + base->C2 = temp; +} + +void UART_Deinit(UART_Type *base) +{ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != base->TCFIFO) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->S1 & UART_S1_TC_MASK)) + { + } + + /* Disable the module. */ + base->C2 = 0; + + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +} + +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 1; +#endif + config->enableTx = false; + config->enableRx = false; +} + +void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t sbr; + uint8_t oldCtrl; + + /* Store C2 before disable Tx and Rx */ + oldCtrl = base->C2; + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (baudRate_Bps * 16); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr; + + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Restore C2. */ + base->C2 = oldCtrl; +} + +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH |= (mask & 0xFF); + base->C2 |= ((mask >> 8) & 0xFF); + base->C3 |= ((mask >> 16) & 0xFF); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO |= ((mask >> 24) & 0xFF); +#endif +} + +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH &= ~(mask & 0xFF); + base->C2 &= ~((mask >> 8) & 0xFF); + base->C3 &= ~((mask >> 16) & 0xFF); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO &= ~((mask >> 24) & 0xFF); +#endif +} + +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + uint32_t temp; + + temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + temp |= ((uint32_t)(base->CFIFO) << 24); +#endif + + return temp; +} + +uint32_t UART_GetStatusFlags(UART_Type *base) +{ + uint32_t status_flag; + + status_flag = base->S1 | ((uint32_t)(base->S2) << 8); + +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + status_flag |= ((uint32_t)(base->ED) << 16); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + status_flag |= ((uint32_t)(base->SFIFO) << 24); +#endif + + return status_flag; +} + +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) +{ + uint8_t reg = base->S2; + status_t status; + +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK); +#else + reg &= ~UART_S2_RXEDGIF_MASK; +#endif + + base->S2 = reg | (uint8_t)(mask >> 8); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->SFIFO = (uint8_t)(mask >> 24); +#endif + + if (mask & (kUART_IdleLineFlag | kUART_RxOverrunFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | + kUART_ParityErrorFlag)) + { + /* Read base->D to clear the flags. */ + (void)base->S1; + (void)base->D; + } + + /* If some flags still pending. */ + if (mask & UART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag, + kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, + kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */ + status = kStatus_UART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->S1 & UART_S1_TDRE_MASK)) + { + } + base->D = *(data++); + } +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->D = data[i]; + } +} + +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + + while (length--) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + while (!base->RCFIFO) +#else + while (!(base->S1 & UART_S1_RDRF_MASK)) +#endif + { + statusFlag = UART_GetStatusFlags(base); + + if (statusFlag & kUART_RxOverrunFlag) + { + return kStatus_UART_RxHardwareOverrun; + } + + if (statusFlag & kUART_NoiseErrorFlag) + { + return kStatus_UART_NoiseError; + } + + if (statusFlag & kUART_FramingErrorFlag) + { + return kStatus_UART_FramingError; + } + + if (statusFlag & kUART_ParityErrorFlag) + { + return kStatus_UART_ParityError; + } + } + *(data++) = base->D; + } + + return kStatus_Success; +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = base->D; + } +} + +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->RWFIFO = 1U; +#endif + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_uartIRQ[instance]); +} + +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ringbuffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } +} + +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kUART_RxIdle) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kUART_TxIdle; +} + +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + } + + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + + /* Enable RX interrupt. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + + assert(handle); + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->D; + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = base->RCFIFO; +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->D; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO; +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->C2 = (base->C2 & ~UART_C2_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } + } + } +} + +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) +{ + /* TODO: To be implemented. */ +} + +#if defined(UART0) +#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \ + ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0))) +void UART0_DriverIRQHandler(void) +{ + s_uartIsr(UART0, s_uartHandle[0]); +} + +void UART0_RX_TX_DriverIRQHandler(void) +{ + UART0_DriverIRQHandler(); +} +#endif +#endif + +#if defined(UART1) +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[1]); +} + +void UART1_RX_TX_DriverIRQHandler(void) +{ + UART1_DriverIRQHandler(); +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[2]); +} + +void UART2_RX_TX_DriverIRQHandler(void) +{ + UART2_DriverIRQHandler(); +} + +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[3]); +} + +void UART3_RX_TX_DriverIRQHandler(void) +{ + UART3_DriverIRQHandler(); +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[4]); +} + +void UART4_RX_TX_DriverIRQHandler(void) +{ + UART4_DriverIRQHandler(); +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[5]); +} + +void UART5_RX_TX_DriverIRQHandler(void) +{ + UART5_DriverIRQHandler(); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h new file mode 100755 index 00000000000..3eec4e66b58 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h @@ -0,0 +1,757 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version 2.1.0. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _uart_status +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ +}; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0U, /*!< One stop bit */ + kUART_TwoStopBit = 1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! + * @brief UART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the UART interrupt configurations. + */ +enum _uart_interrupt_enable +{ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */ +#endif + kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */ + kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */ + kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */ + kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */ + kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */ + kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */ + kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */ + kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */ + kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */ + kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ + kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ +#endif +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum _uart_flags +{ + kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */ + kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */ + kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */ + kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */ + kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */ + kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit. + If any of these samples differ, noise flag sets */ + kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected + where stop bit expected */ + kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakFlag = + (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when + LIN break char detected and LIN circuit enabled */ +#endif + kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag, + sets when active edge detected */ + kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), + sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ + kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ + kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ + kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ + kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ + kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ +#endif +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate */ + uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with user configuration structure and peripheral clock. + * + * This function configures the UART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the UART_GetDefaultConfig() function. + * Example below shows how to use this API to configure UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 0; + * uartConfig.rxFifoWatermark = 1; + * UART_Init(UART1, &uartConfig, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + */ +void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->bitCountPerChar = kUART_8BitsPerChar; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 0; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source freqency in HZ. + */ +void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get UART status flags. + * + * This function get all UART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _uart_flags. To check specific status, + * compare the return value with enumerators in @ref _uart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART status flags which are ORed by the enumerators in the _uart_flags. + */ +uint32_t UART_GetStatusFlags(UART_Type *base); + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears UART status flags with a provided mask. Automatically cleared flag + * can't be cleared by this function. + * Some flags can only be cleared or set by hardware itself. These flags are: + * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, + * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, + * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base UART peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags. + * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX full interrupt: + * @code + * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * specific interrupts enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the UART data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base UART peripheral base address. + * @return UART data register address which are used both by transmitter and receiver. + */ +static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base) +{ + return (uint32_t) & (base->D); +} + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_TDMAS_MASK; +#else + base->C5 |= UART_C5_TDMAS_MASK; +#endif + base->C2 |= UART_C2_TIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_TDMAS_MASK; +#else + base->C5 &= ~UART_C5_TDMAS_MASK; +#endif + base->C2 &= ~UART_C2_TIE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA. + * + * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_RDMAS_MASK; +#else + base->C5 |= UART_C5_RDMAS_MASK; +#endif + base->C2 |= UART_C2_RIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_RDMAS_MASK; +#else + base->C5 &= ~UART_C5_RDMAS_MASK; +#endif + base->C2 &= ~UART_C2_RIE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_TE_MASK; + } + else + { + base->C2 &= ~UART_C2_TE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_RE_MASK; + } + else + { + base->C2 &= ~UART_C2_RE_MASK; + } +} + +/*! + * @brief Writes to the TX register. + * + * This function writes data to the TX register directly. The upper layer must ensure + * that the TX register is empty or TX FIFO has empty room before calling this function. + * + * @param base UART peripheral base address. + * @param data The byte to write. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->D = data; +} + +/*! + * @brief Reads the RX register directly. + * + * This function reads data from the TX register directly. The upper layer must + * ensure that the RX register is full or that the TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return The byte read from UART data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return base->D; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note This function does not check whether all the data has been sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_UART_NoiseError Noise error happened while receiving data. + * @retval kStatus_UART_FramingError Framing error happened while receiving data. + * @retval kStatus_UART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, refer to #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief UART Error IRQ handle function. + * + * This function handle the UART error IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c new file mode 100755 index 00000000000..36734044860 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart_edma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ + +/*base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle, + uartPrivateHandle->handle->userData); + } + } +} + +static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle, + uartPrivateHandle->handle->userData); + } + } +} + +void UART_TransferCreateHandleEDMA(UART_Type *base, + uart_edma_handle_t *handle, + uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint32_t instance = UART_GetInstance(base); + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (rxEdmaHandle) + { + base->RWFIFO = 1U; + } +#endif + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, UART_SendEDMACallback, &s_edmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, UART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); + } +} + +status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txState = kUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base), + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + handle->rxState = kUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle); + + /* Disable UART TX EDMA. */ + UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = kUART_TxIdle; +} + +void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle); + + /* Disable UART RX EDMA. */ + UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle->rxEdmaHandle); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle->txEdmaHandle); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h new file mode 100755 index 00000000000..52cc7373a9f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_EDMA_H_ +#define _FSL_UART_EDMA_H_ + +#include "fsl_uart.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup uart_edma_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_edma_handle uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_edma_transfer_callback_t)(UART_Type *base, + uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART eDMA handle +*/ +struct _uart_edma_handle +{ + uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + * @param callback UART callback, NULL means no callback. + * @param userData User callback function data. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + */ +void UART_TransferCreateHandleEDMA(UART_Type *base, + uart_edma_handle_t *handle, + uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Receive data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + * @param xfer UART eDMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts sent data using eDMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + */ +void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data using eDMA. + * + * This function aborts receive data using eDMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + */ +void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by DMA. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_EDMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c new file mode 100755 index 00000000000..0854ca07577 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_vref.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base VREF peripheral base address + * + * @return The VREF instance + */ +static uint32_t VREF_GetInstance(VREF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to VREF bases for each instance. */ +static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; + +/*! @brief Pointers to VREF clocks for each instance. */ +static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t VREF_GetInstance(VREF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++) + { + if (s_vrefBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_VREF_COUNT); + + return instance; +} + +void VREF_Init(VREF_Type *base, const vref_config_t *config) +{ + assert(config != NULL); + + uint8_t reg = 0U; + + /* Ungate clock for VREF */ + CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); + +/* Configure VREF to a known state */ +#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC + /* Set chop oscillator bit */ + base->TRM |= VREF_TRM_CHOPEN_MASK; +#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ + reg = base->SC; + /* Set buffer Mode selection and Regulator enable bit */ + reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U); +#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION + /* Set second order curvature compensation enable bit */ + reg |= VREF_SC_ICOMPEN(1U); +#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ + /* Enable VREF module */ + reg |= VREF_SC_VREFEN(1U); + /* Update bit-field from value to Status and Control register */ + base->SC = reg; +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + reg = base->VREFL_TRM; + /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/ + reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK); + /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */ + reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef); + base->VREFL_TRM = reg; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} + +void VREF_Deinit(VREF_Type *base) +{ + /* Gate clock for VREF */ + CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); +} + +void VREF_GetDefaultConfig(vref_config_t *config) +{ +/* Set High power buffer mode in */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + config->bufferMode = kVREF_ModeHighPowerBuffer; +#else + config->bufferMode = kVREF_ModeTightRegulationBuffer; +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + /* Select internal voltage reference */ + config->enableExternalVoltRef = false; + /* Set VREFL (0.4 V) reference buffer disable */ + config->enableLowRef = false; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +} + +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) +{ + uint8_t reg = 0U; + + /* Set TRIM bits value in voltage reference */ + reg = base->TRM; + reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue)); + base->TRM = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) +{ + /* The values 111b and 110b are NOT valid/allowed */ + assert((trimValue != 0x7U) && (trimValue != 0x6U)); + + uint8_t reg = 0U; + + /* Set TRIM bits value in low voltage reference */ + reg = base->VREFL_TRM; + reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue)); + base->VREFL_TRM = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h new file mode 100755 index 00000000000..79378863bb6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_VREF_H_ +#define _FSL_VREF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup vref + * @{ + */ + +/*! @file */ + +/****************************************************************************** + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/* Those macros below defined to support SoC family which have VREFL (0.4V) reference */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +#define SC VREFH_SC +#define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV +#define VREF_SC_REGEN VREF_VREFH_SC_REGEN +#define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN +#define VREF_SC_ICOMPEN VREF_VREFH_SC_ICOMPEN +#define VREF_SC_REGEN_MASK VREF_VREFH_SC_REGEN_MASK +#define VREF_SC_VREFST_MASK VREF_VREFH_SC_VREFST_MASK +#define VREF_SC_VREFEN_MASK VREF_VREFH_SC_VREFEN_MASK +#define VREF_SC_MODE_LV_MASK VREF_VREFH_SC_MODE_LV_MASK +#define VREF_SC_ICOMPEN_MASK VREF_VREFH_SC_ICOMPEN_MASK +#define TRM VREFH_TRM +#define VREF_TRM_TRIM VREF_VREFH_TRM_TRIM +#define VREF_TRM_CHOPEN_MASK VREF_VREFH_TRM_CHOPEN_MASK +#define VREF_TRM_TRIM_MASK VREF_VREFH_TRM_TRIM_MASK +#define VREF_TRM_CHOPEN_SHIFT VREF_VREFH_TRM_CHOPEN_SHIFT +#define VREF_TRM_TRIM_SHIFT VREF_VREFH_TRM_TRIM_SHIFT +#define VREF_SC_MODE_LV_SHIFT VREF_VREFH_SC_MODE_LV_SHIFT +#define VREF_SC_REGEN_SHIFT VREF_VREFH_SC_REGEN_SHIFT +#define VREF_SC_VREFST_SHIFT VREF_VREFH_SC_VREFST_SHIFT +#define VREF_SC_ICOMPEN_SHIFT VREF_VREFH_SC_ICOMPEN_SHIFT +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*! + * @brief VREF modes. + */ +typedef enum _vref_buffer_mode +{ + kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + kVREF_ModeHighPowerBuffer = 1U, /*!< High power buffer mode enabled */ + kVREF_ModeLowPowerBuffer = 2U /*!< Low power buffer mode enabled */ +#else + kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */ +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ +} vref_buffer_mode_t; + +/*! + * @brief The description structure for the VREF module. + */ +typedef struct _vref_config +{ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + bool enableLowRef; /*!< Set VREFL (0.4 V) reference buffer enable or disable */ + bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +} vref_config_t; + +/****************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name VREF functional operation + * @{ + */ + +/*! + * @brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all the other VREF driver functions, + * read/write registers, and configurations with user-defined settings. + * The example below shows how to set up vref_config_t parameters and + * how to call the VREF_Init function by passing in these parameters: + * Example: + * @code + * vref_config_t vrefConfig; + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig.enableExternalVoltRef = false; + * vrefConfig.enableLowRef = false; + * VREF_Init(VREF, &vrefConfig); + * @endcode + * + * @param base VREF peripheral address. + * @param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config); + +/*! + * @brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * Example: + * @code + * vref_config_t vrefUserConfig; + * VREF_Init(VREF); + * VREF_GetDefaultConfig(&vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * @endcode + * + * @param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base); + +/*! + * @brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to a default value. + * Example: + * @code + * vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig->enableExternalVoltRef = false; + * vrefConfig->enableLowRef = false; + * @endcode + * + * @param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config); + +/*! + * @brief Sets a TRIM value for reference voltage. + * + * This function sets a TRIM value for reference voltage. + * Note that the TRIM value maximum is 0x3F. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the TRM register. + * + * @param base VREF peripheral address. + * @return Six-bit value of trim setting. + */ +static inline uint8_t VREF_GetTrimVal(VREF_Type *base) +{ + return (base->TRM & VREF_TRM_TRIM_MASK); +} +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + +/*! + * @brief Sets the TRIM value for low voltage reference. + * + * This function sets the TRIM value for low reference voltage. + * NOTE: + * - The TRIM value maximum is 0x05U + * - The values 111b and 110b are not valid/allowed. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)). + */ +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the VREFL_TRM register. + * + * @param base VREF peripheral address. + * @return Three-bit value of the trim setting. + */ +static inline uint8_t VREF_GetLowReferenceTrimVal(VREF_Type *base) +{ + return (base->VREFL_TRM & VREF_VREFL_TRM_VREFL_TRIM_MASK); +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_VREF_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c new file mode 100755 index 00000000000..489798ca889 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wdog.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + config->enableWdog = true; + config->clockSource = kWDOG_LpoClockSource; + config->prescaler = kWDOG_ClockPrescalerDivide1; +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + config->workMode.enableWait = true; +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableUpdate = true; + config->enableInterrupt = false; + config->enableWindowMode = false; + config->windowValue = 0U; + config->timeoutValue = 0xFFFFU; +} + +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = WDOG_STCTRLH_WDOGEN(config->enableWdog) | WDOG_STCTRLH_CLKSRC(config->clockSource) | + WDOG_STCTRLH_IRQRSTEN(config->enableInterrupt) | WDOG_STCTRLH_WINEN(config->enableWindowMode) | + WDOG_STCTRLH_ALLOWUPDATE(config->enableUpdate) | WDOG_STCTRLH_DBGEN(config->workMode.enableDebug) | + WDOG_STCTRLH_STOPEN(config->workMode.enableStop) | +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + WDOG_STCTRLH_WAITEN(config->workMode.enableWait) | +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + WDOG_STCTRLH_DISTESTWDOG(1U); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + /* Set configruation */ + base->PRESC = WDOG_PRESC_PRESCVAL(config->prescaler); + base->WINH = (uint16_t)((config->windowValue >> 16U) & 0xFFFFU); + base->WINL = (uint16_t)((config->windowValue) & 0xFFFFU); + base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); + base->STCTRLH = value; + EnableGlobalIRQ(primaskValue); +} + +void WDOG_Deinit(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupts */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + WDOG_Disable(base); + EnableGlobalIRQ(primaskValue); + WDOG_ClearResetCount(base); +} + +void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = WDOG_STCTRLH_DISTESTWDOG(0U) | WDOG_STCTRLH_TESTWDOG(1U) | WDOG_STCTRLH_TESTSEL(config->testMode) | + WDOG_STCTRLH_BYTESEL(config->testedByte) | WDOG_STCTRLH_IRQRSTEN(0U) | WDOG_STCTRLH_WDOGEN(1U) | + WDOG_STCTRLH_ALLOWUPDATE(1U); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + /* Set configruation */ + base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); + base->STCTRLH = value; + EnableGlobalIRQ(primaskValue); +} + +uint32_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint32_t status_flag = 0U; + + status_flag |= (base->STCTRLH & WDOG_STCTRLH_WDOGEN_MASK); + status_flag |= (base->STCTRLL & WDOG_STCTRLL_INTFLG_MASK); + + return status_flag; +} + +void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask) +{ + if (mask & kWDOG_TimeoutFlag) + { + base->STCTRLL |= WDOG_STCTRLL_INTFLG_MASK; + } +} + +void WDOG_Refresh(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->REFRESH = WDOG_FIRST_WORD_OF_REFRESH; + base->REFRESH = WDOG_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h new file mode 100755 index 00000000000..949a9a8e046 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version 2.0.0. */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Unlock sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_UNLOCK (0xC520U) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK (0xD928U) /*!< Second word of unlock sequence */ +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_REFRESH (0xA602U) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH (0xB480U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WDOG clock source. */ +typedef enum _wdog_clock_source +{ + kWDOG_LpoClockSource = 0U, /*!< WDOG clock sourced from LPO*/ + kWDOG_AlternateClockSource = 1U, /*!< WDOG clock sourced from alternate clock source*/ +} wdog_clock_source_t; + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + bool enableWait; /*!< Enables or disables WDOG in wait mode */ +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + bool enableStop; /*!< Enables or disables WDOG in stop mode */ + bool enableDebug; /*!< Enables or disables WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes the selection of the clock prescaler. */ +typedef enum _wdog_clock_prescaler +{ + kWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kWDOG_ClockPrescalerDivide2 = 0x1U, /*!< Divided by 2 */ + kWDOG_ClockPrescalerDivide3 = 0x2U, /*!< Divided by 3 */ + kWDOG_ClockPrescalerDivide4 = 0x3U, /*!< Divided by 4 */ + kWDOG_ClockPrescalerDivide5 = 0x4U, /*!< Divided by 5 */ + kWDOG_ClockPrescalerDivide6 = 0x5U, /*!< Divided by 6 */ + kWDOG_ClockPrescalerDivide7 = 0x6U, /*!< Divided by 7 */ + kWDOG_ClockPrescalerDivide8 = 0x7U, /*!< Divided by 8 */ +} wdog_clock_prescaler_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_clock_source_t clockSource; /*!< Clock source select */ + wdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableUpdate; /*!< Update write-once register enable */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + bool enableWindowMode; /*!< Enables or disables WDOG window mode */ + uint32_t windowValue; /*!< Window value */ + uint32_t timeoutValue; /*!< Timeout value */ +} wdog_config_t; + +/*! @brief Describes WDOG test mode. */ +typedef enum _wdog_test_mode +{ + kWDOG_QuickTest = 0U, /*!< Selects quick test */ + kWDOG_ByteTest = 1U, /*!< Selects byte test */ +} wdog_test_mode_t; + +/*! @brief Describes WDOG tested byte selection in byte test mode. */ +typedef enum _wdog_tested_byte +{ + kWDOG_TestByte0 = 0U, /*!< Byte 0 selected in byte test mode */ + kWDOG_TestByte1 = 1U, /*!< Byte 1 selected in byte test mode */ + kWDOG_TestByte2 = 2U, /*!< Byte 2 selected in byte test mode */ + kWDOG_TestByte3 = 3U, /*!< Byte 3 selected in byte test mode */ +} wdog_tested_byte_t; + +/*! @brief Describes WDOG test mode configuration structure. */ +typedef struct _wdog_test_config +{ + wdog_test_mode_t testMode; /*!< Selects test mode */ + wdog_tested_byte_t testedByte; /*!< Selects tested byte in byte test mode */ + uint32_t timeoutValue; /*!< Timeout value */ +} wdog_test_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable_t +{ + kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout will generate interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags_t +{ + kWDOG_RunningFlag = WDOG_STCTRLH_WDOGEN_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_TimeoutFlag = WDOG_STCTRLL_INTFLG_MASK, /*!< Interrupt flag, set when an exception occurs*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WDOG configure sturcture. + * + * This function initializes the WDOG configure structure to default value. The default + * value are: + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->clockSource = kWDOG_LpoClockSource; + * wdogConfig->prescaler = kWDOG_ClockPrescalerDivide1; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableUpdate = true; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enableWindowMode = false; + * wdogConfig->windowValue = 0; + * wdogConfig->timeoutValue = 0xFFFFU; + * @endcode + * + * @param config Pointer to WDOG config structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * If user wants to reconfigure WDOG without forcing a reset first, enableUpdate must be set to true + * in configuration. + * + * Example: + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Configures WDOG functional test. + * + * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode + * and runs according to the configuration. + * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + * + * Example: + * @code + * wdog_test_config_t test_config; + * test_config.testMode = kWDOG_QuickTest; + * test_config.timeoutValue = 0xfffffu; + * WDOG_SetTestModeConfig(wdog_base, &test_config); + * @endcode + * @param base WDOG peripheral base address + * @param config The functional test configuration of WDOG + */ +void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config); + +/* @} */ + +/*! + * @name WDOG Functional Operation + * @{ + */ + +/*! + * @brief Enables the WDOG module. + * + * This function write value into WDOG_STCTRLH register to enable the WDOG, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->STCTRLH |= WDOG_STCTRLH_WDOGEN_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function write value into WDOG_STCTRLH register to disable the WDOG, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; +} + +/*! + * @brief Enable WDOG interrupt. + * + * This function write value into WDOG_STCTRLH register to enable WDOG interrupt, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined: + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->STCTRLH |= mask; +} + +/*! + * @brief Disable WDOG interrupt. + * + * This function write value into WDOG_STCTRLH register to disable WDOG interrupt, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined: + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->STCTRLH &= ~mask; +} + +/*! + * @brief Gets WDOG all status flags. + * + * This function gets all status flags. + * + * Example for getting Running Flag: + * @code + * uint32_t status; + * status = WDOG_GetStatusFlags(wdog_base) & kWDOG_RunningFlag; + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +uint32_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clear WDOG flag. + * + * This function clears WDOG status flag. + * + * Example for clearing timeout(interrupt) flag: + * @code + * WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values: + * kWDOG_TimeoutFlag + */ +void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask); + +/*! + * @brief Set the WDOG timeout value. + * + * This function sets the timeout value. + * It should be ensured that the time-out value for the WDOG is always greater than + * 2xWCT time + 20 bus clock cycles. + * This function write value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once. + * Make sure the WCT window is still open and these two registers have not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value, count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount) +{ + base->TOVALH = (uint16_t)((timeoutCount >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((timeoutCount)&0xFFFFU); +} + +/*! + * @brief Sets the WDOG window value. + * + * This function sets the WDOG window value. + * This function write value into WDOG_WINH and WDOG_WINL registers which are wirte-once. + * Make sure the WCT window is still open and these two registers have not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param windowValue WDOG window value. + */ +static inline void WDOG_SetWindowValue(WDOG_Type *base, uint32_t windowValue) +{ + base->WINH = (uint16_t)((windowValue >> 16U) & 0xFFFFU); + base->WINL = (uint16_t)((windowValue)&0xFFFFU); +} + +/*! + * @brief Unlocks the WDOG register written. + * + * This function unlocks the WDOG register written. + * Before starting the unlock sequence and following congfiguration, disable the global interrupts. + * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire, + * After the configuration finishes, re-enable the global interrupts. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Unlock(WDOG_Type *base) +{ + base->UNLOCK = WDOG_FIRST_WORD_OF_UNLOCK; + base->UNLOCK = WDOG_SECOND_WORD_OF_UNLOCK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); + +/*! + * @brief Gets the WDOG reset count. + * + * This function gets the WDOG reset count value. + * + * @param base WDOG peripheral base address + * @return WDOG reset count value + */ +static inline uint16_t WDOG_GetResetCount(WDOG_Type *base) +{ + return base->RSTCNT; +} +/*! + * @brief Clears the WDOG reset count. + * + * This function clears the WDOG reset count value. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_ClearResetCount(WDOG_Type *base) +{ + base->RSTCNT |= UINT16_MAX; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h new file mode 100755 index 00000000000..e78b331e346 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PERIPHERAL_CLOCK_H_ +#define _FSL_PERIPHERAL_CLOCK_H_ + +#include "fsl_clock.h" + +/* Array for UART module clocks */ +#define UART_CLOCK_FREQS \ + { \ + UART0_CLK_SRC, UART1_CLK_SRC, UART2_CLK_SRC, UART3_CLK_SRC, UART4_CLK_SRC, UART5_CLK_SRC \ + } + +/* Array for I2C module clocks */ +#define I2C_CLOCK_FREQS \ + { \ + I2C0_CLK_SRC, I2C1_CLK_SRC, I2C2_CLK_SRC \ + } + +/* Array for DSPI module clocks */ +#define SPI_CLOCK_FREQS \ + { \ + DSPI0_CLK_SRC, DSPI1_CLK_SRC, DSPI2_CLK_SRC \ + } + +#endif /* _FSL_PERIPHERAL_CLOCK_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c new file mode 100644 index 00000000000..6214a774acc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c @@ -0,0 +1,276 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_uart.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" + +static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; +static uart_irq_handler irq_handler; +/* Array of UART peripheral base address. */ +static UART_Type *const uart_addrs[] = UART_BASE_PTRS; +/* Array of UART bus clock frequencies */ +static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS; + + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + + uart_config_t config; + + UART_GetDefaultConfig(&config); + config.baudRate_Bps = 9600; + config.enableTx = false; + config.enableRx = false; + + UART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + UART_EnableTx(uart_addrs[obj->index], true); + pin_mode(tx, PullUp); + } + if (rx != NC) { + UART_EnableRx(uart_addrs[obj->index], true); + pin_mode(rx, PullUp); + } + + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + UART_Deinit(uart_addrs[obj->index]); + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) { + UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index])); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + UART_Type *base = uart_addrs[obj->index]; + uint8_t temp; + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + if (parity != ParityNone) + { + /* Enable Parity */ + temp |= (UART_C1_PE_MASK | UART_C1_M_MASK); + if (parity == ParityOdd) { + temp |= UART_C1_PT_MASK; + } else { + // Hardware does not support forced parity + MBED_ASSERT(0); + } + } + base->C1 = temp; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)--stop_bits); +#endif +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) { + UART_Type *base = uart_addrs[index]; + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->D; + } + + if (serial_irq_ids[index] != 0) { + if (transmit_empty) + irq_handler(serial_irq_ids[index], TxIrq); + + if (receive_full) + irq_handler(serial_irq_ids[index], RxIrq); + } +} + +void uart0_irq() { + uint32_t status_flags = UART0->S1; + uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0); +} + +void uart1_irq() { + uint32_t status_flags = UART1->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1); +} + +void uart2_irq() { + uint32_t status_flags = UART2->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2); +} + +void uart3_irq() { + uint32_t status_flags = UART3->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 3); +} + +void uart4_irq() { + uint32_t status_flags = UART4->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4); +} + +void uart5_irq() { + uint32_t status_flags = UART5->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 5); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; + uint32_t vector = 0; + + switch (obj->index) { + case 0: + vector = (uint32_t)&uart0_irq; + break; + case 1: + vector = (uint32_t)&uart1_irq; + break; + case 2: + vector = (uint32_t)&uart2_irq; + break; + case 3: + vector = (uint32_t)&uart3_irq; + break; + case 4: + vector = (uint32_t)&uart4_irq; + break; + case 5: + vector = (uint32_t)&uart5_irq; + break; + default: + break; + } + + if (enable) { + switch (irq) { + case RxIrq: + UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + NVIC_SetVector(uart_irqs[obj->index], vector); + NVIC_EnableIRQ(uart_irqs[obj->index]); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: + UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + switch (other_irq) { + case RxIrq: + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0); + break; + case TxIrq: + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); + break; + default: + break; + } + if (all_disabled) + NVIC_DisableIRQ(uart_irqs[obj->index]); + } +} + +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + uint8_t data; + data = UART_ReadByte(uart_addrs[obj->index]); + + return data; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + UART_WriteByte(uart_addrs[obj->index], (uint8_t)c); +} + +int serial_readable(serial_t *obj) { + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kUART_RxOverrunFlag) + UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); + return (status_flags & kUART_RxDataRegFullFlag); +} + +int serial_writable(serial_t *obj) { + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kUART_RxOverrunFlag) + UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); + return (status_flags & kUART_TxDataRegEmptyFlag); +} + +void serial_clear(serial_t *obj) { +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) { + uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK; +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c new file mode 100644 index 00000000000..dc2190ee6f3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c @@ -0,0 +1,132 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_assert.h" + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "fsl_dspi.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" + +/* Array of SPI peripheral base address. */ +static SPI_Type *const spi_address[] = SPI_BASE_PTRS; +/* Array of SPI bus clock frequencies */ +static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + + obj->instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) { + DSPI_Deinit(spi_address[obj->instance]); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + + dspi_master_config_t master_config; + dspi_slave_config_t slave_config; + + if (slave) { + /* Slave config */ + DSPI_SlaveGetDefaultConfig(&slave_config); + slave_config.whichCtar = kDSPI_Ctar0; + slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; + slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; + slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; + + DSPI_SlaveInit(spi_address[obj->instance], &slave_config); + } else { + /* Master config */ + DSPI_MasterGetDefaultConfig(&master_config); + master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; + master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; + master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; + master_config.ctarConfig.direction = kDSPI_MsbFirst; + master_config.ctarConfig.pcsToSckDelayInNanoSec = 0; + + DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance])); + } +} + +void spi_frequency(spi_t *obj, int hz) { + uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]); + DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock); + //Half clock period delay after SPI transfer + DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz); +} + +static inline int spi_readable(spi_t * obj) { + return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag); +} + +int spi_master_write(spi_t *obj, int value) { + dspi_command_data_config_t command; + uint32_t rx_data; + DSPI_GetDefaultDataCommandConfig(&command); + command.isEndOfQueue = true; + + DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value); + + DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag); + + // wait rx buffer full + while (!spi_readable(obj)); + rx_data = DSPI_ReadData(spi_address[obj->instance]); + DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag); + return rx_data & 0xffff; +} + +int spi_slave_receive(spi_t *obj) { + return spi_readable(obj); +} + +int spi_slave_read(spi_t *obj) { + uint32_t rx_data; + + while (!spi_readable(obj)); + rx_data = DSPI_ReadData(spi_address[obj->instance]); + DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag); + return rx_data & 0xffff; +} + +void spi_slave_write(spi_t *obj, int value) { + DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c new file mode 100644 index 00000000000..9dcfde85ae8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c @@ -0,0 +1,87 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "fsl_pit.h" +#include "fsl_clock_config.h" + +static int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) { + return; + } + us_ticker_inited = 1; + // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init + if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) + BOARD_BootClockRUN(); + //Common for ticker/timer + uint32_t busClock; + // Structure to initialize PIT + pit_config_t pitConfig; + + PIT_GetDefaultConfig(&pitConfig); + PIT_Init(PIT, &pitConfig); + + busClock = CLOCK_GetFreq(kCLOCK_BusClk); + + //Timer + PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); + PIT_StartTimer(PIT, kPIT_Chnl_0); + PIT_StartTimer(PIT, kPIT_Chnl_1); + + //Ticker + PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); + NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(PIT3_IRQn); +} + + +uint32_t us_ticker_read() { + if (!us_ticker_inited) { + us_ticker_init(); + } + + return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1)); +} + +void us_ticker_disable_interrupt(void) { + PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); +} + +void us_ticker_clear_interrupt(void) { + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int delta = (int)(timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past: + us_ticker_irq_handler(); + return; + } + + PIT_StopTimer(PIT, kPIT_Chnl_3); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); + PIT_StartTimer(PIT, kPIT_Chnl_3); + PIT_StartTimer(PIT, kPIT_Chnl_2); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PeripheralPins.h new file mode 100644 index 00000000000..6cff2fed829 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PeripheralPins.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PortNames.h new file mode 100644 index 00000000000..476845b76d7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PortNames.h @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4 +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogin_api.c new file mode 100644 index 00000000000..35ed9631443 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogin_api.c @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralNames.h" +#include "fsl_adc16.h" +#include "PeripheralPins.h" + +/* Array of ADC peripheral base address. */ +static ADC_Type *const adc_addrs[] = ADC_BASE_PTRS; + +#define MAX_FADC 6000000 + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; + uint32_t bus_clock; + adc16_config_t adc16_config; + + bus_clock = CLOCK_GetFreq(kCLOCK_BusClk); + uint32_t clkdiv; + for (clkdiv = 0; clkdiv < 4; clkdiv++) { + if ((bus_clock >> clkdiv) <= MAX_FADC) + break; + } + if (clkdiv == 4) { + clkdiv = 0x3; //Set max div + } + + ADC16_GetDefaultConfig(&adc16_config); + adc16_config.clockSource = kADC16_ClockSourceAlt0; + adc16_config.clockDivider = (adc16_clock_divider_t)clkdiv; + adc16_config.resolution = kADC16_ResolutionSE16Bit; + ADC16_Init(adc_addrs[instance], &adc16_config); + ADC16_EnableHardwareTrigger(adc_addrs[instance], false); + ADC16_SetHardwareAverage(adc_addrs[instance], kADC16_HardwareAverageCount4); + ADC16_SetChannelMuxMode(adc_addrs[instance], + obj->adc & (1 << ADC_B_CHANNEL_SHIFT) ? kADC16_ChannelMuxB : kADC16_ChannelMuxA); + + pinmap_pinout(pin, PinMap_ADC); +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; + adc16_channel_config_t adc16_channel_config; + + adc16_channel_config.channelNumber = obj->adc & 0xF; + adc16_channel_config.enableInterruptOnConversionCompleted = false; + /* + * When in software trigger mode, each conversion would be launched once calling the "ADC16_ChannelConfigure()" + * function, which works like writing a conversion command and executing it. + */ + ADC16_SetChannelConfig(adc_addrs[instance], 0, &adc16_channel_config); + while (0U == (kADC16_ChannelConversionDoneFlag & + ADC16_GetChannelStatusFlags(adc_addrs[instance], 0))) + { + } + return ADC16_GetChannelConversionValue(adc_addrs[instance], 0); +} + +float analogin_read(analogin_t *obj) { + uint16_t value = analogin_read_u16(obj); + return (float)value * (1.0f / (float)0xFFFF); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogout_api.c new file mode 100644 index 00000000000..0d47241d2d4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogout_api.c @@ -0,0 +1,78 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "fsl_dac.h" +#include "PeripheralPins.h" + +/* Array of DAC peripheral base address. */ +static DAC_Type *const dac_bases[] = DAC_BASE_PTRS; + +#define RANGE_12BIT 0xFFF + +void analogout_init(dac_t *obj, PinName pin) { + dac_config_t dac_config; + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + if (obj->dac == (DACName)NC) { + error("DAC pin mapping failed"); + } + + DAC_GetDefaultConfig(&dac_config); + DAC_Init(dac_bases[obj->dac], &dac_config); + + DAC_SetBufferValue(dac_bases[obj->dac], 0, 0); +} + +void analogout_free(dac_t *obj) {} + +static inline void dac_write(dac_t *obj, int value) { + DAC_SetBufferValue(dac_bases[obj->dac], 0, (uint16_t)value); +} + +static inline int dac_read(dac_t *obj) { + return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL); +} + +void analogout_write(dac_t *obj, float value) { + if (value < 0.0f) { + dac_write(obj, 0); + } else if (value > 1.0f) { + dac_write(obj, RANGE_12BIT); + } else { + dac_write(obj, value * (float)RANGE_12BIT); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> 4); // 12-bit +} + +float analogout_read(dac_t *obj) { + uint32_t value = dac_read(obj); + return (float)value * (1.0f / (float)RANGE_12BIT); +} + +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); // 12-bit + return (value << 4) | ((value >> 8) & 0x003F); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_api.c new file mode 100644 index 00000000000..19d0970ec85 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_api.c @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "fsl_port.h" + +uint32_t gpio_set(PinName pin) { + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_num = pin & 0xFF; + + pin_function(pin, (int)kPORT_MuxAsGpio); + return 1 << pin_num; +} + +void gpio_init(gpio_t *obj, PinName pin) { + obj->pin = pin; + if (pin == (PinName)NC) + return; + + pin_function(pin, (int)kPORT_MuxAsGpio); +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + GPIO_Type *gpio_addrs[] = GPIO_BASE_PTRS; + uint32_t pin_num = obj->pin & 0xFF; + GPIO_Type *base = gpio_addrs[port]; + + switch (direction) { + case PIN_INPUT: + base->PDDR &= ~(1U << pin_num); + break; + case PIN_OUTPUT: + base->PDDR |= (1U << pin_num); + break; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_irq_api.c new file mode 100644 index 00000000000..a18a89459a8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_irq_api.c @@ -0,0 +1,187 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" + +#include "gpio_irq_api.h" + +#if DEVICE_INTERRUPTIN + +#include "gpio_api.h" +#include "fsl_gpio.h" +#include "fsl_port.h" +#include "mbed_error.h" + +#define CHANNEL_NUM 160 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; +/* Array of PORT peripheral base address. */ +static PORT_Type *const port_addrs[] = PORT_BASE_PTRS; +/* Array of PORT IRQ number. */ +static const IRQn_Type port_irqs[] = PORT_IRQS; + + +#define IRQ_DISABLED (0) +#define IRQ_RAISING_EDGE (9) +#define IRQ_FALLING_EDGE (10) +#define IRQ_EITHER_EDGE (11) + +static void handle_interrupt_in(PortName port, int ch_base) { + uint32_t i; + uint32_t interrupt_flags; + PORT_Type *port_base = port_addrs[port]; + + interrupt_flags = PORT_GetPinsInterruptFlags(port_base); + + for (i = 0; i < 32; i++) { + if (interrupt_flags & (1 << i)) { + uint32_t id = channel_ids[ch_base + i]; + if (id == 0) { + continue; + } + + gpio_irq_event event = IRQ_NONE; + GPIO_Type *gpio_addrs[] = GPIO_BASE_PTRS; + GPIO_Type *gpio_base = gpio_addrs[port]; + + switch ((port_base->PCR[i] & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT) { + case IRQ_RAISING_EDGE: + event = IRQ_RISE; + break; + + case IRQ_FALLING_EDGE: + event = IRQ_FALL; + break; + + case IRQ_EITHER_EDGE: + event = (GPIO_ReadPinInput(gpio_base, i)) ? (IRQ_RISE) : (IRQ_FALL); + break; + } + if (event != IRQ_NONE) { + irq_handler(id, event); + } + } + } + PORT_ClearPinsInterruptFlags(port_base, interrupt_flags); +} + +void gpio_irqA(void) {handle_interrupt_in(PortA, 0);} +void gpio_irqB(void) {handle_interrupt_in(PortB, 32);} +void gpio_irqC(void) {handle_interrupt_in(PortC, 64);} +void gpio_irqD(void) {handle_interrupt_in(PortD, 96);} +void gpio_irqE(void) {handle_interrupt_in(PortE, 128);} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) { + return -1; + } + + irq_handler = handler; + obj->port = pin >> GPIO_PORT_SHIFT; + obj->pin = pin & 0x7F; + + uint32_t ch_base = 0; + uint32_t vector = (uint32_t)gpio_irqA; + + switch (obj->port) { + case PortA: + ch_base = 0; + vector = (uint32_t)gpio_irqA; + break; + case PortB: + ch_base = 32; + vector = (uint32_t)gpio_irqB; + break; + case PortC: + ch_base = 64; + vector = (uint32_t)gpio_irqC; + break; + case PortD: + ch_base = 96; + vector = (uint32_t)gpio_irqD; + break; + case PortE: + ch_base = 128; + vector = (uint32_t)gpio_irqE; + break; + default: + error("gpio_irq only supported on port A-E."); + break; + } + NVIC_SetVector(port_irqs[obj->port], vector); + NVIC_EnableIRQ(port_irqs[obj->port]); + + obj->ch = ch_base + obj->pin; + channel_ids[obj->ch] = id; + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + PORT_Type *base = port_addrs[obj->port]; + port_interrupt_t irq_settings = kPORT_InterruptOrDMADisabled; + + switch ((base->PCR[obj->pin] & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT) { + case IRQ_DISABLED: + if (enable) + irq_settings = (event == IRQ_RISE) ? (kPORT_InterruptRisingEdge) : (kPORT_InterruptFallingEdge); + break; + + case IRQ_RAISING_EDGE: + if (enable) { + irq_settings = (event == IRQ_RISE) ? (kPORT_InterruptRisingEdge) : (kPORT_InterruptEitherEdge); + } else { + if (event == IRQ_FALL) + irq_settings = kPORT_InterruptRisingEdge; + } + break; + + case IRQ_FALLING_EDGE: + if (enable) { + irq_settings = (event == IRQ_FALL) ? (kPORT_InterruptFallingEdge) : (kPORT_InterruptEitherEdge); + } else { + if (event == IRQ_RISE) + irq_settings = kPORT_InterruptFallingEdge; + } + break; + + case IRQ_EITHER_EDGE: + if (enable) { + irq_settings = kPORT_InterruptEitherEdge; + } else { + irq_settings = (event == IRQ_RISE) ? (kPORT_InterruptFallingEdge) : (kPORT_InterruptRisingEdge); + } + break; + } + + PORT_SetPinInterruptConfig(base, obj->pin, irq_settings); + base->PCR[obj->pin] |= PORT_PCR_ISF_MASK; +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ(port_irqs[obj->port]); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ(port_irqs[obj->port]); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_object.h new file mode 100644 index 00000000000..2ce1c9591d9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_object.h @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "fsl_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin = obj->pin & 0xFF; + GPIO_Type *gpio_addrs[] = GPIO_BASE_PTRS; + + GPIO_WritePinOutput(gpio_addrs[port], pin, value); +} + +static inline int gpio_read(gpio_t *obj) { + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin = obj->pin & 0xFF; + GPIO_Type *gpio_addrs[] = GPIO_BASE_PTRS; + + return (int)GPIO_ReadPinInput(gpio_addrs[port], pin); +} + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/i2c_api.c new file mode 100644 index 00000000000..0a48a1b11a7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/i2c_api.c @@ -0,0 +1,225 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_i2c.h" +#include "fsl_port.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" + +static int i2c_address = 0; +/* Array of I2C peripheral base address. */ +static I2C_Type *const i2c_addrs[] = I2C_BASE_PTRS; +/* Array of I2C bus clock frequencies */ +static clock_name_t const i2c_clocks[] = I2C_CLOCK_FREQS; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->instance = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->instance != NC); + + i2c_master_config_t master_config; + + I2C_MasterGetDefaultConfig(&master_config); + I2C_MasterInit(i2c_addrs[obj->instance], &master_config, CLOCK_GetFreq(i2c_clocks[obj->instance])); + I2C_EnableInterrupts(i2c_addrs[obj->instance], kI2C_GlobalInterruptEnable); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + PORT_Type *port_addrs[] = PORT_BASE_PTRS; + PORT_Type *base = port_addrs[sda >> GPIO_PORT_SHIFT]; + + base->PCR[sda & 0xFF] |= PORT_PCR_ODE_MASK; + base->PCR[scl & 0xFF] |= PORT_PCR_ODE_MASK; +#endif +} + +int i2c_start(i2c_t *obj) { + I2C_Type *base = i2c_addrs[obj->instance]; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) { + return 1; + } + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + return 0; +} + +int i2c_stop(i2c_t *obj) { + if (I2C_MasterStop(i2c_addrs[obj->instance]) != kStatus_Success) { + return 1; + } + + return 0; +} + +void i2c_frequency(i2c_t *obj, int hz) { + uint32_t busClock; + + busClock = CLOCK_GetFreq(i2c_clocks[obj->instance]); + I2C_MasterSetBaudRate(i2c_addrs[obj->instance], hz, busClock); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + I2C_Type *base = i2c_addrs[obj->instance]; + i2c_master_transfer_t master_xfer; + + i2c_address = address; + memset(&master_xfer, 0, sizeof(master_xfer)); + master_xfer.slaveAddress = address; + master_xfer.direction = kI2C_Read; + master_xfer.data = (uint8_t *)data; + master_xfer.dataSize = length; + + /* The below function will issue a STOP signal at the end of the transfer. + * This is required by the hardware in order to receive the last byte + */ + if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) { + return I2C_ERROR_NO_SLAVE; + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + I2C_Type *base = i2c_addrs[obj->instance]; + i2c_master_transfer_t master_xfer; + + memset(&master_xfer, 0, sizeof(master_xfer)); + master_xfer.slaveAddress = address; + master_xfer.direction = kI2C_Write; + master_xfer.data = (uint8_t *)data; + master_xfer.dataSize = length; + if (!stop) + master_xfer.flags = kI2C_TransferNoStopFlag; + + if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) { + return I2C_ERROR_NO_SLAVE; + } + + return length; +} + +void i2c_reset(i2c_t *obj) { + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) { + uint8_t data; + I2C_Type *base = i2c_addrs[obj->instance]; + i2c_master_transfer_t master_xfer; + + memset(&master_xfer, 0, sizeof(master_xfer)); + master_xfer.slaveAddress = i2c_address; + master_xfer.direction = kI2C_Read; + master_xfer.data = &data; + master_xfer.dataSize = 1; + + /* The below function will issue a STOP signal at the end of the transfer. + * This is required by the hardware in order to receive the last byte + */ + if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) { + return I2C_ERROR_NO_SLAVE; + } + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) { + if (I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1) == kStatus_Success) { + return 1; + } + + return 0; +} + + +#if DEVICE_I2CSLAVE +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + i2c_slave_config_t slave_config; + I2C_SlaveGetDefaultConfig(&slave_config); + slave_config.slaveAddress = 0; + slave_config.enableSlave = (bool)enable_slave; + I2C_SlaveInit(i2c_addrs[obj->instance], &slave_config); +} + +int i2c_slave_receive(i2c_t *obj) { + uint32_t status_flags = I2C_SlaveGetStatusFlags(i2c_addrs[obj->instance]); + + if (status_flags & kI2C_AddressMatchFlag) { + if (status_flags & kI2C_TransferDirectionFlag) { + // read addressed + return 1; + } else { + // write addressed + return 3; + } + } else { + // slave not addressed + return 0; + } +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + I2C_Type *base = i2c_addrs[obj->instance]; + + if (base->S & kI2C_AddressMatchFlag) { + /* Slave receive, master writing to slave. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + /* Read dummy to release the bus. */ + base->D; + } + + I2C_SlaveReadBlocking(base, (uint8_t *)data, length); + + return length; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + I2C_Type *base = i2c_addrs[obj->instance]; + + I2C_SlaveWriteBlocking(base, (uint8_t *)data, length); + + /* Switch to receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + /* Read dummy to release bus. */ + base->D; + + return length; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + i2c_addrs[obj->instance]->A1 = ((uint32_t)(address)) << 1U; +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/objects.h new file mode 100644 index 00000000000..68203df3021 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/objects.h @@ -0,0 +1,69 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + uint32_t port; + uint32_t pin; + uint32_t ch; +}; + +struct port_s { + PortName port; + uint32_t mask; +}; + +struct pwmout_s { + PWMName pwm_name; +}; + +struct serial_s { + int index; +}; + +struct analogin_s { + ADCName adc; +}; + +struct i2c_s { + uint32_t instance; +}; + +struct spi_s { + uint32_t instance; +}; + +struct dac_s { + DACName dac; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pinmap.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pinmap.c new file mode 100644 index 00000000000..f496350b979 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pinmap.c @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "fsl_port.h" + +/* Array of PORT peripheral base address. */ +static PORT_Type *const port_addrs[] = PORT_BASE_PTRS; + +void pin_function(PinName pin, int function) { + MBED_ASSERT(pin != (PinName)NC); + clock_ip_name_t port_clocks[] = PORT_CLOCKS; + + CLOCK_EnableClock(port_clocks[pin >> GPIO_PORT_SHIFT]); + + PORT_SetPinMux(port_addrs[pin >> GPIO_PORT_SHIFT], pin & 0xFF, (port_mux_t)function); +} + +void pin_mode(PinName pin, PinMode mode) { + MBED_ASSERT(pin != (PinName)NC); + uint32_t instance = pin >> GPIO_PORT_SHIFT; + uint32_t pinName = pin & 0xFF; + PORT_Type *base = port_addrs[instance]; + uint32_t reg = base->PCR[pinName]; + + switch (mode) { + case PullNone: + /* Write 0 to the PE, PS and ISF bits */ + reg &= ~(PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK); + break; + case PullDown: + /* Write 0 to PS and ISF bits and 1 to the PE bit to enable the pull configuration */ + reg &= ~(PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK); + reg |= PORT_PCR_PE_MASK; + break; + case PullUp: + /* Write 0 ISF bit, 1 to the PE & PS bits to enable the pull up configuration */ + reg &= ~(PORT_PCR_ISF_MASK); + reg |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK); + break; + default: + break; + } + + base->PCR[pinName] = reg; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/port_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/port_api.c new file mode 100644 index 00000000000..a38c0a73cff --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/port_api.c @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +#include "pinmap.h" +#include "gpio_api.h" + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const port_addrs[] = GPIO_BASE_PTRS; + +PinName port_pin(PortName port, int pin_n) { + return (PinName)((port << GPIO_PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + // The function is set per pin: reuse gpio logic + for (uint32_t i = 0; i < 32; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(obj->port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + + // The mode is set per pin: reuse pinmap logic + for (uint32_t i = 0; i < 32; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + GPIO_Type *base = port_addrs[obj->port]; + uint32_t direction = base->PDDR; + + switch (dir) { + case PIN_INPUT : + direction &= ~obj->mask; + break; + case PIN_OUTPUT: + direction |= obj->mask; + break; + } + base->PDDR = direction; +} + +void port_write(port_t *obj, int value) { + GPIO_Type *base = port_addrs[obj->port]; + uint32_t input = base->PDIR & ~obj->mask; + + base->PDOR = (input | (uint32_t)(value & obj->mask)); +} + +int port_read(port_t *obj) { + GPIO_Type *base = port_addrs[obj->port]; + + return (int)(base->PDIR & obj->mask); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pwmout_api.c new file mode 100644 index 00000000000..216d583191a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pwmout_api.c @@ -0,0 +1,143 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_ftm.h" +#include "PeripheralPins.h" + +static float pwm_clock_mhz; +/* Array of FTM peripheral base address. */ +static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS; + +void pwmout_init(pwmout_t* obj, PinName pin) { + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->pwm_name = pwm; + + uint32_t pwm_base_clock; + pwm_base_clock = CLOCK_GetFreq(kCLOCK_BusClk); + float clkval = (float)pwm_base_clock / 1000000.0f; + uint32_t clkdiv = 0; + while (clkval > 1) { + clkdiv++; + clkval /= 2.0f; + if (clkdiv == 7) { + break; + } + } + + pwm_clock_mhz = clkval; + uint32_t channel = pwm & 0xF; + uint32_t instance = pwm >> TPM_SHIFT; + ftm_config_t ftmInfo; + + FTM_GetDefaultConfig(&ftmInfo); + ftmInfo.prescale = (ftm_clock_prescale_t)clkdiv; + /* Initialize FTM module */ + FTM_Init(ftm_addrs[instance], &ftmInfo); + + ftm_addrs[instance]->CONF |= FTM_CONF_NUMTOF(3); + + ftm_chnl_pwm_signal_param_t config = { + .chnlNumber = (ftm_chnl_t)channel, + .level = kFTM_HighTrue, + .dutyCyclePercent = 0, + .firstEdgeDelayPercent = 0 + }; + // default to 20ms: standard for servos, and fine for e.g. brightness control + FTM_SetupPwm(ftm_addrs[instance], &config, 1, kFTM_EdgeAlignedPwm, 50, pwm_base_clock); + + FTM_StartTimer(ftm_addrs[instance], kFTM_SystemClock); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) { + FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]); +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } + + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; + uint32_t new_count = (uint32_t)((float)(mod) * value); + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = new_count; + base->CNT = 0; + /* Software trigger to update registers */ + FTM_SetSoftwareTrigger(base, true); +} + +float pwmout_read(pwmout_t* obj) { + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK; + uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; + + if (mod == 0) + return 0.0; + float v = (float)(count) / (float)(mod); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + float dc = pwmout_read(obj); + + // Stop FTM clock to ensure instant update of MOD register + base->MOD = FTM_MOD_MOD((pwm_clock_mhz * (float)us) - 1); + pwmout_write(obj, dc); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us); + + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = value; + /* Software trigger to update registers */ + FTM_SetSoftwareTrigger(base, true); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/rtc_api.c new file mode 100644 index 00000000000..6b3f22ad98c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/rtc_api.c @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "pinmap.h" +#include "fsl_rtc.h" +#include "PeripheralPins.h" + +extern void rtc_setup_oscillator(RTC_Type *base); + +void rtc_init(void) { + rtc_config_t rtcConfig; + + RTC_GetDefaultConfig(&rtcConfig); + RTC_Init(RTC, &rtcConfig); + + /* Setup the RTC 32KHz oscillator */ + rtc_setup_oscillator(RTC); + RTC_StartTimer(RTC); +} + +void rtc_free(void) { + RTC_Deinit(RTC); +} + +/* + * Little check routine to see if the RTC has been enabled + * 0 = Disabled, 1 = Enabled + */ +int rtc_isenabled(void) { + CLOCK_EnableClock(kCLOCK_Rtc0); + return (int)((RTC->SR & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT); +} + +time_t rtc_read(void) { + return (time_t)RTC->TSR; +} + +void rtc_write(time_t t) { + if (t == 0) { + t = 1; + } + RTC_StopTimer(RTC); + RTC->TSR = t; + RTC_StartTimer(RTC); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c new file mode 100644 index 00000000000..a0ffa56e0b4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "cmsis.h" +#include "fsl_smc.h" + +void sleep(void) { + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + + SMC_SetPowerModeWait(SMC); +} + +void deepsleep(void) { +#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT) + mcg_mode_t mode = CLOCK_GetMode(); +#endif + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + + SMC_SetPowerModeVlps(SMC); + +#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT) + /* + * If enter stop modes when MCG in PEE mode, then after wakeup, the MCG is in PBE mode, + * need to enter PEE mode manually. + */ + if (mode == kMCG_ModePEE) { + /* Wait for PLL lock. */ + while (!(MCG_S_LOCK0_MASK & MCG->S)) + { + } + CLOCK_SetPeeMode(); + } +#endif +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index ecda1155d7c..0057ddd1674 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -566,6 +566,35 @@ def __init__(self): "template": [os.path.join(os.path.dirname(__file__), 'export', 'uvision_microlib.uvproj.tmpl')], } } + +class K64F(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'FRDM'] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0240"] + self.progen = { + "target":"frdm-k64f", + } + +class MTS_GAMBIT(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'K64F'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.progen = { + "target":"mts-gambit", + } + ### Freescale ### class KL05Z(Target): @@ -2114,6 +2143,8 @@ def __init__(self): LPC4330_M0(), LPC4337(), LPC11U37H_401(), + K64F(), + MTS_GAMBIT(), # FRDM K64F ### Freescale ### KL05Z(), From 6ff2badf1f6e45006e1f49ab1d68c8f4d5bb78ee Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh-R9AADQ Date: Fri, 11 Mar 2016 19:11:39 -0600 Subject: [PATCH 05/11] Added support for Kinetis K22 Use Kinetis SDK 2.0 Moved to TARGET_NXP Signed-off-by: Mahadevan Mahesh --- .../cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h | 8778 +++++++++++++++++ .../TARGET_K22F/MK22F51212_features.h | 1899 ++++ .../TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct | 116 + .../TOOLCHAIN_ARM_STD/startup_MK22F51212.S | 906 ++ .../TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld | 268 + .../TOOLCHAIN_GCC_ARM/startup_MK22F51212.S | 827 ++ .../TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf | 119 + .../TOOLCHAIN_IAR/startup_MK22F12.S | 766 ++ .../cmsis/TARGET_NXP/TARGET_K22F/cmsis.h | 13 + .../cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c | 42 + .../cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h | 48 + .../TARGET_K22F/fsl_device_registers.h | 57 + .../TARGET_K22F/system_MK22F51212.c | 243 + .../TARGET_K22F/system_MK22F51212.h | 164 + .../TARGET_K22F/TARGET_FRDM/PeripheralNames.h | 133 + .../TARGET_K22F/TARGET_FRDM/PeripheralPins.c | 185 + .../TARGET_K22F/TARGET_FRDM/PinNames.h | 259 + .../TARGET_K22F/TARGET_FRDM/device.h | 58 + .../TARGET_FRDM/fsl_clock_config.c | 258 + .../TARGET_FRDM/fsl_clock_config.h | 54 + .../TARGET_K22F/TARGET_FRDM/mbed_overrides.c | 42 + .../TARGET_K22F/drivers/fsl_adc16.c | 363 + .../TARGET_K22F/drivers/fsl_adc16.h | 527 + .../TARGET_K22F/drivers/fsl_clock.c | 1782 ++++ .../TARGET_K22F/drivers/fsl_clock.h | 1453 +++ .../TARGET_K22F/drivers/fsl_cmp.c | 279 + .../TARGET_K22F/drivers/fsl_cmp.h | 346 + .../TARGET_K22F/drivers/fsl_common.c | 97 + .../TARGET_K22F/drivers/fsl_common.h | 255 + .../TARGET_K22F/drivers/fsl_crc.c | 270 + .../TARGET_K22F/drivers/fsl_crc.h | 195 + .../TARGET_K22F/drivers/fsl_dac.c | 213 + .../TARGET_K22F/drivers/fsl_dac.h | 379 + .../TARGET_K22F/drivers/fsl_dmamux.c | 87 + .../TARGET_K22F/drivers/fsl_dmamux.h | 176 + .../TARGET_K22F/drivers/fsl_dspi.c | 1659 ++++ .../TARGET_K22F/drivers/fsl_dspi.h | 1185 +++ .../TARGET_K22F/drivers/fsl_dspi_edma.c | 1262 +++ .../TARGET_K22F/drivers/fsl_dspi_edma.h | 283 + .../TARGET_K22F/drivers/fsl_edma.c | 1313 +++ .../TARGET_K22F/drivers/fsl_edma.h | 879 ++ .../TARGET_K22F/drivers/fsl_ewm.c | 92 + .../TARGET_K22F/drivers/fsl_ewm.h | 242 + .../TARGET_K22F/drivers/fsl_flash.c | 2610 +++++ .../TARGET_K22F/drivers/fsl_flash.h | 1177 +++ .../TARGET_K22F/drivers/fsl_flexbus.c | 196 + .../TARGET_K22F/drivers/fsl_flexbus.h | 266 + .../TARGET_K22F/drivers/fsl_ftm.c | 876 ++ .../TARGET_K22F/drivers/fsl_ftm.h | 862 ++ .../TARGET_K22F/drivers/fsl_gpio.c | 179 + .../TARGET_K22F/drivers/fsl_gpio.h | 390 + .../TARGET_K22F/drivers/fsl_i2c.c | 1536 +++ .../TARGET_K22F/drivers/fsl_i2c.h | 781 ++ .../TARGET_K22F/drivers/fsl_i2c_edma.c | 526 + .../TARGET_K22F/drivers/fsl_i2c_edma.h | 133 + .../TARGET_K22F/drivers/fsl_llwu.c | 404 + .../TARGET_K22F/drivers/fsl_llwu.h | 321 + .../TARGET_K22F/drivers/fsl_lptmr.c | 117 + .../TARGET_K22F/drivers/fsl_lptmr.h | 351 + .../TARGET_K22F/drivers/fsl_lpuart.c | 1103 +++ .../TARGET_K22F/drivers/fsl_lpuart.h | 753 ++ .../TARGET_K22F/drivers/fsl_lpuart_edma.c | 334 + .../TARGET_K22F/drivers/fsl_lpuart_edma.h | 190 + .../TARGET_K22F/drivers/fsl_pdb.c | 135 + .../TARGET_K22F/drivers/fsl_pdb.h | 576 ++ .../TARGET_K22F/drivers/fsl_pit.c | 119 + .../TARGET_K22F/drivers/fsl_pit.h | 355 + .../TARGET_K22F/drivers/fsl_pmc.c | 93 + .../TARGET_K22F/drivers/fsl_pmc.h | 423 + .../TARGET_K22F/drivers/fsl_port.h | 382 + .../TARGET_K22F/drivers/fsl_rcm.c | 63 + .../TARGET_K22F/drivers/fsl_rcm.h | 432 + .../TARGET_K22F/drivers/fsl_rnga.c | 281 + .../TARGET_K22F/drivers/fsl_rnga.h | 138 + .../TARGET_K22F/drivers/fsl_rtc.c | 370 + .../TARGET_K22F/drivers/fsl_rtc.h | 405 + .../TARGET_K22F/drivers/fsl_sai.c | 1048 ++ .../TARGET_K22F/drivers/fsl_sai.h | 850 ++ .../TARGET_K22F/drivers/fsl_sai_edma.c | 379 + .../TARGET_K22F/drivers/fsl_sai_edma.h | 232 + .../TARGET_K22F/drivers/fsl_sim.c | 53 + .../TARGET_K22F/drivers/fsl_sim.h | 128 + .../TARGET_K22F/drivers/fsl_smc.c | 360 + .../TARGET_K22F/drivers/fsl_smc.h | 419 + .../TARGET_K22F/drivers/fsl_uart.c | 1032 ++ .../TARGET_K22F/drivers/fsl_uart.h | 757 ++ .../TARGET_K22F/drivers/fsl_uart_edma.c | 362 + .../TARGET_K22F/drivers/fsl_uart_edma.h | 190 + .../TARGET_K22F/drivers/fsl_vref.c | 172 + .../TARGET_K22F/drivers/fsl_vref.h | 228 + .../TARGET_K22F/drivers/fsl_wdog.c | 153 + .../TARGET_K22F/drivers/fsl_wdog.h | 434 + .../TARGET_K22F/peripheral_clock_defines.h | 54 + .../TARGET_K22F/serial_api.c | 257 + .../TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c | 132 + .../TARGET_K22F/us_ticker.c | 87 + workspace_tools/targets.py | 15 + 98 files changed, 52822 insertions(+) create mode 100755 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h create mode 100755 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212_features.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/fsl_device_registers.h create mode 100755 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.c create mode 100755 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h new file mode 100755 index 00000000000..d86fc03a07c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h @@ -0,0 +1,8778 @@ +/* +** ################################################################### +** Processors: MK22FN512CAP12 +** MK22FN512VDC12 +** MK22FN512VLH12 +** MK22FN512VLL12 +** MK22FN512VMP12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151218 +** +** Abstract: +** CMSIS Peripheral Access Layer for MK22F51212 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-07-23) +** Initial version. +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) +** Update according to reference manual rev. 1.0, +** Update of system and startup files. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** +** ################################################################### +*/ + +/*! + * @file MK22F51212.h + * @version 2.8 + * @date 2015-02-19 + * @brief CMSIS Peripheral Access Layer for MK22F51212 + * + * CMSIS Peripheral Access Layer for MK22F51212 + */ + +#ifndef _MK22F51212_H_ +#define _MK22F51212_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0008U + +/** + * @brief Macro to calculate address of an aliased word in the peripheral + * bitband area for a peripheral register and bit (bit band region 0x40000000 to + * 0x400FFFFF). + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Address of the aliased word in the peripheral bitband area. + */ +#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 32bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 16bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 8bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ + DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ + DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ + DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ + DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ + DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ + DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ + DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ + DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ + DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ + DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ + DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ + DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ + DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ + DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ + DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ + DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ + MCM_IRQn = 17, /**< Normal Interrupt */ + FTF_IRQn = 18, /**< FTFA Command complete interrupt */ + Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ + LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ + LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ + WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ + RNG_IRQn = 23, /**< RNG Interrupt */ + I2C0_IRQn = 24, /**< I2C0 interrupt */ + I2C1_IRQn = 25, /**< I2C1 interrupt */ + SPI0_IRQn = 26, /**< SPI0 Interrupt */ + SPI1_IRQn = 27, /**< SPI1 Interrupt */ + I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ + LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */ + UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ + UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ + UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ + UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ + UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ + UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ + Reserved53_IRQn = 37, /**< Reserved interrupt 53 */ + Reserved54_IRQn = 38, /**< Reserved interrupt 54 */ + ADC0_IRQn = 39, /**< ADC0 interrupt */ + CMP0_IRQn = 40, /**< CMP0 interrupt */ + CMP1_IRQn = 41, /**< CMP1 interrupt */ + FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ + FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt 61 */ + RTC_IRQn = 46, /**< RTC interrupt */ + RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ + PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 52, /**< PDB0 Interrupt */ + USB0_IRQn = 53, /**< USB0 interrupt */ + Reserved70_IRQn = 54, /**< Reserved interrupt 70 */ + Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ + DAC0_IRQn = 56, /**< DAC0 interrupt */ + MCG_IRQn = 57, /**< MCG Interrupt */ + LPTMR0_IRQn = 58, /**< LPTimer interrupt */ + PORTA_IRQn = 59, /**< Port A interrupt */ + PORTB_IRQn = 60, /**< Port B interrupt */ + PORTC_IRQn = 61, /**< Port C interrupt */ + PORTD_IRQn = 62, /**< Port D interrupt */ + PORTE_IRQn = 63, /**< Port E interrupt */ + SWI_IRQn = 64, /**< Software interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt 81 */ + Reserved82_IRQn = 66, /**< Reserved interrupt 82 */ + Reserved83_IRQn = 67, /**< Reserved interrupt 83 */ + Reserved84_IRQn = 68, /**< Reserved interrupt 84 */ + Reserved85_IRQn = 69, /**< Reserved interrupt 85 */ + Reserved86_IRQn = 70, /**< Reserved interrupt 86 */ + FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ + DAC1_IRQn = 72, /**< DAC1 interrupt */ + ADC1_IRQn = 73, /**< ADC1 interrupt */ + Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */ + Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */ + Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */ + Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */ + Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */ + Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */ + Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */ + Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */ + Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */ + Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */ + Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */ + Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK22F51212.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ + kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ + kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ + kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */ + kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */ + kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ + kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ + kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ + kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ + kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ + kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ + kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ + kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ + kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ + kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ + kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ + kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ + kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ + kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ + kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ + kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ + kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ + kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ + kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ + kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ + kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ + kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ + kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ + kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ + kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ + kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name SC1 - ADC Status and Control Registers 1 */ +#define ADC_SC1_ADCH_MASK (0x1FU) +#define ADC_SC1_ADCH_SHIFT (0U) +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK (0x20U) +#define ADC_SC1_DIFF_SHIFT (5U) +#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) +#define ADC_SC1_AIEN_MASK (0x40U) +#define ADC_SC1_AIEN_SHIFT (6U) +#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) +#define ADC_SC1_COCO_MASK (0x80U) +#define ADC_SC1_COCO_SHIFT (7U) +#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) + +/* The count of ADC_SC1 */ +#define ADC_SC1_COUNT (2U) + +/*! @name CFG1 - ADC Configuration Register 1 */ +#define ADC_CFG1_ADICLK_MASK (0x3U) +#define ADC_CFG1_ADICLK_SHIFT (0U) +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK (0xCU) +#define ADC_CFG1_MODE_SHIFT (2U) +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK (0x10U) +#define ADC_CFG1_ADLSMP_SHIFT (4U) +#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) +#define ADC_CFG1_ADIV_MASK (0x60U) +#define ADC_CFG1_ADIV_SHIFT (5U) +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK (0x80U) +#define ADC_CFG1_ADLPC_SHIFT (7U) +#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) + +/*! @name CFG2 - ADC Configuration Register 2 */ +#define ADC_CFG2_ADLSTS_MASK (0x3U) +#define ADC_CFG2_ADLSTS_SHIFT (0U) +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK (0x4U) +#define ADC_CFG2_ADHSC_SHIFT (2U) +#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) +#define ADC_CFG2_ADACKEN_MASK (0x8U) +#define ADC_CFG2_ADACKEN_SHIFT (3U) +#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) +#define ADC_CFG2_MUXSEL_MASK (0x10U) +#define ADC_CFG2_MUXSEL_SHIFT (4U) +#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) + +/*! @name R - ADC Data Result Register */ +#define ADC_R_D_MASK (0xFFFFU) +#define ADC_R_D_SHIFT (0U) +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (2U) + +/*! @name CV1 - Compare Value Registers */ +#define ADC_CV1_CV_MASK (0xFFFFU) +#define ADC_CV1_CV_SHIFT (0U) +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) + +/*! @name CV2 - Compare Value Registers */ +#define ADC_CV2_CV_MASK (0xFFFFU) +#define ADC_CV2_CV_SHIFT (0U) +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) + +/*! @name SC2 - Status and Control Register 2 */ +#define ADC_SC2_REFSEL_MASK (0x3U) +#define ADC_SC2_REFSEL_SHIFT (0U) +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK (0x4U) +#define ADC_SC2_DMAEN_SHIFT (2U) +#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) +#define ADC_SC2_ACREN_MASK (0x8U) +#define ADC_SC2_ACREN_SHIFT (3U) +#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) +#define ADC_SC2_ACFGT_MASK (0x10U) +#define ADC_SC2_ACFGT_SHIFT (4U) +#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) +#define ADC_SC2_ACFE_MASK (0x20U) +#define ADC_SC2_ACFE_SHIFT (5U) +#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) +#define ADC_SC2_ADTRG_MASK (0x40U) +#define ADC_SC2_ADTRG_SHIFT (6U) +#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) +#define ADC_SC2_ADACT_MASK (0x80U) +#define ADC_SC2_ADACT_SHIFT (7U) +#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) + +/*! @name SC3 - Status and Control Register 3 */ +#define ADC_SC3_AVGS_MASK (0x3U) +#define ADC_SC3_AVGS_SHIFT (0U) +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK (0x4U) +#define ADC_SC3_AVGE_SHIFT (2U) +#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) +#define ADC_SC3_ADCO_MASK (0x8U) +#define ADC_SC3_ADCO_SHIFT (3U) +#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) +#define ADC_SC3_CALF_MASK (0x40U) +#define ADC_SC3_CALF_SHIFT (6U) +#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) +#define ADC_SC3_CAL_MASK (0x80U) +#define ADC_SC3_CAL_SHIFT (7U) +#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) + +/*! @name OFS - ADC Offset Correction Register */ +#define ADC_OFS_OFS_MASK (0xFFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) + +/*! @name PG - ADC Plus-Side Gain Register */ +#define ADC_PG_PG_MASK (0xFFFFU) +#define ADC_PG_PG_SHIFT (0U) +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) + +/*! @name MG - ADC Minus-Side Gain Register */ +#define ADC_MG_MG_MASK (0xFFFFU) +#define ADC_MG_MG_SHIFT (0U) +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) + +/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPD_CLPD_MASK (0x3FU) +#define ADC_CLPD_CLPD_SHIFT (0U) +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) + +/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPS_CLPS_MASK (0x3FU) +#define ADC_CLPS_CLPS_SHIFT (0U) +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) + +/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP4_CLP4_MASK (0x3FFU) +#define ADC_CLP4_CLP4_SHIFT (0U) +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) + +/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP3_CLP3_MASK (0x1FFU) +#define ADC_CLP3_CLP3_SHIFT (0U) +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) + +/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP2_CLP2_MASK (0xFFU) +#define ADC_CLP2_CLP2_SHIFT (0U) +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) + +/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP1_CLP1_MASK (0x7FU) +#define ADC_CLP1_CLP1_SHIFT (0U) +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) + +/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP0_CLP0_MASK (0x3FU) +#define ADC_CLP0_CLP0_SHIFT (0U) +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) + +/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMD_CLMD_MASK (0x3FU) +#define ADC_CLMD_CLMD_SHIFT (0U) +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) + +/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMS_CLMS_MASK (0x3FU) +#define ADC_CLMS_CLMS_SHIFT (0U) +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) + +/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM4_CLM4_MASK (0x3FFU) +#define ADC_CLM4_CLM4_SHIFT (0U) +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) + +/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM3_CLM3_MASK (0x1FFU) +#define ADC_CLM3_CLM3_SHIFT (0U) +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) + +/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM2_CLM2_MASK (0xFFU) +#define ADC_CLM2_CLM2_SHIFT (0U) +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) + +/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM1_CLM1_MASK (0x7FU) +#define ADC_CLM1_CLM1_SHIFT (0U) +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) + +/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM0_CLM0_MASK (0x3FU) +#define ADC_CLM0_CLM0_SHIFT (0U) +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x40027000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) + +/*! @name CR1 - CMP Control Register 1 */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_TRIGM_MASK (0x20U) +#define CMP_CR1_TRIGM_SHIFT (5U) +#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) + +/*! @name FPR - CMP Filter Period Register */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) + +/*! @name SCR - CMP Status and Control Register */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) + +/*! @name DACCR - DAC Control Register */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) + +/*! @name MUXCR - MUX Control Register */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40073008u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { CMP0, CMP1 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ + } ACCESS8BIT; + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ + } GPOLY_ACCESS8BIT; + }; + union { /* offset: 0x8 */ + __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ + } CTRL_ACCESS8BIT; + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATAL - CRC_DATAL register. */ +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) + +/*! @name DATAH - CRC_DATAH register. */ +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) + +/*! @name DATA - CRC Data register */ +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) + +/*! @name DATALL - CRC_DATALL register. */ +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) + +/*! @name DATALU - CRC_DATALU register. */ +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) + +/*! @name DATAHL - CRC_DATAHL register. */ +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) + +/*! @name DATAHU - CRC_DATAHU register. */ +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) + +/*! @name GPOLYL - CRC_GPOLYL register. */ +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) + +/*! @name GPOLYH - CRC_GPOLYH register. */ +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) + +/*! @name GPOLY - CRC Polynomial register */ +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) + +/*! @name GPOLYLL - CRC_GPOLYLL register. */ +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) + +/*! @name GPOLYLU - CRC_GPOLYLU register. */ +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) + +/*! @name GPOLYHL - CRC_GPOLYHL register. */ +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) + +/*! @name GPOLYHU - CRC_GPOLYHU register. */ +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) + +/*! @name CTRL - CRC Control register */ +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) + +/*! @name CTRLHU - CRC_CTRLHU register. */ +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC base address */ +#define CRC_BASE (0x40032000u) +/** Peripheral CRC base pointer */ +#define CRC0 ((CRC_Type *)CRC_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/** DAC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x2 */ + __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[16]; + __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ + __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ + __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ + __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ +} DAC_Type; + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/*! @name DATL - DAC Data Low Register */ +#define DAC_DATL_DATA0_MASK (0xFFU) +#define DAC_DATL_DATA0_SHIFT (0U) +#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) + +/* The count of DAC_DATL */ +#define DAC_DATL_COUNT (16U) + +/*! @name DATH - DAC Data High Register */ +#define DAC_DATH_DATA1_MASK (0xFU) +#define DAC_DATH_DATA1_SHIFT (0U) +#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) + +/* The count of DAC_DATH */ +#define DAC_DATH_COUNT (16U) + +/*! @name SR - DAC Status Register */ +#define DAC_SR_DACBFRPBF_MASK (0x1U) +#define DAC_SR_DACBFRPBF_SHIFT (0U) +#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) +#define DAC_SR_DACBFRPTF_MASK (0x2U) +#define DAC_SR_DACBFRPTF_SHIFT (1U) +#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) +#define DAC_SR_DACBFWMF_MASK (0x4U) +#define DAC_SR_DACBFWMF_SHIFT (2U) +#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) + +/*! @name C0 - DAC Control Register */ +#define DAC_C0_DACBBIEN_MASK (0x1U) +#define DAC_C0_DACBBIEN_SHIFT (0U) +#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) +#define DAC_C0_DACBTIEN_MASK (0x2U) +#define DAC_C0_DACBTIEN_SHIFT (1U) +#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) +#define DAC_C0_DACBWIEN_MASK (0x4U) +#define DAC_C0_DACBWIEN_SHIFT (2U) +#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) +#define DAC_C0_LPEN_MASK (0x8U) +#define DAC_C0_LPEN_SHIFT (3U) +#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) +#define DAC_C0_DACSWTRG_MASK (0x10U) +#define DAC_C0_DACSWTRG_SHIFT (4U) +#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) +#define DAC_C0_DACTRGSEL_MASK (0x20U) +#define DAC_C0_DACTRGSEL_SHIFT (5U) +#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) +#define DAC_C0_DACRFS_MASK (0x40U) +#define DAC_C0_DACRFS_SHIFT (6U) +#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) +#define DAC_C0_DACEN_MASK (0x80U) +#define DAC_C0_DACEN_SHIFT (7U) +#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) + +/*! @name C1 - DAC Control Register 1 */ +#define DAC_C1_DACBFEN_MASK (0x1U) +#define DAC_C1_DACBFEN_SHIFT (0U) +#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) +#define DAC_C1_DACBFMD_MASK (0x6U) +#define DAC_C1_DACBFMD_SHIFT (1U) +#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) +#define DAC_C1_DACBFWM_MASK (0x18U) +#define DAC_C1_DACBFWM_SHIFT (3U) +#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) +#define DAC_C1_DMAEN_MASK (0x80U) +#define DAC_C1_DMAEN_SHIFT (7U) +#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) + +/*! @name C2 - DAC Control Register 2 */ +#define DAC_C2_DACBFUP_MASK (0xFU) +#define DAC_C2_DACBFUP_SHIFT (0U) +#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) +#define DAC_C2_DACBFRP_MASK (0xF0U) +#define DAC_C2_DACBFRP_SHIFT (4U) +#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) + + +/*! + * @} + */ /* end of group DAC_Register_Masks */ + + +/* DAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x4003F000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((DAC_Type *)DAC0_BASE) +/** Peripheral DAC1 base address */ +#define DAC1_BASE (0x40028000u) +/** Peripheral DAC1 base pointer */ +#define DAC1 ((DAC_Type *)DAC1_BASE) +/** Array initializer of DAC peripheral base addresses */ +#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } +/** Array initializer of DAC peripheral base pointers */ +#define DAC_BASE_PTRS { DAC0, DAC1 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/*! + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + uint8_t RESERVED_7[3824]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[16]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) + +/*! @name ES - Error Status Register */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0xF00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) + +/*! @name ERQ - Enable Request Register */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) + +/*! @name EEI - Enable Error Interrupt Register */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +#define DMA_CEEI_CEEI_MASK (0xFU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) + +/*! @name SEEI - Set Enable Error Interrupt Register */ +#define DMA_SEEI_SEEI_MASK (0xFU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) + +/*! @name CERQ - Clear Enable Request Register */ +#define DMA_CERQ_CERQ_MASK (0xFU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) + +/*! @name SERQ - Set Enable Request Register */ +#define DMA_SERQ_SERQ_MASK (0xFU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) + +/*! @name CDNE - Clear DONE Status Bit Register */ +#define DMA_CDNE_CDNE_MASK (0xFU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) + +/*! @name SSRT - Set START Bit Register */ +#define DMA_SSRT_SSRT_MASK (0xFU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) + +/*! @name CERR - Clear Error Register */ +#define DMA_CERR_CERR_MASK (0xFU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) + +/*! @name CINT - Clear Interrupt Request Register */ +#define DMA_CINT_CINT_MASK (0xFU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) + +/*! @name INT - Interrupt Request Register */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) + +/*! @name ERR - Error Register */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) + +/*! @name HRS - Hardware Request Status Register */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) + +/*! @name EARS - Enable Asynchronous Request in Stop Register */ +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) + +/*! @name DCHPRI3 - Channel n Priority Register */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) + +/*! @name DCHPRI2 - Channel n Priority Register */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) + +/*! @name DCHPRI1 - Channel n Priority Register */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) + +/*! @name DCHPRI0 - Channel n Priority Register */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) + +/*! @name DCHPRI7 - Channel n Priority Register */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) + +/*! @name DCHPRI6 - Channel n Priority Register */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) + +/*! @name DCHPRI5 - Channel n Priority Register */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) + +/*! @name DCHPRI4 - Channel n Priority Register */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) + +/*! @name DCHPRI11 - Channel n Priority Register */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) + +/*! @name DCHPRI10 - Channel n Priority Register */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) + +/*! @name DCHPRI9 - Channel n Priority Register */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) + +/*! @name DCHPRI8 - Channel n Priority Register */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) + +/*! @name DCHPRI15 - Channel n Priority Register */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) + +/*! @name DCHPRI14 - Channel n Priority Register */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) + +/*! @name DCHPRI13 - Channel n Priority Register */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) + +/*! @name DCHPRI12 - Channel n Priority Register */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) + +/*! @name SADDR - TCD Source Address */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (16U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (16U) + +/*! @name ATTR - TCD Transfer Attributes */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (16U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (16U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (16U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (16U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (16U) + +/*! @name DADDR - TCD Destination Address */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (16U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (16U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (16U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (16U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (16U) + +/*! @name CSR - TCD Control and Status */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0xF00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (16U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (16U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (16U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base address */ +#define DMA_BASE (0x40008000u) +/** Peripheral DMA base pointer */ +#define DMA0 ((DMA_Type *)DMA_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } +#define DMA_ERROR_IRQS { DMA_Error_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel Configuration register */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40U) +#define DMAMUX_CHCFG_TRIG_SHIFT (6U) +#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80U) +#define DMAMUX_CHCFG_ENBL_SHIFT (7U) +#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (16U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x40021000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ + uint8_t RESERVED_0[1]; + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) + +/*! @name SERV - Service Register */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) + +/*! @name CMPL - Compare Low Register */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) + +/*! @name CMPH - Compare High Register */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) + +/*! @name CLKPRESCALER - Clock Prescaler Register */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x40061000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { WDOG_EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer + * @{ + */ + +/** FB - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0xC */ + __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ + __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ + __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ + } CS[6]; + uint8_t RESERVED_0[24]; + __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */ +} FB_Type; + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/*! @name CSAR - Chip Select Address Register */ +#define FB_CSAR_BA_MASK (0xFFFF0000U) +#define FB_CSAR_BA_SHIFT (16U) +#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) + +/* The count of FB_CSAR */ +#define FB_CSAR_COUNT (6U) + +/*! @name CSMR - Chip Select Mask Register */ +#define FB_CSMR_V_MASK (0x1U) +#define FB_CSMR_V_SHIFT (0U) +#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) +#define FB_CSMR_WP_MASK (0x100U) +#define FB_CSMR_WP_SHIFT (8U) +#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) +#define FB_CSMR_BAM_MASK (0xFFFF0000U) +#define FB_CSMR_BAM_SHIFT (16U) +#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) + +/* The count of FB_CSMR */ +#define FB_CSMR_COUNT (6U) + +/*! @name CSCR - Chip Select Control Register */ +#define FB_CSCR_BSTW_MASK (0x8U) +#define FB_CSCR_BSTW_SHIFT (3U) +#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) +#define FB_CSCR_BSTR_MASK (0x10U) +#define FB_CSCR_BSTR_SHIFT (4U) +#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) +#define FB_CSCR_BEM_MASK (0x20U) +#define FB_CSCR_BEM_SHIFT (5U) +#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) +#define FB_CSCR_PS_MASK (0xC0U) +#define FB_CSCR_PS_SHIFT (6U) +#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) +#define FB_CSCR_AA_MASK (0x100U) +#define FB_CSCR_AA_SHIFT (8U) +#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) +#define FB_CSCR_BLS_MASK (0x200U) +#define FB_CSCR_BLS_SHIFT (9U) +#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) +#define FB_CSCR_WS_MASK (0xFC00U) +#define FB_CSCR_WS_SHIFT (10U) +#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) +#define FB_CSCR_WRAH_MASK (0x30000U) +#define FB_CSCR_WRAH_SHIFT (16U) +#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) +#define FB_CSCR_RDAH_MASK (0xC0000U) +#define FB_CSCR_RDAH_SHIFT (18U) +#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) +#define FB_CSCR_ASET_MASK (0x300000U) +#define FB_CSCR_ASET_SHIFT (20U) +#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) +#define FB_CSCR_EXTS_MASK (0x400000U) +#define FB_CSCR_EXTS_SHIFT (22U) +#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) +#define FB_CSCR_SWSEN_MASK (0x800000U) +#define FB_CSCR_SWSEN_SHIFT (23U) +#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) +#define FB_CSCR_SWS_MASK (0xFC000000U) +#define FB_CSCR_SWS_SHIFT (26U) +#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) + +/* The count of FB_CSCR */ +#define FB_CSCR_COUNT (6U) + +/*! @name CSPMCR - Chip Select port Multiplexing Control Register */ +#define FB_CSPMCR_GROUP5_MASK (0xF000U) +#define FB_CSPMCR_GROUP5_SHIFT (12U) +#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) +#define FB_CSPMCR_GROUP4_MASK (0xF0000U) +#define FB_CSPMCR_GROUP4_SHIFT (16U) +#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) +#define FB_CSPMCR_GROUP3_MASK (0xF00000U) +#define FB_CSPMCR_GROUP3_SHIFT (20U) +#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) +#define FB_CSPMCR_GROUP2_MASK (0xF000000U) +#define FB_CSPMCR_GROUP2_SHIFT (24U) +#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) +#define FB_CSPMCR_GROUP1_MASK (0xF0000000U) +#define FB_CSPMCR_GROUP1_SHIFT (28U) +#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) + + +/*! + * @} + */ /* end of group FB_Register_Masks */ + + +/* FB - Peripheral instance base addresses */ +/** Peripheral FB base address */ +#define FB_BASE (0x4000C000u) +/** Peripheral FB base pointer */ +#define FB ((FB_Type *)FB_BASE) +/** Array initializer of FB peripheral base addresses */ +#define FB_BASE_ADDRS { FB_BASE } +/** Array initializer of FB peripheral base pointers */ +#define FB_BASE_PTRS { FB } + +/*! + * @} + */ /* end of group FB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ + __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ + __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */ + uint8_t RESERVED_0[244]; + __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */ + __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */ + __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */ + __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_1[128]; + struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */ + __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */ + __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */ + } SET[4][8]; +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name PFAPR - Flash Access Protection Register */ +#define FMC_PFAPR_M0AP_MASK (0x3U) +#define FMC_PFAPR_M0AP_SHIFT (0U) +#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) +#define FMC_PFAPR_M1AP_MASK (0xCU) +#define FMC_PFAPR_M1AP_SHIFT (2U) +#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) +#define FMC_PFAPR_M2AP_MASK (0x30U) +#define FMC_PFAPR_M2AP_SHIFT (4U) +#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) +#define FMC_PFAPR_M3AP_MASK (0xC0U) +#define FMC_PFAPR_M3AP_SHIFT (6U) +#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) +#define FMC_PFAPR_M4AP_MASK (0x300U) +#define FMC_PFAPR_M4AP_SHIFT (8U) +#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) +#define FMC_PFAPR_M5AP_MASK (0xC00U) +#define FMC_PFAPR_M5AP_SHIFT (10U) +#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK) +#define FMC_PFAPR_M6AP_MASK (0x3000U) +#define FMC_PFAPR_M6AP_SHIFT (12U) +#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK) +#define FMC_PFAPR_M7AP_MASK (0xC000U) +#define FMC_PFAPR_M7AP_SHIFT (14U) +#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK) +#define FMC_PFAPR_M0PFD_MASK (0x10000U) +#define FMC_PFAPR_M0PFD_SHIFT (16U) +#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) +#define FMC_PFAPR_M1PFD_MASK (0x20000U) +#define FMC_PFAPR_M1PFD_SHIFT (17U) +#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) +#define FMC_PFAPR_M2PFD_MASK (0x40000U) +#define FMC_PFAPR_M2PFD_SHIFT (18U) +#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) +#define FMC_PFAPR_M3PFD_MASK (0x80000U) +#define FMC_PFAPR_M3PFD_SHIFT (19U) +#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) +#define FMC_PFAPR_M4PFD_MASK (0x100000U) +#define FMC_PFAPR_M4PFD_SHIFT (20U) +#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) +#define FMC_PFAPR_M5PFD_MASK (0x200000U) +#define FMC_PFAPR_M5PFD_SHIFT (21U) +#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK) +#define FMC_PFAPR_M6PFD_MASK (0x400000U) +#define FMC_PFAPR_M6PFD_SHIFT (22U) +#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK) +#define FMC_PFAPR_M7PFD_MASK (0x800000U) +#define FMC_PFAPR_M7PFD_SHIFT (23U) +#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK) + +/*! @name PFB0CR - Flash Bank 0 Control Register */ +#define FMC_PFB0CR_B0SEBE_MASK (0x1U) +#define FMC_PFB0CR_B0SEBE_SHIFT (0U) +#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) +#define FMC_PFB0CR_B0IPE_MASK (0x2U) +#define FMC_PFB0CR_B0IPE_SHIFT (1U) +#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) +#define FMC_PFB0CR_B0DPE_MASK (0x4U) +#define FMC_PFB0CR_B0DPE_SHIFT (2U) +#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) +#define FMC_PFB0CR_B0ICE_MASK (0x8U) +#define FMC_PFB0CR_B0ICE_SHIFT (3U) +#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) +#define FMC_PFB0CR_B0DCE_MASK (0x10U) +#define FMC_PFB0CR_B0DCE_SHIFT (4U) +#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) +#define FMC_PFB0CR_CRC_MASK (0xE0U) +#define FMC_PFB0CR_CRC_SHIFT (5U) +#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) +#define FMC_PFB0CR_B0MW_MASK (0x60000U) +#define FMC_PFB0CR_B0MW_SHIFT (17U) +#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) +#define FMC_PFB0CR_S_B_INV_MASK (0x80000U) +#define FMC_PFB0CR_S_B_INV_SHIFT (19U) +#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) +#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) +#define FMC_PFB0CR_CINV_WAY_SHIFT (20U) +#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) +#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) +#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) +#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) +#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) +#define FMC_PFB0CR_B0RWSC_SHIFT (28U) +#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) + +/*! @name PFB1CR - Flash Bank 1 Control Register */ +#define FMC_PFB1CR_B1SEBE_MASK (0x1U) +#define FMC_PFB1CR_B1SEBE_SHIFT (0U) +#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK) +#define FMC_PFB1CR_B1IPE_MASK (0x2U) +#define FMC_PFB1CR_B1IPE_SHIFT (1U) +#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK) +#define FMC_PFB1CR_B1DPE_MASK (0x4U) +#define FMC_PFB1CR_B1DPE_SHIFT (2U) +#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK) +#define FMC_PFB1CR_B1ICE_MASK (0x8U) +#define FMC_PFB1CR_B1ICE_SHIFT (3U) +#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK) +#define FMC_PFB1CR_B1DCE_MASK (0x10U) +#define FMC_PFB1CR_B1DCE_SHIFT (4U) +#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK) +#define FMC_PFB1CR_B1MW_MASK (0x60000U) +#define FMC_PFB1CR_B1MW_SHIFT (17U) +#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK) +#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U) +#define FMC_PFB1CR_B1RWSC_SHIFT (28U) +#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK) + +/*! @name TAGVDW0S - Cache Tag Storage */ +#define FMC_TAGVDW0S_valid_MASK (0x1U) +#define FMC_TAGVDW0S_valid_SHIFT (0U) +#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK) +#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW0S_tag_SHIFT (5U) +#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK) + +/* The count of FMC_TAGVDW0S */ +#define FMC_TAGVDW0S_COUNT (8U) + +/*! @name TAGVDW1S - Cache Tag Storage */ +#define FMC_TAGVDW1S_valid_MASK (0x1U) +#define FMC_TAGVDW1S_valid_SHIFT (0U) +#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK) +#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW1S_tag_SHIFT (5U) +#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK) + +/* The count of FMC_TAGVDW1S */ +#define FMC_TAGVDW1S_COUNT (8U) + +/*! @name TAGVDW2S - Cache Tag Storage */ +#define FMC_TAGVDW2S_valid_MASK (0x1U) +#define FMC_TAGVDW2S_valid_SHIFT (0U) +#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK) +#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW2S_tag_SHIFT (5U) +#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK) + +/* The count of FMC_TAGVDW2S */ +#define FMC_TAGVDW2S_COUNT (8U) + +/*! @name TAGVDW3S - Cache Tag Storage */ +#define FMC_TAGVDW3S_valid_MASK (0x1U) +#define FMC_TAGVDW3S_valid_SHIFT (0U) +#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK) +#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW3S_tag_SHIFT (5U) +#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK) + +/* The count of FMC_TAGVDW3S */ +#define FMC_TAGVDW3S_COUNT (8U) + +/*! @name DATA_U - Cache Data Storage (upper word) */ +#define FMC_DATA_U_data_MASK (0xFFFFFFFFU) +#define FMC_DATA_U_data_SHIFT (0U) +#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK) + +/* The count of FMC_DATA_U */ +#define FMC_DATA_U_COUNT (4U) + +/* The count of FMC_DATA_U */ +#define FMC_DATA_U_COUNT2 (8U) + +/*! @name DATA_L - Cache Data Storage (lower word) */ +#define FMC_DATA_L_data_MASK (0xFFFFFFFFU) +#define FMC_DATA_L_data_SHIFT (0U) +#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK) + +/* The count of FMC_DATA_L */ +#define FMC_DATA_L_COUNT (4U) + +/* The count of FMC_DATA_L */ +#define FMC_DATA_L_COUNT2 (8U) + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x4001F000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC } + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTFA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer + * @{ + */ + +/** FTFA - Register Layout Typedef */ +typedef struct { + __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ + __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ + __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ + uint8_t RESERVED_0[4]; + __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */ + __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */ + __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */ + __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */ + __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */ + __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */ + __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */ + __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */ + __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */ + __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */ + __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */ + __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */ + __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */ + __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */ + __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */ + __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */ + __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */ + uint8_t RESERVED_1[2]; + __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */ +} FTFA_Type; + +/* ---------------------------------------------------------------------------- + -- FTFA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFA_Register_Masks FTFA Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +#define FTFA_FSTAT_MGSTAT0_MASK (0x1U) +#define FTFA_FSTAT_MGSTAT0_SHIFT (0U) +#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) +#define FTFA_FSTAT_FPVIOL_MASK (0x10U) +#define FTFA_FSTAT_FPVIOL_SHIFT (4U) +#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) +#define FTFA_FSTAT_ACCERR_MASK (0x20U) +#define FTFA_FSTAT_ACCERR_SHIFT (5U) +#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) +#define FTFA_FSTAT_RDCOLERR_MASK (0x40U) +#define FTFA_FSTAT_RDCOLERR_SHIFT (6U) +#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) +#define FTFA_FSTAT_CCIF_MASK (0x80U) +#define FTFA_FSTAT_CCIF_SHIFT (7U) +#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) + +/*! @name FCNFG - Flash Configuration Register */ +#define FTFA_FCNFG_ERSSUSP_MASK (0x10U) +#define FTFA_FCNFG_ERSSUSP_SHIFT (4U) +#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) +#define FTFA_FCNFG_ERSAREQ_MASK (0x20U) +#define FTFA_FCNFG_ERSAREQ_SHIFT (5U) +#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) +#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) +#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) +#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) +#define FTFA_FCNFG_CCIE_MASK (0x80U) +#define FTFA_FCNFG_CCIE_SHIFT (7U) +#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) + +/*! @name FSEC - Flash Security Register */ +#define FTFA_FSEC_SEC_MASK (0x3U) +#define FTFA_FSEC_SEC_SHIFT (0U) +#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) +#define FTFA_FSEC_FSLACC_MASK (0xCU) +#define FTFA_FSEC_FSLACC_SHIFT (2U) +#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) +#define FTFA_FSEC_MEEN_MASK (0x30U) +#define FTFA_FSEC_MEEN_SHIFT (4U) +#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) +#define FTFA_FSEC_KEYEN_MASK (0xC0U) +#define FTFA_FSEC_KEYEN_SHIFT (6U) +#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) + +/*! @name FOPT - Flash Option Register */ +#define FTFA_FOPT_OPT_MASK (0xFFU) +#define FTFA_FOPT_OPT_SHIFT (0U) +#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) + +/*! @name FCCOB3 - Flash Common Command Object Registers */ +#define FTFA_FCCOB3_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB3_CCOBn_SHIFT (0U) +#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) + +/*! @name FCCOB2 - Flash Common Command Object Registers */ +#define FTFA_FCCOB2_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB2_CCOBn_SHIFT (0U) +#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) + +/*! @name FCCOB1 - Flash Common Command Object Registers */ +#define FTFA_FCCOB1_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB1_CCOBn_SHIFT (0U) +#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) + +/*! @name FCCOB0 - Flash Common Command Object Registers */ +#define FTFA_FCCOB0_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB0_CCOBn_SHIFT (0U) +#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) + +/*! @name FCCOB7 - Flash Common Command Object Registers */ +#define FTFA_FCCOB7_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB7_CCOBn_SHIFT (0U) +#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) + +/*! @name FCCOB6 - Flash Common Command Object Registers */ +#define FTFA_FCCOB6_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB6_CCOBn_SHIFT (0U) +#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) + +/*! @name FCCOB5 - Flash Common Command Object Registers */ +#define FTFA_FCCOB5_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB5_CCOBn_SHIFT (0U) +#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) + +/*! @name FCCOB4 - Flash Common Command Object Registers */ +#define FTFA_FCCOB4_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB4_CCOBn_SHIFT (0U) +#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) + +/*! @name FCCOBB - Flash Common Command Object Registers */ +#define FTFA_FCCOBB_CCOBn_MASK (0xFFU) +#define FTFA_FCCOBB_CCOBn_SHIFT (0U) +#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) + +/*! @name FCCOBA - Flash Common Command Object Registers */ +#define FTFA_FCCOBA_CCOBn_MASK (0xFFU) +#define FTFA_FCCOBA_CCOBn_SHIFT (0U) +#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) + +/*! @name FCCOB9 - Flash Common Command Object Registers */ +#define FTFA_FCCOB9_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB9_CCOBn_SHIFT (0U) +#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) + +/*! @name FCCOB8 - Flash Common Command Object Registers */ +#define FTFA_FCCOB8_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB8_CCOBn_SHIFT (0U) +#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) + +/*! @name FPROT3 - Program Flash Protection Registers */ +#define FTFA_FPROT3_PROT_MASK (0xFFU) +#define FTFA_FPROT3_PROT_SHIFT (0U) +#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Program Flash Protection Registers */ +#define FTFA_FPROT2_PROT_MASK (0xFFU) +#define FTFA_FPROT2_PROT_SHIFT (0U) +#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Program Flash Protection Registers */ +#define FTFA_FPROT1_PROT_MASK (0xFFU) +#define FTFA_FPROT1_PROT_SHIFT (0U) +#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Program Flash Protection Registers */ +#define FTFA_FPROT0_PROT_MASK (0xFFU) +#define FTFA_FPROT0_PROT_SHIFT (0U) +#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) + +/*! @name XACCH3 - Execute-only Access Registers */ +#define FTFA_XACCH3_XA_MASK (0xFFU) +#define FTFA_XACCH3_XA_SHIFT (0U) +#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK) + +/*! @name XACCH2 - Execute-only Access Registers */ +#define FTFA_XACCH2_XA_MASK (0xFFU) +#define FTFA_XACCH2_XA_SHIFT (0U) +#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK) + +/*! @name XACCH1 - Execute-only Access Registers */ +#define FTFA_XACCH1_XA_MASK (0xFFU) +#define FTFA_XACCH1_XA_SHIFT (0U) +#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK) + +/*! @name XACCH0 - Execute-only Access Registers */ +#define FTFA_XACCH0_XA_MASK (0xFFU) +#define FTFA_XACCH0_XA_SHIFT (0U) +#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK) + +/*! @name XACCL3 - Execute-only Access Registers */ +#define FTFA_XACCL3_XA_MASK (0xFFU) +#define FTFA_XACCL3_XA_SHIFT (0U) +#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK) + +/*! @name XACCL2 - Execute-only Access Registers */ +#define FTFA_XACCL2_XA_MASK (0xFFU) +#define FTFA_XACCL2_XA_SHIFT (0U) +#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK) + +/*! @name XACCL1 - Execute-only Access Registers */ +#define FTFA_XACCL1_XA_MASK (0xFFU) +#define FTFA_XACCL1_XA_SHIFT (0U) +#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK) + +/*! @name XACCL0 - Execute-only Access Registers */ +#define FTFA_XACCL0_XA_MASK (0xFFU) +#define FTFA_XACCL0_XA_SHIFT (0U) +#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK) + +/*! @name SACCH3 - Supervisor-only Access Registers */ +#define FTFA_SACCH3_SA_MASK (0xFFU) +#define FTFA_SACCH3_SA_SHIFT (0U) +#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK) + +/*! @name SACCH2 - Supervisor-only Access Registers */ +#define FTFA_SACCH2_SA_MASK (0xFFU) +#define FTFA_SACCH2_SA_SHIFT (0U) +#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK) + +/*! @name SACCH1 - Supervisor-only Access Registers */ +#define FTFA_SACCH1_SA_MASK (0xFFU) +#define FTFA_SACCH1_SA_SHIFT (0U) +#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK) + +/*! @name SACCH0 - Supervisor-only Access Registers */ +#define FTFA_SACCH0_SA_MASK (0xFFU) +#define FTFA_SACCH0_SA_SHIFT (0U) +#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK) + +/*! @name SACCL3 - Supervisor-only Access Registers */ +#define FTFA_SACCL3_SA_MASK (0xFFU) +#define FTFA_SACCL3_SA_SHIFT (0U) +#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK) + +/*! @name SACCL2 - Supervisor-only Access Registers */ +#define FTFA_SACCL2_SA_MASK (0xFFU) +#define FTFA_SACCL2_SA_SHIFT (0U) +#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK) + +/*! @name SACCL1 - Supervisor-only Access Registers */ +#define FTFA_SACCL1_SA_MASK (0xFFU) +#define FTFA_SACCL1_SA_SHIFT (0U) +#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK) + +/*! @name SACCL0 - Supervisor-only Access Registers */ +#define FTFA_SACCL0_SA_MASK (0xFFU) +#define FTFA_SACCL0_SA_SHIFT (0U) +#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK) + +/*! @name FACSS - Flash Access Segment Size Register */ +#define FTFA_FACSS_SGSIZE_MASK (0xFFU) +#define FTFA_FACSS_SGSIZE_SHIFT (0U) +#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK) + +/*! @name FACSN - Flash Access Segment Number Register */ +#define FTFA_FACSN_NUMSG_MASK (0xFFU) +#define FTFA_FACSN_NUMSG_SHIFT (0U) +#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK) + + +/*! + * @} + */ /* end of group FTFA_Register_Masks */ + + +/* FTFA - Peripheral instance base addresses */ +/** Peripheral FTFA base address */ +#define FTFA_BASE (0x40020000u) +/** Peripheral FTFA base pointer */ +#define FTFA ((FTFA_Type *)FTFA_BASE) +/** Array initializer of FTFA peripheral base addresses */ +#define FTFA_BASE_ADDRS { FTFA_BASE } +/** Array initializer of FTFA peripheral base pointers */ +#define FTFA_BASE_PTRS { FTFA } +/** Interrupt vectors for the FTFA peripheral type */ +#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn } +#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn } + +/*! + * @} + */ /* end of group FTFA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/** FTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } CONTROLS[8]; + __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ + __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ + __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ + __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ + __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ + __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ + __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ + __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ + __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ + __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ + __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ + __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ + __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ + __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ + __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ +} FTM_Type; + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/*! @name SC - Status And Control */ +#define FTM_SC_PS_MASK (0x7U) +#define FTM_SC_PS_SHIFT (0U) +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK (0x18U) +#define FTM_SC_CLKS_SHIFT (3U) +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS_MASK (0x20U) +#define FTM_SC_CPWMS_SHIFT (5U) +#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) +#define FTM_SC_TOIE_MASK (0x40U) +#define FTM_SC_TOIE_SHIFT (6U) +#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) +#define FTM_SC_TOF_MASK (0x80U) +#define FTM_SC_TOF_SHIFT (7U) +#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) + +/*! @name CNT - Counter */ +#define FTM_CNT_COUNT_MASK (0xFFFFU) +#define FTM_CNT_COUNT_SHIFT (0U) +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) + +/*! @name MOD - Modulo */ +#define FTM_MOD_MOD_MASK (0xFFFFU) +#define FTM_MOD_MOD_SHIFT (0U) +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) + +/*! @name CnSC - Channel (n) Status And Control */ +#define FTM_CnSC_DMA_MASK (0x1U) +#define FTM_CnSC_DMA_SHIFT (0U) +#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) +#define FTM_CnSC_ICRST_MASK (0x2U) +#define FTM_CnSC_ICRST_SHIFT (1U) +#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) +#define FTM_CnSC_ELSA_MASK (0x4U) +#define FTM_CnSC_ELSA_SHIFT (2U) +#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) +#define FTM_CnSC_ELSB_MASK (0x8U) +#define FTM_CnSC_ELSB_SHIFT (3U) +#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) +#define FTM_CnSC_MSA_MASK (0x10U) +#define FTM_CnSC_MSA_SHIFT (4U) +#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) +#define FTM_CnSC_MSB_MASK (0x20U) +#define FTM_CnSC_MSB_SHIFT (5U) +#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) +#define FTM_CnSC_CHIE_MASK (0x40U) +#define FTM_CnSC_CHIE_SHIFT (6U) +#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) +#define FTM_CnSC_CHF_MASK (0x80U) +#define FTM_CnSC_CHF_SHIFT (7U) +#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) + +/* The count of FTM_CnSC */ +#define FTM_CnSC_COUNT (8U) + +/*! @name CnV - Channel (n) Value */ +#define FTM_CnV_VAL_MASK (0xFFFFU) +#define FTM_CnV_VAL_SHIFT (0U) +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) + +/* The count of FTM_CnV */ +#define FTM_CnV_COUNT (8U) + +/*! @name CNTIN - Counter Initial Value */ +#define FTM_CNTIN_INIT_MASK (0xFFFFU) +#define FTM_CNTIN_INIT_SHIFT (0U) +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) + +/*! @name STATUS - Capture And Compare Status */ +#define FTM_STATUS_CH0F_MASK (0x1U) +#define FTM_STATUS_CH0F_SHIFT (0U) +#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) +#define FTM_STATUS_CH1F_MASK (0x2U) +#define FTM_STATUS_CH1F_SHIFT (1U) +#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) +#define FTM_STATUS_CH2F_MASK (0x4U) +#define FTM_STATUS_CH2F_SHIFT (2U) +#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) +#define FTM_STATUS_CH3F_MASK (0x8U) +#define FTM_STATUS_CH3F_SHIFT (3U) +#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) +#define FTM_STATUS_CH4F_MASK (0x10U) +#define FTM_STATUS_CH4F_SHIFT (4U) +#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) +#define FTM_STATUS_CH5F_MASK (0x20U) +#define FTM_STATUS_CH5F_SHIFT (5U) +#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) +#define FTM_STATUS_CH6F_MASK (0x40U) +#define FTM_STATUS_CH6F_SHIFT (6U) +#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) +#define FTM_STATUS_CH7F_MASK (0x80U) +#define FTM_STATUS_CH7F_SHIFT (7U) +#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) + +/*! @name MODE - Features Mode Selection */ +#define FTM_MODE_FTMEN_MASK (0x1U) +#define FTM_MODE_FTMEN_SHIFT (0U) +#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) +#define FTM_MODE_INIT_MASK (0x2U) +#define FTM_MODE_INIT_SHIFT (1U) +#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) +#define FTM_MODE_WPDIS_MASK (0x4U) +#define FTM_MODE_WPDIS_SHIFT (2U) +#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) +#define FTM_MODE_PWMSYNC_MASK (0x8U) +#define FTM_MODE_PWMSYNC_SHIFT (3U) +#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) +#define FTM_MODE_CAPTEST_MASK (0x10U) +#define FTM_MODE_CAPTEST_SHIFT (4U) +#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) +#define FTM_MODE_FAULTM_MASK (0x60U) +#define FTM_MODE_FAULTM_SHIFT (5U) +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK (0x80U) +#define FTM_MODE_FAULTIE_SHIFT (7U) +#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) + +/*! @name SYNC - Synchronization */ +#define FTM_SYNC_CNTMIN_MASK (0x1U) +#define FTM_SYNC_CNTMIN_SHIFT (0U) +#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) +#define FTM_SYNC_CNTMAX_MASK (0x2U) +#define FTM_SYNC_CNTMAX_SHIFT (1U) +#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) +#define FTM_SYNC_REINIT_MASK (0x4U) +#define FTM_SYNC_REINIT_SHIFT (2U) +#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) +#define FTM_SYNC_SYNCHOM_MASK (0x8U) +#define FTM_SYNC_SYNCHOM_SHIFT (3U) +#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) +#define FTM_SYNC_TRIG0_MASK (0x10U) +#define FTM_SYNC_TRIG0_SHIFT (4U) +#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) +#define FTM_SYNC_TRIG1_MASK (0x20U) +#define FTM_SYNC_TRIG1_SHIFT (5U) +#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) +#define FTM_SYNC_TRIG2_MASK (0x40U) +#define FTM_SYNC_TRIG2_SHIFT (6U) +#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) +#define FTM_SYNC_SWSYNC_MASK (0x80U) +#define FTM_SYNC_SWSYNC_SHIFT (7U) +#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) + +/*! @name OUTINIT - Initial State For Channels Output */ +#define FTM_OUTINIT_CH0OI_MASK (0x1U) +#define FTM_OUTINIT_CH0OI_SHIFT (0U) +#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) +#define FTM_OUTINIT_CH1OI_MASK (0x2U) +#define FTM_OUTINIT_CH1OI_SHIFT (1U) +#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) +#define FTM_OUTINIT_CH2OI_MASK (0x4U) +#define FTM_OUTINIT_CH2OI_SHIFT (2U) +#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) +#define FTM_OUTINIT_CH3OI_MASK (0x8U) +#define FTM_OUTINIT_CH3OI_SHIFT (3U) +#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) +#define FTM_OUTINIT_CH4OI_MASK (0x10U) +#define FTM_OUTINIT_CH4OI_SHIFT (4U) +#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) +#define FTM_OUTINIT_CH5OI_MASK (0x20U) +#define FTM_OUTINIT_CH5OI_SHIFT (5U) +#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) +#define FTM_OUTINIT_CH6OI_MASK (0x40U) +#define FTM_OUTINIT_CH6OI_SHIFT (6U) +#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) +#define FTM_OUTINIT_CH7OI_MASK (0x80U) +#define FTM_OUTINIT_CH7OI_SHIFT (7U) +#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) + +/*! @name OUTMASK - Output Mask */ +#define FTM_OUTMASK_CH0OM_MASK (0x1U) +#define FTM_OUTMASK_CH0OM_SHIFT (0U) +#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) +#define FTM_OUTMASK_CH1OM_MASK (0x2U) +#define FTM_OUTMASK_CH1OM_SHIFT (1U) +#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) +#define FTM_OUTMASK_CH2OM_MASK (0x4U) +#define FTM_OUTMASK_CH2OM_SHIFT (2U) +#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) +#define FTM_OUTMASK_CH3OM_MASK (0x8U) +#define FTM_OUTMASK_CH3OM_SHIFT (3U) +#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) +#define FTM_OUTMASK_CH4OM_MASK (0x10U) +#define FTM_OUTMASK_CH4OM_SHIFT (4U) +#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) +#define FTM_OUTMASK_CH5OM_MASK (0x20U) +#define FTM_OUTMASK_CH5OM_SHIFT (5U) +#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) +#define FTM_OUTMASK_CH6OM_MASK (0x40U) +#define FTM_OUTMASK_CH6OM_SHIFT (6U) +#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) +#define FTM_OUTMASK_CH7OM_MASK (0x80U) +#define FTM_OUTMASK_CH7OM_SHIFT (7U) +#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) + +/*! @name COMBINE - Function For Linked Channels */ +#define FTM_COMBINE_COMBINE0_MASK (0x1U) +#define FTM_COMBINE_COMBINE0_SHIFT (0U) +#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) +#define FTM_COMBINE_COMP0_MASK (0x2U) +#define FTM_COMBINE_COMP0_SHIFT (1U) +#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) +#define FTM_COMBINE_DECAPEN0_MASK (0x4U) +#define FTM_COMBINE_DECAPEN0_SHIFT (2U) +#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) +#define FTM_COMBINE_DECAP0_MASK (0x8U) +#define FTM_COMBINE_DECAP0_SHIFT (3U) +#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) +#define FTM_COMBINE_DTEN0_MASK (0x10U) +#define FTM_COMBINE_DTEN0_SHIFT (4U) +#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) +#define FTM_COMBINE_SYNCEN0_MASK (0x20U) +#define FTM_COMBINE_SYNCEN0_SHIFT (5U) +#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) +#define FTM_COMBINE_FAULTEN0_MASK (0x40U) +#define FTM_COMBINE_FAULTEN0_SHIFT (6U) +#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) +#define FTM_COMBINE_COMBINE1_MASK (0x100U) +#define FTM_COMBINE_COMBINE1_SHIFT (8U) +#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) +#define FTM_COMBINE_COMP1_MASK (0x200U) +#define FTM_COMBINE_COMP1_SHIFT (9U) +#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) +#define FTM_COMBINE_DECAPEN1_MASK (0x400U) +#define FTM_COMBINE_DECAPEN1_SHIFT (10U) +#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) +#define FTM_COMBINE_DECAP1_MASK (0x800U) +#define FTM_COMBINE_DECAP1_SHIFT (11U) +#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) +#define FTM_COMBINE_DTEN1_MASK (0x1000U) +#define FTM_COMBINE_DTEN1_SHIFT (12U) +#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) +#define FTM_COMBINE_SYNCEN1_MASK (0x2000U) +#define FTM_COMBINE_SYNCEN1_SHIFT (13U) +#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) +#define FTM_COMBINE_FAULTEN1_MASK (0x4000U) +#define FTM_COMBINE_FAULTEN1_SHIFT (14U) +#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) +#define FTM_COMBINE_COMBINE2_MASK (0x10000U) +#define FTM_COMBINE_COMBINE2_SHIFT (16U) +#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) +#define FTM_COMBINE_COMP2_MASK (0x20000U) +#define FTM_COMBINE_COMP2_SHIFT (17U) +#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) +#define FTM_COMBINE_DECAPEN2_MASK (0x40000U) +#define FTM_COMBINE_DECAPEN2_SHIFT (18U) +#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) +#define FTM_COMBINE_DECAP2_MASK (0x80000U) +#define FTM_COMBINE_DECAP2_SHIFT (19U) +#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) +#define FTM_COMBINE_DTEN2_MASK (0x100000U) +#define FTM_COMBINE_DTEN2_SHIFT (20U) +#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) +#define FTM_COMBINE_SYNCEN2_MASK (0x200000U) +#define FTM_COMBINE_SYNCEN2_SHIFT (21U) +#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) +#define FTM_COMBINE_FAULTEN2_MASK (0x400000U) +#define FTM_COMBINE_FAULTEN2_SHIFT (22U) +#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) +#define FTM_COMBINE_COMBINE3_MASK (0x1000000U) +#define FTM_COMBINE_COMBINE3_SHIFT (24U) +#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) +#define FTM_COMBINE_COMP3_MASK (0x2000000U) +#define FTM_COMBINE_COMP3_SHIFT (25U) +#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) +#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) +#define FTM_COMBINE_DECAPEN3_SHIFT (26U) +#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) +#define FTM_COMBINE_DECAP3_MASK (0x8000000U) +#define FTM_COMBINE_DECAP3_SHIFT (27U) +#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) +#define FTM_COMBINE_DTEN3_MASK (0x10000000U) +#define FTM_COMBINE_DTEN3_SHIFT (28U) +#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) +#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) +#define FTM_COMBINE_SYNCEN3_SHIFT (29U) +#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) +#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) +#define FTM_COMBINE_FAULTEN3_SHIFT (30U) +#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) + +/*! @name DEADTIME - Deadtime Insertion Control */ +#define FTM_DEADTIME_DTVAL_MASK (0x3FU) +#define FTM_DEADTIME_DTVAL_SHIFT (0U) +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK (0xC0U) +#define FTM_DEADTIME_DTPS_SHIFT (6U) +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) + +/*! @name EXTTRIG - FTM External Trigger */ +#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) +#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) +#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) +#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) +#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) +#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) +#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) +#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) +#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) +#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) +#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) +#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) +#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) +#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) +#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) +#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) +#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) +#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) +#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) +#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) +#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) +#define FTM_EXTTRIG_TRIGF_MASK (0x80U) +#define FTM_EXTTRIG_TRIGF_SHIFT (7U) +#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) + +/*! @name POL - Channels Polarity */ +#define FTM_POL_POL0_MASK (0x1U) +#define FTM_POL_POL0_SHIFT (0U) +#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) +#define FTM_POL_POL1_MASK (0x2U) +#define FTM_POL_POL1_SHIFT (1U) +#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) +#define FTM_POL_POL2_MASK (0x4U) +#define FTM_POL_POL2_SHIFT (2U) +#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) +#define FTM_POL_POL3_MASK (0x8U) +#define FTM_POL_POL3_SHIFT (3U) +#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) +#define FTM_POL_POL4_MASK (0x10U) +#define FTM_POL_POL4_SHIFT (4U) +#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) +#define FTM_POL_POL5_MASK (0x20U) +#define FTM_POL_POL5_SHIFT (5U) +#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) +#define FTM_POL_POL6_MASK (0x40U) +#define FTM_POL_POL6_SHIFT (6U) +#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) +#define FTM_POL_POL7_MASK (0x80U) +#define FTM_POL_POL7_SHIFT (7U) +#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) + +/*! @name FMS - Fault Mode Status */ +#define FTM_FMS_FAULTF0_MASK (0x1U) +#define FTM_FMS_FAULTF0_SHIFT (0U) +#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) +#define FTM_FMS_FAULTF1_MASK (0x2U) +#define FTM_FMS_FAULTF1_SHIFT (1U) +#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) +#define FTM_FMS_FAULTF2_MASK (0x4U) +#define FTM_FMS_FAULTF2_SHIFT (2U) +#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) +#define FTM_FMS_FAULTF3_MASK (0x8U) +#define FTM_FMS_FAULTF3_SHIFT (3U) +#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) +#define FTM_FMS_FAULTIN_MASK (0x20U) +#define FTM_FMS_FAULTIN_SHIFT (5U) +#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) +#define FTM_FMS_WPEN_MASK (0x40U) +#define FTM_FMS_WPEN_SHIFT (6U) +#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) +#define FTM_FMS_FAULTF_MASK (0x80U) +#define FTM_FMS_FAULTF_SHIFT (7U) +#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) + +/*! @name FILTER - Input Capture Filter Control */ +#define FTM_FILTER_CH0FVAL_MASK (0xFU) +#define FTM_FILTER_CH0FVAL_SHIFT (0U) +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK (0xF0U) +#define FTM_FILTER_CH1FVAL_SHIFT (4U) +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK (0xF00U) +#define FTM_FILTER_CH2FVAL_SHIFT (8U) +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK (0xF000U) +#define FTM_FILTER_CH3FVAL_SHIFT (12U) +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) + +/*! @name FLTCTRL - Fault Control */ +#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) +#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) +#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) +#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) +#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) +#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) +#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) +#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) +#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) +#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) +#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) +#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) +#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) +#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) +#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) +#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) +#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) +#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) +#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) +#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) +#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) +#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) +#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) +#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) +#define FTM_FLTCTRL_FFVAL_MASK (0xF00U) +#define FTM_FLTCTRL_FFVAL_SHIFT (8U) +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) + +/*! @name QDCTRL - Quadrature Decoder Control And Status */ +#define FTM_QDCTRL_QUADEN_MASK (0x1U) +#define FTM_QDCTRL_QUADEN_SHIFT (0U) +#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) +#define FTM_QDCTRL_TOFDIR_MASK (0x2U) +#define FTM_QDCTRL_TOFDIR_SHIFT (1U) +#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) +#define FTM_QDCTRL_QUADIR_MASK (0x4U) +#define FTM_QDCTRL_QUADIR_SHIFT (2U) +#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) +#define FTM_QDCTRL_QUADMODE_MASK (0x8U) +#define FTM_QDCTRL_QUADMODE_SHIFT (3U) +#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) +#define FTM_QDCTRL_PHBPOL_MASK (0x10U) +#define FTM_QDCTRL_PHBPOL_SHIFT (4U) +#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) +#define FTM_QDCTRL_PHAPOL_MASK (0x20U) +#define FTM_QDCTRL_PHAPOL_SHIFT (5U) +#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) +#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) +#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) +#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) +#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) +#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) +#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) + +/*! @name CONF - Configuration */ +#define FTM_CONF_NUMTOF_MASK (0x1FU) +#define FTM_CONF_NUMTOF_SHIFT (0U) +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK (0xC0U) +#define FTM_CONF_BDMMODE_SHIFT (6U) +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK (0x200U) +#define FTM_CONF_GTBEEN_SHIFT (9U) +#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) +#define FTM_CONF_GTBEOUT_MASK (0x400U) +#define FTM_CONF_GTBEOUT_SHIFT (10U) +#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) + +/*! @name FLTPOL - FTM Fault Input Polarity */ +#define FTM_FLTPOL_FLT0POL_MASK (0x1U) +#define FTM_FLTPOL_FLT0POL_SHIFT (0U) +#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) +#define FTM_FLTPOL_FLT1POL_MASK (0x2U) +#define FTM_FLTPOL_FLT1POL_SHIFT (1U) +#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) +#define FTM_FLTPOL_FLT2POL_MASK (0x4U) +#define FTM_FLTPOL_FLT2POL_SHIFT (2U) +#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) +#define FTM_FLTPOL_FLT3POL_MASK (0x8U) +#define FTM_FLTPOL_FLT3POL_SHIFT (3U) +#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) + +/*! @name SYNCONF - Synchronization Configuration */ +#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) +#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) +#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) +#define FTM_SYNCONF_CNTINC_MASK (0x4U) +#define FTM_SYNCONF_CNTINC_SHIFT (2U) +#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) +#define FTM_SYNCONF_INVC_MASK (0x10U) +#define FTM_SYNCONF_INVC_SHIFT (4U) +#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) +#define FTM_SYNCONF_SWOC_MASK (0x20U) +#define FTM_SYNCONF_SWOC_SHIFT (5U) +#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) +#define FTM_SYNCONF_SYNCMODE_MASK (0x80U) +#define FTM_SYNCONF_SYNCMODE_SHIFT (7U) +#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) +#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) +#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) +#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) +#define FTM_SYNCONF_SWWRBUF_MASK (0x200U) +#define FTM_SYNCONF_SWWRBUF_SHIFT (9U) +#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) +#define FTM_SYNCONF_SWOM_MASK (0x400U) +#define FTM_SYNCONF_SWOM_SHIFT (10U) +#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) +#define FTM_SYNCONF_SWINVC_MASK (0x800U) +#define FTM_SYNCONF_SWINVC_SHIFT (11U) +#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) +#define FTM_SYNCONF_SWSOC_MASK (0x1000U) +#define FTM_SYNCONF_SWSOC_SHIFT (12U) +#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) +#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) +#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) +#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) +#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) +#define FTM_SYNCONF_HWWRBUF_SHIFT (17U) +#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) +#define FTM_SYNCONF_HWOM_MASK (0x40000U) +#define FTM_SYNCONF_HWOM_SHIFT (18U) +#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) +#define FTM_SYNCONF_HWINVC_MASK (0x80000U) +#define FTM_SYNCONF_HWINVC_SHIFT (19U) +#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) +#define FTM_SYNCONF_HWSOC_MASK (0x100000U) +#define FTM_SYNCONF_HWSOC_SHIFT (20U) +#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) + +/*! @name INVCTRL - FTM Inverting Control */ +#define FTM_INVCTRL_INV0EN_MASK (0x1U) +#define FTM_INVCTRL_INV0EN_SHIFT (0U) +#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) +#define FTM_INVCTRL_INV1EN_MASK (0x2U) +#define FTM_INVCTRL_INV1EN_SHIFT (1U) +#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) +#define FTM_INVCTRL_INV2EN_MASK (0x4U) +#define FTM_INVCTRL_INV2EN_SHIFT (2U) +#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) +#define FTM_INVCTRL_INV3EN_MASK (0x8U) +#define FTM_INVCTRL_INV3EN_SHIFT (3U) +#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) + +/*! @name SWOCTRL - FTM Software Output Control */ +#define FTM_SWOCTRL_CH0OC_MASK (0x1U) +#define FTM_SWOCTRL_CH0OC_SHIFT (0U) +#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) +#define FTM_SWOCTRL_CH1OC_MASK (0x2U) +#define FTM_SWOCTRL_CH1OC_SHIFT (1U) +#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) +#define FTM_SWOCTRL_CH2OC_MASK (0x4U) +#define FTM_SWOCTRL_CH2OC_SHIFT (2U) +#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) +#define FTM_SWOCTRL_CH3OC_MASK (0x8U) +#define FTM_SWOCTRL_CH3OC_SHIFT (3U) +#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) +#define FTM_SWOCTRL_CH4OC_MASK (0x10U) +#define FTM_SWOCTRL_CH4OC_SHIFT (4U) +#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) +#define FTM_SWOCTRL_CH5OC_MASK (0x20U) +#define FTM_SWOCTRL_CH5OC_SHIFT (5U) +#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) +#define FTM_SWOCTRL_CH6OC_MASK (0x40U) +#define FTM_SWOCTRL_CH6OC_SHIFT (6U) +#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) +#define FTM_SWOCTRL_CH7OC_MASK (0x80U) +#define FTM_SWOCTRL_CH7OC_SHIFT (7U) +#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) +#define FTM_SWOCTRL_CH0OCV_MASK (0x100U) +#define FTM_SWOCTRL_CH0OCV_SHIFT (8U) +#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) +#define FTM_SWOCTRL_CH1OCV_MASK (0x200U) +#define FTM_SWOCTRL_CH1OCV_SHIFT (9U) +#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) +#define FTM_SWOCTRL_CH2OCV_MASK (0x400U) +#define FTM_SWOCTRL_CH2OCV_SHIFT (10U) +#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) +#define FTM_SWOCTRL_CH3OCV_MASK (0x800U) +#define FTM_SWOCTRL_CH3OCV_SHIFT (11U) +#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) +#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) +#define FTM_SWOCTRL_CH4OCV_SHIFT (12U) +#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) +#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) +#define FTM_SWOCTRL_CH5OCV_SHIFT (13U) +#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) +#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) +#define FTM_SWOCTRL_CH6OCV_SHIFT (14U) +#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) +#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) +#define FTM_SWOCTRL_CH7OCV_SHIFT (15U) +#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) + +/*! @name PWMLOAD - FTM PWM Load */ +#define FTM_PWMLOAD_CH0SEL_MASK (0x1U) +#define FTM_PWMLOAD_CH0SEL_SHIFT (0U) +#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) +#define FTM_PWMLOAD_CH1SEL_MASK (0x2U) +#define FTM_PWMLOAD_CH1SEL_SHIFT (1U) +#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) +#define FTM_PWMLOAD_CH2SEL_MASK (0x4U) +#define FTM_PWMLOAD_CH2SEL_SHIFT (2U) +#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) +#define FTM_PWMLOAD_CH3SEL_MASK (0x8U) +#define FTM_PWMLOAD_CH3SEL_SHIFT (3U) +#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) +#define FTM_PWMLOAD_CH4SEL_MASK (0x10U) +#define FTM_PWMLOAD_CH4SEL_SHIFT (4U) +#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) +#define FTM_PWMLOAD_CH5SEL_MASK (0x20U) +#define FTM_PWMLOAD_CH5SEL_SHIFT (5U) +#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) +#define FTM_PWMLOAD_CH6SEL_MASK (0x40U) +#define FTM_PWMLOAD_CH6SEL_SHIFT (6U) +#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) +#define FTM_PWMLOAD_CH7SEL_MASK (0x80U) +#define FTM_PWMLOAD_CH7SEL_SHIFT (7U) +#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) +#define FTM_PWMLOAD_LDOK_MASK (0x200U) +#define FTM_PWMLOAD_LDOK_SHIFT (9U) +#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) + + +/*! + * @} + */ /* end of group FTM_Register_Masks */ + + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM0 base address */ +#define FTM0_BASE (0x40038000u) +/** Peripheral FTM0 base pointer */ +#define FTM0 ((FTM_Type *)FTM0_BASE) +/** Peripheral FTM1 base address */ +#define FTM1_BASE (0x40039000u) +/** Peripheral FTM1 base pointer */ +#define FTM1 ((FTM_Type *)FTM1_BASE) +/** Peripheral FTM2 base address */ +#define FTM2_BASE (0x4003A000u) +/** Peripheral FTM2 base pointer */ +#define FTM2 ((FTM_Type *)FTM2_BASE) +/** Peripheral FTM3 base address */ +#define FTM3_BASE (0x40026000u) +/** Peripheral FTM3 base pointer */ +#define FTM3 ((FTM_Type *)FTM3_BASE) +/** Array initializer of FTM peripheral base addresses */ +#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE } +/** Array initializer of FTM peripheral base pointers */ +#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 } +/** Interrupt vectors for the FTM peripheral type */ +#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn } + +/*! + * @} + */ /* end of group FTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name PDOR - Port Data Output Register */ +#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) +#define GPIO_PDOR_PDO_SHIFT (0U) +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) + +/*! @name PSOR - Port Set Output Register */ +#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define GPIO_PSOR_PTSO_SHIFT (0U) +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) + +/*! @name PCOR - Port Clear Output Register */ +#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define GPIO_PCOR_PTCO_SHIFT (0U) +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) + +/*! @name PTOR - Port Toggle Output Register */ +#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define GPIO_PTOR_PTTO_SHIFT (0U) +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) + +/*! @name PDIR - Port Data Input Register */ +#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define GPIO_PDIR_PDI_SHIFT (0U) +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) + +/*! @name PDDR - Port Data Direction Register */ +#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define GPIO_PDDR_PDD_SHIFT (0U) +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral PTA base address */ +#define PTA_BASE (0x400FF000u) +/** Peripheral PTA base pointer */ +#define PTA ((GPIO_Type *)PTA_BASE) +/** Peripheral PTB base address */ +#define PTB_BASE (0x400FF040u) +/** Peripheral PTB base pointer */ +#define PTB ((GPIO_Type *)PTB_BASE) +/** Peripheral PTC base address */ +#define PTC_BASE (0x400FF080u) +/** Peripheral PTC base pointer */ +#define PTC ((GPIO_Type *)PTC_BASE) +/** Peripheral PTD base address */ +#define PTD_BASE (0x400FF0C0u) +/** Peripheral PTD base pointer */ +#define PTD ((GPIO_Type *)PTD_BASE) +/** Peripheral PTE base address */ +#define PTE_BASE (0x400FF100u) +/** Peripheral PTE base pointer */ +#define PTE ((GPIO_Type *)PTE_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ + __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ + __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ + __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ + __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ + __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ + __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ + __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ + __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ + __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ + __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ + __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name A1 - I2C Address Register 1 */ +#define I2C_A1_AD_MASK (0xFEU) +#define I2C_A1_AD_SHIFT (1U) +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) + +/*! @name F - I2C Frequency Divider register */ +#define I2C_F_ICR_MASK (0x3FU) +#define I2C_F_ICR_SHIFT (0U) +#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) +#define I2C_F_MULT_MASK (0xC0U) +#define I2C_F_MULT_SHIFT (6U) +#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) + +/*! @name C1 - I2C Control Register 1 */ +#define I2C_C1_DMAEN_MASK (0x1U) +#define I2C_C1_DMAEN_SHIFT (0U) +#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) +#define I2C_C1_WUEN_MASK (0x2U) +#define I2C_C1_WUEN_SHIFT (1U) +#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) +#define I2C_C1_RSTA_MASK (0x4U) +#define I2C_C1_RSTA_SHIFT (2U) +#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) +#define I2C_C1_TXAK_MASK (0x8U) +#define I2C_C1_TXAK_SHIFT (3U) +#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) +#define I2C_C1_TX_MASK (0x10U) +#define I2C_C1_TX_SHIFT (4U) +#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) +#define I2C_C1_MST_MASK (0x20U) +#define I2C_C1_MST_SHIFT (5U) +#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) +#define I2C_C1_IICIE_MASK (0x40U) +#define I2C_C1_IICIE_SHIFT (6U) +#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) +#define I2C_C1_IICEN_MASK (0x80U) +#define I2C_C1_IICEN_SHIFT (7U) +#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) + +/*! @name S - I2C Status register */ +#define I2C_S_RXAK_MASK (0x1U) +#define I2C_S_RXAK_SHIFT (0U) +#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) +#define I2C_S_IICIF_MASK (0x2U) +#define I2C_S_IICIF_SHIFT (1U) +#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) +#define I2C_S_SRW_MASK (0x4U) +#define I2C_S_SRW_SHIFT (2U) +#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) +#define I2C_S_RAM_MASK (0x8U) +#define I2C_S_RAM_SHIFT (3U) +#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) +#define I2C_S_ARBL_MASK (0x10U) +#define I2C_S_ARBL_SHIFT (4U) +#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) +#define I2C_S_BUSY_MASK (0x20U) +#define I2C_S_BUSY_SHIFT (5U) +#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) +#define I2C_S_IAAS_MASK (0x40U) +#define I2C_S_IAAS_SHIFT (6U) +#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) +#define I2C_S_TCF_MASK (0x80U) +#define I2C_S_TCF_SHIFT (7U) +#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) + +/*! @name D - I2C Data I/O register */ +#define I2C_D_DATA_MASK (0xFFU) +#define I2C_D_DATA_SHIFT (0U) +#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) + +/*! @name C2 - I2C Control Register 2 */ +#define I2C_C2_AD_MASK (0x7U) +#define I2C_C2_AD_SHIFT (0U) +#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) +#define I2C_C2_RMEN_MASK (0x8U) +#define I2C_C2_RMEN_SHIFT (3U) +#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) +#define I2C_C2_SBRC_MASK (0x10U) +#define I2C_C2_SBRC_SHIFT (4U) +#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) +#define I2C_C2_HDRS_MASK (0x20U) +#define I2C_C2_HDRS_SHIFT (5U) +#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) +#define I2C_C2_ADEXT_MASK (0x40U) +#define I2C_C2_ADEXT_SHIFT (6U) +#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) +#define I2C_C2_GCAEN_MASK (0x80U) +#define I2C_C2_GCAEN_SHIFT (7U) +#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) + +/*! @name FLT - I2C Programmable Input Glitch Filter register */ +#define I2C_FLT_FLT_MASK (0xFU) +#define I2C_FLT_FLT_SHIFT (0U) +#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) +#define I2C_FLT_STARTF_MASK (0x10U) +#define I2C_FLT_STARTF_SHIFT (4U) +#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) +#define I2C_FLT_SSIE_MASK (0x20U) +#define I2C_FLT_SSIE_SHIFT (5U) +#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) +#define I2C_FLT_STOPF_MASK (0x40U) +#define I2C_FLT_STOPF_SHIFT (6U) +#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) +#define I2C_FLT_SHEN_MASK (0x80U) +#define I2C_FLT_SHEN_SHIFT (7U) +#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) + +/*! @name RA - I2C Range Address register */ +#define I2C_RA_RAD_MASK (0xFEU) +#define I2C_RA_RAD_SHIFT (1U) +#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) + +/*! @name SMB - I2C SMBus Control and Status register */ +#define I2C_SMB_SHTF2IE_MASK (0x1U) +#define I2C_SMB_SHTF2IE_SHIFT (0U) +#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) +#define I2C_SMB_SHTF2_MASK (0x2U) +#define I2C_SMB_SHTF2_SHIFT (1U) +#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) +#define I2C_SMB_SHTF1_MASK (0x4U) +#define I2C_SMB_SHTF1_SHIFT (2U) +#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) +#define I2C_SMB_SLTF_MASK (0x8U) +#define I2C_SMB_SLTF_SHIFT (3U) +#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) +#define I2C_SMB_TCKSEL_MASK (0x10U) +#define I2C_SMB_TCKSEL_SHIFT (4U) +#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) +#define I2C_SMB_SIICAEN_MASK (0x20U) +#define I2C_SMB_SIICAEN_SHIFT (5U) +#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) +#define I2C_SMB_ALERTEN_MASK (0x40U) +#define I2C_SMB_ALERTEN_SHIFT (6U) +#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) +#define I2C_SMB_FACK_MASK (0x80U) +#define I2C_SMB_FACK_SHIFT (7U) +#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) + +/*! @name A2 - I2C Address Register 2 */ +#define I2C_A2_SAD_MASK (0xFEU) +#define I2C_A2_SAD_SHIFT (1U) +#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) + +/*! @name SLTH - I2C SCL Low Timeout Register High */ +#define I2C_SLTH_SSLT_MASK (0xFFU) +#define I2C_SLTH_SSLT_SHIFT (0U) +#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) + +/*! @name SLTL - I2C SCL Low Timeout Register Low */ +#define I2C_SLTL_SSLT_MASK (0xFFU) +#define I2C_SLTL_SSLT_SHIFT (0U) +#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40066000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40067000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[28]; + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[28]; + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ + __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x7U) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0xFU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x10000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0xF0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (1U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0xFU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0xF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (1U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x7U) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0xFU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x10000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0xF0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (1U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0xFU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0xF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (1U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + +/*! @name MCR - SAI MCLK Control Register */ +#define I2S_MCR_MICS_MASK (0x3000000U) +#define I2S_MCR_MICS_SHIFT (24U) +#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +#define I2S_MCR_DUF_MASK (0x80000000U) +#define I2S_MCR_DUF_SHIFT (31U) +#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) + +/*! @name MDR - SAI MCLK Divide Register */ +#define I2S_MDR_DIVIDE_MASK (0xFFFU) +#define I2S_MDR_DIVIDE_SHIFT (0U) +#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) +#define I2S_MDR_FRACT_MASK (0xFF000U) +#define I2S_MDR_FRACT_SHIFT (12U) +#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x4002F000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { I2S0_Rx_IRQn } +#define I2S_TX_IRQS { I2S0_Tx_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer + * @{ + */ + +/** LLWU - Register Layout Typedef */ +typedef struct { + __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ + __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ + __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ + __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ + __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ + __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ + __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ + __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ + __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ + __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ +} LLWU_Type; + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/*! @name PE1 - LLWU Pin Enable 1 register */ +#define LLWU_PE1_WUPE0_MASK (0x3U) +#define LLWU_PE1_WUPE0_SHIFT (0U) +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) +#define LLWU_PE1_WUPE1_MASK (0xCU) +#define LLWU_PE1_WUPE1_SHIFT (2U) +#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) +#define LLWU_PE1_WUPE2_MASK (0x30U) +#define LLWU_PE1_WUPE2_SHIFT (4U) +#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) +#define LLWU_PE1_WUPE3_MASK (0xC0U) +#define LLWU_PE1_WUPE3_SHIFT (6U) +#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) + +/*! @name PE2 - LLWU Pin Enable 2 register */ +#define LLWU_PE2_WUPE4_MASK (0x3U) +#define LLWU_PE2_WUPE4_SHIFT (0U) +#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) +#define LLWU_PE2_WUPE5_MASK (0xCU) +#define LLWU_PE2_WUPE5_SHIFT (2U) +#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) +#define LLWU_PE2_WUPE6_MASK (0x30U) +#define LLWU_PE2_WUPE6_SHIFT (4U) +#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) +#define LLWU_PE2_WUPE7_MASK (0xC0U) +#define LLWU_PE2_WUPE7_SHIFT (6U) +#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) + +/*! @name PE3 - LLWU Pin Enable 3 register */ +#define LLWU_PE3_WUPE8_MASK (0x3U) +#define LLWU_PE3_WUPE8_SHIFT (0U) +#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) +#define LLWU_PE3_WUPE9_MASK (0xCU) +#define LLWU_PE3_WUPE9_SHIFT (2U) +#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) +#define LLWU_PE3_WUPE10_MASK (0x30U) +#define LLWU_PE3_WUPE10_SHIFT (4U) +#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) +#define LLWU_PE3_WUPE11_MASK (0xC0U) +#define LLWU_PE3_WUPE11_SHIFT (6U) +#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) + +/*! @name PE4 - LLWU Pin Enable 4 register */ +#define LLWU_PE4_WUPE12_MASK (0x3U) +#define LLWU_PE4_WUPE12_SHIFT (0U) +#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) +#define LLWU_PE4_WUPE13_MASK (0xCU) +#define LLWU_PE4_WUPE13_SHIFT (2U) +#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) +#define LLWU_PE4_WUPE14_MASK (0x30U) +#define LLWU_PE4_WUPE14_SHIFT (4U) +#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) +#define LLWU_PE4_WUPE15_MASK (0xC0U) +#define LLWU_PE4_WUPE15_SHIFT (6U) +#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) + +/*! @name ME - LLWU Module Enable register */ +#define LLWU_ME_WUME0_MASK (0x1U) +#define LLWU_ME_WUME0_SHIFT (0U) +#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) +#define LLWU_ME_WUME1_MASK (0x2U) +#define LLWU_ME_WUME1_SHIFT (1U) +#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) +#define LLWU_ME_WUME2_MASK (0x4U) +#define LLWU_ME_WUME2_SHIFT (2U) +#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) +#define LLWU_ME_WUME3_MASK (0x8U) +#define LLWU_ME_WUME3_SHIFT (3U) +#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) +#define LLWU_ME_WUME4_MASK (0x10U) +#define LLWU_ME_WUME4_SHIFT (4U) +#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) +#define LLWU_ME_WUME5_MASK (0x20U) +#define LLWU_ME_WUME5_SHIFT (5U) +#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) +#define LLWU_ME_WUME6_MASK (0x40U) +#define LLWU_ME_WUME6_SHIFT (6U) +#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) +#define LLWU_ME_WUME7_MASK (0x80U) +#define LLWU_ME_WUME7_SHIFT (7U) +#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) + +/*! @name F1 - LLWU Flag 1 register */ +#define LLWU_F1_WUF0_MASK (0x1U) +#define LLWU_F1_WUF0_SHIFT (0U) +#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) +#define LLWU_F1_WUF1_MASK (0x2U) +#define LLWU_F1_WUF1_SHIFT (1U) +#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) +#define LLWU_F1_WUF2_MASK (0x4U) +#define LLWU_F1_WUF2_SHIFT (2U) +#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) +#define LLWU_F1_WUF3_MASK (0x8U) +#define LLWU_F1_WUF3_SHIFT (3U) +#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) +#define LLWU_F1_WUF4_MASK (0x10U) +#define LLWU_F1_WUF4_SHIFT (4U) +#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) +#define LLWU_F1_WUF5_MASK (0x20U) +#define LLWU_F1_WUF5_SHIFT (5U) +#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) +#define LLWU_F1_WUF6_MASK (0x40U) +#define LLWU_F1_WUF6_SHIFT (6U) +#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) +#define LLWU_F1_WUF7_MASK (0x80U) +#define LLWU_F1_WUF7_SHIFT (7U) +#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) + +/*! @name F2 - LLWU Flag 2 register */ +#define LLWU_F2_WUF8_MASK (0x1U) +#define LLWU_F2_WUF8_SHIFT (0U) +#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) +#define LLWU_F2_WUF9_MASK (0x2U) +#define LLWU_F2_WUF9_SHIFT (1U) +#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) +#define LLWU_F2_WUF10_MASK (0x4U) +#define LLWU_F2_WUF10_SHIFT (2U) +#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) +#define LLWU_F2_WUF11_MASK (0x8U) +#define LLWU_F2_WUF11_SHIFT (3U) +#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) +#define LLWU_F2_WUF12_MASK (0x10U) +#define LLWU_F2_WUF12_SHIFT (4U) +#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) +#define LLWU_F2_WUF13_MASK (0x20U) +#define LLWU_F2_WUF13_SHIFT (5U) +#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) +#define LLWU_F2_WUF14_MASK (0x40U) +#define LLWU_F2_WUF14_SHIFT (6U) +#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) +#define LLWU_F2_WUF15_MASK (0x80U) +#define LLWU_F2_WUF15_SHIFT (7U) +#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) + +/*! @name F3 - LLWU Flag 3 register */ +#define LLWU_F3_MWUF0_MASK (0x1U) +#define LLWU_F3_MWUF0_SHIFT (0U) +#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) +#define LLWU_F3_MWUF1_MASK (0x2U) +#define LLWU_F3_MWUF1_SHIFT (1U) +#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) +#define LLWU_F3_MWUF2_MASK (0x4U) +#define LLWU_F3_MWUF2_SHIFT (2U) +#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) +#define LLWU_F3_MWUF3_MASK (0x8U) +#define LLWU_F3_MWUF3_SHIFT (3U) +#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) +#define LLWU_F3_MWUF4_MASK (0x10U) +#define LLWU_F3_MWUF4_SHIFT (4U) +#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) +#define LLWU_F3_MWUF5_MASK (0x20U) +#define LLWU_F3_MWUF5_SHIFT (5U) +#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) +#define LLWU_F3_MWUF6_MASK (0x40U) +#define LLWU_F3_MWUF6_SHIFT (6U) +#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) +#define LLWU_F3_MWUF7_MASK (0x80U) +#define LLWU_F3_MWUF7_SHIFT (7U) +#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) + +/*! @name FILT1 - LLWU Pin Filter 1 register */ +#define LLWU_FILT1_FILTSEL_MASK (0xFU) +#define LLWU_FILT1_FILTSEL_SHIFT (0U) +#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) +#define LLWU_FILT1_FILTE_MASK (0x60U) +#define LLWU_FILT1_FILTE_SHIFT (5U) +#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) +#define LLWU_FILT1_FILTF_MASK (0x80U) +#define LLWU_FILT1_FILTF_SHIFT (7U) +#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) + +/*! @name FILT2 - LLWU Pin Filter 2 register */ +#define LLWU_FILT2_FILTSEL_MASK (0xFU) +#define LLWU_FILT2_FILTSEL_SHIFT (0U) +#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) +#define LLWU_FILT2_FILTE_MASK (0x60U) +#define LLWU_FILT2_FILTE_SHIFT (5U) +#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) +#define LLWU_FILT2_FILTF_MASK (0x80U) +#define LLWU_FILT2_FILTF_SHIFT (7U) +#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) + + +/*! + * @} + */ /* end of group LLWU_Register_Masks */ + + +/* LLWU - Peripheral instance base addresses */ +/** Peripheral LLWU base address */ +#define LLWU_BASE (0x4007C000u) +/** Peripheral LLWU base pointer */ +#define LLWU ((LLWU_Type *)LLWU_BASE) +/** Array initializer of LLWU peripheral base addresses */ +#define LLWU_BASE_ADDRS { LLWU_BASE } +/** Array initializer of LLWU peripheral base pointers */ +#define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } + +/*! + * @} + */ /* end of group LLWU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ + __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ + __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ + __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Low Power Timer Control Status Register */ +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +/*! @name PSR - Low Power Timer Prescale Register */ +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) + +/*! @name CMR - Low Power Timer Compare Register */ +#define LPTMR_CMR_COMPARE_MASK (0xFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) + +/*! @name CNR - Low Power Timer Counter Register */ +#define LPTMR_CNR_COUNTER_MASK (0xFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x40040000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name BAUD - LPUART Baud Rate Register */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) + +/*! @name STAT - LPUART Status Register */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) + +/*! @name CTRL - LPUART Control Register */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) + +/*! @name DATA - LPUART Data Register */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) + +/*! @name MATCH - LPUART Match Address Register */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) + +/*! @name MODIR - LPUART Modem IrDA Register */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4002A000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer + * @{ + */ + +/** MCG - Register Layout Typedef */ +typedef struct { + __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ + __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ + __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ + __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ + __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ + __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ + __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ + uint8_t RESERVED_0[1]; + __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ + uint8_t RESERVED_1[1]; + __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ + __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ + __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ + __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ +} MCG_Type; + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/*! @name C1 - MCG Control 1 Register */ +#define MCG_C1_IREFSTEN_MASK (0x1U) +#define MCG_C1_IREFSTEN_SHIFT (0U) +#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) +#define MCG_C1_IRCLKEN_MASK (0x2U) +#define MCG_C1_IRCLKEN_SHIFT (1U) +#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) +#define MCG_C1_IREFS_MASK (0x4U) +#define MCG_C1_IREFS_SHIFT (2U) +#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) +#define MCG_C1_FRDIV_MASK (0x38U) +#define MCG_C1_FRDIV_SHIFT (3U) +#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) +#define MCG_C1_CLKS_MASK (0xC0U) +#define MCG_C1_CLKS_SHIFT (6U) +#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) + +/*! @name C2 - MCG Control 2 Register */ +#define MCG_C2_IRCS_MASK (0x1U) +#define MCG_C2_IRCS_SHIFT (0U) +#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) +#define MCG_C2_LP_MASK (0x2U) +#define MCG_C2_LP_SHIFT (1U) +#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) +#define MCG_C2_EREFS_MASK (0x4U) +#define MCG_C2_EREFS_SHIFT (2U) +#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) +#define MCG_C2_HGO_MASK (0x8U) +#define MCG_C2_HGO_SHIFT (3U) +#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) +#define MCG_C2_RANGE_MASK (0x30U) +#define MCG_C2_RANGE_SHIFT (4U) +#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) +#define MCG_C2_FCFTRIM_MASK (0x40U) +#define MCG_C2_FCFTRIM_SHIFT (6U) +#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) +#define MCG_C2_LOCRE0_MASK (0x80U) +#define MCG_C2_LOCRE0_SHIFT (7U) +#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) + +/*! @name C3 - MCG Control 3 Register */ +#define MCG_C3_SCTRIM_MASK (0xFFU) +#define MCG_C3_SCTRIM_SHIFT (0U) +#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) + +/*! @name C4 - MCG Control 4 Register */ +#define MCG_C4_SCFTRIM_MASK (0x1U) +#define MCG_C4_SCFTRIM_SHIFT (0U) +#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) +#define MCG_C4_FCTRIM_MASK (0x1EU) +#define MCG_C4_FCTRIM_SHIFT (1U) +#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) +#define MCG_C4_DRST_DRS_MASK (0x60U) +#define MCG_C4_DRST_DRS_SHIFT (5U) +#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) +#define MCG_C4_DMX32_MASK (0x80U) +#define MCG_C4_DMX32_SHIFT (7U) +#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) + +/*! @name C5 - MCG Control 5 Register */ +#define MCG_C5_PRDIV0_MASK (0x1FU) +#define MCG_C5_PRDIV0_SHIFT (0U) +#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) +#define MCG_C5_PLLSTEN0_MASK (0x20U) +#define MCG_C5_PLLSTEN0_SHIFT (5U) +#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) +#define MCG_C5_PLLCLKEN0_MASK (0x40U) +#define MCG_C5_PLLCLKEN0_SHIFT (6U) +#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) + +/*! @name C6 - MCG Control 6 Register */ +#define MCG_C6_VDIV0_MASK (0x1FU) +#define MCG_C6_VDIV0_SHIFT (0U) +#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) +#define MCG_C6_CME0_MASK (0x20U) +#define MCG_C6_CME0_SHIFT (5U) +#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) +#define MCG_C6_PLLS_MASK (0x40U) +#define MCG_C6_PLLS_SHIFT (6U) +#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) +#define MCG_C6_LOLIE0_MASK (0x80U) +#define MCG_C6_LOLIE0_SHIFT (7U) +#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) + +/*! @name S - MCG Status Register */ +#define MCG_S_IRCST_MASK (0x1U) +#define MCG_S_IRCST_SHIFT (0U) +#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) +#define MCG_S_OSCINIT0_MASK (0x2U) +#define MCG_S_OSCINIT0_SHIFT (1U) +#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) +#define MCG_S_CLKST_MASK (0xCU) +#define MCG_S_CLKST_SHIFT (2U) +#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) +#define MCG_S_IREFST_MASK (0x10U) +#define MCG_S_IREFST_SHIFT (4U) +#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) +#define MCG_S_PLLST_MASK (0x20U) +#define MCG_S_PLLST_SHIFT (5U) +#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) +#define MCG_S_LOCK0_MASK (0x40U) +#define MCG_S_LOCK0_SHIFT (6U) +#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) +#define MCG_S_LOLS0_MASK (0x80U) +#define MCG_S_LOLS0_SHIFT (7U) +#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) + +/*! @name SC - MCG Status and Control Register */ +#define MCG_SC_LOCS0_MASK (0x1U) +#define MCG_SC_LOCS0_SHIFT (0U) +#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) +#define MCG_SC_FCRDIV_MASK (0xEU) +#define MCG_SC_FCRDIV_SHIFT (1U) +#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) +#define MCG_SC_FLTPRSRV_MASK (0x10U) +#define MCG_SC_FLTPRSRV_SHIFT (4U) +#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) +#define MCG_SC_ATMF_MASK (0x20U) +#define MCG_SC_ATMF_SHIFT (5U) +#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) +#define MCG_SC_ATMS_MASK (0x40U) +#define MCG_SC_ATMS_SHIFT (6U) +#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) +#define MCG_SC_ATME_MASK (0x80U) +#define MCG_SC_ATME_SHIFT (7U) +#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) + +/*! @name ATCVH - MCG Auto Trim Compare Value High Register */ +#define MCG_ATCVH_ATCVH_MASK (0xFFU) +#define MCG_ATCVH_ATCVH_SHIFT (0U) +#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) + +/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ +#define MCG_ATCVL_ATCVL_MASK (0xFFU) +#define MCG_ATCVL_ATCVL_SHIFT (0U) +#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) + +/*! @name C7 - MCG Control 7 Register */ +#define MCG_C7_OSCSEL_MASK (0x3U) +#define MCG_C7_OSCSEL_SHIFT (0U) +#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) + +/*! @name C8 - MCG Control 8 Register */ +#define MCG_C8_LOCS1_MASK (0x1U) +#define MCG_C8_LOCS1_SHIFT (0U) +#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) +#define MCG_C8_CME1_MASK (0x20U) +#define MCG_C8_CME1_SHIFT (5U) +#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) +#define MCG_C8_LOLRE_MASK (0x40U) +#define MCG_C8_LOLRE_SHIFT (6U) +#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) +#define MCG_C8_LOCRE1_MASK (0x80U) +#define MCG_C8_LOCRE1_SHIFT (7U) +#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) + + +/*! + * @} + */ /* end of group MCG_Register_Masks */ + + +/* MCG - Peripheral instance base addresses */ +/** Peripheral MCG base address */ +#define MCG_BASE (0x40064000u) +/** Peripheral MCG base pointer */ +#define MCG ((MCG_Type *)MCG_BASE) +/** Array initializer of MCG peripheral base addresses */ +#define MCG_BASE_ADDRS { MCG_BASE } +/** Array initializer of MCG peripheral base pointers */ +#define MCG_BASE_PTRS { MCG } + +/*! + * @} + */ /* end of group MCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ + __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */ + uint8_t RESERVED_1[44]; + __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ +} MCM_Type; + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +#define MCM_PLASC_ASC_MASK (0xFFU) +#define MCM_PLASC_ASC_SHIFT (0U) +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) + +/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +#define MCM_PLAMC_AMC_MASK (0xFFU) +#define MCM_PLAMC_AMC_SHIFT (0U) +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) + +/*! @name PLACR - Crossbar Switch (AXBS) Control Register */ +#define MCM_PLACR_ARB_MASK (0x200U) +#define MCM_PLACR_ARB_SHIFT (9U) +#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) + +/*! @name ISCR - Interrupt Status and Control Register */ +#define MCM_ISCR_FIOC_MASK (0x100U) +#define MCM_ISCR_FIOC_SHIFT (8U) +#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) +#define MCM_ISCR_FDZC_MASK (0x200U) +#define MCM_ISCR_FDZC_SHIFT (9U) +#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) +#define MCM_ISCR_FOFC_MASK (0x400U) +#define MCM_ISCR_FOFC_SHIFT (10U) +#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) +#define MCM_ISCR_FUFC_MASK (0x800U) +#define MCM_ISCR_FUFC_SHIFT (11U) +#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) +#define MCM_ISCR_FIXC_MASK (0x1000U) +#define MCM_ISCR_FIXC_SHIFT (12U) +#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) +#define MCM_ISCR_FIDC_MASK (0x8000U) +#define MCM_ISCR_FIDC_SHIFT (15U) +#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) +#define MCM_ISCR_FIOCE_MASK (0x1000000U) +#define MCM_ISCR_FIOCE_SHIFT (24U) +#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) +#define MCM_ISCR_FDZCE_MASK (0x2000000U) +#define MCM_ISCR_FDZCE_SHIFT (25U) +#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) +#define MCM_ISCR_FOFCE_MASK (0x4000000U) +#define MCM_ISCR_FOFCE_SHIFT (26U) +#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) +#define MCM_ISCR_FUFCE_MASK (0x8000000U) +#define MCM_ISCR_FUFCE_SHIFT (27U) +#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) +#define MCM_ISCR_FIXCE_MASK (0x10000000U) +#define MCM_ISCR_FIXCE_SHIFT (28U) +#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) +#define MCM_ISCR_FIDCE_MASK (0x80000000U) +#define MCM_ISCR_FIDCE_SHIFT (31U) +#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) + +/*! @name CPO - Compute Operation Control Register */ +#define MCM_CPO_CPOREQ_MASK (0x1U) +#define MCM_CPO_CPOREQ_SHIFT (0U) +#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) +#define MCM_CPO_CPOACK_MASK (0x2U) +#define MCM_CPO_CPOACK_SHIFT (1U) +#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) +#define MCM_CPO_CPOWOI_MASK (0x4U) +#define MCM_CPO_CPOWOI_SHIFT (2U) +#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) + + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base address */ +#define MCM_BASE (0xE0080000u) +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +/** Array initializer of MCM peripheral base addresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } +/** Interrupt vectors for the MCM peripheral type */ +#define MCM_IRQS { MCM_IRQn } + +/*! + * @} + */ /* end of group MCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer + * @{ + */ + +/** NV - Register Layout Typedef */ +typedef struct { + __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ + __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ + __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ + __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ + __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ + __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ + __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ + __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ + __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ + __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ + __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ + __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ + __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ + __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ +} NV_Type; + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/*! @name BACKKEY3 - Backdoor Comparison Key 3. */ +#define NV_BACKKEY3_KEY_MASK (0xFFU) +#define NV_BACKKEY3_KEY_SHIFT (0U) +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) + +/*! @name BACKKEY2 - Backdoor Comparison Key 2. */ +#define NV_BACKKEY2_KEY_MASK (0xFFU) +#define NV_BACKKEY2_KEY_SHIFT (0U) +#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) + +/*! @name BACKKEY1 - Backdoor Comparison Key 1. */ +#define NV_BACKKEY1_KEY_MASK (0xFFU) +#define NV_BACKKEY1_KEY_SHIFT (0U) +#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) + +/*! @name BACKKEY0 - Backdoor Comparison Key 0. */ +#define NV_BACKKEY0_KEY_MASK (0xFFU) +#define NV_BACKKEY0_KEY_SHIFT (0U) +#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) + +/*! @name BACKKEY7 - Backdoor Comparison Key 7. */ +#define NV_BACKKEY7_KEY_MASK (0xFFU) +#define NV_BACKKEY7_KEY_SHIFT (0U) +#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) + +/*! @name BACKKEY6 - Backdoor Comparison Key 6. */ +#define NV_BACKKEY6_KEY_MASK (0xFFU) +#define NV_BACKKEY6_KEY_SHIFT (0U) +#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) + +/*! @name BACKKEY5 - Backdoor Comparison Key 5. */ +#define NV_BACKKEY5_KEY_MASK (0xFFU) +#define NV_BACKKEY5_KEY_SHIFT (0U) +#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) + +/*! @name BACKKEY4 - Backdoor Comparison Key 4. */ +#define NV_BACKKEY4_KEY_MASK (0xFFU) +#define NV_BACKKEY4_KEY_SHIFT (0U) +#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) + +/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ +#define NV_FPROT3_PROT_MASK (0xFFU) +#define NV_FPROT3_PROT_SHIFT (0U) +#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ +#define NV_FPROT2_PROT_MASK (0xFFU) +#define NV_FPROT2_PROT_SHIFT (0U) +#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ +#define NV_FPROT1_PROT_MASK (0xFFU) +#define NV_FPROT1_PROT_SHIFT (0U) +#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ +#define NV_FPROT0_PROT_MASK (0xFFU) +#define NV_FPROT0_PROT_SHIFT (0U) +#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) + +/*! @name FSEC - Non-volatile Flash Security Register */ +#define NV_FSEC_SEC_MASK (0x3U) +#define NV_FSEC_SEC_SHIFT (0U) +#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) +#define NV_FSEC_FSLACC_MASK (0xCU) +#define NV_FSEC_FSLACC_SHIFT (2U) +#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) +#define NV_FSEC_MEEN_MASK (0x30U) +#define NV_FSEC_MEEN_SHIFT (4U) +#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) +#define NV_FSEC_KEYEN_MASK (0xC0U) +#define NV_FSEC_KEYEN_SHIFT (6U) +#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) + +/*! @name FOPT - Non-volatile Flash Option Register */ +#define NV_FOPT_LPBOOT_MASK (0x1U) +#define NV_FOPT_LPBOOT_SHIFT (0U) +#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) +#define NV_FOPT_EZPORT_DIS_MASK (0x2U) +#define NV_FOPT_EZPORT_DIS_SHIFT (1U) +#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) +#define NV_FOPT_NMI_DIS_MASK (0x4U) +#define NV_FOPT_NMI_DIS_SHIFT (2U) +#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) +#define NV_FOPT_FAST_INIT_MASK (0x20U) +#define NV_FOPT_FAST_INIT_SHIFT (5U) +#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) + + +/*! + * @} + */ /* end of group NV_Register_Masks */ + + +/* NV - Peripheral instance base addresses */ +/** Peripheral FTFA_FlashConfig base address */ +#define FTFA_FlashConfig_BASE (0x400u) +/** Peripheral FTFA_FlashConfig base pointer */ +#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) +/** Array initializer of NV peripheral base addresses */ +#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } +/** Array initializer of NV peripheral base pointers */ +#define NV_BASE_PTRS { FTFA_FlashConfig } + +/*! + * @} + */ /* end of group NV_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer + * @{ + */ + +/** OSC - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ + uint8_t RESERVED_0[1]; + __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */ +} OSC_Type; + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/*! @name CR - OSC Control Register */ +#define OSC_CR_SC16P_MASK (0x1U) +#define OSC_CR_SC16P_SHIFT (0U) +#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) +#define OSC_CR_SC8P_MASK (0x2U) +#define OSC_CR_SC8P_SHIFT (1U) +#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) +#define OSC_CR_SC4P_MASK (0x4U) +#define OSC_CR_SC4P_SHIFT (2U) +#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) +#define OSC_CR_SC2P_MASK (0x8U) +#define OSC_CR_SC2P_SHIFT (3U) +#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) +#define OSC_CR_EREFSTEN_MASK (0x20U) +#define OSC_CR_EREFSTEN_SHIFT (5U) +#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) +#define OSC_CR_ERCLKEN_MASK (0x80U) +#define OSC_CR_ERCLKEN_SHIFT (7U) +#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) + +/*! @name DIV - OSC_DIV */ +#define OSC_DIV_ERPS_MASK (0xC0U) +#define OSC_DIV_ERPS_SHIFT (6U) +#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK) + + +/*! + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC base address */ +#define OSC_BASE (0x40065000u) +/** Peripheral OSC base pointer */ +#define OSC ((OSC_Type *)OSC_BASE) +/** Array initializer of OSC peripheral base addresses */ +#define OSC_BASE_ADDRS { OSC_BASE } +/** Array initializer of OSC peripheral base pointers */ +#define OSC_BASE_PTRS { OSC } + +/*! + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer + * @{ + */ + +/** PDB - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ + __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ + __I uint32_t CNT; /**< Counter register, offset: 0x8 */ + __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ + __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ + uint8_t RESERVED_0[24]; + } CH[2]; + uint8_t RESERVED_0[240]; + struct { /* offset: 0x150, array step: 0x8 */ + __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ + __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ + } DAC[2]; + uint8_t RESERVED_1[48]; + __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ + __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ +} PDB_Type; + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/*! @name SC - Status and Control register */ +#define PDB_SC_LDOK_MASK (0x1U) +#define PDB_SC_LDOK_SHIFT (0U) +#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) +#define PDB_SC_CONT_MASK (0x2U) +#define PDB_SC_CONT_SHIFT (1U) +#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) +#define PDB_SC_MULT_MASK (0xCU) +#define PDB_SC_MULT_SHIFT (2U) +#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) +#define PDB_SC_PDBIE_MASK (0x20U) +#define PDB_SC_PDBIE_SHIFT (5U) +#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) +#define PDB_SC_PDBIF_MASK (0x40U) +#define PDB_SC_PDBIF_SHIFT (6U) +#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) +#define PDB_SC_PDBEN_MASK (0x80U) +#define PDB_SC_PDBEN_SHIFT (7U) +#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) +#define PDB_SC_TRGSEL_MASK (0xF00U) +#define PDB_SC_TRGSEL_SHIFT (8U) +#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) +#define PDB_SC_PRESCALER_MASK (0x7000U) +#define PDB_SC_PRESCALER_SHIFT (12U) +#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) +#define PDB_SC_DMAEN_MASK (0x8000U) +#define PDB_SC_DMAEN_SHIFT (15U) +#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) +#define PDB_SC_SWTRIG_MASK (0x10000U) +#define PDB_SC_SWTRIG_SHIFT (16U) +#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) +#define PDB_SC_PDBEIE_MASK (0x20000U) +#define PDB_SC_PDBEIE_SHIFT (17U) +#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) +#define PDB_SC_LDMOD_MASK (0xC0000U) +#define PDB_SC_LDMOD_SHIFT (18U) +#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) + +/*! @name MOD - Modulus register */ +#define PDB_MOD_MOD_MASK (0xFFFFU) +#define PDB_MOD_MOD_SHIFT (0U) +#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) + +/*! @name CNT - Counter register */ +#define PDB_CNT_CNT_MASK (0xFFFFU) +#define PDB_CNT_CNT_SHIFT (0U) +#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) + +/*! @name IDLY - Interrupt Delay register */ +#define PDB_IDLY_IDLY_MASK (0xFFFFU) +#define PDB_IDLY_IDLY_SHIFT (0U) +#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) + +/*! @name C1 - Channel n Control register 1 */ +#define PDB_C1_EN_MASK (0xFFU) +#define PDB_C1_EN_SHIFT (0U) +#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) +#define PDB_C1_TOS_MASK (0xFF00U) +#define PDB_C1_TOS_SHIFT (8U) +#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) +#define PDB_C1_BB_MASK (0xFF0000U) +#define PDB_C1_BB_SHIFT (16U) +#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) + +/* The count of PDB_C1 */ +#define PDB_C1_COUNT (2U) + +/*! @name S - Channel n Status register */ +#define PDB_S_ERR_MASK (0xFFU) +#define PDB_S_ERR_SHIFT (0U) +#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) +#define PDB_S_CF_MASK (0xFF0000U) +#define PDB_S_CF_SHIFT (16U) +#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) + +/* The count of PDB_S */ +#define PDB_S_COUNT (2U) + +/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ +#define PDB_DLY_DLY_MASK (0xFFFFU) +#define PDB_DLY_DLY_SHIFT (0U) +#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) + +/* The count of PDB_DLY */ +#define PDB_DLY_COUNT (2U) + +/* The count of PDB_DLY */ +#define PDB_DLY_COUNT2 (2U) + +/*! @name INTC - DAC Interval Trigger n Control register */ +#define PDB_INTC_TOE_MASK (0x1U) +#define PDB_INTC_TOE_SHIFT (0U) +#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) +#define PDB_INTC_EXT_MASK (0x2U) +#define PDB_INTC_EXT_SHIFT (1U) +#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) + +/* The count of PDB_INTC */ +#define PDB_INTC_COUNT (2U) + +/*! @name INT - DAC Interval n register */ +#define PDB_INT_INT_MASK (0xFFFFU) +#define PDB_INT_INT_SHIFT (0U) +#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) + +/* The count of PDB_INT */ +#define PDB_INT_COUNT (2U) + +/*! @name POEN - Pulse-Out n Enable register */ +#define PDB_POEN_POEN_MASK (0xFFU) +#define PDB_POEN_POEN_SHIFT (0U) +#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) + +/*! @name PODLY - Pulse-Out n Delay register */ +#define PDB_PODLY_DLY2_MASK (0xFFFFU) +#define PDB_PODLY_DLY2_SHIFT (0U) +#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) +#define PDB_PODLY_DLY1_MASK (0xFFFF0000U) +#define PDB_PODLY_DLY1_SHIFT (16U) +#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) + +/* The count of PDB_PODLY */ +#define PDB_PODLY_COUNT (2U) + + +/*! + * @} + */ /* end of group PDB_Register_Masks */ + + +/* PDB - Peripheral instance base addresses */ +/** Peripheral PDB0 base address */ +#define PDB0_BASE (0x40036000u) +/** Peripheral PDB0 base pointer */ +#define PDB0 ((PDB_Type *)PDB0_BASE) +/** Array initializer of PDB peripheral base addresses */ +#define PDB_BASE_ADDRS { PDB0_BASE } +/** Array initializer of PDB peripheral base pointers */ +#define PDB_BASE_PTRS { PDB0 } +/** Interrupt vectors for the PDB peripheral type */ +#define PDB_IRQS { PDB0_IRQn } + +/*! + * @} + */ /* end of group PDB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[252]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) + +/*! @name LDVAL - Timer Load Value Register */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40037000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ + __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ + __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ +#define PMC_LVDSC1_LVDV_MASK (0x3U) +#define PMC_LVDSC1_LVDV_SHIFT (0U) +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) +#define PMC_LVDSC1_LVDRE_MASK (0x10U) +#define PMC_LVDSC1_LVDRE_SHIFT (4U) +#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) +#define PMC_LVDSC1_LVDIE_MASK (0x20U) +#define PMC_LVDSC1_LVDIE_SHIFT (5U) +#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) +#define PMC_LVDSC1_LVDACK_MASK (0x40U) +#define PMC_LVDSC1_LVDACK_SHIFT (6U) +#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) +#define PMC_LVDSC1_LVDF_MASK (0x80U) +#define PMC_LVDSC1_LVDF_SHIFT (7U) +#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) + +/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ +#define PMC_LVDSC2_LVWV_MASK (0x3U) +#define PMC_LVDSC2_LVWV_SHIFT (0U) +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) +#define PMC_LVDSC2_LVWIE_MASK (0x20U) +#define PMC_LVDSC2_LVWIE_SHIFT (5U) +#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) +#define PMC_LVDSC2_LVWACK_MASK (0x40U) +#define PMC_LVDSC2_LVWACK_SHIFT (6U) +#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) +#define PMC_LVDSC2_LVWF_MASK (0x80U) +#define PMC_LVDSC2_LVWF_SHIFT (7U) +#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) + +/*! @name REGSC - Regulator Status And Control register */ +#define PMC_REGSC_BGBE_MASK (0x1U) +#define PMC_REGSC_BGBE_SHIFT (0U) +#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) +#define PMC_REGSC_REGONS_MASK (0x4U) +#define PMC_REGSC_REGONS_SHIFT (2U) +#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) +#define PMC_REGSC_ACKISO_MASK (0x8U) +#define PMC_REGSC_ACKISO_SHIFT (3U) +#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) +#define PMC_REGSC_BGEN_MASK (0x10U) +#define PMC_REGSC_BGEN_SHIFT (4U) +#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +/** Peripheral PMC base address */ +#define PMC_BASE (0x4007D000u) +/** Peripheral PMC base pointer */ +#define PMC ((PMC_Type *)PMC_BASE) +/** Array initializer of PMC peripheral base addresses */ +#define PMC_BASE_ADDRS { PMC_BASE } +/** Array initializer of PMC peripheral base pointers */ +#define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { LVD_LVW_IRQn } + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ + __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ + __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ + uint8_t RESERVED_1[28]; + __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ + __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ + __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name PCR - Pin Control Register n */ +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) +#define PORT_PCR_SRE_MASK (0x4U) +#define PORT_PCR_SRE_SHIFT (2U) +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) +#define PORT_PCR_MUX_MASK (0x700U) +#define PORT_PCR_MUX_SHIFT (8U) +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +#define PORT_PCR_IRQC_MASK (0xF0000U) +#define PORT_PCR_IRQC_SHIFT (16U) +#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) +#define PORT_PCR_ISF_MASK (0x1000000U) +#define PORT_PCR_ISF_SHIFT (24U) +#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + +/*! @name GPCLR - Global Pin Control Low Register */ +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) +#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCLR_GPWE_SHIFT (16U) +#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) + +/*! @name GPCHR - Global Pin Control High Register */ +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) +#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCHR_GPWE_SHIFT (16U) +#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) + +/*! @name ISFR - Interrupt Status Flag Register */ +#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) +#define PORT_ISFR_ISF_SHIFT (0U) +#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) + +/*! @name DFER - Digital Filter Enable Register */ +#define PORT_DFER_DFE_MASK (0xFFFFFFFFU) +#define PORT_DFER_DFE_SHIFT (0U) +#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) + +/*! @name DFCR - Digital Filter Clock Register */ +#define PORT_DFCR_CS_MASK (0x1U) +#define PORT_DFCR_CS_SHIFT (0U) +#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) + +/*! @name DFWR - Digital Filter Width Register */ +#define PORT_DFWR_FILT_MASK (0x1FU) +#define PORT_DFWR_FILT_SHIFT (0U) +#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORTA base address */ +#define PORTA_BASE (0x40049000u) +/** Peripheral PORTA base pointer */ +#define PORTA ((PORT_Type *)PORTA_BASE) +/** Peripheral PORTB base address */ +#define PORTB_BASE (0x4004A000u) +/** Peripheral PORTB base pointer */ +#define PORTB ((PORT_Type *)PORTB_BASE) +/** Peripheral PORTC base address */ +#define PORTC_BASE (0x4004B000u) +/** Peripheral PORTC base pointer */ +#define PORTC ((PORT_Type *)PORTC_BASE) +/** Peripheral PORTD base address */ +#define PORTD_BASE (0x4004C000u) +/** Peripheral PORTD base pointer */ +#define PORTD ((PORT_Type *)PORTD_BASE) +/** Peripheral PORTE base address */ +#define PORTE_BASE (0x4004D000u) +/** Peripheral PORTE base pointer */ +#define PORTE ((PORT_Type *)PORTE_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer + * @{ + */ + +/** RCM - Register Layout Typedef */ +typedef struct { + __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ + __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ + uint8_t RESERVED_0[2]; + __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ + __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ + uint8_t RESERVED_1[1]; + __I uint8_t MR; /**< Mode Register, offset: 0x7 */ + __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ + __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ +} RCM_Type; + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/*! @name SRS0 - System Reset Status Register 0 */ +#define RCM_SRS0_WAKEUP_MASK (0x1U) +#define RCM_SRS0_WAKEUP_SHIFT (0U) +#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) +#define RCM_SRS0_LVD_MASK (0x2U) +#define RCM_SRS0_LVD_SHIFT (1U) +#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) +#define RCM_SRS0_LOC_MASK (0x4U) +#define RCM_SRS0_LOC_SHIFT (2U) +#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) +#define RCM_SRS0_LOL_MASK (0x8U) +#define RCM_SRS0_LOL_SHIFT (3U) +#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) +#define RCM_SRS0_WDOG_MASK (0x20U) +#define RCM_SRS0_WDOG_SHIFT (5U) +#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) +#define RCM_SRS0_PIN_MASK (0x40U) +#define RCM_SRS0_PIN_SHIFT (6U) +#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) +#define RCM_SRS0_POR_MASK (0x80U) +#define RCM_SRS0_POR_SHIFT (7U) +#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) + +/*! @name SRS1 - System Reset Status Register 1 */ +#define RCM_SRS1_JTAG_MASK (0x1U) +#define RCM_SRS1_JTAG_SHIFT (0U) +#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) +#define RCM_SRS1_LOCKUP_MASK (0x2U) +#define RCM_SRS1_LOCKUP_SHIFT (1U) +#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) +#define RCM_SRS1_SW_MASK (0x4U) +#define RCM_SRS1_SW_SHIFT (2U) +#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) +#define RCM_SRS1_MDM_AP_MASK (0x8U) +#define RCM_SRS1_MDM_AP_SHIFT (3U) +#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) +#define RCM_SRS1_EZPT_MASK (0x10U) +#define RCM_SRS1_EZPT_SHIFT (4U) +#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) +#define RCM_SRS1_SACKERR_MASK (0x20U) +#define RCM_SRS1_SACKERR_SHIFT (5U) +#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) + +/*! @name RPFC - Reset Pin Filter Control register */ +#define RCM_RPFC_RSTFLTSRW_MASK (0x3U) +#define RCM_RPFC_RSTFLTSRW_SHIFT (0U) +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) +#define RCM_RPFC_RSTFLTSS_MASK (0x4U) +#define RCM_RPFC_RSTFLTSS_SHIFT (2U) +#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) + +/*! @name RPFW - Reset Pin Filter Width register */ +#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) +#define RCM_RPFW_RSTFLTSEL_SHIFT (0U) +#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) + +/*! @name MR - Mode Register */ +#define RCM_MR_EZP_MS_MASK (0x2U) +#define RCM_MR_EZP_MS_SHIFT (1U) +#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) + +/*! @name SSRS0 - Sticky System Reset Status Register 0 */ +#define RCM_SSRS0_SWAKEUP_MASK (0x1U) +#define RCM_SSRS0_SWAKEUP_SHIFT (0U) +#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK) +#define RCM_SSRS0_SLVD_MASK (0x2U) +#define RCM_SSRS0_SLVD_SHIFT (1U) +#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK) +#define RCM_SSRS0_SLOC_MASK (0x4U) +#define RCM_SSRS0_SLOC_SHIFT (2U) +#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK) +#define RCM_SSRS0_SLOL_MASK (0x8U) +#define RCM_SSRS0_SLOL_SHIFT (3U) +#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK) +#define RCM_SSRS0_SWDOG_MASK (0x20U) +#define RCM_SSRS0_SWDOG_SHIFT (5U) +#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK) +#define RCM_SSRS0_SPIN_MASK (0x40U) +#define RCM_SSRS0_SPIN_SHIFT (6U) +#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK) +#define RCM_SSRS0_SPOR_MASK (0x80U) +#define RCM_SSRS0_SPOR_SHIFT (7U) +#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK) + +/*! @name SSRS1 - Sticky System Reset Status Register 1 */ +#define RCM_SSRS1_SJTAG_MASK (0x1U) +#define RCM_SSRS1_SJTAG_SHIFT (0U) +#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK) +#define RCM_SSRS1_SLOCKUP_MASK (0x2U) +#define RCM_SSRS1_SLOCKUP_SHIFT (1U) +#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK) +#define RCM_SSRS1_SSW_MASK (0x4U) +#define RCM_SSRS1_SSW_SHIFT (2U) +#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK) +#define RCM_SSRS1_SMDM_AP_MASK (0x8U) +#define RCM_SSRS1_SMDM_AP_SHIFT (3U) +#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK) +#define RCM_SSRS1_SEZPT_MASK (0x10U) +#define RCM_SSRS1_SEZPT_SHIFT (4U) +#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK) +#define RCM_SSRS1_SSACKERR_MASK (0x20U) +#define RCM_SSRS1_SSACKERR_SHIFT (5U) +#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK) + + +/*! + * @} + */ /* end of group RCM_Register_Masks */ + + +/* RCM - Peripheral instance base addresses */ +/** Peripheral RCM base address */ +#define RCM_BASE (0x4007F000u) +/** Peripheral RCM base pointer */ +#define RCM ((RCM_Type *)RCM_BASE) +/** Array initializer of RCM peripheral base addresses */ +#define RCM_BASE_ADDRS { RCM_BASE } +/** Array initializer of RCM peripheral base pointers */ +#define RCM_BASE_PTRS { RCM } + +/*! + * @} + */ /* end of group RCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer + * @{ + */ + +/** RFSYS - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ +} RFSYS_Type; + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/*! @name REG - Register file register */ +#define RFSYS_REG_LL_MASK (0xFFU) +#define RFSYS_REG_LL_SHIFT (0U) +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) +#define RFSYS_REG_LH_MASK (0xFF00U) +#define RFSYS_REG_LH_SHIFT (8U) +#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) +#define RFSYS_REG_HL_MASK (0xFF0000U) +#define RFSYS_REG_HL_SHIFT (16U) +#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) +#define RFSYS_REG_HH_MASK (0xFF000000U) +#define RFSYS_REG_HH_SHIFT (24U) +#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) + +/* The count of RFSYS_REG */ +#define RFSYS_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFSYS_Register_Masks */ + + +/* RFSYS - Peripheral instance base addresses */ +/** Peripheral RFSYS base address */ +#define RFSYS_BASE (0x40041000u) +/** Peripheral RFSYS base pointer */ +#define RFSYS ((RFSYS_Type *)RFSYS_BASE) +/** Array initializer of RFSYS peripheral base addresses */ +#define RFSYS_BASE_ADDRS { RFSYS_BASE } +/** Array initializer of RFSYS peripheral base pointers */ +#define RFSYS_BASE_PTRS { RFSYS } + +/*! + * @} + */ /* end of group RFSYS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer + * @{ + */ + +/** RFVBAT - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ +} RFVBAT_Type; + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/*! @name REG - VBAT register file register */ +#define RFVBAT_REG_LL_MASK (0xFFU) +#define RFVBAT_REG_LL_SHIFT (0U) +#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) +#define RFVBAT_REG_LH_MASK (0xFF00U) +#define RFVBAT_REG_LH_SHIFT (8U) +#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) +#define RFVBAT_REG_HL_MASK (0xFF0000U) +#define RFVBAT_REG_HL_SHIFT (16U) +#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) +#define RFVBAT_REG_HH_MASK (0xFF000000U) +#define RFVBAT_REG_HH_SHIFT (24U) +#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) + +/* The count of RFVBAT_REG */ +#define RFVBAT_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFVBAT_Register_Masks */ + + +/* RFVBAT - Peripheral instance base addresses */ +/** Peripheral RFVBAT base address */ +#define RFVBAT_BASE (0x4003E000u) +/** Peripheral RFVBAT base pointer */ +#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) +/** Array initializer of RFVBAT peripheral base addresses */ +#define RFVBAT_BASE_ADDRS { RFVBAT_BASE } +/** Array initializer of RFVBAT peripheral base pointers */ +#define RFVBAT_BASE_PTRS { RFVBAT } + +/*! + * @} + */ /* end of group RFVBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ + __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ + __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ + __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name CR - RNGA Control Register */ +#define RNG_CR_GO_MASK (0x1U) +#define RNG_CR_GO_SHIFT (0U) +#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) +#define RNG_CR_HA_MASK (0x2U) +#define RNG_CR_HA_SHIFT (1U) +#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) +#define RNG_CR_INTM_MASK (0x4U) +#define RNG_CR_INTM_SHIFT (2U) +#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) +#define RNG_CR_CLRI_MASK (0x8U) +#define RNG_CR_CLRI_SHIFT (3U) +#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) +#define RNG_CR_SLP_MASK (0x10U) +#define RNG_CR_SLP_SHIFT (4U) +#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) + +/*! @name SR - RNGA Status Register */ +#define RNG_SR_SECV_MASK (0x1U) +#define RNG_SR_SECV_SHIFT (0U) +#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) +#define RNG_SR_LRS_MASK (0x2U) +#define RNG_SR_LRS_SHIFT (1U) +#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) +#define RNG_SR_ORU_MASK (0x4U) +#define RNG_SR_ORU_SHIFT (2U) +#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) +#define RNG_SR_ERRI_MASK (0x8U) +#define RNG_SR_ERRI_SHIFT (3U) +#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) +#define RNG_SR_SLP_MASK (0x10U) +#define RNG_SR_SLP_SHIFT (4U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_OREG_LVL_MASK (0xFF00U) +#define RNG_SR_OREG_LVL_SHIFT (8U) +#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) +#define RNG_SR_OREG_SIZE_MASK (0xFF0000U) +#define RNG_SR_OREG_SIZE_SHIFT (16U) +#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) + +/*! @name ER - RNGA Entropy Register */ +#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) +#define RNG_ER_EXT_ENT_SHIFT (0U) +#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) + +/*! @name OR - RNGA Output Register */ +#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OR_RANDOUT_SHIFT (0U) +#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x40029000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } +/** Interrupt vectors for the RNG peripheral type */ +#define RNG_IRQS { RNG_IRQn } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ + uint8_t RESERVED_0[2016]; + __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ + __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name TSR - RTC Time Seconds Register */ +#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) +#define RTC_TSR_TSR_SHIFT (0U) +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) + +/*! @name TPR - RTC Time Prescaler Register */ +#define RTC_TPR_TPR_MASK (0xFFFFU) +#define RTC_TPR_TPR_SHIFT (0U) +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) + +/*! @name TAR - RTC Time Alarm Register */ +#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) +#define RTC_TAR_TAR_SHIFT (0U) +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) + +/*! @name TCR - RTC Time Compensation Register */ +#define RTC_TCR_TCR_MASK (0xFFU) +#define RTC_TCR_TCR_SHIFT (0U) +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) +#define RTC_TCR_CIR_MASK (0xFF00U) +#define RTC_TCR_CIR_SHIFT (8U) +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) +#define RTC_TCR_TCV_MASK (0xFF0000U) +#define RTC_TCR_TCV_SHIFT (16U) +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) +#define RTC_TCR_CIC_MASK (0xFF000000U) +#define RTC_TCR_CIC_SHIFT (24U) +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) + +/*! @name CR - RTC Control Register */ +#define RTC_CR_SWR_MASK (0x1U) +#define RTC_CR_SWR_SHIFT (0U) +#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) +#define RTC_CR_WPE_MASK (0x2U) +#define RTC_CR_WPE_SHIFT (1U) +#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) +#define RTC_CR_SUP_MASK (0x4U) +#define RTC_CR_SUP_SHIFT (2U) +#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) +#define RTC_CR_UM_MASK (0x8U) +#define RTC_CR_UM_SHIFT (3U) +#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) +#define RTC_CR_WPS_MASK (0x10U) +#define RTC_CR_WPS_SHIFT (4U) +#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) +#define RTC_CR_OSCE_MASK (0x100U) +#define RTC_CR_OSCE_SHIFT (8U) +#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) +#define RTC_CR_CLKO_MASK (0x200U) +#define RTC_CR_CLKO_SHIFT (9U) +#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) +#define RTC_CR_SC16P_MASK (0x400U) +#define RTC_CR_SC16P_SHIFT (10U) +#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) +#define RTC_CR_SC8P_MASK (0x800U) +#define RTC_CR_SC8P_SHIFT (11U) +#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) +#define RTC_CR_SC4P_MASK (0x1000U) +#define RTC_CR_SC4P_SHIFT (12U) +#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) +#define RTC_CR_SC2P_MASK (0x2000U) +#define RTC_CR_SC2P_SHIFT (13U) +#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) + +/*! @name SR - RTC Status Register */ +#define RTC_SR_TIF_MASK (0x1U) +#define RTC_SR_TIF_SHIFT (0U) +#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) +#define RTC_SR_TOF_MASK (0x2U) +#define RTC_SR_TOF_SHIFT (1U) +#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) +#define RTC_SR_TAF_MASK (0x4U) +#define RTC_SR_TAF_SHIFT (2U) +#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) +#define RTC_SR_TCE_MASK (0x10U) +#define RTC_SR_TCE_SHIFT (4U) +#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) + +/*! @name LR - RTC Lock Register */ +#define RTC_LR_TCL_MASK (0x8U) +#define RTC_LR_TCL_SHIFT (3U) +#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) +#define RTC_LR_CRL_MASK (0x10U) +#define RTC_LR_CRL_SHIFT (4U) +#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) +#define RTC_LR_SRL_MASK (0x20U) +#define RTC_LR_SRL_SHIFT (5U) +#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) +#define RTC_LR_LRL_MASK (0x40U) +#define RTC_LR_LRL_SHIFT (6U) +#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) + +/*! @name IER - RTC Interrupt Enable Register */ +#define RTC_IER_TIIE_MASK (0x1U) +#define RTC_IER_TIIE_SHIFT (0U) +#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) +#define RTC_IER_TOIE_MASK (0x2U) +#define RTC_IER_TOIE_SHIFT (1U) +#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) +#define RTC_IER_TAIE_MASK (0x4U) +#define RTC_IER_TAIE_SHIFT (2U) +#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) +#define RTC_IER_TSIE_MASK (0x10U) +#define RTC_IER_TSIE_SHIFT (4U) +#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) +#define RTC_IER_WPON_MASK (0x80U) +#define RTC_IER_WPON_SHIFT (7U) +#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) + +/*! @name WAR - RTC Write Access Register */ +#define RTC_WAR_TSRW_MASK (0x1U) +#define RTC_WAR_TSRW_SHIFT (0U) +#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) +#define RTC_WAR_TPRW_MASK (0x2U) +#define RTC_WAR_TPRW_SHIFT (1U) +#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) +#define RTC_WAR_TARW_MASK (0x4U) +#define RTC_WAR_TARW_SHIFT (2U) +#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) +#define RTC_WAR_TCRW_MASK (0x8U) +#define RTC_WAR_TCRW_SHIFT (3U) +#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) +#define RTC_WAR_CRW_MASK (0x10U) +#define RTC_WAR_CRW_SHIFT (4U) +#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) +#define RTC_WAR_SRW_MASK (0x20U) +#define RTC_WAR_SRW_SHIFT (5U) +#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) +#define RTC_WAR_LRW_MASK (0x40U) +#define RTC_WAR_LRW_SHIFT (6U) +#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) +#define RTC_WAR_IERW_MASK (0x80U) +#define RTC_WAR_IERW_SHIFT (7U) +#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) + +/*! @name RAR - RTC Read Access Register */ +#define RTC_RAR_TSRR_MASK (0x1U) +#define RTC_RAR_TSRR_SHIFT (0U) +#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) +#define RTC_RAR_TPRR_MASK (0x2U) +#define RTC_RAR_TPRR_SHIFT (1U) +#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) +#define RTC_RAR_TARR_MASK (0x4U) +#define RTC_RAR_TARR_SHIFT (2U) +#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) +#define RTC_RAR_TCRR_MASK (0x8U) +#define RTC_RAR_TCRR_SHIFT (3U) +#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) +#define RTC_RAR_CRR_MASK (0x10U) +#define RTC_RAR_CRR_SHIFT (4U) +#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) +#define RTC_RAR_SRR_MASK (0x20U) +#define RTC_RAR_SRR_SHIFT (5U) +#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) +#define RTC_RAR_LRR_MASK (0x40U) +#define RTC_RAR_LRR_SHIFT (6U) +#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) +#define RTC_RAR_IERR_MASK (0x80U) +#define RTC_RAR_IERR_SHIFT (7U) +#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4003D000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ + __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ + uint8_t RESERVED_0[4092]; + __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ + __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ + __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */ + uint8_t RESERVED_3[4]; + __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ + __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ + __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ + __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ + __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ + __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ + __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ + __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ + __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ + __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ + __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ + __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ +} SIM_Type; + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/*! @name SOPT1 - System Options Register 1 */ +#define SIM_SOPT1_RAMSIZE_MASK (0xF000U) +#define SIM_SOPT1_RAMSIZE_SHIFT (12U) +#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) +#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U) +#define SIM_SOPT1_OSC32KOUT_SHIFT (16U) +#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK) +#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) +#define SIM_SOPT1_OSC32KSEL_SHIFT (18U) +#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) +#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) +#define SIM_SOPT1_USBVSTBY_SHIFT (29U) +#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) +#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) +#define SIM_SOPT1_USBSSTBY_SHIFT (30U) +#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) +#define SIM_SOPT1_USBREGEN_MASK (0x80000000U) +#define SIM_SOPT1_USBREGEN_SHIFT (31U) +#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) + +/*! @name SOPT1CFG - SOPT1 Configuration Register */ +#define SIM_SOPT1CFG_URWE_MASK (0x1000000U) +#define SIM_SOPT1CFG_URWE_SHIFT (24U) +#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) +#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) +#define SIM_SOPT1CFG_UVSWE_SHIFT (25U) +#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) +#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) +#define SIM_SOPT1CFG_USSWE_SHIFT (26U) +#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) + +/*! @name SOPT2 - System Options Register 2 */ +#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) +#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) +#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) +#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) +#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) +#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) +#define SIM_SOPT2_FBSL_MASK (0x300U) +#define SIM_SOPT2_FBSL_SHIFT (8U) +#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK) +#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) +#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) +#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) +#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) +#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) +#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) +#define SIM_SOPT2_USBSRC_MASK (0x40000U) +#define SIM_SOPT2_USBSRC_SHIFT (18U) +#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) +#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U) +#define SIM_SOPT2_LPUARTSRC_SHIFT (26U) +#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK) + +/*! @name SOPT4 - System Options Register 4 */ +#define SIM_SOPT4_FTM0FLT0_MASK (0x1U) +#define SIM_SOPT4_FTM0FLT0_SHIFT (0U) +#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) +#define SIM_SOPT4_FTM0FLT1_MASK (0x2U) +#define SIM_SOPT4_FTM0FLT1_SHIFT (1U) +#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) +#define SIM_SOPT4_FTM1FLT0_MASK (0x10U) +#define SIM_SOPT4_FTM1FLT0_SHIFT (4U) +#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) +#define SIM_SOPT4_FTM2FLT0_MASK (0x100U) +#define SIM_SOPT4_FTM2FLT0_SHIFT (8U) +#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) +#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U) +#define SIM_SOPT4_FTM3FLT0_SHIFT (12U) +#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK) +#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) +#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) +#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) +#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) +#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) +#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) +#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U) +#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U) +#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK) +#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) +#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) +#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) +#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) +#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) +#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) +#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) +#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) +#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) +#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U) +#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U) +#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK) +#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) +#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) +#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) +#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) +#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) +#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) +#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U) +#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U) +#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK) +#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U) +#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U) +#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK) + +/*! @name SOPT5 - System Options Register 5 */ +#define SIM_SOPT5_UART0TXSRC_MASK (0x3U) +#define SIM_SOPT5_UART0TXSRC_SHIFT (0U) +#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) +#define SIM_SOPT5_UART0RXSRC_MASK (0xCU) +#define SIM_SOPT5_UART0RXSRC_SHIFT (2U) +#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) +#define SIM_SOPT5_UART1TXSRC_MASK (0x30U) +#define SIM_SOPT5_UART1TXSRC_SHIFT (4U) +#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) +#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) +#define SIM_SOPT5_UART1RXSRC_SHIFT (6U) +#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) +#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U) +#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U) +#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) + +/*! @name SOPT7 - System Options Register 7 */ +#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) +#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) +#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) +#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) +#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) +#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) +#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) +#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) +#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) +#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U) +#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U) +#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK) +#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U) +#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U) +#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK) +#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U) +#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U) +#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK) + +/*! @name SOPT8 - System Options Register 8 */ +#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U) +#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U) +#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK) +#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U) +#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U) +#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK) +#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U) +#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U) +#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK) +#define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U) +#define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U) +#define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK) +#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U) +#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U) +#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK) +#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U) +#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U) +#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK) +#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U) +#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U) +#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK) +#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U) +#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U) +#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK) +#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U) +#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U) +#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK) +#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U) +#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U) +#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK) +#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U) +#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U) +#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK) +#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U) +#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U) +#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK) +#define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U) +#define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U) +#define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK) +#define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U) +#define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U) +#define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK) +#define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U) +#define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U) +#define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK) +#define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U) +#define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U) +#define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK) +#define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U) +#define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U) +#define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK) +#define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U) +#define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U) +#define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK) +#define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U) +#define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U) +#define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK) +#define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U) +#define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U) +#define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK) + +/*! @name SDID - System Device Identification Register */ +#define SIM_SDID_PINID_MASK (0xFU) +#define SIM_SDID_PINID_SHIFT (0U) +#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) +#define SIM_SDID_FAMID_MASK (0x70U) +#define SIM_SDID_FAMID_SHIFT (4U) +#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) +#define SIM_SDID_DIEID_MASK (0xF80U) +#define SIM_SDID_DIEID_SHIFT (7U) +#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) +#define SIM_SDID_REVID_MASK (0xF000U) +#define SIM_SDID_REVID_SHIFT (12U) +#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) +#define SIM_SDID_SERIESID_MASK (0xF00000U) +#define SIM_SDID_SERIESID_SHIFT (20U) +#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) +#define SIM_SDID_SUBFAMID_MASK (0xF000000U) +#define SIM_SDID_SUBFAMID_SHIFT (24U) +#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) +#define SIM_SDID_FAMILYID_MASK (0xF0000000U) +#define SIM_SDID_FAMILYID_SHIFT (28U) +#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) + +/*! @name SCGC4 - System Clock Gating Control Register 4 */ +#define SIM_SCGC4_EWM_MASK (0x2U) +#define SIM_SCGC4_EWM_SHIFT (1U) +#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) +#define SIM_SCGC4_I2C0_MASK (0x40U) +#define SIM_SCGC4_I2C0_SHIFT (6U) +#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) +#define SIM_SCGC4_I2C1_MASK (0x80U) +#define SIM_SCGC4_I2C1_SHIFT (7U) +#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) +#define SIM_SCGC4_UART0_MASK (0x400U) +#define SIM_SCGC4_UART0_SHIFT (10U) +#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) +#define SIM_SCGC4_UART1_MASK (0x800U) +#define SIM_SCGC4_UART1_SHIFT (11U) +#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) +#define SIM_SCGC4_UART2_MASK (0x1000U) +#define SIM_SCGC4_UART2_SHIFT (12U) +#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) +#define SIM_SCGC4_USBOTG_MASK (0x40000U) +#define SIM_SCGC4_USBOTG_SHIFT (18U) +#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) +#define SIM_SCGC4_CMP_MASK (0x80000U) +#define SIM_SCGC4_CMP_SHIFT (19U) +#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) +#define SIM_SCGC4_VREF_MASK (0x100000U) +#define SIM_SCGC4_VREF_SHIFT (20U) +#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) + +/*! @name SCGC5 - System Clock Gating Control Register 5 */ +#define SIM_SCGC5_LPTMR_MASK (0x1U) +#define SIM_SCGC5_LPTMR_SHIFT (0U) +#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) +#define SIM_SCGC5_PORTA_MASK (0x200U) +#define SIM_SCGC5_PORTA_SHIFT (9U) +#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) +#define SIM_SCGC5_PORTB_MASK (0x400U) +#define SIM_SCGC5_PORTB_SHIFT (10U) +#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) +#define SIM_SCGC5_PORTC_MASK (0x800U) +#define SIM_SCGC5_PORTC_SHIFT (11U) +#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) +#define SIM_SCGC5_PORTD_MASK (0x1000U) +#define SIM_SCGC5_PORTD_SHIFT (12U) +#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) +#define SIM_SCGC5_PORTE_MASK (0x2000U) +#define SIM_SCGC5_PORTE_SHIFT (13U) +#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) + +/*! @name SCGC6 - System Clock Gating Control Register 6 */ +#define SIM_SCGC6_FTF_MASK (0x1U) +#define SIM_SCGC6_FTF_SHIFT (0U) +#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) +#define SIM_SCGC6_DMAMUX_MASK (0x2U) +#define SIM_SCGC6_DMAMUX_SHIFT (1U) +#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) +#define SIM_SCGC6_FTM3_MASK (0x40U) +#define SIM_SCGC6_FTM3_SHIFT (6U) +#define SIM_SCGC6_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM3_SHIFT)) & SIM_SCGC6_FTM3_MASK) +#define SIM_SCGC6_ADC1_MASK (0x80U) +#define SIM_SCGC6_ADC1_SHIFT (7U) +#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK) +#define SIM_SCGC6_DAC1_MASK (0x100U) +#define SIM_SCGC6_DAC1_SHIFT (8U) +#define SIM_SCGC6_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC1_SHIFT)) & SIM_SCGC6_DAC1_MASK) +#define SIM_SCGC6_RNGA_MASK (0x200U) +#define SIM_SCGC6_RNGA_SHIFT (9U) +#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) +#define SIM_SCGC6_LPUART0_MASK (0x400U) +#define SIM_SCGC6_LPUART0_SHIFT (10U) +#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPUART0_SHIFT)) & SIM_SCGC6_LPUART0_MASK) +#define SIM_SCGC6_SPI0_MASK (0x1000U) +#define SIM_SCGC6_SPI0_SHIFT (12U) +#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) +#define SIM_SCGC6_SPI1_MASK (0x2000U) +#define SIM_SCGC6_SPI1_SHIFT (13U) +#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) +#define SIM_SCGC6_I2S_MASK (0x8000U) +#define SIM_SCGC6_I2S_SHIFT (15U) +#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) +#define SIM_SCGC6_CRC_MASK (0x40000U) +#define SIM_SCGC6_CRC_SHIFT (18U) +#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) +#define SIM_SCGC6_PDB_MASK (0x400000U) +#define SIM_SCGC6_PDB_SHIFT (22U) +#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) +#define SIM_SCGC6_PIT_MASK (0x800000U) +#define SIM_SCGC6_PIT_SHIFT (23U) +#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) +#define SIM_SCGC6_FTM0_MASK (0x1000000U) +#define SIM_SCGC6_FTM0_SHIFT (24U) +#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) +#define SIM_SCGC6_FTM1_MASK (0x2000000U) +#define SIM_SCGC6_FTM1_SHIFT (25U) +#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) +#define SIM_SCGC6_FTM2_MASK (0x4000000U) +#define SIM_SCGC6_FTM2_SHIFT (26U) +#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) +#define SIM_SCGC6_ADC0_MASK (0x8000000U) +#define SIM_SCGC6_ADC0_SHIFT (27U) +#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) +#define SIM_SCGC6_RTC_MASK (0x20000000U) +#define SIM_SCGC6_RTC_SHIFT (29U) +#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) +#define SIM_SCGC6_DAC0_MASK (0x80000000U) +#define SIM_SCGC6_DAC0_SHIFT (31U) +#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) + +/*! @name SCGC7 - System Clock Gating Control Register 7 */ +#define SIM_SCGC7_FLEXBUS_MASK (0x1U) +#define SIM_SCGC7_FLEXBUS_SHIFT (0U) +#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK) +#define SIM_SCGC7_DMA_MASK (0x2U) +#define SIM_SCGC7_DMA_SHIFT (1U) +#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) + +/*! @name CLKDIV1 - System Clock Divider Register 1 */ +#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) +#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) +#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) +#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U) +#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U) +#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK) +#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) +#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) +#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) +#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) +#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) +#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) + +/*! @name CLKDIV2 - System Clock Divider Register 2 */ +#define SIM_CLKDIV2_USBFRAC_MASK (0x1U) +#define SIM_CLKDIV2_USBFRAC_SHIFT (0U) +#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) +#define SIM_CLKDIV2_USBDIV_MASK (0xEU) +#define SIM_CLKDIV2_USBDIV_SHIFT (1U) +#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) + +/*! @name FCFG1 - Flash Configuration Register 1 */ +#define SIM_FCFG1_FLASHDIS_MASK (0x1U) +#define SIM_FCFG1_FLASHDIS_SHIFT (0U) +#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) +#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) +#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) +#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) +#define SIM_FCFG1_PFSIZE_MASK (0xF000000U) +#define SIM_FCFG1_PFSIZE_SHIFT (24U) +#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) + +/*! @name FCFG2 - Flash Configuration Register 2 */ +#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) +#define SIM_FCFG2_MAXADDR1_SHIFT (16U) +#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) +#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) +#define SIM_FCFG2_MAXADDR0_SHIFT (24U) +#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) + +/*! @name UIDH - Unique Identification Register High */ +#define SIM_UIDH_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDH_UID_SHIFT (0U) +#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) + +/*! @name UIDMH - Unique Identification Register Mid-High */ +#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDMH_UID_SHIFT (0U) +#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) + +/*! @name UIDML - Unique Identification Register Mid Low */ +#define SIM_UIDML_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDML_UID_SHIFT (0U) +#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) + +/*! @name UIDL - Unique Identification Register Low */ +#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDL_UID_SHIFT (0U) +#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) + + +/*! + * @} + */ /* end of group SIM_Register_Masks */ + + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM base address */ +#define SIM_BASE (0x40047000u) +/** Peripheral SIM base pointer */ +#define SIM ((SIM_Type *)SIM_BASE) +/** Array initializer of SIM peripheral base addresses */ +#define SIM_BASE_ADDRS { SIM_BASE } +/** Array initializer of SIM peripheral base pointers */ +#define SIM_BASE_PTRS { SIM } + +/*! + * @} + */ /* end of group SIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer + * @{ + */ + +/** SMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ + __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ + __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ + __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ +} SMC_Type; + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/*! @name PMPROT - Power Mode Protection register */ +#define SMC_PMPROT_AVLLS_MASK (0x2U) +#define SMC_PMPROT_AVLLS_SHIFT (1U) +#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) +#define SMC_PMPROT_ALLS_MASK (0x8U) +#define SMC_PMPROT_ALLS_SHIFT (3U) +#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) +#define SMC_PMPROT_AVLP_MASK (0x20U) +#define SMC_PMPROT_AVLP_SHIFT (5U) +#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) +#define SMC_PMPROT_AHSRUN_MASK (0x80U) +#define SMC_PMPROT_AHSRUN_SHIFT (7U) +#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) + +/*! @name PMCTRL - Power Mode Control register */ +#define SMC_PMCTRL_STOPM_MASK (0x7U) +#define SMC_PMCTRL_STOPM_SHIFT (0U) +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) +#define SMC_PMCTRL_STOPA_MASK (0x8U) +#define SMC_PMCTRL_STOPA_SHIFT (3U) +#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) +#define SMC_PMCTRL_RUNM_MASK (0x60U) +#define SMC_PMCTRL_RUNM_SHIFT (5U) +#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) + +/*! @name STOPCTRL - Stop Control Register */ +#define SMC_STOPCTRL_LLSM_MASK (0x7U) +#define SMC_STOPCTRL_LLSM_SHIFT (0U) +#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK) +#define SMC_STOPCTRL_PORPO_MASK (0x20U) +#define SMC_STOPCTRL_PORPO_SHIFT (5U) +#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) +#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) +#define SMC_STOPCTRL_PSTOPO_SHIFT (6U) +#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) + +/*! @name PMSTAT - Power Mode Status register */ +#define SMC_PMSTAT_PMSTAT_MASK (0xFFU) +#define SMC_PMSTAT_PMSTAT_SHIFT (0U) +#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) + + +/*! + * @} + */ /* end of group SMC_Register_Masks */ + + +/* SMC - Peripheral instance base addresses */ +/** Peripheral SMC base address */ +#define SMC_BASE (0x4007E000u) +/** Peripheral SMC base pointer */ +#define SMC ((SMC_Type *)SMC_BASE) +/** Array initializer of SMC peripheral base addresses */ +#define SMC_BASE_ADDRS { SMC_BASE } +/** Array initializer of SMC peripheral base pointers */ +#define SMC_BASE_PTRS { SMC } + +/*! + * @} + */ /* end of group SMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint8_t RESERVED_1[24]; + __IO uint32_t SR; /**< Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ + __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ + __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ + __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ + uint8_t RESERVED_2[48]; + __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ + __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ + __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ + __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define SPI_MCR_HALT_MASK (0x1U) +#define SPI_MCR_HALT_SHIFT (0U) +#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) +#define SPI_MCR_SMPL_PT_MASK (0x300U) +#define SPI_MCR_SMPL_PT_SHIFT (8U) +#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) +#define SPI_MCR_CLR_RXF_MASK (0x400U) +#define SPI_MCR_CLR_RXF_SHIFT (10U) +#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) +#define SPI_MCR_CLR_TXF_MASK (0x800U) +#define SPI_MCR_CLR_TXF_SHIFT (11U) +#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) +#define SPI_MCR_DIS_RXF_MASK (0x1000U) +#define SPI_MCR_DIS_RXF_SHIFT (12U) +#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) +#define SPI_MCR_DIS_TXF_MASK (0x2000U) +#define SPI_MCR_DIS_TXF_SHIFT (13U) +#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) +#define SPI_MCR_MDIS_MASK (0x4000U) +#define SPI_MCR_MDIS_SHIFT (14U) +#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) +#define SPI_MCR_DOZE_MASK (0x8000U) +#define SPI_MCR_DOZE_SHIFT (15U) +#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) +#define SPI_MCR_PCSIS_MASK (0x3F0000U) +#define SPI_MCR_PCSIS_SHIFT (16U) +#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) +#define SPI_MCR_ROOE_MASK (0x1000000U) +#define SPI_MCR_ROOE_SHIFT (24U) +#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) +#define SPI_MCR_PCSSE_MASK (0x2000000U) +#define SPI_MCR_PCSSE_SHIFT (25U) +#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) +#define SPI_MCR_MTFE_MASK (0x4000000U) +#define SPI_MCR_MTFE_SHIFT (26U) +#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) +#define SPI_MCR_FRZ_MASK (0x8000000U) +#define SPI_MCR_FRZ_SHIFT (27U) +#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) +#define SPI_MCR_DCONF_MASK (0x30000000U) +#define SPI_MCR_DCONF_SHIFT (28U) +#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) +#define SPI_MCR_CONT_SCKE_MASK (0x40000000U) +#define SPI_MCR_CONT_SCKE_SHIFT (30U) +#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) +#define SPI_MCR_MSTR_MASK (0x80000000U) +#define SPI_MCR_MSTR_SHIFT (31U) +#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) + +/*! @name TCR - Transfer Count Register */ +#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) +#define SPI_TCR_SPI_TCNT_SHIFT (16U) +#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) + +/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ +#define SPI_CTAR_BR_MASK (0xFU) +#define SPI_CTAR_BR_SHIFT (0U) +#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) +#define SPI_CTAR_DT_MASK (0xF0U) +#define SPI_CTAR_DT_SHIFT (4U) +#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) +#define SPI_CTAR_ASC_MASK (0xF00U) +#define SPI_CTAR_ASC_SHIFT (8U) +#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) +#define SPI_CTAR_CSSCK_MASK (0xF000U) +#define SPI_CTAR_CSSCK_SHIFT (12U) +#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) +#define SPI_CTAR_PBR_MASK (0x30000U) +#define SPI_CTAR_PBR_SHIFT (16U) +#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) +#define SPI_CTAR_PDT_MASK (0xC0000U) +#define SPI_CTAR_PDT_SHIFT (18U) +#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) +#define SPI_CTAR_PASC_MASK (0x300000U) +#define SPI_CTAR_PASC_SHIFT (20U) +#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) +#define SPI_CTAR_PCSSCK_MASK (0xC00000U) +#define SPI_CTAR_PCSSCK_SHIFT (22U) +#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) +#define SPI_CTAR_LSBFE_MASK (0x1000000U) +#define SPI_CTAR_LSBFE_SHIFT (24U) +#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) +#define SPI_CTAR_CPHA_MASK (0x2000000U) +#define SPI_CTAR_CPHA_SHIFT (25U) +#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) +#define SPI_CTAR_CPOL_MASK (0x4000000U) +#define SPI_CTAR_CPOL_SHIFT (26U) +#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) +#define SPI_CTAR_FMSZ_MASK (0x78000000U) +#define SPI_CTAR_FMSZ_SHIFT (27U) +#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) +#define SPI_CTAR_DBR_MASK (0x80000000U) +#define SPI_CTAR_DBR_SHIFT (31U) +#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) + +/* The count of SPI_CTAR */ +#define SPI_CTAR_COUNT (2U) + +/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ +#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) +#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) +#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) +#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) +#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) +#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) +#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) +#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) +#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) + +/* The count of SPI_CTAR_SLAVE */ +#define SPI_CTAR_SLAVE_COUNT (1U) + +/*! @name SR - Status Register */ +#define SPI_SR_POPNXTPTR_MASK (0xFU) +#define SPI_SR_POPNXTPTR_SHIFT (0U) +#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) +#define SPI_SR_RXCTR_MASK (0xF0U) +#define SPI_SR_RXCTR_SHIFT (4U) +#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) +#define SPI_SR_TXNXTPTR_MASK (0xF00U) +#define SPI_SR_TXNXTPTR_SHIFT (8U) +#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) +#define SPI_SR_TXCTR_MASK (0xF000U) +#define SPI_SR_TXCTR_SHIFT (12U) +#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) +#define SPI_SR_RFDF_MASK (0x20000U) +#define SPI_SR_RFDF_SHIFT (17U) +#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) +#define SPI_SR_RFOF_MASK (0x80000U) +#define SPI_SR_RFOF_SHIFT (19U) +#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) +#define SPI_SR_TFFF_MASK (0x2000000U) +#define SPI_SR_TFFF_SHIFT (25U) +#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) +#define SPI_SR_TFUF_MASK (0x8000000U) +#define SPI_SR_TFUF_SHIFT (27U) +#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) +#define SPI_SR_EOQF_MASK (0x10000000U) +#define SPI_SR_EOQF_SHIFT (28U) +#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) +#define SPI_SR_TXRXS_MASK (0x40000000U) +#define SPI_SR_TXRXS_SHIFT (30U) +#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) +#define SPI_SR_TCF_MASK (0x80000000U) +#define SPI_SR_TCF_SHIFT (31U) +#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) + +/*! @name RSER - DMA/Interrupt Request Select and Enable Register */ +#define SPI_RSER_RFDF_DIRS_MASK (0x10000U) +#define SPI_RSER_RFDF_DIRS_SHIFT (16U) +#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) +#define SPI_RSER_RFDF_RE_MASK (0x20000U) +#define SPI_RSER_RFDF_RE_SHIFT (17U) +#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) +#define SPI_RSER_RFOF_RE_MASK (0x80000U) +#define SPI_RSER_RFOF_RE_SHIFT (19U) +#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) +#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) +#define SPI_RSER_TFFF_DIRS_SHIFT (24U) +#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) +#define SPI_RSER_TFFF_RE_MASK (0x2000000U) +#define SPI_RSER_TFFF_RE_SHIFT (25U) +#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) +#define SPI_RSER_TFUF_RE_MASK (0x8000000U) +#define SPI_RSER_TFUF_RE_SHIFT (27U) +#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) +#define SPI_RSER_EOQF_RE_MASK (0x10000000U) +#define SPI_RSER_EOQF_RE_SHIFT (28U) +#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) +#define SPI_RSER_TCF_RE_MASK (0x80000000U) +#define SPI_RSER_TCF_RE_SHIFT (31U) +#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) + +/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ +#define SPI_PUSHR_TXDATA_MASK (0xFFFFU) +#define SPI_PUSHR_TXDATA_SHIFT (0U) +#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) +#define SPI_PUSHR_PCS_MASK (0x3F0000U) +#define SPI_PUSHR_PCS_SHIFT (16U) +#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) +#define SPI_PUSHR_CTCNT_MASK (0x4000000U) +#define SPI_PUSHR_CTCNT_SHIFT (26U) +#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) +#define SPI_PUSHR_EOQ_MASK (0x8000000U) +#define SPI_PUSHR_EOQ_SHIFT (27U) +#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) +#define SPI_PUSHR_CTAS_MASK (0x70000000U) +#define SPI_PUSHR_CTAS_SHIFT (28U) +#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) +#define SPI_PUSHR_CONT_MASK (0x80000000U) +#define SPI_PUSHR_CONT_SHIFT (31U) +#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) + +/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ +#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) +#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) +#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) + +/*! @name POPR - POP RX FIFO Register */ +#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_POPR_RXDATA_SHIFT (0U) +#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) + +/*! @name TXFR0 - Transmit FIFO Registers */ +#define SPI_TXFR0_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR0_TXDATA_SHIFT (0U) +#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) +#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) + +/*! @name TXFR1 - Transmit FIFO Registers */ +#define SPI_TXFR1_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR1_TXDATA_SHIFT (0U) +#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) +#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) + +/*! @name TXFR2 - Transmit FIFO Registers */ +#define SPI_TXFR2_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR2_TXDATA_SHIFT (0U) +#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) +#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) + +/*! @name TXFR3 - Transmit FIFO Registers */ +#define SPI_TXFR3_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR3_TXDATA_SHIFT (0U) +#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) +#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) + +/*! @name RXFR0 - Receive FIFO Registers */ +#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR0_RXDATA_SHIFT (0U) +#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) + +/*! @name RXFR1 - Receive FIFO Registers */ +#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR1_RXDATA_SHIFT (0U) +#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) + +/*! @name RXFR2 - Receive FIFO Registers */ +#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR2_RXDATA_SHIFT (0U) +#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) + +/*! @name RXFR3 - Receive FIFO Registers */ +#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR3_RXDATA_SHIFT (0U) +#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x4002C000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x4002D000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ + __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ + __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ + __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ + __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ + __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ + __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ + __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ + __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ + __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ + __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ + __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ + __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ + __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ + __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ + uint8_t RESERVED_0[1]; + __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ + __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ + __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ + __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ + __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ + __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ + __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ + uint8_t RESERVED_1[1]; + __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ + __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ + __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ + __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ + __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ + __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ + __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ + uint8_t RESERVED_2[26]; + __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */ + __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */ + union { /* offset: 0x3C */ + struct { /* offset: 0x3C */ + __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ + __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ + } TYPE0; + struct { /* offset: 0x3C */ + __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ + __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ + } TYPE1; + }; + __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */ + __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name BDH - UART Baud Rate Registers: High */ +#define UART_BDH_SBR_MASK (0x1FU) +#define UART_BDH_SBR_SHIFT (0U) +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) +#define UART_BDH_RXEDGIE_MASK (0x40U) +#define UART_BDH_RXEDGIE_SHIFT (6U) +#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) +#define UART_BDH_LBKDIE_MASK (0x80U) +#define UART_BDH_LBKDIE_SHIFT (7U) +#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) + +/*! @name BDL - UART Baud Rate Registers: Low */ +#define UART_BDL_SBR_MASK (0xFFU) +#define UART_BDL_SBR_SHIFT (0U) +#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) + +/*! @name C1 - UART Control Register 1 */ +#define UART_C1_PT_MASK (0x1U) +#define UART_C1_PT_SHIFT (0U) +#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) +#define UART_C1_PE_MASK (0x2U) +#define UART_C1_PE_SHIFT (1U) +#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) +#define UART_C1_ILT_MASK (0x4U) +#define UART_C1_ILT_SHIFT (2U) +#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) +#define UART_C1_WAKE_MASK (0x8U) +#define UART_C1_WAKE_SHIFT (3U) +#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) +#define UART_C1_M_MASK (0x10U) +#define UART_C1_M_SHIFT (4U) +#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) +#define UART_C1_RSRC_MASK (0x20U) +#define UART_C1_RSRC_SHIFT (5U) +#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) +#define UART_C1_UARTSWAI_MASK (0x40U) +#define UART_C1_UARTSWAI_SHIFT (6U) +#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) +#define UART_C1_LOOPS_MASK (0x80U) +#define UART_C1_LOOPS_SHIFT (7U) +#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) + +/*! @name C2 - UART Control Register 2 */ +#define UART_C2_SBK_MASK (0x1U) +#define UART_C2_SBK_SHIFT (0U) +#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) +#define UART_C2_RWU_MASK (0x2U) +#define UART_C2_RWU_SHIFT (1U) +#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) +#define UART_C2_RE_MASK (0x4U) +#define UART_C2_RE_SHIFT (2U) +#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) +#define UART_C2_TE_MASK (0x8U) +#define UART_C2_TE_SHIFT (3U) +#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) +#define UART_C2_ILIE_MASK (0x10U) +#define UART_C2_ILIE_SHIFT (4U) +#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) +#define UART_C2_RIE_MASK (0x20U) +#define UART_C2_RIE_SHIFT (5U) +#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) +#define UART_C2_TCIE_MASK (0x40U) +#define UART_C2_TCIE_SHIFT (6U) +#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) +#define UART_C2_TIE_MASK (0x80U) +#define UART_C2_TIE_SHIFT (7U) +#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) + +/*! @name S1 - UART Status Register 1 */ +#define UART_S1_PF_MASK (0x1U) +#define UART_S1_PF_SHIFT (0U) +#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) +#define UART_S1_FE_MASK (0x2U) +#define UART_S1_FE_SHIFT (1U) +#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) +#define UART_S1_NF_MASK (0x4U) +#define UART_S1_NF_SHIFT (2U) +#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) +#define UART_S1_OR_MASK (0x8U) +#define UART_S1_OR_SHIFT (3U) +#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) +#define UART_S1_IDLE_MASK (0x10U) +#define UART_S1_IDLE_SHIFT (4U) +#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) +#define UART_S1_RDRF_MASK (0x20U) +#define UART_S1_RDRF_SHIFT (5U) +#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) +#define UART_S1_TC_MASK (0x40U) +#define UART_S1_TC_SHIFT (6U) +#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) +#define UART_S1_TDRE_MASK (0x80U) +#define UART_S1_TDRE_SHIFT (7U) +#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) + +/*! @name S2 - UART Status Register 2 */ +#define UART_S2_RAF_MASK (0x1U) +#define UART_S2_RAF_SHIFT (0U) +#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) +#define UART_S2_LBKDE_MASK (0x2U) +#define UART_S2_LBKDE_SHIFT (1U) +#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) +#define UART_S2_BRK13_MASK (0x4U) +#define UART_S2_BRK13_SHIFT (2U) +#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) +#define UART_S2_RWUID_MASK (0x8U) +#define UART_S2_RWUID_SHIFT (3U) +#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) +#define UART_S2_RXINV_MASK (0x10U) +#define UART_S2_RXINV_SHIFT (4U) +#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) +#define UART_S2_MSBF_MASK (0x20U) +#define UART_S2_MSBF_SHIFT (5U) +#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) +#define UART_S2_RXEDGIF_MASK (0x40U) +#define UART_S2_RXEDGIF_SHIFT (6U) +#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) +#define UART_S2_LBKDIF_MASK (0x80U) +#define UART_S2_LBKDIF_SHIFT (7U) +#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) + +/*! @name C3 - UART Control Register 3 */ +#define UART_C3_PEIE_MASK (0x1U) +#define UART_C3_PEIE_SHIFT (0U) +#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) +#define UART_C3_FEIE_MASK (0x2U) +#define UART_C3_FEIE_SHIFT (1U) +#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) +#define UART_C3_NEIE_MASK (0x4U) +#define UART_C3_NEIE_SHIFT (2U) +#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) +#define UART_C3_ORIE_MASK (0x8U) +#define UART_C3_ORIE_SHIFT (3U) +#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) +#define UART_C3_TXINV_MASK (0x10U) +#define UART_C3_TXINV_SHIFT (4U) +#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) +#define UART_C3_TXDIR_MASK (0x20U) +#define UART_C3_TXDIR_SHIFT (5U) +#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) +#define UART_C3_T8_MASK (0x40U) +#define UART_C3_T8_SHIFT (6U) +#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) +#define UART_C3_R8_MASK (0x80U) +#define UART_C3_R8_SHIFT (7U) +#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) + +/*! @name D - UART Data Register */ +#define UART_D_RT_MASK (0xFFU) +#define UART_D_RT_SHIFT (0U) +#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) + +/*! @name MA1 - UART Match Address Registers 1 */ +#define UART_MA1_MA_MASK (0xFFU) +#define UART_MA1_MA_SHIFT (0U) +#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) + +/*! @name MA2 - UART Match Address Registers 2 */ +#define UART_MA2_MA_MASK (0xFFU) +#define UART_MA2_MA_SHIFT (0U) +#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) + +/*! @name C4 - UART Control Register 4 */ +#define UART_C4_BRFA_MASK (0x1FU) +#define UART_C4_BRFA_SHIFT (0U) +#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) +#define UART_C4_M10_MASK (0x20U) +#define UART_C4_M10_SHIFT (5U) +#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) +#define UART_C4_MAEN2_MASK (0x40U) +#define UART_C4_MAEN2_SHIFT (6U) +#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) +#define UART_C4_MAEN1_MASK (0x80U) +#define UART_C4_MAEN1_SHIFT (7U) +#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) + +/*! @name C5 - UART Control Register 5 */ +#define UART_C5_RDMAS_MASK (0x20U) +#define UART_C5_RDMAS_SHIFT (5U) +#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) +#define UART_C5_TDMAS_MASK (0x80U) +#define UART_C5_TDMAS_SHIFT (7U) +#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) + +/*! @name ED - UART Extended Data Register */ +#define UART_ED_PARITYE_MASK (0x40U) +#define UART_ED_PARITYE_SHIFT (6U) +#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) +#define UART_ED_NOISY_MASK (0x80U) +#define UART_ED_NOISY_SHIFT (7U) +#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) + +/*! @name MODEM - UART Modem Register */ +#define UART_MODEM_TXCTSE_MASK (0x1U) +#define UART_MODEM_TXCTSE_SHIFT (0U) +#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) +#define UART_MODEM_TXRTSE_MASK (0x2U) +#define UART_MODEM_TXRTSE_SHIFT (1U) +#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) +#define UART_MODEM_TXRTSPOL_MASK (0x4U) +#define UART_MODEM_TXRTSPOL_SHIFT (2U) +#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) +#define UART_MODEM_RXRTSE_MASK (0x8U) +#define UART_MODEM_RXRTSE_SHIFT (3U) +#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) + +/*! @name IR - UART Infrared Register */ +#define UART_IR_TNP_MASK (0x3U) +#define UART_IR_TNP_SHIFT (0U) +#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) +#define UART_IR_IREN_MASK (0x4U) +#define UART_IR_IREN_SHIFT (2U) +#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) + +/*! @name PFIFO - UART FIFO Parameters */ +#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) +#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) +#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) +#define UART_PFIFO_RXFE_MASK (0x8U) +#define UART_PFIFO_RXFE_SHIFT (3U) +#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) +#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) +#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) +#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) +#define UART_PFIFO_TXFE_MASK (0x80U) +#define UART_PFIFO_TXFE_SHIFT (7U) +#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) + +/*! @name CFIFO - UART FIFO Control Register */ +#define UART_CFIFO_RXUFE_MASK (0x1U) +#define UART_CFIFO_RXUFE_SHIFT (0U) +#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) +#define UART_CFIFO_TXOFE_MASK (0x2U) +#define UART_CFIFO_TXOFE_SHIFT (1U) +#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) +#define UART_CFIFO_RXOFE_MASK (0x4U) +#define UART_CFIFO_RXOFE_SHIFT (2U) +#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) +#define UART_CFIFO_RXFLUSH_MASK (0x40U) +#define UART_CFIFO_RXFLUSH_SHIFT (6U) +#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) +#define UART_CFIFO_TXFLUSH_MASK (0x80U) +#define UART_CFIFO_TXFLUSH_SHIFT (7U) +#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) + +/*! @name SFIFO - UART FIFO Status Register */ +#define UART_SFIFO_RXUF_MASK (0x1U) +#define UART_SFIFO_RXUF_SHIFT (0U) +#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) +#define UART_SFIFO_TXOF_MASK (0x2U) +#define UART_SFIFO_TXOF_SHIFT (1U) +#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) +#define UART_SFIFO_RXOF_MASK (0x4U) +#define UART_SFIFO_RXOF_SHIFT (2U) +#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) +#define UART_SFIFO_RXEMPT_MASK (0x40U) +#define UART_SFIFO_RXEMPT_SHIFT (6U) +#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) +#define UART_SFIFO_TXEMPT_MASK (0x80U) +#define UART_SFIFO_TXEMPT_SHIFT (7U) +#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) + +/*! @name TWFIFO - UART FIFO Transmit Watermark */ +#define UART_TWFIFO_TXWATER_MASK (0xFFU) +#define UART_TWFIFO_TXWATER_SHIFT (0U) +#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) + +/*! @name TCFIFO - UART FIFO Transmit Count */ +#define UART_TCFIFO_TXCOUNT_MASK (0xFFU) +#define UART_TCFIFO_TXCOUNT_SHIFT (0U) +#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) + +/*! @name RWFIFO - UART FIFO Receive Watermark */ +#define UART_RWFIFO_RXWATER_MASK (0xFFU) +#define UART_RWFIFO_RXWATER_SHIFT (0U) +#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) + +/*! @name RCFIFO - UART FIFO Receive Count */ +#define UART_RCFIFO_RXCOUNT_MASK (0xFFU) +#define UART_RCFIFO_RXCOUNT_SHIFT (0U) +#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) + +/*! @name C7816 - UART 7816 Control Register */ +#define UART_C7816_ISO_7816E_MASK (0x1U) +#define UART_C7816_ISO_7816E_SHIFT (0U) +#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) +#define UART_C7816_TTYPE_MASK (0x2U) +#define UART_C7816_TTYPE_SHIFT (1U) +#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) +#define UART_C7816_INIT_MASK (0x4U) +#define UART_C7816_INIT_SHIFT (2U) +#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) +#define UART_C7816_ANACK_MASK (0x8U) +#define UART_C7816_ANACK_SHIFT (3U) +#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) +#define UART_C7816_ONACK_MASK (0x10U) +#define UART_C7816_ONACK_SHIFT (4U) +#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) + +/*! @name IE7816 - UART 7816 Interrupt Enable Register */ +#define UART_IE7816_RXTE_MASK (0x1U) +#define UART_IE7816_RXTE_SHIFT (0U) +#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) +#define UART_IE7816_TXTE_MASK (0x2U) +#define UART_IE7816_TXTE_SHIFT (1U) +#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) +#define UART_IE7816_GTVE_MASK (0x4U) +#define UART_IE7816_GTVE_SHIFT (2U) +#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) +#define UART_IE7816_ADTE_MASK (0x8U) +#define UART_IE7816_ADTE_SHIFT (3U) +#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK) +#define UART_IE7816_INITDE_MASK (0x10U) +#define UART_IE7816_INITDE_SHIFT (4U) +#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) +#define UART_IE7816_BWTE_MASK (0x20U) +#define UART_IE7816_BWTE_SHIFT (5U) +#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) +#define UART_IE7816_CWTE_MASK (0x40U) +#define UART_IE7816_CWTE_SHIFT (6U) +#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) +#define UART_IE7816_WTE_MASK (0x80U) +#define UART_IE7816_WTE_SHIFT (7U) +#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) + +/*! @name IS7816 - UART 7816 Interrupt Status Register */ +#define UART_IS7816_RXT_MASK (0x1U) +#define UART_IS7816_RXT_SHIFT (0U) +#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) +#define UART_IS7816_TXT_MASK (0x2U) +#define UART_IS7816_TXT_SHIFT (1U) +#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) +#define UART_IS7816_GTV_MASK (0x4U) +#define UART_IS7816_GTV_SHIFT (2U) +#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) +#define UART_IS7816_ADT_MASK (0x8U) +#define UART_IS7816_ADT_SHIFT (3U) +#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK) +#define UART_IS7816_INITD_MASK (0x10U) +#define UART_IS7816_INITD_SHIFT (4U) +#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) +#define UART_IS7816_BWT_MASK (0x20U) +#define UART_IS7816_BWT_SHIFT (5U) +#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) +#define UART_IS7816_CWT_MASK (0x40U) +#define UART_IS7816_CWT_SHIFT (6U) +#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) +#define UART_IS7816_WT_MASK (0x80U) +#define UART_IS7816_WT_SHIFT (7U) +#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) + +/*! @name WP7816 - UART 7816 Wait Parameter Register */ +#define UART_WP7816_WTX_MASK (0xFFU) +#define UART_WP7816_WTX_SHIFT (0U) +#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK) + +/*! @name WN7816 - UART 7816 Wait N Register */ +#define UART_WN7816_GTN_MASK (0xFFU) +#define UART_WN7816_GTN_SHIFT (0U) +#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) + +/*! @name WF7816 - UART 7816 Wait FD Register */ +#define UART_WF7816_GTFD_MASK (0xFFU) +#define UART_WF7816_GTFD_SHIFT (0U) +#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) + +/*! @name ET7816 - UART 7816 Error Threshold Register */ +#define UART_ET7816_RXTHRESHOLD_MASK (0xFU) +#define UART_ET7816_RXTHRESHOLD_SHIFT (0U) +#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) +#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) +#define UART_ET7816_TXTHRESHOLD_SHIFT (4U) +#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) + +/*! @name TL7816 - UART 7816 Transmit Length Register */ +#define UART_TL7816_TLEN_MASK (0xFFU) +#define UART_TL7816_TLEN_SHIFT (0U) +#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) + +/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */ +#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU) +#define UART_AP7816A_T0_ADTI_H_SHIFT (0U) +#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK) + +/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */ +#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU) +#define UART_AP7816B_T0_ADTI_L_SHIFT (0U) +#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK) + +/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */ +#define UART_WP7816A_T0_WI_H_MASK (0xFFU) +#define UART_WP7816A_T0_WI_H_SHIFT (0U) +#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK) + +/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */ +#define UART_WP7816B_T0_WI_L_MASK (0xFFU) +#define UART_WP7816B_T0_WI_L_SHIFT (0U) +#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK) + +/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */ +#define UART_WP7816A_T1_BWI_H_MASK (0xFFU) +#define UART_WP7816A_T1_BWI_H_SHIFT (0U) +#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK) + +/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */ +#define UART_WP7816B_T1_BWI_L_MASK (0xFFU) +#define UART_WP7816B_T1_BWI_L_SHIFT (0U) +#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK) + +/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */ +#define UART_WGP7816_T1_BGI_MASK (0xFU) +#define UART_WGP7816_T1_BGI_SHIFT (0U) +#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK) +#define UART_WGP7816_T1_CWI1_MASK (0xF0U) +#define UART_WGP7816_T1_CWI1_SHIFT (4U) +#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK) + +/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */ +#define UART_WP7816C_T1_CWI2_MASK (0x1FU) +#define UART_WP7816C_T1_CWI2_SHIFT (0U) +#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART0 base address */ +#define UART0_BASE (0x4006A000u) +/** Peripheral UART0 base pointer */ +#define UART0 ((UART_Type *)UART0_BASE) +/** Peripheral UART1 base address */ +#define UART1_BASE (0x4006B000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x4006C000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { UART0, UART1, UART2 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn } +#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status register, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control register, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ + uint8_t RESERVED_26[43]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ + uint8_t RESERVED_27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ + uint8_t RESERVED_28[23]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID register */ +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) + +/*! @name IDCOMP - Peripheral ID Complement register */ +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) + +/*! @name REV - Peripheral Revision register */ +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) + +/*! @name ADDINFO - Peripheral Additional Info register */ +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) + +/*! @name OTGISTAT - OTG Interrupt Status register */ +#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) +#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) +#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) +#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) +#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) +#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) +#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) +#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) +#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) +#define USB_OTGISTAT_IDCHG_MASK (0x80U) +#define USB_OTGISTAT_IDCHG_SHIFT (7U) +#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) + +/*! @name OTGICR - OTG Interrupt Control register */ +#define USB_OTGICR_AVBUSEN_MASK (0x1U) +#define USB_OTGICR_AVBUSEN_SHIFT (0U) +#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) +#define USB_OTGICR_BSESSEN_MASK (0x4U) +#define USB_OTGICR_BSESSEN_SHIFT (2U) +#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) +#define USB_OTGICR_SESSVLDEN_MASK (0x8U) +#define USB_OTGICR_SESSVLDEN_SHIFT (3U) +#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) +#define USB_OTGICR_IDEN_MASK (0x80U) +#define USB_OTGICR_IDEN_SHIFT (7U) +#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) + +/*! @name OTGSTAT - OTG Status register */ +#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) +#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) +#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) +#define USB_OTGSTAT_BSESSEND_MASK (0x4U) +#define USB_OTGSTAT_BSESSEND_SHIFT (2U) +#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) +#define USB_OTGSTAT_SESS_VLD_MASK (0x8U) +#define USB_OTGSTAT_SESS_VLD_SHIFT (3U) +#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) +#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) +#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) +#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) +#define USB_OTGSTAT_ID_MASK (0x80U) +#define USB_OTGSTAT_ID_SHIFT (7U) +#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) + +/*! @name OTGCTL - OTG Control register */ +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) + +/*! @name ISTAT - Interrupt Status register */ +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) + +/*! @name INTEN - Interrupt Enable register */ +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) + +/*! @name ERRSTAT - Error Interrupt Status register */ +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) + +/*! @name ERREN - Error Interrupt Enable register */ +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) + +/*! @name STAT - Status register */ +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) + +/*! @name CTL - Control register */ +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) + +/*! @name ADDR - Address register */ +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) + +/*! @name BDTPAGE1 - BDT Page register 1 */ +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) + +/*! @name FRMNUML - Frame Number register Low */ +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) + +/*! @name FRMNUMH - Frame Number register High */ +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) + +/*! @name TOKEN - Token register */ +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) + +/*! @name SOFTHLD - SOF Threshold register */ +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) + +/*! @name BDTPAGE2 - BDT Page Register 2 */ +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) + +/*! @name BDTPAGE3 - BDT Page Register 3 */ +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) + +/*! @name ENDPT - Endpoint Control register */ +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control register */ +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) + +/*! @name OBSERVE - USB OTG Observe register */ +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) + +/*! @name CONTROL - USB OTG Control register */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) + +/*! @name USBTRC0 - USB Transceiver Control register 0 */ +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) + +/*! @name USBFRMADJUST - Frame Adjust Register */ +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) + +/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) + +/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ +#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) + +/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40072000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ + __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name TRM - VREF Trim Register */ +#define VREF_TRM_TRIM_MASK (0x3FU) +#define VREF_TRM_TRIM_SHIFT (0U) +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) +#define VREF_TRM_CHOPEN_MASK (0x40U) +#define VREF_TRM_CHOPEN_SHIFT (6U) +#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) + +/*! @name SC - VREF Status and Control Register */ +#define VREF_SC_MODE_LV_MASK (0x3U) +#define VREF_SC_MODE_LV_SHIFT (0U) +#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) +#define VREF_SC_VREFST_MASK (0x4U) +#define VREF_SC_VREFST_SHIFT (2U) +#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) +#define VREF_SC_ICOMPEN_MASK (0x20U) +#define VREF_SC_ICOMPEN_SHIFT (5U) +#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) +#define VREF_SC_REGEN_MASK (0x40U) +#define VREF_SC_REGEN_SHIFT (6U) +#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) +#define VREF_SC_VREFEN_MASK (0x80U) +#define VREF_SC_VREFEN_SHIFT (7U) +#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +/** Peripheral VREF base address */ +#define VREF_BASE (0x40074000u) +/** Peripheral VREF base pointer */ +#define VREF ((VREF_Type *)VREF_BASE) +/** Array initializer of VREF peripheral base addresses */ +#define VREF_BASE_ADDRS { VREF_BASE } +/** Array initializer of VREF peripheral base pointers */ +#define VREF_BASE_PTRS { VREF } + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ + __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ + __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ + __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ + __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ + __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ + __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ + __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ + __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ + __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ + __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ + __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name STCTRLH - Watchdog Status and Control Register High */ +#define WDOG_STCTRLH_WDOGEN_MASK (0x1U) +#define WDOG_STCTRLH_WDOGEN_SHIFT (0U) +#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) +#define WDOG_STCTRLH_CLKSRC_MASK (0x2U) +#define WDOG_STCTRLH_CLKSRC_SHIFT (1U) +#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) +#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) +#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) +#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) +#define WDOG_STCTRLH_WINEN_MASK (0x8U) +#define WDOG_STCTRLH_WINEN_SHIFT (3U) +#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) +#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) +#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) +#define WDOG_STCTRLH_DBGEN_MASK (0x20U) +#define WDOG_STCTRLH_DBGEN_SHIFT (5U) +#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) +#define WDOG_STCTRLH_STOPEN_MASK (0x40U) +#define WDOG_STCTRLH_STOPEN_SHIFT (6U) +#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) +#define WDOG_STCTRLH_WAITEN_MASK (0x80U) +#define WDOG_STCTRLH_WAITEN_SHIFT (7U) +#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) +#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) +#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) +#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) +#define WDOG_STCTRLH_TESTSEL_MASK (0x800U) +#define WDOG_STCTRLH_TESTSEL_SHIFT (11U) +#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) +#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) +#define WDOG_STCTRLH_BYTESEL_SHIFT (12U) +#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) +#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) +#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) +#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) + +/*! @name STCTRLL - Watchdog Status and Control Register Low */ +#define WDOG_STCTRLL_INTFLG_MASK (0x8000U) +#define WDOG_STCTRLL_INTFLG_SHIFT (15U) +#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) + +/*! @name TOVALH - Watchdog Time-out Value Register High */ +#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) +#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) +#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) + +/*! @name TOVALL - Watchdog Time-out Value Register Low */ +#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) +#define WDOG_TOVALL_TOVALLOW_SHIFT (0U) +#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) + +/*! @name WINH - Watchdog Window Register High */ +#define WDOG_WINH_WINHIGH_MASK (0xFFFFU) +#define WDOG_WINH_WINHIGH_SHIFT (0U) +#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) + +/*! @name WINL - Watchdog Window Register Low */ +#define WDOG_WINL_WINLOW_MASK (0xFFFFU) +#define WDOG_WINL_WINLOW_SHIFT (0U) +#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) + +/*! @name REFRESH - Watchdog Refresh register */ +#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) +#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) +#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) + +/*! @name UNLOCK - Watchdog Unlock register */ +#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) +#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) +#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) + +/*! @name TMROUTH - Watchdog Timer Output Register High */ +#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) +#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) +#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) + +/*! @name TMROUTL - Watchdog Timer Output Register Low */ +#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) +#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) +#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) + +/*! @name RSTCNT - Watchdog Reset Count register */ +#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) +#define WDOG_RSTCNT_RSTCNT_SHIFT (0U) +#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) + +/*! @name PRESC - Watchdog Prescaler register */ +#define WDOG_PRESC_PRESCVAL_MASK (0x700U) +#define WDOG_PRESC_PRESCVAL_SHIFT (8U) +#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG base address */ +#define WDOG_BASE (0x40052000u) +/** Peripheral WDOG base pointer */ +#define WDOG ((WDOG_Type *)WDOG_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { WDOG_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG_EWM_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT +#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) +#define MCM_ISR_REG(base) MCM_ISCR_REG(base) +#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK +#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT +#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK +#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT +#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK +#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT +#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK +#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT +#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK +#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT +#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK +#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT +#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK +#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT +#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK +#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT +#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK +#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT +#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK +#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT +#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK +#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT +#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK +#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define GPIOA_BASE PTA_BASE +#define GPIOA PTA +#define GPIOB_BASE PTB_BASE +#define GPIOB PTB +#define GPIOC_BASE PTC_BASE +#define GPIOC PTC +#define GPIOD_BASE PTD_BASE +#define GPIOD PTD +#define GPIOE_BASE PTE_BASE +#define GPIOE PTE +#define DMAMUX0 DMAMUX +#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated +#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated +#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated +#define Watchdog_IRQn WDOG_EWM_IRQn +#define Watchdog_IRQHandler WDOG_EWM_IRQHandler +#define LPTimer_IRQn LPTMR0_IRQn +#define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MK22F51212_H_ */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212_features.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212_features.h new file mode 100755 index 00000000000..04c90fd9887 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212_features.h @@ -0,0 +1,1899 @@ +/* +** ################################################################### +** Version: rev. 2.14, 2015-06-08 +** Build: b151216 +** +** Abstract: +** Chip specific module features. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-07-23) +** Initial version. +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-01-30) +** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.6 (2014-05-06) +** Update according to reference manual rev. 1.0, +** Update of system and startup files. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.7 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.8 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.9 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 2.10 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 2.11 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PDB and PORT. +** - rev. 2.12 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 2.13 (2015-05-27) +** Several USB features added. +** - rev. 2.14 (2015-06-08) +** FTM features BUS_CLOCK and FAST_CLOCK removed. +** +** ################################################################### +*/ + +#ifndef _MK22F51212_FEATURES_H_ +#define _MK22F51212_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (2) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (2) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (2) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (1) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (0) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (4) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (1) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (1) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (1) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (1) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (1) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (3) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (1) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (16) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) +/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXBUS module features */ + +/* No feature definitions */ + +/* FLASH module features */ + +/* @brief Is of type FTFA. */ +#define FSL_FEATURE_FLASH_IS_FTFA (1) +/* @brief Is of type FTFE. */ +#define FSL_FEATURE_FLASH_IS_FTFE (0) +/* @brief Is of type FTFL. */ +#define FSL_FEATURE_FLASH_IS_FTFL (0) +/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ +#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) +/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ +#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) +/* @brief Has EEPROM region protection (register FEPROT). */ +#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) +/* @brief Has data flash region protection (register FDPROT). */ +#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) +/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ +#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) +/* @brief Has flash cache control in FMC module. */ +#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) +/* @brief Has flash cache control in MCM module. */ +#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) +/* @brief P-Flash start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) +/* @brief P-Flash write unit size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) +/* @brief P-Flash data path width. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) +/* @brief P-Flash block swap feature. */ +#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) +/* @brief Has FlexNVM memory. */ +#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) +/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ +#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) +/* @brief FlexNVM block count. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) +/* @brief FlexNVM block size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) +/* @brief FlexNVM sector size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) +/* @brief FlexNVM write unit size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) +/* @brief FlexNVM data path width. */ +#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) +/* @brief Has FlexRAM memory. */ +#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) +/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ +#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) +/* @brief FlexRAM size. */ +#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) +/* @brief Has 0x00 Read 1s Block command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) +/* @brief Has 0x01 Read 1s Section command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) +/* @brief Has 0x02 Program Check command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) +/* @brief Has 0x03 Read Resource command. */ +#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) +/* @brief Has 0x06 Program Longword command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) +/* @brief Has 0x07 Program Phrase command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) +/* @brief Has 0x08 Erase Flash Block command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) +/* @brief Has 0x09 Erase Flash Sector command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) +/* @brief Has 0x0B Program Section command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) +/* @brief Has 0x40 Read 1s All Blocks command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) +/* @brief Has 0x41 Read Once command. */ +#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) +/* @brief Has 0x43 Program Once command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) +/* @brief Has 0x44 Erase All Blocks command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) +/* @brief Has 0x45 Verify Backdoor Access Key command. */ +#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) +/* @brief Has 0x46 Swap Control command. */ +#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) +/* @brief Has 0x49 Erase All Blocks Unsecure command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) +/* @brief Has 0x80 Program Partition command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) +/* @brief Has 0x81 Set FlexRAM Function command. */ +#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) +/* @brief P-Flash Erase/Read 1st all block command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) +/* @brief P-Flash Erase sector command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) +/* @brief P-Flash Rrogram/Verify section command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) +/* @brief P-Flash Read resource command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) +/* @brief P-Flash Program check command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) +/* @brief P-Flash Program check command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Erase/Read 1st all block command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Erase sector command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Rrogram/Verify section command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Read resource command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Program check command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) +/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) +/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) +/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) +/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) +/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) +/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) +/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) +/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) +/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) +/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) +/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) +/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) +/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) +/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) +/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) +/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) + +/* FTM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == FTM0 ? (8) : \ + ((x) == FTM1 ? (2) : \ + ((x) == FTM2 ? (2) : \ + ((x) == FTM3 ? (8) : (-1))))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +/* @brief Enable pwm output for the module. */ +#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) +/* @brief Has half-cycle reload for the module. */ +#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) +/* @brief Has reload interrupt. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) +/* @brief Has reload initialization trigger. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (1) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) +/* @brief Ihe interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (1) + +/* LLWU module features */ + +#if defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF5 register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VMP12) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF5 register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) */ + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (1) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (1) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL (1) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (0) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (1) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) + +/* PDB module features */ + +/* @brief Define the count of supporting ADC pre-trigger for each channel. */ +#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) +/* @brief Has DAC support. */ +#define FSL_FEATURE_PDB_HAS_DAC (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (1) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (0) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (1) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (1) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (1) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (1) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (1) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (3) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (1) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (0) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (0) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) + +/* DSPI module features */ + +#if defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VMP12) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == DSPI0 ? (4) : \ + ((x) == DSPI1 ? (1) : (-1))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == DSPI0 ? (1) : \ + ((x) == DSPI1 ? (0) : (-1))) +#elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == DSPI0 ? (4) : \ + ((x) == DSPI1 ? (1) : (-1))) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == DSPI0 ? (1) : \ + ((x) == DSPI1 ? (0) : (-1))) +#endif /* defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VMP12) */ + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* UART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_HAS_FIFO (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) +/* @brief Peripheral type. */ +#define FSL_FEATURE_UART_IS_SCI (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (1) : \ + ((x) == UART2 ? (1) : (-1)))) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_UART_HAS_DMA_SELECT (1) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* USB module features */ + +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief Describes the set of SC[MODE_LV] bitfield values */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief Has Wait mode support. */ +#define FSL_FEATURE_WDOG_HAS_WAITEN (1) + +#endif /* _MK22F51212_FEATURES_H_ */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct new file mode 100644 index 00000000000..3298c093177 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct @@ -0,0 +1,116 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MK22FN512CAP12 +** MK22FN512VDC12 +** MK22FN512VLH12 +** MK22FN512VLL12 +** MK22FN512VMP12 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151009 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +#define __ram_vector_table__ 1 + +/* Heap 1/4 of ram and stack 1/8 */ +#define __stack_size__ 0x4000 +#define __heap_size__ 0x8000 + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000400 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_flash_config_start 0x00000400 +#define m_flash_config_size 0x00000010 + +#define m_text_start 0x00000410 +#define m_text_size 0x0007FBF0 + +#define m_interrupts_ram_start 0x1FFF0000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x00010000 - m_interrupts_ram_size) + +#define m_data_2_start 0x20000000 +#define m_data_2_size 0x00010000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_flash_config m_flash_config_start m_flash_config_size { ; load address = execution address + * (FlashConfig) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM1 ((ImageLimit(RW_m_data_2) == m_data_2_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up + } + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S new file mode 100644 index 00000000000..232e400e66f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S @@ -0,0 +1,906 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MK22F51212.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * MK22F51212 +; * @version: 1.7 +; * @date: 2015-2-19 +; * @build: b151105 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20010000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTF_IRQHandler ;FTFA Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD Reserved53_IRQHandler ;Reserved interrupt 53 + DCD Reserved54_IRQHandler ;Reserved interrupt 54 + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD Reserved61_IRQHandler ;Reserved interrupt 61 + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD Reserved70_IRQHandler ;Reserved interrupt 70 + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD Reserved81_IRQHandler ;Reserved interrupt 81 + DCD Reserved82_IRQHandler ;Reserved interrupt 82 + DCD Reserved83_IRQHandler ;Reserved interrupt 83 + DCD Reserved84_IRQHandler ;Reserved interrupt 84 + DCD Reserved85_IRQHandler ;Reserved interrupt 85 + DCD Reserved86_IRQHandler ;Reserved interrupt 86 + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD Reserved90_IRQHandler ;Reserved Interrupt 90 + DCD Reserved91_IRQHandler ;Reserved Interrupt 91 + DCD Reserved92_IRQHandler ;Reserved Interrupt 92 + DCD Reserved93_IRQHandler ;Reserved Interrupt 93 + DCD Reserved94_IRQHandler ;Reserved Interrupt 94 + DCD Reserved95_IRQHandler ;Reserved Interrupt 95 + DCD Reserved96_IRQHandler ;Reserved Interrupt 96 + DCD Reserved97_IRQHandler ;Reserved Interrupt 97 + DCD Reserved98_IRQHandler ;Reserved Interrupt 98 + DCD Reserved99_IRQHandler ;Reserved Interrupt 99 + DCD Reserved100_IRQHandler ;Reserved Interrupt 100 + DCD Reserved101_IRQHandler ;Reserved Interrupt 101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; EZPORT_DIS +; <0=> EzPort operation is disabled +; <1=> EzPort operation is enabled +; NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA8_IRQHandler\ + PROC + EXPORT DMA8_IRQHandler [WEAK] + LDR R0, =DMA8_DriverIRQHandler + BX R0 + ENDP + +DMA9_IRQHandler\ + PROC + EXPORT DMA9_IRQHandler [WEAK] + LDR R0, =DMA9_DriverIRQHandler + BX R0 + ENDP + +DMA10_IRQHandler\ + PROC + EXPORT DMA10_IRQHandler [WEAK] + LDR R0, =DMA10_DriverIRQHandler + BX R0 + ENDP + +DMA11_IRQHandler\ + PROC + EXPORT DMA11_IRQHandler [WEAK] + LDR R0, =DMA11_DriverIRQHandler + BX R0 + ENDP + +DMA12_IRQHandler\ + PROC + EXPORT DMA12_IRQHandler [WEAK] + LDR R0, =DMA12_DriverIRQHandler + BX R0 + ENDP + +DMA13_IRQHandler\ + PROC + EXPORT DMA13_IRQHandler [WEAK] + LDR R0, =DMA13_DriverIRQHandler + BX R0 + ENDP + +DMA14_IRQHandler\ + PROC + EXPORT DMA14_IRQHandler [WEAK] + LDR R0, =DMA14_DriverIRQHandler + BX R0 + ENDP + +DMA15_IRQHandler\ + PROC + EXPORT DMA15_IRQHandler [WEAK] + LDR R0, =DMA15_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +I2S0_Tx_IRQHandler\ + PROC + EXPORT I2S0_Tx_IRQHandler [WEAK] + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + ENDP + +I2S0_Rx_IRQHandler\ + PROC + EXPORT I2S0_Rx_IRQHandler [WEAK] + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +UART0_RX_TX_IRQHandler\ + PROC + EXPORT UART0_RX_TX_IRQHandler [WEAK] + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART0_ERR_IRQHandler\ + PROC + EXPORT UART0_ERR_IRQHandler [WEAK] + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + ENDP + +UART1_RX_TX_IRQHandler\ + PROC + EXPORT UART1_RX_TX_IRQHandler [WEAK] + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART1_ERR_IRQHandler\ + PROC + EXPORT UART1_ERR_IRQHandler [WEAK] + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + ENDP + +UART2_RX_TX_IRQHandler\ + PROC + EXPORT UART2_RX_TX_IRQHandler [WEAK] + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART2_ERR_IRQHandler\ + PROC + EXPORT UART2_ERR_IRQHandler [WEAK] + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT DMA8_DriverIRQHandler [WEAK] + EXPORT DMA9_DriverIRQHandler [WEAK] + EXPORT DMA10_DriverIRQHandler [WEAK] + EXPORT DMA11_DriverIRQHandler [WEAK] + EXPORT DMA12_DriverIRQHandler [WEAK] + EXPORT DMA13_DriverIRQHandler [WEAK] + EXPORT DMA14_DriverIRQHandler [WEAK] + EXPORT DMA15_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTF_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT I2S0_Tx_DriverIRQHandler [WEAK] + EXPORT I2S0_Rx_DriverIRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART0_ERR_DriverIRQHandler [WEAK] + EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART1_ERR_DriverIRQHandler [WEAK] + EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART2_ERR_DriverIRQHandler [WEAK] + EXPORT Reserved53_IRQHandler [WEAK] + EXPORT Reserved54_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT Reserved61_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT Reserved70_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT Reserved81_IRQHandler [WEAK] + EXPORT Reserved82_IRQHandler [WEAK] + EXPORT Reserved83_IRQHandler [WEAK] + EXPORT Reserved84_IRQHandler [WEAK] + EXPORT Reserved85_IRQHandler [WEAK] + EXPORT Reserved86_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT Reserved90_IRQHandler [WEAK] + EXPORT Reserved91_IRQHandler [WEAK] + EXPORT Reserved92_IRQHandler [WEAK] + EXPORT Reserved93_IRQHandler [WEAK] + EXPORT Reserved94_IRQHandler [WEAK] + EXPORT Reserved95_IRQHandler [WEAK] + EXPORT Reserved96_IRQHandler [WEAK] + EXPORT Reserved97_IRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT Reserved99_IRQHandler [WEAK] + EXPORT Reserved100_IRQHandler [WEAK] + EXPORT Reserved101_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTF_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +LPUART0_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +Reserved61_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +Reserved81_IRQHandler +Reserved82_IRQHandler +Reserved83_IRQHandler +Reserved84_IRQHandler +Reserved85_IRQHandler +Reserved86_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +Reserved90_IRQHandler +Reserved91_IRQHandler +Reserved92_IRQHandler +Reserved93_IRQHandler +Reserved94_IRQHandler +Reserved95_IRQHandler +Reserved96_IRQHandler +Reserved97_IRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +DefaultISR + B DefaultISR + ENDP + ALIGN + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..b129b2c2a5b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld new file mode 100644 index 00000000000..410b3552e2b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld @@ -0,0 +1,268 @@ +/* +** ################################################################### +** Processors: MK22FN512CAP12 +** MK22FN512VDC12 +** MK22FN512VLH12 +** MK22FN512VLL12 +** MK22FN512VMP12 +** +** Compiler: GNU C Compiler +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151217 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +__stack_size__ = 0x4000; +__heap_size__ = 0x8000; + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + . = ALIGN(512); + USB_RAM_START = .; + . += USB_RAM_GAP; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data_2 + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data_2 + + m_usb_bdt USB_RAM_START (NOLOAD) : + { + *(m_usb_bdt) + USB_RAM_BDT_END = .; + } + + m_usb_global USB_RAM_BDT_END (NOLOAD) : + { + *(m_usb_global) + } + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S new file mode 100644 index 00000000000..2eb41247089 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S @@ -0,0 +1,827 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MK22F51212.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MK22F51212 */ +/* @version: 1.7 */ +/* @date: 2015-2-19 */ +/* @build: b151111 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ + .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ + .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ + .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ + .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/ + .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/ + .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/ + .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/ + .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/ + .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/ + .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/ + .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/ + .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/ + .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/ + .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/ + .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/ + .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ + .long MCM_IRQHandler /* Normal Interrupt*/ + .long FTF_IRQHandler /* FTFA Command complete interrupt*/ + .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ + .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/ + .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ + .long RNG_IRQHandler /* RNG Interrupt*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 Interrupt*/ + .long SPI1_IRQHandler /* SPI1 Interrupt*/ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ + .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/ + .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ + .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ + .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ + .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ + .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ + .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ + .long Reserved53_IRQHandler /* Reserved interrupt 53*/ + .long Reserved54_IRQHandler /* Reserved interrupt 54*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long CMP1_IRQHandler /* CMP1 interrupt*/ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ + .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ + .long Reserved61_IRQHandler /* Reserved interrupt 61*/ + .long RTC_IRQHandler /* RTC interrupt*/ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ + .long PDB0_IRQHandler /* PDB0 Interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long Reserved70_IRQHandler /* Reserved interrupt 70*/ + .long Reserved71_IRQHandler /* Reserved interrupt 71*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long MCG_IRQHandler /* MCG Interrupt*/ + .long LPTMR0_IRQHandler /* LPTimer interrupt*/ + .long PORTA_IRQHandler /* Port A interrupt*/ + .long PORTB_IRQHandler /* Port B interrupt*/ + .long PORTC_IRQHandler /* Port C interrupt*/ + .long PORTD_IRQHandler /* Port D interrupt*/ + .long PORTE_IRQHandler /* Port E interrupt*/ + .long SWI_IRQHandler /* Software interrupt*/ + .long Reserved81_IRQHandler /* Reserved interrupt 81*/ + .long Reserved82_IRQHandler /* Reserved interrupt 82*/ + .long Reserved83_IRQHandler /* Reserved interrupt 83*/ + .long Reserved84_IRQHandler /* Reserved interrupt 84*/ + .long Reserved85_IRQHandler /* Reserved interrupt 85*/ + .long Reserved86_IRQHandler /* Reserved interrupt 86*/ + .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ + .long DAC1_IRQHandler /* DAC1 interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long Reserved90_IRQHandler /* Reserved Interrupt 90*/ + .long Reserved91_IRQHandler /* Reserved Interrupt 91*/ + .long Reserved92_IRQHandler /* Reserved Interrupt 92*/ + .long Reserved93_IRQHandler /* Reserved Interrupt 93*/ + .long Reserved94_IRQHandler /* Reserved Interrupt 94*/ + .long Reserved95_IRQHandler /* Reserved Interrupt 95*/ + .long Reserved96_IRQHandler /* Reserved Interrupt 96*/ + .long Reserved97_IRQHandler /* Reserved Interrupt 97*/ + .long Reserved98_IRQHandler /* Reserved Interrupt 98*/ + .long Reserved99_IRQHandler /* Reserved Interrupt 99*/ + .long Reserved100_IRQHandler /* Reserved Interrupt 100*/ + .long Reserved101_IRQHandler /* Reserved Interrupt 101*/ + .long DefaultISR /* 102*/ + .long DefaultISR /* 103*/ + .long DefaultISR /* 104*/ + .long DefaultISR /* 105*/ + .long DefaultISR /* 106*/ + .long DefaultISR /* 107*/ + .long DefaultISR /* 108*/ + .long DefaultISR /* 109*/ + .long DefaultISR /* 110*/ + .long DefaultISR /* 111*/ + .long DefaultISR /* 112*/ + .long DefaultISR /* 113*/ + .long DefaultISR /* 114*/ + .long DefaultISR /* 115*/ + .long DefaultISR /* 116*/ + .long DefaultISR /* 117*/ + .long DefaultISR /* 118*/ + .long DefaultISR /* 119*/ + .long DefaultISR /* 120*/ + .long DefaultISR /* 121*/ + .long DefaultISR /* 122*/ + .long DefaultISR /* 123*/ + .long DefaultISR /* 124*/ + .long DefaultISR /* 125*/ + .long DefaultISR /* 126*/ + .long DefaultISR /* 127*/ + .long DefaultISR /* 128*/ + .long DefaultISR /* 129*/ + .long DefaultISR /* 130*/ + .long DefaultISR /* 131*/ + .long DefaultISR /* 132*/ + .long DefaultISR /* 133*/ + .long DefaultISR /* 134*/ + .long DefaultISR /* 135*/ + .long DefaultISR /* 136*/ + .long DefaultISR /* 137*/ + .long DefaultISR /* 138*/ + .long DefaultISR /* 139*/ + .long DefaultISR /* 140*/ + .long DefaultISR /* 141*/ + .long DefaultISR /* 142*/ + .long DefaultISR /* 143*/ + .long DefaultISR /* 144*/ + .long DefaultISR /* 145*/ + .long DefaultISR /* 146*/ + .long DefaultISR /* 147*/ + .long DefaultISR /* 148*/ + .long DefaultISR /* 149*/ + .long DefaultISR /* 150*/ + .long DefaultISR /* 151*/ + .long DefaultISR /* 152*/ + .long DefaultISR /* 153*/ + .long DefaultISR /* 154*/ + .long DefaultISR /* 155*/ + .long DefaultISR /* 156*/ + .long DefaultISR /* 157*/ + .long DefaultISR /* 158*/ + .long DefaultISR /* 159*/ + .long DefaultISR /* 160*/ + .long DefaultISR /* 161*/ + .long DefaultISR /* 162*/ + .long DefaultISR /* 163*/ + .long DefaultISR /* 164*/ + .long DefaultISR /* 165*/ + .long DefaultISR /* 166*/ + .long DefaultISR /* 167*/ + .long DefaultISR /* 168*/ + .long DefaultISR /* 169*/ + .long DefaultISR /* 170*/ + .long DefaultISR /* 171*/ + .long DefaultISR /* 172*/ + .long DefaultISR /* 173*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_IRQHandler + .type DMA4_IRQHandler, %function +DMA4_IRQHandler: + ldr r0,=DMA4_DriverIRQHandler + bx r0 + .size DMA4_IRQHandler, . - DMA4_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_IRQHandler + .type DMA5_IRQHandler, %function +DMA5_IRQHandler: + ldr r0,=DMA5_DriverIRQHandler + bx r0 + .size DMA5_IRQHandler, . - DMA5_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_IRQHandler + .type DMA6_IRQHandler, %function +DMA6_IRQHandler: + ldr r0,=DMA6_DriverIRQHandler + bx r0 + .size DMA6_IRQHandler, . - DMA6_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_IRQHandler + .type DMA7_IRQHandler, %function +DMA7_IRQHandler: + ldr r0,=DMA7_DriverIRQHandler + bx r0 + .size DMA7_IRQHandler, . - DMA7_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_IRQHandler + .type DMA8_IRQHandler, %function +DMA8_IRQHandler: + ldr r0,=DMA8_DriverIRQHandler + bx r0 + .size DMA8_IRQHandler, . - DMA8_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_IRQHandler + .type DMA9_IRQHandler, %function +DMA9_IRQHandler: + ldr r0,=DMA9_DriverIRQHandler + bx r0 + .size DMA9_IRQHandler, . - DMA9_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_IRQHandler + .type DMA10_IRQHandler, %function +DMA10_IRQHandler: + ldr r0,=DMA10_DriverIRQHandler + bx r0 + .size DMA10_IRQHandler, . - DMA10_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_IRQHandler + .type DMA11_IRQHandler, %function +DMA11_IRQHandler: + ldr r0,=DMA11_DriverIRQHandler + bx r0 + .size DMA11_IRQHandler, . - DMA11_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_IRQHandler + .type DMA12_IRQHandler, %function +DMA12_IRQHandler: + ldr r0,=DMA12_DriverIRQHandler + bx r0 + .size DMA12_IRQHandler, . - DMA12_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_IRQHandler + .type DMA13_IRQHandler, %function +DMA13_IRQHandler: + ldr r0,=DMA13_DriverIRQHandler + bx r0 + .size DMA13_IRQHandler, . - DMA13_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_IRQHandler + .type DMA14_IRQHandler, %function +DMA14_IRQHandler: + ldr r0,=DMA14_DriverIRQHandler + bx r0 + .size DMA14_IRQHandler, . - DMA14_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_IRQHandler + .type DMA15_IRQHandler, %function +DMA15_IRQHandler: + ldr r0,=DMA15_DriverIRQHandler + bx r0 + .size DMA15_IRQHandler, . - DMA15_IRQHandler + + .align 1 + .thumb_func + .weak DMA_Error_IRQHandler + .type DMA_Error_IRQHandler, %function +DMA_Error_IRQHandler: + ldr r0,=DMA_Error_DriverIRQHandler + bx r0 + .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Tx_IRQHandler + .type I2S0_Tx_IRQHandler, %function +I2S0_Tx_IRQHandler: + ldr r0,=I2S0_Tx_DriverIRQHandler + bx r0 + .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Rx_IRQHandler + .type I2S0_Rx_IRQHandler, %function +I2S0_Rx_IRQHandler: + ldr r0,=I2S0_Rx_DriverIRQHandler + bx r0 + .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler + + .align 1 + .thumb_func + .weak LPUART0_IRQHandler + .type LPUART0_IRQHandler, %function +LPUART0_IRQHandler: + ldr r0,=LPUART0_DriverIRQHandler + bx r0 + .size LPUART0_IRQHandler, . - LPUART0_IRQHandler + + .align 1 + .thumb_func + .weak UART0_RX_TX_IRQHandler + .type UART0_RX_TX_IRQHandler, %function +UART0_RX_TX_IRQHandler: + ldr r0,=UART0_RX_TX_DriverIRQHandler + bx r0 + .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART0_ERR_IRQHandler + .type UART0_ERR_IRQHandler, %function +UART0_ERR_IRQHandler: + ldr r0,=UART0_ERR_DriverIRQHandler + bx r0 + .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART1_RX_TX_IRQHandler + .type UART1_RX_TX_IRQHandler, %function +UART1_RX_TX_IRQHandler: + ldr r0,=UART1_RX_TX_DriverIRQHandler + bx r0 + .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART1_ERR_IRQHandler + .type UART1_ERR_IRQHandler, %function +UART1_ERR_IRQHandler: + ldr r0,=UART1_ERR_DriverIRQHandler + bx r0 + .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART2_RX_TX_IRQHandler + .type UART2_RX_TX_IRQHandler, %function +UART2_RX_TX_IRQHandler: + ldr r0,=UART2_RX_TX_DriverIRQHandler + bx r0 + .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART2_ERR_IRQHandler + .type UART2_ERR_IRQHandler, %function +UART2_ERR_IRQHandler: + ldr r0,=UART2_ERR_DriverIRQHandler + bx r0 + .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler DMA4_DriverIRQHandler + def_irq_handler DMA5_DriverIRQHandler + def_irq_handler DMA6_DriverIRQHandler + def_irq_handler DMA7_DriverIRQHandler + def_irq_handler DMA8_DriverIRQHandler + def_irq_handler DMA9_DriverIRQHandler + def_irq_handler DMA10_DriverIRQHandler + def_irq_handler DMA11_DriverIRQHandler + def_irq_handler DMA12_DriverIRQHandler + def_irq_handler DMA13_DriverIRQHandler + def_irq_handler DMA14_DriverIRQHandler + def_irq_handler DMA15_DriverIRQHandler + def_irq_handler DMA_Error_DriverIRQHandler + def_irq_handler MCM_IRQHandler + def_irq_handler FTF_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler WDOG_EWM_IRQHandler + def_irq_handler RNG_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler I2S0_Tx_DriverIRQHandler + def_irq_handler I2S0_Rx_DriverIRQHandler + def_irq_handler LPUART0_DriverIRQHandler + def_irq_handler UART0_RX_TX_DriverIRQHandler + def_irq_handler UART0_ERR_DriverIRQHandler + def_irq_handler UART1_RX_TX_DriverIRQHandler + def_irq_handler UART1_ERR_DriverIRQHandler + def_irq_handler UART2_RX_TX_DriverIRQHandler + def_irq_handler UART2_ERR_DriverIRQHandler + def_irq_handler Reserved53_IRQHandler + def_irq_handler Reserved54_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler FTM2_IRQHandler + def_irq_handler Reserved61_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler Reserved70_IRQHandler + def_irq_handler Reserved71_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler Reserved81_IRQHandler + def_irq_handler Reserved82_IRQHandler + def_irq_handler Reserved83_IRQHandler + def_irq_handler Reserved84_IRQHandler + def_irq_handler Reserved85_IRQHandler + def_irq_handler Reserved86_IRQHandler + def_irq_handler FTM3_IRQHandler + def_irq_handler DAC1_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler Reserved90_IRQHandler + def_irq_handler Reserved91_IRQHandler + def_irq_handler Reserved92_IRQHandler + def_irq_handler Reserved93_IRQHandler + def_irq_handler Reserved94_IRQHandler + def_irq_handler Reserved95_IRQHandler + def_irq_handler Reserved96_IRQHandler + def_irq_handler Reserved97_IRQHandler + def_irq_handler Reserved98_IRQHandler + def_irq_handler Reserved99_IRQHandler + def_irq_handler Reserved100_IRQHandler + def_irq_handler Reserved101_IRQHandler + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf new file mode 100644 index 00000000000..5ec97d3327b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf @@ -0,0 +1,119 @@ +/* +** ################################################################### +** Processors: MK22FN512CAP12 +** MK22FN512VDC12 +** MK22FN512VLH12 +** MK22FN512VLL12 +** MK22FN512VMP12 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151009 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +define symbol __ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +define symbol __stack_size__=0x4000; +define symbol __heap_size__=0x8000; + +define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x0007FFFF; + +define symbol m_interrupts_ram_start = 0x1FFF0000; +define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x1FFFFFFF; + +define symbol m_data_2_start = 0x20000000; +define symbol m_data_2_end = 0x2000FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end] + | mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S new file mode 100644 index 00000000000..32325af11b2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S @@ -0,0 +1,766 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MK22F51212.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; MK22F51212 +; @version: 1.7 +; @date: 2015-2-19 +; @build: b151105 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTF_IRQHandler ;FTFA Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD Reserved53_IRQHandler ;Reserved interrupt 53 + DCD Reserved54_IRQHandler ;Reserved interrupt 54 + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD Reserved61_IRQHandler ;Reserved interrupt 61 + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD Reserved70_IRQHandler ;Reserved interrupt 70 + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD Reserved81_IRQHandler ;Reserved interrupt 81 + DCD Reserved82_IRQHandler ;Reserved interrupt 82 + DCD Reserved83_IRQHandler ;Reserved interrupt 83 + DCD Reserved84_IRQHandler ;Reserved interrupt 84 + DCD Reserved85_IRQHandler ;Reserved interrupt 85 + DCD Reserved86_IRQHandler ;Reserved interrupt 86 + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD Reserved90_IRQHandler ;Reserved Interrupt 90 + DCD Reserved91_IRQHandler ;Reserved Interrupt 91 + DCD Reserved92_IRQHandler ;Reserved Interrupt 92 + DCD Reserved93_IRQHandler ;Reserved Interrupt 93 + DCD Reserved94_IRQHandler ;Reserved Interrupt 94 + DCD Reserved95_IRQHandler ;Reserved Interrupt 95 + DCD Reserved96_IRQHandler ;Reserved Interrupt 96 + DCD Reserved97_IRQHandler ;Reserved Interrupt 97 + DCD Reserved98_IRQHandler ;Reserved Interrupt 98 + DCD Reserved99_IRQHandler ;Reserved Interrupt 99 + DCD Reserved100_IRQHandler ;Reserved Interrupt 100 + DCD Reserved101_IRQHandler ;Reserved Interrupt 101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_IRQHandler + LDR R0, =DMA8_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_IRQHandler + LDR R0, =DMA9_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_IRQHandler + LDR R0, =DMA10_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_IRQHandler + LDR R0, =DMA11_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA12_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_IRQHandler + LDR R0, =DMA12_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA13_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_IRQHandler + LDR R0, =DMA13_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA14_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_IRQHandler + LDR R0, =DMA14_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA15_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_IRQHandler + LDR R0, =DMA15_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK MCM_IRQHandler + PUBWEAK FTF_IRQHandler + PUBWEAK Read_Collision_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RNG_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Tx_IRQHandler + PUBWEAK I2S0_Tx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Tx_IRQHandler + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Rx_IRQHandler + PUBWEAK I2S0_Rx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Rx_IRQHandler + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK UART0_RX_TX_IRQHandler + PUBWEAK UART0_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_RX_TX_IRQHandler + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART0_ERR_IRQHandler + PUBWEAK UART0_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_ERR_IRQHandler + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART1_RX_TX_IRQHandler + PUBWEAK UART1_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_RX_TX_IRQHandler + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART1_ERR_IRQHandler + PUBWEAK UART1_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_ERR_IRQHandler + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART2_RX_TX_IRQHandler + PUBWEAK UART2_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_RX_TX_IRQHandler + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART2_ERR_IRQHandler + PUBWEAK UART2_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_ERR_IRQHandler + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + + PUBWEAK Reserved53_IRQHandler + PUBWEAK Reserved54_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK FTM0_IRQHandler + PUBWEAK FTM1_IRQHandler + PUBWEAK FTM2_IRQHandler + PUBWEAK Reserved61_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK PIT1_IRQHandler + PUBWEAK PIT2_IRQHandler + PUBWEAK PIT3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK Reserved70_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK Reserved81_IRQHandler + PUBWEAK Reserved82_IRQHandler + PUBWEAK Reserved83_IRQHandler + PUBWEAK Reserved84_IRQHandler + PUBWEAK Reserved85_IRQHandler + PUBWEAK Reserved86_IRQHandler + PUBWEAK FTM3_IRQHandler + PUBWEAK DAC1_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK Reserved90_IRQHandler + PUBWEAK Reserved91_IRQHandler + PUBWEAK Reserved92_IRQHandler + PUBWEAK Reserved93_IRQHandler + PUBWEAK Reserved94_IRQHandler + PUBWEAK Reserved95_IRQHandler + PUBWEAK Reserved96_IRQHandler + PUBWEAK Reserved97_IRQHandler + PUBWEAK Reserved98_IRQHandler + PUBWEAK Reserved99_IRQHandler + PUBWEAK Reserved100_IRQHandler + PUBWEAK Reserved101_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTF_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +LPUART0_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +Reserved61_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +Reserved81_IRQHandler +Reserved82_IRQHandler +Reserved83_IRQHandler +Reserved84_IRQHandler +Reserved85_IRQHandler +Reserved86_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +Reserved90_IRQHandler +Reserved91_IRQHandler +Reserved92_IRQHandler +Reserved93_IRQHandler +Reserved94_IRQHandler +Reserved95_IRQHandler +Reserved96_IRQHandler +Reserved97_IRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis.h new file mode 100644 index 00000000000..7423a125ba6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "fsl_device_registers.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c new file mode 100644 index 00000000000..59b37502b22 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InstallIRQHandler(IRQn, vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h new file mode 100644 index 00000000000..45141f5e2c8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/fsl_device_registers.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/fsl_device_registers.h new file mode 100644 index 00000000000..2937b84bdf6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/fsl_device_registers.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ + defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12)) + +#define K22F51212_SERIES + +/* CMSIS-style register definitions */ +#include "MK22F51212.h" +/* CPU specific feature definitions */ +#include "MK22F51212_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.c new file mode 100755 index 00000000000..5c80378346a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.c @@ -0,0 +1,243 @@ +/* +** ################################################################### +** Processors: MK22FN512CAP12 +** MK22FN512VDC12 +** MK22FN512VLH12 +** MK22FN512VLL12 +** MK22FN512VMP12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151217 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-07-23) +** Initial version. +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) +** Update according to reference manual rev. 1.0, +** Update of system and startup files. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** +** ################################################################### +*/ + +/*! + * @file MK22F51212 + * @version 2.8 + * @date 2015-02-19 + * @brief Device specific configuration file for MK22F51212 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +#if (DISABLE_WDOG) + /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ + /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ + /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | + WDOG_STCTRLH_WAITEN_MASK | + WDOG_STCTRLH_STOPEN_MASK | + WDOG_STCTRLH_ALLOWUPDATE_MASK | + WDOG_STCTRLH_CLKSRC_MASK | + 0x0100U; +#endif /* (DISABLE_WDOG) */ + +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x00U: + MCGOUTClock *= 640U; + break; + case 0x20U: + MCGOUTClock *= 1280U; + break; + case 0x40U: + MCGOUTClock *= 1920U; + break; + case 0x60U: + MCGOUTClock *= 2560U; + break; + case 0x80U: + MCGOUTClock *= 732U; + break; + case 0xA0U: + MCGOUTClock *= 1464U; + break; + case 0xC0U: + MCGOUTClock *= 2197U; + break; + case 0xE0U: + MCGOUTClock *= 2929U; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + /* PLL is selected */ + Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.h new file mode 100755 index 00000000000..d6f7549cd44 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.h @@ -0,0 +1,164 @@ +/* +** ################################################################### +** Processors: MK22FN512CAP12 +** MK22FN512VDC12 +** MK22FN512VLH12 +** MK22FN512VLL12 +** MK22FN512VMP12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151217 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-07-23) +** Initial version. +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) +** Update according to reference manual rev. 1.0, +** Update of system and startup files. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** +** ################################################################### +*/ + +/*! + * @file MK22F51212 + * @version 2.8 + * @date 2015-02-19 + * @brief Device specific configuration file for MK22F51212 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MK22F51212_H_ +#define _SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ +#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ + +/* RTC oscillator setting */ +/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ +#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ + +/* Low power mode enable */ +/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */ + +#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MK22F51212_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h new file mode 100644 index 00000000000..a471a6be718 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_1 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_00 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_01 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_02 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_03 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_04 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_05 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_06 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_07 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_10 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_11 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_12 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_13 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_14 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_15 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_16 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_17 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_20 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_21 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_22 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_23 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_24 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_25 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_26 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_27 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_30 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_31 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_32 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_33 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_34 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_35 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_36 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_37 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, + ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, + ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, + ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, + ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, + ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, + ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, + ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, + ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, + ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, + ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, + ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, + ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, + ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, + ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c new file mode 100644 index 00000000000..50d938862f4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c @@ -0,0 +1,185 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTA17, ADC1_SE17, 0}, + {PTB0 , ADC0_SE8 , 0}, + {PTB1 , ADC0_SE9 , 0}, + {PTB2 , ADC0_SE12, 0}, + {PTB3 , ADC0_SE13, 0}, + {PTB6 , ADC1_SE12, 0}, + {PTB7 , ADC1_SE13, 0}, + {PTB10, ADC1_SE14, 0}, + {PTB11, ADC1_SE15, 0}, + {PTC0 , ADC0_SE14, 0}, + {PTC1 , ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10, ADC1_SE6b, 0}, + {PTC11, ADC1_SE7b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTE0, ADC1_SE4a, 0}, + {PTE1, ADC1_SE5a, 0}, + {PTE2, ADC1_SE6a, 0}, + {PTE3, ADC1_SE7a, 0}, + //{PTE24, ADC0_SE17, 0}, //I2C pull up + //{PTE25, ADC0_SE18, 0}, //I2C pull up + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1 , I2C_0 , 2}, + {PTB3 , I2C_0 , 2}, + {PTC11, I2C_1 , 2}, + {PTD3 , I2C_0 , 7}, + {PTD9 , I2C_0 , 2}, + {PTE0 , I2C_1 , 6}, + {PTE25, I2C_0 , 5}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0 , I2C_0 , 2}, + {PTB2 , I2C_0 , 2}, + {PTC10, I2C_1 , 2}, + {PTD2 , I2C_0 , 7}, + {PTD8 , I2C_0 , 2}, + {PTE1 , I2C_1 , 6}, + {PTE24, I2C_0 , 5}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTA2 , UART_0, 2}, + {PTA14, UART_0, 3}, + {PTB17, UART_0, 3}, + {PTD7 , UART_0, 3}, + {PTC4 , UART_1, 3}, + {PTE0 , UART_1, 3}, + {PTD3 , UART_2, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTA1 , UART_0, 2}, + {PTA15, UART_0, 3}, + {PTB16, UART_0, 3}, + {PTD6 , UART_0, 3}, + {PTC3 , UART_1, 3}, + {PTE1 , UART_1, 3}, + {PTD2 , UART_2, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTD1 , SPI_0, 2}, + {PTE2 , SPI_1, 2}, + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTC5 , SPI_0, 2}, + {PTD5 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2 , SPI_0, 2}, + {PTE1 , SPI_1, 2}, + {PTE3 , SPI_1, 7}, + {PTA16, SPI_0, 2}, + {PTB16, SPI_1, 2}, + {PTC6 , SPI_0, 2}, + {PTD6 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3 , SPI_0, 2}, + {PTE1 , SPI_1, 7}, + {PTE3 , SPI_1, 2}, + {PTA17, SPI_0, 2}, + {PTB17, SPI_1, 2}, + {PTC7 , SPI_0, 2}, + {PTD7 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0 , SPI_0, 2}, + {PTE4 , SPI_1, 2}, + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTC4 , SPI_0, 2}, + {PTD4 , SPI_1, 7}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0 , PWM_05, 3}, + {PTA1 , PWM_06, 3}, + {PTA2 , PWM_07, 3}, + {PTA3 , PWM_00, 3}, + {PTA4 , PWM_01, 3}, + {PTA5 , PWM_02, 3}, + {PTA10, PWM_20, 3}, + {PTA11, PWM_21, 3}, + {PTA12, PWM_10, 3}, + {PTA13, PWM_11, 3}, + + {PTB0 , PWM_10, 3}, + {PTB1 , PWM_11, 3}, + {PTB18, PWM_20, 3}, + {PTB19, PWM_21, 3}, + + {PTC1 , PWM_00, 4}, + {PTC2 , PWM_01, 4}, + {PTC3 , PWM_02, 4}, + {PTC4 , PWM_03, 4}, + {PTC5 , PWM_02, 7}, + + {PTD0 , PWM_30, 4}, + {PTD1 , PWM_31, 4}, + {PTD2 , PWM_32, 4}, + {PTD3 , PWM_33, 4}, + {PTD4 , PWM_04, 4}, + {PTD5 , PWM_05, 4}, + {PTD6 , PWM_06, 4}, + {PTD7 , PWM_07, 4}, + + {PTE5 , PWM_30, 6}, + {PTE6 , PWM_31, 6}, + {NC , NC , 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h new file mode 100644 index 00000000000..c18628ff11a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h @@ -0,0 +1,259 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), + PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), + PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), + PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTA22 = (0 << GPIO_PORT_SHIFT | 22), + PTA23 = (0 << GPIO_PORT_SHIFT | 23), + PTA24 = (0 << GPIO_PORT_SHIFT | 24), + PTA25 = (0 << GPIO_PORT_SHIFT | 25), + PTA26 = (0 << GPIO_PORT_SHIFT | 26), + PTA27 = (0 << GPIO_PORT_SHIFT | 27), + PTA28 = (0 << GPIO_PORT_SHIFT | 28), + PTA29 = (0 << GPIO_PORT_SHIFT | 29), + PTA30 = (0 << GPIO_PORT_SHIFT | 30), + PTA31 = (0 << GPIO_PORT_SHIFT | 31), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), + PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), + PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), + PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), + PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), + PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB12 = (1 << GPIO_PORT_SHIFT | 12), + PTB13 = (1 << GPIO_PORT_SHIFT | 13), + PTB14 = (1 << GPIO_PORT_SHIFT | 14), + PTB15 = (1 << GPIO_PORT_SHIFT | 15), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTB24 = (1 << GPIO_PORT_SHIFT | 24), + PTB25 = (1 << GPIO_PORT_SHIFT | 25), + PTB26 = (1 << GPIO_PORT_SHIFT | 26), + PTB27 = (1 << GPIO_PORT_SHIFT | 27), + PTB28 = (1 << GPIO_PORT_SHIFT | 28), + PTB29 = (1 << GPIO_PORT_SHIFT | 29), + PTB30 = (1 << GPIO_PORT_SHIFT | 30), + PTB31 = (1 << GPIO_PORT_SHIFT | 31), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTC20 = (2 << GPIO_PORT_SHIFT | 20), + PTC21 = (2 << GPIO_PORT_SHIFT | 21), + PTC22 = (2 << GPIO_PORT_SHIFT | 22), + PTC23 = (2 << GPIO_PORT_SHIFT | 23), + PTC24 = (2 << GPIO_PORT_SHIFT | 24), + PTC25 = (2 << GPIO_PORT_SHIFT | 25), + PTC26 = (2 << GPIO_PORT_SHIFT | 26), + PTC27 = (2 << GPIO_PORT_SHIFT | 27), + PTC28 = (2 << GPIO_PORT_SHIFT | 28), + PTC29 = (2 << GPIO_PORT_SHIFT | 29), + PTC30 = (2 << GPIO_PORT_SHIFT | 30), + PTC31 = (2 << GPIO_PORT_SHIFT | 31), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), + PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), + PTD10 = (3 << GPIO_PORT_SHIFT | 10), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTD15 = (3 << GPIO_PORT_SHIFT | 15), + PTD16 = (3 << GPIO_PORT_SHIFT | 16), + PTD17 = (3 << GPIO_PORT_SHIFT | 17), + PTD18 = (3 << GPIO_PORT_SHIFT | 18), + PTD19 = (3 << GPIO_PORT_SHIFT | 19), + PTD20 = (3 << GPIO_PORT_SHIFT | 20), + PTD21 = (3 << GPIO_PORT_SHIFT | 21), + PTD22 = (3 << GPIO_PORT_SHIFT | 22), + PTD23 = (3 << GPIO_PORT_SHIFT | 23), + PTD24 = (3 << GPIO_PORT_SHIFT | 24), + PTD25 = (3 << GPIO_PORT_SHIFT | 25), + PTD26 = (3 << GPIO_PORT_SHIFT | 26), + PTD27 = (3 << GPIO_PORT_SHIFT | 27), + PTD28 = (3 << GPIO_PORT_SHIFT | 28), + PTD29 = (3 << GPIO_PORT_SHIFT | 29), + PTD30 = (3 << GPIO_PORT_SHIFT | 30), + PTD31 = (3 << GPIO_PORT_SHIFT | 31), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), + PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), + PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), + PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), + PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), + PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), + PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), + PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE14 = (4 << GPIO_PORT_SHIFT | 14), + PTE15 = (4 << GPIO_PORT_SHIFT | 15), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE26 = (4 << GPIO_PORT_SHIFT | 26), + PTE27 = (4 << GPIO_PORT_SHIFT | 27), + PTE28 = (4 << GPIO_PORT_SHIFT | 28), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + LED_RED = PTA1, + LED_GREEN = PTA2, + LED_BLUE = PTD5, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + //Push buttons + SW2 = PTC1, + SW3 = PTB17, + + // USB Pins + USBTX = PTE0, + USBRX = PTE1, + + // Arduino Headers + + D0 = PTD2, + D1 = PTD3, + D2 = PTB16, + D3 = PTA2, + D4 = PTA4, + D5 = PTB18, + D6 = PTC3, + D7 = PTC6, + D8 = PTB19, + D9 = PTA1, + D10 = PTD4, + D11 = PTD6, + D12 = PTD7, + D13 = PTD5, + D14 = PTE0, + D15 = PTE1, + + I2C_SCL = D15, + I2C_SDA = D14, + + A0 = PTB0, + A1 = PTB1, + A2 = PTC1, + A3 = PTC2, + A4 = PTB3, + A5 = PTB2, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h new file mode 100644 index 00000000000..8f3ef7e1252 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c new file mode 100755 index 00000000000..3204d12bfb6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 80MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k.*/ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 3U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x3U, .vdiv = 0x10U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01230000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 80000000U, /* Core clock frequency */ +}; + +/* Configuration for HSRUN mode. Core clock = 120MHz. */ +const clock_config_t g_defaultClockConfigHsrun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 3U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x1U, .vdiv = 0x6U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01340000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 120000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} + +void BOARD_BootClockHSRUN(void) +{ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeHsrun(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) + { + } + + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigHsrun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode, + g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig); + + SystemCoreClock = g_defaultClockConfigHsrun.coreClock; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h new file mode 100755 index 00000000000..7b1ca9924d4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 8000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); +void BOARD_BootClockHSRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c new file mode 100644 index 00000000000..d518bef3181 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "fsl_clock_config.h" + +// called before main - implement here if board needs it otherwise, let +// the application override this if necessary +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); + pin_function(PTA2, 1); //By default the GREEN LED is enabled. This disables it +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c new file mode 100755 index 00000000000..8f1aa77b2ea --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc16.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC16 module. + * + * @param base ADC16 peripheral base address + */ +static uint32_t ADC16_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC16 bases for each instance. */ +static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; + +/*! @brief Pointers to ADC16 clocks for each instance. */ +const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC16_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++) + { + if (s_adc16Bases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_ADC16_COUNT); + + return instance; +} + +void ADC16_Init(ADC_Type *base, const adc16_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Enable the clock. */ + CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); + + /* ADCx_CFG1. */ + tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG1_ADLSMP_MASK; + } + tmp32 |= ADC_CFG1_ADIV(config->clockDivider); + if (config->enableLowPower) + { + tmp32 |= ADC_CFG1_ADLPC_MASK; + } + base->CFG1 = tmp32; + + /* ADCx_CFG2. */ + tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG2_ADHSC_MASK; + } + if (config->enableAsynchronousClock) + { + tmp32 |= ADC_CFG2_ADACKEN_MASK; + } + base->CFG2 = tmp32; + + /* ADCx_SC2. */ + tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); + tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); + base->SC2 = tmp32; + + /* ADCx_SC3. */ + if (config->enableContinuousConversion) + { + base->SC3 |= ADC_SC3_ADCO_MASK; + } + else + { + base->SC3 &= ~ADC_SC3_ADCO_MASK; + } +} + +void ADC16_Deinit(ADC_Type *base) +{ + /* Disable the clock. */ + CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +} + +void ADC16_GetDefaultConfig(adc16_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + config->clockSource = kADC16_ClockSourceAsynchronousClock; + config->enableAsynchronousClock = true; + config->clockDivider = kADC16_ClockDivider8; + config->resolution = kADC16_ResolutionSE12Bit; + config->longSampleMode = kADC16_LongSampleDisabled; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableContinuousConversion = false; +} + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +status_t ADC16_DoAutoCalibration(ADC_Type *base) +{ + bool bHWTrigger = false; + uint32_t tmp32; + status_t status = kStatus_Success; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) + { + bHWTrigger = true; + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } + + /* Clear the CALF and launch the calibration. */ + base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; + while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) + { + /* Check the CALF when the calibration is active. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + break; + } + } + + /* Restore the hardware trigger setting if it was enabled before. */ + if (bHWTrigger) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + /* Check the CALF at the end of calibration. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + } + if (kStatus_Success != status) /* Check if the calibration process is succeed. */ + { + return status; + } + + /* Calculate the calibration values. */ + tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->PG = tmp32; + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->MG = tmp32; +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + + return kStatus_Success; +} +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) +{ + if (kADC16_ChannelMuxA == mode) + { + base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; + } + else /* kADC16_ChannelMuxB. */ + { + base->CFG2 |= ADC_CFG2_MUXSEL_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) +{ + uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); + + if (!config) /* Pass "NULL" to disable the feature. */ + { + base->SC2 = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_SC2_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC16_HardwareCompareMode0: + break; + case kADC16_HardwareCompareMode1: + tmp32 |= ADC_SC2_ACFGT_MASK; + break; + case kADC16_HardwareCompareMode2: + tmp32 |= ADC_SC2_ACREN_MASK; + break; + case kADC16_HardwareCompareMode3: + tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; + break; + default: + break; + } + base->SC2 = tmp32; + + /* Load the compare values. */ + base->CV1 = ADC_CV1_CV(config->value1); + base->CV2 = ADC_CV2_CV(config->value2); +} + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) +{ + uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); + + if (kADC16_HardwareAverageDisabled != mode) + { + tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); + } + base->SC3 = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) +{ + uint32_t tmp32; + + if (!config) /* Passing "NULL" is to disable the feature. */ + { + base->PGA = 0U; + return; + } + + /* Enable the PGA and set the gain value. */ + tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); + + /* Configure the misc features for PGA. */ + if (config->enableRunInNormalMode) + { + tmp32 |= ADC_PGA_PGALPb_MASK; + } +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + if (config->disablePgaChopping) + { + tmp32 |= ADC_PGA_PGACHPb_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + if (config->enableRunInOffsetMeasurement) + { + tmp32 |= ADC_PGA_PGAOFSM_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ + base->PGA = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +uint32_t ADC16_GetStatusFlags(ADC_Type *base) +{ + uint32_t ret = 0; + + if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) + { + ret |= kADC16_ActiveFlag; + } +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) + { + ret |= kADC16_CalibrationFailedFlag; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + return ret; +} + +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (mask & kADC16_CalibrationFailedFlag)) + { + base->SC3 |= ADC_SC3_CALF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +} + +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) +{ + assert(channelGroup < ADC_SC1_COUNT); + assert(NULL != config); + + uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + /* Enable the differential conversion. */ + if (config->enableDifferentialConversion) + { + sc1 |= ADC_SC1_DIFF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + /* Enable the interrupt when the conversion is done. */ + if (config->enableInterruptOnConversionCompleted) + { + sc1 |= ADC_SC1_AIEN_MASK; + } + base->SC1[channelGroup] = sc1; +} + +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_SC1_COUNT); + + uint32_t ret = 0U; + + if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) + { + ret |= kADC16_ChannelConversionDoneFlag; + } + return ret; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h new file mode 100755 index 00000000000..c6b5bc0d1ae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC16_H_ +#define _FSL_ADC16_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc16 + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ADC16 driver version 2.0.0. */ +#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Channel status flags. + */ +enum _adc16_channel_status_flags +{ + kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ +}; + +/*! + * @brief Converter status flags. + */ +enum _adc16_status_flags +{ + kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +}; + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Channel multiplexer mode for each channel. + * + * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b + * are the different channels but share the same channel number. + */ +typedef enum _adc_channel_mux_mode +{ + kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ + kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ +} adc16_channel_mux_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc16_clock_divider +{ + kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc16_clock_divider_t; + +/*! + *@brief Converter's resolution. + */ +typedef enum _adc16_resolution +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ + kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ + kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ + + /* This group of enumeration is for public user. */ + kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ + kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ + kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ + kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ + kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + +#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) + /* 16-bit is supported by default. */ + kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ + kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ +} adc16_resolution_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc16_clock_source +{ + kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ + kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ + kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ + kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ + + /* Chip defined clock source */ + kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ +} adc16_clock_source_t; + +/*! + * @brief Long sample mode. + */ +typedef enum _adc16_long_sample_mode +{ + kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ + kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ + kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ + kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ + kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ +} adc16_long_sample_mode_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc16_reference_voltage_source +{ + kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ + kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ +} adc16_reference_voltage_source_t; + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Hardware average mode. + */ +typedef enum _adc16_hardware_average_mode +{ + kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ +} adc16_hardware_average_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +/*! + * @brief Hardware compare mode. + */ +typedef enum _adc16_hardware_compare_mode +{ + kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ + kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ + kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; + else, value1 > x > value2. */ + kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; + else x >= value1 || x <= value2. */ +} adc16_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief PGA's Gain mode. + */ +typedef enum _adc16_pga_gain +{ + kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ + kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ + kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ + kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ + kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ + kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ + kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ +} adc16_pga_gain_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief ADC16 converter configuration . + */ +typedef struct _adc16_config +{ + adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ + bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ + adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ + adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ + adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable low power. */ + bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ +} adc16_config_t; + +/*! + * @brief ADC16 Hardware compare configuration. + */ +typedef struct _adc16_hardware_compare_config +{ + adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc16_hardware_compare_mode_t". */ + int16_t value1; /*!< Setting value1 for hardware compare mode. */ + int16_t value2; /*!< Setting value2 for hardware compare mode. */ +} adc16_hardware_compare_config_t; + +/*! + * @brief ADC16 channel conversion configuration. + */ +typedef struct _adc16_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + bool enableDifferentialConversion; /*!< Using Differential sample mode. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +} adc16_channel_config_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief ADC16 programmable gain amplifier configuration. + */ +typedef struct _adc16_pga_config +{ + adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ + bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + bool disablePgaChopping; /*!< Disable the PGA chopping function. + The PGA employs chopping to remove/reduce offset and 1/f noise and offers + an offset measurement configuration that aids the offset calibration. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. + When this feature is enabled, the PGA disconnects itself from the external + inputs and auto-configures into offset measurement mode. With this field + set, run the ADC in the recommended settings and enable the maximum hardware + averaging to get the PGA offset number. The output is the + (PGA offset * (64+1)) for the given PGA setting. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ +} adc16_pga_config_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to configuration structure. See "adc16_config_t". + */ +void ADC16_Init(ADC_Type *base, const adc16_config_t *config); + +/*! + * @brief De-initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + */ +void ADC16_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for converter's configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + * config->clockSource = kADC16_ClockSourceAsynchronousClock; + * config->enableAsynchronousClock = true; + * config->clockDivider = kADC16_ClockDivider8; + * config->resolution = kADC16_ResolutionSE12Bit; + * config->longSampleMode = kADC16_LongSampleDisabled; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableContinuousConversion = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void ADC16_GetDefaultConfig(adc16_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation. + * Execute the calibration before using the converter. Note that the hardware trigger should be used + * during calibration. + * + * @param base ADC16 peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration is failed. + */ +status_t ADC16_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION +/*! + * @brief Sets the offset value for the conversion result. + * + * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result + * is subtracted by it. Note, the hardware calibration fills the offset value automatically. + * + * @param base ADC16 peripheral base address. + * @param value Setting offset value. + */ +static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFS = (uint32_t)(value); +} +#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ + +/* @} */ + +/*! + * @name Advanced Feature + * @{ + */ + +#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA +/*! + * @brief Enables generating the DMA trigger when conversion is completed. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of DMA feature. "true" means to enable, "false" means not. + */ +static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_DMAEN_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_DMAEN_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_DMA */ + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not. + */ +static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } +} + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Sets the channel mux mode. + * + * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an + * indicated channel. + * + * @param base ADC16 peripheral base address. + * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". + */ +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result + * in + * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference + * manual document for more detailed information. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature. + */ +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Sets the hardware average mode. + * + * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple + * conversion results are accumulated and averaged internally. This aids reading results. + * + * @param base ADC16 peripheral base address. + * @param mode Setting hardware average mode. See "adc16_hardware_average_mode_t". + */ +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief Configures the PGA for converter's front end. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature. + */ +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief Gets the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". + */ +uint32_t ADC16_GetStatusFlags(ADC_Type *base); + +/*! + * @brief Clears the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * @param mask Mask value for the cleared flags. See "_adc16_status_flags". + */ +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Conversion Channel + * @{ + */ + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one + * group of status and control register, one for each conversion. The channel group parameter indicates which group of + * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware + * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion. + * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to "adc16_channel_config_t" structure for conversion channel. + */ +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". + */ +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_ADC16_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c new file mode 100755 index 00000000000..476eeb3cd19 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c @@ -0,0 +1,1782 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Macro definition remap workaround. */ +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#endif +#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#endif +#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK))) +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#endif +#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK))) +#define MCG_C6_CME0_MASK MCG_C6_CME_MASK +#endif + +/* PLL fixed multiplier when there is not PRDIV and VDIV. */ +#define PLL_FIXED_MULT (375U) +/* Max frequency of the reference clock used for internal clock trim. */ +#define TRIM_REF_CLK_MIN (8000000U) +/* Min frequency of the reference clock used for internal clock trim. */ +#define TRIM_REF_CLK_MAX (16000000U) +/* Max trim value of fast internal reference clock. */ +#define TRIM_FIRC_MAX (5000000U) +/* Min trim value of fast internal reference clock. */ +#define TRIM_FIRC_MIN (3000000U) +/* Max trim value of fast internal reference clock. */ +#define TRIM_SIRC_MAX (39063U) +/* Min trim value of fast internal reference clock. */ +#define TRIM_SIRC_MIN (31250U) + +#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT) +#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) +#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT) +#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) +#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) +#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) +#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) +#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) +#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) +#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) +#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) +#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) +#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) +#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) +#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) +#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) +#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) +#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) +#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) + +#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) + +#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) +#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) +#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT) +#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) +#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) +#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) + +/* MCG_S_CLKST definition. */ +enum _mcg_clkout_stat +{ + kMCG_ClkOutStatFll, /* FLL. */ + kMCG_ClkOutStatInt, /* Internal clock. */ + kMCG_ClkOutStatExt, /* External clock. */ + kMCG_ClkOutStatPll /* PLL. */ +}; + +/* MCG_S_PLLST definition. */ +enum _mcg_pllst +{ + kMCG_PllstFll, /* FLL is used. */ + kMCG_PllstPll /* PLL is used. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Slow internal reference clock frequency. */ +static uint32_t s_slowIrcFreq = 32768U; +/* Fast internal reference clock frequency. */ +static uint32_t s_fastIrcFreq = 4000000U; + +/* External XTAL0 (OSC0) clock frequency. */ +uint32_t g_xtal0Freq; + +/* External XTAL32K clock frequency. */ +uint32_t g_xtal32Freq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the MCG external reference clock frequency. + * + * Get the current MCG external reference clock frequency in Hz. It is + * the frequency select by MCG_C7[OSCSEL]. This is an internal function. + * + * @return MCG external reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetMcgExtClkFreq(void); + +/*! + * @brief Get the MCG FLL external reference clock frequency. + * + * Get the current MCG FLL external reference clock frequency in Hz. It is + * the frequency after by MCG_C1[FRDIV]. This is an internal function. + * + * @return MCG FLL external reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetFllExtRefClkFreq(void); + +/*! + * @brief Get the MCG FLL reference clock frequency. + * + * Get the current MCG FLL reference clock frequency in Hz. It is + * the frequency select by MCG_C1[IREFS]. This is an internal function. + * + * @return MCG FLL reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetFllRefClkFreq(void); + +/*! + * @brief Get the frequency of clock selected by MCG_C2[IRCS]. + * + * This clock's two output: + * 1. MCGOUTCLK when MCG_S[CLKST]=0. + * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1. + * + * @return The frequency in Hz. + */ +static uint32_t CLOCK_GetInternalRefClkSelectFreq(void); + +/*! + * @brief Get the MCG PLL/PLL0 reference clock frequency. + * + * Get the current MCG PLL/PLL0 reference clock frequency in Hz. + * This is an internal function. + * + * @return MCG PLL/PLL0 reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetPll0RefFreq(void); + +/*! + * @brief Calculate the RANGE value base on crystal frequency. + * + * To setup external crystal oscillator, must set the register bits RANGE + * base on the crystal frequency. This function returns the RANGE base on the + * input frequency. This is an internal function. + * + * @param freq Crystal frequency in Hz. + * @return The RANGE value. + */ +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); + +/*! + * @brief Delay function to wait FLL stable. + * + * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least + * 1ms. Every time changes FLL setting, should wait this time for FLL stable. + */ +static void CLOCK_FllStableDelay(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetMcgExtClkFreq(void) +{ + uint32_t freq; + + switch (MCG_C7_OSCSEL_VAL) + { + case 0U: + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + freq = g_xtal0Freq; + break; + case 1U: + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 2U: + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +static uint32_t CLOCK_GetFllExtRefClkFreq(void) +{ + /* FllExtRef = McgExtRef / FllExtRefDiv */ + uint8_t frdiv; + uint8_t range; + uint8_t oscsel; + + uint32_t freq = CLOCK_GetMcgExtClkFreq(); + + if (!freq) + { + return freq; + } + + frdiv = MCG_C1_FRDIV_VAL; + freq >>= frdiv; + + range = MCG_C2_RANGE_VAL; + oscsel = MCG_C7_OSCSEL_VAL; + + /* + When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. + 1. MCG_C7[OSCSEL] selects IRC48M. + 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. + */ + if (((0U != range) && (kMCG_OscselOsc == oscsel)) || (kMCG_OscselIrc == oscsel)) + { + switch (frdiv) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + freq >>= 5u; + break; + case 6: + /* 64*20=1280 */ + freq /= 20u; + break; + case 7: + /* 128*12=1536 */ + freq /= 12u; + break; + default: + freq = 0u; + break; + } + } + + return freq; +} + +static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) +{ + if (kMCG_IrcSlow == MCG_S_IRCST_VAL) + { + /* Slow internal reference clock selected*/ + return s_slowIrcFreq; + } + else + { + /* Fast internal reference clock selected*/ + return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; + } +} + +static uint32_t CLOCK_GetFllRefClkFreq(void) +{ + /* If use external reference clock. */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + return CLOCK_GetFllExtRefClkFreq(); + } + /* If use internal reference clock. */ + else + { + return s_slowIrcFreq; + } +} + +static uint32_t CLOCK_GetPll0RefFreq(void) +{ + /* MCG external reference clock. */ + return CLOCK_GetMcgExtClkFreq(); +} + +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) +{ + uint8_t range; + + if (freq <= 39063U) + { + range = 0U; + } + else if (freq <= 8000000U) + { + range = 1U; + } + else + { + range = 2U; + } + + return range; +} + +static void CLOCK_FllStableDelay(void) +{ + /* + Should wait at least 1ms. Because in these modes, the core clock is 100MHz + at most, so this function could obtain the 1ms delay. + */ + volatile uint32_t i = 30000U; + while (i--) + { + __NOP(); + } +} + +uint32_t CLOCK_GetOsc0ErClkUndivFreq(void) +{ + if (OSC0->CR & OSC_CR_ERCLKEN_MASK) + { + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + return g_xtal0Freq; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetOsc0ErClkDivFreq(void) +{ + if (OSC0->CR & OSC_CR_ERCLKEN_MASK) + { + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + return g_xtal0Freq >> ((OSC0->DIV & OSC_DIV_ERPS_MASK) >> OSC_DIV_ERPS_SHIFT); + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetEr32kClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT1_OSC32KSEL_VAL) + { + case 0U: /* OSC 32k clock */ + freq = (CLOCK_GetOsc0ErClkUndivFreq() == 32768U) ? 32768U : 0U; + break; + case 2U: /* RTC 32k clock */ + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 3U: /* LPO clock */ + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; + } + return freq; +} + +uint32_t CLOCK_GetPllFllSelClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT2_PLLFLLSEL_VAL) + { + case 0U: /* FLL. */ + freq = CLOCK_GetFllFreq(); + break; + case 1U: /* PLL. */ + freq = CLOCK_GetPll0Freq(); + break; + case 3U: /* MCG IRC48M. */ + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +uint32_t CLOCK_GetOsc0ErClkFreq(void) +{ + return CLOCK_GetOsc0ErClkDivFreq(); +} + +uint32_t CLOCK_GetPlatClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFlashClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); +} + +uint32_t CLOCK_GetFlexBusClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); +} + +uint32_t CLOCK_GetBusClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); +} + +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + case kCLOCK_PlatClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); + break; + case kCLOCK_FlexBusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); + break; + case kCLOCK_FlashClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); + break; + case kCLOCK_PllFllSelClk: + freq = CLOCK_GetPllFllSelClkFreq(); + break; + case kCLOCK_Er32kClk: + freq = CLOCK_GetEr32kClkFreq(); + break; + case kCLOCK_McgFixedFreqClk: + freq = CLOCK_GetFixedFreqClkFreq(); + break; + case kCLOCK_McgInternalRefClk: + freq = CLOCK_GetInternalRefClkFreq(); + break; + case kCLOCK_McgFllClk: + freq = CLOCK_GetFllFreq(); + break; + case kCLOCK_McgPll0Clk: + freq = CLOCK_GetPll0Freq(); + break; + case kCLOCK_McgIrc48MClk: + freq = MCG_INTERNAL_IRC_48M; + break; + case kCLOCK_LpoClk: + freq = LPO_CLK_FREQ; + break; + case kCLOCK_Osc0ErClkUndiv: + freq = CLOCK_GetOsc0ErClkUndivFreq(); + break; + case kCLOCK_Osc0ErClk: + freq = CLOCK_GetOsc0ErClkDivFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_SetSimConfig(sim_clock_config_t const *config) +{ + SIM->CLKDIV1 = config->clkdiv1; + CLOCK_SetPllFllSelClock(config->pllFllSel); + CLOCK_SetEr32kClock(config->er32kSrc); +} + +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcExt == src) + { + SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; + } + else + { + switch (freq) + { + case 120000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); + break; + case 96000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); + break; + case 72000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); + break; + case 48000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); + break; + default: + ret = false; + break; + } + + SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); + } + + CLOCK_EnableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcIrc48M == src) + { + USB0->CLK_RECOVER_IRC_EN = 0x03U; + USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; + } + return ret; +} + +uint32_t CLOCK_GetOutClkFreq(void) +{ + uint32_t mcgoutclk; + uint32_t clkst = MCG_S_CLKST_VAL; + + switch (clkst) + { + case kMCG_ClkOutStatPll: + mcgoutclk = CLOCK_GetPll0Freq(); + break; + case kMCG_ClkOutStatFll: + mcgoutclk = CLOCK_GetFllFreq(); + break; + case kMCG_ClkOutStatInt: + mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); + break; + case kMCG_ClkOutStatExt: + mcgoutclk = CLOCK_GetMcgExtClkFreq(); + break; + default: + mcgoutclk = 0U; + break; + } + return mcgoutclk; +} + +uint32_t CLOCK_GetFllFreq(void) +{ + static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; + + uint8_t drs, dmx32; + uint32_t freq; + + /* If FLL is not enabled currently, then return 0U. */ + if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) + { + return 0U; + } + + /* Get FLL reference clock frequency. */ + freq = CLOCK_GetFllRefClkFreq(); + if (!freq) + { + return freq; + } + + drs = MCG_C4_DRST_DRS_VAL; + dmx32 = MCG_C4_DMX32_VAL; + + return freq * fllFactorTable[drs][dmx32]; +} + +uint32_t CLOCK_GetInternalRefClkFreq(void) +{ + /* If MCGIRCLK is gated. */ + if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) + { + return 0U; + } + + return CLOCK_GetInternalRefClkSelectFreq(); +} + +uint32_t CLOCK_GetFixedFreqClkFreq(void) +{ + uint32_t freq = CLOCK_GetFllRefClkFreq(); + + /* MCGFFCLK must be no more than MCGOUTCLK/8. */ + if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U))) + { + return freq; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetPll0Freq(void) +{ + uint32_t mcgpll0clk; + + /* If PLL0 is not enabled, return 0. */ + if (!(MCG->S & MCG_S_LOCK0_MASK)) + { + return 0U; + } + + mcgpll0clk = CLOCK_GetPll0RefFreq(); + + mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); + mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); + + return mcgpll0clk; +} + +status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) +{ + bool needDelay; + uint32_t i; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ + if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) + { + return kStatus_MCG_SourceUsed; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + if (MCG_C7_OSCSEL_VAL != oscsel) + { + /* If change OSCSEL, need to delay, ERR009878. */ + needDelay = true; + } + else + { + needDelay = false; + } + + MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); + if (kMCG_OscselOsc == oscsel) + { + if (MCG->C2 & MCG_C2_EREFS_MASK) + { + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } + } + + if (needDelay) + { + /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ + i = 1500U; + while (i--) + { + __NOP(); + } + } + + return kStatus_Success; +} + +status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) +{ + uint32_t mcgOutClkState = MCG_S_CLKST_VAL; + mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL; + uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + /* If MCGIRCLK is used as system clock source. */ + if (kMCG_ClkOutStatInt == mcgOutClkState) + { + /* If need to change MCGIRCLK source or driver, return error. */ + if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) + { + return kStatus_MCG_SourceUsed; + } + } +#endif + + /* If need to update the FCRDIV. */ + if (fcrdiv != curFcrdiv) + { + /* If fast IRC is in use currently, change to slow IRC. */ + if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK))) + { + MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); + while (MCG_S_IRCST_VAL != kMCG_IrcSlow) + { + } + } + /* Update FCRDIV. */ + MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); + } + + /* Set internal reference clock selection. */ + MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); + MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; + + /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ + if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) + { + while (MCG_S_IRCST_VAL != ircs) + { + } + } + + return kStatus_Success; +} + +uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) +{ + uint8_t ret_prdiv; /* PRDIV to return. */ + uint8_t ret_vdiv; /* VDIV to return. */ + uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */ + uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */ + uint8_t prdiv_cur; /* PRDIV value for iteration. */ + uint8_t vdiv_cur; /* VDIV value for iteration. */ + uint32_t ret_freq = 0U; /* PLL output fequency to return. */ + uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ + uint32_t ref_div; /* Reference frequency after PRDIV. */ + + /* + Steps: + 1. Get allowed prdiv with such rules: + 1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN. + 2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX. + 2. For each allowed prdiv, there are two candidate vdiv values: + 1). (desireFreq / (refFreq / prdiv)). + 2). (desireFreq / (refFreq / prdiv)) + 1. + If could get the precise desired frequency, return current prdiv and + vdiv directly. Otherwise choose the one which is closer to desired + frequency. + */ + + /* Reference frequency is out of range. */ + if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) || + (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) + { + return 0U; + } + + /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */ + prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN; + prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX; + + /* PRDIV traversal. */ + for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) + { + /* Reference frequency after PRDIV. */ + ref_div = refFreq / prdiv_cur; + + vdiv_cur = desireFreq / ref_div; + + if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) + { + /* No VDIV is available with this PRDIV. */ + continue; + } + + ret_freq = vdiv_cur * ref_div; + + if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) + { + if (ret_freq == desireFreq) /* If desire frequency is got. */ + { + *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; + return ret_freq; + } + /* New PRDIV/VDIV is closer. */ + if (diff > desireFreq - ret_freq) + { + diff = desireFreq - ret_freq; + ret_prdiv = prdiv_cur; + ret_vdiv = vdiv_cur; + } + } + vdiv_cur++; + if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) + { + ret_freq += ref_div; + /* New PRDIV/VDIV is closer. */ + if (diff > ret_freq - desireFreq) + { + diff = ret_freq - desireFreq; + ret_prdiv = prdiv_cur; + ret_vdiv = vdiv_cur; + } + } + } + + if (0xFFFFFFFFU != diff) + { + /* PRDIV/VDIV found. */ + *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; + ret_freq = (refFreq / ret_prdiv) * ret_vdiv; + return ret_freq; + } + else + { + /* No proper PRDIV/VDIV found. */ + return 0U; + } +} + +void CLOCK_EnablePll0(mcg_pll_config_t const *config) +{ + assert(config); + + uint8_t mcg_c5 = 0U; + + mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); + MCG->C5 = mcg_c5; /* Disable the PLL first. */ + + MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); + + /* Set enable mode. */ + MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); + + /* Wait for PLL lock. */ + while (!(MCG->S & MCG_S_LOCK0_MASK)) + { + } +} + +void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) +{ + /* Clear the previous flag, MCG_SC[LOCS0]. */ + MCG->SC &= ~MCG_SC_ATMF_MASK; + + if (kMCG_MonitorNone == mode) + { + MCG->C6 &= ~MCG_C6_CME0_MASK; + } + else + { + if (kMCG_MonitorInt == mode) + { + MCG->C2 &= ~MCG_C2_LOCRE0_MASK; + } + else + { + MCG->C2 |= MCG_C2_LOCRE0_MASK; + } + MCG->C6 |= MCG_C6_CME0_MASK; + } +} + +void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) +{ + uint8_t mcg_c8 = MCG->C8; + + mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); + + if (kMCG_MonitorNone != mode) + { + if (kMCG_MonitorReset == mode) + { + mcg_c8 |= MCG_C8_LOCRE1_MASK; + } + mcg_c8 |= MCG_C8_CME1_MASK; + } + MCG->C8 = mcg_c8; +} + +void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) +{ + uint8_t mcg_c8; + + /* Clear previous flag. */ + MCG->S = MCG_S_LOLS0_MASK; + + if (kMCG_MonitorNone == mode) + { + MCG->C6 &= ~MCG_C6_LOLIE0_MASK; + } + else + { + mcg_c8 = MCG->C8; + + mcg_c8 &= ~MCG_C8_LOCS1_MASK; + + if (kMCG_MonitorInt == mode) + { + mcg_c8 &= ~MCG_C8_LOLRE_MASK; + } + else + { + mcg_c8 |= MCG_C8_LOLRE_MASK; + } + MCG->C8 = mcg_c8; + MCG->C6 |= MCG_C6_LOLIE0_MASK; + } +} + +uint32_t CLOCK_GetStatusFlags(void) +{ + uint32_t ret = 0U; + uint8_t mcg_s = MCG->S; + + if (MCG->SC & MCG_SC_LOCS0_MASK) + { + ret |= kMCG_Osc0LostFlag; + } + if (mcg_s & MCG_S_OSCINIT0_MASK) + { + ret |= kMCG_Osc0InitFlag; + } + if (MCG->C8 & MCG_C8_LOCS1_MASK) + { + ret |= kMCG_RtcOscLostFlag; + } + if (mcg_s & MCG_S_LOLS0_MASK) + { + ret |= kMCG_Pll0LostFlag; + } + if (mcg_s & MCG_S_LOCK0_MASK) + { + ret |= kMCG_Pll0LockFlag; + } + return ret; +} + +void CLOCK_ClearStatusFlags(uint32_t mask) +{ + uint8_t reg; + + if (mask & kMCG_Osc0LostFlag) + { + MCG->SC &= ~MCG_SC_ATMF_MASK; + } + if (mask & kMCG_RtcOscLostFlag) + { + reg = MCG->C8; + MCG->C8 = reg; + } + if (mask & kMCG_Pll0LostFlag) + { + MCG->S = MCG_S_LOLS0_MASK; + } +} + +void CLOCK_InitOsc0(osc_config_t const *config) +{ + uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); + + OSC_SetCapLoad(OSC0, config->capLoad); + OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); + + MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); + + if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) + { + /* Wait for stable. */ + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } +} + +void CLOCK_DeinitOsc0(void) +{ + OSC0->CR = 0U; + MCG->C2 &= ~OSC_MODE_MASK; +} + +status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) +{ + uint32_t multi; /* extFreq / desireFreq */ + uint32_t actv; /* Auto trim value. */ + uint8_t mcg_sc; + + static const uint32_t trimRange[2][2] = { + /* Min Max */ + {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */ + {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ + }; + + if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) + { + return kStatus_MCG_AtmBusClockInvalid; + } + + /* Check desired frequency range. */ + if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) + { + return kStatus_MCG_AtmDesiredFreqInvalid; + } + + /* + Make sure internal reference clock is not used to generate bus clock. + Here only need to check (MCG_S_IREFST == 1). + */ + if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) + { + return kStatus_MCG_AtmIrcUsed; + } + + multi = extFreq / desireFreq; + actv = multi * 21U; + + if (kMCG_AtmSel4m == atms) + { + actv *= 128U; + } + + /* Now begin to start trim. */ + MCG->ATCVL = (uint8_t)actv; + MCG->ATCVH = (uint8_t)(actv >> 8U); + + mcg_sc = MCG->SC; + mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); + mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); + MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); + + /* Wait for finished. */ + while (MCG->SC & MCG_SC_ATME_MASK) + { + } + + /* Error occurs? */ + if (MCG->SC & MCG_SC_ATMF_MASK) + { + /* Clear the failed flag. */ + MCG->SC = mcg_sc; + return kStatus_MCG_AtmHardwareFail; + } + + *actualFreq = extFreq / multi; + + if (kMCG_AtmSel4m == atms) + { + s_fastIrcFreq = *actualFreq; + } + else + { + s_slowIrcFreq = *actualFreq; + } + + return kStatus_Success; +} + +mcg_mode_t CLOCK_GetMode(void) +{ + mcg_mode_t mode = kMCG_ModeError; + uint32_t clkst = MCG_S_CLKST_VAL; + uint32_t irefst = MCG_S_IREFST_VAL; + uint32_t lp = MCG_C2_LP_VAL; + uint32_t pllst = MCG_S_PLLST_VAL; + + /*------------------------------------------------------------------ + Mode and Registers + ____________________________________________________________________ + + Mode | CLKST | IREFST | PLLST | LP + ____________________________________________________________________ + + FEI | 00(FLL) | 1(INT) | 0(FLL) | X + ____________________________________________________________________ + + FEE | 00(FLL) | 0(EXT) | 0(FLL) | X + ____________________________________________________________________ + + FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) + ____________________________________________________________________ + + BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) + ____________________________________________________________________ + + PEE | 11(PLL) | 0(EXT) | 1(PLL) | X + ____________________________________________________________________ + + PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) + ____________________________________________________________________ + + PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) + ____________________________________________________________________ + + PEI | 11(PLL) | 1(INT) | 1(PLL) | X + ____________________________________________________________________ + + ----------------------------------------------------------------------*/ + + switch (clkst) + { + case kMCG_ClkOutStatFll: + if (kMCG_FllSrcExternal == irefst) + { + mode = kMCG_ModeFEE; + } + else + { + mode = kMCG_ModeFEI; + } + break; + case kMCG_ClkOutStatInt: + if (lp) + { + mode = kMCG_ModeBLPI; + } + else + { + { + mode = kMCG_ModeFBI; + } + } + break; + case kMCG_ClkOutStatExt: + if (lp) + { + mode = kMCG_ModeBLPE; + } + else + { + if (kMCG_PllstPll == pllst) + { + mode = kMCG_ModePBE; + } + else + { + mode = kMCG_ModeFBE; + } + } + break; + case kMCG_ClkOutStatPll: + { + mode = kMCG_ModePEE; + } + break; + default: + break; + } + + return mode; +} + +status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */ + + /* Wait and check status. */ + while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ + MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs)); + + /* Check MCG_S[CLKST] */ + while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) + { + } + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* Wait and check status. */ + while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* Set DRS and DMX32. */ + mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = mcg_c4; + + /* Wait for DRST_DRS update. */ + while (MCG->C4 != mcg_c4) + { + } + + /* Check MCG_S[CLKST] */ + while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) + { + } + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || + (kMCG_ModeBLPI == mode))) + + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + mcg_c4 = MCG->C4; + + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + + /* Wait and check status. */ + while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) + { + } + + MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs)); + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || + (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Change to FLL mode. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + /* Set LP bit to enable the FLL */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* Wait for Reference clock Status bit to clear */ + while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* Set DRST_DRS and DMX32. */ + mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + + /* Wait for clock status bits to show clock source is ext ref clk */ + while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) + { + } + + /* Wait for fll stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetBlpiMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + return kStatus_MCG_ModeUnreachable; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + /* Set LP. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_SetBlpeMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Set LP bit to enter BLPE mode. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +{ + /* + This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, + but with this workflow, the source mode could be all modes except PEI/PBI. + */ + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + /* Change to use external clock first. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + + /* Wait for CLKST clock status bits to show clock source is ext ref clk */ + while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) + { + } + + /* Disable PLL first, then configure PLL. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + /* Configure the PLL. */ + { + CLOCK_EnablePll0(config); + } + + /* Change to PLL mode. */ + MCG->C6 |= MCG_C6_PLLS_MASK; + while (!(MCG->S & MCG_S_PLLST_MASK)) + { + } + + return kStatus_Success; +} + +status_t CLOCK_SetPeeMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (kMCG_ModePBE != mode) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Change to use PLL/FLL output clock first. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + + /* Wait for clock status bits to update */ + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) + { + } + + return kStatus_Success; +} + +status_t CLOCK_ExternalModeToFbeModeQuick(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG->S & MCG_S_IREFST_MASK) + { + return kStatus_MCG_ModeInvalid; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + /* Disable low power */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + } + + /* Disable PLL. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + return kStatus_Success; +} + +status_t CLOCK_InternalModeToFbiModeQuick(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (!(MCG->S & MCG_S_IREFST_MASK)) + { + return kStatus_MCG_ModeInvalid; + } +#endif + + /* Disable low power */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + } + + return kStatus_Success; +} + +status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + return CLOCK_SetFeiMode(drs, fllStableDelay); +} + +status_t CLOCK_BootToFeeMode( + mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + CLOCK_SetExternalRefClkConfig(oscsel); + + return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); +} + +status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) +{ + /* If reset mode is FEI mode, set MCGIRCLK and always success. */ + CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); + + /* If reset mode is not BLPI, first enter FBI mode. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + } + + /* Enter BLPI mode. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) +{ + CLOCK_SetExternalRefClkConfig(oscsel); + + /* Set to FBE mode. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ + while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) + { + } + + /* In FBE now, start to enter BLPE. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +{ + assert(config); + + CLOCK_SetExternalRefClkConfig(oscsel); + + CLOCK_SetPbeMode(pllcs, config); + + /* Change to use PLL output clock. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) + { + } + + return kStatus_Success; +} + +/* + The transaction matrix. It defines the path for mode switch, the row is for + current mode and the column is target mode. + For example, switch from FEI to PEE: + 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE. + 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE. + 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE. + Thus the MCG mode has changed from FEI to PEE. + */ +static const mcg_mode_t mcgModeMatrix[8][8] = { + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FEI */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FBI */ + {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, + kMCG_ModeFBI}, /* BLPI */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FEE */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePBE}, /* FBE */ + {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePBE}, /* BLPE */ + {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePEE}, /* PBE */ + {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, + kMCG_ModePBE} /* PEE */ + /* FEI FBI BLPI FEE FBE BLPE PBE PEE */ +}; + +status_t CLOCK_SetMcgConfig(const mcg_config_t *config) +{ + mcg_mode_t next_mode; + status_t status = kStatus_Success; + + mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0; + + /* If need to change external clock, MCG_C7[OSCSEL]. */ + if (MCG_C7_OSCSEL_VAL != config->oscsel) + { + /* If external clock is in use, change to FEI first. */ + if (!(MCG->S & MCG_S_IRCST_MASK)) + { + CLOCK_ExternalModeToFbeModeQuick(); + CLOCK_SetFeiMode(config->drs, (void (*)(void))0); + } + + CLOCK_SetExternalRefClkConfig(config->oscsel); + } + + /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ + if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt) + { + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + { + CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay); + } + } + + /* Configure MCGIRCLK. */ + CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv); + + next_mode = CLOCK_GetMode(); + + do + { + next_mode = mcgModeMatrix[next_mode][config->mcgMode]; + + switch (next_mode) + { + case kMCG_ModeFEI: + status = CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFEE: + status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFBI: + status = CLOCK_SetFbiMode(config->drs, (void (*)(void))0); + break; + case kMCG_ModeFBE: + status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0); + break; + case kMCG_ModeBLPI: + status = CLOCK_SetBlpiMode(); + break; + case kMCG_ModeBLPE: + status = CLOCK_SetBlpeMode(); + break; + case kMCG_ModePBE: + /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ + if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) + { + { + status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); + } + } + else + { + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + } + } + break; + case kMCG_ModePEE: + status = CLOCK_SetPeeMode(); + break; + default: + break; + } + if (kStatus_Success != status) + { + return status; + } + } while (next_mode != config->mcgMode); + + if (config->pll0Config.enableMode & kMCG_PllEnableIndependent) + { + CLOCK_EnablePll0(&config->pll0Config); + } + else + { + MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; + } + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h new file mode 100755 index 00000000000..b6040ff75d6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h @@ -0,0 +1,1453 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! @addtogroup clock */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock driver version. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief External XTAL0 (OSC0) clock frequency. + * + * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example, + * if XTAL0 is 8MHz, + * @code + * CLOCK_InitOsc0(...); // Setup the OSC0 + * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver. + * @endcode + * + * This is important for the multicore platforms, only one core needs to setup + * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq + * to get valid clock frequency. + */ +extern uint32_t g_xtal0Freq; + +/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. + * + * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtal32Freq to set the value in to clock driver. + * + * This is important for the multicore platforms, only one core needs to setup + * the clock, all other cores need to call CLOCK_SetXtal32Freq + * to get valid clock frequency. + */ +extern uint32_t g_xtal32Freq; + +/*! @brief IRC48M clock frequency in Hz. */ +#define MCG_INTERNAL_IRC_48M 48000000U + +#if (defined(OSC) && !(defined(OSC0))) +#define OSC0 OSC +#endif + +/*! @brief Clock ip name array for DMAMUX. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dmamux0 \ + } + +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_Sai0 \ + } + +/*! @brief Clock ip name array for PORT. */ +#define PORT_CLOCKS \ + { \ + kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ + } + +/*! @brief Clock ip name array for FLEXBUS. */ +#define FLEXBUS_CLOCKS \ + { \ + kCLOCK_Flexbus0 \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit0 \ + } + +/*! @brief Clock ip name array for DSPI. */ +#define DSPI_CLOCKS \ + { \ + kCLOCK_Spi0, kCLOCK_Spi1 \ + } + +/*! @brief Clock ip name array for LPTMR. */ +#define LPTMR_CLOCKS \ + { \ + kCLOCK_Lptmr0 \ + } + +/*! @brief Clock ip name array for FTM. */ +#define FTM_CLOCKS \ + { \ + kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \ + } + +/*! @brief Clock ip name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma0 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_Lpuart0 \ + } + +/*! @brief Clock ip name array for DAC. */ +#define DAC_CLOCKS \ + { \ + kCLOCK_Dac0, kCLOCK_Dac1 \ + } + +/*! @brief Clock ip name array for ADC16. */ +#define ADC16_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } + +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref0 \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \ + } + +/*! @brief Clock ip name array for RNGA. */ +#define RNGA_CLOCKS \ + { \ + kCLOCK_Rnga0 \ + } + +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_I2c0, kCLOCK_I2c1 \ + } + +/*! @brief Clock ip name array for FTF. */ +#define FTF_CLOCKS \ + { \ + kCLOCK_Ftf0 \ + } + +/*! @brief Clock ip name array for PDB. */ +#define PDB_CLOCKS \ + { \ + kCLOCK_Pdb0 \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \ + } + +/*! + * @brief LPO clock frequency. + */ +#define LPO_CLK_FREQ 1000U + +/*! @brief Peripherals clock source definition. */ +#define SYS_CLK kCLOCK_CoreSysClk +#define BUS_CLK kCLOCK_BusClk +#define FAST_CLK kCLOCK_FastPeriphClk + +#define I2C0_CLK_SRC BUS_CLK +#define I2C1_CLK_SRC BUS_CLK +#define DSPI0_CLK_SRC BUS_CLK +#define DSPI1_CLK_SRC BUS_CLK +#define UART0_CLK_SRC SYS_CLK +#define UART1_CLK_SRC SYS_CLK +#define UART2_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + + /* ----------------------------- System layer clock -------------------------------*/ + kCLOCK_CoreSysClk, /*!< Core/system clock */ + kCLOCK_PlatClk, /*!< Platform clock */ + kCLOCK_BusClk, /*!< Bus clock */ + kCLOCK_FlexBusClk, /*!< FlexBus clock */ + kCLOCK_FlashClk, /*!< Flash clock */ + kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ + kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ + + /* ---------------------------------- OSC clock -----------------------------------*/ + kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ + kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ + kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ + kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ + + /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ + kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ + kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ + kCLOCK_McgFllClk, /*!< MCGFLLCLK */ + kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ + kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ + kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ + kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ + kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ + + /* --------------------------------- Other clock ----------------------------------*/ + kCLOCK_LpoClk, /*!< LPO clock */ + +} clock_name_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ + kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */ + kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ +} clock_usb_src_t; +/*------------------------------------------------------------------------------ + + clock_gate_t definition: + + 31 16 0 + ----------------------------------------------------------------- + | SIM_SCGC register offset | control bit offset in SCGC | + ----------------------------------------------------------------- + + For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the + SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as + + kCLOCK_GateSdhc0 = (0x1030 << 16) | 17; + +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 16U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + + kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), + kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), + kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), + kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U), + kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U), + kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), + kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), + kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), + + kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), + kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), + kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), + kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), + kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), + kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), + + kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), + kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), + kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x103CU, 6U), + kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 7U), + kCLOCK_Dac1 = CLK_GATE_DEFINE(0x103CU, 8U), + kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U), + kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x103CU, 10U), + kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), + kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), + kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), + kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), + kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), + kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), + kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), + kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), + kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), + kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), + kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), + kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U), + + kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U), + kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), +} clock_ip_name_t; + +/*!@brief SIM configuration structure for clock setting. */ +typedef struct _sim_clock_config +{ + uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ + uint8_t er32kSrc; /*!< ERCLK32K source selection. */ + uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ +} sim_clock_config_t; + +/*! @brief OSC work mode. */ +typedef enum _osc_mode +{ + kOSC_ModeExt = 0U, /*!< Use external clock. */ +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) + kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ +#else + kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ +#endif + kOSC_ModeOscHighGain = 0U +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) + | + MCG_C2_EREFS_MASK +#else + | + MCG_C2_EREFS0_MASK +#endif +#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) + | + MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ +#else + | + MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ +#endif +} osc_mode_t; + +/*! @brief Oscillator capacitor load setting.*/ +enum _osc_cap_load +{ + kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ + kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ + kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ + kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ +}; + +/*! @brief OSCERCLK enable mode. */ +enum _oscer_enable_mode +{ + kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ + kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ +}; + +/*! @brief OSC configuration for OSCERCLK. */ +typedef struct _oscer_config +{ + uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ + + uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/ +} oscer_config_t; + +/*! + * @brief OSC Initialization Configuration Structure + * + * Defines the configuration data structure to initialize the OSC. + * When porting to a new board, please set the following members + * according to board setting: + * 1. freq: The external frequency. + * 2. workMode: The OSC module mode. + */ +typedef struct _osc_config +{ + uint32_t freq; /*!< External clock frequency. */ + uint8_t capLoad; /*!< Capacitor load setting. */ + osc_mode_t workMode; /*!< OSC work mode setting. */ + oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ +} osc_config_t; + +/*! @brief MCG FLL reference clock source select. */ +typedef enum _mcg_fll_src +{ + kMCG_FllSrcExternal, /*!< External reference clock is selected */ + kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ +} mcg_fll_src_t; + +/*! @brief MCG internal reference clock select */ +typedef enum _mcg_irc_mode +{ + kMCG_IrcSlow, /*!< Slow internal reference clock selected */ + kMCG_IrcFast /*!< Fast internal reference clock selected */ +} mcg_irc_mode_t; + +/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ +typedef enum _mcg_dmx32 +{ + kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ + kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ +} mcg_dmx32_t; + +/*! @brief MCG DCO range select */ +typedef enum _mcg_drs +{ + kMCG_DrsLow, /*!< Low frequency range */ + kMCG_DrsMid, /*!< Mid frequency range */ + kMCG_DrsMidHigh, /*!< Mid-High frequency range */ + kMCG_DrsHigh /*!< High frequency range */ +} mcg_drs_t; + +/*! @brief MCG PLL reference clock select */ +typedef enum _mcg_pll_ref_src +{ + kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ + kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ +} mcg_pll_ref_src_t; + +/*! @brief MCGOUT clock source. */ +typedef enum _mcg_clkout_src +{ + kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ + kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ + kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ +} mcg_clkout_src_t; + +/*! @brief MCG Automatic Trim Machine Select */ +typedef enum _mcg_atm_select +{ + kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ + kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ +} mcg_atm_select_t; + +/*! @brief MCG OSC Clock Select */ +typedef enum _mcg_oscsel +{ + kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ + kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ + kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */ +} mcg_oscsel_t; + +/*! @brief MCG PLLCS select */ +typedef enum _mcg_pll_clk_select +{ + kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ + kMCG_PllClkSelPll1 /* PLL1 output clock is selected */ +} mcg_pll_clk_select_t; + +/*! @brief MCG clock monitor mode. */ +typedef enum _mcg_monitor_mode +{ + kMCG_MonitorNone, /*!< Clock monitor is disabled. */ + kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ + kMCG_MonitorReset /*!< System reset when clock lost. */ +} mcg_monitor_mode_t; + +/*! @brief MCG status. */ +enum _mcg_status +{ + kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ + kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific + function. */ + kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ + kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ + kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ + kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ + kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Could not change clock source because + it is used currently. */ +}; + +/*! @brief MCG status flags. */ +enum _mcg_status_flags_t +{ + kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ + kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ + kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ + kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ + kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ +}; + +/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ +enum _mcg_irclk_enable_mode +{ + kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ + kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ +}; + +/*! @brief MCG PLL clock enable mode definition. */ +enum _mcg_pll_enable_mode +{ + kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of + MCG clock mode. Generally, PLL + is disabled in FLL modes + (FEI/FBI/FEE/FBE), set PLL clock + enable independent will enable + PLL in the FLL modes. */ + kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ +}; + +/*! @brief MCG mode definitions */ +typedef enum _mcg_mode +{ + kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ + kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ + kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ + kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ + kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ + kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ + kMCG_ModePBE, /*!< PBE - PLL Bypassed External */ + kMCG_ModePEE, /*!< PEE - PLL Engaged External */ + kMCG_ModeError /*!< Unknown mode */ +} mcg_mode_t; + +/*! @brief MCG PLL configuration. */ +typedef struct _mcg_pll_config +{ + uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ + uint8_t prdiv; /*!< Reference divider PRDIV. */ + uint8_t vdiv; /*!< VCO divider VDIV. */ +} mcg_pll_config_t; + +/*! @brief MCG configure structure for mode change. + * + * When porting to a new board, please set the following members + * according to board setting: + * 1. frdiv: If FLL uses the external reference clock, please set this + * value to make sure external reference clock divided by frdiv is + * in the range 31.25kHz to 39.0625kHz. + * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after + * PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to + * FSL_FEATURE_MCG_PLL_REF_MAX. + */ +typedef struct _mcg_config +{ + mcg_mode_t mcgMode; /*!< MCG mode. */ + + /* ----------------------- MCGIRCCLK settings ------------------------ */ + uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ + mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ + uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ + + /* ------------------------ MCG FLL settings ------------------------- */ + uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ + mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ + mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ + mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ + + /* ------------------------ MCG PLL settings ------------------------- */ + mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */ + +} mcg_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set the XTAL0 frequency based on board setting. + * + * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal0Freq(uint32_t freq) +{ + g_xtal0Freq = freq; +} + +/*! + * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting. + * + * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal32Freq(uint32_t freq) +{ + g_xtal32Freq = freq; +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Set LPUART clock source. + * + * @param src The value to set LPUART clock source. + */ +static inline void CLOCK_SetLpuartClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src)); +} + +/*! + * @brief Set ERCLK32K source. + * + * @param src The value to set ERCLK32K clock source. + */ +static inline void CLOCK_SetEr32kClock(uint32_t src) +{ + SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); +} + +/*! + * @brief Set debug trace clock source. + * + * @param src The value to set debug trace clock source. + */ +static inline void CLOCK_SetTraceClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); +} + +/*! + * @brief Set PLLFLLSEL clock source. + * + * @param src The value to set PLLFLLSEL clock source. + */ +static inline void CLOCK_SetPllFllSelClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); +} + +/*! + * @brief Set CLKOUT source. + * + * @param src The value to set CLKOUT source. + */ +static inline void CLOCK_SetClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); +} + +/*! + * @brief Set RTC_CLKOUT source. + * + * @param src The value to set RTC_CLKOUT source. + */ +static inline void CLOCK_SetRtcClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); +} + +/*! @brief Enable USB FS clock. + * + * @param src USB FS clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB FS clock. + */ +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB FS clock. + * + * Disable USB FS clock. + */ +static inline void CLOCK_DisableUsbfs0Clock(void) +{ + CLOCK_DisableClock(kCLOCK_Usbfs0); +} + +/*! + * @brief System clock divider + * + * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4]. + * + * @param outdiv1 Clock 1 output divider value. + * + * @param outdiv2 Clock 2 output divider value. + * + * @param outdiv3 Clock 3 output divider value. + * + * @param outdiv4 Clock 4 output divider value. + */ +static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) +{ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | + SIM_CLKDIV1_OUTDIV4(outdiv4); +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * The MCG must be properly configured before using this function. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in Hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Get the core clock or system clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! + * @brief Get the platform clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetPlatClkFreq(void); + +/*! + * @brief Get the bus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetBusClkFreq(void); + +/*! + * @brief Get the flexbus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlexBusClkFreq(void); + +/*! + * @brief Get the flash clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlashClkFreq(void); + +/*! + * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetPllFllSelClkFreq(void); + +/*! + * @brief Get the external reference 32K clock frequency (ERCLK32K). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetEr32kClkFreq(void); + +/*! + * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetOsc0ErClkUndivFreq(void); + +/*! + * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetOsc0ErClkFreq(void); + +/*! + * @brief Set the clock configure in SIM module. + * + * This function sets system layer clock settings in SIM module. + * + * @param config Pointer to the configure structure. + */ +void CLOCK_SetSimConfig(sim_clock_config_t const *config); + +/*! + * @brief Set the system clock dividers in SIM to safe value. + * + * The system level clocks (core clock, bus clock, flexbus clock and flash clock) + * must be in allowed ranges. During MCG clock mode switch, the MCG output clock + * changes then the system level clocks may be out of range. This function could + * be used before MCG mode change, to make sure system level clocks are in allowed + * range. + * + * @param config Pointer to the configure structure. + */ +static inline void CLOCK_SetSimSafeDivs(void) +{ + SIM->CLKDIV1 = 0x01230000U; +} + +/*! @name MCG frequency functions. */ +/*@{*/ + +/*! + * @brief Get the MCG output clock(MCGOUTCLK) frequency. + * + * This function gets the MCG output clock frequency (Hz) based on current MCG + * register value. + * + * @return The frequency of MCGOUTCLK. + */ +uint32_t CLOCK_GetOutClkFreq(void); + +/*! + * @brief Get the MCG FLL clock(MCGFLLCLK) frequency. + * + * This function gets the MCG FLL clock frequency (Hz) based on current MCG + * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other + * modes, FLL is disabled in low power state. + * + * @return The frequency of MCGFLLCLK. + */ +uint32_t CLOCK_GetFllFreq(void); + +/*! + * @brief Get the MCG internal reference clock(MCGIRCLK) frequency. + * + * This function gets the MCG internal reference clock frequency (Hz) based + * on current MCG register value. + * + * @return The frequency of MCGIRCLK. + */ +uint32_t CLOCK_GetInternalRefClkFreq(void); + +/*! + * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency. + * + * This function gets the MCG fixed frequency clock frequency (Hz) based + * on current MCG register value. + * + * @return The frequency of MCGFFCLK. + */ +uint32_t CLOCK_GetFixedFreqClkFreq(void); + +/*! + * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency. + * + * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG + * register value. + * + * @return The frequency of MCGPLL0CLK. + */ +uint32_t CLOCK_GetPll0Freq(void); + +/*@}*/ + +/*! @name MCG clock configuration. */ +/*@{*/ + +/*! + * @brief Enable or disable MCG low power. + * + * Enable MCG low power will disable the PLL and FLL in bypass modes. That is, + * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and + * PBI mode, enable low power will set MCG to BLPI mode. + * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting. + * + * @param enable True to enable MCG low power, false to disable MCG low power. + */ +static inline void CLOCK_SetLowPowerEnable(bool enable) +{ + if (enable) + { + MCG->C2 |= MCG_C2_LP_MASK; + } + else + { + MCG->C2 &= ~MCG_C2_LP_MASK; + } +} + +/*! + * @brief Configure the Internal Reference clock (MCGIRCLK) + * + * This function setups the \c MCGIRCLK base on parameters. It selects the IRC + * source, if fast IRC is used, this function also sets the fast IRC divider. + * This function also sets whether enable \c MCGIRCLK in stop mode. + * Calling this function in FBI/PBI/BLPI modes may change the system clock, so + * it is not allowed to use this in these modes. + * + * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. + * @param ircs MCGIRCLK clock source, choose fast or slow. + * @param fcrdiv Fast IRC divider setting (\c FCRDIV). + * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK. + * @retval kStatus_Success MCGIRCLK configuration finished successfully. + */ +status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); + +/*! + * @brief Select the MCG external reference clock. + * + * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL] + * and wait for the clock source stable. Should not change external reference + * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes. + * + * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. + * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change. + * @retval kStatus_Success External reference clock set successfully. + */ +status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); + +/*! + * @brief Enables the PLL0 in FLL mode. + * + * This function setups the PLL0 in FLL mode, make sure the PLL reference + * clock is enabled before calling this function. This function reconfigures + * the PLL0, make sure the PLL0 is not used as a clock source while calling + * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL + * divider values. + * + * @param config Pointer to the configuration structure. + */ +void CLOCK_EnablePll0(mcg_pll_config_t const *config); + +/*! + * @brief Disables the PLL0 in FLL mode. + * + * This function disables the PLL0 in FLL mode, it should be used together with + * @ref CLOCK_EnablePll0. + */ +static inline void CLOCK_DisablePll0(void) +{ + MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); +} + +/*! + * @brief Calculates the PLL divider setting for desired output frequency. + * + * This function calculates the proper reference clock divider (\c PRDIV) and + * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the + * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are + * returned from parameters. If desired frequency is not valid, this function + * returns 0. + * + * @param refFreq PLL reference clock frequency. + * @param desireFreq Desired PLL output frequency. + * @param prdiv PRDIV value to generate desired PLL frequency. + * @param vdiv VDIV value to generate desired PLL frequency. + * @return Closest frequency PLL could generate. + */ +uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); + +/*@}*/ + +/*! @name MCG clock lock monitor functions. */ +/*@{*/ + +/*! + * @brief Set the OSC0 clock monitor mode. + * + * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details. + * + * @param mode The monitor mode to set. + */ +void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Set the RTC OSC clock monitor mode. + * + * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details. + * + * @param mode The monitor mode to set. + */ +void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Set the PLL0 clock monitor mode. + * + * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details. + * + * @param mode The monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Get the MCG status flags. + * + * This function gets the MCG clock status flags, all the status flags are + * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To + * check specific flags, compare the return value with the flags. + * + * Example: + * @code + // To check the clock lost lock status of OSC0 and PLL0. + uint32_t mcgFlags; + + mcgFlags = CLOCK_GetStatusFlags(); + + if (mcgFlags & kMCG_Osc0LostFlag) + { + // OSC0 clock lock lost. Do something. + } + if (mcgFlags & kMCG_Pll0LostFlag) + { + // PLL0 clock lock lost. Do something. + } + @endcode + * + * @return Logical OR value of the @ref _mcg_status_flags_t. + */ +uint32_t CLOCK_GetStatusFlags(void); + +/*! + * @brief Clears the MCG status flags. + * + * This function clears the MCG clock lock lost status. The parameter is logical + * OR value of the flags to clear, see @ref _mcg_status_flags_t. + * + * Example: + * @code + // To clear the clock lost lock status flags of OSC0 and PLL0. + + CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); + @endcode + * + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration @ref _mcg_status_flags_t. + */ +void CLOCK_ClearStatusFlags(uint32_t mask); + +/*@}*/ + +/*! + * @name OSC configuration + * @{ + */ + +/*! + * @brief Configures the OSC external reference clock (OSCERCLK). + * + * This function configures the OSC external reference clock (OSCERCLK). + * For example, to enable the OSCERCLK in normal mode and stop mode, and also set + * the output divider to 1, as follows: + * + @code + oscer_config_t config = + { + .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, + .erclkDiv = 1U, + }; + + OSC_SetExtRefClkConfig(OSC, &config); + @endcode + * + * @param base OSC peripheral address. + * @param config Pointer to the configuration structure. + */ +static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); + reg |= config->enableMode; + + base->CR = reg; + + base->DIV = OSC_DIV_ERPS(config->erclkDiv); +} + +/*! + * @brief Sets the capacitor load configuration for the oscillator. + * + * This function sets the specified capacitors configuration for the oscillator. + * This should be done in the early system level initialization function call + * based on the system configuration. + * + * @param base OSC peripheral address. + * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. + * + * Example: + @code + // To enable only 2 pF and 8 pF capacitor load, please use like this. + OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); + @endcode + */ +static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Initialize OSC0. + * + * This function initializes OSC0 according to board configuration. + * + * @param config Pointer to the OSC0 configuration structure. + */ +void CLOCK_InitOsc0(osc_config_t const *config); + +/*! + * @brief Deinitialize OSC0. + * + * This function deinitializes OSC0. + */ +void CLOCK_DeinitOsc0(void); + +/* @} */ + +/*! + * @name MCG auto-trim machine. + * @{ + */ + +/*! + * @brief Auto trim the internal reference clock. + * + * This function trims the internal reference clock using external clock. If + * successful, it returns the kStatus_Success and the frequency after + * trimming is received in the parameter @p actualFreq. If an error occurs, + * the error code is returned. + * + * @param extFreq External clock frequency, should be bus clock. + * @param desireFreq Frequency want to trim to. + * @param actualFreq Actual frequency after trim. + * @param atms Trim fast or slow internal reference clock. + * @retval kStatus_Success ATM success. + * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM. + * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. + * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source. + * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim. + */ +status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); +/* @} */ + +/*! @name MCG mode functions. */ +/*@{*/ + +/*! + * @brief Gets the current MCG mode. + * + * This function checks the MCG registers and determine current MCG mode. + * + * @return Current MCG mode or error code, see @ref mcg_mode_t. + */ +mcg_mode_t CLOCK_GetMode(void); + +/*! + * @brief Set MCG to FEI mode. + * + * This function sets MCG to FEI mode. If could not set to FEI mode directly + * from current mode, this function returns error. @ref kMCG_Dmx32Default is used in this + * mode because using kMCG_Dmx32Fine with internal reference clock source + * might damage hardware. + * + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable, if pass + * in NULL, then does not delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FEE mode. + * + * This function sets MCG to FEE mode. If could not set to FEE mode directly + * from current mode, this function returns error. + * + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable, if pass + * in NULL, then does not delay. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FBI mode. + * + * This function sets MCG to FBI mode. If could not set to FBI mode directly + * from current mode, this function returns error. + * + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. If FLL + * is not used in FBI mode, this parameter could be NULL. Pass in + * NULL does not delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FBE mode. + * + * This function sets MCG to FBE mode. If could not set to FBE mode directly + * from current mode, this function returns error. + * + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FBE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. If FLL + * is not used in FBE mode, this parameter could be NULL. Pass in NULL + * does not delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to BLPI mode. + * + * This function sets MCG to BLPI mode. If could not set to BLPI mode directly + * from current mode, this function returns error. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetBlpiMode(void); + +/*! + * @brief Set MCG to BLPE mode. + * + * This function sets MCG to BLPE mode. If could not set to BLPE mode directly + * from current mode, this function returns error. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_SetBlpeMode(void); + +/*! + * @brief Set MCG to PBE mode. + * + * This function sets MCG to PBE mode. If could not set to PBE mode directly + * from current mode, this function returns error. + * + * @param pllcs The PLL selection, PLLCS. + * @param config Pointer to the PLL configuration. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + * + * @note + * 1. The parameter \c pllcs selects the PLL, for some platforms, there is + * only one PLL, the parameter pllcs is kept for interface compatible. + * 2. The parameter \c config is the PLL configuration structure, on some + * platforms, could choose the external PLL directly. This means that the + * configuration structure is not necessary, pass in NULL for this case. + * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); + */ +status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); + +/*! + * @brief Set MCG to PEE mode. + * + * This function sets MCG to PEE mode. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + * + * @note This function only change CLKS to use PLL/FLL output. If the + * PRDIV/VDIV are different from PBE mode, please setup these + * settings in PBE mode and wait for stable then switch to PEE mode. + */ +status_t CLOCK_SetPeeMode(void); + +/*! + * @brief Switch MCG to FBE mode quickly from external mode. + * + * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly. + * It only changes to use external clock as the system clock souce and disable PLL, but does not + * configure FLL settings. This is a lite function with small code size, it is useful + * during mode switch. For example, to switch from PEE mode to FEI mode: + * + * @code + * CLOCK_ExternalModeToFbeModeQuick(); + * CLOCK_SetFeiMode(...); + * @endcode + * + * @retval kStatus_Success Change successfully. + * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function. + */ +status_t CLOCK_ExternalModeToFbeModeQuick(void); + +/*! + * @brief Switch MCG to FBI mode quickly from internal modes. + * + * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly. + * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not + * configure FLL settings. This is a lite function with small code size, it is useful + * during mode switch. For example, to switch from PEI mode to FEE mode: + * + * @code + * CLOCK_InternalModeToFbiModeQuick(); + * CLOCK_SetFeeMode(...); + * @endcode + * + * @retval kStatus_Success Change successfully. + * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function. + */ +status_t CLOCK_InternalModeToFbiModeQuick(void); + +/*! + * @brief Set MCG to FEI mode during system boot up. + * + * This function sets MCG to FEI mode from reset mode, it could be used to + * set up MCG during system boot up. @ref kMCG_Dmx32Default is used in this + * mode because using kMCG_Dmx32Fine with internal reference clock source + * might damage hardware. + * + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to FEE mode during system bootup. + * + * This function sets MCG to FEE mode from reset mode, it could be used to + * set up MCG during system boot up. + * + * @param oscsel OSC clock select, OSCSEL. + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToFeeMode( + mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Set MCG to BLPI mode during system boot up. + * + * This function sets MCG to BLPI mode from reset mode, it could be used to + * setup MCG during sytem boot up. + * + * @param fcrdiv Fast IRC divider, FCRDIV. + * @param ircs The internal reference clock to select, IRCS. + * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. + * + * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); + +/*! + * @brief Set MCG to BLPE mode during sytem boot up. + * + * This function sets MCG to BLPE mode from reset mode, it could be used to + * setup MCG during sytem boot up. + * + * @param oscsel OSC clock select, MCG_C7[OSCSEL]. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); + +/*! + * @brief Set MCG to PEE mode during system boot up. + * + * This function sets MCG to PEE mode from reset mode, it could be used to + * setup MCG during system boot up. + * + * @param oscsel OSC clock select, MCG_C7[OSCSEL]. + * @param pllcs The PLL selection, PLLCS. + * @param config Pointer to the PLL configuration. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switch to target mode successfully. + */ +status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); + +/*! + * @brief Set MCG to some target mode. + * + * This function sets MCG to some target mode defined by the configure + * structure, if cannot switch to target mode directly, this function will + * choose the proper path. + * + * @param config Pointer to the target MCG mode configuration structure. + * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status. + * + * @note If external clock is used in the target mode, please make sure it is + * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before + * this funciton. + */ +status_t CLOCK_SetMcgConfig(mcg_config_t const *config); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c new file mode 100755 index 00000000000..09885e74211 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmp.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for CMP module. + * + * @param base CMP peripheral base address + */ +static uint32_t CMP_GetInstance(CMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CMP bases for each instance. */ +static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; +/*! @brief Pointers to CMP clocks for each instance. */ +const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t CMP_GetInstance(CMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++) + { + if (s_cmpBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_CMP_COUNT); + + return instance; +} + +void CMP_Init(CMP_Type *base, const cmp_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* Enable the clock. */ + CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); + + /* Configure. */ + CMP_Enable(base, false); /* Disable the CMP module during configuring. */ + /* CMPx_CR1. */ + tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); + if (config->enableHighSpeed) + { + tmp8 |= CMP_CR1_PMODE_MASK; + } + if (config->enableInvertOutput) + { + tmp8 |= CMP_CR1_INV_MASK; + } + if (config->useUnfilteredOutput) + { + tmp8 |= CMP_CR1_COS_MASK; + } + if (config->enablePinOut) + { + tmp8 |= CMP_CR1_OPE_MASK; + } +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + if (config->enableTriggerMode) + { + tmp8 |= CMP_CR1_TRIGM_MASK; + } + else + { + tmp8 &= ~CMP_CR1_TRIGM_MASK; + } +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + base->CR1 = tmp8; + + /* CMPx_CR0. */ + tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; + tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); + base->CR0 = tmp8; + + CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ +} + +void CMP_Deinit(CMP_Type *base) +{ + /* Disable the CMP module. */ + CMP_Enable(base, false); + + /* Disable the clock. */ + CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); +} + +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + assert(NULL != config); + + config->enableCmp = true; /* Enable the CMP module after initialization. */ + config->hysteresisMode = kCMP_HysteresisLevel0; + config->enableHighSpeed = false; + config->enableInvertOutput = false; + config->useUnfilteredOutput = false; + config->enablePinOut = false; +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} + +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) +{ + uint8_t tmp8 = base->MUXCR; + + tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); + tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); + base->MUXCR = tmp8; +} + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +void CMP_EnableDMA(CMP_Type *base, bool enable) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (enable) + { + tmp8 |= CMP_SCR_DMAEN_MASK; + } + else + { + tmp8 &= ~CMP_SCR_DMAEN_MASK; + } + base->SCR = tmp8; +} +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + /* Choose the clock source for sampling. */ + if (config->enableSample) + { + base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ + } + else + { + base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ + } +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + /* Set the filter count. */ + tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; + tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); + base->CR0 = tmp8; + /* Set the filter period. It is used as the divider to bus clock. */ + base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); +} + +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) +{ + uint8_t tmp8 = 0U; + + if (NULL == config) + { + /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ + base->DACCR = 0U; + return; + } + /* CMPx_DACCR. */ + tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ + if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) + { + tmp8 |= CMP_DACCR_VRSEL_MASK; + } + tmp8 |= CMP_DACCR_VOSEL(config->DACValue); + + base->DACCR = tmp8; +} + +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +uint32_t CMP_GetStatusFlags(CMP_Type *base) +{ + uint32_t ret32 = 0U; + + if (0U != (CMP_SCR_CFR_MASK & base->SCR)) + { + ret32 |= kCMP_OutputRisingEventFlag; + } + if (0U != (CMP_SCR_CFF_MASK & base->SCR)) + { + ret32 |= kCMP_OutputFallingEventFlag; + } + if (0U != (CMP_SCR_COUT_MASK & base->SCR)) + { + ret32 |= kCMP_OutputAssertEventFlag; + } + return ret32; +} + +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFR_MASK; + } + if (0U != (kCMP_OutputFallingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFF_MASK; + } + base->SCR = tmp8; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h new file mode 100755 index 00000000000..53d84a0f2d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CMP_H_ +#define _FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMP driver version 2.0.0. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! +* @brief Interrupt enable/disable mask. +*/ +enum _cmp_interrupt_enable +{ + kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ + kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ +}; + +/*! + * @brief Status flags' mask. + */ +enum _cmp_status_flags +{ + kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on compare output has occurred. */ + kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */ + kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ +}; + +/*! + * @brief CMP Hysteresis mode. + */ +typedef enum _cmp_hysteresis_mode +{ + kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ + kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ + kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ + kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ +} cmp_hysteresis_mode_t; + +/*! + * @brief CMP Voltage Reference source. + */ +typedef enum _cmp_reference_voltage_source +{ + kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */ + kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */ +} cmp_reference_voltage_source_t; + +/*! + * @brief Configure the comparator. + */ +typedef struct _cmp_config +{ + bool enableCmp; /*!< Enable the CMP module. */ + cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ + bool enableHighSpeed; /*!< Enable High Speed (HS) comparison mode. */ + bool enableInvertOutput; /*!< Enable inverted comparator output. */ + bool useUnfilteredOutput; /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */ + bool enablePinOut; /*!< The comparator output is available on the associated pin. */ +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool enableTriggerMode; /*!< Enable the trigger mode. */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} cmp_config_t; + +/*! + * @brief Configure the filter. + */ +typedef struct _cmp_filter_config +{ +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + bool enableSample; /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */ +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/ + uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */ +} cmp_filter_config_t; + +/*! + * @brief Configure the internal DAC. + */ +typedef struct _cmp_dac_config +{ + cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ + uint8_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-63.*/ +} cmp_dac_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are: + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config); + +/*! + * @brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are: + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * @param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base); + +/*! + * @brief Enables/disables the CMP module. + * + * @param base CMP peripheral base address. + * @param enable Enable the module or not. + */ +static inline void CMP_Enable(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_EN_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_EN_MASK; + } +} + +/*! +* @brief Initializes the CMP user configuration structure. +* +* This function initializes the user configure structure to these default values: +* @code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* @endcode +* @param config Pointer to the configuration structure. +*/ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/*! + * @brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set as same in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * @param base CMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA + * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP + * if the + * DMA is disabled. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable); +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE +/*! + * @brief Enables/disables the window mode. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_WE_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_WE_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ + +#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE +/*! + * @brief Enables/disables the pass through mode. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->MUXCR |= CMP_MUXCR_PSTM_MASK; + } + else + { + base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ + +/*! + * @brief Configures the filter. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); + +/*! + * @brief Configures the internal DAC. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. "NULL" is for disabling the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); + +/*! + * @brief Enables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Results + * @{ + */ + +/*! + * @brief Gets the status flags. + * + * @param base CMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base); + +/*! + * @brief Clears the status flags. + * + * @param base CMP peripheral base address. + * @param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_CMP_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c new file mode 100755 index 00000000000..895bbb04a00 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +/* This is not needed for mbed */ +#if 0 +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __asm("bkpt #0"); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __asm("bkpt #0"); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ +#endif +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + + __disable_irq(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + __enable_irq(); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h new file mode 100755 index 00000000000..105dca049a7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Enable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void EnableIRQ(IRQn_Type interrupt) +{ +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { + NVIC_EnableIRQ(interrupt); + } +} + +/*! + * @brief Disable specific interrupt. + * + * Disable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void DisableIRQ(IRQn_Type interrupt) +{ +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { + NVIC_DisableIRQ(interrupt); + } +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +} + +/*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ + __set_PRIMASK(primask); +} + +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + */ +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c new file mode 100755 index 00000000000..f73647e1c78 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! +* @brief CRC module configuration. +* +* This structure holds the configuration for the CRC module. +*/ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + crc_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + crc_ConfigureAndStart(base, &moduleConfig); +} + +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + crc_SetProtocolConfig(base, config); + } + else + { + crc_SetRawProtocolConfig(base, config); + } +} + +void CRC_GetDefaultConfig(crc_config_t *config) +{ + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((dataSize) && ((uint32_t)data & 3U)) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h new file mode 100755 index 00000000000..ce0b60fbaf9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.0. */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! +* @brief CRC protocol configuration. +* +* This structure holds the configuration for the CRC protocol. +* +*/ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral. + * It also configures the CRC module and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +} + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register (intermediate or final checksum). + * The configured type of transpose and complement are applied. + * + * @param base CRC peripheral address. + * @return intermediate or final 32-bit checksum, after configured transpose and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register (intermediate or final checksum). + * The configured type of transpose and complement are applied. + * + * @param base CRC peripheral address. + * @return intermediate or final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c new file mode 100755 index 00000000000..2f83f5ee9e6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dac.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DAC module. + * + * @param base DAC peripheral base address + */ +static uint32_t DAC_GetInstance(DAC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DAC bases for each instance. */ +static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS; +/*! @brief Pointers to DAC clocks for each instance. */ +const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t DAC_GetInstance(DAC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DAC_COUNT; instance++) + { + if (s_dacBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DAC_COUNT); + + return instance; +} + +void DAC_Init(DAC_Type *base, const dac_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* Enable the clock. */ + CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); + + /* Configure. */ + /* DACx_C0. */ + tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK); + if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource) + { + tmp8 |= DAC_C0_DACRFS_MASK; + } + if (config->enableLowPowerMode) + { + tmp8 |= DAC_C0_LPEN_MASK; + } + base->C0 = tmp8; + + DAC_Enable(base, true); +} + +void DAC_Deinit(DAC_Type *base) +{ + DAC_Enable(base, false); + + /* Disable the clock. */ + CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); +} + +void DAC_GetDefaultConfig(dac_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + config->enableLowPowerMode = false; +} + +void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* DACx_C0. */ + tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK); + if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode) + { + tmp8 |= DAC_C0_DACTRGSEL_MASK; + } + base->C0 = tmp8; + + /* DACx_C1. */ + tmp8 = base->C1 & + ~( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + DAC_C1_DACBFWM_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + DAC_C1_DACBFMD_MASK); +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + tmp8 |= DAC_C1_DACBFWM(config->watermark); +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + tmp8 |= DAC_C1_DACBFMD(config->workMode); + base->C1 = tmp8; + + /* DACx_C2. */ + tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK; + tmp8 |= DAC_C2_DACBFUP(config->upperLimit); + base->C2 = tmp8; +} + +void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config) +{ + assert(NULL != config); + + config->triggerMode = kDAC_BufferTriggerBySoftwareMode; +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + config->watermark = kDAC_BufferWatermark1Word; +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + config->workMode = kDAC_BufferWorkAsNormalMode; + config->upperLimit = DAC_DATL_COUNT - 1U; +} + +void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value) +{ + assert(index < DAC_DATL_COUNT); + + base->DAT[index].DATL = (uint8_t)(0xFFU & value); /* Low 8-bit. */ + base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */ +} + +void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index) +{ + assert(index < DAC_DATL_COUNT); + + uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK; + + tmp8 |= DAC_C2_DACBFRP(index); + base->C2 = tmp8; +} + +void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_C0_DACBWIEN_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); + base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ +} + +void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_C0_DACBWIEN_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); + base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ +} + +uint32_t DAC_GetBufferStatusFlags(DAC_Type *base) +{ + return (uint32_t)(base->SR & ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_SR_DACBFWMF_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK)); +} + +void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_SR_DACBFWMF_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK); + base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */ +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h new file mode 100755 index 00000000000..44e2d048bd9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DAC_H_ +#define _FSL_DAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dac + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DAC driver version 2.0.0. */ +#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief DAC buffer flags. + */ +enum _dac_buffer_status_flags +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK, /*!< DAC Buffer Watermark Flag. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + kDAC_BufferReadPointerTopPositionFlag = DAC_SR_DACBFRPTF_MASK, /*!< DAC Buffer Read Pointer Top Position Flag. */ + kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position + Flag. */ +}; + +/*! + * @brief DAC buffer interrupts. + */ +enum _dac_buffer_interrupt_enable +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK, /*!< DAC Buffer Watermark Interrupt Enable. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK, /*!< DAC Buffer Read Pointer Top Flag Interrupt + Enable. */ + kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag + Interrupt Enable */ +}; + +/*! + * @brief DAC reference voltage source. + */ +typedef enum _dac_reference_voltage_source +{ + kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ + kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ +} dac_reference_voltage_source_t; + +/*! + * @brief DAC buffer trigger mode. + */ +typedef enum _dac_buffer_trigger_mode +{ + kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */ + kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */ +} dac_buffer_trigger_mode_t; + +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION +/*! + * @brief DAC buffer watermark. + */ +typedef enum _dac_buffer_watermark +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD + kDAC_BufferWatermark1Word = 0U, /*!< 1 word away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD + kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD + kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD + kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD */ +} dac_buffer_watermark_t; +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + +/*! + * @brief DAC buffer work mode. + */ +typedef enum _dac_buffer_work_mode +{ + kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */ +#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE + kDAC_BufferWorkAsSwingMode, /*!< Swing mode. */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */ + kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */ +#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE + kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */ +} dac_buffer_work_mode_t; + +/*! + * @brief DAC module configuration. + */ +typedef struct _dac_config +{ + dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */ + bool enableLowPowerMode; /*!< Enable the low power mode. */ +} dac_config_t; + +/*! + * @brief DAC buffer configuration. + */ +typedef struct _dac_buffer_config +{ + dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + dac_buffer_work_mode_t workMode; /*!< Select the buffer's work mode. */ + uint8_t upperLimit; /*!< Set the upper limit for buffer index. + Normally, 0-15 is available for buffer with 16 item. */ +} dac_buffer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the DAC module. + * + * This function initializes the DAC module, including: + * - Enabling the clock for DAC module. + * - Configuring the DAC converter with a user configuration. + * - Enabling the DAC module. + * + * @param base DAC peripheral base address. + * @param config Pointer to the configuration structure. See "dac_config_t". + */ +void DAC_Init(DAC_Type *base, const dac_config_t *config); + +/*! + * @brief De-initializes the DAC module. + * + * This function de-initializes the DAC module, including: + * - Disabling the DAC module. + * - Disabling the clock for the DAC module. + * + * @param base DAC peripheral base address. + */ +void DAC_Deinit(DAC_Type *base); + +/*! + * @brief Initializes the DAC user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are: + * @code + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + * config->enableLowPowerMode = false; + * @endcode + * @param config Pointer to the configuration structure. See "dac_config_t". + */ +void DAC_GetDefaultConfig(dac_config_t *config); + +/*! + * @brief Enables the DAC module. + * + * @param base DAC peripheral base address. + * @param enable Enables the feature or not. + */ +static inline void DAC_Enable(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C0 |= DAC_C0_DACEN_MASK; + } + else + { + base->C0 &= ~DAC_C0_DACEN_MASK; + } +} + +/* @} */ + +/*! + * @name Buffer + * @{ + */ + +/*! + * @brief Enables the DAC buffer. + * + * @param base DAC peripheral base address. + * @param enable Enables the feature or not. + */ +static inline void DAC_EnableBuffer(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= DAC_C1_DACBFEN_MASK; + } + else + { + base->C1 &= ~DAC_C1_DACBFEN_MASK; + } +} + +/*! + * @brief Configures the CMP buffer. + * + * @param base DAC peripheral base address. + * @param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ +void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config); + +/*! + * @brief Initializes the DAC buffer configuration structure. + * + * This function initializes the DAC buffer configuration structure to a default value. The default values are: + * @code + * config->triggerMode = kDAC_BufferTriggerBySoftwareMode; + * config->watermark = kDAC_BufferWatermark1Word; + * config->workMode = kDAC_BufferWorkAsNormalMode; + * config->upperLimit = DAC_DATL_COUNT - 1U; + * @endcode + * @param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ +void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config); + +/*! + * @brief Enables the DMA for DAC buffer. + * + * @param base DAC peripheral base address. + * @param enable Enables the feature or not. + */ +static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= DAC_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~DAC_C1_DMAEN_MASK; + } +} + +/*! + * @brief Sets the value for items in the buffer. + * + * @param base DAC peripheral base address. + * @param index Setting index for items in the buffer. The available index should not exceed the size of the DAC buffer. + * @param value Setting value for items in the buffer. 12-bits are available. + */ +void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value); + +/*! + * @brief Triggers the buffer by software and updates the read pointer of the DAC buffer. + * + * This function triggers the function by software. The read pointer of the DAC buffer is updated with one step + * after this function is called. Changing the read pointer depends on the buffer's work mode. + * + * @param base DAC peripheral base address. + */ +static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base) +{ + base->C0 |= DAC_C0_DACSWTRG_MASK; +} + +/*! + * @brief Gets the current read pointer of the DAC buffer. + * + * This function gets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated + * by software trigger or hardware trigger. + * + * @param base DAC peripheral base address. + * + * @return Current read pointer of DAC buffer. + */ +static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base) +{ + return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT); +} + +/*! + * @brief Sets the current read pointer of the DAC buffer. + * + * This function sets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated by + * software trigger or hardware trigger. After the read pointer changes, the DAC output value also changes. + * + * @param base DAC peripheral base address. + * @param index Setting index value for the pointer. + */ +void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index); + +/*! + * @brief Enables interrupts for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ +void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask); + +/*! + * @brief Disables interrupts for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ +void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask); + +/*! + * @brief Gets the flags of events for the DAC buffer. + * + * @param base DAC peripheral base address. + * + * @return Mask value for the asserted flags. See "_dac_buffer_status_flags". + */ +uint32_t DAC_GetBufferStatusFlags(DAC_Type *base); + +/*! + * @brief Clears the flags of events for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for flags. See "_dac_buffer_status_flags_t". + */ +void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_DAC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c new file mode 100755 index 00000000000..a288b9f22fc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMAMUX. + * + * @param base DMAMUX peripheral base address. + */ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMAMUX instance number to base pointer. */ +static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; + +/*! @brief Array to map DMAMUX instance number to clock name. */ +static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++) + { + if (s_dmamuxBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT); + + return instance; +} + +void DMAMUX_Init(DMAMUX_Type *base) +{ + CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +} + +void DMAMUX_Deinit(DMAMUX_Type *base) +{ + CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h new file mode 100755 index 00000000000..f4294d4dfa8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMAMUX_H_ +#define _FSL_DMAMUX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmamux + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMAMUX driver version 2.0.0. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMAMUX Initialize and De-initialize + * @{ + */ + +/*! + * @brief Initializes DMAMUX peripheral. + * + * This function ungate the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base); + +/*! + * @brief Deinitializes DMAMUX peripheral. + * + * This function gate the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base); + +/* @} */ +/*! + * @name DMAMUX Channel Operation + * @{ + */ + +/*! + * @brief Enable DMAMUX channel. + * + * This function enable DMAMUX channel to work. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Disable DMAMUX channel. + * + * This function disable DMAMUX channel. + * + * @note User must disable DMAMUX channel before configure it. + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Configure DMAMUX channel source. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param source Channel source which is used to trigger DMA transfer. + */ +static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t source) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); +} + +#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U +/*! + * @brief Enable DMAMUX period trigger. + * + * This function enable DMAMUX period trigger feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; +} + +/*! + * @brief Disable DMAMUX period trigger. + * + * This function disable DMAMUX period trigger. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; +} +#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /* _FSL_DMAMUX_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c new file mode 100755 index 00000000000..5654ce7aac6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c @@ -0,0 +1,1659 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_dspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Typedef for master interrupt handler. */ +typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DSPI module. + * + * @param base DSPI peripheral base address. + */ +uint32_t DSPI_GetInstance(SPI_Type *base); + +/*! + * @brief Configures the DSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base DSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type dspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type dspi_pcs_polarity_config_t. + */ +static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Master fill up the TX FIFO with data. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Slave fill up the TX FIFO with data. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API as it is called from other driver functions. + */ +static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief DSPI common interrupt handler. + * + * @param base DSPI peripheral address. + * @param handle pointer to g_dspiHandle which stores the transfer state. + */ +static void DSPI_CommonIRQHandler(SPI_Type *base, void *param); + +/*! + * @brief Master prepare the transfer. + * Basically it set up dspi_master_handle . + * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function. + */ +static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint32_t s_baudratePrescaler[] = {2, 3, 5, 7}; +static const uint32_t s_baudrateScaler[] = {2, 4, 6, 8, 16, 32, 64, 128, + 256, 512, 1024, 2048, 4096, 8192, 16384, 32768}; + +static const uint32_t s_delayPrescaler[] = {1, 3, 5, 7}; +static const uint32_t s_delayScaler[] = {2, 4, 8, 16, 32, 64, 128, 256, + 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536}; + +/*! @brief Pointers to dspi bases for each instance. */ +static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS; + +/*! @brief Pointers to dspi IRQ number for each instance. */ +static IRQn_Type const s_dspiIRQ[] = SPI_IRQS; + +/*! @brief Pointers to dspi clocks for each instance. */ +static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS; + +/*! @brief Pointers to dspi handles for each instance. */ +static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT]; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static dspi_master_isr_t s_dspiMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static dspi_slave_isr_t s_dspiSlaveIsr; + +/********************************************************************************************************************** +* Code +*********************************************************************************************************************/ +uint32_t DSPI_GetInstance(SPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++) + { + if (s_dspiBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DSPI_COUNT); + + return instance; +} + +void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + uint32_t temp; + /* enable DSPI clock */ + CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); + + DSPI_Enable(base, true); + DSPI_StopTransfer(base); + + DSPI_SetMasterSlaveMode(base, kDSPI_Master); + + temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | + SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); + + base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) | + SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) | + SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) | + SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); + + DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + if (0 == DSPI_MasterSetBaudRate(base, masterConfig->whichCtar, masterConfig->ctarConfig.baudRate, srcClock_Hz)) + { + assert(false); + } + + temp = base->CTAR[masterConfig->whichCtar] & + ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); + + base->CTAR[masterConfig->whichCtar] = + temp | SPI_CTAR_FMSZ(masterConfig->ctarConfig.bitsPerFrame - 1) | SPI_CTAR_CPOL(masterConfig->ctarConfig.cpol) | + SPI_CTAR_CPHA(masterConfig->ctarConfig.cpha) | SPI_CTAR_LSBFE(masterConfig->ctarConfig.direction); + + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_PcsToSck, srcClock_Hz, + masterConfig->ctarConfig.pcsToSckDelayInNanoSec); + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_LastSckToPcs, srcClock_Hz, + masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec); + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz, + masterConfig->ctarConfig.betweenTransferDelayInNanoSec); + + DSPI_StartTransfer(base); +} + +void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) +{ + masterConfig->whichCtar = kDSPI_Ctar0; + masterConfig->ctarConfig.baudRate = 500000; + masterConfig->ctarConfig.bitsPerFrame = 8; + masterConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + masterConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + masterConfig->ctarConfig.direction = kDSPI_MsbFirst; + + masterConfig->ctarConfig.pcsToSckDelayInNanoSec = 1000; + masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec = 1000; + masterConfig->ctarConfig.betweenTransferDelayInNanoSec = 1000; + + masterConfig->whichPcs = kDSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kDSPI_PcsActiveLow; + + masterConfig->enableContinuousSCK = false; + masterConfig->enableRxFifoOverWrite = false; + masterConfig->enableModifiedTimingFormat = false; + masterConfig->samplePoint = kDSPI_SckToSin0Clock; +} + +void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) +{ + uint32_t temp = 0; + + /* enable DSPI clock */ + CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); + + DSPI_Enable(base, true); + DSPI_StopTransfer(base); + + DSPI_SetMasterSlaveMode(base, kDSPI_Slave); + + temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | + SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); + + base->MCR = temp | SPI_MCR_CONT_SCKE(slaveConfig->enableContinuousSCK) | + SPI_MCR_MTFE(slaveConfig->enableModifiedTimingFormat) | + SPI_MCR_ROOE(slaveConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(slaveConfig->samplePoint) | + SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); + + DSPI_SetOnePcsPolarity(base, kDSPI_Pcs0, kDSPI_PcsActiveLow); + + temp = base->CTAR[slaveConfig->whichCtar] & + ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); + + base->CTAR[slaveConfig->whichCtar] = temp | SPI_CTAR_SLAVE_FMSZ(slaveConfig->ctarConfig.bitsPerFrame - 1) | + SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) | + SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha); + + DSPI_StartTransfer(base); +} + +void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) +{ + slaveConfig->whichCtar = kDSPI_Ctar0; + slaveConfig->ctarConfig.bitsPerFrame = 8; + slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + + slaveConfig->enableContinuousSCK = false; + slaveConfig->enableRxFifoOverWrite = false; + slaveConfig->enableModifiedTimingFormat = false; + slaveConfig->samplePoint = kDSPI_SckToSin0Clock; +} + +void DSPI_Deinit(SPI_Type *base) +{ + DSPI_StopTransfer(base); + DSPI_Enable(base, false); + + /* disable DSPI clock */ + CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]); +} + +static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t temp; + + temp = base->MCR; + + if (activeLowOrHigh == kDSPI_PcsActiveLow) + { + temp |= SPI_MCR_PCSIS(pcs); + } + else + { + temp &= ~SPI_MCR_PCSIS(pcs); + } + + base->MCR = temp; +} + +uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz) +{ + /* for master mode configuration, if slave mode detected, return 0*/ + if (!DSPI_IsMaster(base)) + { + return 0; + } + uint32_t temp; + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t dbr, bestDbr; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t baudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the requested value */ + min_diff = 0xFFFFFFFFU; + bestPrescaler = 0; + bestScaler = 0; + bestDbr = 1; + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 16) && min_diff; scaler++) + { + for (dbr = 1; (dbr < 3) && min_diff; dbr++) + { + realBaudrate = ((srcClock_Hz * dbr) / (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler]))); + + /* calculate the baud rate difference based on the conditional statement that states that the calculated + * baud rate must not exceed the desired baud rate. + */ + if (baudrate >= realBaudrate) + { + diff = baudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + bestDbr = dbr; + } + } + } + } + } + + /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ + temp = base->CTAR[whichCtar] & ~(SPI_CTAR_DBR_MASK | SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK); + + base->CTAR[whichCtar] = temp | ((bestDbr - 1) << SPI_CTAR_DBR_SHIFT) | (bestPrescaler << SPI_CTAR_PBR_SHIFT) | + (bestScaler << SPI_CTAR_BR_SHIFT); + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +void DSPI_MasterSetDelayScaler( + SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay) +{ + /* these settings are only relevant in master mode */ + if (DSPI_IsMaster(base)) + { + switch (whichDelay) + { + case kDSPI_PcsToSck: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK)) | + SPI_CTAR_PCSSCK(prescaler) | SPI_CTAR_CSSCK(scaler); + break; + case kDSPI_LastSckToPcs: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PASC_MASK) & (~SPI_CTAR_ASC_MASK)) | + SPI_CTAR_PASC(prescaler) | SPI_CTAR_ASC(scaler); + break; + case kDSPI_BetweenTransfer: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PDT_MASK) & (~SPI_CTAR_DT_MASK)) | + SPI_CTAR_PDT(prescaler) | SPI_CTAR_DT(scaler); + break; + default: + break; + } + } +} + +uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, + uint32_t srcClock_Hz, + uint32_t delayTimeInNanoSec) +{ + /* for master mode configuration, if slave mode detected, return 0 */ + if (!DSPI_IsMaster(base)) + { + return 0; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realDelay, bestDelay; + uint32_t diff, min_diff; + uint32_t initialDelayNanoSec; + + /* find combination of prescaler and scaler resulting in the delay closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + /* Initialize prescaler and scaler to their max values to generate the max delay */ + bestPrescaler = 0x3; + bestScaler = 0xF; + bestDelay = (((1000000000U * 4) / srcClock_Hz) * s_delayPrescaler[bestPrescaler] * s_delayScaler[bestScaler]) / 4; + + /* First calculate the initial, default delay */ + initialDelayNanoSec = 1000000000U / srcClock_Hz * 2; + + /* If the initial, default delay is already greater than the desired delay, then + * set the delays to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + DSPI_MasterSetDelayScaler(base, whichCtar, 0, 0, whichDelay); + return initialDelayNanoSec; + } + + /* In all for loops, if min_diff = 0, the exit for loop */ + for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 16) && min_diff; scaler++) + { + realDelay = ((4000000000U / srcClock_Hz) * s_delayPrescaler[prescaler] * s_delayScaler[scaler]) / 4; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = realDelay - delayTimeInNanoSec; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + } + + /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ + DSPI_MasterSetDelayScaler(base, whichCtar, bestPrescaler, bestScaler, whichDelay); + + /* return the actual calculated baud rate */ + return bestDelay; +} + +void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) +{ + command->isPcsContinuous = false; + command->whichCtar = kDSPI_Ctar0; + command->whichPcs = kDSPI_Pcs0; + command->isEndOfQueue = false; + command->clearTransferCount = false; +} + +void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR = data; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR_SLAVE = data; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) +{ + if (mask & SPI_RSER_TFFF_RE_MASK) + { + base->RSER &= ~SPI_RSER_TFFF_DIRS_MASK; + } + if (mask & SPI_RSER_RFDF_RE_MASK) + { + base->RSER &= ~SPI_RSER_RFDF_DIRS_MASK; + } + base->RSER |= mask; +} + +/*Transactional APIs -- Master*/ + +void DSPI_MasterTransferCreateHandle(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + g_dspiHandle[DSPI_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; +} + +status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) +{ + assert(transfer); + + uint16_t wordToSend = 0; + uint16_t wordReceived = 0; + uint8_t dummyData = DSPI_MASTER_DUMMY_DATA; + uint8_t bitsPerFrame; + + uint32_t command; + uint32_t lastCommand; + + uint8_t *txData; + uint8_t *rxData; + uint32_t remainingSendByteCount; + uint32_t remainingReceiveByteCount; + + uint32_t fifoSize; + dspi_command_data_config_t commandStruct; + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + DSPI_StopTransfer(base); + DSPI_DisableInterrupts(base, kDSPI_AllInterruptEnable); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + /*Calculate the command and lastCommand*/ + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + + command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + /*Calculate the bitsPerFrame*/ + bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + txData = transfer->txData; + rxData = transfer->rxData; + remainingSendByteCount = transfer->dataSize; + remainingReceiveByteCount = transfer->dataSize; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + fifoSize = 1; + } + else + { + fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + + DSPI_StartTransfer(base); + + if (bitsPerFrame <= 8) + { + while (remainingSendByteCount > 0) + { + if (remainingSendByteCount == 1) + { + while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + base->PUSHR = (*txData) | (lastCommand); + txData++; + } + else + { + base->PUSHR = (lastCommand) | (dummyData); + } + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + remainingSendByteCount--; + + while (remainingReceiveByteCount > 0) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + /* Read data from POPR*/ + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + else + { + /*Wait until Tx Fifo is not full*/ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + if (txData != NULL) + { + base->PUSHR = command | (uint16_t)(*txData); + txData++; + } + else + { + base->PUSHR = command | dummyData; + } + remainingSendByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + } + else + { + while (remainingSendByteCount > 0) + { + if (remainingSendByteCount <= 2) + { + while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (rxData != NULL) + { + *rxData = wordReceived; + ++rxData; + *rxData = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + wordToSend = *(txData); + ++txData; + + if (remainingSendByteCount > 1) + { + wordToSend |= (unsigned)(*(txData)) << 8U; + ++txData; + } + } + else + { + wordToSend = dummyData; + } + + base->PUSHR = lastCommand | wordToSend; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + remainingSendByteCount = 0; + + while (remainingReceiveByteCount > 0) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (remainingReceiveByteCount != 1) + { + if (rxData != NULL) + { + *(rxData) = wordReceived; + ++rxData; + *(rxData) = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + } + else + { + if (rxData != NULL) + { + *(rxData) = wordReceived; + ++rxData; + } + remainingReceiveByteCount--; + } + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + else + { + /*Wait until Tx Fifo is not full*/ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + wordToSend = *(txData); + ++txData; + wordToSend |= (unsigned)(*(txData)) << 8U; + ++txData; + } + else + { + wordToSend = dummyData; + } + base->PUSHR = command | wordToSend; + remainingSendByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (rxData != NULL) + { + *rxData = wordReceived; + ++rxData; + *rxData = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + } + + return kStatus_Success; +} + +static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) +{ + dspi_command_data_config_t commandStruct; + + DSPI_StopTransfer(base); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + handle->fifoSize = 1; + } + else + { + handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; +} + +status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + handle->state = kDSPI_Busy; + + DSPI_MasterTransferPrepare(base, handle, transfer); + DSPI_StartTransfer(base); + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + + DSPI_MasterTransferFillUpTxFifo(base, handle); + + /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt + * Since SPI is a synchronous interface, we only need to enable the RX interrupt. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ; + + DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + + return kStatus_Success; +} + +status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->remainingReceiveByteCount; + return kStatus_Success; +} + +static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle) +{ + /* Disable interrupt requests*/ + DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); + + status_t status = 0; + if (handle->state == kDSPI_Error) + { + status = kStatus_DSPI_Error; + } + else + { + status = kStatus_Success; + } + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } + + /* The transfer is complete.*/ + handle->state = kDSPI_Idle; +} + +static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle) +{ + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_MASTER_DUMMY_DATA; + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + /* Fill the fifo until it is full or until the send word count is 0 or until the difference + * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. + * The reason for checking the difference is to ensure we only send as much as the + * RX FIFO can receive. + * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the + * send data, hence the difference between the remainingReceiveByteCount and + * remainingSendByteCount must be divided by 2 to convert this difference into a + * 16-bit (2 byte) value. + */ + while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && + ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) / 2 < handle->fifoSize)) + { + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->remainingSendByteCount == 1) + { + wordToSend = *(handle->txData); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = dummyData; + } + handle->remainingSendByteCount = 0; + base->PUSHR = handle->lastCommand | wordToSend; + } + /* For all words except the last word */ + else + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* increment to next data byte */ + } + else + { + wordToSend = dummyData; + } + handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ + base->PUSHR = handle->command | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* exit loop if send count is zero, else update local variables for next loop */ + if (handle->remainingSendByteCount == 0) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + /* Optimized for bits/frame less than or equal to one byte. */ + else + { + /* Fill the fifo until it is full or until the send word count is 0 or until the difference + * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. + * The reason for checking the difference is to ensure we only send as much as the + * RX FIFO can receive. + */ + while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && + ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) < handle->fifoSize)) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + base->PUSHR = handle->lastCommand | wordToSend; + } + else + { + base->PUSHR = handle->command | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + --handle->remainingSendByteCount; + + /* exit loop if send count is zero, else update local variables for next loop */ + if (handle->remainingSendByteCount == 0) + { + break; + } + } + } +} + +void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) +{ + DSPI_StopTransfer(base); + + /* Disable interrupt requests*/ + DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); + + handle->state = kDSPI_Idle; +} + +void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) +{ + /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */ + if (handle->remainingReceiveByteCount) + { + /* Check read buffer.*/ + uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */ + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + /* clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* Store read bytes into rx buffer only if a buffer pointer was provided */ + if (handle->rxData) + { + /* For the last word received, if there is an extra byte due to the odd transfer + * byte count, only save the the last byte and discard the upper byte + */ + if (handle->remainingReceiveByteCount == 1) + { + *handle->rxData = wordReceived; /* Write first data byte */ + --handle->remainingReceiveByteCount; + } + else + { + *handle->rxData = wordReceived; /* Write first data byte */ + ++handle->rxData; /* increment to next data byte */ + *handle->rxData = wordReceived >> 8; /* Write second data byte */ + ++handle->rxData; /* increment to next data byte */ + handle->remainingReceiveByteCount -= 2; + } + } + else + { + if (handle->remainingReceiveByteCount == 1) + { + --handle->remainingReceiveByteCount; + } + else + { + handle->remainingReceiveByteCount -= 2; + } + } + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } /* End of RX FIFO drain while loop */ + } + /* Optimized for bits/frame less than or equal to one byte. */ + else + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + /* clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* Store read bytes into rx buffer only if a buffer pointer was provided */ + if (handle->rxData) + { + *handle->rxData = wordReceived; + ++handle->rxData; + } + + --handle->remainingReceiveByteCount; + + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } /* End of RX FIFO drain while loop */ + } + } + + /* Check write buffer. We always have to send a word in order to keep the transfer + * moving. So if the caller didn't provide a send buffer, we just send a zero. + */ + if (handle->remainingSendByteCount) + { + DSPI_MasterTransferFillUpTxFifo(base, handle); + } + + /* Check if we're done with this transfer.*/ + if ((handle->remainingSendByteCount == 0) && (handle->remainingReceiveByteCount == 0)) + { + /* Complete the transfer and disable the interrupts */ + DSPI_MasterTransferComplete(base, handle); + } +} + +/*Transactional APIs -- Slave*/ +void DSPI_SlaveTransferCreateHandle(SPI_Type *base, + dspi_slave_handle_t *handle, + dspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + g_dspiHandle[DSPI_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; +} + +status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If receive length is zero */ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + handle->state = kDSPI_Busy; + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + + /* Store transfer information */ + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->errorCount = 0; + + uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; + handle->bitsPerFrame = + (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; + + DSPI_StopTransfer(base); + + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + DSPI_StartTransfer(base); + + /* Prepare data to transmit */ + DSPI_SlaveTransferFillUpTxFifo(base, handle); + + s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ; + + /* Enable RX FIFO drain request, the slave only use this interrupt */ + DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + + if (handle->rxData) + { + /* RX FIFO overflow request enable */ + DSPI_EnableInterrupts(base, kDSPI_RxFifoOverflowInterruptEnable); + } + if (handle->txData) + { + /* TX FIFO underflow request enable */ + DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable); + } + + return kStatus_Success; +} + +status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->remainingReceiveByteCount; + return kStatus_Success; +} + +static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle) +{ + uint16_t transmitData = 0; + uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA; + + /* Service the transmitter, if transmit buffer provided, transmit the data, + * else transmit dummy pattern + */ + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + /* Transmit data */ + if (handle->remainingSendByteCount > 0) + { + /* Have data to transmit, update the transmit data and push to FIFO */ + if (handle->bitsPerFrame <= 8) + { + /* bits/frame is 1 byte */ + if (handle->txData) + { + /* Update transmit data and transmit pointer */ + transmitData = *handle->txData; + handle->txData++; + } + else + { + transmitData = dummyPattern; + } + + /* Decrease remaining dataSize */ + --handle->remainingSendByteCount; + } + /* bits/frame is 2 bytes */ + else + { + /* With multibytes per frame transmission, the transmit frame contains data from + * transmit buffer until sent dataSize matches user request. Other bytes will set to + * dummy pattern value. + */ + if (handle->txData) + { + /* Update first byte of transmit data and transmit pointer */ + transmitData = *handle->txData; + handle->txData++; + + if (handle->remainingSendByteCount == 1) + { + /* Decrease remaining dataSize */ + --handle->remainingSendByteCount; + /* Update second byte of transmit data to second byte of dummy pattern */ + transmitData = transmitData | (uint16_t)(((uint16_t)dummyPattern) << 8); + } + else + { + /* Update second byte of transmit data and transmit pointer */ + transmitData = transmitData | (uint16_t)((uint16_t)(*handle->txData) << 8); + handle->txData++; + handle->remainingSendByteCount -= 2; + } + } + else + { + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + } + else + { + handle->remainingSendByteCount -= 2; + } + transmitData = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; + } + } + } + else + { + break; + } + + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = transmitData; + + /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } +} + +static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle) +{ + /* Disable interrupt requests */ + DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | + kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); + + /* The transfer is complete. */ + handle->txData = NULL; + handle->rxData = NULL; + handle->remainingReceiveByteCount = 0; + handle->remainingSendByteCount = 0; + + status_t status = 0; + if (handle->state == kDSPI_Error) + { + status = kStatus_DSPI_Error; + } + else + { + status = kStatus_Success; + } + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } + + handle->state = kDSPI_Idle; +} + +void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) +{ + DSPI_StopTransfer(base); + + /* Disable interrupt requests */ + DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | + kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); + + handle->state = kDSPI_Idle; + handle->remainingSendByteCount = 0; + handle->remainingReceiveByteCount = 0; +} + +void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) +{ + uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA; + uint32_t dataReceived; + uint32_t dataSend = 0; + + /* Because SPI protocol is synchronous, the number of bytes that that slave received from the + * master is the actual number of bytes that the slave transmitted to the master. So we only + * monitor the received dataSize to know when the transfer is complete. + */ + if (handle->remainingReceiveByteCount > 0) + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + /* Have received data in the buffer. */ + dataReceived = base->POPR; + /*Clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* If bits/frame is one byte */ + if (handle->bitsPerFrame <= 8) + { + if (handle->rxData) + { + /* Receive buffer is not null, store data into it */ + *handle->rxData = dataReceived; + ++handle->rxData; + } + /* Descrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + dataSend = *handle->txData; + ++handle->txData; + } + else + { + dataSend = dummyPattern; + } + + --handle->remainingSendByteCount; + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = dataSend; + } + } + else /* If bits/frame is 2 bytes */ + { + /* With multibytes frame receiving, we only receive till the received dataSize + * matches user request. Other bytes will be ignored. + */ + if (handle->rxData) + { + /* Receive buffer is not null, store first byte into it */ + *handle->rxData = dataReceived; + ++handle->rxData; + + if (handle->remainingReceiveByteCount == 1) + { + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + } + else + { + /* Receive buffer is not null, store second byte into it */ + *handle->rxData = dataReceived >> 8; + ++handle->rxData; + handle->remainingReceiveByteCount -= 2; + } + } + /* If no handle->rxData*/ + else + { + if (handle->remainingReceiveByteCount == 1) + { + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + } + else + { + handle->remainingReceiveByteCount -= 2; + } + } + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + dataSend = *handle->txData; + ++handle->txData; + + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + dataSend |= (uint16_t)((uint16_t)(dummyPattern) << 8); + } + else + { + dataSend |= (uint32_t)(*handle->txData) << 8; + ++handle->txData; + handle->remainingSendByteCount -= 2; + } + } + /* If no handle->txData*/ + else + { + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + } + else + { + handle->remainingSendByteCount -= 2; + } + dataSend = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; + } + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = dataSend; + } + } + /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } + } + /* Check if remaining receive byte count matches user request */ + if ((handle->remainingReceiveByteCount == 0) || (handle->state == kDSPI_Error)) + { + /* Other cases, stop the transfer. */ + DSPI_SlaveTransferComplete(base, handle); + return; + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoUnderflowFlag) && (base->RSER & SPI_RSER_TFUF_RE_MASK)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoUnderflowFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kDSPI_Error; + } + handle->errorCount++; + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if ((DSPI_GetStatusFlags(base) & kDSPI_RxFifoOverflowFlag) && (base->RSER & SPI_RSER_RFOF_RE_MASK)) + { + DSPI_ClearStatusFlags(base, kDSPI_RxFifoOverflowFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kDSPI_Error; + } + handle->errorCount++; + } +} + +static void DSPI_CommonIRQHandler(SPI_Type *base, void *param) +{ + if (DSPI_IsMaster(base)) + { + s_dspiMasterIsr(base, (dspi_master_handle_t *)param); + } + else + { + s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param); + } +} + +#if defined(SPI0) +void SPI0_DriverIRQHandler(void) +{ + assert(g_dspiHandle[0]); + DSPI_CommonIRQHandler(SPI0, g_dspiHandle[0]); +} +#endif + +#if defined(SPI1) +void SPI1_DriverIRQHandler(void) +{ + assert(g_dspiHandle[1]); + DSPI_CommonIRQHandler(SPI1, g_dspiHandle[1]); +} +#endif + +#if defined(SPI2) +void SPI2_DriverIRQHandler(void) +{ + assert(g_dspiHandle[2]); + DSPI_CommonIRQHandler(SPI2, g_dspiHandle[2]); +} +#endif + +#if defined(SPI3) +void SPI3_DriverIRQHandler(void) +{ + assert(g_dspiHandle[3]); + DSPI_CommonIRQHandler(SPI3, g_dspiHandle[3]); +} +#endif + +#if defined(SPI4) +void SPI4_DriverIRQHandler(void) +{ + assert(g_dspiHandle[4]); + DSPI_CommonIRQHandler(SPI4, g_dspiHandle[4]); +} +#endif + +#if defined(SPI5) +void SPI5_DriverIRQHandler(void) +{ + assert(g_dspiHandle[5]); + DSPI_CommonIRQHandler(SPI5, g_dspiHandle[5]); +} +#endif + +#if (FSL_FEATURE_SOC_DSPI_COUNT > 6) +#error "Should write the SPIx_DriverIRQHandler function that instance greater than 5 !" +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h new file mode 100755 index 00000000000..93da32fa2f7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h @@ -0,0 +1,1185 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DSPI_H_ +#define _FSL_DSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dspi + * @{ + */ + +/*! @file */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DSPI driver version 2.1.0. */ +#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @name Dummy data */ +/*@{*/ +#define DSPI_MASTER_DUMMY_DATA (0x00U) /*!< Master dummy data used for tx if there is not txData. */ +#define DSPI_SLAVE_DUMMY_DATA (0x00U) /*!< Slave dummy data used for tx if there is not txData. */ +/*@}*/ + +/*! @brief Status for the DSPI driver.*/ +enum _dspi_status +{ + kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/ + kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */ + kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/ + kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out Of range. */ +}; + +/*! @brief DSPI status flags in SPIx_SR register.*/ +enum _dspi_flags +{ + kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ + kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ + kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ + kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ + kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ + kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ + kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ + kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | + SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All status above.*/ +}; + +/*! @brief DSPI interrupt source.*/ +enum _dspi_interrupt_enable +{ + kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ + kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ + kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ + kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ + kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ + kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ + kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | + SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK + /*!< All above interrupts enable.*/ +}; + +/*! @brief DSPI DMA source.*/ +enum _dspi_dma_enable +{ + kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests. + No Tx interrupt request. */ + kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests. + No Rx interrupt request. */ +}; + +/*! @brief DSPI master or slave mode configuration.*/ +typedef enum _dspi_master_slave_mode +{ + kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/ + kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/ +} dspi_master_slave_mode_t; + +/*! + * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid + * only when CPHA bit in CTAR register is 0. + */ +typedef enum _dspi_master_sample_point +{ + kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/ + kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/ + kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/ +} dspi_master_sample_point_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/ +typedef enum _dspi_which_pcs_config +{ + kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */ + kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */ + kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */ + kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */ + kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */ + kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */ +} dspi_which_pcs_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/ +typedef enum _dspi_pcs_polarity_config +{ + kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */ + kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */ +} dspi_pcs_polarity_config_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/ +enum _dspi_pcs_polarity +{ + kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */ + kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */ + kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief DSPI clock polarity configuration for a given CTAR.*/ +typedef enum _dspi_clock_polarity +{ + kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/ + kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/ +} dspi_clock_polarity_t; + +/*! @brief DSPI clock phase configuration for a given CTAR.*/ +typedef enum _dspi_clock_phase +{ + kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} dspi_clock_phase_t; + +/*! @brief DSPI data shifter direction options for a given CTAR.*/ +typedef enum _dspi_shift_direction +{ + kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} dspi_shift_direction_t; + +/*! @brief DSPI delay type selection.*/ +typedef enum _dspi_delay_type +{ + kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */ + kDSPI_LastSckToPcs, /*!< Last SCK edge to Pcs delay. */ + kDSPI_BetweenTransfer /*!< Delay between transfers. */ +} dspi_delay_type_t; + +/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/ +typedef enum _dspi_ctar_selection +{ + kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the + same register address. */ + kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */ + kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. */ + kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. */ + kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. */ + kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. */ + kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. */ + kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. */ +} dspi_ctar_selection_t; + +#define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro , internal used. */ +#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro , internal used. */ +#define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro , internal used. */ +#define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro , internal used. */ +/*! @brief Can use this enumeration for DSPI master transfer configFlags. */ +enum _dspi_transfer_config_flag_for_master +{ + kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ + kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */ + kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */ + kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */ + kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */ + kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */ + kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */ + kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */ + + kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */ + kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */ + kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/ + kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */ + kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ + kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ + + kDSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous. */ + kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/ +}; + +#define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro , internal used. */ +#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro , internal used. */ +/*! @brief Can use this enum for DSPI slave transfer configFlags. */ +enum _dspi_transfer_config_flag_for_slave +{ + kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */ + /*!< DSPI slave can only use PCS0. */ +}; + +/*! @brief DSPI transfer state, which is used for DSPI transactional APIs' state machine. */ +enum _dspi_transfer_state +{ + kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kDSPI_Busy, /*!< Transfer queue is not finished. */ + kDSPI_Error /*!< Transfer error. */ +}; + +/*! @brief DSPI master command date configuration used for SPIx_PUSHR.*/ +typedef struct _dspi_command_data_config +{ + bool isPcsContinuous; /*!< Option to enable the continuous assertion of chip select between transfers.*/ + dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes + Register (CTAR) to use for CTAS.*/ + dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ + bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/ + bool clearTransferCount; /*!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts.*/ +} dspi_command_data_config_t; + +/*! @brief DSPI master ctar configuration structure.*/ +typedef struct _dspi_master_ctar_config +{ + uint32_t baudRate; /*!< Baud Rate for DSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ + dspi_clock_polarity_t cpol; /*!< Clock polarity. */ + dspi_clock_phase_t cpha; /*!< Clock phase. */ + dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum + delay. It sets the boundary value if out of range that can be set.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the + minimum delay.It sets the boundary value if out of range that can be + set.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum + delay.It sets the boundary value if out of range that can be set.*/ +} dspi_master_ctar_config_t; + +/*! @brief DSPI master configuration structure.*/ +typedef struct _dspi_master_config +{ + dspi_ctar_selection_t whichCtar; /*!< Desired CTAR to use. */ + dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ + + dspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs). */ + dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low. */ + + bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only + supported for CPHA = 1.*/ + bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming + data is ignored, the data from the transfer that generated the overflow + is either ignored. ROOE = 1, the incoming data is shifted in to the + shift to the shift register. */ + + bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if it's true.*/ + dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer + Format. It's valid only when CPHA=0. */ +} dspi_master_config_t; + +/*! @brief DSPI slave ctar configuration structure.*/ +typedef struct _dspi_slave_ctar_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ + dspi_clock_polarity_t cpol; /*!< Clock polarity. */ + dspi_clock_phase_t cpha; /*!< Clock phase. */ + /*!< Slave only supports MSB , does not support LSB.*/ +} dspi_slave_ctar_config_t; + +/*! @brief DSPI slave configuration structure.*/ +typedef struct _dspi_slave_config +{ + dspi_ctar_selection_t whichCtar; /*!< Desired CTAR to use. */ + dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ + + bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only + supported for CPHA = 1.*/ + bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming + data is ignored, the data from the transfer that generated the overflow + is either ignored. ROOE = 1, the incoming data is shifted in to the + shift to the shift register. */ + bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if it's true.*/ + dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer + Format. It's valid only when CPHA=0. */ +} dspi_slave_config_t; + +/*! +* @brief Forward declaration of the _dspi_master_handle typedefs. +*/ +typedef struct _dspi_master_handle dspi_master_handle_t; + +/*! +* @brief Forward declaration of the _dspi_slave_handle typedefs. +*/ +typedef struct _dspi_slave_handle dspi_slave_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral address. + * @param handle Pointer to the handle for the DSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base, + dspi_master_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral address. + * @param handle Pointer to the handle for the DSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base, + dspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief DSPI master/slave transfer structure.*/ +typedef struct _dspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t + configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the + transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer + is used for slave.*/ +} dspi_transfer_t; + +/*! @brief DSPI master transfer handle structure used for transactional API. */ +struct _dspi_master_handle +{ + uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */ + volatile uint32_t command; /*!< Desired data command. */ + volatile uint32_t lastCommand; /*!< Desired last data command. */ + + uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/ + volatile bool isThereExtraByte; /*!< Is there extra byte.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ + + dspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief DSPI slave transfer handle structure used for transactional API. */ +struct _dspi_slave_handle +{ + uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */ + volatile bool isThereExtraByte; /*!< Is there extra byte.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< DSPI transfer state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + dspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the DSPI master. + * + * This function initializes the DSPI master configuration. An example use case is as follows: + * @code + * dspi_master_config_t masterConfig; + * masterConfig.whichCtar = kDSPI_Ctar0; + * masterConfig.ctarConfig.baudRate = 500000000; + * masterConfig.ctarConfig.bitsPerFrame = 8; + * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; + * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ; + * masterConfig.whichPcs = kDSPI_Pcs0; + * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; + * masterConfig.enableContinuousSCK = false; + * masterConfig.enableRxFifoOverWrite = false; + * masterConfig.enableModifiedTimingFormat = false; + * masterConfig.samplePoint = kDSPI_SckToSin0Clock; + * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); + * @endcode + * + * @param base DSPI peripheral address. + * @param masterConfig Pointer to structure dspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the dspi_master_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). + * User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure + * before calling DSPI_MasterInit(). + * Example: + * @code + * dspi_master_config_t masterConfig; + * DSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to dspi_master_config_t structure + */ +void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig); + +/*! + * @brief DSPI slave configuration. + * + * This function initializes the DSPI slave configuration. An example use case is as follows: + * @code + * dspi_slave_config_t slaveConfig; + * slaveConfig->whichCtar = kDSPI_Ctar0; + * slaveConfig->ctarConfig.bitsPerFrame = 8; + * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * slaveConfig->enableContinuousSCK = false; + * slaveConfig->enableRxFifoOverWrite = false; + * slaveConfig->enableModifiedTimingFormat = false; + * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; + * DSPI_SlaveInit(base, &slaveConfig); + * @endcode + * + * @param base DSPI peripheral address. + * @param slaveConfig Pointer to structure dspi_master_config_t. + */ +void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the dspi_slave_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). + * User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure + * before calling DSPI_SlaveInit(). + * Example: + * @code + * dspi_slave_config_t slaveConfig; + * DSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to dspi_slave_config_t structure. + */ +void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. + * @param base DSPI peripheral address. + */ +void DSPI_Deinit(SPI_Type *base); + +/*! + * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. + * + * @param base DSPI peripheral address. + * @param enable pass true to enable module, false to disable module. + */ +static inline void DSPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~SPI_MCR_MDIS_MASK; + } + else + { + base->MCR |= SPI_MCR_MDIS_MASK; + } +} + +/*! + *@} +*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the DSPI status flag state. + * @param base DSPI peripheral address. + * @return The DSPI status(in SR register). + */ +static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Clears the DSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The + * function uses these bit positions in its algorithm to clear the desired flag state. + * Example usage: + * @code + * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag); + * @endcode + * + * @param base DSPI peripheral address. + * @param statusFlags The status flag , used from type dspi_flags. + */ +static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} +*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the DSPI interrupts. + * + * This function configures the various interrupt masks of the DSPI. The parameters are base and an interrupt mask. + * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. + * + * @code + * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable. + */ +void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the DSPI interrupts. + * + * @code + * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable. + */ +static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! + *@} +*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask. + * @code + * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask can use the enum dspi_dma_enable. + */ +static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask) +{ + base->RSER |= mask; +} + +/*! + * @brief Disables the DSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask can use the enum dspi_dma_enable. + */ +static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! + * @brief Gets the DSPI master PUSHR data register address for the DMA operation. + * + * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI master PUSHR data register address. + */ +static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->PUSHR); +} + +/*! + * @brief Gets the DSPI slave PUSHR data register address for the DMA operation. + * + * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI slave PUSHR data register address. + */ +static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->PUSHR_SLAVE); +} + +/*! + * @brief Gets the DSPI POPR data register address for the DMA operation. + * + * This function gets the DSPI POPR data register address as this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI POPR data register address. + */ +static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->POPR); +} + +/*! + *@} +*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the DSPI for master or slave. + * + * @param base DSPI peripheral address. + * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. + */ +static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode) +{ + base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode); +} + +/*! + * @brief Returns whether the DSPI module is in master mode. + * + * @param base DSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool DSPI_IsMaster(SPI_Type *base) +{ + return (bool)((base->MCR) & SPI_MCR_MSTR_MASK); +} +/*! + * @brief Starts the DSPI transfers and clears HALT bit in MCR. + * + * This function sets the module to begin data transfer in either master or slave mode. + * + * @param base DSPI peripheral address. + */ +static inline void DSPI_StartTransfer(SPI_Type *base) +{ + base->MCR &= ~SPI_MCR_HALT_MASK; +} +/*! + * @brief Stops (halts) DSPI transfers and sets HALT bit in MCR. + * + * This function stops data transfers in either master or slave mode. + * + * @param base DSPI peripheral address. + */ +static inline void DSPI_StopTransfer(SPI_Type *base) +{ + base->MCR |= SPI_MCR_HALT_MASK; +} + +/*! + * @brief Enables (or disables) the DSPI FIFOs. + * + * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently). + * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration. To enable, + * the caller must pass in a logic 1 (true). + * + * @param base DSPI peripheral address. + * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO + * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO + */ +static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo) +{ + base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) | + SPI_MCR_DIS_RXF(!enableRxFifo); +} + +/*! + * @brief Flushes the DSPI FIFOs. + * + * @param base DSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO + */ +static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) | + SPI_MCR_CLR_RXF(flushRxFifo); +} + +/*! + * @brief Configures the DSPI peripheral chip select polarity simultaneously. + * For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of + * PCSs is specific to the device. + * @code + * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow); + @endcode + * @param base DSPI peripheral address. + * @param mask The PCS polarity mask , can use the enum _dspi_pcs_polarity. + */ +static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask) +{ + base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask); +} + +/*! + * @brief Sets the DSPI baud rate in bits per second. + * + * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without + * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the + * caller also provide the frequency of the module source clock (in Hertz). + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t + * @param baudRate_Bps The desired baud rate in bits per second + * @param srcClock_Hz Module source input clock in Hertz + * @return The actual calculated baud rate + */ +uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz); + +/*! + * @brief Manually configures the delay prescaler and scaler for a particular CTAR. + * + * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar + * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT). + * + * These delay names are available in type dspi_delay_type_t. + * + * The user passes the delay to configure along with the prescaler and scaler value. + * This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply + * wish to manually increment either value. + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). + * @param scaler The scaler delay value (can be any integer between 0 to 15). + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + */ +void DSPI_MasterSetDelayScaler( + SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. + * + * This function calculates the values for: + * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or + * After SCK delay pre-scalar (PASC) and scalar (ASC), or + * Delay after transfer pre-scalar (PDT)and scalar (DT). + * + * These delay names are available in type dspi_delay_type_t. + * + * The user passes which delay they want to configure along with the desired delay value in nanoseconds. The function + * calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact + * delay match may not be possible. In this case, the closest match is calculated without going below the desired + * delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum + * supported delay is returned. The higher level peripheral driver alerts the user of an out of range delay + * input. + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + * @param srcClock_Hz Module source input clock in Hertz + * @param delayTimeInNanoSec The desired delay value in nanoseconds. + * @return The actual calculated delay value. + */ +uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, + uint32_t srcClock_Hz, + uint32_t delayTimeInNanoSec); + +/*! + * @brief Writes data into the data buffer for master mode. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example: + * @code + * dspi_command_data_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs0; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteData(base, &commandConfig, dataWord); + @endcode + * + * @param base DSPI peripheral address. + * @param command Pointer to command structure. + * @param data The data word to be sent. + */ +static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) +{ + base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); +} + +/*! + * @brief Sets the dspi_command_data_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). + * User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure + * before calling DSPI_MasterWrite_xx(). + * Example: + * @code + * dspi_command_data_config_t command; + * DSPI_GetDefaultDataCommandConfig(&command); + * @endcode + * @param command pointer to dspi_command_data_config_t structure. + */ +void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command); + +/*! + * @brief Writes data into the data buffer master mode and waits till complete to return. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example: + * @code + * dspi_command_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs1; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); + * @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, + * receive data is available when transmit completes. + * + * @param base DSPI peripheral address. + * @param command Pointer to command structure. + * @param data The data word to be sent. + */ +void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data); + +/*! + * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. + * + * This function allows the caller to pass in the data command structure and returns the command word formatted + * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the + * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or + * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps + * improve performance in cases where the command structure is constant. For example, the user calls this function + * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR + * this formatted command word with the desired data to transmit. This process increases transmit performance when + * compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a + * data word is to be sent. + * + * @param command Pointer to command structure. + * @return The command word formatted to the PUSHR data register bit field. + */ +static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command) +{ + /* Format the 16-bit command word according to the PUSHR data register bit field*/ + return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount)); +} + +/*! + * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data + * buffer, master mode and waits till complete to return. + * + * In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word + * as the data to send. + * The command portion provides characteristics of the data such as the optional continuous chip select operation +* between + * transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS + * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the + * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for + * appending this command with the data to send. This is an example: + * @code + * dataWord = <16-bit command> | <16-bit data>; + * DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord); + * @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). + * Because the SPI is a synchronous protocol, the receive data is available when transmit completes. + * + * For a blocking polling transfer, see methods below. + * Option 1: +* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); +* uint32_t data0 = command_to_send | data_need_to_send_0; +* uint32_t data1 = command_to_send | data_need_to_send_1; +* uint32_t data2 = command_to_send | data_need_to_send_2; +* +* DSPI_MasterWriteCommandDataBlocking(base,data0); +* DSPI_MasterWriteCommandDataBlocking(base,data1); +* DSPI_MasterWriteCommandDataBlocking(base,data2); +* +* Option 2: +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); +* + * @param base DSPI peripheral address. + * @param data The data word (command and data combined) to be sent + */ +void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data); + +/*! + * @brief Writes data into the data buffer in slave mode. + * + * In slave mode, up to 16-bit words may be written. + * + * @param base DSPI peripheral address. + * @param data The data to send. + */ +static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data) +{ + base->PUSHR_SLAVE = data; +} + +/*! + * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. + * + * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data + * into data register, and finally waits until the data is transmitted. + * + * @param base DSPI peripheral address. + * @param data The data to send. + */ +void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data); + +/*! + * @brief Reads data from the data buffer. + * + * @param base DSPI peripheral address. + * @return The data from the read data buffer. + */ +static inline uint32_t DSPI_ReadData(SPI_Type *base) +{ + return (base->POPR); +} + +/*! + *@} +*/ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the DSPI master handle. + * + * This function initializes the DSPI handle which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * @param base DSPI peripheral base address. + * @param handle DSPI handle pointer to dspi_master_handle_t. + * @param callback dspi callback. + * @param userData callback function parameter. + */ +void DSPI_MasterTransferCreateHandle(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief DSPI master transfer data using polling. + * + * This function transfers data with polling. This is a blocking function, which does not return until all transfers + * have been + * completed. + * + * @param base DSPI peripheral base address. + * @param transfer pointer to dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); + +/*! + * @brief DSPI master transfer data using interrupts. + * + * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all + data + * have been transferred, the callback function is called. + + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count); + +/*! + * @brief DSPI master aborts transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + */ +void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + */ +void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Initializes the DSPI slave handle. + * + * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * @param handle DSPI handle pointer to dspi_slave_handle_t. + * @param base DSPI peripheral base address. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void DSPI_SlaveTransferCreateHandle(SPI_Type *base, + dspi_slave_handle_t *handle, + dspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief DSPI slave transfers data using an interrupt. + * + * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all + * data + * have been transferred, the callback function is called. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief DSPI slave aborts a transfer using an interrupt. + * + * This function aborts transfer using an interrupt. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state. + */ +void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + * + * @param base DSPI peripheral base address. + * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state. + */ +void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + *@} +*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + /*! + *@} + */ + +#endif /*_FSL_DSPI_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c new file mode 100755 index 00000000000..4d9e129ff24 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c @@ -0,0 +1,1262 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_dspi_edma.h" + +/*********************************************************************************************************************** +* Definitons +***********************************************************************************************************************/ + +/*! +* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. +*/ +typedef struct _dspi_master_edma_private_handle +{ + SPI_Type *base; /*!< DSPI peripheral base address. */ + dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ +} dspi_master_edma_private_handle_t; + +/*! +* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. +*/ +typedef struct _dspi_slave_edma_private_handle +{ + SPI_Type *base; /*!< DSPI peripheral base address. */ + dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ +} dspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** +* Prototypes +***********************************************************************************************************************/ +/*! +* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA. +* This is not a public API as it is called from other driver functions. +*/ +static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! +* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA. +* This is not a public API as it is called from other driver functions. +*/ +static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); +/*! +* @brief Get instance number for DSPI module. +* +* This is not a public API and it's extern from fsl_dspi.c. +* +* @param base DSPI peripheral base address +*/ +extern uint32_t DSPI_GetInstance(SPI_Type *base); + +/*********************************************************************************************************************** +* Variables +***********************************************************************************************************************/ + +/*! @brief Pointers to dspi edma handles for each instance. */ +static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; +static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; + +/*********************************************************************************************************************** +* Code +***********************************************************************************************************************/ + +void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, + dspi_master_edma_handle_t *handle, + dspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToIntermediaryHandle, + edma_handle_t *edmaIntermediaryToTxRegHandle) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = DSPI_GetInstance(base); + + s_dspiMasterEdmaPrivateHandle[instance].base = base; + s_dspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle; + handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle; +} + +status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + uint32_t instance = DSPI_GetInstance(base); + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_MASTER_DUMMY_DATA; + uint8_t dataAlreadyFed = 0; + uint8_t dataFedMax = 2; + + uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); + uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base); + + edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); + + edma_transfer_config_t transferConfigA; + edma_transfer_config_t transferConfigB; + edma_transfer_config_t transferConfigC; + + handle->txBuffIfNull = ((uint32_t)DSPI_MASTER_DUMMY_DATA << 8) | DSPI_MASTER_DUMMY_DATA; + + handle->state = kDSPI_Busy; + + dspi_command_data_config_t commandStruct; + DSPI_StopTransfer(base); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + handle->fifoSize = 1; + } + else + { + handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + /* this limits the amount of data we can transfer due to the linked channel. + * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame + */ + if (handle->bitsPerFrame > 8) + { + if (transfer->dataSize > 1022) + { + return kStatus_DSPI_OutOfRange; + } + } + else + { + if (transfer->dataSize > 511) + { + return kStatus_DSPI_OutOfRange; + } + } + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback, + &s_dspiMasterEdmaPrivateHandle[instance]); + + handle->isThereExtraByte = false; + if (handle->bitsPerFrame > 8) + { + if (handle->remainingSendByteCount % 2 == 1) + { + handle->remainingSendByteCount++; + handle->remainingReceiveByteCount--; + handle->isThereExtraByte = true; + } + } + + /*If dspi has separate dma request , prepare the first data in "intermediary" . + else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to + * trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel + */ + + /*Prepare the firt data*/ + if (handle->bitsPerFrame > 8) + { + /* If it's the last word */ + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->isThereExtraByte) + { + wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else /* For all words except the last word , frame > 8bits */ + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* increment to next data byte */ + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->command = (handle->command & 0xffff0000U) | wordToSend; + } + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data word*/ + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else + { + handle->command = (handle->command & 0xffff0000U) | wordToSend; + } + } + } + + else /*dspi has shared dma request*/ + + { + /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->isThereExtraByte) + { + wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + ; + } + handle->remainingSendByteCount = 0; + base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + /* For all words except the last word */ + else + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + ; + } + handle->remainingSendByteCount -= 2; + base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + dataAlreadyFed += 2; + + /* exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else + { + base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + --handle->remainingSendByteCount; + + dataAlreadyFed++; + + /* exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + } + + /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + transferConfigA.srcAddr = (uint32_t)rxAddr; + transferConfigA.srcOffset = 0; + + if (handle->rxData) + { + transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigA.destOffset = 1; + } + else + { + transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigA.destOffset = 0; + } + + transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigA.minorLoopBytes = 1; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; + } + else + { + transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigA.minorLoopBytes = 2; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; + } + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigA, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + + /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should + write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the + SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ + EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + transferConfigB.srcAddr = (uint32_t)(handle->txData); + transferConfigB.srcOffset = 1; + } + else + { + transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigB.srcOffset = 0; + } + + transferConfigB.destAddr = (uint32_t)(&handle->command); + transferConfigB.destOffset = 0; + + transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigB.minorLoopBytes = 1; + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*already prepared the first data in "intermediary" , so minus 1 */ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1; + } + else + { + /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is + majorlink , the majorlink would not trigger the channel_C*/ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1; + } + } + else + { + transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigB.minorLoopBytes = 2; + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*already prepared the first data in "intermediary" , so minus 1 */ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + else + { + /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is + * majorlink*/ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1; + } + } + + EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL); + } + + /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to + handle the last data */ + EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); + + if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || + ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) && + (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) + { + if (handle->txData) + { + uint32_t bufferIndex = 0; + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->bitsPerFrame <= 8) + { + bufferIndex = handle->remainingSendByteCount - 1; + } + else + { + bufferIndex = handle->remainingSendByteCount - 2; + } + } + else + { + bufferIndex = handle->remainingSendByteCount; + } + + if (handle->bitsPerFrame <= 8) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1]; + } + else + { + if (handle->isThereExtraByte) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 2] | + ((uint32_t)dummyData << 8); + } + else + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | + ((uint32_t)handle->txData[bufferIndex - 1] << 8) | + handle->txData[bufferIndex - 2]; + } + } + } + else + { + if (handle->bitsPerFrame <= 8) + { + wordToSend = dummyData; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + } + + if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) || + ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0))) + { + transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand); + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + transferConfigC.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL); + } + + if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) + { + transferConfigC.srcAddr = (uint32_t)(&(handle->command)); + transferConfigC.destAddr = (uint32_t)txAddr; + + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + + if (handle->bitsPerFrame <= 8) + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1; + } + else + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD); + EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, false); + } + else + { + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL); + } + + /*Start the EDMA channel_A , channel_B , channel_C transfer*/ + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle); + EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); + + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel; + uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; + uint8_t t = 0; + if (channelPriorityLow > channelPriorityMid) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityMid; + channelPriorityMid = t; + } + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + if (channelPriorityMid > channelPriorityHigh) + { + t = channelPriorityMid; + channelPriorityMid = channelPriorityHigh; + channelPriorityHigh = t; + } + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityMid; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + } + else + { + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityMid; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + } + + /*Set the channel link. + For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C. + For DSPI instances with separate RX and TX DMA requests: + Rx DMA request -> channel_A + Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary" before the DMA + transfer and then channel_B is used to prepare the next data to "intermediary" ) */ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB + to prepare the next 32bits data (User_send_buffer to handle->command) */ + if (handle->remainingSendByteCount > 1) + { + EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink, + handle->edmaTxDataToIntermediaryHandle->channel); + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + } + else + { + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel); + + if (handle->isThereExtraByte) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorLink, handle->edmaTxDataToIntermediaryHandle->channel); + } + + EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink, + handle->edmaIntermediaryToTxRegHandle->channel); + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable); + } + + DSPI_StartTransfer(base); + + return kStatus_Success; +} + +static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle; + + dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle; + + uint32_t dataReceived; + + DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + if (dspiEdmaPrivateHandle->handle->isThereExtraByte) + { + while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK)) + { + } + dataReceived = (dspiEdmaPrivateHandle->base)->POPR; + if (dspiEdmaPrivateHandle->handle->rxData) + { + (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived; + } + } + + if (dspiEdmaPrivateHandle->handle->callback) + { + dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, + kStatus_Success, dspiEdmaPrivateHandle->handle->userData); + } + + dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; +} + +void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle) +{ + DSPI_StopTransfer(base); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle); + EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle); + + handle->state = kDSPI_Idle; +} + +status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - bytes; + + return kStatus_Success; +} + +void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, + dspi_slave_edma_handle_t *handle, + dspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = DSPI_GetInstance(base); + + s_dspiSlaveEdmaPrivateHandle[instance].base = base; + s_dspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle && transfer); + + /* If send/receive length is zero */ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); + + uint32_t instance = DSPI_GetInstance(base); + uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; + handle->bitsPerFrame = + (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; + + /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer + * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame + */ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->bitsPerFrame > 8) + { + if (transfer->dataSize > 1022) + { + return kStatus_DSPI_OutOfRange; + } + } + else + { + if (transfer->dataSize > 511) + { + return kStatus_DSPI_OutOfRange; + } + } + } + + if ((handle->bitsPerFrame > 8) && (transfer->dataSize < 2)) + { + return kStatus_InvalidArgument; + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]); + + handle->state = kDSPI_Busy; + + /* Store transfer information */ + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->errorCount = 0; + + handle->isThereExtraByte = false; + if (handle->bitsPerFrame > 8) + { + if (handle->remainingSendByteCount % 2 == 1) + { + handle->remainingSendByteCount++; + handle->remainingReceiveByteCount--; + handle->isThereExtraByte = true; + } + } + + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_SLAVE_DUMMY_DATA; + uint8_t dataAlreadyFed = 0; + uint8_t dataFedMax = 2; + + uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); + uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base); + + edma_transfer_config_t transferConfigA; + edma_transfer_config_t transferConfigC; + + DSPI_StopTransfer(base); + + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + DSPI_StartTransfer(base); + + /*if dspi has separate dma request , need not prepare data first . + else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to + slaveGetTxRegister if there is no fifo*/ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* Increment to next data byte */ + if ((handle->remainingSendByteCount == 2) && (handle->isThereExtraByte)) + { + wordToSend |= (unsigned)(dummyData) << 8U; + ++handle->txData; /* Increment to next data byte */ + } + else + { + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* Increment to next data byte */ + } + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ + base->PUSHR_SLAVE = wordToSend; + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + dataAlreadyFed += 2; + + /* Exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + /* Increment to next data word*/ + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + base->PUSHR_SLAVE = wordToSend; + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + /* Decrement remainingSendByteCount*/ + --handle->remainingSendByteCount; + + dataAlreadyFed++; + + /* Exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + } + + /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ + if (handle->remainingReceiveByteCount > 0) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + transferConfigA.srcAddr = (uint32_t)rxAddr; + transferConfigA.srcOffset = 0; + + if (handle->rxData) + { + transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigA.destOffset = 1; + } + else + { + transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigA.destOffset = 0; + } + + transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigA.minorLoopBytes = 1; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; + } + else + { + transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigA.minorLoopBytes = 2; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; + } + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigA, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + } + + if (handle->remainingSendByteCount > 0) + { + /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + /*If there is extra byte , it would use the */ + if (handle->isThereExtraByte) + { + if (handle->txData) + { + handle->txLastData = + handle->txData[handle->remainingSendByteCount - 2] | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8); + } + else + { + handle->txLastData = DSPI_SLAVE_DUMMY_DATA | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8); + } + transferConfigC.srcAddr = (uint32_t)(&(handle->txLastData)); + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + transferConfigC.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL); + } + + /*Set another transferConfigC*/ + if ((handle->isThereExtraByte) && (handle->remainingSendByteCount == 2)) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, NULL); + } + else + { + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.destOffset = 0; + + if (handle->txData) + { + transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0])); + transferConfigC.srcOffset = 1; + } + else + { + transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigC.srcOffset = 0; + if (handle->bitsPerFrame <= 8) + { + handle->txBuffIfNull = DSPI_SLAVE_DUMMY_DATA; + } + else + { + handle->txBuffIfNull = (DSPI_SLAVE_DUMMY_DATA << 8) | DSPI_SLAVE_DUMMY_DATA; + } + } + + transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigC.minorLoopBytes = 1; + transferConfigC.majorLoopCounts = handle->remainingSendByteCount; + } + else + { + transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigC.minorLoopBytes = 2; + if (handle->isThereExtraByte) + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + else + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2; + } + } + + if (handle->isThereExtraByte) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, softwareTCD); + EDMA_EnableAutoStopRequest(handle->edmaTxDataToTxRegHandle->base, + handle->edmaTxDataToTxRegHandle->channel, false); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + } + } + + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel; + uint8_t t = 0; + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &preemption_config_t); + } + else + { + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + } + + /*Set the channel link. + For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C. + For DSPI instances with separate RX and TX DMA requests: + Rx DMA request -> channel_A + Tx DMA request -> channel_C */ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel); + } + DSPI_EnableDMA(base, kDSPI_RxDmaEnable); + } + else + { + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + } + + return kStatus_Success; +} + +static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle; + + dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle; + + uint32_t dataReceived; + + DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + if (dspiEdmaPrivateHandle->handle->isThereExtraByte) + { + while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK)) + { + } + dataReceived = (dspiEdmaPrivateHandle->base)->POPR; + if (dspiEdmaPrivateHandle->handle->rxData) + { + (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived; + } + } + + if (dspiEdmaPrivateHandle->handle->callback) + { + dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, + kStatus_Success, dspiEdmaPrivateHandle->handle->userData); + } + + dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; +} + +void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle) +{ + DSPI_StopTransfer(base); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kDSPI_Idle; +} + +status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - bytes; + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h new file mode 100755 index 00000000000..326b7ee442a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DSPI_EDMA_H_ +#define _FSL_DSPI_EDMA_H_ + +#include "fsl_dspi.h" +#include "fsl_edma.h" +/*! + * @addtogroup dspi_edma_driver + * @{ + */ + +/*! @file */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! +* @brief Forward declaration of the DSPI eDMA master handle typedefs. +*/ +typedef struct _dspi_master_edma_handle dspi_master_edma_handle_t; + +/*! +* @brief Forward declaration of the DSPI eDMA slave handle typedefs. +*/ +typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the handle for the DSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base, + dspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the handle for the DSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base, + dspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief DSPI master eDMA transfer handle structure used for transactional API. */ +struct _dspi_master_edma_handle +{ + uint32_t bitsPerFrame; /*!< Desired number of bits per frame. */ + volatile uint32_t command; /*!< Desired data command. */ + volatile uint32_t lastCommand; /*!< Desired last data command. */ + + uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/ + volatile bool isThereExtraByte; /*!< Is there extra byte.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + + volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ + + dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!TCD[channel].SADDR = tcd->SADDR; + base->TCD[channel].SOFF = tcd->SOFF; + base->TCD[channel].ATTR = tcd->ATTR; + base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; + base->TCD[channel].SLAST = tcd->SLAST; + base->TCD[channel].DADDR = tcd->DADDR; + base->TCD[channel].DOFF = tcd->DOFF; + base->TCD[channel].CITER_ELINKNO = tcd->CITER; + base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; + /* Clear DONE bit first, otherwise ESG cannot be set */ + base->TCD[channel].CSR = 0; + base->TCD[channel].CSR = tcd->CSR; + base->TCD[channel].BITER_ELINKNO = tcd->BITER; +} + +void EDMA_Init(DMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + + uint32_t tmpreg; + + /* Ungate EDMA periphral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = base->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); + base->CR = tmpreg; +} + +void EDMA_Deinit(DMA_Type *base) +{ + /* Gate EDMA periphral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +} + +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + config->enableRoundRobinArbitration = false; + config->enableHaltOnError = true; + config->enableContinuousLinkMode = false; + config->enableDebugMode = false; +} + +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); +} + +void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); +} + +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].NBYTES_MLOFFYES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + base->TCD[channel].NBYTES_MLOFFYES = tmpreg; +} + +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); +} + +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Enable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI |= (0x1U << channel); + } + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Disable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI &= ~(0x1U << channel); + } + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(true); + tcd->BITER = 0U; +} + +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + /* source address */ + tcd->SADDR = config->srcAddr; + /* destination address */ + tcd->DADDR = config->destAddr; + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); + /* Source address signed offset */ + tcd->SOFF = config->srcOffset; + /* Destination address signed offset */ + tcd->DOFF = config->destOffset; + /* Minor byte transfer count */ + tcd->NBYTES = config->minorLoopBytes; + /* Current major iteration count */ + tcd->CITER = config->majorLoopCounts; + /* Starting major iteration count */ + tcd->BITER = config->majorLoopCounts; + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = (uint32_t)nextTcd; + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + } +} + +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint32_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set likned channel */ + tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint32_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; + } +} + +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t nbytes = 0; + uint32_t remainingBytes = 0; + + if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) + { + remainingBytes = 0; + } + else + { + /* Calculate the nbytes */ + if (base->TCD[channel].NBYTES_MLOFFYES & (DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK)) + { + nbytes = (base->TCD[channel].NBYTES_MLOFFYES & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> + DMA_NBYTES_MLOFFYES_NBYTES_SHIFT; + } + else + { + nbytes = + (base->TCD[channel].NBYTES_MLOFFNO & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT; + } + /* Calculate the unfinished bytes */ + if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) + { + remainingBytes = ((base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT) * + nbytes; + } + else + { + remainingBytes = + ((base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT) * + nbytes; + } + } + + return remainingBytes; +} + +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + /* Get ERROR bit flag */ + retval |= (((base->ERR >> channel) & 0x1U) << 1U); + /* Get INT bit flag */ + retval |= (((base->INT >> channel) & 0x1U) << 2U); + + return retval; +} + +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Clear DONE bit flag */ + if (mask & kEDMA_DoneFlag) + { + base->CDNE = channel; + } + /* Clear ERROR bit flag */ + if (mask & kEDMA_ErrorFlag) + { + base->CERR = channel; + } + /* Clear INT bit flag */ + if (mask & kEDMA_InterruptFlag) + { + base->CINT = channel; + } +} + +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t edmaInstance; + uint32_t channelIndex; + edma_tcd_t *tcdRegs; + + handle->base = base; + handle->channel = channel; + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; + s_EDMAHandle[channelIndex] = handle; + /* Enable NVIC interrupt */ + EnableIRQ(s_edmaIRQNumber[channelIndex]); + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0); + + /* Initialize tcd queue attibute. */ + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + handle->tcdSize = tcdSize; + handle->flags = 0; + handle->tcdPool = tcdPool; +} + +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); + assert(srcWidth == 1U || srcWidth == 2U || srcWidth == 4U || srcWidth == 16U || srcWidth == 32U); + assert(destWidth == 1U || destWidth == 2U || destWidth == 4U || destWidth == 16U || destWidth == 32U); + assert(transferBytes % bytesEachRequest == 0); + + config->destAddr = (uint32_t)destAddr; + config->srcAddr = (uint32_t)srcAddr; + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + switch (srcWidth) + { + case 1U: + config->srcTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->srcTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->srcTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->srcTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->srcTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (destWidth) + { + case 1U: + config->destTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->destTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->destTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->destTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->destTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (type) + { + case kEDMA_MemoryToMemory: + config->destOffset = destWidth; + config->srcOffset = srcWidth; + break; + case kEDMA_MemoryToPeripheral: + config->destOffset = 0U; + config->srcOffset = srcWidth; + break; + case kEDMA_PeripheralToMemory: + config->destOffset = destWidth; + config->srcOffset = 0U; + break; + default: + break; + } +} + +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + if (handle->tcdPool == NULL) + { + /* + Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because + if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit + this check mechanism, EDMA_CreatHandle will clear CSR register. + */ + if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); + /* Enable auto disable request feature */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint32_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + if (handle->tcdUsed >= handle->tcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1U; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0U; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Enable scatter/gather also in the TCD registers. */ + csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + link succeed. + */ + if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + { + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; + } +} + +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + handle->flags |= EDMA_TRANSFER_ENABLED_MASK; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & (1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +} + +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +} + +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + handle->base->TCD[handle->channel].CSR = 0; + /* Cancel all next TCD transfer. */ + handle->base->TCD[handle->channel].DLAST_SGA = 0; +} + +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Clear EDMA interrupt flag */ + handle->base->CINT = handle->channel; + if (handle->tcdPool == NULL) + { + (handle->callback)(handle, handle->userData, true, 0); + } + else /* Use the TCD queue. */ + { + uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool transfer_done; + + /* Check if transfer is already finished. */ + transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); + /* Get the offset of the current transfer TCD blcoks. */ + sga -= (uint32_t)handle->tcdPool; + /* Get the index of the current transfer TCD blcoks. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD (current one is already finished) */ + new_header = sga_index; + } + else + { + /* New header shall point to this descriptor (not finished yet) */ + new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == handle->header) + { + if (handle->tcdUsed == handle->tcdSize) + { + tcds_done = handle->tcdUsed; + } + else + { + /* Internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = new_header - handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + } + /* Advance header to the point beyond the last finished TCD block. */ + handle->header = new_header; + /* Release TCD blocks. */ + handle->tcdUsed -= tcds_done; + /* Invoke callback function. */ + if (handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + } +} + +/* 8 channels (Shared): kl28 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U + +void DMA0_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +} + +void DMA0_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +} + +void DMA0_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +} + +void DMA0_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +} +#endif /* 8 channels (Shared) */ + +/* 32 channels (Shared): k80 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_DMA16_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } +} + +void DMA1_DMA17_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } +} + +void DMA2_DMA18_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } +} + +void DMA3_DMA19_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } +} + +void DMA4_DMA20_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } +} + +void DMA5_DMA21_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } +} + +void DMA6_DMA22_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } +} + +void DMA7_DMA23_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } +} + +void DMA8_DMA24_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } +} + +void DMA9_DMA25_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } +} + +void DMA10_DMA26_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } +} + +void DMA11_DMA27_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } +} + +void DMA12_DMA28_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +} + +void DMA13_DMA29_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +} + +void DMA14_DMA30_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +} + +void DMA15_DMA31_IRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +} +#endif /* 32 channels (Shared) */ + +/* 4 channels (No Shared): kv10 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 + +void DMA0_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[0]); +} + +void DMA1_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[1]); +} + +void DMA2_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[2]); +} + +void DMA3_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[3]); +} + +/* 8 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U + +void DMA4_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[4]); +} + +void DMA5_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[5]); +} + +void DMA6_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[6]); +} + +void DMA7_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[7]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ + +/* 16 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U + +void DMA8_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[8]); +} + +void DMA9_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[9]); +} + +void DMA10_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[10]); +} + +void DMA11_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[11]); +} + +void DMA12_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[12]); +} + +void DMA13_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[13]); +} + +void DMA14_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[14]); +} + +void DMA15_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[15]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ + +/* 32 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U + +void DMA16_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[16]); +} + +void DMA17_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[17]); +} + +void DMA18_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[18]); +} + +void DMA19_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[19]); +} + +void DMA20_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[20]); +} + +void DMA21_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[21]); +} + +void DMA22_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[22]); +} + +void DMA23_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[23]); +} + +void DMA24_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[24]); +} + +void DMA25_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[25]); +} + +void DMA26_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[26]); +} + +void DMA27_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[27]); +} + +void DMA28_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[28]); +} + +void DMA29_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[29]); +} + +void DMA30_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[30]); +} + +void DMA31_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[31]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ + +#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h new file mode 100755 index 00000000000..ca9632e247a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h @@ -0,0 +1,879 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _FSL_EDMA_H_ +#define _FSL_EDMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_driver + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) + +/*! @brief Get the pointer of DCHPRIn */ +#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2G bytes. */ +} edma_modulo_t; + +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief eDMA channel status flags. */ +enum _edma_channel_status_flags +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief eDMA channel error status flags. */ +enum _edma_error_status_flags +{ + kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ + kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ + kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 + kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit will be 0, otherwise be 1 */ +}; + +/*! @brief eDMA interrupt source */ +typedef enum _edma_interrupt_enable +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +} edma_interrupt_enable_t; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA transfer status */ +enum _edma_transfer_status +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority + arbitration is used for channel selection */ + bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of + a new channel. Executing channels are allowed to complete. */ +} edma_config_t; + +/*! + * @brief eDMA transfer configuration + * + * This structure configures the source/destination transfer attribute. + * This figure shows the eDMA's transfer model: + * _________________________________________________ + * | Transfer Size | | + * Minor Loop |_______________| Major loop Count 1 | + * Bytes | Transfer Size | | + * ____________|_______________|____________________|--> Minor loop complete + * ____________________________________ + * | | | + * |_______________| Major Loop Count 2 | + * | | | + * |_______________|____________________|--> Minor loop Complete + * + * ---------------------------------------------------------> Transfer complete + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to + form the next-state value as each source read is completed. */ + int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to + form the next-state value as each destination write is completed. */ + uint16_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ + uint32_t majorLoopCounts; /*!< Major loop iteration count. */ +} edma_transfer_config_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for minor loop mapping. */ +} edma_minor_offset_config_t; + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure scatter/gather feature as a next hardware TCD. + */ +typedef struct _edma_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_tcd_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define Callback function for eDMA. */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + DMA_Type *base; /*!< eDMA peripheral base address. */ + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint8_t channel; /*!< eDMA channel number. */ + volatile int8_t header; /*!< The first TCD index. */ + volatile int8_t tail; /*!< The last TCD index. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ + uint8_t flags; /*!< The status of the current channel. */ +} edma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes eDMA peripheral. + * + * This function ungates the eDMA clock and configure eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config Pointer to configuration structure, see "edma_config_t". + * @note This function enable the minor loop map feature. + */ +void EDMA_Init(DMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(DMA_Type *base); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to a default value. + * The default configuration is set to the following value: + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config Pointer to eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +/*! + * @brief Sets all TCD registers to a default value. + * + * This function sets TCD registers for this channel to default value. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is on-going, + * or it will case unpredicated results. + * @note This function will enable auto stop request feature. + */ +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configure the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if user + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature will be enabled. + * And DREQ bit will be cleared in the previous transfer configuration which + * will be set in eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(DMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * Minor offset means signed-extended value added to source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to Minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config Pointer to channel preemption configuration structure. + */ +static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, + uint32_t channel, + const edma_channel_Preemption_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + DMA_DCHPRIn(base, channel) = + (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | + DMA_DCHPRI0_CHPRI(config->channelPriority)); +} + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures minor link or major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid. + */ +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth Bandwidth setting, it can be one of: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); + +/*! + * @brief Sets the source modulo and destination modulo for eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo Source modulo value. + * @param destModulo Destination modulo value. + */ +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command for enable(ture) or disable(false). + */ +static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); +} +#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command for enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. User need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function will enable auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers. + * STCD is used in scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if user + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned, or it will cause eDMA error. + * @note If nextTcd is not NULL, it means scatter gather feature will be enabled. + * And DREQ bit will be cleared in the previous transfer configuration which + * will be set in EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * Minor offset is a signed-extended value added to the source address or destination + * address after each minor loop. + * + * @param tcd Point to the TCD structure. + * @param config Pointer to Minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted. + * + * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd Point to the TCD structure. + * @param bandWidth Bandwidth setting, it can be one of: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +/*! + * @brief Sets the source modulo and destination modulo for eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd Point to the TCD structure. + * @param srcModulo Source modulo value. + * @param destModulo Destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd Point to the TCD structure. + * @param enable The command for enable(ture) or disable(false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. User need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. User need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SERQ = DMA_SERQ_SERQ(channel); +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CERQ = DMA_CERQ_CERQ(channel); +} + +/*! + * @brief Starts the eDMA transfer by software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SSRT = DMA_SSRT_SSRT(channel); +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the Remaining bytes from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the the number of bytes that have not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Bytes have not been transferred yet for the current TCD. + * @note This function can only be used to get unfinished bytes of transfer without + * the next TCD, or it might be inaccuracy. + */ +uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. User need to use the + * _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) +{ + return base->ES; +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. User need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. User need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using transaction API for eDMA. This function + * initializes the internal state of eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. + * + * @param handle eDMA handle pointer. + * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData Parameter for callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief eDMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stop transfer. + * + * This function disables the channel request to pause the transfer. User can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA abort transfer. + * + * This function disables the channel request and clear transfer status bits. + * User can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA IRQ handler for current major loop transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_EDMA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c new file mode 100755 index 00000000000..1a71a07e582 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ewm.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void EWM_Init(EWM_Type *base, const ewm_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + + CLOCK_EnableClock(kCLOCK_Ewm0); + value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | + EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + base->CLKPRESCALER = config->prescaler; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + base->CLKCTRL = config->clockSource; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ + + base->CMPL = config->compareLowValue; + base->CMPH = config->compareHighValue; + base->CTRL = value; +} + +void EWM_Deinit(EWM_Type *base) +{ + EWM_DisableInterrupts(base, kEWM_InterruptEnable); + CLOCK_DisableClock(kCLOCK_Ewm0); +} + +void EWM_GetDefaultConfig(ewm_config_t *config) +{ + assert(config); + + config->enableEwm = true; + config->enableEwmInput = false; + config->setInputAssertLogic = false; + config->enableInterrupt = false; +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + config->clockSource = kEWM_LpoClockSource0; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + config->prescaler = 0U; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + config->compareLowValue = 0U; + config->compareHighValue = 0xFEU; +} + +void EWM_Refresh(EWM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; + EnableGlobalIRQ(primaskValue); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h new file mode 100755 index 00000000000..a5c45b3fe76 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_EWM_H_ +#define _FSL_EWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ewm_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EWM driver version 2.0.1. */ +#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Describes ewm clock source. */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT +typedef enum _ewm_lpo_clock_source +{ + kEWM_LpoClockSource0 = 0U, /*!< ewm clock sourced from lpo_clk[0]*/ + kEWM_LpoClockSource1 = 1U, /*!< ewm clock sourced from lpo_clk[1]*/ + kEWM_LpoClockSource2 = 2U, /*!< ewm clock sourced from lpo_clk[2]*/ + kEWM_LpoClockSource3 = 3U, /*!< ewm clock sourced from lpo_clk[3]*/ +} ewm_lpo_clock_source_t; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ + +/*! +* @brief Data structure for EWM configuration. +* +* This structure is used to configure the EWM. +*/ +typedef struct _ewm_config +{ + bool enableEwm; /*!< Enable EWM module */ + bool enableEwmInput; /*!< Enable EWM_in input */ + bool setInputAssertLogic; /*!< EWM_in signal assertion state */ + bool enableInterrupt; /*!< Enable EWM interrupt */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t prescaler; /*!< Clock prescaler value */ +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + uint8_t compareLowValue; /*!< Compare low register value */ + uint8_t compareHighValue; /*!< Compare high register value */ +} ewm_config_t; + +/*! + * @brief EWM interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the EWM interrupt configurations. + */ +enum _ewm_interrupt_enable_t +{ + kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable EWM to generate an interrupt*/ +}; + +/*! + * @brief EWM status flags. + * + * This structure contains the constants for the EWM status flags for use in the EWM functions. + */ +enum _ewm_status_flags_t +{ + kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when ewm is enabled*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name EWM Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that except for interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * Example: + * @code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * @endcode + * + * @param base EWM peripheral base address + * @param config The configuration of EWM +*/ +void EWM_Init(EWM_Type *base, const ewm_config_t *config); + +/*! + * @brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * @param base EWM peripheral base address +*/ +void EWM_Deinit(EWM_Type *base); + +/*! + * @brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configure structure to default values. The default + * values are: + * @code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * @endcode + * + * @param config Pointer to EWM configuration structure. + * @see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config); + +/* @} */ + +/*! + * @name EWM functional Operation + * @{ + */ + +/*! + * @brief Enables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined: + * @arg kEWM_InterruptEnable + */ +static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL |= mask; +} + +/*! + * @brief Disables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined: + * @arg kEWM_InterruptEnable + */ +static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL &= ~mask; +} + +/*! + * @brief Gets EWM all status flags. + * + * This function gets all status flags. + * + * Example for getting Running Flag: + * @code + * uint32_t status; + * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; + * @endcode + * @param base EWM peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) +{ + return (base->CTRL & EWM_CTRL_EWMEN_MASK); +} + +/*! + * @brief Service EWM. + * + * This function reset EWM counter to zero. + * + * @param base EWM peripheral base address +*/ +void EWM_Refresh(EWM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_EWM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c new file mode 100755 index 00000000000..2add4e96352 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c @@ -0,0 +1,2610 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flash.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Misc utility defines + * @{ + */ +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif +#ifndef ALIGN_UP +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU)) +#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU)) +#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU)) +#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU)) +#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU)) +#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \ + ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU)) +#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \ + ((uint32_t)(w)&0xFFU)) +/*@}*/ + +/*! @brief Data flash IFR map Field*/ +#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U +#endif + +/*! + * @name Reserved FlexNVM size (For a variety of purposes) defines + * @{ + */ +#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU +#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU +/*@}*/ + +/*! + * @name Flash Program Once Field defines + * @{ + */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ + 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ + 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +/* FTFL parts(eg. K20) only support 4-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 +#endif +/*@}*/ + +/*! + * @name Flash security status defines + * @{ + */ +#define FLASH_SECURITY_STATE_KEYEN 0x80U +#define FLASH_SECURITY_STATE_UNSECURED 0x02U +#define FLASH_NOT_SECURE 0x01U +#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U +#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U +/*@}*/ + +/*! + * @name Flash controller command numbers + * @{ + */ +#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ +#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ +#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ +#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ +#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ +#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ +#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ +#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ +#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ +#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ +#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ +#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ +#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ +#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ +#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ +#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ +#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ +#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ +#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ +#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ + /*@}*/ + +/*! + * @name Common flash register info defines + * @{ + */ +#if defined(FTFA) +#define FTFx FTFA +#define FTFx_BASE FTFA_BASE +#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFE) +#define FTFx FTFE +#define FTFx_BASE FTFE_BASE +#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFL) +#define FTFx FTFL +#define FTFx_BASE FTFL_BASE +#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#else +#error "Unknown flash controller" +#endif +/*@}*/ + +/*! + * @brief Enumeration for access segment property. + */ +enum _flash_access_segment_property +{ + kFLASH_accessSegmentBase = 256UL, +}; + +/*! + * @brief Enumeration for acceleration ram property. + */ +enum _flash_acceleration_ram_property +{ + kFLASH_accelerationRamSize = 0x400U +}; + +/*! + * @brief Enumeration for flash config area. + */ +enum _flash_config_area_range +{ + kFLASH_configAreaStart = 0x400U, + kFLASH_configAreaEnd = 0x40FU +}; + +/*! @brief program Flash block base address*/ +#define PFLASH_BLOCK_BASE 0x00U + +/*! @brief Total flash region count*/ +#define FSL_FEATURE_FTFx_REGION_COUNT (32U) + +/*! + * @name Flash register access type defines + * @{ + */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT +#define FTFx_REG_ACCESS_TYPE volatile uint8_t * +#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + /*@}*/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Copy flash_run_command() to RAM*/ +static void copy_flash_run_command(uint8_t *flashRunCommand); +/*! @brief Copy flash_cache_clear_command() to RAM*/ +static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand); +/*! @brief Check whether flash execute-in-ram functions are ready*/ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ +static status_t flash_command_sequence(flash_config_t *config); + +/*! @brief Perform the cache clear to the flash*/ +void flash_cache_clear(flash_config_t *config); + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline); +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info); +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Access to FTFx->FCCOB */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3; +#else +#error "Unknown flash controller" +#endif + +/*! @brief Access to FTFx->FPROT */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3; +#else +#error "Unknown flash controller" +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief A function pointer used to point to relocated flash_run_command() */ +static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat); +/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */ +static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) +/*! @brief A static buffer used to hold flash_run_command() */ +static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize]; +/*! @brief A static buffer used to hold flash_cache_clear_command() */ +static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize]; +/*! @brief Flash execute-in-ram function information */ +static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; +#endif + +/*! + * @brief Table of pflash sizes. + * + * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. + * + * The values in this table have been right shifted 10 bits so that they will all fit within + * an 16-bit integer. To get the actual flash density, you must left shift the looked up value + * by 10 bits. + * + * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is + * reserved. + * + * Code to use the table: + * @code + * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + * @endcode + */ +const uint16_t kPFlashDensities[] = { + 8, /* 0x0 - 8192, 8KB */ + 16, /* 0x1 - 16384, 16KB */ + 24, /* 0x2 - 24576, 24KB */ + 32, /* 0x3 - 32768, 32KB */ + 48, /* 0x4 - 49152, 48KB */ + 64, /* 0x5 - 65536, 64KB */ + 96, /* 0x6 - 98304, 96KB */ + 128, /* 0x7 - 131072, 128KB */ + 192, /* 0x8 - 196608, 192KB */ + 256, /* 0x9 - 262144, 256KB */ + 384, /* 0xa - 393216, 384KB */ + 512, /* 0xb - 524288, 512KB */ + 768, /* 0xc - 786432, 768KB */ + 1024, /* 0xd - 1048576, 1MB */ + 1536, /* 0xe - 1572864, 1.5MB */ + /* 2048, 0xf - 2097152, 2MB */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FLASH_Init(flash_config_t *config) +{ + uint32_t flashDensity; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* calculate the flash density from SIM_FCFG1.PFSIZE */ + uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. + * We just use the pre-defined flash size in feature file here to support pre-production parts */ + if (pfsize == 0xf) + { + flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; + } + else + { + flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + } + + /* fill out a few of the structure members */ + config->PFlashBlockBase = PFLASH_BLOCK_BASE; + config->PFlashTotalSize = flashDensity; + config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + config->PFlashAccessSegmentSize = kFLASH_accessSegmentBase << FTFx->FACSS; + config->PFlashAccessSegmentCount = FTFx->FACSN; +#else + config->PFlashAccessSegmentSize = 0; + config->PFlashAccessSegmentCount = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + config->PFlashCallback = NULL; + +/* copy required flash commands to RAM */ +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) + if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) + { + s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; + s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; + s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand; + config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; + FLASH_PrepareExecuteInRamFunctions(config); + } +#endif + + config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; + config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + { + status_t returnCode; + config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; + returnCode = flash_update_flexnvm_memory_partition_status(config); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + } +#endif + + return kStatus_FLASH_Success; +} + +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + config->PFlashCallback = callback; + + return kStatus_FLASH_Success; +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); + copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand); + flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all flash blocks */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} + +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + uint32_t sectorSize; + flash_operation_config_t flashInfo; + uint32_t endAddress; /* storing end address */ + uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + sectorSize = flashInfo.activeSectorSize; + + /* calculating Flash end address */ + endAddress = start + lengthInBytes - 1; + + /* re-calculate the endAddress and align it to the start of the next sector + * which will be used in the comparison below */ + if (endAddress % sectorSize) + { + numberOfSectors = endAddress / sectorSize + 1; + endAddress = numberOfSectors * sectorSize - 1; + } + + /* the start address will increment to the next sector address + * until it reaches the endAdddress */ + while (start <= endAddress) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* Increment to the next sector */ + start += sectorSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Prepare passing parameter to erase all flash blocks (unsecure). */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all unsecure command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ + +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all execute-only segments + * 1st element for the FCCOB register */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + + while (lengthInBytes > 0) + { + /* preparing passing parameter to program the flash block */ + kFCCOBx[1] = *src++; + if (4 == flashInfo.blockWriteUnitSize) + { + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); + } + else if (8 == flashInfo.blockWriteUnitSize) + { + kFCCOBx[2] = *src++; + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* update start address for next iteration */ + start += flashInfo.blockWriteUnitSize; + + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashInfo.blockWriteUnitSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (src == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); + + kFCCOBx[1] = *src; + +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + kFCCOBx[2] = *(src + 1); + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + uint32_t sectorSize; + flash_operation_config_t flashInfo; +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + bool needSwitchFlexRamMode = false; +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + sectorSize = flashInfo.activeSectorSize; + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsRamError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + while (lengthInBytes > 0) + { + /* Make sure the write operation doesn't span two sectors */ + uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); + uint32_t lengthTobeProgrammedOfCurrentSector; + uint32_t currentOffset = 0; + + if (endAddressOfCurrentSector == start) + { + endAddressOfCurrentSector += sectorSize; + } + + if (lengthInBytes + start > endAddressOfCurrentSector) + { + lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; + } + else + { + lengthTobeProgrammedOfCurrentSector = lengthInBytes; + } + + /* Program Current Sector */ + while (lengthTobeProgrammedOfCurrentSector > 0) + { + /* Make sure the program size doesn't exceeds Acceleration RAM size */ + uint32_t programSizeOfCurrentPass; + uint32_t numberOfPhases; + + if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize) + { + programSizeOfCurrentPass = kFLASH_accelerationRamSize; + } + else + { + programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; + } + + /* Copy data to FlexRAM */ + memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); + /* Set start address of the data to be programmed */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); + /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ + numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment; + + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); + + /* Peform command sequence */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + if (returnCode != kStatus_FLASH_Success) + { + flash_cache_clear(config); + return returnCode; + } + + lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; + currentOffset += programSizeOfCurrentPass; + } + + src += currentOffset / 4; + start += currentOffset; + lengthInBytes -= currentOffset; + } + + flash_cache_clear(config); + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Restore function of FlexRAM if needed. */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsEepromError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + bool needSwitchFlexRamMode = false; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Validates the range of the given address */ + if ((start < config->FlexRAMBlockBase) || + ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) + { + return kStatus_FLASH_AddressError; + } + + returnCode = kStatus_FLASH_Success; + + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsEepromError; + } + } + + /* Write data to FlexRAM when it is used as EEPROM emulator */ + while (lengthInBytes > 0) + { + if ((!(start & 0x3U)) && (lengthInBytes >= 4)) + { + *(uint32_t *)start = *(uint32_t *)src; + start += 4; + src += 4; + lengthInBytes -= 4; + } + else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) + { + *(uint16_t *)start = *(uint16_t *)src; + start += 2; + src += 2; + lengthInBytes -= 2; + } + else + { + *(uint8_t *)start = *src; + start += 1; + src += 1; + lengthInBytes -= 1; + } + /* Wait till EEERDY bit is set */ + while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + } + + /* Check for protection violation error */ + if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + } + + /* Switch function of FlexRAM if needed */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsRamError; + } + } + + return returnCode; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + while (lengthInBytes > 0) + { + /* preparing passing parameter */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); + if (flashInfo.resourceCmdAddressAligment == 4) + { + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else if (flashInfo.resourceCmdAddressAligment == 8) + { + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success != returnCode) + { + break; + } + + /* fetch data */ + *dst++ = kFCCOBx[1]; + if (flashInfo.resourceCmdAddressAligment == 8) + { + *dst++ = kFCCOBx[2]; + } + /* update start address for next iteration */ + start += flashInfo.resourceCmdAddressAligment; + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashInfo.resourceCmdAddressAligment; + } + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success == returnCode) + { + *dst = kFCCOBx[1]; +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + *(dst + 1) = kFCCOBx[2]; + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + } + + return returnCode; +} + +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) +{ + /* store data read from flash register */ + uint8_t registerValue; + + if ((config == NULL) || (state == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* check the status of the flash security bits in the security register */ + if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) + { + /* Flash in unsecured state */ + *state = kFLASH_securityStateNotSecure; + } + else + { + /* Flash in secured state + * check for backdoor key security enable bit */ + if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) + { + /* Backdoor key security enabled */ + *state = kFLASH_securityStateBackdoorEnabled; + } + else + { + /* Backdoor key security disabled */ + *state = kFLASH_securityStateBackdoorDisabled; + } + } + + return (kStatus_FLASH_Success); +} + +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) +{ + uint8_t registerValue; /* registerValue */ + status_t returnCode; /* return code variable */ + + if ((config == NULL) || (backdoorKey == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* set the default return code as kStatus_Success */ + returnCode = kStatus_FLASH_Success; + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* Check to see if flash is in secure state (any state other than 0x2) + * If not, then skip this since flash is not secure */ + if (0x02 != (registerValue & 0x03)) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) +{ + /* Check arguments. */ + uint32_t blockSize; + flash_operation_config_t flashInfo; + uint32_t nextBlockStartAddress; + uint32_t remainingBytes; + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + start = flashInfo.convertedAddress; + blockSize = flashInfo.activeBlockSize; + + nextBlockStartAddress = ALIGN_UP(start, blockSize); + if (nextBlockStartAddress == start) + { + nextBlockStartAddress += blockSize; + } + + remainingBytes = lengthInBytes; + + while (remainingBytes) + { + uint32_t numberOfPhrases; + uint32_t verifyLength = nextBlockStartAddress - start; + if (verifyLength > remainingBytes) + { + verifyLength = remainingBytes; + } + + numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment; + + /* Fill in verify section command parameters. */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + if (returnCode) + { + return returnCode; + } + + remainingBytes -= verifyLength; + start += verifyLength; + nextBlockStartAddress += blockSize; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if (expectedData == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + + while (lengthInBytes) + { + /* preparing passing parameter to program check the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); + kFCCOBx[2] = *expectedData; + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + if (failedAddress) + { + *failedAddress = start; + } + if (failedData) + { + *failedData = 0; + } + break; + } + + lengthInBytes -= flashInfo.checkCmdAddressAligment; + expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData); + start += flashInfo.checkCmdAddressAligment; + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify erase all execute-only segments command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state) +{ + uint32_t endAddress; /* end address for protection check */ + uint32_t protectionRegionSize; /* size of flash protection region */ + uint32_t regionCheckedCounter; /* increments each time the flash address was checked for + * protection status */ + uint32_t regionCounter; /* incrementing variable used to increment through the flash + * protection regions */ + uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ + + uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each + * protection region */ + uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1]; /* array of the start addresses for each flash + * protection region. Note this is REGION_COUNT+1 + * due to requiring the next start address after + * the end of flash for loop-check purposes below */ + status_t returnCode; + + if (protection_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + + /* calculating Flash end address */ + endAddress = start + lengthInBytes; + + /* Calculate the size of the flash protection region + * If the flash density is > 32KB, then protection region is 1/32 of total flash density + * Else if flash density is < 32KB, then flash protection region is set to 1KB */ + if (config->PFlashTotalSize > 32 * 1024) + { + protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT; + } + else + { + protectionRegionSize = 1024; + } + + /* populate the flashRegionAddress array with the start address of each flash region */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + + /* populate up to 33rd element of array, this is the next address after end of flash array */ + while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT) + { + flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter; + regionCounter++; + } + + /* populate flashRegionProtectStatus array with status information + * Protection status for each region is stored in the FPROT[3:0] registers + * Each bit represents one region of flash + * 4 registers * 8-bits-per-register = 32-bits (32-regions) + * The convention is: + * FPROT3[bit 0] is the first protection region (start of flash memory) + * FPROT0[bit 7] is the last protection region (end of flash memory) + * regionCounter is used to determine which FPROT[3:0] register to check for protection status + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT) + { + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u); + } + else if ((regionCounter >= 8) && (regionCounter < 16)) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u); + } + else if ((regionCounter >= 16) && (regionCounter < 24)) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u); + } + else + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u); + } + regionCounter++; + } + + /* loop through the flash regions and check + * desired flash address range for protection status + * loop stops when it is detected that start has exceeded the endAddress */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + regionCheckedCounter = 0; + protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ + while (start < endAddress) + { + /* check to see if the address falls within this protection region + * Note that if the entire flash is to be checked, the last protection + * region checked would consist of the last protection start address and + * the start address following the end of flash */ + if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) + { + /* increment regionCheckedCounter to indicate this region was checked */ + regionCheckedCounter++; + + /* check the protection status of this region + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + if (!flashRegionProtectStatus[regionCounter]) + { + /* increment protectStatusCounter to indicate this region is protected */ + protectStatusCounter++; + } + start += protectionRegionSize; /* increment to an address within the next region */ + } + regionCounter++; /* increment regionCounter to check for the next flash protection region */ + } + + /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ + if (protectStatusCounter == 0) + { + *protection_state = kFLASH_protectionStateUnprotected; + } + /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ + else if (protectStatusCounter == regionCheckedCounter) + { + *protection_state = kFLASH_protectionStateProtected; + } + /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed + * In other words, some regions are protected while others are unprotected */ + else + { + *protection_state = kFLASH_protectionStateMixed; + } + + return (returnCode); +} + +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state) +{ + status_t returnCode; + + if (access_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + { + uint32_t executeOnlySegmentCounter = 0; + + /* calculating end address */ + uint32_t endAddress = start + lengthInBytes; + + /* Aligning start address and end address */ + uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize); + uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize); + + uint32_t segmentIndex = 0; + uint32_t maxSupportedExecuteOnlySegmentCount = + (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize; + + while (start < endAddress) + { + uint32_t xacc; + + segmentIndex = start / config->PFlashAccessSegmentSize; + + if (segmentIndex < 32) + { + xacc = *(const volatile uint32_t *)&FTFx->XACCL3; + } + else if (segmentIndex < config->PFlashAccessSegmentCount) + { + xacc = *(const volatile uint32_t *)&FTFx->XACCH3; + segmentIndex -= 32; + } + else + { + break; + } + + /* Determine if this address range is in a execute-only protection flash segment. */ + if ((~xacc) & (1u << segmentIndex)) + { + executeOnlySegmentCounter++; + } + + start += config->PFlashAccessSegmentSize; + } + + if (executeOnlySegmentCounter < 1u) + { + *access_state = kFLASH_accessStateUnLimited; + } + else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) + { + *access_state = kFLASH_accessStateMixed; + } + else + { + *access_state = kFLASH_accessStateExecuteOnly; + } + } +#else + *access_state = kFLASH_accessStateUnLimited; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + return (returnCode); +} + +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + if ((config == NULL) || (value == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + switch (whichProperty) + { + case kFLASH_propertyPflashSectorSize: + *value = config->PFlashSectorSize; + break; + + case kFLASH_propertyPflashTotalSize: + *value = config->PFlashTotalSize; + break; + + case kFLASH_propertyPflashBlockSize: + *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + break; + + case kFLASH_propertyPflashBlockCount: + *value = config->PFlashBlockCount; + break; + + case kFLASH_propertyPflashBlockBaseAddr: + *value = config->PFlashBlockBase; + break; + + case kFLASH_propertyPflashFacSupport: +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) + *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; +#else + *value = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + break; + + case kFLASH_propertyPflashAccessSegmentSize: + *value = config->PFlashAccessSegmentSize; + break; + + case kFLASH_propertyPflashAccessSegmentCount: + *value = config->PFlashAccessSegmentCount; + break; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + case kFLASH_propertyDflashSectorSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + break; + case kFLASH_propertyDflashTotalSize: + *value = config->DFlashTotalSize; + break; + case kFLASH_propertyDflashBlockSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; + break; + case kFLASH_propertyDflashBlockCount: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + break; + case kFLASH_propertyDflashBlockBaseAddr: + *value = config->DFlashBlockBase; + break; + case kFLASH_propertyEepromTotalSize: + *value = config->EEpromTotalSize; + break; +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + + default: /* catch inputs that are not recognized */ + return kStatus_FLASH_UnknownProperty; + } + + return kStatus_FLASH_Success; +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) +{ + status_t status; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + status = flasn_check_flexram_function_option_range(option); + if (status != kStatus_FLASH_Success) + { + return status; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo) +{ + status_t returnCode; + + if ((config == NULL) || (returnInfo == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) + { + return kStatus_FLASH_AlignmentError; + } + + /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ + if ((address >= (config->PFlashTotalSize / 2)) || + ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd))) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + /* Check the option. */ + returnCode = flash_check_swap_control_option(option); + if (returnCode) + { + return returnCode; + } + + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + + returnCode = flash_command_sequence(config); + + returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5; + returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6; + returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7; + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) +{ + flash_swap_state_config_t returnInfo; + status_t returnCode; + + memset(&returnInfo, 0xFFU, sizeof(returnInfo)); + + do + { + returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + if (kFLASH_swapFunctionOptionDisable == option) + { + if (returnInfo.flashSwapState == kFLASH_swapStateDisabled) + { + return kStatus_FLASH_Success; + } + else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized) + { + /* The swap system changed to the DISABLED state with Program flash block 0 + * located at relative flash address 0x0_0000 */ + returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo); + } + else + { + /* Swap disable should be requested only when swap system is in the uninitialized state */ + return kStatus_FLASH_SwapSystemNotInUninitialized; + } + } + else + { + /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, + * the swap procedure should be Uninitialized -> Update-Erased -> Complete. + * After the first swap has been completed, the flash swap inidicator address cannot be modified + * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> + * Complete. */ + switch (returnInfo.flashSwapState) + { + case kFLASH_swapStateUninitialized: + /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo); + break; + case kFLASH_swapStateReady: + /* Validate whether the address provided to the swap system is matched to + * swap indicator address in the IFR */ + returnCode = flash_validate_swap_indicator_address(config, address); + if (returnCode == kStatus_FLASH_Success) + { + /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo); + } + break; + case kFLASH_swapStateUpdate: + /* If current swap mode is Update, Erase indicator sector in non active block + * to proceed swap system to update-erased state */ + returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), + FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey); + break; + case kFLASH_swapStateUpdateErased: + /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo); + break; + case kFLASH_swapStateComplete: + break; + case kFLASH_swapStateDisabled: + /* When swap system is in disabled state, We need to clear swap system back to uninitialized + * by issuing EraseAllBlocks command */ + returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; + break; + default: + returnCode = kStatus_FLASH_InvalidArgument; + break; + } + } + if (returnCode != kStatus_FLASH_Success) + { + break; + } + } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option))); + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 + * or it will cause access error. */ + /* eepromDataSizeCode &= 0x3FU; */ + /* flexnvmPartitionCode &= 0x0FU; */ + + /* preparing passing parameter to program the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be updated by program partition command during reset sequence, + * so we just set reserved values for partitioned FlexNVM size here */ + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ + +status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + *kFPROT = protectStatus; + + if (protectStatus != *kFPROT) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + *protectStatus = *kFPROT; + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FDPROT = protectStatus; + + if (FTFx->FDPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FDPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FEPROT = protectStatus; + + if (FTFx->FEPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FEPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Run flash command + * + * This function should be copied to RAM for execution to make sure that code works + * properly even flash cache is disabled. + * It is for flash-resident bootloader only, not technically required for ROM or + * flashloader (RAM-resident bootloader). + */ +void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) +{ + /* clear CCIF bit */ + *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) + { + } +} + +/*! + * @brief Be used for determining the size of flash_run_command() + * + * This function must be defined that lexically follows flash_run_command(), + * so we can determine the size of flash_run_command() at runtime and not worry + * about toolchain or code generation differences. + */ +void flash_run_command_end(void) +{ +} + +/*! + * @brief Copy flash_run_command() to RAM + * + * This function copys the memory between flash_run_command() and flash_run_command_end() + * into the buffer which is also means that copying flash_run_command() to RAM. + */ +static void copy_flash_run_command(uint8_t *flashRunCommand) +{ + /* Calculate the valid length of flash_run_command() memory. + * Set max size(64 bytes) as default function size, in case some compiler allocates + * flash_run_command_end ahead of flash_run_command. */ + uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; + uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U); + uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U); + if (flash_run_command_end_addr > flash_run_command_start_addr) + { + funcLength = flash_run_command_end_addr - flash_run_command_start_addr; + + assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); + + /* In case some compiler allocates other function in the middle of flash_run_command + * and flash_run_command_end. */ + if (funcLength > kFLASH_executeInRamFunctionMaxSize) + { + funcLength = kFLASH_executeInRamFunctionMaxSize; + } + } + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why -1 and +1 operation exist. */ + memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength); + callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Command Sequence + * + * This function is used to perform the command write sequence to the flash. + * + * @param driver Pointer to storage for the driver runtime state. + * @return An error code or kStatus_FLASH_Success + */ +static status_t flash_command_sequence(flash_config_t *config) +{ + uint8_t registerValue; + +#if FLASH_DRIVER_IS_FLASH_RESIDENT + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + + /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using + * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() + * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ + callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT)); +#else + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + /* clear CCIF bit */ + FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) + { + } +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + + /* Check error bits */ + /* Get flash status register value */ + registerValue = FTFx->FSTAT; + + /* checking access error */ + if (registerValue & FTFx_FSTAT_ACCERR_MASK) + { + return kStatus_FLASH_AccessError; + } + /* checking protection error */ + else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + /* checking MGSTAT0 non-correctable error */ + else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) + { + return kStatus_FLASH_CommandFailure; + } + else + { + return kStatus_FLASH_Success; + } +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Run flash cache clear command + * + * This function should be copied to RAM for execution to make sure that code works + * properly even flash cache is disabled. + * It is for flash-resident bootloader only, not technically required for ROM or + * flashloader (RAM-resident bootloader). + */ +void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) +{ +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS + *ftfx_reg |= MCM_PLACR_CFCC_MASK; +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + *ftfx_reg |= MSCM_OCMDR_OCMC1(2); + *ftfx_reg |= MSCM_OCMDR_OCMC1(1); +#else +/* #error "Unknown flash cache controller" */ +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +} + +/*! + * @brief Be used for determining the size of flash_cache_clear_command() + * + * This function must be defined that lexically follows flash_cache_clear_command(), + * so we can determine the size of flash_cache_clear_command() at runtime and not worry + * about toolchain or code generation differences. + */ +void flash_cache_clear_command_end(void) +{ +} + +/*! + * @brief Copy flash_cache_clear_command() to RAM + * + * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end() + * into the buffer which is also means that copying flash_cache_clear_command() to RAM. + */ +static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand) +{ + /* Calculate the valid length of flash_cache_clear_command() memory. + * Set max size(64 bytes) as default function size, in case some compiler allocates + * flash_cache_clear_command_end ahead of flash_cache_clear_command. */ + uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; + uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U); + uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U); + if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr) + { + funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr; + + assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); + + /* In case some compiler allocates other function in the middle of flash_cache_clear_command + * and flash_cache_clear_command_end. */ + if (funcLength > kFLASH_executeInRamFunctionMaxSize) + { + funcLength = kFLASH_executeInRamFunctionMaxSize; + } + } + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why -1 and +1 operation exist. */ + memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength); + callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Cache Clear + * + * This function is used to perform the cache clear to the flash. + */ +#if (defined(__GNUC__)) +/* #pragma GCC push_options */ +/* #pragma GCC optimize("O0") */ +void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) +#else +#if (defined(__ICCARM__)) +#pragma optimize = none +#endif +#if (defined(__CC_ARM)) +#pragma push +#pragma O0 +#endif +void flash_cache_clear(flash_config_t *config) +#endif +{ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return; + } + +/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using + * pre-processed MACROs or a global variable in flash_cache_clear_comamnd() + * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */ +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS +#if defined(MCM) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR); +#endif +#if defined(MCM0) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR); +#endif +#if defined(MCM1) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR); +#else + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]); +#else + /* #error "Unknown flash cache controller" */ + /* meaningless code, just a workaround to solve warning*/ + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0); +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + +#else + +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS +#if defined(MCM) + MCM->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#if defined(MCM0) + MCM0->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#if defined(MCM1) + MCM1->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2); + MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1); +#else +/* #error "Unknown flash cache controller" */ +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#if (defined(__CC_ARM)) +#pragma pop +#endif +#if (defined(__GNUC__)) +/* #pragma GCC pop_options */ +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Check whether flash execute-in-ram functions are ready */ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + if ((config->flashExecuteInRamFunctionInfo) && + (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_ExecuteInRamFunctionNotReady; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Verify the start and length are alignmentBaseline aligned. */ + if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + +/* check for valid range of the target addresses */ +#if !FLASH_SSD_IS_FLEXNVM_ENABLED + if ((startAddress < config->PFlashBlockBase) || + ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize))) +#else + if (!(((startAddress >= config->PFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) || + ((startAddress >= config->DFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))))) +#endif + { + return kStatus_FLASH_AddressError; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Clean up info Structure*/ + memset(info, 0, sizeof(flash_operation_config_t)); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) + { + info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; + info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; + } + else +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + { + info->convertedAddress = address; + info->activeSectorSize = config->PFlashSectorSize; + info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key) +{ + /* Validate the user key */ + if (key != kFLASH_apiEraseKey) + { + return kStatus_FLASH_EraseKeyError; + } + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) +{ + struct + { + uint32_t reserved0; + uint8_t FlexNVMPartitionCode; + uint8_t EEPROMDataSetSize; + uint16_t reserved1; + } dataIFRReadOut; + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get FlexNVM memory partition info from data flash IFR */ + returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, + sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_PartitionStatusUpdateFailure; + } + + /* Fill out partitioned EEPROM size */ + dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; + switch (dataIFRReadOut.EEPROMDataSetSize) + { + case 0x00U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; + break; + case 0x01U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; + break; + case 0x02U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; + break; + case 0x03U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; + break; + case 0x04U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; + break; + case 0x05U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; + break; + case 0x06U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; + break; + case 0x07U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; + break; + case 0x08U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; + break; + case 0x09U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; + break; + case 0x0AU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; + break; + case 0x0BU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; + break; + case 0x0CU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; + break; + case 0x0DU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; + break; + case 0x0EU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; + break; + case 0x0FU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; + break; + default: + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + break; + } + + /* Fill out partitioned DFlash size */ + dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; + switch (dataIFRReadOut.FlexNVMPartitionCode) + { + case 0x00U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ + break; + case 0x01U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ + break; + case 0x02U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ + break; + case 0x03U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ + break; + case 0x04U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ + break; + case 0x05U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ + break; + case 0x06U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ + break; + case 0x07U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ + break; + case 0x08U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ + break; + case 0x09U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ + break; + case 0x0AU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ + break; + case 0x0BU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ + break; + case 0x0CU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ + break; + case 0x0DU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ + break; + case 0x0EU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ + break; + case 0x0FU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ + break; + default: + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; + break; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option) +{ + status_t status; + uint32_t maxReadbleAddress; + + if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + + status = kStatus_FLASH_Success; + + maxReadbleAddress = start + lengthInBytes - 1; + if (option == kFLASH_resourceOptionVersionId) + { + if ((start != kFLASH_resourceRangeVersionIdStart) || + ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd)) + { + status = kStatus_FLASH_InvalidArgument; + } + } + else if (option == kFLASH_resourceOptionFlashIfr) + { + if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes) + { + } +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP + else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) && + (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd)) + { + } +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + else if ((start >= kFLASH_resourceRangeDflashIfrStart) && + (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd)) + { + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + + return status; +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option) +{ + if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) || + (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) || + (option == kFLASH_swapControlOptionDisableSystem)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_InvalidArgument; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) +{ + flash_swap_ifr_field_config_t flashSwapIfrField; + uint32_t swapIndicatorAddress; + + status_t returnCode; + returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField, + sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field, + * the low 4 bit value of Swap Indicator Address is always 4'b0000 */ + swapIndicatorAddress = + (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; + if (address != swapIndicatorAddress) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) +{ + if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) && + (option != kFLASH_flexramFunctionOptionAvailableForEeprom)) + { + return kStatus_FLASH_InvalidArgument; + } + + return kStatus_FLASH_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h new file mode 100755 index 00000000000..63463e03cb4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h @@ -0,0 +1,1177 @@ +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLASH_H_ +#define _FSL_FLASH_H_ + +#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) +#include +#include +#include "fsl_device_registers.h" +#include "bootloader_common.h" +#else +#include "fsl_common.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! + * @name Flash version + * @{ + */ +/*! @brief Construct the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief FLASH driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief FLASH driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_driverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_driverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_driverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_driverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Whether to support FlexNVM in flash driver */ +#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) +#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */ +#endif + +/*! @brief Whether the FlexNVM is enabled in flash driver */ +#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) + +/*! @brief Flash driver location. */ +#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) +#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) +#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */ +#else +#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */ +#endif +#endif + +/*! @brief Flash Driver Export option */ +#if !defined(FLASH_DRIVER_IS_EXPORTED) +#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) +#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */ +#else +#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */ +#endif +#endif +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASH) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Construct a status code value from a group and code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< Api is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< Api erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-ram function is not available.*/ + kStatus_FLASH_PartitionStatusUpdateFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ + kStatus_FLASH_SetFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/ + kStatus_FLASH_RecoverFlexramAsRamError = + MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as ram.*/ + kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as ram.*/ + kStatus_FLASH_RecoverFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/ + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash api is not supported.*/ + kStatus_FLASH_SwapSystemNotInUninitialized = + MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/ + kStatus_FLASH_SwapIndicatorAddressError = + MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Construct the four char code for flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_apiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for supported flash margin levels. + */ +typedef enum _flash_margin_value +{ + kFLASH_marginValueNormal, /*!< Use the 'normal' read level for 1s.*/ + kFLASH_marginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ + kFLASH_marginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ + kFLASH_marginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ +} flash_margin_value_t; + +/*! + * @brief Enumeration for the three possible flash security states. + */ +typedef enum _flash_security_state +{ + kFLASH_securityStateNotSecure, /*!< Flash is not secure.*/ + kFLASH_securityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ + kFLASH_securityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ +} flash_security_state_t; + +/*! + * @brief Enumeration for the three possible flash protection levels. + */ +typedef enum _flash_protection_state +{ + kFLASH_protectionStateUnprotected, /*!< Flash region is not protected.*/ + kFLASH_protectionStateProtected, /*!< Flash region is protected.*/ + kFLASH_protectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ +} flash_protection_state_t; + +/*! + * @brief Enumeration for the three possible flash execute access levels. + */ +typedef enum _flash_execute_only_access_state +{ + kFLASH_accessStateUnLimited, /*!< Flash region is unLimited.*/ + kFLASH_accessStateExecuteOnly, /*!< Flash region is execute only.*/ + kFLASH_accessStateMixed /*!< Flash is mixed with unLimited and execute only region.*/ +} flash_execute_only_access_state_t; + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_propertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_propertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_propertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_propertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_propertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + kFLASH_propertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ + kFLASH_propertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ + kFLASH_propertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ + kFLASH_propertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ + kFLASH_propertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ + kFLASH_propertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ + kFLASH_propertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ + kFLASH_propertyDflashBlockSize = 0x12U, /*!< Dflash block count property.*/ + kFLASH_propertyDflashBlockCount = 0x13U, /*!< Dflash block base address property.*/ + kFLASH_propertyDflashBlockBaseAddr = 0x14U, /*!< Eeprom total size property.*/ + kFLASH_propertyEepromTotalSize = 0x15U +} flash_property_tag_t; + +/*! + * @brief Constants for execute-in-ram flash function. + */ +enum _flash_execute_in_ram_function_constants +{ + kFLASH_executeInRamFunctionMaxSize = 64U, /*!< Max size of execute-in-ram function.*/ + kFLASH_executeInRamFunctionTotalNum = 2U /*!< Total number of execute-in-ram functions.*/ +}; + +/*! + * @brief Flash execute-in-ram function information. + */ +typedef struct _flash_execute_in_ram_function_config +{ + uint32_t activeFunctionCount; /*!< Number of available execute-in-ram functions.*/ + uint8_t *flashRunCommand; /*!< execute-in-ram function: flash_run_command.*/ + uint8_t *flashCacheClearCommand; /*!< execute-in-ram function: flash_cache_clear_command.*/ +} flash_execute_in_ram_function_config_t; + +/*! + * @brief Enumeration for the two possible options of flash read resource command. + */ +typedef enum _flash_read_resource_option +{ + kFLASH_resourceOptionFlashIfr = + 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ + kFLASH_resourceOptionVersionId = 0x01U /*!< Select code for Version ID*/ +} flash_read_resource_option_t; + +/*! + * @brief Enumeration for the range of special-purpose flash resource + */ +enum _flash_read_resource_range +{ +#if (FSL_FEATURE_FLASH_IS_FTFE == 1) + kFLASH_resourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ + kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_resourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ + kFLASH_resourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ + kFLASH_resourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ + kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_resourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ + kFLASH_resourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ +#endif + kFLASH_resourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ + kFLASH_resourceRangePflashSwapIfrEnd = 0x403FFU, /*!< Pflash swap IFR end address.*/ + kFLASH_resourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ + kFLASH_resourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ +}; + +/*! + * @brief Enumeration for the two possilbe options of set flexram function command. + */ +typedef enum _flash_flexram_function_option +{ + kFLASH_flexramFunctionOptionAvailableAsRam = 0xFFU, /*!< Option used to make FlexRAM available as RAM */ + kFLASH_flexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */ +} flash_flexram_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap function + */ +typedef enum _flash_swap_function_option +{ + kFLASH_swapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */ + kFLASH_swapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */ +} flash_swap_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap Control commands + */ +typedef enum _flash_swap_control_option +{ + kFLASH_swapControlOptionIntializeSystem = 0x01U, /*!< Option used to Intialize Swap System */ + kFLASH_swapControlOptionSetInUpdateState = 0x02U, /*!< Option used to Set Swap in Update State */ + kFLASH_swapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */ + kFLASH_swapControlOptionReportStatus = 0x08U, /*!< Option used to Report Swap Status */ + kFLASH_swapControlOptionDisableSystem = 0x10U /*!< Option used to Disable Swap Status */ +} flash_swap_control_option_t; + +/*! + * @brief Enumeration for the possible flash swap status. + */ +typedef enum _flash_swap_state +{ + kFLASH_swapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/ + kFLASH_swapStateReady = 0x01U, /*!< Flash swap system is in ready state.*/ + kFLASH_swapStateUpdate = 0x02U, /*!< Flash swap system is in update state.*/ + kFLASH_swapStateUpdateErased = 0x03U, /*!< Flash swap system is in updateErased state.*/ + kFLASH_swapStateComplete = 0x04U, /*!< Flash swap system is in complete state.*/ + kFLASH_swapStateDisabled = 0x05U /*!< Flash swap system is in disabled state.*/ +} flash_swap_state_t; + +/*! + * @breif Enumeration for the possible flash swap block status + */ +typedef enum _flash_swap_block_status +{ + kFLASH_swapBlockStatusLowerHalfProgramBlocksAtZero = + 0x00U, /*!< Swap block status is that lower half program block at zero.*/ + kFLASH_swapBlockStatusUpperHalfProgramBlocksAtZero = + 0x01U, /*!< Swap block status is that upper half program block at zero.*/ +} flash_swap_block_status_t; + +/*! + * @brief Flash Swap information. + */ +typedef struct _flash_swap_state_config +{ + flash_swap_state_t flashSwapState; /*!< Current swap system status.*/ + flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/ + flash_swap_block_status_t nextSwapBlockStatus; /*!< Next swap block status.*/ +} flash_swap_state_config_t; + +/*! + * @brief Flash Swap IFR fileds. + */ +typedef struct _flash_swap_ifr_field_config +{ + uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/ + uint16_t swapEnableWord; /*!< Swap enable word field.*/ + uint8_t reserved0[6]; /*!< Reserved field.*/ + uint16_t swapDisableWord; /*!< Swap disable word field.*/ + uint8_t reserved1[4]; /*!< Reserved field.*/ +} flash_swap_ifr_field_config_t; + +/*! + * @brief Enumeration for FlexRAM load during reset option. + */ +typedef enum _flash_partition_flexram_load_option +{ + kFLASH_partitionFlexramLoadOptionLoadedWithValidEepromData = + 0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/ + kFLASH_partitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/ +} flash_partition_flexram_load_option_t; + +/*! @brief callback type used for pflash block*/ +typedef void (*flash_callback_t)(void); + +/*! + * @brief Active flash information for current operation. + */ +typedef struct _flash_operation_config +{ + uint32_t convertedAddress; /*!< Converted address for current flash type.*/ + uint32_t activeSectorSize; /*!< Sector size of current flash type.*/ + uint32_t activeBlockSize; /*!< Block size of current flash type.*/ + uint32_t blockWriteUnitSize; /*!< write unit size.*/ + uint32_t sectorCmdAddressAligment; /*!< Erase sector command address alignment.*/ + uint32_t sectionCmdAddressAligment; /*!< Program/Verify section command address alignment.*/ + uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/ + uint32_t checkCmdAddressAligment; /*!< Program check command address alignment.*/ +} flash_operation_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< Base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< Size of all combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< Number of PFlash blocks. */ + uint32_t PFlashSectorSize; /*!< Size in bytes of a sector of PFlash. */ + flash_callback_t PFlashCallback; /*!< Callback function for flash API. */ + uint32_t PFlashAccessSegmentSize; /*!< Size in bytes of a access segment of PFlash. */ + uint32_t PFlashAccessSegmentCount; /*!< Number of PFlash access segments. */ + uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-ram function. */ + uint32_t FlexRAMBlockBase; /*!< For FlexNVM device, this is the base address of FlexRAM + For non-FlexNVM device, this is the base address of acceleration RAM memory */ + uint32_t FlexRAMTotalSize; /*!< For FlexNVM device, this is the size of FlexRAM + For non-FlexNVM device, this is the size of acceleration RAM memory */ + uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory); + For non-FlexNVM device, this field is unused */ + uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory; + For non-FlexNVM device, this field is unused */ + uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned + from FlexRAM; + For non-FlexNVM device, this field is unused */ +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes global flash properties structure members + * + * This function checks and initializes Flash module for the other Flash APIs. + * + * @param config Pointer to storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! + * @brief Set the desired flash callback function + * + * @param config Pointer to storage for the driver runtime state. + * @param callback callback function to be stored in driver + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback); + +/*! + * @brief Prepare flash execute-in-ram functions + * + * @param config Pointer to storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config); +#endif + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases entire flash + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status + */ +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key); + +/*! + * @brief Erases flash sectors encompassed by parameters passed into function + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address does not need to be sector aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be word aligned. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! + * @brief Erases entire flash, including protected sectors. + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status + */ +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key); +#endif + +/*! + * @brief Erases all program flash execute-only segments defined by the FXACC registers. + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters + * + * This function programs the flash memory with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); + +/*! + * @brief Programs Program Once Field through parameters + * + * This function programs the Program Once Field with desired data for a given + * flash area as determined by the index and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param index The index indicating which area of Program Once Field to be programmed. + * @param src Pointer to the source buffer of data that is to be programmed + * into the Program Once Field. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes); + +/*! + * @brief Programs flash with data at locations passed in through parameters via Program Section command + * + * This function programs the flash memory with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as ram + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); +#endif + +/*! + * @brief Programs EEPROM with data at locations passed in through parameters + * + * This function programs the Emulated EEPROM with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as ram + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); +#endif + +/*@}*/ + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Read resource with data at locations passed in through parameters + * + * This function reads the flash memory with desired location for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param dst Pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be read. Must be word-aligned. + * @param option The resource option which indicates which area should be read back. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option); +#endif + +/*! + * @brief Read Program Once Field through parameters + * + * This function reads the read once feild with given index and length + * + * @param config Pointer to storage for the driver runtime state. + * @param index The index indicating the area of program once field to be read. + * @param dst Pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Security + * @{ + */ + +/*! + * @brief Returns the security state via the pointer passed into the function + * + * This function retrieves the current Flash security status, including the + * security enabling state and the backdoor key enabling state. + * + * @param config Pointer to storage for the driver runtime state. + * @param state Pointer to the value returned for the current security status code: + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state); + +/*! + * @brief Allows user to bypass security with a backdoor key + * + * If the MCU is in secured state, this function will unsecure the MCU by + * comparing the provided backdoor key with ones in the Flash Configuration + * Field. + * + * @param config Pointer to storage for the driver runtime state. + * @param backdoorKey Pointer to the user buffer containing the backdoor key. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies erasure of entire flash at specified margin level + * + * This function will check to see if the flash have been erased to the + * specified read margin level. + * + * @param config Pointer to storage for the driver runtime state. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin); + +/*! + * @brief Verifies erasure of desired flash area at specified margin level + * + * This function will check the appropriate number of flash sectors based on + * the desired start address and length to see if the flash have been erased + * to the specified read margin level. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be verified. Must be word-aligned. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin); + +/*! + * @brief Verifies programming of desired flash area at specified margin level + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it with expected data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be verified. Must be word-aligned. + * @param expectedData Pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice + * @param failedAddress Pointer to returned failing address. + * @param failedData Pointer to returned failing data. Some derivitives do + * not included failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData); + +/*! + * @brief Verifies if the program flash executeonly segments have been erased to + * the specified read margin level + * + * @param config Pointer to storage for the driver runtime state. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin); + +/*@}*/ + +/*! + * @name Protection + * @{ + */ + +/*! + * @brief Returns the protection state of desired flash area via the pointer passed into the function + * + * This function retrieves the current Flash protect status for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param protection_state Pointer to the value returned for the current + * protection status code for the desired flash area. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + */ +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state); + +/*! + * @brief Returns the access state of desired flash area via the pointer passed into the function + * + * This function retrieves the current Flash access status for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param access_state Pointer to the value returned for the current + * access status code for the desired flash area. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + */ +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config Pointer to storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value Pointer to the value returned for the desired flash property + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty unknown property tag + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +/*! + * @name FlexRAM + * @{ + */ + +/*! + * @brief Set FlexRAM Function command + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set work mode of FlexRAM + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option); +#endif + +/*@}*/ + +/*! + * @name Swap + * @{ + */ + +/*! + * @brief Configure Swap function or Check the swap state of Flash Module + * + * @param config Pointer to storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param option The possible option used to configure Flash Swap function or check the flash swap status + * @param returnInfo Pointer to the data which is used to return the information of flash swap. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo); +#endif + +/*! + * @brief Swap the lower half flash with the higher half flaock + * + * @param config Pointer to storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param option The possible option used to configure Flash Swap function or check the flash swap status + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state + */ +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option); +#endif + +/*! + * @name FlexNVM + * @{ + */ + +/*! + * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the + * FlexRAM. + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set FlexRAM load behavior during reset. + * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems. + * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup + * memory supporting EEPROM functions. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode); +#endif + +/*@}*/ + +/*! +* @name Flash Protection Utilities +* @{ +*/ + +/*! + * @brief Set PFLASH Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is + * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest + * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus); + +/*! + * @brief Get PFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the + * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant + * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus); + +/*! + * @brief Set DFLASH Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is + * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest + * address area of DFlash. The most significant bit is corresponding to the highest address area of DFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus); +#endif + +/*! + * @brief Get DFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of + * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most + * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as + * below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus); +#endif + +/*! + * @brief Set EEPROM Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is + * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest + * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on. + * There are two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus); +#endif + +/*! + * @brief Get DFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of + * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most + * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus); +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLASH_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c new file mode 100755 index 00000000000..009a730fdf6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexbus.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base FLEXBUS peripheral base address + * + * @return The FLEXBUS instance + */ +static uint32_t FLEXBUS_GetInstance(FB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to FLEXBUS bases for each instance. */ +static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS; + +/*! @brief Pointers to FLEXBUS clocks for each instance. */ +static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FLEXBUS_GetInstance(FB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FB_COUNT; instance++) + { + if (s_flexbusBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FB_COUNT); + + return instance; +} + +void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) +{ + assert(config != NULL); + assert(config->chip < FB_CSAR_COUNT); + assert(config->waitStates <= 0x3FU); + + uint32_t chip = 0; + uint32_t reg_value = 0; + + /* Ungate clock for FLEXBUS */ + CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); + + /* Reset all the register to default state */ + for (chip = 0; chip < FB_CSAR_COUNT; chip++) + { + /* Reset CSMR register, all chips not valid (disabled) */ + base->CS[chip].CSMR = 0x0000U; + /* Set default base address */ + base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); + /* Reset FB_CSCRx register */ + base->CS[chip].CSCR = 0x0000U; + } + /* Set FB_CSPMCR register */ + /* FlexBus signal group 1 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT; + /* FlexBus signal group 2 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT; + /* FlexBus signal group 3 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT; + /* FlexBus signal group 4 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT; + /* FlexBus signal group 5 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT; + /* Write to CSPMCR register */ + base->CSPMCR = reg_value; + + /* Update chip value */ + chip = config->chip; + + /* Base address */ + reg_value = config->chipBaseAddress; + /* Write to CSAR register */ + base->CS[chip].CSAR = reg_value; + /* Chip-select validation */ + reg_value = 0x1U << FB_CSMR_V_SHIFT; + /* Write protect */ + reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT; + /* Base address mask */ + reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT; + /* Write to CSMR register */ + base->CS[chip].CSMR = reg_value; + /* Burst write */ + reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT; + /* Burst read */ + reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT; + /* Byte-enable mode */ + reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT; + /* Port size */ + reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT; + /* The internal transfer acknowledge for accesses */ + reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT; + /* Byte-Lane shift */ + reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT; + /* The number of wait states */ + reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT; + /* Write address hold or deselect */ + reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT; + /* Read address hold or deselect */ + reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT; + /* Address setup */ + reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT; + /* Extended transfer start/extended address latch */ + reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT; + /* Secondary wait state */ + reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT; + /* Write to CSCR register */ + base->CS[chip].CSCR = reg_value; + /* FlexBus signal group 1 multiplex control */ + reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT; + /* FlexBus signal group 2 multiplex control */ + reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT; + /* FlexBus signal group 3 multiplex control */ + reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT; + /* FlexBus signal group 4 multiplex control */ + reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT; + /* FlexBus signal group 5 multiplex control */ + reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT; + /* Write to CSPMCR register */ + base->CSPMCR = reg_value; +} + +void FLEXBUS_Deinit(FB_Type *base) +{ + /* Gate clock for FLEXBUS */ + CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); +} + +void FLEXBUS_GetDefaultConfig(flexbus_config_t *config) +{ + config->chip = 0; /* Chip 0 FlexBus for validation */ + config->writeProtect = 0; /* Write accesses are allowed */ + config->burstWrite = 0; /* Burst-Write disable */ + config->burstRead = 0; /* Burst-Read disable */ + config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */ + config->autoAcknowledge = true; /* Auto-Acknowledge enable */ + config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */ + config->secondaryWaitStates = 0; /* Secondary wait state disable */ + config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */ + config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */ + config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */ + config->addressSetup = + kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */ + config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */ + config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */ + config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */ + config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */ + config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */ + config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */ +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h new file mode 100755 index 00000000000..23cde14a569 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXBUS_H_ +#define _FSL_FLEXBUS_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexbus + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! + * @brief Defines port size for FlexBus peripheral. + */ +typedef enum _flexbus_port_size +{ + kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */ + kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */ + kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */ +} flexbus_port_size_t; + +/*! + * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. + */ +typedef enum _flexbus_write_address_hold +{ + kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */ +} flexbus_write_address_hold_t; + +/*! + * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. + */ +typedef enum _flexbus_read_address_hold +{ + kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */ + kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */ + kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */ + kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */ +} flexbus_read_address_hold_t; + +/*! + * @brief Address setup for FlexBus peripheral. + */ +typedef enum _flexbus_address_setup +{ + kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */ + kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */ + kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */ + kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */ +} flexbus_address_setup_t; + +/*! + * @brief Defines byte-lane shift for FlexBus peripheral. + */ +typedef enum _flexbus_bytelane_shift +{ + kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */ + kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */ +} flexbus_bytelane_shift_t; + +/*! + * @brief Defines multiplex group1 valid signals. + */ +typedef enum _flexbus_multiplex_group1_signal +{ + kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */ + kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */ + kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */ +} flexbus_multiplex_group1_t; + +/*! + * @brief Defines multiplex group2 valid signals. + */ +typedef enum _flexbus_multiplex_group2_signal +{ + kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */ + kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */ + kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */ +} flexbus_multiplex_group2_t; + +/*! + * @brief Defines multiplex group3 valid signals. + */ +typedef enum _flexbus_multiplex_group3_signal +{ + kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */ + kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */ + kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */ +} flexbus_multiplex_group3_t; + +/*! + * @brief Defines multiplex group4 valid signals. + */ +typedef enum _flexbus_multiplex_group4_signal +{ + kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */ + kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */ + kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */ +} flexbus_multiplex_group4_t; + +/*! + * @brief Defines multiplex group5 valid signals. + */ +typedef enum _flexbus_multiplex_group5_signal +{ + kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */ + kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */ + kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */ +} flexbus_multiplex_group5_t; + +/*! + * @brief Configuration structure that the user needs to set. + */ +typedef struct _flexbus_config +{ + uint8_t chip; /*!< Chip FlexBus for validation */ + uint8_t waitStates; /*!< Value of wait states */ + uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */ + uint32_t chipBaseAddressMask; /*!< Chip base address mask */ + bool writeProtect; /*!< Write protected */ + bool burstWrite; /*!< Burst-Write enable */ + bool burstRead; /*!< Burst-Read enable */ + bool byteEnableMode; /*!< Byte-enable mode support */ + bool autoAcknowledge; /*!< Auto acknowledge setting */ + bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */ + bool secondaryWaitStates; /*!< Secondary wait states number */ + flexbus_port_size_t portSize; /*!< Port size of transfer */ + flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */ + flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */ + flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option */ + flexbus_address_setup_t addressSetup; /*!< Address setup setting */ + flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control */ + flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control */ + flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control */ + flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control */ + flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control */ +} flexbus_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name FlexBus functional operation + * @{ + */ + +/*! + * @brief Initializes and configures the FlexBus module. + * + * This function enables the clock gate for FlexBus module. + * Only chip 0 is validated and set to known values. Other chips are disabled. + * NOTE: In this function, certain parameters, depending on external memories, must + * be set before using FLEXBUS_Init() function. + * This example shows how to set up the uart_state_t and the + * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing + * in these parameters: + @code + flexbus_config_t flexbusConfig; + FLEXBUS_GetDefaultConfig(&flexbusConfig); + flexbusConfig.waitStates = 2U; + flexbusConfig.chipBaseAddress = 0x60000000U; + flexbusConfig.chipBaseAddressMask = 7U; + FLEXBUS_Init(FB, &flexbusConfig); + @endcode + * + * @param base FlexBus peripheral address. + * @param config Pointer to the configure structure +*/ +void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config); + +/*! + * @brief De-initializes a FlexBus instance. + * + * This function disables the clock gate of the FlexBus module clock. + * + * @param base FlexBus peripheral address. + */ +void FLEXBUS_Deinit(FB_Type *base); + +/*! + * @brief Initializes the FlexBus configuration structure. + * + * This function initializes the FlexBus configuration structure to default value. The default + * values are: + @code + fbConfig->chip = 0; + fbConfig->writeProtect = 0; + fbConfig->burstWrite = 0; + fbConfig->burstRead = 0; + fbConfig->byteEnableMode = 0; + fbConfig->autoAcknowledge = true; + fbConfig->extendTransferAddress = 0; + fbConfig->secondaryWaitStates = 0; + fbConfig->byteLaneShift = kFLEXBUS_NotShifted; + fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle; + fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles; + fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge; + fbConfig->portSize = kFLEXBUS_1Byte; + fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; + fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ; + fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; + fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; + fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; + @endcode + * @param config Pointer to the initialization structure. + * @see FLEXBUS_Init + */ +void FLEXBUS_GetDefaultConfig(flexbus_config_t *config); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_FLEXBUS_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c new file mode 100755 index 00000000000..a9056097574 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c @@ -0,0 +1,876 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ftm.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base FTM peripheral base address + * + * @return The FTM instance + */ +static uint32_t FTM_GetInstance(FTM_Type *base); + +/*! + * @brief Sets the FTM register PWM synchronization method + * + * This function will set the necessary bits for the PWM synchronization mode that + * user wishes to use. + * + * @param base FTM peripheral base address + * @param syncMethod Syncronization methods to use to update buffered registers. This is a logical + * OR of members of the enumeration ::ftm_pwm_sync_method_t + */ +static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod); + +/*! + * @brief Sets the reload points used as loading points for register update + * + * This function will set the necessary bits based on what the user wishes to use as loading + * points for FTM register update. When using this it is not required to use PWM synchnronization. + * + * @param base FTM peripheral base address + * @param reloadPoints FTM reload points. This is a logical OR of members of the + * enumeration ::ftm_reload_point_t + */ +static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to FTM bases for each instance. */ +static FTM_Type *const s_ftmBases[] = FTM_BASE_PTRS; + +/*! @brief Pointers to FTM clocks for each instance. */ +static const clock_ip_name_t s_ftmClocks[] = FTM_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FTM_GetInstance(FTM_Type *base) +{ + uint32_t instance; + uint32_t ftmArrayCount = (sizeof(s_ftmBases) / sizeof(s_ftmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ftmArrayCount; instance++) + { + if (s_ftmBases[instance] == base) + { + break; + } + } + + assert(instance < ftmArrayCount); + + return instance; +} + +static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod) +{ + uint8_t chnlNumber = 0; + uint32_t reg = 0, syncReg = 0; + + syncReg = base->SYNC; + /* Enable PWM synchronization of output mask register */ + syncReg |= FTM_SYNC_SYNCHOM_MASK; + + reg = base->COMBINE; + for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) + { + /* Enable PWM synchronization of registers C(n)V and C(n+1)V */ + reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); + } + base->COMBINE = reg; + + reg = base->SYNCONF; + + /* Use enhanced PWM synchronization method. Use PWM sync to update register values */ + reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_SWOC_MASK); + + if (syncMethod & FTM_SYNC_SWSYNC_MASK) + { + /* Enable needed bits for software trigger to update registers with its buffer value */ + reg |= (FTM_SYNCONF_SWRSTCNT_MASK | FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK | + FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_SWOM_MASK); + } + + if (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) + { + /* Enable needed bits for hardware trigger to update registers with its buffer value */ + reg |= (FTM_SYNCONF_HWRSTCNT_MASK | FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK | + FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_HWOM_MASK); + + /* Enable the appropriate hardware trigger that is used for PWM sync */ + if (syncMethod & FTM_SYNC_TRIG0_MASK) + { + syncReg |= FTM_SYNC_TRIG0_MASK; + } + if (syncMethod & FTM_SYNC_TRIG1_MASK) + { + syncReg |= FTM_SYNC_TRIG1_MASK; + } + if (syncMethod & FTM_SYNC_TRIG2_MASK) + { + syncReg |= FTM_SYNC_TRIG2_MASK; + } + } + + /* Write back values to the SYNC register */ + base->SYNC = syncReg; + + /* Write the PWM synch values to the SYNCONF register */ + base->SYNCONF = reg; +} + +static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints) +{ + uint32_t chnlNumber = 0; + uint32_t reg = 0; + + /* Need CNTINC bit to be 1 for CNTIN register to update with its buffer value on reload */ + base->SYNCONF |= FTM_SYNCONF_CNTINC_MASK; + + reg = base->COMBINE; + for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) + { + /* Need SYNCEN bit to be 1 for CnV reg to update with its buffer value on reload */ + reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); + } + base->COMBINE = reg; + + /* Set the reload points */ + reg = base->PWMLOAD; + + /* Enable the selected channel match reload points */ + reg &= ~((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1); + reg |= (reloadPoints & ((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1)); + +#if defined(FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) && (FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) + /* Enable half cycle match as a reload point */ + if (reloadPoints & kFTM_HalfCycMatch) + { + reg |= FTM_PWMLOAD_HCSEL_MASK; + } + else + { + reg &= ~FTM_PWMLOAD_HCSEL_MASK; + } +#endif /* FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD */ + + base->PWMLOAD = reg; + + /* These reload points are used when counter is in up-down counting mode */ + reg = base->SYNC; + if (reloadPoints & kFTM_CntMax) + { + /* Reload when counter turns from up to down */ + reg |= FTM_SYNC_CNTMAX_MASK; + } + else + { + reg &= ~FTM_SYNC_CNTMAX_MASK; + } + + if (reloadPoints & kFTM_CntMin) + { + /* Reload when counter turns from down to up */ + reg |= FTM_SYNC_CNTMIN_MASK; + } + else + { + reg &= ~FTM_SYNC_CNTMIN_MASK; + } + base->SYNC = reg; +} + +status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) +{ + assert(config); + + uint32_t reg; + + if (!(config->pwmSyncMode & + (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_SWSYNC_MASK))) + { + /* Invalid PWM sync mode */ + return kStatus_Fail; + } + + /* Ungate the FTM clock*/ + CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]); + + /* Configure the fault mode, enable FTM mode and disable write protection */ + base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK; + + /* Configure the update mechanism for buffered registers */ + FTM_SetPwmSync(base, config->pwmSyncMode); + + if (config->reloadPoints) + { + /* Setup intermediate register reload points */ + FTM_SetReloadPoints(base, config->reloadPoints); + } + + /* Set the clock prescale factor */ + base->SC = FTM_SC_PS(config->prescale); + + /* Setup the counter operation */ + base->CONF = (FTM_CONF_BDMMODE(config->bdmMode) | FTM_CONF_GTBEEN(config->useGlobalTimeBase)); + + /* Initial state of channel output */ + base->OUTINIT = config->chnlInitState; + + /* Channel polarity */ + base->POL = config->chnlPolarity; + + /* Set the external trigger sources */ + base->EXTTRIG = config->extTriggers; +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) + if (config->extTriggers & kFTM_ReloadInitTrigger) + { + base->CONF |= FTM_CONF_ITRIGR_MASK; + } + else + { + base->CONF &= ~FTM_CONF_ITRIGR_MASK; + } +#endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */ + + /* FTM deadtime insertion control */ + base->DEADTIME = (FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue)); + + /* FTM fault filter value */ + reg = base->FLTCTRL; + reg &= ~FTM_FLTCTRL_FFVAL_MASK; + reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue); + base->FLTCTRL = reg; + + return kStatus_Success; +} + +void FTM_Deinit(FTM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(FTM_SC_CLKS_MASK); + + /* Gate the FTM clock */ + CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]); +} + +void FTM_GetDefaultConfig(ftm_config_t *config) +{ + assert(config); + + /* Divide FTM clock by 1 */ + config->prescale = kFTM_Prescale_Divide_1; + /* FTM behavior in BDM mode */ + config->bdmMode = kFTM_BdmMode_0; + /* Software trigger will be used to update registers */ + config->pwmSyncMode = kFTM_SoftwareTrigger; + /* No intermediate register load */ + config->reloadPoints = 0; + /* Fault control disabled for all channels */ + config->faultMode = kFTM_Fault_Disable; + /* Disable the fault filter */ + config->faultFilterValue = 0; + /* Divide the system clock by 1 */ + config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + /* No counts are inserted */ + config->deadTimeValue = 0; + /* No external trigger */ + config->extTriggers = 0; + /* Initialization value is 0 for all channels */ + config->chnlInitState = 0; + /* Active high polarity for all channels */ + config->chnlPolarity = 0; + /* Use internal FTM counter as timebase */ + config->useGlobalTimeBase = false; +} + +status_t FTM_SetupPwm(FTM_Type *base, + const ftm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + + uint32_t mod, reg; + uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK))); + uint16_t cnv, cnvFirstEdge; + uint8_t i; + + switch (mode) + { + case kFTM_EdgeAlignedPwm: + case kFTM_CombinedPwm: + base->SC &= ~FTM_SC_CPWMS_MASK; + mod = (ftmClock / pwmFreq_Hz) - 1; + break; + case kFTM_CenterAlignedPwm: + base->SC |= FTM_SC_CPWMS_MASK; + mod = ftmClock / (pwmFreq_Hz * 2); + break; + default: + return kStatus_Fail; + } + + /* Return an error in case we overflow the registers, probably would require changing + * clock source to get the desired frequency */ + if (mod > 65535U) + { + return kStatus_Fail; + } + /* Set the PWM period */ + base->MOD = mod; + + /* Setup each FTM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Return error if requested dutycycle is greater than the max allowed */ + if (chnlParams->dutyCyclePercent > 100) + { + return kStatus_Fail; + } + + if ((mode == kFTM_EdgeAlignedPwm) || (mode == kFTM_CenterAlignedPwm)) + { + /* Clear the current mode and edge level bits */ + reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level */ + reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level)); + + /* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */ + reg |= FTM_CnSC_MSB(1U); + + /* Update the mode and edge level */ + base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; + + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlParams->chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return kStatus_Fail; + } + + /* Return error if requested value is greater than the max allowed */ + if (chnlParams->firstEdgeDelayPercent > 100) + { + return kStatus_Fail; + } + + /* Configure delay of the first edge */ + if (chnlParams->firstEdgeDelayPercent == 0) + { + /* No delay for the first edge */ + cnvFirstEdge = 0; + } + else + { + cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; + } + + /* Configure dutycycle */ + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + cnvFirstEdge = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + /* Clear the current mode and edge level bits for channel n */ + reg = base->CONTROLS[chnlParams->chnlNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n */ + reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level)); + + /* Update the mode and edge level for channel n */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg; + + /* Clear the current mode and edge level bits for channel n + 1 */ + reg = base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n + 1 */ + reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level)); + + /* Update the mode and edge level for channel n + 1*/ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg; + + /* Set the channel pair values */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + + /* Set the combine bit for the channel pair */ + base->COMBINE |= + (1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber))); + } + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true); +#endif + + chnlParams++; + } + + return kStatus_Success; +} + +void FTM_UpdatePwmDutycycle(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent) +{ + uint16_t cnv, cnvFirstEdge = 0, mod; + + mod = base->MOD; + if ((currentPwmMode == kFTM_EdgeAlignedPwm) || (currentPwmMode == kFTM_CenterAlignedPwm)) + { + cnv = (mod * dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[chnlNumber].CnV = cnv; + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return; + } + + cnv = (mod * dutyCyclePercent) / 100; + cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + } +} + +void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level) +{ + uint32_t reg = base->CONTROLS[chnlNumber].CnSC; + + /* Clear the field and write the new level value */ + reg &= ~(FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)level << FTM_CnSC_ELSA_SHIFT) & (FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + base->CONTROLS[chnlNumber].CnSC = reg; +} + +void FTM_SetupInputCapture(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_input_capture_edge_t captureMode, + uint32_t filterValue) +{ + uint32_t reg; + + reg = base->CONTROLS[chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= captureMode; + + /* Set the requested input capture mode */ + base->CONTROLS[chnlNumber].CnSC = reg; + /* Input filter available only for channels 0, 1, 2, 3 */ + if (chnlNumber < kFTM_Chnl_4) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); + reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); + base->FILTER = reg; + } +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to input mode */ + FTM_SetPwmOutputEnable(base, chnlNumber, false); +#endif +} + +void FTM_SetupOutputCompare(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_output_compare_mode_t compareMode, + uint32_t compareValue) +{ + uint32_t reg; + + /* Set output on match to the requested level */ + base->CONTROLS[chnlNumber].CnV = compareValue; + + reg = base->CONTROLS[chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= compareMode; + /* Setup the channel output behaviour when a match occurs with the compare value */ + base->CONTROLS[chnlNumber].CnSC = reg; + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlNumber, true); +#endif +} + +void FTM_SetupDualEdgeCapture(FTM_Type *base, + ftm_chnl_t chnlPairNumber, + const ftm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue) +{ + assert(edgeParam); + + uint32_t reg; + + reg = base->COMBINE; + /* Clear the combine bit for the channel pair */ + reg &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + /* Enable the DECAPEN bit */ + reg |= (1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + reg |= (1U << (FTM_COMBINE_DECAP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + base->COMBINE = reg; + + /* Setup the edge detection from channel n and n + 1 */ + reg = base->CONTROLS[chnlPairNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->currChanEdgeMode); + base->CONTROLS[chnlPairNumber * 2].CnSC = reg; + + reg = base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->nextChanEdgeMode); + base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC = reg; + + /* Input filter available only for channels 0, 1, 2, 3 */ + if (chnlPairNumber < kFTM_Chnl_4) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + base->FILTER = reg; + } + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to input mode */ + FTM_SetPwmOutputEnable(base, chnlPairNumber, false); +#endif +} + +void FTM_SetupQuadDecode(FTM_Type *base, + const ftm_phase_params_t *phaseAParams, + const ftm_phase_params_t *phaseBParams, + ftm_quad_decode_mode_t quadMode) +{ + assert(phaseAParams); + assert(phaseBParams); + + uint32_t reg; + + /* Set Phase A filter value if phase filter is enabled */ + if (phaseAParams->enablePhaseFilter) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK); + reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); + base->FILTER = reg; + } + + /* Set Phase B filter value if phase filter is enabled */ + if (phaseBParams->enablePhaseFilter) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH1FVAL_MASK); + reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); + base->FILTER = reg; + } + + /* Set Quadrature decode properties */ + reg = base->QDCTRL; + reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK | + FTM_QDCTRL_PHBPOL_MASK); + reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) | + FTM_QDCTRL_PHBFLTREN(phaseBParams->enablePhaseFilter) | FTM_QDCTRL_PHAPOL(phaseAParams->phasePolarity) | + FTM_QDCTRL_PHBPOL(phaseBParams->phasePolarity)); + base->QDCTRL = reg; + /* Enable Quad decode */ + base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK; +} + +void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams) +{ + uint32_t reg; + + reg = base->FLTCTRL; + if (faultParams->enableFaultInput) + { + /* Enable the fault input */ + reg |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + else + { + /* Disable the fault input */ + reg &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + + if (faultParams->useFaultFilter) + { + /* Enable the fault filter */ + reg |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + } + else + { + /* Disable the fault filter */ + reg &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + } + base->FLTCTRL = reg; + + if (faultParams->faultLevel) + { + /* Active low polarity for the fault input pin */ + base->FLTPOL |= (1U << faultNumber); + } + else + { + /* Active high polarity for the fault input pin */ + base->FLTPOL &= ~(1U << faultNumber); + } +} + +void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask) +{ + uint32_t chnlInts = (mask & 0xFFU); + uint8_t chnlNumber = 0; + + /* Enable the timer overflow interrupt */ + if (mask & kFTM_TimeOverflowInterruptEnable) + { + base->SC |= FTM_SC_TOIE_MASK; + } + + /* Enable the fault interrupt */ + if (mask & kFTM_FaultInterruptEnable) + { + base->MODE |= FTM_MODE_FAULTIE_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Enable the reload interrupt available only on certain SoC's */ + if (mask & kFTM_ReloadInterruptEnable) + { + base->SC |= FTM_SC_RIE_MASK; + } +#endif + + /* Enable the channel interrupts */ + while (chnlInts) + { + if (chnlInts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInts = chnlInts >> 1U; + } +} + +void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask) +{ + uint32_t chnlInts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Disable the timer overflow interrupt */ + if (mask & kFTM_TimeOverflowInterruptEnable) + { + base->SC &= ~FTM_SC_TOIE_MASK; + } + /* Disable the fault interrupt */ + if (mask & kFTM_FaultInterruptEnable) + { + base->MODE &= ~FTM_MODE_FAULTIE_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Disable the reload interrupt available only on certain SoC's */ + if (mask & kFTM_ReloadInterruptEnable) + { + base->SC &= ~FTM_SC_RIE_MASK; + } +#endif + + /* Disable the channel interrupts */ + while (chnlInts) + { + if (chnlInts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInts = chnlInts >> 1U; + } +} + +uint32_t FTM_GetEnabledInterrupts(FTM_Type *base) +{ + uint32_t enabledInterrupts = 0; + int8_t chnlCount = FSL_FEATURE_FTM_CHANNEL_COUNTn(base); + + /* The CHANNEL_COUNT macro returns -1 if it cannot match the FTM instance */ + assert(chnlCount != -1); + + /* Check if timer overflow interrupt is enabled */ + if (base->SC & FTM_SC_TOIE_MASK) + { + enabledInterrupts |= kFTM_TimeOverflowInterruptEnable; + } + /* Check if fault interrupt is enabled */ + if (base->MODE & FTM_MODE_FAULTIE_MASK) + { + enabledInterrupts |= kFTM_FaultInterruptEnable; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check if the reload interrupt is enabled */ + if (base->SC & FTM_SC_RIE_MASK) + { + enabledInterrupts |= kFTM_ReloadInterruptEnable; + } +#endif + + /* Check if the channel interrupts are enabled */ + while (chnlCount > 0) + { + chnlCount--; + if (base->CONTROLS[chnlCount].CnSC & FTM_CnSC_CHIE_MASK) + { + enabledInterrupts |= (1U << chnlCount); + } + } + + return enabledInterrupts; +} + +uint32_t FTM_GetStatusFlags(FTM_Type *base) +{ + uint32_t statusFlags = 0; + + /* Check the timer flag */ + if (base->SC & FTM_SC_TOF_MASK) + { + statusFlags |= kFTM_TimeOverflowFlag; + } + /* Check fault flag */ + if (base->FMS & FTM_FMS_FAULTF_MASK) + { + statusFlags |= kFTM_FaultFlag; + } + /* Check channel trigger flag */ + if (base->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) + { + statusFlags |= kFTM_ChnlTriggerFlag; + } +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check reload flag */ + if (base->SC & FTM_SC_RF_MASK) + { + statusFlags |= kFTM_ReloadFlag; + } +#endif + + /* Lower 8 bits contain the channel status flags */ + statusFlags |= (base->STATUS & 0xFFU); + + return statusFlags; +} + +void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask) +{ + /* Clear the timer overflow flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_TimeOverflowFlag) + { + base->SC &= ~FTM_SC_TOF_MASK; + } + /* Clear fault flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_FaultFlag) + { + base->FMS &= ~FTM_FMS_FAULTF_MASK; + } + /* Clear channel trigger flag */ + if (mask & kFTM_ChnlTriggerFlag) + { + base->EXTTRIG &= ~FTM_EXTTRIG_TRIGF_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check reload flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_ReloadFlag) + { + base->SC &= ~FTM_SC_RF_MASK; + } +#endif + /* Clear the channel status flags by writing a 0 to the bit */ + base->STATUS &= ~(mask & 0xFFU); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h new file mode 100755 index 00000000000..eb1ebf79f4c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h @@ -0,0 +1,862 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FTM_H_ +#define _FSL_FTM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ftm_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of FTM channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _ftm_chnl +{ + kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/ + kFTM_Chnl_1, /*!< FTM channel number 1 */ + kFTM_Chnl_2, /*!< FTM channel number 2 */ + kFTM_Chnl_3, /*!< FTM channel number 3 */ + kFTM_Chnl_4, /*!< FTM channel number 4 */ + kFTM_Chnl_5, /*!< FTM channel number 5 */ + kFTM_Chnl_6, /*!< FTM channel number 6 */ + kFTM_Chnl_7 /*!< FTM channel number 7 */ +} ftm_chnl_t; + +/*! @brief List of FTM faults */ +typedef enum _ftm_fault_input +{ + kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */ + kFTM_Fault_1, /*!< FTM fault 1 input pin */ + kFTM_Fault_2, /*!< FTM fault 2 input pin */ + kFTM_Fault_3 /*!< FTM fault 3 input pin */ +} ftm_fault_input_t; + +/*! @brief FTM PWM operation modes */ +typedef enum _ftm_pwm_mode +{ + kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */ + kFTM_CombinedPwm /*!< Combined PWM */ +} ftm_pwm_mode_t; + +/*! @brief FTM PWM output pulse mode: high-true, low-true or no output */ +typedef enum _ftm_pwm_level_select +{ + kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */ + kFTM_LowTrue, /*!< Low true pulses */ + kFTM_HighTrue /*!< High true pulses */ +} ftm_pwm_level_select_t; + +/*! @brief Options to configure a FTM channel's PWM signal */ +typedef struct _ftm_chnl_pwm_signal_param +{ + ftm_chnl_t chnlNumber; /*!< The channel/channel pair number. + In combined mode, this represents the channel pair number. */ + ftm_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0 = inactive signal(0% duty cycle)... + 100 = always active signal (100% duty cycle).*/ + uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate an asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure leave as 0; Should be specified as a + percentage of the PWM period */ +} ftm_chnl_pwm_signal_param_t; + +/*! @brief FlexTimer output compare mode */ +typedef enum _ftm_output_compare_mode +{ + kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ + kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ + kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */ + kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */ +} ftm_output_compare_mode_t; + +/*! @brief FlexTimer input capture edge */ +typedef enum _ftm_input_capture_edge +{ + kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/ + kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/ + kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ +} ftm_input_capture_edge_t; + +/*! @brief FlexTimer dual edge capture modes */ +typedef enum _ftm_dual_edge_capture_mode +{ + kFTM_OneShot = 0U, /*!< One-shot capture mode */ + kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */ +} ftm_dual_edge_capture_mode_t; + +/*! @brief FlexTimer dual edge capture parameters */ +typedef struct _ftm_dual_edge_capture_param +{ + ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */ + ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ + ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ +} ftm_dual_edge_capture_param_t; + +/*! @brief FlexTimer quadrature decode modes */ +typedef enum _ftm_quad_decode_mode +{ + kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ + kFTM_QuadCountAndDir /*!< Count and direction encoding mode */ +} ftm_quad_decode_mode_t; + +/*! @brief FlexTimer quadrature phase polarities */ +typedef enum _ftm_phase_polarity +{ + kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ + kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */ +} ftm_phase_polarity_t; + +/*! @brief FlexTimer quadrature decode phase parameters */ +typedef struct _ftm_phase_param +{ + bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */ + uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */ + ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */ +} ftm_phase_params_t; + +/*! @brief Structure is used to hold the parameters to configure a FTM fault */ +typedef struct _ftm_fault_param +{ + bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */ + bool faultLevel; /*!< True: Fault polarity is active low i.e '0' indicates a fault; + False: Fault polarity is active high */ + bool useFaultFilter; /*!< True: Use the filtered fault signal; + False: Use the direct path from fault input */ +} ftm_fault_param_t; + +/*! @brief FlexTimer pre-scaler factor for the dead time insertion*/ +typedef enum _ftm_deadtime_prescale +{ + kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */ + kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */ + kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */ +} ftm_deadtime_prescale_t; + +/*! @brief FlexTimer clock source selection*/ +typedef enum _ftm_clock_source +{ + kFTM_SystemClock = 1U, /*!< System clock selected */ + kFTM_FixedClock, /*!< Fixed frequency clock */ + kFTM_ExternalClock /*!< External clock */ +} ftm_clock_source_t; + +/*! @brief FlexTimer pre-scaler factor selection for the clock source*/ +typedef enum _ftm_clock_prescale +{ + kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ + kFTM_Prescale_Divide_2, /*!< Divide by 2 */ + kFTM_Prescale_Divide_4, /*!< Divide by 4 */ + kFTM_Prescale_Divide_8, /*!< Divide by 8 */ + kFTM_Prescale_Divide_16, /*!< Divide by 16 */ + kFTM_Prescale_Divide_32, /*!< Divide by 32 */ + kFTM_Prescale_Divide_64, /*!< Divide by 64 */ + kFTM_Prescale_Divide_128 /*!< Divide by 128 */ +} ftm_clock_prescale_t; + +/*! @brief Options for the FlexTimer behaviour in BDM Mode */ +typedef enum _ftm_bdm_mode +{ + kFTM_BdmMode_0 = 0U, + /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V + registers bypass the register buffers */ + kFTM_BdmMode_1, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to + MOD,CNTIN and C(n)V registers bypass the register buffers */ + kFTM_BdmMode_2, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, + writes to MOD,CNTIN and C(n)V registers bypass the register buffers */ + kFTM_BdmMode_3 + /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and + C(n)V registers is in fully functional mode */ +} ftm_bdm_mode_t; + +/*! @brief Options for the FTM fault control mode */ +typedef enum _ftm_fault_mode +{ + kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */ + kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */ + kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */ + kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */ +} ftm_fault_mode_t; + +/*! + * @brief FTM external trigger options + * @note Actual available external trigger sources are SoC-specific + */ +typedef enum _ftm_external_trigger +{ + kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */ + kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */ + kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */ + kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */ + kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */ + kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */ + kFTM_Chnl6Trigger = + (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */ + kFTM_Chnl7Trigger = + (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */ + kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */ + kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */ +} ftm_external_trigger_t; + +/*! @brief FlexTimer PWM sync options to update registers with buffer */ +typedef enum _ftm_pwm_sync_method +{ + kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */ + kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */ + kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */ + kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */ +} ftm_pwm_sync_method_t; + +/*! + * @brief FTM options available as loading point for register reload + * @note Actual available reload points are SoC-specific + */ +typedef enum _ftm_reload_point +{ + kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */ + kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */ + kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */ + kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */ + kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */ + kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */ + kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */ + kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */ + kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */ + kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */ + kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */ +} ftm_reload_point_t; + +/*! + * @brief List of FTM interrupts + * @note Actual available interrupts are SoC-specific + */ +typedef enum _ftm_interrupt_enable +{ + kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */ + kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */ + kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */ + kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */ + kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */ + kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */ + kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */ + kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */ + kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */ + kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */ + kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */ +} ftm_interrupt_enable_t; + +/*! + * @brief List of FTM flags + * @note Actual available flags are SoC-specific + */ +typedef enum _ftm_status_flags +{ + kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */ + kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */ + kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */ + kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */ + kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */ + kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */ + kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */ + kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */ + kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */ + kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */ + kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */ + kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */ +} ftm_status_flags_t; + +/*! + * @brief FTM configuration structure + * + * This structure holds the configuration settings for the FTM peripheral. To initialize this + * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ftm_config +{ + ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */ + ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */ + uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple + update modes can be used by providing an OR'ed list of options + available in enumeration ::ftm_pwm_sync_method_t. */ + uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM + synchronization is not required. Multiple reload points can be used by providing + an OR'ed list of options available in + enumeration ::ftm_reload_point_t. */ + ftm_fault_mode_t faultMode; /*!< FTM fault control mode */ + uint8_t faultFilterValue; /*!< Fault input filter value */ + ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */ + uint8_t deadTimeValue; /*!< The dead time value */ + uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be + enabled by providing an OR'ed list of options available in + enumeration ::ftm_external_trigger_t. */ + uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */ + uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */ + bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled; + False: disabled */ +} ftm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FTM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the FTM driver. + * + * @param base FTM peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t FTM_Init(FTM_Type *base, const ftm_config_t *config); + +/*! + * @brief Gates the FTM clock. + * + * @param base FTM peripheral base address + */ +void FTM_Deinit(FTM_Type *base); + +/*! + * @brief Fills in the FTM configuration structure with the default settings. + * + * The default values are: + * @code + * config->prescale = kFTM_Prescale_Divide_1; + * config->bdmMode = kFTM_BdmMode_0; + * config->pwmSyncMode = kFTM_SoftwareTrigger; + * config->reloadPoints = 0; + * config->faultMode = kFTM_Fault_Disable; + * config->faultFilterValue = 0; + * config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + * config->deadTimeValue = 0; + * config->extTriggers = 0; + * config->chnlInitState = 0; + * config->chnlPolarity = 0; + * config->useGlobalTimeBase = false; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void FTM_GetDefaultConfig(ftm_config_t *config); + +/*! @}*/ + +/*! + * @name Channel mode operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this + * function to configure all FTM channels that are used to output a PWM signal. + * + * @param base FTM peripheral base address + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure; This should be the size of the array passed in + * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz FTM counter clock in Hz + * + * @return kStatus_Success if the PWM setup was successful + * kStatus_Error on failure + */ +status_t FTM_SetupPwm(FTM_Type *base, + const ftm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel/channel pair number. In combined mode, this represents + * the channel pair number + * @param currentPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void FTM_UpdatePwmDutycycle(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Updates the edge level selection for a channel. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. + * See the Kinetis SoC reference manual for details about this field. + */ +void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level); + +/*! + * @brief Enables capturing an input signal on the channel using the function parameters. + * + * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is + * captured into the CnV register. The user has to read the CnV register separately to get this + * value. The filter function is disabled if the filterVal argument passed in is 0. The filter + * function is available only for channels 0, 1, 2, 3. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param captureMode Specifies which edge to capture + * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3. + */ +void FTM_SetupInputCapture(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_input_capture_edge_t captureMode, + uint32_t filterValue); + +/*! + * @brief Configures the FTM to generate timed pulses. + * + * When the FTM counter matches the value of compareVal argument (this is written into CnV reg), + * the channel output is changed based on what is specified in the compareMode argument. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param compareMode Action to take on the channel output when the compare condition is met + * @param compareValue Value to be programmed in the CnV register. + */ +void FTM_SetupOutputCompare(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_output_compare_mode_t compareMode, + uint32_t compareValue); + +/*! + * @brief Configures the dual edge capture mode of the FTM. + * + * This function sets up the dual edge capture mode on a channel pair. The capture edge for the + * channel pair and the capture mode (one-shot or continuous) is specified in the parameter + * argument. The filter function is disabled if the filterVal argument passed is zero. The filter + * function is available only on channels 0 and 2. The user has to read the channel CnV registers + * separately to get the capture values. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param edgeParam Sets up the dual edge capture function + * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1. + */ +void FTM_SetupDualEdgeCapture(FTM_Type *base, + ftm_chnl_t chnlPairNumber, + const ftm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue); + +/*! @}*/ + +/*! + * @brief Configures the parameters and activates the quadrature decoder mode. + * + * @param base FTM peripheral base address + * @param phaseAParams Phase A configuration parameters + * @param phaseBParams Phase B configuration parameters + * @param quadMode Selects encoding mode used in quadrature decoder mode + */ +void FTM_SetupQuadDecode(FTM_Type *base, + const ftm_phase_params_t *phaseAParams, + const ftm_phase_params_t *phaseBParams, + ftm_quad_decode_mode_t quadMode); + +/*! + * @brief Sets up the working of the FTM fault protection. + * + * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter. + * + * @param base FTM peripheral base address + * @param faultNumber FTM fault to configure. + * @param faultParams Parameters passed in to set up the fault + */ +void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected FTM interrupts. + * + * @param base FTM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected FTM interrupts. + * + * @param base FTM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled FTM interrupts. + * + * @param base FTM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +uint32_t FTM_GetEnabledInterrupts(FTM_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the FTM status flags. + * + * @param base FTM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ftm_status_flags_t + */ +uint32_t FTM_GetStatusFlags(FTM_Type *base); + +/*! + * @brief Clears the FTM status flags. + * + * @param base FTM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ftm_status_flags_t + */ +void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the FTM counter. + * + * @param base FTM peripheral base address + * @param clockSource FTM clock source; After the clock source is set, the counter starts running. + */ +static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource) +{ + uint32_t reg = base->SC; + + reg &= ~(FTM_SC_CLKS_MASK); + reg |= FTM_SC_CLKS(clockSource); + base->SC = reg; +} + +/*! + * @brief Stops the FTM counter. + * + * @param base FTM peripheral base address + */ +static inline void FTM_StopTimer(FTM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(FTM_SC_CLKS_MASK); +} + +/*! @}*/ + +/*! + * @name Software output control + * @{ + */ + +/*! + * @brief Enables or disables the channel software output control. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be enabled or disabled + * @param value true: channel output is affected by software output control + false: channel output is unaffected by software output control + */ +static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SWOCTRL |= (1U << chnlNumber); + } + else + { + base->SWOCTRL &= ~(1U << chnlNumber); + } +} + +/*! + * @brief Sets the channel software output control value. + * + * @param base FTM peripheral base address. + * @param chnlNumber Channel to be configured + * @param value true to set 1, false to set 0 + */ +static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SWOCTRL |= (1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); + } + else + { + base->SWOCTRL &= ~(1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); + } +} + +/*! @}*/ + +/*! + * @brief Enables or disables the FTM global time base signal generation to other FTMs. + * + * @param base FTM peripheral base address + * @param enable true to enable, false to disable + */ +static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable) +{ + if (enable) + { + base->CONF |= FTM_CONF_GTBEOUT_MASK; + } + else + { + base->CONF &= ~FTM_CONF_GTBEOUT_MASK; + } +} + +/*! + * @brief Sets the FTM peripheral timer channel output mask. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be configured + * @param mask true: masked, channel is forced to its inactive state; false: unmasked + */ +static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask) +{ + if (mask) + { + base->OUTMASK |= (1U << chnlNumber); + } + else + { + base->OUTMASK &= ~(1U << chnlNumber); + } +} + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) +/*! + * @brief Allows user to enable an output on an FTM channel. + * + * To enable the PWM channel output call this function with val=true. For input mode, + * call this function with val=false. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be configured + * @param value true: enable output; false: output is disabled, used in input mode + */ +static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SC |= (1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); + } + else + { + base->SC &= ~(1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); + } +} +#endif + +/*! + * @name Channel pair operations + * @{ + */ + +/*! + * @brief This function enables/disables the fault control in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: Enable fault control for this channel pair; false: No fault control + */ +static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables the dead time insertion in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: Insert dead time in this channel pair; false: No dead time inserted + */ +static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables complementary mode in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: enable complementary mode; false: disable complementary mode + */ +static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables inverting control in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: enable inverting; false: disable inverting + */ +static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->INVCTRL |= (1U << chnlPairNumber); + } + else + { + base->INVCTRL &= ~(1U << chnlPairNumber); + } +} + +/*! @}*/ + +/*! + * @brief Enables or disables the FTM software trigger for PWM synchronization. + * + * @param base FTM peripheral base address + * @param enable true: software trigger is selected, false: software trigger is not selected + */ +static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable) +{ + if (enable) + { + base->SYNC |= FTM_SYNC_SWSYNC_MASK; + } + else + { + base->SYNC &= ~FTM_SYNC_SWSYNC_MASK; + } +} + +/*! + * @brief Enables or disables the FTM write protection. + * + * @param base FTM peripheral base address + * @param enable true: Write-protection is enabled, false: Write-protection is disabled + */ +static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable) +{ + /* Configure write protection */ + if (enable) + { + base->FMS |= FTM_FMS_WPEN_MASK; + } + else + { + base->MODE |= FTM_MODE_WPDIS_MASK; + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FTM_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c new file mode 100755 index 00000000000..8fc068f2d6a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_GPIO_COUNT); + + return instance; +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + GPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! +* @brief Gets the FGPIO instance according to the GPIO base +* +* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval FGPIO instance +*/ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT); + + return instance; +} + +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + FGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h new file mode 100755 index 00000000000..6eaaaa08744 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.1.0. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief GPIO direction definition*/ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused + * Note : In some cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig() + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin's number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low logic level. + * - 1: corresponding pin output high logic level. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin's number + * @retval GPIO port input value + * - 0: corresponding pin input low logic level. + * - 1: corresponding pin input high logic level. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name GPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads whole GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pins' interrupt status flag. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); + +/*@}*/ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduce the FGPIO feature. + * + * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name FGPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO pin's number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low logic level. + * - 1: corresponding pin output high logic level. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name FGPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the whole FGPIO port. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO pin's number + * @retval FGPIO port input value + * - 0: corresponding pin input low logic level. + * - 1: corresponding pin input high logic level. + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name FGPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads the whole FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pins' interrupt status flag. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); + +/*@}*/ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c new file mode 100755 index 00000000000..e77a3832399 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c @@ -0,0 +1,1536 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ +/*! All flags which are cleared by the driver upon starting a transfer. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, +#else + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +#endif + +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; + +/*! @brief SCL clock divider used to calculate baudrate. */ +const uint16_t s_i2cDividerTable[] = {20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, + 48, 56, 68, 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, + 112, 128, 144, 160, 192, 240, 160, 192, 224, 256, 288, 320, 384, + 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768, 896, 1024, + 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +/*! @brief Pointers to i2c clocks for each instance. */ +const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_I2C_COUNT; instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_I2C_COUNT); + + return instance; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + uint16_t timeout = UINT16_MAX; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + else + { + handle->state = kCheckAddressState; + } + + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout)) + { + } + + /* Failed to start the transfer. */ + if (timeout == 0) + { + return kStatus_I2C_Timeout; + } + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->S; + *isDone = false; + volatile uint8_t dummy = 0; + bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + if (result) + { + return result; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == kCheckAddressState) + { + if (statusFlags & kI2C_ReceiveNakFlag) + { + return kStatus_I2C_Nak; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case kSendCommandState: + if (handle->transfer.subaddressSize) + { + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case kReceiveDataBeginState: + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Next state, receive data. */ + handle->state = kReceiveDataState; + break; + + /* Receive I2C data. */ + case kReceiveDataState: + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->D; + handle->transfer.data++; + } + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig && srcClock_Hz); + + /* Temporary register for filter read. */ + uint8_t fltReg; +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + uint8_t c2Reg; +#endif + + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); + + /* Disable I2C prior to configuring it. */ + base->C1 &= ~(I2C_C1_IICEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + /* Configure high drive feature. */ + c2Reg = base->C2; + c2Reg &= ~(I2C_C2_HDRS_MASK); + c2Reg |= I2C_C2_HDRS(masterConfig->enableHighDrive); + base->C2 = c2Reg; +#endif + + /* Read out the FLT register. */ + fltReg = base->FLT; + +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + /* Configure the stop / hold enable. */ + fltReg &= ~(I2C_FLT_SHEN_MASK); + fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); +#endif + + /* Configure the glitch filter value. */ + fltReg &= ~(I2C_FLT_FLT_MASK); + fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); + + /* Write the register value back to the filter register. */ + base->FLT = fltReg; + + /* Enable the I2C peripheral based on the configuration. */ + base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + +/* Default pin high drive is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + masterConfig->enableHighDrive = false; +#endif + +/* Default stop hold enable is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + masterConfig->enableStopHold = false; +#endif + + /* Default glitch filter value is no filter. */ + masterConfig->glitchFilterWidth = 0U; + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 |= I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT |= I2C_FLT_STOPIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT |= I2C_FLT_SSIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 &= ~I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT &= ~I2C_FLT_STOPIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT &= ~I2C_FLT_SSIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t multiplier; + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) + { + multiplier = 1u << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) + { + computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint8_t savedMult; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + uint8_t timeDelay = 6; + + /* Return an error if the bus is already in use, but not by us. */ + if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0)) + { + result = kStatus_I2C_Busy; + } + else + { + savedMult = base->F; + base->F = savedMult & (~I2C_F_MULT_MASK); + + /* We are already in a transfer, so send a repeated start. */ + base->C1 |= I2C_C1_RSTA_MASK; + + /* Restore the multiplier factor. */ + base->F = savedMult; + + /* Add some delay to wait the Re-Start signal. */ + while (timeDelay--) + { + __NOP(); + } + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + /* Issue the STOP command on the bus. */ + base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Wait until data transfer complete. */ + while ((base->S & kI2C_BusBusyFlag) && (--timeout)) + { + } + + if (timeout == 0) + { + result = kStatus_I2C_Timeout; + } + + return result; +} + +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + uint32_t statusFlags = base->S; + +#ifdef I2C_HAS_STOP_DETECT + /* Look up the STOPF bit from the filter register. */ + if (base->FLT & I2C_FLT_STOPF_MASK) + { + statusFlags |= kI2C_StopDetectFlag; + } +#endif + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Look up the STARTF bit from the filter register. */ + if (base->FLT & I2C_FLT_STARTF_MASK) + { + statusFlags |= kI2C_StartDetectFlag; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + return statusFlags; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->C1 |= I2C_C1_TX_MASK; + + while (txSize--) + { + /* Send a byte of data. */ + base->D = *txBuff++; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + statusFlags = base->S; + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (statusFlags & kI2C_ArbitrationLostFlag) + { + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if (statusFlags & kI2C_ReceiveNakFlag) + { + base->S = kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + return result; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = base->D; + + while ((rxSize--)) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0) + { + /* Read the final byte. */ + result = I2C_MasterStop(base); + } + + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = base->D; + } + + return result; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Wait until ready to complete. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + /* Return if error. */ + if (result) + { + return result; + } + + /* Send subaddress. */ + if (xfer->subaddressSize) + { + do + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + xfer->subaddressSize--; + base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); + + } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + + if (xfer->direction == kI2C_Read) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result) + { + return result; + } + } + } + + /* Wait until address + command transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + /* Transmit data. */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize); + + if (((result == kStatus_Success) && (!(xfer->flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + } + + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || result) + { + /* Send stop command if transfer done or received Nak. */ + if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->C1 & I2C_C1_MST_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + uint8_t tmpReg; + + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); + + /* Configure addressing mode. */ + switch (slaveConfig->addressingMode) + { + case kI2C_Address7bit: + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + break; + + case kI2C_RangeMatch: + assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U; + base->C2 |= I2C_C2_RMEN_MASK; + break; + + default: + break; + } + + /* Configure low power wake up feature. */ + tmpReg = base->C1; + tmpReg &= ~I2C_C1_WUEN_MASK; + base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); + + /* Configure general call & baud rate control & high drive feature. */ + tmpReg = base->C2; + tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); + tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + tmpReg &= ~I2C_C2_HDRS_MASK; + tmpReg |= I2C_C2_HDRS(slaveConfig->enableHighDrive); +#endif + base->C2 = tmpReg; +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* By default slave is addressed with 7-bit address. */ + slaveConfig->addressingMode = kI2C_Address7bit; + + /* General call mode is disabled by default. */ + slaveConfig->enableGeneralCall = false; + + /* Slave address match waking up MCU from low power mode is disabled. */ + slaveConfig->enableWakeUp = false; + +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + /* Default pin high drive is disabled. */ + slaveConfig->enableHighDrive = false; +#endif + + /* Independent slave mode baud rate at maximum frequency is disabled. */ + slaveConfig->enableBaudRateCtl = false; + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + return I2C_MasterWriteBlocking(base, txBuff, txSize); +} + +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Wait until the data register is ready for receive. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK); + + while (rxSize--) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->D; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + } +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->isBusy) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, kIrqFlags); + } + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle); + + if (handle->isBusy) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->isBusy = false; + } +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + +#ifdef I2C_HAS_STOP_DETECT + /* Check stop flag. */ + if (status & kI2C_StopDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Call slave callback if this is the STOP of the transfer. */ + if (handle->isBusy) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + return; + } +#endif /* I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + if (status & kI2C_StartDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + xfer->event = kI2C_SlaveRepeatedStartEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (!(status & kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check NAK */ + if (status & kI2C_ReceiveNakFlag) + { + /* Set receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy. */ + dummy = base->D; + + if (handle->transfer.dataSize != 0) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + /* Check address match. */ + else if (status & kI2C_AddressMatchFlag) + { + handle->isBusy = true; + xfer->event = kI2C_SlaveAddressMatchEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + /* Change direction to send data. */ + base->C1 |= I2C_C1_TX_MASK; + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + } + } + /* Check transfer complete flag. */ + else if (status & kI2C_TransferCompleteFlag) + { + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + uint8_t data = base->D; + + if (handle->transfer.dataSize) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + if (!handle->transfer.dataSize) + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed receive complete event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->D; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + if (handle->transfer.dataSize) + { + /* Send data. */ + base->D = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed txdone event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } +} + +void I2C0_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); +} + +#if (FSL_FEATURE_SOC_I2C_COUNT > 1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif /* I2C COUNT > 1 */ + +#if (FSL_FEATURE_SOC_I2C_COUNT > 2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif /* I2C COUNT > 2 */ +#if (FSL_FEATURE_SOC_I2C_COUNT > 3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif /* I2C COUNT > 3 */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h new file mode 100755 index 00000000000..41a9afbdd54 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h @@ -0,0 +1,781 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.0. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ + defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) +#define I2C_HAS_STOP_DETECT +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * - #kI2C_StartDetectFlag + * - #kI2C_StopDetectFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ + kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ +#ifdef I2C_HAS_STOP_DETECT + kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmit to slave. */ + kI2C_Read = 0x1U, /*!< Master receive from slave. */ +} i2c_direction_t; + +/*! @brief Addressing mode. */ +typedef enum _i2c_slave_address_mode +{ + kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ + kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ +} i2c_slave_address_mode_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< Transfer starts without a start signal. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< Transfer ends without a stop signal. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ +#endif + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveRepeatedStartEvent | +#endif + kI2C_SlaveCompletionEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */ +#endif +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + bool enableStopHold; /*!< Controls the stop hold enable. */ +#endif + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ + uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ +} i2c_master_config_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + bool enableGeneralCall; /*!< Enable general call addressing mode. */ + bool enableWakeUp; /*!< Enables/disables waking up MCU from low power mode. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */ +#endif + bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ + uint16_t slaveAddress; /*!< Slave address configuration. */ + uint16_t upperAddress; /*!< Maximum boundary slave address used in range matching mode. */ + i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */ +} i2c_slave_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t *volatile data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t *volatile data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + bool isBusy; /*!< Whether transfer is busy. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application to use + * the I2C driver, or any operation to the I2C module could cause hard fault + * because clock is not enabled. The configuration structure can be filled by user + * from scratch, or be set with default values by I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * Example: + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig pointer to master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initializes the I2C with slave configuration. + * + * @note This API should be called at the beginning of the application to use + * the I2C driver, or any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user. + * Example + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false + * }; + * I2C_SlaveInit(I2C0, &config); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig pointer to slave configuration structure + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of + * the structure before calling I2C_MasterConfigure(). + * Example: + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig Pointer to the master configuration structure. +*/ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * Example: + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig Pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disabless the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_IICEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_IICEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags could get the related status. + */ +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags could get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter could be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ +/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (statusMask & kI2C_StartDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + +#ifdef I2C_HAS_STOP_DETECT + if (statusMask & kI2C_StopDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + + base->S = (uint8_t)statusMask; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter could be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @name DMA Control + * @{ + */ +#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT +/*! + * @brief Enables/disables the I2C DMA interrupt. + * + * @param base I2C base pointer + * @param enable true to enable, false to disable +*/ +static inline void I2C_EnableDMA(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_DMAEN_MASK; + } +} + +#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ + +/*! + * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address + * for I2C DMA transfer configuration. + * + * @param base I2C base pointer + * @return data register address + */ +static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) +{ + return (uint32_t)(&(base->D)); +} + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus without a STOP signal. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus with a STOP signal. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user paramater passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API will return immediately after transfer initiates, user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished, if the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Sucessully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c new file mode 100755 index 00000000000..c8f7c20629f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, false); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) + { + /* Change to send NAK at the last byte. */ + i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; + + /* Wait the last data to be received. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + + /* Read the last data byte. */ + *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = + i2cPrivateHandle->base->D; + } + else + { + /* Wait the last data to be sent. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + } + } + + i2cPrivateHandle->handle->state = kIdleState; + + if (i2cPrivateHandle->handle->completionCallback) + { + i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result, + i2cPrivateHandle->handle->userData); + } +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + i2c_direction_t direction = xfer->direction; + + /* Init the handle member. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + handle->state = kTransferDataState; + + /* Wait until ready to complete. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout)) + { + } + + /* Failed to start the transfer. */ + if (timeout == 0) + { + return kStatus_I2C_Timeout; + } + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + /* Send subaddress. */ + if (handle->transfer.subaddressSize) + { + do + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + return result; + } + + } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success)); + + if (handle->transfer.direction == kI2C_Read) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + } + } + + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + } + + return result; +} + +static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle) +{ + edma_transfer_config_t transfer_config; + + if (handle->transfer.direction == kI2C_Read) + { + transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.destAddr = (uint32_t)(handle->transfer.data); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); + } + else + { + transfer_config.majorLoopCounts = handle->transfer.dataSize; + } + + transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.srcOffset = 0; + transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.destOffset = 1; + transfer_config.minorLoopBytes = 1; + } + else + { + transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1); + transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); + transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.srcOffset = 1; + transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.destOffset = 0; + transfer_config.minorLoopBytes = 1; + } + + EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config); + EDMA_StartTransfer(handle->dmaHandle); +} + +void I2C_MasterCreateEDMAHandle(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaHandle) +{ + assert(handle); + assert(edmaHandle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Set the base for the handle. */ + base = base; + + /* Set the handle for EDMA. */ + handle->dmaHandle = edmaHandle; + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]); +} + +status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result; + uint8_t tmpReg; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable dma xfer. */ + I2C_EnableDMA(base, false); + + /* Send address and command buffer(if there is), until senddata phase or receive data phase. */ + result = I2C_InitTransferStateMachineEDMA(base, handle, xfer); + + if (result) + { + /* Send stop if received Nak. */ + if (result == kStatus_I2C_Nak) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + + /* Reset the state to idle state. */ + handle->state = kIdleState; + + return result; + } + + /* Configure dma transfer. */ + /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read, + need to send stop before reading the last byte, so the dma transfer size should + be (xSize - 1). */ + if (handle->transfer.dataSize > 1) + { + I2C_MasterTransferEDMAConfig(base, handle); + if (handle->transfer.direction == kI2C_Read) + { + /* Change direction for receive. */ + base->C1 &= ~I2C_C1_TX_MASK; + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + } + else + { + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + + /* Send the first data. */ + base->D = *handle->transfer.data; + } + } + else /* If transfer size is 1, use polling method. */ + { + if (handle->transfer.direction == kI2C_Read) + { + tmpReg = base->C1; + + /* Change direction to Rx. */ + tmpReg &= ~I2C_C1_TX_MASK; + + /* Configure send NAK */ + tmpReg |= I2C_C1_TXAK_MASK; + + base->C1 = tmpReg; + + /* Read dummy to release the bus. */ + dummy = base->D; + } + else + { + base->D = *handle->transfer.data; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + + /* Read the last byte of data. */ + if (handle->transfer.direction == kI2C_Read) + { + *handle->transfer.data = base->D; + } + + /* Reset the state to idle. */ + handle->state = kIdleState; + } + + return result; +} + +status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle->dmaHandle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kIdleState != handle->state) + { + *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + else + { + *count = handle->transferSize; + } + + return kStatus_Success; +} + +void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle) +{ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable dma transfer. */ + I2C_EnableDMA(base, false); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h new file mode 100755 index 00000000000..234876d451c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup i2c_edma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief I2C master edma handle typedef. */ +typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t; + +/*! @brief I2C master edma transfer callback typedef. */ +typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base, + i2c_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master edma transfer structure. */ +struct _i2c_master_edma_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< I2C master transfer status. */ + edma_handle_t *dmaHandle; /*!< The eDMA handler used. */ + i2c_master_edma_transfer_callback_t + completionCallback; /*!< Callback function called after edma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block EDMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transcational functions. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + * @param callback pointer to user callback function. + * @param userData user param passed to the callback function. + * @param edmaHandle EDMA handle pointer. + */ +void I2C_MasterCreateEDMAHandle(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaHandle); + +/*! + * @brief Performs a master edma non-blocking transfer on the I2C bus. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + * @param xfer pointer to transfer structure of i2c_master_transfer_t. + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a edma non-blocking transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master edma non-blocking transfer in a early time. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_edma_handle_t structure. + */ +void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c new file mode 100755 index 00000000000..c27b91e9f04 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_llwu.h" + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + volatile uint32_t *regBase; + uint32_t regOffset; + uint32_t reg; + + switch (pinIndex >> 4U) + { + case 0U: + regBase = &base->PE1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 1U: + regBase = &base->PE2; + break; +#endif + default: + regBase = NULL; + break; + } +#else + volatile uint8_t *regBase; + uint8_t regOffset; + uint8_t reg; + switch (pinIndex >> 2U) + { + case 0U: + regBase = &base->PE1; + break; + case 1U: + regBase = &base->PE2; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 2U: + regBase = &base->PE3; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) + case 3U: + regBase = &base->PE4; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 4U: + regBase = &base->PE5; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) + case 5U: + regBase = &base->PE6; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 6U: + regBase = &base->PE7; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) + case 7U: + regBase = &base->PE8; + break; +#endif + default: + regBase = NULL; + break; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ + + if (regBase) + { + reg = *regBase; +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + regOffset = ((pinIndex & 0x0FU) << 1U); +#else + regOffset = ((pinIndex & 0x03U) << 1U); +#endif + reg &= ~(0x3U << regOffset); + reg |= ((uint32_t)pinMode << regOffset); + *regBase = reg; + } +} + +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->PF & (1U << pinIndex)); +#else + volatile uint8_t *regBase; + + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + return (bool)(*regBase & (1U << pinIndex % 8)); + } + else + { + return false; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + base->PF = (1U << pinIndex); +#else + volatile uint8_t *regBase; + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + if (regBase) + { + *regBase = (1U << pinIndex % 8U); + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); + reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) + /* Clear the Filter Detect Flag */ + | LLWU_FILT_FILTF1_MASK) + << (filterIndex * 8U - 1U)); + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); + reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); + reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); + /* Clear the Filter Detect Flag */ + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); +#else + bool status = false; + + switch (filterIndex) + { + case 1: + status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + break; + } + + return status; +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + switch (filterIndex) + { + case 1: + reg |= LLWU_FILT_FILTF1_MASK; + break; + case 2: + reg |= LLWU_FILT_FILTF2_MASK; + break; + case 3: + reg |= LLWU_FILT_FILTF3_MASK; + break; + case 4: + reg |= LLWU_FILT_FILTF4_MASK; + break; + default: + break; + } + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) +{ + uint8_t reg; + + reg = base->RST; + reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); + reg |= + (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); + base->RST = reg; +} +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h new file mode 100755 index 00000000000..7c11572e806 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LLWU_H_ +#define _FSL_LLWU_H_ + +#include "fsl_common.h" + +/*! @addtogroup llwu */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LLWU driver version 2.0.1. */ +#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief External input pin control modes + */ +typedef enum _llwu_external_pin_mode +{ + kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as wakeup input. */ + kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with rising edge detection. */ + kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/ + kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ +} llwu_external_pin_mode_t; + +/*! + * @brief Digital filter control modes + */ +typedef enum _llwu_pin_filter_mode +{ + kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ + kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ + kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ + kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ +} llwu_pin_filter_mode_t; + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _llwu_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} llwu_version_id_t; +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _llwu_param +{ + uint8_t filters; /*!< Number of pin filter. */ + uint8_t dmas; /*!< Number of wakeup DMA. */ + uint8_t modules; /*!< Number of wakeup module. */ + uint8_t pins; /*!< Number of wake up pin. */ +} llwu_param_t; +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief External input pin filter control structure + */ +typedef struct _llwu_external_pin_filter_mode +{ + uint32_t pinIndex; /*!< Pin number */ + llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ +} llwu_external_pin_filter_mode_t; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Low-Leakage Wakeup Unit Control APIs + * @{ + */ + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief Gets the LLWU version ID. + * + * This function gets the LLWU version ID, including major version number, + * minor version number, and feature specification number. + * + * @param base LLWU peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief Gets the LLWU parameter. + * + * This function gets the LLWU parameter, including wakeup pin number, module + * number, DMA number, and pin filter number. + * + * @param base LLWU peripheral base address. + * @param param Pointer to LLWU param structure. + */ +static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) +{ + *((uint32_t *)param) = base->PARAM; +} +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * @brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index which to be enabled as external wakeup source, start from 1. + * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t + */ +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woke up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index, start from 1. + * @return true if the specific pin is wake up source. + */ +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); + +/*! + * @brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index, start from 1. + */ +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) +/*! + * @brief Enables/disables the internal module source. + * + * This function enables/disables the internal module source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex module index which to be enabled as internal wakeup source, start from 1. + * @param enable enable or disable setting + */ +static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->ME |= 1U << moduleIndex; + } + else + { + base->ME &= ~(1U << moduleIndex); + } +} + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the system is + * woke up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param moduleIndex module index, start from 1. + * @return true if the specific pin is wake up source. + */ +static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->MF & (1U << moduleIndex)); +#else +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->MF5 & (1U << moduleIndex)); +#else + return (bool)(base->F5 & (1U << moduleIndex)); +#endif /* FSL_FEATURE_LLWU_HAS_PF */ +#else +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->PF3 & (1U << moduleIndex)); +#else + return (bool)(base->F3 & (1U << moduleIndex)); +#endif +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ + +#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) +/*! + * @brief Enables/disables the internal module DMA wakeup source. + * + * This function enables/disables the internal DMA that is used as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex Internal module index which used as DMA request source, start from 1. + * @param enable Enable or disable DMA request source + */ +static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->DE |= 1U << moduleIndex; + } + else + { + base->DE &= ~(1U << moduleIndex); + } +} +#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1. + * @param filterMode filter mode configuration + */ +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index, start from 1. + * @return true if the flag is a source of existing a low-leakage power mode. + */ +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +/*! + * @brief Clear the pin filter configuration. + * + * This function clear the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index which to be clear the flag, start from 1. + */ +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +/*! + * @brief Sets the reset pin mode. + * + * This function sets how the reset pin is used as a low leakage mode exit source. + * + * @param pinEnable Enable reset pin filter + * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif /* _FSL_LLWU_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c new file mode 100755 index 00000000000..b3dcc89d55d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lptmr.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base LPTMR peripheral base address + * + * @return The LPTMR instance + */ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPTMR bases for each instance. */ +static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; + +/*! @brief Pointers to LPTMR clocks for each instance. */ +static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++) + { + if (s_lptmrBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT); + + return instance; +} + +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) +{ + assert(config); + + /* Ungate the LPTMR clock*/ + CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); + + /* Configure the timers operation mode and input pin setup */ + base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); + + /* Configure the prescale value and clock source */ + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + LPTMR_PSR_PCS(config->prescalerClockSource)); +} + +void LPTMR_Deinit(LPTMR_Type *base) +{ + /* Disable the LPTMR and reset the internal logic */ + base->CSR &= ~LPTMR_CSR_TEN_MASK; + /* Gate the LPTMR clock*/ + CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); +} + +void LPTMR_GetDefaultConfig(lptmr_config_t *config) +{ + assert(config); + + /* Use time counter mode */ + config->timerMode = kLPTMR_TimerModeTimeCounter; + /* Use input 0 as source in pulse counter mode */ + config->pinSelect = kLPTMR_PinSelectInput_0; + /* Pulse input pin polarity is active-high */ + config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + /* Counter resets whenever TCF flag is set */ + config->enableFreeRunning = false; + /* Bypass the prescaler */ + config->bypassPrescaler = true; + /* LPTMR clock source */ + config->prescalerClockSource = kLPTMR_PrescalerClock_1; + /* Divide the prescaler clock by 2 */ + config->value = kLPTMR_Prescale_Glitch_0; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h new file mode 100755 index 00000000000..fd3cb1ed242 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPTMR_H_ +#define _FSL_LPTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lptmr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief LPTMR pin selection, used in pulse counter mode.*/ +typedef enum _lptmr_pin_select +{ + kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ + kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ + kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ + kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity, used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity +{ + kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ + kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode +{ + kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ + kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler/glitch filter values*/ +typedef enum _lptmr_prescaler_glitch_value +{ + kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ + kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ + kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ + kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ + kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ + kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ + kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ + kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ + kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ + kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ + kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ + kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ + kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ + kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ + kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ + kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ +} lptmr_prescaler_glitch_value_t; + +/*! + * @brief LPTMR prescaler/glitch filter clock select. + * @note Clock connections are SoC-specific + */ +typedef enum _lptmr_prescaler_clock_select +{ + kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ + kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ + kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ + kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +} lptmr_prescaler_clock_select_t; + +/*! @brief List of LPTMR interrupts */ +typedef enum _lptmr_interrupt_enable +{ + kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ +} lptmr_interrupt_enable_t; + +/*! @brief List of LPTMR status flags */ +typedef enum _lptmr_status_flags +{ + kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ +} lptmr_status_flags_t; + +/*! + * @brief LPTMR config structure + * + * This structure holds the configuration settings for the LPTMR peripheral. To initialize this + * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _lptmr_config +{ + lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ + lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ + lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ + bool enableFreeRunning; /*!< true: enable free running, counter is reset on overflow + false: counter is reset when the compare flag is set */ + bool bypassPrescaler; /*!< true: bypass prescaler; false: use clock from prescaler */ + lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ + lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ +} lptmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungate the LPTMR clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the LPTMR driver. + * + * @param base LPTMR peripheral base address + * @param config Pointer to user's LPTMR config structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); + +/*! + * @brief Gate the LPTMR clock + * + * @param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base); + +/*! + * @brief Fill in the LPTMR config struct with the default settings + * + * The default values are: + * @code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * @endcode + * @param config Pointer to user's LPTMR config structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! + * @brief Disables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + base->CSR &= ~mask; +} + +/*! + * @brief Gets the enabled LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPTMR status flags + * + * @param base LPTMR peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TCF_MASK); +} + +/*! + * @brief Clears the LPTMR status flags + * + * @param base LPTMR peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers counts from 0 till it equals the count value set here. The count value is written to + * the CMR register. + * + * @note + * 1. The TCF flag is set with the CNR equals the count provided here and then increments. + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base LPTMR peripheral base address + * @param ticks Timer period in units of ticks + */ +static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks) +{ + base->CMR = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base LPTMR peripheral base address + * + * @return Current counter value in ticks + */ +static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) +{ + /* Must first write any value to the CNR. This will synchronize and register the current value + * of the CNR into a temporary register which can then be read + */ + base->CNR = 0U; + return (uint16_t)base->CNR; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, the timer counts up to the CMR register value. + * Each time the timer reaches CMR value and then increments, it generates a + * trigger pulse and sets the timeout interrupt flag. An interrupt will also be + * triggered if the timer interrupt is enabled. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StartTimer(LPTMR_Type *base) +{ + base->CSR |= LPTMR_CSR_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer counting and resets the timer's counter register + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StopTimer(LPTMR_Type *base) +{ + base->CSR &= ~LPTMR_CSR_TEN_MASK; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPTMR_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c new file mode 100755 index 00000000000..b1b015f6f49 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpuart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* LPUART transfer state. */ +enum _lpuart_transfer_states +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @userData handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART handle. */ +static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT]; +/* Array of LPUART peripheral base address. */ +static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; +/* Array of LPUART IRQ number. */ +static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; +/* Array of LPUART clock name. */ +static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; +/* LPUART ISR for transactional APIs. */ +static lpuart_isr_t s_lpuartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++) + { + if (s_lpuartBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_LPUART_COUNT); + + return instance; +} + +static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = base->DATA; + } +} + +void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + uint32_t temp; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* Enable lpuart clock */ + CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]); + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4; osrTemp <= 32; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0) + { + sbrTemp = 1; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - config->baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + { + tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < ((config->baudRate_Bps / 100) * 3)) + { + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3) && (osr < 8)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + } + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); + + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= (LPUART_CTRL_M_MASK | (uint8_t)config->parityMode); + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_IDLE_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; +} +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_IDLE_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0; + + /* Disable lpuart clock */ + CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]); +} + +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(config); + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 0; +#endif + config->enableTx = false; + config->enableRx = false; +} + +void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4; osrTemp <= 32; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0) + { + sbrTemp = 1; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + { + tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < ((baudRate_Bps / 100) * 3)) + { + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3) && (osr < 8)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + } + + /* Restore CTRL. */ + base->CTRL = oldCtrl; +} + +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO |= ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL |= mask; +} + +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO &= ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL &= ~mask; +} + +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + uint32_t temp; + temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; +#endif + temp |= (base->CTRL & 0xFF0C000); + + return temp; +} + +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16; +#endif + return temp; +} + +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag)); + temp |= mask & (kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag); + base->FIFO = temp; +#endif + temp = (uint32_t)base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp &= (uint32_t)(~(kLPUART_LinBreakFlag)); + temp |= mask & kLPUART_LinBreakFlag; +#endif + temp &= (uint32_t)(~(kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | + kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag)); + temp |= mask & (kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_NoiseErrorFlag | + kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag); +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp &= (uint32_t)(~(kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag)); + temp |= mask & (kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag); +#endif + base->STAT |= temp; + /* If some flags still pending. */ + if (mask & LPUART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, + kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, + kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ + status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ + } + else + { + status = kStatus_Success; + } + + return status; +} + +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->STAT & LPUART_STAT_TDRE_MASK)) + { + } + base->DATA = *(data++); + } +} + +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + + while (length--) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (!(base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { + statusFlag = LPUART_GetStatusFlags(base); + + if (statusFlag & kLPUART_RxOverrunFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); + return kStatus_LPUART_RxHardwareOverrun; + } + + if (statusFlag & kLPUART_NoiseErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); + return kStatus_LPUART_NoiseError; + } + + if (statusFlag & kLPUART_FramingErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); + return kStatus_LPUART_FramingError; + } + + if (statusFlag & kLPUART_ParityErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); + return kStatus_LPUART_ParityError; + } + } + *(data++) = base->DATA; + } + + return kStatus_Success; +} + +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = kLPUART_RxIdle; + handle->txState = kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER &= (~LPUART_WATER_RXWATER_SHIFT); +#endif + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr = LPUART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_lpuartIRQ[instance]); +} + +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ring buffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } +} + +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kLPUART_RxIdle) + { + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kLPUART_TxBusy; + + /* Enable transmiter interrupt. */ + LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kLPUART_TxIdle; +} + +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + if (kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kLPUART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kLPUART_RxBusy; + + /* Enable RX interrupt. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kLPUART_RxIdle; +} + +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + if (kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + volatile uint8_t dummy; + + assert(handle); + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & base->STAT) + { + /* Read base->DATA, otherwise the RX does not work. */ + dummy = base->DATA; + /* Avoid optimization */ + dummy++; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kLPUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kLPUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } + } + } +} + +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* TODO: To be implemented. */ +} + +#if defined(LPUART0) +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +} +void LPUART0_RX_TX_DriverIRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} +#endif + +#if defined(LPUART1) +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +} +void LPUART1_RX_TX_DriverIRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} +#endif + +#if defined(LPUART2) +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +} +void LPUART2_RX_TX_DriverIRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} +#endif + +#if defined(LPUART3) +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +} +void LPUART3_RX_TX_DriverIRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} +#endif + +#if defined(LPUART4) +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +} +void LPUART4_RX_TX_DriverIRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} +#endif + +#if defined(LPUART5) +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +} +void LPUART5_RX_TX_DriverIRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h new file mode 100755 index 00000000000..a357400b56a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version 2.1.0. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Error codes for the LPUART driver. */ +enum _lpuart_status +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char + detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configure structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! +* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. +* +* This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function +* to configure the configuration structure and get the default configuration. +* The example below shows how to use this API to configure the LPUART. +* @code +* lpuart_config_t lpuartConfig; +* lpuartConfig.baudRate_Bps = 115200U; +* lpuartConfig.parityMode = kLPUART_ParityDisabled; +* lpuartConfig.stopBitCount = kLPUART_OneStopBit; +* lpuartConfig.txFifoWatermark = 0; +* lpuartConfig.rxFifoWatermark = 1; +* LPUART_Init(LPUART1, &lpuartConfig, 20000000U); +* @endcode +* +* @param base LPUART peripheral base address. +* @param config Pointer to a user-defined configuration structure. +* @param srcClock_Hz LPUART clock source frequency in HZ. +*/ +void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + */ +void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + base->CTRL |= LPUART_CTRL_TIE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + base->CTRL &= ~LPUART_CTRL_TIE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + base->CTRL |= LPUART_CTRL_RIE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + base->CTRL &= ~LPUART_CTRL_RIE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the RX register. + * + * This function reads data from the TX register directly. The upper layer must + * ensure that the RX register is full or that the TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ + return base->DATA; +} + +/*! + * @brief Writes to transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room and then writes data to the transmitter buffer. + * + * @note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! +* @brief Reads the RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register full or RX FIFO + * has data then reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, refer to #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Abort the background transfer and uninstall the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, refer to #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c new file mode 100755 index 00000000000..b4242f62625 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c @@ -0,0 +1,334 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpuart_edma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, lpuartPrivateHandle->handle); + + if (lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint32_t instance = LPUART_GetInstance(base); + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kLPUART_RxIdle; + handle->txState = kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); + } +} +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = kLPUART_TxIdle; +} + +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = kLPUART_RxIdle; +} + +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle->rxEdmaHandle); + + if (kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle->txEdmaHandle); + + if (kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h new file mode 100755 index 00000000000..35e922e1251 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPUART_EDMA_H_ +#define _FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief LPUART eDMA handle +*/ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, refer to #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_EDMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c new file mode 100755 index 00000000000..b5c9b88ec6c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pdb.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for PDB module. + * + * @param base PDB peripheral base address + */ +static uint32_t PDB_GetInstance(PDB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PDB bases for each instance. */ +static PDB_Type *const s_pdbBases[] = PDB_BASE_PTRS; +/*! @brief Pointers to PDB clocks for each instance. */ +const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t PDB_GetInstance(PDB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_PDB_COUNT; instance++) + { + if (s_pdbBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_PDB_COUNT); + + return instance; +} + +void PDB_Init(PDB_Type *base, const pdb_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Enable the clock. */ + CLOCK_EnableClock(s_pdbClocks[PDB_GetInstance(base)]); + + /* Configure. */ + /* PDBx_SC. */ + tmp32 = base->SC & + ~(PDB_SC_LDMOD_MASK | PDB_SC_PRESCALER_MASK | PDB_SC_TRGSEL_MASK | PDB_SC_MULT_MASK | PDB_SC_CONT_MASK); + + tmp32 |= PDB_SC_LDMOD(config->loadValueMode) | PDB_SC_PRESCALER(config->prescalerDivider) | + PDB_SC_TRGSEL(config->triggerInputSource) | PDB_SC_MULT(config->dividerMultiplicationFactor); + if (config->enableContinuousMode) + { + tmp32 |= PDB_SC_CONT_MASK; + } + base->SC = tmp32; + + PDB_Enable(base, true); /* Enable the PDB module. */ +} + +void PDB_Deinit(PDB_Type *base) +{ + PDB_Enable(base, false); /* Disable the PDB module. */ + + /* Disable the clock. */ + CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]); +} + +void PDB_GetDefaultConfig(pdb_config_t *config) +{ + assert(NULL != config); + + config->loadValueMode = kPDB_LoadValueImmediately; + config->prescalerDivider = kPDB_PrescalerDivider1; + config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + config->triggerInputSource = kPDB_TriggerSoftware; + config->enableContinuousMode = false; +} + +#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC +void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config) +{ + assert(channel < PDB_INTC_COUNT); + assert(NULL != config); + + uint32_t tmp32 = 0U; + + /* PDBx_DACINTC. */ + if (config->enableExternalTriggerInput) + { + tmp32 |= PDB_INTC_EXT_MASK; + } + if (config->enableIntervalTrigger) + { + tmp32 |= PDB_INTC_TOE_MASK; + } + base->DAC[channel].INTC = tmp32; +} +#endif /* FSL_FEATURE_PDB_HAS_DAC */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h new file mode 100755 index 00000000000..1f05b61b26b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h @@ -0,0 +1,576 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PDB_H_ +#define _FSL_PDB_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pdb + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PDB driver version 2.0.1. */ +#define FSL_PDB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief PDB flags. + */ +enum _pdb_status_flags +{ + kPDB_LoadOKFlag = PDB_SC_LDOK_MASK, /*!< This flag is automatically cleared when the values in buffers are + loaded into the internal registers after the LDOK bit is set or the + PDBEN is cleared. */ + kPDB_DelayEventFlag = PDB_SC_PDBIF_MASK, /*!< PDB timer delay event flag. */ +}; + +/*! + * @brief PDB ADC PreTrigger channel flags. + */ +enum _pdb_adc_pretrigger_flags +{ + /* PDB PreTrigger channel match flags. */ + kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-Trigger 0 flag. */ + kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-Trigger 1 flag. */ +#if (PDB_DLY_COUNT > 2) + kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-Trigger 2 flag. */ + kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-Trigger 3 flag. */ +#endif /* PDB_DLY_COUNT > 2 */ +#if (PDB_DLY_COUNT > 4) + kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-Trigger 4 flag. */ + kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-Trigger 5 flag. */ + kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-Trigger 6 flag. */ + kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-Trigger 7 flag. */ +#endif /* PDB_DLY_COUNT > 4 */ + + /* PDB PreTrigger channel error flags. */ + kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-Trigger 0 Error. */ + kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-Trigger 1 Error. */ +#if (PDB_DLY_COUNT > 2) + kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-Trigger 2 Error. */ + kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-Trigger 3 Error. */ +#endif /* PDB_DLY_COUNT > 2 */ +#if (PDB_DLY_COUNT > 4) + kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-Trigger 4 Error. */ + kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-Trigger 5 Error. */ + kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-Trigger 6 Error. */ + kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-Trigger 7 Error. */ +#endif /* PDB_DLY_COUNT > 4 */ +}; + +/*! + * @brief PDB buffer interrupts. + */ +enum _pdb_interrupt_enable +{ + kPDB_SequenceErrorInterruptEnable = PDB_SC_PDBEIE_MASK, /*!< PDB sequence error interrupt enable. */ + kPDB_DelayInterruptEnable = PDB_SC_PDBIE_MASK, /*!< PDB delay interrupt enable. */ +}; + +/*! + * @brief PDB load value mode. + * + * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]). + * These values are for: + * - PDB counter (PDBx_MOD, PDBx_IDLY) + * - ADC trigger (PDBx_CHnDLYm) + * - DAC trigger (PDBx_DACINTx) + * - CMP trigger (PDBx_POyDLY) + */ +typedef enum _pdb_load_value_mode +{ + kPDB_LoadValueImmediately = 0U, /*!< Load immediately after 1 is written to LDOK. */ + kPDB_LoadValueOnCounterOverflow = 1U, /*!< Load when the PDB counter overflows (reaches the MOD + register value). */ + kPDB_LoadValueOnTriggerInput = 2U, /*!< Load a trigger input event is detected. */ + kPDB_LoadValueOnCounterOverflowOrTriggerInput = 3U, /*!< Load either when the PDB counter overflows or a trigger + input is detected. */ +} pdb_load_value_mode_t; + +/*! + * @brief Prescaler divider. + * + * Counting uses the peripheral clock divided by multiplication factor selected by times of MULT. + */ +typedef enum _pdb_prescaler_divider +{ + kPDB_PrescalerDivider1 = 0U, /*!< Divider x1. */ + kPDB_PrescalerDivider2 = 1U, /*!< Divider x2. */ + kPDB_PrescalerDivider4 = 2U, /*!< Divider x4. */ + kPDB_PrescalerDivider8 = 3U, /*!< Divider x8. */ + kPDB_PrescalerDivider16 = 4U, /*!< Divider x16. */ + kPDB_PrescalerDivider32 = 5U, /*!< Divider x32. */ + kPDB_PrescalerDivider64 = 6U, /*!< Divider x64. */ + kPDB_PrescalerDivider128 = 7U, /*!< Divider x128. */ +} pdb_prescaler_divider_t; + +/*! + * @brief Multiplication factor select for prescaler. + * + * Selects the multiplication factor of the prescaler divider for the counter clock. + */ +typedef enum _pdb_divider_multiplication_factor +{ + kPDB_DividerMultiplicationFactor1 = 0U, /*!< Multiplication factor is 1. */ + kPDB_DividerMultiplicationFactor10 = 1U, /*!< Multiplication factor is 10. */ + kPDB_DividerMultiplicationFactor20 = 2U, /*!< Multiplication factor is 20. */ + kPDB_DividerMultiplicationFactor40 = 3U, /*!< Multiplication factor is 40. */ +} pdb_divider_multiplication_factor_t; + +/*! + * @brief Trigger input source + * + * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or + * the software trigger. Refer to chip configuration details for the actual PDB input trigger connections. + */ +typedef enum _pdb_trigger_input_source +{ + kPDB_TriggerInput0 = 0U, /*!< Trigger-In 0. */ + kPDB_TriggerInput1 = 1U, /*!< Trigger-In 1. */ + kPDB_TriggerInput2 = 2U, /*!< Trigger-In 2. */ + kPDB_TriggerInput3 = 3U, /*!< Trigger-In 3. */ + kPDB_TriggerInput4 = 4U, /*!< Trigger-In 4. */ + kPDB_TriggerInput5 = 5U, /*!< Trigger-In 5. */ + kPDB_TriggerInput6 = 6U, /*!< Trigger-In 6. */ + kPDB_TriggerInput7 = 7U, /*!< Trigger-In 7. */ + kPDB_TriggerInput8 = 8U, /*!< Trigger-In 8. */ + kPDB_TriggerInput9 = 9U, /*!< Trigger-In 9. */ + kPDB_TriggerInput10 = 10U, /*!< Trigger-In 10. */ + kPDB_TriggerInput11 = 11U, /*!< Trigger-In 11. */ + kPDB_TriggerInput12 = 12U, /*!< Trigger-In 12. */ + kPDB_TriggerInput13 = 13U, /*!< Trigger-In 13. */ + kPDB_TriggerInput14 = 14U, /*!< Trigger-In 14. */ + kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15. */ +} pdb_trigger_input_source_t; + +/*! + * @brief PDB module configuration. + */ +typedef struct _pdb_config +{ + pdb_load_value_mode_t loadValueMode; /*!< Select the load value mode. */ + pdb_prescaler_divider_t prescalerDivider; /*!< Select the prescaler divider. */ + pdb_divider_multiplication_factor_t dividerMultiplicationFactor; /*!< Multiplication factor select for prescaler. */ + pdb_trigger_input_source_t triggerInputSource; /*!< Select the trigger input source. */ + bool enableContinuousMode; /*!< Enable the PDB operation in Continuous mode.*/ +} pdb_config_t; + +/*! + * @brief PDB ADC Pre-Trigger configuration. + */ +typedef struct _pdb_adc_pretrigger_config +{ + uint32_t enablePreTriggerMask; /*!< PDB Channel Pre-Trigger Enable. */ + uint32_t enableOutputMask; /*!< PDB Channel Pre-Trigger Output Select. + PDB channel's corresponding pre-trigger asserts when the counter + reaches the channel delay register. */ + uint32_t enableBackToBackOperationMask; /*!< PDB Channel Pre-Trigger Back-to-Back Operation Enable. + Back-to-back operation enables the ADC conversions complete to trigger + the next PDB channel pre-trigger and trigger output, so that the ADC + conversions can be triggered on next set of configuration and results + registers.*/ +} pdb_adc_pretrigger_config_t; + +/*! + * @brief PDB DAC trigger configuration. + */ +typedef struct _pdb_dac_trigger_config +{ + bool enableExternalTriggerInput; /*!< Enables the external trigger for DAC interval counter. */ + bool enableIntervalTrigger; /*!< Enables the DAC interval trigger. */ +} pdb_dac_trigger_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the PDB module. + * + * This function is to make the initialization for PDB module. The operations includes are: + * - Enable the clock for PDB instance. + * - Configure the PDB module. + * - Enable the PDB module. + * + * @param base PDB peripheral base address. + * @param config Pointer to configuration structure. See "pdb_config_t". + */ +void PDB_Init(PDB_Type *base, const pdb_config_t *config); + +/*! + * @brief De-initializes the PDB module. + * + * @param base PDB peripheral base address. + */ +void PDB_Deinit(PDB_Type *base); + +/*! + * @brief Initializes the PDB user configure structure. + * + * This function initializes the user configure structure to default value. the default value are: + * @code + * config->loadValueMode = kPDB_LoadValueImmediately; + * config->prescalerDivider = kPDB_PrescalerDivider1; + * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + * config->triggerInputSource = kPDB_TriggerSoftware; + * config->enableContinuousMode = false; + * @endcode + * @param config Pointer to configuration structure. See "pdb_config_t". + */ +void PDB_GetDefaultConfig(pdb_config_t *config); + +/*! + * @brief Enables the PDB module. + * + * @param base PDB peripheral base address. + * @param enable Enable the module or not. + */ +static inline void PDB_Enable(PDB_Type *base, bool enable) +{ + if (enable) + { + base->SC |= PDB_SC_PDBEN_MASK; + } + else + { + base->SC &= ~PDB_SC_PDBEN_MASK; + } +} + +/* @} */ + +/*! + * @name Basic Counter + * @{ + */ + +/*! + * @brief Triggers the PDB counter by software. + * + * @param base PDB peripheral base address. + */ +static inline void PDB_DoSoftwareTrigger(PDB_Type *base) +{ + base->SC |= PDB_SC_SWTRIG_MASK; +} + +/*! + * @brief Loads the counter values. + * + * This function is to load the counter values from their internal buffer. + * See "pdb_load_value_mode_t" about PDB's load mode. + * + * @param base PDB peripheral base address. + */ +static inline void PDB_DoLoadValues(PDB_Type *base) +{ + base->SC |= PDB_SC_LDOK_MASK; +} + +/*! + * @brief Enables the DMA for the PDB module. + * + * @param base PDB peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PDB_EnableDMA(PDB_Type *base, bool enable) +{ + if (enable) + { + base->SC |= PDB_SC_DMAEN_MASK; + } + else + { + base->SC &= ~PDB_SC_DMAEN_MASK; + } +} + +/*! + * @brief Enables the interrupts for the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". + */ +static inline void PDB_EnableInterrupts(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); + + base->SC |= mask; +} + +/*! + * @brief Disables the interrupts for the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". + */ +static inline void PDB_DisableInterrupts(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); + + base->SC &= ~mask; +} + +/*! + * @brief Gets the status flags of the PDB module. + * + * @param base PDB peripheral base address. + * + * @return Mask value for asserted flags. See "_pdb_status_flags". + */ +static inline uint32_t PDB_GetStatusFlags(PDB_Type *base) +{ + return base->SC & (PDB_SC_PDBIF_MASK | PDB_SC_LDOK_MASK); +} + +/*! + * @brief Clears the status flags of the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value of flags. See "_pdb_status_flags". + */ +static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~PDB_SC_PDBIF_MASK)); + + base->SC &= ~mask; +} + +/*! + * @brief Specifies the period of the counter. + * + * @param base PDB peripheral base address. + * @param value Setting value for the modulus. 16-bit is available. + */ +static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value) +{ + base->MOD = PDB_MOD_MOD(value); +} + +/*! + * @brief Gets the PDB counter's current value. + * + * @param base PDB peripheral base address. + * + * @return PDB counter's current value. + */ +static inline uint32_t PDB_GetCounterValue(PDB_Type *base) +{ + return base->CNT; +} + +/*! + * @brief Sets the value for PDB counter delay event. + * + * @param base PDB peripheral base address. + * @param value Setting value for PDB counter delay event. 16-bit is available. + */ +static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value) +{ + base->IDLY = PDB_IDLY_IDLY(value); +} +/* @} */ + +/*! + * @name ADC Pre-Trigger + * @{ + */ + +/*! + * @brief Configures the ADC PreTrigger in PDB module. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param config Pointer to configuration structure. See "pdb_adc_pretrigger_config_t". + */ +static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config) +{ + assert(channel < PDB_C1_COUNT); + assert(NULL != config); + + base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) | + PDB_C1_EN(config->enableOutputMask); +} + +/*! + * @brief Sets the value for ADC Pre-Trigger delay event. + * + * This function is to set the value for ADC Pre-Trigger delay event. IT Specifies the delay value for the channel's + * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the setting value here. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param preChannel Channel group index for ADC instance. + * @param value Setting value for ADC Pre-Trigger delay event. 16-bit is available. + */ +static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value) +{ + assert(channel < PDB_C1_COUNT); + assert(preChannel < PDB_DLY_COUNT); + + base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value); +} + +/*! + * @brief Gets the ADC Pre-Trigger's status flags. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * + * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags". + */ +static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel) +{ + assert(channel < PDB_C1_COUNT); + + return base->CH[channel].S; +} + +/*! + * @brief Clears the ADC Pre-Trigger's status flags. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags". + */ +static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < PDB_C1_COUNT); + + base->CH[channel].S &= ~mask; +} + +/* @} */ + +#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC +/*! + * @name DAC Interval Trigger + * @{ + */ + +/*! + * @brief Configures the DAC trigger in PDB module. + * + * @param base PDB peripheral base address. + * @param channel Channel index for DAC instance. + * @param config Pointer to configuration structure. See "pdb_dac_trigger_config_t". + */ +void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config); + +/*! + * @brief Sets the value for the DAC interval event. + * + * This fucntion is to set the value for DAC interval event. DAC interval trigger would trigger the DAC module to update + * buffer when the DAC interval counter is equal to the setting value here. + * + * @param base PDB peripheral base address. + * @param channel Channel index for DAC instance. + * @param value Setting value for the DAC interval event. + */ +static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value) +{ + assert(channel < PDB_INT_COUNT); + + base->DAC[channel].INT = PDB_INT_INT(value); +} + +/* @} */ +#endif /* FSL_FEATURE_PDB_HAS_DAC */ + +/*! + * @name Pulse-Out Trigger + * @{ + */ + +/*! + * @brief Enables the pulse out trigger channels. + * + * @param base PDB peripheral base address. + * @param channelMask Channel mask value for multiple pulse out trigger channel. + * @param enable Enable the feature or not. + */ +static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable) +{ + if (enable) + { + base->POEN |= PDB_POEN_POEN(channelMask); + } + else + { + base->POEN &= ~(PDB_POEN_POEN(channelMask)); + } +} + +/*! + * @brief Sets event values for pulse out trigger. + * + * This function is used to set event values for pulse output trigger. + * These pulse output trigger delay values specify the delay for the PDB Pulse-Out. Pulse-Out goes high when the PDB + * counter is equal to the pulse output high value (value1). Pulse-Out goes low when the PDB counter is equal to the + * pulse output low value (value2). + * + * @param base PDB peripheral base address. + * @param channel Channel index for pulse out trigger channel. + * @param value1 Setting value for pulse out high. + * @param value2 Setting value for pulse out low. + */ +static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2) +{ + assert(channel < PDB_PODLY_COUNT); + + base->PODLY[channel] = PDB_PODLY_DLY1(value1) | PDB_PODLY_DLY2(value2); +} + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_PDB_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c new file mode 100755 index 00000000000..1f2fdfe8b45 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pit.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base PIT peripheral base address + * + * @return The PIT instance + */ +static uint32_t PIT_GetInstance(PIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PIT bases for each instance. */ +static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; + +/*! @brief Pointers to PIT clocks for each instance. */ +static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PIT_GetInstance(PIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++) + { + if (s_pitBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_PIT_COUNT); + + return instance; +} + +void PIT_Init(PIT_Type *base, const pit_config_t *config) +{ + assert(config); + + /* Ungate the PIT clock*/ + CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); + + /* Enable PIT timers */ + base->MCR &= ~PIT_MCR_MDIS_MASK; + + /* Config timer operation when in debug mode */ + if (config->enableRunInDebug) + { + base->MCR &= ~PIT_MCR_FRZ_MASK; + } + else + { + base->MCR |= PIT_MCR_FRZ_MASK; + } +} + +void PIT_Deinit(PIT_Type *base) +{ + /* Disable PIT timers */ + base->MCR |= PIT_MCR_MDIS_MASK; + + /* Gate the PIT clock*/ + CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); +} + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) +{ + uint32_t valueH = 0U; + uint32_t valueL = 0U; + + /* LTMR64H should be read before LTMR64L */ + valueH = base->LTMR64H; + valueL = base->LTMR64L; + + return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); +} + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h new file mode 100755 index 00000000000..61606e7e8bd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PIT_H_ +#define _FSL_PIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pit_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of PIT channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pit_chnl +{ + kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ + kPIT_Chnl_1, /*!< PIT channel number 1 */ + kPIT_Chnl_2, /*!< PIT channel number 2 */ + kPIT_Chnl_3, /*!< PIT channel number 3 */ +} pit_chnl_t; + +/*! @brief List of PIT interrupts */ +typedef enum _pit_interrupt_enable +{ + kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ +} pit_interrupt_enable_t; + +/*! @brief List of PIT status flags */ +typedef enum _pit_status_flags +{ + kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ +} pit_status_flags_t; + +/*! + * @brief PIT config structure + * + * This structure holds the configuration settings for the PIT peripheral. To initialize this + * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ +} pit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PIT driver. + * + * @param base PIT peripheral base address + * @param config Pointer to user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config); + +/*! + * @brief Gate the PIT clock and disable the PIT module + * + * @param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base); + +/*! + * @brief Fill in the PIT config struct with the default settings + * + * The default values are: + * @code + * config->enableRunInDebug = false; + * @endcode + * @param config Pointer to user's PIT config structure. + */ +static inline void PIT_GetDefaultConfig(pit_config_t *config) +{ + assert(config); + + /* Timers are stopped in Debug mode */ + config->enableRunInDebug = false; +} + +#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE + +/*! + * @brief Enables or disables chaining a timer with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. Each timer is 32-bits, this allows the developers + * to chain timers together and form a longer timer (64-bits and larger). The first timer + * (timer 0) cannot be chained to any other timer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number which is chained with the previous timer + * @param enable Enable or disable chain. + * true: Current timer is chained with the previous timer. + * false: Timer doesn't chain with other timers. + */ +static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; + } + else + { + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; + } +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL &= ~mask; +} + +/*! + * @brief Gets the enabled PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PIT status flags + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); +} + +/*! + * @brief Clears the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TFLG = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function until it reaches 0, + * then it will generate an interrupt and load this regiter value again. + * Writing a new value to this register will not restart the timer; instead the value + * will be loaded after the timer expires. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + */ +static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) +{ + base->CHANNEL[channel].LDVAL = count; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, count down to 0 and + * then load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops every timer counting. Timers reload their periods + * respectively after the next time they call the PIT_DRV_StartTimer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * @param base PIT peripheral base address + * + * @return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PIT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c new file mode 100755 index 00000000000..82d7b7ace13 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_pmc.h" + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +void PMC_GetParam(PMC_Type *base, pmc_param_t *param) +{ + uint32_t reg = base->PARAM; + ; + param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); + param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) +{ + base->LVDSC1 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) + /* Clear the Low Voltage Detect Flag with previouse power detect setting */ + | PMC_LVDSC1_LVDACK_MASK); +} + +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) +{ + base->LVDSC2 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) + /* Clear the Low Voltage Warning Flag with previouse power detect setting */ + | PMC_LVDSC2_LVWACK_MASK); +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) +{ + base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | + ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) + /* Clear the High Voltage Detect Flag with previouse power detect setting */ + | PMC_HVDSC1_HVDACK_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) +{ + base->REGSC = (0U +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBE */ +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + ); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h new file mode 100755 index 00000000000..c60c19c01e9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PMC_H_ +#define _FSL_PMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmc */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMC driver version */ +#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) +/*! + * @brief Low-Voltage Detect Voltage Select + */ +typedef enum _pmc_low_volt_detect_volt_select +{ + kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/ + kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/ +} pmc_low_volt_detect_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) +/*! + * @brief Low-Voltage Warning Voltage Select + */ +typedef enum _pmc_low_volt_warning_volt_select +{ + kPMC_LowVoltWarningLowTrip = 0U, /*!< Low trip point selected (VLVW = VLVW1)*/ + kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ + kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ + kPMC_LowVoltWarningHighTrip = 3U /*!< High trip point selected (VLVW = VLVW4)*/ +} pmc_low_volt_warning_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-Voltage Detect Voltage Select + */ +typedef enum _pmc_high_volt_detect_volt_select +{ + kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/ + kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/ +} pmc_high_volt_detect_volt_select_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) +/*! + * @brief Bandgap Buffer Drive Select. + */ +typedef enum _pmc_bandgap_buffer_drive_select +{ + kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive. */ + kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */ +} pmc_bandgap_buffer_drive_select_t; +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + +#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) +/*! + * @brief VLPx Option + */ +typedef enum _pmc_vlp_freq_option +{ + kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ + kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ +} pmc_vlp_freq_mode_t; +#endif /* FSL_FEATURE_PMC_HAS_VLPO */ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + @brief IP version ID definition. + */ +typedef struct _pmc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} pmc_version_id_t; +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! @brief IP parameter definition. */ +typedef struct _pmc_param +{ + bool vlpoEnable; /*!< VLPO enable. */ + bool hvdEnable; /*!< HVD enable. */ +} pmc_param_t; +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +/*! + * @brief Low-Voltage Detect Configuration Structure + */ +typedef struct _pmc_low_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when low voltage detect*/ + bool enableReset; /*!< Enable system reset when low voltage detect*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low voltage detect trip point voltage selection*/ +#endif +} pmc_low_volt_detect_config_t; + +/*! + * @brief Low-Voltage Warning Configuration Structure + */ +typedef struct _pmc_low_volt_warning_config +{ + bool enableInt; /*!< Enable interrupt when low voltage warning*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low voltage warning trip point voltage selection*/ +#endif +} pmc_low_volt_warning_config_t; + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-Voltage Detect Configuration Structure + */ +typedef struct _pmc_high_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when high voltage detect*/ + bool enableReset; /*!< Enable system reset when high voltage detect*/ + pmc_high_volt_detect_volt_select_t voltSelect; /*!< High voltage detect trip point voltage selection*/ +} pmc_high_volt_detect_config_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Bandgap Buffer configuration. + */ +typedef struct _pmc_bandgap_buffer_config +{ +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + bool enable; /*!< Enable bandgap buffer. */ +#endif +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + bool enableInLowPowerMode; /*!< Enable bandgap buffer in low power mode. */ +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ +} pmc_bandgap_buffer_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Power Management Controller Control APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + * @brief Gets the PMC version ID. + * + * This function gets the PMC version ID, including major version number, + * minor version number and feature specification number. + * + * @param base PMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * @brief Gets the PMC parameter. + * + * This function gets the PMC parameter, including VLPO enable and HVD enable. + * + * @param base PMC peripheral base address. + * @param param Pointer to PMC param structure. + */ +void PMC_GetParam(PMC_Type *base, pmc_param_t *param); +#endif + +/*! + * @brief Configure the low voltage detect setting. + * + * This function configures the low voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable system reset or not. + * + * @param base PMC peripheral base address. + * @param config Low-Voltage detect configuration structure. + */ +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); + +/*! + * @brief Get Low-Voltage Detect Flag status + * + * This function reads the current LVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current low voltage detect flag + * - true: Low-Voltage detected + * - false: Low-Voltage not detected + */ +static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK); +} + +/*! + * @brief Acknowledge to clear the Low-Voltage Detect flag + * + * This function acknowledges the low voltage detection errors (write 1 to + * clear LVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) +{ + base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; +} + +/*! + * @brief Configure the low voltage warning setting. + * + * This function configures the low voltage warning setting, including the trip + * point voltage setting and enable interrupt or not. + * + * @param base PMC peripheral base address. + * @param config Low-Voltage warning configuration structure. + */ +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); + +/*! + * @brief Get Low-Voltage Warning Flag status + * + * This function polls the current LVWF status. When 1 is returned, it + * indicates a low-voltage warning event. LVWF is set when V Supply transitions + * below the trip point or after reset and V Supply is already below the V LVW. + * + * @param base PMC peripheral base address. + * @return Current LVWF status + * - true: Low-Voltage Warning Flag is set. + * - false: the Low-Voltage Warning does not happen. + */ +static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK); +} + +/*! + * @brief Acknowledge to Low-Voltage Warning flag + * + * This function acknowledges the low voltage warning errors (write 1 to + * clear LVWF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) +{ + base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief Configure the high voltage detect setting. + * + * This function configures the high voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable system reset or not. + * + * @param base PMC peripheral base address. + * @param config High-Voltage detect configuration structure. + */ +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); + +/*! + * @brief Get High-Voltage Detect Flag status + * + * This function reads the current HVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current high voltage detect flag + * - true: High-Voltage detected + * - false: High-Voltage not detected + */ +static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); +} + +/*! + * @brief Acknowledge to clear the High-Voltage Detect flag + * + * This function acknowledges the high voltage detection errors (write 1 to + * clear HVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) +{ + base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Configure the PMC bandgap + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low power mode. + * + * @param base PMC peripheral base address. + * @param config Pointer to the configuration structure + */ +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) +/*! + * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. + * + * This function reads the Acknowledge Isolation setting that indicates + * whether certain peripherals and the I/O pads are in a latched state as + * a result of having been in the VLLS mode. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return ACK isolation + * 0 - Peripherals and I/O pads are in a normal run state. + * 1 - Certain peripherals and I/O pads are in an isolated and + * latched state. + */ +static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK); +} + +/*! + * @brief Acknowledge to Peripherals and I/O pads isolation flag. + * + * This function clears the ACK Isolation flag. Writing one to this setting + * when it is set releases the I/O pads and certain peripherals to their normal + * run mode state. + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) +{ + base->REGSC |= PMC_REGSC_ACKISO_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ + +#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) +/*! + * @brief Gets the Regulator regulation status. + * + * This function returns the regulator to a run regulation status. It provides + * the current status of the internal voltage regulator. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return Regulation status + * 0 - Regulator is in a stop regulation or in transition to/from the regulation. + * 1 - Regulator is in a run regulation. + * + */ +static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_REGONS */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMC_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h new file mode 100755 index 00000000000..790518ccd3c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PORT_H_ +#define _FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! Version 2.0.1. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */ +}; + +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */ +}; + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Internal resistor pull feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */ + kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */ +}; + +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */ +}; + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ + kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */ + kPORT_MuxAlt2 = 2U, /*!< chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< chip-specific */ +} port_mux_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */ +#endif +} port_interrupt_t; + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*! @brief PORT pin config structure */ +typedef struct _port_pin_config +{ + uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */ + uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */ + uint16_t : 1; + uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */ +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */ + uint16_t : 1; + uint16_t mux : 3; /*!< pin mux Configure */ + uint16_t : 4; +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration: + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configure structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration: + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + * @param config PORT PCR register configure structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)config); + + if (mask & 0xffffU) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (mask >> 16) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will + * be reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use in the case you just need to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*@}*/ + +/*! @name Interrupt */ +/*@{*/ + +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} + +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pins' interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PORT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c new file mode 100755 index 00000000000..538f6872a3a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rcm.h" + +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + uint32_t reg; + + reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); + } + base->RPC = reg; +#else + base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + base->RPFW = config->busClockFilterCount; + } +#endif /* FSL_FEATURE_RCM_REG_WIDTH */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) +{ + uint32_t reg; + + reg = base->FM; + reg &= ~RCM_FM_FORCEROM_MASK; + reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); + base->FM = reg; +} +#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h new file mode 100755 index 00000000000..81e25559eaf --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RCM_H_ +#define _FSL_RCM_H_ + +#include "fsl_common.h" + +/*! @addtogroup rcm */ +/*! @{*/ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RCM driver version 2.0.0. */ +#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief System Reset Source Name definitions + */ +typedef enum _rcm_reset_source +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) +/* RCM register bit width is 32. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ + +#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +/* RCM register bit width is 8. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ + kRCM_SourceAll = 0xffffffffU, +} rcm_reset_source_t; + +/*! + * @brief Reset pin filter select in Run and Wait modes + */ +typedef enum _rcm_run_wait_filter_mode +{ + kRCM_FilterDisable = 0U, /*!< All filtering disabled */ + kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ + kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ +} rcm_run_wait_filter_mode_t; + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Boot from ROM configuration. + */ +typedef enum _rcm_boot_rom_config +{ + kRCM_BootFlash = 0U, /*!< Boot from flash */ + kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ + kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ + kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ +} rcm_boot_rom_config_t; +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Max delay time from interrupt asserts to system reset. + */ +typedef enum _rcm_reset_delay +{ + kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ + kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ + kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ + kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ +} rcm_reset_delay_t; + +/*! + * @brief System reset interrupt enable bit definitions. + */ +typedef enum _rcm_interrupt_enable +{ + kRCM_IntNone = 0U, /*!< No interrupt enabled. */ + kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ + kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ + kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ + kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ + kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ + kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ + kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ + kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ +#endif + kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ + | + RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | + RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + | + RCM_SRIE_CORE1_MASK +#endif +} rcm_interrupt_enable_t; +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _rcm_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} rcm_version_id_t; +#endif + +/*! + * @brief Reset pin filter configuration + */ +typedef struct _rcm_reset_pin_filter_config +{ + bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ + rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ + uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ +} rcm_reset_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Reset Control Module APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief Gets the RCM version ID. + * + * This function gets the RCM version ID including the major version number, + * the minor version number, and the feature specification number. + * + * @param base RCM peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif + +#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) +/*! + * @brief Gets the reset source implemented status. + * + * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. + * Use source masks defined in the rcm_reset_source_t to get the desired source status. + * + * Example: + @code + uint32_t status; + + // To test whether the MCU is reset using Watchdog. + status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source implemented status bit map. + */ +static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) +{ + return base->PARAM; +} +#endif /* FSL_FEATURE_RCM_HAS_PARAM */ + +/*! + * @brief Gets the reset source status which caused a previous reset. + * + * This function gets the current reset source status. Use source masks + * defined in the rcm_reset_source_t to get the desired source status. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SRS; +#else + return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) +/*! + * @brief Gets the sticky reset source status. + * + * This function gets the current reset source status that has not been cleared + * by software for some specific source. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SSRS; +#else + return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +/*! + * @brief Clears the sticky reset source status. + * + * This function clears the sticky system reset flags indicated by source masks. + * + * Example: + @code + // Clears multiple reset sources. + RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @param sourceMasks reset source status bit map + */ +static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + base->SSRS = sourceMasks; +#else + base->SSRS0 = (sourceMasks & 0xffU); + base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} +#endif /* FSL_FEATURE_RCM_HAS_SSRS */ + +/*! + * @brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * @param base RCM peripheral base address. + * @param config Pointer to the configuration structure. + */ +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); + +#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) +/*! + * @brief Gets the EZP_MS_B pin assert status. + * + * This function gets the easy port mode status (EZP_MS_B) pin assert status. + * + * @param base RCM peripheral base address. + * @return status true - asserted, false - reasserted + */ +static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) +{ + return (bool)(base->MR & RCM_MR_EZP_MS_MASK); +} +#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Gets the ROM boot source. + * + * This function gets the ROM boot source during the last chip reset. + * + * @param base RCM peripheral base address. + * @return The ROM boot source. + */ +static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) +{ + return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); +} + +/*! + * @brief Clears the ROM boot source flag. + * + * This function clears the ROM boot source flag. + * + * @param base Register base address of RCM + */ +static inline void RCM_ClearBootRomSource(RCM_Type *base) +{ + base->MR |= RCM_MR_BOOTROM_MASK; +} + +/*! + * @brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * @param base RCM peripheral base address. + * @param config Boot configuration. + */ +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Sets the system reset interrupt configuration. + * + * For graceful shutdown, the RCM supports delaying the assertion of the system + * reset for a period of time when the reset interrupt is generated. This function + * can be used to enable the interrupt and the delay period. The interrupts + * are passed in as bit mask. See rcm_int_t for details. For example, to + * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, + * configure as follows: + * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); + * + * @param base RCM peripheral base address. + * @param intMask Bit mask of the system reset interrupts to enable. See + * rcm_interrupt_enable_t for details. + * @param Delay Bit mask of the system reset interrupts to enable. + */ +static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) +{ + base->SRIE = (intMask | delay); +} +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_RCM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c new file mode 100755 index 00000000000..9be27499efd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rnga.h" + +#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/******************************************************************************* + * RNG_CR - RNGA Control Register + ******************************************************************************/ +/*! + * @brief RNG_CR - RNGA Control Register (RW) + * + * Reset value: 0x00000000U + * + * Controls the operation of RNGA. + */ +/*! + * @name Constants and macros for entire RNG_CR register + */ +/*@{*/ +#define RNG_CR_REG(base) ((base)->CR) +#define RNG_RD_CR(base) (RNG_CR_REG(base)) +#define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value)) +#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register RNG_CR, field GO[0] (RW) + * + * Specifies whether random-data generation and loading (into OR[RANDOUT]) is + * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading + * OR[RANDOUT] with data. + * + * Values: + * - 0b0 - Disabled + * - 0b1 - Enabled + */ +/*@{*/ +/*! @brief Read current value of the RNG_CR_GO field. */ +#define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT) + +/*! @brief Set the GO field to a new value. */ +#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value))) +/*@}*/ + +/*! + * @name Register RNG_CR, field SLP[4] (RW) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0b0 - Normal mode + * - 0b1 - Sleep (low-power) mode + */ +/*@{*/ +/*! @brief Read current value of the RNG_CR_SLP field. */ +#define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT) + +/*! @brief Set the SLP field to a new value. */ +#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value))) +/*@}*/ + +/******************************************************************************* + * RNG_SR - RNGA Status Register + ******************************************************************************/ +#define RNG_SR_REG(base) ((base)->SR) + +/*! + * @name Register RNG_SR, field OREG_LVL[15:8] (RO) + * + * Indicates the number of random-data words that are in OR[RANDOUT], which + * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] + * is not 0, then the contents of a random number contained in OR[RANDOUT] are + * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. + * + * Values: + * - 0b00000000 - No words (empty) + * - 0b00000001 - One word (valid) + */ +/*@{*/ +/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ +#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT) +/*@}*/ + +/*! + * @name Register RNG_SR, field SLP[4] (RO) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0b0 - Normal mode + * - 0b1 - Sleep (low-power) mode + */ +/*@{*/ +/*! @brief Read current value of the RNG_SR_SLP field. */ +#define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT) +/*@}*/ + +/******************************************************************************* + * RNG_OR - RNGA Output Register + ******************************************************************************/ +/*! + * @brief RNG_OR - RNGA Output Register (RO) + * + * Reset value: 0x00000000U + * + * Stores a random-data word generated by RNGA. + */ +/*! + * @name Constants and macros for entire RNG_OR register + */ +/*@{*/ +#define RNG_OR_REG(base) ((base)->OR) +#define RNG_RD_OR(base) (RNG_OR_REG(base)) +/*@}*/ + +/******************************************************************************* + * RNG_ER - RNGA Entropy Register + ******************************************************************************/ +/*! + * @brief RNG_ER - RNGA Entropy Register (WORZ) + * + * Reset value: 0x00000000U + * + * Specifies an entropy value that RNGA uses in addition to its ring oscillators + * to seed its pseudorandom algorithm. This is a write-only register; reads + * return all zeros. + */ +/*! + * @name Constants and macros for entire RNG_ER register + */ +/*@{*/ +#define RNG_ER_REG(base) ((base)->ER) +#define RNG_RD_ER(base) (RNG_ER_REG(base)) +#define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value)) +/*@}*/ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ + +static uint32_t rnga_ReadEntropy(RNG_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +void RNGA_Init(RNG_Type *base) +{ + /* Enable the clock gate. */ + CLOCK_EnableClock(kCLOCK_Rnga0); + CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */ + CLOCK_EnableClock(kCLOCK_Rnga0); + + /* Reset the registers for RNGA module to reset state. */ + RNG_WR_CR(base, 0); + /* Enables the RNGA random data generation and loading.*/ + RNG_WR_CR_GO(base, 1); +} + +void RNGA_Deinit(RNG_Type *base) +{ + /* Disable the clock for RNGA module.*/ + CLOCK_DisableClock(kCLOCK_Rnga0); +} + +/*! + * @brief Get a random data from RNGA. + * + * @param base RNGA base address + */ +static uint32_t rnga_ReadEntropy(RNG_Type *base) +{ + uint32_t data = 0; + if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/ + { + /* Wait for valid random-data.*/ + while (RNG_RD_SR_OREG_LVL(base) == 0) + { + } + data = RNG_RD_OR(base); + } + /* Get random-data word generated by RNGA.*/ + return data; +} + +status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size) +{ + status_t result = kStatus_Success; + uint32_t random_32; + uint8_t *random_p; + uint32_t random_size; + uint8_t *data_p = (uint8_t *)data; + uint32_t i; + + /* Check input parameters.*/ + if (base && data && data_size) + { + do + { + /* Read Entropy.*/ + random_32 = rnga_ReadEntropy(base); + + random_p = (uint8_t *)&random_32; + + if (data_size < sizeof(random_32)) + { + random_size = data_size; + } + else + { + random_size = sizeof(random_32); + } + + for (i = 0; i < random_size; i++) + { + *data_p++ = *random_p++; + } + + data_size -= random_size; + } while (data_size > 0); + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode) +{ + RNG_WR_CR_SLP(base, (uint32_t)mode); +} + +rnga_mode_t RNGA_GetMode(RNG_Type *base) +{ + return (rnga_mode_t)RNG_RD_SR_SLP(base); +} + +void RNGA_Seed(RNG_Type *base, uint32_t seed) +{ + /* Write to RNGA Entropy Register.*/ + RNG_WR_ER(base, seed); +} + +#endif /* FSL_FEATURE_SOC_RNG_COUNT */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h new file mode 100755 index 00000000000..04950a4540c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RNGA_DRIVER_H_ +#define _FSL_RNGA_DRIVER_H_ + +#include "fsl_common.h" + +#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT +/*! + * @addtogroup rnga_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RNGA driver version 2.0.1. */ +#define FSL_RNGA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief RNGA working mode */ +typedef enum _rnga_mode +{ + kRNGA_ModeNormal = 0U, /*!< Normal Mode. The ring-oscillator clocks are active; RNGA generates entropy + (randomness) from the clocks and stores it in shift registers.*/ + kRNGA_ModeSleep = 1U, /*!< Sleep Mode. The ring-oscillator clocks are inactive; RNGA does not generate entropy.*/ +} rnga_mode_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RNGA. + * + * This function initializes the RNGA. + * When called, the RNGA entropy generation starts immediately. + * + * @param base RNGA base address + */ +void RNGA_Init(RNG_Type *base); + +/*! + * @brief Shuts down the RNGA. + * + * This function shuts down the RNGA. + * + * @param base RNGA base address + */ +void RNGA_Deinit(RNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the RNGA. + * + * @param base RNGA base address + * @param data pointer to user buffer to be filled by random data + * @param data_size size of data in bytes + * @return RNGA status + */ +status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size); + +/*! + * @brief Feeds the RNGA module. + * + * This function inputs an entropy value that the RNGA uses to seed its + * pseudo-random algorithm. + * + * @param base RNGA base address + * @param seed input seed value + */ +void RNGA_Seed(RNG_Type *base, uint32_t seed); + +/*! + * @brief Sets the RNGA in normal mode or sleep mode. + * + * This function sets the RNGA in sleep mode or normal mode. + * + * @param base RNGA base address + * @param mode normal mode or sleep mode + */ +void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode); + +/*! + * @brief Gets the RNGA working mode. + * + * This function gets the RNGA working mode. + * + * @param base RNGA base address + * @return normal mode or sleep mode + */ +rnga_mode_t RNGA_GetMode(RNG_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_RNG_COUNT */ +#endif /* _FSL_RNGA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c new file mode 100755 index 00000000000..898a544a467 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if (datetime->day > daysPerMonth[datetime->month]) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +void RTC_Init(RTC_Type *base, const rtc_config_t *config) +{ + assert(config); + + uint32_t reg; + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Issue a software reset if timer is invalid */ + if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) + { + RTC_Reset(RTC); + } + + reg = base->CR; + /* Setup the update mode and supervisor access mode */ + reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); + reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); +#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN + /* Setup the wakeup pin select */ + reg &= ~(RTC_CR_WPS_MASK); + reg |= RTC_CR_WPS(config->wakeupSelect); +#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ + base->CR = reg; + + /* Configure the RTC time compensation register */ + base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); +} + +void RTC_GetDefaultConfig(rtc_config_t *config) +{ + assert(config); + + /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ + config->wakeupSelect = false; + /* Registers cannot be written when locked */ + config->updateMode = false; + /* Non-supervisor mode write accesses are not supported and will generate a bus error */ + config->supervisorAccess = false; + /* Compensation interval used by the crystal compensation logic */ + config->compensationInterval = 0; + /* Compensation time used by the crystal compensation logic */ + config->compensationTime = 0; +} + +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->TSR = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = base->TSR; + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = base->TSR; + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->TAR = alarmSeconds; + + return kStatus_Success; +} + +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->TAR; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + /* The alarm flag is cleared by writing to the TAR register */ + if (mask & kRTC_AlarmFlag) + { + base->TAR = 0U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeOverflowFlag) + { + base->TSR = 1U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeInvalidFlag) + { + base->TSR = 1U; + } +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) +{ + *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); +} + +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) +{ + /* Prepare to initialize the register with the new value written */ + base->MER &= ~RTC_MER_MCE_MASK; + + base->MCHR = (uint32_t)((counter) >> 32); + base->MCLR = (uint32_t)(counter); +} + +status_t RTC_IncrementMonotonicCounter(RTC_Type *base) +{ + if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) + { + return kStatus_Fail; + } + + /* Prepare to switch to increment mode */ + base->MER |= RTC_MER_MCE_MASK; + /* Write anything so the counter increments*/ + base->MCLR = 1U; + + return kStatus_Success; +} + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h new file mode 100755 index 00000000000..063d1d40c34 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ + kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ + kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ + kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ + kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ + kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ +} rtc_status_flags_t; + +/*! @brief List of RTC Oscillator capacitor load settings */ +typedef enum _rtc_osc_cap_load +{ + kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2pF capacitor load */ + kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4pF capacitor load */ + kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8pF capacitor load */ + kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */ +} rtc_osc_cap_load_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/*! + * @brief RTC config structure + * + * This structure holds the configuration settings for the RTC peripheral. To initialize this + * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _rtc_config +{ + bool wakeupSelect; /*!< true: Wakeup pin outputs the 32KHz clock; + false:Wakeup pin used to wakeup the chip */ + bool updateMode; /*!< true: Registers can be written even when locked under certain + conditions, false: No writes allowed when registers are locked */ + bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; + false: Non-supervisor accesses are not supported */ + uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ + uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ +} rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the RTC clock and configures the peripheral for basic operation. + * + * This function will issue a software reset if the timer invalid flag is set. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + * @param config Pointer to user's RTC config structure. + */ +void RTC_Init(RTC_Type *base, const rtc_config_t *config); + +/*! + * @brief Stop the timer and gate the RTC clock + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->SR &= ~RTC_SR_TCE_MASK; + + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +/*! + * @brief Fill in the RTC config struct with the default settings + * + * The default values are: + * @code + * config->wakeupSelect = false; + * config->updateMode = false; + * config->supervisorAccess = false; + * config->compensationInterval = 0; + * config->compensationTime = 0; + * @endcode + * @param config Pointer to user's RTC config structure. + */ +void RTC_GetDefaultConfig(rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the RTC status flags + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); +} + +/*! + * @brief Clears the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->SR |= RTC_SR_TCE_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->SR &= ~RTC_SR_TCE_MASK; +} + +/*! @}*/ + +/*! + * @brief This function sets the specified capacitor configuration for the RTC oscillator. + * + * @param base RTC peripheral base address + * @param capLoad Oscillator loads to enable. This is a logical OR of members of the + * enumeration ::rtc_osc_cap_load_t + */ +static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) +{ + uint32_t reg = base->CR; + + reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR + * registers. The SWR bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CR |= RTC_CR_SWR_MASK; + base->CR &= ~RTC_CR_SWR_MASK; + + /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ + base->TSR = 1U; +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +/*! + * @name Monotonic counter functions + * @{ + */ + +/*! + * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns + * them as a single value. + * + * @param base RTC peripheral base address + * @param counter Pointer to variable where the value is stored. + */ +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); + +/*! + * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing + * the given single value. + * + * @param base RTC peripheral base address + * @param counter Counter value + */ +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); + +/*! + * @brief Increments the Monotonic Counter by one. + * + * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting + * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the + * monotonic counter low that causes it to overflow also increments the monotonic counter high. + * + * @param base RTC peripheral base address + * + * @return kStatus_Success: success + * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found + */ +status_t RTC_IncrementMonotonicCounter(RTC_Type *base); + +/*! @}*/ + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c new file mode 100755 index 00000000000..a45e9e62134 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c @@ -0,0 +1,1048 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _sai_transfer_state +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occured. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ +/*!@brief SAI handle pointer */ +sai_handle_t *s_saiHandle[FSL_FEATURE_SOC_I2S_COUNT][2]; +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + uint32_t freq = mclkSrcClock_Hz; + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /*In order to prevent overflow */ + freq /= 100; + mclk_Hz /= 100; + + /* Compute the max fract number */ + max_fract = mclk_Hz * 4096 / freq + 1; + if (max_fract > 256) + { + max_fract = 256; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = freq * fract; + remaind = mul_freq % mclk_Hz; + divide = mul_freq / mclk_Hz; + + /* Find the exactly frequency */ + if (remaind == 0) + { + current_fract = fract; + current_divide = mul_freq / mclk_Hz; + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2) + { + remaind = mclk_Hz - remaind; + divide += 1; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); + + /* Waiting for the divider updated */ + while (base->MCR & I2S_MCR_DUF_MASK) + { + } +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_I2S_COUNT; instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_I2S_COUNT); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * j)); + buffer++; + } + base->TDR[channel] = data; + data = 0; + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = base->RDR[channel]; + for (j = 0; j < bytesPerWord; j++) + { + *buffer = (data >> (8U * j)) & 0xFF; + buffer++; + } + } +} + +void SAI_TxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Configure Master clock output enable */ + base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); + + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + base->TCR4 |= I2S_TCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; + default: + break; + } +} + +void SAI_RxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + + /* Enable SAI clock first. */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Configure Master clock output enable */ + base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); + + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + base->RCR4 |= I2S_RCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; + default: + break; + } +} + +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); + CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +} + +void SAI_TxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusLeftJustified; + config->syncMode = kSAI_ModeAsync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_RxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusLeftJustified; + config->syncMode = kSAI_ModeSync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + else + { + /* Should not close RE even sync with Rx */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } +} + +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } +} + +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = format->sampleRate_Hz * 32U * 2U; + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->TCR2 & I2S_TCR2_BCD_MASK) + { + base->TCR2 &= ~I2S_TCR2_DIV_MASK; + base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + if (format->protocol == kSAI_BusRightJustified) + { + base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(31U); + } + else + { + base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(format->bitWidth - 1); + } + + /* Set mono or stereo */ + base->TMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->TCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = format->sampleRate_Hz * 32U * 2U; + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->RCR2 & I2S_RCR2_BCD_MASK) + { + base->RCR2 &= ~I2S_RCR2_DIV_MASK; + base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + if (format->protocol == kSAI_BusRightJustified) + { + base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(31U); + } + else + { + base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(format->bitWidth - 1); + } + + /* Set mono or stereo */ + base->RMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->RCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size; i++) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size; i++) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + } +} + +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Enable Tx irq */ + EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Enable Rx irq */ + EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->TCSR & I2S_TCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->TCSR & I2S_TCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->TCSR & I2S_TCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->RCSR & I2S_RCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->RCSR & I2S_RCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->RCSR & I2S_RCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +#if defined(FSL_FEATURE_SAI_INT_SOURCE_NUM) && (FSL_FEATURE_SAI_INT_SOURCE_NUM == 1) +void I2S0_DriverIRQHandler(void) +{ + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) + { + SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + } + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) + { + SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + } +} +#else +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0]); + SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); +} + +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1]); + SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); +} +#endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0]); + SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); +} + +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1]); + SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h new file mode 100755 index 00000000000..72b6efd06bc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SAI_H_ +#define _FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +/*@}*/ + +/*! @brief SAI return status*/ +enum _sai_status_t +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode */ + kSAI_Slave = 0x1U /*!< Slave mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoLeft, /*!< Only left channel have sound. */ + kSAI_MonoRight /*!< Only Right channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +} sai_sync_mode_t; + +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief The SAI interrupt enable flag */ +enum _sai_interrupt_enable_t +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The DMA request sources */ +enum _sai_dma_enable_t +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The SAI status flag */ +enum _sai_flags +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configure structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + sai_mclk_source_t mclkSource; /*!< Master Clock source */ + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ + kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + uint8_t channel; /*!< Data channel used in transfer.*/ + sai_protocol_t protocol; /*!< Which audio protocol used */ +} sai_transfer_format_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32bits */ + uint8_t channel; /*!< Transfer channel */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI Tx peripheral. + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configure structure. +*/ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Initializes the the SAI Rx peripheral. + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configure structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Sets the SAI Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * Example: + @code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Sets the SAI Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * Example: + @code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer +*/ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables SAI Tx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables SAI Rx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following source if defined: + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following source if defined: + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. +*/ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. +*/ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for SAI Tx transactional APIs. Call + * this function one time to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback pointer to user callback function + * @param userData user parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for SAI Rx transactional APIs. Call + * this function one time to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback pointer to user callback function + * @param userData user parameter passed to the callback function + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal to masterClockHz in format. + * @return Status of this function. Return value is one of status_t. +*/ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @return Status of this function. Return value is one of status_t. +*/ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle pointer to sai_handle_t structure which stores the transfer state + * @param xfer pointer to sai_transfer_t structure + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle pointer to sai_handle_t structure which stores the transfer state + * @param xfer pointer to sai_transfer_t structure + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the the current IRQ receive. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle pointer to sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle pointer to sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SAI_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c new file mode 100755 index 00000000000..9b1b2f6c490 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai_edma.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + SAI_TransferAbortSendEDMA(privHandle->base, saiHandle); + } +} + +static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; + sai_edma_handle_t *saiHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + SAI_TransferAbortReceiveEDMA(privHandle->base, saiHandle); + } +} + +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; + + /* Update the data channel SAI used */ + handle->channel = format->channel; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; + + /* Update the data channel SAI used */ + handle->channel = format->channel; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h new file mode 100755 index 00000000000..44506fa039d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SAI_EDMA_H_ +#define _FSL_SAI_EDMA_H_ + +#include "fsl_sai.h" +#include "fsl_edma.h" + +/*! + * @addtogroup sai_edma + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef struct _sai_edma_handle sai_edma_handle_t; + +/*! @brief SAI eDMA transfer callback function for finish and error */ +typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ +struct _sai_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs a non-blocking SAI transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Aborts a SAI transfer using eDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI receive using eDMA. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SAI. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param count Bytes count sent by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SAI. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param count Bytes count received by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c new file mode 100755 index 00000000000..3a4b801b7b3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_sim.h" + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) +{ + SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); + + SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; +} +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +void SIM_GetUniqueId(sim_uid_t *uid) +{ +#if defined(SIM_UIDH) + uid->H = SIM->UIDH; +#endif + uid->MH = SIM->UIDMH; + uid->ML = SIM->UIDML; + uid->L = SIM->UIDL; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h new file mode 100755 index 00000000000..a3b69188841 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _FSL_SIM_H_ +#define _FSL_SIM_H_ + +#include "fsl_common.h" + +/*! @addtogroup sim */ +/*! @{*/ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ +/*@}*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*!@brief USB voltage regulator enable setting. */ +enum _sim_usb_volt_reg_enable_mode +{ + kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ + kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ + kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ + kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | + SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ +}; +#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ + +/*!@brief Unique ID. */ +typedef struct _sim_uid +{ +#if defined(SIM_UIDH) + uint32_t H; /*!< UIDH. */ +#endif + uint32_t MH; /*!< UIDMH. */ + uint32_t ML; /*!< UIDML. */ + uint32_t L; /*!< UIDL. */ +} sim_uid_t; + +/*!@brief Flash enable mode. */ +enum _sim_flash_mode +{ + kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ + kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*! + * @brief Sets the USB voltage regulator setting. + * + * This function configures whether the USB voltage regulator is enabled in + * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations + * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable + * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, + * please use: + * + * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); + * + * @param mask USB voltage regulator enable setting. + */ +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +/*! + * @brief Get the unique identification register value. + * + * @param uid Pointer to the structure to save the UID value. + */ +void SIM_GetUniqueId(sim_uid_t *uid); + +/*! + * @brief Set the flash enable mode. + * + * @param mode The mode to set, see \ref _sim_flash_mode for mode details. + */ +static inline void SIM_SetFlashMode(uint8_t mode) +{ + SIM->FCFG1 = mode; +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_SIM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c new file mode 100755 index 00000000000..0018cf7dce2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_smc.h" + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +void SMC_GetParam(SMC_Type *base, smc_param_t *param) +{ + uint32_t reg = base->PARAM; + param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); + param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); + param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); + param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); +} +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +status_t SMC_SetPowerModeRun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure Normal RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +status_t SMC_SetPowerModeHsrun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure High Speed RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +status_t SMC_SetPowerModeWait(SMC_Type *base) +{ + /* configure Normal Wait mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) + /* configure the Partial Stop mode in Noraml Stop mode */ + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_PSTOPO_MASK; + reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); + base->STOPCTRL = reg; +#endif + + /* configure Normal Stop mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter Stop mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +status_t SMC_SetPowerModeVlpr(SMC_Type *base +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + , + bool wakeupMode +#endif + ) +{ + uint8_t reg; + + reg = base->PMCTRL; +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + /* configure whether the system remains in VLP mode on an interrupt */ + if (wakeupMode) + { + /* exits to RUN mode on an interrupt */ + reg |= SMC_PMCTRL_LPWUI_MASK; + } + else + { + /* remains in VLP mode on an interrupt */ + reg &= ~SMC_PMCTRL_LPWUI_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + + /* configure VLPR mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlpw(SMC_Type *base) +{ + /* Power mode transaction to VLPW can only happen in VLPR mode */ + if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base)) + { + return kStatus_Fail; + } + + /* configure VLPW mode */ + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlps(SMC_Type *base) +{ + uint8_t reg; + + /* configure VLPS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter VLPS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeLls(SMC_Type *base +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) + , + const smc_power_mode_lls_config_t *config +#endif + ) +{ + uint8_t reg; + + /* configure to LLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure LLS sub-mode*/ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + if (config->subMode == kSMC_StopSub0) +#endif + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enablePorDetectInVlls0) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; +#endif + } + } +#endif /* FSL_FEATURE_SMC_HAS_PORPO */ + +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + else if (config->subMode == kSMC_StopSub2) + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enableRam2InVlls2) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + } + else + { + } +#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ + + /* configure to VLLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure the VLLS sub-mode */ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + reg = base->VLLSCTRL; + reg &= ~SMC_VLLSCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); + base->VLLSCTRL = reg; +#else +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#else + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ +#endif + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h new file mode 100755 index 00000000000..5149f87e346 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SMC_H_ +#define _FSL_SMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup smc */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMC driver version 2.0.1. */ +#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief Power Modes Protection + */ +typedef enum _smc_power_mode_protection +{ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + kSMC_AllowPowerModeAll = (0U +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_AVLLS_MASK +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_ALLS_MASK +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + | + SMC_PMPROT_AVLP_MASK +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + | + kSMC_AllowPowerModeHsrun +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + ) /*!< Allow all power mode. */ +} smc_power_mode_protection_t; + +/*! + * @brief Power Modes in PMSTAT + */ +typedef enum _smc_power_state +{ + kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ + kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ + kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ + kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ + kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_power_state_t; + +/*! + * @brief Run mode definition + */ +typedef enum _smc_run_mode +{ + kSMC_RunNormal = 0U, /*!< normal RUN mode. */ + kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_run_mode_t; + +/*! + * @brief Stop mode definition + */ +typedef enum _smc_stop_mode +{ + kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ + kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_StopVlls = 4U /*!< Very-Low-Leakage Stop mode. */ +#endif +} smc_stop_mode_t; + +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) +/*! + * @brief VLLS/LLS stop sub mode definition + */ +typedef enum _smc_stop_submode +{ + kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ + kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ + kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ + kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ +} smc_stop_submode_t; +#endif + +/*! + * @brief Partial STOP option + */ +typedef enum _smc_partial_stop_mode +{ + kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ + kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ + kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ +} smc_partial_stop_option_t; + +/*! + * @brief SMC configuration status + */ +enum _smc_status +{ + kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ +}; + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _smc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} smc_version_id_t; +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _smc_param +{ + bool hsrunEnable; /*!< HSRUN mode enable. */ + bool llsEnable; /*!< LLS mode enable. */ + bool lls2Enable; /*!< LLS2 mode enable. */ + bool vlls0Enable; /*!< VLLS0 mode enable. */ +} smc_param_t; +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) +/*! + * @brief SMC Low-Leakage Stop power mode config + */ +typedef struct _smc_power_mode_lls_config +{ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ +#endif +} smc_power_mode_lls_config_t; +#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief SMC Very Low-Leakage Stop power mode config + */ +typedef struct _smc_power_mode_vlls_config +{ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) + bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ +#endif +} smc_power_mode_vlls_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name System mode controller APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief Gets the SMC version ID. + * + * This function gets the SMC version ID, including major version number, + * minor version number and feature specification number. + * + * @param base SMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief Gets the SMC parameter. + * + * This function gets the SMC parameter, including the enabled power mdoes. + * + * @param base SMC peripheral base address. + * @param param Pointer to SMC param structure. + */ +void SMC_GetParam(SMC_Type *base, smc_param_t *param); +#endif + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes in the specified chip family. The available power modes + * are defined in the smc_power_mode_protection_t. This should be done at an early + * system level initialization stage. See the reference manual for details. + * This register can only write once after the power reset. + * + * The allowed modes are passed as bit map, for example, to allow LLS and VLLS, + * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). + * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). + * + * @param base SMC peripheral base address. + * @param allowedModes Bitmap of the allowed power modes. + */ +static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) +{ + base->PMPROT = allowedModes; +} + +/*! + * @brief Gets the current power mode status. + * + * This function returns the current power mode stat. Once application + * switches the power mode, it should always check the stat to check whether it + * runs into the specified mode or not. An application should check + * this mode before switching to a different mode. The system requires that + * only certain modes can switch to other specific modes. See the + * reference manual for details and the smc_power_state_t for information about + * the power stat. + * + * @param base SMC peripheral base address. + * @return Current power mode status. + */ +static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) +{ + return (smc_power_state_t)base->PMSTAT; +} + +/*! + * @brief Configure the system to RUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeRun(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * @brief Configure the system to HSRUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeHsrun(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +/*! + * @brief Configure the system to WAIT power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeWait(SMC_Type *base); + +/*! + * @brief Configure the system to Stop power mode. + * + * @param base SMC peripheral base address. + * @param option Partial Stop mode option. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); + +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) +/*! + * @brief Configure the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); +#else +/*! + * @brief Configure the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + +/*! + * @brief Configure the system to VLPW power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpw(SMC_Type *base); + +/*! + * @brief Configure the system to VLPS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlps(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) +/*! + * @brief Configure the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @param config The LLS power mode configuration structure + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); +#else +/*! + * @brief Configure the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base); +#endif +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief Configure the system to VLLS power mode. + * + * @param base SMC peripheral base address. + * @param config The VLLS power mode configuration structure. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_SMC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c new file mode 100755 index 00000000000..b0b92399db4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c @@ -0,0 +1,1032 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy /* RX busy. */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ +static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS; +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; + +/* UART ISR for transactional APIs. */ +static uart_isr_t s_uartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + + assert(instance < uartArrayCount); + + return instance; +} + +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + uint16_t sbr; + uint8_t temp; + + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (config->baudRate_Bps * 16); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr; + + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + + if (kUART_ParityDisabled != config->parityMode) + { + temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode); + } + + base->C1 = temp; + +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Set tx/rx FIFO watermark */ + base->TWFIFO = config->txFifoWatermark; + base->RWFIFO = config->rxFifoWatermark; + + /* Enable tx/rx FIFO */ + base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK); + + /* Flush FIFO */ + base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); +#endif + + /* Enable TX/RX base on configure structure. */ + temp = base->C2; + + if (config->enableTx) + { + temp |= UART_C2_TE_MASK; + } + + if (config->enableRx) + { + temp |= UART_C2_RE_MASK; + } + + base->C2 = temp; +} + +void UART_Deinit(UART_Type *base) +{ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != base->TCFIFO) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->S1 & UART_S1_TC_MASK)) + { + } + + /* Disable the module. */ + base->C2 = 0; + + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +} + +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 1; +#endif + config->enableTx = false; + config->enableRx = false; +} + +void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t sbr; + uint8_t oldCtrl; + + /* Store C2 before disable Tx and Rx */ + oldCtrl = base->C2; + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (baudRate_Bps * 16); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr; + + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Restore C2. */ + base->C2 = oldCtrl; +} + +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH |= (mask & 0xFF); + base->C2 |= ((mask >> 8) & 0xFF); + base->C3 |= ((mask >> 16) & 0xFF); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO |= ((mask >> 24) & 0xFF); +#endif +} + +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH &= ~(mask & 0xFF); + base->C2 &= ~((mask >> 8) & 0xFF); + base->C3 &= ~((mask >> 16) & 0xFF); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO &= ~((mask >> 24) & 0xFF); +#endif +} + +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + uint32_t temp; + + temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + temp |= ((uint32_t)(base->CFIFO) << 24); +#endif + + return temp; +} + +uint32_t UART_GetStatusFlags(UART_Type *base) +{ + uint32_t status_flag; + + status_flag = base->S1 | ((uint32_t)(base->S2) << 8); + +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + status_flag |= ((uint32_t)(base->ED) << 16); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + status_flag |= ((uint32_t)(base->SFIFO) << 24); +#endif + + return status_flag; +} + +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) +{ + uint8_t reg = base->S2; + status_t status; + +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK); +#else + reg &= ~UART_S2_RXEDGIF_MASK; +#endif + + base->S2 = reg | (uint8_t)(mask >> 8); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->SFIFO = (uint8_t)(mask >> 24); +#endif + + if (mask & (kUART_IdleLineFlag | kUART_RxOverrunFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | + kUART_ParityErrorFlag)) + { + /* Read base->D to clear the flags. */ + (void)base->S1; + (void)base->D; + } + + /* If some flags still pending. */ + if (mask & UART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag, + kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, + kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */ + status = kStatus_UART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->S1 & UART_S1_TDRE_MASK)) + { + } + base->D = *(data++); + } +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->D = data[i]; + } +} + +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + + while (length--) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + while (!base->RCFIFO) +#else + while (!(base->S1 & UART_S1_RDRF_MASK)) +#endif + { + statusFlag = UART_GetStatusFlags(base); + + if (statusFlag & kUART_RxOverrunFlag) + { + return kStatus_UART_RxHardwareOverrun; + } + + if (statusFlag & kUART_NoiseErrorFlag) + { + return kStatus_UART_NoiseError; + } + + if (statusFlag & kUART_FramingErrorFlag) + { + return kStatus_UART_FramingError; + } + + if (statusFlag & kUART_ParityErrorFlag) + { + return kStatus_UART_ParityError; + } + } + *(data++) = base->D; + } + + return kStatus_Success; +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = base->D; + } +} + +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->RWFIFO = 1U; +#endif + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_uartIRQ[instance]); +} + +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ringbuffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } +} + +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kUART_RxIdle) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kUART_TxIdle; +} + +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + } + + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + + /* Enable RX interrupt. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + + assert(handle); + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->D; + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = base->RCFIFO; +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->D; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO; +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->C2 = (base->C2 & ~UART_C2_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } + } + } +} + +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) +{ + /* TODO: To be implemented. */ +} + +#if defined(UART0) +#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \ + ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0))) +void UART0_DriverIRQHandler(void) +{ + s_uartIsr(UART0, s_uartHandle[0]); +} + +void UART0_RX_TX_DriverIRQHandler(void) +{ + UART0_DriverIRQHandler(); +} +#endif +#endif + +#if defined(UART1) +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[1]); +} + +void UART1_RX_TX_DriverIRQHandler(void) +{ + UART1_DriverIRQHandler(); +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[2]); +} + +void UART2_RX_TX_DriverIRQHandler(void) +{ + UART2_DriverIRQHandler(); +} + +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[3]); +} + +void UART3_RX_TX_DriverIRQHandler(void) +{ + UART3_DriverIRQHandler(); +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[4]); +} + +void UART4_RX_TX_DriverIRQHandler(void) +{ + UART4_DriverIRQHandler(); +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[5]); +} + +void UART5_RX_TX_DriverIRQHandler(void) +{ + UART5_DriverIRQHandler(); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h new file mode 100755 index 00000000000..3eec4e66b58 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h @@ -0,0 +1,757 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version 2.1.0. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _uart_status +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ +}; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0U, /*!< One stop bit */ + kUART_TwoStopBit = 1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! + * @brief UART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the UART interrupt configurations. + */ +enum _uart_interrupt_enable +{ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */ +#endif + kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */ + kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */ + kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */ + kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */ + kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */ + kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */ + kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */ + kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */ + kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */ + kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ + kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ +#endif +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum _uart_flags +{ + kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */ + kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */ + kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */ + kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */ + kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */ + kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit. + If any of these samples differ, noise flag sets */ + kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected + where stop bit expected */ + kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakFlag = + (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when + LIN break char detected and LIN circuit enabled */ +#endif + kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag, + sets when active edge detected */ + kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), + sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ + kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ + kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ + kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ + kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ + kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ +#endif +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate */ + uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with user configuration structure and peripheral clock. + * + * This function configures the UART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the UART_GetDefaultConfig() function. + * Example below shows how to use this API to configure UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 0; + * uartConfig.rxFifoWatermark = 1; + * UART_Init(UART1, &uartConfig, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + */ +void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->bitCountPerChar = kUART_8BitsPerChar; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 0; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source freqency in HZ. + */ +void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get UART status flags. + * + * This function get all UART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _uart_flags. To check specific status, + * compare the return value with enumerators in @ref _uart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART status flags which are ORed by the enumerators in the _uart_flags. + */ +uint32_t UART_GetStatusFlags(UART_Type *base); + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears UART status flags with a provided mask. Automatically cleared flag + * can't be cleared by this function. + * Some flags can only be cleared or set by hardware itself. These flags are: + * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, + * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, + * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base UART peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags. + * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX full interrupt: + * @code + * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * specific interrupts enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the UART data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base UART peripheral base address. + * @return UART data register address which are used both by transmitter and receiver. + */ +static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base) +{ + return (uint32_t) & (base->D); +} + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_TDMAS_MASK; +#else + base->C5 |= UART_C5_TDMAS_MASK; +#endif + base->C2 |= UART_C2_TIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_TDMAS_MASK; +#else + base->C5 &= ~UART_C5_TDMAS_MASK; +#endif + base->C2 &= ~UART_C2_TIE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA. + * + * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_RDMAS_MASK; +#else + base->C5 |= UART_C5_RDMAS_MASK; +#endif + base->C2 |= UART_C2_RIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_RDMAS_MASK; +#else + base->C5 &= ~UART_C5_RDMAS_MASK; +#endif + base->C2 &= ~UART_C2_RIE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_TE_MASK; + } + else + { + base->C2 &= ~UART_C2_TE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_RE_MASK; + } + else + { + base->C2 &= ~UART_C2_RE_MASK; + } +} + +/*! + * @brief Writes to the TX register. + * + * This function writes data to the TX register directly. The upper layer must ensure + * that the TX register is empty or TX FIFO has empty room before calling this function. + * + * @param base UART peripheral base address. + * @param data The byte to write. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->D = data; +} + +/*! + * @brief Reads the RX register directly. + * + * This function reads data from the TX register directly. The upper layer must + * ensure that the RX register is full or that the TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return The byte read from UART data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return base->D; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note This function does not check whether all the data has been sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_UART_NoiseError Noise error happened while receiving data. + * @retval kStatus_UART_FramingError Framing error happened while receiving data. + * @retval kStatus_UART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, refer to #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief UART Error IRQ handle function. + * + * This function handle the UART error IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c new file mode 100755 index 00000000000..36734044860 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart_edma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ + +/*base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle, + uartPrivateHandle->handle->userData); + } + } +} + +static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle, + uartPrivateHandle->handle->userData); + } + } +} + +void UART_TransferCreateHandleEDMA(UART_Type *base, + uart_edma_handle_t *handle, + uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint32_t instance = UART_GetInstance(base); + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (rxEdmaHandle) + { + base->RWFIFO = 1U; + } +#endif + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, UART_SendEDMACallback, &s_edmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, UART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); + } +} + +status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txState = kUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base), + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + handle->rxState = kUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle); + + /* Disable UART TX EDMA. */ + UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = kUART_TxIdle; +} + +void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle); + + /* Disable UART RX EDMA. */ + UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle->rxEdmaHandle); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle->txEdmaHandle); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h new file mode 100755 index 00000000000..52cc7373a9f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_EDMA_H_ +#define _FSL_UART_EDMA_H_ + +#include "fsl_uart.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup uart_edma_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_edma_handle uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_edma_transfer_callback_t)(UART_Type *base, + uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART eDMA handle +*/ +struct _uart_edma_handle +{ + uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + * @param callback UART callback, NULL means no callback. + * @param userData User callback function data. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + */ +void UART_TransferCreateHandleEDMA(UART_Type *base, + uart_edma_handle_t *handle, + uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Receive data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + * @param xfer UART eDMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts sent data using eDMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + */ +void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data using eDMA. + * + * This function aborts receive data using eDMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_edma_handle_t structure. + */ +void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by DMA. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_EDMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c new file mode 100755 index 00000000000..0854ca07577 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_vref.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base VREF peripheral base address + * + * @return The VREF instance + */ +static uint32_t VREF_GetInstance(VREF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to VREF bases for each instance. */ +static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; + +/*! @brief Pointers to VREF clocks for each instance. */ +static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t VREF_GetInstance(VREF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++) + { + if (s_vrefBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_VREF_COUNT); + + return instance; +} + +void VREF_Init(VREF_Type *base, const vref_config_t *config) +{ + assert(config != NULL); + + uint8_t reg = 0U; + + /* Ungate clock for VREF */ + CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); + +/* Configure VREF to a known state */ +#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC + /* Set chop oscillator bit */ + base->TRM |= VREF_TRM_CHOPEN_MASK; +#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ + reg = base->SC; + /* Set buffer Mode selection and Regulator enable bit */ + reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U); +#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION + /* Set second order curvature compensation enable bit */ + reg |= VREF_SC_ICOMPEN(1U); +#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ + /* Enable VREF module */ + reg |= VREF_SC_VREFEN(1U); + /* Update bit-field from value to Status and Control register */ + base->SC = reg; +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + reg = base->VREFL_TRM; + /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/ + reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK); + /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */ + reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef); + base->VREFL_TRM = reg; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} + +void VREF_Deinit(VREF_Type *base) +{ + /* Gate clock for VREF */ + CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); +} + +void VREF_GetDefaultConfig(vref_config_t *config) +{ +/* Set High power buffer mode in */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + config->bufferMode = kVREF_ModeHighPowerBuffer; +#else + config->bufferMode = kVREF_ModeTightRegulationBuffer; +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + /* Select internal voltage reference */ + config->enableExternalVoltRef = false; + /* Set VREFL (0.4 V) reference buffer disable */ + config->enableLowRef = false; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +} + +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) +{ + uint8_t reg = 0U; + + /* Set TRIM bits value in voltage reference */ + reg = base->TRM; + reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue)); + base->TRM = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) +{ + /* The values 111b and 110b are NOT valid/allowed */ + assert((trimValue != 0x7U) && (trimValue != 0x6U)); + + uint8_t reg = 0U; + + /* Set TRIM bits value in low voltage reference */ + reg = base->VREFL_TRM; + reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue)); + base->VREFL_TRM = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h new file mode 100755 index 00000000000..79378863bb6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_VREF_H_ +#define _FSL_VREF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup vref + * @{ + */ + +/*! @file */ + +/****************************************************************************** + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/* Those macros below defined to support SoC family which have VREFL (0.4V) reference */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +#define SC VREFH_SC +#define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV +#define VREF_SC_REGEN VREF_VREFH_SC_REGEN +#define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN +#define VREF_SC_ICOMPEN VREF_VREFH_SC_ICOMPEN +#define VREF_SC_REGEN_MASK VREF_VREFH_SC_REGEN_MASK +#define VREF_SC_VREFST_MASK VREF_VREFH_SC_VREFST_MASK +#define VREF_SC_VREFEN_MASK VREF_VREFH_SC_VREFEN_MASK +#define VREF_SC_MODE_LV_MASK VREF_VREFH_SC_MODE_LV_MASK +#define VREF_SC_ICOMPEN_MASK VREF_VREFH_SC_ICOMPEN_MASK +#define TRM VREFH_TRM +#define VREF_TRM_TRIM VREF_VREFH_TRM_TRIM +#define VREF_TRM_CHOPEN_MASK VREF_VREFH_TRM_CHOPEN_MASK +#define VREF_TRM_TRIM_MASK VREF_VREFH_TRM_TRIM_MASK +#define VREF_TRM_CHOPEN_SHIFT VREF_VREFH_TRM_CHOPEN_SHIFT +#define VREF_TRM_TRIM_SHIFT VREF_VREFH_TRM_TRIM_SHIFT +#define VREF_SC_MODE_LV_SHIFT VREF_VREFH_SC_MODE_LV_SHIFT +#define VREF_SC_REGEN_SHIFT VREF_VREFH_SC_REGEN_SHIFT +#define VREF_SC_VREFST_SHIFT VREF_VREFH_SC_VREFST_SHIFT +#define VREF_SC_ICOMPEN_SHIFT VREF_VREFH_SC_ICOMPEN_SHIFT +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*! + * @brief VREF modes. + */ +typedef enum _vref_buffer_mode +{ + kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + kVREF_ModeHighPowerBuffer = 1U, /*!< High power buffer mode enabled */ + kVREF_ModeLowPowerBuffer = 2U /*!< Low power buffer mode enabled */ +#else + kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */ +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ +} vref_buffer_mode_t; + +/*! + * @brief The description structure for the VREF module. + */ +typedef struct _vref_config +{ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + bool enableLowRef; /*!< Set VREFL (0.4 V) reference buffer enable or disable */ + bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +} vref_config_t; + +/****************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name VREF functional operation + * @{ + */ + +/*! + * @brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all the other VREF driver functions, + * read/write registers, and configurations with user-defined settings. + * The example below shows how to set up vref_config_t parameters and + * how to call the VREF_Init function by passing in these parameters: + * Example: + * @code + * vref_config_t vrefConfig; + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig.enableExternalVoltRef = false; + * vrefConfig.enableLowRef = false; + * VREF_Init(VREF, &vrefConfig); + * @endcode + * + * @param base VREF peripheral address. + * @param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config); + +/*! + * @brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * Example: + * @code + * vref_config_t vrefUserConfig; + * VREF_Init(VREF); + * VREF_GetDefaultConfig(&vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * @endcode + * + * @param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base); + +/*! + * @brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to a default value. + * Example: + * @code + * vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig->enableExternalVoltRef = false; + * vrefConfig->enableLowRef = false; + * @endcode + * + * @param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config); + +/*! + * @brief Sets a TRIM value for reference voltage. + * + * This function sets a TRIM value for reference voltage. + * Note that the TRIM value maximum is 0x3F. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the TRM register. + * + * @param base VREF peripheral address. + * @return Six-bit value of trim setting. + */ +static inline uint8_t VREF_GetTrimVal(VREF_Type *base) +{ + return (base->TRM & VREF_TRM_TRIM_MASK); +} +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + +/*! + * @brief Sets the TRIM value for low voltage reference. + * + * This function sets the TRIM value for low reference voltage. + * NOTE: + * - The TRIM value maximum is 0x05U + * - The values 111b and 110b are not valid/allowed. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)). + */ +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the VREFL_TRM register. + * + * @param base VREF peripheral address. + * @return Three-bit value of the trim setting. + */ +static inline uint8_t VREF_GetLowReferenceTrimVal(VREF_Type *base) +{ + return (base->VREFL_TRM & VREF_VREFL_TRM_VREFL_TRIM_MASK); +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_VREF_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c new file mode 100755 index 00000000000..489798ca889 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wdog.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + config->enableWdog = true; + config->clockSource = kWDOG_LpoClockSource; + config->prescaler = kWDOG_ClockPrescalerDivide1; +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + config->workMode.enableWait = true; +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableUpdate = true; + config->enableInterrupt = false; + config->enableWindowMode = false; + config->windowValue = 0U; + config->timeoutValue = 0xFFFFU; +} + +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = WDOG_STCTRLH_WDOGEN(config->enableWdog) | WDOG_STCTRLH_CLKSRC(config->clockSource) | + WDOG_STCTRLH_IRQRSTEN(config->enableInterrupt) | WDOG_STCTRLH_WINEN(config->enableWindowMode) | + WDOG_STCTRLH_ALLOWUPDATE(config->enableUpdate) | WDOG_STCTRLH_DBGEN(config->workMode.enableDebug) | + WDOG_STCTRLH_STOPEN(config->workMode.enableStop) | +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + WDOG_STCTRLH_WAITEN(config->workMode.enableWait) | +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + WDOG_STCTRLH_DISTESTWDOG(1U); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + /* Set configruation */ + base->PRESC = WDOG_PRESC_PRESCVAL(config->prescaler); + base->WINH = (uint16_t)((config->windowValue >> 16U) & 0xFFFFU); + base->WINL = (uint16_t)((config->windowValue) & 0xFFFFU); + base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); + base->STCTRLH = value; + EnableGlobalIRQ(primaskValue); +} + +void WDOG_Deinit(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupts */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + WDOG_Disable(base); + EnableGlobalIRQ(primaskValue); + WDOG_ClearResetCount(base); +} + +void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = WDOG_STCTRLH_DISTESTWDOG(0U) | WDOG_STCTRLH_TESTWDOG(1U) | WDOG_STCTRLH_TESTSEL(config->testMode) | + WDOG_STCTRLH_BYTESEL(config->testedByte) | WDOG_STCTRLH_IRQRSTEN(0U) | WDOG_STCTRLH_WDOGEN(1U) | + WDOG_STCTRLH_ALLOWUPDATE(1U); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + /* Set configruation */ + base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); + base->STCTRLH = value; + EnableGlobalIRQ(primaskValue); +} + +uint32_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint32_t status_flag = 0U; + + status_flag |= (base->STCTRLH & WDOG_STCTRLH_WDOGEN_MASK); + status_flag |= (base->STCTRLL & WDOG_STCTRLL_INTFLG_MASK); + + return status_flag; +} + +void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask) +{ + if (mask & kWDOG_TimeoutFlag) + { + base->STCTRLL |= WDOG_STCTRLL_INTFLG_MASK; + } +} + +void WDOG_Refresh(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->REFRESH = WDOG_FIRST_WORD_OF_REFRESH; + base->REFRESH = WDOG_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h new file mode 100755 index 00000000000..949a9a8e046 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version 2.0.0. */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Unlock sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_UNLOCK (0xC520U) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK (0xD928U) /*!< Second word of unlock sequence */ +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_REFRESH (0xA602U) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH (0xB480U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WDOG clock source. */ +typedef enum _wdog_clock_source +{ + kWDOG_LpoClockSource = 0U, /*!< WDOG clock sourced from LPO*/ + kWDOG_AlternateClockSource = 1U, /*!< WDOG clock sourced from alternate clock source*/ +} wdog_clock_source_t; + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + bool enableWait; /*!< Enables or disables WDOG in wait mode */ +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + bool enableStop; /*!< Enables or disables WDOG in stop mode */ + bool enableDebug; /*!< Enables or disables WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes the selection of the clock prescaler. */ +typedef enum _wdog_clock_prescaler +{ + kWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kWDOG_ClockPrescalerDivide2 = 0x1U, /*!< Divided by 2 */ + kWDOG_ClockPrescalerDivide3 = 0x2U, /*!< Divided by 3 */ + kWDOG_ClockPrescalerDivide4 = 0x3U, /*!< Divided by 4 */ + kWDOG_ClockPrescalerDivide5 = 0x4U, /*!< Divided by 5 */ + kWDOG_ClockPrescalerDivide6 = 0x5U, /*!< Divided by 6 */ + kWDOG_ClockPrescalerDivide7 = 0x6U, /*!< Divided by 7 */ + kWDOG_ClockPrescalerDivide8 = 0x7U, /*!< Divided by 8 */ +} wdog_clock_prescaler_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_clock_source_t clockSource; /*!< Clock source select */ + wdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableUpdate; /*!< Update write-once register enable */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + bool enableWindowMode; /*!< Enables or disables WDOG window mode */ + uint32_t windowValue; /*!< Window value */ + uint32_t timeoutValue; /*!< Timeout value */ +} wdog_config_t; + +/*! @brief Describes WDOG test mode. */ +typedef enum _wdog_test_mode +{ + kWDOG_QuickTest = 0U, /*!< Selects quick test */ + kWDOG_ByteTest = 1U, /*!< Selects byte test */ +} wdog_test_mode_t; + +/*! @brief Describes WDOG tested byte selection in byte test mode. */ +typedef enum _wdog_tested_byte +{ + kWDOG_TestByte0 = 0U, /*!< Byte 0 selected in byte test mode */ + kWDOG_TestByte1 = 1U, /*!< Byte 1 selected in byte test mode */ + kWDOG_TestByte2 = 2U, /*!< Byte 2 selected in byte test mode */ + kWDOG_TestByte3 = 3U, /*!< Byte 3 selected in byte test mode */ +} wdog_tested_byte_t; + +/*! @brief Describes WDOG test mode configuration structure. */ +typedef struct _wdog_test_config +{ + wdog_test_mode_t testMode; /*!< Selects test mode */ + wdog_tested_byte_t testedByte; /*!< Selects tested byte in byte test mode */ + uint32_t timeoutValue; /*!< Timeout value */ +} wdog_test_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable_t +{ + kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout will generate interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags_t +{ + kWDOG_RunningFlag = WDOG_STCTRLH_WDOGEN_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_TimeoutFlag = WDOG_STCTRLL_INTFLG_MASK, /*!< Interrupt flag, set when an exception occurs*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WDOG configure sturcture. + * + * This function initializes the WDOG configure structure to default value. The default + * value are: + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->clockSource = kWDOG_LpoClockSource; + * wdogConfig->prescaler = kWDOG_ClockPrescalerDivide1; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableUpdate = true; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enableWindowMode = false; + * wdogConfig->windowValue = 0; + * wdogConfig->timeoutValue = 0xFFFFU; + * @endcode + * + * @param config Pointer to WDOG config structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * If user wants to reconfigure WDOG without forcing a reset first, enableUpdate must be set to true + * in configuration. + * + * Example: + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Configures WDOG functional test. + * + * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode + * and runs according to the configuration. + * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + * + * Example: + * @code + * wdog_test_config_t test_config; + * test_config.testMode = kWDOG_QuickTest; + * test_config.timeoutValue = 0xfffffu; + * WDOG_SetTestModeConfig(wdog_base, &test_config); + * @endcode + * @param base WDOG peripheral base address + * @param config The functional test configuration of WDOG + */ +void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config); + +/* @} */ + +/*! + * @name WDOG Functional Operation + * @{ + */ + +/*! + * @brief Enables the WDOG module. + * + * This function write value into WDOG_STCTRLH register to enable the WDOG, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->STCTRLH |= WDOG_STCTRLH_WDOGEN_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function write value into WDOG_STCTRLH register to disable the WDOG, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; +} + +/*! + * @brief Enable WDOG interrupt. + * + * This function write value into WDOG_STCTRLH register to enable WDOG interrupt, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined: + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->STCTRLH |= mask; +} + +/*! + * @brief Disable WDOG interrupt. + * + * This function write value into WDOG_STCTRLH register to disable WDOG interrupt, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined: + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->STCTRLH &= ~mask; +} + +/*! + * @brief Gets WDOG all status flags. + * + * This function gets all status flags. + * + * Example for getting Running Flag: + * @code + * uint32_t status; + * status = WDOG_GetStatusFlags(wdog_base) & kWDOG_RunningFlag; + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +uint32_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clear WDOG flag. + * + * This function clears WDOG status flag. + * + * Example for clearing timeout(interrupt) flag: + * @code + * WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values: + * kWDOG_TimeoutFlag + */ +void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask); + +/*! + * @brief Set the WDOG timeout value. + * + * This function sets the timeout value. + * It should be ensured that the time-out value for the WDOG is always greater than + * 2xWCT time + 20 bus clock cycles. + * This function write value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once. + * Make sure the WCT window is still open and these two registers have not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value, count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount) +{ + base->TOVALH = (uint16_t)((timeoutCount >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((timeoutCount)&0xFFFFU); +} + +/*! + * @brief Sets the WDOG window value. + * + * This function sets the WDOG window value. + * This function write value into WDOG_WINH and WDOG_WINL registers which are wirte-once. + * Make sure the WCT window is still open and these two registers have not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + * @param windowValue WDOG window value. + */ +static inline void WDOG_SetWindowValue(WDOG_Type *base, uint32_t windowValue) +{ + base->WINH = (uint16_t)((windowValue >> 16U) & 0xFFFFU); + base->WINL = (uint16_t)((windowValue)&0xFFFFU); +} + +/*! + * @brief Unlocks the WDOG register written. + * + * This function unlocks the WDOG register written. + * Before starting the unlock sequence and following congfiguration, disable the global interrupts. + * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire, + * After the configuration finishes, re-enable the global interrupts. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Unlock(WDOG_Type *base) +{ + base->UNLOCK = WDOG_FIRST_WORD_OF_UNLOCK; + base->UNLOCK = WDOG_SECOND_WORD_OF_UNLOCK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); + +/*! + * @brief Gets the WDOG reset count. + * + * This function gets the WDOG reset count value. + * + * @param base WDOG peripheral base address + * @return WDOG reset count value + */ +static inline uint16_t WDOG_GetResetCount(WDOG_Type *base) +{ + return base->RSTCNT; +} +/*! + * @brief Clears the WDOG reset count. + * + * This function clears the WDOG reset count value. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_ClearResetCount(WDOG_Type *base) +{ + base->RSTCNT |= UINT16_MAX; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h new file mode 100755 index 00000000000..ba26b7b802d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PERIPHERAL_CLOCK_H_ +#define _FSL_PERIPHERAL_CLOCK_H_ + +#include "fsl_clock.h" + +/* Array for UART module clocks */ +#define UART_CLOCK_FREQS \ + { \ + UART0_CLK_SRC, UART1_CLK_SRC, UART2_CLK_SRC \ + } + +/* Array for I2C module clocks */ +#define I2C_CLOCK_FREQS \ + { \ + I2C0_CLK_SRC, I2C1_CLK_SRC \ + } + +/* Array for DSPI module clocks */ +#define SPI_CLOCK_FREQS \ + { \ + DSPI0_CLK_SRC, DSPI1_CLK_SRC \ + } + +#endif /* _FSL_PERIPHERAL_CLOCK_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/serial_api.c new file mode 100644 index 00000000000..21c4ab20caa --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/serial_api.c @@ -0,0 +1,257 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_uart.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" +#include "fsl_clock_config.h" + +static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; +static uart_irq_handler irq_handler; +/* Array of UART peripheral base address. */ +static UART_Type *const uart_addrs[] = UART_BASE_PTRS; +/* Array of UART bus clock frequencies */ +static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS; + + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + + // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init + if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) + BOARD_BootClockRUN(); + + uart_config_t config; + + UART_GetDefaultConfig(&config); + config.baudRate_Bps = 9600; + config.enableTx = false; + config.enableRx = false; + + UART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + UART_EnableTx(uart_addrs[obj->index], true); + pin_mode(tx, PullUp); + } + if (rx != NC) { + UART_EnableRx(uart_addrs[obj->index], true); + pin_mode(rx, PullUp); + } + + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + UART_Deinit(uart_addrs[obj->index]); + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) { + UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index])); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + UART_Type *base = uart_addrs[obj->index]; + uint8_t temp; + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + if (parity != ParityNone) + { + /* Enable Parity */ + temp |= (UART_C1_PE_MASK | UART_C1_M_MASK); + if (parity == ParityOdd) { + temp |= UART_C1_PT_MASK; + } else { + // Hardware does not support forced parity + MBED_ASSERT(0); + } + } + base->C1 = temp; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)--stop_bits); +#endif +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) { + UART_Type *base = uart_addrs[index]; + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->D; + } + + if (serial_irq_ids[index] != 0) { + if (transmit_empty) + irq_handler(serial_irq_ids[index], TxIrq); + + if (receive_full) + irq_handler(serial_irq_ids[index], RxIrq); + } +} + +void uart0_irq() { + uint32_t status_flags = UART0->S1; + uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0); +} + +void uart1_irq() { + uint32_t status_flags = UART1->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1); +} + +void uart2_irq() { + uint32_t status_flags = UART2->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; + uint32_t vector = 0; + + switch (obj->index) { + case 0: + vector = (uint32_t)&uart0_irq; + break; + case 1: + vector = (uint32_t)&uart1_irq; + break; + case 2: + vector = (uint32_t)&uart2_irq; + break; + default: + break; + } + + if (enable) { + switch (irq) { + case RxIrq: + UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + NVIC_SetVector(uart_irqs[obj->index], vector); + NVIC_EnableIRQ(uart_irqs[obj->index]); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: + UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + switch (other_irq) { + case RxIrq: + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0); + break; + case TxIrq: + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); + break; + default: + break; + } + if (all_disabled) + NVIC_DisableIRQ(uart_irqs[obj->index]); + } +} + +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + uint8_t data; + data = UART_ReadByte(uart_addrs[obj->index]); + + return data; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + UART_WriteByte(uart_addrs[obj->index], (uint8_t)c); +} + +int serial_readable(serial_t *obj) { + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kUART_RxOverrunFlag) + UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); + return (status_flags & kUART_RxDataRegFullFlag); +} + +int serial_writable(serial_t *obj) { + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kUART_RxOverrunFlag) + UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); + return (status_flags & kUART_TxDataRegEmptyFlag); +} + +void serial_clear(serial_t *obj) { +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) { + uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK; +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c new file mode 100644 index 00000000000..dc2190ee6f3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c @@ -0,0 +1,132 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_assert.h" + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "fsl_dspi.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" + +/* Array of SPI peripheral base address. */ +static SPI_Type *const spi_address[] = SPI_BASE_PTRS; +/* Array of SPI bus clock frequencies */ +static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + + obj->instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) { + DSPI_Deinit(spi_address[obj->instance]); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + + dspi_master_config_t master_config; + dspi_slave_config_t slave_config; + + if (slave) { + /* Slave config */ + DSPI_SlaveGetDefaultConfig(&slave_config); + slave_config.whichCtar = kDSPI_Ctar0; + slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; + slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; + slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; + + DSPI_SlaveInit(spi_address[obj->instance], &slave_config); + } else { + /* Master config */ + DSPI_MasterGetDefaultConfig(&master_config); + master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; + master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; + master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; + master_config.ctarConfig.direction = kDSPI_MsbFirst; + master_config.ctarConfig.pcsToSckDelayInNanoSec = 0; + + DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance])); + } +} + +void spi_frequency(spi_t *obj, int hz) { + uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]); + DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock); + //Half clock period delay after SPI transfer + DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz); +} + +static inline int spi_readable(spi_t * obj) { + return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag); +} + +int spi_master_write(spi_t *obj, int value) { + dspi_command_data_config_t command; + uint32_t rx_data; + DSPI_GetDefaultDataCommandConfig(&command); + command.isEndOfQueue = true; + + DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value); + + DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag); + + // wait rx buffer full + while (!spi_readable(obj)); + rx_data = DSPI_ReadData(spi_address[obj->instance]); + DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag); + return rx_data & 0xffff; +} + +int spi_slave_receive(spi_t *obj) { + return spi_readable(obj); +} + +int spi_slave_read(spi_t *obj) { + uint32_t rx_data; + + while (!spi_readable(obj)); + rx_data = DSPI_ReadData(spi_address[obj->instance]); + DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag); + return rx_data & 0xffff; +} + +void spi_slave_write(spi_t *obj, int value) { + DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c new file mode 100644 index 00000000000..9dcfde85ae8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c @@ -0,0 +1,87 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "fsl_pit.h" +#include "fsl_clock_config.h" + +static int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) { + return; + } + us_ticker_inited = 1; + // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init + if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) + BOARD_BootClockRUN(); + //Common for ticker/timer + uint32_t busClock; + // Structure to initialize PIT + pit_config_t pitConfig; + + PIT_GetDefaultConfig(&pitConfig); + PIT_Init(PIT, &pitConfig); + + busClock = CLOCK_GetFreq(kCLOCK_BusClk); + + //Timer + PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); + PIT_StartTimer(PIT, kPIT_Chnl_0); + PIT_StartTimer(PIT, kPIT_Chnl_1); + + //Ticker + PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); + NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(PIT3_IRQn); +} + + +uint32_t us_ticker_read() { + if (!us_ticker_inited) { + us_ticker_init(); + } + + return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1)); +} + +void us_ticker_disable_interrupt(void) { + PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); +} + +void us_ticker_clear_interrupt(void) { + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int delta = (int)(timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past: + us_ticker_irq_handler(); + return; + } + + PIT_StopTimer(PIT, kPIT_Chnl_3); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); + PIT_StartTimer(PIT, kPIT_Chnl_3); + PIT_StartTimer(PIT, kPIT_Chnl_2); +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 0057ddd1674..5f5b41605c1 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -567,6 +567,20 @@ def __init__(self): } } +class K22F(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'FRDM'] + self.macros = ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.detect_code = ["0231"] + self.progen = { + "target":"frdm-k22f", + } + class K64F(Target): def __init__(self): Target.__init__(self) @@ -2143,6 +2157,7 @@ def __init__(self): LPC4330_M0(), LPC4337(), LPC11U37H_401(), + K22F(), K64F(), MTS_GAMBIT(), # FRDM K64F From 06698f4ffacaf74fad4ecfe3eeb0d7e982382ccb Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Tue, 22 Mar 2016 15:14:13 -0500 Subject: [PATCH 06/11] Add support for the K64F Hexiwear board Signed-off-by: Mahadevan Mahesh --- .../TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct | 30 +-- .../TARGET_HEXIWEAR/PeripheralNames.h | 135 +++++++++++ .../TARGET_HEXIWEAR/PeripheralPins.c | 165 +++++++++++++ .../TARGET_K64F/TARGET_HEXIWEAR/PinNames.h | 229 ++++++++++++++++++ .../TARGET_K64F/TARGET_HEXIWEAR/device.h | 58 +++++ .../TARGET_HEXIWEAR/fsl_clock_config.c | 196 +++++++++++++++ .../TARGET_HEXIWEAR/fsl_clock_config.h | 53 ++++ .../TARGET_HEXIWEAR/mbed_overrides.c | 32 +++ .../TARGET_K64F/serial_api.c | 5 + workspace_tools/targets.py | 19 +- 10 files changed, 897 insertions(+), 25 deletions(-) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct index 5409a2e9f1f..b13dfda2a8c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct @@ -90,7 +90,13 @@ #define Heap_Size 0x0400 #endif -LR_m_text m_text_start m_text_size { ; load region size_region +LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_flash_config m_flash_config_start m_flash_config_size { ; load address = execution address + * (FlashConfig) + } ER_m_text m_text_start m_text_size { ; load address = execution address * (InRoot$$Sections) .ANY (+RO) @@ -103,28 +109,6 @@ LR_m_text m_text_start m_text_size { ; load region size_region } RW_IRAM1 ((ImageLimit(RW_m_data_2) == m_data_2_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up } -} - -LR_m_interrupts m_interrupts_start m_interrupts_size { -#if (!defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - -LR_m_flash_config m_flash_config_start m_flash_config_size { - ER_m_flash_config m_flash_config_start m_flash_config_size { ; load address = execution address - * (FlashConfig) - } -} - -#if (defined(__ram_vector_table__)) -LR_m_interrupts_ram m_interrupts_ram_start m_interrupts_ram_size { VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { } } -#endif - diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h new file mode 100644 index 00000000000..687ca33049e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h @@ -0,0 +1,135 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, + ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, + ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, + ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, + ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, + ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, + ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, + ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, + ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, + ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, + ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, + ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, + ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, + ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, + ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c new file mode 100644 index 00000000000..0c704cbee53 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c @@ -0,0 +1,165 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTA17, ADC1_SE17, 0}, + {PTB0 , ADC0_SE8 , 0}, + {PTB1 , ADC0_SE9 , 0}, + {PTB2 , ADC0_SE12, 0}, + {PTB3 , ADC0_SE13, 0}, + {PTB6 , ADC1_SE12, 0}, + {PTB7 , ADC1_SE13, 0}, + {PTB10, ADC1_SE14, 0}, + {PTB11, ADC1_SE15, 0}, + {PTC0 , ADC0_SE14, 0}, + {PTC1 , ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10, ADC1_SE6b, 0}, + {PTC11, ADC1_SE7b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTE0, ADC1_SE4a, 0}, + {PTE1, ADC1_SE5a, 0}, + {PTE2, ADC1_SE6a, 0}, + {PTE3, ADC1_SE7a, 0}, + //{PTE24, ADC0_SE17, 0}, //I2C pull up + //{PTE25, ADC0_SE18, 0}, //I2C pull up + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTD9 , I2C_0, 2}, + {PTC11, I2C_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTD8 , I2C_0, 2}, + {PTC10, I2C_1, 2}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC17, UART_3, 3}, + {PTD3 , UART_2, 3}, + {PTE24, UART_4, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTE25, UART_4, 3}, + {PTC16, UART_3, 3}, + {PTD2 , UART_2, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTB21, SPI_2, 2}, + {PTC5 , SPI_0, 2}, + {PTD5 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTB22, SPI_2, 2}, + {PTC6 , SPI_0, 2}, + {PTD6 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTB23, SPI_2, 2}, + {PTC7 , SPI_0, 2}, + {PTD7 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTB20, SPI_2, 2}, + {PTC4 , SPI_0, 2}, + {PTD4 , SPI_1, 7}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0 , PWM_6 , 3}, + {PTA1 , PWM_7 , 3}, + {PTA2 , PWM_8 , 3}, + {PTA3 , PWM_1 , 3}, + {PTA4 , PWM_2 , 3}, + {PTA5 , PWM_3 , 3}, + {PTA6 , PWM_4 , 3}, + {PTA7 , PWM_5 , 3}, + {PTA8 , PWM_9 , 3}, + {PTA9 , PWM_10, 3}, + {PTA10, PWM_17, 3}, + {PTA11, PWM_18, 3}, + {PTA12, PWM_9 , 3}, + {PTA13, PWM_10, 3}, + + {PTB0 , PWM_9 , 3}, + {PTB1 , PWM_10, 3}, + {PTB18, PWM_17, 3}, + {PTB19, PWM_18, 3}, + + {PTC1 , PWM_1 , 4}, + {PTC2 , PWM_2 , 4}, + {PTC3 , PWM_3 , 4}, + {PTC4 , PWM_4 , 4}, + {PTC5 , PWM_3 , 7}, + {PTC8 , PWM_29, 3}, + {PTC9 , PWM_30, 3}, + {PTC10, PWM_31, 3}, + {PTC11, PWM_32, 3}, + + {PTD0 , PWM_25, 4}, + {PTD1 , PWM_26, 4}, + {PTD2 , PWM_27, 4}, + {PTD3 , PWM_28, 4}, + {PTD4 , PWM_5 , 4}, + {PTD5 , PWM_6 , 4}, + {PTD6 , PWM_7 , 4}, + {PTD4 , PWM_5 , 4}, + {PTD7 , PWM_8 , 4}, + + {PTE5 , PWM_25, 6}, + {PTE6 , PWM_26, 6}, + + {NC , NC , 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h new file mode 100644 index 00000000000..32983d0a369 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h @@ -0,0 +1,229 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), + PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), + PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), + PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTA22 = (0 << GPIO_PORT_SHIFT | 22), + PTA23 = (0 << GPIO_PORT_SHIFT | 23), + PTA24 = (0 << GPIO_PORT_SHIFT | 24), + PTA25 = (0 << GPIO_PORT_SHIFT | 25), + PTA26 = (0 << GPIO_PORT_SHIFT | 26), + PTA27 = (0 << GPIO_PORT_SHIFT | 27), + PTA28 = (0 << GPIO_PORT_SHIFT | 28), + PTA29 = (0 << GPIO_PORT_SHIFT | 29), + PTA30 = (0 << GPIO_PORT_SHIFT | 30), + PTA31 = (0 << GPIO_PORT_SHIFT | 31), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), + PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), + PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), + PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), + PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), + PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB12 = (1 << GPIO_PORT_SHIFT | 12), + PTB13 = (1 << GPIO_PORT_SHIFT | 13), + PTB14 = (1 << GPIO_PORT_SHIFT | 14), + PTB15 = (1 << GPIO_PORT_SHIFT | 15), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTB24 = (1 << GPIO_PORT_SHIFT | 24), + PTB25 = (1 << GPIO_PORT_SHIFT | 25), + PTB26 = (1 << GPIO_PORT_SHIFT | 26), + PTB27 = (1 << GPIO_PORT_SHIFT | 27), + PTB28 = (1 << GPIO_PORT_SHIFT | 28), + PTB29 = (1 << GPIO_PORT_SHIFT | 29), + PTB30 = (1 << GPIO_PORT_SHIFT | 30), + PTB31 = (1 << GPIO_PORT_SHIFT | 31), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTC20 = (2 << GPIO_PORT_SHIFT | 20), + PTC21 = (2 << GPIO_PORT_SHIFT | 21), + PTC22 = (2 << GPIO_PORT_SHIFT | 22), + PTC23 = (2 << GPIO_PORT_SHIFT | 23), + PTC24 = (2 << GPIO_PORT_SHIFT | 24), + PTC25 = (2 << GPIO_PORT_SHIFT | 25), + PTC26 = (2 << GPIO_PORT_SHIFT | 26), + PTC27 = (2 << GPIO_PORT_SHIFT | 27), + PTC28 = (2 << GPIO_PORT_SHIFT | 28), + PTC29 = (2 << GPIO_PORT_SHIFT | 29), + PTC30 = (2 << GPIO_PORT_SHIFT | 30), + PTC31 = (2 << GPIO_PORT_SHIFT | 31), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), + PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), + PTD10 = (3 << GPIO_PORT_SHIFT | 10), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTD15 = (3 << GPIO_PORT_SHIFT | 15), + PTD16 = (3 << GPIO_PORT_SHIFT | 16), + PTD17 = (3 << GPIO_PORT_SHIFT | 17), + PTD18 = (3 << GPIO_PORT_SHIFT | 18), + PTD19 = (3 << GPIO_PORT_SHIFT | 19), + PTD20 = (3 << GPIO_PORT_SHIFT | 20), + PTD21 = (3 << GPIO_PORT_SHIFT | 21), + PTD22 = (3 << GPIO_PORT_SHIFT | 22), + PTD23 = (3 << GPIO_PORT_SHIFT | 23), + PTD24 = (3 << GPIO_PORT_SHIFT | 24), + PTD25 = (3 << GPIO_PORT_SHIFT | 25), + PTD26 = (3 << GPIO_PORT_SHIFT | 26), + PTD27 = (3 << GPIO_PORT_SHIFT | 27), + PTD28 = (3 << GPIO_PORT_SHIFT | 28), + PTD29 = (3 << GPIO_PORT_SHIFT | 29), + PTD30 = (3 << GPIO_PORT_SHIFT | 30), + PTD31 = (3 << GPIO_PORT_SHIFT | 31), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), + PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), + PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), + PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), + PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), + PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), + PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), + PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE14 = (4 << GPIO_PORT_SHIFT | 14), + PTE15 = (4 << GPIO_PORT_SHIFT | 15), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE26 = (4 << GPIO_PORT_SHIFT | 26), + PTE27 = (4 << GPIO_PORT_SHIFT | 27), + PTE28 = (4 << GPIO_PORT_SHIFT | 28), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + LED_RED = PTC8, + LED_GREEN = PTD0, + LED_BLUE = PTC9, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + // USB Pins + USBTX = PTB17, + USBRX = PTB16, + + I2C_SCL = PTC10, + I2C_SDA = PTC11, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h new file mode 100644 index 00000000000..8f3ef7e1252 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c new file mode 100755 index 00000000000..8a3854f4dc2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 120MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 7U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 120000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC, false); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h new file mode 100755 index 00000000000..32d74cc4001 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c new file mode 100644 index 00000000000..7b93dffa50a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" + +#include "fsl_clock_config.h" + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c index 6214a774acc..6dd34f38cbe 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c @@ -28,6 +28,7 @@ #include "fsl_uart.h" #include "peripheral_clock_defines.h" #include "PeripheralPins.h" +#include "fsl_clock_config.h" static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; static uart_irq_handler irq_handler; @@ -46,6 +47,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->index = pinmap_merge(uart_tx, uart_rx); MBED_ASSERT((int)obj->index != NC); + // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init + if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) + BOARD_BootClockRUN(); + uart_config_t config; UART_GetDefaultConfig(&config); diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 5f5b41605c1..51d6c8c67df 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -609,6 +609,20 @@ def __init__(self): "target":"mts-gambit", } +class HEXIWEAR(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'K64F'] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0240"] + self.progen = { + "target":"hexiwear-k64f", + } + ### Freescale ### class KL05Z(Target): @@ -2158,8 +2172,9 @@ def __init__(self): LPC4337(), LPC11U37H_401(), K22F(), - K64F(), - MTS_GAMBIT(), # FRDM K64F + K64F(), # FRDM K64F + MTS_GAMBIT(), + HEXIWEAR(), ### Freescale ### KL05Z(), From f512738f91c14392fff2f36ffd1664e5013993eb Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Tue, 29 Mar 2016 14:01:02 -0500 Subject: [PATCH 07/11] Add support for KL27Z FRDM board Signed-off-by: Mahadevan Mahesh --- .../cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h | 5809 +++++++++++++++++ .../TARGET_KL27Z/MKL27Z644_features.h | 1708 +++++ .../TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct | 110 + .../TOOLCHAIN_ARM_STD/startup_MKL27Z644.S | 449 ++ .../TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld | 277 + .../TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S | 382 ++ .../TOOLCHAIN_IAR/MKL27Z64xxx4.icf | 115 + .../TOOLCHAIN_IAR/startup_MKL27Z644.S | 317 + .../cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h | 13 + .../TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c | 42 + .../TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h | 48 + .../TARGET_KL27Z/fsl_device_registers.h | 59 + .../TARGET_KL27Z/system_MKL27Z644.c | 155 + .../TARGET_KL27Z/system_MKL27Z644.h | 166 + .../TARGET_FRDM/PeripheralNames.h | 91 + .../TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c | 150 + .../TARGET_KL27Z/TARGET_FRDM/PinNames.h | 151 + .../TARGET_KL27Z/TARGET_FRDM/device.h | 58 + .../TARGET_FRDM/fsl_clock_config.c | 149 + .../TARGET_FRDM/fsl_clock_config.h | 53 + .../TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c | 41 + .../TARGET_KL27Z/drivers/fsl_adc16.c | 363 + .../TARGET_KL27Z/drivers/fsl_adc16.h | 527 ++ .../TARGET_KL27Z/drivers/fsl_clock.c | 408 ++ .../TARGET_KL27Z/drivers/fsl_clock.h | 792 +++ .../TARGET_KL27Z/drivers/fsl_cmp.c | 279 + .../TARGET_KL27Z/drivers/fsl_cmp.h | 346 + .../TARGET_KL27Z/drivers/fsl_common.c | 97 + .../TARGET_KL27Z/drivers/fsl_common.h | 255 + .../TARGET_KL27Z/drivers/fsl_cop.c | 77 + .../TARGET_KL27Z/drivers/fsl_cop.h | 188 + .../TARGET_KL27Z/drivers/fsl_crc.c | 270 + .../TARGET_KL27Z/drivers/fsl_crc.h | 195 + .../TARGET_KL27Z/drivers/fsl_dma.c | 306 + .../TARGET_KL27Z/drivers/fsl_dma.h | 609 ++ .../TARGET_KL27Z/drivers/fsl_dmamux.c | 87 + .../TARGET_KL27Z/drivers/fsl_dmamux.h | 176 + .../TARGET_KL27Z/drivers/fsl_flash.c | 2610 ++++++++ .../TARGET_KL27Z/drivers/fsl_flash.h | 1177 ++++ .../TARGET_KL27Z/drivers/fsl_flexio.c | 262 + .../TARGET_KL27Z/drivers/fsl_flexio.h | 707 ++ .../drivers/fsl_flexio_i2c_master.c | 732 +++ .../drivers/fsl_flexio_i2c_master.h | 490 ++ .../TARGET_KL27Z/drivers/fsl_flexio_i2s.c | 637 ++ .../TARGET_KL27Z/drivers/fsl_flexio_i2s.h | 570 ++ .../TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c | 339 + .../TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h | 218 + .../TARGET_KL27Z/drivers/fsl_flexio_spi.c | 935 +++ .../TARGET_KL27Z/drivers/fsl_flexio_spi.h | 708 ++ .../TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c | 415 ++ .../TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h | 223 + .../TARGET_KL27Z/drivers/fsl_flexio_uart.c | 690 ++ .../TARGET_KL27Z/drivers/fsl_flexio_uart.h | 586 ++ .../drivers/fsl_flexio_uart_dma.c | 358 + .../drivers/fsl_flexio_uart_dma.h | 191 + .../TARGET_KL27Z/drivers/fsl_gpio.c | 179 + .../TARGET_KL27Z/drivers/fsl_gpio.h | 390 ++ .../TARGET_KL27Z/drivers/fsl_i2c.c | 1536 +++++ .../TARGET_KL27Z/drivers/fsl_i2c.h | 781 +++ .../TARGET_KL27Z/drivers/fsl_i2c_dma.c | 523 ++ .../TARGET_KL27Z/drivers/fsl_i2c_dma.h | 132 + .../TARGET_KL27Z/drivers/fsl_llwu.c | 404 ++ .../TARGET_KL27Z/drivers/fsl_llwu.h | 321 + .../TARGET_KL27Z/drivers/fsl_lptmr.c | 117 + .../TARGET_KL27Z/drivers/fsl_lptmr.h | 351 + .../TARGET_KL27Z/drivers/fsl_lpuart.c | 1103 ++++ .../TARGET_KL27Z/drivers/fsl_lpuart.h | 753 +++ .../TARGET_KL27Z/drivers/fsl_lpuart_dma.c | 339 + .../TARGET_KL27Z/drivers/fsl_lpuart_dma.h | 189 + .../TARGET_KL27Z/drivers/fsl_pit.c | 119 + .../TARGET_KL27Z/drivers/fsl_pit.h | 355 + .../TARGET_KL27Z/drivers/fsl_pmc.c | 93 + .../TARGET_KL27Z/drivers/fsl_pmc.h | 423 ++ .../TARGET_KL27Z/drivers/fsl_port.h | 382 ++ .../TARGET_KL27Z/drivers/fsl_rcm.c | 63 + .../TARGET_KL27Z/drivers/fsl_rcm.h | 432 ++ .../TARGET_KL27Z/drivers/fsl_rtc.c | 370 ++ .../TARGET_KL27Z/drivers/fsl_rtc.h | 405 ++ .../TARGET_KL27Z/drivers/fsl_sim.c | 53 + .../TARGET_KL27Z/drivers/fsl_sim.h | 128 + .../TARGET_KL27Z/drivers/fsl_smc.c | 360 + .../TARGET_KL27Z/drivers/fsl_smc.h | 419 ++ .../TARGET_KL27Z/drivers/fsl_spi.c | 873 +++ .../TARGET_KL27Z/drivers/fsl_spi.h | 708 ++ .../TARGET_KL27Z/drivers/fsl_spi_dma.c | 327 + .../TARGET_KL27Z/drivers/fsl_spi_dma.h | 207 + .../TARGET_KL27Z/drivers/fsl_tpm.c | 656 ++ .../TARGET_KL27Z/drivers/fsl_tpm.h | 578 ++ .../TARGET_KL27Z/drivers/fsl_uart.c | 1032 +++ .../TARGET_KL27Z/drivers/fsl_uart.h | 757 +++ .../TARGET_KL27Z/drivers/fsl_uart_dma.c | 365 ++ .../TARGET_KL27Z/drivers/fsl_uart_dma.h | 193 + .../TARGET_KL27Z/drivers/fsl_vref.c | 172 + .../TARGET_KL27Z/drivers/fsl_vref.h | 228 + .../TARGET_KL27Z/peripheral_clock_defines.h | 60 + .../TARGET_KL27Z/serial_api.c | 256 + .../TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c | 131 + .../TARGET_KL27Z/us_ticker.c | 95 + libraries/rpc/parse_pins.cpp | 2 +- .../rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 3 + .../rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 6 +- libraries/tests/mbed/i2c_eeprom/main.cpp | 3 + libraries/tests/mbed/i2c_eeprom_line/main.cpp | 3 + workspace_tools/build_release.py | 1 + workspace_tools/build_travis.py | 1 + workspace_tools/targets.py | 16 + 107 files changed, 44586 insertions(+), 4 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644_features.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/fsl_device_registers.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h create mode 100755 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h new file mode 100644 index 00000000000..506d7c43b99 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h @@ -0,0 +1,5809 @@ +/* +** ################################################################### +** Processors: MKL27Z32VDA4 +** MKL27Z32VFM4 +** MKL27Z32VFT4 +** MKL27Z32VLH4 +** MKL27Z32VMP4 +** MKL27Z64VDA4 +** MKL27Z64VFM4 +** MKL27Z64VFT4 +** MKL27Z64VLH4 +** MKL27Z64VMP4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 +** Version: rev. 1.4, 2014-09-22 +** Build: b151221 +** +** Abstract: +** CMSIS Peripheral Access Layer for MKL27Z644 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-12) +** Initial version. +** - rev. 1.1 (2014-07-10) +** UART0 - UART0 module renamed to UART2. +** - rev. 1.2 (2014-08-12) +** CRC - CRC register renamed to DATA. +** - rev. 1.3 (2014-09-02) +** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. +** USB - USB0_CTL1 was renamed to USB0_CTL register. +** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. +** - rev. 1.4 (2014-09-22) +** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. +** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. +** SIM - Removed bitfield DIEID in SDID register. +** UART2 - Removed ED register. +** UART2 - Removed MODEM register. +** UART2 - Removed IR register. +** UART2 - Removed PFIFO register. +** UART2 - Removed CFIFO register. +** UART2 - Removed SFIFO register. +** UART2 - Removed TWFIFO register. +** UART2 - Removed TCFIFO register. +** UART2 - Removed RWFIFO register. +** UART2 - Removed RCFIFO register. +** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. +** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. +** +** ################################################################### +*/ + +/*! + * @file MKL27Z644.h + * @version 1.4 + * @date 2014-09-22 + * @brief CMSIS Peripheral Access Layer for MKL27Z644 + * + * CMSIS Peripheral Access Layer for MKL27Z644 + */ + +#ifndef _MKL27Z644_H_ +#define _MKL27Z644_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0004U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ + Reserved20_IRQn = 4, /**< Reserved interrupt */ + FTFA_IRQn = 5, /**< Command complete and read collision */ + PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ + LLWU_IRQn = 7, /**< Low leakage wakeup */ + I2C0_IRQn = 8, /**< I2C0 interrupt */ + I2C1_IRQn = 9, /**< I2C1 interrupt */ + SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ + SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ + LPUART0_IRQn = 12, /**< LPUART0 status and error */ + LPUART1_IRQn = 13, /**< LPUART1 status and error */ + UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */ + ADC0_IRQn = 15, /**< ADC0 interrupt */ + CMP0_IRQn = 16, /**< CMP0 interrupt */ + TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ + TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ + TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ + RTC_IRQn = 20, /**< RTC alarm */ + RTC_Seconds_IRQn = 21, /**< RTC seconds */ + PIT_IRQn = 22, /**< PIT interrupt */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + USB0_IRQn = 24, /**< USB0 interrupt */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + Reserved43_IRQn = 27, /**< Reserved interrupt */ + LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ + Reserved45_IRQn = 29, /**< Reserved interrupt */ + PORTA_IRQn = 30, /**< PORTA Pin detect */ + PORTB_PORTC_PORTD_PORTE_IRQn = 31 /**< Single interrupt vector for PORTB,PORTC,PORTD,PORTE */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M0 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration + * @{ + */ + +#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm0plus.h" /* Core Peripheral Access Layer */ +#include "system_MKL27Z644.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */ + kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0FlexIOChannel0 = 10|0x100U, /**< FLEXIO. */ + kDmaRequestMux0FlexIOChannel1 = 11|0x100U, /**< FLEXIO. */ + kDmaRequestMux0FlexIOChannel2 = 12|0x100U, /**< FLEXIO. */ + kDmaRequestMux0FlexIOChannel3 = 13|0x100U, /**< FLEXIO. */ + kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ + kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ + kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ + kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ + kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ + kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ + kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ + kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ + kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 C4V. */ + kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 C5V. */ + kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ + kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ + kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ + kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ + kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ + kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ + kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ + kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ + kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ + kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ + kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ + kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name SC1 - ADC Status and Control Registers 1 */ +#define ADC_SC1_ADCH_MASK (0x1FU) +#define ADC_SC1_ADCH_SHIFT (0U) +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK (0x20U) +#define ADC_SC1_DIFF_SHIFT (5U) +#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) +#define ADC_SC1_AIEN_MASK (0x40U) +#define ADC_SC1_AIEN_SHIFT (6U) +#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) +#define ADC_SC1_COCO_MASK (0x80U) +#define ADC_SC1_COCO_SHIFT (7U) +#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) + +/* The count of ADC_SC1 */ +#define ADC_SC1_COUNT (2U) + +/*! @name CFG1 - ADC Configuration Register 1 */ +#define ADC_CFG1_ADICLK_MASK (0x3U) +#define ADC_CFG1_ADICLK_SHIFT (0U) +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK (0xCU) +#define ADC_CFG1_MODE_SHIFT (2U) +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK (0x10U) +#define ADC_CFG1_ADLSMP_SHIFT (4U) +#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) +#define ADC_CFG1_ADIV_MASK (0x60U) +#define ADC_CFG1_ADIV_SHIFT (5U) +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK (0x80U) +#define ADC_CFG1_ADLPC_SHIFT (7U) +#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) + +/*! @name CFG2 - ADC Configuration Register 2 */ +#define ADC_CFG2_ADLSTS_MASK (0x3U) +#define ADC_CFG2_ADLSTS_SHIFT (0U) +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK (0x4U) +#define ADC_CFG2_ADHSC_SHIFT (2U) +#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) +#define ADC_CFG2_ADACKEN_MASK (0x8U) +#define ADC_CFG2_ADACKEN_SHIFT (3U) +#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) +#define ADC_CFG2_MUXSEL_MASK (0x10U) +#define ADC_CFG2_MUXSEL_SHIFT (4U) +#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) + +/*! @name R - ADC Data Result Register */ +#define ADC_R_D_MASK (0xFFFFU) +#define ADC_R_D_SHIFT (0U) +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (2U) + +/*! @name CV1 - Compare Value Registers */ +#define ADC_CV1_CV_MASK (0xFFFFU) +#define ADC_CV1_CV_SHIFT (0U) +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) + +/*! @name CV2 - Compare Value Registers */ +#define ADC_CV2_CV_MASK (0xFFFFU) +#define ADC_CV2_CV_SHIFT (0U) +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) + +/*! @name SC2 - Status and Control Register 2 */ +#define ADC_SC2_REFSEL_MASK (0x3U) +#define ADC_SC2_REFSEL_SHIFT (0U) +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK (0x4U) +#define ADC_SC2_DMAEN_SHIFT (2U) +#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) +#define ADC_SC2_ACREN_MASK (0x8U) +#define ADC_SC2_ACREN_SHIFT (3U) +#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) +#define ADC_SC2_ACFGT_MASK (0x10U) +#define ADC_SC2_ACFGT_SHIFT (4U) +#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) +#define ADC_SC2_ACFE_MASK (0x20U) +#define ADC_SC2_ACFE_SHIFT (5U) +#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) +#define ADC_SC2_ADTRG_MASK (0x40U) +#define ADC_SC2_ADTRG_SHIFT (6U) +#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) +#define ADC_SC2_ADACT_MASK (0x80U) +#define ADC_SC2_ADACT_SHIFT (7U) +#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) + +/*! @name SC3 - Status and Control Register 3 */ +#define ADC_SC3_AVGS_MASK (0x3U) +#define ADC_SC3_AVGS_SHIFT (0U) +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK (0x4U) +#define ADC_SC3_AVGE_SHIFT (2U) +#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) +#define ADC_SC3_ADCO_MASK (0x8U) +#define ADC_SC3_ADCO_SHIFT (3U) +#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) +#define ADC_SC3_CALF_MASK (0x40U) +#define ADC_SC3_CALF_SHIFT (6U) +#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) +#define ADC_SC3_CAL_MASK (0x80U) +#define ADC_SC3_CAL_SHIFT (7U) +#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) + +/*! @name OFS - ADC Offset Correction Register */ +#define ADC_OFS_OFS_MASK (0xFFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) + +/*! @name PG - ADC Plus-Side Gain Register */ +#define ADC_PG_PG_MASK (0xFFFFU) +#define ADC_PG_PG_SHIFT (0U) +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) + +/*! @name MG - ADC Minus-Side Gain Register */ +#define ADC_MG_MG_MASK (0xFFFFU) +#define ADC_MG_MG_SHIFT (0U) +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) + +/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPD_CLPD_MASK (0x3FU) +#define ADC_CLPD_CLPD_SHIFT (0U) +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) + +/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPS_CLPS_MASK (0x3FU) +#define ADC_CLPS_CLPS_SHIFT (0U) +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) + +/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP4_CLP4_MASK (0x3FFU) +#define ADC_CLP4_CLP4_SHIFT (0U) +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) + +/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP3_CLP3_MASK (0x1FFU) +#define ADC_CLP3_CLP3_SHIFT (0U) +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) + +/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP2_CLP2_MASK (0xFFU) +#define ADC_CLP2_CLP2_SHIFT (0U) +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) + +/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP1_CLP1_MASK (0x7FU) +#define ADC_CLP1_CLP1_SHIFT (0U) +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) + +/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP0_CLP0_MASK (0x3FU) +#define ADC_CLP0_CLP0_SHIFT (0U) +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) + +/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMD_CLMD_MASK (0x3FU) +#define ADC_CLMD_CLMD_SHIFT (0U) +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) + +/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMS_CLMS_MASK (0x3FU) +#define ADC_CLMS_CLMS_SHIFT (0U) +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) + +/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM4_CLM4_MASK (0x3FFU) +#define ADC_CLM4_CLM4_SHIFT (0U) +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) + +/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM3_CLM3_MASK (0x1FFU) +#define ADC_CLM3_CLM3_SHIFT (0U) +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) + +/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM2_CLM2_MASK (0xFFU) +#define ADC_CLM2_CLM2_SHIFT (0U) +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) + +/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM1_CLM1_MASK (0x7FU) +#define ADC_CLM1_CLM1_SHIFT (0U) +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) + +/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM0_CLM0_MASK (0x3FU) +#define ADC_CLM0_CLM0_SHIFT (0U) +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) + +/*! @name CR1 - CMP Control Register 1 */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_TRIGM_MASK (0x20U) +#define CMP_CR1_TRIGM_SHIFT (5U) +#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) + +/*! @name FPR - CMP Filter Period Register */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) + +/*! @name SCR - CMP Status and Control Register */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) + +/*! @name DACCR - DAC Control Register */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) + +/*! @name MUXCR - MUX Control Register */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +#define CMP_MUXCR_PSTM_MASK (0x80U) +#define CMP_MUXCR_PSTM_SHIFT (7U) +#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { CMP0_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { CMP0 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ + } ACCESS8BIT; + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ + } GPOLY_ACCESS8BIT; + }; + union { /* offset: 0x8 */ + __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ + } CTRL_ACCESS8BIT; + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATAL - CRC_DATAL register. */ +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) + +/*! @name DATAH - CRC_DATAH register. */ +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) + +/*! @name DATA - CRC Data register */ +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) + +/*! @name DATALL - CRC_DATALL register. */ +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) + +/*! @name DATALU - CRC_DATALU register. */ +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) + +/*! @name DATAHL - CRC_DATAHL register. */ +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) + +/*! @name DATAHU - CRC_DATAHU register. */ +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) + +/*! @name GPOLYL - CRC_GPOLYL register. */ +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) + +/*! @name GPOLYH - CRC_GPOLYH register. */ +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) + +/*! @name GPOLY - CRC Polynomial register */ +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) + +/*! @name GPOLYLL - CRC_GPOLYLL register. */ +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) + +/*! @name GPOLYLU - CRC_GPOLYLU register. */ +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) + +/*! @name GPOLYHL - CRC_GPOLYHL register. */ +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) + +/*! @name GPOLYHU - CRC_GPOLYHU register. */ +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) + +/*! @name CTRL - CRC Control register */ +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) + +/*! @name CTRLHU - CRC_CTRLHU register. */ +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC base address */ +#define CRC_BASE (0x40032000u) +/** Peripheral CRC base pointer */ +#define CRC0 ((CRC_Type *)CRC_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[256]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ + __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ + union { /* offset: 0x108, array step: 0x10 */ + __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ + struct { /* offset: 0x108, array step: 0x10 */ + uint8_t RESERVED_0[3]; + __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ + } DMA_DSR_ACCESS8BIT; + }; + __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ + } DMA[4]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name SAR - Source Address Register */ +#define DMA_SAR_SAR_MASK (0xFFFFFFFFU) +#define DMA_SAR_SAR_SHIFT (0U) +#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK) + +/* The count of DMA_SAR */ +#define DMA_SAR_COUNT (4U) + +/*! @name DAR - Destination Address Register */ +#define DMA_DAR_DAR_MASK (0xFFFFFFFFU) +#define DMA_DAR_DAR_SHIFT (0U) +#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK) + +/* The count of DMA_DAR */ +#define DMA_DAR_COUNT (4U) + +/*! @name DSR_BCR - DMA Status Register / Byte Count Register */ +#define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU) +#define DMA_DSR_BCR_BCR_SHIFT (0U) +#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK) +#define DMA_DSR_BCR_DONE_MASK (0x1000000U) +#define DMA_DSR_BCR_DONE_SHIFT (24U) +#define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK) +#define DMA_DSR_BCR_BSY_MASK (0x2000000U) +#define DMA_DSR_BCR_BSY_SHIFT (25U) +#define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK) +#define DMA_DSR_BCR_REQ_MASK (0x4000000U) +#define DMA_DSR_BCR_REQ_SHIFT (26U) +#define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK) +#define DMA_DSR_BCR_BED_MASK (0x10000000U) +#define DMA_DSR_BCR_BED_SHIFT (28U) +#define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK) +#define DMA_DSR_BCR_BES_MASK (0x20000000U) +#define DMA_DSR_BCR_BES_SHIFT (29U) +#define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK) +#define DMA_DSR_BCR_CE_MASK (0x40000000U) +#define DMA_DSR_BCR_CE_SHIFT (30U) +#define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK) + +/* The count of DMA_DSR_BCR */ +#define DMA_DSR_BCR_COUNT (4U) + +/* The count of DMA_DSR */ +#define DMA_DSR_COUNT (4U) + +/*! @name DCR - DMA Control Register */ +#define DMA_DCR_LCH2_MASK (0x3U) +#define DMA_DCR_LCH2_SHIFT (0U) +#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK) +#define DMA_DCR_LCH1_MASK (0xCU) +#define DMA_DCR_LCH1_SHIFT (2U) +#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK) +#define DMA_DCR_LINKCC_MASK (0x30U) +#define DMA_DCR_LINKCC_SHIFT (4U) +#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK) +#define DMA_DCR_D_REQ_MASK (0x80U) +#define DMA_DCR_D_REQ_SHIFT (7U) +#define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK) +#define DMA_DCR_DMOD_MASK (0xF00U) +#define DMA_DCR_DMOD_SHIFT (8U) +#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK) +#define DMA_DCR_SMOD_MASK (0xF000U) +#define DMA_DCR_SMOD_SHIFT (12U) +#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK) +#define DMA_DCR_START_MASK (0x10000U) +#define DMA_DCR_START_SHIFT (16U) +#define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK) +#define DMA_DCR_DSIZE_MASK (0x60000U) +#define DMA_DCR_DSIZE_SHIFT (17U) +#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK) +#define DMA_DCR_DINC_MASK (0x80000U) +#define DMA_DCR_DINC_SHIFT (19U) +#define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK) +#define DMA_DCR_SSIZE_MASK (0x300000U) +#define DMA_DCR_SSIZE_SHIFT (20U) +#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK) +#define DMA_DCR_SINC_MASK (0x400000U) +#define DMA_DCR_SINC_SHIFT (22U) +#define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK) +#define DMA_DCR_EADREQ_MASK (0x800000U) +#define DMA_DCR_EADREQ_SHIFT (23U) +#define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK) +#define DMA_DCR_AA_MASK (0x10000000U) +#define DMA_DCR_AA_SHIFT (28U) +#define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK) +#define DMA_DCR_CS_MASK (0x20000000U) +#define DMA_DCR_CS_SHIFT (29U) +#define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK) +#define DMA_DCR_ERQ_MASK (0x40000000U) +#define DMA_DCR_ERQ_SHIFT (30U) +#define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK) +#define DMA_DCR_EINT_MASK (0x80000000U) +#define DMA_DCR_EINT_SHIFT (31U) +#define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK) + +/* The count of DMA_DCR */ +#define DMA_DCR_COUNT (4U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base address */ +#define DMA_BASE (0x40008000u) +/** Peripheral DMA base pointer */ +#define DMA0 ((DMA_Type *)DMA_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel Configuration register */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40U) +#define DMAMUX_CHCFG_TRIG_SHIFT (6U) +#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80U) +#define DMAMUX_CHCFG_ENBL_SHIFT (7U) +#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (4U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX0 base address */ +#define DMAMUX0_BASE (0x40021000u) +/** Peripheral DMAMUX0 base pointer */ +#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX0 } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_3[76]; + __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_5[240]; + __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) + +/*! @name PARAM - Parameter Register */ +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) + +/*! @name CTRL - FlexIO Control Register */ +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) + +/*! @name SHIFTSTAT - Shifter Status Register */ +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) + +/*! @name SHIFTERR - Shifter Error Register */ +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) + +/*! @name TIMSTAT - Timer Status Register */ +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) + +/*! @name TIMIEN - Timer Interrupt Enable Register */ +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) + +/*! @name SHIFTCTL - Shifter Control N Register */ +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (4U) + +/*! @name SHIFTCFG - Shifter Configuration N Register */ +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (4U) + +/*! @name SHIFTBUF - Shifter Buffer N Register */ +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (4U) + +/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (4U) + +/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (4U) + +/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (4U) + +/*! @name TIMCTL - Timer Control N Register */ +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) +#define FLEXIO_TIMCTL_PINSEL_MASK (0x700U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) +#define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (4U) + +/*! @name TIMCFG - Timer Configuration N Register */ +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (4U) + +/*! @name TIMCMP - Timer Compare N Register */ +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (4U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO base address */ +#define FLEXIO_BASE (0x4005F000u) +/** Peripheral FLEXIO base pointer */ +#define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { UART2_FLEXIO_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTFA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer + * @{ + */ + +/** FTFA - Register Layout Typedef */ +typedef struct { + __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ + __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ + __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ +} FTFA_Type; + +/* ---------------------------------------------------------------------------- + -- FTFA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFA_Register_Masks FTFA Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +#define FTFA_FSTAT_MGSTAT0_MASK (0x1U) +#define FTFA_FSTAT_MGSTAT0_SHIFT (0U) +#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) +#define FTFA_FSTAT_FPVIOL_MASK (0x10U) +#define FTFA_FSTAT_FPVIOL_SHIFT (4U) +#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) +#define FTFA_FSTAT_ACCERR_MASK (0x20U) +#define FTFA_FSTAT_ACCERR_SHIFT (5U) +#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) +#define FTFA_FSTAT_RDCOLERR_MASK (0x40U) +#define FTFA_FSTAT_RDCOLERR_SHIFT (6U) +#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) +#define FTFA_FSTAT_CCIF_MASK (0x80U) +#define FTFA_FSTAT_CCIF_SHIFT (7U) +#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) + +/*! @name FCNFG - Flash Configuration Register */ +#define FTFA_FCNFG_ERSSUSP_MASK (0x10U) +#define FTFA_FCNFG_ERSSUSP_SHIFT (4U) +#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) +#define FTFA_FCNFG_ERSAREQ_MASK (0x20U) +#define FTFA_FCNFG_ERSAREQ_SHIFT (5U) +#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) +#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) +#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) +#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) +#define FTFA_FCNFG_CCIE_MASK (0x80U) +#define FTFA_FCNFG_CCIE_SHIFT (7U) +#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) + +/*! @name FSEC - Flash Security Register */ +#define FTFA_FSEC_SEC_MASK (0x3U) +#define FTFA_FSEC_SEC_SHIFT (0U) +#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) +#define FTFA_FSEC_FSLACC_MASK (0xCU) +#define FTFA_FSEC_FSLACC_SHIFT (2U) +#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) +#define FTFA_FSEC_MEEN_MASK (0x30U) +#define FTFA_FSEC_MEEN_SHIFT (4U) +#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) +#define FTFA_FSEC_KEYEN_MASK (0xC0U) +#define FTFA_FSEC_KEYEN_SHIFT (6U) +#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) + +/*! @name FOPT - Flash Option Register */ +#define FTFA_FOPT_OPT_MASK (0xFFU) +#define FTFA_FOPT_OPT_SHIFT (0U) +#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) + +/*! @name FCCOB3 - Flash Common Command Object Registers */ +#define FTFA_FCCOB3_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB3_CCOBn_SHIFT (0U) +#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) + +/*! @name FCCOB2 - Flash Common Command Object Registers */ +#define FTFA_FCCOB2_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB2_CCOBn_SHIFT (0U) +#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) + +/*! @name FCCOB1 - Flash Common Command Object Registers */ +#define FTFA_FCCOB1_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB1_CCOBn_SHIFT (0U) +#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) + +/*! @name FCCOB0 - Flash Common Command Object Registers */ +#define FTFA_FCCOB0_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB0_CCOBn_SHIFT (0U) +#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) + +/*! @name FCCOB7 - Flash Common Command Object Registers */ +#define FTFA_FCCOB7_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB7_CCOBn_SHIFT (0U) +#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) + +/*! @name FCCOB6 - Flash Common Command Object Registers */ +#define FTFA_FCCOB6_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB6_CCOBn_SHIFT (0U) +#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) + +/*! @name FCCOB5 - Flash Common Command Object Registers */ +#define FTFA_FCCOB5_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB5_CCOBn_SHIFT (0U) +#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) + +/*! @name FCCOB4 - Flash Common Command Object Registers */ +#define FTFA_FCCOB4_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB4_CCOBn_SHIFT (0U) +#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) + +/*! @name FCCOBB - Flash Common Command Object Registers */ +#define FTFA_FCCOBB_CCOBn_MASK (0xFFU) +#define FTFA_FCCOBB_CCOBn_SHIFT (0U) +#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) + +/*! @name FCCOBA - Flash Common Command Object Registers */ +#define FTFA_FCCOBA_CCOBn_MASK (0xFFU) +#define FTFA_FCCOBA_CCOBn_SHIFT (0U) +#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) + +/*! @name FCCOB9 - Flash Common Command Object Registers */ +#define FTFA_FCCOB9_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB9_CCOBn_SHIFT (0U) +#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) + +/*! @name FCCOB8 - Flash Common Command Object Registers */ +#define FTFA_FCCOB8_CCOBn_MASK (0xFFU) +#define FTFA_FCCOB8_CCOBn_SHIFT (0U) +#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) + +/*! @name FPROT3 - Program Flash Protection Registers */ +#define FTFA_FPROT3_PROT_MASK (0xFFU) +#define FTFA_FPROT3_PROT_SHIFT (0U) +#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Program Flash Protection Registers */ +#define FTFA_FPROT2_PROT_MASK (0xFFU) +#define FTFA_FPROT2_PROT_SHIFT (0U) +#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Program Flash Protection Registers */ +#define FTFA_FPROT1_PROT_MASK (0xFFU) +#define FTFA_FPROT1_PROT_SHIFT (0U) +#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Program Flash Protection Registers */ +#define FTFA_FPROT0_PROT_MASK (0xFFU) +#define FTFA_FPROT0_PROT_SHIFT (0U) +#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) + + +/*! + * @} + */ /* end of group FTFA_Register_Masks */ + + +/* FTFA - Peripheral instance base addresses */ +/** Peripheral FTFA base address */ +#define FTFA_BASE (0x40020000u) +/** Peripheral FTFA base pointer */ +#define FTFA ((FTFA_Type *)FTFA_BASE) +/** Array initializer of FTFA peripheral base addresses */ +#define FTFA_BASE_ADDRS { FTFA_BASE } +/** Array initializer of FTFA peripheral base pointers */ +#define FTFA_BASE_PTRS { FTFA } +/** Interrupt vectors for the FTFA peripheral type */ +#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } + +/*! + * @} + */ /* end of group FTFA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name PDOR - Port Data Output Register */ +#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) +#define GPIO_PDOR_PDO_SHIFT (0U) +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) + +/*! @name PSOR - Port Set Output Register */ +#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define GPIO_PSOR_PTSO_SHIFT (0U) +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) + +/*! @name PCOR - Port Clear Output Register */ +#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define GPIO_PCOR_PTCO_SHIFT (0U) +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) + +/*! @name PTOR - Port Toggle Output Register */ +#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define GPIO_PTOR_PTTO_SHIFT (0U) +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) + +/*! @name PDIR - Port Data Input Register */ +#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define GPIO_PDIR_PDI_SHIFT (0U) +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) + +/*! @name PDDR - Port Data Direction Register */ +#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define GPIO_PDDR_PDD_SHIFT (0U) +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIOA base address */ +#define GPIOA_BASE (0x400FF000u) +/** Peripheral GPIOA base pointer */ +#define GPIOA ((GPIO_Type *)GPIOA_BASE) +/** Peripheral GPIOB base address */ +#define GPIOB_BASE (0x400FF040u) +/** Peripheral GPIOB base pointer */ +#define GPIOB ((GPIO_Type *)GPIOB_BASE) +/** Peripheral GPIOC base address */ +#define GPIOC_BASE (0x400FF080u) +/** Peripheral GPIOC base pointer */ +#define GPIOC ((GPIO_Type *)GPIOC_BASE) +/** Peripheral GPIOD base address */ +#define GPIOD_BASE (0x400FF0C0u) +/** Peripheral GPIOD base pointer */ +#define GPIOD ((GPIO_Type *)GPIOD_BASE) +/** Peripheral GPIOE base address */ +#define GPIOE_BASE (0x400FF100u) +/** Peripheral GPIOE base pointer */ +#define GPIOE ((GPIO_Type *)GPIOE_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ + __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ + __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ + __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ + __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ + __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ + __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ + __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ + __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ + __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ + __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ + __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ + __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name A1 - I2C Address Register 1 */ +#define I2C_A1_AD_MASK (0xFEU) +#define I2C_A1_AD_SHIFT (1U) +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) + +/*! @name F - I2C Frequency Divider register */ +#define I2C_F_ICR_MASK (0x3FU) +#define I2C_F_ICR_SHIFT (0U) +#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) +#define I2C_F_MULT_MASK (0xC0U) +#define I2C_F_MULT_SHIFT (6U) +#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) + +/*! @name C1 - I2C Control Register 1 */ +#define I2C_C1_DMAEN_MASK (0x1U) +#define I2C_C1_DMAEN_SHIFT (0U) +#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) +#define I2C_C1_WUEN_MASK (0x2U) +#define I2C_C1_WUEN_SHIFT (1U) +#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) +#define I2C_C1_RSTA_MASK (0x4U) +#define I2C_C1_RSTA_SHIFT (2U) +#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) +#define I2C_C1_TXAK_MASK (0x8U) +#define I2C_C1_TXAK_SHIFT (3U) +#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) +#define I2C_C1_TX_MASK (0x10U) +#define I2C_C1_TX_SHIFT (4U) +#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) +#define I2C_C1_MST_MASK (0x20U) +#define I2C_C1_MST_SHIFT (5U) +#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) +#define I2C_C1_IICIE_MASK (0x40U) +#define I2C_C1_IICIE_SHIFT (6U) +#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) +#define I2C_C1_IICEN_MASK (0x80U) +#define I2C_C1_IICEN_SHIFT (7U) +#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) + +/*! @name S - I2C Status register */ +#define I2C_S_RXAK_MASK (0x1U) +#define I2C_S_RXAK_SHIFT (0U) +#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) +#define I2C_S_IICIF_MASK (0x2U) +#define I2C_S_IICIF_SHIFT (1U) +#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) +#define I2C_S_SRW_MASK (0x4U) +#define I2C_S_SRW_SHIFT (2U) +#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) +#define I2C_S_RAM_MASK (0x8U) +#define I2C_S_RAM_SHIFT (3U) +#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) +#define I2C_S_ARBL_MASK (0x10U) +#define I2C_S_ARBL_SHIFT (4U) +#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) +#define I2C_S_BUSY_MASK (0x20U) +#define I2C_S_BUSY_SHIFT (5U) +#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) +#define I2C_S_IAAS_MASK (0x40U) +#define I2C_S_IAAS_SHIFT (6U) +#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) +#define I2C_S_TCF_MASK (0x80U) +#define I2C_S_TCF_SHIFT (7U) +#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) + +/*! @name D - I2C Data I/O register */ +#define I2C_D_DATA_MASK (0xFFU) +#define I2C_D_DATA_SHIFT (0U) +#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) + +/*! @name C2 - I2C Control Register 2 */ +#define I2C_C2_AD_MASK (0x7U) +#define I2C_C2_AD_SHIFT (0U) +#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) +#define I2C_C2_RMEN_MASK (0x8U) +#define I2C_C2_RMEN_SHIFT (3U) +#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) +#define I2C_C2_SBRC_MASK (0x10U) +#define I2C_C2_SBRC_SHIFT (4U) +#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) +#define I2C_C2_HDRS_MASK (0x20U) +#define I2C_C2_HDRS_SHIFT (5U) +#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) +#define I2C_C2_ADEXT_MASK (0x40U) +#define I2C_C2_ADEXT_SHIFT (6U) +#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) +#define I2C_C2_GCAEN_MASK (0x80U) +#define I2C_C2_GCAEN_SHIFT (7U) +#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) + +/*! @name FLT - I2C Programmable Input Glitch Filter Register */ +#define I2C_FLT_FLT_MASK (0xFU) +#define I2C_FLT_FLT_SHIFT (0U) +#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) +#define I2C_FLT_STARTF_MASK (0x10U) +#define I2C_FLT_STARTF_SHIFT (4U) +#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) +#define I2C_FLT_SSIE_MASK (0x20U) +#define I2C_FLT_SSIE_SHIFT (5U) +#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) +#define I2C_FLT_STOPF_MASK (0x40U) +#define I2C_FLT_STOPF_SHIFT (6U) +#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) +#define I2C_FLT_SHEN_MASK (0x80U) +#define I2C_FLT_SHEN_SHIFT (7U) +#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) + +/*! @name RA - I2C Range Address register */ +#define I2C_RA_RAD_MASK (0xFEU) +#define I2C_RA_RAD_SHIFT (1U) +#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) + +/*! @name SMB - I2C SMBus Control and Status register */ +#define I2C_SMB_SHTF2IE_MASK (0x1U) +#define I2C_SMB_SHTF2IE_SHIFT (0U) +#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) +#define I2C_SMB_SHTF2_MASK (0x2U) +#define I2C_SMB_SHTF2_SHIFT (1U) +#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) +#define I2C_SMB_SHTF1_MASK (0x4U) +#define I2C_SMB_SHTF1_SHIFT (2U) +#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) +#define I2C_SMB_SLTF_MASK (0x8U) +#define I2C_SMB_SLTF_SHIFT (3U) +#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) +#define I2C_SMB_TCKSEL_MASK (0x10U) +#define I2C_SMB_TCKSEL_SHIFT (4U) +#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) +#define I2C_SMB_SIICAEN_MASK (0x20U) +#define I2C_SMB_SIICAEN_SHIFT (5U) +#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) +#define I2C_SMB_ALERTEN_MASK (0x40U) +#define I2C_SMB_ALERTEN_SHIFT (6U) +#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) +#define I2C_SMB_FACK_MASK (0x80U) +#define I2C_SMB_FACK_SHIFT (7U) +#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) + +/*! @name A2 - I2C Address Register 2 */ +#define I2C_A2_SAD_MASK (0xFEU) +#define I2C_A2_SAD_SHIFT (1U) +#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) + +/*! @name SLTH - I2C SCL Low Timeout Register High */ +#define I2C_SLTH_SSLT_MASK (0xFFU) +#define I2C_SLTH_SSLT_SHIFT (0U) +#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) + +/*! @name SLTL - I2C SCL Low Timeout Register Low */ +#define I2C_SLTL_SSLT_MASK (0xFFU) +#define I2C_SLTL_SSLT_SHIFT (0U) +#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) + +/*! @name S2 - I2C Status register 2 */ +#define I2C_S2_EMPTY_MASK (0x1U) +#define I2C_S2_EMPTY_SHIFT (0U) +#define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK) +#define I2C_S2_ERROR_MASK (0x2U) +#define I2C_S2_ERROR_SHIFT (1U) +#define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40066000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40067000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer + * @{ + */ + +/** LLWU - Register Layout Typedef */ +typedef struct { + __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ + __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ + __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ + __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ + __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ + __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ + __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ + __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ + __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ + __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ +} LLWU_Type; + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/*! @name PE1 - LLWU Pin Enable 1 register */ +#define LLWU_PE1_WUPE0_MASK (0x3U) +#define LLWU_PE1_WUPE0_SHIFT (0U) +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) +#define LLWU_PE1_WUPE1_MASK (0xCU) +#define LLWU_PE1_WUPE1_SHIFT (2U) +#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) +#define LLWU_PE1_WUPE2_MASK (0x30U) +#define LLWU_PE1_WUPE2_SHIFT (4U) +#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) +#define LLWU_PE1_WUPE3_MASK (0xC0U) +#define LLWU_PE1_WUPE3_SHIFT (6U) +#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) + +/*! @name PE2 - LLWU Pin Enable 2 register */ +#define LLWU_PE2_WUPE4_MASK (0x3U) +#define LLWU_PE2_WUPE4_SHIFT (0U) +#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) +#define LLWU_PE2_WUPE5_MASK (0xCU) +#define LLWU_PE2_WUPE5_SHIFT (2U) +#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) +#define LLWU_PE2_WUPE6_MASK (0x30U) +#define LLWU_PE2_WUPE6_SHIFT (4U) +#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) +#define LLWU_PE2_WUPE7_MASK (0xC0U) +#define LLWU_PE2_WUPE7_SHIFT (6U) +#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) + +/*! @name PE3 - LLWU Pin Enable 3 register */ +#define LLWU_PE3_WUPE8_MASK (0x3U) +#define LLWU_PE3_WUPE8_SHIFT (0U) +#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) +#define LLWU_PE3_WUPE9_MASK (0xCU) +#define LLWU_PE3_WUPE9_SHIFT (2U) +#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) +#define LLWU_PE3_WUPE10_MASK (0x30U) +#define LLWU_PE3_WUPE10_SHIFT (4U) +#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) +#define LLWU_PE3_WUPE11_MASK (0xC0U) +#define LLWU_PE3_WUPE11_SHIFT (6U) +#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) + +/*! @name PE4 - LLWU Pin Enable 4 register */ +#define LLWU_PE4_WUPE12_MASK (0x3U) +#define LLWU_PE4_WUPE12_SHIFT (0U) +#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) +#define LLWU_PE4_WUPE13_MASK (0xCU) +#define LLWU_PE4_WUPE13_SHIFT (2U) +#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) +#define LLWU_PE4_WUPE14_MASK (0x30U) +#define LLWU_PE4_WUPE14_SHIFT (4U) +#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) +#define LLWU_PE4_WUPE15_MASK (0xC0U) +#define LLWU_PE4_WUPE15_SHIFT (6U) +#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) + +/*! @name ME - LLWU Module Enable register */ +#define LLWU_ME_WUME0_MASK (0x1U) +#define LLWU_ME_WUME0_SHIFT (0U) +#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) +#define LLWU_ME_WUME1_MASK (0x2U) +#define LLWU_ME_WUME1_SHIFT (1U) +#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) +#define LLWU_ME_WUME2_MASK (0x4U) +#define LLWU_ME_WUME2_SHIFT (2U) +#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) +#define LLWU_ME_WUME3_MASK (0x8U) +#define LLWU_ME_WUME3_SHIFT (3U) +#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) +#define LLWU_ME_WUME4_MASK (0x10U) +#define LLWU_ME_WUME4_SHIFT (4U) +#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) +#define LLWU_ME_WUME5_MASK (0x20U) +#define LLWU_ME_WUME5_SHIFT (5U) +#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) +#define LLWU_ME_WUME6_MASK (0x40U) +#define LLWU_ME_WUME6_SHIFT (6U) +#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) +#define LLWU_ME_WUME7_MASK (0x80U) +#define LLWU_ME_WUME7_SHIFT (7U) +#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) + +/*! @name F1 - LLWU Flag 1 register */ +#define LLWU_F1_WUF0_MASK (0x1U) +#define LLWU_F1_WUF0_SHIFT (0U) +#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) +#define LLWU_F1_WUF1_MASK (0x2U) +#define LLWU_F1_WUF1_SHIFT (1U) +#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) +#define LLWU_F1_WUF2_MASK (0x4U) +#define LLWU_F1_WUF2_SHIFT (2U) +#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) +#define LLWU_F1_WUF3_MASK (0x8U) +#define LLWU_F1_WUF3_SHIFT (3U) +#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) +#define LLWU_F1_WUF4_MASK (0x10U) +#define LLWU_F1_WUF4_SHIFT (4U) +#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) +#define LLWU_F1_WUF5_MASK (0x20U) +#define LLWU_F1_WUF5_SHIFT (5U) +#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) +#define LLWU_F1_WUF6_MASK (0x40U) +#define LLWU_F1_WUF6_SHIFT (6U) +#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) +#define LLWU_F1_WUF7_MASK (0x80U) +#define LLWU_F1_WUF7_SHIFT (7U) +#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) + +/*! @name F2 - LLWU Flag 2 register */ +#define LLWU_F2_WUF8_MASK (0x1U) +#define LLWU_F2_WUF8_SHIFT (0U) +#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) +#define LLWU_F2_WUF9_MASK (0x2U) +#define LLWU_F2_WUF9_SHIFT (1U) +#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) +#define LLWU_F2_WUF10_MASK (0x4U) +#define LLWU_F2_WUF10_SHIFT (2U) +#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) +#define LLWU_F2_WUF11_MASK (0x8U) +#define LLWU_F2_WUF11_SHIFT (3U) +#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) +#define LLWU_F2_WUF12_MASK (0x10U) +#define LLWU_F2_WUF12_SHIFT (4U) +#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) +#define LLWU_F2_WUF13_MASK (0x20U) +#define LLWU_F2_WUF13_SHIFT (5U) +#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) +#define LLWU_F2_WUF14_MASK (0x40U) +#define LLWU_F2_WUF14_SHIFT (6U) +#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) +#define LLWU_F2_WUF15_MASK (0x80U) +#define LLWU_F2_WUF15_SHIFT (7U) +#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) + +/*! @name F3 - LLWU Flag 3 register */ +#define LLWU_F3_MWUF0_MASK (0x1U) +#define LLWU_F3_MWUF0_SHIFT (0U) +#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) +#define LLWU_F3_MWUF1_MASK (0x2U) +#define LLWU_F3_MWUF1_SHIFT (1U) +#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) +#define LLWU_F3_MWUF2_MASK (0x4U) +#define LLWU_F3_MWUF2_SHIFT (2U) +#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) +#define LLWU_F3_MWUF3_MASK (0x8U) +#define LLWU_F3_MWUF3_SHIFT (3U) +#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) +#define LLWU_F3_MWUF4_MASK (0x10U) +#define LLWU_F3_MWUF4_SHIFT (4U) +#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) +#define LLWU_F3_MWUF5_MASK (0x20U) +#define LLWU_F3_MWUF5_SHIFT (5U) +#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) +#define LLWU_F3_MWUF6_MASK (0x40U) +#define LLWU_F3_MWUF6_SHIFT (6U) +#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) +#define LLWU_F3_MWUF7_MASK (0x80U) +#define LLWU_F3_MWUF7_SHIFT (7U) +#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) + +/*! @name FILT1 - LLWU Pin Filter 1 register */ +#define LLWU_FILT1_FILTSEL_MASK (0xFU) +#define LLWU_FILT1_FILTSEL_SHIFT (0U) +#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) +#define LLWU_FILT1_FILTE_MASK (0x60U) +#define LLWU_FILT1_FILTE_SHIFT (5U) +#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) +#define LLWU_FILT1_FILTF_MASK (0x80U) +#define LLWU_FILT1_FILTF_SHIFT (7U) +#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) + +/*! @name FILT2 - LLWU Pin Filter 2 register */ +#define LLWU_FILT2_FILTSEL_MASK (0xFU) +#define LLWU_FILT2_FILTSEL_SHIFT (0U) +#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) +#define LLWU_FILT2_FILTE_MASK (0x60U) +#define LLWU_FILT2_FILTE_SHIFT (5U) +#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) +#define LLWU_FILT2_FILTF_MASK (0x80U) +#define LLWU_FILT2_FILTF_SHIFT (7U) +#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) + + +/*! + * @} + */ /* end of group LLWU_Register_Masks */ + + +/* LLWU - Peripheral instance base addresses */ +/** Peripheral LLWU base address */ +#define LLWU_BASE (0x4007C000u) +/** Peripheral LLWU base pointer */ +#define LLWU ((LLWU_Type *)LLWU_BASE) +/** Array initializer of LLWU peripheral base addresses */ +#define LLWU_BASE_ADDRS { LLWU_BASE } +/** Array initializer of LLWU peripheral base pointers */ +#define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } + +/*! + * @} + */ /* end of group LLWU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ + __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ + __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ + __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Low Power Timer Control Status Register */ +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +/*! @name PSR - Low Power Timer Prescale Register */ +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) + +/*! @name CMR - Low Power Timer Compare Register */ +#define LPTMR_CMR_COMPARE_MASK (0xFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) + +/*! @name CNR - Low Power Timer Counter Register */ +#define LPTMR_CNR_COUNTER_MASK (0xFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x40040000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name BAUD - LPUART Baud Rate Register */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) + +/*! @name STAT - LPUART Status Register */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) + +/*! @name CTRL - LPUART Control Register */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) + +/*! @name DATA - LPUART Data Register */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) + +/*! @name MATCH - LPUART Match Address Register */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x40054000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x40055000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer + * @{ + */ + +/** MCG - Register Layout Typedef */ +typedef struct { + __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */ + __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */ + uint8_t RESERVED_0[4]; + __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ + uint8_t RESERVED_1[1]; + __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ + uint8_t RESERVED_2[15]; + __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */ +} MCG_Type; + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/*! @name C1 - MCG Control Register 1 */ +#define MCG_C1_IREFSTEN_MASK (0x1U) +#define MCG_C1_IREFSTEN_SHIFT (0U) +#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) +#define MCG_C1_IRCLKEN_MASK (0x2U) +#define MCG_C1_IRCLKEN_SHIFT (1U) +#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) +#define MCG_C1_CLKS_MASK (0xC0U) +#define MCG_C1_CLKS_SHIFT (6U) +#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) + +/*! @name C2 - MCG Control Register 2 */ +#define MCG_C2_IRCS_MASK (0x1U) +#define MCG_C2_IRCS_SHIFT (0U) +#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) +#define MCG_C2_EREFS0_MASK (0x4U) +#define MCG_C2_EREFS0_SHIFT (2U) +#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) +#define MCG_C2_HGO0_MASK (0x8U) +#define MCG_C2_HGO0_SHIFT (3U) +#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) +#define MCG_C2_RANGE0_MASK (0x30U) +#define MCG_C2_RANGE0_SHIFT (4U) +#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) + +/*! @name S - MCG Status Register */ +#define MCG_S_OSCINIT0_MASK (0x2U) +#define MCG_S_OSCINIT0_SHIFT (1U) +#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) +#define MCG_S_CLKST_MASK (0xCU) +#define MCG_S_CLKST_SHIFT (2U) +#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) + +/*! @name SC - MCG Status and Control Register */ +#define MCG_SC_FCRDIV_MASK (0xEU) +#define MCG_SC_FCRDIV_SHIFT (1U) +#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) + +/*! @name MC - MCG Miscellaneous Control Register */ +#define MCG_MC_LIRC_DIV2_MASK (0x7U) +#define MCG_MC_LIRC_DIV2_SHIFT (0U) +#define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK) +#define MCG_MC_HIRCLPEN_MASK (0x40U) +#define MCG_MC_HIRCLPEN_SHIFT (6U) +#define MCG_MC_HIRCLPEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCLPEN_SHIFT)) & MCG_MC_HIRCLPEN_MASK) +#define MCG_MC_HIRCEN_MASK (0x80U) +#define MCG_MC_HIRCEN_SHIFT (7U) +#define MCG_MC_HIRCEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK) + + +/*! + * @} + */ /* end of group MCG_Register_Masks */ + + +/* MCG - Peripheral instance base addresses */ +/** Peripheral MCG base address */ +#define MCG_BASE (0x40064000u) +/** Peripheral MCG base pointer */ +#define MCG ((MCG_Type *)MCG_BASE) +/** Array initializer of MCG peripheral base addresses */ +#define MCG_BASE_ADDRS { MCG_BASE } +/** Array initializer of MCG peripheral base pointers */ +#define MCG_BASE_PTRS { MCG } + +/*! + * @} + */ /* end of group MCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ + uint8_t RESERVED_1[48]; + __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ +} MCM_Type; + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +#define MCM_PLASC_ASC_MASK (0xFFU) +#define MCM_PLASC_ASC_SHIFT (0U) +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) + +/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +#define MCM_PLAMC_AMC_MASK (0xFFU) +#define MCM_PLAMC_AMC_SHIFT (0U) +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) + +/*! @name PLACR - Platform Control Register */ +#define MCM_PLACR_ARB_MASK (0x200U) +#define MCM_PLACR_ARB_SHIFT (9U) +#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) +#define MCM_PLACR_CFCC_MASK (0x400U) +#define MCM_PLACR_CFCC_SHIFT (10U) +#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) +#define MCM_PLACR_DFCDA_MASK (0x800U) +#define MCM_PLACR_DFCDA_SHIFT (11U) +#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) +#define MCM_PLACR_DFCIC_MASK (0x1000U) +#define MCM_PLACR_DFCIC_SHIFT (12U) +#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) +#define MCM_PLACR_DFCC_MASK (0x2000U) +#define MCM_PLACR_DFCC_SHIFT (13U) +#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) +#define MCM_PLACR_EFDS_MASK (0x4000U) +#define MCM_PLACR_EFDS_SHIFT (14U) +#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) +#define MCM_PLACR_DFCS_MASK (0x8000U) +#define MCM_PLACR_DFCS_SHIFT (15U) +#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) +#define MCM_PLACR_ESFC_MASK (0x10000U) +#define MCM_PLACR_ESFC_SHIFT (16U) +#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) + +/*! @name CPO - Compute Operation Control Register */ +#define MCM_CPO_CPOREQ_MASK (0x1U) +#define MCM_CPO_CPOREQ_SHIFT (0U) +#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) +#define MCM_CPO_CPOACK_MASK (0x2U) +#define MCM_CPO_CPOACK_SHIFT (1U) +#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) +#define MCM_CPO_CPOWOI_MASK (0x4U) +#define MCM_CPO_CPOWOI_SHIFT (2U) +#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) + + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base address */ +#define MCM_BASE (0xF0003000u) +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +/** Array initializer of MCM peripheral base addresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } + +/*! + * @} + */ /* end of group MCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MTB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer + * @{ + */ + +/** MTB - Register Layout Typedef */ +typedef struct { + __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ + __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ + __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ + __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ + uint8_t RESERVED_0[3824]; + __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ + uint8_t RESERVED_1[156]; + __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ + __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ + uint8_t RESERVED_2[8]; + __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ + __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ + __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ + __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ + uint8_t RESERVED_3[8]; + __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ + __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ + __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ + __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ +} MTB_Type; + +/* ---------------------------------------------------------------------------- + -- MTB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MTB_Register_Masks MTB Register Masks + * @{ + */ + +/*! @name POSITION - MTB Position Register */ +#define MTB_POSITION_WRAP_MASK (0x4U) +#define MTB_POSITION_WRAP_SHIFT (2U) +#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) +#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) +#define MTB_POSITION_POINTER_SHIFT (3U) +#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) + +/*! @name MASTER - MTB Master Register */ +#define MTB_MASTER_MASK_MASK (0x1FU) +#define MTB_MASTER_MASK_SHIFT (0U) +#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) +#define MTB_MASTER_TSTARTEN_MASK (0x20U) +#define MTB_MASTER_TSTARTEN_SHIFT (5U) +#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) +#define MTB_MASTER_TSTOPEN_MASK (0x40U) +#define MTB_MASTER_TSTOPEN_SHIFT (6U) +#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) +#define MTB_MASTER_SFRWPRIV_MASK (0x80U) +#define MTB_MASTER_SFRWPRIV_SHIFT (7U) +#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) +#define MTB_MASTER_RAMPRIV_MASK (0x100U) +#define MTB_MASTER_RAMPRIV_SHIFT (8U) +#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) +#define MTB_MASTER_HALTREQ_MASK (0x200U) +#define MTB_MASTER_HALTREQ_SHIFT (9U) +#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) +#define MTB_MASTER_EN_MASK (0x80000000U) +#define MTB_MASTER_EN_SHIFT (31U) +#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) + +/*! @name FLOW - MTB Flow Register */ +#define MTB_FLOW_AUTOSTOP_MASK (0x1U) +#define MTB_FLOW_AUTOSTOP_SHIFT (0U) +#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) +#define MTB_FLOW_AUTOHALT_MASK (0x2U) +#define MTB_FLOW_AUTOHALT_SHIFT (1U) +#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) +#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) +#define MTB_FLOW_WATERMARK_SHIFT (3U) +#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) + +/*! @name BASE - MTB Base Register */ +#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) +#define MTB_BASE_BASEADDR_SHIFT (0U) +#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) + +/*! @name MODECTRL - Integration Mode Control Register */ +#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) +#define MTB_MODECTRL_MODECTRL_SHIFT (0U) +#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) + +/*! @name TAGSET - Claim TAG Set Register */ +#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) +#define MTB_TAGSET_TAGSET_SHIFT (0U) +#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) + +/*! @name TAGCLEAR - Claim TAG Clear Register */ +#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) +#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) +#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) + +/*! @name LOCKACCESS - Lock Access Register */ +#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) +#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) +#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) + +/*! @name LOCKSTAT - Lock Status Register */ +#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) +#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) +#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) + +/*! @name AUTHSTAT - Authentication Status Register */ +#define MTB_AUTHSTAT_BIT0_MASK (0x1U) +#define MTB_AUTHSTAT_BIT0_SHIFT (0U) +#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) +#define MTB_AUTHSTAT_BIT1_MASK (0x2U) +#define MTB_AUTHSTAT_BIT1_SHIFT (1U) +#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) +#define MTB_AUTHSTAT_BIT2_MASK (0x4U) +#define MTB_AUTHSTAT_BIT2_SHIFT (2U) +#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) +#define MTB_AUTHSTAT_BIT3_MASK (0x8U) +#define MTB_AUTHSTAT_BIT3_SHIFT (3U) +#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) + +/*! @name DEVICEARCH - Device Architecture Register */ +#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) +#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) +#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) + +/*! @name DEVICECFG - Device Configuration Register */ +#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) +#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) +#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) + +/*! @name DEVICETYPID - Device Type Identifier Register */ +#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) +#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) +#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) + +/*! @name PERIPHID - Peripheral ID Register */ +#define MTB_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU) +#define MTB_PERIPHID_PERIPHID_SHIFT (0U) +#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID_PERIPHID_SHIFT)) & MTB_PERIPHID_PERIPHID_MASK) + +/* The count of MTB_PERIPHID */ +#define MTB_PERIPHID_COUNT (8U) + +/*! @name COMPID - Component ID Register */ +#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) +#define MTB_COMPID_COMPID_SHIFT (0U) +#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) + +/* The count of MTB_COMPID */ +#define MTB_COMPID_COUNT (4U) + + +/*! + * @} + */ /* end of group MTB_Register_Masks */ + + +/* MTB - Peripheral instance base addresses */ +/** Peripheral MTB base address */ +#define MTB_BASE (0xF0000000u) +/** Peripheral MTB base pointer */ +#define MTB ((MTB_Type *)MTB_BASE) +/** Array initializer of MTB peripheral base addresses */ +#define MTB_BASE_ADDRS { MTB_BASE } +/** Array initializer of MTB peripheral base pointers */ +#define MTB_BASE_PTRS { MTB } + +/*! + * @} + */ /* end of group MTB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MTBDWT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer + * @{ + */ + +/** MTBDWT - Register Layout Typedef */ +typedef struct { + __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + struct { /* offset: 0x20, array step: 0x10 */ + __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ + __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ + __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } COMPARATOR[2]; + uint8_t RESERVED_1[448]; + __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ + uint8_t RESERVED_2[3524]; + __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ + __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ + __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ + __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ +} MTBDWT_Type; + +/* ---------------------------------------------------------------------------- + -- MTBDWT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks + * @{ + */ + +/*! @name CTRL - MTB DWT Control Register */ +#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) +#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) +#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) +#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) +#define MTBDWT_CTRL_NUMCMP_SHIFT (28U) +#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) + +/*! @name COMP - MTB_DWT Comparator Register */ +#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) +#define MTBDWT_COMP_COMP_SHIFT (0U) +#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) + +/* The count of MTBDWT_COMP */ +#define MTBDWT_COMP_COUNT (2U) + +/*! @name MASK - MTB_DWT Comparator Mask Register */ +#define MTBDWT_MASK_MASK_MASK (0x1FU) +#define MTBDWT_MASK_MASK_SHIFT (0U) +#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) + +/* The count of MTBDWT_MASK */ +#define MTBDWT_MASK_COUNT (2U) + +/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ +#define MTBDWT_FCT_FUNCTION_MASK (0xFU) +#define MTBDWT_FCT_FUNCTION_SHIFT (0U) +#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) +#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) +#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) +#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) +#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) +#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) +#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) +#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) +#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) +#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) +#define MTBDWT_FCT_MATCHED_MASK (0x1000000U) +#define MTBDWT_FCT_MATCHED_SHIFT (24U) +#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) + +/* The count of MTBDWT_FCT */ +#define MTBDWT_FCT_COUNT (2U) + +/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ +#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) +#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) +#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) +#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) +#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) +#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) +#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) +#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) +#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) + +/*! @name DEVICECFG - Device Configuration Register */ +#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) +#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) +#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) + +/*! @name DEVICETYPID - Device Type Identifier Register */ +#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) +#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) +#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) + +/*! @name PERIPHID - Peripheral ID Register */ +#define MTBDWT_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU) +#define MTBDWT_PERIPHID_PERIPHID_SHIFT (0U) +#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID_PERIPHID_SHIFT)) & MTBDWT_PERIPHID_PERIPHID_MASK) + +/* The count of MTBDWT_PERIPHID */ +#define MTBDWT_PERIPHID_COUNT (8U) + +/*! @name COMPID - Component ID Register */ +#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) +#define MTBDWT_COMPID_COMPID_SHIFT (0U) +#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) + +/* The count of MTBDWT_COMPID */ +#define MTBDWT_COMPID_COUNT (4U) + + +/*! + * @} + */ /* end of group MTBDWT_Register_Masks */ + + +/* MTBDWT - Peripheral instance base addresses */ +/** Peripheral MTBDWT base address */ +#define MTBDWT_BASE (0xF0001000u) +/** Peripheral MTBDWT base pointer */ +#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) +/** Array initializer of MTBDWT peripheral base addresses */ +#define MTBDWT_BASE_ADDRS { MTBDWT_BASE } +/** Array initializer of MTBDWT peripheral base pointers */ +#define MTBDWT_BASE_PTRS { MTBDWT } + +/*! + * @} + */ /* end of group MTBDWT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer + * @{ + */ + +/** NV - Register Layout Typedef */ +typedef struct { + __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ + __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ + __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ + __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ + __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ + __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ + __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ + __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ + __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ + __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ + __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ + __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ + __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ + __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ +} NV_Type; + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/*! @name BACKKEY3 - Backdoor Comparison Key 3. */ +#define NV_BACKKEY3_KEY_MASK (0xFFU) +#define NV_BACKKEY3_KEY_SHIFT (0U) +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) + +/*! @name BACKKEY2 - Backdoor Comparison Key 2. */ +#define NV_BACKKEY2_KEY_MASK (0xFFU) +#define NV_BACKKEY2_KEY_SHIFT (0U) +#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) + +/*! @name BACKKEY1 - Backdoor Comparison Key 1. */ +#define NV_BACKKEY1_KEY_MASK (0xFFU) +#define NV_BACKKEY1_KEY_SHIFT (0U) +#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) + +/*! @name BACKKEY0 - Backdoor Comparison Key 0. */ +#define NV_BACKKEY0_KEY_MASK (0xFFU) +#define NV_BACKKEY0_KEY_SHIFT (0U) +#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) + +/*! @name BACKKEY7 - Backdoor Comparison Key 7. */ +#define NV_BACKKEY7_KEY_MASK (0xFFU) +#define NV_BACKKEY7_KEY_SHIFT (0U) +#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) + +/*! @name BACKKEY6 - Backdoor Comparison Key 6. */ +#define NV_BACKKEY6_KEY_MASK (0xFFU) +#define NV_BACKKEY6_KEY_SHIFT (0U) +#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) + +/*! @name BACKKEY5 - Backdoor Comparison Key 5. */ +#define NV_BACKKEY5_KEY_MASK (0xFFU) +#define NV_BACKKEY5_KEY_SHIFT (0U) +#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) + +/*! @name BACKKEY4 - Backdoor Comparison Key 4. */ +#define NV_BACKKEY4_KEY_MASK (0xFFU) +#define NV_BACKKEY4_KEY_SHIFT (0U) +#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) + +/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ +#define NV_FPROT3_PROT_MASK (0xFFU) +#define NV_FPROT3_PROT_SHIFT (0U) +#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ +#define NV_FPROT2_PROT_MASK (0xFFU) +#define NV_FPROT2_PROT_SHIFT (0U) +#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ +#define NV_FPROT1_PROT_MASK (0xFFU) +#define NV_FPROT1_PROT_SHIFT (0U) +#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ +#define NV_FPROT0_PROT_MASK (0xFFU) +#define NV_FPROT0_PROT_SHIFT (0U) +#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) + +/*! @name FSEC - Non-volatile Flash Security Register */ +#define NV_FSEC_SEC_MASK (0x3U) +#define NV_FSEC_SEC_SHIFT (0U) +#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) +#define NV_FSEC_FSLACC_MASK (0xCU) +#define NV_FSEC_FSLACC_SHIFT (2U) +#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) +#define NV_FSEC_MEEN_MASK (0x30U) +#define NV_FSEC_MEEN_SHIFT (4U) +#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) +#define NV_FSEC_KEYEN_MASK (0xC0U) +#define NV_FSEC_KEYEN_SHIFT (6U) +#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) + +/*! @name FOPT - Non-volatile Flash Option Register */ +#define NV_FOPT_LPBOOT0_MASK (0x1U) +#define NV_FOPT_LPBOOT0_SHIFT (0U) +#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) +#define NV_FOPT_BOOTPIN_OPT_MASK (0x2U) +#define NV_FOPT_BOOTPIN_OPT_SHIFT (1U) +#define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK) +#define NV_FOPT_NMI_DIS_MASK (0x4U) +#define NV_FOPT_NMI_DIS_SHIFT (2U) +#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) +#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) +#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) +#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) +#define NV_FOPT_LPBOOT1_MASK (0x10U) +#define NV_FOPT_LPBOOT1_SHIFT (4U) +#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) +#define NV_FOPT_FAST_INIT_MASK (0x20U) +#define NV_FOPT_FAST_INIT_SHIFT (5U) +#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) +#define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U) +#define NV_FOPT_BOOTSRC_SEL_SHIFT (6U) +#define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK) + + +/*! + * @} + */ /* end of group NV_Register_Masks */ + + +/* NV - Peripheral instance base addresses */ +/** Peripheral FTFA_FlashConfig base address */ +#define FTFA_FlashConfig_BASE (0x400u) +/** Peripheral FTFA_FlashConfig base pointer */ +#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) +/** Array initializer of NV peripheral base addresses */ +#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } +/** Array initializer of NV peripheral base pointers */ +#define NV_BASE_PTRS { FTFA_FlashConfig } + +/*! + * @} + */ /* end of group NV_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer + * @{ + */ + +/** OSC - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ +} OSC_Type; + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/*! @name CR - OSC Control Register */ +#define OSC_CR_SC16P_MASK (0x1U) +#define OSC_CR_SC16P_SHIFT (0U) +#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) +#define OSC_CR_SC8P_MASK (0x2U) +#define OSC_CR_SC8P_SHIFT (1U) +#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) +#define OSC_CR_SC4P_MASK (0x4U) +#define OSC_CR_SC4P_SHIFT (2U) +#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) +#define OSC_CR_SC2P_MASK (0x8U) +#define OSC_CR_SC2P_SHIFT (3U) +#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) +#define OSC_CR_EREFSTEN_MASK (0x20U) +#define OSC_CR_EREFSTEN_SHIFT (5U) +#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) +#define OSC_CR_ERCLKEN_MASK (0x80U) +#define OSC_CR_ERCLKEN_SHIFT (7U) +#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) + + +/*! + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC0 base address */ +#define OSC0_BASE (0x40065000u) +/** Peripheral OSC0 base pointer */ +#define OSC0 ((OSC_Type *)OSC0_BASE) +/** Array initializer of OSC peripheral base addresses */ +#define OSC_BASE_ADDRS { OSC0_BASE } +/** Array initializer of OSC peripheral base pointers */ +#define OSC_BASE_PTRS { OSC0 } + +/*! + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[220]; + __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ + __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ + uint8_t RESERVED_1[24]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[2]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) + +/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) +#define PIT_LTMR64H_LTH_SHIFT (0U) +#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) + +/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) +#define PIT_LTMR64L_LTL_SHIFT (0U) +#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) + +/*! @name LDVAL - Timer Load Value Register */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (2U) + +/*! @name CVAL - Current Timer Value Register */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (2U) + +/*! @name TCTRL - Timer Control Register */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (2U) + +/*! @name TFLG - Timer Flag Register */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (2U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40037000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { PIT_IRQn, PIT_IRQn } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ + __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ + __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ +#define PMC_LVDSC1_LVDV_MASK (0x3U) +#define PMC_LVDSC1_LVDV_SHIFT (0U) +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) +#define PMC_LVDSC1_LVDRE_MASK (0x10U) +#define PMC_LVDSC1_LVDRE_SHIFT (4U) +#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) +#define PMC_LVDSC1_LVDIE_MASK (0x20U) +#define PMC_LVDSC1_LVDIE_SHIFT (5U) +#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) +#define PMC_LVDSC1_LVDACK_MASK (0x40U) +#define PMC_LVDSC1_LVDACK_SHIFT (6U) +#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) +#define PMC_LVDSC1_LVDF_MASK (0x80U) +#define PMC_LVDSC1_LVDF_SHIFT (7U) +#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) + +/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ +#define PMC_LVDSC2_LVWV_MASK (0x3U) +#define PMC_LVDSC2_LVWV_SHIFT (0U) +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) +#define PMC_LVDSC2_LVWIE_MASK (0x20U) +#define PMC_LVDSC2_LVWIE_SHIFT (5U) +#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) +#define PMC_LVDSC2_LVWACK_MASK (0x40U) +#define PMC_LVDSC2_LVWACK_SHIFT (6U) +#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) +#define PMC_LVDSC2_LVWF_MASK (0x80U) +#define PMC_LVDSC2_LVWF_SHIFT (7U) +#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) + +/*! @name REGSC - Regulator Status And Control register */ +#define PMC_REGSC_BGBE_MASK (0x1U) +#define PMC_REGSC_BGBE_SHIFT (0U) +#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) +#define PMC_REGSC_REGONS_MASK (0x4U) +#define PMC_REGSC_REGONS_SHIFT (2U) +#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) +#define PMC_REGSC_ACKISO_MASK (0x8U) +#define PMC_REGSC_ACKISO_SHIFT (3U) +#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) +#define PMC_REGSC_BGEN_MASK (0x10U) +#define PMC_REGSC_BGEN_SHIFT (4U) +#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) +#define PMC_REGSC_VLPO_MASK (0x40U) +#define PMC_REGSC_VLPO_SHIFT (6U) +#define PMC_REGSC_VLPO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK) + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +/** Peripheral PMC base address */ +#define PMC_BASE (0x4007D000u) +/** Peripheral PMC base pointer */ +#define PMC ((PMC_Type *)PMC_BASE) +/** Array initializer of PMC peripheral base addresses */ +#define PMC_BASE_ADDRS { PMC_BASE } +/** Array initializer of PMC peripheral base pointers */ +#define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { PMC_IRQn } + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ + __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ + __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name PCR - Pin Control Register n */ +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) +#define PORT_PCR_SRE_MASK (0x4U) +#define PORT_PCR_SRE_SHIFT (2U) +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) +#define PORT_PCR_MUX_MASK (0x700U) +#define PORT_PCR_MUX_SHIFT (8U) +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) +#define PORT_PCR_IRQC_MASK (0xF0000U) +#define PORT_PCR_IRQC_SHIFT (16U) +#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) +#define PORT_PCR_ISF_MASK (0x1000000U) +#define PORT_PCR_ISF_SHIFT (24U) +#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + +/*! @name GPCLR - Global Pin Control Low Register */ +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) +#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCLR_GPWE_SHIFT (16U) +#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) + +/*! @name GPCHR - Global Pin Control High Register */ +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) +#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCHR_GPWE_SHIFT (16U) +#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) + +/*! @name ISFR - Interrupt Status Flag Register */ +#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) +#define PORT_ISFR_ISF_SHIFT (0U) +#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORTA base address */ +#define PORTA_BASE (0x40049000u) +/** Peripheral PORTA base pointer */ +#define PORTA ((PORT_Type *)PORTA_BASE) +/** Peripheral PORTB base address */ +#define PORTB_BASE (0x4004A000u) +/** Peripheral PORTB base pointer */ +#define PORTB ((PORT_Type *)PORTB_BASE) +/** Peripheral PORTC base address */ +#define PORTC_BASE (0x4004B000u) +/** Peripheral PORTC base pointer */ +#define PORTC ((PORT_Type *)PORTC_BASE) +/** Peripheral PORTD base address */ +#define PORTD_BASE (0x4004C000u) +/** Peripheral PORTD base pointer */ +#define PORTD ((PORT_Type *)PORTD_BASE) +/** Peripheral PORTE base address */ +#define PORTE_BASE (0x4004D000u) +/** Peripheral PORTE base pointer */ +#define PORTE ((PORT_Type *)PORTE_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn } + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer + * @{ + */ + +/** RCM - Register Layout Typedef */ +typedef struct { + __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ + __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ + uint8_t RESERVED_0[2]; + __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ + __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ + __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */ + __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ + __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ + __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ +} RCM_Type; + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/*! @name SRS0 - System Reset Status Register 0 */ +#define RCM_SRS0_WAKEUP_MASK (0x1U) +#define RCM_SRS0_WAKEUP_SHIFT (0U) +#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) +#define RCM_SRS0_LVD_MASK (0x2U) +#define RCM_SRS0_LVD_SHIFT (1U) +#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) +#define RCM_SRS0_WDOG_MASK (0x20U) +#define RCM_SRS0_WDOG_SHIFT (5U) +#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) +#define RCM_SRS0_PIN_MASK (0x40U) +#define RCM_SRS0_PIN_SHIFT (6U) +#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) +#define RCM_SRS0_POR_MASK (0x80U) +#define RCM_SRS0_POR_SHIFT (7U) +#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) + +/*! @name SRS1 - System Reset Status Register 1 */ +#define RCM_SRS1_LOCKUP_MASK (0x2U) +#define RCM_SRS1_LOCKUP_SHIFT (1U) +#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) +#define RCM_SRS1_SW_MASK (0x4U) +#define RCM_SRS1_SW_SHIFT (2U) +#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) +#define RCM_SRS1_MDM_AP_MASK (0x8U) +#define RCM_SRS1_MDM_AP_SHIFT (3U) +#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) +#define RCM_SRS1_SACKERR_MASK (0x20U) +#define RCM_SRS1_SACKERR_SHIFT (5U) +#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) + +/*! @name RPFC - Reset Pin Filter Control register */ +#define RCM_RPFC_RSTFLTSRW_MASK (0x3U) +#define RCM_RPFC_RSTFLTSRW_SHIFT (0U) +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) +#define RCM_RPFC_RSTFLTSS_MASK (0x4U) +#define RCM_RPFC_RSTFLTSS_SHIFT (2U) +#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) + +/*! @name RPFW - Reset Pin Filter Width register */ +#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) +#define RCM_RPFW_RSTFLTSEL_SHIFT (0U) +#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) + +/*! @name FM - Force Mode Register */ +#define RCM_FM_FORCEROM_MASK (0x6U) +#define RCM_FM_FORCEROM_SHIFT (1U) +#define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) + +/*! @name MR - Mode Register */ +#define RCM_MR_BOOTROM_MASK (0x6U) +#define RCM_MR_BOOTROM_SHIFT (1U) +#define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) + +/*! @name SSRS0 - Sticky System Reset Status Register 0 */ +#define RCM_SSRS0_SWAKEUP_MASK (0x1U) +#define RCM_SSRS0_SWAKEUP_SHIFT (0U) +#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK) +#define RCM_SSRS0_SLVD_MASK (0x2U) +#define RCM_SSRS0_SLVD_SHIFT (1U) +#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK) +#define RCM_SSRS0_SWDOG_MASK (0x20U) +#define RCM_SSRS0_SWDOG_SHIFT (5U) +#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK) +#define RCM_SSRS0_SPIN_MASK (0x40U) +#define RCM_SSRS0_SPIN_SHIFT (6U) +#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK) +#define RCM_SSRS0_SPOR_MASK (0x80U) +#define RCM_SSRS0_SPOR_SHIFT (7U) +#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK) + +/*! @name SSRS1 - Sticky System Reset Status Register 1 */ +#define RCM_SSRS1_SLOCKUP_MASK (0x2U) +#define RCM_SSRS1_SLOCKUP_SHIFT (1U) +#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK) +#define RCM_SSRS1_SSW_MASK (0x4U) +#define RCM_SSRS1_SSW_SHIFT (2U) +#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK) +#define RCM_SSRS1_SMDM_AP_MASK (0x8U) +#define RCM_SSRS1_SMDM_AP_SHIFT (3U) +#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK) +#define RCM_SSRS1_SSACKERR_MASK (0x20U) +#define RCM_SSRS1_SSACKERR_SHIFT (5U) +#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK) + + +/*! + * @} + */ /* end of group RCM_Register_Masks */ + + +/* RCM - Peripheral instance base addresses */ +/** Peripheral RCM base address */ +#define RCM_BASE (0x4007F000u) +/** Peripheral RCM base pointer */ +#define RCM ((RCM_Type *)RCM_BASE) +/** Array initializer of RCM peripheral base addresses */ +#define RCM_BASE_ADDRS { RCM_BASE } +/** Array initializer of RCM peripheral base pointers */ +#define RCM_BASE_PTRS { RCM } + +/*! + * @} + */ /* end of group RCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer + * @{ + */ + +/** RFSYS - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ +} RFSYS_Type; + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/*! @name REG - Register file register */ +#define RFSYS_REG_LL_MASK (0xFFU) +#define RFSYS_REG_LL_SHIFT (0U) +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) +#define RFSYS_REG_LH_MASK (0xFF00U) +#define RFSYS_REG_LH_SHIFT (8U) +#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) +#define RFSYS_REG_HL_MASK (0xFF0000U) +#define RFSYS_REG_HL_SHIFT (16U) +#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) +#define RFSYS_REG_HH_MASK (0xFF000000U) +#define RFSYS_REG_HH_SHIFT (24U) +#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) + +/* The count of RFSYS_REG */ +#define RFSYS_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFSYS_Register_Masks */ + + +/* RFSYS - Peripheral instance base addresses */ +/** Peripheral RFSYS base address */ +#define RFSYS_BASE (0x40041000u) +/** Peripheral RFSYS base pointer */ +#define RFSYS ((RFSYS_Type *)RFSYS_BASE) +/** Array initializer of RFSYS peripheral base addresses */ +#define RFSYS_BASE_ADDRS { RFSYS_BASE } +/** Array initializer of RFSYS peripheral base pointers */ +#define RFSYS_BASE_PTRS { RFSYS } + +/*! + * @} + */ /* end of group RFSYS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer + * @{ + */ + +/** ROM - Register Layout Typedef */ +typedef struct { + __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ + __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ + uint8_t RESERVED_0[4028]; + __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ + __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ + __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ + __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ + __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ + __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ + __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ + __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ + __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ + __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ +} ROM_Type; + +/* ---------------------------------------------------------------------------- + -- ROM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROM_Register_Masks ROM Register Masks + * @{ + */ + +/*! @name ENTRY - Entry */ +#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) +#define ROM_ENTRY_ENTRY_SHIFT (0U) +#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) + +/* The count of ROM_ENTRY */ +#define ROM_ENTRY_COUNT (3U) + +/*! @name TABLEMARK - End of Table Marker Register */ +#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) +#define ROM_TABLEMARK_MARK_SHIFT (0U) +#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) + +/*! @name SYSACCESS - System Access Register */ +#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) +#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) +#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) + +/*! @name PERIPHID4 - Peripheral ID Register */ +#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID4_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) + +/*! @name PERIPHID5 - Peripheral ID Register */ +#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID5_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) + +/*! @name PERIPHID6 - Peripheral ID Register */ +#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID6_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) + +/*! @name PERIPHID7 - Peripheral ID Register */ +#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID7_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) + +/*! @name PERIPHID0 - Peripheral ID Register */ +#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID0_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) + +/*! @name PERIPHID1 - Peripheral ID Register */ +#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID1_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) + +/*! @name PERIPHID2 - Peripheral ID Register */ +#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID2_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) + +/*! @name PERIPHID3 - Peripheral ID Register */ +#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) +#define ROM_PERIPHID3_PERIPHID_SHIFT (0U) +#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) + +/*! @name COMPID - Component ID Register */ +#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) +#define ROM_COMPID_COMPID_SHIFT (0U) +#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) + +/* The count of ROM_COMPID */ +#define ROM_COMPID_COUNT (4U) + + +/*! + * @} + */ /* end of group ROM_Register_Masks */ + + +/* ROM - Peripheral instance base addresses */ +/** Peripheral ROM base address */ +#define ROM_BASE (0xF0002000u) +/** Peripheral ROM base pointer */ +#define ROM ((ROM_Type *)ROM_BASE) +/** Array initializer of ROM peripheral base addresses */ +#define ROM_BASE_ADDRS { ROM_BASE } +/** Array initializer of ROM peripheral base pointers */ +#define ROM_BASE_PTRS { ROM } + +/*! + * @} + */ /* end of group ROM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name TSR - RTC Time Seconds Register */ +#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) +#define RTC_TSR_TSR_SHIFT (0U) +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) + +/*! @name TPR - RTC Time Prescaler Register */ +#define RTC_TPR_TPR_MASK (0xFFFFU) +#define RTC_TPR_TPR_SHIFT (0U) +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) + +/*! @name TAR - RTC Time Alarm Register */ +#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) +#define RTC_TAR_TAR_SHIFT (0U) +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) + +/*! @name TCR - RTC Time Compensation Register */ +#define RTC_TCR_TCR_MASK (0xFFU) +#define RTC_TCR_TCR_SHIFT (0U) +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) +#define RTC_TCR_CIR_MASK (0xFF00U) +#define RTC_TCR_CIR_SHIFT (8U) +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) +#define RTC_TCR_TCV_MASK (0xFF0000U) +#define RTC_TCR_TCV_SHIFT (16U) +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) +#define RTC_TCR_CIC_MASK (0xFF000000U) +#define RTC_TCR_CIC_SHIFT (24U) +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) + +/*! @name CR - RTC Control Register */ +#define RTC_CR_SWR_MASK (0x1U) +#define RTC_CR_SWR_SHIFT (0U) +#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) +#define RTC_CR_WPE_MASK (0x2U) +#define RTC_CR_WPE_SHIFT (1U) +#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) +#define RTC_CR_SUP_MASK (0x4U) +#define RTC_CR_SUP_SHIFT (2U) +#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) +#define RTC_CR_UM_MASK (0x8U) +#define RTC_CR_UM_SHIFT (3U) +#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) +#define RTC_CR_WPS_MASK (0x10U) +#define RTC_CR_WPS_SHIFT (4U) +#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) +#define RTC_CR_OSCE_MASK (0x100U) +#define RTC_CR_OSCE_SHIFT (8U) +#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) +#define RTC_CR_CLKO_MASK (0x200U) +#define RTC_CR_CLKO_SHIFT (9U) +#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) +#define RTC_CR_SC16P_MASK (0x400U) +#define RTC_CR_SC16P_SHIFT (10U) +#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) +#define RTC_CR_SC8P_MASK (0x800U) +#define RTC_CR_SC8P_SHIFT (11U) +#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) +#define RTC_CR_SC4P_MASK (0x1000U) +#define RTC_CR_SC4P_SHIFT (12U) +#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) +#define RTC_CR_SC2P_MASK (0x2000U) +#define RTC_CR_SC2P_SHIFT (13U) +#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) + +/*! @name SR - RTC Status Register */ +#define RTC_SR_TIF_MASK (0x1U) +#define RTC_SR_TIF_SHIFT (0U) +#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) +#define RTC_SR_TOF_MASK (0x2U) +#define RTC_SR_TOF_SHIFT (1U) +#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) +#define RTC_SR_TAF_MASK (0x4U) +#define RTC_SR_TAF_SHIFT (2U) +#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) +#define RTC_SR_TCE_MASK (0x10U) +#define RTC_SR_TCE_SHIFT (4U) +#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) + +/*! @name LR - RTC Lock Register */ +#define RTC_LR_TCL_MASK (0x8U) +#define RTC_LR_TCL_SHIFT (3U) +#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) +#define RTC_LR_CRL_MASK (0x10U) +#define RTC_LR_CRL_SHIFT (4U) +#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) +#define RTC_LR_SRL_MASK (0x20U) +#define RTC_LR_SRL_SHIFT (5U) +#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) +#define RTC_LR_LRL_MASK (0x40U) +#define RTC_LR_LRL_SHIFT (6U) +#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) + +/*! @name IER - RTC Interrupt Enable Register */ +#define RTC_IER_TIIE_MASK (0x1U) +#define RTC_IER_TIIE_SHIFT (0U) +#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) +#define RTC_IER_TOIE_MASK (0x2U) +#define RTC_IER_TOIE_SHIFT (1U) +#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) +#define RTC_IER_TAIE_MASK (0x4U) +#define RTC_IER_TAIE_SHIFT (2U) +#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) +#define RTC_IER_TSIE_MASK (0x10U) +#define RTC_IER_TSIE_SHIFT (4U) +#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) +#define RTC_IER_WPON_MASK (0x80U) +#define RTC_IER_WPON_SHIFT (7U) +#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4003D000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ + uint8_t RESERVED_0[4096]; + __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ + __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ + uint8_t RESERVED_3[8]; + __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ + __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ + __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ + __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ + __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ + __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ + uint8_t RESERVED_6[4]; + __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ + __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ + __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ + uint8_t RESERVED_7[156]; + __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ + __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */ +} SIM_Type; + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/*! @name SOPT1 - System Options Register 1 */ +#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U) +#define SIM_SOPT1_OSC32KOUT_SHIFT (16U) +#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK) +#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) +#define SIM_SOPT1_OSC32KSEL_SHIFT (18U) +#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) + +/*! @name SOPT2 - System Options Register 2 */ +#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) +#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) +#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) +#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) +#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) +#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) +#define SIM_SOPT2_USBSRC_MASK (0x40000U) +#define SIM_SOPT2_USBSRC_SHIFT (18U) +#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) +#define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U) +#define SIM_SOPT2_FLEXIOSRC_SHIFT (22U) +#define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK) +#define SIM_SOPT2_TPMSRC_MASK (0x3000000U) +#define SIM_SOPT2_TPMSRC_SHIFT (24U) +#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) +#define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U) +#define SIM_SOPT2_LPUART0SRC_SHIFT (26U) +#define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK) +#define SIM_SOPT2_LPUART1SRC_MASK (0x30000000U) +#define SIM_SOPT2_LPUART1SRC_SHIFT (28U) +#define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART1SRC_SHIFT)) & SIM_SOPT2_LPUART1SRC_MASK) + +/*! @name SOPT4 - System Options Register 4 */ +#define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U) +#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U) +#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK) +#define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U) +#define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U) +#define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK) +#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U) +#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U) +#define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK) +#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U) +#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U) +#define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK) +#define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U) +#define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U) +#define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK) + +/*! @name SOPT5 - System Options Register 5 */ +#define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U) +#define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U) +#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK) +#define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U) +#define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U) +#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) +#define SIM_SOPT5_LPUART1TXSRC_MASK (0x30U) +#define SIM_SOPT5_LPUART1TXSRC_SHIFT (4U) +#define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK) +#define SIM_SOPT5_LPUART1RXSRC_MASK (0x40U) +#define SIM_SOPT5_LPUART1RXSRC_SHIFT (6U) +#define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK) +#define SIM_SOPT5_LPUART0ODE_MASK (0x10000U) +#define SIM_SOPT5_LPUART0ODE_SHIFT (16U) +#define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK) +#define SIM_SOPT5_LPUART1ODE_MASK (0x20000U) +#define SIM_SOPT5_LPUART1ODE_SHIFT (17U) +#define SIM_SOPT5_LPUART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1ODE_SHIFT)) & SIM_SOPT5_LPUART1ODE_MASK) +#define SIM_SOPT5_UART2ODE_MASK (0x40000U) +#define SIM_SOPT5_UART2ODE_SHIFT (18U) +#define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK) + +/*! @name SOPT7 - System Options Register 7 */ +#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) +#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) +#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) +#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) +#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) +#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) +#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) +#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) +#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) + +/*! @name SDID - System Device Identification Register */ +#define SIM_SDID_PINID_MASK (0xFU) +#define SIM_SDID_PINID_SHIFT (0U) +#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) +#define SIM_SDID_REVID_MASK (0xF000U) +#define SIM_SDID_REVID_SHIFT (12U) +#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) +#define SIM_SDID_SRAMSIZE_MASK (0xF0000U) +#define SIM_SDID_SRAMSIZE_SHIFT (16U) +#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) +#define SIM_SDID_SERIESID_MASK (0xF00000U) +#define SIM_SDID_SERIESID_SHIFT (20U) +#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) +#define SIM_SDID_SUBFAMID_MASK (0xF000000U) +#define SIM_SDID_SUBFAMID_SHIFT (24U) +#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) +#define SIM_SDID_FAMID_MASK (0xF0000000U) +#define SIM_SDID_FAMID_SHIFT (28U) +#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) + +/*! @name SCGC4 - System Clock Gating Control Register 4 */ +#define SIM_SCGC4_I2C0_MASK (0x40U) +#define SIM_SCGC4_I2C0_SHIFT (6U) +#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) +#define SIM_SCGC4_I2C1_MASK (0x80U) +#define SIM_SCGC4_I2C1_SHIFT (7U) +#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) +#define SIM_SCGC4_UART2_MASK (0x1000U) +#define SIM_SCGC4_UART2_SHIFT (12U) +#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) +#define SIM_SCGC4_USBFS_MASK (0x40000U) +#define SIM_SCGC4_USBFS_SHIFT (18U) +#define SIM_SCGC4_USBFS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBFS_SHIFT)) & SIM_SCGC4_USBFS_MASK) +#define SIM_SCGC4_CMP0_MASK (0x80000U) +#define SIM_SCGC4_CMP0_SHIFT (19U) +#define SIM_SCGC4_CMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK) +#define SIM_SCGC4_VREF_MASK (0x100000U) +#define SIM_SCGC4_VREF_SHIFT (20U) +#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) +#define SIM_SCGC4_SPI0_MASK (0x400000U) +#define SIM_SCGC4_SPI0_SHIFT (22U) +#define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK) +#define SIM_SCGC4_SPI1_MASK (0x800000U) +#define SIM_SCGC4_SPI1_SHIFT (23U) +#define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK) + +/*! @name SCGC5 - System Clock Gating Control Register 5 */ +#define SIM_SCGC5_LPTMR_MASK (0x1U) +#define SIM_SCGC5_LPTMR_SHIFT (0U) +#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) +#define SIM_SCGC5_PORTA_MASK (0x200U) +#define SIM_SCGC5_PORTA_SHIFT (9U) +#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) +#define SIM_SCGC5_PORTB_MASK (0x400U) +#define SIM_SCGC5_PORTB_SHIFT (10U) +#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) +#define SIM_SCGC5_PORTC_MASK (0x800U) +#define SIM_SCGC5_PORTC_SHIFT (11U) +#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) +#define SIM_SCGC5_PORTD_MASK (0x1000U) +#define SIM_SCGC5_PORTD_SHIFT (12U) +#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) +#define SIM_SCGC5_PORTE_MASK (0x2000U) +#define SIM_SCGC5_PORTE_SHIFT (13U) +#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) +#define SIM_SCGC5_LPUART0_MASK (0x100000U) +#define SIM_SCGC5_LPUART0_SHIFT (20U) +#define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK) +#define SIM_SCGC5_LPUART1_MASK (0x200000U) +#define SIM_SCGC5_LPUART1_SHIFT (21U) +#define SIM_SCGC5_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK) +#define SIM_SCGC5_FLEXIO_MASK (0x80000000U) +#define SIM_SCGC5_FLEXIO_SHIFT (31U) +#define SIM_SCGC5_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO_SHIFT)) & SIM_SCGC5_FLEXIO_MASK) + +/*! @name SCGC6 - System Clock Gating Control Register 6 */ +#define SIM_SCGC6_FTF_MASK (0x1U) +#define SIM_SCGC6_FTF_SHIFT (0U) +#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) +#define SIM_SCGC6_DMAMUX_MASK (0x2U) +#define SIM_SCGC6_DMAMUX_SHIFT (1U) +#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) +#define SIM_SCGC6_CRC_MASK (0x40000U) +#define SIM_SCGC6_CRC_SHIFT (18U) +#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) +#define SIM_SCGC6_PIT_MASK (0x800000U) +#define SIM_SCGC6_PIT_SHIFT (23U) +#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) +#define SIM_SCGC6_TPM0_MASK (0x1000000U) +#define SIM_SCGC6_TPM0_SHIFT (24U) +#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) +#define SIM_SCGC6_TPM1_MASK (0x2000000U) +#define SIM_SCGC6_TPM1_SHIFT (25U) +#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) +#define SIM_SCGC6_TPM2_MASK (0x4000000U) +#define SIM_SCGC6_TPM2_SHIFT (26U) +#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) +#define SIM_SCGC6_ADC0_MASK (0x8000000U) +#define SIM_SCGC6_ADC0_SHIFT (27U) +#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) +#define SIM_SCGC6_RTC_MASK (0x20000000U) +#define SIM_SCGC6_RTC_SHIFT (29U) +#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) + +/*! @name SCGC7 - System Clock Gating Control Register 7 */ +#define SIM_SCGC7_DMA_MASK (0x100U) +#define SIM_SCGC7_DMA_SHIFT (8U) +#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) + +/*! @name CLKDIV1 - System Clock Divider Register 1 */ +#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) +#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) +#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) +#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) +#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) +#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) + +/*! @name FCFG1 - Flash Configuration Register 1 */ +#define SIM_FCFG1_FLASHDIS_MASK (0x1U) +#define SIM_FCFG1_FLASHDIS_SHIFT (0U) +#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) +#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) +#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) +#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) +#define SIM_FCFG1_PFSIZE_MASK (0xF000000U) +#define SIM_FCFG1_PFSIZE_SHIFT (24U) +#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) + +/*! @name FCFG2 - Flash Configuration Register 2 */ +#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) +#define SIM_FCFG2_MAXADDR0_SHIFT (24U) +#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) + +/*! @name UIDMH - Unique Identification Register Mid-High */ +#define SIM_UIDMH_UID_MASK (0xFFFFU) +#define SIM_UIDMH_UID_SHIFT (0U) +#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) + +/*! @name UIDML - Unique Identification Register Mid Low */ +#define SIM_UIDML_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDML_UID_SHIFT (0U) +#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) + +/*! @name UIDL - Unique Identification Register Low */ +#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDL_UID_SHIFT (0U) +#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) + +/*! @name COPC - COP Control Register */ +#define SIM_COPC_COPW_MASK (0x1U) +#define SIM_COPC_COPW_SHIFT (0U) +#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK) +#define SIM_COPC_COPCLKS_MASK (0x2U) +#define SIM_COPC_COPCLKS_SHIFT (1U) +#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK) +#define SIM_COPC_COPT_MASK (0xCU) +#define SIM_COPC_COPT_SHIFT (2U) +#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK) +#define SIM_COPC_COPSTPEN_MASK (0x10U) +#define SIM_COPC_COPSTPEN_SHIFT (4U) +#define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK) +#define SIM_COPC_COPDBGEN_MASK (0x20U) +#define SIM_COPC_COPDBGEN_SHIFT (5U) +#define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK) +#define SIM_COPC_COPCLKSEL_MASK (0xC0U) +#define SIM_COPC_COPCLKSEL_SHIFT (6U) +#define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK) + +/*! @name SRVCOP - Service COP */ +#define SIM_SRVCOP_SRVCOP_MASK (0xFFU) +#define SIM_SRVCOP_SRVCOP_SHIFT (0U) +#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK) + + +/*! + * @} + */ /* end of group SIM_Register_Masks */ + + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM base address */ +#define SIM_BASE (0x40047000u) +/** Peripheral SIM base pointer */ +#define SIM ((SIM_Type *)SIM_BASE) +/** Array initializer of SIM peripheral base addresses */ +#define SIM_BASE_ADDRS { SIM_BASE } +/** Array initializer of SIM peripheral base pointers */ +#define SIM_BASE_PTRS { SIM } + +/*! + * @} + */ /* end of group SIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer + * @{ + */ + +/** SMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ + __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ + __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ + __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ +} SMC_Type; + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/*! @name PMPROT - Power Mode Protection register */ +#define SMC_PMPROT_AVLLS_MASK (0x2U) +#define SMC_PMPROT_AVLLS_SHIFT (1U) +#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) +#define SMC_PMPROT_ALLS_MASK (0x8U) +#define SMC_PMPROT_ALLS_SHIFT (3U) +#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) +#define SMC_PMPROT_AVLP_MASK (0x20U) +#define SMC_PMPROT_AVLP_SHIFT (5U) +#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) + +/*! @name PMCTRL - Power Mode Control register */ +#define SMC_PMCTRL_STOPM_MASK (0x7U) +#define SMC_PMCTRL_STOPM_SHIFT (0U) +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) +#define SMC_PMCTRL_STOPA_MASK (0x8U) +#define SMC_PMCTRL_STOPA_SHIFT (3U) +#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) +#define SMC_PMCTRL_RUNM_MASK (0x60U) +#define SMC_PMCTRL_RUNM_SHIFT (5U) +#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) + +/*! @name STOPCTRL - Stop Control Register */ +#define SMC_STOPCTRL_VLLSM_MASK (0x7U) +#define SMC_STOPCTRL_VLLSM_SHIFT (0U) +#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) +#define SMC_STOPCTRL_LPOPO_MASK (0x8U) +#define SMC_STOPCTRL_LPOPO_SHIFT (3U) +#define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK) +#define SMC_STOPCTRL_PORPO_MASK (0x20U) +#define SMC_STOPCTRL_PORPO_SHIFT (5U) +#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) +#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) +#define SMC_STOPCTRL_PSTOPO_SHIFT (6U) +#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) + +/*! @name PMSTAT - Power Mode Status register */ +#define SMC_PMSTAT_PMSTAT_MASK (0xFFU) +#define SMC_PMSTAT_PMSTAT_SHIFT (0U) +#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) + + +/*! + * @} + */ /* end of group SMC_Register_Masks */ + + +/* SMC - Peripheral instance base addresses */ +/** Peripheral SMC base address */ +#define SMC_BASE (0x4007E000u) +/** Peripheral SMC base pointer */ +#define SMC ((SMC_Type *)SMC_BASE) +/** Array initializer of SMC peripheral base addresses */ +#define SMC_BASE_ADDRS { SMC_BASE } +/** Array initializer of SMC peripheral base pointers */ +#define SMC_BASE_PTRS { SMC } + +/*! + * @} + */ /* end of group SMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */ + __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */ + __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */ + __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */ + __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */ + __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ + __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */ + __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ + uint8_t RESERVED_0[2]; + __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ + __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name S - SPI Status Register */ +#define SPI_S_RFIFOEF_MASK (0x1U) +#define SPI_S_RFIFOEF_SHIFT (0U) +#define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK) +#define SPI_S_TXFULLF_MASK (0x2U) +#define SPI_S_TXFULLF_SHIFT (1U) +#define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK) +#define SPI_S_TNEAREF_MASK (0x4U) +#define SPI_S_TNEAREF_SHIFT (2U) +#define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK) +#define SPI_S_RNFULLF_MASK (0x8U) +#define SPI_S_RNFULLF_SHIFT (3U) +#define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK) +#define SPI_S_MODF_MASK (0x10U) +#define SPI_S_MODF_SHIFT (4U) +#define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) +#define SPI_S_SPTEF_MASK (0x20U) +#define SPI_S_SPTEF_SHIFT (5U) +#define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) +#define SPI_S_SPMF_MASK (0x40U) +#define SPI_S_SPMF_SHIFT (6U) +#define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) +#define SPI_S_SPRF_MASK (0x80U) +#define SPI_S_SPRF_SHIFT (7U) +#define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) + +/*! @name BR - SPI Baud Rate Register */ +#define SPI_BR_SPR_MASK (0xFU) +#define SPI_BR_SPR_SHIFT (0U) +#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) +#define SPI_BR_SPPR_MASK (0x70U) +#define SPI_BR_SPPR_SHIFT (4U) +#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) + +/*! @name C2 - SPI Control Register 2 */ +#define SPI_C2_SPC0_MASK (0x1U) +#define SPI_C2_SPC0_SHIFT (0U) +#define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) +#define SPI_C2_SPISWAI_MASK (0x2U) +#define SPI_C2_SPISWAI_SHIFT (1U) +#define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) +#define SPI_C2_RXDMAE_MASK (0x4U) +#define SPI_C2_RXDMAE_SHIFT (2U) +#define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK) +#define SPI_C2_BIDIROE_MASK (0x8U) +#define SPI_C2_BIDIROE_SHIFT (3U) +#define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) +#define SPI_C2_MODFEN_MASK (0x10U) +#define SPI_C2_MODFEN_SHIFT (4U) +#define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) +#define SPI_C2_TXDMAE_MASK (0x20U) +#define SPI_C2_TXDMAE_SHIFT (5U) +#define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK) +#define SPI_C2_SPIMODE_MASK (0x40U) +#define SPI_C2_SPIMODE_SHIFT (6U) +#define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK) +#define SPI_C2_SPMIE_MASK (0x80U) +#define SPI_C2_SPMIE_SHIFT (7U) +#define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) + +/*! @name C1 - SPI Control Register 1 */ +#define SPI_C1_LSBFE_MASK (0x1U) +#define SPI_C1_LSBFE_SHIFT (0U) +#define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) +#define SPI_C1_SSOE_MASK (0x2U) +#define SPI_C1_SSOE_SHIFT (1U) +#define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) +#define SPI_C1_CPHA_MASK (0x4U) +#define SPI_C1_CPHA_SHIFT (2U) +#define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) +#define SPI_C1_CPOL_MASK (0x8U) +#define SPI_C1_CPOL_SHIFT (3U) +#define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) +#define SPI_C1_MSTR_MASK (0x10U) +#define SPI_C1_MSTR_SHIFT (4U) +#define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) +#define SPI_C1_SPTIE_MASK (0x20U) +#define SPI_C1_SPTIE_SHIFT (5U) +#define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) +#define SPI_C1_SPE_MASK (0x40U) +#define SPI_C1_SPE_SHIFT (6U) +#define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) +#define SPI_C1_SPIE_MASK (0x80U) +#define SPI_C1_SPIE_SHIFT (7U) +#define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) + +/*! @name ML - SPI Match Register low */ +#define SPI_ML_Bits_MASK (0xFFU) +#define SPI_ML_Bits_SHIFT (0U) +#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK) + +/*! @name MH - SPI match register high */ +#define SPI_MH_Bits_MASK (0xFFU) +#define SPI_MH_Bits_SHIFT (0U) +#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK) + +/*! @name DL - SPI Data Register low */ +#define SPI_DL_Bits_MASK (0xFFU) +#define SPI_DL_Bits_SHIFT (0U) +#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK) + +/*! @name DH - SPI data register high */ +#define SPI_DH_Bits_MASK (0xFFU) +#define SPI_DH_Bits_SHIFT (0U) +#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK) + +/*! @name CI - SPI clear interrupt register */ +#define SPI_CI_SPRFCI_MASK (0x1U) +#define SPI_CI_SPRFCI_SHIFT (0U) +#define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK) +#define SPI_CI_SPTEFCI_MASK (0x2U) +#define SPI_CI_SPTEFCI_SHIFT (1U) +#define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK) +#define SPI_CI_RNFULLFCI_MASK (0x4U) +#define SPI_CI_RNFULLFCI_SHIFT (2U) +#define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK) +#define SPI_CI_TNEAREFCI_MASK (0x8U) +#define SPI_CI_TNEAREFCI_SHIFT (3U) +#define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK) +#define SPI_CI_RXFOF_MASK (0x10U) +#define SPI_CI_RXFOF_SHIFT (4U) +#define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK) +#define SPI_CI_TXFOF_MASK (0x20U) +#define SPI_CI_TXFOF_SHIFT (5U) +#define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK) +#define SPI_CI_RXFERR_MASK (0x40U) +#define SPI_CI_RXFERR_SHIFT (6U) +#define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK) +#define SPI_CI_TXFERR_MASK (0x80U) +#define SPI_CI_TXFERR_SHIFT (7U) +#define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK) + +/*! @name C3 - SPI control register 3 */ +#define SPI_C3_FIFOMODE_MASK (0x1U) +#define SPI_C3_FIFOMODE_SHIFT (0U) +#define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK) +#define SPI_C3_RNFULLIEN_MASK (0x2U) +#define SPI_C3_RNFULLIEN_SHIFT (1U) +#define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK) +#define SPI_C3_TNEARIEN_MASK (0x4U) +#define SPI_C3_TNEARIEN_SHIFT (2U) +#define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK) +#define SPI_C3_INTCLR_MASK (0x8U) +#define SPI_C3_INTCLR_SHIFT (3U) +#define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK) +#define SPI_C3_RNFULLF_MARK_MASK (0x10U) +#define SPI_C3_RNFULLF_MARK_SHIFT (4U) +#define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK) +#define SPI_C3_TNEAREF_MARK_MASK (0x20U) +#define SPI_C3_TNEAREF_MARK_SHIFT (5U) +#define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK) + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x40076000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x40077000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TPM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer + * @{ + */ + +/** TPM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } CONTROLS[6]; + uint8_t RESERVED_0[20]; + __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ + uint8_t RESERVED_1[28]; + __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ + uint8_t RESERVED_2[16]; + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ +} TPM_Type; + +/* ---------------------------------------------------------------------------- + -- TPM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TPM_Register_Masks TPM Register Masks + * @{ + */ + +/*! @name SC - Status and Control */ +#define TPM_SC_PS_MASK (0x7U) +#define TPM_SC_PS_SHIFT (0U) +#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) +#define TPM_SC_CMOD_MASK (0x18U) +#define TPM_SC_CMOD_SHIFT (3U) +#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) +#define TPM_SC_CPWMS_MASK (0x20U) +#define TPM_SC_CPWMS_SHIFT (5U) +#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) +#define TPM_SC_TOIE_MASK (0x40U) +#define TPM_SC_TOIE_SHIFT (6U) +#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) +#define TPM_SC_TOF_MASK (0x80U) +#define TPM_SC_TOF_SHIFT (7U) +#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) +#define TPM_SC_DMA_MASK (0x100U) +#define TPM_SC_DMA_SHIFT (8U) +#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) + +/*! @name CNT - Counter */ +#define TPM_CNT_COUNT_MASK (0xFFFFU) +#define TPM_CNT_COUNT_SHIFT (0U) +#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) + +/*! @name MOD - Modulo */ +#define TPM_MOD_MOD_MASK (0xFFFFU) +#define TPM_MOD_MOD_SHIFT (0U) +#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) + +/*! @name CnSC - Channel (n) Status and Control */ +#define TPM_CnSC_DMA_MASK (0x1U) +#define TPM_CnSC_DMA_SHIFT (0U) +#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) +#define TPM_CnSC_ELSA_MASK (0x4U) +#define TPM_CnSC_ELSA_SHIFT (2U) +#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) +#define TPM_CnSC_ELSB_MASK (0x8U) +#define TPM_CnSC_ELSB_SHIFT (3U) +#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) +#define TPM_CnSC_MSA_MASK (0x10U) +#define TPM_CnSC_MSA_SHIFT (4U) +#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) +#define TPM_CnSC_MSB_MASK (0x20U) +#define TPM_CnSC_MSB_SHIFT (5U) +#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) +#define TPM_CnSC_CHIE_MASK (0x40U) +#define TPM_CnSC_CHIE_SHIFT (6U) +#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) +#define TPM_CnSC_CHF_MASK (0x80U) +#define TPM_CnSC_CHF_SHIFT (7U) +#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) + +/* The count of TPM_CnSC */ +#define TPM_CnSC_COUNT (6U) + +/*! @name CnV - Channel (n) Value */ +#define TPM_CnV_VAL_MASK (0xFFFFU) +#define TPM_CnV_VAL_SHIFT (0U) +#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) + +/* The count of TPM_CnV */ +#define TPM_CnV_COUNT (6U) + +/*! @name STATUS - Capture and Compare Status */ +#define TPM_STATUS_CH0F_MASK (0x1U) +#define TPM_STATUS_CH0F_SHIFT (0U) +#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) +#define TPM_STATUS_CH1F_MASK (0x2U) +#define TPM_STATUS_CH1F_SHIFT (1U) +#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) +#define TPM_STATUS_CH2F_MASK (0x4U) +#define TPM_STATUS_CH2F_SHIFT (2U) +#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) +#define TPM_STATUS_CH3F_MASK (0x8U) +#define TPM_STATUS_CH3F_SHIFT (3U) +#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) +#define TPM_STATUS_CH4F_MASK (0x10U) +#define TPM_STATUS_CH4F_SHIFT (4U) +#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) +#define TPM_STATUS_CH5F_MASK (0x20U) +#define TPM_STATUS_CH5F_SHIFT (5U) +#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) +#define TPM_STATUS_TOF_MASK (0x100U) +#define TPM_STATUS_TOF_SHIFT (8U) +#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) + +/*! @name POL - Channel Polarity */ +#define TPM_POL_POL0_MASK (0x1U) +#define TPM_POL_POL0_SHIFT (0U) +#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) +#define TPM_POL_POL1_MASK (0x2U) +#define TPM_POL_POL1_SHIFT (1U) +#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) +#define TPM_POL_POL2_MASK (0x4U) +#define TPM_POL_POL2_SHIFT (2U) +#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) +#define TPM_POL_POL3_MASK (0x8U) +#define TPM_POL_POL3_SHIFT (3U) +#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) +#define TPM_POL_POL4_MASK (0x10U) +#define TPM_POL_POL4_SHIFT (4U) +#define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) +#define TPM_POL_POL5_MASK (0x20U) +#define TPM_POL_POL5_SHIFT (5U) +#define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) + +/*! @name CONF - Configuration */ +#define TPM_CONF_DOZEEN_MASK (0x20U) +#define TPM_CONF_DOZEEN_SHIFT (5U) +#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) +#define TPM_CONF_DBGMODE_MASK (0xC0U) +#define TPM_CONF_DBGMODE_SHIFT (6U) +#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) +#define TPM_CONF_GTBSYNC_MASK (0x100U) +#define TPM_CONF_GTBSYNC_SHIFT (8U) +#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) +#define TPM_CONF_GTBEEN_MASK (0x200U) +#define TPM_CONF_GTBEEN_SHIFT (9U) +#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) +#define TPM_CONF_CSOT_MASK (0x10000U) +#define TPM_CONF_CSOT_SHIFT (16U) +#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) +#define TPM_CONF_CSOO_MASK (0x20000U) +#define TPM_CONF_CSOO_SHIFT (17U) +#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) +#define TPM_CONF_CROT_MASK (0x40000U) +#define TPM_CONF_CROT_SHIFT (18U) +#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) +#define TPM_CONF_CPOT_MASK (0x80000U) +#define TPM_CONF_CPOT_SHIFT (19U) +#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) +#define TPM_CONF_TRGPOL_MASK (0x400000U) +#define TPM_CONF_TRGPOL_SHIFT (22U) +#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) +#define TPM_CONF_TRGSRC_MASK (0x800000U) +#define TPM_CONF_TRGSRC_SHIFT (23U) +#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) +#define TPM_CONF_TRGSEL_MASK (0xF000000U) +#define TPM_CONF_TRGSEL_SHIFT (24U) +#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) + + +/*! + * @} + */ /* end of group TPM_Register_Masks */ + + +/* TPM - Peripheral instance base addresses */ +/** Peripheral TPM0 base address */ +#define TPM0_BASE (0x40038000u) +/** Peripheral TPM0 base pointer */ +#define TPM0 ((TPM_Type *)TPM0_BASE) +/** Peripheral TPM1 base address */ +#define TPM1_BASE (0x40039000u) +/** Peripheral TPM1 base pointer */ +#define TPM1 ((TPM_Type *)TPM1_BASE) +/** Peripheral TPM2 base address */ +#define TPM2_BASE (0x4003A000u) +/** Peripheral TPM2 base pointer */ +#define TPM2 ((TPM_Type *)TPM2_BASE) +/** Array initializer of TPM peripheral base addresses */ +#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } +/** Array initializer of TPM peripheral base pointers */ +#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } +/** Interrupt vectors for the TPM peripheral type */ +#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } + +/*! + * @} + */ /* end of group TPM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ + __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ + __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ + __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ + __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ + __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ + __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ + __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ + __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ + __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ + __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ + __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ + uint8_t RESERVED_0[12]; + __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ + __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ + __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ + __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ + __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ + __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ + __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ + uint8_t RESERVED_1[26]; + __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */ + __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */ + union { /* offset: 0x3C */ + struct { /* offset: 0x3C */ + __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ + __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ + } TYPE0; + struct { /* offset: 0x3C */ + __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ + __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ + } TYPE1; + }; + __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */ + __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name BDH - UART Baud Rate Registers: High */ +#define UART_BDH_SBR_MASK (0x1FU) +#define UART_BDH_SBR_SHIFT (0U) +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) +#define UART_BDH_RXEDGIE_MASK (0x40U) +#define UART_BDH_RXEDGIE_SHIFT (6U) +#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) + +/*! @name BDL - UART Baud Rate Registers: Low */ +#define UART_BDL_SBR_MASK (0xFFU) +#define UART_BDL_SBR_SHIFT (0U) +#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) + +/*! @name C1 - UART Control Register 1 */ +#define UART_C1_PT_MASK (0x1U) +#define UART_C1_PT_SHIFT (0U) +#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) +#define UART_C1_PE_MASK (0x2U) +#define UART_C1_PE_SHIFT (1U) +#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) +#define UART_C1_ILT_MASK (0x4U) +#define UART_C1_ILT_SHIFT (2U) +#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) +#define UART_C1_WAKE_MASK (0x8U) +#define UART_C1_WAKE_SHIFT (3U) +#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) +#define UART_C1_M_MASK (0x10U) +#define UART_C1_M_SHIFT (4U) +#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) +#define UART_C1_RSRC_MASK (0x20U) +#define UART_C1_RSRC_SHIFT (5U) +#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) +#define UART_C1_LOOPS_MASK (0x80U) +#define UART_C1_LOOPS_SHIFT (7U) +#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) + +/*! @name C2 - UART Control Register 2 */ +#define UART_C2_SBK_MASK (0x1U) +#define UART_C2_SBK_SHIFT (0U) +#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) +#define UART_C2_RWU_MASK (0x2U) +#define UART_C2_RWU_SHIFT (1U) +#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) +#define UART_C2_RE_MASK (0x4U) +#define UART_C2_RE_SHIFT (2U) +#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) +#define UART_C2_TE_MASK (0x8U) +#define UART_C2_TE_SHIFT (3U) +#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) +#define UART_C2_ILIE_MASK (0x10U) +#define UART_C2_ILIE_SHIFT (4U) +#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) +#define UART_C2_RIE_MASK (0x20U) +#define UART_C2_RIE_SHIFT (5U) +#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) +#define UART_C2_TCIE_MASK (0x40U) +#define UART_C2_TCIE_SHIFT (6U) +#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) +#define UART_C2_TIE_MASK (0x80U) +#define UART_C2_TIE_SHIFT (7U) +#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) + +/*! @name S1 - UART Status Register 1 */ +#define UART_S1_PF_MASK (0x1U) +#define UART_S1_PF_SHIFT (0U) +#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) +#define UART_S1_FE_MASK (0x2U) +#define UART_S1_FE_SHIFT (1U) +#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) +#define UART_S1_NF_MASK (0x4U) +#define UART_S1_NF_SHIFT (2U) +#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) +#define UART_S1_OR_MASK (0x8U) +#define UART_S1_OR_SHIFT (3U) +#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) +#define UART_S1_IDLE_MASK (0x10U) +#define UART_S1_IDLE_SHIFT (4U) +#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) +#define UART_S1_RDRF_MASK (0x20U) +#define UART_S1_RDRF_SHIFT (5U) +#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) +#define UART_S1_TC_MASK (0x40U) +#define UART_S1_TC_SHIFT (6U) +#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) +#define UART_S1_TDRE_MASK (0x80U) +#define UART_S1_TDRE_SHIFT (7U) +#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) + +/*! @name S2 - UART Status Register 2 */ +#define UART_S2_RAF_MASK (0x1U) +#define UART_S2_RAF_SHIFT (0U) +#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) +#define UART_S2_BRK13_MASK (0x4U) +#define UART_S2_BRK13_SHIFT (2U) +#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) +#define UART_S2_RWUID_MASK (0x8U) +#define UART_S2_RWUID_SHIFT (3U) +#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) +#define UART_S2_RXINV_MASK (0x10U) +#define UART_S2_RXINV_SHIFT (4U) +#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) +#define UART_S2_MSBF_MASK (0x20U) +#define UART_S2_MSBF_SHIFT (5U) +#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) +#define UART_S2_RXEDGIF_MASK (0x40U) +#define UART_S2_RXEDGIF_SHIFT (6U) +#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) + +/*! @name C3 - UART Control Register 3 */ +#define UART_C3_PEIE_MASK (0x1U) +#define UART_C3_PEIE_SHIFT (0U) +#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) +#define UART_C3_FEIE_MASK (0x2U) +#define UART_C3_FEIE_SHIFT (1U) +#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) +#define UART_C3_NEIE_MASK (0x4U) +#define UART_C3_NEIE_SHIFT (2U) +#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) +#define UART_C3_ORIE_MASK (0x8U) +#define UART_C3_ORIE_SHIFT (3U) +#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) +#define UART_C3_TXINV_MASK (0x10U) +#define UART_C3_TXINV_SHIFT (4U) +#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) +#define UART_C3_TXDIR_MASK (0x20U) +#define UART_C3_TXDIR_SHIFT (5U) +#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) +#define UART_C3_T8_MASK (0x40U) +#define UART_C3_T8_SHIFT (6U) +#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) +#define UART_C3_R8_MASK (0x80U) +#define UART_C3_R8_SHIFT (7U) +#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) + +/*! @name D - UART Data Register */ +#define UART_D_RT_MASK (0xFFU) +#define UART_D_RT_SHIFT (0U) +#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) + +/*! @name MA1 - UART Match Address Registers 1 */ +#define UART_MA1_MA_MASK (0xFFU) +#define UART_MA1_MA_SHIFT (0U) +#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) + +/*! @name MA2 - UART Match Address Registers 2 */ +#define UART_MA2_MA_MASK (0xFFU) +#define UART_MA2_MA_SHIFT (0U) +#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) + +/*! @name C4 - UART Control Register 4 */ +#define UART_C4_BRFA_MASK (0x1FU) +#define UART_C4_BRFA_SHIFT (0U) +#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) +#define UART_C4_M10_MASK (0x20U) +#define UART_C4_M10_SHIFT (5U) +#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) +#define UART_C4_MAEN2_MASK (0x40U) +#define UART_C4_MAEN2_SHIFT (6U) +#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) +#define UART_C4_MAEN1_MASK (0x80U) +#define UART_C4_MAEN1_SHIFT (7U) +#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) + +/*! @name C5 - UART Control Register 5 */ +#define UART_C5_RDMAS_MASK (0x20U) +#define UART_C5_RDMAS_SHIFT (5U) +#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) +#define UART_C5_TDMAS_MASK (0x80U) +#define UART_C5_TDMAS_SHIFT (7U) +#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) + +/*! @name C7816 - UART 7816 Control Register */ +#define UART_C7816_ISO_7816E_MASK (0x1U) +#define UART_C7816_ISO_7816E_SHIFT (0U) +#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) +#define UART_C7816_TTYPE_MASK (0x2U) +#define UART_C7816_TTYPE_SHIFT (1U) +#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) +#define UART_C7816_INIT_MASK (0x4U) +#define UART_C7816_INIT_SHIFT (2U) +#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) +#define UART_C7816_ANACK_MASK (0x8U) +#define UART_C7816_ANACK_SHIFT (3U) +#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) +#define UART_C7816_ONACK_MASK (0x10U) +#define UART_C7816_ONACK_SHIFT (4U) +#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) + +/*! @name IE7816 - UART 7816 Interrupt Enable Register */ +#define UART_IE7816_RXTE_MASK (0x1U) +#define UART_IE7816_RXTE_SHIFT (0U) +#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) +#define UART_IE7816_TXTE_MASK (0x2U) +#define UART_IE7816_TXTE_SHIFT (1U) +#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) +#define UART_IE7816_GTVE_MASK (0x4U) +#define UART_IE7816_GTVE_SHIFT (2U) +#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) +#define UART_IE7816_ADTE_MASK (0x8U) +#define UART_IE7816_ADTE_SHIFT (3U) +#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK) +#define UART_IE7816_INITDE_MASK (0x10U) +#define UART_IE7816_INITDE_SHIFT (4U) +#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) +#define UART_IE7816_BWTE_MASK (0x20U) +#define UART_IE7816_BWTE_SHIFT (5U) +#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) +#define UART_IE7816_CWTE_MASK (0x40U) +#define UART_IE7816_CWTE_SHIFT (6U) +#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) +#define UART_IE7816_WTE_MASK (0x80U) +#define UART_IE7816_WTE_SHIFT (7U) +#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) + +/*! @name IS7816 - UART 7816 Interrupt Status Register */ +#define UART_IS7816_RXT_MASK (0x1U) +#define UART_IS7816_RXT_SHIFT (0U) +#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) +#define UART_IS7816_TXT_MASK (0x2U) +#define UART_IS7816_TXT_SHIFT (1U) +#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) +#define UART_IS7816_GTV_MASK (0x4U) +#define UART_IS7816_GTV_SHIFT (2U) +#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) +#define UART_IS7816_ADT_MASK (0x8U) +#define UART_IS7816_ADT_SHIFT (3U) +#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK) +#define UART_IS7816_INITD_MASK (0x10U) +#define UART_IS7816_INITD_SHIFT (4U) +#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) +#define UART_IS7816_BWT_MASK (0x20U) +#define UART_IS7816_BWT_SHIFT (5U) +#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) +#define UART_IS7816_CWT_MASK (0x40U) +#define UART_IS7816_CWT_SHIFT (6U) +#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) +#define UART_IS7816_WT_MASK (0x80U) +#define UART_IS7816_WT_SHIFT (7U) +#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) + +/*! @name WP7816 - UART 7816 Wait Parameter Register */ +#define UART_WP7816_WTX_MASK (0xFFU) +#define UART_WP7816_WTX_SHIFT (0U) +#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK) + +/*! @name WN7816 - UART 7816 Wait N Register */ +#define UART_WN7816_GTN_MASK (0xFFU) +#define UART_WN7816_GTN_SHIFT (0U) +#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) + +/*! @name WF7816 - UART 7816 Wait FD Register */ +#define UART_WF7816_GTFD_MASK (0xFFU) +#define UART_WF7816_GTFD_SHIFT (0U) +#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) + +/*! @name ET7816 - UART 7816 Error Threshold Register */ +#define UART_ET7816_RXTHRESHOLD_MASK (0xFU) +#define UART_ET7816_RXTHRESHOLD_SHIFT (0U) +#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) +#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) +#define UART_ET7816_TXTHRESHOLD_SHIFT (4U) +#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) + +/*! @name TL7816 - UART 7816 Transmit Length Register */ +#define UART_TL7816_TLEN_MASK (0xFFU) +#define UART_TL7816_TLEN_SHIFT (0U) +#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) + +/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */ +#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU) +#define UART_AP7816A_T0_ADTI_H_SHIFT (0U) +#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK) + +/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */ +#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU) +#define UART_AP7816B_T0_ADTI_L_SHIFT (0U) +#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK) + +/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */ +#define UART_WP7816A_T0_WI_H_MASK (0xFFU) +#define UART_WP7816A_T0_WI_H_SHIFT (0U) +#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK) + +/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */ +#define UART_WP7816B_T0_WI_L_MASK (0xFFU) +#define UART_WP7816B_T0_WI_L_SHIFT (0U) +#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK) + +/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */ +#define UART_WP7816A_T1_BWI_H_MASK (0xFFU) +#define UART_WP7816A_T1_BWI_H_SHIFT (0U) +#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK) + +/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */ +#define UART_WP7816B_T1_BWI_L_MASK (0xFFU) +#define UART_WP7816B_T1_BWI_L_SHIFT (0U) +#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK) + +/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */ +#define UART_WGP7816_T1_BGI_MASK (0xFU) +#define UART_WGP7816_T1_BGI_SHIFT (0U) +#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK) +#define UART_WGP7816_T1_CWI1_MASK (0xF0U) +#define UART_WGP7816_T1_CWI1_SHIFT (4U) +#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK) + +/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */ +#define UART_WP7816C_T1_CWI2_MASK (0x1FU) +#define UART_WP7816C_T1_CWI2_SHIFT (0U) +#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART2 base address */ +#define UART2_BASE (0x4006C000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { 0u, 0u, UART2_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { (UART_Type *)0u, (UART_Type *)0u, UART2 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_RX_TX_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn } +#define UART_ERR_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ + uint8_t RESERVED_3[15]; + __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ + uint8_t RESERVED_4[99]; + __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ + uint8_t RESERVED_5[3]; + __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ + uint8_t RESERVED_6[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ + uint8_t RESERVED_7[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ + uint8_t RESERVED_8[3]; + __I uint8_t STAT; /**< Status register, offset: 0x90 */ + uint8_t RESERVED_9[3]; + __IO uint8_t CTL; /**< Control register, offset: 0x94 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ + uint8_t RESERVED_11[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ + uint8_t RESERVED_12[3]; + __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ + uint8_t RESERVED_13[3]; + __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ + uint8_t RESERVED_14[11]; + __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ + uint8_t RESERVED_15[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ + uint8_t RESERVED_16[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ + uint8_t RESERVED_17[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ + uint8_t RESERVED_18[3]; + __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ + uint8_t RESERVED_19[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ + uint8_t RESERVED_20[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ + uint8_t RESERVED_21[15]; + __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */ + uint8_t RESERVED_22[3]; + __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */ + uint8_t RESERVED_23[23]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ + uint8_t RESERVED_24[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ + uint8_t RESERVED_25[15]; + __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ + uint8_t RESERVED_26[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID register */ +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) + +/*! @name IDCOMP - Peripheral ID Complement register */ +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) + +/*! @name REV - Peripheral Revision register */ +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) + +/*! @name ADDINFO - Peripheral Additional Info register */ +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) + +/*! @name OTGCTL - OTG Control register */ +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) + +/*! @name ISTAT - Interrupt Status register */ +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) + +/*! @name INTEN - Interrupt Enable register */ +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) + +/*! @name ERRSTAT - Error Interrupt Status register */ +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) +#define USB_ERRSTAT_CRC5_MASK (0x2U) +#define USB_ERRSTAT_CRC5_SHIFT (1U) +#define USB_ERRSTAT_CRC5(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5_SHIFT)) & USB_ERRSTAT_CRC5_MASK) +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) + +/*! @name ERREN - Error Interrupt Enable register */ +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) + +/*! @name STAT - Status register */ +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) + +/*! @name CTL - Control register */ +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) + +/*! @name ADDR - Address register */ +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) + +/*! @name BDTPAGE1 - BDT Page register 1 */ +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) + +/*! @name FRMNUML - Frame Number register Low */ +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) + +/*! @name FRMNUMH - Frame Number register High */ +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) + +/*! @name BDTPAGE2 - BDT Page Register 2 */ +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) + +/*! @name BDTPAGE3 - BDT Page Register 3 */ +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) + +/*! @name ENDPT - Endpoint Control register */ +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control register */ +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) + +/*! @name OBSERVE - USB OTG Observe register */ +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) + +/*! @name CONTROL - USB OTG Control register */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) + +/*! @name USBTRC0 - USB Transceiver Control register 0 */ +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) + +/*! @name USBFRMADJUST - Frame Adjust Register */ +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) + +/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */ +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) +#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) +#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) +#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) +#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK (0x8U) +#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT (3U) +#define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) +#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) + +/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */ +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) +#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) + +/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) + +/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) + +/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) + +/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40072000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ + __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name TRM - VREF Trim Register */ +#define VREF_TRM_TRIM_MASK (0x3FU) +#define VREF_TRM_TRIM_SHIFT (0U) +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) +#define VREF_TRM_CHOPEN_MASK (0x40U) +#define VREF_TRM_CHOPEN_SHIFT (6U) +#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) + +/*! @name SC - VREF Status and Control Register */ +#define VREF_SC_MODE_LV_MASK (0x3U) +#define VREF_SC_MODE_LV_SHIFT (0U) +#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) +#define VREF_SC_VREFST_MASK (0x4U) +#define VREF_SC_VREFST_SHIFT (2U) +#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) +#define VREF_SC_ICOMPEN_MASK (0x20U) +#define VREF_SC_ICOMPEN_SHIFT (5U) +#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) +#define VREF_SC_REGEN_MASK (0x40U) +#define VREF_SC_REGEN_SHIFT (6U) +#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) +#define VREF_SC_VREFEN_MASK (0x80U) +#define VREF_SC_VREFEN_SHIFT (7U) +#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +/** Peripheral VREF base address */ +#define VREF_BASE (0x40074000u) +/** Peripheral VREF base pointer */ +#define VREF ((VREF_Type *)VREF_BASE) +/** Array initializer of VREF peripheral base addresses */ +#define VREF_BASE_ADDRS { VREF_BASE } +/** Array initializer of VREF peripheral base pointers */ +#define VREF_BASE_PTRS { VREF } + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MKL27Z644_H_ */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644_features.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644_features.h new file mode 100644 index 00000000000..25ab5f0da99 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644_features.h @@ -0,0 +1,1708 @@ +/* +** ################################################################### +** Version: rev. 1.8, 2015-05-27 +** Build: b151216 +** +** Abstract: +** Chip specific module features. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-12) +** Initial version. +** - rev. 1.1 (2014-07-10) +** UART0 - UART0 module renamed to UART2. +** - rev. 1.2 (2014-08-12) +** CRC - CRC register renamed to DATA. +** - rev. 1.3 (2014-09-02) +** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. +** USB - USB0_CTL1 was renamed to USB0_CTL register. +** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. +** - rev. 1.4 (2014-09-22) +** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. +** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. +** SIM - Removed bitfield DIEID in SDID register. +** UART2 - Removed ED register. +** UART2 - Removed MODEM register. +** UART2 - Removed IR register. +** UART2 - Removed PFIFO register. +** UART2 - Removed CFIFO register. +** UART2 - Removed SFIFO register. +** UART2 - Removed TWFIFO register. +** UART2 - Removed TCFIFO register. +** UART2 - Removed RWFIFO register. +** UART2 - Removed RCFIFO register. +** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. +** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. +** - rev. 1.5 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 1.6 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PORT. +** - rev. 1.7 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 1.8 (2015-05-27) +** Several USB features added. +** +** ################################################################### +*/ + +#ifndef _MKL27Z644_FEATURES_H_ +#define _MKL27Z644_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (0) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (0) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (2) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (1) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (1) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (2) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + +/* DMA module features */ + +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404) + +/* FLASH module features */ + +#if defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z32VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z32VLH4) || \ + defined(CPU_MKL27Z32VMP4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z64VFT4) || defined(CPU_MKL27Z64VLH4) || \ + defined(CPU_MKL27Z64VMP4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z32VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z32VLH4) || \ + defined(CPU_MKL27Z32VMP4) */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) + +/* LLWU module features */ + +/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) +/* @brief Has pins 8-15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) +/* @brief Maximum number of internal modules connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) +/* @brief Number of digital filters. */ +#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) +/* @brief Has MF5 register. */ +#define FSL_FEATURE_LLWU_HAS_MF (0) +/* @brief Has PF register. */ +#define FSL_FEATURE_LLWU_HAS_PF (0) +/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ +#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +/* @brief Has external pin 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) +/* @brief Has external pin 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) +/* @brief Has external pin 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) +/* @brief Has external pin 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) +/* @brief Has external pin 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) +/* @brief Has external pin 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) +/* @brief Has external pin 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) +/* @brief Has external pin 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) +/* @brief Has external pin 8 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) +/* @brief Has external pin 9 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) +/* @brief Has external pin 10 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) +/* @brief Has external pin 11 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) +/* @brief Has external pin 12 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) +/* @brief Has external pin 13 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) +/* @brief Has external pin 14 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) +/* @brief Has external pin 15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) +/* @brief Has external pin 16 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) +/* @brief Has external pin 17 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) +/* @brief Has external pin 18 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) +/* @brief Has external pin 19 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) +/* @brief Has external pin 20 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) +/* @brief Has external pin 21 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) +/* @brief Has external pin 22 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) +/* @brief Has external pin 23 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) +/* @brief Has external pin 24 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) +/* @brief Has external pin 25 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) +/* @brief Has external pin 26 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) +/* @brief Has external pin 27 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) +/* @brief Has external pin 28 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) +/* @brief Has external pin 29 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) +/* @brief Has external pin 30 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) +/* @brief Has external pin 31 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) +/* @brief Has internal module 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) +/* @brief Has internal module 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) +/* @brief Has internal module 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) +/* @brief Has internal module 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) +/* @brief Has internal module 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) +/* @brief Has internal module 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) +/* @brief Has internal module 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) +/* @brief Has internal module 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) +/* @brief Has Version ID Register (LLWU_VERID). */ +#define FSL_FEATURE_LLWU_HAS_VERID (0) +/* @brief Has Parameter Register (LLWU_PARAM). */ +#define FSL_FEATURE_LLWU_HAS_PARAM (0) +/* @brief Width of registers of the LLWU. */ +#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) +/* @brief Has DMA Enable register (LLWU_DE). */ +#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (0) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* MCGLITE module features */ + +/* @brief Defines that clock generator is MCG Lite. */ +#define FSL_FEATURE_MCGLITE_MCGLITE (1) +/* @brief Has Crystal Oscillator Operation Mode Selection. */ +#define FSL_FEATURE_MCGLITE_HAS_HGO0 (1) +/* @brief Has HCTRIM register available. */ +#define FSL_FEATURE_MCGLITE_HAS_HCTRIM (0) +/* @brief Has HTTRIM register available. */ +#define FSL_FEATURE_MCGLITE_HAS_HTTRIM (0) +/* @brief Has HFTRIM register available. */ +#define FSL_FEATURE_MCGLITE_HAS_HFTRIM (0) +/* @brief Has LTRIMRNG register available. */ +#define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (0) +/* @brief Has LFTRIM register available. */ +#define FSL_FEATURE_MCGLITE_HAS_LFTRIM (0) +/* @brief Has LSTRIM register available. */ +#define FSL_FEATURE_MCGLITE_HAS_LSTRIM (0) +/* @brief Has External Clock Source Frequency Range Selection. */ +#define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (1) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (0) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (1) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (0) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (1) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (1) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (1) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (1) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (1) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) + +/* SPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_SPI_HAS_FIFO (1) +/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ +#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ +#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ + ((x) == SPI0 ? (0) : \ + ((x) == SPI1 ? (4) : (-1))) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) +/* @brief The data register name has postfix (L as low and H as high). */ +#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (6) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (0) +/* @brief Has TPM_FILTER. */ +#define FSL_FEATURE_TPM_HAS_FILTER (0) +/* @brief Has TPM_QDCTRL. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (0) + +/* UART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_HAS_FIFO (0) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) +/* @brief Peripheral type. */ +#define FSL_FEATURE_UART_IS_SCI (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_UART_HAS_DMA_SELECT (1) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* USB module features */ + +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (512) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074782208) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief Describes the set of SC[MODE_LV] bitfield values */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +#endif /* _MKL27Z644_FEATURES_H_ */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct new file mode 100644 index 00000000000..3caef7f66ad --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct @@ -0,0 +1,110 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MKL27Z64VDA4 +** MKL27Z64VFM4 +** MKL27Z64VFT4 +** MKL27Z64VLH4 +** MKL27Z64VMP4 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 +** Version: rev. 1.4, 2014-09-22 +** Build: b151009 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +#define __ram_vector_table__ 1 + +/* Heap 1/4 of ram and stack 1/8 */ +#define __stack_size__ 0x800 +#define __heap_size__ 0x1000 + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000200 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_flash_config_start 0x00000400 +#define m_flash_config_size 0x00000010 + +#define m_text_start 0x00000410 +#define m_text_size 0x0000FBF0 + +#define m_interrupts_ram_start 0x1FFFF000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x00004000 - m_interrupts_ram_size) + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start 0x10000 { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (FlashConfig) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM1 +0 EMPTY Heap_Size { ; Heap region growing up + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S new file mode 100644 index 00000000000..fb04f25e794 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S @@ -0,0 +1,449 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL27Z644.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL27Z644 +; * @version: 1.4 +; * @date: 2014-9-22 +; * @build: b151105 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20003000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD Reserved39_IRQHandler ;Reserved interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD Reserved41_IRQHandler ;Reserved interrupt + DCD Reserved42_IRQHandler ;Reserved interrupt + DCD Reserved43_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD Reserved45_IRQHandler ;Reserved interrupt + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTBCDE_IRQHandler ;Single interrupt vector for PORTB,PORTC,PORTD,PORTE +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT0 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. +; BOOTPIN_OPT +; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin +; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits +; NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; RESET_PIN_CFG +; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function +; <1=> RESET_b pin is dedicated +; LPBOOT1 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. +; FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +; BOOTSRC_SEL +; <0=> Boot from Flash +; <2=> Boot from ROM +; <3=> Boot from ROM +; Boot source selection +FOPT EQU 0x3D +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +UART2_FLEXIO_IRQHandler\ + PROC + EXPORT UART2_FLEXIO_IRQHandler [WEAK] + LDR R0, =UART2_FLEXIO_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT Reserved20_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT UART2_FLEXIO_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT Reserved39_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT Reserved41_IRQHandler [WEAK] + EXPORT Reserved42_IRQHandler [WEAK] + EXPORT Reserved43_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT Reserved45_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTBCDE_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +UART2_FLEXIO_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +Reserved39_IRQHandler +USB0_IRQHandler +Reserved41_IRQHandler +Reserved42_IRQHandler +Reserved43_IRQHandler +LPTMR0_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTBCDE_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..b129b2c2a5b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld new file mode 100644 index 00000000000..10d3cc4bdcb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld @@ -0,0 +1,277 @@ +/* +** ################################################################### +** Processors: MKL27Z64VDA4 +** MKL27Z64VFM4 +** MKL27Z64VFT4 +** MKL27Z64VLH4 +** MKL27Z64VMP4 +** +** Compiler: GNU C Compiler +** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 +** Version: rev. 1.4, 2014-09-22 +** Build: b151217 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +__stack_size__ = 0x800; +__heap_size__ = 0x1000; + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0200 : 0x0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0000FBF0 + m_data (RW) : ORIGIN = 0x1FFFF000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + /* reserve MTB memory at the beginning of m_data */ + .mtb : /* MTB buffer address as defined by the hardware */ + { + . = ALIGN(8); + _mtb_start = .; + KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ + . = ALIGN(8); + _mtb_end = .; + } > m_data + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + . = ALIGN(512); + USB_RAM_START = .; + . += USB_RAM_GAP; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt USB_RAM_START (NOLOAD) : + { + *(m_usb_bdt) + USB_RAM_BDT_END = .; + } + + m_usb_global USB_RAM_BDT_END (NOLOAD) : + { + *(m_usb_global) + } + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S new file mode 100644 index 00000000000..d446050bbd3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S @@ -0,0 +1,382 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MKL27Z644.s */ +/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ +/* MKL27Z644 */ +/* @version: 1.4 */ +/* @date: 2014-9-22 */ +/* @build: b151111 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv6-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ + .long Reserved20_IRQHandler /* Reserved interrupt*/ + .long FTFA_IRQHandler /* Command complete and read collision*/ + .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/ + .long LLWU_IRQHandler /* Low leakage wakeup*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ + .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ + .long LPUART0_IRQHandler /* LPUART0 status and error*/ + .long LPUART1_IRQHandler /* LPUART1 status and error*/ + .long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ + .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ + .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ + .long RTC_IRQHandler /* RTC alarm*/ + .long RTC_Seconds_IRQHandler /* RTC seconds*/ + .long PIT_IRQHandler /* PIT interrupt*/ + .long Reserved39_IRQHandler /* Reserved interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long Reserved41_IRQHandler /* Reserved interrupt*/ + .long Reserved42_IRQHandler /* Reserved interrupt*/ + .long Reserved43_IRQHandler /* Reserved interrupt*/ + .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ + .long Reserved45_IRQHandler /* Reserved interrupt*/ + .long PORTA_IRQHandler /* PORTA Pin detect*/ + .long PORTBCDE_IRQHandler /* Single interrupt vector for PORTB,PORTC,PORTD,PORTE*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFF3DFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC0 + +.LC1: + subs r3, 4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .LC1 +.LC0: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + ldr r0, =DefaultISR + bx r0 + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak LPUART0_IRQHandler + .type LPUART0_IRQHandler, %function +LPUART0_IRQHandler: + ldr r0,=LPUART0_DriverIRQHandler + bx r0 + .size LPUART0_IRQHandler, . - LPUART0_IRQHandler + + .align 1 + .thumb_func + .weak LPUART1_IRQHandler + .type LPUART1_IRQHandler, %function +LPUART1_IRQHandler: + ldr r0,=LPUART1_DriverIRQHandler + bx r0 + .size LPUART1_IRQHandler, . - LPUART1_IRQHandler + + .align 1 + .thumb_func + .weak UART2_FLEXIO_IRQHandler + .type UART2_FLEXIO_IRQHandler, %function +UART2_FLEXIO_IRQHandler: + ldr r0,=UART2_FLEXIO_DriverIRQHandler + bx r0 + .size UART2_FLEXIO_IRQHandler, . - UART2_FLEXIO_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler Reserved20_IRQHandler + def_irq_handler FTFA_IRQHandler + def_irq_handler PMC_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler LPUART0_DriverIRQHandler + def_irq_handler LPUART1_DriverIRQHandler + def_irq_handler UART2_FLEXIO_DriverIRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler TPM0_IRQHandler + def_irq_handler TPM1_IRQHandler + def_irq_handler TPM2_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT_IRQHandler + def_irq_handler Reserved39_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler Reserved41_IRQHandler + def_irq_handler Reserved42_IRQHandler + def_irq_handler Reserved43_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler Reserved45_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTBCDE_IRQHandler + + .end diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf new file mode 100644 index 00000000000..206fcf91fe0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf @@ -0,0 +1,115 @@ +/* +** ################################################################### +** Processors: MKL27Z64VDA4 +** MKL27Z64VFM4 +** MKL27Z64VFT4 +** MKL27Z64VLH4 +** MKL27Z64VMP4 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 +** Version: rev. 1.4, 2014-09-22 +** Build: b151009 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +define symbol __ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +define symbol __stack_size__=0x800; +define symbol __heap_size__=0x1000; + +define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000200 : 0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000001FF : 0; + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000001FF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x0000FFFF; + +define symbol m_interrupts_ram_start = 0x1FFFF000; +define symbol m_interrupts_ram_end = 0x1FFFF000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x20002FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S new file mode 100644 index 00000000000..9c3120cc4d0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S @@ -0,0 +1,317 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL27Z644.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL27Z644 +; @version: 1.4 +; @date: 2014-9-22 +; @build: b151105 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD Reserved39_IRQHandler ;Reserved interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD Reserved41_IRQHandler ;Reserved interrupt + DCD Reserved42_IRQHandler ;Reserved interrupt + DCD Reserved43_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD Reserved45_IRQHandler ;Reserved interrupt + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTBCDE_IRQHandler ;Single interrupt vector for PORTB,PORTC,PORTD,PORTE +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFF3DFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK UART2_FLEXIO_IRQHandler + PUBWEAK UART2_FLEXIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_FLEXIO_IRQHandler + LDR R0, =UART2_FLEXIO_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK Reserved39_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK Reserved41_IRQHandler + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved43_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK Reserved45_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTBCDE_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +UART2_FLEXIO_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +Reserved39_IRQHandler +USB0_IRQHandler +Reserved41_IRQHandler +Reserved42_IRQHandler +Reserved43_IRQHandler +LPTMR0_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTBCDE_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h new file mode 100644 index 00000000000..7423a125ba6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "fsl_device_registers.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c new file mode 100644 index 00000000000..59b37502b22 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InstallIRQHandler(IRQn, vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h new file mode 100644 index 00000000000..45141f5e2c8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/fsl_device_registers.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/fsl_device_registers.h new file mode 100644 index 00000000000..b05ac1d5b9f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/fsl_device_registers.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \ + defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \ + defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \ + defined(CPU_MKL27Z64VMP4)) + +#define KL27Z644_SERIES + +/* CMSIS-style register definitions */ +#include "MKL27Z644.h" +/* CPU specific feature definitions */ +#include "MKL27Z644_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.c new file mode 100644 index 00000000000..d40c32d1446 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.c @@ -0,0 +1,155 @@ +/* +** ################################################################### +** Processors: MKL27Z32VDA4 +** MKL27Z32VFM4 +** MKL27Z32VFT4 +** MKL27Z32VLH4 +** MKL27Z32VMP4 +** MKL27Z64VDA4 +** MKL27Z64VFM4 +** MKL27Z64VFT4 +** MKL27Z64VLH4 +** MKL27Z64VMP4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 +** Version: rev. 1.4, 2014-09-22 +** Build: b151217 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-12) +** Initial version. +** - rev. 1.1 (2014-07-10) +** UART0 - UART0 module renamed to UART2. +** - rev. 1.2 (2014-08-12) +** CRC - CRC register renamed to DATA. +** - rev. 1.3 (2014-09-02) +** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. +** USB - USB0_CTL1 was renamed to USB0_CTL register. +** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. +** - rev. 1.4 (2014-09-22) +** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. +** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. +** SIM - Removed bitfield DIEID in SDID register. +** UART2 - Removed ED register. +** UART2 - Removed MODEM register. +** UART2 - Removed IR register. +** UART2 - Removed PFIFO register. +** UART2 - Removed CFIFO register. +** UART2 - Removed SFIFO register. +** UART2 - Removed TWFIFO register. +** UART2 - Removed TCFIFO register. +** UART2 - Removed RWFIFO register. +** UART2 - Removed RCFIFO register. +** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. +** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. +** +** ################################################################### +*/ + +/*! + * @file MKL27Z644 + * @version 1.4 + * @date 2014-09-22 + * @brief Device specific configuration file for MKL27Z644 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + +#if (ACK_ISOLATION) + if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) { + PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */ + } +#endif +#if (DISABLE_WDOG) + /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */ + SIM->COPC = (uint32_t)0x00u; +#endif /* (DISABLE_WDOG) */ + +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; + + if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) { + /* High internal reference clock is selected */ + MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */ + } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) { + /* Internal reference clock is selected */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */ + } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) { + /* External reference clock is selected */ + MCGOUTClock = CPU_XTAL_CLK_HZ; + } else { + /* Reserved value */ + return; + } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); + +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.h new file mode 100644 index 00000000000..f186b88082d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.h @@ -0,0 +1,166 @@ +/* +** ################################################################### +** Processors: MKL27Z32VDA4 +** MKL27Z32VFM4 +** MKL27Z32VFT4 +** MKL27Z32VLH4 +** MKL27Z32VMP4 +** MKL27Z64VDA4 +** MKL27Z64VFM4 +** MKL27Z64VFT4 +** MKL27Z64VLH4 +** MKL27Z64VMP4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 +** Version: rev. 1.4, 2014-09-22 +** Build: b151217 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-12) +** Initial version. +** - rev. 1.1 (2014-07-10) +** UART0 - UART0 module renamed to UART2. +** - rev. 1.2 (2014-08-12) +** CRC - CRC register renamed to DATA. +** - rev. 1.3 (2014-09-02) +** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. +** USB - USB0_CTL1 was renamed to USB0_CTL register. +** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. +** - rev. 1.4 (2014-09-22) +** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. +** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. +** SIM - Removed bitfield DIEID in SDID register. +** UART2 - Removed ED register. +** UART2 - Removed MODEM register. +** UART2 - Removed IR register. +** UART2 - Removed PFIFO register. +** UART2 - Removed CFIFO register. +** UART2 - Removed SFIFO register. +** UART2 - Removed TWFIFO register. +** UART2 - Removed TCFIFO register. +** UART2 - Removed RWFIFO register. +** UART2 - Removed RCFIFO register. +** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. +** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. +** +** ################################################################### +*/ + +/*! + * @file MKL27Z644 + * @version 1.4 + * @date 2014-09-22 + * @brief Device specific configuration file for MKL27Z644 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MKL27Z644_H_ +#define _SYSTEM_MKL27Z644_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +#ifndef ACK_ISOLATION + #define ACK_ISOLATION 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */ +#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ + +/* Low power mode enable */ +/* SMC_PMPROT: AVLP=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0x2Au /* SMC_PMPROT */ + +#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ +#define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MKL27Z644_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h new file mode 100644 index 00000000000..fff903f8499 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +/* LPUART */ +typedef enum { + LPUART_0 = 0, + LPUART_1 = 1, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART LPUART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, +} I2CName; + +typedef enum { + PWM = 0, +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0, + ADC0_SE1 = (0 << ADC_INSTANCE_SHIFT) | 1, + ADC0_SE2 = (0 << ADC_INSTANCE_SHIFT) | 2, + ADC0_SE3 = (0 << ADC_INSTANCE_SHIFT) | 3, + ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4, + ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5, + ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6, + ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7, + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, +} SPIName; + +typedef enum { + DAC = 0, +} DACName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c new file mode 100644 index 00000000000..fb0ea4a2ff4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c @@ -0,0 +1,150 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTE17, ADC0_SE5a, 0}, + {PTE18, ADC0_SE2, 0}, + {PTE16, ADC0_SE1, 0}, + {PTE20, ADC0_SE0, 0}, + {PTE21, ADC0_SE4a, 0}, + {PTE22, ADC0_SE3, 0}, + {PTE23, ADC0_SE7a, 0}, + {PTE29, ADC0_SE4b, 0}, + {PTE30, ADC0_SE23, 0}, + {PTB0 , ADC0_SE8 , 0}, + {PTB1 , ADC0_SE9 , 0}, + {PTB2 , ADC0_SE12, 0}, + {PTB3 , ADC0_SE13, 0}, + {PTC0 , ADC0_SE14, 0}, + {PTC1 , ADC0_SE15, 0}, + {PTC2, ADC0_SE11, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + //{PTD6, ADC0_SE7b, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE18 , I2C_0 , 4}, + {PTE25 , I2C_0 , 5}, + {PTB1 , I2C_0 , 2}, + {PTB3 , I2C_0 , 2}, + {PTC9 , I2C_0 , 2}, + {PTE0 , I2C_1 , 6}, + {PTA4 , I2C_1 , 2}, + {PTC2 , I2C_1 , 2}, + {PTC11 , I2C_1 , 2}, + {PTD6 , I2C_1 , 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE24 , I2C_0 , 5}, + {PTB0 , I2C_0 , 2}, + {PTB2 , I2C_0 , 2}, + {PTC8 , I2C_0 , 2}, + {PTE1 , I2C_1 , 6}, + {PTA3 , I2C_1 , 2}, + {PTC1 , I2C_1 , 2}, + {PTC10 , I2C_1 , 2}, + {PTD7 , I2C_1 , 4}, + {NC , NC , 0} +}; + +/************LPUART***************/ +const PinMap PinMap_UART_TX[] = { + {PTE20 , LPUART_0 , 4}, + {PTA2 , LPUART_0 , 2}, + {PTB17 , LPUART_0 , 3}, + {PTD7 , LPUART_0 , 3}, + {PTE0 , LPUART_1 , 3}, + {PTE30 , LPUART_1 , 5}, + {PTA19 , LPUART_1 , 3}, + {PTC4 , LPUART_1 , 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTE21 , LPUART_0, 4}, + {PTA1 , LPUART_0, 2}, + {PTB16 , LPUART_0, 3}, + {PTD6 , LPUART_0, 3}, + {PTE1 , LPUART_1, 3}, + {PTA18 , LPUART_1, 3}, + {PTC3 , LPUART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTE17 , SPI_0, 2}, + {PTC5 , SPI_0, 2}, + {PTD1 , SPI_0, 2}, + {PTC3 , SPI_1, 2}, + {PTD5 , SPI_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTE18 , SPI_0, 2}, + {PTC6 , SPI_0, 2}, + {PTC7 , SPI_0, 5}, + {PTD2 , SPI_0, 2}, + {PTD3 , SPI_0, 5}, + {PTE1 , SPI_1, 2}, + {PTB0 , SPI_1, 4}, + {PTB1 , SPI_1, 5}, + {PTB16 , SPI_1, 2}, + {PTB17 , SPI_1, 5}, + {PTD6 , SPI_1, 2}, + {PTD7 , SPI_1, 5}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTE18 , SPI_0, 5}, + {PTC6 , SPI_0, 5}, + {PTC7 , SPI_0, 2}, + {PTD2 , SPI_0, 5}, + {PTD3 , SPI_0, 2}, + {PTE0 , SPI_1, 2}, + {PTE1 , SPI_1, 5}, + {PTB0 , SPI_1, 5}, + {PTB1 , SPI_1, 4}, + {PTB16 , SPI_1, 5}, + {PTB17 , SPI_1, 2}, + {PTD6 , SPI_1, 5}, + {PTD7 , SPI_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTE16 , SPI_0, 2}, + {PTC4 , SPI_0, 2}, + {PTD0 , SPI_0, 2}, + {PTC4 , SPI_1, 5}, + {PTD4 , SPI_1, 2}, + {NC , NC , 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h new file mode 100644 index 00000000000..dab9a16ce70 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h @@ -0,0 +1,151 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + LED_RED = PTB18, + LED_GREEN = PTB19, + LED_BLUE = PTA13, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + //Push buttons + SW1 = PTA4, + SW3 = PTC1, + + // USB Pins + USBTX = PTA2, + USBRX = PTA1, + + // Arduino Headers + + D0 = PTA1, + D1 = PTA2, + D2 = PTA12, + D3 = PTE25, + D4 = PTA13, + D5 = PTE24, + D6 = PTC9, + D7 = PTC8, + D8 = PTE31, + D9 = PTA5, + D10 = PTC4, + D11 = PTC6, + D12 = PTC7, + D13 = PTC5, + D14 = PTD6, + D15 = PTD7, + + I2C_SCL = D15, + I2C_SDA = D14, + + A0 = PTE16, + A1 = PTC0, + A2 = PTE20, + A3 = PTE21, + A4 = PTB1, + A5 = PTB0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h new file mode 100644 index 00000000000..135a13814d9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 0 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c new file mode 100755 index 00000000000..630742cd4b9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcglite_config_t mcgliteConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 2MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgliteConfig = + { + .outSrc = kMCGLITE_ClkSrcLirc, + .irclkEnableMode = kMCGLITE_IrclkEnable, + .ircs = kMCGLITE_Lirc2M, + .fcrdiv = kMCGLITE_LircDivBy1, + .lircDiv2 = kMCGLITE_LircDivBy1, + .hircEnableInNotHircMode = false, + }, + .simConfig = + { + .clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0U, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 2000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 48000000Hz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgliteConfig = + { + .outSrc = kMCGLITE_ClkSrcHirc, + .irclkEnableMode = kMCGLITE_IrclkEnable, + .ircs = kMCGLITE_Lirc8M, + .fcrdiv = kMCGLITE_LircDivBy1, + .lircDiv2 = kMCGLITE_LircDivBy1, + .hircEnableInNotHircMode = true, + }, + .simConfig = + { + .clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0U, + .workMode = kOSC_ModeOscLowPower, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 48000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration. + * + * 3. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_SetMcgliteConfig(&g_defaultClockConfigVlpr.mcgliteConfig); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_SetMcgliteConfig(&g_defaultClockConfigRun.mcgliteConfig); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h new file mode 100755 index 00000000000..429619806ac --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 32768U +#define BOARD_XTAL32K_CLK_HZ 0U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c new file mode 100644 index 00000000000..d4577de95fd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "fsl_clock_config.h" + +// called before main - implement here if board needs it otherwise, let +// the application override this if necessary +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c new file mode 100755 index 00000000000..8f1aa77b2ea --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc16.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC16 module. + * + * @param base ADC16 peripheral base address + */ +static uint32_t ADC16_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC16 bases for each instance. */ +static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; + +/*! @brief Pointers to ADC16 clocks for each instance. */ +const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC16_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++) + { + if (s_adc16Bases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_ADC16_COUNT); + + return instance; +} + +void ADC16_Init(ADC_Type *base, const adc16_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Enable the clock. */ + CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); + + /* ADCx_CFG1. */ + tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG1_ADLSMP_MASK; + } + tmp32 |= ADC_CFG1_ADIV(config->clockDivider); + if (config->enableLowPower) + { + tmp32 |= ADC_CFG1_ADLPC_MASK; + } + base->CFG1 = tmp32; + + /* ADCx_CFG2. */ + tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG2_ADHSC_MASK; + } + if (config->enableAsynchronousClock) + { + tmp32 |= ADC_CFG2_ADACKEN_MASK; + } + base->CFG2 = tmp32; + + /* ADCx_SC2. */ + tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); + tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); + base->SC2 = tmp32; + + /* ADCx_SC3. */ + if (config->enableContinuousConversion) + { + base->SC3 |= ADC_SC3_ADCO_MASK; + } + else + { + base->SC3 &= ~ADC_SC3_ADCO_MASK; + } +} + +void ADC16_Deinit(ADC_Type *base) +{ + /* Disable the clock. */ + CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +} + +void ADC16_GetDefaultConfig(adc16_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + config->clockSource = kADC16_ClockSourceAsynchronousClock; + config->enableAsynchronousClock = true; + config->clockDivider = kADC16_ClockDivider8; + config->resolution = kADC16_ResolutionSE12Bit; + config->longSampleMode = kADC16_LongSampleDisabled; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableContinuousConversion = false; +} + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +status_t ADC16_DoAutoCalibration(ADC_Type *base) +{ + bool bHWTrigger = false; + uint32_t tmp32; + status_t status = kStatus_Success; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) + { + bHWTrigger = true; + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } + + /* Clear the CALF and launch the calibration. */ + base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; + while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) + { + /* Check the CALF when the calibration is active. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + break; + } + } + + /* Restore the hardware trigger setting if it was enabled before. */ + if (bHWTrigger) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + /* Check the CALF at the end of calibration. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + } + if (kStatus_Success != status) /* Check if the calibration process is succeed. */ + { + return status; + } + + /* Calculate the calibration values. */ + tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->PG = tmp32; + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->MG = tmp32; +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + + return kStatus_Success; +} +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) +{ + if (kADC16_ChannelMuxA == mode) + { + base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; + } + else /* kADC16_ChannelMuxB. */ + { + base->CFG2 |= ADC_CFG2_MUXSEL_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) +{ + uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); + + if (!config) /* Pass "NULL" to disable the feature. */ + { + base->SC2 = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_SC2_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC16_HardwareCompareMode0: + break; + case kADC16_HardwareCompareMode1: + tmp32 |= ADC_SC2_ACFGT_MASK; + break; + case kADC16_HardwareCompareMode2: + tmp32 |= ADC_SC2_ACREN_MASK; + break; + case kADC16_HardwareCompareMode3: + tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; + break; + default: + break; + } + base->SC2 = tmp32; + + /* Load the compare values. */ + base->CV1 = ADC_CV1_CV(config->value1); + base->CV2 = ADC_CV2_CV(config->value2); +} + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) +{ + uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); + + if (kADC16_HardwareAverageDisabled != mode) + { + tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); + } + base->SC3 = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) +{ + uint32_t tmp32; + + if (!config) /* Passing "NULL" is to disable the feature. */ + { + base->PGA = 0U; + return; + } + + /* Enable the PGA and set the gain value. */ + tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); + + /* Configure the misc features for PGA. */ + if (config->enableRunInNormalMode) + { + tmp32 |= ADC_PGA_PGALPb_MASK; + } +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + if (config->disablePgaChopping) + { + tmp32 |= ADC_PGA_PGACHPb_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + if (config->enableRunInOffsetMeasurement) + { + tmp32 |= ADC_PGA_PGAOFSM_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ + base->PGA = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +uint32_t ADC16_GetStatusFlags(ADC_Type *base) +{ + uint32_t ret = 0; + + if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) + { + ret |= kADC16_ActiveFlag; + } +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) + { + ret |= kADC16_CalibrationFailedFlag; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + return ret; +} + +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (mask & kADC16_CalibrationFailedFlag)) + { + base->SC3 |= ADC_SC3_CALF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +} + +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) +{ + assert(channelGroup < ADC_SC1_COUNT); + assert(NULL != config); + + uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + /* Enable the differential conversion. */ + if (config->enableDifferentialConversion) + { + sc1 |= ADC_SC1_DIFF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + /* Enable the interrupt when the conversion is done. */ + if (config->enableInterruptOnConversionCompleted) + { + sc1 |= ADC_SC1_AIEN_MASK; + } + base->SC1[channelGroup] = sc1; +} + +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_SC1_COUNT); + + uint32_t ret = 0U; + + if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) + { + ret |= kADC16_ChannelConversionDoneFlag; + } + return ret; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h new file mode 100755 index 00000000000..c6b5bc0d1ae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC16_H_ +#define _FSL_ADC16_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc16 + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ADC16 driver version 2.0.0. */ +#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Channel status flags. + */ +enum _adc16_channel_status_flags +{ + kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ +}; + +/*! + * @brief Converter status flags. + */ +enum _adc16_status_flags +{ + kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +}; + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Channel multiplexer mode for each channel. + * + * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b + * are the different channels but share the same channel number. + */ +typedef enum _adc_channel_mux_mode +{ + kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ + kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ +} adc16_channel_mux_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc16_clock_divider +{ + kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc16_clock_divider_t; + +/*! + *@brief Converter's resolution. + */ +typedef enum _adc16_resolution +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ + kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ + kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ + + /* This group of enumeration is for public user. */ + kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ + kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ + kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ + kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ + kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + +#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) + /* 16-bit is supported by default. */ + kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ + kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ +} adc16_resolution_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc16_clock_source +{ + kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ + kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ + kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ + kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ + + /* Chip defined clock source */ + kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ +} adc16_clock_source_t; + +/*! + * @brief Long sample mode. + */ +typedef enum _adc16_long_sample_mode +{ + kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ + kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ + kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ + kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ + kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ +} adc16_long_sample_mode_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc16_reference_voltage_source +{ + kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ + kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ +} adc16_reference_voltage_source_t; + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Hardware average mode. + */ +typedef enum _adc16_hardware_average_mode +{ + kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ +} adc16_hardware_average_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +/*! + * @brief Hardware compare mode. + */ +typedef enum _adc16_hardware_compare_mode +{ + kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ + kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ + kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; + else, value1 > x > value2. */ + kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; + else x >= value1 || x <= value2. */ +} adc16_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief PGA's Gain mode. + */ +typedef enum _adc16_pga_gain +{ + kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ + kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ + kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ + kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ + kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ + kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ + kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ +} adc16_pga_gain_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief ADC16 converter configuration . + */ +typedef struct _adc16_config +{ + adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ + bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ + adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ + adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ + adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable low power. */ + bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ +} adc16_config_t; + +/*! + * @brief ADC16 Hardware compare configuration. + */ +typedef struct _adc16_hardware_compare_config +{ + adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc16_hardware_compare_mode_t". */ + int16_t value1; /*!< Setting value1 for hardware compare mode. */ + int16_t value2; /*!< Setting value2 for hardware compare mode. */ +} adc16_hardware_compare_config_t; + +/*! + * @brief ADC16 channel conversion configuration. + */ +typedef struct _adc16_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + bool enableDifferentialConversion; /*!< Using Differential sample mode. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +} adc16_channel_config_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief ADC16 programmable gain amplifier configuration. + */ +typedef struct _adc16_pga_config +{ + adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ + bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + bool disablePgaChopping; /*!< Disable the PGA chopping function. + The PGA employs chopping to remove/reduce offset and 1/f noise and offers + an offset measurement configuration that aids the offset calibration. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. + When this feature is enabled, the PGA disconnects itself from the external + inputs and auto-configures into offset measurement mode. With this field + set, run the ADC in the recommended settings and enable the maximum hardware + averaging to get the PGA offset number. The output is the + (PGA offset * (64+1)) for the given PGA setting. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ +} adc16_pga_config_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to configuration structure. See "adc16_config_t". + */ +void ADC16_Init(ADC_Type *base, const adc16_config_t *config); + +/*! + * @brief De-initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + */ +void ADC16_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for converter's configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + * config->clockSource = kADC16_ClockSourceAsynchronousClock; + * config->enableAsynchronousClock = true; + * config->clockDivider = kADC16_ClockDivider8; + * config->resolution = kADC16_ResolutionSE12Bit; + * config->longSampleMode = kADC16_LongSampleDisabled; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableContinuousConversion = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void ADC16_GetDefaultConfig(adc16_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation. + * Execute the calibration before using the converter. Note that the hardware trigger should be used + * during calibration. + * + * @param base ADC16 peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration is failed. + */ +status_t ADC16_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION +/*! + * @brief Sets the offset value for the conversion result. + * + * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result + * is subtracted by it. Note, the hardware calibration fills the offset value automatically. + * + * @param base ADC16 peripheral base address. + * @param value Setting offset value. + */ +static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFS = (uint32_t)(value); +} +#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ + +/* @} */ + +/*! + * @name Advanced Feature + * @{ + */ + +#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA +/*! + * @brief Enables generating the DMA trigger when conversion is completed. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of DMA feature. "true" means to enable, "false" means not. + */ +static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_DMAEN_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_DMAEN_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_DMA */ + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not. + */ +static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } +} + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Sets the channel mux mode. + * + * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an + * indicated channel. + * + * @param base ADC16 peripheral base address. + * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". + */ +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result + * in + * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference + * manual document for more detailed information. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature. + */ +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Sets the hardware average mode. + * + * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple + * conversion results are accumulated and averaged internally. This aids reading results. + * + * @param base ADC16 peripheral base address. + * @param mode Setting hardware average mode. See "adc16_hardware_average_mode_t". + */ +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief Configures the PGA for converter's front end. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature. + */ +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief Gets the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". + */ +uint32_t ADC16_GetStatusFlags(ADC_Type *base); + +/*! + * @brief Clears the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * @param mask Mask value for the cleared flags. See "_adc16_status_flags". + */ +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Conversion Channel + * @{ + */ + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one + * group of status and control register, one for each conversion. The channel group parameter indicates which group of + * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware + * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion. + * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to "adc16_channel_config_t" structure for conversion channel. + */ +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". + */ +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_ADC16_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c new file mode 100755 index 00000000000..5f0eba1d37a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c @@ -0,0 +1,408 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if (defined(OSC) && !(defined(OSC0))) +#define OSC0 OSC +#endif + +#define MCG_HIRC_FREQ (48000000U) +#define MCG_LIRC_FREQ1 (2000000U) +#define MCG_LIRC_FREQ2 (8000000U) + +#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) +#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) +#define MCG_MC_LIRC_DIV2_VAL ((MCG->MC & MCG_MC_LIRC_DIV2_MASK) >> MCG_MC_LIRC_DIV2_SHIFT) +#define MCG_C2_IRCS_VAL ((MCG->C2 & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT) + +#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) +#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) +#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL0 (OSC0) clock frequency. */ +uint32_t g_xtal0Freq; + +/* External XTAL32K clock frequency. */ +uint32_t g_xtal32Freq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the current MCG_Lite LIRC_CLK frequency in Hz. + * + * This function will return the LIRC_CLK value in frequency(Hz) based + * on current MCG_Lite configurations and settings. It is an internal function. + * + * @return MCG_Lite LIRC_CLK frequency. + */ +static uint32_t CLOCK_GetLircClkFreq(void); + +/*! + * @brief Get RANGE value based on OSC frequency. + * + * To setup external crystal oscillator, must set the register bits RANGE base + * on the crystal frequency. This function returns the RANGE base on the input + * frequency. This is an internal function. + * + * @return RANGE value. + */ +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetLircClkFreq(void) +{ + static const uint32_t lircFreqs[] = {MCG_LIRC_FREQ1, MCG_LIRC_FREQ2}; + + /* Check whether the LIRC is enabled. */ + if ((MCG->C1 & MCG_C1_IRCLKEN_MASK) || (kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL)) + { + return lircFreqs[MCG_C2_IRCS_VAL]; + } + else + { + return 0U; + } +} + +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) +{ + uint8_t range; + + if (freq <= 39063U) + { + range = 0U; + } + else if (freq <= 8000000U) + { + range = 1U; + } + else + { + range = 2U; + } + + return range; +} + +uint32_t CLOCK_GetOsc0ErClkFreq(void) +{ + if (OSC0->CR & OSC_CR_ERCLKEN_MASK) + { + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + return g_xtal0Freq; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetEr32kClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT1_OSC32KSEL_VAL) + { + case 0U: /* OSC 32k clock */ + freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; + break; + case 2U: /* RTC 32k clock */ + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 3U: /* LPO clock */ + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; + } + return freq; +} + +uint32_t CLOCK_GetPlatClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFlashClkFreq(void) +{ + uint32_t freq; + + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); + + return freq; +} + +uint32_t CLOCK_GetBusClkFreq(void) +{ + uint32_t freq; + + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); + + return freq; +} + +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + case kCLOCK_PlatClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + break; + case kCLOCK_BusClk: + case kCLOCK_FlashClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); + break; + case kCLOCK_Er32kClk: + freq = CLOCK_GetEr32kClkFreq(); + break; + case kCLOCK_Osc0ErClk: + freq = CLOCK_GetOsc0ErClkFreq(); + break; + case kCLOCK_McgInternalRefClk: + freq = CLOCK_GetInternalRefClkFreq(); + break; + case kCLOCK_McgPeriphClk: + case kCLOCK_McgIrc48MClk: + freq = CLOCK_GetPeriphClkFreq(); + break; + case kCLOCK_LpoClk: + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_SetSimConfig(sim_clock_config_t const *config) +{ + SIM->CLKDIV1 = config->clkdiv1; + CLOCK_SetEr32kClock(config->er32kSrc); +} + +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcExt == src) + { + SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; + } + else + { + SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK; + } + + CLOCK_EnableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcIrc48M == src) + { + USB0->CLK_RECOVER_IRC_EN = 0x03U; + USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; + } + + return ret; +} + +uint32_t CLOCK_GetInternalRefClkFreq(void) +{ + uint8_t divider1 = MCG_SC_FCRDIV_VAL; + uint8_t divider2 = MCG_MC_LIRC_DIV2_VAL; + /* LIRC internal reference clock is selected*/ + return CLOCK_GetLircClkFreq() >> (divider1 + divider2); +} + +uint32_t CLOCK_GetPeriphClkFreq(void) +{ + /* Check whether the HIRC is enabled. */ + if ((MCG->MC & MCG_MC_HIRCEN_MASK) || (kMCGLITE_ClkSrcHirc == MCG_S_CLKST_VAL)) + { + return MCG_HIRC_FREQ; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetOutClkFreq(void) +{ + uint32_t freq; + + switch (MCG_S_CLKST_VAL) + { + case kMCGLITE_ClkSrcHirc: + freq = MCG_HIRC_FREQ; + break; + case kMCGLITE_ClkSrcLirc: + freq = CLOCK_GetLircClkFreq() >> MCG_SC_FCRDIV_VAL; + break; + case kMCGLITE_ClkSrcExt: + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + freq = g_xtal0Freq; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +mcglite_mode_t CLOCK_GetMode(void) +{ + mcglite_mode_t mode; + + switch (MCG_S_CLKST_VAL) + { + case kMCGLITE_ClkSrcHirc: /* HIRC */ + mode = kMCGLITE_ModeHirc48M; + break; + case kMCGLITE_ClkSrcLirc: /* LIRC */ + if (kMCGLITE_Lirc2M == MCG_C2_IRCS_VAL) + { + mode = kMCGLITE_ModeLirc2M; + } + else + { + mode = kMCGLITE_ModeLirc8M; + } + break; + case kMCGLITE_ClkSrcExt: /* EXT */ + mode = kMCGLITE_ModeExt; + break; + default: + mode = kMCGLITE_ModeError; + break; + } + + return mode; +} + +status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig) +{ + assert(targetConfig); + + /* + * If switch between LIRC8M and LIRC2M, need to switch to HIRC mode first, + * because could not switch directly. + */ + if ((kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL) && (kMCGLITE_ClkSrcLirc == targetConfig->outSrc) && + (MCG_C2_IRCS_VAL != targetConfig->ircs)) + { + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCGLITE_ClkSrcHirc); + while (kMCGLITE_ClkSrcHirc != MCG_S_CLKST_VAL) + { + } + } + + /* Set configuration now. */ + MCG->SC = MCG_SC_FCRDIV(targetConfig->fcrdiv); + MCG->MC = MCG_MC_HIRCEN(targetConfig->hircEnableInNotHircMode) | MCG_MC_LIRC_DIV2(targetConfig->lircDiv2); + MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | MCG_C2_IRCS(targetConfig->ircs); + MCG->C1 = MCG_C1_CLKS(targetConfig->outSrc) | targetConfig->irclkEnableMode; + + /* + * If external oscillator used and MCG_Lite is set to EXT mode, need to + * wait for the OSC stable. + */ + if ((MCG->C2 & MCG_C2_EREFS0_MASK) && (kMCGLITE_ClkSrcExt == targetConfig->outSrc)) + { + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } + + /* Wait for clock source change completed. */ + while (targetConfig->outSrc != MCG_S_CLKST_VAL) + { + } + + return kStatus_Success; +} + +void CLOCK_InitOsc0(osc_config_t const *config) +{ + uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); + + OSC_SetCapLoad(OSC0, config->capLoad); + OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); + + MCG->C2 = ((MCG->C2 & MCG_C2_IRCS_MASK) | MCG_C2_RANGE0(range) | (uint8_t)config->workMode); + + if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) + { + /* Wait for stable. */ + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } +} + +void CLOCK_DeinitOsc0(void) +{ + OSC0->CR = 0U; + MCG->C2 &= MCG_C2_IRCS_MASK; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h new file mode 100755 index 00000000000..b1f95fd5211 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h @@ -0,0 +1,792 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! @addtogroup clock */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock driver version. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief External XTAL0 (OSC0) clock frequency. + * + * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example, + * if XTAL0 is 8MHz, + * @code + * CLOCK_InitOsc0(...); // Setup the OSC0 + * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver. + * @endcode + * + * This is important for the multicore platforms, only one core needs to setup + * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq + * to get valid clock frequency. + */ +extern uint32_t g_xtal0Freq; + +/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. + * + * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtal32Freq to set the value in to clock driver. + * + * This is important for the multicore platforms, only one core needs to setup + * the clock, all other cores need to call CLOCK_SetXtal32Freq + * to get valid clock frequency. + */ +extern uint32_t g_xtal32Freq; + +/*! @brief Clock ip name array for DMAMUX. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dmamux0 \ + } + +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } + +/*! @brief Clock ip name array for SPI. */ +#define SPI_CLOCKS \ + { \ + kCLOCK_Spi0, kCLOCK_Spi1 \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit0 \ + } + +/*! @brief Clock ip name array for PORT. */ +#define PORT_CLOCKS \ + { \ + kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_Lpuart0, kCLOCK_Lpuart1 \ + } + +/*! @brief Clock ip name array for LPTMR. */ +#define LPTMR_CLOCKS \ + { \ + kCLOCK_Lptmr0 \ + } + +/*! @brief Clock ip name array for ADC16. */ +#define ADC16_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_Flexio0 \ + } + +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref0 \ + } + +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0 \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Uart2 \ + } + +/*! @brief Clock ip name array for TPM. */ +#define TPM_CLOCKS \ + { \ + kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \ + } + +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_I2c0, kCLOCK_I2c1 \ + } + +/*! @brief Clock ip name array for FTF. */ +#define FTF_CLOCKS \ + { \ + kCLOCK_Ftf0 \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \ + } + +/*! + * @brief LPO clock frequency. + */ +#define LPO_CLK_FREQ 1000U + +/*! @brief Peripherals clock source definition. */ +#define SYS_CLK kCLOCK_CoreSysClk +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC SYS_CLK +#define I2C1_CLK_SRC SYS_CLK +#define SPI0_CLK_SRC BUS_CLK +#define SPI1_CLK_SRC SYS_CLK +#define UART2_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + + /* ----------------------------- System layer clock -------------------------------*/ + kCLOCK_CoreSysClk, /*!< Core/system clock */ + kCLOCK_PlatClk, /*!< Platform clock */ + kCLOCK_BusClk, /*!< Bus clock */ + kCLOCK_FlexBusClk, /*!< FlexBus clock */ + kCLOCK_FlashClk, /*!< Flash clock */ + kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ + kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ + + /* ---------------------------------- OSC clock -----------------------------------*/ + kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ + kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ + kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ + kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ + + /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ + kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ + kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ + kCLOCK_McgFllClk, /*!< MCGFLLCLK */ + kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ + kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ + kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ + kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ + kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ + + /* --------------------------------- Other clock ----------------------------------*/ + kCLOCK_LpoClk, /*!< LPO clock */ + +} clock_name_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U), /*!< Use IRC48M. */ + kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ +} clock_usb_src_t; +/*------------------------------------------------------------------------------ + + clock_gate_t definition: + + 31 16 0 + ----------------------------------------------------------------- + | SIM_SCGC register offset | control bit offset in SCGC | + ----------------------------------------------------------------- + + For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the + SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as + + kCLOCK_GateSdhc0 = (0x1030 << 16) | 17; + +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 16U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), + kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), + kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), + kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), + kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), + kCLOCK_Spi0 = CLK_GATE_DEFINE(0x1034U, 22U), + kCLOCK_Spi1 = CLK_GATE_DEFINE(0x1034U, 23U), + + kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), + kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), + kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), + kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), + kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), + kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), + kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U), + kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U), + kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U), + + kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), + kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), + kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), + kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), + kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U), + kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U), + kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U), + kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), + kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), + + kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U), +} clock_ip_name_t; + +/*!@brief SIM configuration structure for clock setting. */ +typedef struct _sim_clock_config +{ + uint8_t er32kSrc; /*!< ERCLK32K source selection. */ + uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ +} sim_clock_config_t; + +/*! @brief Oscillator capacitor load setting.*/ +enum _osc_cap_load +{ + kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ + kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ + kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ + kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ +}; + +/*! @brief OSCERCLK enable mode. */ +enum _oscer_enable_mode +{ + kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ + kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ +}; + +/*! @brief OSC configuration for OSCERCLK. */ +typedef struct _oscer_config +{ + uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of \ref _oscer_enable_mode. */ + +} oscer_config_t; + +/*! @brief OSC work mode. */ +typedef enum _osc_mode +{ + kOSC_ModeExt = 0U, /*!< Use external clock. */ + kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ + kOSC_ModeOscHighGain = MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ +} osc_mode_t; + +/*! + * @brief OSC Initialization Configuration Structure + * + * Defines the configuration data structure to initialize the OSC. + * When porting to a new board, set the following members + * according to board settings: + * 1. freq: The external frequency. + * 2. workMode: The OSC module mode. + */ +typedef struct _osc_config +{ + uint32_t freq; /*!< External clock frequency. */ + uint8_t capLoad; /*!< Capacitor load setting. */ + osc_mode_t workMode; /*!< OSC work mode setting. */ + oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ +} osc_config_t; + +/*! @brief MCG_Lite clock source selection. */ +typedef enum _mcglite_clkout_src +{ + kMCGLITE_ClkSrcHirc, /*!< MCGOUTCLK source is HIRC */ + kMCGLITE_ClkSrcLirc, /*!< MCGOUTCLK source is LIRC */ + kMCGLITE_ClkSrcExt, /*!< MCGOUTCLK source is external clock source */ + kMCGLITE_ClkSrcReserved +} mcglite_clkout_src_t; + +/*! @brief MCG_Lite LIRC select. */ +typedef enum _mcglite_lirc_mode +{ + kMCGLITE_Lirc2M, /*!< Slow internal reference(LIRC) 2MHz clock selected */ + kMCGLITE_Lirc8M, /*!< Slow internal reference(LIRC) 8MHz clock selected */ +} mcglite_lirc_mode_t; + +/*! @brief MCG_Lite divider factor selection for clock source*/ +typedef enum _mcglite_lirc_div +{ + kMCGLITE_LircDivBy1 = 0U, /*!< Divider is 1 */ + kMCGLITE_LircDivBy2, /*!< Divider is 2 */ + kMCGLITE_LircDivBy4, /*!< Divider is 4 */ + kMCGLITE_LircDivBy8, /*!< Divider is 8 */ + kMCGLITE_LircDivBy16, /*!< Divider is 16 */ + kMCGLITE_LircDivBy32, /*!< Divider is 32 */ + kMCGLITE_LircDivBy64, /*!< Divider is 64 */ + kMCGLITE_LircDivBy128 /*!< Divider is 128 */ +} mcglite_lirc_div_t; + +/*! @brief MCG_Lite clock mode definitions */ +typedef enum _mcglite_mode +{ + kMCGLITE_ModeHirc48M, /*!< Clock mode is HIRC 48 M */ + kMCGLITE_ModeLirc8M, /*!< Clock mode is LIRC 8 M */ + kMCGLITE_ModeLirc2M, /*!< Clock mode is LIRC 2 M */ + kMCGLITE_ModeExt, /*!< Clock mode is EXT */ + kMCGLITE_ModeError /*!< Unknown mode */ +} mcglite_mode_t; + +/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ +enum _mcglite_irclk_enable_mode +{ + kMCGLITE_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ + kMCGLITE_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ +}; + +/*! @brief MCG_Lite configure structure for mode change. */ +typedef struct _mcglite_config +{ + mcglite_clkout_src_t outSrc; /*!< MCGOUT clock select. */ + uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode, OR'ed value of _mcglite_irclk_enable_mode. */ + mcglite_lirc_mode_t ircs; /*!< MCG_C2[IRCS]. */ + mcglite_lirc_div_t fcrdiv; /*!< MCG_SC[FCRDIV]. */ + mcglite_lirc_div_t lircDiv2; /*!< MCG_MC[LIRC_DIV2]. */ + bool hircEnableInNotHircMode; /*!< HIRC enable when not in HIRC mode. */ +} mcglite_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set the XTAL0 frequency based on board setting. + * + * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal0Freq(uint32_t freq) +{ + g_xtal0Freq = freq; +} + +/*! + * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting. + * + * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal32Freq(uint32_t freq) +{ + g_xtal32Freq = freq; +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Set ERCLK32K source. + * + * @param src The value to set ERCLK32K clock source. + */ +static inline void CLOCK_SetEr32kClock(uint32_t src) +{ + SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); +} + +/*! + * @brief Set LPUART0 clock source. + * + * @param src The value to set LPUART0 clock source. + */ +static inline void CLOCK_SetLpuart0Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src)); +} + +/*! + * @brief Set LPUART1 clock source. + * + * @param src The value to set LPUART1 clock source. + */ +static inline void CLOCK_SetLpuart1Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) | SIM_SOPT2_LPUART1SRC(src)); +} + +/*! + * @brief Set TPM clock source. + * + * @param src The value to set TPM clock source. + */ +static inline void CLOCK_SetTpmClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src)); +} + +/*! + * @brief Set FLEXIO clock source. + * + * @param src The value to set FLEXIO clock source. + */ +static inline void CLOCK_SetFlexio0Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src)); +} + +/*! @brief Enable USB FS clock. + * + * @param src USB FS clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB FS clock. + */ +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB FS clock. + * + * Disable USB FS clock. + */ +static inline void CLOCK_DisableUsbfs0Clock(void) +{ + CLOCK_DisableClock(kCLOCK_Usbfs0); +} + +/*! + * @brief Set CLKOUT source. + * + * @param src The value to set CLKOUT source. + */ +static inline void CLOCK_SetClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); +} + +/*! + * @brief Set RTC_CLKOUT source. + * + * @param src The value to set RTC_CLKOUT source. + */ +static inline void CLOCK_SetRtcClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); +} + +/*! + * @brief System clock divider + * + * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4]. + * + * @param outdiv1 Clock 1 output divider value. + * + * @param outdiv4 Clock 4 output divider value. + */ +static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4) +{ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4); +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * The MCG must be properly configured before using this function. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in Hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Get the core clock or system clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! + * @brief Get the platform clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetPlatClkFreq(void); + +/*! + * @brief Get the bus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetBusClkFreq(void); + +/*! + * @brief Get the flash clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlashClkFreq(void); + +/*! + * @brief Get the external reference 32K clock frequency (ERCLK32K). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetEr32kClkFreq(void); + +/*! + * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetOsc0ErClkFreq(void); + +/*! + * @brief Set the clock configure in SIM module. + * + * This function sets system layer clock settings in SIM module. + * + * @param config Pointer to the configure structure. + */ +void CLOCK_SetSimConfig(sim_clock_config_t const *config); + +/*! + * @brief Set the system clock dividers in SIM to safe value. + * + * The system level clocks (core clock, bus clock, flexbus clock and flash clock) + * must be in allowed ranges. During MCG clock mode switch, the MCG output clock + * changes then the system level clocks may be out of range. This function could + * be used before MCG mode change, to make sure system level clocks are in allowed + * range. + * + * @param config Pointer to the configure structure. + */ +static inline void CLOCK_SetSimSafeDivs(void) +{ + SIM->CLKDIV1 = 0x10030000U; +} + +/*! + * @name MCG_Lite clock frequency + * @{ + */ + +/*! + * @brief Gets the MCG_Lite output clock (MCGOUTCLK) frequency. + * + * This function gets the MCG_Lite output clock frequency (Hz) based on the current + * MCG_Lite register value. + * + * @return The frequency of MCGOUTCLK. + */ +uint32_t CLOCK_GetOutClkFreq(void); + +/*! + * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency. + * + * This function gets the MCG_Lite internal reference clock frequency (Hz) based + * on the current MCG register value. + * + * @return The frequency of MCGIRCLK. + */ +uint32_t CLOCK_GetInternalRefClkFreq(void); + +/*! +* @brief Gets the current MCGPCLK frequency. +* +* This function gets the MCGPCLK frequency (Hertz) based on the current MCG_Lite +* register settings. +* +* @return The frequency of MCGPCLK. +*/ +uint32_t CLOCK_GetPeriphClkFreq(void); + +/*! @}*/ + +/*! + * @name MCG_Lite mode. + * @{ + */ + +/*! + * @brief Gets the current MCG_Lite mode. + * + * This function checks the MCG_Lite registers and determines the current MCG_Lite mode. + * + * @return Current MCG_Lite mode or error code. + */ +mcglite_mode_t CLOCK_GetMode(void); + +/*! + * @brief Sets the MCG_Lite configuration. + * + * This function configures the MCG_Lite, include output clock source, MCGIRCLK + * setting, HIRC setting and so on, see @ref mcglite_config_t for details. + * + * @param targetConfig Pointer to the target MCG_Lite mode configuration structure. + * @return Error code. + */ +status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig); + +/*! @}*/ + +/*! + * @name OSC configuration + * @{ + */ + +/*! + * @brief Configures the OSC external reference clock (OSCERCLK). + * + * This function configures the OSC external reference clock (OSCERCLK). + * For example, to enable the OSCERCLK in normal mode and stop mode, and also set + * the output divider to 1, as follows: + * + @code + oscer_config_t config = + { + .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, + .erclkDiv = 1U, + }; + + OSC_SetExtRefClkConfig(OSC, &config); + @endcode + * + * @param base OSC peripheral address. + * @param config Pointer to the configuration structure. + */ +static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); + reg |= config->enableMode; + + base->CR = reg; +} + +/*! + * @brief Sets the capacitor load configuration for the oscillator. + * + * This function sets the specified capacitors configuration for the oscillator. + * This should be done in the early system level initialization function call + * based on the system configuration. + * + * @param base OSC peripheral address. + * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. + * + * Example: + @code + // To enable only 2 pF and 8 pF capacitor load, please use like this. + OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); + @endcode + */ + +static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Initialize OSC0. + * + * This function initializes the OSC0 according to the board configuration. + * + * @param config Pointer to the OSC0 configuration structure. + */ +void CLOCK_InitOsc0(osc_config_t const *config); + +/*! + * @brief Deinitializes the OSC0. + * + * This function deinitializes the OSC0. + */ +void CLOCK_DeinitOsc0(void); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c new file mode 100755 index 00000000000..09885e74211 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmp.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for CMP module. + * + * @param base CMP peripheral base address + */ +static uint32_t CMP_GetInstance(CMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CMP bases for each instance. */ +static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; +/*! @brief Pointers to CMP clocks for each instance. */ +const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t CMP_GetInstance(CMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++) + { + if (s_cmpBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_CMP_COUNT); + + return instance; +} + +void CMP_Init(CMP_Type *base, const cmp_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* Enable the clock. */ + CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); + + /* Configure. */ + CMP_Enable(base, false); /* Disable the CMP module during configuring. */ + /* CMPx_CR1. */ + tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); + if (config->enableHighSpeed) + { + tmp8 |= CMP_CR1_PMODE_MASK; + } + if (config->enableInvertOutput) + { + tmp8 |= CMP_CR1_INV_MASK; + } + if (config->useUnfilteredOutput) + { + tmp8 |= CMP_CR1_COS_MASK; + } + if (config->enablePinOut) + { + tmp8 |= CMP_CR1_OPE_MASK; + } +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + if (config->enableTriggerMode) + { + tmp8 |= CMP_CR1_TRIGM_MASK; + } + else + { + tmp8 &= ~CMP_CR1_TRIGM_MASK; + } +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + base->CR1 = tmp8; + + /* CMPx_CR0. */ + tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; + tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); + base->CR0 = tmp8; + + CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ +} + +void CMP_Deinit(CMP_Type *base) +{ + /* Disable the CMP module. */ + CMP_Enable(base, false); + + /* Disable the clock. */ + CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); +} + +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + assert(NULL != config); + + config->enableCmp = true; /* Enable the CMP module after initialization. */ + config->hysteresisMode = kCMP_HysteresisLevel0; + config->enableHighSpeed = false; + config->enableInvertOutput = false; + config->useUnfilteredOutput = false; + config->enablePinOut = false; +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} + +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) +{ + uint8_t tmp8 = base->MUXCR; + + tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); + tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); + base->MUXCR = tmp8; +} + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +void CMP_EnableDMA(CMP_Type *base, bool enable) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (enable) + { + tmp8 |= CMP_SCR_DMAEN_MASK; + } + else + { + tmp8 &= ~CMP_SCR_DMAEN_MASK; + } + base->SCR = tmp8; +} +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + /* Choose the clock source for sampling. */ + if (config->enableSample) + { + base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ + } + else + { + base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ + } +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + /* Set the filter count. */ + tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; + tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); + base->CR0 = tmp8; + /* Set the filter period. It is used as the divider to bus clock. */ + base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); +} + +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) +{ + uint8_t tmp8 = 0U; + + if (NULL == config) + { + /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ + base->DACCR = 0U; + return; + } + /* CMPx_DACCR. */ + tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ + if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) + { + tmp8 |= CMP_DACCR_VRSEL_MASK; + } + tmp8 |= CMP_DACCR_VOSEL(config->DACValue); + + base->DACCR = tmp8; +} + +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +uint32_t CMP_GetStatusFlags(CMP_Type *base) +{ + uint32_t ret32 = 0U; + + if (0U != (CMP_SCR_CFR_MASK & base->SCR)) + { + ret32 |= kCMP_OutputRisingEventFlag; + } + if (0U != (CMP_SCR_CFF_MASK & base->SCR)) + { + ret32 |= kCMP_OutputFallingEventFlag; + } + if (0U != (CMP_SCR_COUT_MASK & base->SCR)) + { + ret32 |= kCMP_OutputAssertEventFlag; + } + return ret32; +} + +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFR_MASK; + } + if (0U != (kCMP_OutputFallingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFF_MASK; + } + base->SCR = tmp8; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h new file mode 100755 index 00000000000..53d84a0f2d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CMP_H_ +#define _FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMP driver version 2.0.0. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! +* @brief Interrupt enable/disable mask. +*/ +enum _cmp_interrupt_enable +{ + kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ + kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ +}; + +/*! + * @brief Status flags' mask. + */ +enum _cmp_status_flags +{ + kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on compare output has occurred. */ + kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */ + kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ +}; + +/*! + * @brief CMP Hysteresis mode. + */ +typedef enum _cmp_hysteresis_mode +{ + kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ + kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ + kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ + kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ +} cmp_hysteresis_mode_t; + +/*! + * @brief CMP Voltage Reference source. + */ +typedef enum _cmp_reference_voltage_source +{ + kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */ + kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */ +} cmp_reference_voltage_source_t; + +/*! + * @brief Configure the comparator. + */ +typedef struct _cmp_config +{ + bool enableCmp; /*!< Enable the CMP module. */ + cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ + bool enableHighSpeed; /*!< Enable High Speed (HS) comparison mode. */ + bool enableInvertOutput; /*!< Enable inverted comparator output. */ + bool useUnfilteredOutput; /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */ + bool enablePinOut; /*!< The comparator output is available on the associated pin. */ +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool enableTriggerMode; /*!< Enable the trigger mode. */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} cmp_config_t; + +/*! + * @brief Configure the filter. + */ +typedef struct _cmp_filter_config +{ +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + bool enableSample; /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */ +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/ + uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */ +} cmp_filter_config_t; + +/*! + * @brief Configure the internal DAC. + */ +typedef struct _cmp_dac_config +{ + cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ + uint8_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-63.*/ +} cmp_dac_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are: + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config); + +/*! + * @brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are: + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * @param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base); + +/*! + * @brief Enables/disables the CMP module. + * + * @param base CMP peripheral base address. + * @param enable Enable the module or not. + */ +static inline void CMP_Enable(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_EN_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_EN_MASK; + } +} + +/*! +* @brief Initializes the CMP user configuration structure. +* +* This function initializes the user configure structure to these default values: +* @code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* @endcode +* @param config Pointer to the configuration structure. +*/ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/*! + * @brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set as same in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * @param base CMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA + * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP + * if the + * DMA is disabled. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable); +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE +/*! + * @brief Enables/disables the window mode. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_WE_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_WE_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ + +#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE +/*! + * @brief Enables/disables the pass through mode. + * + * @param base CMP peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->MUXCR |= CMP_MUXCR_PSTM_MASK; + } + else + { + base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ + +/*! + * @brief Configures the filter. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); + +/*! + * @brief Configures the internal DAC. + * + * @param base CMP peripheral base address. + * @param config Pointer to configuration structure. "NULL" is for disabling the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); + +/*! + * @brief Enables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Results + * @{ + */ + +/*! + * @brief Gets the status flags. + * + * @param base CMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base); + +/*! + * @brief Clears the status flags. + * + * @param base CMP peripheral base address. + * @param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_CMP_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c new file mode 100755 index 00000000000..895bbb04a00 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +/* This is not needed for mbed */ +#if 0 +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __asm("bkpt #0"); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __asm("bkpt #0"); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ +#endif +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + + __disable_irq(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + __enable_irq(); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h new file mode 100755 index 00000000000..105dca049a7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Enable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void EnableIRQ(IRQn_Type interrupt) +{ +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { + NVIC_EnableIRQ(interrupt); + } +} + +/*! + * @brief Disable specific interrupt. + * + * Disable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void DisableIRQ(IRQn_Type interrupt) +{ +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { + NVIC_DisableIRQ(interrupt); + } +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +} + +/*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ + __set_PRIMASK(primask); +} + +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + */ +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c new file mode 100755 index 00000000000..16add3b2618 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cop.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void COP_GetDefaultConfig(cop_config_t *config) +{ + assert(config); + + config->enableWindowMode = false; +#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE + config->timeoutMode = kCOP_LongTimeoutMode; + config->enableStop = false; + config->enableDebug = false; +#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ + config->clockSource = kCOP_LpoClock; + config->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles; +} + +void COP_Init(SIM_Type *base, const cop_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + +#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE + value = SIM_COPC_COPW(config->enableWindowMode) | SIM_COPC_COPCLKS(config->timeoutMode) | + SIM_COPC_COPT(config->timeoutCycles) | SIM_COPC_COPSTPEN(config->enableStop) | + SIM_COPC_COPDBGEN(config->enableDebug) | SIM_COPC_COPCLKSEL(config->clockSource); +#else + value = SIM_COPC_COPW(config->enableWindowMode) | SIM_COPC_COPCLKS(config->clockSource) | + SIM_COPC_COPT(config->timeoutCycles); +#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ + base->COPC = value; +} + +void COP_Refresh(SIM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SRVCOP = COP_FIRST_BYTE_OF_REFRESH; + base->SRVCOP = COP_SECOND_BYTE_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h new file mode 100755 index 00000000000..1a7ab82fab0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_COP_H_ +#define _FSL_COP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cop_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief COP driver version 2.0.0. */ +#define FSL_COP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name COP refresh sequence. */ +/*@{*/ +#define COP_FIRST_BYTE_OF_REFRESH (0x55U) /*!< First byte of refresh sequence */ +#define COP_SECOND_BYTE_OF_REFRESH (0xAAU) /*!< Second byte of refresh sequence */ +/*@}*/ + +/*! @brief COP clock source selection. */ +typedef enum _cop_clock_source +{ + kCOP_LpoClock = 0U, /*!< COP clock sourced from LPO */ +#if defined(FSL_FEATURE_COP_HAS_MORE_CLKSRC) && FSL_FEATURE_COP_HAS_MORE_CLKSRC + kCOP_McgIrClock = 1U, /*!< COP clock sourced from MCGIRCLK */ + kCOP_OscErClock = 2U, /*!< COP clock sourced from OSCERCLK */ +#endif /* FSL_FEATURE_COP_HAS_MORE_CLKSRC */ + kCOP_BusClock = 3U, /*!< COP clock sourced from Bus clock */ +} cop_clock_source_t; + +/*! @brief Define the COP timeout cycles. */ +typedef enum _cop_timeout_cycles +{ + kCOP_2Power5CyclesOr2Power13Cycles = 1U, /*!< 2^5 or 2^13 clock cycles */ + kCOP_2Power8CyclesOr2Power16Cycles = 2U, /*!< 2^8 or 2^16 clock cycles */ + kCOP_2Power10CyclesOr2Power18Cycles = 3U, /*!< 2^10 or 2^18 clock cycles */ +} cop_timeout_cycles_t; + +#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE +/*! @breif Define the COP timeout mode. */ +typedef enum _cop_timeout_mode +{ + kCOP_ShortTimeoutMode = 0U, /*!< COP selects long timeout */ + kCOP_LongTimeoutMode = 1U, /*!< COP selects short timeout */ +} cop_timeout_mode_t; +#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ + +/*! @brief Describes COP configuration structure. */ +typedef struct _cop_config +{ + bool enableWindowMode; /*!< COP run mode: window mode or normal mode */ +#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE + cop_timeout_mode_t timeoutMode; /*!< COP timeout mode: long timeout or short timeout */ + bool enableStop; /*!< Enable or disable COP in STOP mode */ + bool enableDebug; /*!< Enable or disable COP in DEBUG mode */ +#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ + cop_clock_source_t clockSource; /*!< Set COP clock source */ + cop_timeout_cycles_t timeoutCycles; /*!< Set COP timeout value */ +} cop_config_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name COP Functional Operation + * @{ + */ + +/*! + * @brief Initializes the COP configuration structure. + * + * This function initializes the COP configuration structure to default values. The default + * values are: + * @code + * copConfig->enableWindowMode = false; + * copConfig->timeoutMode = kCOP_LongTimeoutMode; + * copConfig->enableStop = false; + * copConfig->enableDebug = false; + * copConfig->clockSource = kCOP_LpoClock; + * copConfig->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles; + * @endcode + * + * @param config Pointer to the COP configuration structure. + * @see cop_config_t + */ +void COP_GetDefaultConfig(cop_config_t *config); + +/*! + * @brief Initializes the COP module. + * + * This function configures the COP. After it is called, the COP + * starts running according to the configuration. + * Because all COP control registers are write-once only, the COP_Init function + * and the COP_Disable function can be called only once. A second call has no effect. + * + * Example: + * @code + * cop_config_t config; + * COP_GetDefaultConfig(&config); + * config.timeoutCycles = kCOP_2Power8CyclesOr2Power16Cycles; + * COP_Init(sim_base,&config); + * @endcode + * + * @param base SIM peripheral base address. + * @param config The configuration of COP. + */ +void COP_Init(SIM_Type *base, const cop_config_t *config); + +/*! + * @brief De-initializes the COP module. + * This dedicated function is not provided. Instead, the COP_Disable function can be used to disable the COP. + */ + +/*! + * @brief Disables the COP module. + * + * This function disables the COP Watchdog. + * Note: The COP configuration register is a write-once after reset. + * To disable the COP Watchdog, call this function first. + * + * @param base SIM peripheral base address. + */ +static inline void COP_Disable(SIM_Type *base) +{ + base->COPC &= ~SIM_COPC_COPT_MASK; +} + +/*! + * @brief Refreshes the COP timer + * + * This function feeds the COP. + * + * @param base SIM peripheral base address. + */ +void COP_Refresh(SIM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_COP_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c new file mode 100755 index 00000000000..f73647e1c78 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! +* @brief CRC module configuration. +* +* This structure holds the configuration for the CRC module. +*/ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + crc_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + crc_ConfigureAndStart(base, &moduleConfig); +} + +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + crc_SetProtocolConfig(base, config); + } + else + { + crc_SetRawProtocolConfig(base, config); + } +} + +void CRC_GetDefaultConfig(crc_config_t *config) +{ + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((dataSize) && ((uint32_t)data & 3U)) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h new file mode 100755 index 00000000000..ce0b60fbaf9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.0. */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! +* @brief CRC protocol configuration. +* +* This structure holds the configuration for the CRC protocol. +* +*/ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral. + * It also configures the CRC module and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +} + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register (intermediate or final checksum). + * The configured type of transpose and complement are applied. + * + * @param base CRC peripheral address. + * @return intermediate or final 32-bit checksum, after configured transpose and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register (intermediate or final checksum). + * The configured type of transpose and complement are applied. + * + * @param base CRC peripheral address. + * @return intermediate or final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c new file mode 100755 index 00000000000..6bef321ca70 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c @@ -0,0 +1,306 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetInstance(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; + +/*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_CHN_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMAMUX_MODULE_CHANNEL * FSL_FEATURE_SOC_DMA_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMA_GetInstance(DMA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DMA_COUNT; instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DMA_COUNT); + + return instance; +} + +void DMA_Init(DMA_Type *base) +{ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +} + +void DMA_Deinit(DMA_Type *base) +{ + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +} + +void DMA_ResetChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + /* clear all status bit */ + base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); + /* clear all registers */ + base->DMA[channel].SAR = 0; + base->DMA[channel].DAR = 0; + base->DMA[channel].DSR_BCR = 0; + /* enable cycle steal and enable auto disable channel request */ + base->DMA[channel].DCR = DMA_DCR_D_REQ(true) | DMA_DCR_CS(true); +} + +void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + /* Set source address */ + base->DMA[channel].SAR = config->srcAddr; + /* Set destination address */ + base->DMA[channel].DAR = config->destAddr; + /* Set transfer bytes */ + base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(config->transferSize); + /* Set DMA Control Register */ + tmpreg = base->DMA[channel].DCR; + tmpreg &= ~(DMA_DCR_DSIZE_MASK | DMA_DCR_DINC_MASK | DMA_DCR_SSIZE_MASK | DMA_DCR_SINC_MASK); + tmpreg |= (DMA_DCR_DSIZE(config->destSize) | DMA_DCR_DINC(config->enableDestIncrement) | + DMA_DCR_SSIZE(config->srcSize) | DMA_DCR_SINC(config->enableSrcIncrement)); + base->DMA[channel].DCR = tmpreg; +} + +void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = base->DMA[channel].DCR; + tmpreg &= ~(DMA_DCR_LINKCC_MASK | DMA_DCR_LCH1_MASK | DMA_DCR_LCH2_MASK); + tmpreg |= (DMA_DCR_LINKCC(config->linkType) | DMA_DCR_LCH1(config->channel1) | DMA_DCR_LCH2(config->channel2)); + base->DMA[channel].DCR = tmpreg; +} + +void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + uint32_t tmpreg; + + tmpreg = base->DMA[channel].DCR; + tmpreg &= ~(DMA_DCR_SMOD_MASK | DMA_DCR_DMOD_MASK); + tmpreg |= (DMA_DCR_SMOD(srcModulo) | DMA_DCR_DMOD(destModulo)); + base->DMA[channel].DCR = tmpreg; +} + +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + uint32_t dmaInstance; + uint32_t channelIndex; + + handle->base = base; + handle->channel = channel; + /* Get the DMA instance number */ + dmaInstance = DMA_GetInstance(base); + channelIndex = (dmaInstance * FSL_FEATURE_DMAMUX_MODULE_CHANNEL) + channel; + /* Store handle */ + s_DMAHandle[channelIndex] = handle; + /* Enable NVIC interrupt. */ + EnableIRQ(s_dmaIRQNumber[channelIndex]); +} + +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t transferBytes, + dma_transfer_type_t type) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); + assert(srcWidth == 1U || srcWidth == 2U || srcWidth == 4U); + assert(destWidth == 1U || destWidth == 2U || destWidth == 4U); + + config->srcAddr = (uint32_t)srcAddr; + config->destAddr = (uint32_t)destAddr; + config->transferSize = transferBytes; + switch (srcWidth) + { + case 1U: + config->srcSize = kDMA_Transfersize8bits; + break; + case 2U: + config->srcSize = kDMA_Transfersize16bits; + break; + case 4U: + config->srcSize = kDMA_Transfersize32bits; + break; + default: + break; + } + switch (destWidth) + { + case 1U: + config->destSize = kDMA_Transfersize8bits; + break; + case 2U: + config->destSize = kDMA_Transfersize16bits; + break; + case 4U: + config->destSize = kDMA_Transfersize32bits; + break; + default: + break; + } + switch (type) + { + case kDMA_MemoryToMemory: + config->enableSrcIncrement = true; + config->enableDestIncrement = true; + break; + case kDMA_PeripheralToMemory: + config->enableSrcIncrement = false; + config->enableDestIncrement = true; + break; + case kDMA_MemoryToPeripheral: + config->enableSrcIncrement = true; + config->enableDestIncrement = false; + break; + default: + break; + } +} + +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options) +{ + assert(handle != NULL); + assert(config != NULL); + + /* Check if DMA is busy */ + if (handle->base->DMA[handle->channel].DSR_BCR & DMA_DSR_BCR_BSY_MASK) + { + return kStatus_DMA_Busy; + } + DMA_ResetChannel(handle->base, handle->channel); + DMA_SetTransferConfig(handle->base, handle->channel, config); + if (options & kDMA_EnableInterrupt) + { + DMA_EnableInterrupts(handle->base, handle->channel); + } + return kStatus_Success; +} + +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(handle != NULL); + + handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK; + /* clear all status bit */ + handle->base->DMA[handle->channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); +} + +void DMA_HandleIRQ(dma_handle_t *handle) +{ + assert(handle != NULL); + + /* Clear interrupt pending bit */ + DMA_ClearChannelStatusFlags(handle->base, handle->channel, kDMA_TransactionsDoneFlag); + if (handle->callback) + { + (handle->callback)(handle, handle->userData); + } +} + +#if defined(FSL_FEATURE_DMAMUX_MODULE_CHANNEL) && (FSL_FEATURE_DMAMUX_MODULE_CHANNEL == 4U) +void DMA0_DriverIRQHandler(void) +{ + DMA_HandleIRQ(s_DMAHandle[0]); +} + +void DMA1_DriverIRQHandler(void) +{ + DMA_HandleIRQ(s_DMAHandle[1]); +} + +void DMA2_DriverIRQHandler(void) +{ + DMA_HandleIRQ(s_DMAHandle[2]); +} + +void DMA3_DriverIRQHandler(void) +{ + DMA_HandleIRQ(s_DMAHandle[3]); +} +#endif /* FSL_FEATURE_DMAMUX_MODULE_CHANNEL */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h new file mode 100755 index 00000000000..b7c00fc0924 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version 2.0.0. */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief status flag for the DMA driver. */ +enum _dma_channel_status_flags +{ + kDMA_TransactionsBCRFlag = DMA_DSR_BCR_BCR_MASK, /*!< Contains the number of bytes yet to be + transferred for a given block */ + kDMA_TransactionsDoneFlag = DMA_DSR_BCR_DONE_MASK, /*!< Transactions Done */ + kDMA_TransactionsBusyFlag = DMA_DSR_BCR_BSY_MASK, /*!< Transactions Busy */ + kDMA_TransactionsRequestFlag = DMA_DSR_BCR_REQ_MASK, /*!< Transactions Request */ + kDMA_BusErrorOnDestinationFlag = DMA_DSR_BCR_BED_MASK, /*!< Bus Error on Destination */ + kDMA_BusErrorOnSourceFlag = DMA_DSR_BCR_BES_MASK, /*!< Bus Error on Source */ + kDMA_ConfigurationErrorFlag = DMA_DSR_BCR_CE_MASK, /*!< Configuration Error */ +}; + +/*! @brief DMA transfer size type*/ +typedef enum _dma_transfer_size +{ + kDMA_Transfersize32bits = 0x0U, /*!< 32 bits are transferred for every read/write */ + kDMA_Transfersize8bits, /*!< 8 bits are transferred for every read/write */ + kDMA_Transfersize16bits, /*!< 16b its are transferred for every read/write */ +} dma_transfer_size_t; + +/*! @brief Configuration type for the DMA modulo */ +typedef enum _dma_modulo +{ + kDMA_ModuloDisable = 0x0U, /*!< Buffer disabled */ + kDMA_Modulo16Bytes, /*!< Circular buffer size is 16 bytes. */ + kDMA_Modulo32Bytes, /*!< Circular buffer size is 32 bytes. */ + kDMA_Modulo64Bytes, /*!< Circular buffer size is 64 bytes. */ + kDMA_Modulo128Bytes, /*!< Circular buffer size is 128 bytes. */ + kDMA_Modulo256Bytes, /*!< Circular buffer size is 256 bytes. */ + kDMA_Modulo512Bytes, /*!< Circular buffer size is 512 bytes. */ + kDMA_Modulo1KBytes, /*!< Circular buffer size is 1 KB. */ + kDMA_Modulo2KBytes, /*!< Circular buffer size is 2 KB. */ + kDMA_Modulo4KBytes, /*!< Circular buffer size is 4 KB. */ + kDMA_Modulo8KBytes, /*!< Circular buffer size is 8 KB. */ + kDMA_Modulo16KBytes, /*!< Circular buffer size is 16 KB. */ + kDMA_Modulo32KBytes, /*!< Circular buffer size is 32 KB. */ + kDMA_Modulo64KBytes, /*!< Circular buffer size is 64 KB. */ + kDMA_Modulo128KBytes, /*!< Circular buffer size is 128 KB. */ + kDMA_Modulo256KBytes, /*!< Circular buffer size is 256 KB. */ +} dma_modulo_t; + +/*! @brief DMA channel link type */ +typedef enum _dma_channel_link_type +{ + kDMA_ChannelLinkDisable = 0x0U, /*!< No channel link. */ + kDMA_ChannelLinkChannel1AndChannel2, /*!< Perform a link to channel LCH1 after each cycle-steal transfer. + followed by a link to LCH2 after the BCR decrements to 0. */ + kDMA_ChannelLinkChannel1, /*!< Perform a link to LCH1 after each cycle-steal transfer. */ + kDMA_ChannelLinkChannel1AfterBCR0, /*!< Perform a link to LCH1 after the BCR decrements. */ +} dma_channel_link_type_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Memory to Memory transfer. */ + kDMA_PeripheralToMemory, /*!< Peripheral to Memory transfer. */ + kDMA_MemoryToPeripheral, /*!< Memory to Peripheral transfer. */ +} dma_transfer_type_t; + +/*! @brief DMA transfer options */ +typedef enum _dma_transfer_options +{ + kDMA_NoOptions = 0x0U, /*!< Transfer without options. */ + kDMA_EnableInterrupt, /*!< Enable interrupt while transfer complete. */ +} dma_transfer_options_t; + +/*! @brief DMA transfer status */ +enum _dma_transfer_status +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), +}; + +/*! @brief DMA transfer configuration structure */ +typedef struct _dma_transfer_config +{ + uint32_t srcAddr; /*!< DMA transfer source address. */ + uint32_t destAddr; /*!< DMA destination address.*/ + bool enableSrcIncrement; /*!< Source address increase after each transfer. */ + dma_transfer_size_t srcSize; /*!< Source transfer size unit. */ + bool enableDestIncrement; /*!< Destination address increase after each transfer. */ + dma_transfer_size_t destSize; /*!< Destination transfer unit.*/ + uint32_t transferSize; /*!< The number of bytes to be transferred. */ +} dma_transfer_config_t; + +/*! @brief DMA transfer configuration structure */ +typedef struct _dma_channel_link_config +{ + dma_channel_link_type_t linkType; /*!< Channel link type. */ + uint32_t channel1; /*!< The index of channel 1. */ + uint32_t channel2; /*!< The index of channel 2. */ +} dma_channel_link_config_t; + +struct _dma_handle; +/*! @brief Callback function prototype for the DMA driver. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData); + +/*! @brief DMA DMA handle structure */ +typedef struct _dma_handle +{ + DMA_Type *base; /*!< DMA peripheral address. */ + uint8_t channel; /*!< DMA channel used. */ + dma_callback callback; /*!< DMA callback function.*/ + void *userData; /*!< Callback parameter. */ +} dma_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the DMA peripheral. + * + * This function ungates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes the DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/* @} */ +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! + * @brief Resets the DMA channel. + * + * Sets all register values to reset values and enables + * the cycle steal and auto stop channel request features. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_ResetChannel(DMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the DMA transfer attribute. + * + * This function configures the transfer attribute including the source address, + * destination address, transfer size, and so on. + * This example shows how to set up the the dma_transfer_config_t + * parameters and how to call the DMA_ConfigBasicTransfer function. + * @code + * dma_transfer_config_t transferConfig; + * memset(&transferConfig, 0, sizeof(transferConfig)); + * transferConfig.srcAddr = (uint32_t)srcAddr; + * transferConfig.destAddr = (uint32_t)destAddr; + * transferConfig.enbaleSrcIncrement = true; + * transferConfig.enableDestIncrement = true; + * transferConfig.srcSize = kDMA_Transfersize32bits; + * transferConfig.destSize = kDMA_Transfersize32bits; + * transferConfig.transferSize = sizeof(uint32_t) * BUFF_LENGTH; + * DMA_SetTransferConfig(DMA0, 0, &transferConfig); + * @endcode + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param config Pointer to the DMA transfer configuration structure. + */ +void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config); + +/*! + * @brief Configures the DMA channel link feature. + * + * This function allows DMA channels to have their transfers linked. The current DMA channel + * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the channel link + * type. + * Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 + * after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AndChannel2. + * Perform a link to LCH1 after each cycle-steal transfer if the type is kDMA_ChannelLinkChannel1. + * Perform a link to LCH1 after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AfterBCR0. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param config Pointer to the channel link configuration structure. + */ +void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config); + +/*! + * @brief Sets the DMA source address for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param srcAddr DMA source address. + */ +static inline void DMA_SetSourceAddress(DMA_Type *base, uint32_t channel, uint32_t srcAddr) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].SAR = srcAddr; +} + +/*! + * @brief Sets the DMA destination address for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param destAddr DMA destination address. + */ +static inline void DMA_SetDestinationAddress(DMA_Type *base, uint32_t channel, uint32_t destAddr) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DAR = destAddr; +} + +/*! + * @brief Sets the DMA transfer size for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param size The number of bytes to be transferred. + */ +static inline void DMA_SetTransferSize(DMA_Type *base, uint32_t channel, uint32_t size) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size); +} + +/*! + * @brief Sets the DMA modulo for the DMA transfer. + * + * This function defines a specific address range specified to be the value after (SAR + SSIZE)/(DAR + DSIZE) + * calculation is performed or the original register value. It provides the ability to implement a circular + * data queue easily. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param srcModulo source address modulo. + * @param destModulo destination address modulo. + */ +void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo); + +/*! + * @brief Enables the DMA cycle steal for the DMA transfer. + * + * If the cycle steal feature is enabled (true), the DMA controller forces a single read/write transfer per request, + * or it continuously makes read/write transfers until the BCR decrements to 0. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param enable The command for enable (true) or disable (false). + */ +static inline void DMA_EnableCycleSteal(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable); +} + +/*! + * @brief Enables the DMA auto align for the DMA transfer. + * + * If the auto align feature is enabled (true), the appropriate address register increments, + * regardless of DINC or SINC. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param enable The command for enable (true) or disable (false). + */ +static inline void DMA_EnableAutoAlign(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable); +} + +/*! + * @brief Enables the DMA async request for the DMA transfer. + * + * If the async request feature is enabled (true), the DMA supports asynchronous DREQs + * while the MCU is in stop mode. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param enable The command for enable (true) or disable (false). + */ +static inline void DMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable); +} + +/*! + * @brief Enables an interrupt for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR |= DMA_DCR_EINT(true); +} + +/*! + * @brief Disables an interrupt for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK; +} + +/* @} */ +/*! + * @name DMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the DMA hardware channel request. + * + * @param base DMA peripheral base address. + * @param channel The DMA channel number. + */ +static inline void DMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK; +} + +/*! + * @brief Disables the DMA hardware channel request. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK; +} + +/*! + * @brief Starts the DMA transfer with a software trigger. + * + * This function starts only one read/write iteration. + * + * @param base DMA peripheral base address. + * @param channel The DMA channel number. + */ +static inline void DMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->DMA[channel].DCR |= DMA_DCR_START_MASK; +} + +/* @} */ +/*! + * @name DMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining bytes of the current DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +static inline uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + return (base->DMA[channel].DSR_BCR & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT; +} + +/*! + * @brief Gets the DMA channel status flags. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The mask of the channel status. Use the _dma_channel_status_flags + * type to decode the return 32 bit variables. + */ +static inline uint32_t DMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + return base->DMA[channel].DSR_BCR; +} + +/*! + * @brief Clears the DMA channel status flags. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param mask The mask of the channel status to be cleared. Use + * the defined _dma_channel_status_flags type. + */ +static inline void DMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + if (mask != 0U) + { + base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); + } +} + +/* @} */ +/*! + * @name DMA Channel Transactional Operation + * @{ + */ + +/*! + * @brief Creates the DMA handle. + * + * This function is called first if using the transactional API for the DMA. This function + * initializes the internal state of the DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Sets the DMA callback function. + * + * This callback is called in the DMA IRQ handler. Use the callback to do something + * after the current transfer complete. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. If it is not needed, just set to NULL. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer configuration structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config Pointer to the user configuration structure of type dma_transfer_config_t. + * @param srcAddr DMA transfer source address. + * @param srcWidth DMA transfer source address width (byte). + * @param destAddr DMA transfer destination address. + * @param destWidth DMA transfer destination address width (byte). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t transferBytes, + dma_transfer_type_t type); + +/*! + * @brief Submits the DMA transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @param options Additional configurations for transfer. Use + * the defined dma_transfer_options_t type. + * @retval kStatus_DMA_Success It indicates that the DMA submit transfer request succeeded. + * @retval kStatus_DMA_Busy It indicates that the DMA is busy. Submit transfer request is not allowed. + * @note This function can't process multi transfer request. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options); + +/*! + * @brief DMA starts a transfer. + * + * This function enables the channel request. Call this function + * after submitting a transfer request. + * + * @param handle DMA handle pointer. + * @retval kStatus_DMA_Success It indicates that the DMA start transfer succeed. + * @retval kStatus_DMA_Busy It indicates that the DMA has started a transfer. + */ +static inline void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(handle != NULL); + + handle->base->DMA[handle->channel].DCR |= DMA_DCR_ERQ_MASK; +} + +/*! + * @brief DMA stops a transfer. + * + * This function disables the channel request to stop a DMA transfer. + * The transfer can be resumed by calling the DMA_StartTransfer. + * + * @param handle DMA handle pointer. + */ +static inline void DMA_StopTransfer(dma_handle_t *handle) +{ + assert(handle != NULL); + + handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK; +} + +/*! + * @brief DMA aborts a transfer. + * + * This function disables the channel request and clears all status bits. + * Submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for current transfer complete. + * + * This function clears the channel interrupt flag and calls + * the callback function if it is not NULL. + * + * @param handle DMA handle pointer. + */ +void DMA_HandleIRQ(dma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @}*/ + +#endif /* _FSL_DMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c new file mode 100755 index 00000000000..a288b9f22fc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMAMUX. + * + * @param base DMAMUX peripheral base address. + */ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMAMUX instance number to base pointer. */ +static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; + +/*! @brief Array to map DMAMUX instance number to clock name. */ +static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++) + { + if (s_dmamuxBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT); + + return instance; +} + +void DMAMUX_Init(DMAMUX_Type *base) +{ + CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +} + +void DMAMUX_Deinit(DMAMUX_Type *base) +{ + CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h new file mode 100755 index 00000000000..f4294d4dfa8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMAMUX_H_ +#define _FSL_DMAMUX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmamux + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMAMUX driver version 2.0.0. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMAMUX Initialize and De-initialize + * @{ + */ + +/*! + * @brief Initializes DMAMUX peripheral. + * + * This function ungate the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base); + +/*! + * @brief Deinitializes DMAMUX peripheral. + * + * This function gate the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base); + +/* @} */ +/*! + * @name DMAMUX Channel Operation + * @{ + */ + +/*! + * @brief Enable DMAMUX channel. + * + * This function enable DMAMUX channel to work. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Disable DMAMUX channel. + * + * This function disable DMAMUX channel. + * + * @note User must disable DMAMUX channel before configure it. + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Configure DMAMUX channel source. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param source Channel source which is used to trigger DMA transfer. + */ +static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t source) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); +} + +#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U +/*! + * @brief Enable DMAMUX period trigger. + * + * This function enable DMAMUX period trigger feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; +} + +/*! + * @brief Disable DMAMUX period trigger. + * + * This function disable DMAMUX period trigger. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; +} +#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /* _FSL_DMAMUX_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c new file mode 100755 index 00000000000..2add4e96352 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c @@ -0,0 +1,2610 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flash.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Misc utility defines + * @{ + */ +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif +#ifndef ALIGN_UP +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU)) +#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU)) +#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU)) +#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU)) +#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU)) +#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \ + ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU)) +#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) \ + ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \ + ((uint32_t)(w)&0xFFU)) +/*@}*/ + +/*! @brief Data flash IFR map Field*/ +#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U +#endif + +/*! + * @name Reserved FlexNVM size (For a variety of purposes) defines + * @{ + */ +#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU +#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU +/*@}*/ + +/*! + * @name Flash Program Once Field defines + * @{ + */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ + 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ + 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +/* FTFL parts(eg. K20) only support 4-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 +#endif +/*@}*/ + +/*! + * @name Flash security status defines + * @{ + */ +#define FLASH_SECURITY_STATE_KEYEN 0x80U +#define FLASH_SECURITY_STATE_UNSECURED 0x02U +#define FLASH_NOT_SECURE 0x01U +#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U +#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U +/*@}*/ + +/*! + * @name Flash controller command numbers + * @{ + */ +#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ +#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ +#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ +#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ +#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ +#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ +#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ +#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ +#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ +#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ +#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ +#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ +#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ +#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ +#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ +#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ +#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ +#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ +#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ +#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ + /*@}*/ + +/*! + * @name Common flash register info defines + * @{ + */ +#if defined(FTFA) +#define FTFx FTFA +#define FTFx_BASE FTFA_BASE +#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFE) +#define FTFx FTFE +#define FTFx_BASE FTFE_BASE +#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFL) +#define FTFx FTFL +#define FTFx_BASE FTFL_BASE +#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#else +#error "Unknown flash controller" +#endif +/*@}*/ + +/*! + * @brief Enumeration for access segment property. + */ +enum _flash_access_segment_property +{ + kFLASH_accessSegmentBase = 256UL, +}; + +/*! + * @brief Enumeration for acceleration ram property. + */ +enum _flash_acceleration_ram_property +{ + kFLASH_accelerationRamSize = 0x400U +}; + +/*! + * @brief Enumeration for flash config area. + */ +enum _flash_config_area_range +{ + kFLASH_configAreaStart = 0x400U, + kFLASH_configAreaEnd = 0x40FU +}; + +/*! @brief program Flash block base address*/ +#define PFLASH_BLOCK_BASE 0x00U + +/*! @brief Total flash region count*/ +#define FSL_FEATURE_FTFx_REGION_COUNT (32U) + +/*! + * @name Flash register access type defines + * @{ + */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT +#define FTFx_REG_ACCESS_TYPE volatile uint8_t * +#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + /*@}*/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Copy flash_run_command() to RAM*/ +static void copy_flash_run_command(uint8_t *flashRunCommand); +/*! @brief Copy flash_cache_clear_command() to RAM*/ +static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand); +/*! @brief Check whether flash execute-in-ram functions are ready*/ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ +static status_t flash_command_sequence(flash_config_t *config); + +/*! @brief Perform the cache clear to the flash*/ +void flash_cache_clear(flash_config_t *config); + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline); +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info); +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Access to FTFx->FCCOB */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3; +#else +#error "Unknown flash controller" +#endif + +/*! @brief Access to FTFx->FPROT */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3; +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3; +#else +#error "Unknown flash controller" +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief A function pointer used to point to relocated flash_run_command() */ +static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat); +/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */ +static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) +/*! @brief A static buffer used to hold flash_run_command() */ +static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize]; +/*! @brief A static buffer used to hold flash_cache_clear_command() */ +static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize]; +/*! @brief Flash execute-in-ram function information */ +static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; +#endif + +/*! + * @brief Table of pflash sizes. + * + * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. + * + * The values in this table have been right shifted 10 bits so that they will all fit within + * an 16-bit integer. To get the actual flash density, you must left shift the looked up value + * by 10 bits. + * + * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is + * reserved. + * + * Code to use the table: + * @code + * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + * @endcode + */ +const uint16_t kPFlashDensities[] = { + 8, /* 0x0 - 8192, 8KB */ + 16, /* 0x1 - 16384, 16KB */ + 24, /* 0x2 - 24576, 24KB */ + 32, /* 0x3 - 32768, 32KB */ + 48, /* 0x4 - 49152, 48KB */ + 64, /* 0x5 - 65536, 64KB */ + 96, /* 0x6 - 98304, 96KB */ + 128, /* 0x7 - 131072, 128KB */ + 192, /* 0x8 - 196608, 192KB */ + 256, /* 0x9 - 262144, 256KB */ + 384, /* 0xa - 393216, 384KB */ + 512, /* 0xb - 524288, 512KB */ + 768, /* 0xc - 786432, 768KB */ + 1024, /* 0xd - 1048576, 1MB */ + 1536, /* 0xe - 1572864, 1.5MB */ + /* 2048, 0xf - 2097152, 2MB */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FLASH_Init(flash_config_t *config) +{ + uint32_t flashDensity; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* calculate the flash density from SIM_FCFG1.PFSIZE */ + uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. + * We just use the pre-defined flash size in feature file here to support pre-production parts */ + if (pfsize == 0xf) + { + flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; + } + else + { + flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + } + + /* fill out a few of the structure members */ + config->PFlashBlockBase = PFLASH_BLOCK_BASE; + config->PFlashTotalSize = flashDensity; + config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + config->PFlashAccessSegmentSize = kFLASH_accessSegmentBase << FTFx->FACSS; + config->PFlashAccessSegmentCount = FTFx->FACSN; +#else + config->PFlashAccessSegmentSize = 0; + config->PFlashAccessSegmentCount = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + config->PFlashCallback = NULL; + +/* copy required flash commands to RAM */ +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) + if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) + { + s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; + s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; + s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand; + config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; + FLASH_PrepareExecuteInRamFunctions(config); + } +#endif + + config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; + config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + { + status_t returnCode; + config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; + returnCode = flash_update_flexnvm_memory_partition_status(config); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + } +#endif + + return kStatus_FLASH_Success; +} + +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + config->PFlashCallback = callback; + + return kStatus_FLASH_Success; +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); + copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand); + flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all flash blocks */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} + +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + uint32_t sectorSize; + flash_operation_config_t flashInfo; + uint32_t endAddress; /* storing end address */ + uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + sectorSize = flashInfo.activeSectorSize; + + /* calculating Flash end address */ + endAddress = start + lengthInBytes - 1; + + /* re-calculate the endAddress and align it to the start of the next sector + * which will be used in the comparison below */ + if (endAddress % sectorSize) + { + numberOfSectors = endAddress / sectorSize + 1; + endAddress = numberOfSectors * sectorSize - 1; + } + + /* the start address will increment to the next sector address + * until it reaches the endAdddress */ + while (start <= endAddress) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* Increment to the next sector */ + start += sectorSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Prepare passing parameter to erase all flash blocks (unsecure). */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all unsecure command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ + +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all execute-only segments + * 1st element for the FCCOB register */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + + while (lengthInBytes > 0) + { + /* preparing passing parameter to program the flash block */ + kFCCOBx[1] = *src++; + if (4 == flashInfo.blockWriteUnitSize) + { + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); + } + else if (8 == flashInfo.blockWriteUnitSize) + { + kFCCOBx[2] = *src++; + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* update start address for next iteration */ + start += flashInfo.blockWriteUnitSize; + + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashInfo.blockWriteUnitSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (src == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); + + kFCCOBx[1] = *src; + +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + kFCCOBx[2] = *(src + 1); + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + uint32_t sectorSize; + flash_operation_config_t flashInfo; +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + bool needSwitchFlexRamMode = false; +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + sectorSize = flashInfo.activeSectorSize; + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsRamError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + while (lengthInBytes > 0) + { + /* Make sure the write operation doesn't span two sectors */ + uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); + uint32_t lengthTobeProgrammedOfCurrentSector; + uint32_t currentOffset = 0; + + if (endAddressOfCurrentSector == start) + { + endAddressOfCurrentSector += sectorSize; + } + + if (lengthInBytes + start > endAddressOfCurrentSector) + { + lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; + } + else + { + lengthTobeProgrammedOfCurrentSector = lengthInBytes; + } + + /* Program Current Sector */ + while (lengthTobeProgrammedOfCurrentSector > 0) + { + /* Make sure the program size doesn't exceeds Acceleration RAM size */ + uint32_t programSizeOfCurrentPass; + uint32_t numberOfPhases; + + if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize) + { + programSizeOfCurrentPass = kFLASH_accelerationRamSize; + } + else + { + programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; + } + + /* Copy data to FlexRAM */ + memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); + /* Set start address of the data to be programmed */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); + /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ + numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment; + + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); + + /* Peform command sequence */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + if (returnCode != kStatus_FLASH_Success) + { + flash_cache_clear(config); + return returnCode; + } + + lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; + currentOffset += programSizeOfCurrentPass; + } + + src += currentOffset / 4; + start += currentOffset; + lengthInBytes -= currentOffset; + } + + flash_cache_clear(config); + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Restore function of FlexRAM if needed. */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsEepromError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + bool needSwitchFlexRamMode = false; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Validates the range of the given address */ + if ((start < config->FlexRAMBlockBase) || + ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) + { + return kStatus_FLASH_AddressError; + } + + returnCode = kStatus_FLASH_Success; + + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsEepromError; + } + } + + /* Write data to FlexRAM when it is used as EEPROM emulator */ + while (lengthInBytes > 0) + { + if ((!(start & 0x3U)) && (lengthInBytes >= 4)) + { + *(uint32_t *)start = *(uint32_t *)src; + start += 4; + src += 4; + lengthInBytes -= 4; + } + else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) + { + *(uint16_t *)start = *(uint16_t *)src; + start += 2; + src += 2; + lengthInBytes -= 2; + } + else + { + *(uint8_t *)start = *src; + start += 1; + src += 1; + lengthInBytes -= 1; + } + /* Wait till EEERDY bit is set */ + while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + } + + /* Check for protection violation error */ + if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + } + + /* Switch function of FlexRAM if needed */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsRamError; + } + } + + return returnCode; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + while (lengthInBytes > 0) + { + /* preparing passing parameter */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); + if (flashInfo.resourceCmdAddressAligment == 4) + { + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else if (flashInfo.resourceCmdAddressAligment == 8) + { + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success != returnCode) + { + break; + } + + /* fetch data */ + *dst++ = kFCCOBx[1]; + if (flashInfo.resourceCmdAddressAligment == 8) + { + *dst++ = kFCCOBx[2]; + } + /* update start address for next iteration */ + start += flashInfo.resourceCmdAddressAligment; + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashInfo.resourceCmdAddressAligment; + } + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success == returnCode) + { + *dst = kFCCOBx[1]; +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + *(dst + 1) = kFCCOBx[2]; + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + } + + return returnCode; +} + +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) +{ + /* store data read from flash register */ + uint8_t registerValue; + + if ((config == NULL) || (state == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* check the status of the flash security bits in the security register */ + if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) + { + /* Flash in unsecured state */ + *state = kFLASH_securityStateNotSecure; + } + else + { + /* Flash in secured state + * check for backdoor key security enable bit */ + if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) + { + /* Backdoor key security enabled */ + *state = kFLASH_securityStateBackdoorEnabled; + } + else + { + /* Backdoor key security disabled */ + *state = kFLASH_securityStateBackdoorDisabled; + } + } + + return (kStatus_FLASH_Success); +} + +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) +{ + uint8_t registerValue; /* registerValue */ + status_t returnCode; /* return code variable */ + + if ((config == NULL) || (backdoorKey == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* set the default return code as kStatus_Success */ + returnCode = kStatus_FLASH_Success; + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* Check to see if flash is in secure state (any state other than 0x2) + * If not, then skip this since flash is not secure */ + if (0x02 != (registerValue & 0x03)) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) +{ + /* Check arguments. */ + uint32_t blockSize; + flash_operation_config_t flashInfo; + uint32_t nextBlockStartAddress; + uint32_t remainingBytes; + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + start = flashInfo.convertedAddress; + blockSize = flashInfo.activeBlockSize; + + nextBlockStartAddress = ALIGN_UP(start, blockSize); + if (nextBlockStartAddress == start) + { + nextBlockStartAddress += blockSize; + } + + remainingBytes = lengthInBytes; + + while (remainingBytes) + { + uint32_t numberOfPhrases; + uint32_t verifyLength = nextBlockStartAddress - start; + if (verifyLength > remainingBytes) + { + verifyLength = remainingBytes; + } + + numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment; + + /* Fill in verify section command parameters. */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + if (returnCode) + { + return returnCode; + } + + remainingBytes -= verifyLength; + start += verifyLength; + nextBlockStartAddress += blockSize; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + flash_operation_config_t flashInfo; + + if (expectedData == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashInfo.convertedAddress; + + while (lengthInBytes) + { + /* preparing passing parameter to program check the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); + kFCCOBx[2] = *expectedData; + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + if (failedAddress) + { + *failedAddress = start; + } + if (failedData) + { + *failedData = 0; + } + break; + } + + lengthInBytes -= flashInfo.checkCmdAddressAligment; + expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData); + start += flashInfo.checkCmdAddressAligment; + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify erase all execute-only segments command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state) +{ + uint32_t endAddress; /* end address for protection check */ + uint32_t protectionRegionSize; /* size of flash protection region */ + uint32_t regionCheckedCounter; /* increments each time the flash address was checked for + * protection status */ + uint32_t regionCounter; /* incrementing variable used to increment through the flash + * protection regions */ + uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ + + uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each + * protection region */ + uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1]; /* array of the start addresses for each flash + * protection region. Note this is REGION_COUNT+1 + * due to requiring the next start address after + * the end of flash for loop-check purposes below */ + status_t returnCode; + + if (protection_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + + /* calculating Flash end address */ + endAddress = start + lengthInBytes; + + /* Calculate the size of the flash protection region + * If the flash density is > 32KB, then protection region is 1/32 of total flash density + * Else if flash density is < 32KB, then flash protection region is set to 1KB */ + if (config->PFlashTotalSize > 32 * 1024) + { + protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT; + } + else + { + protectionRegionSize = 1024; + } + + /* populate the flashRegionAddress array with the start address of each flash region */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + + /* populate up to 33rd element of array, this is the next address after end of flash array */ + while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT) + { + flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter; + regionCounter++; + } + + /* populate flashRegionProtectStatus array with status information + * Protection status for each region is stored in the FPROT[3:0] registers + * Each bit represents one region of flash + * 4 registers * 8-bits-per-register = 32-bits (32-regions) + * The convention is: + * FPROT3[bit 0] is the first protection region (start of flash memory) + * FPROT0[bit 7] is the last protection region (end of flash memory) + * regionCounter is used to determine which FPROT[3:0] register to check for protection status + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT) + { + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u); + } + else if ((regionCounter >= 8) && (regionCounter < 16)) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u); + } + else if ((regionCounter >= 16) && (regionCounter < 24)) + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u); + } + else + { + flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u); + } + regionCounter++; + } + + /* loop through the flash regions and check + * desired flash address range for protection status + * loop stops when it is detected that start has exceeded the endAddress */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + regionCheckedCounter = 0; + protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ + while (start < endAddress) + { + /* check to see if the address falls within this protection region + * Note that if the entire flash is to be checked, the last protection + * region checked would consist of the last protection start address and + * the start address following the end of flash */ + if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) + { + /* increment regionCheckedCounter to indicate this region was checked */ + regionCheckedCounter++; + + /* check the protection status of this region + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + if (!flashRegionProtectStatus[regionCounter]) + { + /* increment protectStatusCounter to indicate this region is protected */ + protectStatusCounter++; + } + start += protectionRegionSize; /* increment to an address within the next region */ + } + regionCounter++; /* increment regionCounter to check for the next flash protection region */ + } + + /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ + if (protectStatusCounter == 0) + { + *protection_state = kFLASH_protectionStateUnprotected; + } + /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ + else if (protectStatusCounter == regionCheckedCounter) + { + *protection_state = kFLASH_protectionStateProtected; + } + /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed + * In other words, some regions are protected while others are unprotected */ + else + { + *protection_state = kFLASH_protectionStateMixed; + } + + return (returnCode); +} + +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state) +{ + status_t returnCode; + + if (access_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + { + uint32_t executeOnlySegmentCounter = 0; + + /* calculating end address */ + uint32_t endAddress = start + lengthInBytes; + + /* Aligning start address and end address */ + uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize); + uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize); + + uint32_t segmentIndex = 0; + uint32_t maxSupportedExecuteOnlySegmentCount = + (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize; + + while (start < endAddress) + { + uint32_t xacc; + + segmentIndex = start / config->PFlashAccessSegmentSize; + + if (segmentIndex < 32) + { + xacc = *(const volatile uint32_t *)&FTFx->XACCL3; + } + else if (segmentIndex < config->PFlashAccessSegmentCount) + { + xacc = *(const volatile uint32_t *)&FTFx->XACCH3; + segmentIndex -= 32; + } + else + { + break; + } + + /* Determine if this address range is in a execute-only protection flash segment. */ + if ((~xacc) & (1u << segmentIndex)) + { + executeOnlySegmentCounter++; + } + + start += config->PFlashAccessSegmentSize; + } + + if (executeOnlySegmentCounter < 1u) + { + *access_state = kFLASH_accessStateUnLimited; + } + else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) + { + *access_state = kFLASH_accessStateMixed; + } + else + { + *access_state = kFLASH_accessStateExecuteOnly; + } + } +#else + *access_state = kFLASH_accessStateUnLimited; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + return (returnCode); +} + +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + if ((config == NULL) || (value == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + switch (whichProperty) + { + case kFLASH_propertyPflashSectorSize: + *value = config->PFlashSectorSize; + break; + + case kFLASH_propertyPflashTotalSize: + *value = config->PFlashTotalSize; + break; + + case kFLASH_propertyPflashBlockSize: + *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + break; + + case kFLASH_propertyPflashBlockCount: + *value = config->PFlashBlockCount; + break; + + case kFLASH_propertyPflashBlockBaseAddr: + *value = config->PFlashBlockBase; + break; + + case kFLASH_propertyPflashFacSupport: +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) + *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; +#else + *value = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + break; + + case kFLASH_propertyPflashAccessSegmentSize: + *value = config->PFlashAccessSegmentSize; + break; + + case kFLASH_propertyPflashAccessSegmentCount: + *value = config->PFlashAccessSegmentCount; + break; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + case kFLASH_propertyDflashSectorSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + break; + case kFLASH_propertyDflashTotalSize: + *value = config->DFlashTotalSize; + break; + case kFLASH_propertyDflashBlockSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; + break; + case kFLASH_propertyDflashBlockCount: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + break; + case kFLASH_propertyDflashBlockBaseAddr: + *value = config->DFlashBlockBase; + break; + case kFLASH_propertyEepromTotalSize: + *value = config->EEpromTotalSize; + break; +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + + default: /* catch inputs that are not recognized */ + return kStatus_FLASH_UnknownProperty; + } + + return kStatus_FLASH_Success; +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) +{ + status_t status; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + status = flasn_check_flexram_function_option_range(option); + if (status != kStatus_FLASH_Success) + { + return status; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo) +{ + status_t returnCode; + + if ((config == NULL) || (returnInfo == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) + { + return kStatus_FLASH_AlignmentError; + } + + /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ + if ((address >= (config->PFlashTotalSize / 2)) || + ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd))) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + /* Check the option. */ + returnCode = flash_check_swap_control_option(option); + if (returnCode) + { + return returnCode; + } + + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + + returnCode = flash_command_sequence(config); + + returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5; + returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6; + returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7; + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) +{ + flash_swap_state_config_t returnInfo; + status_t returnCode; + + memset(&returnInfo, 0xFFU, sizeof(returnInfo)); + + do + { + returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + if (kFLASH_swapFunctionOptionDisable == option) + { + if (returnInfo.flashSwapState == kFLASH_swapStateDisabled) + { + return kStatus_FLASH_Success; + } + else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized) + { + /* The swap system changed to the DISABLED state with Program flash block 0 + * located at relative flash address 0x0_0000 */ + returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo); + } + else + { + /* Swap disable should be requested only when swap system is in the uninitialized state */ + return kStatus_FLASH_SwapSystemNotInUninitialized; + } + } + else + { + /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, + * the swap procedure should be Uninitialized -> Update-Erased -> Complete. + * After the first swap has been completed, the flash swap inidicator address cannot be modified + * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> + * Complete. */ + switch (returnInfo.flashSwapState) + { + case kFLASH_swapStateUninitialized: + /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo); + break; + case kFLASH_swapStateReady: + /* Validate whether the address provided to the swap system is matched to + * swap indicator address in the IFR */ + returnCode = flash_validate_swap_indicator_address(config, address); + if (returnCode == kStatus_FLASH_Success) + { + /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo); + } + break; + case kFLASH_swapStateUpdate: + /* If current swap mode is Update, Erase indicator sector in non active block + * to proceed swap system to update-erased state */ + returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), + FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey); + break; + case kFLASH_swapStateUpdateErased: + /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo); + break; + case kFLASH_swapStateComplete: + break; + case kFLASH_swapStateDisabled: + /* When swap system is in disabled state, We need to clear swap system back to uninitialized + * by issuing EraseAllBlocks command */ + returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; + break; + default: + returnCode = kStatus_FLASH_InvalidArgument; + break; + } + } + if (returnCode != kStatus_FLASH_Success) + { + break; + } + } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option))); + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 + * or it will cause access error. */ + /* eepromDataSizeCode &= 0x3FU; */ + /* flexnvmPartitionCode &= 0x0FU; */ + + /* preparing passing parameter to program the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be updated by program partition command during reset sequence, + * so we just set reserved values for partitioned FlexNVM size here */ + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ + +status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + *kFPROT = protectStatus; + + if (protectStatus != *kFPROT) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + *protectStatus = *kFPROT; + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FDPROT = protectStatus; + + if (FTFx->FDPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FDPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FEPROT = protectStatus; + + if (FTFx->FEPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FEPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Run flash command + * + * This function should be copied to RAM for execution to make sure that code works + * properly even flash cache is disabled. + * It is for flash-resident bootloader only, not technically required for ROM or + * flashloader (RAM-resident bootloader). + */ +void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) +{ + /* clear CCIF bit */ + *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) + { + } +} + +/*! + * @brief Be used for determining the size of flash_run_command() + * + * This function must be defined that lexically follows flash_run_command(), + * so we can determine the size of flash_run_command() at runtime and not worry + * about toolchain or code generation differences. + */ +void flash_run_command_end(void) +{ +} + +/*! + * @brief Copy flash_run_command() to RAM + * + * This function copys the memory between flash_run_command() and flash_run_command_end() + * into the buffer which is also means that copying flash_run_command() to RAM. + */ +static void copy_flash_run_command(uint8_t *flashRunCommand) +{ + /* Calculate the valid length of flash_run_command() memory. + * Set max size(64 bytes) as default function size, in case some compiler allocates + * flash_run_command_end ahead of flash_run_command. */ + uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; + uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U); + uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U); + if (flash_run_command_end_addr > flash_run_command_start_addr) + { + funcLength = flash_run_command_end_addr - flash_run_command_start_addr; + + assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); + + /* In case some compiler allocates other function in the middle of flash_run_command + * and flash_run_command_end. */ + if (funcLength > kFLASH_executeInRamFunctionMaxSize) + { + funcLength = kFLASH_executeInRamFunctionMaxSize; + } + } + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why -1 and +1 operation exist. */ + memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength); + callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Command Sequence + * + * This function is used to perform the command write sequence to the flash. + * + * @param driver Pointer to storage for the driver runtime state. + * @return An error code or kStatus_FLASH_Success + */ +static status_t flash_command_sequence(flash_config_t *config) +{ + uint8_t registerValue; + +#if FLASH_DRIVER_IS_FLASH_RESIDENT + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + + /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using + * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() + * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ + callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT)); +#else + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + /* clear CCIF bit */ + FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) + { + } +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + + /* Check error bits */ + /* Get flash status register value */ + registerValue = FTFx->FSTAT; + + /* checking access error */ + if (registerValue & FTFx_FSTAT_ACCERR_MASK) + { + return kStatus_FLASH_AccessError; + } + /* checking protection error */ + else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + /* checking MGSTAT0 non-correctable error */ + else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) + { + return kStatus_FLASH_CommandFailure; + } + else + { + return kStatus_FLASH_Success; + } +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Run flash cache clear command + * + * This function should be copied to RAM for execution to make sure that code works + * properly even flash cache is disabled. + * It is for flash-resident bootloader only, not technically required for ROM or + * flashloader (RAM-resident bootloader). + */ +void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) +{ +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS + *ftfx_reg |= MCM_PLACR_CFCC_MASK; +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + *ftfx_reg |= MSCM_OCMDR_OCMC1(2); + *ftfx_reg |= MSCM_OCMDR_OCMC1(1); +#else +/* #error "Unknown flash cache controller" */ +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +} + +/*! + * @brief Be used for determining the size of flash_cache_clear_command() + * + * This function must be defined that lexically follows flash_cache_clear_command(), + * so we can determine the size of flash_cache_clear_command() at runtime and not worry + * about toolchain or code generation differences. + */ +void flash_cache_clear_command_end(void) +{ +} + +/*! + * @brief Copy flash_cache_clear_command() to RAM + * + * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end() + * into the buffer which is also means that copying flash_cache_clear_command() to RAM. + */ +static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand) +{ + /* Calculate the valid length of flash_cache_clear_command() memory. + * Set max size(64 bytes) as default function size, in case some compiler allocates + * flash_cache_clear_command_end ahead of flash_cache_clear_command. */ + uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; + uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U); + uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U); + if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr) + { + funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr; + + assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); + + /* In case some compiler allocates other function in the middle of flash_cache_clear_command + * and flash_cache_clear_command_end. */ + if (funcLength > kFLASH_executeInRamFunctionMaxSize) + { + funcLength = kFLASH_executeInRamFunctionMaxSize; + } + } + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why -1 and +1 operation exist. */ + memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength); + callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Cache Clear + * + * This function is used to perform the cache clear to the flash. + */ +#if (defined(__GNUC__)) +/* #pragma GCC push_options */ +/* #pragma GCC optimize("O0") */ +void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) +#else +#if (defined(__ICCARM__)) +#pragma optimize = none +#endif +#if (defined(__CC_ARM)) +#pragma push +#pragma O0 +#endif +void flash_cache_clear(flash_config_t *config) +#endif +{ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return; + } + +/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using + * pre-processed MACROs or a global variable in flash_cache_clear_comamnd() + * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */ +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS +#if defined(MCM) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR); +#endif +#if defined(MCM0) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR); +#endif +#if defined(MCM1) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR); +#else + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]); +#else + /* #error "Unknown flash cache controller" */ + /* meaningless code, just a workaround to solve warning*/ + callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0); +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + +#else + +#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS +#if defined(MCM) + MCM->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#if defined(MCM0) + MCM0->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#if defined(MCM1) + MCM1->PLACR |= MCM_PLACR_CFCC_MASK; +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif +#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS + MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2); + MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1); +#else +/* #error "Unknown flash cache controller" */ +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#if (defined(__CC_ARM)) +#pragma pop +#endif +#if (defined(__GNUC__)) +/* #pragma GCC pop_options */ +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Check whether flash execute-in-ram functions are ready */ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + if ((config->flashExecuteInRamFunctionInfo) && + (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_ExecuteInRamFunctionNotReady; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Verify the start and length are alignmentBaseline aligned. */ + if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + +/* check for valid range of the target addresses */ +#if !FLASH_SSD_IS_FLEXNVM_ENABLED + if ((startAddress < config->PFlashBlockBase) || + ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize))) +#else + if (!(((startAddress >= config->PFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) || + ((startAddress >= config->DFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))))) +#endif + { + return kStatus_FLASH_AddressError; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Clean up info Structure*/ + memset(info, 0, sizeof(flash_operation_config_t)); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) + { + info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; + info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; + } + else +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + { + info->convertedAddress = address; + info->activeSectorSize = config->PFlashSectorSize; + info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key) +{ + /* Validate the user key */ + if (key != kFLASH_apiEraseKey) + { + return kStatus_FLASH_EraseKeyError; + } + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) +{ + struct + { + uint32_t reserved0; + uint8_t FlexNVMPartitionCode; + uint8_t EEPROMDataSetSize; + uint16_t reserved1; + } dataIFRReadOut; + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get FlexNVM memory partition info from data flash IFR */ + returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, + sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_PartitionStatusUpdateFailure; + } + + /* Fill out partitioned EEPROM size */ + dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; + switch (dataIFRReadOut.EEPROMDataSetSize) + { + case 0x00U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; + break; + case 0x01U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; + break; + case 0x02U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; + break; + case 0x03U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; + break; + case 0x04U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; + break; + case 0x05U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; + break; + case 0x06U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; + break; + case 0x07U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; + break; + case 0x08U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; + break; + case 0x09U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; + break; + case 0x0AU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; + break; + case 0x0BU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; + break; + case 0x0CU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; + break; + case 0x0DU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; + break; + case 0x0EU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; + break; + case 0x0FU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; + break; + default: + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + break; + } + + /* Fill out partitioned DFlash size */ + dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; + switch (dataIFRReadOut.FlexNVMPartitionCode) + { + case 0x00U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ + break; + case 0x01U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ + break; + case 0x02U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ + break; + case 0x03U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ + break; + case 0x04U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ + break; + case 0x05U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ + break; + case 0x06U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ + break; + case 0x07U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ + break; + case 0x08U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ + break; + case 0x09U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ + break; + case 0x0AU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ + break; + case 0x0BU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ + break; + case 0x0CU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ + break; + case 0x0DU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ + break; + case 0x0EU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ + break; + case 0x0FU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ + break; + default: + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; + break; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option) +{ + status_t status; + uint32_t maxReadbleAddress; + + if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + + status = kStatus_FLASH_Success; + + maxReadbleAddress = start + lengthInBytes - 1; + if (option == kFLASH_resourceOptionVersionId) + { + if ((start != kFLASH_resourceRangeVersionIdStart) || + ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd)) + { + status = kStatus_FLASH_InvalidArgument; + } + } + else if (option == kFLASH_resourceOptionFlashIfr) + { + if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes) + { + } +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP + else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) && + (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd)) + { + } +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + else if ((start >= kFLASH_resourceRangeDflashIfrStart) && + (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd)) + { + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + + return status; +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option) +{ + if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) || + (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) || + (option == kFLASH_swapControlOptionDisableSystem)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_InvalidArgument; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) +{ + flash_swap_ifr_field_config_t flashSwapIfrField; + uint32_t swapIndicatorAddress; + + status_t returnCode; + returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField, + sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field, + * the low 4 bit value of Swap Indicator Address is always 4'b0000 */ + swapIndicatorAddress = + (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; + if (address != swapIndicatorAddress) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) +{ + if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) && + (option != kFLASH_flexramFunctionOptionAvailableForEeprom)) + { + return kStatus_FLASH_InvalidArgument; + } + + return kStatus_FLASH_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h new file mode 100755 index 00000000000..63463e03cb4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h @@ -0,0 +1,1177 @@ +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLASH_H_ +#define _FSL_FLASH_H_ + +#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) +#include +#include +#include "fsl_device_registers.h" +#include "bootloader_common.h" +#else +#include "fsl_common.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! + * @name Flash version + * @{ + */ +/*! @brief Construct the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief FLASH driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief FLASH driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_driverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_driverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_driverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_driverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Whether to support FlexNVM in flash driver */ +#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) +#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */ +#endif + +/*! @brief Whether the FlexNVM is enabled in flash driver */ +#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) + +/*! @brief Flash driver location. */ +#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) +#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) +#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */ +#else +#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */ +#endif +#endif + +/*! @brief Flash Driver Export option */ +#if !defined(FLASH_DRIVER_IS_EXPORTED) +#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) +#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */ +#else +#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */ +#endif +#endif +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASH) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Construct a status code value from a group and code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< Api is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< Api erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-ram function is not available.*/ + kStatus_FLASH_PartitionStatusUpdateFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ + kStatus_FLASH_SetFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/ + kStatus_FLASH_RecoverFlexramAsRamError = + MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as ram.*/ + kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as ram.*/ + kStatus_FLASH_RecoverFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/ + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash api is not supported.*/ + kStatus_FLASH_SwapSystemNotInUninitialized = + MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/ + kStatus_FLASH_SwapIndicatorAddressError = + MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Construct the four char code for flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_apiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for supported flash margin levels. + */ +typedef enum _flash_margin_value +{ + kFLASH_marginValueNormal, /*!< Use the 'normal' read level for 1s.*/ + kFLASH_marginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ + kFLASH_marginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ + kFLASH_marginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ +} flash_margin_value_t; + +/*! + * @brief Enumeration for the three possible flash security states. + */ +typedef enum _flash_security_state +{ + kFLASH_securityStateNotSecure, /*!< Flash is not secure.*/ + kFLASH_securityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ + kFLASH_securityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ +} flash_security_state_t; + +/*! + * @brief Enumeration for the three possible flash protection levels. + */ +typedef enum _flash_protection_state +{ + kFLASH_protectionStateUnprotected, /*!< Flash region is not protected.*/ + kFLASH_protectionStateProtected, /*!< Flash region is protected.*/ + kFLASH_protectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ +} flash_protection_state_t; + +/*! + * @brief Enumeration for the three possible flash execute access levels. + */ +typedef enum _flash_execute_only_access_state +{ + kFLASH_accessStateUnLimited, /*!< Flash region is unLimited.*/ + kFLASH_accessStateExecuteOnly, /*!< Flash region is execute only.*/ + kFLASH_accessStateMixed /*!< Flash is mixed with unLimited and execute only region.*/ +} flash_execute_only_access_state_t; + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_propertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_propertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_propertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_propertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_propertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + kFLASH_propertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ + kFLASH_propertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ + kFLASH_propertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ + kFLASH_propertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ + kFLASH_propertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ + kFLASH_propertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ + kFLASH_propertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ + kFLASH_propertyDflashBlockSize = 0x12U, /*!< Dflash block count property.*/ + kFLASH_propertyDflashBlockCount = 0x13U, /*!< Dflash block base address property.*/ + kFLASH_propertyDflashBlockBaseAddr = 0x14U, /*!< Eeprom total size property.*/ + kFLASH_propertyEepromTotalSize = 0x15U +} flash_property_tag_t; + +/*! + * @brief Constants for execute-in-ram flash function. + */ +enum _flash_execute_in_ram_function_constants +{ + kFLASH_executeInRamFunctionMaxSize = 64U, /*!< Max size of execute-in-ram function.*/ + kFLASH_executeInRamFunctionTotalNum = 2U /*!< Total number of execute-in-ram functions.*/ +}; + +/*! + * @brief Flash execute-in-ram function information. + */ +typedef struct _flash_execute_in_ram_function_config +{ + uint32_t activeFunctionCount; /*!< Number of available execute-in-ram functions.*/ + uint8_t *flashRunCommand; /*!< execute-in-ram function: flash_run_command.*/ + uint8_t *flashCacheClearCommand; /*!< execute-in-ram function: flash_cache_clear_command.*/ +} flash_execute_in_ram_function_config_t; + +/*! + * @brief Enumeration for the two possible options of flash read resource command. + */ +typedef enum _flash_read_resource_option +{ + kFLASH_resourceOptionFlashIfr = + 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ + kFLASH_resourceOptionVersionId = 0x01U /*!< Select code for Version ID*/ +} flash_read_resource_option_t; + +/*! + * @brief Enumeration for the range of special-purpose flash resource + */ +enum _flash_read_resource_range +{ +#if (FSL_FEATURE_FLASH_IS_FTFE == 1) + kFLASH_resourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ + kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_resourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ + kFLASH_resourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ + kFLASH_resourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ + kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_resourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ + kFLASH_resourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ +#endif + kFLASH_resourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ + kFLASH_resourceRangePflashSwapIfrEnd = 0x403FFU, /*!< Pflash swap IFR end address.*/ + kFLASH_resourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ + kFLASH_resourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ +}; + +/*! + * @brief Enumeration for the two possilbe options of set flexram function command. + */ +typedef enum _flash_flexram_function_option +{ + kFLASH_flexramFunctionOptionAvailableAsRam = 0xFFU, /*!< Option used to make FlexRAM available as RAM */ + kFLASH_flexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */ +} flash_flexram_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap function + */ +typedef enum _flash_swap_function_option +{ + kFLASH_swapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */ + kFLASH_swapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */ +} flash_swap_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap Control commands + */ +typedef enum _flash_swap_control_option +{ + kFLASH_swapControlOptionIntializeSystem = 0x01U, /*!< Option used to Intialize Swap System */ + kFLASH_swapControlOptionSetInUpdateState = 0x02U, /*!< Option used to Set Swap in Update State */ + kFLASH_swapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */ + kFLASH_swapControlOptionReportStatus = 0x08U, /*!< Option used to Report Swap Status */ + kFLASH_swapControlOptionDisableSystem = 0x10U /*!< Option used to Disable Swap Status */ +} flash_swap_control_option_t; + +/*! + * @brief Enumeration for the possible flash swap status. + */ +typedef enum _flash_swap_state +{ + kFLASH_swapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/ + kFLASH_swapStateReady = 0x01U, /*!< Flash swap system is in ready state.*/ + kFLASH_swapStateUpdate = 0x02U, /*!< Flash swap system is in update state.*/ + kFLASH_swapStateUpdateErased = 0x03U, /*!< Flash swap system is in updateErased state.*/ + kFLASH_swapStateComplete = 0x04U, /*!< Flash swap system is in complete state.*/ + kFLASH_swapStateDisabled = 0x05U /*!< Flash swap system is in disabled state.*/ +} flash_swap_state_t; + +/*! + * @breif Enumeration for the possible flash swap block status + */ +typedef enum _flash_swap_block_status +{ + kFLASH_swapBlockStatusLowerHalfProgramBlocksAtZero = + 0x00U, /*!< Swap block status is that lower half program block at zero.*/ + kFLASH_swapBlockStatusUpperHalfProgramBlocksAtZero = + 0x01U, /*!< Swap block status is that upper half program block at zero.*/ +} flash_swap_block_status_t; + +/*! + * @brief Flash Swap information. + */ +typedef struct _flash_swap_state_config +{ + flash_swap_state_t flashSwapState; /*!< Current swap system status.*/ + flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/ + flash_swap_block_status_t nextSwapBlockStatus; /*!< Next swap block status.*/ +} flash_swap_state_config_t; + +/*! + * @brief Flash Swap IFR fileds. + */ +typedef struct _flash_swap_ifr_field_config +{ + uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/ + uint16_t swapEnableWord; /*!< Swap enable word field.*/ + uint8_t reserved0[6]; /*!< Reserved field.*/ + uint16_t swapDisableWord; /*!< Swap disable word field.*/ + uint8_t reserved1[4]; /*!< Reserved field.*/ +} flash_swap_ifr_field_config_t; + +/*! + * @brief Enumeration for FlexRAM load during reset option. + */ +typedef enum _flash_partition_flexram_load_option +{ + kFLASH_partitionFlexramLoadOptionLoadedWithValidEepromData = + 0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/ + kFLASH_partitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/ +} flash_partition_flexram_load_option_t; + +/*! @brief callback type used for pflash block*/ +typedef void (*flash_callback_t)(void); + +/*! + * @brief Active flash information for current operation. + */ +typedef struct _flash_operation_config +{ + uint32_t convertedAddress; /*!< Converted address for current flash type.*/ + uint32_t activeSectorSize; /*!< Sector size of current flash type.*/ + uint32_t activeBlockSize; /*!< Block size of current flash type.*/ + uint32_t blockWriteUnitSize; /*!< write unit size.*/ + uint32_t sectorCmdAddressAligment; /*!< Erase sector command address alignment.*/ + uint32_t sectionCmdAddressAligment; /*!< Program/Verify section command address alignment.*/ + uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/ + uint32_t checkCmdAddressAligment; /*!< Program check command address alignment.*/ +} flash_operation_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< Base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< Size of all combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< Number of PFlash blocks. */ + uint32_t PFlashSectorSize; /*!< Size in bytes of a sector of PFlash. */ + flash_callback_t PFlashCallback; /*!< Callback function for flash API. */ + uint32_t PFlashAccessSegmentSize; /*!< Size in bytes of a access segment of PFlash. */ + uint32_t PFlashAccessSegmentCount; /*!< Number of PFlash access segments. */ + uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-ram function. */ + uint32_t FlexRAMBlockBase; /*!< For FlexNVM device, this is the base address of FlexRAM + For non-FlexNVM device, this is the base address of acceleration RAM memory */ + uint32_t FlexRAMTotalSize; /*!< For FlexNVM device, this is the size of FlexRAM + For non-FlexNVM device, this is the size of acceleration RAM memory */ + uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory); + For non-FlexNVM device, this field is unused */ + uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory; + For non-FlexNVM device, this field is unused */ + uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned + from FlexRAM; + For non-FlexNVM device, this field is unused */ +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes global flash properties structure members + * + * This function checks and initializes Flash module for the other Flash APIs. + * + * @param config Pointer to storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! + * @brief Set the desired flash callback function + * + * @param config Pointer to storage for the driver runtime state. + * @param callback callback function to be stored in driver + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback); + +/*! + * @brief Prepare flash execute-in-ram functions + * + * @param config Pointer to storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config); +#endif + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases entire flash + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status + */ +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key); + +/*! + * @brief Erases flash sectors encompassed by parameters passed into function + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address does not need to be sector aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be word aligned. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! + * @brief Erases entire flash, including protected sectors. + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status + */ +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key); +#endif + +/*! + * @brief Erases all program flash execute-only segments defined by the FXACC registers. + * + * @param config Pointer to storage for the driver runtime state. + * @param key value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters + * + * This function programs the flash memory with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); + +/*! + * @brief Programs Program Once Field through parameters + * + * This function programs the Program Once Field with desired data for a given + * flash area as determined by the index and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param index The index indicating which area of Program Once Field to be programmed. + * @param src Pointer to the source buffer of data that is to be programmed + * into the Program Once Field. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes); + +/*! + * @brief Programs flash with data at locations passed in through parameters via Program Section command + * + * This function programs the flash memory with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as ram + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); +#endif + +/*! + * @brief Programs EEPROM with data at locations passed in through parameters + * + * This function programs the Emulated EEPROM with desired data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src Pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as ram + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); +#endif + +/*@}*/ + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Read resource with data at locations passed in through parameters + * + * This function reads the flash memory with desired location for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param dst Pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be read. Must be word-aligned. + * @param option The resource option which indicates which area should be read back. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option); +#endif + +/*! + * @brief Read Program Once Field through parameters + * + * This function reads the read once feild with given index and length + * + * @param config Pointer to storage for the driver runtime state. + * @param index The index indicating the area of program once field to be read. + * @param dst Pointer to the destination buffer of data that is used to store + * data to be read. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Security + * @{ + */ + +/*! + * @brief Returns the security state via the pointer passed into the function + * + * This function retrieves the current Flash security status, including the + * security enabling state and the backdoor key enabling state. + * + * @param config Pointer to storage for the driver runtime state. + * @param state Pointer to the value returned for the current security status code: + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state); + +/*! + * @brief Allows user to bypass security with a backdoor key + * + * If the MCU is in secured state, this function will unsecure the MCU by + * comparing the provided backdoor key with ones in the Flash Configuration + * Field. + * + * @param config Pointer to storage for the driver runtime state. + * @param backdoorKey Pointer to the user buffer containing the backdoor key. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies erasure of entire flash at specified margin level + * + * This function will check to see if the flash have been erased to the + * specified read margin level. + * + * @param config Pointer to storage for the driver runtime state. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin); + +/*! + * @brief Verifies erasure of desired flash area at specified margin level + * + * This function will check the appropriate number of flash sectors based on + * the desired start address and length to see if the flash have been erased + * to the specified read margin level. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be verified. Must be word-aligned. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin); + +/*! + * @brief Verifies programming of desired flash area at specified margin level + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it with expected data for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be verified. Must be word-aligned. + * @param expectedData Pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice + * @param failedAddress Pointer to returned failing address. + * @param failedData Pointer to returned failing data. Some derivitives do + * not included failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData); + +/*! + * @brief Verifies if the program flash executeonly segments have been erased to + * the specified read margin level + * + * @param config Pointer to storage for the driver runtime state. + * @param margin Read margin choice + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin); + +/*@}*/ + +/*! + * @name Protection + * @{ + */ + +/*! + * @brief Returns the protection state of desired flash area via the pointer passed into the function + * + * This function retrieves the current Flash protect status for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param protection_state Pointer to the value returned for the current + * protection status code for the desired flash area. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + */ +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state); + +/*! + * @brief Returns the access state of desired flash area via the pointer passed into the function + * + * This function retrieves the current Flash access status for a given + * flash area as determined by the start address and length. + * + * @param config Pointer to storage for the driver runtime state. + * @param start The start address of the desired flash memory to be checked. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be checked. Must be word-aligned. + * @param access_state Pointer to the value returned for the current + * access status code for the desired flash area. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + */ +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config Pointer to storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value Pointer to the value returned for the desired flash property + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty unknown property tag + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +/*! + * @name FlexRAM + * @{ + */ + +/*! + * @brief Set FlexRAM Function command + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set work mode of FlexRAM + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option); +#endif + +/*@}*/ + +/*! + * @name Swap + * @{ + */ + +/*! + * @brief Configure Swap function or Check the swap state of Flash Module + * + * @param config Pointer to storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param option The possible option used to configure Flash Swap function or check the flash swap status + * @param returnInfo Pointer to the data which is used to return the information of flash swap. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo); +#endif + +/*! + * @brief Swap the lower half flash with the higher half flaock + * + * @param config Pointer to storage for the driver runtime state. + * @param address Address used to configure the flash swap function + * @param option The possible option used to configure Flash Swap function or check the flash swap status + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state + */ +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option); +#endif + +/*! + * @name FlexNVM + * @{ + */ + +/*! + * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the + * FlexRAM. + * + * @param config Pointer to storage for the driver runtime state. + * @param option The option used to set FlexRAM load behavior during reset. + * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems. + * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup + * memory supporting EEPROM functions. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode); +#endif + +/*@}*/ + +/*! +* @name Flash Protection Utilities +* @{ +*/ + +/*! + * @brief Set PFLASH Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is + * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest + * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus); + +/*! + * @brief Get PFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the + * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant + * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + */ +status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus); + +/*! + * @brief Set DFLASH Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is + * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest + * address area of DFlash. The most significant bit is corresponding to the highest address area of DFlash. There are + * two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus); +#endif + +/*! + * @brief Get DFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of + * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most + * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as + * below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus); +#endif + +/*! + * @brief Set EEPROM Protection to the intended protection status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is + * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest + * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on. + * There are two possible cases as shown below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus); +#endif + +/*! + * @brief Get DFLASH Protection Status. + * + * @param config Pointer to storage for the driver runtime state. + * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of + * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most + * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below: + * 0: this area is protected. + * 1: this area is unprotected. + * + * @retval #kStatus_FLASH_Success Api was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided. + * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported. + */ +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus); +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLASH_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c new file mode 100755 index 00000000000..ea15f00a4e7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*< @brief user configurable flexio handle count. */ +#define FLEXIO_HANDLE_COUNT 2 + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*< @brief pointer to array of FLEXIO handle. */ +static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO IP types. */ +static void *s_flexioType[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO Isr. */ +static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) +{ + uint32_t ctrlReg = 0; + + CLOCK_EnableClock(kCLOCK_Flexio0); + + FLEXIO_Reset(base); + + ctrlReg = base->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DOZEN(userConfig->enableInDoze) | FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | + FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); + + base->CTRL = ctrlReg; +} + +void FLEXIO_Deinit(FLEXIO_Type *base) +{ + FLEXIO_Enable(base, false); + CLOCK_DisableClock(kCLOCK_Flexio0); +} + +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) +{ + assert(userConfig); + + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; +} + +void FLEXIO_Reset(FLEXIO_Type *base) +{ + /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ + base->CTRL |= FLEXIO_CTRL_SWRST_MASK; + base->CTRL = 0; +} + +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) +{ + assert(index < FLEXIO_SHIFTBUF_COUNT); + + uint32_t address = 0; + + switch (type) + { + case kFLEXIO_ShifterBuffer: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + + case kFLEXIO_ShifterBufferBitSwapped: + address = (uint32_t) & (base->SHIFTBUFBIS[index]); + break; + + case kFLEXIO_ShifterBufferByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBYS[index]); + break; + + case kFLEXIO_ShifterBufferBitByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBBS[index]); + break; + +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + case kFLEXIO_ShifterBufferNibbleByteSwapped: + address = (uint32_t) & (base->SHIFTBUFNBS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + case kFLEXIO_ShifterBufferHalfWordSwapped: + address = (uint32_t) & (base->SHIFTBUFHWS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + case kFLEXIO_ShifterBufferNibbleSwapped: + address = (uint32_t) & (base->SHIFTBUFNIS[index]); + break; + +#endif + default: + break; + } + return address; +} + +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) +{ + base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | + FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); + + base->SHIFTCTL[index] = + FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | + FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | + FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); +} + +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) +{ + base->TIMCFG[index] = + FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | + FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | + FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | + FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); + + base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); + + base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | + FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | + FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | + FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | + FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); +} + +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) +{ + assert(base); + assert(handle); + assert(isr); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] == NULL) + { + /* Register FLEXIO simulated driver base, handle and isr. */ + s_flexioType[index] = base; + s_flexioHandle[index] = handle; + s_flexioIsr[index] = isr; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +status_t FLEXIO_UnregisterHandleIRQ(void *base) +{ + assert(base); + + uint8_t index = 0; + + /* Find the index from base address mappings. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioType[index] == base) + { + /* Unregister FLEXIO simulated driver handle and isr. */ + s_flexioType[index] = NULL; + s_flexioHandle[index] = NULL; + s_flexioIsr[index] = NULL; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +void FLEXIO_CommonIRQHandler(void) +{ + uint8_t index; + + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index]) + { + s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); + } + } +} + +void FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO0_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void UART2_FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h new file mode 100755 index 00000000000..24fdfa64471 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_H_ +#define _FSL_FLEXIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexio_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO driver version 2.0.0. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Calculate FlexIO timer trigger.*/ +#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) +#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) +#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) + +/*! @brief Define time of timer trigger polarity.*/ +typedef enum _flexio_timer_trigger_polarity +{ + kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! @brief Define type of timer trigger source.*/ +typedef enum _flexio_timer_trigger_source +{ + kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ + kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! @brief Define type of timer/shifter pin configuration.*/ +typedef enum _flexio_pin_config +{ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ +} flexio_pin_config_t; + +/*! @brief Definition of pin polarity.*/ +typedef enum _flexio_pin_polarity +{ + kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! @brief Define type of timer work mode.*/ +typedef enum _flexio_timer_mode +{ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! @brief Define type of timer initial output or timer reset condition.*/ +typedef enum _flexio_timer_output +{ + kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! @brief Define type of timer decrement.*/ +typedef enum _flexio_timer_decrement_source +{ + kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock + equals Timer output. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U, /*!< Decrement counter on Pin input (both edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Trigger input. */ +} flexio_timer_decrement_source_t; + +/*! @brief Define type of timer reset condition.*/ +typedef enum _flexio_timer_reset_condition +{ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to + Timer Output. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! @brief Define type of timer disable condition.*/ +typedef enum _flexio_timer_disable_condition +{ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided + Trigger is high. */ + kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! @brief Define type of timer enable condition.*/ +typedef enum _flexio_timer_enable_condition +{ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! @brief Define type of timer stop bit generate condition.*/ +typedef enum _flexio_timer_stop_bit_condition +{ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer + disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! @brief Define type of timer start bit generate condition.*/ +typedef enum _flexio_timer_start_bit_condition +{ + kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @brief Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */ +} flexio_shifter_timer_polarity_t; + +/*! @brief Define type of shifter working mode.*/ +typedef enum _flexio_shifter_mode +{ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE + kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing + programmable state attributes. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE + kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing + programmable logic look up table. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ +} flexio_shifter_mode_t; + +/*! @brief Define type of shifter input source.*/ +typedef enum _flexio_shifter_input_source +{ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! @brief Define of STOP bit configuration.*/ +typedef enum _flexio_shifter_stop_bit +{ + kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! @brief Define type of START bit configuration.*/ +typedef enum _flexio_shifter_start_bit +{ + kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads + data on enable. */ + kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads + data on first shift. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ +} flexio_shifter_start_bit_t; + +/*! @brief Define FlexIO shifter buffer type*/ +typedef enum _flexio_shifter_buffer_type +{ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ +#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ +#endif +} flexio_shifter_buffer_type_t; + +/*! @brief Define FlexIO user configuration structure. */ +typedef struct _flexio_config_ +{ + bool enableFlexio; /*!< Enable/disable FlexIO module */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ +} flexio_config_t; + +/*! @brief Define FlexIO timer configuration structure. */ +typedef struct _flexio_timer_config +{ + /* Trigger. */ + uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ + uint32_t pinSelect; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ + flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and + whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the + source of the Shift clock. */ + flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter + (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be + disabled and stop decrementing. */ + flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be + enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ + uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +/*! @brief Define FlexIO shifter configuration structure. */ +typedef struct _flexio_shifter_config +{ + /* Timer. */ + uint32_t timerSelect; /*!< Selects which Timer is used for controlling the + logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ + uint32_t pinSelect; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ +typedef void (*flexio_isr_t)(void *base, void *handle); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the default configuration to configure FlexIO module. The configuration + * can used directly for calling FLEXIO_Configure(). + * + * Example: + @code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + @endcode + * + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); + +/*! + * @brief Configures the FlexIO with FlexIO configuration. The configuration structure + * can be filled by the user, or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + @code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); + +/*! + * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * @note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * @param base FlexIO peripheral base address +*/ +void FLEXIO_Deinit(FLEXIO_Type *base); + +/* @} */ + +/*! + * @name FlexIO Basic Operation + * @{ + */ + +/*! + * @brief Resets the FlexIO module. + * + * @param base FlexIO peripheral base address +*/ +void FLEXIO_Reset(FLEXIO_Type *base); + +/*! + * @brief Enables the FlexIO module operation. + * + * @param base FlexIO peripheral base address + * @param enable true to enable, false to disable. +*/ +static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Reads the input data on each of the FlexIO pins. + * + * @param base FlexIO peripheral base address + * @return FlexIO pin input data +*/ +static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) +{ + return base->PIN; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +/*! + * @brief Gets the current state pointer for state mode use. + * + * @param base FlexIO peripheral base address + * @return current state pointer +*/ +static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) +{ + return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); +} +#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ + +/*! + * @brief Configures the shifter with shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + @code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index shifter index + * @param shifterConfig pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); +/*! + * @brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + @code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index timer index + * @param timerConfig pointer to flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); + +/* @} */ + +/*! + * @name FlexIO Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask the shifter status mask which could be calculated by (1 << shifter index) + * @note for multiple shifter status interrupt enable, for example, two shifter status enable, could calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN |= mask; +} + +/*! + * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask the shifter status mask which could be calculated by (1 << shifter index) + * @note for multiple shifter status interrupt enable, for example, two shifter status enable, could calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN &= ~mask; +} + +/*! + * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask the shifter error mask which could be calculated by (1 << shifter index) + * @note for multiple shifter error interrupt enable, for example, two shifter error enable, could calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN |= mask; +} + +/*! + * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask the shifter error mask which could be calculated by (1 << shifter index) + * @note for multiple shifter error interrupt enable, for example, two shifter error enable, could calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN &= ~mask; +} + +/*! + * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask the timer status mask which could be calculated by (1 << timer index) + * @note for multiple timer status interrupt enable, for example, two timer status enable, could calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) +*/ +static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN |= mask; +} + +/*! + * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask the timer status mask which could be calculated by (1 << timer index) + * @note for multiple timer status interrupt enable, for example, two timer status enable, could calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) +*/ +static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN &= ~mask; +} + +/* @} */ + +/*! + * @name FlexIO Status Operation + * @{ + */ + +/*! + * @brief Gets the shifter status flags. + * + * @param base FlexIO peripheral base address + * @return shifter status flags +*/ +static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); +} + +/*! + * @brief Clears the shifter status flags. + * + * @param base FlexIO peripheral base address + * @param mask the shifter status mask which could be calculated by (1 << shifter index) + * @note for clearing multiple shifter status flags, for example, two shifter status flags, could calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSTAT = mask; +} + +/*! + * @brief Gets the shifter error flags. + * + * @param base FlexIO peripheral base address + * @return shifter error flags +*/ +static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); +} + +/*! + * @brief Clears the shifter error flags. + * + * @param base FlexIO peripheral base address + * @param mask the shifter error mask which could be calculated by (1 << shifter index) + * @note for clearing multiple shifter error flags, for example, two shifter error flags, could calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) +*/ +static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTERR = mask; +} + +/*! + * @brief Gets the timer status flags. + * + * @param base FlexIO peripheral base address + * @return timer status flags +*/ +static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) +{ + return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); +} + +/*! + * @brief Clears the timer status flags. + * + * @param base FlexIO peripheral base address + * @param mask the timer status mask which could be calculated by (1 << timer index) + * @note for clearing multiple timer status flags, for example, two timer status flags, could calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) +*/ +static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMSTAT = mask; +} + +/* @} */ + +/*! + * @name FlexIO DMA Operation + * @{ + */ + +/*! + * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. + * + * @note For multiple shifter status DMA enables, for example, calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + * + * @param base FlexIO peripheral base address + * @param mask the shifter status mask which could be calculated by (1 << shifter index) + * @param enable True to enable, false to disable. +*/ +static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SHIFTSDEN |= mask; + } + else + { + base->SHIFTSDEN &= ~mask; + } +} + +/*! + * @brief Gets the shifter buffer address for the DMA transfer usage. + * + * @param base FlexIO peripheral base address + * @param type shifter type of flexio_shifter_buffer_type_t + * @param index shifter index + * @return corresponding shifter buffer index +*/ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); + +/*! + * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base pointer to FlexIO simulated peripheral type. + * @param handle pointer to handler for FlexIO simulated peripheral. + * @param isr FlexIO simulated peripheral interrupt handler. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. +*/ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); + +/*! + * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base pointer to FlexIO simulated peripheral type. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. +*/ +status_t FLEXIO_UnregisterHandleIRQ(void *base); +/* @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c new file mode 100755 index 00000000000..0d7f20fc9e2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c @@ -0,0 +1,732 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_i2c_master.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief FLEXIO I2C transfer state */ +enum _flexio_i2c_master_transfer_states +{ + kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ + kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ + kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ + kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ + kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ + kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param transfer pointer to flexio_i2c_master_transfer_t structure + */ +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * @retval kStatus_Success Successfully run state machine + * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer + */ +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief Complete transfer, disable interrupt and call callback. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param status flexio transfer status + */ +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status); + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + bool needRestart; + uint32_t byteCount; + + /* Init the handle member. */ + handle->transfer.slaveAddress = xfer->slaveAddress; + handle->transfer.direction = xfer->direction; + handle->transfer.subaddress = xfer->subaddress; + handle->transfer.subaddressSize = xfer->subaddressSize; + handle->transfer.data = xfer->data; + handle->transfer.dataSize = xfer->dataSize; + handle->transfer.flags = xfer->flags; + handle->transferSize = xfer->dataSize; + + /* Initial state, i2c check address state. */ + handle->state = kFLEXIO_I2C_CheckAddress; + + /* Clear all status before transfer. */ + FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag); + + /* Calculate whether need to send re-start. */ + needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read); + + /* Calculate total byte count in a frame. */ + byteCount = 1; + + if (!needRestart) + { + byteCount += handle->transfer.dataSize; + } + + if (handle->transfer.subaddressSize != 0) + { + byteCount += handle->transfer.subaddressSize; + /* Next state, send command byte. */ + handle->state = kFLEXIO_I2C_SendCommand; + } + + /* Configure data count. */ + if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success) + { + return kStatus_InvalidArgument; + } + + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + + /* Send address byte first. */ + if (needRestart) + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); + } + else + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); + } + + return kStatus_Success; +} + +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag) + { + /* Clear receive nak flag. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + + if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && + (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) && + (handle->transfer.dataSize == 1U)))) + { + FLEXIO_I2C_MasterReadByte(base); + + FLEXIO_I2C_MasterAbortStop(base); + + handle->state = kFLEXIO_I2C_Idle; + + return kStatus_FLEXIO_I2C_Nak; + } + } + + if (handle->state == kFLEXIO_I2C_CheckAddress) + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = kFLEXIO_I2C_SendData; + } + else + { + /* Next state, receive data begin. */ + handle->state = kFLEXIO_I2C_ReceiveDataBegin; + } + } + + if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData)) + { + FLEXIO_I2C_MasterReadByte(base); + } + + switch (handle->state) + { + case kFLEXIO_I2C_SendCommand: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + if (handle->transfer.subaddressSize > 0) + { + handle->transfer.subaddressSize--; + FLEXIO_I2C_MasterWriteByte( + base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize))); + + if (handle->transfer.subaddressSize == 0) + { + /* Load re-start in advance. */ + if (handle->transfer.direction == kFLEXIO_I2C_Read) + { + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterRepeatedStart(base); + } + } + } + else + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = kFLEXIO_I2C_SendData; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1)); + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); + + /* Next state, receive data begin. */ + handle->state = kFLEXIO_I2C_ReceiveDataBegin; + } + } + } + break; + + /* Send command byte. */ + case kFLEXIO_I2C_SendData: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + handle->state = kFLEXIO_I2C_Idle; + } + } + break; + + case kFLEXIO_I2C_ReceiveDataBegin: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + /* Read one byte of data. */ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + FLEXIO_I2C_MasterEnableAck(base, false); + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterStop(base); + } + else + { + FLEXIO_I2C_MasterEnableAck(base, true); + } + } + else + { + handle->state = kFLEXIO_I2C_ReceiveData; + } + break; + + case kFLEXIO_I2C_ReceiveData: + if (statusFlags & kFLEXIO_I2C_RxFullFlag) + { + *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); + handle->transfer.data++; + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize != 0) + { + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + else + { + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable); + handle->state = kFLEXIO_I2C_Idle; + } + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + FLEXIO_I2C_MasterEnableAck(base, false); + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterStop(base); + } + } + } + break; + + default: + break; + } + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status) +{ + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + if (handle->completionCallback) + { + handle->completionCallback(base, handle, status, handle->userData); + } +} + +void FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base && masterConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t controlVal = 0; + + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + + /* Ungate flexio clock. */ + CLOCK_EnableClock(kCLOCK_Flexio0); + + FLEXIO_Reset(base->flexioBase); + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for generating bit clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */ + timerConfig.timerCompare = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for controlling shifters. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ + timerConfig.timerCompare = 8 * 2 - 1; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + /* Configure FLEXIO I2C Master. */ + controlVal = base->flexioBase->CTRL; + controlVal &= + ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + controlVal |= + (FLEXIO_CTRL_DOZEN(masterConfig->enableInDoze) | FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | + FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + + base->flexioBase->CTRL = controlVal; +} + +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) +{ + FLEXIO_Deinit(base->flexioBase); +} + +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; +} + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) +{ + uint32_t status = 0; + + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + + return status; +} + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + + if (mask & kFLEXIO_I2C_RxFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } + + if (mask & kFLEXIO_I2C_ReceiveNakFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_I2C_RxFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_I2C_RxFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = srcClock_Hz / baudRate_Bps; + timerDiv = timerDiv / 2 - 1U; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0xFF00; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) +{ + if (count > 14U) + { + return kStatus_InvalidArgument; + } + + uint16_t timerCmp = 0; + uint32_t timerConfig = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0x00FFU; + timerCmp |= (count * 18 + 1U) << 8U; + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; + timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; + timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; + + return kStatus_Success; +} + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) +{ + uint32_t data; + + data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); + + FLEXIO_I2C_MasterWriteByte(base, data); +} + +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) +{ + /* Prepare for RESTART condition, no stop.*/ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); +} + +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) +{ + /* Prepare normal stop. */ + FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); + FLEXIO_I2C_MasterWriteByte(base, 0x0U); +} + +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) +{ + uint32_t tmpConfig; + + /* Prepare abort stop. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; +} + +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) +{ + uint32_t tmpConfig = 0; + + tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; + tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; + if (enable) + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); + } + else + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); + } + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; +} + +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) +{ + assert(txBuff); + assert(txSize); + + uint32_t status; + + while (txSize--) + { + FLEXIO_I2C_MasterWriteByte(base, *txBuff++); + + /* Wait until data transfer complete. */ + while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag)) + { + } + + if (status & kFLEXIO_I2C_ReceiveNakFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + return kStatus_FLEXIO_I2C_Nak; + } + } + return kStatus_Success; +} + +void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) +{ + assert(rxBuff); + assert(rxSize); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) + { + } + + *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); + } +} + +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[0]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); +} + +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + if (handle->state != kFLEXIO_I2C_Idle) + { + return kStatus_FLEXIO_I2C_Busy; + } + else + { + /* Set up transfer machine. */ + FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); + + /* Enable both tx empty and rxfull interrupt. */ + FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + return kStatus_Success; + } +} + +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupts. */ + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + /* Reset to idle state. */ + handle->state = kFLEXIO_I2C_Idle; +} + +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) +{ + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) +{ + FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; + flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; + uint32_t statusFlags; + status_t result; + + statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); + + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); + + if (handle->state == kFLEXIO_I2C_Idle) + { + FLEXIO_I2C_MasterTransferComplete(base, handle, result); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h new file mode 100755 index 00000000000..1ebea372a6b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_I2C_MASTER_H_ +#define _FSL_FLEXIO_I2C_MASTER_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2c_master + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2C master driver version 2.1.0. */ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief FlexIO I2C transfer status*/ +enum _flexio_i2c_status +{ + kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ +}; + +/*! @brief Define FlexIO I2C master interrupt mask. */ +enum _flexio_i2c_master_interrupt +{ + kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ + kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO I2C master status mask. */ +enum _flexio_i2c_master_status_flags +{ + kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ + kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ + kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ +}; + +/*! @brief Direction of master transfer.*/ +typedef enum _flexio_i2c_direction +{ + kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ + kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ +} flexio_i2c_direction_t; + +/*! @brief Define FlexIO I2C master access structure typedef. */ +typedef struct _flexio_i2c_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ + uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO I2C. */ +} FLEXIO_I2C_Type; + +/*! @brief Define FlexIO I2C master user configuration structure. */ +typedef struct _flexio_i2c_master_config +{ + bool enableMaster; /*!< Enables the FLEXIO I2C peripheral at initialization time. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ +} flexio_i2c_master_config_t; + +/*! @brief Define FlexIO I2C master transfer structure. */ +typedef struct _flexio_i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for flexio i2c. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t volatile *data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} flexio_i2c_master_transfer_t; + +/*! @brief FlexIO I2C master handle typedef. */ +typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; + +/*! @brief FlexIO I2C master transfer callback typedef. */ +typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2C master handle structure. */ +struct _flexio_i2c_master_handle +{ + flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ + /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + @code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + @endcode + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param masterConfig pointer to flexio_i2c_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the FlexIO I2C master peripheral. Calling this API gates the FlexIO clock, + * so the FlexIO I2C master module can't work unless call FLEXIO_I2C_MasterInit. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling FLEXIO_I2C_MasterInit(). + * + * Example: + @code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + @endcode + * @param masterConfig pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); + +/*! + * @brief Enables/disables the FlexIO module operation. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param enable pass true to enable module, false to disable module. +*/ +static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2C master status flags. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @return status flag, use status flag to AND #_flexio_i2c_master_status_flags could get the related status. +*/ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); + +/*! + * @brief Clears the FlexIO I2C master status flags. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param mask status flag. + * The parameter could be any combination of the following values: + * @arg kFLEXIO_I2C_RxFullFlag + * @arg kFLEXIO_I2C_ReceiveNakFlag +*/ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO i2c master interrupt requests. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param mask interrupt source. + * Currently only one interrupt request source: + * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2C master interrupt requests. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param mask interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the FlexIO I2C master transfer baudrate. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param baudRate_Bps the baud rate value in HZ + * @param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends START + 7-bit address to the bus. + * + * @note This is API should be called when transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but not address transfer finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * @param base pointer to FLEXIO_I2C_Type structure. + * @param address 7-bit address. + * @param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * @arg kFLEXIO_I2C_Write: Transmit + * @arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); + +/*! + * @brief Sends the stop signal on the bus. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the repeated start signal on the bus. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the stop signal when transfer is still on-going. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Configures the sent ACK/NAK for the following byte. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param enable true to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); + +/*! + * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * @note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param count number of bytes need to be transferred from a start signal to a re-start/stop signal + * @retval kStatus_Success Successfully configured the count. + * @retval kStatus_InvalidArgument Input argument is invalid. +*/ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count); + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but not data transfer finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param data a byte of data. + */ +static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; +} + +/*! + * @brief Reads one byte of data from the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the data is ready in the register. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @return data byte read. + */ +static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) +{ + return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; +} + +/*! + * @brief Sends a buffer of data in bytes. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param txBuff The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_Success Successfully write data. + * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param rxBuff The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + */ +void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to flexio_i2c_master_transfer_t structure. + * @return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); +/*@}*/ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param handle pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user param passed to the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2c_master_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_FLEXIO_I2C_Busy FLEXIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param i2cType pointer to FLEXIO_I2C_Type structure + * @param i2cHandle pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c new file mode 100755 index 00000000000..3bace5b7bf9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c @@ -0,0 +1,637 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_i2s.h" + +/******************************************************************************* +* Definitations +******************************************************************************/ +enum _sai_transfer_state +{ + kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */ + kFLEXIO_I2S_Idle, /*!< Transfer is done. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base FLEXIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base FLEXIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*txData); + data |= (temp << (8U * j)); + txData++; + } + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); + data = 0; + } +} + +static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]; + for (j = 0; j < bytesPerWord; j++) + { + *rxData = (data >> (8U * j)) & 0xFF; + rxData++; + } + } +} + +void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) +{ + assert(base && config); + + flexio_shifter_config_t shifterConfig = {0}; + flexio_timer_config_t timerConfig = {0}; + + /* Ungate flexio clock. */ + CLOCK_EnableClock(kCLOCK_Flexio0); + + FLEXIO_Reset(base->flexioBase); + + /* Set shifter for I2S Tx data */ + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->txPinIndex; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (config->masterSlave == kFLEXIO_I2S_Master) + { + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + else + { + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig); + + /* Set shifter for I2S Rx Data */ + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->rxPinIndex; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig); + + /* Set Timer to I2S frame sync */ + if (config->masterSlave == kFLEXIO_I2S_Master) + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->bclkTimerIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + else + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig); + + /* Set Timer to I2S bit clock */ + if (config->masterSlave == kFLEXIO_I2S_Master) + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + else + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig); + + /* If enable flexio I2S */ + if (config->enableI2S) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) +{ + config->masterSlave = kFLEXIO_I2S_Master; + config->enableI2S = true; +} + +void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) +{ + /* Disable FLEXIO I2S module. */ + FLEXIO_I2S_Enable(base, false); + + /* Gate flexio clock. */ + CLOCK_DisableClock(kCLOCK_Flexio0); +} + +void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); + } + if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); + } +} + +uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) +{ + uint32_t status = 0; + status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex)) + << 1U); + return status; +} + +void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); + } + if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); + } +} + +void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz) +{ + uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U); + uint32_t bclkDiv = 0; + + /* Set Frame sync timer cmp */ + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U); + + /* Set bit clock timer cmp */ + bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U)); + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv); +} + +void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format) +{ + /* Set Frame sync timer cmp */ + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4U - 3U); + + /* Set bit clock timer cmp */ + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2U - 1U); +} + +void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size / bytesPerWord; i++) + { + /* Wait until it can write data */ + while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) + { + } + + FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord); + txData += bytesPerWord; + } + + /* Wait until the last data is sent */ + while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) + { + } +} + +void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size / bytesPerWord; i++) + { + /* Wait until data is received */ + while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex))) + { + } + + FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord); + rxData += bytesPerWord; + } +} + +void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Store callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ); + + /* Set the TX/RX state. */ + handle->state = kFLEXIO_I2S_Idle; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[0]); +} + +void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Store callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ); + + /* Set the TX/RX state. */ + handle->state = kFLEXIO_I2S_Idle; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[0]); +} + +void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz) +{ + assert(handle && format); + + /* Set the bitWidth to handle */ + handle->bitWidth = format->bitWidth; + + /* Set sample rate */ + if (srcClock_Hz != 0) + { + /* It is master */ + FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); + } + else + { + FLEXIO_I2S_SlaveSetFormat(base, format); + } +} + +status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + if ((xfer->dataSize == 0) || (xfer->data == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Add into queue */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kFLEXIO_I2S_Busy; + + FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); + + /* Enable Tx transfer */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + if ((xfer->dataSize == 0) || (xfer->data == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Add into queue */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kFLEXIO_I2S_Busy; + + /* Enable interrupt */ + FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); + + /* Enable Rx transfer */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + FLEXIO_I2S_Enable(base, false); + + FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); + handle->state = kFLEXIO_I2S_Idle; + + /* Clear the queue */ + memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + FLEXIO_I2S_Enable(base, false); + + FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); + handle->state = kFLEXIO_I2S_Idle; + + /* Clear the queue */ + memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); + } + + return status; +} + +void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) +{ + assert(i2sHandle); + + flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle error */ + if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex)) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex)); + } + /* Handle transfer */ + if ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) + { + FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize); + + /* Update internal counter */ + handle->queue[handle->queueDriver].dataSize -= dataSize; + handle->queue[handle->queueDriver].data += dataSize; + } + + /* If finished a blcok, call the callback function */ + if (handle->queue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->queue[handle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortSend(base, handle); + } +} + +void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) +{ + assert(i2sHandle); + + flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle transfer */ + if ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) + { + FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize); + + /* Update internal state */ + handle->queue[handle->queueDriver].dataSize -= dataSize; + handle->queue[handle->queueDriver].data += dataSize; + } + + /* If finished a blcok, call the callback function */ + if (handle->queue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->queue[handle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortReceive(base, handle); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h new file mode 100755 index 00000000000..ff17ea70be3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_I2S_H_ +#define _FSL_FLEXIO_I2S_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2s + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2S driver version 2.1.0. */ +#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief FlexIO I2S transfer status */ +enum _flexio_i2s_status +{ + kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */ + kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */ + kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */ +}; + +/*! @brief Define FlexIO I2S access structure typedef */ +typedef struct _flexio_i2s_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer */ + uint8_t txPinIndex; /*!< Tx data pin index in FlexIO pins */ + uint8_t rxPinIndex; /*!< Rx data pin index */ + uint8_t bclkPinIndex; /*!< Bit clock pin index */ + uint8_t fsPinIndex; /*!< Frame sync pin index */ + uint8_t txShifterIndex; /*!< Tx data shifter index */ + uint8_t rxShifterIndex; /*!< Rx data shifter index */ + uint8_t bclkTimerIndex; /*!< Bit clock timer index */ + uint8_t fsTimerIndex; /*!< Frame sync timer index */ +} FLEXIO_I2S_Type; + +/*! @brief Master or slave mode */ +typedef enum _flexio_i2s_master_slave +{ + kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */ + kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */ +} flexio_i2s_master_slave_t; + +/*! @brief Define FlexIO FlexIO I2S interrupt mask. */ +enum _flexio_i2s_interrupt_enable +{ + kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO FlexIO I2S status mask. */ +enum _flexio_i2s_status_flags +{ + kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief FlexIO I2S configure structure */ +typedef struct _flexio_i2s_config +{ + bool enableI2S; /*!< Enable FlexIO I2S */ + flexio_i2s_master_slave_t masterSlave; /*!< Master or slave */ +} flexio_i2s_config_t; + +/*! @brief FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx */ +typedef struct _flexio_i2s_format +{ + uint8_t bitWidth; /*!< Bit width of audio data, always 8/16/24/32 bits */ + uint32_t sampleRate_Hz; /*!< Sample rate of the audio data */ +} flexio_i2s_format_t; + +/*!@brief FlexIO I2S transfer queue size, user can refine it according to use case. */ +#define FLEXIO_I2S_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _flexio_i2s_sample_rate +{ + kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ + kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ + kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ + kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ + kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ + kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ + kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ + kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ + kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ + kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ +} flexio_i2s_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _flexio_i2s_word_width +{ + kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kFLEXIO_I2S_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} flexio_i2s_word_width_t; + +/*! @brief Define FlexIO I2S transfer structure. */ +typedef struct _flexio_i2s_transfer +{ + uint8_t *data; /*!< Data buffer start pointer */ + size_t dataSize; /*!< Bytes to be transferred. */ +} flexio_i2s_transfer_t; + +typedef struct _flexio_i2s_handle flexio_i2s_handle_t; + +/*! @brief FlexIO I2S xfer callback prototype */ +typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2S handle structure. */ +struct _flexio_i2s_handle +{ + uint32_t state; /*!< Internal state */ + flexio_i2s_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32bits */ + flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S. + * + * This API configures FlexIO pins and shifter to I2S and configure FlexIO I2S with configuration structure. + * The configuration structure can be filled by the user, or be set with default values by + * FLEXIO_I2S_GetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the FlexIO I2S driver, or any access to the FlexIO I2S module could cause hard fault + * because clock is not enabled. + * + * @param base FlexIO I2S base pointer + * @param config FlexIO I2S configure structure. +*/ +void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config); + +/*! + * @brief Sets the FlexIO I2S configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). + * User may use the initialized structure unchanged in FLEXIO_I2S_Init(), or modify + * some fields of the structure before calling FLEXIO_I2S_Init(). + * + * @param config pointer to master configuration structure + */ +void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config); + +/*! + * @brief De-initializes the FlexIO I2S. + * + * Calling this API gates the FlexIO i2s clock. After calling this API, call the FLEXO_I2S_Init to use the + * FlexIO I2S module. + * + * @param base FlexIO I2S base pointer +*/ +void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base); + +/*! + * @brief Enables/disables the FlexIO I2S module operation. + * + * @param base pointer to FLEXIO_I2S_Type + * @param enable True to enable, false to disable. +*/ +static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2S status flags. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. +*/ +uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param mask interrupt source + */ +void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param mask interrupt source + */ +void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO I2S Tx DMA requests. + * + * @param base FlexIO I2S base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->txShifterIndex, enable); +} + +/*! + * @brief Enables/disables the FlexIO I2S Rx DMA requests. + * + * @param base FlexIO I2S base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->rxShifterIndex, enable); +} + +/*! + * @brief Gets the FlexIO I2S send data register address. + * + * This function returns the I2S data register address, mainly used by DMA/eDMA. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @return FlexIO i2s send data register address. + */ +static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->txShifterIndex); +} + +/*! + * @brief Gets the FlexIO I2S receive data register address. + * + * This function returns the I2S data register address, mainly used by DMA/eDMA. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @return FlexIO i2s receive data register address. + */ +static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->rxShifterIndex); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the FlexIO I2S audio format in master mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param format Pointer to FlexIO I2S audio data format structure. + * @param srcClock_Hz I2S master clock source frequency in Hz. +*/ +void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz); + +/*! + * @brief Configures the FlexIO I2S audio format in slave mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param format Pointer to FlexIO I2S audio data format structure. +*/ +void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format); + +/*! + * @brief Sends a piece of data using a blocking method. + * + * @note This function blocks via polling until data is ready to be sent. + * + * @param base FlexIO I2S base pointer. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param txData Pointer to the data to be written. + * @param size Bytes to be written. + */ +void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); + +/*! + * @brief Writes a data into data register. + * + * @param base FlexIO I2S base pointer. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param data Data to be written. + */ +static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data) +{ + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); +} + +/*! + * @brief Receives a piece of data using a blocking method. + * + * @note This function blocks via polling until data is ready to be sent. + * + * @param base FlexIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param rxData Pointer to the data to be read. + * @param size Bytes to be read. + */ +void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); + +/*! + * @brief Reads a data from the data register. + * + * @param base FlexIO I2S base pointer + * @return Data read from data register. + */ +static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base) +{ + return base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param handle pointer to flexio_i2s_handle_t structure to store the transfer state. + * @param callback FlexIO I2S callback function, which is called while finished a block. + * @param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData); + +/*! + * @brief Configures the FlexIO I2S audio format. + * + * Audio format can be changed in run-time of FlexIO i2s. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle FlexIO I2S handle pointer. + * @param format Pointer to audio data format structure. + * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. +*/ +void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz); + +/*! + * @brief Initializes the FlexIO I2S receive handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Usually, user only need to call this API once to get the + * initialized handle. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure to store the transfer state. + * @param callback FlexIO I2S callback function, which is called while finished a block. + * @param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData); + +/*! + * @brief Performs an interrupt non-blocking send transfer on FlexIO I2S. + * + * @note Calling the API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2s_transfer_t structure + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on FlexIO I2S. + * + * @note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2s_transfer_t structure + * @retval kStatus_Success Successfully start the data receive. + * @retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); + +/*! + * @brief Aborts the current receive. + * + * @note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be sent. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param count Bytes sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); + +/*! + * @brief Gets the remaining bytes to be received. + * + * @param base pointer to FLEXIO_I2S_Type structure. + * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state + * @return count Bytes received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); + +/*! + * @brief Tx interrupt handler. + * + * @param i2sBase pointer to FLEXIO_I2S_Type structure. + * @param i2sHandle pointer to flexio_i2s_handle_t structure + */ +void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle); + +/*! + * @brief Rx interrupt handler. + * + * @param i2sBase pointer to FLEXIO_I2S_Type structure. + * @param i2sHandle pointer to flexio_i2s_handle_t structure + */ +void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_FLEXIO_I2S_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c new file mode 100755 index 00000000000..07a1178691a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_i2s_dma.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (flexio_i2sHandle->callback) + { + (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortSendDMA(privHandle->base, flexio_i2sHandle); + } +} + +static void FLEXIO_I2S_RxDMACallback(dma_handle_t *handle, void *userData) +{ + flexio_i2s_dma_private_handle_t *privHandle = (flexio_i2s_dma_private_handle_t *)userData; + flexio_i2s_dma_handle_t *flexio_i2sHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (flexio_i2sHandle->callback) + { + (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortReceiveDMA(privHandle->base, flexio_i2sHandle); + } +} + +void FLEXIO_I2S_TransferTxCreateHandleDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_dma_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + /* Set flexio_i2s base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set FLEXIO I2S state to idle */ + handle->state = kFLEXIO_I2S_Idle; + + s_dmaPrivateHandle[0].base = base; + s_dmaPrivateHandle[0].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(dmaHandle, FLEXIO_I2S_TxDMACallback, &s_dmaPrivateHandle[0]); +} + +void FLEXIO_I2S_TransferRxCreateHandleDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_dma_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + /* Set flexio_i2s base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set FLEXIO I2S state to idle */ + handle->state = kFLEXIO_I2S_Idle; + + s_dmaPrivateHandle[1].base = base; + s_dmaPrivateHandle[1].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(dmaHandle, FLEXIO_I2S_RxDMACallback, &s_dmaPrivateHandle[1]); +} + +void FLEXIO_I2S_TransferSetFormatDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz) +{ + assert(handle && format); + + /* Configure the audio format to FLEXIO I2S registers */ + if (srcClock_Hz != 0) + { + /* It is master */ + FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); + } + else + { + FLEXIO_I2S_SlaveSetFormat(base, format); + } + + /* Get the tranfer size from format, this should be used in DMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; +} + +status_t FLEXIO_I2S_TransferSendDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, flexio_i2s_transfer_t *xfer) +{ + assert(handle && xfer); + + dma_transfer_config_t config = {0}; + uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + /* Change the state of handle */ + handle->state = kFLEXIO_I2S_Busy; + + /* Update the queue state */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + DMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + xfer->dataSize, kDMA_MemoryToPeripheral); + + /* Configure DMA channel */ + DMA_SubmitTransfer(handle->dmaHandle, &config, true); + + /* Start DMA transfer */ + DMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + FLEXIO_I2S_TxEnableDMA(base, true); + + /* Enable FLEXIO I2S Tx clock */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +status_t FLEXIO_I2S_TransferReceiveDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle && xfer); + + dma_transfer_config_t config = {0}; + uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) - (4U - handle->bytesPerFrame); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + /* Change the state of handle */ + handle->state = kFLEXIO_I2S_Busy; + + /* Update queue state */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Prepare dma configure */ + DMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + xfer->dataSize, kDMA_PeripheralToMemory); + + DMA_SubmitTransfer(handle->dmaHandle, &config, true); + + /* Start DMA transfer */ + DMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + FLEXIO_I2S_RxEnableDMA(base, true); + + /* Enable FLEXIO I2S Rx clock */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +void FLEXIO_I2S_TransferAbortSendDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + FLEXIO_I2S_TxEnableDMA(base, false); + + /* Set the handle state */ + handle->state = kFLEXIO_I2S_Idle; +} + +void FLEXIO_I2S_TransferAbortReceiveDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + FLEXIO_I2S_RxEnableDMA(base, false); + + /* Set the handle state */ + handle->state = kFLEXIO_I2S_Idle; +} + +status_t FLEXIO_I2S_TransferGetSendCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferSize[handle->queueDriver] - + DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel); + } + + return status; +} + +status_t FLEXIO_I2S_TransferGetReceiveCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferSize[handle->queueDriver] - + DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel); + } + + return status; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h new file mode 100755 index 00000000000..a8e52c184f5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_I2S_DMA_H_ +#define _FSL_FLEXIO_I2S_DMA_H_ + +#include "fsl_flexio_i2s.h" +#include "fsl_dma.h" + +/*! + * @addtogroup flexio_dma_i2s + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef struct _flexio_i2s_dma_handle flexio_i2s_dma_handle_t; + +/*! @brief FlexIO I2S DMA transfer callback function for finish and error */ +typedef void (*flexio_i2s_dma_callback_t)(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO I2S DMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_i2s_dma_handle +{ + dma_handle_t *dmaHandle; /*!< DMA handler for FlexIO I2S send */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint32_t state; /*!< Internal state for FlexIO I2S DMA transfer */ + flexio_i2s_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ + void *userData; /*!< User callback parameter */ + flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S DMA handle. + * + * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master + * transactional APIs. + * Usually, for a specified FlexIO I2S instance, user need only call this API once to get the initialized handle. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param callback FlexIO I2S DMA callback function called while finished a block. + * @param userData User parameter for callback. + * @param dmaHandle DMA handle for FlexIO I2S. This handle shall be a static value allocated by users. + */ +void FLEXIO_I2S_TransferTxCreateHandleDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_dma_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Initializes the FlexIO I2S Rx DMA handle. + * + * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional + * APIs. + * Usually, for a specified FlexIO I2S instance, user need only call this API once to get the initialized handle. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param callback FlexIO I2S DMA callback function called while finished a block. + * @param userData User parameter for callback. + * @param dmaHandle DMA handle for FlexIO I2S. This handle shall be a static value allocated by users. + */ +void FLEXIO_I2S_TransferRxCreateHandleDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_dma_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Configures the FlexIO I2S Tx audio format. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. This function also sets DMA parameter according to format. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer + * @param format Pointer to FlexIO I2S audio data format structure. + * @param srcClock_Hz FlexIO I2S clock source frequency in Hz. It should be 0 while in slave mode. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. +*/ +void FLEXIO_I2S_TransferSetFormatDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz); + +/*! + * @brief Performs a non-blocking FlexIO I2S transfer using DMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether FLEXIO I2S transfer finished. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a FlexIO I2S DMA send successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + * @retval kStatus_TxBusy FlexIO I2S is busy sending data. + */ +status_t FLEXIO_I2S_TransferSendDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking FlexIO I2S receive using DMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status to check whether the FlexIO I2S transfer is finished. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a FlexIO I2S DMA receive successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + * @retval kStatus_RxBusy FlexIO I2S is busy receiving data. + */ +status_t FLEXIO_I2S_TransferReceiveDMA(FLEXIO_I2S_Type *base, + flexio_i2s_dma_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO I2S transfer using DMA. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortSendDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle); + +/*! + * @brief Aborts a FlexIO I2S receive using DMA. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortReceiveDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be sent. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param count Bytes sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count); + +/*! + * @brief Gets the remaining bytes to be received. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param count Bytes received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCountDMA(FLEXIO_I2S_Type *base, flexio_i2s_dma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c new file mode 100755 index 00000000000..65c987a6ffd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c @@ -0,0 +1,935 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_spi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ +enum _flexio_spi_transfer_states +{ + kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ + kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Send a piece of data for SPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for SPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = *(handle->txData); + handle->txData++; + } + else + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += handle->txData[1]; + handle->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes -= handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + if (!handle->txRemainingBytes) + { + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + } +} + +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint16_t tmpData; + + tmpData = FLEXIO_SPI_ReadData(base, handle->direction); + + if (handle->rxData != NULL) + { + if (handle->bytePerFrame == 1U) + { + *handle->rxData = tmpData; + handle->rxData++; + } + else + { + *((uint16_t *)(handle->rxData)) = tmpData; + handle->rxData += 2U; + } + } + handle->rxRemainingBytes -= handle->bytePerFrame; +} + +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base); + assert(masterConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + + /* Ungate flexio clock. */ + CLOCK_EnableClock(kCLOCK_Flexio0); + + /* Configure FLEXIO SPI Master */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DOZEN(masterConfig->enableInDoze) | FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | + FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for SCK. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = srcClock_Hz / masterConfig->baudRate_Bps; + timerDiv = timerDiv / 2 - 1; + + timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for CSn. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->CSnPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + timerConfig.timerCompare = 0xFFFFU; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); +} + +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) +{ + /* Disable FLEXIO SPI module. */ + FLEXIO_SPI_Enable(base, false); + + /* Gate flexio clock. */ + CLOCK_DisableClock(kCLOCK_Flexio0); +} + +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) +{ + assert(masterConfig); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + /* Default baud rate 500kbps. */ + masterConfig->baudRate_Bps = 500000U; + /* Default CPHA = 0. */ + masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + masterConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) +{ + assert(base && slaveConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + + /* Ungate flexio clock. */ + CLOCK_EnableClock(kCLOCK_Flexio0); + + /* Configure FLEXIO SPI Slave */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DOZEN(slaveConfig->enableInDoze) | FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | + FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for shift clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous + PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + } + else + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + } + + timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); +} + +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) +{ + FLEXIO_SPI_MasterDeinit(base); +} + +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + slaveConfig->enableSlave = true; + slaveConfig->enableInDoze = false; + slaveConfig->enableInDebug = true; + slaveConfig->enableFastAccess = false; + /* Default CPHA = 0. */ + slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); + } +} + +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); + } +} + +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) +{ + if (mask & kFLEXIO_SPI_TxDmaEnable) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable); + } + + if (mask & kFLEXIO_SPI_RxDmaEnable) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable); + } +} + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) +{ + uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); + uint32_t status = 0; + + status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); + + return status; +} + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxBufferEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxBufferFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = srcClockHz / baudRate_Bps; + timerDiv = timerDiv / 2 - 1U; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0xFF00U; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size) +{ + assert(buffer); + assert(size); + + while (size--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) + { + } + FLEXIO_SPI_WriteData(base, direction, *buffer++); + } +} + +void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size) +{ + assert(buffer); + assert(size); + + while (size--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) + { + } + *buffer++ = FLEXIO_SPI_ReadData(base, direction); + } +} + +void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) +{ + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + timerCmp &= 0x00FFU; + /* Configure the values in handle. */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case kFLEXIO_SPI_8bitLsb: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case kFLEXIO_SPI_16bitMsb: + dataMode = (16 * 2 - 1U) << 8U; + bytesPerFrame = 2; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case kFLEXIO_SPI_16bitLsb: + dataMode = (16 * 2 - 1U) << 8U; + bytesPerFrame = 2; + direction = kFLEXIO_SPI_LsbFirst; + break; + + default: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + while (xfer->dataSize) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) + { + } + if (xfer->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (bytesPerFrame == 1U) + { + tmpData = *(xfer->txData); + xfer->txData++; + } + else + { + tmpData = (uint32_t)(xfer->txData[0]) << 8U; + tmpData += xfer->txData[1]; + xfer->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + xfer->dataSize -= bytesPerFrame; + + FLEXIO_SPI_WriteData(base, direction, tmpData); + + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) + { + } + tmpData = FLEXIO_SPI_ReadData(base, direction); + + if (xfer->rxData != NULL) + { + if (bytesPerFrame == 1U) + { + *xfer->rxData = tmpData; + xfer->rxData++; + } + else + { + *((uint16_t *)(xfer->rxData)) = tmpData; + xfer->rxData += 2U; + } + } + } +} + +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[0]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); +} + +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + timerCmp &= 0x00FFU; + + /* Check if SPI is busy. */ + if (handle->state == kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Configure the values in handle */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + dataMode = (16 * 2 - 1U) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + dataMode = (16 * 2 - 1U) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Send first byte of data to trigger the rx interrupt. */ + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = *(handle->txData); + handle->txData++; + } + else + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += handle->txData[1]; + handle->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + /* Enable transmit and receive interrupt to handle rx. */ + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Return remaing bytes in different cases. */ + if (handle->rxData) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + + return kStatus_Success; +} + +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + assert(handle); + + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + + /* Transfer finished, set the state to idle. */ + handle->state = kFLEXIO_SPI_Idle; + + /* Clear the internal state. */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle rx. */ + if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* Handle tx. */ + if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_MasterTransferAbort(base, handle); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[0]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); +} + +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + + /* Check if SPI is busy. */ + if (handle->state == kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Configure the values in handle */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + dataMode = 16 * 2 - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + dataMode = 16 * 2 - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Enable transmit and receive interrupt to handle tx and rx. */ + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle tx. */ + if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* Handle rx. */ + if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_SlaveTransferAbort(base, handle); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h new file mode 100755 index 00000000000..34c7fba02b1 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXIO_SPI_H_ +#define _FSL_FLEXIO_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_spi + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI driver version 2.1.0. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ +#define FLEXIO_SPI_DUMMYDATA (0xFFFFU) + +/*! @brief Error codes for the FlexIO SPI driver. */ +enum _flexio_spi_status +{ + kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ + kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ + kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ +}; + +/*! @brief FlexIO SPI clock phase configuration. */ +typedef enum _flexio_spi_clock_phase +{ + kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. */ + kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer. */ +} flexio_spi_clock_phase_t; + +/*! @brief FlexIO SPI data shifter direction options. */ +typedef enum _flexio_spi_shift_direction +{ + kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ + kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ +} flexio_spi_shift_direction_t; + +/*! @brief FlexIO SPI data length mode options. */ +typedef enum _flexio_spi_data_bitcount_mode +{ + kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ + kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ +} flexio_spi_data_bitcount_mode_t; + +/*! @brief Define FlexIO SPI interrupt mask. */ +enum _flexio_spi_interrupt_enable +{ + kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO SPI status mask. */ +enum _flexio_spi_status_flags +{ + kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO SPI DMA mask. */ +enum _flexio_spi_dma_enable +{ + kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ + kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ +}; + +/*! @brief Define FlexIO SPI transfer flags. */ +enum _flexio_spi_transfer_flags +{ + kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ + kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ +}; + +/*! @brief Define FlexIO SPI access structure typedef. */ +typedef struct _flexio_spi_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDOPinIndex; /*!< Pin select for data output. */ + uint8_t SDIPinIndex; /*!< Pin select for data input. */ + uint8_t SCKPinIndex; /*!< Pin select for clock. */ + uint8_t CSnPinIndex; /*!< Pin select for enable. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ +} FLEXIO_SPI_Type; + +/*! @brief Define FlexIO SPI master configuration structure. */ +typedef struct _flexio_spi_master_config +{ + bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_master_config_t; + +/*! @brief Define FlexIO SPI slave configuration structure. */ +typedef struct _flexio_spi_slave_config +{ + bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_slave_config_t; + +/*! @brief Define FlexIO SPI transfer structure. */ +typedef struct _flexio_spi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t dataSize; /*!< Transfer bytes. */ + uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ +} flexio_spi_transfer_t; + +/*! @brief typedef for flexio_spi_master_handle_t in advance. */ +typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO SPI handle structure. */ +struct _flexio_spi_master_handle +{ + uint8_t *txData; /*!< Transfer buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ + volatile uint32_t state; /*!< FlexIO SPI internal state. */ + uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ + flexio_spi_shift_direction_t direction; /*!< Shift direction. */ + flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO SPI Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module and configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Gates the FlexIO clock. + * + * @param base Pointer to the FLEXIO_SPI_Type. +*/ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + @code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + @endcode + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + @endcode + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); + +/*! + * @brief Gates the FlexIO clock. + * + * @param base Pointer to the FLEXIO_SPI_Type. +*/ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + @code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + @endcode + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @return status flag; Use the status flag to AND the following flag mask and get the status. + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag +*/ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); + +/*! + * @brief Clears FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask status flag + * The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag +*/ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source. The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask SPI DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI transmit data register address. + */ +static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, + base->shifterIndex[0]) + + 3U; + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); + } +} + +/*! + * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI receive data register address. + */ +static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, + base->shifterIndex[1]); + } +} + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI module operation. + * + * @param base Pointer to the FLEXIO_SPI_Type. + * @param enable True to enable, false to disable. +*/ +static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param baudRate_Bps Baud Rate needed in Hz. + * @param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); + +/*! + * @brief Writes one byte of data, which is sent using the MSB method. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param data 8 bit/16 bit data. + */ +static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; + } + else + { + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; + } +} + +/*! + * @brief Reads 8 bit/16 bit data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return 8 bit/16 bit data received. + */ +static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; + } + else + { + return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + } +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The data bytes to send. + * @param size The number of data bytes to send. + */ +void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The buffer to store the received bytes. + * @param size The number of data bytes to be received. + * @param direction Shift direction of MSB first or LSB first. + */ +void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + */ +void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the master data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO SPI master IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); + +/*! + * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the slave data transfer which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbort(base, handle); +} +/*! + * @brief Gets the data transfer status which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief FlexIO SPI slave IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_SPI_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c new file mode 100755 index 00000000000..157d0eb466c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_spi_dma.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ + +/*base, kFLEXIO_SPI_TxDmaEnable, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(handle->base, handle->channel); + + /* change the state. */ + spiPrivateHandle->handle->txInProgress = false; + + /* All finished, call the callback. */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } +} + +static void FLEXIO_SPI_RxDMACallback(dma_handle_t *handle, void *param) +{ + flexio_spi_master_dma_private_handle_t *spiPrivateHandle = (flexio_spi_master_dma_private_handle_t *)param; + + /* Disable Rx DMA. */ + FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_RxDmaEnable, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(handle->base, handle->channel); + + /* change the state. */ + spiPrivateHandle->handle->rxInProgress = false; + + /* All finished, call the callback. */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } +} + +static void FLEXIO_SPI_DMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + dma_transfer_config_t xferConfig; + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + + /* Configure the values in handle. */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + bytesPerFrame = 2; + direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + bytesPerFrame = 2; + direction = kFLEXIO_SPI_LsbFirst; + break; + default: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Configure tx transfer DMA. */ + xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); + xferConfig.enableDestIncrement = false; + if (bytesPerFrame == 1U) + { + xferConfig.srcSize = kDMA_Transfersize8bits; + xferConfig.destSize = kDMA_Transfersize8bits; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 1U; + } + xferConfig.srcSize = kDMA_Transfersize16bits; + xferConfig.destSize = kDMA_Transfersize16bits; + } + + /* Configure DMA channel. */ + if (xfer->txData) + { + xferConfig.enableSrcIncrement = true; + xferConfig.srcAddr = (uint32_t)(xfer->txData); + } + else + { + /* Disable the source increasement and source set to dummyData. */ + xferConfig.enableSrcIncrement = false; + xferConfig.srcAddr = (uint32_t)(&s_dummyData); + } + + xferConfig.transferSize = xfer->dataSize; + + if (handle->txHandle) + { + DMA_SubmitTransfer(handle->txHandle, &xferConfig, kDMA_EnableInterrupt); + } + + /* Configure tx transfer DMA. */ + if (xfer->rxData) + { + xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); + xferConfig.enableSrcIncrement = false; + xferConfig.destAddr = (uint32_t)(xfer->rxData); + xferConfig.enableDestIncrement = true; + DMA_SubmitTransfer(handle->rxHandle, &xferConfig, kDMA_EnableInterrupt); + handle->rxInProgress = true; + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true); + DMA_StartTransfer(handle->rxHandle); + } + + /* Always start Tx transfer. */ + if (handle->txHandle) + { + handle->txInProgress = true; + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true); + DMA_StartTransfer(handle->txHandle); + } +} + +status_t FLEXIO_SPI_MasterTransferCreateHandleDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + flexio_spi_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + assert(handle); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_SPI_HANDLE_COUNT; index++) + { + if (s_dmaPrivateHandle[index].base == NULL) + { + s_dmaPrivateHandle[index].base = base; + s_dmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_SPI_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + /* Set spi base to handle. */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle. */ + handle->txInProgress = false; + handle->rxInProgress = false; + + /* Install callback for Tx/Rx dma channel. */ + if (handle->txHandle) + { + DMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxDMACallback, &s_dmaPrivateHandle[index]); + } + if (handle->rxHandle) + { + DMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxDMACallback, &s_dmaPrivateHandle[index]); + } + + return kStatus_Success; +} + +status_t FLEXIO_SPI_MasterTransferDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + + timerCmp &= 0x00FFU; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) + { + dataMode = (8 * 2 - 1U) << 8U; + } + else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) + { + dataMode = (16 * 2 - 1U) << 8U; + } + else + { + dataMode = 8 * 2 - 1U; + } + + dataMode |= timerCmp; + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + FLEXIO_SPI_DMAConfig(base, handle, xfer); + + return kStatus_Success; +} + +status_t FLEXIO_SPI_MasterTransferGetCountDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->rxInProgress) + { + *count = (handle->transferSize - DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel)); + } + else + { + *count = (handle->transferSize - DMA_GetRemainingBytes(handle->txHandle->base, handle->txHandle->channel)); + } + + return kStatus_Success; +} + +void FLEXIO_SPI_MasterTransferAbortDMA(FLEXIO_SPI_Type *base, flexio_spi_master_dma_handle_t *handle) +{ + assert(handle); + + /* Disable dma. */ + DMA_AbortTransfer(handle->txHandle); + DMA_AbortTransfer(handle->rxHandle); + + /* Disable DMA enable bit. */ + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_DmaAllEnable, false); + + /* Set the handle state. */ + handle->txInProgress = false; + handle->rxInProgress = false; +} + +status_t FLEXIO_SPI_SlaveTransferDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_dma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) + { + dataMode = 8 * 2 - 1U; + } + else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) + { + dataMode = 16 * 2 - 1U; + } + else + { + dataMode = 8 * 2 - 1U; + } + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + FLEXIO_SPI_DMAConfig(base, handle, xfer); + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h new file mode 100755 index 00000000000..e154090b44e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_SPI_DMA_H_ +#define _FSL_FLEXIO_SPI_DMA_H_ + +#include "fsl_flexio_spi.h" +#include "fsl_dma.h" + +/*! + * @addtogroup flexio_dma_spi + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief typedef for flexio_spi_master_dma_handle_t in advance. */ +typedef struct _flexio_spi_master_dma_handle flexio_spi_master_dma_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_dma_handle_t flexio_spi_slave_dma_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_dma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_dma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_spi_master_dma_handle +{ + size_t transferSize; /*!< Total bytes to be transferred. */ + bool txInProgress; /*!< Send transfer in progress */ + bool rxInProgress; /*!< Receive transfer in progress */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + flexio_spi_master_dma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXO SPI master DMA handle. + * + * This function initializes the FLEXO SPI master DMA handle which can be used for other FLEXO SPI master transactional + * APIs. + * Usually, for a specified FLEXO SPI instance, user need only call this API once to get the initialized handle. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle pointer to flexio_spi_master_dma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested DMA handle for FlexIO SPI RX DMA transfer. + * @param rxHandle User requested DMA handle for FlexIO SPI TX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI DMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + flexio_spi_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users could call + * FLEXIO_SPI_MasterGetTransferCountDMA to poll the transfer status to check + * whether FlexIO SPI transfer finished. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle pointer to flexio_spi_master_dma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using DMA. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI DMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortDMA(FLEXIO_SPI_Type *base, flexio_spi_master_dma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO SPI DMA transfer. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI DMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_dma_handle_t *handle, + size_t *count); + +/*! + * @brief Initializes the FlexIO SPI slave DMA handle. + * + * This function initializes the FlexIO SPI slave DMA handle. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested DMA handle for FlexIO SPI TX DMA transfer. + * @param rxHandle User requested DMA handle for FlexIO SPI RX DMA transfer. + */ +static inline void FLEXIO_SPI_SlaveTransferCreateHandleDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_dma_handle_t *handle, + flexio_spi_slave_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + FLEXIO_SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users could call + * FLEXIO_SPI_SlaveGetTransferCountDMA to poll the transfer status to + * check whether FlexIO SPI transfer finished. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_dma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using DMA. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle pointer to flexio_spi_slave_dma_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbortDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_dma_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Gets the remaining bytes to be transferred for FlexIO SPI DMA. + * + * @param base pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI DMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCountDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_dma_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c new file mode 100755 index 00000000000..92349ea5a5f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c @@ -0,0 +1,690 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) +{ + bool full; + + if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +void FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) +{ + assert(base && userConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + + /* Ungate flexio clock. */ + CLOCK_EnableClock(kCLOCK_Flexio0); + + /* Reset FLEXIO before configuration. */ + FLEXIO_Reset(base->flexioBase); + + /* Configure FLEXIO UART */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DOZEN(userConfig->enableInDoze) | FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | + FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->TxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /*2. Configure the timer 0 for tx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->TxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = srcClock_Hz / userConfig->baudRate_Bps; + timerDiv = timerDiv / 2 - 1; + + timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 3. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->RxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /* 4. Configure the timer 1 for rx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->RxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); +} + +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) +{ + /* Disable FLEXIO UART module. */ + FLEXIO_UART_Enable(base, false); + + /* Gate flexio clock. */ + CLOCK_DisableClock(kCLOCK_Flexio0); +} + +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) +{ + assert(userConfig); + + userConfig->enableUart = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; + /* Default baud rate 115200. */ + userConfig->baudRate_Bps = 115200U; + /* Default bit count at 8. */ + userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; +} + +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) +{ + uint32_t status = 0; + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + return status; +} + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } + if (mask & kFLEXIO_UART_RxOverRunFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) +{ + assert(txData); + assert(txSize); + + while (txSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))) + { + } + + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; + } +} + +void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) +{ + assert(rxData); + assert(rxSize); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag)) + { + } + + *rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + } +} + +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kFLEXIO_UART_RxIdle; + handle->txState = kFLEXIO_UART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[0]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); +} + +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ringbuffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } +} + +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kFLEXIO_UART_RxIdle) + { + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txState = kFLEXIO_UART_TxBusy; + + /* Enable transmiter interrupt. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Disable the transmitter and disable the interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kFLEXIO_UART_TxIdle; +} + +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_Success; + } + + *count = handle->txSize - handle->txDataSize; + + return kStatus_Success; +} + +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = __get_PRIMASK(); + __disable_irq(); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxState = kFLEXIO_UART_RxBusy; + } + + /* Recover PRIMASK, enable IRQ if previously enabled. */ + __set_PRIMASK(regPrimask); + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxState = kFLEXIO_UART_RxBusy; + + /* Enable RX interrupt. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kFLEXIO_UART_RxIdle; +} + +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_Success; + } + + *count = handle->rxSize - handle->rxDataSize; + + return kStatus_Success; +} + +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) +{ + uint8_t count = 1; + FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; + flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; + + /* Read the status back. */ + uint8_t status = FLEXIO_UART_GetStatusFlags(base); + + /* If RX overrun. */ + if (kFLEXIO_UART_RxOverRunFlag & status) + { + /* Clear Overrun flag. */ + FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1]))) + { + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + if (handle->rxDataSize) + { + /* Using non block API to read the data from the registers. */ + FLEXIO_UART_ReadByte(base, handle->rxData); + handle->rxDataSize--; + handle->rxData++; + count--; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kFLEXIO_UART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + + if (handle->rxRingBuffer) + { + if (count) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0]))) + { + if (handle->txDataSize) + { + /* Using non block API to write the data to the registers. */ + FLEXIO_UART_WriteByte(base, handle->txData); + handle->txData++; + handle->txDataSize--; + count--; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kFLEXIO_UART_TxIdle; + + /* Disable TX register empty interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); + } + } + } + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h new file mode 100755 index 00000000000..9ffe6a8a62c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h @@ -0,0 +1,586 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXIO_UART_H_ +#define _FSL_FLEXIO_UART_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_uart + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART driver version 2.1.0. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _flexio_uart_status +{ + kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ + kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ + kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ + kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ + kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ + kStatus_FLEXIO_UART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ + kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */ +}; + +/*! @brief FlexIO UART bit count per char. */ +typedef enum _flexio_uart_bit_count_per_char +{ + kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ + kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ + kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ +} flexio_uart_bit_count_per_char_t; + +/*! @brief Define FlexIO UART interrupt mask. */ +enum _flexio_uart_interrupt_enable +{ + kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO UART status mask. */ +enum _flexio_uart_status_flags +{ + kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ +}; + +/*! @brief Define FlexIO UART access structure typedef. */ +typedef struct _flexio_uart_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ + uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ +} FLEXIO_UART_Type; + +/*! @brief Define FlexIO UART user configuration structure. */ +typedef struct _flexio_uart_config +{ + bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ +} flexio_uart_config_t; + +/*! @brief Define FlexIO UART transfer structure. */ +typedef struct _flexio_uart_transfer +{ + uint8_t *data; /*!< Transfer buffer*/ + size_t dataSize; /*!< Transfer size*/ +} flexio_uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_handle flexio_uart_handle_t; + +/*! @brief FlexIO UART transfer callback function. */ +typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FLEXIO UART handle structure*/ +struct _flexio_uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t txSize; /*!< Total bytes to be sent. */ + size_t rxSize; /*!< Total bytes to be received. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + flexio_uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user, or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + @code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param userConfig Pointer to the flexio_uart_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); + +/*! + * @brief Disables the FlexIO UART and gates the FlexIO clock. + * + * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * @param base pointer to FLEXIO_UART_Type structure +*/ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + @code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + @endcode + * @param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART status flags. +*/ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_UART_TxDataRegEmptyFlag + * @arg kFLEXIO_UART_RxEmptyFlag + * @arg kFLEXIO_UART_RxOverRunFlag +*/ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the FlexIO UARt transmit data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART transmit data register address. + */ +static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); +} + +/*! + * @brief Gets the FlexIO UART receive data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART receive data register address. + */ +static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); +} + +/*! + * @brief Enables/disables the FlexIO UART transmit DMA. + * This function enables/disables the FlexIO UART Tx DMA, + * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[0], enable); +} + +/*! + * @brief Enables/disables the FlexIO UART receive DMA. + * This function enables/disables the FlexIO UART Rx DMA, + * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[1], enable); +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO UART module operation. + * + * @param base Pointer to the FLEXIO_UART_Type. + * @param enable True to enable, false to disable. +*/ +static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Writes one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register. Ensure that the TxEmptyFlag is asserted before calling + * this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The data bytes to send. + */ +static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) +{ + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; +} + +/*! + * @brief Reads one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The buffer to store the received bytes. + */ +static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) +{ + *buffer = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param txData The data bytes to send. + * @param txSize The number of data bytes to send. + */ +void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param rxData The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + */ +void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that user can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, user can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base to FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there are already data received + * in the ring buffer, user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_StopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data are written to TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * @retval kStatus_Success Successfully starts the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to know + * how many bytes are still not sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of remaining bytes not sent. + * + * This function gets the number of remaining bytes not sent driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer UART transfer structure. See #flexio_uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of remaining bytes not received. + * + * This function gets the number of remaining bytes not received driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * @param uartType Pointer to the FLEXIO_UART_Type structure. + * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_UART_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c new file mode 100755 index 00000000000..10a06fa5934 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c @@ -0,0 +1,358 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexio_uart_dma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(handle->base, handle->channel); + + uartPrivateHandle->handle->txState = kFLEXIO_UART_TxIdle; + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); + } +} + +static void FLEXIO_UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param) +{ + flexio_uart_dma_private_handle_t *uartPrivateHandle = (flexio_uart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + FLEXIO_UART_EnableRxDMA(uartPrivateHandle->base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(handle->base, handle->channel); + + uartPrivateHandle->handle->rxState = kFLEXIO_UART_RxIdle; + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); + } +} + +status_t FLEXIO_UART_TransferCreateHandleDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + flexio_uart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + assert(handle); + + dma_transfer_config_t dmaXferConfig; + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++) + { + if (s_dmaPrivateHandle[index].base == NULL) + { + s_dmaPrivateHandle[index].base = base; + s_dmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_UART_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kFLEXIO_UART_RxIdle; + handle->txState = kFLEXIO_UART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Set DMA channel configuration. */ + memset(&dmaXferConfig, 0, sizeof(dmaXferConfig)); + dmaXferConfig.srcSize = kDMA_Transfersize8bits; + dmaXferConfig.destSize = kDMA_Transfersize8bits; + + /* Configure TX. */ + if (txDmaHandle) + { + DMA_SetCallback(txDmaHandle, FLEXIO_UART_TransferSendDMACallback, &s_dmaPrivateHandle[index]); + + DMA_ResetChannel(txDmaHandle->base, txDmaHandle->channel); + + dmaXferConfig.destAddr = FLEXIO_UART_GetTxDataRegisterAddress(base); + dmaXferConfig.enableSrcIncrement = true; + dmaXferConfig.enableDestIncrement = false; + DMA_SetTransferConfig(txDmaHandle->base, txDmaHandle->channel, &dmaXferConfig); + } + + /* Configure RX. */ + if (rxDmaHandle) + { + DMA_SetCallback(rxDmaHandle, FLEXIO_UART_TransferReceiveDMACallback, &s_dmaPrivateHandle[index]); + + DMA_ResetChannel(rxDmaHandle->base, rxDmaHandle->channel); + + dmaXferConfig.destAddr = 0U; + dmaXferConfig.srcAddr = FLEXIO_UART_GetRxDataRegisterAddress(base); + dmaXferConfig.enableSrcIncrement = false; + dmaXferConfig.enableDestIncrement = true; + DMA_SetTransferConfig(rxDmaHandle->base, rxDmaHandle->channel, &dmaXferConfig); + } + + return kStatus_Success; +} + +status_t FLEXIO_UART_TransferSendDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->txDmaHandle); + + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txState = kFLEXIO_UART_TxBusy; + + /* Set transfer data address and data size. */ + DMA_SetSourceAddress(handle->txDmaHandle->base, handle->txDmaHandle->channel, (uint32_t)xfer->data); + DMA_SetTransferSize(handle->txDmaHandle->base, handle->txDmaHandle->channel, xfer->dataSize); + + /* Enable FLEXIO UART TX DMA. */ + FLEXIO_UART_EnableTxDMA(base, true); + + /* Enable DMA transfer complete interrupt and start transfer. */ + DMA_EnableInterrupts(handle->txDmaHandle->base, handle->txDmaHandle->channel); + DMA_EnableChannelRequest(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + status = kStatus_Success; + } + + return status; +} + +status_t FLEXIO_UART_TransferReceiveDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->rxDmaHandle); + + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + handle->rxState = kFLEXIO_UART_RxBusy; + + /* Set transfer data address and data size. */ + DMA_SetDestinationAddress(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, (uint32_t)xfer->data); + DMA_SetTransferSize(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, xfer->dataSize); + + /* Enable FLEXIO UART RX DMA. */ + FLEXIO_UART_EnableRxDMA(base, true); + + /* Enable DMA transfer complete interrupt and start transfer. */ + DMA_EnableInterrupts(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + DMA_EnableChannelRequest(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + status = kStatus_Success; + } + + return status; +} + +void FLEXIO_UART_TransferAbortSendDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle) +{ + assert(handle->txDmaHandle); + + /* Disable FLEXIO UART TX DMA. */ + FLEXIO_UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + DMA_StopTransfer(handle->txDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag); + + handle->txState = kFLEXIO_UART_TxIdle; +} + +void FLEXIO_UART_TransferAbortReceiveDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle) +{ + assert(handle->rxDmaHandle); + + /* Disable FLEXIO UART RX DMA. */ + FLEXIO_UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + DMA_StopTransfer(handle->rxDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag); + + handle->rxState = kFLEXIO_UART_RxIdle; +} + +status_t FLEXIO_UART_TransferGetSendCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count) +{ + assert(handle->txDmaHandle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kFLEXIO_UART_TxBusy == handle->txState) + { + *count = (handle->txSize - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel)); + } + else + { + *count = handle->txSize; + } + + return kStatus_Success; +} + +status_t FLEXIO_UART_TransferGetReceiveCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count) +{ + assert(handle->rxDmaHandle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + *count = (handle->rxSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel)); + } + else + { + *count = handle->rxSize; + } + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h new file mode 100755 index 00000000000..e1defb6d05f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXIO_UART_DMA_H_ +#define _FSL_FLEXIO_UART_DMA_H_ + +#include "fsl_flexio_uart.h" +#include "fsl_dmamux.h" +#include "fsl_dma.h" + +/*! + * @addtogroup flexio_dma_uart + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_dma_handle flexio_uart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*flexio_uart_dma_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART DMA handle +*/ +struct _flexio_uart_dma_handle +{ + flexio_uart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + size_t txSize; /*!< Total bytes to be sent. */ + size_t rxSize; /*!< Total bytes to be received. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXIO_UART handle which is used in transactional functions + * + * @param base Pointer to FLEXIO_UART_Type structure. + * @param handle Pointer to flexio_uart_dma_handle_t structure. + * @param callback FlexIO UART callback, NULL means no callback. + * @param userData User callback function data. + * @param txDmaHandle User requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User requested DMA handle for RX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO UART DMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + flexio_uart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function send data using DMA, this is non-blocking function, which return + * right away. When all data have been sent out, the send callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type structure + * @param handle Pointer to flexio_uart_dma_handle_t structure + * @param xfer FLEXIO_UART DMA transfer structure, refer to #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is non-blocking function, which returns + * right away. When all data have been received, the receive callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type structure + * @param handle Pointer to flexio_uart_dma_handle_t structure + * @param xfer FLEXIO_UART DMA transfer sturcture, refer to #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXIO_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data which using DMA. + * + * This function aborts the sent data which using DMA. + * + * @param base Pointer to FLEXIO_UART_Type structure + * @param handle Pointer to flexio_uart_dma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle); + +/*! + * @brief Aborts the receive data which using DMA. + * + * This function aborts the receive data which using DMA. + * + * @param base Pointer to FLEXIO_UART_Type structure + * @param handle Pointer to flexio_uart_dma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle); + +/*! + * @brief Gets the number of bytes still not sent out. + * + * This function gets the number of bytes still not sent out. + * + * @param base Pointer to FLEXIO_UART_Type structure + * @param handle Pointer to flexio_uart_dma_handle_t structure + * @param count Number of bytes sent so far by the non-blocking transaction. + */ +status_t FLEXIO_UART_TransferGetSendCountDMA(FLEXIO_UART_Type *base, flexio_uart_dma_handle_t *handle, size_t *count); + +/*! + * @brief Gets the number of bytes still not received. + * + * This function gets the number of bytes still not received. + * + * @param base Pointer to FLEXIO_UART_Type structure + * @param handle Pointer to flexio_uart_dma_handle_t structure + * @param count Number of bytes received so far by the non-blocking transaction. + */ +status_t FLEXIO_UART_TransferGetReceiveCountDMA(FLEXIO_UART_Type *base, + flexio_uart_dma_handle_t *handle, + size_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_DMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c new file mode 100755 index 00000000000..8fc068f2d6a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_GPIO_COUNT); + + return instance; +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + GPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! +* @brief Gets the FGPIO instance according to the GPIO base +* +* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval FGPIO instance +*/ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT); + + return instance; +} + +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + FGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h new file mode 100755 index 00000000000..6eaaaa08744 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.1.0. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief GPIO direction definition*/ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused + * Note : In some cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig() + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin's number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low logic level. + * - 1: corresponding pin output high logic level. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin's number + * @retval GPIO port input value + * - 0: corresponding pin input low logic level. + * - 1: corresponding pin input high logic level. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name GPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads whole GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pins' interrupt status flag. + * + * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pins' numbers macro + */ +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); + +/*@}*/ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduce the FGPIO feature. + * + * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name FGPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO pin's number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low logic level. + * - 1: corresponding pin output high logic level. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name FGPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the whole FGPIO port. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param pin FGPIO pin's number + * @retval FGPIO port input value + * - 0: corresponding pin input low logic level. + * - 1: corresponding pin input high logic level. + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name FGPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads the whole FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pins' interrupt status flag. + * + * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) + * @param mask FGPIO pins' numbers macro + */ +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); + +/*@}*/ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c new file mode 100755 index 00000000000..e77a3832399 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c @@ -0,0 +1,1536 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ +/*! All flags which are cleared by the driver upon starting a transfer. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, +#else + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +#endif + +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; + +/*! @brief SCL clock divider used to calculate baudrate. */ +const uint16_t s_i2cDividerTable[] = {20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, + 48, 56, 68, 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, + 112, 128, 144, 160, 192, 240, 160, 192, 224, 256, 288, 320, 384, + 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768, 896, 1024, + 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +/*! @brief Pointers to i2c clocks for each instance. */ +const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_I2C_COUNT; instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_I2C_COUNT); + + return instance; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + uint16_t timeout = UINT16_MAX; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + else + { + handle->state = kCheckAddressState; + } + + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout)) + { + } + + /* Failed to start the transfer. */ + if (timeout == 0) + { + return kStatus_I2C_Timeout; + } + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->S; + *isDone = false; + volatile uint8_t dummy = 0; + bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + if (result) + { + return result; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == kCheckAddressState) + { + if (statusFlags & kI2C_ReceiveNakFlag) + { + return kStatus_I2C_Nak; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case kSendCommandState: + if (handle->transfer.subaddressSize) + { + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case kReceiveDataBeginState: + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Next state, receive data. */ + handle->state = kReceiveDataState; + break; + + /* Receive I2C data. */ + case kReceiveDataState: + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->D; + handle->transfer.data++; + } + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig && srcClock_Hz); + + /* Temporary register for filter read. */ + uint8_t fltReg; +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + uint8_t c2Reg; +#endif + + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); + + /* Disable I2C prior to configuring it. */ + base->C1 &= ~(I2C_C1_IICEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + /* Configure high drive feature. */ + c2Reg = base->C2; + c2Reg &= ~(I2C_C2_HDRS_MASK); + c2Reg |= I2C_C2_HDRS(masterConfig->enableHighDrive); + base->C2 = c2Reg; +#endif + + /* Read out the FLT register. */ + fltReg = base->FLT; + +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + /* Configure the stop / hold enable. */ + fltReg &= ~(I2C_FLT_SHEN_MASK); + fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); +#endif + + /* Configure the glitch filter value. */ + fltReg &= ~(I2C_FLT_FLT_MASK); + fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); + + /* Write the register value back to the filter register. */ + base->FLT = fltReg; + + /* Enable the I2C peripheral based on the configuration. */ + base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + +/* Default pin high drive is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + masterConfig->enableHighDrive = false; +#endif + +/* Default stop hold enable is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + masterConfig->enableStopHold = false; +#endif + + /* Default glitch filter value is no filter. */ + masterConfig->glitchFilterWidth = 0U; + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 |= I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT |= I2C_FLT_STOPIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT |= I2C_FLT_SSIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 &= ~I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT &= ~I2C_FLT_STOPIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT &= ~I2C_FLT_SSIE_MASK; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t multiplier; + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) + { + multiplier = 1u << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) + { + computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint8_t savedMult; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + uint8_t timeDelay = 6; + + /* Return an error if the bus is already in use, but not by us. */ + if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0)) + { + result = kStatus_I2C_Busy; + } + else + { + savedMult = base->F; + base->F = savedMult & (~I2C_F_MULT_MASK); + + /* We are already in a transfer, so send a repeated start. */ + base->C1 |= I2C_C1_RSTA_MASK; + + /* Restore the multiplier factor. */ + base->F = savedMult; + + /* Add some delay to wait the Re-Start signal. */ + while (timeDelay--) + { + __NOP(); + } + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + /* Issue the STOP command on the bus. */ + base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Wait until data transfer complete. */ + while ((base->S & kI2C_BusBusyFlag) && (--timeout)) + { + } + + if (timeout == 0) + { + result = kStatus_I2C_Timeout; + } + + return result; +} + +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + uint32_t statusFlags = base->S; + +#ifdef I2C_HAS_STOP_DETECT + /* Look up the STOPF bit from the filter register. */ + if (base->FLT & I2C_FLT_STOPF_MASK) + { + statusFlags |= kI2C_StopDetectFlag; + } +#endif + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Look up the STARTF bit from the filter register. */ + if (base->FLT & I2C_FLT_STARTF_MASK) + { + statusFlags |= kI2C_StartDetectFlag; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + return statusFlags; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->C1 |= I2C_C1_TX_MASK; + + while (txSize--) + { + /* Send a byte of data. */ + base->D = *txBuff++; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + statusFlags = base->S; + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (statusFlags & kI2C_ArbitrationLostFlag) + { + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if (statusFlags & kI2C_ReceiveNakFlag) + { + base->S = kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + return result; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = base->D; + + while ((rxSize--)) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0) + { + /* Read the final byte. */ + result = I2C_MasterStop(base); + } + + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = base->D; + } + + return result; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Wait until ready to complete. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + /* Return if error. */ + if (result) + { + return result; + } + + /* Send subaddress. */ + if (xfer->subaddressSize) + { + do + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + xfer->subaddressSize--; + base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); + + } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + + if (xfer->direction == kI2C_Read) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result) + { + return result; + } + } + } + + /* Wait until address + command transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + /* Transmit data. */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize); + + if (((result == kStatus_Success) && (!(xfer->flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + } + + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || result) + { + /* Send stop command if transfer done or received Nak. */ + if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->C1 & I2C_C1_MST_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + uint8_t tmpReg; + + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); + + /* Configure addressing mode. */ + switch (slaveConfig->addressingMode) + { + case kI2C_Address7bit: + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + break; + + case kI2C_RangeMatch: + assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U; + base->C2 |= I2C_C2_RMEN_MASK; + break; + + default: + break; + } + + /* Configure low power wake up feature. */ + tmpReg = base->C1; + tmpReg &= ~I2C_C1_WUEN_MASK; + base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); + + /* Configure general call & baud rate control & high drive feature. */ + tmpReg = base->C2; + tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); + tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + tmpReg &= ~I2C_C2_HDRS_MASK; + tmpReg |= I2C_C2_HDRS(slaveConfig->enableHighDrive); +#endif + base->C2 = tmpReg; +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* By default slave is addressed with 7-bit address. */ + slaveConfig->addressingMode = kI2C_Address7bit; + + /* General call mode is disabled by default. */ + slaveConfig->enableGeneralCall = false; + + /* Slave address match waking up MCU from low power mode is disabled. */ + slaveConfig->enableWakeUp = false; + +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + /* Default pin high drive is disabled. */ + slaveConfig->enableHighDrive = false; +#endif + + /* Independent slave mode baud rate at maximum frequency is disabled. */ + slaveConfig->enableBaudRateCtl = false; + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + return I2C_MasterWriteBlocking(base, txBuff, txSize); +} + +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Wait until the data register is ready for receive. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK); + + while (rxSize--) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->D; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + } +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->isBusy) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, kIrqFlags); + } + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle); + + if (handle->isBusy) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->isBusy = false; + } +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + +#ifdef I2C_HAS_STOP_DETECT + /* Check stop flag. */ + if (status & kI2C_StopDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Call slave callback if this is the STOP of the transfer. */ + if (handle->isBusy) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + return; + } +#endif /* I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + if (status & kI2C_StartDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + xfer->event = kI2C_SlaveRepeatedStartEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (!(status & kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check NAK */ + if (status & kI2C_ReceiveNakFlag) + { + /* Set receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy. */ + dummy = base->D; + + if (handle->transfer.dataSize != 0) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + /* Check address match. */ + else if (status & kI2C_AddressMatchFlag) + { + handle->isBusy = true; + xfer->event = kI2C_SlaveAddressMatchEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + /* Change direction to send data. */ + base->C1 |= I2C_C1_TX_MASK; + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + } + } + /* Check transfer complete flag. */ + else if (status & kI2C_TransferCompleteFlag) + { + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + uint8_t data = base->D; + + if (handle->transfer.dataSize) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + if (!handle->transfer.dataSize) + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed receive complete event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->D; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + if (handle->transfer.dataSize) + { + /* Send data. */ + base->D = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed txdone event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } +} + +void I2C0_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); +} + +#if (FSL_FEATURE_SOC_I2C_COUNT > 1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif /* I2C COUNT > 1 */ + +#if (FSL_FEATURE_SOC_I2C_COUNT > 2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif /* I2C COUNT > 2 */ +#if (FSL_FEATURE_SOC_I2C_COUNT > 3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif /* I2C COUNT > 3 */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h new file mode 100755 index 00000000000..41a9afbdd54 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h @@ -0,0 +1,781 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.0. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ + defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) +#define I2C_HAS_STOP_DETECT +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * - #kI2C_StartDetectFlag + * - #kI2C_StopDetectFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ + kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ +#ifdef I2C_HAS_STOP_DETECT + kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmit to slave. */ + kI2C_Read = 0x1U, /*!< Master receive from slave. */ +} i2c_direction_t; + +/*! @brief Addressing mode. */ +typedef enum _i2c_slave_address_mode +{ + kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ + kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ +} i2c_slave_address_mode_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< Transfer starts without a start signal. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< Transfer ends without a stop signal. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ +#endif + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveRepeatedStartEvent | +#endif + kI2C_SlaveCompletionEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */ +#endif +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + bool enableStopHold; /*!< Controls the stop hold enable. */ +#endif + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ + uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ +} i2c_master_config_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + bool enableGeneralCall; /*!< Enable general call addressing mode. */ + bool enableWakeUp; /*!< Enables/disables waking up MCU from low power mode. */ +#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION + bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */ +#endif + bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ + uint16_t slaveAddress; /*!< Slave address configuration. */ + uint16_t upperAddress; /*!< Maximum boundary slave address used in range matching mode. */ + i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */ +} i2c_slave_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t *volatile data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t *volatile data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + bool isBusy; /*!< Whether transfer is busy. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application to use + * the I2C driver, or any operation to the I2C module could cause hard fault + * because clock is not enabled. The configuration structure can be filled by user + * from scratch, or be set with default values by I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * Example: + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig pointer to master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initializes the I2C with slave configuration. + * + * @note This API should be called at the beginning of the application to use + * the I2C driver, or any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user. + * Example + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false + * }; + * I2C_SlaveInit(I2C0, &config); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig pointer to slave configuration structure + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of + * the structure before calling I2C_MasterConfigure(). + * Example: + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig Pointer to the master configuration structure. +*/ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * Example: + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig Pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disabless the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_IICEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_IICEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags could get the related status. + */ +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags could get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter could be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ +/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (statusMask & kI2C_StartDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + +#ifdef I2C_HAS_STOP_DETECT + if (statusMask & kI2C_StopDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + + base->S = (uint8_t)statusMask; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter could be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @name DMA Control + * @{ + */ +#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT +/*! + * @brief Enables/disables the I2C DMA interrupt. + * + * @param base I2C base pointer + * @param enable true to enable, false to disable +*/ +static inline void I2C_EnableDMA(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_DMAEN_MASK; + } +} + +#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ + +/*! + * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address + * for I2C DMA transfer configuration. + * + * @param base I2C base pointer + * @return data register address + */ +static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) +{ + return (uint32_t)(&(base->D)); +} + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus without a STOP signal. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus with a STOP signal. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user paramater passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API will return immediately after transfer initiates, user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished, if the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Sucessully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c new file mode 100755 index 00000000000..a5ee3e57457 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2c_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, false); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) + { + /* Change to send NAK at the last byte. */ + i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; + + /* Wait the last data to be received. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + + /* Read the last data byte. */ + *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = + i2cPrivateHandle->base->D; + } + else + { + /* Wait the last data to be sent. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + } + } + + i2cPrivateHandle->handle->state = kIdleState; + + if (i2cPrivateHandle->handle->completionCallback) + { + i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result, + i2cPrivateHandle->handle->userData); + } +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + /* Set up transfer first. */ + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + /* Init the handle member. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + handle->state = kTransferDataState; + + /* Wait until ready to complete. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout)) + { + } + + /* Failed to start the transfer. */ + if (timeout == 0) + { + return kStatus_I2C_Timeout; + } + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + /* Send subaddress. */ + if (handle->transfer.subaddressSize) + { + do + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + return result; + } + + } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success)); + + if (handle->transfer.direction == kI2C_Read) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + } + } + + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + } + + return result; +} + +static void I2C_MasterTransferDMAConfig(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + dma_transfer_config_t transfer_config; + dma_transfer_options_t transfer_options = kDMA_EnableInterrupt; + + if (handle->transfer.direction == kI2C_Read) + { + transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.destAddr = (uint32_t)(handle->transfer.data); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + transfer_config.transferSize = (handle->transfer.dataSize - 1); + } + else + { + transfer_config.transferSize = handle->transfer.dataSize; + } + + transfer_config.srcSize = kDMA_Transfersize8bits; + transfer_config.enableSrcIncrement = false; + transfer_config.destSize = kDMA_Transfersize8bits; + transfer_config.enableDestIncrement = true; + } + else + { + transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1); + transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.transferSize = (handle->transfer.dataSize - 1); + transfer_config.srcSize = kDMA_Transfersize8bits; + transfer_config.enableSrcIncrement = true; + transfer_config.destSize = kDMA_Transfersize8bits; + transfer_config.enableDestIncrement = false; + } + + DMA_SubmitTransfer(handle->dmaHandle, &transfer_config, transfer_options); + DMA_StartTransfer(handle->dmaHandle); +} + +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + assert(handle); + assert(dmaHandle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Set the handle for DMA. */ + handle->dmaHandle = dmaHandle; + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); +} + +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result; + uint8_t tmpReg; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable dma transfer. */ + I2C_EnableDMA(base, false); + + /* Send address and command buffer(if there is), until senddata phase or receive data phase. */ + result = I2C_InitTransferStateMachineDMA(base, handle, xfer); + + if (result != kStatus_Success) + { + /* Send stop if received Nak. */ + if (result == kStatus_I2C_Nak) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + + /* Reset the state to idle state. */ + handle->state = kIdleState; + + return result; + } + + /* Configure dma transfer. */ + /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read, + need to send stop before reading the last byte, so the dma transfer size should + be (xSize - 1). */ + if (handle->transfer.dataSize > 1) + { + I2C_MasterTransferDMAConfig(base, handle); + if (handle->transfer.direction == kI2C_Read) + { + /* Change direction for receive. */ + base->C1 &= ~I2C_C1_TX_MASK; + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + } + else + { + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + + /* Send the first data. */ + base->D = *handle->transfer.data; + } + } + else /* If transfer size is 1, use polling method. */ + { + if (handle->transfer.direction == kI2C_Read) + { + tmpReg = base->C1; + + /* Change direction to Rx. */ + tmpReg &= ~I2C_C1_TX_MASK; + + /* Configure send NAK */ + tmpReg |= I2C_C1_TXAK_MASK; + + base->C1 = tmpReg; + + /* Read dummy to release the bus. */ + dummy = base->D; + } + else + { + base->D = *handle->transfer.data; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + + /* Read the last byte of data. */ + if (handle->transfer.direction == kI2C_Read) + { + *handle->transfer.data = base->D; + } + + /* Reset the state to idle. */ + handle->state = kIdleState; + } + + return result; +} + +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kIdleState != handle->state) + { + *count = (handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + else + { + *count = handle->transferSize; + } + + return kStatus_Success; +} + +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable dma transfer. */ + I2C_EnableDMA(base, false); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h new file mode 100755 index 00000000000..321f79ec343 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dmamux.h" +#include "fsl_dma.h" + +/*! + * @addtogroup i2c_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief I2C master dma handle typedef. */ +typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; + +/*! @brief I2C master dma transfer callback typedef. */ +typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, + i2c_master_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master dma transfer structure. */ +struct _i2c_master_dma_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< I2C master transfer status. */ + dma_handle_t *dmaHandle; /*!< The DMA handler used. */ + i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block DMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transcational functions + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param callback pointer to user callback function + * @param userData user param passed to the callback function + * @param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Performs a master dma non-blocking transfer on the I2C bus + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param xfer pointer to transfer structure of i2c_master_transfer_t + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a dma non-blocking transfer + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master dma non-blocking transfer in a early time + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c new file mode 100755 index 00000000000..c27b91e9f04 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_llwu.h" + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + volatile uint32_t *regBase; + uint32_t regOffset; + uint32_t reg; + + switch (pinIndex >> 4U) + { + case 0U: + regBase = &base->PE1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 1U: + regBase = &base->PE2; + break; +#endif + default: + regBase = NULL; + break; + } +#else + volatile uint8_t *regBase; + uint8_t regOffset; + uint8_t reg; + switch (pinIndex >> 2U) + { + case 0U: + regBase = &base->PE1; + break; + case 1U: + regBase = &base->PE2; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 2U: + regBase = &base->PE3; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) + case 3U: + regBase = &base->PE4; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 4U: + regBase = &base->PE5; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) + case 5U: + regBase = &base->PE6; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 6U: + regBase = &base->PE7; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) + case 7U: + regBase = &base->PE8; + break; +#endif + default: + regBase = NULL; + break; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ + + if (regBase) + { + reg = *regBase; +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + regOffset = ((pinIndex & 0x0FU) << 1U); +#else + regOffset = ((pinIndex & 0x03U) << 1U); +#endif + reg &= ~(0x3U << regOffset); + reg |= ((uint32_t)pinMode << regOffset); + *regBase = reg; + } +} + +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->PF & (1U << pinIndex)); +#else + volatile uint8_t *regBase; + + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + return (bool)(*regBase & (1U << pinIndex % 8)); + } + else + { + return false; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + base->PF = (1U << pinIndex); +#else + volatile uint8_t *regBase; + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + if (regBase) + { + *regBase = (1U << pinIndex % 8U); + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); + reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) + /* Clear the Filter Detect Flag */ + | LLWU_FILT_FILTF1_MASK) + << (filterIndex * 8U - 1U)); + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); + reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); + reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); + /* Clear the Filter Detect Flag */ + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); +#else + bool status = false; + + switch (filterIndex) + { + case 1: + status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + break; + } + + return status; +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + switch (filterIndex) + { + case 1: + reg |= LLWU_FILT_FILTF1_MASK; + break; + case 2: + reg |= LLWU_FILT_FILTF2_MASK; + break; + case 3: + reg |= LLWU_FILT_FILTF3_MASK; + break; + case 4: + reg |= LLWU_FILT_FILTF4_MASK; + break; + default: + break; + } + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) +{ + uint8_t reg; + + reg = base->RST; + reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); + reg |= + (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); + base->RST = reg; +} +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h new file mode 100755 index 00000000000..7c11572e806 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LLWU_H_ +#define _FSL_LLWU_H_ + +#include "fsl_common.h" + +/*! @addtogroup llwu */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LLWU driver version 2.0.1. */ +#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief External input pin control modes + */ +typedef enum _llwu_external_pin_mode +{ + kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as wakeup input. */ + kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with rising edge detection. */ + kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/ + kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ +} llwu_external_pin_mode_t; + +/*! + * @brief Digital filter control modes + */ +typedef enum _llwu_pin_filter_mode +{ + kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ + kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ + kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ + kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ +} llwu_pin_filter_mode_t; + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _llwu_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} llwu_version_id_t; +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _llwu_param +{ + uint8_t filters; /*!< Number of pin filter. */ + uint8_t dmas; /*!< Number of wakeup DMA. */ + uint8_t modules; /*!< Number of wakeup module. */ + uint8_t pins; /*!< Number of wake up pin. */ +} llwu_param_t; +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief External input pin filter control structure + */ +typedef struct _llwu_external_pin_filter_mode +{ + uint32_t pinIndex; /*!< Pin number */ + llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ +} llwu_external_pin_filter_mode_t; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Low-Leakage Wakeup Unit Control APIs + * @{ + */ + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief Gets the LLWU version ID. + * + * This function gets the LLWU version ID, including major version number, + * minor version number, and feature specification number. + * + * @param base LLWU peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief Gets the LLWU parameter. + * + * This function gets the LLWU parameter, including wakeup pin number, module + * number, DMA number, and pin filter number. + * + * @param base LLWU peripheral base address. + * @param param Pointer to LLWU param structure. + */ +static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) +{ + *((uint32_t *)param) = base->PARAM; +} +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * @brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index which to be enabled as external wakeup source, start from 1. + * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t + */ +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woke up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index, start from 1. + * @return true if the specific pin is wake up source. + */ +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); + +/*! + * @brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex pin index, start from 1. + */ +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) +/*! + * @brief Enables/disables the internal module source. + * + * This function enables/disables the internal module source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex module index which to be enabled as internal wakeup source, start from 1. + * @param enable enable or disable setting + */ +static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->ME |= 1U << moduleIndex; + } + else + { + base->ME &= ~(1U << moduleIndex); + } +} + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the system is + * woke up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param moduleIndex module index, start from 1. + * @return true if the specific pin is wake up source. + */ +static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->MF & (1U << moduleIndex)); +#else +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->MF5 & (1U << moduleIndex)); +#else + return (bool)(base->F5 & (1U << moduleIndex)); +#endif /* FSL_FEATURE_LLWU_HAS_PF */ +#else +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->PF3 & (1U << moduleIndex)); +#else + return (bool)(base->F3 & (1U << moduleIndex)); +#endif +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ + +#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) +/*! + * @brief Enables/disables the internal module DMA wakeup source. + * + * This function enables/disables the internal DMA that is used as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex Internal module index which used as DMA request source, start from 1. + * @param enable Enable or disable DMA request source + */ +static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->DE |= 1U << moduleIndex; + } + else + { + base->DE &= ~(1U << moduleIndex); + } +} +#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1. + * @param filterMode filter mode configuration + */ +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index, start from 1. + * @return true if the flag is a source of existing a low-leakage power mode. + */ +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +/*! + * @brief Clear the pin filter configuration. + * + * This function clear the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex pin filter index which to be clear the flag, start from 1. + */ +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +/*! + * @brief Sets the reset pin mode. + * + * This function sets how the reset pin is used as a low leakage mode exit source. + * + * @param pinEnable Enable reset pin filter + * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif /* _FSL_LLWU_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c new file mode 100755 index 00000000000..b3dcc89d55d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lptmr.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base LPTMR peripheral base address + * + * @return The LPTMR instance + */ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPTMR bases for each instance. */ +static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; + +/*! @brief Pointers to LPTMR clocks for each instance. */ +static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++) + { + if (s_lptmrBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT); + + return instance; +} + +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) +{ + assert(config); + + /* Ungate the LPTMR clock*/ + CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); + + /* Configure the timers operation mode and input pin setup */ + base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); + + /* Configure the prescale value and clock source */ + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + LPTMR_PSR_PCS(config->prescalerClockSource)); +} + +void LPTMR_Deinit(LPTMR_Type *base) +{ + /* Disable the LPTMR and reset the internal logic */ + base->CSR &= ~LPTMR_CSR_TEN_MASK; + /* Gate the LPTMR clock*/ + CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); +} + +void LPTMR_GetDefaultConfig(lptmr_config_t *config) +{ + assert(config); + + /* Use time counter mode */ + config->timerMode = kLPTMR_TimerModeTimeCounter; + /* Use input 0 as source in pulse counter mode */ + config->pinSelect = kLPTMR_PinSelectInput_0; + /* Pulse input pin polarity is active-high */ + config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + /* Counter resets whenever TCF flag is set */ + config->enableFreeRunning = false; + /* Bypass the prescaler */ + config->bypassPrescaler = true; + /* LPTMR clock source */ + config->prescalerClockSource = kLPTMR_PrescalerClock_1; + /* Divide the prescaler clock by 2 */ + config->value = kLPTMR_Prescale_Glitch_0; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h new file mode 100755 index 00000000000..fd3cb1ed242 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPTMR_H_ +#define _FSL_LPTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lptmr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief LPTMR pin selection, used in pulse counter mode.*/ +typedef enum _lptmr_pin_select +{ + kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ + kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ + kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ + kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity, used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity +{ + kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ + kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode +{ + kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ + kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler/glitch filter values*/ +typedef enum _lptmr_prescaler_glitch_value +{ + kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ + kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ + kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ + kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ + kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ + kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ + kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ + kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ + kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ + kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ + kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ + kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ + kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ + kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ + kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ + kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ +} lptmr_prescaler_glitch_value_t; + +/*! + * @brief LPTMR prescaler/glitch filter clock select. + * @note Clock connections are SoC-specific + */ +typedef enum _lptmr_prescaler_clock_select +{ + kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ + kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ + kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ + kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +} lptmr_prescaler_clock_select_t; + +/*! @brief List of LPTMR interrupts */ +typedef enum _lptmr_interrupt_enable +{ + kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ +} lptmr_interrupt_enable_t; + +/*! @brief List of LPTMR status flags */ +typedef enum _lptmr_status_flags +{ + kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ +} lptmr_status_flags_t; + +/*! + * @brief LPTMR config structure + * + * This structure holds the configuration settings for the LPTMR peripheral. To initialize this + * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _lptmr_config +{ + lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ + lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ + lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ + bool enableFreeRunning; /*!< true: enable free running, counter is reset on overflow + false: counter is reset when the compare flag is set */ + bool bypassPrescaler; /*!< true: bypass prescaler; false: use clock from prescaler */ + lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ + lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ +} lptmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungate the LPTMR clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the LPTMR driver. + * + * @param base LPTMR peripheral base address + * @param config Pointer to user's LPTMR config structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); + +/*! + * @brief Gate the LPTMR clock + * + * @param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base); + +/*! + * @brief Fill in the LPTMR config struct with the default settings + * + * The default values are: + * @code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * @endcode + * @param config Pointer to user's LPTMR config structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! + * @brief Disables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + base->CSR &= ~mask; +} + +/*! + * @brief Gets the enabled LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPTMR status flags + * + * @param base LPTMR peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TCF_MASK); +} + +/*! + * @brief Clears the LPTMR status flags + * + * @param base LPTMR peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers counts from 0 till it equals the count value set here. The count value is written to + * the CMR register. + * + * @note + * 1. The TCF flag is set with the CNR equals the count provided here and then increments. + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base LPTMR peripheral base address + * @param ticks Timer period in units of ticks + */ +static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks) +{ + base->CMR = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base LPTMR peripheral base address + * + * @return Current counter value in ticks + */ +static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) +{ + /* Must first write any value to the CNR. This will synchronize and register the current value + * of the CNR into a temporary register which can then be read + */ + base->CNR = 0U; + return (uint16_t)base->CNR; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, the timer counts up to the CMR register value. + * Each time the timer reaches CMR value and then increments, it generates a + * trigger pulse and sets the timeout interrupt flag. An interrupt will also be + * triggered if the timer interrupt is enabled. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StartTimer(LPTMR_Type *base) +{ + base->CSR |= LPTMR_CSR_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer counting and resets the timer's counter register + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StopTimer(LPTMR_Type *base) +{ + base->CSR &= ~LPTMR_CSR_TEN_MASK; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPTMR_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c new file mode 100755 index 00000000000..b1b015f6f49 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lpuart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* LPUART transfer state. */ +enum _lpuart_transfer_states +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @userData handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART handle. */ +static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT]; +/* Array of LPUART peripheral base address. */ +static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; +/* Array of LPUART IRQ number. */ +static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; +/* Array of LPUART clock name. */ +static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; +/* LPUART ISR for transactional APIs. */ +static lpuart_isr_t s_lpuartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++) + { + if (s_lpuartBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_LPUART_COUNT); + + return instance; +} + +static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = base->DATA; + } +} + +void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + uint32_t temp; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* Enable lpuart clock */ + CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]); + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4; osrTemp <= 32; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0) + { + sbrTemp = 1; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - config->baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + { + tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < ((config->baudRate_Bps / 100) * 3)) + { + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3) && (osr < 8)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + } + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); + + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= (LPUART_CTRL_M_MASK | (uint8_t)config->parityMode); + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_IDLE_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; +} +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_IDLE_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0; + + /* Disable lpuart clock */ + CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]); +} + +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(config); + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 0; +#endif + config->enableTx = false; + config->enableRx = false; +} + +void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4; osrTemp <= 32; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0) + { + sbrTemp = 1; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + { + tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < ((baudRate_Bps / 100) * 3)) + { + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3) && (osr < 8)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + } + + /* Restore CTRL. */ + base->CTRL = oldCtrl; +} + +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO |= ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL |= mask; +} + +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO &= ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL &= ~mask; +} + +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + uint32_t temp; + temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; +#endif + temp |= (base->CTRL & 0xFF0C000); + + return temp; +} + +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16; +#endif + return temp; +} + +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag)); + temp |= mask & (kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag); + base->FIFO = temp; +#endif + temp = (uint32_t)base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp &= (uint32_t)(~(kLPUART_LinBreakFlag)); + temp |= mask & kLPUART_LinBreakFlag; +#endif + temp &= (uint32_t)(~(kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | + kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag)); + temp |= mask & (kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_NoiseErrorFlag | + kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag); +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp &= (uint32_t)(~(kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag)); + temp |= mask & (kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag); +#endif + base->STAT |= temp; + /* If some flags still pending. */ + if (mask & LPUART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, + kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, + kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ + status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ + } + else + { + status = kStatus_Success; + } + + return status; +} + +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->STAT & LPUART_STAT_TDRE_MASK)) + { + } + base->DATA = *(data++); + } +} + +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + + while (length--) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (!(base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { + statusFlag = LPUART_GetStatusFlags(base); + + if (statusFlag & kLPUART_RxOverrunFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); + return kStatus_LPUART_RxHardwareOverrun; + } + + if (statusFlag & kLPUART_NoiseErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); + return kStatus_LPUART_NoiseError; + } + + if (statusFlag & kLPUART_FramingErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); + return kStatus_LPUART_FramingError; + } + + if (statusFlag & kLPUART_ParityErrorFlag) + { + LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); + return kStatus_LPUART_ParityError; + } + } + *(data++) = base->DATA; + } + + return kStatus_Success; +} + +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = kLPUART_RxIdle; + handle->txState = kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER &= (~LPUART_WATER_RXWATER_SHIFT); +#endif + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr = LPUART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_lpuartIRQ[instance]); +} + +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ring buffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } +} + +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kLPUART_RxIdle) + { + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kLPUART_TxBusy; + + /* Enable transmiter interrupt. */ + LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kLPUART_TxIdle; +} + +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + if (kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kLPUART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kLPUART_RxBusy; + + /* Enable RX interrupt. */ + LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kLPUART_RxIdle; +} + +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + if (kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + volatile uint8_t dummy; + + assert(handle); + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & base->STAT) + { + /* Read base->DATA, otherwise the RX does not work. */ + dummy = base->DATA; + /* Avoid optimization */ + dummy++; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kLPUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kLPUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } + } + } +} + +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* TODO: To be implemented. */ +} + +#if defined(LPUART0) +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +} +void LPUART0_RX_TX_DriverIRQHandler(void) +{ + LPUART0_DriverIRQHandler(); +} +#endif + +#if defined(LPUART1) +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +} +void LPUART1_RX_TX_DriverIRQHandler(void) +{ + LPUART1_DriverIRQHandler(); +} +#endif + +#if defined(LPUART2) +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +} +void LPUART2_RX_TX_DriverIRQHandler(void) +{ + LPUART2_DriverIRQHandler(); +} +#endif + +#if defined(LPUART3) +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +} +void LPUART3_RX_TX_DriverIRQHandler(void) +{ + LPUART3_DriverIRQHandler(); +} +#endif + +#if defined(LPUART4) +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +} +void LPUART4_RX_TX_DriverIRQHandler(void) +{ + LPUART4_DriverIRQHandler(); +} +#endif + +#if defined(LPUART5) +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +} +void LPUART5_RX_TX_DriverIRQHandler(void) +{ + LPUART5_DriverIRQHandler(); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h new file mode 100755 index 00000000000..a357400b56a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version 2.1.0. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Error codes for the LPUART driver. */ +enum _lpuart_status +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char + detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configure structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! +* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. +* +* This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function +* to configure the configuration structure and get the default configuration. +* The example below shows how to use this API to configure the LPUART. +* @code +* lpuart_config_t lpuartConfig; +* lpuartConfig.baudRate_Bps = 115200U; +* lpuartConfig.parityMode = kLPUART_ParityDisabled; +* lpuartConfig.stopBitCount = kLPUART_OneStopBit; +* lpuartConfig.txFifoWatermark = 0; +* lpuartConfig.rxFifoWatermark = 1; +* LPUART_Init(LPUART1, &lpuartConfig, 20000000U); +* @endcode +* +* @param base LPUART peripheral base address. +* @param config Pointer to a user-defined configuration structure. +* @param srcClock_Hz LPUART clock source frequency in HZ. +*/ +void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + */ +void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + base->CTRL |= LPUART_CTRL_TIE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + base->CTRL &= ~LPUART_CTRL_TIE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + base->CTRL |= LPUART_CTRL_RIE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + base->CTRL &= ~LPUART_CTRL_RIE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the RX register. + * + * This function reads data from the TX register directly. The upper layer must + * ensure that the RX register is full or that the TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ + return base->DATA; +} + +/*! + * @brief Writes to transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room and then writes data to the transmitter buffer. + * + * @note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! +* @brief Reads the RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register full or RX FIFO + * has data then reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, refer to #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Abort the background transfer and uninstall the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, refer to #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c new file mode 100755 index 00000000000..f92e2ff204d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_lpuart_dma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(lpuartPrivateHandle->handle->txDmaHandle->base, + lpuartPrivateHandle->handle->txDmaHandle->channel); + + lpuartPrivateHandle->handle->txState = kLPUART_TxIdle; + + if (lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); + } +} + +static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param) +{ + lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param; + + /* Disable LPUART RX DMA. */ + LPUART_EnableRxDMA(lpuartPrivateHandle->base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(lpuartPrivateHandle->handle->rxDmaHandle->base, + lpuartPrivateHandle->handle->rxDmaHandle->channel); + + lpuartPrivateHandle->handle->rxState = kLPUART_RxIdle; + + if (lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } +} + +void LPUART_TransferCreateHandleDMA(LPUART_Type *base, + lpuart_dma_handle_t *handle, + lpuart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + assert(handle); + + uint32_t instance = LPUART_GetInstance(base); + + memset(handle, 0, sizeof(lpuart_dma_handle_t)); + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + handle->rxState = kLPUART_RxIdle; + handle->txState = kLPUART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, DMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + DMA transfer because the water mark is 2. + */ + if (rxDmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Configure TX. */ + if (txDmaHandle) + { + DMA_SetCallback(txDmaHandle, LPUART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle) + { + DMA_SetCallback(rxDmaHandle, LPUART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } +} + +status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle->txDmaHandle); + + status_t status; + dma_transfer_config_t xferConfig; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), + sizeof(uint8_t), xfer->dataSize, kDMA_MemoryToPeripheral); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, kDMA_EnableInterrupt); + DMA_StartTransfer(handle->txDmaHandle); + + /* Enable LPUART TX DMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle->rxDmaHandle); + + status_t status; + dma_transfer_config_t xferConfig; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), xfer->dataSize, kDMA_PeripheralToMemory); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, kDMA_EnableInterrupt); + DMA_StartTransfer(handle->rxDmaHandle); + + /* Enable LPUART RX DMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle) +{ + assert(handle->txDmaHandle); + + /* Disable LPUART TX DMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag); + + handle->txState = kLPUART_TxIdle; +} + +void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle) +{ + assert(handle->rxDmaHandle); + + /* Disable LPUART RX DMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag); + + handle->rxState = kLPUART_RxIdle; +} + +status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle->txDmaHandle); + + if (kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle->rxDmaHandle); + + if (kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h new file mode 100755 index 00000000000..c592d17ea34 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPUART_DMA_H_ +#define _FSL_LPUART_DMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_dma.h" + +/*! + * @addtogroup lpuart_dma_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_dma_handle lpuart_dma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_dma_transfer_callback_t)(LPUART_Type *base, + lpuart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief LPUART DMA handle +*/ +struct _lpuart_dma_handle +{ + lpuart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleDMA(LPUART_Type *base, + lpuart_dma_handle_t *handle, + lpuart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_dma_handle_t structure. + * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base LPUART peripheral base address + * @param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base LPUART peripheral base address + * @param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_DMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c new file mode 100755 index 00000000000..1f2fdfe8b45 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pit.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base PIT peripheral base address + * + * @return The PIT instance + */ +static uint32_t PIT_GetInstance(PIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PIT bases for each instance. */ +static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; + +/*! @brief Pointers to PIT clocks for each instance. */ +static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PIT_GetInstance(PIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++) + { + if (s_pitBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_PIT_COUNT); + + return instance; +} + +void PIT_Init(PIT_Type *base, const pit_config_t *config) +{ + assert(config); + + /* Ungate the PIT clock*/ + CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); + + /* Enable PIT timers */ + base->MCR &= ~PIT_MCR_MDIS_MASK; + + /* Config timer operation when in debug mode */ + if (config->enableRunInDebug) + { + base->MCR &= ~PIT_MCR_FRZ_MASK; + } + else + { + base->MCR |= PIT_MCR_FRZ_MASK; + } +} + +void PIT_Deinit(PIT_Type *base) +{ + /* Disable PIT timers */ + base->MCR |= PIT_MCR_MDIS_MASK; + + /* Gate the PIT clock*/ + CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); +} + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) +{ + uint32_t valueH = 0U; + uint32_t valueL = 0U; + + /* LTMR64H should be read before LTMR64L */ + valueH = base->LTMR64H; + valueL = base->LTMR64L; + + return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); +} + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h new file mode 100755 index 00000000000..61606e7e8bd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PIT_H_ +#define _FSL_PIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pit_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of PIT channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pit_chnl +{ + kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ + kPIT_Chnl_1, /*!< PIT channel number 1 */ + kPIT_Chnl_2, /*!< PIT channel number 2 */ + kPIT_Chnl_3, /*!< PIT channel number 3 */ +} pit_chnl_t; + +/*! @brief List of PIT interrupts */ +typedef enum _pit_interrupt_enable +{ + kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ +} pit_interrupt_enable_t; + +/*! @brief List of PIT status flags */ +typedef enum _pit_status_flags +{ + kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ +} pit_status_flags_t; + +/*! + * @brief PIT config structure + * + * This structure holds the configuration settings for the PIT peripheral. To initialize this + * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ +} pit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PIT driver. + * + * @param base PIT peripheral base address + * @param config Pointer to user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config); + +/*! + * @brief Gate the PIT clock and disable the PIT module + * + * @param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base); + +/*! + * @brief Fill in the PIT config struct with the default settings + * + * The default values are: + * @code + * config->enableRunInDebug = false; + * @endcode + * @param config Pointer to user's PIT config structure. + */ +static inline void PIT_GetDefaultConfig(pit_config_t *config) +{ + assert(config); + + /* Timers are stopped in Debug mode */ + config->enableRunInDebug = false; +} + +#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE + +/*! + * @brief Enables or disables chaining a timer with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. Each timer is 32-bits, this allows the developers + * to chain timers together and form a longer timer (64-bits and larger). The first timer + * (timer 0) cannot be chained to any other timer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number which is chained with the previous timer + * @param enable Enable or disable chain. + * true: Current timer is chained with the previous timer. + * false: Timer doesn't chain with other timers. + */ +static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; + } + else + { + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; + } +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL &= ~mask; +} + +/*! + * @brief Gets the enabled PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PIT status flags + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); +} + +/*! + * @brief Clears the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TFLG = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function until it reaches 0, + * then it will generate an interrupt and load this regiter value again. + * Writing a new value to this register will not restart the timer; instead the value + * will be loaded after the timer expires. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + */ +static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) +{ + base->CHANNEL[channel].LDVAL = count; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, count down to 0 and + * then load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops every timer counting. Timers reload their periods + * respectively after the next time they call the PIT_DRV_StartTimer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * @param base PIT peripheral base address + * + * @return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PIT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c new file mode 100755 index 00000000000..82d7b7ace13 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_pmc.h" + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +void PMC_GetParam(PMC_Type *base, pmc_param_t *param) +{ + uint32_t reg = base->PARAM; + ; + param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); + param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) +{ + base->LVDSC1 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) + /* Clear the Low Voltage Detect Flag with previouse power detect setting */ + | PMC_LVDSC1_LVDACK_MASK); +} + +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) +{ + base->LVDSC2 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) + /* Clear the Low Voltage Warning Flag with previouse power detect setting */ + | PMC_LVDSC2_LVWACK_MASK); +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) +{ + base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | + ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) + /* Clear the High Voltage Detect Flag with previouse power detect setting */ + | PMC_HVDSC1_HVDACK_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) +{ + base->REGSC = (0U +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBE */ +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + ); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h new file mode 100755 index 00000000000..c60c19c01e9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PMC_H_ +#define _FSL_PMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmc */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMC driver version */ +#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) +/*! + * @brief Low-Voltage Detect Voltage Select + */ +typedef enum _pmc_low_volt_detect_volt_select +{ + kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/ + kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/ +} pmc_low_volt_detect_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) +/*! + * @brief Low-Voltage Warning Voltage Select + */ +typedef enum _pmc_low_volt_warning_volt_select +{ + kPMC_LowVoltWarningLowTrip = 0U, /*!< Low trip point selected (VLVW = VLVW1)*/ + kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ + kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ + kPMC_LowVoltWarningHighTrip = 3U /*!< High trip point selected (VLVW = VLVW4)*/ +} pmc_low_volt_warning_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-Voltage Detect Voltage Select + */ +typedef enum _pmc_high_volt_detect_volt_select +{ + kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/ + kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/ +} pmc_high_volt_detect_volt_select_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) +/*! + * @brief Bandgap Buffer Drive Select. + */ +typedef enum _pmc_bandgap_buffer_drive_select +{ + kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive. */ + kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */ +} pmc_bandgap_buffer_drive_select_t; +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + +#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) +/*! + * @brief VLPx Option + */ +typedef enum _pmc_vlp_freq_option +{ + kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ + kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ +} pmc_vlp_freq_mode_t; +#endif /* FSL_FEATURE_PMC_HAS_VLPO */ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + @brief IP version ID definition. + */ +typedef struct _pmc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} pmc_version_id_t; +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! @brief IP parameter definition. */ +typedef struct _pmc_param +{ + bool vlpoEnable; /*!< VLPO enable. */ + bool hvdEnable; /*!< HVD enable. */ +} pmc_param_t; +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +/*! + * @brief Low-Voltage Detect Configuration Structure + */ +typedef struct _pmc_low_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when low voltage detect*/ + bool enableReset; /*!< Enable system reset when low voltage detect*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low voltage detect trip point voltage selection*/ +#endif +} pmc_low_volt_detect_config_t; + +/*! + * @brief Low-Voltage Warning Configuration Structure + */ +typedef struct _pmc_low_volt_warning_config +{ + bool enableInt; /*!< Enable interrupt when low voltage warning*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low voltage warning trip point voltage selection*/ +#endif +} pmc_low_volt_warning_config_t; + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-Voltage Detect Configuration Structure + */ +typedef struct _pmc_high_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when high voltage detect*/ + bool enableReset; /*!< Enable system reset when high voltage detect*/ + pmc_high_volt_detect_volt_select_t voltSelect; /*!< High voltage detect trip point voltage selection*/ +} pmc_high_volt_detect_config_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Bandgap Buffer configuration. + */ +typedef struct _pmc_bandgap_buffer_config +{ +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + bool enable; /*!< Enable bandgap buffer. */ +#endif +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + bool enableInLowPowerMode; /*!< Enable bandgap buffer in low power mode. */ +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ +} pmc_bandgap_buffer_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Power Management Controller Control APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + * @brief Gets the PMC version ID. + * + * This function gets the PMC version ID, including major version number, + * minor version number and feature specification number. + * + * @param base PMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * @brief Gets the PMC parameter. + * + * This function gets the PMC parameter, including VLPO enable and HVD enable. + * + * @param base PMC peripheral base address. + * @param param Pointer to PMC param structure. + */ +void PMC_GetParam(PMC_Type *base, pmc_param_t *param); +#endif + +/*! + * @brief Configure the low voltage detect setting. + * + * This function configures the low voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable system reset or not. + * + * @param base PMC peripheral base address. + * @param config Low-Voltage detect configuration structure. + */ +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); + +/*! + * @brief Get Low-Voltage Detect Flag status + * + * This function reads the current LVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current low voltage detect flag + * - true: Low-Voltage detected + * - false: Low-Voltage not detected + */ +static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK); +} + +/*! + * @brief Acknowledge to clear the Low-Voltage Detect flag + * + * This function acknowledges the low voltage detection errors (write 1 to + * clear LVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) +{ + base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; +} + +/*! + * @brief Configure the low voltage warning setting. + * + * This function configures the low voltage warning setting, including the trip + * point voltage setting and enable interrupt or not. + * + * @param base PMC peripheral base address. + * @param config Low-Voltage warning configuration structure. + */ +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); + +/*! + * @brief Get Low-Voltage Warning Flag status + * + * This function polls the current LVWF status. When 1 is returned, it + * indicates a low-voltage warning event. LVWF is set when V Supply transitions + * below the trip point or after reset and V Supply is already below the V LVW. + * + * @param base PMC peripheral base address. + * @return Current LVWF status + * - true: Low-Voltage Warning Flag is set. + * - false: the Low-Voltage Warning does not happen. + */ +static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK); +} + +/*! + * @brief Acknowledge to Low-Voltage Warning flag + * + * This function acknowledges the low voltage warning errors (write 1 to + * clear LVWF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) +{ + base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief Configure the high voltage detect setting. + * + * This function configures the high voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable system reset or not. + * + * @param base PMC peripheral base address. + * @param config High-Voltage detect configuration structure. + */ +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); + +/*! + * @brief Get High-Voltage Detect Flag status + * + * This function reads the current HVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current high voltage detect flag + * - true: High-Voltage detected + * - false: High-Voltage not detected + */ +static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); +} + +/*! + * @brief Acknowledge to clear the High-Voltage Detect flag + * + * This function acknowledges the high voltage detection errors (write 1 to + * clear HVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) +{ + base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Configure the PMC bandgap + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low power mode. + * + * @param base PMC peripheral base address. + * @param config Pointer to the configuration structure + */ +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) +/*! + * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. + * + * This function reads the Acknowledge Isolation setting that indicates + * whether certain peripherals and the I/O pads are in a latched state as + * a result of having been in the VLLS mode. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return ACK isolation + * 0 - Peripherals and I/O pads are in a normal run state. + * 1 - Certain peripherals and I/O pads are in an isolated and + * latched state. + */ +static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK); +} + +/*! + * @brief Acknowledge to Peripherals and I/O pads isolation flag. + * + * This function clears the ACK Isolation flag. Writing one to this setting + * when it is set releases the I/O pads and certain peripherals to their normal + * run mode state. + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) +{ + base->REGSC |= PMC_REGSC_ACKISO_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ + +#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) +/*! + * @brief Gets the Regulator regulation status. + * + * This function returns the regulator to a run regulation status. It provides + * the current status of the internal voltage regulator. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return Regulation status + * 0 - Regulator is in a stop regulation or in transition to/from the regulation. + * 1 - Regulator is in a run regulation. + * + */ +static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_REGONS */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMC_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h new file mode 100755 index 00000000000..790518ccd3c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PORT_H_ +#define _FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! Version 2.0.1. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */ +}; + +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */ +}; + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Internal resistor pull feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */ + kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */ +}; + +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */ +}; + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ + kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */ + kPORT_MuxAlt2 = 2U, /*!< chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< chip-specific */ +} port_mux_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */ +#endif +} port_interrupt_t; + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*! @brief PORT pin config structure */ +typedef struct _port_pin_config +{ + uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */ + uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */ + uint16_t : 1; + uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */ +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */ + uint16_t : 1; + uint16_t mux : 3; /*!< pin mux Configure */ + uint16_t : 4; +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration: + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configure structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration: + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + * @param config PORT PCR register configure structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)config); + + if (mask & 0xffffU) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (mask >> 16) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will + * be reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use in the case you just need to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*@}*/ + +/*! @name Interrupt */ +/*@{*/ + +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} + +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pins' interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pins' numbers macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PORT_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c new file mode 100755 index 00000000000..538f6872a3a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rcm.h" + +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + uint32_t reg; + + reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); + } + base->RPC = reg; +#else + base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + base->RPFW = config->busClockFilterCount; + } +#endif /* FSL_FEATURE_RCM_REG_WIDTH */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) +{ + uint32_t reg; + + reg = base->FM; + reg &= ~RCM_FM_FORCEROM_MASK; + reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); + base->FM = reg; +} +#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h new file mode 100755 index 00000000000..81e25559eaf --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RCM_H_ +#define _FSL_RCM_H_ + +#include "fsl_common.h" + +/*! @addtogroup rcm */ +/*! @{*/ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RCM driver version 2.0.0. */ +#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief System Reset Source Name definitions + */ +typedef enum _rcm_reset_source +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) +/* RCM register bit width is 32. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ + +#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +/* RCM register bit width is 8. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ + kRCM_SourceAll = 0xffffffffU, +} rcm_reset_source_t; + +/*! + * @brief Reset pin filter select in Run and Wait modes + */ +typedef enum _rcm_run_wait_filter_mode +{ + kRCM_FilterDisable = 0U, /*!< All filtering disabled */ + kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ + kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ +} rcm_run_wait_filter_mode_t; + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Boot from ROM configuration. + */ +typedef enum _rcm_boot_rom_config +{ + kRCM_BootFlash = 0U, /*!< Boot from flash */ + kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ + kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ + kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ +} rcm_boot_rom_config_t; +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Max delay time from interrupt asserts to system reset. + */ +typedef enum _rcm_reset_delay +{ + kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ + kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ + kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ + kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ +} rcm_reset_delay_t; + +/*! + * @brief System reset interrupt enable bit definitions. + */ +typedef enum _rcm_interrupt_enable +{ + kRCM_IntNone = 0U, /*!< No interrupt enabled. */ + kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ + kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ + kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ + kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ + kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ + kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ + kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ + kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ +#endif + kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ + | + RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | + RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + | + RCM_SRIE_CORE1_MASK +#endif +} rcm_interrupt_enable_t; +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _rcm_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} rcm_version_id_t; +#endif + +/*! + * @brief Reset pin filter configuration + */ +typedef struct _rcm_reset_pin_filter_config +{ + bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ + rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ + uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ +} rcm_reset_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Reset Control Module APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief Gets the RCM version ID. + * + * This function gets the RCM version ID including the major version number, + * the minor version number, and the feature specification number. + * + * @param base RCM peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif + +#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) +/*! + * @brief Gets the reset source implemented status. + * + * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. + * Use source masks defined in the rcm_reset_source_t to get the desired source status. + * + * Example: + @code + uint32_t status; + + // To test whether the MCU is reset using Watchdog. + status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source implemented status bit map. + */ +static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) +{ + return base->PARAM; +} +#endif /* FSL_FEATURE_RCM_HAS_PARAM */ + +/*! + * @brief Gets the reset source status which caused a previous reset. + * + * This function gets the current reset source status. Use source masks + * defined in the rcm_reset_source_t to get the desired source status. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SRS; +#else + return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) +/*! + * @brief Gets the sticky reset source status. + * + * This function gets the current reset source status that has not been cleared + * by software for some specific source. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SSRS; +#else + return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +/*! + * @brief Clears the sticky reset source status. + * + * This function clears the sticky system reset flags indicated by source masks. + * + * Example: + @code + // Clears multiple reset sources. + RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @param sourceMasks reset source status bit map + */ +static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + base->SSRS = sourceMasks; +#else + base->SSRS0 = (sourceMasks & 0xffU); + base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} +#endif /* FSL_FEATURE_RCM_HAS_SSRS */ + +/*! + * @brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * @param base RCM peripheral base address. + * @param config Pointer to the configuration structure. + */ +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); + +#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) +/*! + * @brief Gets the EZP_MS_B pin assert status. + * + * This function gets the easy port mode status (EZP_MS_B) pin assert status. + * + * @param base RCM peripheral base address. + * @return status true - asserted, false - reasserted + */ +static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) +{ + return (bool)(base->MR & RCM_MR_EZP_MS_MASK); +} +#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Gets the ROM boot source. + * + * This function gets the ROM boot source during the last chip reset. + * + * @param base RCM peripheral base address. + * @return The ROM boot source. + */ +static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) +{ + return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); +} + +/*! + * @brief Clears the ROM boot source flag. + * + * This function clears the ROM boot source flag. + * + * @param base Register base address of RCM + */ +static inline void RCM_ClearBootRomSource(RCM_Type *base) +{ + base->MR |= RCM_MR_BOOTROM_MASK; +} + +/*! + * @brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * @param base RCM peripheral base address. + * @param config Boot configuration. + */ +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Sets the system reset interrupt configuration. + * + * For graceful shutdown, the RCM supports delaying the assertion of the system + * reset for a period of time when the reset interrupt is generated. This function + * can be used to enable the interrupt and the delay period. The interrupts + * are passed in as bit mask. See rcm_int_t for details. For example, to + * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, + * configure as follows: + * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); + * + * @param base RCM peripheral base address. + * @param intMask Bit mask of the system reset interrupts to enable. See + * rcm_interrupt_enable_t for details. + * @param Delay Bit mask of the system reset interrupts to enable. + */ +static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) +{ + base->SRIE = (intMask | delay); +} +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_RCM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c new file mode 100755 index 00000000000..898a544a467 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if (datetime->day > daysPerMonth[datetime->month]) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +void RTC_Init(RTC_Type *base, const rtc_config_t *config) +{ + assert(config); + + uint32_t reg; + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Issue a software reset if timer is invalid */ + if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) + { + RTC_Reset(RTC); + } + + reg = base->CR; + /* Setup the update mode and supervisor access mode */ + reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); + reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); +#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN + /* Setup the wakeup pin select */ + reg &= ~(RTC_CR_WPS_MASK); + reg |= RTC_CR_WPS(config->wakeupSelect); +#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ + base->CR = reg; + + /* Configure the RTC time compensation register */ + base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); +} + +void RTC_GetDefaultConfig(rtc_config_t *config) +{ + assert(config); + + /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ + config->wakeupSelect = false; + /* Registers cannot be written when locked */ + config->updateMode = false; + /* Non-supervisor mode write accesses are not supported and will generate a bus error */ + config->supervisorAccess = false; + /* Compensation interval used by the crystal compensation logic */ + config->compensationInterval = 0; + /* Compensation time used by the crystal compensation logic */ + config->compensationTime = 0; +} + +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->TSR = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = base->TSR; + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = base->TSR; + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->TAR = alarmSeconds; + + return kStatus_Success; +} + +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->TAR; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + /* The alarm flag is cleared by writing to the TAR register */ + if (mask & kRTC_AlarmFlag) + { + base->TAR = 0U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeOverflowFlag) + { + base->TSR = 1U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeInvalidFlag) + { + base->TSR = 1U; + } +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) +{ + *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); +} + +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) +{ + /* Prepare to initialize the register with the new value written */ + base->MER &= ~RTC_MER_MCE_MASK; + + base->MCHR = (uint32_t)((counter) >> 32); + base->MCLR = (uint32_t)(counter); +} + +status_t RTC_IncrementMonotonicCounter(RTC_Type *base) +{ + if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) + { + return kStatus_Fail; + } + + /* Prepare to switch to increment mode */ + base->MER |= RTC_MER_MCE_MASK; + /* Write anything so the counter increments*/ + base->MCLR = 1U; + + return kStatus_Success; +} + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h new file mode 100755 index 00000000000..063d1d40c34 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ + kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ + kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ + kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ + kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ + kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ +} rtc_status_flags_t; + +/*! @brief List of RTC Oscillator capacitor load settings */ +typedef enum _rtc_osc_cap_load +{ + kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2pF capacitor load */ + kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4pF capacitor load */ + kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8pF capacitor load */ + kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */ +} rtc_osc_cap_load_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/*! + * @brief RTC config structure + * + * This structure holds the configuration settings for the RTC peripheral. To initialize this + * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _rtc_config +{ + bool wakeupSelect; /*!< true: Wakeup pin outputs the 32KHz clock; + false:Wakeup pin used to wakeup the chip */ + bool updateMode; /*!< true: Registers can be written even when locked under certain + conditions, false: No writes allowed when registers are locked */ + bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; + false: Non-supervisor accesses are not supported */ + uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ + uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ +} rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the RTC clock and configures the peripheral for basic operation. + * + * This function will issue a software reset if the timer invalid flag is set. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + * @param config Pointer to user's RTC config structure. + */ +void RTC_Init(RTC_Type *base, const rtc_config_t *config); + +/*! + * @brief Stop the timer and gate the RTC clock + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->SR &= ~RTC_SR_TCE_MASK; + + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +/*! + * @brief Fill in the RTC config struct with the default settings + * + * The default values are: + * @code + * config->wakeupSelect = false; + * config->updateMode = false; + * config->supervisorAccess = false; + * config->compensationInterval = 0; + * config->compensationTime = 0; + * @endcode + * @param config Pointer to user's RTC config structure. + */ +void RTC_GetDefaultConfig(rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the RTC status flags + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); +} + +/*! + * @brief Clears the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->SR |= RTC_SR_TCE_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->SR &= ~RTC_SR_TCE_MASK; +} + +/*! @}*/ + +/*! + * @brief This function sets the specified capacitor configuration for the RTC oscillator. + * + * @param base RTC peripheral base address + * @param capLoad Oscillator loads to enable. This is a logical OR of members of the + * enumeration ::rtc_osc_cap_load_t + */ +static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) +{ + uint32_t reg = base->CR; + + reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR + * registers. The SWR bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CR |= RTC_CR_SWR_MASK; + base->CR &= ~RTC_CR_SWR_MASK; + + /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ + base->TSR = 1U; +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +/*! + * @name Monotonic counter functions + * @{ + */ + +/*! + * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns + * them as a single value. + * + * @param base RTC peripheral base address + * @param counter Pointer to variable where the value is stored. + */ +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); + +/*! + * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing + * the given single value. + * + * @param base RTC peripheral base address + * @param counter Counter value + */ +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); + +/*! + * @brief Increments the Monotonic Counter by one. + * + * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting + * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the + * monotonic counter low that causes it to overflow also increments the monotonic counter high. + * + * @param base RTC peripheral base address + * + * @return kStatus_Success: success + * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found + */ +status_t RTC_IncrementMonotonicCounter(RTC_Type *base); + +/*! @}*/ + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c new file mode 100755 index 00000000000..3a4b801b7b3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_sim.h" + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) +{ + SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); + + SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; +} +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +void SIM_GetUniqueId(sim_uid_t *uid) +{ +#if defined(SIM_UIDH) + uid->H = SIM->UIDH; +#endif + uid->MH = SIM->UIDMH; + uid->ML = SIM->UIDML; + uid->L = SIM->UIDL; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h new file mode 100755 index 00000000000..a3b69188841 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _FSL_SIM_H_ +#define _FSL_SIM_H_ + +#include "fsl_common.h" + +/*! @addtogroup sim */ +/*! @{*/ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ +/*@}*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*!@brief USB voltage regulator enable setting. */ +enum _sim_usb_volt_reg_enable_mode +{ + kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ + kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ + kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ + kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | + SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ +}; +#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ + +/*!@brief Unique ID. */ +typedef struct _sim_uid +{ +#if defined(SIM_UIDH) + uint32_t H; /*!< UIDH. */ +#endif + uint32_t MH; /*!< UIDMH. */ + uint32_t ML; /*!< UIDML. */ + uint32_t L; /*!< UIDL. */ +} sim_uid_t; + +/*!@brief Flash enable mode. */ +enum _sim_flash_mode +{ + kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ + kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*! + * @brief Sets the USB voltage regulator setting. + * + * This function configures whether the USB voltage regulator is enabled in + * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations + * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable + * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, + * please use: + * + * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); + * + * @param mask USB voltage regulator enable setting. + */ +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +/*! + * @brief Get the unique identification register value. + * + * @param uid Pointer to the structure to save the UID value. + */ +void SIM_GetUniqueId(sim_uid_t *uid); + +/*! + * @brief Set the flash enable mode. + * + * @param mode The mode to set, see \ref _sim_flash_mode for mode details. + */ +static inline void SIM_SetFlashMode(uint8_t mode) +{ + SIM->FCFG1 = mode; +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_SIM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c new file mode 100755 index 00000000000..0018cf7dce2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_smc.h" + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +void SMC_GetParam(SMC_Type *base, smc_param_t *param) +{ + uint32_t reg = base->PARAM; + param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); + param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); + param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); + param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); +} +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +status_t SMC_SetPowerModeRun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure Normal RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +status_t SMC_SetPowerModeHsrun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure High Speed RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +status_t SMC_SetPowerModeWait(SMC_Type *base) +{ + /* configure Normal Wait mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) + /* configure the Partial Stop mode in Noraml Stop mode */ + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_PSTOPO_MASK; + reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); + base->STOPCTRL = reg; +#endif + + /* configure Normal Stop mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter Stop mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +status_t SMC_SetPowerModeVlpr(SMC_Type *base +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + , + bool wakeupMode +#endif + ) +{ + uint8_t reg; + + reg = base->PMCTRL; +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + /* configure whether the system remains in VLP mode on an interrupt */ + if (wakeupMode) + { + /* exits to RUN mode on an interrupt */ + reg |= SMC_PMCTRL_LPWUI_MASK; + } + else + { + /* remains in VLP mode on an interrupt */ + reg &= ~SMC_PMCTRL_LPWUI_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + + /* configure VLPR mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlpw(SMC_Type *base) +{ + /* Power mode transaction to VLPW can only happen in VLPR mode */ + if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base)) + { + return kStatus_Fail; + } + + /* configure VLPW mode */ + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlps(SMC_Type *base) +{ + uint8_t reg; + + /* configure VLPS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter VLPS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeLls(SMC_Type *base +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) + , + const smc_power_mode_lls_config_t *config +#endif + ) +{ + uint8_t reg; + + /* configure to LLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure LLS sub-mode*/ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + if (config->subMode == kSMC_StopSub0) +#endif + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enablePorDetectInVlls0) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; +#endif + } + } +#endif /* FSL_FEATURE_SMC_HAS_PORPO */ + +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + else if (config->subMode == kSMC_StopSub2) + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enableRam2InVlls2) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + } + else + { + } +#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ + + /* configure to VLLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure the VLLS sub-mode */ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + reg = base->VLLSCTRL; + reg &= ~SMC_VLLSCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); + base->VLLSCTRL = reg; +#else +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#else + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ +#endif + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __WFI(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h new file mode 100755 index 00000000000..5149f87e346 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SMC_H_ +#define _FSL_SMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup smc */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMC driver version 2.0.1. */ +#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief Power Modes Protection + */ +typedef enum _smc_power_mode_protection +{ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + kSMC_AllowPowerModeAll = (0U +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_AVLLS_MASK +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_ALLS_MASK +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + | + SMC_PMPROT_AVLP_MASK +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + | + kSMC_AllowPowerModeHsrun +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + ) /*!< Allow all power mode. */ +} smc_power_mode_protection_t; + +/*! + * @brief Power Modes in PMSTAT + */ +typedef enum _smc_power_state +{ + kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ + kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ + kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ + kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ + kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_power_state_t; + +/*! + * @brief Run mode definition + */ +typedef enum _smc_run_mode +{ + kSMC_RunNormal = 0U, /*!< normal RUN mode. */ + kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_run_mode_t; + +/*! + * @brief Stop mode definition + */ +typedef enum _smc_stop_mode +{ + kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ + kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_StopVlls = 4U /*!< Very-Low-Leakage Stop mode. */ +#endif +} smc_stop_mode_t; + +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) +/*! + * @brief VLLS/LLS stop sub mode definition + */ +typedef enum _smc_stop_submode +{ + kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ + kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ + kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ + kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ +} smc_stop_submode_t; +#endif + +/*! + * @brief Partial STOP option + */ +typedef enum _smc_partial_stop_mode +{ + kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ + kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ + kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ +} smc_partial_stop_option_t; + +/*! + * @brief SMC configuration status + */ +enum _smc_status +{ + kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ +}; + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _smc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} smc_version_id_t; +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _smc_param +{ + bool hsrunEnable; /*!< HSRUN mode enable. */ + bool llsEnable; /*!< LLS mode enable. */ + bool lls2Enable; /*!< LLS2 mode enable. */ + bool vlls0Enable; /*!< VLLS0 mode enable. */ +} smc_param_t; +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) +/*! + * @brief SMC Low-Leakage Stop power mode config + */ +typedef struct _smc_power_mode_lls_config +{ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ +#endif +} smc_power_mode_lls_config_t; +#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief SMC Very Low-Leakage Stop power mode config + */ +typedef struct _smc_power_mode_vlls_config +{ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) + bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ +#endif +} smc_power_mode_vlls_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name System mode controller APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief Gets the SMC version ID. + * + * This function gets the SMC version ID, including major version number, + * minor version number and feature specification number. + * + * @param base SMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief Gets the SMC parameter. + * + * This function gets the SMC parameter, including the enabled power mdoes. + * + * @param base SMC peripheral base address. + * @param param Pointer to SMC param structure. + */ +void SMC_GetParam(SMC_Type *base, smc_param_t *param); +#endif + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes in the specified chip family. The available power modes + * are defined in the smc_power_mode_protection_t. This should be done at an early + * system level initialization stage. See the reference manual for details. + * This register can only write once after the power reset. + * + * The allowed modes are passed as bit map, for example, to allow LLS and VLLS, + * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). + * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). + * + * @param base SMC peripheral base address. + * @param allowedModes Bitmap of the allowed power modes. + */ +static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) +{ + base->PMPROT = allowedModes; +} + +/*! + * @brief Gets the current power mode status. + * + * This function returns the current power mode stat. Once application + * switches the power mode, it should always check the stat to check whether it + * runs into the specified mode or not. An application should check + * this mode before switching to a different mode. The system requires that + * only certain modes can switch to other specific modes. See the + * reference manual for details and the smc_power_state_t for information about + * the power stat. + * + * @param base SMC peripheral base address. + * @return Current power mode status. + */ +static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) +{ + return (smc_power_state_t)base->PMSTAT; +} + +/*! + * @brief Configure the system to RUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeRun(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * @brief Configure the system to HSRUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeHsrun(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +/*! + * @brief Configure the system to WAIT power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeWait(SMC_Type *base); + +/*! + * @brief Configure the system to Stop power mode. + * + * @param base SMC peripheral base address. + * @param option Partial Stop mode option. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); + +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) +/*! + * @brief Configure the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); +#else +/*! + * @brief Configure the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + +/*! + * @brief Configure the system to VLPW power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpw(SMC_Type *base); + +/*! + * @brief Configure the system to VLPS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlps(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) +/*! + * @brief Configure the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @param config The LLS power mode configuration structure + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); +#else +/*! + * @brief Configure the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base); +#endif +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief Configure the system to VLLS power mode. + * + * @param base SMC peripheral base address. + * @param config The VLLS power mode configuration structure. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_SMC_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c new file mode 100755 index 00000000000..2132fd641c3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c @@ -0,0 +1,873 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spi.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ +enum _spi_transfer_states_t +{ + kSPI_Idle = 0x0, /*!< SPI is idle state */ + kSPI_Busy /*!< SPI is busy tranferring data. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance for SPI module. + * + * @param base SPI base address + */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @brief Sends a buffer of data bytes in non-blocking way. + * + * @param base SPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void SPI_WriteNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size); + +/*! + * @brief Receive a buffer of data bytes in non-blocking way. + * + * @param base SPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void SPI_ReadNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size); + +/*! + * @brief Send a piece of data for SPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param handle Pointer to SPI master handle structure. + */ +static void SPI_SendTransfer(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for SPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param handle Pointer to SPI master handle structure. + */ +static void SPI_ReceiveTransfer(SPI_Type *base, spi_master_handle_t *handle); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* SPI internal handle pointer array */ +static spi_master_handle_t *s_spiHandle[FSL_FEATURE_SOC_SPI_COUNT]; +/* Base pointer array */ +static SPI_Type *const s_spiBases[] = SPI_BASE_PTRS; +/* IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; +/* Clock array name */ +static const clock_ip_name_t s_spiClock[] = SPI_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_SPI_COUNT; instance++) + { + if (s_spiBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_SPI_COUNT); + + return instance; +} + +static void SPI_WriteNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerFrame = 1U; + +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + /* Check if 16 bits or 8 bits */ + bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; +#endif + + while (i < size) + { + if (buffer != NULL) + { +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + /*16 bit mode*/ + if (base->C2 & SPI_C2_SPIMODE_MASK) + { + base->DL = *buffer++; + base->DH = *buffer++; + } + /* 8 bit mode */ + else + { + base->DL = *buffer++; + } +#else + base->D = *buffer++; +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + } + /* Send dummy data */ + else + { + SPI_WriteData(base, SPI_DUMMYDATA); + } + i += bytesPerFrame; + } +} + +static void SPI_ReadNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerFrame = 1U; + +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + /* Check if 16 bits or 8 bits */ + bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; +#endif + + while (i < size) + { + if (buffer != NULL) + { +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + /*16 bit mode*/ + if (base->C2 & SPI_C2_SPIMODE_MASK) + { + *buffer++ = base->DL; + *buffer++ = base->DH; + } + /* 8 bit mode */ + else + { + *buffer++ = base->DL; + } +#else + *buffer++ = base->D; +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + } + else + { + SPI_ReadData(base); + } + i += bytesPerFrame; + } +} + +static void SPI_SendTransfer(SPI_Type *base, spi_master_handle_t *handle) +{ + uint8_t bytes = MIN((handle->watermark * 2U), handle->txRemainingBytes); + uint8_t val = 1U; + + /* Read S register and ensure SPTEF is 1, otherwise the write would be ignored. */ + if (handle->watermark == 1U) + { + val = (base->S & SPI_S_SPTEF_MASK); + if (bytes != 0U) + { + bytes = handle->bytePerFrame; + } + } +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO) + else + { + val = (base->S & SPI_S_TNEAREF_MASK); + } +#endif + + /* Write data */ + if (val) + { + SPI_WriteNonBlocking(base, handle->txData, bytes); + + /* Update handle information */ + if (handle->txData) + { + handle->txData += bytes; + } + handle->txRemainingBytes -= bytes; + } +} + +static void SPI_ReceiveTransfer(SPI_Type *base, spi_master_handle_t *handle) +{ + uint8_t bytes = MIN((handle->watermark * 2U), handle->rxRemainingBytes); + uint8_t val = 1U; + + /* Read S register and ensure SPRF is 1, otherwise the write would be ignored. */ + if (handle->watermark == 1U) + { + val = base->S & SPI_S_SPRF_MASK; + if (bytes != 0U) + { + bytes = handle->bytePerFrame; + } + } + + if (val) + { + SPI_ReadNonBlocking(base, handle->rxData, bytes); + + /* Update information in handle */ + if (handle->rxData) + { + handle->rxData += bytes; + } + handle->rxRemainingBytes -= bytes; + } +} + +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + config->enableMaster = true; + config->enableStopInWaitMode = false; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + config->dataMode = kSPI_8BitMode; +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + config->txWatermark = kSPI_TxFifoOneHalfEmpty; + config->rxWatermark = kSPI_RxFifoOneHalfFull; +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + + config->pinMode = kSPI_PinModeNormal; + config->outputMode = kSPI_SlaveSelectAutomaticOutput; + config->baudRate_Bps = 500000U; +} + +void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_spiClock[SPI_GetInstance(base)]); + + /* Disable SPI before configuration */ + base->C1 &= ~SPI_C1_SPE_MASK; + + /* Configure clock polarity and phase, set SPI to master */ + base->C1 = SPI_C1_MSTR(1U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) | + SPI_C1_SSOE(config->outputMode & 1U) | SPI_C1_LSBFE(config->direction); + +/* Set data mode, and also pin mode and mode fault settings */ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + base->C2 = SPI_C2_MODFEN(config->outputMode >> 1U) | SPI_C2_BIDIROE(config->pinMode >> 1U) | + SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_SPC0(config->pinMode & 1U) | + SPI_C2_SPIMODE(config->dataMode); +#else + base->C2 = SPI_C2_MODFEN(config->outputMode >> 1U) | SPI_C2_BIDIROE(config->pinMode >> 1U) | + SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_SPC0(config->pinMode & 1U); +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + +/* Set watermark, FIFO is enabled */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) | + SPI_C3_INTCLR(0U) | SPI_C3_FIFOMODE(1U); + } +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + + /* Set baud rate */ + SPI_MasterSetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + + /* Enable SPI */ + if (config->enableMaster) + { + base->C1 |= SPI_C1_SPE_MASK; + } +} + +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->enableStopInWaitMode = false; + +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + config->dataMode = kSPI_8BitMode; +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + config->txWatermark = kSPI_TxFifoOneHalfEmpty; + config->rxWatermark = kSPI_RxFifoOneHalfFull; +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +} + +void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_spiClock[SPI_GetInstance(base)]); + + /* Disable SPI before configuration */ + base->C1 &= ~SPI_C1_SPE_MASK; + + /* Configure master and clock polarity and phase */ + base->C1 = + SPI_C1_MSTR(0U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) | SPI_C1_LSBFE(config->direction); + +/* Configure data mode if needed */ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + base->C2 = SPI_C2_SPIMODE(config->dataMode) | SPI_C2_SPISWAI(config->enableStopInWaitMode); +#else + base->C2 = SPI_C2_SPISWAI(config->enableStopInWaitMode); +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + +/* Set watermark */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0U) + { + base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) | + SPI_C3_INTCLR(0U) | SPI_C3_FIFOMODE(1U); + } +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + + /* Enable SPI */ + if (config->enableSlave) + { + base->C1 |= SPI_C1_SPE_MASK; + } +} + +void SPI_Deinit(SPI_Type *base) +{ + /* Disable SPI module before shutting down */ + base->C1 &= ~SPI_C1_SPE_MASK; + + /* Gate the clock */ + CLOCK_DisableClock(s_spiClock[SPI_GetInstance(base)]); +} + +uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + return ((base->S) | (((uint32_t)base->CI) << 8U)); + } + else + { + return (base->S); + } +#else + return (base->S); +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +} + +void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask) +{ + /* Rx full interrupt */ + if (mask & kSPI_RxFullAndModfInterruptEnable) + { + base->C1 |= SPI_C1_SPIE_MASK; + } + + /* Tx empty interrupt */ + if (mask & kSPI_TxEmptyInterruptEnable) + { + base->C1 |= SPI_C1_SPTIE_MASK; + } + + /* Data match interrupt */ + if (mask & kSPI_MatchInterruptEnable) + { + base->C2 |= SPI_C2_SPMIE_MASK; + } + +/* FIFO related interrupts */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + /* Rx FIFO near full interrupt */ + if (mask & kSPI_RxFifoNearFullInterruptEnable) + { + base->C3 |= SPI_C3_RNFULLIEN_MASK; + } + + /* Tx FIFO near empty interrupt */ + if (mask & kSPI_TxFifoNearEmptyInterruptEnable) + { + base->C3 |= SPI_C3_TNEARIEN_MASK; + } + } +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +} + +void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask) +{ + /* Rx full interrupt */ + if (mask & kSPI_RxFullAndModfInterruptEnable) + { + base->C1 &= (~SPI_C1_SPIE_MASK); + } + + /* Tx empty interrupt */ + if (mask & kSPI_TxEmptyInterruptEnable) + { + base->C1 &= (~SPI_C1_SPTIE_MASK); + } + + /* Data match interrupt */ + if (mask & kSPI_MatchInterruptEnable) + { + base->C2 &= (~SPI_C2_SPMIE_MASK); + } + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + /* Rx FIFO near full interrupt */ + if (mask & kSPI_RxFifoNearFullInterruptEnable) + { + base->C3 &= ~SPI_C3_RNFULLIEN_MASK; + } + + /* Tx FIFO near empty interrupt */ + if (mask & kSPI_TxFifoNearEmptyInterruptEnable) + { + base->C3 &= ~SPI_C3_TNEARIEN_MASK; + } + } +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +} + +void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t prescaler; + uint32_t bestPrescaler; + uint32_t rateDivisor; + uint32_t bestDivisor; + uint32_t rateDivisorValue; + uint32_t realBaudrate; + uint32_t diff; + uint32_t min_diff; + uint32_t freq = baudRate_Bps; + + /* Find combination of prescaler and scaler resulting in baudrate closest to the requested value */ + min_diff = 0xFFFFFFFFU; + + /* Set the maximum divisor bit settings for each of the following divisors */ + bestPrescaler = 7U; + bestDivisor = 8U; + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0; (prescaler <= 7) && min_diff; prescaler++) + { + /* Initialize to div-by-2 */ + rateDivisorValue = 2U; + + for (rateDivisor = 0; (rateDivisor <= 8U) && min_diff; rateDivisor++) + { + /* Calculate actual baud rate, note need to add 1 to prescaler */ + realBaudrate = ((srcClock_Hz) / ((prescaler + 1) * rateDivisorValue)); + + /* Calculate the baud rate difference based on the conditional statement ,that states that the + calculated baud rate must not exceed the desired baud rate */ + if (freq >= realBaudrate) + { + diff = freq - realBaudrate; + if (min_diff > diff) + { + /* A better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestDivisor = rateDivisor; + } + } + + /* Multiply by 2 for each iteration, possible divisor values: 2, 4, 8, 16, ... 512 */ + rateDivisorValue *= 2U; + } + } + + /* Write the best prescalar and baud rate scalar */ + base->BR = SPI_BR_SPR(bestDivisor) | SPI_BR_SPPR(bestPrescaler); +} + +void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size) +{ + uint32_t i = 0; + + while (i < size) + { + while ((base->S & SPI_S_SPTEF_MASK) == 0) + { + } + + /* Send data */ + SPI_WriteNonBlocking(base, buffer, size); + + /* Wait the data to be sent */ + while ((base->S & SPI_S_SPTEF_MASK) == 0) + { + } + i++; + } +} + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO +void SPI_EnableFIFO(SPI_Type *base, bool enable) +{ + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0U) + { + if (enable) + { + base->C3 |= SPI_C3_FIFOMODE_MASK; + } + else + { + base->C3 &= ~SPI_C3_FIFOMODE_MASK; + } + } +} +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + +void SPI_WriteData(SPI_Type *base, uint16_t data) +{ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) + base->DL = data & 0xFFU; + base->DH = (data >> 8U) & 0xFFU; +#else + base->D = data & 0xFFU; +#endif +} + +uint16_t SPI_ReadData(SPI_Type *base) +{ + uint16_t val = 0; +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) + val = base->DL; + val |= (uint16_t)((uint16_t)(base->DH) << 8U); +#else + val = base->D; +#endif + return val; +} + +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + assert(xfer); + + uint8_t bytesPerFrame = 1U; + + /* Check if the argument is legal */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + /* Check if 16 bits or 8 bits */ + bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; +#endif + + /* Disable SPI and then enable it, this is used to clear S register */ + base->C1 &= ~SPI_C1_SPE_MASK; + base->C1 |= SPI_C1_SPE_MASK; + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + + /* Disable FIFO, as the FIFO may cause data loss if the data size is not integer + times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO + size. */ + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + base->C3 &= ~SPI_C3_FIFOMODE_MASK; + } + +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + + /* Begin the polling transfer until all data sent */ + while (xfer->dataSize > 0) + { + /* Data send */ + while ((base->S & SPI_S_SPTEF_MASK) == 0U) + { + } + SPI_WriteNonBlocking(base, xfer->txData, bytesPerFrame); + if (xfer->txData) + { + xfer->txData += bytesPerFrame; + } + + while ((base->S & SPI_S_SPRF_MASK) == 0U) + { + } + SPI_ReadNonBlocking(base, xfer->rxData, bytesPerFrame); + if (xfer->rxData) + { + xfer->rxData += bytesPerFrame; + } + + /* Decrease the number */ + xfer->dataSize -= bytesPerFrame; + } + + return kStatus_Success; +} + +void SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + assert(handle); + + uint8_t instance = SPI_GetInstance(base); + + /* Initialize the handle */ + s_spiHandle[instance] = handle; + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + uint8_t txSize = 0U; + /* Get the number to be sent if there is FIFO */ + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + txSize = (base->C3 & SPI_C3_TNEAREF_MARK_MASK) >> SPI_C3_TNEAREF_MARK_SHIFT; + if (txSize == 0U) + { + handle->watermark = FSL_FEATURE_SPI_FIFO_SIZEn(base) * 3U / 4U; + } + else + { + handle->watermark = FSL_FEATURE_SPI_FIFO_SIZEn(base) / 2U; + } + } + /* If no FIFO, just set the watermark to 1 */ + else + { + handle->watermark = 1U; + } +#else + handle->watermark = 1U; +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + +/* Get the bytes per frame */ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) + handle->bytePerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; +#else + handle->bytePerFrame = 1U; +#endif + + /* Enable SPI NVIC */ + EnableIRQ(s_spiIRQ[instance]); +} + +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + assert(handle && xfer); + + /* Check if SPI is busy */ + if (handle->state == kSPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Check if the input arguments valid */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->transferSize = xfer->dataSize; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Set the SPI state to busy */ + handle->state = kSPI_Busy; + + /* Disable SPI and then enable it, this is used to clear S register*/ + base->C1 &= ~SPI_C1_SPE_MASK; + base->C1 |= SPI_C1_SPE_MASK; + +/* Enable Interrupt, only enable Rx interrupt, use rx interrupt to driver SPI transfer */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (handle->watermark > 1U) + { + /* Enable Rx near full interrupt */ + SPI_EnableInterrupts(base, kSPI_RxFifoNearFullInterruptEnable); + } + else + { + SPI_EnableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); + } +#else + SPI_EnableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); +#endif + + /* First send a piece of data to Tx Data or FIFO to start a SPI transfer */ + SPI_SendTransfer(base, handle); + + return kStatus_Success; +} + +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kStatus_SPI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + /* Return remaing bytes in different cases */ + if (handle->rxData) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + } + + return status; +} + +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(handle); + +/* Stop interrupts */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + if (handle->watermark > 1U) + { + SPI_DisableInterrupts(base, kSPI_RxFifoNearFullInterruptEnable | kSPI_RxFullAndModfInterruptEnable); + } + else + { + SPI_DisableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); + } +#else + SPI_DisableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); +#endif + + /* Transfer finished, set the state to Done*/ + handle->state = kSPI_Idle; + + /* Clear the internal state */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(handle); + + /* If needs to receive data, do a receive */ + if (handle->rxRemainingBytes) + { + SPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the SPI run */ + if (handle->txRemainingBytes) + { + SPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) + { + /* Complete the transfer */ + SPI_MasterTransferAbort(base, handle); + + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPI_Idle, handle->userData); + } + } +} + +static void SPI_TransferCommonIRQHandler(SPI_Type *base, void *handle) +{ + if (base->C1 & SPI_C1_MSTR_MASK) + { + SPI_MasterTransferHandleIRQ(base, (spi_master_handle_t *)handle); + } + else + { + SPI_SlaveTransferHandleIRQ(base, (spi_slave_handle_t *)handle); + } +} + +#if defined(SPI0) +void SPI0_DriverIRQHandler(void) +{ + assert(s_spiHandle[0]); + SPI_TransferCommonIRQHandler(SPI0, s_spiHandle[0]); +} +#endif + +#if defined(SPI1) +void SPI1_DriverIRQHandler(void) +{ + assert(s_spiHandle[1]); + SPI_TransferCommonIRQHandler(SPI1, s_spiHandle[1]); +} +#endif + +#if defined(SPI2) +void SPI2_DriverIRQHandler(void) +{ + assert(s_spiHandle[2]); + SPI_TransferCommonIRQHandler(SPI0, s_spiHandle[2]); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h new file mode 100755 index 00000000000..56da5a785a9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used tom endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPI_H_ +#define _FSL_SPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI driver version 2.0.0. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) + +/*! @brief Return status for the SPI driver.*/ +enum _spi_status +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2) /*!< SPI error */ +}; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0x0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI slave select output mode options.*/ +typedef enum _spi_ss_output_mode +{ + kSPI_SlaveSelectAsGpio = 0x0U, /*!< Slave select pin configured as GPIO. */ + kSPI_SlaveSelectFaultInput = 0x2U, /*!< Slave select pin configured for fault detection. */ + kSPI_SlaveSelectAutomaticOutput = 0x3U /*!< Slave select pin configured for automatic SPI output. */ +} spi_ss_output_mode_t; + +/*! @brief SPI pin mode options.*/ +typedef enum _spi_pin_mode +{ + kSPI_PinModeNormal = 0x0U, /*!< Pins operate in normal, single-direction mode.*/ + kSPI_PinModeInput = 0x1U, /*!< Bidirectional mode. Master: MOSI pin is input; + * Slave: MISO pin is input. */ + kSPI_PinModeOutput = 0x3U /*!< Bidirectional mode. Master: MOSI pin is output; + * Slave: MISO pin is output. */ +} spi_pin_mode_t; + +/*! @brief SPI data length mode options.*/ +typedef enum _spi_data_bitcount_mode +{ + kSPI_8BitMode = 0x0U, /*!< 8-bit data transmission mode*/ + kSPI_16BitMode /*!< 16-bit data transmission mode*/ +} spi_data_bitcount_mode_t; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxFullAndModfInterruptEnable = 0x1U, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */ + kSPI_TxEmptyInterruptEnable = 0x2U, /*!< Transmit buffer empty interrupt */ + kSPI_MatchInterruptEnable = 0x4U, /*!< Match interrupt */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + kSPI_RxFifoNearFullInterruptEnable = 0x8U, /*!< Receive FIFO nearly full interrupt */ + kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, /*!< Transmit FIFO nearly empty interrupt */ +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_flags +{ + kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK, /*!< Read buffer full flag */ + kSPI_MatchFlag = SPI_S_SPMF_MASK, /*!< Match flag */ + kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, /*!< Transmit buffer empty flag */ + kSPI_ModeFaultFlag = SPI_S_MODF_MASK, /*!< Mode fault flag */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK, /*!< Rx FIFO near full */ + kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK, /*!< Tx FIFO near empty */ + kSPI_RxFifoFullFlag = SPI_S_TXFULLF_MASK, /*!< Rx FIFO full */ + kSPI_TxFifoEmptyFlag = SPI_S_RFIFOEF_MASK, /*!< Tx FIFO empty */ + kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U, /*!< Tx FIFO error */ + kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U, /*!< Rx FIFO Overflow */ + kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U, /*!< Tx FIFO Overflow */ + kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U /*!< Rx FIFO Overflow */ +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +}; + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO +/*! @brief SPI FIFO write-1-to-clear interrupt flags.*/ +typedef enum _spi_w1c_interrupt +{ + kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK, /*!< Receive FIFO full interrupt */ + kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK, /*!< Transmit FIFO empty interrupt */ + kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */ + kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK /*!< Transmit FIFO nearly empty interrupt */ +} spi_w1c_interrupt_t; + +/*! @brief SPI TX FIFO watermark settings.*/ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifoOneFourthEmpty = 0, /*!< SPI tx watermark at 1/4 FIFO size */ + kSPI_TxFifoOneHalfEmpty = 1 /*!< SPI tx watermark at 1/2 FIFO size */ +} spi_txfifo_watermark_t; + +/*! @brief SPI RX FIFO watermark settings.*/ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifoThreeFourthsFull = 0, /*!< SPI rx watermark at 3/4 FIFO size */ + kSPI_RxFifoOneHalfFull = 1 /*!< SPI rx watermark at 1/2 FIFO size */ +} spi_rxfifo_watermark_t; +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + +#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT +/*! @brief SPI DMA source*/ +enum _spi_dma_enable_t +{ + kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK, /*!< Tx DMA request source */ + kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK, /*!< Rx DMA request source */ + kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) /*!< All DMA request source*/ +}; +#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */ + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableMaster; /*!< Enable SPI at initialization time */ + bool enableStopInWaitMode; /*!< SPI stop in wait mode */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */ +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */ + spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */ +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + spi_ss_output_mode_t outputMode; /*!< SS pin setting */ + spi_pin_mode_t pinMode; /*!< SPI pin mode select */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + bool enableStopInWaitMode; /*!< SPI stop in wait mode */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */ +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO + spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */ + spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */ +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ +} spi_slave_config_t; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t dataSize; /*!< Transfer bytes */ + uint32_t flags; /*!< SPI control flag, useless to SPI.*/ +} spi_transfer_t; + +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle is the same with master handle */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */ + volatile uint32_t state; /*!< SPI internal state */ + size_t transferSize; /*!< Bytes to be transferred */ + uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ + uint8_t watermark; /*!< Watermark value for SPI transfer */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * APIs + ******************************************************************************/ +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = kSPIClockPolarity_ActiveHigh; + .phase = kSPIClockPhase_FirstEdge; + .direction = kSPIMsbFirst; + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + */ +void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enables or disables the SPI. + * + * @param base SPI base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void SPI_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= SPI_C1_SPE_MASK; + } + else + { + base->C1 &= ~SPI_C1_SPE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND #_spi_flags could get the related status. + */ +uint32_t SPI_GetStatusFlags(SPI_Type *base); + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO +/*! + * @brief Clear the interrupt if enable INCTLR. + * + * @param base SPI base pointer + * @param interrupt Interrupt need to be cleared + * The parameter could be any combination of the following values: + * @arg kSPIRxFifoFullClearInt + * @arg kSPITxFifoEmptyClearInt + * @arg kSPIRxNearFullClearInt + * @arg kSPITxNearEmptyClearInt + */ +static inline void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask) +{ + base->CI |= mask; +} +#endif /* FSL_FEATURE_SPI_HAS_FIFO */ + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param mask SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxFullAndModfInterruptEnable + * @arg kSPI_TxEmptyInterruptEnable + * @arg kSPI_MatchInterruptEnable + * @arg kSPI_RxFifoNearFullInterruptEnable + * @arg kSPI_TxFifoNearEmptyInterruptEnable + */ +void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param mask SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxFullAndModfInterruptEnable + * @arg kSPI_TxEmptyInterruptEnable + * @arg kSPI_MatchInterruptEnable + * @arg kSPI_RxFifoNearFullInterruptEnable + * @arg kSPI_TxFifoNearEmptyInterruptEnable + */ +void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +#if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT +/*! + * @brief Enables the DMA source for SPI. + * + * @param base SPI base pointer + * @param source SPI DMA source. + * @param enable True means enable DMA, false means disable DMA + */ +static inline void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->C2 |= mask; + } + else + { + base->C2 &= ~mask; + } +} +#endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */ + +/*! + * @brief Gets the SPI tx/rx data register address. + * + * This API is used to provide a transfer address for the SPI DMA transfer configuration. + * + * @param base SPI base pointer + * @return data register address + */ +static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base) +{ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + return (uint32_t)(&(base->DL)); +#else + return (uint32_t)(&(base->D)); +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudRate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sets the match data for SPI. + * + * The match data is a hardware comparison value. When the value received in the SPI receive data + * buffer equals the hardware comparison value, the SPI Match Flag in the S register (S[SPMF]) sets. + * This can also generate an interrupt if the enable bit sets. + * + * @param base SPI base pointer + * @param matchData Match data. + */ +static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData) +{ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS + base->ML = matchData & 0xFFU; + base->MH = (matchData >> 8U) & 0xFFU; +#else + base->M = matchData; +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ +} + +#if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO +/*! + * @brief Enables or disables the FIFO if there is a FIFO. + * + * @param base SPI base pointer + * @param enable True means enable FIFO, false means disable FIFO. + */ +void SPI_EnableFIFO(SPI_Type *base, bool enable); +#endif + +/*! + * @brief Sends a buffer of data bytes using a blocking method. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base SPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + */ +void SPI_WriteData(SPI_Type *base, uint16_t data); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +uint16_t SPI_ReadData(SPI_Type *base); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @note The API immediately returns after transfer initialization is finished. + * Call SPI_GetStatusIRQ() to get the transfer status. + * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times of the watermark. Otherwise, + * the last data may be lost because it cannot generate an interrupt request. Users can also call the functional API to get the last + * received data. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Gets the bytes of the SPI interrupt transferred. + * + * @param base SPI peripheral base address. + * @param handle Pointer to SPI transfer handle, this should be a static variable. + * @param count Transferred bytes of SPI master. + * @retval kStatus_SPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an SPI transfer using interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to SPI transfer handle, this should be a static variable. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline void SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * Call SPI_GetStatusIRQ() to get the transfer status. + * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times the watermark. Otherwise, + * the last data may be lost because it cannot generate an interrupt request. Call the functional API to get the last several + * receive data. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the bytes of the SPI interrupt transferred. + * + * @param base SPI peripheral base address. + * @param handle Pointer to SPI transfer handle, this should be a static variable. + * @param count Transferred bytes of SPI slave. + * @retval kStatus_SPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief Aborts an SPI slave transfer using interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to SPI transfer handle, this should be a static variable. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_H_*/ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c new file mode 100755 index 00000000000..b7b85454cf0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spi_dma.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*handle; + SPI_Type *base = privHandle->base; + + /* Disable Tx dma */ + SPI_EnableDMA(base, kSPI_TxDmaEnable, false); + + /* Stop DMA tranfer */ + DMA_StopTransfer(spiHandle->txHandle); + + /* change the state */ + spiHandle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* Disable Tx dma */ + SPI_EnableDMA(base, kSPI_RxDmaEnable, false); + + /* Stop DMA tranfer */ + DMA_StopTransfer(spiHandle->rxHandle); + + /* change the state */ + spiHandle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +void SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + assert(handle); + dma_transfer_config_t config = {0}; + uint32_t instance = SPI_GetInstance(base); + + /* Set spi base to handle */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle */ + handle->state = kSPI_Idle; + + /* Set handle to global state */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + +/* Compute internal state */ +#if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) + handle->bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; +#else + handle->bytesPerFrame = 1U; +#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ + +#if defined(FSL_FEATURE_SPI_FIFO_SIZE) && (FSL_FEATURE_SPI_FIFO_SIZE > 1) + /* If using DMA, disable FIFO, as the FIFO may cause data loss if the data size is not integer + times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO + size. */ + if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) + { + base->C3 &= ~SPI_C3_FIFOMODE_MASK; + } + +#endif /* FSL_FEATURE_SPI_FIFO_SIZE */ + + /* Set the non-change attribute for Tx DMA transfer, to improve efficiency */ + config.destAddr = SPI_GetDataRegisterAddress(base); + config.enableDestIncrement = false; + config.enableSrcIncrement = true; + if (handle->bytesPerFrame == 1U) + { + config.srcSize = kDMA_Transfersize8bits; + config.destSize = kDMA_Transfersize8bits; + } + else + { + config.srcSize = kDMA_Transfersize16bits; + config.destSize = kDMA_Transfersize16bits; + } + + DMA_SubmitTransfer(handle->txHandle, &config, true); + + /* Set non-change attribute for Rx DMA */ + config.srcAddr = SPI_GetDataRegisterAddress(base); + config.destAddr = 0U; + config.enableDestIncrement = true; + config.enableSrcIncrement = false; + DMA_SubmitTransfer(handle->rxHandle, &config, true); + + /* Install callback for Tx dma channel */ + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); +} + +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + assert(handle && xfer); + + dma_transfer_config_t config = {0}; + + /* Check if the device is busy */ + if (handle->state == kSPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Check if input parameter invalid */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Configure tx transfer DMA */ + config.destAddr = SPI_GetDataRegisterAddress(base); + config.enableDestIncrement = false; + if (handle->bytesPerFrame == 1U) + { + config.srcSize = kDMA_Transfersize8bits; + config.destSize = kDMA_Transfersize8bits; + } + else + { + config.srcSize = kDMA_Transfersize16bits; + config.destSize = kDMA_Transfersize16bits; + } + config.transferSize = xfer->dataSize; + /* Configure DMA channel */ + if (xfer->txData) + { + config.enableSrcIncrement = true; + config.srcAddr = (uint32_t)(xfer->txData); + } + else + { + /* Disable the source increasement and source set to dummyData */ + config.enableSrcIncrement = false; + config.srcAddr = (uint32_t)(&s_dummyData); + } + DMA_SubmitTransfer(handle->txHandle, &config, true); + + /* Handle rx transfer */ + if (xfer->rxData) + { + /* Set the source address */ + DMA_SetDestinationAddress(handle->rxHandle->base, handle->rxHandle->channel, (uint32_t)(xfer->rxData)); + + /* Set the transfer size */ + DMA_SetTransferSize(handle->rxHandle->base, handle->rxHandle->channel, xfer->dataSize); + } + + /* Change the state of handle */ + handle->transferSize = xfer->dataSize; + handle->state = kSPI_Busy; + + /* Start Rx transfer if needed */ + if (xfer->rxData) + { + handle->rxInProgress = true; + SPI_EnableDMA(base, kSPI_RxDmaEnable, true); + DMA_StartTransfer(handle->rxHandle); + } + + /* Always start Tx transfer */ + handle->txInProgress = true; + SPI_EnableDMA(base, kSPI_TxDmaEnable, true); + DMA_StartTransfer(handle->txHandle); + + return kStatus_Success; +} + +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + if (handle->rxInProgress) + { + *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); + } + else + { + *count = handle->transferSize - DMA_GetRemainingBytes(handle->txHandle->base, handle->txHandle->channel); + } + } + + return status; +} + +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + DMA_StopTransfer(handle->txHandle); + DMA_StopTransfer(handle->rxHandle); + + /* Disable DMA enable bit */ + SPI_EnableDMA(base, kSPI_DmaAllEnable, false); + + /* Set the handle state */ + handle->txInProgress = false; + handle->rxInProgress = false; + handle->state = kSPI_Idle; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h new file mode 100755 index 00000000000..264d5884900 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPI_DMA_H_ +#define _FSL_SPI_DMA_H_ + +#include "fsl_spi.h" +#include "fsl_dma.h" + +/*! + * @addtogroup spi_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef struct _spi_dma_handle spi_dma_handle_t; + +/*! @brief SPI DMA callback called at the end of transfer. */ +typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _spi_dma_handle +{ + bool txInProgress; /*!< Send transfer finished */ + bool rxInProgress; /*!< Receive transfer finished */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */ + spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ + uint32_t state; /*!< Internal state of SPI DMA transfer */ + size_t transferSize; /*!< Bytes need to be transfer */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +void SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); + +/*! + * @brief Get the transferred bytes for SPI slave DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param count Transferred bytes. + * @retval kStatus_SPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); + +/*! + * @brief Initialize the SPI slave DMA handle. + * + * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +static inline void SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferDMA(base, handle, xfer); +} + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Get the transferred bytes for SPI slave DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param count Transferred bytes. + * @retval kStatus_SPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c new file mode 100755 index 00000000000..8a7abea621c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c @@ -0,0 +1,656 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_tpm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define TPM_COMBINE_SHIFT (8U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base TPM peripheral base address + * + * @return The TPM instance + */ +static uint32_t TPM_GetInstance(TPM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to TPM bases for each instance. */ +static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS; + +/*! @brief Pointers to TPM clocks for each instance. */ +static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t TPM_GetInstance(TPM_Type *base) +{ + uint32_t instance; + uint32_t tpmArrayCount = (sizeof(s_tpmBases) / sizeof(s_tpmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < tpmArrayCount; instance++) + { + if (s_tpmBases[instance] == base) + { + break; + } + } + + assert(instance < tpmArrayCount); + + return instance; +} + +void TPM_Init(TPM_Type *base, const tpm_config_t *config) +{ + assert(config); + + /* Enable the module clock */ + CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]); + +#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL + /* TPM reset is available on certain SoC's */ + TPM_Reset(base); +#endif + + /* Set the clock prescale factor */ + base->SC = TPM_SC_PS(config->prescale); + + /* Setup the counter operation */ + base->CONF = TPM_CONF_DOZEEN(config->enableDoze) | TPM_CONF_DBGMODE(config->enableDebugMode) | + TPM_CONF_GTBEEN(config->useGlobalTimeBase) | TPM_CONF_CROT(config->enableReloadOnTrigger) | + TPM_CONF_CSOT(config->enableStartOnTrigger) | TPM_CONF_CSOO(config->enableStopOnOverflow) | +#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + TPM_CONF_CPOT(config->enablePauseOnTrigger) | +#endif +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + TPM_CONF_TRGSRC(config->triggerSource) | +#endif + TPM_CONF_TRGSEL(config->triggerSelect); +} + +void TPM_Deinit(TPM_Type *base) +{ + /* Stop the counter */ + base->SC &= ~TPM_SC_CMOD_MASK; + /* Gate the TPM clock */ + CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]); +} + +void TPM_GetDefaultConfig(tpm_config_t *config) +{ + assert(config); + + /* TPM clock divide by 1 */ + config->prescale = kTPM_Prescale_Divide_1; + /* Use internal TPM counter as timebase */ + config->useGlobalTimeBase = false; + /* TPM counter continues in doze mode */ + config->enableDoze = false; + /* TPM counter pauses when in debug mode */ + config->enableDebugMode = false; + /* TPM counter will not be reloaded on input trigger */ + config->enableReloadOnTrigger = false; + /* TPM counter continues running after overflow */ + config->enableStopOnOverflow = false; + /* TPM counter starts immediately once it is enabled */ + config->enableStartOnTrigger = false; +#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + config->enablePauseOnTrigger = false; +#endif + /* Choose trigger select 0 as input trigger for controlling counter operation */ + config->triggerSelect = kTPM_Trigger_Select_0; +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + /* Choose external trigger source to control counter operation */ + config->triggerSource = kTPM_TriggerSource_External; +#endif +} + +status_t TPM_SetupPwm(TPM_Type *base, + const tpm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + tpm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + + uint32_t mod; + uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK))); + uint16_t cnv; + uint8_t i; + + switch (mode) + { + case kTPM_EdgeAlignedPwm: +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + case kTPM_CombinedPwm: +#endif + base->SC &= ~TPM_SC_CPWMS_MASK; + mod = (tpmClock / pwmFreq_Hz) - 1; + break; + case kTPM_CenterAlignedPwm: + base->SC |= TPM_SC_CPWMS_MASK; + mod = tpmClock / (pwmFreq_Hz * 2); + break; + default: + return kStatus_Fail; + } + + /* Return an error in case we overflow the registers, probably would require changing + * clock source to get the desired frequency */ + if (mod > 65535U) + { + return kStatus_Fail; + } + /* Set the PWM period */ + base->MOD = mod; + + /* Setup each TPM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Return error if requested dutycycle is greater than the max allowed */ + if (chnlParams->dutyCyclePercent > 100) + { + return kStatus_Fail; + } +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + if (mode == kTPM_CombinedPwm) + { + uint16_t cnvFirstEdge; + + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlParams->chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) + { + return kStatus_Fail; + } + + /* Return error if requested value is greater than the max allowed */ + if (chnlParams->firstEdgeDelayPercent > 100) + { + return kStatus_Fail; + } + /* Configure delay of the first edge */ + if (chnlParams->firstEdgeDelayPercent == 0) + { + /* No delay for the first edge */ + cnvFirstEdge = 0; + } + else + { + cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; + } + /* Configure dutycycle */ + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + cnvFirstEdge = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + /* Set the channel pair values */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + + /* Set the combine bit for the channel pair */ + base->COMBINE |= (1U << (TPM_COMBINE_COMBINE0_SHIFT + (TPM_COMBINE_SHIFT * chnlParams->chnlNumber))); + + /* When switching mode, disable channel n first */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Set the requested PWM mode for channel n, PWM output requires mode select to be set to 2 */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC |= + ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* When switching mode, disable channel n + 1 first */ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Set the requested PWM mode for channel n + 1, PWM output requires mode select to be set to 2 */ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC |= + ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + } + else + { +#endif + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlParams->chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Set the requested PWM mode, PWM output requires mode select to be set to 2 */ + base->CONTROLS[chnlParams->chnlNumber].CnSC |= + ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlParams->chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + } +#endif + + chnlParams++; + } + + return kStatus_Success; +} + +void TPM_UpdatePwmDutycycle(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + + uint16_t cnv, mod; + + mod = base->MOD; +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + if (currentPwmMode == kTPM_CombinedPwm) + { + uint16_t cnvFirstEdge; + + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) + { + return; + } + cnv = (mod * dutyCyclePercent) / 100; + cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + } + else + { +#endif + cnv = (mod * dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[chnlNumber].CnV = cnv; +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + } +#endif +} + +void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + + uint32_t reg = base->CONTROLS[chnlNumber].CnSC & ~(TPM_CnSC_CHF_MASK); + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + /* Wait till mode change is acknowledged */ + while (0U != (base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Clear the field and write the new level value */ + reg &= ~(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + reg |= ((uint32_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + base->CONTROLS[chnlNumber].CnSC = reg; + + /* Wait till mode change is acknowledged */ + reg &= (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + while (reg != (base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} + +void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Set the requested input capture mode */ + base->CONTROLS[chnlNumber].CnSC |= captureMode; + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} + +void TPM_SetupOutputCompare(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_output_compare_mode_t compareMode, + uint32_t compareValue) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + + /* Setup the compare value */ + base->CONTROLS[chnlNumber].CnV = compareValue; + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Setup the channel output behaviour when a match occurs with the compare value */ + base->CONTROLS[chnlNumber].CnSC |= compareMode; + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE +void TPM_SetupDualEdgeCapture(TPM_Type *base, + tpm_chnl_t chnlPairNumber, + const tpm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue) +{ + assert(edgeParam); + + uint32_t reg; + + /* Unlock: When switching mode, disable channel first */ + base->CONTROLS[chnlPairNumber * 2].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + /* Wait till mode change is acknowledged */ + while (0U != (base->CONTROLS[chnlPairNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + /* Wait till mode change is acknowledged */ + while (0U != (base->CONTROLS[chnlPairNumber * 2 + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + /* Now, the registers for input mode can be operated. */ + + if (edgeParam->enableSwap) + { + /* Set the combine and swap bits for the channel pair */ + base->COMBINE |= (TPM_COMBINE_COMBINE0_MASK | TPM_COMBINE_COMSWAP0_MASK) + << (TPM_COMBINE_SHIFT * chnlPairNumber); + + /* Input filter setup for channel n+1 input */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); + reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); + base->FILTER = reg; + } + else + { + reg = base->COMBINE; + /* Clear the swap bit for the channel pair */ + reg &= ~(TPM_COMBINE_COMSWAP0_MASK << (TPM_COMBINE_COMSWAP0_SHIFT * chnlPairNumber)); + + /* Set the combine bit for the channel pair */ + reg |= TPM_COMBINE_COMBINE0_MASK << (TPM_COMBINE_SHIFT * chnlPairNumber); + base->COMBINE = reg; + + /* Input filter setup for channel n input */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + base->FILTER = reg; + } + + /* Setup the edge detection from channel n */ + base->CONTROLS[chnlPairNumber * 2].CnSC |= edgeParam->currChanEdgeMode; + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlPairNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Setup the edge detection from channel n+1 */ + base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC |= edgeParam->nextChanEdgeMode; + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} +#endif + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL +void TPM_SetupQuadDecode(TPM_Type *base, + const tpm_phase_params_t *phaseAParams, + const tpm_phase_params_t *phaseBParams, + tpm_quad_decode_mode_t quadMode) +{ + assert(phaseAParams); + assert(phaseBParams); + + uint32_t reg; + + /* Set Phase A filter value */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH0FVAL_MASK); + reg |= TPM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); + base->FILTER = reg; + + /* Set Phase A polarity */ + if (phaseAParams->phasePolarity) + { + base->POL |= TPM_POL_POL0_MASK; + } + else + { + base->POL &= ~TPM_POL_POL0_MASK; + } + + /* Set Phase B filter value */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH1FVAL_MASK); + reg |= TPM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); + base->FILTER = reg; + + /* Set Phase B polarity */ + if (phaseBParams->phasePolarity) + { + base->POL |= TPM_POL_POL1_MASK; + } + else + { + base->POL &= ~TPM_POL_POL1_MASK; + } + + /* Set Quadrature mode */ + reg = base->QDCTRL; + reg &= ~(TPM_QDCTRL_QUADMODE_MASK); + reg |= TPM_QDCTRL_QUADMODE(quadMode); + base->QDCTRL = reg; + + /* Enable Quad decode */ + base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK; +} + +#endif + +void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask) +{ + uint32_t chnlInterrupts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Enable the timer overflow interrupt */ + if (mask & kTPM_TimeOverflowInterruptEnable) + { + base->SC |= TPM_SC_TOIE_MASK; + } + + /* Enable the channel interrupts */ + while (chnlInterrupts) + { + if (chnlInterrupts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInterrupts = chnlInterrupts >> 1U; + } +} + +void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask) +{ + uint32_t chnlInterrupts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Disable the timer overflow interrupt */ + if (mask & kTPM_TimeOverflowInterruptEnable) + { + base->SC &= ~TPM_SC_TOIE_MASK; + } + + /* Disable the channel interrupts */ + while (chnlInterrupts) + { + if (chnlInterrupts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInterrupts = chnlInterrupts >> 1U; + } +} + +uint32_t TPM_GetEnabledInterrupts(TPM_Type *base) +{ + uint32_t enabledInterrupts = 0; + int8_t chnlCount = FSL_FEATURE_TPM_CHANNEL_COUNTn(base); + + /* The CHANNEL_COUNT macro returns -1 if it cannot match the TPM instance */ + assert(chnlCount != -1); + + /* Check if timer overflow interrupt is enabled */ + if (base->SC & TPM_SC_TOIE_MASK) + { + enabledInterrupts |= kTPM_TimeOverflowInterruptEnable; + } + + /* Check if the channel interrupts are enabled */ + while (chnlCount > 0) + { + chnlCount--; + if (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK) + { + enabledInterrupts |= (1U << chnlCount); + } + } + + return enabledInterrupts; +} + +uint32_t TPM_GetStatusFlags(TPM_Type *base) +{ + uint32_t statusFlags = 0; + + /* Check timer flag */ + if (base->SC & TPM_SC_TOF_MASK) + { + statusFlags |= kTPM_TimeOverflowFlag; + } + + statusFlags |= base->STATUS; + + return statusFlags; +} + +void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask) +{ + /* Clear the timer overflow flag */ + if (mask & kTPM_TimeOverflowFlag) + { + base->SC |= TPM_SC_TOF_MASK; + } + + /* Clear the channel status flags */ + base->STATUS = (mask & 0xFF); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h new file mode 100755 index 00000000000..50138a47a2a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_TPM_H_ +#define _FSL_TPM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup tpm_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +/*@}*/ + +/*! + * @brief List of TPM channels. + * @note Actual number of available channels is SoC dependent + */ +typedef enum _tpm_chnl +{ + kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/ + kTPM_Chnl_1, /*!< TPM channel number 1 */ + kTPM_Chnl_2, /*!< TPM channel number 2 */ + kTPM_Chnl_3, /*!< TPM channel number 3 */ + kTPM_Chnl_4, /*!< TPM channel number 4 */ + kTPM_Chnl_5, /*!< TPM channel number 5 */ + kTPM_Chnl_6, /*!< TPM channel number 6 */ + kTPM_Chnl_7 /*!< TPM channel number 7 */ +} tpm_chnl_t; + +/*! @brief TPM PWM operation modes */ +typedef enum _tpm_pwm_mode +{ + kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */ + kTPM_CenterAlignedPwm, /*!< Center aligned PWM */ +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + kTPM_CombinedPwm /*!< Combined PWM */ +#endif +} tpm_pwm_mode_t; + +/*! @brief TPM PWM output pulse mode: high-true, low-true or no output */ +typedef enum _tpm_pwm_level_select +{ + kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */ + kTPM_LowTrue, /*!< Low true pulses */ + kTPM_HighTrue /*!< High true pulses */ +} tpm_pwm_level_select_t; + +/*! @brief Options to configure a TPM channel's PWM signal */ +typedef struct _tpm_chnl_pwm_signal_param +{ + tpm_chnl_t chnlNumber; /*!< TPM channel to configure. + In combined mode (available in some SoC's, this represents the + channel pair number */ + tpm_pwm_level_select_t level; /*!< PWM output active level select */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure, leave as 0; Should be specified as + percentage of the PWM period */ +#endif +} tpm_chnl_pwm_signal_param_t; + +/*! + * @brief Trigger options available. + * + * This is used for both internal & external trigger sources (external option available in certain SoC's) + * + * @note The actual trigger options available is SoC-specific. + */ +typedef enum _tpm_trigger_select +{ + kTPM_Trigger_Select_0 = 0U, + kTPM_Trigger_Select_1, + kTPM_Trigger_Select_2, + kTPM_Trigger_Select_3, + kTPM_Trigger_Select_4, + kTPM_Trigger_Select_5, + kTPM_Trigger_Select_6, + kTPM_Trigger_Select_7, + kTPM_Trigger_Select_8, + kTPM_Trigger_Select_9, + kTPM_Trigger_Select_10, + kTPM_Trigger_Select_11, + kTPM_Trigger_Select_12, + kTPM_Trigger_Select_13, + kTPM_Trigger_Select_14, + kTPM_Trigger_Select_15 +} tpm_trigger_select_t; + +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION +/*! + * @brief Trigger source options available + * + * @note This selection is available only on some SoC's. For SoC's without this selection, the only + * trigger source available is internal triger. + */ +typedef enum _tpm_trigger_source +{ + kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */ + kTPM_TriggerSource_Internal /*!< Use internal trigger */ +} tpm_trigger_source_t; +#endif + +/*! @brief TPM output compare modes */ +typedef enum _tpm_output_compare_mode +{ + kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ + kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ + kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */ + kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */ + kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */ + kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */ +} tpm_output_compare_mode_t; + +/*! @brief TPM input capture edge */ +typedef enum _tpm_input_capture_edge +{ + kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */ + kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */ + kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ +} tpm_input_capture_edge_t; + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE +/*! + * @brief TPM dual edge capture parameters + * + * @note This mode is available only on some SoC's. + */ +typedef struct _tpm_dual_edge_capture_param +{ + bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored; + false: Use channel n input, channel n+1 input is ignored */ + tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ + tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ +} tpm_dual_edge_capture_param_t; +#endif + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL +/*! + * @brief TPM quadrature decode modes + * + * @note This mode is available only on some SoC's. + */ +typedef enum _tpm_quad_decode_mode +{ + kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ + kTPM_QuadCountAndDir /*!< Count and direction encoding mode */ +} tpm_quad_decode_mode_t; + +/*! @brief TPM quadrature phase polarities */ +typedef enum _tpm_phase_polarity +{ + kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ + kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */ +} tpm_phase_polarity_t; + +/*! @brief TPM quadrature decode phase parameters */ +typedef struct _tpm_phase_param +{ + uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */ + tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */ +} tpm_phase_params_t; +#endif + +/*! @brief TPM clock source selection*/ +typedef enum _tpm_clock_source +{ + kTPM_SystemClock = 1U, /*!< System clock */ + kTPM_ExternalClock /*!< External clock */ +} tpm_clock_source_t; + +/*! @brief TPM prescale value selection for the clock source*/ +typedef enum _tpm_clock_prescale +{ + kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ + kTPM_Prescale_Divide_2, /*!< Divide by 2 */ + kTPM_Prescale_Divide_4, /*!< Divide by 4 */ + kTPM_Prescale_Divide_8, /*!< Divide by 8 */ + kTPM_Prescale_Divide_16, /*!< Divide by 16 */ + kTPM_Prescale_Divide_32, /*!< Divide by 32 */ + kTPM_Prescale_Divide_64, /*!< Divide by 64 */ + kTPM_Prescale_Divide_128 /*!< Divide by 128 */ +} tpm_clock_prescale_t; + +/*! + * @brief TPM config structure + * + * This structure holds the configuration settings for the TPM peripheral. To initialize this + * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _tpm_config +{ + tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */ + bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled; + false: disabled */ + tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */ +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */ +#endif + bool enableDoze; /*!< true: TPM counter is paused in doze mode; + false: TPM counter continues in doze mode */ + bool enableDebugMode; /*!< true: TPM counter continues in debug mode; + false: TPM counter is paused in debug mode */ + bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger; + false: TPM counter not reloaded */ + bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow; + false: TPM counter continues running after overflow */ + bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected; + false: TPM counter starts immediately */ +#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted; + false: TPM counter continues running */ +#endif +} tpm_config_t; + +/*! @brief List of TPM interrupts */ +typedef enum _tpm_interrupt_enable +{ + kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/ + kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/ + kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/ + kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/ + kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/ + kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/ + kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/ + kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/ + kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/ +} tpm_interrupt_enable_t; + +/*! @brief List of TPM flags */ +typedef enum _tpm_status_flags +{ + kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */ + kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */ + kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */ + kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */ + kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */ + kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */ + kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */ + kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */ + kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */ +} tpm_status_flags_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the TPM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the TPM driver. + * + * @param base TPM peripheral base address + * @param config Pointer to user's TPM config structure. + */ +void TPM_Init(TPM_Type *base, const tpm_config_t *config); + +/*! + * @brief Stops the counter and gates the TPM clock + * + * @param base TPM peripheral base address + */ +void TPM_Deinit(TPM_Type *base); + +/*! + * @brief Fill in the TPM config struct with the default settings + * + * The default values are: + * @code + * config->prescale = kTPM_Prescale_Divide_1; + * config->useGlobalTimeBase = false; + * config->dozeEnable = false; + * config->dbgMode = false; + * config->enableReloadOnTrigger = false; + * config->enableStopOnOverflow = false; + * config->enableStartOnTrigger = false; + *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + * config->enablePauseOnTrigger = false; + *#endif + * config->triggerSelect = kTPM_Trigger_Select_0; + *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + * config->triggerSource = kTPM_TriggerSource_External; + *#endif + * @endcode + * @param config Pointer to user's TPM config structure. + */ +void TPM_GetDefaultConfig(tpm_config_t *config); + +/*! @}*/ + +/*! + * @name Channel mode operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters + * + * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this + * function to configure all the TPM channels that will be used to output a PWM signal + * + * @param base TPM peripheral base address + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in + * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz TPM counter clock in Hz + * + * @return kStatus_Success if the PWM setup was successful, + * kStatus_Error on failure + */ +status_t TPM_SetupPwm(TPM_Type *base, + const tpm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + tpm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Update the duty cycle of an active PWM signal + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number. In combined mode, this represents + * the channel pair number + * @param currentPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void TPM_UpdatePwmDutycycle(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Update the edge level selection for a channel + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number + * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. + * See the appropriate SoC reference manual for details about this field. + */ +void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level); + +/*! + * @brief Enables capturing an input signal on the channel using the function parameters. + * + * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into + * the CnV register. The user has to read the CnV register separately to get this value. + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number + * @param captureMode Specifies which edge to capture + */ +void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode); + +/*! + * @brief Configures the TPM to generate timed pulses. + * + * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel + * output is changed based on what is specified in the compareMode argument. + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number + * @param compareMode Action to take on the channel output when the compare condition is met + * @param compareValue Value to be programmed in the CnV register. + */ +void TPM_SetupOutputCompare(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_output_compare_mode_t compareMode, + uint32_t compareValue); + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE +/*! + * @brief Configures the dual edge capture mode of the TPM. + * + * This function allows to measure a pulse width of the signal on the input of channel of a + * channel pair. The filter function is disabled if the filterVal argument passed is zero. + * + * @param base TPM peripheral base address + * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3 + * @param edgeParam Sets up the dual edge capture function + * @param filterValue Filter value, specify 0 to disable filter. + */ +void TPM_SetupDualEdgeCapture(TPM_Type *base, + tpm_chnl_t chnlPairNumber, + const tpm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue); +#endif + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL +/*! + * @brief Configures the parameters and activates the quadrature decode mode. + * + * @param base TPM peripheral base address + * @param phaseAParams Phase A configuration parameters + * @param phaseBParams Phase B configuration parameters + * @param quadMode Selects encoding mode used in quadrature decoder mode + */ +void TPM_SetupQuadDecode(TPM_Type *base, + const tpm_phase_params_t *phaseAParams, + const tpm_phase_params_t *phaseBParams, + tpm_quad_decode_mode_t quadMode); +#endif + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected TPM interrupts. + * + * @param base TPM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::tpm_interrupt_enable_t + */ +void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected TPM interrupts. + * + * @param base TPM peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::tpm_interrupt_enable_t + */ +void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled TPM interrupts. + * + * @param base TPM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::tpm_interrupt_enable_t + */ +uint32_t TPM_GetEnabledInterrupts(TPM_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the TPM status flags + * + * @param base TPM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::tpm_status_flags_t + */ +uint32_t TPM_GetStatusFlags(TPM_Type *base); + +/*! + * @brief Clears the TPM status flags + * + * @param base TPM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::tpm_status_flags_t + */ +void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the TPM counter. + * + * + * @param base TPM peripheral base address + * @param clockSource TPM clock source; once clock source is set the counter will start running + */ +static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource) +{ + uint32_t reg = base->SC; + + reg &= ~(TPM_SC_CMOD_MASK); + reg |= TPM_SC_CMOD(clockSource); + base->SC = reg; +} + +/*! + * @brief Stops the TPM counter. + * + * @param base TPM peripheral base address + */ +static inline void TPM_StopTimer(TPM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(TPM_SC_CMOD_MASK); +} + +/*! @}*/ + +#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL +/*! + * @brief Performs a software reset on the TPM module. + * + * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.. + * + * @note TPM software reset is available on certain SoC's only + * + * @param base TPM peripheral base address + */ +static inline void TPM_Reset(TPM_Type *base) +{ + base->GLOBAL |= TPM_GLOBAL_RST_MASK; + base->GLOBAL &= ~TPM_GLOBAL_RST_MASK; +} +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_TPM_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c new file mode 100755 index 00000000000..b0b92399db4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c @@ -0,0 +1,1032 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy /* RX busy. */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ +static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS; +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; + +/* UART ISR for transactional APIs. */ +static uart_isr_t s_uartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + + assert(instance < uartArrayCount); + + return instance; +} + +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + uint16_t sbr; + uint8_t temp; + + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (config->baudRate_Bps * 16); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr; + + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + + if (kUART_ParityDisabled != config->parityMode) + { + temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode); + } + + base->C1 = temp; + +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Set tx/rx FIFO watermark */ + base->TWFIFO = config->txFifoWatermark; + base->RWFIFO = config->rxFifoWatermark; + + /* Enable tx/rx FIFO */ + base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK); + + /* Flush FIFO */ + base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); +#endif + + /* Enable TX/RX base on configure structure. */ + temp = base->C2; + + if (config->enableTx) + { + temp |= UART_C2_TE_MASK; + } + + if (config->enableRx) + { + temp |= UART_C2_RE_MASK; + } + + base->C2 = temp; +} + +void UART_Deinit(UART_Type *base) +{ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != base->TCFIFO) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->S1 & UART_S1_TC_MASK)) + { + } + + /* Disable the module. */ + base->C2 = 0; + + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +} + +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 1; +#endif + config->enableTx = false; + config->enableRx = false; +} + +void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t sbr; + uint8_t oldCtrl; + + /* Store C2 before disable Tx and Rx */ + oldCtrl = base->C2; + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (baudRate_Bps * 16); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr; + + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Restore C2. */ + base->C2 = oldCtrl; +} + +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH |= (mask & 0xFF); + base->C2 |= ((mask >> 8) & 0xFF); + base->C3 |= ((mask >> 16) & 0xFF); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO |= ((mask >> 24) & 0xFF); +#endif +} + +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH &= ~(mask & 0xFF); + base->C2 &= ~((mask >> 8) & 0xFF); + base->C3 &= ~((mask >> 16) & 0xFF); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO &= ~((mask >> 24) & 0xFF); +#endif +} + +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + uint32_t temp; + + temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + temp |= ((uint32_t)(base->CFIFO) << 24); +#endif + + return temp; +} + +uint32_t UART_GetStatusFlags(UART_Type *base) +{ + uint32_t status_flag; + + status_flag = base->S1 | ((uint32_t)(base->S2) << 8); + +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + status_flag |= ((uint32_t)(base->ED) << 16); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + status_flag |= ((uint32_t)(base->SFIFO) << 24); +#endif + + return status_flag; +} + +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) +{ + uint8_t reg = base->S2; + status_t status; + +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK); +#else + reg &= ~UART_S2_RXEDGIF_MASK; +#endif + + base->S2 = reg | (uint8_t)(mask >> 8); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->SFIFO = (uint8_t)(mask >> 24); +#endif + + if (mask & (kUART_IdleLineFlag | kUART_RxOverrunFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | + kUART_ParityErrorFlag)) + { + /* Read base->D to clear the flags. */ + (void)base->S1; + (void)base->D; + } + + /* If some flags still pending. */ + if (mask & UART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag, + kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, + kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */ + status = kStatus_UART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->S1 & UART_S1_TDRE_MASK)) + { + } + base->D = *(data++); + } +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->D = data[i]; + } +} + +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + + while (length--) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + while (!base->RCFIFO) +#else + while (!(base->S1 & UART_S1_RDRF_MASK)) +#endif + { + statusFlag = UART_GetStatusFlags(base); + + if (statusFlag & kUART_RxOverrunFlag) + { + return kStatus_UART_RxHardwareOverrun; + } + + if (statusFlag & kUART_NoiseErrorFlag) + { + return kStatus_UART_NoiseError; + } + + if (statusFlag & kUART_FramingErrorFlag) + { + return kStatus_UART_FramingError; + } + + if (statusFlag & kUART_ParityErrorFlag) + { + return kStatus_UART_ParityError; + } + } + *(data++) = base->D; + } + + return kStatus_Success; +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = base->D; + } +} + +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->RWFIFO = 1U; +#endif + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_uartIRQ[instance]); +} + +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ringbuffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } +} + +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kUART_RxIdle) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kUART_TxIdle; +} + +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + } + + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + + /* Enable RX interrupt. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + + assert(handle); + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->D; + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = base->RCFIFO; +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->D; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO; +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->C2 = (base->C2 & ~UART_C2_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } + } + } +} + +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) +{ + /* TODO: To be implemented. */ +} + +#if defined(UART0) +#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \ + ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0))) +void UART0_DriverIRQHandler(void) +{ + s_uartIsr(UART0, s_uartHandle[0]); +} + +void UART0_RX_TX_DriverIRQHandler(void) +{ + UART0_DriverIRQHandler(); +} +#endif +#endif + +#if defined(UART1) +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[1]); +} + +void UART1_RX_TX_DriverIRQHandler(void) +{ + UART1_DriverIRQHandler(); +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[2]); +} + +void UART2_RX_TX_DriverIRQHandler(void) +{ + UART2_DriverIRQHandler(); +} + +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[3]); +} + +void UART3_RX_TX_DriverIRQHandler(void) +{ + UART3_DriverIRQHandler(); +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[4]); +} + +void UART4_RX_TX_DriverIRQHandler(void) +{ + UART4_DriverIRQHandler(); +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[5]); +} + +void UART5_RX_TX_DriverIRQHandler(void) +{ + UART5_DriverIRQHandler(); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h new file mode 100755 index 00000000000..3eec4e66b58 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h @@ -0,0 +1,757 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version 2.1.0. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _uart_status +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ +}; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0U, /*!< One stop bit */ + kUART_TwoStopBit = 1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! + * @brief UART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the UART interrupt configurations. + */ +enum _uart_interrupt_enable +{ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */ +#endif + kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */ + kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */ + kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */ + kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */ + kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */ + kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */ + kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */ + kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */ + kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */ + kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ + kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ +#endif +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum _uart_flags +{ + kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */ + kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */ + kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */ + kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */ + kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */ + kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit. + If any of these samples differ, noise flag sets */ + kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected + where stop bit expected */ + kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakFlag = + (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when + LIN break char detected and LIN circuit enabled */ +#endif + kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag, + sets when active edge detected */ + kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), + sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ + kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ + kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ + kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ + kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ + kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ +#endif +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate */ + uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with user configuration structure and peripheral clock. + * + * This function configures the UART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the UART_GetDefaultConfig() function. + * Example below shows how to use this API to configure UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 0; + * uartConfig.rxFifoWatermark = 1; + * UART_Init(UART1, &uartConfig, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + */ +void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->bitCountPerChar = kUART_8BitsPerChar; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 0; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source freqency in HZ. + */ +void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get UART status flags. + * + * This function get all UART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _uart_flags. To check specific status, + * compare the return value with enumerators in @ref _uart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART status flags which are ORed by the enumerators in the _uart_flags. + */ +uint32_t UART_GetStatusFlags(UART_Type *base); + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears UART status flags with a provided mask. Automatically cleared flag + * can't be cleared by this function. + * Some flags can only be cleared or set by hardware itself. These flags are: + * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, + * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, + * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base UART peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags. + * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX full interrupt: + * @code + * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * specific interrupts enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the UART data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base UART peripheral base address. + * @return UART data register address which are used both by transmitter and receiver. + */ +static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base) +{ + return (uint32_t) & (base->D); +} + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_TDMAS_MASK; +#else + base->C5 |= UART_C5_TDMAS_MASK; +#endif + base->C2 |= UART_C2_TIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_TDMAS_MASK; +#else + base->C5 &= ~UART_C5_TDMAS_MASK; +#endif + base->C2 &= ~UART_C2_TIE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA. + * + * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_RDMAS_MASK; +#else + base->C5 |= UART_C5_RDMAS_MASK; +#endif + base->C2 |= UART_C2_RIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_RDMAS_MASK; +#else + base->C5 &= ~UART_C5_RDMAS_MASK; +#endif + base->C2 &= ~UART_C2_RIE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_TE_MASK; + } + else + { + base->C2 &= ~UART_C2_TE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_RE_MASK; + } + else + { + base->C2 &= ~UART_C2_RE_MASK; + } +} + +/*! + * @brief Writes to the TX register. + * + * This function writes data to the TX register directly. The upper layer must ensure + * that the TX register is empty or TX FIFO has empty room before calling this function. + * + * @param base UART peripheral base address. + * @param data The byte to write. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->D = data; +} + +/*! + * @brief Reads the RX register directly. + * + * This function reads data from the TX register directly. The upper layer must + * ensure that the RX register is full or that the TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return The byte read from UART data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return base->D; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note This function does not check whether all the data has been sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_UART_NoiseError Noise error happened while receiving data. + * @retval kStatus_UART_FramingError Framing error happened while receiving data. + * @retval kStatus_UART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, refer to #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief UART Error IRQ handle function. + * + * This function handle the UART error IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c new file mode 100755 index 00000000000..c4a2f000a14 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart_dma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ + +/*base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(handle->base, handle->channel); + + uartPrivateHandle->handle->txState = kUART_TxIdle; + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle, + uartPrivateHandle->handle->userData); + } +} + +static void UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param) +{ + uart_dma_private_handle_t *uartPrivateHandle = (uart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + UART_EnableRxDMA(uartPrivateHandle->base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(handle->base, handle->channel); + + uartPrivateHandle->handle->rxState = kUART_RxIdle; + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle, + uartPrivateHandle->handle->userData); + } +} + +void UART_TransferCreateHandleDMA(UART_Type *base, + uart_dma_handle_t *handle, + uart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + assert(handle); + + uint32_t instance = UART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, DMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + DMA transfer because the water mark is 2. + */ + if (rxDmaHandle) + { + base->RWFIFO = 1U; + } +#endif + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Configure TX. */ + if (txDmaHandle) + { + DMA_SetCallback(txDmaHandle, UART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle) + { + DMA_SetCallback(rxDmaHandle, UART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } +} + +status_t UART_TransferSendDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle->txDmaHandle); + + dma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txState = kUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base), + sizeof(uint8_t), xfer->dataSize, kDMA_MemoryToPeripheral); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, kDMA_EnableInterrupt); + DMA_StartTransfer(handle->txDmaHandle); + + /* Enable UART TX DMA. */ + UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t UART_TransferReceiveDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle->rxDmaHandle); + + dma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + handle->rxState = kUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), xfer->dataSize, kDMA_PeripheralToMemory); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, kDMA_EnableInterrupt); + DMA_StartTransfer(handle->rxDmaHandle); + + /* Enable UART RX DMA. */ + UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSendDMA(UART_Type *base, uart_dma_handle_t *handle) +{ + assert(handle->txDmaHandle); + + /* Disable UART TX DMA. */ + UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag); + + handle->txState = kUART_TxIdle; +} + +void UART_TransferAbortReceiveDMA(UART_Type *base, uart_dma_handle_t *handle) +{ + assert(handle->rxDmaHandle); + + /* Disable UART RX DMA. */ + UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag); + + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetSendCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle->txDmaHandle); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +status_t UART_TransferGetReceiveCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle->rxDmaHandle); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h new file mode 100755 index 00000000000..cd26fa0f123 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_DMA_H_ +#define _FSL_UART_DMA_H_ + +#include "fsl_uart.h" +#include "fsl_dmamux.h" +#include "fsl_dma.h" + +/*! + * @addtogroup uart_dma_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_dma_handle uart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_dma_transfer_callback_t)(UART_Type *base, + uart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART DMA handle +*/ +struct _uart_dma_handle +{ + UART_Type *base; /*!< UART peripheral base address. */ + + uart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions and sets the callback. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_dma_handle_t structure. + * @param callback UART callback, NULL means no callback. + * @param userData User callback function data. + * @param rxDmaHandle User requested DMA handle for RX DMA transfer. + * @param txDmaHandle User requested DMA handle for TX DMA transfer. + */ +void UART_TransferCreateHandleDMA(UART_Type *base, + uart_dma_handle_t *handle, + uart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART DMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_dma_handle_t structure. + * @param xfer UART DMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the send data using DMA. + * + * This function aborts the sent data using DMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_dma_handle_t structure. + */ +void UART_TransferAbortSendDMA(UART_Type *base, uart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function abort receive data which using DMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to uart_dma_handle_t structure. + */ +void UART_TransferAbortReceiveDMA(UART_Type *base, uart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by DMA. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_DMA_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c new file mode 100755 index 00000000000..0854ca07577 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_vref.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base VREF peripheral base address + * + * @return The VREF instance + */ +static uint32_t VREF_GetInstance(VREF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to VREF bases for each instance. */ +static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; + +/*! @brief Pointers to VREF clocks for each instance. */ +static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t VREF_GetInstance(VREF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++) + { + if (s_vrefBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_VREF_COUNT); + + return instance; +} + +void VREF_Init(VREF_Type *base, const vref_config_t *config) +{ + assert(config != NULL); + + uint8_t reg = 0U; + + /* Ungate clock for VREF */ + CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); + +/* Configure VREF to a known state */ +#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC + /* Set chop oscillator bit */ + base->TRM |= VREF_TRM_CHOPEN_MASK; +#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ + reg = base->SC; + /* Set buffer Mode selection and Regulator enable bit */ + reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U); +#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION + /* Set second order curvature compensation enable bit */ + reg |= VREF_SC_ICOMPEN(1U); +#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ + /* Enable VREF module */ + reg |= VREF_SC_VREFEN(1U); + /* Update bit-field from value to Status and Control register */ + base->SC = reg; +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + reg = base->VREFL_TRM; + /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/ + reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK); + /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */ + reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef); + base->VREFL_TRM = reg; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} + +void VREF_Deinit(VREF_Type *base) +{ + /* Gate clock for VREF */ + CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); +} + +void VREF_GetDefaultConfig(vref_config_t *config) +{ +/* Set High power buffer mode in */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + config->bufferMode = kVREF_ModeHighPowerBuffer; +#else + config->bufferMode = kVREF_ModeTightRegulationBuffer; +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + /* Select internal voltage reference */ + config->enableExternalVoltRef = false; + /* Set VREFL (0.4 V) reference buffer disable */ + config->enableLowRef = false; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +} + +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) +{ + uint8_t reg = 0U; + + /* Set TRIM bits value in voltage reference */ + reg = base->TRM; + reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue)); + base->TRM = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) +{ + /* The values 111b and 110b are NOT valid/allowed */ + assert((trimValue != 0x7U) && (trimValue != 0x6U)); + + uint8_t reg = 0U; + + /* Set TRIM bits value in low voltage reference */ + reg = base->VREFL_TRM; + reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue)); + base->VREFL_TRM = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h new file mode 100755 index 00000000000..79378863bb6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_VREF_H_ +#define _FSL_VREF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup vref + * @{ + */ + +/*! @file */ + +/****************************************************************************** + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/* Those macros below defined to support SoC family which have VREFL (0.4V) reference */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +#define SC VREFH_SC +#define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV +#define VREF_SC_REGEN VREF_VREFH_SC_REGEN +#define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN +#define VREF_SC_ICOMPEN VREF_VREFH_SC_ICOMPEN +#define VREF_SC_REGEN_MASK VREF_VREFH_SC_REGEN_MASK +#define VREF_SC_VREFST_MASK VREF_VREFH_SC_VREFST_MASK +#define VREF_SC_VREFEN_MASK VREF_VREFH_SC_VREFEN_MASK +#define VREF_SC_MODE_LV_MASK VREF_VREFH_SC_MODE_LV_MASK +#define VREF_SC_ICOMPEN_MASK VREF_VREFH_SC_ICOMPEN_MASK +#define TRM VREFH_TRM +#define VREF_TRM_TRIM VREF_VREFH_TRM_TRIM +#define VREF_TRM_CHOPEN_MASK VREF_VREFH_TRM_CHOPEN_MASK +#define VREF_TRM_TRIM_MASK VREF_VREFH_TRM_TRIM_MASK +#define VREF_TRM_CHOPEN_SHIFT VREF_VREFH_TRM_CHOPEN_SHIFT +#define VREF_TRM_TRIM_SHIFT VREF_VREFH_TRM_TRIM_SHIFT +#define VREF_SC_MODE_LV_SHIFT VREF_VREFH_SC_MODE_LV_SHIFT +#define VREF_SC_REGEN_SHIFT VREF_VREFH_SC_REGEN_SHIFT +#define VREF_SC_VREFST_SHIFT VREF_VREFH_SC_VREFST_SHIFT +#define VREF_SC_ICOMPEN_SHIFT VREF_VREFH_SC_ICOMPEN_SHIFT +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*! + * @brief VREF modes. + */ +typedef enum _vref_buffer_mode +{ + kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + kVREF_ModeHighPowerBuffer = 1U, /*!< High power buffer mode enabled */ + kVREF_ModeLowPowerBuffer = 2U /*!< Low power buffer mode enabled */ +#else + kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */ +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ +} vref_buffer_mode_t; + +/*! + * @brief The description structure for the VREF module. + */ +typedef struct _vref_config +{ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + bool enableLowRef; /*!< Set VREFL (0.4 V) reference buffer enable or disable */ + bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +} vref_config_t; + +/****************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name VREF functional operation + * @{ + */ + +/*! + * @brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all the other VREF driver functions, + * read/write registers, and configurations with user-defined settings. + * The example below shows how to set up vref_config_t parameters and + * how to call the VREF_Init function by passing in these parameters: + * Example: + * @code + * vref_config_t vrefConfig; + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig.enableExternalVoltRef = false; + * vrefConfig.enableLowRef = false; + * VREF_Init(VREF, &vrefConfig); + * @endcode + * + * @param base VREF peripheral address. + * @param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config); + +/*! + * @brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * Example: + * @code + * vref_config_t vrefUserConfig; + * VREF_Init(VREF); + * VREF_GetDefaultConfig(&vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * @endcode + * + * @param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base); + +/*! + * @brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to a default value. + * Example: + * @code + * vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig->enableExternalVoltRef = false; + * vrefConfig->enableLowRef = false; + * @endcode + * + * @param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config); + +/*! + * @brief Sets a TRIM value for reference voltage. + * + * This function sets a TRIM value for reference voltage. + * Note that the TRIM value maximum is 0x3F. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the TRM register. + * + * @param base VREF peripheral address. + * @return Six-bit value of trim setting. + */ +static inline uint8_t VREF_GetTrimVal(VREF_Type *base) +{ + return (base->TRM & VREF_TRM_TRIM_MASK); +} +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + +/*! + * @brief Sets the TRIM value for low voltage reference. + * + * This function sets the TRIM value for low reference voltage. + * NOTE: + * - The TRIM value maximum is 0x05U + * - The values 111b and 110b are not valid/allowed. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)). + */ +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the VREFL_TRM register. + * + * @param base VREF peripheral address. + * @return Three-bit value of the trim setting. + */ +static inline uint8_t VREF_GetLowReferenceTrimVal(VREF_Type *base) +{ + return (base->VREFL_TRM & VREF_VREFL_TRM_VREFL_TRIM_MASK); +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_VREF_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h new file mode 100755 index 00000000000..93be44de1b2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PERIPHERAL_CLOCK_H_ +#define _FSL_PERIPHERAL_CLOCK_H_ + +#include "fsl_clock.h" + +/* Array for UART module clocks */ +#define UART_CLOCK_FREQS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, UART2_CLK_SRC \ + } + +/* Array for LPUART module clocks */ +#define LPUART_CLOCK_FREQS \ + { \ + kCLOCK_McgIrc48MClk, kCLOCK_McgIrc48MClk \ + } + +/* Array for I2C module clocks */ +#define I2C_CLOCK_FREQS \ + { \ + I2C0_CLK_SRC, I2C1_CLK_SRC \ + } + +/* Array for DSPI module clocks */ +#define SPI_CLOCK_FREQS \ + { \ + SPI0_CLK_SRC, SPI1_CLK_SRC \ + } + +#endif /* _FSL_PERIPHERAL_CLOCK_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/serial_api.c new file mode 100644 index 00000000000..7e48db79861 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/serial_api.c @@ -0,0 +1,256 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_lpuart.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" +#include "fsl_clock_config.h" + +static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; +static uart_irq_handler irq_handler; +/* Array of UART peripheral base address. */ +static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; +/* Array of LPUART bus clock frequencies */ +static clock_name_t const uart_clocks[] = LPUART_CLOCK_FREQS; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + + // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init + if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) + BOARD_BootClockRUN(); + + /* Set the LPUART clock source */ + if (obj->index == LPUART_0) { + CLOCK_SetLpuart0Clock(1U); + } else { + CLOCK_SetLpuart1Clock(1U); + } + + lpuart_config_t config; + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = 9600; + config.enableTx = false; + config.enableRx = false; + + LPUART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + LPUART_EnableTx(uart_addrs[obj->index], true); + pin_mode(tx, PullUp); + } + if (rx != NC) { + LPUART_EnableRx(uart_addrs[obj->index], true); + pin_mode(rx, PullUp); + } + + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + LPUART_Deinit(uart_addrs[obj->index]); + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) { + LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index])); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + LPUART_Type *base = uart_addrs[obj->index]; + uint8_t temp; + /* Set bit count and parity mode. */ + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); + if (parity != ParityNone) + { + /* Enable Parity */ + temp |= (LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK); + if (parity == ParityOdd) { + temp |= LPUART_CTRL_PT_MASK; + } else { + // Hardware does not support forced parity + MBED_ASSERT(0); + } + } + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)--stop_bits); +#endif +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) { + LPUART_Type *base = uart_addrs[index]; + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & base->STAT) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->DATA; + LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); + } + + if (serial_irq_ids[index] != 0) { + if (transmit_empty) + irq_handler(serial_irq_ids[index], TxIrq); + + if (receive_full) + irq_handler(serial_irq_ids[index], RxIrq); + } +} + +void uart0_irq() { + uint32_t status_flags = LPUART0->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0); +} + +void uart1_irq() { + uint32_t status_flags = LPUART1->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS; + uint32_t vector = 0; + + switch (obj->index) { + case 0: + vector = (uint32_t)&uart0_irq; + break; + case 1: + vector = (uint32_t)&uart1_irq; + break; + default: + break; + } + + if (enable) { + switch (irq) { + case RxIrq: + LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + NVIC_SetVector(uart_irqs[obj->index], vector); + NVIC_EnableIRQ(uart_irqs[obj->index]); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: + LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + switch (other_irq) { + case RxIrq: + all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_RxDataRegFullInterruptEnable) == 0); + break; + case TxIrq: + all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_TxDataRegEmptyInterruptEnable) == 0); + break; + default: + break; + } + if (all_disabled) + NVIC_DisableIRQ(uart_irqs[obj->index]); + } +} + +int serial_getc(serial_t *obj) { + uint8_t data; + + LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1); + return data; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c); +} + +int serial_readable(serial_t *obj) { + uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kLPUART_RxOverrunFlag) + LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag); + return (status_flags & kLPUART_RxDataRegFullFlag); +} + +int serial_writable(serial_t *obj) { + uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kLPUART_RxOverrunFlag) + LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag); + return (status_flags & kLPUART_TxDataRegEmptyFlag); +} + +void serial_clear(serial_t *obj) { +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) { + uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK; +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c new file mode 100644 index 00000000000..19404ced607 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c @@ -0,0 +1,131 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_assert.h" + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "fsl_spi.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" + +/* Array of SPI peripheral base address. */ +static SPI_Type *const spi_address[] = SPI_BASE_PTRS; +/* Array of SPI bus clock frequencies */ +static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + + obj->instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) { + SPI_Deinit(spi_address[obj->instance]); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + + spi_master_config_t master_config; + spi_slave_config_t slave_config; + + if ((bits != 8) || (bits != 16)) { + error("Only 8bits and 16bits SPI supported"); + return; + } + + if (slave) { + /* Slave config */ + SPI_SlaveGetDefaultConfig(&slave_config); + slave_config.dataMode = (bits == 16) ? kSPI_16BitMode : kSPI_8BitMode; + slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; + slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; + + SPI_SlaveInit(spi_address[obj->instance], &slave_config); + } else { + /* Master config */ + SPI_MasterGetDefaultConfig(&master_config); + master_config.dataMode = (bits == 16) ? kSPI_16BitMode : kSPI_8BitMode; + master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; + master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; + master_config.direction = kSPI_MsbFirst; + + SPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance])); + } +} + +void spi_frequency(spi_t *obj, int hz) { + SPI_MasterSetBaudRate(spi_address[obj->instance], (uint32_t)hz, CLOCK_GetFreq(spi_clocks[obj->instance])); +} + +static inline int spi_readable(spi_t * obj) { + return (SPI_GetStatusFlags(spi_address[obj->instance]) & kSPI_RxBufferFullFlag); +} + +int spi_master_write(spi_t *obj, int value) { + spi_transfer_t xfer = {0}; + uint32_t rx_data; + SPI_Type *base = spi_address[obj->instance]; + + /* SPI master start transfer */ + xfer.txData = (uint8_t *)&value; + xfer.rxData = (uint8_t *)&rx_data; + xfer.dataSize = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; + SPI_MasterTransferBlocking(base, &xfer); + + return rx_data & 0xffff; +} + +int spi_slave_receive(spi_t *obj) { + return spi_readable(obj); +} + +int spi_slave_read(spi_t *obj) { + uint32_t rx_data; + + while (!spi_readable(obj)); + rx_data = SPI_ReadData(spi_address[obj->instance]); + + return rx_data & 0xffff; +} + +void spi_slave_write(spi_t *obj, int value) { + SPI_Type *base = spi_address[obj->instance]; + size_t size = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; + SPI_WriteBlocking(spi_address[obj->instance], (uint8_t *)&value, size); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c new file mode 100644 index 00000000000..180a72f7c13 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c @@ -0,0 +1,95 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "fsl_pit.h" +#include "fsl_lptmr.h" +#include "fsl_clock_config.h" + +static int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) { + return; + } + us_ticker_inited = 1; + + // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init + if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) + BOARD_BootClockRUN(); + + //Timer uses PIT + //Common for ticker/timer + uint32_t busClock; + + // Structure to initialize PIT + pit_config_t pitConfig; + + PIT_GetDefaultConfig(&pitConfig); + PIT_Init(PIT, &pitConfig); + + busClock = CLOCK_GetFreq(kCLOCK_BusClk); + + PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); + PIT_StartTimer(PIT, kPIT_Chnl_0); + PIT_StartTimer(PIT, kPIT_Chnl_1); + + //Ticker uses LPTMR + lptmr_config_t lptmrConfig; + LPTMR_GetDefaultConfig(&lptmrConfig); + lptmrConfig.prescalerClockSource = kLPTMR_PrescalerClock_0; + LPTMR_Init(LPTMR0, &lptmrConfig); + + busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk); + LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1); + /* Set interrupt handler */ + NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(LPTMR0_IRQn); +} + + +uint32_t us_ticker_read() { + if (!us_ticker_inited) { + us_ticker_init(); + } + + return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1)); +} + +void us_ticker_disable_interrupt(void) { + LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); +} + +void us_ticker_clear_interrupt(void) { + LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int delta = (int)(timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past: + us_ticker_irq_handler(); + return; + } + + LPTMR_StopTimer(LPTMR0); + LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta); + LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); + LPTMR_StartTimer(LPTMR0); +} diff --git a/libraries/rpc/parse_pins.cpp b/libraries/rpc/parse_pins.cpp index bc86964f701..1168f5c012f 100644 --- a/libraries/rpc/parse_pins.cpp +++ b/libraries/rpc/parse_pins.cpp @@ -48,7 +48,7 @@ PinName parse_pins(const char *str) { } return port_pin((PortName)port, pin); -#elif defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_K64F) +#elif defined(TARGET_KL25Z) || defined(TARGET_KL27Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_K22F) || defined(TARGET_K64F) if (str[0] == 'P' && str[1] == 'T') { // PTxn uint32_t port = str[2] - 'A'; uint32_t pin = str[3] - '0'; // PTxn diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index bd2f0e5b721..bf676375a72 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -223,6 +223,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_KL26Z) #define INITIAL_SP (0x20003000UL) +#elif defined(TARGET_KL27Z) +#define INITIAL_SP (0x20003000UL) + #elif defined(TARGET_K64F) #define INITIAL_SP (0x20030000UL) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index c8295fcecd5..cad4e04bfe0 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -55,7 +55,7 @@ || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32L152RC) # define OS_TASKCNT 14 # elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ - || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ + || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL27Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \ || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \ || defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB) @@ -73,7 +73,7 @@ || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32L152RC) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ - || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ + || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL27Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \ || defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB) # define OS_SCHEDULERSTKSIZE 128 @@ -130,7 +130,7 @@ # define OS_CLOCK 64000000 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) \ - || defined(TARGET_KL26Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) + || defined(TARGET_KL26Z) || defined(TARGET_KL27Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) # define OS_CLOCK 48000000 # elif defined(TARGET_LPC812) diff --git a/libraries/tests/mbed/i2c_eeprom/main.cpp b/libraries/tests/mbed/i2c_eeprom/main.cpp index 06c589906da..dea4474fb58 100644 --- a/libraries/tests/mbed/i2c_eeprom/main.cpp +++ b/libraries/tests/mbed/i2c_eeprom/main.cpp @@ -24,6 +24,9 @@ #if defined(TARGET_KL25Z) I2C i2c(PTC9, PTC8); +#elif defined(TARGET_KL27Z) +I2C i2c(PTD6, PTD7); + #elif defined(TARGET_KL46Z) I2C i2c(PTC9, PTC8); diff --git a/libraries/tests/mbed/i2c_eeprom_line/main.cpp b/libraries/tests/mbed/i2c_eeprom_line/main.cpp index 67c66f2ed6c..e31b9b5480c 100644 --- a/libraries/tests/mbed/i2c_eeprom_line/main.cpp +++ b/libraries/tests/mbed/i2c_eeprom_line/main.cpp @@ -34,6 +34,9 @@ const int i2c_delay_us = 0; #if defined(TARGET_KL25Z) I2C i2c(PTC9, PTC8); +#elif defined(TARGET_KL27Z) +I2C i2c(PTD6, PTD7); + #elif defined(TARGET_KL46Z) I2C i2c(PTC9, PTC8); diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index b7a279bac6a..5e509da1fb9 100644 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -59,6 +59,7 @@ ('KL05Z', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), ('KL25Z', ('ARM', 'GCC_ARM', 'IAR')), + ('KL27Z', ('ARM', 'GCC_ARM', 'IAR')), ('KL43Z', ('ARM', 'GCC_ARM')), ('KL46Z', ('ARM', 'GCC_ARM', 'IAR')), ('K64F', ('ARM', 'GCC_ARM', 'IAR')), diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index d64219dd00b..233cc1ea0f1 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -83,6 +83,7 @@ { "target": "KL05Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "KL25Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, + { "target": "KL27Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "KL43Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "KL46Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "K20D50M", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 51d6c8c67df..06346bb97c5 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -581,6 +581,21 @@ def __init__(self): "target":"frdm-k22f", } +class KL27Z(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'FRDM'] + self.macros = ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM","GCC_ARM","IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0261"] + self.progen_target = { + "target":"frdm-kl27z", + } + class K64F(Target): def __init__(self): Target.__init__(self) @@ -2172,6 +2187,7 @@ def __init__(self): LPC4337(), LPC11U37H_401(), K22F(), + KL27Z(), K64F(), # FRDM K64F MTS_GAMBIT(), HEXIWEAR(), From fffadba3096ec22131b4e3ee0ab5547e1db8fb34 Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Mon, 4 Apr 2016 09:06:46 -0500 Subject: [PATCH 08/11] Moved SDK 2.0 platforms back to TARGET_Freescale from TARGET_NXP. Signed-off-by: Mahadevan Mahesh --- .../TARGET_K22F/MK22F51212.h | 0 .../TARGET_K22F/MK22F51212_features.h | 0 .../TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct | 0 .../TOOLCHAIN_ARM_STD/startup_MK22F51212.S | 0 .../TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp | 0 .../TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_MK22F51212.S | 0 .../TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf | 0 .../TOOLCHAIN_IAR/startup_MK22F12.S | 0 .../TARGET_K22F/cmsis.h | 0 .../TARGET_K22F/cmsis_nvic.c | 0 .../TARGET_K22F/cmsis_nvic.h | 0 .../TARGET_K22F/fsl_device_registers.h | 0 .../TARGET_K22F/system_MK22F51212.c | 0 .../TARGET_K22F/system_MK22F51212.h | 0 .../TARGET_K64F/MK64F12.h | 0 .../TARGET_K64F/MK64F12_features.h | 0 .../TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct | 0 .../TOOLCHAIN_ARM_STD/startup_MK64F12.S | 0 .../TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp | 0 .../TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_MK64F12.S | 0 .../TOOLCHAIN_IAR/MK64FN1M0xxx12.icf | 0 .../TOOLCHAIN_IAR/startup_MK64F12.S | 0 .../TARGET_K64F/cmsis.h | 0 .../TARGET_K64F/cmsis_nvic.c | 0 .../TARGET_K64F/cmsis_nvic.h | 0 .../TARGET_K64F/fsl_device_registers.h | 0 .../TARGET_K64F/system_MK64F12.c | 0 .../TARGET_K64F/system_MK64F12.h | 0 .../TARGET_KL27Z/MKL27Z644.h | 0 .../TARGET_KL27Z/MKL27Z644_features.h | 0 .../TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct | 0 .../TOOLCHAIN_ARM_STD/startup_MKL27Z644.S | 0 .../TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp | 0 .../TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S | 0 .../TOOLCHAIN_IAR/MKL27Z64xxx4.icf | 0 .../TOOLCHAIN_IAR/startup_MKL27Z644.S | 0 .../TARGET_KL27Z/cmsis.h | 0 .../TARGET_KL27Z/cmsis_nvic.c | 0 .../TARGET_KL27Z/cmsis_nvic.h | 0 .../TARGET_KL27Z/fsl_device_registers.h | 0 .../TARGET_KL27Z/system_MKL27Z644.c | 0 .../TARGET_KL27Z/system_MKL27Z644.h | 0 .../TARGET_K22F/TARGET_FRDM/PeripheralNames.h | 0 .../TARGET_K22F/TARGET_FRDM/PeripheralPins.c | 0 .../TARGET_K22F/TARGET_FRDM/PinNames.h | 0 .../TARGET_K22F/TARGET_FRDM/device.h | 0 .../TARGET_FRDM/fsl_clock_config.c | 0 .../TARGET_FRDM/fsl_clock_config.h | 0 .../TARGET_K22F/TARGET_FRDM/mbed_overrides.c | 0 .../TARGET_K22F/drivers/fsl_adc16.c | 0 .../TARGET_K22F/drivers/fsl_adc16.h | 0 .../TARGET_K22F/drivers/fsl_clock.c | 0 .../TARGET_K22F/drivers/fsl_clock.h | 0 .../TARGET_K22F/drivers/fsl_cmp.c | 0 .../TARGET_K22F/drivers/fsl_cmp.h | 0 .../TARGET_K22F/drivers/fsl_common.c | 0 .../TARGET_K22F/drivers/fsl_common.h | 0 .../TARGET_K22F/drivers/fsl_crc.c | 0 .../TARGET_K22F/drivers/fsl_crc.h | 0 .../TARGET_K22F/drivers/fsl_dac.c | 0 .../TARGET_K22F/drivers/fsl_dac.h | 0 .../TARGET_K22F/drivers/fsl_dmamux.c | 0 .../TARGET_K22F/drivers/fsl_dmamux.h | 0 .../TARGET_K22F/drivers/fsl_dspi.c | 0 .../TARGET_K22F/drivers/fsl_dspi.h | 0 .../TARGET_K22F/drivers/fsl_dspi_edma.c | 0 .../TARGET_K22F/drivers/fsl_dspi_edma.h | 0 .../TARGET_K22F/drivers/fsl_edma.c | 0 .../TARGET_K22F/drivers/fsl_edma.h | 0 .../TARGET_K22F/drivers/fsl_ewm.c | 0 .../TARGET_K22F/drivers/fsl_ewm.h | 0 .../TARGET_K22F/drivers/fsl_flash.c | 0 .../TARGET_K22F/drivers/fsl_flash.h | 0 .../TARGET_K22F/drivers/fsl_flexbus.c | 0 .../TARGET_K22F/drivers/fsl_flexbus.h | 0 .../TARGET_K22F/drivers/fsl_ftm.c | 0 .../TARGET_K22F/drivers/fsl_ftm.h | 0 .../TARGET_K22F/drivers/fsl_gpio.c | 0 .../TARGET_K22F/drivers/fsl_gpio.h | 0 .../TARGET_K22F/drivers/fsl_i2c.c | 0 .../TARGET_K22F/drivers/fsl_i2c.h | 0 .../TARGET_K22F/drivers/fsl_i2c_edma.c | 0 .../TARGET_K22F/drivers/fsl_i2c_edma.h | 0 .../TARGET_K22F/drivers/fsl_llwu.c | 0 .../TARGET_K22F/drivers/fsl_llwu.h | 0 .../TARGET_K22F/drivers/fsl_lptmr.c | 0 .../TARGET_K22F/drivers/fsl_lptmr.h | 0 .../TARGET_K22F/drivers/fsl_lpuart.c | 0 .../TARGET_K22F/drivers/fsl_lpuart.h | 0 .../TARGET_K22F/drivers/fsl_lpuart_edma.c | 0 .../TARGET_K22F/drivers/fsl_lpuart_edma.h | 0 .../TARGET_K22F/drivers/fsl_pdb.c | 0 .../TARGET_K22F/drivers/fsl_pdb.h | 0 .../TARGET_K22F/drivers/fsl_pit.c | 0 .../TARGET_K22F/drivers/fsl_pit.h | 0 .../TARGET_K22F/drivers/fsl_pmc.c | 0 .../TARGET_K22F/drivers/fsl_pmc.h | 0 .../TARGET_K22F/drivers/fsl_port.h | 0 .../TARGET_K22F/drivers/fsl_rcm.c | 0 .../TARGET_K22F/drivers/fsl_rcm.h | 0 .../TARGET_K22F/drivers/fsl_rnga.c | 0 .../TARGET_K22F/drivers/fsl_rnga.h | 0 .../TARGET_K22F/drivers/fsl_rtc.c | 0 .../TARGET_K22F/drivers/fsl_rtc.h | 0 .../TARGET_K22F/drivers/fsl_sai.c | 0 .../TARGET_K22F/drivers/fsl_sai.h | 0 .../TARGET_K22F/drivers/fsl_sai_edma.c | 0 .../TARGET_K22F/drivers/fsl_sai_edma.h | 0 .../TARGET_K22F/drivers/fsl_sim.c | 0 .../TARGET_K22F/drivers/fsl_sim.h | 0 .../TARGET_K22F/drivers/fsl_smc.c | 0 .../TARGET_K22F/drivers/fsl_smc.h | 0 .../TARGET_K22F/drivers/fsl_uart.c | 0 .../TARGET_K22F/drivers/fsl_uart.h | 0 .../TARGET_K22F/drivers/fsl_uart_edma.c | 0 .../TARGET_K22F/drivers/fsl_uart_edma.h | 0 .../TARGET_K22F/drivers/fsl_vref.c | 0 .../TARGET_K22F/drivers/fsl_vref.h | 0 .../TARGET_K22F/drivers/fsl_wdog.c | 0 .../TARGET_K22F/drivers/fsl_wdog.h | 0 .../TARGET_K22F/peripheral_clock_defines.h | 0 .../TARGET_K22F/serial_api.c | 0 .../TARGET_KSDK2_MCUS}/TARGET_K22F/spi_api.c | 0 .../TARGET_K22F/us_ticker.c | 7 +- .../TARGET_K64F/TARGET_FRDM/PeripheralNames.h | 0 .../TARGET_K64F/TARGET_FRDM/PeripheralPins.c | 0 .../TARGET_K64F/TARGET_FRDM/PinNames.h | 0 .../TARGET_K64F/TARGET_FRDM/crc.c | 0 .../TARGET_K64F/TARGET_FRDM/crc.h | 0 .../TARGET_K64F/TARGET_FRDM/device.h | 0 .../TARGET_FRDM/fsl_clock_config.c | 0 .../TARGET_FRDM/fsl_clock_config.h | 0 .../TARGET_K64F/TARGET_FRDM/mbed_overrides.c | 0 .../TARGET_HEXIWEAR/PeripheralNames.h | 0 .../TARGET_HEXIWEAR/PeripheralPins.c | 0 .../TARGET_K64F/TARGET_HEXIWEAR/PinNames.h | 0 .../TARGET_K64F/TARGET_HEXIWEAR/device.h | 0 .../TARGET_HEXIWEAR/fsl_clock_config.c | 0 .../TARGET_HEXIWEAR/fsl_clock_config.h | 0 .../TARGET_HEXIWEAR/mbed_overrides.c | 0 .../TARGET_MTS_GAMBIT/PeripheralNames.h | 0 .../TARGET_MTS_GAMBIT/PeripheralPins.c | 0 .../TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h | 0 .../TARGET_K64F/TARGET_MTS_GAMBIT/device.h | 0 .../TARGET_MTS_GAMBIT/fsl_clock_config.c | 0 .../TARGET_MTS_GAMBIT/fsl_clock_config.h | 0 .../TARGET_MTS_GAMBIT/mbed_overrides.c | 0 .../TARGET_K64F/drivers/fsl_adc16.c | 0 .../TARGET_K64F/drivers/fsl_adc16.h | 0 .../TARGET_K64F/drivers/fsl_clock.c | 0 .../TARGET_K64F/drivers/fsl_clock.h | 0 .../TARGET_K64F/drivers/fsl_cmp.c | 0 .../TARGET_K64F/drivers/fsl_cmp.h | 0 .../TARGET_K64F/drivers/fsl_cmt.c | 0 .../TARGET_K64F/drivers/fsl_cmt.h | 0 .../TARGET_K64F/drivers/fsl_common.c | 0 .../TARGET_K64F/drivers/fsl_common.h | 0 .../TARGET_K64F/drivers/fsl_crc.c | 0 .../TARGET_K64F/drivers/fsl_crc.h | 0 .../TARGET_K64F/drivers/fsl_dac.c | 0 .../TARGET_K64F/drivers/fsl_dac.h | 0 .../TARGET_K64F/drivers/fsl_dmamux.c | 0 .../TARGET_K64F/drivers/fsl_dmamux.h | 0 .../TARGET_K64F/drivers/fsl_dspi.c | 0 .../TARGET_K64F/drivers/fsl_dspi.h | 0 .../TARGET_K64F/drivers/fsl_dspi_edma.c | 0 .../TARGET_K64F/drivers/fsl_dspi_edma.h | 0 .../TARGET_K64F/drivers/fsl_edma.c | 0 .../TARGET_K64F/drivers/fsl_edma.h | 0 .../TARGET_K64F/drivers/fsl_enet.c | 0 .../TARGET_K64F/drivers/fsl_enet.h | 0 .../TARGET_K64F/drivers/fsl_ewm.c | 0 .../TARGET_K64F/drivers/fsl_ewm.h | 0 .../TARGET_K64F/drivers/fsl_flash.c | 0 .../TARGET_K64F/drivers/fsl_flash.h | 0 .../TARGET_K64F/drivers/fsl_flexbus.c | 0 .../TARGET_K64F/drivers/fsl_flexbus.h | 0 .../TARGET_K64F/drivers/fsl_flexcan.c | 0 .../TARGET_K64F/drivers/fsl_flexcan.h | 0 .../TARGET_K64F/drivers/fsl_flexcan_edma.c | 0 .../TARGET_K64F/drivers/fsl_flexcan_edma.h | 0 .../TARGET_K64F/drivers/fsl_ftm.c | 0 .../TARGET_K64F/drivers/fsl_ftm.h | 0 .../TARGET_K64F/drivers/fsl_gpio.c | 0 .../TARGET_K64F/drivers/fsl_gpio.h | 0 .../TARGET_K64F/drivers/fsl_i2c.c | 0 .../TARGET_K64F/drivers/fsl_i2c.h | 0 .../TARGET_K64F/drivers/fsl_i2c_edma.c | 0 .../TARGET_K64F/drivers/fsl_i2c_edma.h | 0 .../TARGET_K64F/drivers/fsl_llwu.c | 0 .../TARGET_K64F/drivers/fsl_llwu.h | 0 .../TARGET_K64F/drivers/fsl_lptmr.c | 0 .../TARGET_K64F/drivers/fsl_lptmr.h | 0 .../TARGET_K64F/drivers/fsl_mpu.c | 0 .../TARGET_K64F/drivers/fsl_mpu.h | 0 .../TARGET_K64F/drivers/fsl_pdb.c | 0 .../TARGET_K64F/drivers/fsl_pdb.h | 0 .../TARGET_K64F/drivers/fsl_pit.c | 0 .../TARGET_K64F/drivers/fsl_pit.h | 0 .../TARGET_K64F/drivers/fsl_pmc.c | 0 .../TARGET_K64F/drivers/fsl_pmc.h | 0 .../TARGET_K64F/drivers/fsl_port.h | 0 .../TARGET_K64F/drivers/fsl_rcm.c | 0 .../TARGET_K64F/drivers/fsl_rcm.h | 0 .../TARGET_K64F/drivers/fsl_rnga.c | 0 .../TARGET_K64F/drivers/fsl_rnga.h | 0 .../TARGET_K64F/drivers/fsl_rtc.c | 0 .../TARGET_K64F/drivers/fsl_rtc.h | 0 .../TARGET_K64F/drivers/fsl_sai.c | 0 .../TARGET_K64F/drivers/fsl_sai.h | 0 .../TARGET_K64F/drivers/fsl_sai_edma.c | 0 .../TARGET_K64F/drivers/fsl_sai_edma.h | 0 .../TARGET_K64F/drivers/fsl_sdhc.c | 0 .../TARGET_K64F/drivers/fsl_sdhc.h | 0 .../TARGET_K64F/drivers/fsl_sim.c | 0 .../TARGET_K64F/drivers/fsl_sim.h | 0 .../TARGET_K64F/drivers/fsl_smc.c | 0 .../TARGET_K64F/drivers/fsl_smc.h | 0 .../TARGET_K64F/drivers/fsl_uart.c | 0 .../TARGET_K64F/drivers/fsl_uart.h | 0 .../TARGET_K64F/drivers/fsl_uart_edma.c | 0 .../TARGET_K64F/drivers/fsl_uart_edma.h | 0 .../TARGET_K64F/drivers/fsl_vref.c | 0 .../TARGET_K64F/drivers/fsl_vref.h | 0 .../TARGET_K64F/drivers/fsl_wdog.c | 0 .../TARGET_K64F/drivers/fsl_wdog.h | 0 .../TARGET_K64F/peripheral_clock_defines.h | 0 .../TARGET_K64F/serial_api.c | 0 .../TARGET_KSDK2_MCUS}/TARGET_K64F/spi_api.c | 0 .../TARGET_K64F/us_ticker.c | 7 +- .../TARGET_FRDM/PeripheralNames.h | 0 .../TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c | 0 .../TARGET_KL27Z/TARGET_FRDM/PinNames.h | 0 .../TARGET_KL27Z/TARGET_FRDM/device.h | 0 .../TARGET_FRDM/fsl_clock_config.c | 0 .../TARGET_FRDM/fsl_clock_config.h | 0 .../TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c | 0 .../TARGET_KL27Z/drivers/fsl_adc16.c | 0 .../TARGET_KL27Z/drivers/fsl_adc16.h | 0 .../TARGET_KL27Z/drivers/fsl_clock.c | 0 .../TARGET_KL27Z/drivers/fsl_clock.h | 0 .../TARGET_KL27Z/drivers/fsl_cmp.c | 0 .../TARGET_KL27Z/drivers/fsl_cmp.h | 0 .../TARGET_KL27Z/drivers/fsl_common.c | 0 .../TARGET_KL27Z/drivers/fsl_common.h | 0 .../TARGET_KL27Z/drivers/fsl_cop.c | 0 .../TARGET_KL27Z/drivers/fsl_cop.h | 0 .../TARGET_KL27Z/drivers/fsl_crc.c | 0 .../TARGET_KL27Z/drivers/fsl_crc.h | 0 .../TARGET_KL27Z/drivers/fsl_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_dmamux.c | 0 .../TARGET_KL27Z/drivers/fsl_dmamux.h | 0 .../TARGET_KL27Z/drivers/fsl_flash.c | 0 .../TARGET_KL27Z/drivers/fsl_flash.h | 0 .../TARGET_KL27Z/drivers/fsl_flexio.c | 0 .../TARGET_KL27Z/drivers/fsl_flexio.h | 0 .../drivers/fsl_flexio_i2c_master.c | 0 .../drivers/fsl_flexio_i2c_master.h | 0 .../TARGET_KL27Z/drivers/fsl_flexio_i2s.c | 0 .../TARGET_KL27Z/drivers/fsl_flexio_i2s.h | 0 .../TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_flexio_spi.c | 0 .../TARGET_KL27Z/drivers/fsl_flexio_spi.h | 0 .../TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_flexio_uart.c | 0 .../TARGET_KL27Z/drivers/fsl_flexio_uart.h | 0 .../drivers/fsl_flexio_uart_dma.c | 0 .../drivers/fsl_flexio_uart_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_gpio.c | 0 .../TARGET_KL27Z/drivers/fsl_gpio.h | 0 .../TARGET_KL27Z/drivers/fsl_i2c.c | 0 .../TARGET_KL27Z/drivers/fsl_i2c.h | 0 .../TARGET_KL27Z/drivers/fsl_i2c_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_i2c_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_llwu.c | 0 .../TARGET_KL27Z/drivers/fsl_llwu.h | 0 .../TARGET_KL27Z/drivers/fsl_lptmr.c | 0 .../TARGET_KL27Z/drivers/fsl_lptmr.h | 0 .../TARGET_KL27Z/drivers/fsl_lpuart.c | 0 .../TARGET_KL27Z/drivers/fsl_lpuart.h | 0 .../TARGET_KL27Z/drivers/fsl_lpuart_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_lpuart_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_pit.c | 0 .../TARGET_KL27Z/drivers/fsl_pit.h | 0 .../TARGET_KL27Z/drivers/fsl_pmc.c | 0 .../TARGET_KL27Z/drivers/fsl_pmc.h | 0 .../TARGET_KL27Z/drivers/fsl_port.h | 0 .../TARGET_KL27Z/drivers/fsl_rcm.c | 0 .../TARGET_KL27Z/drivers/fsl_rcm.h | 0 .../TARGET_KL27Z/drivers/fsl_rtc.c | 0 .../TARGET_KL27Z/drivers/fsl_rtc.h | 0 .../TARGET_KL27Z/drivers/fsl_sim.c | 0 .../TARGET_KL27Z/drivers/fsl_sim.h | 0 .../TARGET_KL27Z/drivers/fsl_smc.c | 0 .../TARGET_KL27Z/drivers/fsl_smc.h | 0 .../TARGET_KL27Z/drivers/fsl_spi.c | 0 .../TARGET_KL27Z/drivers/fsl_spi.h | 0 .../TARGET_KL27Z/drivers/fsl_spi_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_spi_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_tpm.c | 0 .../TARGET_KL27Z/drivers/fsl_tpm.h | 0 .../TARGET_KL27Z/drivers/fsl_uart.c | 0 .../TARGET_KL27Z/drivers/fsl_uart.h | 0 .../TARGET_KL27Z/drivers/fsl_uart_dma.c | 0 .../TARGET_KL27Z/drivers/fsl_uart_dma.h | 0 .../TARGET_KL27Z/drivers/fsl_vref.c | 0 .../TARGET_KL27Z/drivers/fsl_vref.h | 0 .../TARGET_KL27Z/peripheral_clock_defines.h | 0 .../TARGET_KL27Z/serial_api.c | 0 .../TARGET_KSDK2_MCUS}/TARGET_KL27Z/spi_api.c | 0 .../TARGET_KL27Z/us_ticker.c | 7 +- .../TARGET_KSDK2_MCUS}/api/PeripheralPins.h | 0 .../TARGET_KSDK2_MCUS}/api/PortNames.h | 0 .../TARGET_KSDK2_MCUS}/api/analogin_api.c | 0 .../TARGET_KSDK2_MCUS}/api/analogout_api.c | 0 .../TARGET_KSDK2_MCUS}/api/gpio_api.c | 0 .../TARGET_KSDK2_MCUS}/api/gpio_irq_api.c | 0 .../TARGET_KSDK2_MCUS}/api/gpio_object.h | 0 .../TARGET_KSDK2_MCUS}/api/i2c_api.c | 0 .../TARGET_KSDK2_MCUS}/api/objects.h | 0 .../TARGET_KSDK2_MCUS}/api/pinmap.c | 0 .../TARGET_KSDK2_MCUS}/api/port_api.c | 0 .../TARGET_KSDK2_MCUS}/api/pwmout_api.c | 0 .../TARGET_KSDK2_MCUS}/api/rtc_api.c | 0 .../TARGET_KSDK2_MCUS}/api/sleep.c | 0 workspace_tools/targets.py | 152 +++++++++--------- 332 files changed, 91 insertions(+), 82 deletions(-) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/MK22F51212.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/MK22F51212_features.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/cmsis.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/cmsis_nvic.c (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/cmsis_nvic.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/fsl_device_registers.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/system_MK22F51212.c (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K22F/system_MK22F51212.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/MK64F12.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/MK64F12_features.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/cmsis.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/cmsis_nvic.c (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/cmsis_nvic.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/fsl_device_registers.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/system_MK64F12.c (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_K64F/system_MK64F12.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/MKL27Z644.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/MKL27Z644_features.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/cmsis.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/cmsis_nvic.c (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/cmsis_nvic.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/fsl_device_registers.h (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/system_MKL27Z644.c (100%) rename libraries/mbed/targets/cmsis/{TARGET_NXP => TARGET_Freescale}/TARGET_KL27Z/system_MKL27Z644.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/PinNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/device.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/TARGET_FRDM/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_adc16.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_adc16.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_clock.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_clock.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_cmp.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_cmp.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_common.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_common.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_crc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_crc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dac.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dac.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dmamux.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dmamux.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dspi.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dspi.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dspi_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_dspi_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_ewm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_ewm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_flash.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_flash.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_flexbus.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_flexbus.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_ftm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_ftm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_gpio.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_gpio.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_i2c.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_i2c.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_i2c_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_i2c_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_llwu.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_llwu.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_lptmr.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_lptmr.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_lpuart.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_lpuart.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_lpuart_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_lpuart_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_pdb.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_pdb.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_pit.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_pit.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_pmc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_pmc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_port.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_rcm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_rcm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_rnga.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_rnga.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_rtc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_rtc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_sai.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_sai.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_sai_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_sai_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_sim.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_sim.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_smc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_smc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_uart.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_uart.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_uart_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_uart_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_vref.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_vref.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_wdog.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/drivers/fsl_wdog.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/peripheral_clock_defines.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/serial_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/spi_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K22F/us_ticker.c (91%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/PinNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/crc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/crc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/device.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_FRDM/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/device.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/device.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_adc16.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_adc16.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_clock.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_clock.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_cmp.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_cmp.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_cmt.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_cmt.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_common.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_common.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_crc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_crc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dac.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dac.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dmamux.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dmamux.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dspi.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dspi.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dspi_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_dspi_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_enet.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_enet.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_ewm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_ewm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flash.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flash.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flexbus.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flexbus.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flexcan.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flexcan.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flexcan_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_flexcan_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_ftm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_ftm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_gpio.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_gpio.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_i2c.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_i2c.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_i2c_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_i2c_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_llwu.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_llwu.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_lptmr.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_lptmr.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_mpu.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_mpu.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_pdb.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_pdb.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_pit.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_pit.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_pmc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_pmc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_port.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_rcm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_rcm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_rnga.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_rnga.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_rtc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_rtc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sai.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sai.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sai_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sai_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sdhc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sdhc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sim.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_sim.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_smc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_smc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_uart.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_uart.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_uart_edma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_uart_edma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_vref.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_vref.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_wdog.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/drivers/fsl_wdog.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/peripheral_clock_defines.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/serial_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/spi_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_K64F/us_ticker.c (91%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/PinNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/device.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_adc16.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_adc16.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_clock.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_clock.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_cmp.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_cmp.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_common.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_common.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_cop.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_cop.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_crc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_crc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_dmamux.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_dmamux.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flash.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flash.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_i2s.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_i2s.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_spi.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_spi.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_uart.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_uart.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_gpio.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_gpio.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_i2c.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_i2c.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_i2c_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_i2c_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_llwu.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_llwu.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_lptmr.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_lptmr.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_lpuart.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_lpuart.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_lpuart_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_lpuart_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_pit.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_pit.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_pmc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_pmc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_port.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_rcm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_rcm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_rtc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_rtc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_sim.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_sim.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_smc.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_smc.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_spi.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_spi.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_spi_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_spi_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_tpm.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_tpm.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_uart.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_uart.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_uart_dma.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_uart_dma.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_vref.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/drivers/fsl_vref.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/peripheral_clock_defines.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/serial_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/spi_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/TARGET_KL27Z/us_ticker.c (91%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/PeripheralPins.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/PortNames.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/analogin_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/analogout_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/gpio_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/gpio_irq_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/gpio_object.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/i2c_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/objects.h (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/pinmap.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/port_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/pwmout_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/rtc_api.c (100%) rename libraries/mbed/targets/hal/{TARGET_NXP/TARGET_KPSDK2_MCUS => TARGET_Freescale/TARGET_KSDK2_MCUS}/api/sleep.c (100%) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212_features.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212_features.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/MK22F51212_features.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212_features.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F51212.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F51212.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/fsl_device_registers.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/fsl_device_registers.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/fsl_device_registers.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/fsl_device_registers.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K22F/system_MK22F51212.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/MK64F12.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/MK64F12.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12_features.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/MK64F12_features.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/MK64F12_features.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/MK64F12_features.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_IAR/MK64FN1M0xxx12.icf diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_IAR/startup_MK64F12.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/fsl_device_registers.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/fsl_device_registers.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/fsl_device_registers.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/fsl_device_registers.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_K64F/system_MK64F12.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/MKL27Z644.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/MKL27Z644.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644_features.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/MKL27Z644_features.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/MKL27Z644_features.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/MKL27Z644_features.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/startup_MKL27Z644.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_GCC_ARM/startup_MKL27Z644.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_IAR/MKL27Z64xxx4.icf diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/TOOLCHAIN_IAR/startup_MKL27Z644.S diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/fsl_device_registers.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/fsl_device_registers.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/fsl_device_registers.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/fsl_device_registers.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/system_MKL27Z644.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/system_MKL27Z644.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/system_MKL27Z644.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_KL27Z/system_MKL27Z644.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/system_MKL27Z644.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/fsl_clock_config.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/TARGET_FRDM/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_adc16.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_clock.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_cmp.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_common.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_common.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_crc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dac.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dmamux.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_dspi_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ewm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flash.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_flexbus.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_gpio.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_i2c_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_llwu.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lptmr.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_lpuart_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pdb.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pit.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_pmc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_port.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rcm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rnga.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_rtc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sim.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_smc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_uart_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_vref.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_wdog.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/peripheral_clock_defines.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/serial_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/spi_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/us_ticker.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/us_ticker.c index 9dcfde85ae8..fd248033ae1 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K22F/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/us_ticker.c @@ -73,8 +73,11 @@ void us_ticker_clear_interrupt(void) { void us_ticker_set_interrupt(timestamp_t timestamp) { int delta = (int)(timestamp - us_ticker_read()); if (delta <= 0) { - // This event was in the past: - us_ticker_irq_handler(); + // This event was in the past. + // Set the interrupt as pending, but don't process it here. + // This prevents a recurive loop under heavy load + // which can lead to a stack overflow. + NVIC_SetPendingIRQ(PIT3_IRQn); return; } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/crc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_clock_config.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/fsl_clock_config.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_HEXIWEAR/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_adc16.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmp.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_cmt.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_common.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_common.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_crc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dac.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dmamux.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_dspi_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ewm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flash.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexbus.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_flexcan_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_gpio.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_i2c_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_llwu.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_lptmr.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_mpu.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pdb.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pit.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_pmc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_port.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rcm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rnga.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_rtc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sai_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sdhc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_sim.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_smc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_uart_edma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_vref.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_wdog.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/peripheral_clock_defines.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/serial_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/spi_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/us_ticker.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/us_ticker.c index 9dcfde85ae8..fd248033ae1 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_K64F/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/us_ticker.c @@ -73,8 +73,11 @@ void us_ticker_clear_interrupt(void) { void us_ticker_set_interrupt(timestamp_t timestamp) { int delta = (int)(timestamp - us_ticker_read()); if (delta <= 0) { - // This event was in the past: - us_ticker_irq_handler(); + // This event was in the past. + // Set the interrupt as pending, but don't process it here. + // This prevents a recurive loop under heavy load + // which can lead to a stack overflow. + NVIC_SetPendingIRQ(PIT3_IRQn); return; } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/fsl_clock_config.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cmp.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_cop.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_crc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_dmamux.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flash.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2c_master.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_i2s_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_spi_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_flexio_uart_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_gpio.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_i2c_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_llwu.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lptmr.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_lpuart_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pit.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_pmc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_port.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rcm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_rtc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_sim.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_smc.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_spi_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_tpm.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_uart_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_vref.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/peripheral_clock_defines.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/serial_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/spi_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/us_ticker.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/us_ticker.c index 180a72f7c13..9acf9fe7164 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/TARGET_KL27Z/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/us_ticker.c @@ -83,8 +83,11 @@ void us_ticker_clear_interrupt(void) { void us_ticker_set_interrupt(timestamp_t timestamp) { int delta = (int)(timestamp - us_ticker_read()); if (delta <= 0) { - // This event was in the past: - us_ticker_irq_handler(); + // This event was in the past. + // Set the interrupt as pending, but don't process it here. + // This prevents a recurive loop under heavy load + // which can lead to a stack overflow. + NVIC_SetPendingIRQ(LPTMR0_IRQn); return; } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/PeripheralPins.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/PeripheralPins.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PortNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/PortNames.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/analogout_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_object.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_object.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/objects.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/objects.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pinmap.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pinmap.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/port_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/port_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/port_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/port_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/rtc_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/sleep.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_KPSDK2_MCUS/api/sleep.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/sleep.c diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 06346bb97c5..624e40ecd1f 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -567,77 +567,6 @@ def __init__(self): } } -class K22F(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'FRDM'] - self.macros = ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.detect_code = ["0231"] - self.progen = { - "target":"frdm-k22f", - } - -class KL27Z(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M0+" - self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'FRDM'] - self.macros = ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM","GCC_ARM","IAR"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.detect_code = ["0261"] - self.progen_target = { - "target":"frdm-kl27z", - } - -class K64F(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'FRDM'] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] - self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] - self.supported_form_factors = ["ARDUINO"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.detect_code = ["0240"] - self.progen = { - "target":"frdm-k64f", - } - -class MTS_GAMBIT(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'K64F'] - self.supported_toolchains = ["ARM", "GCC_ARM"] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.progen = { - "target":"mts-gambit", - } - -class HEXIWEAR(Target): - def __init__(self): - Target.__init__(self) - self.core = "Cortex-M4F" - self.extra_labels = ['NXP', 'KPSDK2_MCUS', 'K64F'] - self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] - self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] - self.is_disk_virtual = True - self.default_toolchain = "ARM" - self.detect_code = ["0240"] - self.progen = { - "target":"hexiwear-k64f", - } - ### Freescale ### class KL05Z(Target): @@ -718,6 +647,77 @@ def __init__(self): "target":"frdm-k20d50m", } +class K22F(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['Freescale', 'KSDK2_MCUS', 'FRDM'] + self.macros = ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.detect_code = ["0231"] + self.progen = { + "target":"frdm-k22f", + } + +class KL27Z(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Freescale', 'KSDK2_MCUS', 'FRDM'] + self.macros = ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM","GCC_ARM","IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0261"] + self.progen_target = { + "target":"frdm-kl27z", + } + +class K64F(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['Freescale', 'KSDK2_MCUS', 'FRDM'] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.supported_form_factors = ["ARDUINO"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0240"] + self.progen = { + "target":"frdm-k64f", + } + +class MTS_GAMBIT(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['Freescale', 'KSDK2_MCUS', 'K64F'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.progen = { + "target":"mts-gambit", + } + +class HEXIWEAR(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['Freescale', 'KSDK2_MCUS', 'K64F'] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] + self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] + self.is_disk_virtual = True + self.default_toolchain = "ARM" + self.detect_code = ["0240"] + self.progen = { + "target":"hexiwear-k64f", + } + class TEENSY3_1(Target): OUTPUT_EXT = 'hex' @@ -2186,11 +2186,6 @@ def __init__(self): LPC4330_M0(), LPC4337(), LPC11U37H_401(), - K22F(), - KL27Z(), - K64F(), # FRDM K64F - MTS_GAMBIT(), - HEXIWEAR(), ### Freescale ### KL05Z(), @@ -2199,6 +2194,11 @@ def __init__(self): KL43Z(), KL46Z(), K20D50M(), + K22F(), + KL27Z(), + K64F(), # FRDM K64F + MTS_GAMBIT(), + HEXIWEAR(), TEENSY3_1(), ### STMicro ### From 840cd1ccb57659928722e5727b945247dc1f5414 Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Tue, 5 Apr 2016 12:08:25 -0500 Subject: [PATCH 09/11] Move PWM API to the target specific folder Some use the FTM module and some use the TPM module. Signed-off-by: Mahadevan Mahesh --- .../{api => TARGET_K22F}/pwmout_api.c | 0 .../TARGET_K64F/pwmout_api.c | 143 ++++++++++++++++++ .../TARGET_FRDM/PeripheralNames.h | 12 +- .../TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c | 44 ++++++ .../TARGET_KL27Z/pwmout_api.c | 136 +++++++++++++++++ libraries/tests/mbed/pwm_led/pwm.cpp | 1 + 6 files changed, 335 insertions(+), 1 deletion(-) rename libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/{api => TARGET_K22F}/pwmout_api.c (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/pwmout_api.c new file mode 100644 index 00000000000..216d583191a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/pwmout_api.c @@ -0,0 +1,143 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_ftm.h" +#include "PeripheralPins.h" + +static float pwm_clock_mhz; +/* Array of FTM peripheral base address. */ +static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS; + +void pwmout_init(pwmout_t* obj, PinName pin) { + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->pwm_name = pwm; + + uint32_t pwm_base_clock; + pwm_base_clock = CLOCK_GetFreq(kCLOCK_BusClk); + float clkval = (float)pwm_base_clock / 1000000.0f; + uint32_t clkdiv = 0; + while (clkval > 1) { + clkdiv++; + clkval /= 2.0f; + if (clkdiv == 7) { + break; + } + } + + pwm_clock_mhz = clkval; + uint32_t channel = pwm & 0xF; + uint32_t instance = pwm >> TPM_SHIFT; + ftm_config_t ftmInfo; + + FTM_GetDefaultConfig(&ftmInfo); + ftmInfo.prescale = (ftm_clock_prescale_t)clkdiv; + /* Initialize FTM module */ + FTM_Init(ftm_addrs[instance], &ftmInfo); + + ftm_addrs[instance]->CONF |= FTM_CONF_NUMTOF(3); + + ftm_chnl_pwm_signal_param_t config = { + .chnlNumber = (ftm_chnl_t)channel, + .level = kFTM_HighTrue, + .dutyCyclePercent = 0, + .firstEdgeDelayPercent = 0 + }; + // default to 20ms: standard for servos, and fine for e.g. brightness control + FTM_SetupPwm(ftm_addrs[instance], &config, 1, kFTM_EdgeAlignedPwm, 50, pwm_base_clock); + + FTM_StartTimer(ftm_addrs[instance], kFTM_SystemClock); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) { + FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]); +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } + + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; + uint32_t new_count = (uint32_t)((float)(mod) * value); + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = new_count; + base->CNT = 0; + /* Software trigger to update registers */ + FTM_SetSoftwareTrigger(base, true); +} + +float pwmout_read(pwmout_t* obj) { + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK; + uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; + + if (mod == 0) + return 0.0; + float v = (float)(count) / (float)(mod); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + float dc = pwmout_read(obj); + + // Stop FTM clock to ensure instant update of MOD register + base->MOD = FTM_MOD_MOD((pwm_clock_mhz * (float)us) - 1); + pwmout_write(obj, dc); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us); + + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = value; + /* Software trigger to update registers */ + FTM_SetSoftwareTrigger(base, true); +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h index fff903f8499..5e9ed77bcf7 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralNames.h @@ -41,8 +41,18 @@ typedef enum { I2C_1 = 1, } I2CName; +#define TPM_SHIFT 8 typedef enum { - PWM = 0, + PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5 + PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0 + PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1 + PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0 + PWM_10 = (2 << TPM_SHIFT) | (1), // TPM2 CH1 } PWMName; #define ADC_INSTANCE_SHIFT 8 diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c index fb0ea4a2ff4..ff132832b6c 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/TARGET_FRDM/PeripheralPins.c @@ -148,3 +148,47 @@ const PinMap PinMap_SPI_SSEL[] = { {PTD4 , SPI_1, 2}, {NC , NC , 0} }; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTE29, PWM_3 , 3}, + {PTE30, PWM_4 , 3}, + {PTE31, PWM_5 , 3}, + {PTE24, PWM_1 , 3}, + {PTE25, PWM_2 , 3}, + {PTA0 , PWM_6 , 3}, + {PTA3 , PWM_1 , 3}, + {PTA4 , PWM_2 , 3}, + {PTA5 , PWM_3 , 3}, + {PTC1 , PWM_1 , 4}, + {PTC2 , PWM_2 , 4}, + {PTC3 , PWM_3 , 4}, + {PTC4 , PWM_4 , 4}, + {PTC8 , PWM_5 , 3}, + {PTC9 , PWM_6 , 3}, + {PTD0 , PWM_1 , 4}, + {PTD1 , PWM_2 , 4}, + {PTD2 , PWM_3 , 4}, + {PTD3 , PWM_4 , 4}, + {PTD4 , PWM_5 , 4}, + {PTD5 , PWM_6 , 4}, + + {PTE20, PWM_7 , 3}, + {PTE21, PWM_8 , 3}, + {PTA12, PWM_7 , 3}, + {PTA13, PWM_8 , 3}, + {PTB0, PWM_7 , 3}, + {PTB1, PWM_8 , 3}, + + {PTE22, PWM_9 , 3}, + {PTE23, PWM_10, 3}, + {PTA1 , PWM_9 , 3}, + {PTA2 , PWM_10, 3}, + {PTB2 , PWM_9 , 3}, + {PTB3 , PWM_10, 3}, + {PTB18, PWM_9 , 3}, + {PTB19, PWM_10, 3}, + + {NC , NC , 0} +}; + diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/pwmout_api.c new file mode 100644 index 00000000000..dd5e5fd1b3c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/pwmout_api.c @@ -0,0 +1,136 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_tpm.h" +#include "PeripheralPins.h" + +static float pwm_clock_mhz; +/* Array of TPM peripheral base address. */ +static TPM_Type *const tpm_addrs[] = TPM_BASE_PTRS; + +void pwmout_init(pwmout_t* obj, PinName pin) { + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->pwm_name = pwm; + + uint32_t pwm_base_clock; + pwm_base_clock = CLOCK_GetFreq(kCLOCK_McgIrc48MClk); + float clkval = (float)pwm_base_clock / 1000000.0f; + uint32_t clkdiv = 0; + while (clkval > 1) { + clkdiv++; + clkval /= 2.0f; + if (clkdiv == 7) { + break; + } + } + + pwm_clock_mhz = clkval; + uint32_t channel = pwm & 0xF; + uint32_t instance = pwm >> TPM_SHIFT; + tpm_config_t tpmInfo; + + TPM_GetDefaultConfig(&tpmInfo); + tpmInfo.prescale = (tpm_clock_prescale_t)clkdiv; + /* Initialize TPM module */ + TPM_Init(tpm_addrs[instance], &tpmInfo); + + tpm_chnl_pwm_signal_param_t config = { + .chnlNumber = (tpm_chnl_t)channel, + .level = kTPM_HighTrue, + .dutyCyclePercent = 0, + }; + // default to 20ms: standard for servos, and fine for e.g. brightness control + TPM_SetupPwm(tpm_addrs[instance], &config, 1, kTPM_EdgeAlignedPwm, 50, pwm_base_clock); + + TPM_StartTimer(tpm_addrs[instance], kTPM_SystemClock); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) { + TPM_Deinit(tpm_addrs[obj->pwm_name >> TPM_SHIFT]); +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } + + TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t mod = base->MOD & TPM_MOD_MOD_MASK; + uint32_t new_count = (uint32_t)((float)(mod) * value); + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = new_count; + base->CNT = 0; +} + +float pwmout_read(pwmout_t* obj) { + TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & TPM_CnV_VAL_MASK; + uint16_t mod = base->MOD & TPM_MOD_MOD_MASK; + + if (mod == 0) + return 0.0; + float v = (float)(count) / (float)(mod); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT]; + float dc = pwmout_read(obj); + + // Stop TPM clock to ensure instant update of MOD register + base->MOD = TPM_MOD_MOD((pwm_clock_mhz * (float)us) - 1); + pwmout_write(obj, dc); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us); + + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = value; +} + +#endif diff --git a/libraries/tests/mbed/pwm_led/pwm.cpp b/libraries/tests/mbed/pwm_led/pwm.cpp index 61656d9a0a5..429a3d8dc4c 100644 --- a/libraries/tests/mbed/pwm_led/pwm.cpp +++ b/libraries/tests/mbed/pwm_led/pwm.cpp @@ -20,6 +20,7 @@ #define TEST_LED D3 #elif defined (TARGET_K22F) || \ + defined(TARGET_KL27Z) || \ defined (TARGET_LPC824) #define TEST_LED LED_GREEN From da0924f95cae22e1ffd537528a050fbb43c8a9ac Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Wed, 27 Apr 2016 15:41:31 -0500 Subject: [PATCH 10/11] Networking update for FRDM K64 platform Signed-off-by: Mahadevan Mahesh --- .../TARGET_K64F/TARGET_FRDM/fsl_phy.c | 292 ++++++++ .../TARGET_K64F/TARGET_FRDM/fsl_phy.h | 216 ++++++ .../TARGET_K64F/drivers/fsl_enet.c | 29 +- .../TARGET_K64F/drivers/fsl_enet.h | 1 + .../arch/TARGET_Freescale/fsl_enet_driver.c | 469 ------------ .../TARGET_Freescale/hardware_init_MK64F12.c | 76 +- .../arch/TARGET_Freescale/k64f_emac.c | 674 ++++++------------ .../arch/TARGET_Freescale/k64f_emac_config.h | 13 +- .../arch/TARGET_Freescale/lwipopts_conf.h | 2 +- workspace_tools/targets.py | 2 +- 10 files changed, 782 insertions(+), 992 deletions(-) create mode 100755 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.c create mode 100755 libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.h delete mode 100644 libraries/net/eth/lwip-eth/arch/TARGET_Freescale/fsl_enet_driver.c diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.c new file mode 100755 index 00000000000..961a97f339f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.c @@ -0,0 +1,292 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_phy.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0xFFFFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) +{ + uint32_t bssReg; + uint32_t counter = PHY_TIMEOUT_COUNT; + status_t result = kStatus_Success; + uint32_t instance = ENET_GetInstance(base); + + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); + ENET_SetSMI(base, srcClock_Hz, false); + + /* Reset PHY. */ + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter --) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { + if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) + { + break; + } + } + + if (!counter) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + } + + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + assert(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in the basic control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + assert(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); + if (result == kStatus_Success) + { + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = kPHY_FullDuplex; + } + else + { + /* Half duplex. */ + *duplex = kPHY_HalfDuplex; + } + + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = kPHY_Speed100M; + } + else + { /* 10M speed. */ + *speed = kPHY_Speed10M; + } + } + + return result; +} diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.h new file mode 100755 index 00000000000..bf3167fa69a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/TARGET_FRDM/fsl_phy.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the PHY status. */ +enum _phy_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c index c999f7714d2..7f15c05183a 100755 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.c @@ -295,20 +295,7 @@ void ENET_Init(ENET_Type *base, assert(bufferConfig->rxBdStartAddrAlign); assert(bufferConfig->txBdStartAddrAlign); assert(bufferConfig->rxBufferAlign); - assert(bufferConfig->txBufferAlign); assert(macAddr); - assert(bufferConfig->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); - - /* Make sure the buffers should be have the capability of process at least one maximum frame. */ - if (config->macSpecialConfig & kENET_ControlVLANTagEnable) - { - assert(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > ENET_FRAME_MAX_VALNFRAMELEN); - } - else - { - assert(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > ENET_FRAME_MAX_FRAMELEN); - assert(bufferConfig->rxBuffSizeAlign * bufferConfig->rxBdNumber > config->rxMaxFrameLen); - } uint32_t instance = ENET_GetInstance(base); @@ -339,6 +326,7 @@ void ENET_Init(ENET_Type *base, handle->rxBdDirty = bufferConfig->rxBdStartAddrAlign; handle->txBdBase = bufferConfig->txBdStartAddrAlign; handle->txBdCurrent = bufferConfig->txBdStartAddrAlign; + handle->txBdDirty = bufferConfig->txBdStartAddrAlign; handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign; handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign; @@ -496,15 +484,22 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA uint32_t txBdNumber) { assert(txBdStartAlign); - assert(txBuffStartAlign); uint32_t count; volatile enet_tx_bd_struct_t *curBuffDescrip = txBdStartAlign; for (count = 0; count < txBdNumber; count++) { - /* Set data buffer address. */ - curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]); + if (txBuffSizeAlign != NULL) + { + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]); + } + else + { + /* User should provide the transmit buffer at a later time */ + curBuffDescrip->buffer = NULL; + } /* Initializes data length. */ curBuffDescrip->length = 0; /* Sets the crc. */ @@ -540,7 +535,7 @@ static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartA for (count = 0; count < rxBdNumber; count++) { /* Set data buffer and the length. */ - curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffStartAlign[count * rxBuffSizeAlign]); + curBuffDescrip->buffer = (uint8_t *)(*((uint32_t *)(rxBuffStartAlign + count * 4))); curBuffDescrip->length = 0; /* Initializes the buffer descriptors with empty bit. */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h index 8a53c821e5b..9897f7651f6 100755 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_enet.h @@ -506,6 +506,7 @@ struct _enet_handle volatile enet_rx_bd_struct_t *rxBdDirty; /*!< The dirty receive buffer descriptor needed to be updated from. */ volatile enet_tx_bd_struct_t *txBdBase; /*!< Transmit buffer descriptor base address pointer. */ volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */ + volatile enet_tx_bd_struct_t *txBdDirty; /*!< The dirty transmit buffer descriptor needed to be updated from. */ uint32_t rxBuffSizeAlign; /*!< Receive buffer size alignment. */ uint32_t txBuffSizeAlign; /*!< Transmit buffer size alignment. */ enet_callback_t callback; /*!< Callback function. */ diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/fsl_enet_driver.c b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/fsl_enet_driver.c deleted file mode 100644 index cb3481cf0ae..00000000000 --- a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/fsl_enet_driver.c +++ /dev/null @@ -1,469 +0,0 @@ -/* -* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/* Modified by mbed for the lwIP port */ - -#include "fsl_enet_driver.h" -#include "fsl_enet_hal.h" -#include "fsl_clock_manager.h" -#include "fsl_interrupt_manager.h" -#include - -#include "sys_arch.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Define ENET's IRQ list */ - -void *enetIfHandle; - -/*! @brief Define MAC driver API structure and for application of stack adaptor layer*/ -const enet_mac_api_t g_enetMacApi = -{ - enet_mac_init, - NULL, // enet_mac_deinit, - NULL, // enet_mac_send, -#if !ENET_RECEIVE_ALL_INTERRUPT - NULL, // enet_mac_receive, -#endif - enet_mii_read, - enet_mii_write, - NULL, // enet_mac_add_multicast_group, - NULL, //enet_mac_leave_multicast_group, -}; -/******************************************************************************* - * Code - ******************************************************************************/ - -// NOTE: we need these functions to be non-blocking fpr the PHY task, hence the -// osDelay() below - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mii_read - * Return Value: The execution status. - * Description: Read function. - * This interface read data over the (R)MII bus from the specified PHY register, - * This function is called by all PHY interfaces. - *END*********************************************************************/ -uint32_t enet_mii_read(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) -{ - uint32_t counter; - - /* Check the input parameters*/ - if (!dataPtr) - { - return kStatus_ENET_InvalidInput; - } - - /* Check if the mii is enabled*/ - if (!enet_hal_is_mii_enabled(instance)) - { - return kStatus_ENET_Miiuninitialized; - } - - /* Clear the MII interrupt event*/ - enet_hal_clear_interrupt(instance, kEnetMiiInterrupt); - - /* Read command operation*/ - enet_hal_set_mii_command(instance, phyAddr, phyReg, kEnetReadValidFrame, 0); - - /* Poll for MII complete*/ - for (counter = 0; counter < kEnetMaxTimeout; counter++) - { - if (enet_hal_get_interrupt_status(instance, kEnetMiiInterrupt)) - { - break; - } - osDelay(1); - } - - /* Check for timeout*/ - if (counter == kEnetMaxTimeout) - { - return kStatus_ENET_TimeOut; - } - - /* Get data from mii register*/ - *dataPtr = enet_hal_get_mii_data(instance); - - /* Clear MII interrupt event*/ - enet_hal_clear_interrupt(instance, kEnetMiiInterrupt); - - return kStatus_ENET_Success; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mii_write - * Return Value: The execution status. - * Description: Write function. - * This interface write data over the (R)MII bus to the specified PHY register. - * This function is called by all PHY interfaces. - *END*********************************************************************/ -uint32_t enet_mii_write(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, uint32_t data) -{ - uint32_t counter; - - /* Check if the mii is enabled*/ - if (!enet_hal_is_mii_enabled(instance)) - { - return kStatus_ENET_Miiuninitialized; - } - - /* Clear the MII interrupt event*/ - enet_hal_clear_interrupt(instance, kEnetMiiInterrupt); - - /* Read command operation*/ - enet_hal_set_mii_command(instance, phyAddr, phyReg, kEnetWriteValidFrame, data); - - /* Poll for MII complete*/ - for (counter = 0; counter < kEnetMaxTimeout; counter++) - { - if (enet_hal_get_interrupt_status(instance, kEnetMiiInterrupt)) - { - break; - } - osDelay(1); - } - - /* Check for timeout*/ - if (counter == kEnetMaxTimeout) - { - return kStatus_ENET_TimeOut; - } - - /* Clear MII intrrupt event*/ - enet_hal_clear_interrupt(instance, kEnetMiiInterrupt); - - return kStatus_ENET_Success; -} -/*FUNCTION**************************************************************** - * - * Function Name: enet_mac_mii_init - * Return Value: The execution status. - * Description:Initialize the ENET Mac mii(mdc/mdio)interface. - *END*********************************************************************/ -uint32_t enet_mac_mii_init(enet_dev_if_t * enetIfPtr) -{ - uint32_t frequency; - - /* Check the input parameters*/ - if (enetIfPtr == NULL) - { - return kStatus_ENET_InvalidInput; - } - - /* Configure mii speed*/ - CLOCK_SYS_GetFreq(kSystemClock, &frequency); - enet_hal_config_mii(enetIfPtr->deviceNumber, (frequency/(2 * enetIfPtr->macCfgPtr->miiClock) + 1), - kEnetMdioHoldOneClkCycle, false); - - return kStatus_ENET_Success; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mac_rxbd_init - * Return Value: The execution status. - * Description:Initialize the ENET receive buffer descriptors. - * Note: If you do receive on receive interrupt handler the receive - * data buffer number can be the same as the receive descriptor numbers. - * But if you are polling receive frames please make sure the receive data - * buffers are more than buffer descriptors to guarantee a good performance. - *END*********************************************************************/ -uint32_t enet_mac_rxbd_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg) -{ - /* Check the input parameters*/ - if ((!enetIfPtr) || (!rxbdCfg)) - { - return kStatus_ENET_InvalidInput; - } - - enetIfPtr->macContextPtr->bufferdescSize = enet_hal_get_bd_size(); - - /* Initialize the bd status*/ - enetIfPtr->macContextPtr->isRxFull = false; - - /* Initialize receive bd base address and current address*/ - enetIfPtr->macContextPtr->rxBdBasePtr = rxbdCfg->rxBdPtrAlign; - enetIfPtr->macContextPtr->rxBdCurPtr = enetIfPtr->macContextPtr->rxBdBasePtr; - enetIfPtr->macContextPtr->rxBdDirtyPtr = enetIfPtr->macContextPtr->rxBdBasePtr; - enet_hal_set_rxbd_address(enetIfPtr->deviceNumber, (uint32_t)(enetIfPtr->macContextPtr->rxBdBasePtr)); - - return kStatus_ENET_Success; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mac_txbd_init - * Return Value: The execution status. - * Description:Initialize the ENET transmit buffer descriptors. - * This function prepare all of the transmit buffer descriptors. - *END*********************************************************************/ -uint32_t enet_mac_txbd_init(enet_dev_if_t * enetIfPtr, enet_txbd_config_t *txbdCfg) -{ - /* Check the input parameters*/ - if ((!enetIfPtr) || (!txbdCfg)) - { - return kStatus_ENET_InvalidInput; - } - - /* Initialize the bd status*/ - enetIfPtr->macContextPtr->isTxFull = false; - - /* Initialize transmit bd base address and current address*/ - enetIfPtr->macContextPtr->txBdBasePtr = txbdCfg->txBdPtrAlign; - enetIfPtr->macContextPtr->txBdCurPtr = enetIfPtr->macContextPtr->txBdBasePtr; - enetIfPtr->macContextPtr->txBdDirtyPtr = enetIfPtr->macContextPtr->txBdBasePtr; - enet_hal_set_txbd_address(enetIfPtr->deviceNumber, (uint32_t)(enetIfPtr->macContextPtr->txBdBasePtr)); - return kStatus_ENET_Success; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mac_configure_fifo_accel - * Return Value: The execution status. - * Description: Configure the ENET FIFO and Accelerator. - *END*********************************************************************/ -uint32_t enet_mac_configure_fifo_accel(enet_dev_if_t * enetIfPtr) -{ - enet_config_rx_fifo_t rxFifo; - enet_config_tx_fifo_t txFifo; - - /* Check the input parameters*/ - if (!enetIfPtr) - { - return kStatus_ENET_InvalidInput; - } - - /* Initialize values that will not be initialized later on */ - rxFifo.rxEmpty = 0; - rxFifo.rxFull = 0; - txFifo.isStoreForwardEnabled = 0; - txFifo.txFifoWrite = 0; - txFifo.txEmpty = 0; - - /* Configure tx/rx accelerator*/ - if (enetIfPtr->macCfgPtr->isRxAccelEnabled) - { - enet_hal_config_rx_accelerator(enetIfPtr->deviceNumber, - (enet_config_rx_accelerator_t *)&(enetIfPtr->macCfgPtr->rxAcceler)); - if ((enetIfPtr->macCfgPtr->rxAcceler.isIpcheckEnabled) || (enetIfPtr->macCfgPtr->rxAcceler.isProtocolCheckEnabled)) - { - rxFifo.rxFull = 0; - } - } - if (enetIfPtr->macCfgPtr->isTxAccelEnabled) - { - enet_hal_config_tx_accelerator(enetIfPtr->deviceNumber, - (enet_config_tx_accelerator_t *)&(enetIfPtr->macCfgPtr->txAcceler)); - if ((enetIfPtr->macCfgPtr->txAcceler.isIpCheckEnabled) || (enetIfPtr->macCfgPtr->txAcceler.isProtocolCheckEnabled)) - { - txFifo.isStoreForwardEnabled = 1; - } - } - if (enetIfPtr->macCfgPtr->isStoreAndFwEnabled) - { - rxFifo.rxFull = 0; - txFifo.isStoreForwardEnabled = 1; - } - - - /* Set TFWR value if STRFWD is not being used */ - if (txFifo.isStoreForwardEnabled == 1) - txFifo.txFifoWrite = 0; - else - /* TFWR value is a trade-off between transmit latency and risk of transmit FIFO underrun due to contention for the system bus - TFWR = 15 means transmission will begin once 960 bytes has been written to the Tx FIFO (for frames larger than 960 bytes) - See Section 45.4.18 - Transmit FIFO Watermark Register of the K64F Reference Manual for details */ - txFifo.txFifoWrite = 15; - - /* Configure tx/rx FIFO with default value*/ - rxFifo.rxAlmostEmpty = 4; - rxFifo.rxAlmostFull = 4; - txFifo.txAlmostEmpty = 4; - txFifo.txAlmostFull = 8; - enet_hal_config_rx_fifo(enetIfPtr->deviceNumber, &rxFifo); - enet_hal_config_tx_fifo(enetIfPtr->deviceNumber, &txFifo); - - return kStatus_ENET_Success; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mac_configure_controller - * Return Value: The execution status. - * Description: Configure the ENET controller with the basic configuration. - *END*********************************************************************/ -uint32_t enet_mac_configure_controller(enet_dev_if_t * enetIfPtr) -{ - uint32_t macCtlCfg; - - /* Check the input parameters*/ - if (enetIfPtr == NULL) - { - return kStatus_ENET_InvalidInput; - } - - macCtlCfg = enetIfPtr->macCfgPtr->macCtlConfigure; - /* Configure rmii/mii interface*/ - enet_hal_config_rmii(enetIfPtr->deviceNumber, enetIfPtr->macCfgPtr->rmiiCfgMode, - enetIfPtr->macCfgPtr->speed, enetIfPtr->macCfgPtr->duplex, false, - (macCtlCfg & kEnetRxMiiLoopback)); - /* Configure receive buffer size*/ - if (enetIfPtr->macCfgPtr->isVlanEnabled) - { - enetIfPtr->maxFrameSize = kEnetMaxFrameVlanSize; - enet_hal_set_rx_max_size(enetIfPtr->deviceNumber, - enetIfPtr->macContextPtr->rxBufferSizeAligned, kEnetMaxFrameVlanSize); - } - else - { - enetIfPtr->maxFrameSize = kEnetMaxFrameSize; - enet_hal_set_rx_max_size(enetIfPtr->deviceNumber, - enetIfPtr->macContextPtr->rxBufferSizeAligned, kEnetMaxFrameSize); - } - - /* Set receive controller promiscuous */ - enet_hal_config_promiscuous(enetIfPtr->deviceNumber, macCtlCfg & kEnetRxPromiscuousEnable); - /* Set receive flow control*/ - enet_hal_enable_flowcontrol(enetIfPtr->deviceNumber, (macCtlCfg & kEnetRxFlowControlEnable)); - /* Set received PAUSE frames are forwarded/terminated*/ - enet_hal_enable_pauseforward(enetIfPtr->deviceNumber, (macCtlCfg & kEnetRxPauseFwdEnable)); - /* Set receive broadcast frame reject*/ - enet_hal_enable_broadcastreject(enetIfPtr->deviceNumber, (macCtlCfg & kEnetRxBcRejectEnable)); - /* Set padding is removed from the received frame*/ - enet_hal_enable_padremove(enetIfPtr->deviceNumber, (macCtlCfg & kEnetRxPadRemoveEnable)); - /* Set the crc of the received frame is stripped from the frame*/ - enet_hal_enable_rxcrcforward(enetIfPtr->deviceNumber, (macCtlCfg & kEnetRxCrcFwdEnable)); - /* Set receive payload length check*/ - enet_hal_enable_payloadcheck(enetIfPtr->deviceNumber, (macCtlCfg & kEnetPayloadlenCheckEnable)); - /* Set control sleep mode*/ - enet_hal_enable_sleep(enetIfPtr->deviceNumber, (macCtlCfg & kEnetSleepModeEnable)); - return kStatus_ENET_Success; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_mac_init - * Return Value: The execution status. - * Description:Initialize the ENET device with the basic configuration - * When ENET is used, this function need to be called by the NET initialize - * interface. - *END*********************************************************************/ -uint32_t enet_mac_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg, - enet_txbd_config_t *txbdCfg) -{ - uint32_t timeOut = 0; - uint32_t devNumber, result = 0; - - /* Check the input parameters*/ - if (enetIfPtr == NULL) - { - return kStatus_ENET_InvalidInput; - } - - /* Get device number and check the parameter*/ - devNumber = enetIfPtr->deviceNumber; - - /* Store the global ENET structure for ISR input parameters */ - enetIfHandle = enetIfPtr; - - /* Turn on ENET module clock gate */ - CLOCK_SYS_EnableEnetClock(0U); - - /* Reset ENET mac*/ - enet_hal_reset_ethernet(devNumber); - while ((!enet_hal_is_reset_completed(devNumber)) && (timeOut < kEnetMaxTimeout)) - { - time_delay(1); - timeOut++; - } - - /* Check out if timeout*/ - if (timeOut == kEnetMaxTimeout) - { - return kStatus_ENET_TimeOut; - } - - /* Disable all ENET mac interrupt and Clear all interrupt events*/ - enet_hal_config_interrupt(devNumber, kEnetAllInterrupt, false); - enet_hal_clear_interrupt(devNumber, kEnetAllInterrupt); - - /* Program this station's physical address*/ - enet_hal_set_mac_address(devNumber, enetIfPtr->macCfgPtr->macAddr); - - /* Clear group and individual hash register*/ - enet_hal_set_group_hashtable(devNumber, 0, kEnetSpecialAddressInit); - enet_hal_set_individual_hashtable(devNumber, 0, kEnetSpecialAddressInit); - - /* Configure mac controller*/ - result = enet_mac_configure_controller(enetIfPtr); - if(result != kStatus_ENET_Success) - { - return result; - } - /* Clear mib zero counters*/ - enet_hal_clear_mib(devNumber, true); - - /* Initialize FIFO and accelerator*/ - result = enet_mac_configure_fifo_accel(enetIfPtr); - if(result != kStatus_ENET_Success) - { - return result; - } - /* Initialize receive buffer descriptors*/ - result = enet_mac_rxbd_init(enetIfPtr, rxbdCfg); - if(result != kStatus_ENET_Success) - { - return result; - } - /* Initialize transmit buffer descriptors*/ - result = enet_mac_txbd_init(enetIfPtr, txbdCfg); - if(result != kStatus_ENET_Success) - { - return result; - } - /* Initialize rmii/mii interface*/ - result = enet_mac_mii_init(enetIfPtr); - if (result != kStatus_ENET_Success) - { - return result; - } - - return kStatus_ENET_Success; -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c index aa832ab8c20..a6a4c04126f 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c +++ b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c @@ -28,53 +28,57 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "fsl_port_hal.h" -#include "fsl_clock_manager.h" -#include "fsl_device_registers.h" -#include "fsl_sim_hal.h" +#include "fsl_port.h" /******************************************************************************* * Code ******************************************************************************/ void k64f_init_eth_hardware(void) { - uint8_t count; + port_pin_config_t configENET = {0}; - /* Disable the mpu*/ - BW_MPU_CESR_VLD(MPU_BASE, 0); - - /* Open POTR clock gate*/ - for (count = 0; count < HW_PORT_INSTANCE_COUNT; count++) - { - CLOCK_SYS_EnablePortClock(count); - } + /* Disable MPU. */ + MPU->CESR &= ~MPU_CESR_VLD_MASK; - /* Configure gpio*/ - PORT_HAL_SetMuxMode(PORTA_BASE, 12, kPortMuxAlt4); /*!< ENET RMII0_RXD1/MII0_RXD1*/ - PORT_HAL_SetMuxMode(PORTA_BASE, 13, kPortMuxAlt4); /*!< ENET RMII0_RXD0/MII0_RXD0*/ - PORT_HAL_SetMuxMode(PORTA_BASE, 14, kPortMuxAlt4); /*!< ENET RMII0_CRS_DV/MII0_RXDV*/ - PORT_HAL_SetMuxMode(PORTA_BASE, 15, kPortMuxAlt4); /*!< ENET RMII0_TXEN/MII0_TXEN*/ - PORT_HAL_SetMuxMode(PORTA_BASE, 16, kPortMuxAlt4); /*!< ENET RMII0_TXD0/MII0_TXD0*/ - PORT_HAL_SetMuxMode(PORTA_BASE, 17, kPortMuxAlt4); /*!< ENET RMII0_TXD01/MII0_TXD1*/ - PORT_HAL_SetMuxMode(PORTB_BASE, 0, kPortMuxAlt4); /*!< ENET RMII0_MDIO/MII0_MDIO*/ - PORT_HAL_SetOpenDrainCmd(PORTB_BASE,0, true); /*!< ENET RMII0_MDC/MII0_MDC*/ + CLOCK_EnableClock(kCLOCK_PortC); + /* Affects PORTC_PCR16 register */ + PORT_SetPinMux(PORTC, 16u, kPORT_MuxAlt4); + /* Affects PORTC_PCR17 register */ + PORT_SetPinMux(PORTC, 17u, kPORT_MuxAlt4); + /* Affects PORTC_PCR18 register */ + PORT_SetPinMux(PORTC, 18u, kPORT_MuxAlt4); + /* Affects PORTC_PCR19 register */ + PORT_SetPinMux(PORTC, 19u, kPORT_MuxAlt4); + /* Affects PORTB_PCR1 register */ + PORT_SetPinMux(PORTB, 1u, kPORT_MuxAlt4); - // Added for FRDM-K64F - PORT_HAL_SetPullMode(PORTB_BASE, 0, kPortPullUp); - PORT_HAL_SetPullCmd(PORTB_BASE, 0, true); - - PORT_HAL_SetMuxMode(PORTB_BASE, 1, kPortMuxAlt4); - -#if FSL_FEATURE_ENET_SUPPORT_PTP - PORT_HAL_SetMuxMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortMuxAlt4); /* ENET ENET0_1588_TMR0*/ - PORT_HAL_SetDriveStrengthMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortHighDriveStrength); -#endif + configENET.openDrainEnable = kPORT_OpenDrainEnable; + configENET.mux = kPORT_MuxAlt4; + configENET.pullSelect = kPORT_PullUp; + /* Ungate the port clock */ + CLOCK_EnableClock(kCLOCK_PortA); + /* Affects PORTB_PCR0 register */ + PORT_SetPinConfig(PORTB, 0u, &configENET); - /* Open ENET clock gate*/ - CLOCK_SYS_EnableEnetClock( 0U); + /* Affects PORTA_PCR13 register */ + PORT_SetPinMux(PORTA, 13u, kPORT_MuxAlt4); + /* Affects PORTA_PCR12 register */ + PORT_SetPinMux(PORTA, 12u, kPORT_MuxAlt4); + /* Affects PORTA_PCR14 register */ + PORT_SetPinMux(PORTA, 14u, kPORT_MuxAlt4); + /* Affects PORTA_PCR5 register */ + PORT_SetPinMux(PORTA, 5u, kPORT_MuxAlt4); + /* Affects PORTA_PCR16 register */ + PORT_SetPinMux(PORTA, 16u, kPORT_MuxAlt4); + /* Affects PORTA_PCR17 register */ + PORT_SetPinMux(PORTA, 17u, kPORT_MuxAlt4); + /* Affects PORTA_PCR15 register */ + PORT_SetPinMux(PORTA, 15u, kPORT_MuxAlt4); + /* Affects PORTA_PCR28 register */ + PORT_SetPinMux(PORTA, 28u, kPORT_MuxAlt4); - /* Select the ptp timer outclk*/ - CLOCK_HAL_SetSource(g_simBaseAddr[0], kClockTimeSrc, 2); + /* Select the Ethernet timestamp clock source */ + CLOCK_SetEnetTime0Clock(0x2); } /******************************************************************************* diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac.c b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac.c index a2ec35c39a7..705db64484b 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac.c +++ b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac.c @@ -12,11 +12,7 @@ #include "eth_arch.h" #include "sys_arch.h" -#include "fsl_enet_driver.h" -#include "fsl_enet_hal.h" -#include "fsl_device_registers.h" -#include "fsl_phy_driver.h" -#include "fsl_interrupt_manager.h" +#include "fsl_phy.h" #include "k64f_emac_config.h" #include #include @@ -25,14 +21,23 @@ #include "mbed_interface.h" -extern IRQn_Type enet_irq_ids[HW_ENET_INSTANCE_COUNT][FSL_FEATURE_ENET_INTERRUPT_COUNT]; -extern uint8_t enetIntMap[kEnetIntNum]; -extern void *enetIfHandle; +enet_handle_t g_handle; +// TX Buffer descriptors +uint8_t *tx_desc_start_addr; +// RX Buffer descriptors +uint8_t *rx_desc_start_addr; +// RX packet buffer pointers +struct pbuf *rx_buff[ENET_RX_RING_LEN]; +// TX packet buffer pointers +struct pbuf *tx_buff[ENET_RX_RING_LEN]; +// RX packet payload pointers +uint32_t *rx_ptr[ENET_RX_RING_LEN]; /******************************************************************************** * Internal data ********************************************************************************/ - +#define ENET_BuffSizeAlign(n) ENET_ALIGN(n, ENET_BUFF_ALIGNMENT) +#define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1))) extern void k64f_init_eth_hardware(void); /* K64F EMAC driver data structure */ @@ -42,49 +47,11 @@ struct k64f_enetdata { sys_sem_t TxCleanSem; /**< TX cleanup thread wakeup semaphore */ sys_mutex_t TXLockMutex; /**< TX critical section mutex */ sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */ - volatile u32_t rx_free_descs; /**< Count of free RX descriptors */ - struct pbuf *rxb[ENET_RX_RING_LEN]; /**< RX pbuf pointer list, zero-copy mode */ - uint8_t *rx_desc_start_addr; /**< RX descriptor start address */ - uint8_t *tx_desc_start_addr; /**< TX descriptor start address */ uint8_t tx_consume_index, tx_produce_index; /**< TX buffers ring */ - uint8_t rx_fill_index; /**< RX ring fill index */ - struct pbuf *txb[ENET_TX_RING_LEN]; /**< TX pbuf pointer list, zero-copy mode */ - void *txb_aligned[ENET_TX_RING_LEN]; /**< TX aligned buffers (if needed) */ }; static struct k64f_enetdata k64f_enetdata; -static enet_dev_if_t enetDevIf[HW_ENET_INSTANCE_COUNT]; -static enet_mac_config_t g_enetMacCfg[HW_ENET_INSTANCE_COUNT] = -{ - { - ENET_ETH_MAX_FLEN , /*!< enet receive buffer size*/ - ENET_RX_LARGE_BUFFER_NUM, /*!< enet large receive buffer number*/ - ENET_RX_RING_LEN, /*!< enet receive bd number*/ - ENET_TX_RING_LEN, /*!< enet transmit bd number*/ - {0}, /*!< enet mac address*/ - kEnetCfgRmii, /*!< enet rmii interface*/ - kEnetCfgSpeed100M, /*!< enet rmii 100M*/ - kEnetCfgFullDuplex, /*!< enet rmii Full- duplex*/ - /*!< enet mac control flag recommended to use enet_mac_control_flag_t - we send frame with crc so receive crc forward for data length check test*/ - kEnetRxCrcFwdEnable | kEnetRxFlowControlEnable, - true, /*!< enet txaccelerator enabled*/ - true, /*!< enet rxaccelerator enabled*/ - false, /*!< enet store and forward*/ - {false, false, true, false, true}, /*!< enet rxaccelerator config*/ - {false, false, true}, /*!< enet txaccelerator config*/ - true, /*!< vlan frame support*/ - true, /*!< phy auto discover*/ - ENET_MII_CLOCK, /*!< enet MDC clock*/ - }, -}; - -static enet_phy_config_t g_enetPhyCfg[HW_ENET_INSTANCE_COUNT] = -{ - {0, false} -}; - /** \brief Driver transmit and receive thread priorities * * Thread priorities for receive thread and TX cleanup thread. Alter @@ -95,166 +62,35 @@ static enet_phy_config_t g_enetPhyCfg[HW_ENET_INSTANCE_COUNT] = #define TX_PRIORITY (osPriorityNormal) #define PHY_PRIORITY (osPriorityNormal) -/** \brief Debug output formatter lock define - * - * When using FreeRTOS and with LWIP_DEBUG enabled, enabling this - * define will allow RX debug messages to not interleave with the - * TX messages (so they are actually readable). Not enabling this - * define when the system is under load will cause the output to - * be unreadable. There is a small tradeoff in performance for this - * so use it only for debug. */ -//#define LOCK_RX_THREAD - -/** \brief Signal used for ethernet ISR to signal packet_rx() thread. - */ -#define RX_SIGNAL 1 - -// K64F-specific macros -#define RX_PBUF_AUTO_INDEX (-1) - /******************************************************************************** * Buffer management ********************************************************************************/ - -/** \brief Queues a pbuf into the RX descriptor list - * - * \param[in] k64f_enet Pointer to the drvier data structure - * \param[in] p Pointer to pbuf to queue - * \param[in] bidx Index to queue into - */ -static void k64f_rxqueue_pbuf(struct k64f_enetdata *k64f_enet, struct pbuf *p, int bidx) -{ - enet_bd_struct_t *start = (enet_bd_struct_t *)k64f_enet->rx_desc_start_addr; - int idx; - - /* Get next free descriptor index */ - if (bidx == RX_PBUF_AUTO_INDEX) - idx = k64f_enet->rx_fill_index; - else - idx = bidx; - - /* Setup descriptor and clear statuses */ - enet_hal_init_rxbds(start + idx, (uint8_t*)p->payload, idx == ENET_RX_RING_LEN - 1); - - /* Save pbuf pointer for push to network layer later */ - k64f_enet->rxb[idx] = p; - - /* Wrap at end of descriptor list */ - idx = (idx + 1) % ENET_RX_RING_LEN; - - /* Queue descriptor(s) */ - k64f_enet->rx_free_descs -= 1; - - if (bidx == RX_PBUF_AUTO_INDEX) - k64f_enet->rx_fill_index = idx; - - enet_hal_active_rxbd(BOARD_DEBUG_ENET_INSTANCE_ADDR); - - LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, - ("k64f_rxqueue_pbuf: pbuf packet queued: %p (free desc=%d)\n", p, - k64f_enet->rx_free_descs)); -} - -/** \brief Attempt to allocate and requeue a new pbuf for RX - * - * \param[in] netif Pointer to the netif structure - * \returns number of queued packets +/* + * This function will queue a new receive buffer */ -s32_t k64f_rx_queue(struct netif *netif, int idx) +static void update_read_buffer(uint8_t *buf) { - struct k64f_enetdata *k64f_enet = netif->state; - enet_dev_if_t *enetIfPtr = (enet_dev_if_t *)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE]; - struct pbuf *p; - int queued = 0; - - /* Attempt to requeue as many packets as possible */ - while (k64f_enet->rx_free_descs > 0) { - /* Allocate a pbuf from the pool. We need to allocate at the - maximum size as we don't know the size of the yet to be - received packet. */ - p = pbuf_alloc(PBUF_RAW, enetIfPtr->macCfgPtr->rxBufferSize + RX_BUF_ALIGNMENT, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, - ("k64_rx_queue: could not allocate RX pbuf (free desc=%d)\n", - k64f_enet->rx_free_descs)); - return queued; + if (buf != NULL) { + g_handle.rxBdCurrent->buffer = buf; } - /* K64F note: the next line ensures that the RX buffer is properly aligned for the K64F - RX descriptors (16 bytes alignment). However, by doing so, we're effectively changing - a data structure which is internal to lwIP. This might not prove to be a good idea - in the long run, but a better fix would probably involve modifying lwIP itself */ - p->payload = (void*)ENET_ALIGN((uint32_t)p->payload, RX_BUF_ALIGNMENT); - - /* pbufs allocated from the RAM pool should be non-chained. */ - LWIP_ASSERT("k64f_rx_queue: pbuf is not contiguous (chained)", pbuf_clen(p) <= 1); - - /* Queue packet */ - k64f_rxqueue_pbuf(k64f_enet, p, idx); - queued++; - } - - return queued; -} - -/** \brief Sets up the RX descriptor ring buffers. - * - * This function sets up the descriptor list used for receive packets. - * - * \param[in] netif Pointer to driver data structure - * \returns ERR_MEM if out of memory, ERR_OK otherwise - */ -static err_t k64f_rx_setup(struct netif *netif, enet_rxbd_config_t *rxbdCfg) { - struct k64f_enetdata *k64f_enet = netif->state; - enet_dev_if_t *enetIfPtr = (enet_dev_if_t *)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE]; - uint8_t *rxBdPtr; - uint32_t rxBufferSizeAligned; - - // Allocate RX descriptors - rxBdPtr = (uint8_t *)calloc(1, enet_hal_get_bd_size() * enetIfPtr->macCfgPtr->rxBdNumber + ENET_BD_ALIGNMENT); - if(!rxBdPtr) - return ERR_MEM; - k64f_enet->rx_desc_start_addr = (uint8_t *)ENET_ALIGN((uint32_t)rxBdPtr, ENET_BD_ALIGNMENT); - k64f_enet->rx_free_descs = enetIfPtr->macCfgPtr->rxBdNumber; - k64f_enet->rx_fill_index = 0; - - rxBufferSizeAligned = ENET_ALIGN(enetIfPtr->macCfgPtr->rxBufferSize, ENET_RX_BUFFER_ALIGNMENT); - enetIfPtr->macContextPtr->rxBufferSizeAligned = rxBufferSizeAligned; - rxbdCfg->rxBdPtrAlign = k64f_enet->rx_desc_start_addr; - rxbdCfg->rxBdNum = enetIfPtr->macCfgPtr->rxBdNumber; - rxbdCfg->rxBufferNum = enetIfPtr->macCfgPtr->rxBdNumber; - - k64f_rx_queue(netif, RX_PBUF_AUTO_INDEX); - return ERR_OK; -} - -/** \brief Sets up the TX descriptor ring buffers. - * - * This function sets up the descriptor list used for transmit packets. - * - * \param[in] netif Pointer to driver data structure - * \returns ERR_MEM if out of memory, ERR_OK otherwise - */ -static err_t k64f_tx_setup(struct netif *netif, enet_txbd_config_t *txbdCfg) { - struct k64f_enetdata *k64f_enet = netif->state; - enet_dev_if_t *enetIfPtr = (enet_dev_if_t *)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE]; - uint8_t *txBdPtr; - - // Allocate TX descriptors - txBdPtr = (uint8_t *)calloc(1, enet_hal_get_bd_size() * enetIfPtr->macCfgPtr->txBdNumber + ENET_BD_ALIGNMENT); - if(!txBdPtr) - return ERR_MEM; - k64f_enet->tx_desc_start_addr = (uint8_t *)ENET_ALIGN((uint32_t)txBdPtr, ENET_BD_ALIGNMENT); - k64f_enet->tx_consume_index = k64f_enet->tx_produce_index = 0; + /* Clears status. */ + g_handle.rxBdCurrent->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; - txbdCfg->txBdPtrAlign = k64f_enet->tx_desc_start_addr; - txbdCfg->txBufferNum = enetIfPtr->macCfgPtr->txBdNumber; - txbdCfg->txBufferSizeAlign = ENET_ALIGN(enetIfPtr->maxFrameSize, ENET_TX_BUFFER_ALIGNMENT); + /* Sets the receive buffer descriptor with the empty flag. */ + g_handle.rxBdCurrent->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; - // Make the TX descriptor ring circular - enet_hal_init_txbds(k64f_enet->tx_desc_start_addr + enet_hal_get_bd_size() * (ENET_TX_RING_LEN - 1), 1); + /* Increases the buffer descriptor to the next one. */ + if (g_handle.rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) { + g_handle.rxBdCurrent = g_handle.rxBdBase; + g_handle.rxBdDirty = g_handle.rxBdBase; + } else { + g_handle.rxBdCurrent++; + g_handle.rxBdDirty++; + } - return ERR_OK; + /* Actives the receive buffer descriptor. */ + ENET->RDAR = ENET_RDAR_RDAR_MASK; } /** \brief Free TX buffers that are complete @@ -263,126 +99,142 @@ static err_t k64f_tx_setup(struct netif *netif, enet_txbd_config_t *txbdCfg) { */ static void k64f_tx_reclaim(struct k64f_enetdata *k64f_enet) { - uint8_t i; - volatile enet_bd_struct_t * bdPtr = (enet_bd_struct_t *)k64f_enet->tx_desc_start_addr; + uint8_t i = 0 ; /* Get exclusive access */ sys_mutex_lock(&k64f_enet->TXLockMutex); - // Traverse all descriptors, looking for the ones modified by the uDMA i = k64f_enet->tx_consume_index; - while(i != k64f_enet->tx_produce_index && !(bdPtr[i].control & kEnetTxBdReady)) { - if (k64f_enet->txb_aligned[i]) { - free(k64f_enet->txb_aligned[i]); - k64f_enet->txb_aligned[i] = NULL; - } else if (k64f_enet->txb[i]) { - pbuf_free(k64f_enet->txb[i]); - k64f_enet->txb[i] = NULL; - } - osSemaphoreRelease(k64f_enet->xTXDCountSem.id); - bdPtr[i].controlExtend2 &= ~TX_DESC_UPDATED_MASK; + // Traverse all descriptors, looking for the ones modified by the uDMA + while((i != k64f_enet->tx_produce_index) && (!(g_handle.txBdDirty->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK))) { + pbuf_free(tx_buff[i]); + if (g_handle.txBdDirty->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + g_handle.txBdDirty = g_handle.txBdBase; + else + g_handle.txBdDirty++; + i = (i + 1) % ENET_TX_RING_LEN; } - k64f_enet->tx_consume_index = i; + k64f_enet->tx_consume_index = i; /* Restore access */ sys_mutex_unlock(&k64f_enet->TXLockMutex); } +/** \brief Ethernet receive interrupt handler + * + * This function handles the receive interrupt of K64F. + */ +void enet_mac_rx_isr() +{ + sys_sem_signal(&k64f_enetdata.RxReadySem); +} + +void enet_mac_tx_isr() +{ + sys_sem_signal(&k64f_enetdata.TxCleanSem); +} + +void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param) +{ + switch (event) + { + case kENET_RxEvent: + enet_mac_rx_isr(); + break; + case kENET_TxEvent: + enet_mac_tx_isr(); + break; + default: + break; + } +} + /** \brief Low level init of the MAC and PHY. * * \param[in] netif Pointer to LWIP netif structure */ static err_t low_level_init(struct netif *netif) { - enet_dev_if_t * enetIfPtr; - uint32_t device = BOARD_DEBUG_ENET_INSTANCE_ADDR; - enet_rxbd_config_t rxbdCfg; - enet_txbd_config_t txbdCfg; - enet_phy_speed_t phy_speed; - enet_phy_duplex_t phy_duplex; + struct k64f_enetdata *k64f_enet = netif->state; + uint8_t i; + uint32_t sysClock; + phy_speed_t phy_speed; + phy_duplex_t phy_duplex; + uint32_t phyAddr = 0; + bool link = false; + enet_config_t config; - k64f_init_eth_hardware(); - - /* Initialize device*/ - enetIfPtr = (enet_dev_if_t *)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE]; - enetIfPtr->deviceNumber = device; - enetIfPtr->macCfgPtr = &g_enetMacCfg[BOARD_DEBUG_ENET_INSTANCE]; - enetIfPtr->phyCfgPtr = &g_enetPhyCfg[BOARD_DEBUG_ENET_INSTANCE]; - enetIfPtr->macApiPtr = &g_enetMacApi; - enetIfPtr->phyApiPtr = (void *)&g_enetPhyApi; - memcpy(enetIfPtr->macCfgPtr->macAddr, (char*)netif->hwaddr, kEnetMacAddrLen); - - /* Allocate buffer for ENET mac context*/ - enetIfPtr->macContextPtr = (enet_mac_context_t *)calloc(1, sizeof(enet_mac_context_t)); - if (!enetIfPtr->macContextPtr) { - return ERR_BUF; - } + // Allocate RX descriptors + rx_desc_start_addr = (uint8_t *)calloc(1, sizeof(enet_rx_bd_struct_t) * ENET_RX_RING_LEN + ENET_BUFF_ALIGNMENT); + if(!rx_desc_start_addr) + return ERR_MEM; - /* Initialize enet buffers*/ - if(k64f_rx_setup(netif, &rxbdCfg) != ERR_OK) { - return ERR_BUF; - } - /* Initialize enet buffers*/ - if(k64f_tx_setup(netif, &txbdCfg) != ERR_OK) { - return ERR_BUF; - } - /* Initialize enet module*/ - if (enet_mac_init(enetIfPtr, &rxbdCfg, &txbdCfg) == kStatus_ENET_Success) - { - /* Initialize PHY*/ - if (enetIfPtr->macCfgPtr->isPhyAutoDiscover) { - if (((enet_phy_api_t *)(enetIfPtr->phyApiPtr))->phy_auto_discover(enetIfPtr) != kStatus_PHY_Success) - return ERR_IF; - } - if (((enet_phy_api_t *)(enetIfPtr->phyApiPtr))->phy_init(enetIfPtr) != kStatus_PHY_Success) - return ERR_IF; + // Allocate TX descriptors + tx_desc_start_addr = (uint8_t *)calloc(1, sizeof(enet_tx_bd_struct_t) * ENET_TX_RING_LEN + ENET_BUFF_ALIGNMENT); + if(!tx_desc_start_addr) + return ERR_MEM; - enetIfPtr->isInitialized = true; - } - else - { - // TODOETH: cleanup memory - return ERR_IF; + rx_desc_start_addr = (uint8_t *)ENET_ALIGN(rx_desc_start_addr, ENET_BUFF_ALIGNMENT); + tx_desc_start_addr = (uint8_t *)ENET_ALIGN(tx_desc_start_addr, ENET_BUFF_ALIGNMENT); + + /* Create buffers for each receive BD */ + for (i = 0; i < ENET_RX_RING_LEN; i++) { + rx_buff[i] = pbuf_alloc(PBUF_RAW, ENET_ETH_MAX_FLEN + ENET_BUFF_ALIGNMENT, PBUF_RAM); + if (NULL == rx_buff[i]) + return ERR_MEM; + + /* K64F note: the next line ensures that the RX buffer is properly aligned for the K64F + RX descriptors (16 bytes alignment). However, by doing so, we're effectively changing + a data structure which is internal to lwIP. This might not prove to be a good idea + in the long run, but a better fix would probably involve modifying lwIP itself */ + rx_buff[i]->payload = (void*)ENET_ALIGN((uint32_t)rx_buff[i]->payload, ENET_BUFF_ALIGNMENT); + rx_ptr[i] = rx_buff[i]->payload; } - /* Get link information from PHY */ - phy_get_link_speed(enetIfPtr, &phy_speed); - phy_get_link_duplex(enetIfPtr, &phy_duplex); - BW_ENET_RCR_RMII_10T(enetIfPtr->deviceNumber, phy_speed == kEnetSpeed10M ? kEnetCfgSpeed10M : kEnetCfgSpeed100M); - BW_ENET_TCR_FDEN(enetIfPtr->deviceNumber, phy_duplex == kEnetFullDuplex ? kEnetCfgFullDuplex : kEnetCfgHalfDuplex); + k64f_enet->tx_consume_index = k64f_enet->tx_produce_index = 0; - /* Enable Ethernet module*/ - enet_hal_config_ethernet(BOARD_DEBUG_ENET_INSTANCE_ADDR, true, true); + /* prepare the buffer configuration. */ + enet_buffer_config_t buffCfg = { + ENET_RX_RING_LEN, + ENET_TX_RING_LEN, + ENET_ALIGN(ENET_ETH_MAX_FLEN, ENET_BUFF_ALIGNMENT), + 0, + (volatile enet_rx_bd_struct_t *)rx_desc_start_addr, + (volatile enet_tx_bd_struct_t *)tx_desc_start_addr, + (uint8_t *)&rx_ptr, + NULL, + }; - /* Active Receive buffer descriptor must be done after module enable*/ - enet_hal_active_rxbd(enetIfPtr->deviceNumber); + k64f_init_eth_hardware(); - return ERR_OK; -} + sysClock = CLOCK_GetFreq(kCLOCK_CoreSysClk); -/******************************************************************************** - * LWIP port - ********************************************************************************/ + ENET_GetDefaultConfig(&config); -/** \brief Ethernet receive interrupt handler - * - * This function handles the receive interrupt of K64F. - */ -void enet_mac_rx_isr(void *enetIfPtr) -{ - /* Clear interrupt */ - enet_hal_clear_interrupt(((enet_dev_if_t *)enetIfPtr)->deviceNumber, kEnetRxFrameInterrupt); - sys_sem_signal(&k64f_enetdata.RxReadySem); -} + PHY_Init(ENET, 0, sysClock); + PHY_GetLinkStatus(ENET, phyAddr, &link); + if (link) + { + /* Get link information from PHY */ + PHY_GetLinkSpeedDuplex(ENET, phyAddr, &phy_speed, &phy_duplex); + /* Change the MII speed and duplex for actual link status. */ + config.miiSpeed = (enet_mii_speed_t)phy_speed; + config.miiDuplex = (enet_mii_duplex_t)phy_duplex; + config.interrupt = kENET_RxFrameInterrupt | kENET_TxFrameInterrupt; + } + config.rxMaxFrameLen = ENET_ETH_MAX_FLEN; + config.macSpecialConfig = kENET_ControlFlowControlEnable; + config.txAccelerConfig = kENET_TxAccelIsShift16Enabled; + config.rxAccelerConfig = kENET_RxAccelisShift16Enabled | kENET_RxAccelMacCheckEnabled; + ENET_Init(ENET, &g_handle, &config, &buffCfg, netif->hwaddr, sysClock); + ENET_SetCallback(&g_handle, ethernet_callback, netif); + ENET_ActiveRead(ENET); -void enet_mac_tx_isr(void *enetIfPtr) -{ - /*Clear interrupt*/ - enet_hal_clear_interrupt(((enet_dev_if_t *)enetIfPtr)->deviceNumber, kEnetTxFrameInterrupt); - sys_sem_signal(&k64f_enetdata.TxCleanSem); + return ERR_OK; } + /** * This function is the ethernet packet send function. It calls * etharp_output after checking link status. @@ -409,11 +261,13 @@ err_t k64f_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr) */ static struct pbuf *k64f_low_level_input(struct netif *netif, int idx) { - struct k64f_enetdata *k64f_enet = netif->state; - enet_bd_struct_t * bdPtr = (enet_bd_struct_t*)k64f_enet->rx_desc_start_addr; + volatile enet_rx_bd_struct_t *bdPtr = g_handle.rxBdCurrent; struct pbuf *p = NULL; - u32_t length = 0, orig_length; - const u16_t err_mask = kEnetRxBdTrunc | kEnetRxBdCrc | kEnetRxBdNoOctet | kEnetRxBdLengthViolation; + struct pbuf *temp_rxbuf = NULL; + u32_t length = 0; + const u16_t err_mask = ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK | + ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK; + #ifdef LOCK_RX_THREAD /* Get exclusive access */ @@ -421,42 +275,32 @@ static struct pbuf *k64f_low_level_input(struct netif *netif, int idx) #endif /* Determine if a frame has been received */ - if ((bdPtr[idx].control & err_mask) != 0) { + if ((bdPtr->control & err_mask) != 0) { #if LINK_STATS - if ((bdPtr[idx].control & kEnetRxBdLengthViolation) != 0) + if ((bdPtr->control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) != 0) LINK_STATS_INC(link.lenerr); else LINK_STATS_INC(link.chkerr); #endif LINK_STATS_INC(link.drop); - - /* Re-queue the same buffer */ - k64f_enet->rx_free_descs++; - p = k64f_enet->rxb[idx]; - k64f_enet->rxb[idx] = NULL; - k64f_rxqueue_pbuf(k64f_enet, p, idx); - p = NULL; + /* Re-use the same buffer in case of error */ + update_read_buffer(NULL); } else { /* A packet is waiting, get length */ - length = enet_hal_get_bd_length(bdPtr + idx); + length = bdPtr->length; /* Zero-copy */ - p = k64f_enet->rxb[idx]; - orig_length = p->len; - p->len = (u16_t) length; - - /* Free pbuf from descriptor */ - k64f_enet->rxb[idx] = NULL; - k64f_enet->rx_free_descs++; - + p = rx_buff[idx]; + p->len = length; + /* Attempt to queue new buffer */ - if (k64f_rx_queue(netif, idx) == 0) { + temp_rxbuf = pbuf_alloc(PBUF_RAW, ENET_ETH_MAX_FLEN + ENET_BUFF_ALIGNMENT, PBUF_RAM); + if (NULL == temp_rxbuf) { /* Drop frame (out of memory) */ LINK_STATS_INC(link.drop); /* Re-queue the same buffer */ - p->len = orig_length; - k64f_rxqueue_pbuf(k64f_enet, p, idx); + update_read_buffer(NULL); LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, ("k64f_low_level_input: Packet index %d dropped for OOM\n", @@ -468,6 +312,15 @@ static struct pbuf *k64f_low_level_input(struct netif *netif, int idx) return NULL; } + rx_buff[idx] = temp_rxbuf; + /* K64F note: the next line ensures that the RX buffer is properly aligned for the K64F + RX descriptors (16 bytes alignment). However, by doing so, we're effectively changing + a data structure which is internal to lwIP. This might not prove to be a good idea + in the long run, but a better fix would probably involve modifying lwIP itself */ + rx_buff[idx]->payload = (void*)ENET_ALIGN((uint32_t)rx_buff[idx]->payload, ENET_BUFF_ALIGNMENT); + rx_ptr[idx] = rx_buff[idx]->payload; + + update_read_buffer(rx_buff[idx]->payload); LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, ("k64f_low_level_input: Packet received: %p, size %d (index=%d)\n", p, length, idx)); @@ -533,14 +386,13 @@ void k64f_enetif_input(struct netif *netif, int idx) */ static void packet_rx(void* pvParameters) { struct k64f_enetdata *k64f_enet = pvParameters; - volatile enet_bd_struct_t * bdPtr = (enet_bd_struct_t*)k64f_enet->rx_desc_start_addr; int idx = 0; while (1) { /* Wait for receive task to wakeup */ sys_arch_sem_wait(&k64f_enet->RxReadySem, 0); - while ((bdPtr[idx].control & kEnetRxBdEmpty) == 0) { + while ((g_handle.rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) == 0) { k64f_enetif_input(k64f_enet->netif, idx); idx = (idx + 1) % ENET_RX_RING_LEN; } @@ -561,58 +413,10 @@ static void packet_tx(void* pvParameters) { while (1) { /* Wait for transmit cleanup task to wakeup */ sys_arch_sem_wait(&k64f_enet->TxCleanSem, 0); - // TODOETH: handle TX underrun? k64f_tx_reclaim(k64f_enet); } } - /** \brief Polls if an available TX descriptor is ready. Can be used to - * determine if the low level transmit function will block. - * - * \param[in] netif the lwip network interface structure - * \return 0 if no descriptors are read, or >0 - */ -s32_t k64f_tx_ready(struct netif *netif) -{ - struct k64f_enetdata *k64f_enet = netif->state; - s32_t fb; - u32_t idx, cidx; - - cidx = k64f_enet->tx_consume_index; - idx = k64f_enet->tx_produce_index; - - /* Determine number of free buffers */ - if (idx == cidx) - fb = ENET_TX_RING_LEN; - else if (cidx > idx) - fb = (ENET_TX_RING_LEN - 1) - - ((idx + ENET_TX_RING_LEN) - cidx); - else - fb = (ENET_TX_RING_LEN - 1) - (cidx - idx); - - return fb; -} - -/*FUNCTION**************************************************************** - * - * Function Name: enet_hal_update_txbds - * Description: Update ENET transmit buffer descriptors. - *END*********************************************************************/ -void k64f_update_txbds(struct k64f_enetdata *k64f_enet, int idx, uint8_t *buffer, uint16_t length, bool isLast) -{ - volatile enet_bd_struct_t * bdPtr = (enet_bd_struct_t *)(k64f_enet->tx_desc_start_addr + idx * enet_hal_get_bd_size()); - - bdPtr->length = HTONS(length); /* Set data length*/ - bdPtr->buffer = (uint8_t *)HTONL((uint32_t)buffer); /* Set data buffer*/ - if (isLast) - bdPtr->control |= kEnetTxBdLast; - else - bdPtr->control &= ~kEnetTxBdLast; - bdPtr->controlExtend1 |= kEnetTxBdTxInterrupt; - bdPtr->controlExtend2 &= ~TX_DESC_UPDATED_MASK; // descriptor not updated by DMA - bdPtr->control |= kEnetTxBdTransmitCrc | kEnetTxBdReady; -} - /** \brief Low level output of a packet. Never call this from an * interrupt context, as it may block until TX descriptors * become available. @@ -625,83 +429,51 @@ static err_t k64f_low_level_output(struct netif *netif, struct pbuf *p) { struct k64f_enetdata *k64f_enet = netif->state; struct pbuf *q; - u32_t idx; - s32_t dn; + struct pbuf *temp_pbuf; uint8_t *psend = NULL, *dst; - /* Get free TX buffer index */ - idx = k64f_enet->tx_produce_index; - - /* Check the pbuf chain for payloads that are not 8-byte aligned. - If found, a new properly aligned buffer needs to be allocated - and the data copied there */ - for (q = p; q != NULL; q = q->next) - if (((u32_t)q->payload & (TX_BUF_ALIGNMENT - 1)) != 0) - break; - if (q != NULL) { - // Allocate properly aligned buffer - psend = (uint8_t*)malloc(p->tot_len); - if (NULL == psend) - return ERR_MEM; - LWIP_ASSERT("k64f_low_level_output: buffer not properly aligned", ((u32_t)psend & (TX_BUF_ALIGNMENT - 1)) == 0); - for (q = p, dst = psend; q != NULL; q = q->next) { - MEMCPY(dst, q->payload, q->len); - dst += q->len; - } - k64f_enet->txb_aligned[idx] = psend; - dn = 1; - } else { - k64f_enet->txb_aligned[idx] = NULL; - dn = (s32_t) pbuf_clen(p); - pbuf_ref(p); + + temp_pbuf = pbuf_alloc(PBUF_RAW, p->tot_len + ENET_BUFF_ALIGNMENT, PBUF_RAM); + if (NULL == temp_pbuf) + return ERR_MEM; + + /* K64F note: the next line ensures that the RX buffer is properly aligned for the K64F + RX descriptors (16 bytes alignment). However, by doing so, we're effectively changing + a data structure which is internal to lwIP. This might not prove to be a good idea + in the long run, but a better fix would probably involve modifying lwIP itself */ + psend = (uint8_t *)ENET_ALIGN((uint32_t)temp_pbuf->payload, ENET_BUFF_ALIGNMENT); + + for (q = p, dst = psend; q != NULL; q = q->next) { + MEMCPY(dst, q->payload, q->len); + dst += q->len; } - /* Wait until enough descriptors are available for the transfer. */ - /* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */ - while (dn > k64f_tx_ready(netif)) + /* Wait until a descriptor is available for the transfer. */ + /* THIS WILL BLOCK UNTIL THERE ARE A DESCRIPTOR AVAILABLE */ + while (g_handle.txBdCurrent->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) osSemaphoreWait(k64f_enet->xTXDCountSem.id, osWaitForever); /* Get exclusive access */ sys_mutex_lock(&k64f_enet->TXLockMutex); - /* Setup transfers */ - q = p; - while (dn > 0) { - dn--; - if (psend != NULL) { - k64f_update_txbds(k64f_enet, idx, psend, p->tot_len, 1); - k64f_enet->txb[idx] = NULL; - - LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, - ("k64f_low_level_output: aligned packet(%p) sent" - " size = %d (index=%d)\n", psend, p->tot_len, idx)); - } else { - LWIP_ASSERT("k64f_low_level_output: buffer not properly aligned", ((u32_t)q->payload & 0x07) == 0); + /* Save the buffer so that it can be freed when transmit is done */ + tx_buff[k64f_enet->tx_produce_index] = temp_pbuf; + k64f_enet->tx_produce_index = (k64f_enet->tx_produce_index + 1) % ENET_TX_RING_LEN; - /* Only save pointer to free on last descriptor */ - if (dn == 0) { - /* Save size of packet and signal it's ready */ - k64f_update_txbds(k64f_enet, idx, q->payload, q->len, 1); - k64f_enet->txb[idx] = p; - } - else { - /* Save size of packet, descriptor is not last */ - k64f_update_txbds(k64f_enet, idx, q->payload, q->len, 0); - k64f_enet->txb[idx] = NULL; - } - - LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, - ("k64f_low_level_output: pbuf packet(%p) sent, chain#=%d," - " size = %d (index=%d)\n", q->payload, dn, q->len, idx)); - } + /* Setup transfers */ + g_handle.txBdCurrent->buffer = psend; + g_handle.txBdCurrent->length = p->tot_len; + g_handle.txBdCurrent->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); - q = q->next; + /* Increase the buffer descriptor address. */ + if (g_handle.txBdCurrent->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + g_handle.txBdCurrent = g_handle.txBdBase; + else + g_handle.txBdCurrent++; - idx = (idx + 1) % ENET_TX_RING_LEN; - } + /* Active the transmit buffer descriptor. */ + ENET->TDAR = ENET_TDAR_TDAR_MASK; - k64f_enet->tx_produce_index = idx; - enet_hal_active_txbd(BOARD_DEBUG_ENET_INSTANCE_ADDR); LINK_STATS_INC(link.xmit); /* Restore access */ @@ -719,31 +491,33 @@ static err_t k64f_low_level_output(struct netif *netif, struct pbuf *p) typedef struct { int connected; - enet_phy_speed_t speed; - enet_phy_duplex_t duplex; + phy_speed_t speed; + phy_duplex_t duplex; } PHY_STATE; int phy_link_status() { bool connection_status; - enet_dev_if_t * enetIfPtr = (enet_dev_if_t*)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE]; - phy_get_link_status(enetIfPtr, &connection_status); + uint32_t phyAddr = 0; + + PHY_GetLinkStatus(ENET, phyAddr, &connection_status); return (int)connection_status; } static void k64f_phy_task(void *data) { struct netif *netif = (struct netif*)data; bool connection_status; - enet_dev_if_t * enetIfPtr = (enet_dev_if_t*)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE]; - PHY_STATE crt_state = {STATE_UNKNOWN, (enet_phy_speed_t)STATE_UNKNOWN, (enet_phy_duplex_t)STATE_UNKNOWN}; + PHY_STATE crt_state = {STATE_UNKNOWN, (phy_speed_t)STATE_UNKNOWN, (phy_duplex_t)STATE_UNKNOWN}; PHY_STATE prev_state; + uint32_t phyAddr = 0; + uint32_t rcr = 0; prev_state = crt_state; while (true) { // Get current status - phy_get_link_status(enetIfPtr, &connection_status); + PHY_GetLinkStatus(ENET, phyAddr, &connection_status); crt_state.connected = connection_status ? 1 : 0; - phy_get_link_speed(enetIfPtr, &crt_state.speed); - phy_get_link_duplex(enetIfPtr, &crt_state.duplex); + // Get the actual PHY link speed + PHY_GetLinkSpeedDuplex(ENET, phyAddr, &crt_state.speed, &crt_state.duplex); // Compare with previous state if (crt_state.connected != prev_state.connected) { @@ -753,10 +527,12 @@ static void k64f_phy_task(void *data) { tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1); } - if (crt_state.speed != prev_state.speed) - BW_ENET_RCR_RMII_10T(enetIfPtr->deviceNumber, crt_state.speed == kEnetSpeed10M ? kEnetCfgSpeed10M : kEnetCfgSpeed100M); - - // TODO: duplex change requires disable/enable of Ethernet interface, to be implemented + if (crt_state.speed != prev_state.speed) { + rcr = ENET->RCR; + rcr &= ~ENET_RCR_RMII_10T_MASK; + rcr |= ENET_RCR_RMII_10T(!crt_state.speed); + ENET->RCR = rcr; + } prev_state = crt_state; osDelay(PHY_TASK_PERIOD_MS); @@ -851,32 +627,14 @@ err_t eth_arch_enetif_init(struct netif *netif) } void eth_arch_enable_interrupts(void) { - enet_hal_config_interrupt(BOARD_DEBUG_ENET_INSTANCE_ADDR, (kEnetTxFrameInterrupt | kEnetRxFrameInterrupt), true); - INT_SYS_EnableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetRxfInt]]); - INT_SYS_EnableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetTxfInt]]); + //NVIC_SetPriority(ENET_Receive_IRQn, 6U); + //NVIC_SetPriority(ENET_Transmit_IRQn, 6U); } void eth_arch_disable_interrupts(void) { - INT_SYS_DisableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetRxfInt]]); - INT_SYS_DisableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetTxfInt]]); -} -void ENET_Transmit_IRQHandler(void) -{ - enet_mac_tx_isr(enetIfHandle); } -void ENET_Receive_IRQHandler(void) -{ - enet_mac_rx_isr(enetIfHandle); -} - -#if FSL_FEATURE_ENET_SUPPORT_PTP -void ENET_1588_Timer_IRQHandler(void) -{ - enet_mac_ts_isr(enetIfHandle); -} -#endif /** * @} */ diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac_config.h b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac_config.h index fda77aaebc6..8ec5f2ddaf3 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac_config.h +++ b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/k64f_emac_config.h @@ -29,18 +29,11 @@ */ #ifndef K64F_EMAC_CONFIG_H__ #define K64F_EMAC_CONFIG_H__ - + +#include "fsl_enet.h" + #define ENET_RX_RING_LEN (16) #define ENET_TX_RING_LEN (8) -#define ENET_RX_LARGE_BUFFER_NUM (0) -#define ENET_RX_BUFFER_ALIGNMENT (16) -#define ENET_TX_BUFFER_ALIGNMENT (16) -#define ENET_BD_ALIGNMENT (16) -#define ENET_MII_CLOCK (2500000L) -#define RX_BUF_ALIGNMENT (16) -#define TX_BUF_ALIGNMENT (8) -#define BOARD_DEBUG_ENET_INSTANCE (0) -#define BOARD_DEBUG_ENET_INSTANCE_ADDR (ENET_BASE) #define ENET_ETH_MAX_FLEN (1522) // recommended size for a VLAN frame diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/lwipopts_conf.h b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/lwipopts_conf.h index 4b135c6f13b..20d961abe5a 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/lwipopts_conf.h +++ b/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/lwipopts_conf.h @@ -24,6 +24,6 @@ #define LWIP_TRANSPORT_ETHERNET 1 #define ETH_PAD_SIZE 2 -#define MEM_SIZE (ENET_RX_RING_LEN * (ENET_ETH_MAX_FLEN + RX_BUF_ALIGNMENT) + ENET_TX_RING_LEN * ENET_ETH_MAX_FLEN) +#define MEM_SIZE (ENET_RX_RING_LEN * (ENET_ETH_MAX_FLEN + ENET_BUFF_ALIGNMENT) + ENET_TX_RING_LEN * ENET_ETH_MAX_FLEN) #endif diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 624e40ecd1f..aeed45d5968 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -713,7 +713,7 @@ def __init__(self): self.macros = ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"] self.is_disk_virtual = True self.default_toolchain = "ARM" - self.detect_code = ["0240"] + self.detect_code = ["0214"] self.progen = { "target":"hexiwear-k64f", } From fef9bc3961017c35908b827b4f5eb2047d47a5e8 Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Mon, 2 May 2016 14:52:31 -0500 Subject: [PATCH 11/11] USB support for KL27 Signed-off-by: Mahadevan Mahesh --- libraries/USBDevice/USBDevice/USBEndpoints.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index ff3f2f0c464..d828314d759 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -41,7 +41,7 @@ typedef enum { #include "USBEndpoints_LPC17_LPC23.h" #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549) #include "USBEndpoints_LPC11U.h" -#elif defined(TARGET_KL25Z) | defined(TARGET_KL26Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) +#elif defined(TARGET_KL25Z) | defined(TARGET_KL26Z) | defined(TARGET_KL27Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) #include "USBEndpoints_KL25Z.h" #elif defined (TARGET_STM32F4) #include "USBEndpoints_STM32F4.h"